text
stringlengths 992
1.04M
|
|---|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_atan(clock, resetn, enable, dataa, result);
input clock, resetn, enable;
input [31:0] dataa;
output [31:0] result;
fp_atan core(
.sysclk(clock),
.reset(~resetn),
.enable(enable),
.signin(dataa[31]),
.exponentin(dataa[30:23]),
.mantissain(dataa[22:0]),
.signout(result[31]),
.exponentout(result[30:23]),
.mantissaout(result[22:0])
);
endmodule
|
module decoder (cx,d);
output [5:0] d;
input [18:0] cx;
reg [5:0] d;
reg [12:0] s;
reg [18:0] cx1;
parameter s0 = 13'b1001001110000;
parameter s1 = 13'b1000101100111;
parameter s2 = 13'b0010010001011;
parameter s3 = 13'b0011100010101;
parameter s4 = 13'b1101110101110;
parameter s5 = 13'b1110101100010;
parameter s6 = 13'b1000000000000;
parameter s7 = 13'b0100000000000;
parameter s8 = 13'b0010000000000;
parameter s9 = 13'b0001000000000;
parameter s10 = 13'b0000100000000;
parameter s11 = 13'b0000010000000;
parameter s12 = 13'b0000001000000;
parameter s13 = 13'b0000000100000;
parameter s14 = 13'b0000000010000;
parameter s15 = 13'b0000000001000;
parameter s16 = 13'b0000000000100;
parameter s17 = 13'b0000000000010;
parameter s18 = 13'b0000000000001;
always @(cx)
begin
cx1[0] = cx[0];
cx1[1] = cx[1];
cx1[2] = cx[2];
cx1[3] = cx[3];
cx1[4] = cx[4];
cx1[5] = cx[5];
cx1[6] = cx[6];
cx1[7] = cx[7];
cx1[8] = cx[8];
cx1[9] = cx[9];
cx1[10] = cx[10];
cx1[11] = cx[11];
cx1[12] = cx[12];
cx1[13] = cx[13];
cx1[14] = cx[14];
cx1[15] = cx[15];
cx1[16] = cx[16];
cx1[17] = cx[17];
cx1[18] = cx[18];
s[0]= cx[0]+ cx[1]+ cx[4]+ cx[5]+ cx[6];
s[1]= cx[4]+ cx[5]+ cx[7];
s[2]= cx[2]+ cx[3]+ cx[5]+ cx[8];
s[3]= cx[0]+ cx[3]+ cx[4]+ cx[9];
s[4]= cx[1]+ cx[3]+ cx[4]+ cx[5]+ cx[10];
s[5]= cx[2]+ cx[4]+ cx[11];
s[6]= cx[0]+ cx[1]+ cx[5]+ cx[12];
s[7]= cx[0]+ cx[1]+ cx[4]+ cx[5]+ cx[13];
s[8]= cx[0]+ cx[3]+ cx[14];
s[9]= cx[2]+ cx[4]+ cx[15];
s[10]= cx[1]+ cx[3]+ cx[4]+ cx[16];
s[11]= cx[1]+ cx[2]+ cx[4]+ cx[5]+ cx[17];
s[12]= cx[1]+ cx[2]+ cx[3]+ cx[18];
case(s)
s0:
begin
if(cx[0]==1'b0)
begin
cx1[0]=1'b1;
end
else
begin
cx1[0]=1'b0;
end
end
s1:
begin
if(cx[1]==1'b0)
begin
cx1[1]=1'b1;
end
else
begin
cx1[1]=1'b0;
end
end
s2:
begin
if(cx[2]==1'b0)
begin
cx1[2]=1'b1;
end
else
begin
cx1[2]=1'b0;
end
end
s3:
begin
if(cx[3]==1'b0)
begin
cx1[3]=1'b1;
end
else
begin
cx1[3]=1'b0;
end
end
s4:
begin
if(cx[4]==1'b0)
begin
cx1[4]=1'b1;
end
else
begin
cx1[4]=1'b0;
end
end
s5:
begin
if(cx[5]==1'b0)
begin
cx1[5]=1'b1;
end
else
begin
cx1[5]=1'b0;
end
end
s6:
begin
if(cx[6]==1'b0)
begin
cx1[6]=1'b1;
end
else
begin
cx1[6]=1'b0;
end
end
s7:
begin
if(cx[7]==1'b0)
begin
cx1[7]=1'b1;
end
else
begin
cx1[7]=1'b0;
end
end
s8:
begin
if(cx[8]==1'b0)
begin
cx1[8]=1'b1;
end
else
begin
cx1[8]=1'b0;
end
end
s9:
begin
if(cx[9]==1'b0)
begin
cx1[9]=1'b1;
end
else
begin
cx1[9]=1'b0;
end
end
s10:
begin
if(cx[10]==1'b0)
begin
cx1[10]=1'b1;
end
else
begin
cx1[10]=1'b0;
end
end
s11:
begin
if(cx[11]==1'b0)
begin
cx1[11]=1'b1;
end
else
begin
cx1[11]=1'b0;
end
end
s12:
begin
if(cx[12]==1'b0)
begin
cx1[12]=1'b1;
end
else
begin
cx1[12]=1'b0;
end
end
s13:
begin
if(cx[13]==1'b0)
begin
cx1[13]=1'b1;
end
else
begin
cx1[13]=1'b0;
end
end
s14:
begin
if(cx[14]==1'b0)
begin
cx1[14]=1'b1;
end
else
begin
cx1[14]=1'b0;
end
end
s15:
begin
if(cx[15]==1'b0)
begin
cx1[15]=1'b1;
end
else
begin
cx1[15]=1'b0;
end
end
s16:
begin
if(cx[16]==1'b0)
begin
cx1[16]=1'b1;
end
else
begin
cx1[16]=1'b0;
end
end
s17:
begin
if(cx[17]==1'b0)
begin
cx1[17]=1'b1;
end
else
begin
cx1[17]=1'b0;
end
end
s18:
begin
if(cx[18]==1'b0)
begin
cx1[18]=1'b1;
end
else
begin
cx1[18]=1'b0;
end
end
default:
begin
cx1[0]=cx[0];
cx1[1]=cx[1];
cx1[2]=cx[2];
cx1[3]=cx[3];
cx1[4]=cx[4];
cx1[5]=cx[5];
cx1[6]=cx[6];
cx1[7]=cx[7];
cx1[8]=cx[8];
cx1[9]=cx[9];
cx1[10]=cx[10];
cx1[11]=cx[11];
cx1[12]=cx[12];
cx1[13]=cx[13];
cx1[14]=cx[14];
cx1[15]=cx[15];
cx1[16]=cx[16];
cx1[17]=cx[17];
cx1[18]=cx[18];
end
endcase
d[0] = cx1[0];
d[1] = cx1[1];
d[2] = cx1[2];
d[3] = cx1[3];
d[4] = cx1[4];
d[5] = cx1[5];
end
endmodule
|
// ZX-Evo Base Configuration (c) NedoPC 2008,2009,2010,2011,2012,2013,2014
//
// SPI mode 0 8-bit master module
/*
This file is part of ZX-Evo Base Configuration firmware.
ZX-Evo Base Configuration firmware is free software:
you can redistribute it and/or modify it under the terms of
the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
ZX-Evo Base Configuration firmware is distributed in the hope that
it will be useful, but WITHOUT ANY WARRANTY; without even
the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
See the GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with ZX-Evo Base Configuration firmware.
If not, see <http://www.gnu.org/licenses/>.
*/
// short diagram for speed=0 (Fclk/Fspi=2, no rdy shown)
//
// clock: ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ (positive edges)
// counter: |00|00|10|11|12|13|14|15|16|17|18|19|1A|1B|1C|1D|1E|1F|00|00|00 // internal!
// sck: ___________/``\__/``\__/``\__/``\__/``\__/``\__/``\__/``\_______
// sdo: --------< do7 X do6 X do5 X do4 X do3 X do2 X do1 X do0 >-------
// sdi: --------< di7 X di6 X di5 X di4 X di3 X di2 X di1 X di0 >-------
// bsync: ________/`````\_________________________________________________
// start: _____/``\_______________________________________________________
// din: -----<IN>-------------------------------------------------------
// dout: old old old old old old old old old old old old old | new new new
//
// data on sdo must be latched by slave on rising sck edge. data on sdo changes on falling edge of sck
//
// data from sdi is latched by master on positive edge of sck, while slave changes it on falling edge.
// WARNING: slave must emit valid di7 bit BEFORE first pulse on sck!
//
// bsync is 1 while do7 is outting, otherwise it is 0
//
// start is synchronous pulse, which starts all transfer and also latches din data on the same clock edge
// as it is registered high. start can be given anytime (only when speed=0),
// so it is functioning then as synchronous reset. when speed!=0, there is global enable for majority of
// flipflops in the module, so start can't be accepted at any time
//
// dout updates with freshly received data at the clock edge in which sck goes high for the last time, thus
// latching last bit on sdi.
//
// sdo emits last bit shifted out after the transfer end
//
// when speed=0, data transfer rate could be as fast as one byte every 16 clock pulses. To achieve that,
// start must be pulsed high simultaneously with the last high pulse of sck
//
// speed[1:0] determines Fclk/Fspi
//
// speed | Fclk/Fspi
// ------+----------
// 2'b00 | 2
// 2'b01 | 4
// 2'b10 | 8
// 2'b11 | 16
//
// for speed=0 you can start new transfer as fast as every 16 clocks
// for speed=1 - every 34 clocks.
// alternatively, you can check rdy output: it goes to 0 after start pulse and when it goes back to 1, you can
// issue another start at the next clock cycle. See spi2_modelled.png and .zip (modelsim project)
//
// warning: if using rdy-driven transfers and speed=0, new transfer will be started every 18 clocks.
// it is recommended to use rdy-driven transfers when speed!=0
//
// warning: this module does not contain asynchronous reset. Provided clock is stable, start=0
// and speed=0, module returns to initial ready state after maximum of 18+8=26 clocks. To reset module
// to the known state from any operational state, set speed=0 and start=1 for 8 clocks
// (that starts Fclk/Fspi=2 speed transfer for sure), then remain start=0, speed=0 for at least 18 clocks.
module spi2(
clock, // system clock
sck, // SPI bus pins...
sdo, //
sdi, //
bsync, // ...and bsync for vs1001
start, // positive strobe that starts transfer
rdy, // ready (idle) - when module can accept data
speed, // =2'b00 - sck full speed (1/2 of clock), =2'b01 - half (1/4 of clock), =2'b10 - one fourth (1/8 of clock), =2'b11 - one eighth (1/16 of clock)
din, // input
dout // and output 8bit busses
);
input clock;
output sck;
wire sck;
output sdo;
input sdi;
output reg bsync;
input start;
output rdy;
input [1:0] speed;
input [7:0] din;
output reg [7:0] dout;
// internal regs
reg [4:0] counter; // governs transmission
wire enable_n; // =1 when transmission in progress
reg [6:0] shiftin; // shifting in data from sdi before emitting it on dout
reg [7:0] shiftout; // shifting out data to the sdo
wire ena_shout_load; // enable load of shiftout register
wire g_ena;
reg [2:0] wcnt;
initial // for simulation only!
begin
counter = 5'b10000;
shiftout = 8'd0;
shiftout = 7'd0;
bsync = 1'd0;
dout = 1'b0;
end
// rdy is enable_n
assign rdy = enable_n;
// sck is low bit of counter
assign sck = counter[0];
// enable_n is high bit of counter
assign enable_n = counter[4];
// sdo is high bit of shiftout
assign sdo = shiftout[7];
assign ena_shout_load = (start | sck) & g_ena;
always @(posedge clock)
begin
if( g_ena )
begin
if( start )
begin
counter <= 5'b00000; // enable_n = 0; sck = 0;
bsync <= 1'b1; // begin bsync pulse
end
else
begin
if( !sck ) // on the rising edge of sck
begin
shiftin[6:0] <= { shiftin[5:0], sdi };
if( (&counter[3:1]) && (!enable_n) )
dout <= { shiftin[6:0], sdi }; // update dout at the last sck rising edge
end
else // on the falling edge of sck
begin
bsync <= 1'b0;
end
if( !enable_n )
counter <= counter + 5'd1;
end
end
end
// shiftout treatment is done so just to save LCELLs in acex1k
always @(posedge clock)
begin
if( ena_shout_load )
begin
if( start )
shiftout <= din;
else // sck
shiftout[7:0] <= { shiftout[6:0], shiftout[0] }; // last bit remains after end of exchange
end
end
// slow speeds - governed by g_ena
always @(posedge clock)
begin
if( speed!=2'b00 )
begin
if( start )
wcnt <= 3'b001;
else if( enable_n )
wcnt <= 3'b000;
else
wcnt <= wcnt + 3'd1;
end
else
wcnt <= 3'b000;
end
assign g_ena = (speed==2'b00) ? 1'b1 :
(speed==2'b01) ? (wcnt[0] == 1'b0 ) :
(speed==2'b10) ? (wcnt[1:0]== 2'b00 ) :
(wcnt[2:0]== 3'b000 ) ;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__HA_4_V
`define SKY130_FD_SC_MS__HA_4_V
/**
* ha: Half adder.
*
* Verilog wrapper for ha with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__ha.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_4 (
COUT,
SUM ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output COUT;
output SUM ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__ha_4 (
COUT,
SUM ,
A ,
B
);
output COUT;
output SUM ;
input A ;
input B ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__ha base (
.COUT(COUT),
.SUM(SUM),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__HA_4_V
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
input wire DI,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = (CIN & S) | (DI & ~S);
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (DI),
.S (S)
);
end
endgenerate
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:07:12 10/28/2015
// Design Name:
// Module Name: UART_echo_test_module
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module UART_echo_test_module(
input clock,
input echo_test_rx,
input echo_test_reset,
output echo_test_tx
);
wire baud_rate_rx,
baud_rate_tx,
echo_test_rx_done,
echo_test_tx_done,
echo_test_tx_start,
read_next_tx,
echo_test_empty_flag_rx,
echo_test_not_empty_flag_rx,
echo_test_empty_flag_tx,
echo_test_not_empty_flag_tx;
// echo_test_full_flag_rx,
// echo_test_full_flag_tx;
wire [7:0] echo_test_data_rx;
wire [7:0] echo_test_data_tx;
wire [7:0] echo_test_data;
localparam echo_test_COUNT = 651;
UART_baud_rate_generator #(.COUNT(echo_test_COUNT)) rx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_rx)
);
UART_rx receptor(
.rx(echo_test_rx),
.s_tick(baud_rate_rx),
.clock(clock),
.reset(echo_test_reset),
.rx_done(echo_test_rx_done),
.d_out(echo_test_data_rx)
);
UART_fifo_interface fifo_rx(
.clock(clock),
.reset(echo_test_reset),
.write_flag(echo_test_rx_done),
.read_next(echo_test_not_empty_flag_rx),
.data_in(echo_test_data_rx),
.data_out(echo_test_data),
.empty_flag(echo_test_empty_flag_rx)
// .full_flag(echo_test_full_flag_rx)
);
UART_baud_rate_generator #(.COUNT(echo_test_COUNT*16)) tx_baud_rate(
.clock(clock),
.baud_rate(baud_rate_tx)
);
UART_tx transmisor(
.clock(clock),
.reset(echo_test_reset),
.s_tick(baud_rate_tx),
.tx_start(echo_test_start_tx),
.data_in(echo_test_data_tx),
.tx(echo_test_tx),
.tx_done(echo_test_tx_done)
);
UART_fifo_interface fifo_tx(
.clock(clock),
.reset(echo_test_reset),
.write_flag(echo_test_not_empty_flag_rx),
.read_next(echo_test_not_empty_flag_tx),
.data_in(echo_test_data),
.data_out(echo_test_data_tx),
.empty_flag(echo_test_empty_flag_tx)
// .full_flag(echo_test_full_flag_tx)
);
// assign read_next_tx = echo_test_not_empty_flag_tx && echo_test_tx_done;
assign echo_test_start_tx = echo_test_empty_flag_tx;
assign echo_test_not_empty_flag_tx = ~echo_test_empty_flag_tx;
assign echo_test_not_empty_flag_rx = ~echo_test_empty_flag_rx;
endmodule
|
`timescale 1ns / 1ps
module LCD_DISPLAY_CTRL(PATTERN, CLEAR, CALLFORPATTERN, mole16bit, reset, clk);
input clk;
input reset, CLEAR, CALLFORPATTERN;
input [15:0] mole16bit;
output [255:0] PATTERN;
reg [255:0] PATTERN, next_PATTERN;
reg [4:0] counter, next_counter;
wire [255:0] MOLE_UPPER_PATTERN, MOLE_LOWER_PATTERN;
wire [255:0] EDGE_UPPER_PATTERN, EDGE_LOWER_PATTERN;
always @(negedge clk or negedge reset) begin
if (!reset) begin
PATTERN <= 256'd0;
counter <= 5'd31;
end else begin
if(!CLEAR)begin
PATTERN <= next_PATTERN;
counter <= next_counter;
end else begin
PATTERN <= 256'd0;
counter <= 5'd31;
end
end
end
always @(*)begin
case(counter)
5'd0 :
if(mole16bit[15]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd2 :
if(mole16bit[15]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd1 :
if(mole16bit[14]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd3 :
if(mole16bit[14]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd4 :
if(mole16bit[11]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd6 :
if(mole16bit[11]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd5 :
if(mole16bit[3]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd7 :
if(mole16bit[3]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd8 :
if(mole16bit[10]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd10:
if(mole16bit[10]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd9 :
if(mole16bit[2]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd11:
if(mole16bit[2]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd12:
if(mole16bit[0]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd14:
if(mole16bit[0]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd13:
if(mole16bit[1]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd15:
if(mole16bit[1]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd16:
if(mole16bit[13]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd18:
if(mole16bit[13]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd17:
if(mole16bit[12]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd19:
if(mole16bit[12]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd20:
if(mole16bit[6]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd22:
if(mole16bit[6]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd21:
if(mole16bit[9]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd23:
if(mole16bit[9]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd24:
if(mole16bit[5]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd26:
if(mole16bit[5]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd25:
if(mole16bit[8]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd27:
if(mole16bit[8]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd28:
if(mole16bit[4]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd30:
if(mole16bit[4]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
5'd29:
if(mole16bit[7]==1)next_PATTERN = MOLE_UPPER_PATTERN;
else next_PATTERN = EDGE_UPPER_PATTERN;
5'd31:
if(mole16bit[7]==1)next_PATTERN = MOLE_LOWER_PATTERN;
else next_PATTERN = EDGE_LOWER_PATTERN;
default:
next_PATTERN = PATTERN;
endcase
end
always @( * )begin
if(CALLFORPATTERN) next_counter = counter + 5'd1;
else next_counter = counter;
end
assign MOLE_UPPER_PATTERN[255:0] = 256'hFF01_0101_0101_0101_8141_2111_0905_0303_0303_0305_0911_2141_8101_0101_0101_01FF;
assign MOLE_LOWER_PATTERN[255:0] = 256'hFF80_8080_8080_8080_8182_8488_90A0_C0C0_C0C0_C0A0_9088_8482_8180_8080_8080_80FF;
assign EDGE_UPPER_PATTERN[255:0] = 256'hFF01_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_0101_01FF;
assign EDGE_LOWER_PATTERN[255:0] = 256'hFF80_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_8080_80FF;
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk, fastclk
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
reg reset_l;
int cyc;
initial reset_l = 0;
always @ (posedge clk) begin
if (cyc==0) reset_l <= 1'b1;
else if (cyc==1) reset_l <= 1'b0;
else if (cyc==10) reset_l <= 1'b1;
end
t_clk t (/*AUTOINST*/
// Inputs
.clk (clk),
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk (/*AUTOARG*/
// Inputs
clk, fastclk, reset_l
);
input clk /*verilator sc_clock*/;
input fastclk /*verilator sc_clock*/;
input reset_l;
// surefire lint_off STMINI
// surefire lint_off CWECSB
// surefire lint_off NBAJAM
reg _ranit; initial _ranit=0;
// surefire lint_off UDDSMX
reg [7:0] clk_clocks; initial clk_clocks = 0; // surefire lint_off_line WRTWRT
wire [7:0] clk_clocks_d1r;
wire [7:0] clk_clocks_d1sr;
wire [7:0] clk_clocks_cp2_d1r;
wire [7:0] clk_clocks_cp2_d1sr;
// verilator lint_off MULTIDRIVEN
reg [7:0] int_clocks; initial int_clocks = 0;
// verilator lint_on MULTIDRIVEN
reg [7:0] int_clocks_copy;
// verilator lint_off GENCLK
reg internal_clk; initial internal_clk = 0;
reg reset_int_;
// verilator lint_on GENCLK
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK1 %x\n", $time, reset_l);
`endif
if (!reset_l) begin
clk_clocks <= 0;
int_clocks <= 0;
internal_clk <= 1'b1;
reset_int_ <= 0;
end
else begin
internal_clk <= ~internal_clk;
if (!_ranit) begin
_ranit <= 1;
`ifdef TEST_VERBOSE
$write("[%0t] t_clk: Running\n",$time);
`endif
reset_int_ <= 1;
end
end
end
reg [7:0] sig_rst;
always @ (posedge clk or negedge reset_l) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK2 %x sr=%x\n", $time, reset_l, sig_rst);
`endif
if (!reset_l) begin
sig_rst <= 0;
end
else begin
sig_rst <= sig_rst + 1; // surefire lint_off_line ASWIBB
end
end
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK3 %x cc=%x sr=%x\n", $time, reset_l, clk_clocks, sig_rst);
`endif
if (!reset_l) begin
clk_clocks <= 0;
end
else begin
clk_clocks <= clk_clocks + 8'd1;
if (clk_clocks == 4) begin
if (sig_rst !== 4) $stop;
if (clk_clocks_d1r !== 3) $stop;
if (int_clocks !== 2) $stop;
if (int_clocks_copy !== 2) $stop;
if (clk_clocks_d1r !== clk_clocks_cp2_d1r) $stop;
if (clk_clocks_d1sr !== clk_clocks_cp2_d1sr) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
reg [7:0] resetted;
always @ (posedge clk or negedge reset_int_) begin
`ifdef TEST_VERBOSE
$write("[%0t] CLK4 %x\n", $time, reset_l);
`endif
if (!reset_int_) begin
resetted <= 0;
end
else begin
resetted <= resetted + 8'd1;
end
end
always @ (int_clocks) begin
int_clocks_copy = int_clocks;
end
always @ (negedge internal_clk) begin
int_clocks <= int_clocks + 8'd1;
end
t_clk_flop flopa (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_d1r), .q2(clk_clocks_d1sr));
t_clk_flop flopb (.clk(clk), .clk2(fastclk), .a(clk_clocks),
.q(clk_clocks_cp2_d1r), .q2(clk_clocks_cp2_d1sr));
t_clk_two two (/*AUTOINST*/
// Inputs
.fastclk (fastclk),
.reset_l (reset_l));
endmodule
module t_clk_flop (/*AUTOARG*/
// Outputs
q, q2,
// Inputs
clk, clk2, a
);
parameter WIDTH=8;
input clk;
input clk2;
input [(WIDTH-1):0] a;
output [(WIDTH-1):0] q;
output [(WIDTH-1):0] q2;
reg [(WIDTH-1):0] q;
reg [(WIDTH-1):0] q2;
always @ (posedge clk) q<=a;
always @ (posedge clk2) q2<=a;
endmodule
module t_clk_two (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
// verilator lint_off GENCLK
reg clk2;
// verilator lint_on GENCLK
reg [31:0] count;
t_clk_twob tb (.*);
wire reset_h = ~reset_l;
always @ (posedge fastclk) begin
if (reset_h) clk2 <= 0;
else clk2 <= ~clk2;
end
always @ (posedge clk2) begin
if (reset_h) count <= 0;
else count <= count + 1;
end
endmodule
module t_clk_twob (/*AUTOARG*/
// Inputs
fastclk, reset_l
);
input fastclk;
input reset_l;
always @ (posedge fastclk) begin
// Extra line coverage point, just to make sure coverage
// hierarchy under inlining lands properly
if (reset_l) ;
end
endmodule
|
/******************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Instruction cache implementation
Copyright (C) 2012-2013
Stefan Kristiansson <[email protected]>
Stefan Wallentowitz <[email protected]>
******************************************************************************/
`include "mor1kx-defines.v"
module mor1kx_icache
#(
parameter OPTION_OPERAND_WIDTH = 32,
parameter OPTION_ICACHE_BLOCK_WIDTH = 5,
parameter OPTION_ICACHE_SET_WIDTH = 9,
parameter OPTION_ICACHE_WAYS = 2,
parameter OPTION_ICACHE_LIMIT_WIDTH = 32
)
(
input clk,
input rst,
input ic_imem_err_i,
input ic_access_i,
output refill_o,
output refill_req_o,
output refill_done_o,
output invalidate_o,
// CPU Interface
output cpu_ack_o,
output reg [`OR1K_INSN_WIDTH-1:0] cpu_dat_o,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_i,
input [OPTION_OPERAND_WIDTH-1:0] cpu_adr_match_i,
input cpu_req_i,
input [OPTION_OPERAND_WIDTH-1:0] wradr_i,
input [`OR1K_INSN_WIDTH-1:0] wrdat_i,
input we_i,
// SPR interface
input [15:0] spr_bus_addr_i,
input spr_bus_we_i,
input spr_bus_stb_i,
input [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_i,
output [OPTION_OPERAND_WIDTH-1:0] spr_bus_dat_o,
output reg spr_bus_ack_o
);
// States
localparam IDLE = 4'b0001;
localparam READ = 4'b0010;
localparam REFILL = 4'b0100;
localparam INVALIDATE = 4'b1000;
// Address space in bytes for a way
localparam WAY_WIDTH = OPTION_ICACHE_BLOCK_WIDTH + OPTION_ICACHE_SET_WIDTH;
/*
* Tag memory layout
* +---------------------------------------------------------+
* (index) -> | LRU | wayN valid | wayN tag |...| way0 valid | way0 tag |
* +---------------------------------------------------------+
*/
// The tag is the part left of the index
localparam TAG_WIDTH = (OPTION_ICACHE_LIMIT_WIDTH - WAY_WIDTH);
// The tag memory contains entries with OPTION_ICACHE_WAYS parts of
// each TAGMEM_WAY_WIDTH. Each of those is tag and a valid flag.
localparam TAGMEM_WAY_WIDTH = TAG_WIDTH + 1;
localparam TAGMEM_WAY_VALID = TAGMEM_WAY_WIDTH - 1;
// Additionally, the tag memory entry contains an LRU value. The
// width of this is actually 0 for OPTION_ICACHE_LIMIT_WIDTH==1
localparam TAG_LRU_WIDTH = OPTION_ICACHE_WAYS*(OPTION_ICACHE_WAYS-1) >> 1;
// We have signals for the LRU which are not used for one way
// caches. To avoid signal width [-1:0] this generates [0:0]
// vectors for them, which are removed automatically then.
localparam TAG_LRU_WIDTH_BITS = (OPTION_ICACHE_WAYS >= 2) ? TAG_LRU_WIDTH : 1;
// Compute the total sum of the entry elements
localparam TAGMEM_WIDTH = TAGMEM_WAY_WIDTH * OPTION_ICACHE_WAYS + TAG_LRU_WIDTH;
// For convenience we define the position of the LRU in the tag
// memory entries
localparam TAG_LRU_MSB = TAGMEM_WIDTH - 1;
localparam TAG_LRU_LSB = TAG_LRU_MSB - TAG_LRU_WIDTH + 1;
// FSM state signals
reg [3:0] state;
wire idle;
wire read;
wire refill;
wire invalidate;
reg [WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] invalidate_adr;
wire [31:0] next_refill_adr;
wire refill_done;
wire refill_hit;
reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid;
reg [(1<<(OPTION_ICACHE_BLOCK_WIDTH-2))-1:0] refill_valid_r;
// The index we read and write from tag memory
wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_rindex;
wire [OPTION_ICACHE_SET_WIDTH-1:0] tag_windex;
// The data from the tag memory
wire [TAGMEM_WIDTH-1:0] tag_dout;
wire [TAG_LRU_WIDTH_BITS-1:0] tag_lru_out;
wire [TAGMEM_WAY_WIDTH-1:0] tag_way_out [OPTION_ICACHE_WAYS-1:0];
// The data to the tag memory
wire [TAGMEM_WIDTH-1:0] tag_din;
reg [TAG_LRU_WIDTH_BITS-1:0] tag_lru_in;
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_in [OPTION_ICACHE_WAYS-1:0];
reg [TAGMEM_WAY_WIDTH-1:0] tag_way_save [OPTION_ICACHE_WAYS-1:0];
// Whether to write to the tag memory in this cycle
reg tag_we;
// This is the tag we need to write to the tag memory during refill
wire [TAG_WIDTH-1:0] tag_wtag;
// This is the tag we check against
wire [TAG_WIDTH-1:0] tag_tag;
// Access to the way memories
wire [WAY_WIDTH-3:0] way_raddr[OPTION_ICACHE_WAYS-1:0];
wire [WAY_WIDTH-3:0] way_waddr[OPTION_ICACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_din[OPTION_ICACHE_WAYS-1:0];
wire [OPTION_OPERAND_WIDTH-1:0] way_dout[OPTION_ICACHE_WAYS-1:0];
reg [OPTION_ICACHE_WAYS-1:0] way_we;
// Does any way hit?
wire hit;
wire [OPTION_ICACHE_WAYS-1:0] way_hit;
// This is the least recently used value before access the memory.
// Those are one hot encoded.
wire [OPTION_ICACHE_WAYS-1:0] lru;
// Register that stores the LRU value from lru
reg [OPTION_ICACHE_WAYS-1:0] tag_save_lru;
// The access vector to update the LRU history is the way that has
// a hit or is refilled. It is also one-hot encoded.
reg [OPTION_ICACHE_WAYS-1:0] access;
// The current LRU history as read from tag memory and the update
// value after we accessed it to write back to tag memory.
wire [TAG_LRU_WIDTH_BITS-1:0] current_lru_history;
wire [TAG_LRU_WIDTH_BITS-1:0] next_lru_history;
// Intermediate signals to ease debugging
wire [TAG_WIDTH-1:0] check_way_tag [OPTION_ICACHE_WAYS-1:0];
wire check_way_match [OPTION_ICACHE_WAYS-1:0];
wire check_way_valid [OPTION_ICACHE_WAYS-1:0];
genvar i;
// Allowing (out of the cache line being refilled) accesses during refill
// exposes a bug somewhere, causing the Linux kernel to end up with a
// bus error UNHANDLED EXCEPTION.
// Until that is sorted out, disable it.
assign cpu_ack_o = (read /*| refill & ic_access_i*/) & hit |
refill_hit & ic_access_i;
assign tag_rindex = cpu_adr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
/*
* The tag mem is written during reads to write the lru info and during
* refill and invalidate
*/
assign tag_windex = read ?
cpu_adr_match_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH] :
invalidate ? invalidate_adr :
wradr_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
assign tag_tag = cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH];
assign tag_wtag = wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1:WAY_WIDTH];
generate
if (OPTION_ICACHE_WAYS >= 2) begin
// Multiplex the LRU history from and to tag memory
assign current_lru_history = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
assign tag_din[TAG_LRU_MSB:TAG_LRU_LSB] = tag_lru_in;
assign tag_lru_out = tag_dout[TAG_LRU_MSB:TAG_LRU_LSB];
end
for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : ways
assign way_raddr[i] = cpu_adr_i[WAY_WIDTH-1:2];
assign way_waddr[i] = wradr_i[WAY_WIDTH-1:2];
assign way_din[i] = wrdat_i;
// compare stored tag with incoming tag and check valid bit
assign check_way_tag[i] = tag_way_out[i][TAG_WIDTH-1:0];
assign check_way_match[i] = (check_way_tag[i] == tag_tag);
assign check_way_valid[i] = tag_way_out[i][TAGMEM_WAY_VALID];
assign way_hit[i] = check_way_valid[i] & check_way_match[i];
// Multiplex the way entries in the tag memory
assign tag_din[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH] = tag_way_in[i];
assign tag_way_out[i] = tag_dout[(i+1)*TAGMEM_WAY_WIDTH-1:i*TAGMEM_WAY_WIDTH];
end
endgenerate
assign hit = |way_hit;
integer w0;
always @(*) begin
cpu_dat_o = {OPTION_OPERAND_WIDTH{1'bx}};
// Put correct way on the data port
for (w0 = 0; w0 < OPTION_ICACHE_WAYS; w0 = w0 + 1) begin
if (way_hit[w0] | (refill_hit & tag_save_lru[w0])) begin
cpu_dat_o = way_dout[w0];
end
end
end
assign next_refill_adr = (OPTION_ICACHE_BLOCK_WIDTH == 5) ?
{wradr_i[31:5], wradr_i[4:0] + 5'd4} : // 32 byte
{wradr_i[31:4], wradr_i[3:0] + 4'd4}; // 16 byte
assign refill_done_o = refill_done;
assign refill_done = refill_valid[next_refill_adr[OPTION_ICACHE_BLOCK_WIDTH-1:2]];
assign refill_hit = refill_valid_r[cpu_adr_match_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] &
cpu_adr_match_i[OPTION_ICACHE_LIMIT_WIDTH-1:
OPTION_ICACHE_BLOCK_WIDTH] ==
wradr_i[OPTION_ICACHE_LIMIT_WIDTH-1:
OPTION_ICACHE_BLOCK_WIDTH] &
refill;
assign idle = (state == IDLE);
assign refill = (state == REFILL);
assign read = (state == READ);
assign invalidate = (state == INVALIDATE);
assign refill_o = refill;
assign refill_req_o = read & cpu_req_i & !hit | refill;
/*
* SPR bus interface
*/
assign invalidate_o = spr_bus_stb_i & spr_bus_we_i &
(spr_bus_addr_i == `OR1K_SPR_ICBIR_ADDR);
/*
* Cache FSM
*/
integer w1;
always @(posedge clk `OR_ASYNC_RST) begin
refill_valid_r <= refill_valid;
spr_bus_ack_o <= 0;
case (state)
IDLE: begin
if (cpu_req_i)
state <= READ;
end
READ: begin
if (ic_access_i) begin
if (hit) begin
state <= READ;
end else if (cpu_req_i) begin
refill_valid <= 0;
refill_valid_r <= 0;
// Store the LRU information for correct replacement
// on refill. Always one when only one way.
tag_save_lru <= (OPTION_ICACHE_WAYS==1) | lru;
for (w1 = 0; w1 < OPTION_ICACHE_WAYS; w1 = w1 + 1) begin
tag_way_save[w1] <= tag_way_out[w1];
end
state <= REFILL;
end
end else begin
state <= IDLE;
end
end
REFILL: begin
if (we_i) begin
refill_valid[wradr_i[OPTION_ICACHE_BLOCK_WIDTH-1:2]] <= 1;
if (refill_done)
state <= IDLE;
end
end
INVALIDATE: begin
if (!invalidate_o)
state <= IDLE;
spr_bus_ack_o <= 1;
end
default:
state <= IDLE;
endcase
if (invalidate_o & !refill) begin
invalidate_adr <= spr_bus_dat_i[WAY_WIDTH-1:OPTION_ICACHE_BLOCK_WIDTH];
spr_bus_ack_o <= 1;
state <= INVALIDATE;
end
if (rst)
state <= IDLE;
else if(ic_imem_err_i)
state <= IDLE;
end
integer w2;
always @(*) begin
// Default is to keep data, don't write and don't access
tag_lru_in = tag_lru_out;
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_out[w2];
end
tag_we = 1'b0;
way_we = {(OPTION_ICACHE_WAYS){1'b0}};
access = {(OPTION_ICACHE_WAYS){1'b0}};
case (state)
READ: begin
if (hit) begin
// We got a hit. The LRU module gets the access
// information. Depending on this we update the LRU
// history in the tag.
access = way_hit;
// This is the updated LRU history after hit
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
REFILL: begin
if (we_i) begin
// Write the data to the way that is replaced (which is
// the LRU)
way_we = tag_save_lru;
// Access pattern
access = tag_save_lru;
/* Invalidate the way on the first write */
if (refill_valid == 0) begin
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
if (tag_save_lru[w2]) begin
tag_way_in[w2][TAGMEM_WAY_VALID] = 1'b0;
end
end
tag_we = 1'b1;
end
// After refill update the tag memory entry of the
// filled way with the LRU history, the tag and set
// valid to 1.
if (refill_done) begin
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = tag_way_save[w2];
if (tag_save_lru[w2]) begin
tag_way_in[w2] = { 1'b1, tag_wtag };
end
end
tag_lru_in = next_lru_history;
tag_we = 1'b1;
end
end
end
INVALIDATE: begin
// Lazy invalidation, invalidate everything that matches tag address
tag_lru_in = 0;
for (w2 = 0; w2 < OPTION_ICACHE_WAYS; w2 = w2 + 1) begin
tag_way_in[w2] = 0;
end
tag_we = 1'b1;
end
default: begin
end
endcase
end
/* mor1kx_simple_dpram_sclk AUTO_TEMPLATE (
// Outputs
.dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]),
// Inputs
.raddr (way_raddr[i][WAY_WIDTH-3:0]),
.re (1'b1),
.waddr (way_waddr[i][WAY_WIDTH-3:0]),
.we (way_we[i]),
.din (way_din[i][31:0]));
*/
generate
for (i = 0; i < OPTION_ICACHE_WAYS; i=i+1) begin : way_memories
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(WAY_WIDTH-2),
.DATA_WIDTH(OPTION_OPERAND_WIDTH),
.ENABLE_BYPASS(0)
)
way_data_ram
(/*AUTOINST*/
// Outputs
.dout (way_dout[i][OPTION_OPERAND_WIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.raddr (way_raddr[i][WAY_WIDTH-3:0]), // Templated
.re (1'b1), // Templated
.waddr (way_waddr[i][WAY_WIDTH-3:0]), // Templated
.we (way_we[i]), // Templated
.din (way_din[i][31:0])); // Templated
end // block: way_memories
if (OPTION_ICACHE_WAYS >= 2) begin : gen_u_lru
/* mor1kx_cache_lru AUTO_TEMPLATE(
.current (current_lru_history),
.update (next_lru_history),
.lru_pre (lru),
.lru_post (),
.access (access),
); */
mor1kx_cache_lru
#(.NUMWAYS(OPTION_ICACHE_WAYS))
u_lru(/*AUTOINST*/
// Outputs
.update (next_lru_history), // Templated
.lru_pre (lru), // Templated
.lru_post (), // Templated
// Inputs
.current (current_lru_history), // Templated
.access (access)); // Templated
end // if (OPTION_ICACHE_WAYS >= 2)
endgenerate
/* mor1kx_simple_dpram_sclk AUTO_TEMPLATE (
// Outputs
.dout (tag_dout[TAGMEM_WIDTH-1:0]),
// Inputs
.raddr (tag_rindex),
.re (1'b1),
.waddr (tag_windex),
.we (tag_we),
.din (tag_din));
*/
mor1kx_simple_dpram_sclk
#(
.ADDR_WIDTH(OPTION_ICACHE_SET_WIDTH),
.DATA_WIDTH(TAGMEM_WIDTH),
.ENABLE_BYPASS(0)
)
tag_ram
(/*AUTOINST*/
// Outputs
.dout (tag_dout[TAGMEM_WIDTH-1:0]), // Templated
// Inputs
.clk (clk),
.raddr (tag_rindex), // Templated
.re (1'b1), // Templated
.waddr (tag_windex), // Templated
.we (tag_we), // Templated
.din (tag_din)); // Templated
endmodule
|
//Legal Notice: (C)2016 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_nios2_gen2_0_cpu_debug_slave_tck (
// inputs:
MonDReg,
break_readreg,
dbrk_hit0_latch,
dbrk_hit1_latch,
dbrk_hit2_latch,
dbrk_hit3_latch,
debugack,
ir_in,
jtag_state_rti,
monitor_error,
monitor_ready,
reset_n,
resetlatch,
tck,
tdi,
tracemem_on,
tracemem_trcdata,
tracemem_tw,
trc_im_addr,
trc_on,
trc_wrap,
trigbrktype,
trigger_state_1,
vs_cdr,
vs_sdr,
vs_uir,
// outputs:
ir_out,
jrst_n,
sr,
st_ready_test_idle,
tdo
)
;
output [ 1: 0] ir_out;
output jrst_n;
output [ 37: 0] sr;
output st_ready_test_idle;
output tdo;
input [ 31: 0] MonDReg;
input [ 31: 0] break_readreg;
input dbrk_hit0_latch;
input dbrk_hit1_latch;
input dbrk_hit2_latch;
input dbrk_hit3_latch;
input debugack;
input [ 1: 0] ir_in;
input jtag_state_rti;
input monitor_error;
input monitor_ready;
input reset_n;
input resetlatch;
input tck;
input tdi;
input tracemem_on;
input [ 35: 0] tracemem_trcdata;
input tracemem_tw;
input [ 6: 0] trc_im_addr;
input trc_on;
input trc_wrap;
input trigbrktype;
input trigger_state_1;
input vs_cdr;
input vs_sdr;
input vs_uir;
reg [ 2: 0] DRsize /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire debugack_sync;
reg [ 1: 0] ir_out;
wire jrst_n;
wire monitor_ready_sync;
reg [ 37: 0] sr /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=\"D101,D103,R101\"" */;
wire st_ready_test_idle;
wire tdo;
wire unxcomplemented_resetxx1;
wire unxcomplemented_resetxx2;
always @(posedge tck)
begin
if (vs_cdr)
case (ir_in)
2'b00: begin
sr[35] <= debugack_sync;
sr[34] <= monitor_error;
sr[33] <= resetlatch;
sr[32 : 1] <= MonDReg;
sr[0] <= monitor_ready_sync;
end // 2'b00
2'b01: begin
sr[35 : 0] <= tracemem_trcdata;
sr[37] <= tracemem_tw;
sr[36] <= tracemem_on;
end // 2'b01
2'b10: begin
sr[37] <= trigger_state_1;
sr[36] <= dbrk_hit3_latch;
sr[35] <= dbrk_hit2_latch;
sr[34] <= dbrk_hit1_latch;
sr[33] <= dbrk_hit0_latch;
sr[32 : 1] <= break_readreg;
sr[0] <= trigbrktype;
end // 2'b10
2'b11: begin
sr[15 : 2] <= trc_im_addr;
sr[1] <= trc_wrap;
sr[0] <= trc_on;
end // 2'b11
endcase // ir_in
if (vs_sdr)
case (DRsize)
3'b000: begin
sr <= {tdi, sr[37 : 2], tdi};
end // 3'b000
3'b001: begin
sr <= {tdi, sr[37 : 9], tdi, sr[7 : 1]};
end // 3'b001
3'b010: begin
sr <= {tdi, sr[37 : 17], tdi, sr[15 : 1]};
end // 3'b010
3'b011: begin
sr <= {tdi, sr[37 : 33], tdi, sr[31 : 1]};
end // 3'b011
3'b100: begin
sr <= {tdi, sr[37], tdi, sr[35 : 1]};
end // 3'b100
3'b101: begin
sr <= {tdi, sr[37 : 1]};
end // 3'b101
default: begin
sr <= {tdi, sr[37 : 2], tdi};
end // default
endcase // DRsize
if (vs_uir)
case (ir_in)
2'b00: begin
DRsize <= 3'b100;
end // 2'b00
2'b01: begin
DRsize <= 3'b101;
end // 2'b01
2'b10: begin
DRsize <= 3'b101;
end // 2'b10
2'b11: begin
DRsize <= 3'b010;
end // 2'b11
endcase // ir_in
end
assign tdo = sr[0];
assign st_ready_test_idle = jtag_state_rti;
assign unxcomplemented_resetxx1 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer1
(
.clk (tck),
.din (debugack),
.dout (debugack_sync),
.reset_n (unxcomplemented_resetxx1)
);
defparam the_altera_std_synchronizer1.depth = 2;
assign unxcomplemented_resetxx2 = jrst_n;
altera_std_synchronizer the_altera_std_synchronizer2
(
.clk (tck),
.din (monitor_ready),
.dout (monitor_ready_sync),
.reset_n (unxcomplemented_resetxx2)
);
defparam the_altera_std_synchronizer2.depth = 2;
always @(posedge tck or negedge jrst_n)
begin
if (jrst_n == 0)
ir_out <= 2'b0;
else
ir_out <= {debugack_sync, monitor_ready_sync};
end
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign jrst_n = reset_n;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// assign jrst_n = 1;
//synthesis read_comments_as_HDL off
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4B_SYMBOL_V
`define SKY130_FD_SC_HS__NOR4B_SYMBOL_V
/**
* nor4b: 4-input NOR, first input inverted.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nor4b (
//# {{data|Data Signals}}
input A ,
input B ,
input C ,
input D_N,
output Y
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4B_SYMBOL_V
|
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 27.11.2014 14:15:43
// Design Name:
// Module Name:
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
/*
###############################################################################
# pyrpl - DSP servo controller for quantum optics with the RedPitaya
# Copyright (C) 2014-2016 Leonhard Neuhaus ([email protected])
#
# This program is free software: you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>.
###############################################################################
*/
module red_pitaya_iq_demodulator_block #(
parameter INBITS = 14,
parameter OUTBITS = 18,
parameter SINBITS = 14,
parameter SHIFTBITS = 1
// why SHIFTBITS SHOULD ALWAYS BE 1:
// the sin from fgen ranges from -2**(SINBITS-1)+1 to 2**(SINBITS-1)-1
// i.e. the strange number is excluded by definition. Including the
// strange number -2**(SINBITS-1), the product signal_i * sin / cos
// would be maximally
// 2**(SINBITS+INBITS-1-1). That is, including the sign bit it would
// occupy SINBITS+INBITS-1 bits. Excluding the strange number of the sin
// factor makes the maximum less than that, i.e. we can safely represent
// the product with SINBITS+INBITS-2 bits, including the sign bit.
// That makes SHIFTBITS = -1 (see below). OUTBITS only determines how many
// LSB's we cut off.
)
(
input clk_i,
input signed [SINBITS-1:0] sin,
input signed [SINBITS-1:0] cos,
input signed [INBITS-1:0] signal_i,
output signed [OUTBITS-1:0] signal1_o,
output signed [OUTBITS-1:0] signal2_o
);
reg signed [INBITS-1:0] firstproduct_reg;
always @(posedge clk_i) begin
firstproduct_reg <= signal_i;
end
reg signed [SINBITS+INBITS-1:0] product1;
reg signed [SINBITS+INBITS-1:0] product2;
// soft implementation of symmetric rounding
//wire signed [SINBITS+INBITS-1:0] product1_unrounded;
//wire signed [SINBITS+INBITS-1:0] product2_unrounded;
//assign product1_unrounded = firstproduct_reg * sin;
//assign product2_unrounded = firstproduct_reg * cos;
//wire signed [SINBITS+INBITS-1:0] product1_roundoffset;
//wire signed [SINBITS+INBITS-1:0] product2_roundoffset;
//assign product1_roundoffset = (product1_unrounded[SINBITS+INBITS-1]) ? {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b1},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b0}}}
// : {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b0},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b1}}};
//
//assign product2_roundoffset = (product2_unrounded[SINBITS+INBITS-1]) ? {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b1},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b0}}}
// : {{(OUTBITS+SHIFTBITS+1){1'b0}},{1'b0},{(SINBITS+INBITS-OUTBITS-SHIFTBITS-2){1'b1}}};
// after some problems, we choose asymmetric rounding for now - at least
// some rounding
always @(posedge clk_i) begin
// product1 <= product1_unrounded + product1_roundoffset;
// product2 <= product2_unrounded + product2_roundoffset;
product1 <= firstproduct_reg * sin + $signed(1 << (SINBITS+INBITS-OUTBITS-SHIFTBITS-1));
product2 <= firstproduct_reg * cos + $signed(1 << (SINBITS+INBITS-OUTBITS-SHIFTBITS-1));
end
assign signal1_o = product1[SINBITS+INBITS-1-SHIFTBITS:SINBITS+INBITS-OUTBITS-SHIFTBITS];
assign signal2_o = product2[SINBITS+INBITS-1-SHIFTBITS:SINBITS+INBITS-OUTBITS-SHIFTBITS];
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's Debug Unit ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/cores/or1k/ ////
//// ////
//// Description ////
//// Basic OR1200 debug unit. ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
//
// Debug unit
//
module or1200_du(
// RISC Internal Interface
clk, rst,
dcpu_cycstb_i, dcpu_we_i, dcpu_adr_i, dcpu_dat_lsu,
dcpu_dat_dc, icpu_cycstb_i,
ex_freeze, branch_op, ex_insn, id_pc,
spr_dat_npc, rf_dataw,
du_dsr, du_stall, du_addr, du_dat_i, du_dat_o,
du_read, du_write, du_except, du_hwbkpt,
spr_cs, spr_write, spr_addr, spr_dat_i, spr_dat_o,
// External Debug Interface
dbg_stall_i, dbg_ewt_i, dbg_lss_o, dbg_is_o, dbg_wp_o, dbg_bp_o,
dbg_stb_i, dbg_we_i, dbg_adr_i, dbg_dat_i, dbg_dat_o, dbg_ack_o
);
parameter dw = `OR1200_OPERAND_WIDTH;
parameter aw = `OR1200_OPERAND_WIDTH;
//
// I/O
//
//
// RISC Internal Interface
//
input clk; // Clock
input rst; // Reset
input dcpu_cycstb_i; // LSU status
input dcpu_we_i; // LSU status
input [31:0] dcpu_adr_i; // LSU addr
input [31:0] dcpu_dat_lsu; // LSU store data
input [31:0] dcpu_dat_dc; // LSU load data
input [`OR1200_FETCHOP_WIDTH-1:0] icpu_cycstb_i; // IFETCH unit status
input ex_freeze; // EX stage freeze
input [`OR1200_BRANCHOP_WIDTH-1:0] branch_op; // Branch op
input [dw-1:0] ex_insn; // EX insn
input [31:0] id_pc; // insn fetch EA
input [31:0] spr_dat_npc; // Next PC (for trace)
input [31:0] rf_dataw; // ALU result (for trace)
output [`OR1200_DU_DSR_WIDTH-1:0] du_dsr; // DSR
output du_stall; // Debug Unit Stall
output [aw-1:0] du_addr; // Debug Unit Address
input [dw-1:0] du_dat_i; // Debug Unit Data In
output [dw-1:0] du_dat_o; // Debug Unit Data Out
output du_read; // Debug Unit Read Enable
output du_write; // Debug Unit Write Enable
input [12:0] du_except; // Exception masked by DSR
output du_hwbkpt; // Cause trap exception (HW Breakpoints)
input spr_cs; // SPR Chip Select
input spr_write; // SPR Read/Write
input [aw-1:0] spr_addr; // SPR Address
input [dw-1:0] spr_dat_i; // SPR Data Input
output [dw-1:0] spr_dat_o; // SPR Data Output
//
// External Debug Interface
//
input dbg_stall_i; // External Stall Input
input dbg_ewt_i; // External Watchpoint Trigger Input
output [3:0] dbg_lss_o; // External Load/Store Unit Status
output [1:0] dbg_is_o; // External Insn Fetch Status
output [10:0] dbg_wp_o; // Watchpoints Outputs
output dbg_bp_o; // Breakpoint Output
input dbg_stb_i; // External Address/Data Strobe
input dbg_we_i; // External Write Enable
input [aw-1:0] dbg_adr_i; // External Address Input
input [dw-1:0] dbg_dat_i; // External Data Input
output [dw-1:0] dbg_dat_o; // External Data Output
output dbg_ack_o; // External Data Acknowledge (not WB compatible)
//
// Some connections go directly from the CPU through DU to Debug I/F
//
`ifdef OR1200_DU_STATUS_UNIMPLEMENTED
assign dbg_lss_o = 4'b0000;
reg [1:0] dbg_is_o;
//
// Show insn activity (temp, must be removed)
//
always @(posedge clk or posedge rst)
if (rst)
dbg_is_o <= #1 2'b00;
else if (!ex_freeze &
~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]))
dbg_is_o <= #1 ~dbg_is_o;
`ifdef UNUSED
assign dbg_is_o = 2'b00;
`endif
`else
assign dbg_lss_o = dcpu_cycstb_i ? {dcpu_we_i, 3'b000} : 4'b0000;
assign dbg_is_o = {1'b0, icpu_cycstb_i};
`endif
assign dbg_wp_o = 11'b000_0000_0000;
assign dbg_dat_o = du_dat_i;
//
// Some connections go directly from Debug I/F through DU to the CPU
//
assign du_stall = dbg_stall_i;
assign du_addr = dbg_adr_i;
assign du_dat_o = dbg_dat_i;
assign du_read = dbg_stb_i && !dbg_we_i;
assign du_write = dbg_stb_i && dbg_we_i;
//
// Generate acknowledge -- just delay stb signal
//
reg dbg_ack_o;
always @(posedge clk or posedge rst)
if (rst)
dbg_ack_o <= #1 1'b0;
else
dbg_ack_o <= #1 dbg_stb_i;
`ifdef OR1200_DU_IMPLEMENTED
//
// Debug Mode Register 1
//
`ifdef OR1200_DU_DMR1
reg [24:0] dmr1; // DMR1 implemented
`else
wire [24:0] dmr1; // DMR1 not implemented
`endif
//
// Debug Mode Register 2
//
`ifdef OR1200_DU_DMR2
reg [23:0] dmr2; // DMR2 implemented
`else
wire [23:0] dmr2; // DMR2 not implemented
`endif
//
// Debug Stop Register
//
`ifdef OR1200_DU_DSR
reg [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR implemented
`else
wire [`OR1200_DU_DSR_WIDTH-1:0] dsr; // DSR not implemented
`endif
//
// Debug Reason Register
//
`ifdef OR1200_DU_DRR
reg [13:0] drr; // DRR implemented
`else
wire [13:0] drr; // DRR not implemented
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR0
reg [31:0] dvr0;
`else
wire [31:0] dvr0;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR1
reg [31:0] dvr1;
`else
wire [31:0] dvr1;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR2
reg [31:0] dvr2;
`else
wire [31:0] dvr2;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR3
reg [31:0] dvr3;
`else
wire [31:0] dvr3;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR4
reg [31:0] dvr4;
`else
wire [31:0] dvr4;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR5
reg [31:0] dvr5;
`else
wire [31:0] dvr5;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR6
reg [31:0] dvr6;
`else
wire [31:0] dvr6;
`endif
//
// Debug Value Register N
//
`ifdef OR1200_DU_DVR7
reg [31:0] dvr7;
`else
wire [31:0] dvr7;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR0
reg [7:0] dcr0;
`else
wire [7:0] dcr0;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR1
reg [7:0] dcr1;
`else
wire [7:0] dcr1;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR2
reg [7:0] dcr2;
`else
wire [7:0] dcr2;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR3
reg [7:0] dcr3;
`else
wire [7:0] dcr3;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR4
reg [7:0] dcr4;
`else
wire [7:0] dcr4;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR5
reg [7:0] dcr5;
`else
wire [7:0] dcr5;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR6
reg [7:0] dcr6;
`else
wire [7:0] dcr6;
`endif
//
// Debug Control Register N
//
`ifdef OR1200_DU_DCR7
reg [7:0] dcr7;
`else
wire [7:0] dcr7;
`endif
//
// Debug Watchpoint Counter Register 0
//
`ifdef OR1200_DU_DWCR0
reg [31:0] dwcr0;
`else
wire [31:0] dwcr0;
`endif
//
// Debug Watchpoint Counter Register 1
//
`ifdef OR1200_DU_DWCR1
reg [31:0] dwcr1;
`else
wire [31:0] dwcr1;
`endif
//
// Internal wires
//
wire dmr1_sel; // DMR1 select
wire dmr2_sel; // DMR2 select
wire dsr_sel; // DSR select
wire drr_sel; // DRR select
wire dvr0_sel,
dvr1_sel,
dvr2_sel,
dvr3_sel,
dvr4_sel,
dvr5_sel,
dvr6_sel,
dvr7_sel; // DVR selects
wire dcr0_sel,
dcr1_sel,
dcr2_sel,
dcr3_sel,
dcr4_sel,
dcr5_sel,
dcr6_sel,
dcr7_sel; // DCR selects
wire dwcr0_sel,
dwcr1_sel; // DWCR selects
reg dbg_bp_r;
`ifdef OR1200_DU_HWBKPTS
reg [31:0] match_cond0_ct;
reg [31:0] match_cond1_ct;
reg [31:0] match_cond2_ct;
reg [31:0] match_cond3_ct;
reg [31:0] match_cond4_ct;
reg [31:0] match_cond5_ct;
reg [31:0] match_cond6_ct;
reg [31:0] match_cond7_ct;
reg match_cond0_stb;
reg match_cond1_stb;
reg match_cond2_stb;
reg match_cond3_stb;
reg match_cond4_stb;
reg match_cond5_stb;
reg match_cond6_stb;
reg match_cond7_stb;
reg match0;
reg match1;
reg match2;
reg match3;
reg match4;
reg match5;
reg match6;
reg match7;
reg wpcntr0_match;
reg wpcntr1_match;
reg incr_wpcntr0;
reg incr_wpcntr1;
reg [10:0] wp;
reg dcpu_cycstb_r;
`endif
wire du_hwbkpt;
`ifdef OR1200_DU_READREGS
reg [31:0] spr_dat_o;
`endif
reg [13:0] except_stop; // Exceptions that stop because of DSR
`ifdef OR1200_DU_TB_IMPLEMENTED
wire tb_enw;
reg [7:0] tb_wadr;
reg [31:0] tb_timstmp;
`endif
wire [31:0] tbia_dat_o;
wire [31:0] tbim_dat_o;
wire [31:0] tbar_dat_o;
wire [31:0] tbts_dat_o;
//
// DU registers address decoder
//
`ifdef OR1200_DU_DMR1
assign dmr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR1));
`endif
`ifdef OR1200_DU_DMR2
assign dmr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DMR2));
`endif
`ifdef OR1200_DU_DSR
assign dsr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DSR));
`endif
`ifdef OR1200_DU_DRR
assign drr_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DRR));
`endif
`ifdef OR1200_DU_DVR0
assign dvr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR0));
`endif
`ifdef OR1200_DU_DVR1
assign dvr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR1));
`endif
`ifdef OR1200_DU_DVR2
assign dvr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR2));
`endif
`ifdef OR1200_DU_DVR3
assign dvr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR3));
`endif
`ifdef OR1200_DU_DVR4
assign dvr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR4));
`endif
`ifdef OR1200_DU_DVR5
assign dvr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR5));
`endif
`ifdef OR1200_DU_DVR6
assign dvr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR6));
`endif
`ifdef OR1200_DU_DVR7
assign dvr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DVR7));
`endif
`ifdef OR1200_DU_DCR0
assign dcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR0));
`endif
`ifdef OR1200_DU_DCR1
assign dcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR1));
`endif
`ifdef OR1200_DU_DCR2
assign dcr2_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR2));
`endif
`ifdef OR1200_DU_DCR3
assign dcr3_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR3));
`endif
`ifdef OR1200_DU_DCR4
assign dcr4_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR4));
`endif
`ifdef OR1200_DU_DCR5
assign dcr5_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR5));
`endif
`ifdef OR1200_DU_DCR6
assign dcr6_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR6));
`endif
`ifdef OR1200_DU_DCR7
assign dcr7_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DCR7));
`endif
`ifdef OR1200_DU_DWCR0
assign dwcr0_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR0));
`endif
`ifdef OR1200_DU_DWCR1
assign dwcr1_sel = (spr_cs && (spr_addr[`OR1200_DUOFS_BITS] == `OR1200_DU_DWCR1));
`endif
//
// Decode started exception
//
always @(du_except) begin
except_stop = 14'b0000_0000_0000;
casex (du_except)
13'b1_xxxx_xxxx_xxxx:
except_stop[`OR1200_DU_DRR_TTE] = 1'b1;
13'b0_1xxx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_IE] = 1'b1;
end
13'b0_01xx_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_IME] = 1'b1;
end
13'b0_001x_xxxx_xxxx:
except_stop[`OR1200_DU_DRR_IPFE] = 1'b1;
13'b0_0001_xxxx_xxxx: begin
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
end
13'b0_0000_1xxx_xxxx:
except_stop[`OR1200_DU_DRR_IIE] = 1'b1;
13'b0_0000_01xx_xxxx: begin
except_stop[`OR1200_DU_DRR_AE] = 1'b1;
end
13'b0_0000_001x_xxxx: begin
except_stop[`OR1200_DU_DRR_DME] = 1'b1;
end
13'b0_0000_0001_xxxx:
except_stop[`OR1200_DU_DRR_DPFE] = 1'b1;
13'b0_0000_0000_1xxx:
except_stop[`OR1200_DU_DRR_BUSEE] = 1'b1;
13'b0_0000_0000_01xx: begin
except_stop[`OR1200_DU_DRR_RE] = 1'b1;
end
13'b0_0000_0000_001x: begin
except_stop[`OR1200_DU_DRR_TE] = 1'b1;
end
13'b0_0000_0000_0001:
except_stop[`OR1200_DU_DRR_SCE] = 1'b1;
default:
except_stop = 14'b0000_0000_0000;
endcase
end
//
// dbg_bp_o is registered
//
assign dbg_bp_o = dbg_bp_r;
//
// Breakpoint activation register
//
always @(posedge clk or posedge rst)
if (rst)
dbg_bp_r <= #1 1'b0;
else if (!ex_freeze)
dbg_bp_r <= #1 |except_stop
`ifdef OR1200_DU_DMR1_ST
| ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]) & dmr1[`OR1200_DU_DMR1_ST]
`endif
`ifdef OR1200_DU_DMR1_BT
| (branch_op != `OR1200_BRANCHOP_NOP) & dmr1[`OR1200_DU_DMR1_BT]
`endif
;
else
dbg_bp_r <= #1 |except_stop;
//
// Write to DMR1
//
`ifdef OR1200_DU_DMR1
always @(posedge clk or posedge rst)
if (rst)
dmr1 <= 25'h000_0000;
else if (dmr1_sel && spr_write)
`ifdef OR1200_DU_HWBKPTS
dmr1 <= #1 spr_dat_i[24:0];
`else
dmr1 <= #1 {1'b0, spr_dat_i[23:22], 22'h00_0000};
`endif
`else
assign dmr1 = 25'h000_0000;
`endif
//
// Write to DMR2
//
`ifdef OR1200_DU_DMR2
always @(posedge clk or posedge rst)
if (rst)
dmr2 <= 24'h00_0000;
else if (dmr2_sel && spr_write)
dmr2 <= #1 spr_dat_i[23:0];
`else
assign dmr2 = 24'h00_0000;
`endif
//
// Write to DSR
//
`ifdef OR1200_DU_DSR
always @(posedge clk or posedge rst)
if (rst)
dsr <= {`OR1200_DU_DSR_WIDTH{1'b0}};
else if (dsr_sel && spr_write)
dsr <= #1 spr_dat_i[`OR1200_DU_DSR_WIDTH-1:0];
`else
assign dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
`endif
//
// Write to DRR
//
`ifdef OR1200_DU_DRR
always @(posedge clk or posedge rst)
if (rst)
drr <= 14'b0;
else if (drr_sel && spr_write)
drr <= #1 spr_dat_i[13:0];
else
drr <= #1 drr | except_stop;
`else
assign drr = 14'b0;
`endif
//
// Write to DVR0
//
`ifdef OR1200_DU_DVR0
always @(posedge clk or posedge rst)
if (rst)
dvr0 <= 32'h0000_0000;
else if (dvr0_sel && spr_write)
dvr0 <= #1 spr_dat_i[31:0];
`else
assign dvr0 = 32'h0000_0000;
`endif
//
// Write to DVR1
//
`ifdef OR1200_DU_DVR1
always @(posedge clk or posedge rst)
if (rst)
dvr1 <= 32'h0000_0000;
else if (dvr1_sel && spr_write)
dvr1 <= #1 spr_dat_i[31:0];
`else
assign dvr1 = 32'h0000_0000;
`endif
//
// Write to DVR2
//
`ifdef OR1200_DU_DVR2
always @(posedge clk or posedge rst)
if (rst)
dvr2 <= 32'h0000_0000;
else if (dvr2_sel && spr_write)
dvr2 <= #1 spr_dat_i[31:0];
`else
assign dvr2 = 32'h0000_0000;
`endif
//
// Write to DVR3
//
`ifdef OR1200_DU_DVR3
always @(posedge clk or posedge rst)
if (rst)
dvr3 <= 32'h0000_0000;
else if (dvr3_sel && spr_write)
dvr3 <= #1 spr_dat_i[31:0];
`else
assign dvr3 = 32'h0000_0000;
`endif
//
// Write to DVR4
//
`ifdef OR1200_DU_DVR4
always @(posedge clk or posedge rst)
if (rst)
dvr4 <= 32'h0000_0000;
else if (dvr4_sel && spr_write)
dvr4 <= #1 spr_dat_i[31:0];
`else
assign dvr4 = 32'h0000_0000;
`endif
//
// Write to DVR5
//
`ifdef OR1200_DU_DVR5
always @(posedge clk or posedge rst)
if (rst)
dvr5 <= 32'h0000_0000;
else if (dvr5_sel && spr_write)
dvr5 <= #1 spr_dat_i[31:0];
`else
assign dvr5 = 32'h0000_0000;
`endif
//
// Write to DVR6
//
`ifdef OR1200_DU_DVR6
always @(posedge clk or posedge rst)
if (rst)
dvr6 <= 32'h0000_0000;
else if (dvr6_sel && spr_write)
dvr6 <= #1 spr_dat_i[31:0];
`else
assign dvr6 = 32'h0000_0000;
`endif
//
// Write to DVR7
//
`ifdef OR1200_DU_DVR7
always @(posedge clk or posedge rst)
if (rst)
dvr7 <= 32'h0000_0000;
else if (dvr7_sel && spr_write)
dvr7 <= #1 spr_dat_i[31:0];
`else
assign dvr7 = 32'h0000_0000;
`endif
//
// Write to DCR0
//
`ifdef OR1200_DU_DCR0
always @(posedge clk or posedge rst)
if (rst)
dcr0 <= 8'h00;
else if (dcr0_sel && spr_write)
dcr0 <= #1 spr_dat_i[7:0];
`else
assign dcr0 = 8'h00;
`endif
//
// Write to DCR1
//
`ifdef OR1200_DU_DCR1
always @(posedge clk or posedge rst)
if (rst)
dcr1 <= 8'h00;
else if (dcr1_sel && spr_write)
dcr1 <= #1 spr_dat_i[7:0];
`else
assign dcr1 = 8'h00;
`endif
//
// Write to DCR2
//
`ifdef OR1200_DU_DCR2
always @(posedge clk or posedge rst)
if (rst)
dcr2 <= 8'h00;
else if (dcr2_sel && spr_write)
dcr2 <= #1 spr_dat_i[7:0];
`else
assign dcr2 = 8'h00;
`endif
//
// Write to DCR3
//
`ifdef OR1200_DU_DCR3
always @(posedge clk or posedge rst)
if (rst)
dcr3 <= 8'h00;
else if (dcr3_sel && spr_write)
dcr3 <= #1 spr_dat_i[7:0];
`else
assign dcr3 = 8'h00;
`endif
//
// Write to DCR4
//
`ifdef OR1200_DU_DCR4
always @(posedge clk or posedge rst)
if (rst)
dcr4 <= 8'h00;
else if (dcr4_sel && spr_write)
dcr4 <= #1 spr_dat_i[7:0];
`else
assign dcr4 = 8'h00;
`endif
//
// Write to DCR5
//
`ifdef OR1200_DU_DCR5
always @(posedge clk or posedge rst)
if (rst)
dcr5 <= 8'h00;
else if (dcr5_sel && spr_write)
dcr5 <= #1 spr_dat_i[7:0];
`else
assign dcr5 = 8'h00;
`endif
//
// Write to DCR6
//
`ifdef OR1200_DU_DCR6
always @(posedge clk or posedge rst)
if (rst)
dcr6 <= 8'h00;
else if (dcr6_sel && spr_write)
dcr6 <= #1 spr_dat_i[7:0];
`else
assign dcr6 = 8'h00;
`endif
//
// Write to DCR7
//
`ifdef OR1200_DU_DCR7
always @(posedge clk or posedge rst)
if (rst)
dcr7 <= 8'h00;
else if (dcr7_sel && spr_write)
dcr7 <= #1 spr_dat_i[7:0];
`else
assign dcr7 = 8'h00;
`endif
//
// Write to DWCR0
//
`ifdef OR1200_DU_DWCR0
always @(posedge clk or posedge rst)
if (rst)
dwcr0 <= 32'h0000_0000;
else if (dwcr0_sel && spr_write)
dwcr0 <= #1 spr_dat_i[31:0];
else if (incr_wpcntr0)
dwcr0[`OR1200_DU_DWCR_COUNT] <= #1 dwcr0[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr0 = 32'h0000_0000;
`endif
//
// Write to DWCR1
//
`ifdef OR1200_DU_DWCR1
always @(posedge clk or posedge rst)
if (rst)
dwcr1 <= 32'h0000_0000;
else if (dwcr1_sel && spr_write)
dwcr1 <= #1 spr_dat_i[31:0];
else if (incr_wpcntr1)
dwcr1[`OR1200_DU_DWCR_COUNT] <= #1 dwcr1[`OR1200_DU_DWCR_COUNT] + 16'h0001;
`else
assign dwcr1 = 32'h0000_0000;
`endif
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
always @(spr_addr or dsr or drr or dmr1 or dmr2
or dvr0 or dvr1 or dvr2 or dvr3 or dvr4
or dvr5 or dvr6 or dvr7
or dcr0 or dcr1 or dcr2 or dcr3 or dcr4
or dcr5 or dcr6 or dcr7
or dwcr0 or dwcr1
`ifdef OR1200_DU_TB_IMPLEMENTED
or tb_wadr or tbia_dat_o or tbim_dat_o
or tbar_dat_o or tbts_dat_o
`endif
)
casex (spr_addr[`OR1200_DUOFS_BITS]) // synopsys parallel_case
`ifdef OR1200_DU_DVR0
`OR1200_DU_DVR0:
spr_dat_o = dvr0;
`endif
`ifdef OR1200_DU_DVR1
`OR1200_DU_DVR1:
spr_dat_o = dvr1;
`endif
`ifdef OR1200_DU_DVR2
`OR1200_DU_DVR2:
spr_dat_o = dvr2;
`endif
`ifdef OR1200_DU_DVR3
`OR1200_DU_DVR3:
spr_dat_o = dvr3;
`endif
`ifdef OR1200_DU_DVR4
`OR1200_DU_DVR4:
spr_dat_o = dvr4;
`endif
`ifdef OR1200_DU_DVR5
`OR1200_DU_DVR5:
spr_dat_o = dvr5;
`endif
`ifdef OR1200_DU_DVR6
`OR1200_DU_DVR6:
spr_dat_o = dvr6;
`endif
`ifdef OR1200_DU_DVR7
`OR1200_DU_DVR7:
spr_dat_o = dvr7;
`endif
`ifdef OR1200_DU_DCR0
`OR1200_DU_DCR0:
spr_dat_o = {24'h00_0000, dcr0};
`endif
`ifdef OR1200_DU_DCR1
`OR1200_DU_DCR1:
spr_dat_o = {24'h00_0000, dcr1};
`endif
`ifdef OR1200_DU_DCR2
`OR1200_DU_DCR2:
spr_dat_o = {24'h00_0000, dcr2};
`endif
`ifdef OR1200_DU_DCR3
`OR1200_DU_DCR3:
spr_dat_o = {24'h00_0000, dcr3};
`endif
`ifdef OR1200_DU_DCR4
`OR1200_DU_DCR4:
spr_dat_o = {24'h00_0000, dcr4};
`endif
`ifdef OR1200_DU_DCR5
`OR1200_DU_DCR5:
spr_dat_o = {24'h00_0000, dcr5};
`endif
`ifdef OR1200_DU_DCR6
`OR1200_DU_DCR6:
spr_dat_o = {24'h00_0000, dcr6};
`endif
`ifdef OR1200_DU_DCR7
`OR1200_DU_DCR7:
spr_dat_o = {24'h00_0000, dcr7};
`endif
`ifdef OR1200_DU_DMR1
`OR1200_DU_DMR1:
spr_dat_o = {7'h00, dmr1};
`endif
`ifdef OR1200_DU_DMR2
`OR1200_DU_DMR2:
spr_dat_o = {8'h00, dmr2};
`endif
`ifdef OR1200_DU_DWCR0
`OR1200_DU_DWCR0:
spr_dat_o = dwcr0;
`endif
`ifdef OR1200_DU_DWCR1
`OR1200_DU_DWCR1:
spr_dat_o = dwcr1;
`endif
`ifdef OR1200_DU_DSR
`OR1200_DU_DSR:
spr_dat_o = {18'b0, dsr};
`endif
`ifdef OR1200_DU_DRR
`OR1200_DU_DRR:
spr_dat_o = {18'b0, drr};
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
`OR1200_DU_TBADR:
spr_dat_o = {24'h000000, tb_wadr};
`OR1200_DU_TBIA:
spr_dat_o = tbia_dat_o;
`OR1200_DU_TBIM:
spr_dat_o = tbim_dat_o;
`OR1200_DU_TBAR:
spr_dat_o = tbar_dat_o;
`OR1200_DU_TBTS:
spr_dat_o = tbts_dat_o;
`endif
default:
spr_dat_o = 32'h0000_0000;
endcase
`endif
//
// DSR alias
//
assign du_dsr = dsr;
`ifdef OR1200_DU_HWBKPTS
always @(posedge clk or posedge rst)
if (rst)
dcpu_cycstb_r <= 1'b0;
else
dcpu_cycstb_r <= #1 dcpu_cycstb_i;
//
// Compare To What (Match Condition 0)
//
always @(dcr0 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond0_ct = id_pc; // insn fetch EA
3'b010: match_cond0_ct = dcpu_adr_i; // load EA
3'b011: match_cond0_ct = dcpu_adr_i; // store EA
3'b100: match_cond0_ct = dcpu_dat_dc; // load data
3'b101: match_cond0_ct = dcpu_dat_lsu; // store data
3'b110: match_cond0_ct = dcpu_adr_i; // load/store EA
default:match_cond0_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 0)
//
always @(dcr0 or dcpu_cycstb_r or dcpu_we_i)
case (dcr0[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond0_stb = 1'b0; //comparison disabled
3'b001: match_cond0_stb = 1'b1; // insn fetch EA
3'b010: match_cond0_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond0_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond0_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond0_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond0_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 0
//
always @(match_cond0_stb or dcr0 or dvr0 or match_cond0_ct)
casex ({match_cond0_stb, dcr0[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match0 = 1'b0;
4'b1_001: match0 =
match_cond0_ct == dvr0;
4'b1_010: match0 =
match_cond0_ct < dvr0;
4'b1_011: match0 =
match_cond0_ct <= dvr0;
4'b1_100: match0 =
match_cond0_ct > dvr0;
4'b1_101: match0 =
match_cond0_ct >= dvr0;
4'b1_110: match0 =
match_cond0_ct != dvr0;
endcase
//
// Watchpoint 0
//
always @(dmr1 or match0)
case (dmr1[`OR1200_DU_DMR1_CW0])
2'b00: wp[0] = match0;
2'b01: wp[0] = match0;
2'b10: wp[0] = match0;
2'b11: wp[0] = 1'b0;
endcase
//
// Compare To What (Match Condition 1)
//
always @(dcr1 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond1_ct = id_pc; // insn fetch EA
3'b010: match_cond1_ct = dcpu_adr_i; // load EA
3'b011: match_cond1_ct = dcpu_adr_i; // store EA
3'b100: match_cond1_ct = dcpu_dat_dc; // load data
3'b101: match_cond1_ct = dcpu_dat_lsu; // store data
3'b110: match_cond1_ct = dcpu_adr_i; // load/store EA
default:match_cond1_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 1)
//
always @(dcr1 or dcpu_cycstb_r or dcpu_we_i)
case (dcr1[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond1_stb = 1'b0; //comparison disabled
3'b001: match_cond1_stb = 1'b1; // insn fetch EA
3'b010: match_cond1_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond1_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond1_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond1_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond1_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 1
//
always @(match_cond1_stb or dcr1 or dvr1 or match_cond1_ct)
casex ({match_cond1_stb, dcr1[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match1 = 1'b0;
4'b1_001: match1 = match_cond1_ct == dvr1;
4'b1_010: match1 = match_cond1_ct < dvr1;
4'b1_011: match1 = match_cond1_ct <= dvr1;
4'b1_100: match1 = match_cond1_ct > dvr1;
4'b1_101: match1 = match_cond1_ct >= dvr1;
4'b1_110: match1 = match_cond1_ct != dvr1;
endcase
//
// Watchpoint 1
//
always @(dmr1 or match1 or wp)
case (dmr1[`OR1200_DU_DMR1_CW1])
2'b00: wp[1] = match1;
2'b01: wp[1] = match1 & wp[0];
2'b10: wp[1] = match1 | wp[0];
2'b11: wp[1] = 1'b0;
endcase
//
// Compare To What (Match Condition 2)
//
always @(dcr2 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond2_ct = id_pc; // insn fetch EA
3'b010: match_cond2_ct = dcpu_adr_i; // load EA
3'b011: match_cond2_ct = dcpu_adr_i; // store EA
3'b100: match_cond2_ct = dcpu_dat_dc; // load data
3'b101: match_cond2_ct = dcpu_dat_lsu; // store data
3'b110: match_cond2_ct = dcpu_adr_i; // load/store EA
default:match_cond2_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 2)
//
always @(dcr2 or dcpu_cycstb_r or dcpu_we_i)
case (dcr2[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond2_stb = 1'b0; //comparison disabled
3'b001: match_cond2_stb = 1'b1; // insn fetch EA
3'b010: match_cond2_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond2_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond2_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond2_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond2_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 2
//
always @(match_cond2_stb or dcr2 or dvr2 or match_cond2_ct)
casex ({match_cond2_stb, dcr2[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match2 = 1'b0;
4'b1_001: match2 = match_cond2_ct == dvr2;
4'b1_010: match2 = match_cond2_ct < dvr2;
4'b1_011: match2 = match_cond2_ct <= dvr2;
4'b1_100: match2 = match_cond2_ct > dvr2;
4'b1_101: match2 = match_cond2_ct >= dvr2;
4'b1_110: match2 = match_cond2_ct != dvr2;
endcase
//
// Watchpoint 2
//
always @(dmr1 or match2 or wp)
case (dmr1[`OR1200_DU_DMR1_CW2])
2'b00: wp[2] = match2;
2'b01: wp[2] = match2 & wp[1];
2'b10: wp[2] = match2 | wp[1];
2'b11: wp[2] = 1'b0;
endcase
//
// Compare To What (Match Condition 3)
//
always @(dcr3 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond3_ct = id_pc; // insn fetch EA
3'b010: match_cond3_ct = dcpu_adr_i; // load EA
3'b011: match_cond3_ct = dcpu_adr_i; // store EA
3'b100: match_cond3_ct = dcpu_dat_dc; // load data
3'b101: match_cond3_ct = dcpu_dat_lsu; // store data
3'b110: match_cond3_ct = dcpu_adr_i; // load/store EA
default:match_cond3_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 3)
//
always @(dcr3 or dcpu_cycstb_r or dcpu_we_i)
case (dcr3[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond3_stb = 1'b0; //comparison disabled
3'b001: match_cond3_stb = 1'b1; // insn fetch EA
3'b010: match_cond3_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond3_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond3_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond3_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond3_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 3
//
always @(match_cond3_stb or dcr3 or dvr3 or match_cond3_ct)
casex ({match_cond3_stb, dcr3[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match3 = 1'b0;
4'b1_001: match3 = match_cond3_ct == dvr3;
4'b1_010: match3 = match_cond3_ct < dvr3;
4'b1_011: match3 = match_cond3_ct <= dvr3;
4'b1_100: match3 = match_cond3_ct > dvr3;
4'b1_101: match3 = match_cond3_ct >= dvr3;
4'b1_110: match3 = match_cond3_ct != dvr3;
endcase
//
// Watchpoint 3
//
always @(dmr1 or match3 or wp)
case (dmr1[`OR1200_DU_DMR1_CW3])
2'b00: wp[3] = match3;
2'b01: wp[3] = match3 & wp[2];
2'b10: wp[3] = match3 | wp[2];
2'b11: wp[3] = 1'b0;
endcase
//
// Compare To What (Match Condition 4)
//
always @(dcr4 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond4_ct = id_pc; // insn fetch EA
3'b010: match_cond4_ct = dcpu_adr_i; // load EA
3'b011: match_cond4_ct = dcpu_adr_i; // store EA
3'b100: match_cond4_ct = dcpu_dat_dc; // load data
3'b101: match_cond4_ct = dcpu_dat_lsu; // store data
3'b110: match_cond4_ct = dcpu_adr_i; // load/store EA
default:match_cond4_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 4)
//
always @(dcr4 or dcpu_cycstb_r or dcpu_we_i)
case (dcr4[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond4_stb = 1'b0; //comparison disabled
3'b001: match_cond4_stb = 1'b1; // insn fetch EA
3'b010: match_cond4_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond4_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond4_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond4_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond4_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 4
//
always @(match_cond4_stb or dcr4 or dvr4 or match_cond4_ct)
casex ({match_cond4_stb, dcr4[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match4 = 1'b0;
4'b1_001: match4 = match_cond4_ct == dvr4;
4'b1_010: match4 = match_cond4_ct < dvr4;
4'b1_011: match4 = match_cond4_ct <= dvr4;
4'b1_100: match4 = match_cond4_ct > dvr4;
4'b1_101: match4 = match_cond4_ct >= dvr4;
4'b1_110: match4 = match_cond4_ct != dvr4;
endcase
//
// Watchpoint 4
//
always @(dmr1 or match4 or wp)
case (dmr1[`OR1200_DU_DMR1_CW4])
2'b00: wp[4] = match4;
2'b01: wp[4] = match4 & wp[3];
2'b10: wp[4] = match4 | wp[3];
2'b11: wp[4] = 1'b0;
endcase
//
// Compare To What (Match Condition 5)
//
always @(dcr5 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond5_ct = id_pc; // insn fetch EA
3'b010: match_cond5_ct = dcpu_adr_i; // load EA
3'b011: match_cond5_ct = dcpu_adr_i; // store EA
3'b100: match_cond5_ct = dcpu_dat_dc; // load data
3'b101: match_cond5_ct = dcpu_dat_lsu; // store data
3'b110: match_cond5_ct = dcpu_adr_i; // load/store EA
default:match_cond5_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 5)
//
always @(dcr5 or dcpu_cycstb_r or dcpu_we_i)
case (dcr5[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond5_stb = 1'b0; //comparison disabled
3'b001: match_cond5_stb = 1'b1; // insn fetch EA
3'b010: match_cond5_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond5_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond5_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond5_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond5_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 5
//
always @(match_cond5_stb or dcr5 or dvr5 or match_cond5_ct)
casex ({match_cond5_stb, dcr5[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match5 = 1'b0;
4'b1_001: match5 = match_cond5_ct == dvr5;
4'b1_010: match5 = match_cond5_ct < dvr5;
4'b1_011: match5 = match_cond5_ct <= dvr5;
4'b1_100: match5 = match_cond5_ct > dvr5;
4'b1_101: match5 = match_cond5_ct >= dvr5;
4'b1_110: match5 = match_cond5_ct != dvr5;
endcase
//
// Watchpoint 5
//
always @(dmr1 or match5 or wp)
case (dmr1[`OR1200_DU_DMR1_CW5])
2'b00: wp[5] = match5;
2'b01: wp[5] = match5 & wp[4];
2'b10: wp[5] = match5 | wp[4];
2'b11: wp[5] = 1'b0;
endcase
//
// Compare To What (Match Condition 6)
//
always @(dcr6 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond6_ct = id_pc; // insn fetch EA
3'b010: match_cond6_ct = dcpu_adr_i; // load EA
3'b011: match_cond6_ct = dcpu_adr_i; // store EA
3'b100: match_cond6_ct = dcpu_dat_dc; // load data
3'b101: match_cond6_ct = dcpu_dat_lsu; // store data
3'b110: match_cond6_ct = dcpu_adr_i; // load/store EA
default:match_cond6_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 6)
//
always @(dcr6 or dcpu_cycstb_r or dcpu_we_i)
case (dcr6[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond6_stb = 1'b0; //comparison disabled
3'b001: match_cond6_stb = 1'b1; // insn fetch EA
3'b010: match_cond6_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond6_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond6_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond6_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond6_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 6
//
always @(match_cond6_stb or dcr6 or dvr6 or match_cond6_ct)
casex ({match_cond6_stb, dcr6[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match6 = 1'b0;
4'b1_001: match6 = match_cond6_ct == dvr6;
4'b1_010: match6 = match_cond6_ct < dvr6;
4'b1_011: match6 = match_cond6_ct <= dvr6;
4'b1_100: match6 = match_cond6_ct > dvr6;
4'b1_101: match6 = match_cond6_ct >= dvr6;
4'b1_110: match6 = match_cond6_ct != dvr6;
endcase
//
// Watchpoint 6
//
always @(dmr1 or match6 or wp)
case (dmr1[`OR1200_DU_DMR1_CW6])
2'b00: wp[6] = match6;
2'b01: wp[6] = match6 & wp[5];
2'b10: wp[6] = match6 | wp[5];
2'b11: wp[6] = 1'b0;
endcase
//
// Compare To What (Match Condition 7)
//
always @(dcr7 or id_pc or dcpu_adr_i or dcpu_dat_dc
or dcpu_dat_lsu or dcpu_we_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b001: match_cond7_ct = id_pc; // insn fetch EA
3'b010: match_cond7_ct = dcpu_adr_i; // load EA
3'b011: match_cond7_ct = dcpu_adr_i; // store EA
3'b100: match_cond7_ct = dcpu_dat_dc; // load data
3'b101: match_cond7_ct = dcpu_dat_lsu; // store data
3'b110: match_cond7_ct = dcpu_adr_i; // load/store EA
default:match_cond7_ct = dcpu_we_i ? dcpu_dat_lsu : dcpu_dat_dc;
endcase
//
// When To Compare (Match Condition 7)
//
always @(dcr7 or dcpu_cycstb_r or dcpu_we_i)
case (dcr7[`OR1200_DU_DCR_CT]) // synopsys parallel_case
3'b000: match_cond7_stb = 1'b0; //comparison disabled
3'b001: match_cond7_stb = 1'b1; // insn fetch EA
3'b010: match_cond7_stb = dcpu_cycstb_r && !dcpu_we_i; // load EA
3'b011: match_cond7_stb = dcpu_cycstb_r && dcpu_we_i; // store EA
3'b100: match_cond7_stb = dcpu_cycstb_r && !dcpu_we_i; // load data
3'b101: match_cond7_stb = dcpu_cycstb_r && dcpu_we_i; // store data
default:match_cond7_stb = dcpu_cycstb_r; // any load/store
endcase
//
// Match Condition 7
//
always @(match_cond7_stb or dcr7 or dvr7 or match_cond7_ct)
casex ({match_cond7_stb, dcr7[`OR1200_DU_DCR_CC]})
4'b0_xxx,
4'b1_000,
4'b1_111: match7 = 1'b0;
4'b1_001: match7 = match_cond7_ct == dvr7;
4'b1_010: match7 = match_cond7_ct < dvr7;
4'b1_011: match7 = match_cond7_ct <= dvr7;
4'b1_100: match7 = match_cond7_ct > dvr7;
4'b1_101: match7 = match_cond7_ct >= dvr7;
4'b1_110: match7 = match_cond7_ct != dvr7;
endcase
//
// Watchpoint 7
//
always @(dmr1 or match7 or wp)
case (dmr1[`OR1200_DU_DMR1_CW7])
2'b00: wp[7] = match7;
2'b01: wp[7] = match7 & wp[6];
2'b10: wp[7] = match7 | wp[6];
2'b11: wp[7] = 1'b0;
endcase
//
// Increment Watchpoint Counter 0
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE0])
incr_wpcntr0 = |(wp & ~dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr0 = 1'b0;
//
// Match Condition Watchpoint Counter 0
//
always @(dwcr0)
if (dwcr0[`OR1200_DU_DWCR_MATCH] == dwcr0[`OR1200_DU_DWCR_COUNT])
wpcntr0_match = 1'b1;
else
wpcntr0_match = 1'b0;
//
// Watchpoint 8
//
always @(dmr1 or wpcntr0_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW8])
2'b00: wp[8] = wpcntr0_match;
2'b01: wp[8] = wpcntr0_match & wp[7];
2'b10: wp[8] = wpcntr0_match | wp[7];
2'b11: wp[8] = 1'b0;
endcase
//
// Increment Watchpoint Counter 1
//
always @(wp or dmr2)
if (dmr2[`OR1200_DU_DMR2_WCE1])
incr_wpcntr1 = |(wp & dmr2[`OR1200_DU_DMR2_AWTC]);
else
incr_wpcntr1 = 1'b0;
//
// Match Condition Watchpoint Counter 1
//
always @(dwcr1)
if (dwcr1[`OR1200_DU_DWCR_MATCH] == dwcr1[`OR1200_DU_DWCR_COUNT])
wpcntr1_match = 1'b1;
else
wpcntr1_match = 1'b0;
//
// Watchpoint 9
//
always @(dmr1 or wpcntr1_match or wp)
case (dmr1[`OR1200_DU_DMR1_CW9])
2'b00: wp[9] = wpcntr1_match;
2'b01: wp[9] = wpcntr1_match & wp[8];
2'b10: wp[9] = wpcntr1_match | wp[8];
2'b11: wp[9] = 1'b0;
endcase
//
// Watchpoint 10
//
always @(dmr1 or dbg_ewt_i or wp)
case (dmr1[`OR1200_DU_DMR1_CW10])
2'b00: wp[10] = dbg_ewt_i;
2'b01: wp[10] = dbg_ewt_i & wp[9];
2'b10: wp[10] = dbg_ewt_i | wp[9];
2'b11: wp[10] = 1'b0;
endcase
`endif
//
// Watchpoints can cause trap exception
//
`ifdef OR1200_DU_HWBKPTS
assign du_hwbkpt = |(wp & dmr2[`OR1200_DU_DMR2_WGB]);
`else
assign du_hwbkpt = 1'b0;
`endif
`ifdef OR1200_DU_TB_IMPLEMENTED
//
// Simple trace buffer
// (right now hardcoded for Xilinx Virtex FPGAs)
//
// Stores last 256 instruction addresses, instruction
// machine words and ALU results
//
//
// Trace buffer write enable
//
assign tb_enw = ~ex_freeze & ~((ex_insn[31:26] == `OR1200_OR32_NOP) & ex_insn[16]);
//
// Trace buffer write address pointer
//
always @(posedge clk or posedge rst)
if (rst)
tb_wadr <= #1 8'h00;
else if (tb_enw)
tb_wadr <= #1 tb_wadr + 8'd1;
//
// Free running counter (time stamp)
//
always @(posedge clk or posedge rst)
if (rst)
tb_timstmp <= #1 32'h00000000;
else if (!dbg_bp_r)
tb_timstmp <= #1 tb_timstmp + 32'd1;
//
// Trace buffer RAMs
//
RAMB4_S16_S16 tbia_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(spr_dat_npc[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbia_dat_o[15:0])
);
RAMB4_S16_S16 tbia_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(spr_dat_npc[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbia_dat_o[31:16])
);
RAMB4_S16_S16 tbim_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(ex_insn[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbim_dat_o[15:0])
);
RAMB4_S16_S16 tbim_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(ex_insn[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbim_dat_o[31:16])
);
RAMB4_S16_S16 tbar_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(rf_dataw[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbar_dat_o[15:0])
);
RAMB4_S16_S16 tbar_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(rf_dataw[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbar_dat_o[31:16])
);
RAMB4_S16_S16 tbts_ramb4_s16_0(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(tb_timstmp[15:0]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbts_dat_o[15:0])
);
RAMB4_S16_S16 tbts_ramb4_s16_1(
.CLKA(clk),
.RSTA(rst),
.ADDRA(tb_wadr),
.DIA(tb_timstmp[31:16]),
.ENA(1'b1),
.WEA(tb_enw),
.DOA(),
.CLKB(clk),
.RSTB(rst),
.ADDRB(spr_addr[7:0]),
.DIB(16'h0000),
.ENB(1'b1),
.WEB(1'b0),
.DOB(tbts_dat_o[31:16])
);
`else
assign tbia_dat_o = 32'h0000_0000;
assign tbim_dat_o = 32'h0000_0000;
assign tbar_dat_o = 32'h0000_0000;
assign tbts_dat_o = 32'h0000_0000;
`endif // OR1200_DU_TB_IMPLEMENTED
`else // OR1200_DU_IMPLEMENTED
//
// When DU is not implemented, drive all outputs as would when DU is disabled
//
assign dbg_bp_o = 1'b0;
assign du_dsr = {`OR1200_DU_DSR_WIDTH{1'b0}};
assign du_hwbkpt = 1'b0;
//
// Read DU registers
//
`ifdef OR1200_DU_READREGS
assign spr_dat_o = 32'h0000_0000;
`ifdef OR1200_DU_UNUSED_ZERO
`endif
`endif
`endif
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: nto1_mux.v
//
// Description: N:1 MUX based on either binary-encoded or one-hot select input
// One-hot mode does not protect against multiple active SEL_ONEHOT inputs.
// Note: All port signals changed to all-upper-case (w.r.t. prior version).
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_nto1_mux #
(
parameter integer C_RATIO = 1, // Range: >=1
parameter integer C_SEL_WIDTH = 1, // Range: >=1; recommended: ceil_log2(C_RATIO)
parameter integer C_DATAOUT_WIDTH = 1, // Range: >=1
parameter integer C_ONEHOT = 0 // Values: 0 = binary-encoded (use SEL); 1 = one-hot (use SEL_ONEHOT)
)
(
input wire [C_RATIO-1:0] SEL_ONEHOT, // One-hot generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=1)
input wire [C_SEL_WIDTH-1:0] SEL, // Binary-encoded generic_baseblocks_v2_1_0_mux select (only used if C_ONEHOT=0)
input wire [C_RATIO*C_DATAOUT_WIDTH-1:0] IN, // Data input array (num_selections x data_width)
output wire [C_DATAOUT_WIDTH-1:0] OUT // Data output vector
);
wire [C_DATAOUT_WIDTH*C_RATIO-1:0] carry;
genvar i;
generate
if (C_ONEHOT == 0) begin : gen_encoded
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{(SEL==0)?1'b1:1'b0}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_enc
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{(SEL==i)?1'b1:1'b0}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end else begin : gen_onehot
assign carry[C_DATAOUT_WIDTH-1:0] = {C_DATAOUT_WIDTH{SEL_ONEHOT[0]}} & IN[C_DATAOUT_WIDTH-1:0];
for (i=1;i<C_RATIO;i=i+1) begin : gen_carrychain_hot
assign carry[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH] =
carry[i*C_DATAOUT_WIDTH-1:(i-1)*C_DATAOUT_WIDTH] |
{C_DATAOUT_WIDTH{SEL_ONEHOT[i]}} & IN[(i+1)*C_DATAOUT_WIDTH-1:i*C_DATAOUT_WIDTH];
end
end
endgenerate
assign OUT = carry[C_DATAOUT_WIDTH*C_RATIO-1:
C_DATAOUT_WIDTH*(C_RATIO-1)];
endmodule
`default_nettype wire
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR (against constant) with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_comparator_sel_static #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter C_VALUE = 4'b0,
// Static value to compare against.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {C_VALUE, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = C_VALUE;
end
// Instantiate one generic_baseblocks_v2_1_0_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_0_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A32OI_1_V
`define SKY130_FD_SC_HDLL__A32OI_1_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog wrapper for a32oi with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__a32oi.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_1 (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__a32oi_1 (
Y ,
A1,
A2,
A3,
B1,
B2
);
output Y ;
input A1;
input A2;
input A3;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__a32oi base (
.Y(Y),
.A1(A1),
.A2(A2),
.A3(A3),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A32OI_1_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: FIFO_16_256.v
// Megafunction Name(s):
// dcfifo
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 6.0 Build 202 06/20/2006 SP 1 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2006 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module FIFO_16_256 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrfull);
input aclr;
input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [15:0] q;
output wrfull;
wire sub_wire0;
wire [15:0] sub_wire1;
wire wrfull = sub_wire0;
wire [15:0] q = sub_wire1[15:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
.rdreq (rdreq),
.aclr (aclr),
.rdclk (rdclk),
.wrreq (wrreq),
.data (data),
.wrfull (sub_wire0),
.q (sub_wire1)
// synopsys translate_off
,
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrusedw ()
// synopsys translate_on
);
defparam
dcfifo_component.intended_device_family = "Cyclone II",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "OFF",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 16,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "4"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL FIFO_16_256_wave*.jpg FALSE
|
module usb_packet_fifo
( input reset,
input clock_in,
input clock_out,
input [15:0]ram_data_in,
input write_enable,
output reg [15:0]ram_data_out,
output reg pkt_waiting,
output reg have_space,
input read_enable,
input skip_packet ) ;
/* Some parameters for usage later on */
parameter DATA_WIDTH = 16 ;
parameter NUM_PACKETS = 4 ;
/* Create the RAM here */
reg [DATA_WIDTH-1:0] usb_ram [256*NUM_PACKETS-1:0] ;
/* Create the address signals */
reg [7-2+NUM_PACKETS:0] usb_ram_ain ;
reg [7:0] usb_ram_offset ;
reg [1:0] usb_ram_packet ;
wire [7-2+NUM_PACKETS:0] usb_ram_aout ;
reg isfull;
assign usb_ram_aout = {usb_ram_packet,usb_ram_offset} ;
// Check if there is one full packet to process
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
pkt_waiting <= 0;
else if (usb_ram_ain == usb_ram_aout)
pkt_waiting <= isfull;
else if (usb_ram_ain > usb_ram_aout)
pkt_waiting <= (usb_ram_ain - usb_ram_aout) >= 256;
else
pkt_waiting <= (usb_ram_ain + 10'b1111111111 - usb_ram_aout) >= 256;
end
// Check if there is room
always @(usb_ram_ain, usb_ram_aout)
begin
if (reset)
have_space <= 1;
else if (usb_ram_ain == usb_ram_aout)
have_space <= ~isfull;
else if (usb_ram_ain > usb_ram_aout)
have_space <= (usb_ram_ain - usb_ram_aout) <= 256 * (NUM_PACKETS - 1);
else
have_space <= (usb_ram_aout - usb_ram_ain) >= 256;
end
/* RAM Write Address process */
always @(posedge clock_in)
begin
if( reset )
usb_ram_ain <= 0 ;
else
if( write_enable )
begin
usb_ram_ain <= usb_ram_ain + 1 ;
if (usb_ram_ain + 1 == usb_ram_aout)
isfull <= 1;
end
end
/* RAM Writing process */
always @(posedge clock_in)
begin
if( write_enable )
begin
usb_ram[usb_ram_ain] <= ram_data_in ;
end
end
/* RAM Read Address process */
always @(posedge clock_out)
begin
if( reset )
begin
usb_ram_packet <= 0 ;
usb_ram_offset <= 0 ;
isfull <= 0;
end
else
if( skip_packet )
begin
usb_ram_packet <= usb_ram_packet + 1 ;
usb_ram_offset <= 0 ;
end
else if(read_enable)
if( usb_ram_offset == 8'b11111111 )
begin
usb_ram_offset <= 0 ;
usb_ram_packet <= usb_ram_packet + 1 ;
end
else
usb_ram_offset <= usb_ram_offset + 1 ;
if (usb_ram_ain == usb_ram_aout)
isfull <= 0;
end
/* RAM Reading Process */
always @(posedge clock_out)
begin
ram_data_out <= usb_ram[usb_ram_aout] ;
end
endmodule |
(** * Norm: Normalization of STLC *)
(* Chapter maintained by Andrew Tolmach *)
(* (Based on TAPL Ch. 12.) *)
Require Export Smallstep.
Hint Constructors multi.
(**
(This chapter is optional.)
In this chapter, we consider another fundamental theoretical property
of the simply typed lambda-calculus: the fact that the evaluation of a
well-typed program is guaranteed to halt in a finite number of
steps---i.e., every well-typed term is _normalizable_.
Unlike the type-safety properties we have considered so far, the
normalization property does not extend to full-blown programming
languages, because these languages nearly always extend the simply
typed lambda-calculus with constructs, such as general recursion
(as we discussed in the MoreStlc chapter) or recursive types, that can
be used to write nonterminating programs. However, the issue of
normalization reappears at the level of _types_ when we consider the
metatheory of polymorphic versions of the lambda calculus such as
F_omega: in this system, the language of types effectively contains a
copy of the simply typed lambda-calculus, and the termination of the
typechecking algorithm will hinge on the fact that a ``normalization''
operation on type expressions is guaranteed to terminate.
Another reason for studying normalization proofs is that they are some
of the most beautiful---and mind-blowing---mathematics to be found in
the type theory literature, often (as here) involving the fundamental
proof technique of _logical relations_.
The calculus we shall consider here is the simply typed
lambda-calculus over a single base type [bool] and with pairs. We'll
give full details of the development for the basic lambda-calculus
terms treating [bool] as an uninterpreted base type, and leave the
extension to the boolean operators and pairs to the reader. Even for
the base calculus, normalization is not entirely trivial to prove,
since each reduction of a term can duplicate redexes in subterms. *)
(** **** Exercise: 1 star *)
(** Where do we fail if we attempt to prove normalization by a
straightforward induction on the size of a well-typed term? *)
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * Language *)
(** We begin by repeating the relevant language definition, which is
similar to those in the MoreStlc chapter, and supporting results
including type preservation and step determinism. (We won't need
progress.) You may just wish to skip down to the Normalization
section... *)
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty
| TProd : ty -> ty -> ty
.
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* booleans *)
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
(* i.e., [if t0 then t1 else t2] *)
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y => if eq_id_dec x y then s else t
| tabs y T t1 => tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 => tapp (subst x s t1) (subst x s t2)
| tpair t1 t2 => tpair (subst x s t1) (subst x s t2)
| tfst t1 => tfst (subst x s t1)
| tsnd t1 => tsnd (subst x s t1)
| ttrue => ttrue
| tfalse => tfalse
| tif t0 t1 t2 => tif (subst x s t0) (subst x s t1) (subst x s t2)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
| v_true : value ttrue
| v_false : value tfalse
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* booleans *)
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t0 t0' t1 t2,
t0 ==> t0' ->
(tif t0 t1 t2) ==> (tif t0' t1 t2)
where "t1 '==>' t2" := (step t1 t2).
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
Notation step_normal_form := (normal_form step).
Lemma value__normal : forall t, value t -> step_normal_form t.
Proof with eauto.
intros t H; induction H; intros [t' ST]; inversion ST...
Qed.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
has_type Gamma (tvar x) T
| T_Abs : forall Gamma x T11 T12 t12,
has_type (extend Gamma x T11) t12 T12 ->
has_type Gamma (tabs x T11 t12) (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
has_type Gamma t1 (TArrow T1 T2) ->
has_type Gamma t2 T1 ->
has_type Gamma (tapp t1 t2) T2
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
has_type Gamma t1 T1 ->
has_type Gamma t2 T2 ->
has_type Gamma (tpair t1 t2) (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tfst t) T1
| T_Snd : forall Gamma t T1 T2,
has_type Gamma t (TProd T1 T2) ->
has_type Gamma (tsnd t) T2
(* booleans *)
| T_True : forall Gamma,
has_type Gamma ttrue TBool
| T_False : forall Gamma,
has_type Gamma tfalse TBool
| T_If : forall Gamma t0 t1 t2 T,
has_type Gamma t0 TBool ->
has_type Gamma t1 T ->
has_type Gamma t2 T ->
has_type Gamma (tif t0 t1 t2) T
.
Hint Constructors has_type.
Hint Extern 2 (has_type _ (tapp _ _) _) => eapply T_App; auto.
Hint Extern 2 (_ = _) => compute; reflexivity.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* booleans *)
| afi_if0 : forall x t0 t1 t2,
appears_free_in x t0 ->
appears_free_in x (tif t0 t1 t2)
| afi_if1 : forall x t0 t1 t2,
appears_free_in x t1 ->
appears_free_in x (tif t0 t1 t2)
| afi_if2 : forall x t0 t1 t2,
appears_free_in x t2 ->
appears_free_in x (tif t0 t1 t2)
.
Hint Constructors appears_free_in.
Definition closed (t:tm) :=
forall x, ~ appears_free_in x t.
Lemma context_invariance : forall Gamma Gamma' t S,
has_type Gamma t S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
has_type Gamma' t S.
Proof with eauto.
intros. generalize dependent Gamma'.
induction H;
intros Gamma' Heqv...
- (* T_Var *)
apply T_Var... rewrite <- Heqv...
- (* T_Abs *)
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend. destruct (eq_id_dec x y)...
- (* T_Pair *)
apply T_Pair...
- (* T_If *)
eapply T_If...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
has_type Gamma t T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
induction Htyp; inversion Hafi; subst...
- (* T_Abs *)
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Qed.
Corollary typable_empty__closed : forall t T,
has_type empty t T ->
closed t.
Proof.
intros. unfold closed. intros x H1.
destruct (free_in_context _ _ _ _ H1 H) as [T' C].
inversion C. Qed.
(* ###################################################################### *)
(** *** Preservation *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
has_type (extend Gamma x U) t S ->
has_type empty v U ->
has_type Gamma ([x:=v]t) S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- ([x:=v]t) S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
induction t;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
- (* tvar *)
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
+ (* x<>y *)
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
- (* tabs *)
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
+ (* x=y *)
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
+ (* x<>y *)
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
Qed.
Theorem preservation : forall t t' T,
has_type empty t T ->
t ==> t' ->
has_type empty t' T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
induction HT;
intros t' HeqGamma HE; subst; inversion HE; subst...
- (* T_App *)
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
+ (* ST_AppAbs *)
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
- (* T_Fst *)
inversion HT...
- (* T_Snd *)
inversion HT...
Qed.
(** [] *)
(* ###################################################################### *)
(** *** Determinism *)
Lemma step_deterministic :
deterministic step.
Proof with eauto.
unfold deterministic.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** * Normalization *)
(** Now for the actual normalization proof.
Our goal is to prove that every well-typed term evaluates to a
normal form. In fact, it turns out to be convenient to prove
something slightly stronger, namely that every well-typed term
evaluates to a _value_. This follows from the weaker property
anyway via the Progress lemma (why?) but otherwise we don't need
Progress, and we didn't bother re-proving it above.
Here's the key definition: *)
Definition halts (t:tm) : Prop := exists t', t ==>* t' /\ value t'.
(** A trivial fact: *)
Lemma value_halts : forall v, value v -> halts v.
Proof.
intros v H. unfold halts.
exists v. split.
apply multi_refl.
assumption.
Qed.
(** The key issue in the normalization proof (as in many proofs by
induction) is finding a strong enough induction hypothesis. To this
end, we begin by defining, for each type [T], a set [R_T] of closed
terms of type [T]. We will specify these sets using a relation [R]
and write [R T t] when [t] is in [R_T]. (The sets [R_T] are sometimes
called _saturated sets_ or _reducibility candidates_.)
Here is the definition of [R] for the base language:
- [R bool t] iff [t] is a closed term of type [bool] and [t] halts in a value
- [R (T1 -> T2) t] iff [t] is a closed term of type [T1 -> T2] and [t] halts
in a value _and_ for any term [s] such that [R T1 s], we have [R
T2 (t s)]. *)
(** This definition gives us the strengthened induction hypothesis that we
need. Our primary goal is to show that all _programs_ ---i.e., all
closed terms of base type---halt. But closed terms of base type can
contain subterms of functional type, so we need to know something
about these as well. Moreover, it is not enough to know that these
subterms halt, because the application of a normalized function to a
normalized argument involves a substitution, which may enable more
evaluation steps. So we need a stronger condition for terms of
functional type: not only should they halt themselves, but, when
applied to halting arguments, they should yield halting results.
The form of [R] is characteristic of the _logical relations_ proof
technique. (Since we are just dealing with unary relations here, we
could perhaps more properly say _logical predicates_.) If we want to
prove some property [P] of all closed terms of type [A], we proceed by
proving, by induction on types, that all terms of type [A] _possess_
property [P], all terms of type [A->A] _preserve_ property [P], all
terms of type [(A->A)->(A->A)] _preserve the property of preserving_
property [P], and so on. We do this by defining a family of
predicates, indexed by types. For the base type [A], the predicate is
just [P]. For functional types, it says that the function should map
values satisfying the predicate at the input type to values satisfying
the predicate at the output type.
When we come to formalize the definition of [R] in Coq, we hit a
problem. The most obvious formulation would be as a parameterized
Inductive proposition like this:
Inductive R : ty -> tm -> Prop :=
| R_bool : forall b t, has_type empty t TBool ->
halts t ->
R TBool t
| R_arrow : forall T1 T2 t, has_type empty t (TArrow T1 T2) ->
halts t ->
(forall s, R T1 s -> R T2 (tapp t s)) ->
R (TArrow T1 T2) t.
Unfortunately, Coq rejects this definition because it violates the
_strict positivity requirement_ for inductive definitions, which says
that the type being defined must not occur to the left of an arrow in
the type of a constructor argument. Here, it is the third argument to
[R_arrow], namely [(forall s, R T1 s -> R TS (tapp t s))], and
specifically the [R T1 s] part, that violates this rule. (The
outermost arrows separating the constructor arguments don't count when
applying this rule; otherwise we could never have genuinely inductive
predicates at all!) The reason for the rule is that types defined
with non-positive recursion can be used to build non-terminating
functions, which as we know would be a disaster for Coq's logical
soundness. Even though the relation we want in this case might be
perfectly innocent, Coq still rejects it because it fails the
positivity test.
Fortunately, it turns out that we _can_ define [R] using a
[Fixpoint]: *)
Fixpoint R (T:ty) (t:tm) {struct T} : Prop :=
has_type empty t T /\ halts t /\
(match T with
| TBool => True
| TArrow T1 T2 => (forall s, R T1 s -> R T2 (tapp t s))
(* FILL IN HERE *)
| TProd T1 T2 => False (* ... and delete this line *)
end).
(** As immediate consequences of this definition, we have that every
element of every set [R_T] halts in a value and is closed with type
[t] :*)
Lemma R_halts : forall {T} {t}, R T t -> halts t.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
Lemma R_typable_empty : forall {T} {t}, R T t -> has_type empty t T.
Proof.
intros. destruct T; unfold R in H; inversion H; inversion H1; assumption.
Qed.
(** Now we proceed to show the main result, which is that every
well-typed term of type [T] is an element of [R_T]. Together with
[R_halts], that will show that every well-typed term halts in a
value. *)
(* ###################################################################### *)
(** ** Membership in [R_T] is invariant under evaluation *)
(** We start with a preliminary lemma that shows a kind of strong
preservation property, namely that membership in [R_T] is _invariant_
under evaluation. We will need this property in both directions,
i.e. both to show that a term in [R_T] stays in [R_T] when it takes a
forward step, and to show that any term that ends up in [R_T] after a
step must have been in [R_T] to begin with.
First of all, an easy preliminary lemma. Note that in the forward
direction the proof depends on the fact that our language is
determinstic. This lemma might still be true for non-deterministic
languages, but the proof would be harder! *)
Lemma step_preserves_halting : forall t t', (t ==> t') -> (halts t <-> halts t').
Proof.
intros t t' ST. unfold halts.
split.
- (* -> *)
intros [t'' [STM V]].
inversion STM; subst.
apply ex_falso_quodlibet. apply value__normal in V. unfold normal_form in V. apply V. exists t'. auto.
rewrite (step_deterministic _ _ _ ST H). exists t''. split; assumption.
- (* <- *)
intros [t'0 [STM V]].
exists t'0. split; eauto.
Qed.
(** Now the main lemma, which comes in two parts, one for each
direction. Each proceeds by induction on the structure of the type
[T]. In fact, this is where we make fundamental use of the
structure of types.
One requirement for staying in [R_T] is to stay in type [T]. In the
forward direction, we get this from ordinary type Preservation. *)
Lemma step_preserves_R : forall T t t', (t ==> t') -> R T t -> R T t'.
Proof.
induction T; intros t t' E Rt; unfold R; fold R; unfold R in Rt; fold R in Rt;
destruct Rt as [typable_empty_t [halts_t RRt]].
(* TBool *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
auto.
(* TArrow *)
split. eapply preservation; eauto.
split. apply (step_preserves_halting _ _ E); eauto.
intros.
eapply IHT2.
apply ST_App1. apply E.
apply RRt; auto.
(* FILL IN HERE *) Admitted.
(** The generalization to multiple steps is trivial: *)
Lemma multistep_preserves_R : forall T t t',
(t ==>* t') -> R T t -> R T t'.
Proof.
intros T t t' STM; induction STM; intros.
assumption.
apply IHSTM. eapply step_preserves_R. apply H. assumption.
Qed.
(** In the reverse direction, we must add the fact that [t] has type
[T] before stepping as an additional hypothesis. *)
Lemma step_preserves_R' : forall T t t',
has_type empty t T -> (t ==> t') -> R T t' -> R T t.
Proof.
(* FILL IN HERE *) Admitted.
Lemma multistep_preserves_R' : forall T t t',
has_type empty t T -> (t ==>* t') -> R T t' -> R T t.
Proof.
intros T t t' HT STM.
induction STM; intros.
assumption.
eapply step_preserves_R'. assumption. apply H. apply IHSTM.
eapply preservation; eauto. auto.
Qed.
(* ###################################################################### *)
(** ** Closed instances of terms of type [T] belong to [R_T] *)
(** Now we proceed to show that every term of type [T] belongs to
[R_T]. Here, the induction will be on typing derivations (it would be
surprising to see a proof about well-typed terms that did not
somewhere involve induction on typing derivations!). The only
technical difficulty here is in dealing with the abstraction case.
Since we are arguing by induction, the demonstration that a term
[tabs x T1 t2] belongs to [R_(T1->T2)] should involve applying the
induction hypothesis to show that [t2] belongs to [R_(T2)]. But
[R_(T2)] is defined to be a set of _closed_ terms, while [t2] may
contain [x] free, so this does not make sense.
This problem is resolved by using a standard trick to suitably
generalize the induction hypothesis: instead of proving a statement
involving a closed term, we generalize it to cover all closed
_instances_ of an open term [t]. Informally, the statement of the
lemma will look like this:
If [x1:T1,..xn:Tn |- t : T] and [v1,...,vn] are values such that
[R T1 v1], [R T2 v2], ..., [R Tn vn], then
[R T ([x1:=v1][x2:=v2]...[xn:=vn]t)].
The proof will proceed by induction on the typing derivation
[x1:T1,..xn:Tn |- t : T]; the most interesting case will be the one
for abstraction. *)
(* ###################################################################### *)
(** *** Multisubstitutions, multi-extensions, and instantiations *)
(** However, before we can proceed to formalize the statement and
proof of the lemma, we'll need to build some (rather tedious)
machinery to deal with the fact that we are performing _multiple_
substitutions on term [t] and _multiple_ extensions of the typing
context. In particular, we must be precise about the order in which
the substitutions occur and how they act on each other. Often these
details are simply elided in informal paper proofs, but of course Coq
won't let us do that. Since here we are substituting closed terms, we
don't need to worry about how one substitution might affect the term
put in place by another. But we still do need to worry about the
_order_ of substitutions, because it is quite possible for the same
identifier to appear multiple times among the [x1,...xn] with
different associated [vi] and [Ti].
To make everything precise, we will assume that environments are
extended from left to right, and multiple substitutions are performed
from right to left. To see that this is consistent, suppose we have
an environment written as [...,y:bool,...,y:nat,...] and a
corresponding term substitution written as [...[y:=(tbool
true)]...[y:=(tnat 3)]...t]. Since environments are extended from
left to right, the binding [y:nat] hides the binding [y:bool]; since
substitutions are performed right to left, we do the substitution
[y:=(tnat 3)] first, so that the substitution [y:=(tbool true)] has
no effect. Substitution thus correctly preserves the type of the term.
With these points in mind, the following definitions should make sense.
A _multisubstitution_ is the result of applying a list of
substitutions, which we call an _environment_. *)
Definition env := list (id * tm).
Fixpoint msubst (ss:env) (t:tm) {struct ss} : tm :=
match ss with
| nil => t
| ((x,s)::ss') => msubst ss' ([x:=s]t)
end.
(** We need similar machinery to talk about repeated extension of a
typing context using a list of (identifier, type) pairs, which we
call a _type assignment_. *)
Definition tass := list (id * ty).
Fixpoint mextend (Gamma : context) (xts : tass) :=
match xts with
| nil => Gamma
| ((x,v)::xts') => extend (mextend Gamma xts') x v
end.
(** We will need some simple operations that work uniformly on
environments and type assigments *)
Fixpoint lookup {X:Set} (k : id) (l : list (id * X)) {struct l} : option X :=
match l with
| nil => None
| (j,x) :: l' =>
if eq_id_dec j k then Some x else lookup k l'
end.
Fixpoint drop {X:Set} (n:id) (nxs:list (id * X)) {struct nxs} : list (id * X) :=
match nxs with
| nil => nil
| ((n',x)::nxs') => if eq_id_dec n' n then drop n nxs' else (n',x)::(drop n nxs')
end.
(** An _instantiation_ combines a type assignment and a value
environment with the same domains, where corresponding elements are
in R *)
Inductive instantiation : tass -> env -> Prop :=
| V_nil : instantiation nil nil
| V_cons : forall x T v c e, value v -> R T v -> instantiation c e -> instantiation ((x,T)::c) ((x,v)::e).
(** We now proceed to prove various properties of these definitions. *)
(* ###################################################################### *)
(** *** More Substitution Facts *)
(** First we need some additional lemmas on (ordinary) substitution. *)
Lemma vacuous_substitution : forall t x,
~ appears_free_in x t ->
forall t', [x:=t']t = t.
Proof with eauto.
(* FILL IN HERE *) Admitted.
Lemma subst_closed: forall t,
closed t ->
forall x t', [x:=t']t = t.
Proof.
intros. apply vacuous_substitution. apply H. Qed.
Lemma subst_not_afi : forall t x v, closed v -> ~ appears_free_in x ([x:=v]t).
Proof with eauto. (* rather slow this way *)
unfold closed, not.
induction t; intros x v P A; simpl in A.
- (* tvar *)
destruct (eq_id_dec x i)...
inversion A; subst. auto.
- (* tapp *)
inversion A; subst...
- (* tabs *)
destruct (eq_id_dec x i)...
inversion A; subst...
inversion A; subst...
- (* tpair *)
inversion A; subst...
- (* tfst *)
inversion A; subst...
- (* tsnd *)
inversion A; subst...
- (* ttrue *)
inversion A.
- (* tfalse *)
inversion A.
- (* tif *)
inversion A; subst...
Qed.
Lemma duplicate_subst : forall t' x t v,
closed v -> [x:=t]([x:=v]t') = [x:=v]t'.
Proof.
intros. eapply vacuous_substitution. apply subst_not_afi. auto.
Qed.
Lemma swap_subst : forall t x x1 v v1, x <> x1 -> closed v -> closed v1 ->
[x1:=v1]([x:=v]t) = [x:=v]([x1:=v1]t).
Proof with eauto.
induction t; intros; simpl.
- (* tvar *)
destruct (eq_id_dec x i); destruct (eq_id_dec x1 i).
subst. apply ex_falso_quodlibet...
subst. simpl. rewrite eq_id. apply subst_closed...
subst. simpl. rewrite eq_id. rewrite subst_closed...
simpl. rewrite neq_id... rewrite neq_id...
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Properties of multi-substitutions *)
Lemma msubst_closed: forall t, closed t -> forall ss, msubst ss t = t.
Proof.
induction ss.
reflexivity.
destruct a. simpl. rewrite subst_closed; assumption.
Qed.
(** Closed environments are those that contain only closed terms. *)
Fixpoint closed_env (env:env) {struct env} :=
match env with
| nil => True
| (x,t)::env' => closed t /\ closed_env env'
end.
(** Next come a series of lemmas charcterizing how [msubst] of closed terms
distributes over [subst] and over each term form *)
Lemma subst_msubst: forall env x v t, closed v -> closed_env env ->
msubst env ([x:=v]t) = [x:=v](msubst (drop x env) t).
Proof.
induction env0; intros.
auto.
destruct a. simpl.
inversion H0. fold closed_env in H2.
destruct (eq_id_dec i x).
subst. rewrite duplicate_subst; auto.
simpl. rewrite swap_subst; eauto.
Qed.
Lemma msubst_var: forall ss x, closed_env ss ->
msubst ss (tvar x) =
match lookup x ss with
| Some t => t
| None => tvar x
end.
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x).
apply msubst_closed. inversion H; auto.
apply IHss. inversion H; auto.
Qed.
Lemma msubst_abs: forall ss x T t,
msubst ss (tabs x T t) = tabs x T (msubst (drop x ss) t).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. destruct (eq_id_dec i x); simpl; auto.
Qed.
Lemma msubst_app : forall ss t1 t2, msubst ss (tapp t1 t2) = tapp (msubst ss t1) (msubst ss t2).
Proof.
induction ss; intros.
reflexivity.
destruct a.
simpl. rewrite <- IHss. auto.
Qed.
(** You'll need similar functions for the other term constructors. *)
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** Properties of multi-extensions *)
(** We need to connect the behavior of type assignments with that of their
corresponding contexts. *)
Lemma mextend_lookup : forall (c : tass) (x:id), lookup x c = (mextend empty c) x.
Proof.
induction c; intros.
auto.
destruct a. unfold lookup, mextend, extend. destruct (eq_id_dec i x); auto.
Qed.
Lemma mextend_drop : forall (c: tass) Gamma x x',
mextend Gamma (drop x c) x' = if eq_id_dec x x' then Gamma x' else mextend Gamma c x'.
induction c; intros.
destruct (eq_id_dec x x'); auto.
destruct a. simpl.
destruct (eq_id_dec i x).
subst. rewrite IHc.
destruct (eq_id_dec x x'). auto. unfold extend. rewrite neq_id; auto.
simpl. unfold extend. destruct (eq_id_dec i x').
subst.
destruct (eq_id_dec x x').
subst. exfalso. auto.
auto.
auto.
Qed.
(* ###################################################################### *)
(** *** Properties of Instantiations *)
(** These are strightforward. *)
Lemma instantiation_domains_match: forall {c} {e},
instantiation c e -> forall {x} {T}, lookup x c = Some T -> exists t, lookup x e = Some t.
Proof.
intros c e V. induction V; intros x0 T0 C.
solve by inversion .
simpl in *.
destruct (eq_id_dec x x0); eauto.
Qed.
Lemma instantiation_env_closed : forall c e, instantiation c e -> closed_env e.
Proof.
intros c e V; induction V; intros.
econstructor.
unfold closed_env. fold closed_env.
split. eapply typable_empty__closed. eapply R_typable_empty. eauto.
auto.
Qed.
Lemma instantiation_R : forall c e, instantiation c e ->
forall x t T, lookup x c = Some T ->
lookup x e = Some t -> R T t.
Proof.
intros c e V. induction V; intros x' t' T' G E.
solve by inversion.
unfold lookup in *. destruct (eq_id_dec x x').
inversion G; inversion E; subst. auto.
eauto.
Qed.
Lemma instantiation_drop : forall c env,
instantiation c env -> forall x, instantiation (drop x c) (drop x env).
Proof.
intros c e V. induction V.
intros. simpl. constructor.
intros. unfold drop. destruct (eq_id_dec x x0); auto. constructor; eauto.
Qed.
(* ###################################################################### *)
(** *** Congruence lemmas on multistep *)
(** We'll need just a few of these; add them as the demand arises. *)
Lemma multistep_App2 : forall v t t',
value v -> (t ==>* t') -> (tapp v t) ==>* (tapp v t').
Proof.
intros v t t' V STM. induction STM.
apply multi_refl.
eapply multi_step.
apply ST_App2; eauto. auto.
Qed.
(* FILL IN HERE *)
(* ###################################################################### *)
(** *** The R Lemma. *)
(** We finally put everything together.
The key lemma about preservation of typing under substitution can
be lifted to multi-substitutions: *)
Lemma msubst_preserves_typing : forall c e,
instantiation c e ->
forall Gamma t S, has_type (mextend Gamma c) t S ->
has_type Gamma (msubst e t) S.
Proof.
induction 1; intros.
simpl in H. simpl. auto.
simpl in H2. simpl.
apply IHinstantiation.
eapply substitution_preserves_typing; eauto.
apply (R_typable_empty H0).
Qed.
(** And at long last, the main lemma. *)
Lemma msubst_R : forall c env t T,
has_type (mextend empty c) t T -> instantiation c env -> R T (msubst env t).
Proof.
intros c env0 t T HT V.
generalize dependent env0.
(* We need to generalize the hypothesis a bit before setting up the induction. *)
remember (mextend empty c) as Gamma.
assert (forall x, Gamma x = lookup x c).
intros. rewrite HeqGamma. rewrite mextend_lookup. auto.
clear HeqGamma.
generalize dependent c.
induction HT; intros.
- (* T_Var *)
rewrite H0 in H. destruct (instantiation_domains_match V H) as [t P].
eapply instantiation_R; eauto.
rewrite msubst_var. rewrite P. auto. eapply instantiation_env_closed; eauto.
- (* T_Abs *)
rewrite msubst_abs.
(* We'll need variants of the following fact several times, so its simplest to
establish it just once. *)
assert (WT: has_type empty (tabs x T11 (msubst (drop x env0) t12)) (TArrow T11 T12)).
eapply T_Abs. eapply msubst_preserves_typing. eapply instantiation_drop; eauto.
eapply context_invariance. apply HT.
intros.
unfold extend. rewrite mextend_drop. destruct (eq_id_dec x x0). auto.
rewrite H.
clear - c n. induction c.
simpl. rewrite neq_id; auto.
simpl. destruct a. unfold extend. destruct (eq_id_dec i x0); auto.
unfold R. fold R. split.
auto.
split. apply value_halts. apply v_abs.
intros.
destruct (R_halts H0) as [v [P Q]].
pose proof (multistep_preserves_R _ _ _ P H0).
apply multistep_preserves_R' with (msubst ((x,v)::env0) t12).
eapply T_App. eauto.
apply R_typable_empty; auto.
eapply multi_trans. eapply multistep_App2; eauto.
eapply multi_R.
simpl. rewrite subst_msubst.
eapply ST_AppAbs; eauto.
eapply typable_empty__closed.
apply (R_typable_empty H1).
eapply instantiation_env_closed; eauto.
eapply (IHHT ((x,T11)::c)).
intros. unfold extend, lookup. destruct (eq_id_dec x x0); auto.
constructor; auto.
- (* T_App *)
rewrite msubst_app.
destruct (IHHT1 c H env0 V) as [_ [_ P1]].
pose proof (IHHT2 c H env0 V) as P2. fold R in P1. auto.
(* FILL IN HERE *) Admitted.
(* ###################################################################### *)
(** *** Normalization Theorem *)
Theorem normalization : forall t T, has_type empty t T -> halts t.
Proof.
intros.
replace t with (msubst nil t) by reflexivity.
apply (@R_halts T).
apply (msubst_R nil); eauto.
eapply V_nil.
Qed.
(** $Date$ *)
|
//+FHDR------------------------------------------------------------------------
//Copyright (c) 2013 Latin Group American Integhrated Circuit, Inc. All rights reserved
//GLADIC Open Source RTL
//-----------------------------------------------------------------------------
//FILE NAME :
//DEPARTMENT : IC Design / Verification
//AUTHOR : Felipe Fernandes da Costa
//AUTHOR’S EMAIL :
//-----------------------------------------------------------------------------
//RELEASE HISTORY
//VERSION DATE AUTHOR DESCRIPTION
//1.0 YYYY-MM-DD name
//-----------------------------------------------------------------------------
//KEYWORDS : General file searching keywords, leave blank if none.
//-----------------------------------------------------------------------------
//PURPOSE : ECSS_E_ST_50_12C_31_july_2008
//-----------------------------------------------------------------------------
//PARAMETERS
//PARAM NAME RANGE : DESCRIPTION : DEFAULT : UNITS
//e.g.DATA_WIDTH [32,16] : width of the data : 32:
//-----------------------------------------------------------------------------
//REUSE ISSUES
//Reset Strategy :
//Clock Domains :
//Critical Timing :
//Test Features :
//Asynchronous I/F :
//Scan Methodology :
//Instantiations :
//Synthesizable (y/n) :
//Other :
//-FHDR------------------------------------------------------------------------
module counter_neg(
input negedge_clk,
input rx_resetn,
input rx_din,
output reg is_control,
output reg [5:0] counter_neg
);
reg control_bit_found;
always@(posedge negedge_clk or negedge rx_resetn)
begin
if(!rx_resetn)
begin
is_control <= 1'b0;
control_bit_found <= 1'b0;
counter_neg <= 6'd1;
end
else
begin
control_bit_found <= rx_din;
case(counter_neg)
6'd1:
begin
counter_neg <= 6'd2;
end
6'd2:
begin
if(control_bit_found)
begin
is_control <= 1'b1;
end
else
begin
is_control <= 1'b0;
end
counter_neg <= 6'd4;
end
6'd4:
begin
is_control <= 1'b0;
if(is_control)
begin
counter_neg <= 6'd2;
end
else
begin
counter_neg <= 6'd8;
end
end
6'd8:
begin
is_control <= 1'b0;
counter_neg <= 6'd16;
end
6'd16:
begin
is_control <= 1'b0;
counter_neg <= 6'd32;
end
6'd32:
begin
is_control <= 1'b0;
counter_neg <= 6'd2;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_PP_V
/**
* srsdfrtp: Scan flop with sleep mode, inverted reset, non-inverted
* clock, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_pr_pp_pkg_sn/sky130_fd_sc_lp__udp_dff_pr_pp_pkg_sn.v"
`include "../../models/udp_mux_2to1/sky130_fd_sc_lp__udp_mux_2to1.v"
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__srsdfrtp (
Q ,
CLK ,
D ,
SCD ,
SCE ,
RESET_B,
SLEEP_B,
KAPWR ,
VPWR ,
VGND ,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input RESET_B;
input SLEEP_B;
input KAPWR ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
// Local signals
wire RESET ;
wire mux_out ;
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire SCD_delayed ;
wire SCE_delayed ;
wire RESET_B_delayed ;
wire CLK_delayed ;
wire awake ;
wire cond0 ;
wire cond1 ;
wire cond2 ;
wire cond3 ;
wire cond4 ;
wire pwrgood_pp0_out_Q;
// Name Output Other arguments
not not0 (RESET , RESET_B_delayed );
sky130_fd_sc_lp__udp_mux_2to1 mux_2to10 (mux_out , D_delayed, SCD_delayed, SCE_delayed );
sky130_fd_sc_lp__udp_dff$PR_pp$PKG$sN dff0 (buf_Q , mux_out, CLK_delayed, RESET, SLEEP_B, notifier, KAPWR, VGND, VPWR);
assign awake = ( ( SLEEP_B === 1'b1 ) && awake );
assign cond0 = ( ( RESET_B_delayed === 1'b1 ) && awake );
assign cond1 = ( ( SCE_delayed === 1'b0 ) && cond0 && awake );
assign cond2 = ( ( SCE_delayed === 1'b1 ) && cond0 && awake );
assign cond3 = ( ( D_delayed !== SCD_delayed ) && cond0 && awake );
assign cond4 = ( ( RESET_B === 1'b1 ) && awake );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Q, buf_Q, VPWR, VGND );
buf buf0 (Q , pwrgood_pp0_out_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__SRSDFRTP_BEHAVIORAL_PP_V |
(** * Smallstep: Small-step Operational Semantics *)
Set Warnings "-notation-overridden,-parsing".
From Coq Require Import Arith.Arith.
From Coq Require Import Arith.EqNat.
From Coq Require Import Init.Nat.
From Coq Require Import Lia.
From Coq Require Import Lists.List.
Import ListNotations.
From PLF Require Import Maps.
From PLF Require Import Imp.
(** The evaluators we have seen so far (for [aexp]s, [bexp]s,
commands, ...) have been formulated in a "big-step" style: they
specify how a given expression can be evaluated to its final
value (or a command plus a store to a final store) "all in one big
step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized it, called it _natural semantics_.
But there are some things it does not do well. In particular, it
does not give us a natural way of talking about _concurrent_
programming languages, where the semantics of a program -- i.e.,
the essence of how it behaves -- is not just which input states
get mapped to which output states, but also includes the
intermediate states that it passes through along the way, since
these states can also be observed by concurrently executing code.
Another shortcoming of the big-step style is more technical, but
critical in many situations. Suppose we want to define a variant
of Imp where variables could hold _either_ numbers _or_ lists of
numbers. In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One possibility is
to maintain the convention that every arithmetic expression
evaluates to some number by choosing some way of viewing a list as
a number -- e.g., by specifying that a list should be interpreted
as [0] when it occurs in a context expecting a number. But this
is really a bit of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- i.e., it doesn't
evaluate to any result at all. And we can easily do this: we just
have to formulate [aeval] and [beval] as [Inductive] propositions
rather than [Fixpoint]s, so that we can make them partial functions
instead of total ones.
Now, however, we encounter a serious deficiency. In this
language, a command might fail to map a given starting state to
any ending state for _two quite different reasons_: either because
the execution gets into an infinite loop or because, at some
point, the program tries to do an operation that makes no sense,
such as adding a number to a list, so that none of the evaluation
rules can be applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- should not be confused. In particular, we
want to _allow_ the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but _prevent_ the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a way
of presenting the semantics that allows us to distinguish
nontermination from erroneous "stuck states."
So, for lots of reasons, we'd often like to have a finer-grained
way of defining and reasoning about program behaviors. This is
the topic of the present chapter. Our goal is to replace the
"big-step" [eval] relation with a "small-step" relation that
specifies, for a given program, how the "atomic steps" of
computation are performed. *)
(* ################################################################# *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] (for Constant and
Plus) -- as constructor names, for brevity.) At the end of the
chapter, we'll see how to apply the same techniques to the full
Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
(** Here is a standard evaluator for this language, written in
the big-step style that we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P t1 t2 => evalF t1 + evalF t2
end.
(** Here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation.
We use the notation [t ==> n] for "[t] evaluates to [n]."
--------- (E_Const)
C n ==> n
t1 ==> n1
t2 ==> n2
------------------- (E_Plus)
P t1 t2 ==> n1 + n2
*)
Reserved Notation " t '==>' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n ==> n
| E_Plus : forall t1 t2 n1 n2,
t1 ==> n1 ->
t2 ==> n2 ->
P t1 t2 ==> (n1 + n2)
where " t '==>' n " := (eval t n).
Module SimpleArith1.
(** Now, here is the corresponding _small-step_ evaluation relation.
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) --> C (n1 + n2)
t1 --> t1'
-------------------- (ST_Plus1)
P t1 t2 --> P t1' t2
t2 --> t2'
---------------------------- (ST_Plus2)
P (C n1) t2 --> P (C n1) t2'
*)
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) --> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 --> t2' ->
P (C n1) t2 --> P (C n1) t2'
where " t '-->' t' " := (step t t').
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 1) (C 3))
(P (C 2) (C 4))
-->
P
(C 4)
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star, standard (test_step_2)
Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n) t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 1) (C 3)))
-->
P
(C 0)
(P
(C 2)
(C 4)).
Proof.
constructor. constructor. constructor.
Qed.
(** [] *)
End SimpleArith1.
(* ################################################################# *)
(** * Relations *)
(** We will be working with several different single-step relations,
so it is helpful to generalize a bit and state a few definitions
and theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.)
A _binary relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X : Type) := X -> X -> Prop.
(** Our main examples of such relations in this chapter will be
the single-step reduction relation, [-->], and its multi-step
variant, [-->*] (defined below), but there are many other
examples -- e.g., the "equals," "less than," "less than or equal
to," and "is the square of" relations on numbers, and the "prefix
of" relation on lists and strings. *)
(** One simple property of the [-->] relation is that, like the
big-step evaluation relation for Imp, it is _deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t --> t'] is provable). *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and
[y2], then [y1] and [y2] are equal, by induction on a derivation
of [step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and the last rule in the
given derivation of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x]
has the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2]
has the form [P _].
- Similarly, it cannot happen that one is [ST_Plus1] and the
other is [ST_Plus2], since this would imply that [x] has the
form [P t1 t2] where [t1] has both the form [P t11 t12] and the
form [C n]. [] *)
(** Formally: *)
Definition deterministic {X : Type} (R : relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Module SimpleArith2.
Import SimpleArith1.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2.
- (* ST_PlusConstConst *) inversion Hy2; subst.
+ (* ST_PlusConstConst *) reflexivity.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *) inversion H2.
- (* ST_Plus1 *) inversion Hy2; subst.
+ (* ST_PlusConstConst *)
inversion Hy1.
+ (* ST_Plus1 *)
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
+ (* ST_Plus2 *)
inversion Hy1.
- (* ST_Plus2 *) inversion Hy2; subst.
+ (* ST_PlusConstConst *)
inversion Hy1.
+ (* ST_Plus1 *) inversion H2.
+ (* ST_Plus2 *)
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
End SimpleArith2.
(** There is some annoying repetition in this proof. Each use of
[inversion Hy2] results in three subcases, only one of which is
relevant (the one that matches the current case in the induction
on [Hy1]). The other two subcases need to be dismissed by finding
the contradiction among the hypotheses and doing inversion on it.
The following custom tactic, called [solve_by_inverts], can be
helpful in such cases. It will solve the goal if it can be solved
by inverting some hypothesis; otherwise, it fails. *)
Ltac solve_by_inverts n :=
match goal with | H : ?T |- _ =>
match type of T with Prop =>
solve [
inversion H;
match n with S (S (?n')) => subst; solve_by_inverts (S n') end ]
end end.
(** The details of how this works are not important for now, but it
illustrates the power of Coq's [Ltac] language for
programmatically defining special-purpose tactics. It looks
through the current proof state for a hypothesis [H] (the first
[match]) of type [Prop] (the second [match]) such that performing
inversion on [H] (followed by a recursive invocation of the same
tactic, if its argument [n] is greater than one) completely solves
the current goal. If no such hypothesis exists, it fails.
We will usually want to call [solve_by_inverts] with argument
[1] (especially as larger arguments can lead to very slow proof
checking), so we define [solve_by_invert] as a shorthand for this
case. *)
Ltac solve_by_invert :=
solve_by_inverts 1.
(** The proof of the previous theorem can now be simplified... *)
Module SimpleArith3.
Import SimpleArith1.
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2;
inversion Hy2; subst; try solve_by_invert.
- (* ST_PlusConstConst *) reflexivity.
- (* ST_Plus1 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
- (* ST_Plus2 *)
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith3.
(* ================================================================= *)
(** ** Values *)
(** Next, it will be useful to slightly reformulate the
definition of single-step reduction by stating it in terms of
"values." *)
(** It can be useful to think of the [-->] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done. *)
(** We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [-->] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [-->] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) --> C (n1 + n2)
t1 --> t1'
-------------------- (ST_Plus1)
P t1 t2 --> P t1' t2
value v1
t2 --> t2'
-------------------- (ST_Plus2)
P v1 t2 --> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant, since the naming
convention tells us where to add it when translating the informal
rule to Coq. We'll keep it for now, to maintain a close
correspondence between the informal and Coq versions of the rules,
but later on we'll drop it in informal rules for brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
--> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <--- n.b. *)
t2 --> t2' ->
P v1 t2 --> P v1 t2'
where " t '-->' t' " := (step t t').
(** **** Exercise: 3 stars, standard, especially useful (redo_determinism)
As a sanity check on this change, let's re-verify determinism.
Here's an informal proof:
_Proof sketch_: We must show that if [x] steps to both [y1] and
[y2], then [y1] and [y2] are equal. Consider the final rules used
in the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are constants (by
[ST_PlusConstConst]) _and_ one of [t1] or [t2] has the form [P
_].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form [P
t1 t2] where [t1] both has the form [P t11 t12] and is a
value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write your
formal version from scratch and just use the earlier one if you
get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2. induction Hy1; subst; intros y2 Hy2.
- inversion Hy2; subst; try solve_by_invert.
reflexivity.
- inversion Hy2; subst; try solve_by_invert.
+ apply IHHy1 in H2. subst. reflexivity.
+ inversion H1; subst. solve_by_invert.
- inversion Hy2; subst; try solve_by_invert.
+ inversion H3; subst; try solve_by_invert.
+ apply IHHy1 in H4. subst. reflexivity.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language
is fairly simple, but for a larger language it would be easy to
forget one of the rules and accidentally create a situation where
some term cannot take a step even though it has not been
completely reduced to a value. The following theorem shows that
we did not, in fact, make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value or else there exists a term [t'] such that [t --> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a value.
- Suppose [t = P t1 t2], where (by the IH) [t1] either is a value
or can step to some [t1'], and where [t2] is either a value or
can step to some [t2']. We must show [P t1 t2] is either a value
or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. []
Or, formally: *)
Theorem strong_progress : forall t,
value t \/ (exists t', t --> t').
Proof.
induction t.
- (* C *) left. apply v_const.
- (* P *) right. destruct IHt1 as [IHt1 | [t1' Ht1] ].
+ (* l *) destruct IHt2 as [IHt2 | [t2' Ht2] ].
* (* l *) inversion IHt1. inversion IHt2.
exists (C (n + n0)).
apply ST_PlusConstConst.
* (* r *)
exists (P t1 t2').
apply ST_Plus2. apply IHt1. apply Ht2.
+ (* r *)
exists (P t1' t2).
apply ST_Plus1. apply Ht1.
Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
just _progress_.) *)
(** The idea of "making progress" can be extended to tell us something
interesting about values: they are exactly the terms that _cannot_
make progress in this sense.
To state this observation formally, let's begin by giving a name
to "terms that cannot make progress." We'll call them _normal
forms_. *)
Definition normal_form {X : Type}
(R : relation X) (t : X) : Prop :=
~ exists t', R t t'.
(** Note that this definition specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. destruct H.
intros contra. destruct contra. inversion H.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t --> t').
{ apply strong_progress. }
destruct G as [G | G].
- (* l *) apply G.
- (* r *) exfalso. apply H. assumption.
Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf.
Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the way a term is written -- while [normal_form] is a semantic
one -- it is defined by looking at how the term steps.
It is not obvious that these concepts should define the same set
of terms! *)
(** Indeed, we could easily have written the definitions (incorrectly)
so that they would _not_ coincide. *)
(** **** Exercise: 3 stars, standard, optional (value_not_same_as_normal_form1)
We might, for example, define [value] so that it
includes some terms that are not finished reducing.
(Even if you don't work this exercise and the following ones
in Coq, make sure you can think of an example of such a term.) *)
Module Temp1.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2,
value (P t1 (C n2)). (* <--- *)
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) --> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
P v1 t2 --> P v1 t2'
where " t '-->' t' " := (step t t').
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (P (C 0) (C 2)).
split.
- constructor.
- intro. unfold normal_form in H. apply H.
exists (C 2).
constructor.
Qed.
End Temp1.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (value_not_same_as_normal_form2)
Or we might (again, wrongly) define [step] so that it permits
something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n). (* Original definition *)
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n,
C n --> P (C n) (C 0) (* <--- NEW *)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) --> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
P v1 t2 --> P v1 t2'
where " t '-->' t' " := (step t t').
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
exists (C 0). split.
- constructor.
- unfold normal_form. intro.
apply H.
exists (P (C 0) (C 0)). constructor.
Qed.
End Temp2.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (value_not_same_as_normal_form3)
Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) --> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
where " t '-->' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
exists (P (C 0) (P (C 1) (C 2))). split.
- intro. inversion H.
- unfold normal_form. intro.
destruct H as [t' H].
inversion H; subst. inversion H3.
Qed.
End Temp3.
(** [] *)
(* ----------------------------------------------------------------- *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just addition expressions and numbers, are just the booleans true
and false and a conditional expression... *)
Inductive tm : Type :=
| tru : tm
| fls : tm
| test : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_tru : value tru
| v_fls : value fls.
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
test tru t1 t2 --> t1
| ST_IfFalse : forall t1 t2,
test fls t1 t2 --> t2
| ST_If : forall t1 t1' t2 t3,
t1 --> t1' ->
test t1 t2 t3 --> test t1' t2 t3
where " t '-->' t' " := (step t t').
(** **** Exercise: 1 star, standard (smallstep_bools)
Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
fls --> fls.
(* not provable because fls is normal form *)
Definition bool_step_prop2 :=
test
tru
(test tru tru tru)
(test fls fls fls)
-->
tru.
(* not provable because it takes more than one step to reach tru *)
Definition bool_step_prop3 :=
test
(test tru tru tru)
(test tru tru tru)
fls
-->
test
tru
(test tru tru tru)
fls.
(* provable because (test tru tru tru) --> tru *)
Theorem bool_step_prop3_provable : bool_step_prop3.
Proof.
constructor. constructor.
Qed.
(* Do not modify the following line: *)
Definition manual_grade_for_smallstep_bools : option (nat*string) := None.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (progress_bool)
Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t --> t').
Proof.
intro.
induction t.
- left. apply v_tru.
- left. apply v_fls.
- right. destruct IHt1.
+ inversion H.
* exists t2. constructor.
* exists t3. constructor.
+ destruct H as [t' H].
exists (test t' t2 t3).
constructor. apply H.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
induction Hy1; intros y2 Hy2; inversion Hy2; subst; clear Hy2; try easy.
(* only one case left *)
apply IHHy1 in H3. subst. auto.
Qed.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars, standard (smallstep_bool_shortcut)
Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[tru] or [fls]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
test
(test tru tru tru)
fls
fls
-->
fls.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
test tru t1 t2 --> t1
| ST_IfFalse : forall t1 t2,
test fls t1 t2 --> t2
| ST_If : forall t1 t1' t2 t3,
t1 --> t1' ->
test t1 t2 t3 --> test t1' t2 t3
| ST_IfShortcut : forall t1 t2,
test t1 t2 t2 --> t2
where " t '-->' t' " := (step t t').
Definition bool_step_prop4 :=
test
(test tru tru tru)
fls
fls
-->
fls.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof. constructor. Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (properties_of_altered_step)
It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq. *)
(* My answer: no. The following program has two next steps.
test (test tru fls fls) fls fls can be reduced to:
- test fls fls fls by ST_If, or
- fls by ST_IfShortcut
Here's the proof with this exact example.
*)
Theorem step_non_deterministic :
~deterministic step.
Proof.
unfold deterministic. intro.
specialize H with
(x := test (test tru fls fls) fls fls)
(y1 := test fls fls fls)
(y2 := fls).
assert (test (test tru fls fls) fls fls --> test fls fls fls)
by repeat constructor.
assert (test (test tru fls fls) fls fls --> fls)
by constructor.
apply (H H0) in H1.
inversion H1.
Qed.
(*
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* My answer: yes. We are only adding a new clause.
It doesn't introduce a term that is not a value nor can be reduced further.
The previous proof for strong_progress should work here without changing.
Here's my proof. It is identical to the previous one.
*)
Theorem strong_progress : forall t,
value t \/ (exists t', t --> t').
Proof.
intro.
induction t.
- left. apply v_tru.
- left. apply v_fls.
- right. destruct IHt1.
+ inversion H.
* exists t2. constructor.
* exists t3. constructor.
+ destruct H as [t' H].
exists (test t' t2 t3).
constructor. apply H.
Qed.
(*
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
*)
(* My answer: yes. If we take away some step constructor, then some
expression may have no way to reduce to a value. In that case,
this expression will be neither a value nor a reducible expression.
*)
(** [] *)
End Temp5.
End Temp4.
(* ################################################################# *)
(** * Multi-Step Reduction *)
(** We've been working so far with the _single-step reduction_
relation [-->], which formalizes the individual steps of an
abstract machine for executing programs.
We can use the same machine to reduce programs to completion -- to
find out what final result they yield. This can be formalized as
follows:
- First, we define a _multi-step reduction relation_ [-->*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
(including zero) of single reduction steps.
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(** Since we'll want to reuse the idea of multi-step reduction many
times, let's pause and define it generically.
Given a relation [R] (which will be [-->] for present purposes),
we define a relation [multi R], called the _multi-step closure of
[R]_ as follows. *)
Inductive multi {X : Type} (R : relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** (In the [Rel] chapter of _Logical Foundations_ and
the Coq standard library, this relation is called
[clos_refl_trans_1n]. We give it a shorter name here for the sake
of readability.) *)
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if
- [x = y], or
- [R x y], or
- there is some nonempty sequence [z1], [z2], ..., [zn] such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, then [z1] ... [zn]
is the sequence of intermediate steps of computation between [x] and
[y]. *)
(** We write [-->*] for the [multi step] relation on terms. *)
Notation " t '-->*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [-->*] (i.e., [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution. *)
(** Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X : Type) (R : relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl.
Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X : Type) (R : relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
induction G.
- (* multi_refl *) assumption.
- (* multi_step *)
apply multi_step with y. assumption.
apply IHG. assumption.
Qed.
(** In particular, for the [multi step] relation on terms, if
[t1 -->* t2] and [t2 -->* t3], then [t1 -->* t3]. *)
(* ================================================================= *)
(** ** Examples *)
(** Here's a specific instance of the [multi step] relation: *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
-->*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P (C (0 + 3))
(P (C 2) (C 4))).
{ apply ST_Plus1. apply ST_PlusConstConst. }
apply multi_step with
(P (C (0 + 3))
(C (2 + 4))).
{ apply ST_Plus2. apply v_const. apply ST_PlusConstConst. }
apply multi_R.
apply ST_PlusConstConst.
Qed.
(** Here's an alternate proof of the same fact that uses [eapply] to
avoid explicitly constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
-->*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. { apply ST_Plus1. apply ST_PlusConstConst. }
eapply multi_step. { apply ST_Plus2. apply v_const.
apply ST_PlusConstConst. }
eapply multi_step. { apply ST_PlusConstConst. }
apply multi_refl.
Qed.
(** **** Exercise: 1 star, standard, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 -->* C 3.
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
-->*
P (C 0) (C 3).
Proof.
apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 2 stars, standard (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
-->*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
eapply multi_step.
{ apply ST_Plus2. apply v_const. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
}
eapply multi_step.
{ apply ST_Plus2. apply v_const. apply ST_PlusConstConst.
}
apply multi_refl.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t -->* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, standard, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
(* We recommend using this initial setup as-is! *)
unfold deterministic. unfold normal_form_of.
intros x y1 y2 P1 P2.
destruct P1 as [P11 P12].
destruct P2 as [P21 P22].
generalize dependent y2.
unfold step_normal_form, normal_form in *.
induction P11; intros.
- (* multi_refl *)
inversion P21; subst; clear P21; try reflexivity.
exfalso. apply P12. exists y. apply H.
- (* multi_step *)
inversion P21; subst; clear P21.
+ exfalso. apply P22. exists y. apply H.
+ apply IHP11; try assumption.
(* Hypo: x --> y; x --> y0; y0 -->* y2, Goal: y -->* y2 *)
assert (y = y0).
{ apply (step_deterministic x); assumption. }
subst. assumption.
Qed.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X : Type} (R : relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the first argument to [P], and
similarly when [t] appears as the second argument to [P]
when the first argument is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 -->* t1' ->
P t1 t2 -->* P t1' t2.
Proof.
intros t1 t1' t2 H. induction H.
- (* multi_refl *) apply multi_refl.
- (* multi_step *) apply multi_step with (P y t2).
+ apply ST_Plus1. apply H.
+ apply IHmulti.
Qed.
(** **** Exercise: 2 stars, standard (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 -->* t2' ->
P t1 t2 -->* P t1 t2'.
Proof.
intros t1 t2 t2'.
intros Hv H.
induction H.
- (* multi_refl *)
apply multi_refl.
- (* multi_step *)
apply multi_step with (P t1 y).
{ apply ST_Plus2. apply Hv. apply H.
}
apply IHmulti.
Qed.
(** [] *)
(** With these lemmas in hand, the main proof is a straightforward
induction.
_Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] reduces to [t'] and [t']
is a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step, and we
have [t' = t]. We can derive the left-hand side by reflexivity
and the right-hand side by observing (a) that values are normal
forms (by [nf_same_as_value]) and (b) that [t] is a value (by
[v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and [t2]
reduce to normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we therefore know that
[t1' = C n1] and [t2' = C n2], for some [n1] and [n2]. We can
combine the [-->*] derivations for [t1] and [t2] using
[multi_congr_1] and [multi_congr_2] to prove that [P t1 t2]
reduces in many steps to [t' = C (n1 + n2)].
Finally, [C (n1 + n2)] is a value, which is in turn a normal
form by [nf_same_as_value]. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
induction t.
- (* C *)
exists (C n).
split.
+ (* l *) apply multi_refl.
+ (* r *)
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
- (* P *)
destruct IHt1 as [t1' [Hsteps1 Hnormal1] ].
destruct IHt2 as [t2' [Hsteps2 Hnormal2] ].
rewrite nf_same_as_value in Hnormal1.
rewrite nf_same_as_value in Hnormal2.
destruct Hnormal1 as [n1].
destruct Hnormal2 as [n2].
exists (C (n1 + n2)).
split.
+ (* l *)
apply multi_trans with (P (C n1) t2).
* apply multistep_congr_1. apply Hsteps1.
* apply multi_trans with (P (C n1) (C n2)).
{ apply multistep_congr_2. apply v_const. apply Hsteps2. }
apply multi_R. apply ST_PlusConstConst.
+ (* r *)
rewrite nf_same_as_value. apply v_const.
Qed.
(* ================================================================= *)
(** ** Equivalence of Big-Step and Small-Step *)
(** Having defined the operational semantics of our tiny programming
language in two different ways (big-step and small-step), it makes
sense to ask whether these definitions actually define the same
thing! *)
(** They do, though it takes a little work to show it. The
details are left as an exercise. *)
(** **** Exercise: 3 stars, standard (eval__multistep) *)
Theorem eval__multistep : forall t n,
t ==> n -> t -->* C n.
(** The key ideas in the proof can be seen in the following picture:
P t1 t2 --> (by ST_Plus1)
P t1' t2 --> (by ST_Plus1)
P t1'' t2 --> (by ST_Plus1)
...
P (C n1) t2 --> (by ST_Plus2)
P (C n1) t2' --> (by ST_Plus2)
P (C n1) t2'' --> (by ST_Plus2)
...
P (C n1) (C n2) --> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [-->*]: that it is reflexive, transitive, and
includes [-->]. *)
Proof.
intros.
induction H.
- apply multi_refl.
- inversion IHeval1; subst; clear IHeval1.
+ apply multi_trans with (P (C n1) (C n2)).
apply multistep_congr_2; easy.
eapply multi_step. constructor. apply multi_refl.
+ apply multi_trans with (P (C n1) t2).
apply multistep_congr_1.
* eapply multi_step. apply H1. apply H2.
* apply multi_trans with (P (C n1) (C n2)).
-- apply multistep_congr_2; easy.
-- eapply multi_step. constructor. apply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf)
Write a detailed informal version of the proof of [eval__multistep].
Proof:
Suppose t ==> n, I need to prove t -->* C n. To do this, I will
perform induction on t ==> n. There are two cases:
- E_Const: in this case, t = C n. C n -->* C n can be proven by multi_refl.
- E_Plus: in this case, t = P t1 t2, t1 ==> n1 and t2 ==> n2.
I also get inductive hypotheses that t1 -->* C n1 and t2 -->* C n2.
The goal is to prove that P t1 t2 -->* C (n1 + n2).
For induction hypothesis t1 -->* C n1, there are two possible cases: either
multi_refl where (t1 = C n1) or multi_step where (t1 -> y and y -->* C n1).
I will analyze these two cases:
+ Case 1: t1 = C n1. Goal: P (C n1) t2 -->* C (n1 + n2).
We can use multi_trans to convert the goal into two separate goals:
- P (C n1) t2 -->* P (C n1) (C n2): I can prove this using
multistep_congr_2.
- P (C n1) (C n2) -->* C (n1 + n2): I can prove it because the result
is a single step of (-->).
+ Case 2: we have t1 -> y and y -->* C n1. By multi_trans, we can convert
it into three goals:
- P t1 t2 -->* P (C n1) t2: I can prove this using multistep_congr_1.
- P (C n1) t2 -->* P (C n1) (C n2): this is proven in same way as in case 1.
- P (C n1) (C n2) -->* C (n1 + n2): this is proven in same way as in case 1.
Qed.
*)
(* Do not modify the following line: *)
Definition manual_grade_for_eval__multistep_inf : option (nat*string) := None.
(** [] *)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars, standard (step__eval) *)
Lemma step__eval : forall t t' n,
t --> t' ->
t' ==> n ->
t ==> n.
Proof.
intros t t' n Hs. generalize dependent n.
induction Hs; intros; inversion H; subst; clear H.
- repeat constructor.
- constructor.
+ apply IHHs. apply H2.
+ apply H4.
- inversion H0; subst; clear H0. constructor.
+ apply H2.
+ apply IHHs. apply H4.
Qed.
(** [] *)
(** The fact that small-step reduction implies big-step evaluation is now
straightforward to prove.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars, standard (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t ==> n.
Proof.
intros.
destruct H; unfold step_normal_form in H0.
induction H.
- assert (value x \/ (exists t', x --> t')) by apply strong_progress.
destruct H.
+ inversion H. exists n. split. reflexivity. constructor.
+ exfalso. apply H0. apply H.
- assert (value z \/ (exists t', z --> t')) by apply strong_progress.
destruct H2.
+ inversion H2. subst. apply IHmulti in H0.
destruct H0. destruct H0. inversion H0; subst.
exists x0. split.
* reflexivity.
* eapply step__eval. apply H. apply H3.
+ exfalso. apply H0. apply H2.
Qed.
(** [] *)
(* ================================================================= *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, standard, optional (interp_tm)
Remember that we also defined big-step evaluation of terms as a
function [evalF]. Prove that it is equivalent to the existing
semantics. (Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though!) *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t ==> n.
Proof.
intro.
induction t.
- split; intro.
+ simpl in H. subst. constructor.
+ inversion H; subst. reflexivity.
- split; intro.
+ simpl in H. subst.
constructor.
apply IHt1; reflexivity.
apply IHt2; reflexivity.
+ inversion H; subst; clear H. simpl.
apply IHt1 in H2. apply IHt2 in H4.
subst. reflexivity.
Qed.
(** [] *)
(** **** Exercise: 4 stars, standard (combined_properties)
We've considered arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| tru : tm
| fls : tm
| test : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_tru : value tru
| v_fls : value fls.
Reserved Notation " t '-->' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) --> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 --> t1' ->
P t1 t2 --> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 --> t2' ->
P v1 t2 --> P v1 t2'
| ST_IfTrue : forall t1 t2,
test tru t1 t2 --> t1
| ST_IfFalse : forall t1 t2,
test fls t1 t2 --> t2
| ST_If : forall t1 t1' t2 t3,
t1 --> t1' ->
test t1 t2 t3 --> test t1' t2 t3
where " t '-->' t' " := (step t t').
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Formally prove or disprove these two properties for the combined
language. (That is, state a theorem saying that the property
holds or does not hold, and prove your theorem.) *)
(*
My answer:
1. step will still be deterministic.
2. strong progress lemma doesn't hold. Here's a counter example:
test (C 0) tru tru
Below are the proofs:
*)
Theorem step_deterministic :
deterministic step.
Proof.
unfold deterministic.
intros. generalize dependent y2.
induction H; intros y2 Hy2; inversion Hy2; subst; clear Hy2;
try auto; try easy.
- f_equal. auto.
- inversion H2; subst; clear H2; inversion H.
- inversion H; subst; clear H; inversion H4.
- f_equal. auto.
- f_equal. apply IHstep. apply H4.
Qed.
Theorem strong_progress_does_not_hold:
~(forall t, value t \/ (exists t', t --> t')).
Proof.
intros. intro.
specialize H with (test (C 0) tru tru).
destruct H.
- inversion H.
- inversion H. inversion H0. inversion H5.
Qed.
End Combined.
(* Do not modify the following line: *)
Definition manual_grade_for_combined_properties : option (nat*string) := None.
(** [] *)
(* ################################################################# *)
(** * Small-Step Imp *)
(** Now for a more serious example: a small-step version of the Imp
operational semantics. *)
(** The small-step reduction relations for arithmetic and
boolean expressions are straightforward extensions of the tiny
language we've been working up to now. To make them easier to
read, we introduce the symbolic notations [-->a] and [-->b] for
the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
| av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [-->b]
below (why?), though they might be if our language were a bit
more complicated (why?). *)
Reserved Notation " a '/' st '-->a' a' "
(at level 40, st at level 39).
Inductive astep (st : state) : aexp -> aexp -> Prop :=
| AS_Id : forall i,
AId i / st -->a ANum (st i)
| AS_Plus1 : forall a1 a1' a2,
a1 / st -->a a1' ->
(APlus a1 a2) / st -->a (APlus a1' a2)
| AS_Plus2 : forall v1 a2 a2',
aval v1 ->
a2 / st -->a a2' ->
(APlus v1 a2) / st -->a (APlus v1 a2')
| AS_Plus : forall n1 n2,
APlus (ANum n1) (ANum n2) / st -->a ANum (n1 + n2)
| AS_Minus1 : forall a1 a1' a2,
a1 / st -->a a1' ->
(AMinus a1 a2) / st -->a (AMinus a1' a2)
| AS_Minus2 : forall v1 a2 a2',
aval v1 ->
a2 / st -->a a2' ->
(AMinus v1 a2) / st -->a (AMinus v1 a2')
| AS_Minus : forall n1 n2,
(AMinus (ANum n1) (ANum n2)) / st -->a (ANum (minus n1 n2))
| AS_Mult1 : forall a1 a1' a2,
a1 / st -->a a1' ->
(AMult a1 a2) / st -->a (AMult a1' a2)
| AS_Mult2 : forall v1 a2 a2',
aval v1 ->
a2 / st -->a a2' ->
(AMult v1 a2) / st -->a (AMult v1 a2')
| AS_Mult : forall n1 n2,
(AMult (ANum n1) (ANum n2)) / st -->a (ANum (mult n1 n2))
where " a '/' st '-->a' a' " := (astep st a a').
Reserved Notation " b '/' st '-->b' b' "
(at level 40, st at level 39).
Inductive bstep (st : state) : bexp -> bexp -> Prop :=
| BS_Eq1 : forall a1 a1' a2,
a1 / st -->a a1' ->
(BEq a1 a2) / st -->b (BEq a1' a2)
| BS_Eq2 : forall v1 a2 a2',
aval v1 ->
a2 / st -->a a2' ->
(BEq v1 a2) / st -->b (BEq v1 a2')
| BS_Eq : forall n1 n2,
(BEq (ANum n1) (ANum n2)) / st -->b
(if (n1 =? n2) then BTrue else BFalse)
| BS_LtEq1 : forall a1 a1' a2,
a1 / st -->a a1' ->
(BLe a1 a2) / st -->b (BLe a1' a2)
| BS_LtEq2 : forall v1 a2 a2',
aval v1 ->
a2 / st -->a a2' ->
(BLe v1 a2) / st -->b (BLe v1 a2')
| BS_LtEq : forall n1 n2,
(BLe (ANum n1) (ANum n2)) / st -->b
(if (n1 <=? n2) then BTrue else BFalse)
| BS_NotStep : forall b1 b1',
b1 / st -->b b1' ->
(BNot b1) / st -->b (BNot b1')
| BS_NotTrue : (BNot BTrue) / st -->b BFalse
| BS_NotFalse : (BNot BFalse) / st -->b BTrue
| BS_AndStep : forall b1 b1' b2,
b1 / st -->b b1' ->
(BAnd b1 b2) / st -->b (BAnd b1' b2)
| BS_AndTrueStep : forall b2 b2',
b2 / st -->b b2' ->
(BAnd BTrue b2) / st -->b (BAnd BTrue b2')
| BS_AndFalse : forall b2,
(BAnd BFalse b2) / st -->b BFalse
| BS_AndTrueTrue : (BAnd BTrue BTrue) / st -->b BTrue
| BS_AndTrueFalse : (BAnd BTrue BFalse) / st -->b BFalse
where " b '/' st '-->b' b' " := (bstep st b b').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [skip] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [skip] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [skip], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [while] command by transforming it into a
conditional followed by the same [while]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [while]
command needs to be saved somewhere while a single copy of the loop
body is being reduced.) *)
Reserved Notation " t '/' st '-->' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a1 a1',
a1 / st -->a a1' ->
<{ i := a1 }> / st --> <{ i := a1' }> / st
| CS_Ass : forall st i n,
<{ i := ANum n }> / st --> <{ skip }> / (i !-> n ; st)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st --> c1' / st' ->
<{ c1 ; c2 }> / st --> <{ c1' ; c2 }> / st'
| CS_SeqFinish : forall st c2,
<{ skip ; c2 }> / st --> c2 / st
| CS_IfStep : forall st b1 b1' c1 c2,
b1 / st -->b b1' ->
<{ if b1 then c1 else c2 end }> / st
-->
<{ if b1' then c1 else c2 end }> / st
| CS_IfTrue : forall st c1 c2,
<{ if true then c1 else c2 end }> / st --> c1 / st
| CS_IfFalse : forall st c1 c2,
<{ if false then c1 else c2 end }> / st --> c2 / st
| CS_While : forall st b1 c1,
<{ while b1 do c1 end }> / st
-->
<{ if b1 then c1; while b1 do c1 end else skip end }> / st
where " t '/' st '-->' t' '/' st' " := (cstep (t,st) (t',st')).
(* ################################################################# *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : string -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CPar : com -> com -> com. (* <--- NEW *)
Notation "'par' c1 'with' c2 'end'" :=
(CPar c1 c2)
(in custom com at level 0, c1 at level 99, c2 at level 99).
Notation "'skip'" :=
CSkip (in custom com at level 0).
Notation "x := y" :=
(CAss x y)
(in custom com at level 0, x constr at level 0,
y at level 85, no associativity).
Notation "x ; y" :=
(CSeq x y)
(in custom com at level 90, right associativity).
Notation "'if' x 'then' y 'else' z 'end'" :=
(CIf x y z)
(in custom com at level 89, x at level 99,
y at level 99, z at level 99).
Notation "'while' x 'do' y 'end'" :=
(CWhile x y)
(in custom com at level 89, x at level 99, y at level 99).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a1 a1',
a1 / st -->a a1' ->
<{ i := a1 }> / st --> <{i := a1'}> / st
| CS_Ass : forall st i n,
<{i := ANum n}> / st --> <{skip}> / (i !-> n ; st)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st --> c1' / st' ->
<{c1 ; c2}> / st --> <{c1' ; c2}> / st'
| CS_SeqFinish : forall st c2,
<{skip ; c2}> / st --> c2 / st
| CS_IfStep : forall st b1 b1' c1 c2,
b1 /st -->b b1' ->
<{if b1 then c1 else c2 end}> / st
--> <{if b1' then c1 else c2 end}> / st
| CS_IfTrue : forall st c1 c2,
<{if true then c1 else c2 end}> / st --> c1 / st
| CS_IfFalse : forall st c1 c2,
<{if false then c1 else c2 end}> / st --> c2 / st
| CS_While : forall st b1 c1,
<{while b1 do c1 end}> / st
--> <{if b1 then (c1; (while b1 do c1 end)) else skip end}> / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st --> c1' / st' ->
<{par c1 with c2 end}> / st --> <{par c1' with c2 end}> / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st --> c2' / st' ->
<{par c1 with c2 end}> / st --> <{par c1 with c2' end}> / st'
| CS_ParDone : forall st,
<{par skip with skip end}> / st --> <{skip}> / st
where " t '/' st '-->' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '-->*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value. *)
Definition par_loop : com :=
<{
par
Y := 1
with
while (Y = 0) do
X := X + 1
end
end}>.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_st -->* <{skip}> / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_st -->* <{skip}> / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, standard, optional (par_body_n__Sn) *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st -->* par_loop / (X !-> S n ; st).
Proof.
intros.
destruct H as [Hx Hy].
unfold par_loop.
eapply multi_step.
apply CS_Par2.
apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep. apply BS_Eq1. apply AS_Id.
rewrite Hy.
eapply multi_step. apply CS_Par2. apply CS_IfStep. apply BS_Eq.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep. apply CS_AssStep.
apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. rewrite Hx. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep. apply CS_Ass.
rewrite plus_comm. simpl.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_refl.
Qed.
(** [] *)
(** **** Exercise: 3 stars, standard, optional (par_body_n) *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st -->* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
intros.
destruct H as [Hx Hy].
unfold par_loop.
induction n.
- eapply ex_intro. split.
+ apply multi_refl.
+ easy.
- destruct IHn as [st' [IHn [Hx' Hy']]].
eapply ex_intro.
split.
+ eapply multi_trans.
* apply IHn.
* apply par_body_n__Sn.
auto.
+ unfold t_update. simpl. auto.
Qed.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_st -->* <{skip}> / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_st).
split; reflexivity.
rename x into st.
inversion H as [H' [HX HY] ]; clear H.
exists (Y !-> 1 ; st). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite t_update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite t_update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ################################################################# *)
(** * A Small-Step Stack Machine *)
(** Our last example is a small-step semantics for the stack machine
example from the [Imp] chapter of _Logical Foundations_. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step (st : state) : prog * stack -> prog * stack -> Prop :=
| SS_Push : forall stk n p,
stack_step st (SPush n :: p, stk) (p, n :: stk)
| SS_Load : forall stk i p,
stack_step st (SLoad i :: p, stk) (p, st i :: stk)
| SS_Plus : forall stk n m p,
stack_step st (SPlus :: p, n::m::stk) (p, (m+n)::stk)
| SS_Minus : forall stk n m p,
stack_step st (SMinus :: p, n::m::stk) (p, (m-n)::stk)
| SS_Mult : forall stk n m p,
stack_step st (SMult :: p, n::m::stk) (p, (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct)
Remember the definition of [compile] for [aexp] given in the
[Imp] chapter of _Logical Foundations_. We want now to
prove [s_compile] correct with respect to the stack machine.
Copy your definition of [s_compile] from Imp here, then state
what it means for the compiler to be correct according to the
stack machine small step semantics, and then prove it. *)
(* Copy your definition of s_compile here *)
Fixpoint s_compile (e : aexp) : list sinstr :=
match e with
| ANum n => [SPush n]
| AId x => [SLoad x]
| APlus a1 a2 => s_compile a1 ++ s_compile a2 ++ [SPlus]
| AMinus a1 a2 => s_compile a1 ++ s_compile a2 ++ [SMinus]
| AMult a1 a2 => s_compile a1 ++ s_compile a2 ++ [SMult]
end.
Definition compiler_is_correct_statement : Prop := forall st e n stk,
aeval st e = n ->
stack_multistep st (s_compile e, stk) ([], n :: stk).
Hint Constructors multi : core.
Hint Resolve multi_trans : core.
Hint Constructors stack_step : core.
Hint Unfold stack_multistep : core.
Theorem stack_execute_app : forall st p1 p2 stk stk' stk'',
stack_multistep st (p1, stk) ([], stk') ->
stack_multistep st (p2, stk') ([], stk'') ->
stack_multistep st ((p1 ++ p2), stk) ([], stk'').
Proof.
unfold stack_multistep.
intros.
generalize dependent stk'.
generalize dependent stk''.
generalize dependent stk.
induction p1; simpl; intros.
- inversion H; subst; clear H.
+ apply H0.
+ inversion H1.
- destruct a;
inversion H; subst; clear H;
inversion H1; subst; clear H1;
eauto.
Qed.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
unfold compiler_is_correct_statement.
intros.
generalize dependent n.
generalize dependent stk.
induction e; intros; simpl in *; subst;
(* ANum, AId *)
try eauto;
(* APlus, AMinus, AMult *)
try eauto 7 using stack_execute_app.
Qed.
(** [] *)
(* ################################################################# *)
(** * Aside: A [normalize] Tactic *)
(** When experimenting with definitions of programming languages
in Coq, we often want to see what a particular concrete term steps
to -- i.e., we want to find proofs for goals of the form [t -->*
t'], where [t] is a completely concrete term and [t'] is unknown.
These proofs are quite tedious to do by hand. Consider, for
example, reducing an arithmetic expression using the small-step
relation [astep]. *)
Example step_example1 :
(P (C 3) (P (C 3) (C 4)))
-->* (C 10).
Proof.
apply multi_step with (P (C 3) (C 7)).
apply ST_Plus2.
apply v_const.
apply ST_PlusConstConst.
apply multi_step with (C 10).
apply ST_PlusConstConst.
apply multi_refl.
Qed.
(** The proof repeatedly applies [multi_step] until the term reaches a
normal form. Fortunately The sub-proofs for the intermediate
steps are simple enough that [auto], with appropriate hints, can
solve them. *)
Hint Constructors step value : core.
Example step_example1' :
(P (C 3) (P (C 3) (C 4)))
-->* (C 10).
Proof.
eapply multi_step. auto. simpl.
eapply multi_step. auto. simpl.
apply multi_refl.
Qed.
(** The following custom [Tactic Notation] definition captures this
pattern. In addition, before each step, we print out the current
goal, so that we can follow how the term is being reduced. *)
Tactic Notation "print_goal" :=
match goal with |- ?x => idtac x end.
Tactic Notation "normalize" :=
repeat (print_goal; eapply multi_step ;
[ (eauto 10; fail) | (instantiate; simpl)]);
apply multi_refl.
Example step_example1'' :
(P (C 3) (P (C 3) (C 4)))
-->* (C 10).
Proof.
normalize.
(* The [print_goal] in the [normalize] tactic shows
a trace of how the expression reduced...
(P (C 3) (P (C 3) (C 4)) -->* C 10)
(P (C 3) (C 7) -->* C 10)
(C 10 -->* C 10)
*)
Qed.
(** The [normalize] tactic also provides a simple way to calculate the
normal form of a term, by starting with a goal with an existentially
bound variable. *)
Example step_example1''' : exists e',
(P (C 3) (P (C 3) (C 4)))
-->* e'.
Proof.
eexists. normalize.
Qed.
(** This time, the trace is:
(P (C 3) (P (C 3) (C 4)) -->* ?e')
(P (C 3) (C 7) -->* ?e')
(C 10 -->* ?e')
where [?e'] is the variable ``guessed'' by eapply. *)
(** **** Exercise: 1 star, standard (normalize_ex) *)
Theorem normalize_ex : exists e',
(P (C 3) (P (C 2) (C 1)))
-->* e' /\ value e'.
Proof.
intros.
eexists.
split.
- normalize.
- auto.
Qed.
(** [] *)
(** **** Exercise: 1 star, standard, optional (normalize_ex')
For comparison, prove it using [apply] instead of [eapply]. *)
Theorem normalize_ex' : exists e',
(P (C 3) (P (C 2) (C 1)))
-->* e' /\ value e'.
Proof.
intros.
exists (C 6).
split.
- apply multi_step with (P (C 3) (C 3)).
+ constructor. constructor. constructor.
+ apply multi_step with (C 6).
* replace 6 with (3 + 3) by auto.
constructor.
* apply multi_refl.
- constructor.
Qed.
(** [] *)
(* 2020-09-09 21:08 *)
|
module top;
reg pass;
reg [2:0] res [0:7];
reg [2:0] in [0:7];
reg [7:0] dummy [0:6];
time run_time [0:7];
time exp_time [0:7];
integer i;
initial begin
pass = 1'b1;
#1;
// Initialize the input array.
for (i=0; i<8; i=i+1) begin
in[i] = i[2:0];
end
#1;
for (i=0; i<8; i=i+1) begin
exp_time[i] = $time-1;
end
check;
// We only have 6 dummy items, check that each triggers correctly.
for (i=0; i<7; i=i+1) begin
dummy[i] = 1'b0;
#1;
exp_time[i] = $time-1;
check;
end
if (pass) $display("PASSED");
end
// Check that the value and time are correct.
task check;
integer j;
begin
for (j=0; j<8; j=j+1) begin
if (res[j] !== j[2:0]) begin
$display("FAILED: index %0d value, at %2t, expexted %b, got %b.",
j, $time, j[2:0], res[j]);
pass = 1'b0;
end
if (run_time[j] !== exp_time[j]) begin
$display("FAILED: index %0d time, at %2t, expexted %2t, got %2t.",
j, $time, exp_time[j], run_time[j]);
pass = 1'b0;
end
end
end
endtask
genvar m;
generate
for (m=0; m<=7; m=m+1) begin: idac_loop
// This should complain that dummy[7] is out of bounds.
always @ (in[m] or dummy[m]) begin
res[m] = in[m];
run_time[m] = $time;
end
end
endgenerate
endmodule
|
/*
* Copyright (c) 2001 Uwe Bonnes
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
`define ADC_DATA_OFFSET 5
`define ADC_CHANELS 8*48
//`define ADC_CHANELS 348
module mymod (out1,out2,state,reset);
input [8:0] state;
input reset;
output out1,out2;
assign out1 = (state > `ADC_DATA_OFFSET) ? 1 : 0;
assign out2 = (state > `ADC_CHANELS + `ADC_DATA_OFFSET +1)|| (reset);
endmodule // mymod
module t;
reg [8:0] state;
reg reset;
wire out1,out2;
mymod m1 (out1,out2,state,reset);
initial
begin
//$timeformat(-9,0,"ns",5);
$display(" TIME:state:out1:out2");
$monitor("%7t:%5d:%3d:%3d",$time,state,out1,out2);
state =0;
reset = 0;
#10
reset=1;
#20
reset=0;
#5110
$finish;
end
always
begin
#10
if (reset)
state = 0;
else
state=state+1;
end
endmodule // t
|
module Datapath_FunctionUnit_ArithmeticLogicUnit_Behavioral(F, C, A, B, FS);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter SB_WIDTH = DR_WIDTH;
parameter SA_WIDTH = DR_WIDTH;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
output reg [WORD_WIDTH-1:0] F;
output reg C;
input [WORD_WIDTH-1:0] A, B;
input [3:0] FS;
always@(*)
case(FS)
4'b0000: {C, F} = A; // Transfer
4'b0001: {C, F} = A+1; // Increment
4'b0010: {C, F} = A+B; // Add
4'b0011: {C, F} = A+B+1; // (Unused)
4'b0100: {C, F} = A+(~B); // (Unused)
4'b0101: {C, F} = A+(~B)+1; // Subtraction
4'b0110: {C, F} = A-1; // Decrement
4'b0111: {C, F} = A; // (Unused)
4'b1000: {C, F} = A&B; // Bitwize and
4'b1001: {C, F} = A|B; // Bitwize or
4'b1010: {C, F} = A^B; // Bitwize xor
4'b1011: {C, F} = (~A); // Bitwize Invert
4'b1100: {C, F} = B; // Move B
4'b1101: {C, F} = (B>>1); // Shift Right B
4'b1110: {C, F} = (B<<1); // Shift Left B
4'b1111: {C, F} = (~B); // (Unused)
default:;
endcase
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V
`define SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V
/**
* iso1n: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__iso1n (
X ,
A ,
SLEEP_B
);
// Module ports
output X ;
input A ;
input SLEEP_B;
// Local signals
wire SLEEP;
// Name Output Other arguments
not not0 (SLEEP , SLEEP_B );
or or0 (X , A, SLEEP );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1N_FUNCTIONAL_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__XOR2_4_V
`define SKY130_FD_SC_LP__XOR2_4_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog wrapper for xor2 with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__xor2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_4 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__xor2_4 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__xor2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__XOR2_4_V
|
//////////////////////////////////////////////////////////////////////////////////
// SCFIFO_80x64_withCount for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: Single clock FIFO (288 width, 16 depth) wrapper
// Module Name: DRSCFIFO_288x16_withCount
// File Name: DRSCFIFO_288x16_withCount.v
//
// Version: v1.0.0
//
// Description: Standard FIFO, 1 cycle data out latency
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module DRSCFIFO_288x16_withCount
(
input iClock ,
input iReset ,
input [287:0] iPushData ,
input iPushEnable ,
output oIsFull ,
output [287:0] oPopData ,
input iPopEnable ,
output oIsEmpty ,
output [3:0] oDataCount
);
DRSCFIFO288x16WC
Inst_DPBSCFIFO288x16WC
(
.clk (iClock ),
.srst (iReset ),
.din (iPushData ),
.wr_en (iPushEnable ),
.full (oIsFull ),
.dout (oPopData ),
.rd_en (iPopEnable ),
.empty (oIsEmpty ),
.data_count (oDataCount )
);
endmodule
|
//Legal Notice: (C)2015 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_sys_Onchip_Memory (
// inputs:
address,
byteenable,
chipselect,
clk,
clken,
reset,
write,
writedata,
// outputs:
readdata
)
;
parameter INIT_FILE = "../video_sys_Onchip_Memory.hex";
output [ 31: 0] readdata;
input [ 11: 0] address;
input [ 3: 0] byteenable;
input chipselect;
input clk;
input clken;
input reset;
input write;
input [ 31: 0] writedata;
wire [ 31: 0] readdata;
wire wren;
assign wren = chipselect & write;
//s1, which is an e_avalon_slave
//s2, which is an e_avalon_slave
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
altsyncram the_altsyncram
(
.address_a (address),
.byteena_a (byteenable),
.clock0 (clk),
.clocken0 (clken),
.data_a (writedata),
.q_a (readdata),
.wren_a (wren)
);
defparam the_altsyncram.byte_size = 8,
the_altsyncram.init_file = INIT_FILE,
the_altsyncram.lpm_type = "altsyncram",
the_altsyncram.maximum_depth = 4096,
the_altsyncram.numwords_a = 4096,
the_altsyncram.operation_mode = "SINGLE_PORT",
the_altsyncram.outdata_reg_a = "UNREGISTERED",
the_altsyncram.ram_block_type = "AUTO",
the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
the_altsyncram.width_a = 32,
the_altsyncram.width_byteena_a = 4,
the_altsyncram.widthad_a = 12;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// altsyncram the_altsyncram
// (
// .address_a (address),
// .byteena_a (byteenable),
// .clock0 (clk),
// .clocken0 (clken),
// .data_a (writedata),
// .q_a (readdata),
// .wren_a (wren)
// );
//
// defparam the_altsyncram.byte_size = 8,
// the_altsyncram.init_file = "video_sys_Onchip_Memory.hex",
// the_altsyncram.lpm_type = "altsyncram",
// the_altsyncram.maximum_depth = 4096,
// the_altsyncram.numwords_a = 4096,
// the_altsyncram.operation_mode = "SINGLE_PORT",
// the_altsyncram.outdata_reg_a = "UNREGISTERED",
// the_altsyncram.ram_block_type = "AUTO",
// the_altsyncram.read_during_write_mode_mixed_ports = "DONT_CARE",
// the_altsyncram.width_a = 32,
// the_altsyncram.width_byteena_a = 4,
// the_altsyncram.widthad_a = 12;
//
//synthesis read_comments_as_HDL off
endmodule
|
module top;
parameter parm = 1;
parameter name0_s = 1; // signal
wire [1:0] out;
/***********
* Check signals
***********/
// Check signal/parameter name issues.
wire name0_s;
// Check signal/genvar name issues.
genvar name0_v;
generate
for (name0_v = 0; name0_v < 2; name0_v = name0_v + 1) begin
assign out[name0_v] = name0_v;
end
endgenerate
wire name0_v;
// Check signal/task name issues.
task name1_st;
$display("FAILED in task name1_st");
endtask
wire name1_st;
// Check signal/function name issues.
function name2_sf;
input in;
name2_sf = in;
endfunction
wire name2_sf;
// Check signal/module instance name issues.
test name3_si(out[0]);
wire name3_si;
// Check signal/named block name issues.
initial begin: name4_sb
$display("FAILED in name4_sb");
end
wire name4_sb;
// Check signal/named event name issues.
event name5_se;
wire name5_se;
// Check signal/generate loop name issues.
genvar i;
generate
for (i = 0; i < 2 ; i = i + 1) begin: name6_sgl
assign out[i] = i;
end
endgenerate
wire name6_sgl;
// Check signal/generate if name issues.
generate
if (parm == 1) begin: name7_sgi
assign out[1] = 1;
end
endgenerate
wire name7_sgi;
// Check signal/generate case name issues.
generate
case (parm)
1: begin: name8_sgc
assign out[1] = 1;
end
default: begin: name8_sgc
assign out[1] = 0;
end
endcase
endgenerate
wire name8_sgc;
// Check signal/generate block name issues.
generate
begin: name9_sgb
assign out[0] = 0;
end
endgenerate
wire name9_sgb;
initial $display("FAILED");
endmodule
module test(out);
output out;
reg out = 1'b0;
endmodule
|
//-------------------------------------------------------------------------
// This Verilog file was developed by Altera Corporation. It may be
// freely copied and/or distributed at no cost. Any persons using this
// file for any purpose do so at their own risk, and are responsible for
// the results of such use. Altera Corporation does not guarantee that
// this file is complete, correct, or fit for any particular purpose.
// NO WARRANTY OF ANY KIND IS EXPRESSED OR IMPLIED. This notice must
// accompany any copy of this file.
//------------------------------------------------------------------------
//
// Quartus II 13.1.0 Build 162 10/23/2013
//
//------------------------------------------------------------------------
// LPM Synthesizable Models (Support string type generic)
// These models are based on LPM version 220 (EIA-IS103 October 1998).
//------------------------------------------------------------------------
//
//-----------------------------------------------------------------------------
// Assumptions:
//
// 1. The default value for LPM_SVALUE, LPM_AVALUE, LPM_PVALUE, and
// LPM_STRENGTH is string UNUSED.
//
//-----------------------------------------------------------------------------
// Verilog Language Issues:
//
// Two dimensional ports are not supported. Modules with two dimensional
// ports are implemented as one dimensional signal of (LPM_SIZE * LPM_WIDTH)
// bits wide.
//
//-----------------------------------------------------------------------------
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_MEMORY_INITIALIZATION
//
// Description : Common function to read intel-hex format data file with
// extension .hex and creates the equivalent verilog format
// data file with extension .ver.
//
// Limitation : Supports only record type '00'(data record), '01'(end of
// file record) and '02'(extended segment address record).
//
// Results expected: Creates the verilog format data file with extension .ver
// and return the name of the file.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
`define LPM_TRUE 1
`define LPM_FALSE 0
`define LPM_NULL 0
`define LPM_EOF -1
`define LPM_MAX_NAME_SZ 128
`define LPM_MAX_WIDTH 256
`define LPM_COLON ":"
`define LPM_DOT "."
`define LPM_NEWLINE "\n"
`define LPM_CARRIAGE_RETURN 8'h0D
`define LPM_SPACE " "
`define LPM_TAB "\t"
`define LPM_OPEN_BRACKET "["
`define LPM_CLOSE_BRACKET "]"
`define LPM_OFFSET 9
`define LPM_H10 8'h10
`define LPM_H10000 20'h10000
`define LPM_AWORD 8
`define LPM_MASK15 32'h000000FF
`define LPM_EXT_STR "ver"
`define LPM_PERCENT "%"
`define LPM_MINUS "-"
`define LPM_SEMICOLON ";"
`define LPM_EQUAL "="
// MODULE DECLARATION
module LPM_MEMORY_INITIALIZATION;
/****************************************************************/
/* convert uppercase character values to lowercase. */
/****************************************************************/
function [8:1] tolower;
input [8:1] given_character;
reg [8:1] conv_char;
begin
if ((given_character >= 65) && (given_character <= 90)) // ASCII number of 'A' is 65, 'Z' is 90
begin
conv_char = given_character + 32; // 32 is the difference in the position of 'A' and 'a' in the ASCII char set
tolower = conv_char;
end
else
tolower = given_character;
end
endfunction
/****************************************************************/
/* Read in Altera-mif format data to verilog format data. */
/****************************************************************/
task convert_mif2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] buffer;
reg [`LPM_MAX_WIDTH : 0] memory_data1, memory_data2;
reg [8 : 1] c;
reg [3 : 0] hex, tmp_char;
reg [24 : 1] address_radix, data_radix;
reg get_width;
reg get_depth;
reg get_data_radix;
reg get_address_radix;
reg width_found;
reg depth_found;
reg data_radix_found;
reg address_radix_found;
reg get_address_data_pairs;
reg get_address;
reg get_data;
reg display_address;
reg invalid_address;
reg get_start_address;
reg get_end_address;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer memory_width, memory_depth;
integer value;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, address, tt, cc, aah, aal, dd, sum ;
integer start_address, end_address;
integer line_no;
integer character_count;
integer comment_with_percent_found;
integer comment_with_double_minus_found;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
comment_with_percent_found = `LPM_FALSE;
comment_with_double_minus_found = `LPM_FALSE;
off_addr= 0;
nn= 0;
address = 0;
start_address = 0;
end_address = 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
value = 0;
buffer = "";
character_count = 0;
memory_width = 0;
memory_depth = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
memory_data2 = {(`LPM_MAX_WIDTH+1) {1'b0}};
address_radix = "hex";
data_radix = "hex";
get_width = `LPM_FALSE;
get_depth = `LPM_FALSE;
get_data_radix = `LPM_FALSE;
get_address_radix = `LPM_FALSE;
width_found = `LPM_FALSE;
depth_found = `LPM_FALSE;
data_radix_found = `LPM_FALSE;
address_radix_found = `LPM_FALSE;
get_address_data_pairs = `LPM_FALSE;
display_address = `LPM_FALSE;
invalid_address = `LPM_FALSE;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_FALSE;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".mif") || (out_file[4*8 : 1] == ".MIF"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .mif extension and Altera-mif data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
// to do : add more checking on whether a particular assigment(width, depth, memory/address) are mising
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `end` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
done = `LPM_TRUE;
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
else if (buffer == "content")
begin
// continue to next character
end
else
if (buffer != "")
begin
// found invalid syntax in the particular line.
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
disable READER;
end
line_no = line_no +1;
end
else if ((r == `LPM_SPACE) || (r == `LPM_TAB))
begin
// continue to next character;
end
else if (r == `LPM_PERCENT)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_PERCENT) && (r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else if (r == `LPM_MINUS)
begin
r = $fgetc(ifp);
if (r == `LPM_MINUS)
begin
// Ignore all the characters which which is part of comment.
r = $fgetc(ifp);
while ((r != `LPM_NEWLINE) && (r != `LPM_CARRIAGE_RETURN))
begin
r = $fgetc(ifp);
end
if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
if ((buffer == "contentbegin") && (get_address_data_pairs == `LPM_FALSE))
begin
get_address_data_pairs = `LPM_TRUE;
get_address = `LPM_TRUE;
buffer = "";
end
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_EQUAL)
begin
if (buffer == "width")
begin
if (width_found == `LPM_FALSE)
begin
get_width = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Width has already been specified once.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (buffer == "depth")
begin
get_depth = `LPM_TRUE;
buffer = "";
end
else if (buffer == "data_radix")
begin
get_data_radix = `LPM_TRUE;
buffer = "";
end
else if (buffer == "address_radix")
begin
get_address_radix = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown setting (%0s).", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
if (!get_address_data_pairs)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else if (invalid_address == `LPM_TRUE)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
begin
get_address = `LPM_FALSE;
get_data = `LPM_TRUE;
display_address = `LPM_TRUE;
end
end
else if (r == `LPM_DOT)
begin
r = $fgetc(ifp);
if (r == `LPM_DOT)
begin
if (get_start_address == `LPM_TRUE)
begin
start_address = address;
address = 0;
get_start_address = `LPM_FALSE;
get_end_address = `LPM_TRUE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_OPEN_BRACKET)
begin
get_start_address = `LPM_TRUE;
end
else if (r == `LPM_CLOSE_BRACKET)
begin
if (get_end_address == `LPM_TRUE)
begin
end_address = address;
address = 0;
get_end_address = `LPM_FALSE;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid Altera-mif record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
else if (r == `LPM_SEMICOLON)
begin
if (get_width == `LPM_TRUE)
begin
width_found = `LPM_TRUE;
memory_width = value;
value = 0;
get_width = `LPM_FALSE;
end
else if (get_depth == `LPM_TRUE)
begin
depth_found = `LPM_TRUE;
memory_depth = value;
value = 0;
get_depth = `LPM_FALSE;
end
else if (get_data_radix == `LPM_TRUE)
begin
data_radix_found = `LPM_TRUE;
get_data_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
data_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to data_radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (get_address_radix == `LPM_TRUE)
begin
address_radix_found = `LPM_TRUE;
get_address_radix = `LPM_FALSE;
if ((buffer == "bin") || (buffer == "oct") || (buffer == "dec") || (buffer == "uns") ||
(buffer == "hex"))
begin
address_radix = buffer[24 : 1];
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment (%0s) to address radix.", in_file, line_no, buffer);
$display("Time: %0t Instance: %m", $time);
end
buffer = "";
end
else if (buffer == "end")
begin
if (get_address_data_pairs == `LPM_TRUE)
begin
last_rec = `LPM_TRUE;
buffer = "";
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing `content begin` statement.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_data == `LPM_TRUE)
begin
get_address = `LPM_TRUE;
get_data = `LPM_FALSE;
buffer = "";
character_count = 0;
if (start_address != end_address)
begin
for (address = start_address; address <= end_address; address = address+1)
begin
$fdisplay(ofp,"@%0h", address);
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
end
start_address = 0;
end_address = 0;
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
else
begin
if (display_address == `LPM_TRUE)
begin
$fdisplay(ofp,"@%0h", address);
display_address = `LPM_FALSE;
end
for (i = memory_width -1; i >= 0; i = i-1 )
begin
hex[(i % 4)] = memory_data1[i];
if ((i % 4) == 0)
begin
$fwrite(ofp, "%0h", hex);
hex = 0;
end
end
$fwrite(ofp, "\n");
address = 0;
hex = 0;
memory_data1 = {(`LPM_MAX_WIDTH+1) {1'b0}};
end
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assigment.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if ((get_width == `LPM_TRUE) || (get_depth == `LPM_TRUE))
begin
if ((r >= "0") && (r <= "9"))
value = (value * 10) + (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid assignment to width/depth.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (get_address == `LPM_TRUE)
begin
if (address_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 16) + value;
end
else if ((address_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 10) + value;
end
else if (address_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 2) + value;
end
else if (address_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
invalid_address = `LPM_TRUE;
end
address = (address * 8) + value;
end
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
else if (get_data == `LPM_TRUE)
begin
character_count = character_count +1;
if (data_radix == "hex")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
value = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
value = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 16) + value;
end
else if ((data_radix == "dec"))
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "uns")
begin
if ((r >= "0") && (r <= "9"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 10) + value;
end
else if (data_radix == "bin")
begin
if ((r >= "0") && (r <= "1"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 2) + value;
end
else if (data_radix == "oct")
begin
if ((r >= "0") && (r <= "7"))
value = (r - 'h30);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
memory_data1 = (memory_data1 * 8) + value;
end
end
else
begin
first_rec = `LPM_TRUE;
if ((r >= 65) && (r <= 90))
c = tolower(r);
else
c = r;
{tmp_char,buffer} = {buffer, c};
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_mif2ver
/****************************************************************/
/* Read in Intel-hex format data to verilog format data. */
/* Intel-hex format :nnaaaaattddddcc */
/****************************************************************/
task convert_hex2ver;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [8:1] c;
reg [3:0] hex, tmp_char;
reg done;
reg error_status;
reg first_rec;
reg last_rec;
integer width;
integer ifp, ofp, r, r2;
integer i, j, k, m, n;
integer off_addr, nn, aaaa, tt, cc, aah, aal, dd, sum ;
integer line_no;
begin
done = `LPM_FALSE;
error_status = `LPM_FALSE;
first_rec = `LPM_FALSE;
last_rec = `LPM_FALSE;
off_addr= 0;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
line_no = 1;
c = 0;
hex = 0;
if((in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
out_file = in_file;
else
begin
ifp = $fopen(in_file, "r");
if (ifp == `LPM_NULL)
begin
$display("ERROR: cannot read %0s.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
out_file = in_file;
if((out_file[4*8 : 1] == ".hex") || (out_file[4*8 : 1] == ".HEX"))
out_file[3*8 : 1] = `LPM_EXT_STR;
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension and Intel-hex data format.", in_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
if (!done)
begin
ofp = $fopen(out_file, "w");
if (ofp == `LPM_NULL)
begin
$display("ERROR : cannot write %0s.", out_file);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
while((!done) && (!error_status))
begin : READER
r = $fgetc(ifp);
if (r == `LPM_EOF)
begin
if(!first_rec)
begin
error_status = `LPM_TRUE;
$display("WARNING: %0s, Intel-hex data file is empty.", in_file);
$display ("Time: %0t Instance: %m", $time);
end
else if(!last_rec)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Missing the last record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
else if (r == `LPM_COLON)
begin
first_rec = `LPM_TRUE;
nn= 0;
aaaa= 0;
tt= 0;
cc= 0;
aah= 0;
aal= 0;
dd= 0;
sum = 0;
// get record length bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
nn = (nn * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
nn = (nn * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
nn = (nn * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// get address bytes
for (i = 0; i < 4; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
aaaa = (aaaa * 16) + hex;
if (i < 2)
aal = (aal * 16) + hex;
else
aah = (aah * 16) + hex;
end
// get record type bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
tt = (tt * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
tt = (tt * 16) + 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
tt = (tt * 16) + 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
if((tt == 2) && (nn != 2) )
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid data record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
else
begin
// get the sum of all the bytes for record length, address and record types
sum = nn + aah + aal + tt ;
// check the record type
case(tt)
// normal_record
8'h00 :
begin
first_rec = `LPM_TRUE;
i = 0;
k = width / `LPM_AWORD;
if ((width % `LPM_AWORD) != 0)
k = k + 1;
// k = no. of bytes per entry.
while (i < nn)
begin
$fdisplay(ofp,"@%0h", (aaaa + off_addr));
for (j = 1; j <= k; j = j +1)
begin
if ((k - j +1) > nn)
begin
for(m = 1; m <= 2; m= m+1)
begin
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "0");
end
end
else
begin
// get the data bytes
for(m = 1; m <= 2; m= m+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
if((((k-j)*8) + ((3-m)*4) - width) < 4)
$fwrite(ofp, "%h", hex);
dd = (dd * 16) + hex;
if(m % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
end
end
$fwrite(ofp, "\n");
i = i + k;
aaaa = aaaa + 1;
end // end of while (i < nn)
end
// last record
8'h01:
begin
last_rec = `LPM_TRUE;
done = `LPM_TRUE;
end
// address base record
8'h02:
begin
off_addr= 0;
// get the extended segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10;
end
// address base record
8'h03:
// get the start segment address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
// address base record
8'h04:
begin
off_addr= 0;
// get the extended linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
off_addr = (off_addr * `LPM_H10) + hex;
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
off_addr = off_addr * `LPM_H10000;
end
// address base record
8'h05:
// get the start linear address record
for(i = 1; i <= (nn*2); i= i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
hex = (r - 'h30);
else if ((r >= "A") && (r <= "F"))
hex = 10 + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
hex = 10 + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
dd = (dd * 16) + hex;
if(i % 2 == 0)
begin
sum = sum + dd;
dd = 0;
end
end
default:
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Unknown record type.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
endcase
// get the checksum bytes
for (i = 0; i < 2; i = i+1)
begin
r = $fgetc(ifp);
if ((r >= "0") && (r <= "9"))
cc = (cc * 16) + (r - 'h30);
else if ((r >= "A") && (r <= "F"))
cc = 10 + (cc * 16) + (r - 'h41);
else if ((r >= "a") && (r <= "f"))
cc = 10 + (cc * 16) + (r - 'h61);
else
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
disable READER;
end
end
// Perform check sum.
if(((~sum+1)& `LPM_MASK15) != cc)
begin
error_status = `LPM_TRUE;
$display("ERROR: %0s, line %0d, Invalid checksum.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
end
end
end
else if ((r == `LPM_NEWLINE) || (r == `LPM_CARRIAGE_RETURN))
begin
line_no = line_no +1;
end
else if (r == `LPM_SPACE)
begin
// continue to next character;
end
else
begin
error_status = `LPM_TRUE;
$display("ERROR:%0s, line %0d, Invalid INTEL HEX record.", in_file, line_no);
$display("Time: %0t Instance: %m", $time);
done = `LPM_TRUE;
end
end
$fclose(ifp);
$fclose(ofp);
end
end
endtask // convert_hex2ver
task convert_to_ver_file;
input[`LPM_MAX_NAME_SZ*8 : 1] in_file;
input width;
output [`LPM_MAX_NAME_SZ*8 : 1] out_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] in_file;
reg [`LPM_MAX_NAME_SZ*8 : 1] out_file;
integer width;
begin
if((in_file[4*8 : 1] == ".hex") || (in_file[4*8 : 1] == ".HEX") ||
(in_file[4*8 : 1] == ".dat") || (in_file[4*8 : 1] == ".DAT"))
convert_hex2ver(in_file, width, out_file);
else if((in_file[4*8 : 1] == ".mif") || (in_file[4*8 : 1] == ".MIF"))
convert_mif2ver(in_file, width, out_file);
else
begin
$display("ERROR: Invalid input file name %0s. Expecting file with .hex extension (with Intel-hex data format) or .mif extension (with Altera-mif data format).", in_file);
$display("Time: %0t Instance: %m", $time);
end
end
endtask // convert_to_ver_file
endmodule // LPM_MEMORY_INITIALIZATION
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : LPM_HINT_EVALUATION
//
// Description : Common function to grep the value of altera specific parameters
// within the lpm_hint parameter.
//
// Limitation : No error checking to check whether the content of the lpm_hint
// is valid or not.
//
// Results expected: If the target parameter found, return the value of the parameter.
// Otherwise, return empty string.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_HINT_EVALUATION;
// FUNCTON DECLARATION
// This function will search through the string (given string) to look for a match for the
// a given parameter(compare_param_name). It will return the value for the given parameter.
function [8*200:1] GET_PARAMETER_VALUE;
input [8*200:1] given_string; // string to be searched
input [8*50:1] compare_param_name; // parameter name to be looking for in the given_string.
integer param_value_char_count; // to indicate current character count in the param_value
integer param_name_char_count; // to indicate current character count in the param_name
integer white_space_count;
reg extract_param_value; // if 1 mean extracting parameters value from given string
reg extract_param_name; // if 1 mean extracting parameters name from given string
reg param_found; // to indicate whether compare_param_name have been found in the given_string
reg include_white_space; // if 1, include white space in the parameter value
reg [8*200:1] reg_string; // to store the value of the given string
reg [8*50:1] param_name; // to store parameter name
reg [8*20:1] param_value; // to store parameter value
reg [8:1] tmp; // to get the value of the current byte
begin
reg_string = given_string;
param_value_char_count = 0;
param_name_char_count =0;
extract_param_value = 1;
extract_param_name = 0;
param_found = 0;
include_white_space = 0;
white_space_count = 0;
tmp = reg_string[8:1];
// checking every bytes of the reg_string from right to left.
while ((tmp != 0 ) && (param_found != 1))
begin
tmp = reg_string[8:1];
//if tmp != ' ' or should include white space (trailing white space are ignored)
if((tmp != 32) || (include_white_space == 1))
begin
if(tmp == 32)
begin
white_space_count = 1;
end
else if(tmp == 61) // if tmp = '='
begin
extract_param_value = 0;
extract_param_name = 1; // subsequent bytes should be part of param_name
include_white_space = 0; // ignore the white space (if any) between param_name and '='
white_space_count = 0;
param_value = param_value >> (8 * (20 - param_value_char_count));
param_value_char_count = 0;
end
else if (tmp == 44) // if tmp = ','
begin
extract_param_value = 1; // subsequent bytes should be part of param_value
extract_param_name = 0;
param_name = param_name >> (8 * (50 - param_name_char_count));
param_name_char_count = 0;
if(param_name == compare_param_name)
param_found = 1; // the compare_param_name have been found in the reg_string
end
else
begin
if(extract_param_value == 1)
begin
param_value_char_count = param_value_char_count + white_space_count + 1;
include_white_space = 1;
if(white_space_count > 0)
begin
param_value = {8'b100000, param_value[20*8:9]};
white_space_count = 0;
end
param_value = {tmp, param_value[20*8:9]};
end
else if(extract_param_name == 1)
begin
param_name = {tmp, param_name[50*8:9]};
param_name_char_count = param_name_char_count + 1;
end
end
end
reg_string = reg_string >> 8; // shift 1 byte to the right
end
// for the case whether param_name is the left most part of the reg_string
if(extract_param_name == 1)
begin
param_name = param_name >> (8 * (50 - param_name_char_count));
if(param_name == compare_param_name)
param_found = 1;
end
if (param_found == 1)
GET_PARAMETER_VALUE = param_value; // return the value of the parameter been looking for
else
GET_PARAMETER_VALUE = ""; // return empty string if parameter not found
end
endfunction
endmodule // LPM_HINT_EVALUATION
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module LPM_DEVICE_FAMILIES;
function IS_FAMILY_CYCLONE;
input[8*20:1] device;
reg is_cyclone;
begin
if ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
is_cyclone = 1;
else
is_cyclone = 0;
IS_FAMILY_CYCLONE = is_cyclone;
end
endfunction //IS_FAMILY_CYCLONE
function IS_FAMILY_MAX3000A;
input[8*20:1] device;
reg is_max3000a;
begin
if ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
is_max3000a = 1;
else
is_max3000a = 0;
IS_FAMILY_MAX3000A = is_max3000a;
end
endfunction //IS_FAMILY_MAX3000A
function IS_FAMILY_MAX7000A;
input[8*20:1] device;
reg is_max7000a;
begin
if ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
is_max7000a = 1;
else
is_max7000a = 0;
IS_FAMILY_MAX7000A = is_max7000a;
end
endfunction //IS_FAMILY_MAX7000A
function IS_FAMILY_MAX7000AE;
input[8*20:1] device;
reg is_max7000ae;
begin
if ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
is_max7000ae = 1;
else
is_max7000ae = 0;
IS_FAMILY_MAX7000AE = is_max7000ae;
end
endfunction //IS_FAMILY_MAX7000AE
function IS_FAMILY_MAX7000B;
input[8*20:1] device;
reg is_max7000b;
begin
if ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
is_max7000b = 1;
else
is_max7000b = 0;
IS_FAMILY_MAX7000B = is_max7000b;
end
endfunction //IS_FAMILY_MAX7000B
function IS_FAMILY_MAX7000S;
input[8*20:1] device;
reg is_max7000s;
begin
if ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
is_max7000s = 1;
else
is_max7000s = 0;
IS_FAMILY_MAX7000S = is_max7000s;
end
endfunction //IS_FAMILY_MAX7000S
function IS_FAMILY_STRATIXGX;
input[8*20:1] device;
reg is_stratixgx;
begin
if ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
is_stratixgx = 1;
else
is_stratixgx = 0;
IS_FAMILY_STRATIXGX = is_stratixgx;
end
endfunction //IS_FAMILY_STRATIXGX
function IS_FAMILY_STRATIX;
input[8*20:1] device;
reg is_stratix;
begin
if ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
is_stratix = 1;
else
is_stratix = 0;
IS_FAMILY_STRATIX = is_stratix;
end
endfunction //IS_FAMILY_STRATIX
function FEATURE_FAMILY_BASE_STRATIX;
input[8*20:1] device;
reg var_family_base_stratix;
begin
if (IS_FAMILY_STRATIX(device) || IS_FAMILY_STRATIXGX(device) )
var_family_base_stratix = 1;
else
var_family_base_stratix = 0;
FEATURE_FAMILY_BASE_STRATIX = var_family_base_stratix;
end
endfunction //FEATURE_FAMILY_BASE_STRATIX
function FEATURE_FAMILY_BASE_CYCLONE;
input[8*20:1] device;
reg var_family_base_cyclone;
begin
if (IS_FAMILY_CYCLONE(device) )
var_family_base_cyclone = 1;
else
var_family_base_cyclone = 0;
FEATURE_FAMILY_BASE_CYCLONE = var_family_base_cyclone;
end
endfunction //FEATURE_FAMILY_BASE_CYCLONE
function FEATURE_FAMILY_MAX;
input[8*20:1] device;
reg var_family_max;
begin
if ((device == "MAX5000") || IS_FAMILY_MAX3000A(device) || (device == "MAX7000") || IS_FAMILY_MAX7000A(device) || IS_FAMILY_MAX7000AE(device) || (device == "MAX7000E") || IS_FAMILY_MAX7000S(device) || IS_FAMILY_MAX7000B(device) || (device == "MAX9000") )
var_family_max = 1;
else
var_family_max = 0;
FEATURE_FAMILY_MAX = var_family_max;
end
endfunction //FEATURE_FAMILY_MAX
function IS_VALID_FAMILY;
input[8*20:1] device;
reg is_valid;
begin
if (((device == "Arria 10") || (device == "ARRIA 10") || (device == "arria 10") || (device == "Arria10") || (device == "ARRIA10") || (device == "arria10") || (device == "Arria VI") || (device == "ARRIA VI") || (device == "arria vi") || (device == "ArriaVI") || (device == "ARRIAVI") || (device == "arriavi") || (device == "Night Fury") || (device == "NIGHT FURY") || (device == "night fury") || (device == "nightfury") || (device == "NIGHTFURY") || (device == "Arria 10 (GX/SX/GT)") || (device == "ARRIA 10 (GX/SX/GT)") || (device == "arria 10 (gx/sx/gt)") || (device == "Arria10(GX/SX/GT)") || (device == "ARRIA10(GX/SX/GT)") || (device == "arria10(gx/sx/gt)") || (device == "Arria 10 (GX)") || (device == "ARRIA 10 (GX)") || (device == "arria 10 (gx)") || (device == "Arria10(GX)") || (device == "ARRIA10(GX)") || (device == "arria10(gx)") || (device == "Arria 10 (SX)") || (device == "ARRIA 10 (SX)") || (device == "arria 10 (sx)") || (device == "Arria10(SX)") || (device == "ARRIA10(SX)") || (device == "arria10(sx)") || (device == "Arria 10 (GT)") || (device == "ARRIA 10 (GT)") || (device == "arria 10 (gt)") || (device == "Arria10(GT)") || (device == "ARRIA10(GT)") || (device == "arria10(gt)"))
|| ((device == "Arria GX") || (device == "ARRIA GX") || (device == "arria gx") || (device == "ArriaGX") || (device == "ARRIAGX") || (device == "arriagx") || (device == "Stratix II GX Lite") || (device == "STRATIX II GX LITE") || (device == "stratix ii gx lite") || (device == "StratixIIGXLite") || (device == "STRATIXIIGXLITE") || (device == "stratixiigxlite"))
|| ((device == "Arria II GX") || (device == "ARRIA II GX") || (device == "arria ii gx") || (device == "ArriaIIGX") || (device == "ARRIAIIGX") || (device == "arriaiigx") || (device == "Arria IIGX") || (device == "ARRIA IIGX") || (device == "arria iigx") || (device == "ArriaII GX") || (device == "ARRIAII GX") || (device == "arriaii gx") || (device == "Arria II") || (device == "ARRIA II") || (device == "arria ii") || (device == "ArriaII") || (device == "ARRIAII") || (device == "arriaii") || (device == "Arria II (GX/E)") || (device == "ARRIA II (GX/E)") || (device == "arria ii (gx/e)") || (device == "ArriaII(GX/E)") || (device == "ARRIAII(GX/E)") || (device == "arriaii(gx/e)") || (device == "PIRANHA") || (device == "piranha"))
|| ((device == "Arria II GZ") || (device == "ARRIA II GZ") || (device == "arria ii gz") || (device == "ArriaII GZ") || (device == "ARRIAII GZ") || (device == "arriaii gz") || (device == "Arria IIGZ") || (device == "ARRIA IIGZ") || (device == "arria iigz") || (device == "ArriaIIGZ") || (device == "ARRIAIIGZ") || (device == "arriaiigz"))
|| ((device == "Arria V GZ") || (device == "ARRIA V GZ") || (device == "arria v gz") || (device == "ArriaVGZ") || (device == "ARRIAVGZ") || (device == "arriavgz"))
|| ((device == "Arria V") || (device == "ARRIA V") || (device == "arria v") || (device == "Arria V (GT/GX)") || (device == "ARRIA V (GT/GX)") || (device == "arria v (gt/gx)") || (device == "ArriaV(GT/GX)") || (device == "ARRIAV(GT/GX)") || (device == "arriav(gt/gx)") || (device == "ArriaV") || (device == "ARRIAV") || (device == "arriav") || (device == "Arria V (GT/GX/ST/SX)") || (device == "ARRIA V (GT/GX/ST/SX)") || (device == "arria v (gt/gx/st/sx)") || (device == "ArriaV(GT/GX/ST/SX)") || (device == "ARRIAV(GT/GX/ST/SX)") || (device == "arriav(gt/gx/st/sx)") || (device == "Arria V (GT)") || (device == "ARRIA V (GT)") || (device == "arria v (gt)") || (device == "ArriaV(GT)") || (device == "ARRIAV(GT)") || (device == "arriav(gt)") || (device == "Arria V (GX)") || (device == "ARRIA V (GX)") || (device == "arria v (gx)") || (device == "ArriaV(GX)") || (device == "ARRIAV(GX)") || (device == "arriav(gx)") || (device == "Arria V (ST)") || (device == "ARRIA V (ST)") || (device == "arria v (st)") || (device == "ArriaV(ST)") || (device == "ARRIAV(ST)") || (device == "arriav(st)") || (device == "Arria V (SX)") || (device == "ARRIA V (SX)") || (device == "arria v (sx)") || (device == "ArriaV(SX)") || (device == "ARRIAV(SX)") || (device == "arriav(sx)"))
|| ((device == "BS") || (device == "bs"))
|| ((device == "Cyclone II") || (device == "CYCLONE II") || (device == "cyclone ii") || (device == "Cycloneii") || (device == "CYCLONEII") || (device == "cycloneii") || (device == "Magellan") || (device == "MAGELLAN") || (device == "magellan") || (device == "CycloneII") || (device == "CYCLONEII") || (device == "cycloneii"))
|| ((device == "Cyclone III LS") || (device == "CYCLONE III LS") || (device == "cyclone iii ls") || (device == "CycloneIIILS") || (device == "CYCLONEIIILS") || (device == "cycloneiiils") || (device == "Cyclone III LPS") || (device == "CYCLONE III LPS") || (device == "cyclone iii lps") || (device == "Cyclone LPS") || (device == "CYCLONE LPS") || (device == "cyclone lps") || (device == "CycloneLPS") || (device == "CYCLONELPS") || (device == "cyclonelps") || (device == "Tarpon") || (device == "TARPON") || (device == "tarpon") || (device == "Cyclone IIIE") || (device == "CYCLONE IIIE") || (device == "cyclone iiie"))
|| ((device == "Cyclone III") || (device == "CYCLONE III") || (device == "cyclone iii") || (device == "CycloneIII") || (device == "CYCLONEIII") || (device == "cycloneiii") || (device == "Barracuda") || (device == "BARRACUDA") || (device == "barracuda") || (device == "Cuda") || (device == "CUDA") || (device == "cuda") || (device == "CIII") || (device == "ciii"))
|| ((device == "Cyclone IV E") || (device == "CYCLONE IV E") || (device == "cyclone iv e") || (device == "CycloneIV E") || (device == "CYCLONEIV E") || (device == "cycloneiv e") || (device == "Cyclone IVE") || (device == "CYCLONE IVE") || (device == "cyclone ive") || (device == "CycloneIVE") || (device == "CYCLONEIVE") || (device == "cycloneive"))
|| ((device == "Cyclone IV GX") || (device == "CYCLONE IV GX") || (device == "cyclone iv gx") || (device == "Cyclone IVGX") || (device == "CYCLONE IVGX") || (device == "cyclone ivgx") || (device == "CycloneIV GX") || (device == "CYCLONEIV GX") || (device == "cycloneiv gx") || (device == "CycloneIVGX") || (device == "CYCLONEIVGX") || (device == "cycloneivgx") || (device == "Cyclone IV") || (device == "CYCLONE IV") || (device == "cyclone iv") || (device == "CycloneIV") || (device == "CYCLONEIV") || (device == "cycloneiv") || (device == "Cyclone IV (GX)") || (device == "CYCLONE IV (GX)") || (device == "cyclone iv (gx)") || (device == "CycloneIV(GX)") || (device == "CYCLONEIV(GX)") || (device == "cycloneiv(gx)") || (device == "Cyclone III GX") || (device == "CYCLONE III GX") || (device == "cyclone iii gx") || (device == "CycloneIII GX") || (device == "CYCLONEIII GX") || (device == "cycloneiii gx") || (device == "Cyclone IIIGX") || (device == "CYCLONE IIIGX") || (device == "cyclone iiigx") || (device == "CycloneIIIGX") || (device == "CYCLONEIIIGX") || (device == "cycloneiiigx") || (device == "Cyclone III GL") || (device == "CYCLONE III GL") || (device == "cyclone iii gl") || (device == "CycloneIII GL") || (device == "CYCLONEIII GL") || (device == "cycloneiii gl") || (device == "Cyclone IIIGL") || (device == "CYCLONE IIIGL") || (device == "cyclone iiigl") || (device == "CycloneIIIGL") || (device == "CYCLONEIIIGL") || (device == "cycloneiiigl") || (device == "Stingray") || (device == "STINGRAY") || (device == "stingray"))
|| ((device == "Cyclone V") || (device == "CYCLONE V") || (device == "cyclone v") || (device == "CycloneV") || (device == "CYCLONEV") || (device == "cyclonev") || (device == "Cyclone V (GT/GX/E/SX)") || (device == "CYCLONE V (GT/GX/E/SX)") || (device == "cyclone v (gt/gx/e/sx)") || (device == "CycloneV(GT/GX/E/SX)") || (device == "CYCLONEV(GT/GX/E/SX)") || (device == "cyclonev(gt/gx/e/sx)") || (device == "Cyclone V (E/GX/GT/SX/SE/ST)") || (device == "CYCLONE V (E/GX/GT/SX/SE/ST)") || (device == "cyclone v (e/gx/gt/sx/se/st)") || (device == "CycloneV(E/GX/GT/SX/SE/ST)") || (device == "CYCLONEV(E/GX/GT/SX/SE/ST)") || (device == "cyclonev(e/gx/gt/sx/se/st)") || (device == "Cyclone V (E)") || (device == "CYCLONE V (E)") || (device == "cyclone v (e)") || (device == "CycloneV(E)") || (device == "CYCLONEV(E)") || (device == "cyclonev(e)") || (device == "Cyclone V (GX)") || (device == "CYCLONE V (GX)") || (device == "cyclone v (gx)") || (device == "CycloneV(GX)") || (device == "CYCLONEV(GX)") || (device == "cyclonev(gx)") || (device == "Cyclone V (GT)") || (device == "CYCLONE V (GT)") || (device == "cyclone v (gt)") || (device == "CycloneV(GT)") || (device == "CYCLONEV(GT)") || (device == "cyclonev(gt)") || (device == "Cyclone V (SX)") || (device == "CYCLONE V (SX)") || (device == "cyclone v (sx)") || (device == "CycloneV(SX)") || (device == "CYCLONEV(SX)") || (device == "cyclonev(sx)") || (device == "Cyclone V (SE)") || (device == "CYCLONE V (SE)") || (device == "cyclone v (se)") || (device == "CycloneV(SE)") || (device == "CYCLONEV(SE)") || (device == "cyclonev(se)") || (device == "Cyclone V (ST)") || (device == "CYCLONE V (ST)") || (device == "cyclone v (st)") || (device == "CycloneV(ST)") || (device == "CYCLONEV(ST)") || (device == "cyclonev(st)"))
|| ((device == "Cyclone") || (device == "CYCLONE") || (device == "cyclone") || (device == "ACEX2K") || (device == "acex2k") || (device == "ACEX 2K") || (device == "acex 2k") || (device == "Tornado") || (device == "TORNADO") || (device == "tornado"))
|| ((device == "HardCopy II") || (device == "HARDCOPY II") || (device == "hardcopy ii") || (device == "HardCopyII") || (device == "HARDCOPYII") || (device == "hardcopyii") || (device == "Fusion") || (device == "FUSION") || (device == "fusion"))
|| ((device == "HardCopy III") || (device == "HARDCOPY III") || (device == "hardcopy iii") || (device == "HardCopyIII") || (device == "HARDCOPYIII") || (device == "hardcopyiii") || (device == "HCX") || (device == "hcx"))
|| ((device == "HardCopy IV") || (device == "HARDCOPY IV") || (device == "hardcopy iv") || (device == "HardCopyIV") || (device == "HARDCOPYIV") || (device == "hardcopyiv") || (device == "HardCopy IV (GX)") || (device == "HARDCOPY IV (GX)") || (device == "hardcopy iv (gx)") || (device == "HardCopy IV (E)") || (device == "HARDCOPY IV (E)") || (device == "hardcopy iv (e)") || (device == "HardCopyIV(GX)") || (device == "HARDCOPYIV(GX)") || (device == "hardcopyiv(gx)") || (device == "HardCopyIV(E)") || (device == "HARDCOPYIV(E)") || (device == "hardcopyiv(e)") || (device == "HCXIV") || (device == "hcxiv") || (device == "HardCopy IV (GX/E)") || (device == "HARDCOPY IV (GX/E)") || (device == "hardcopy iv (gx/e)") || (device == "HardCopy IV (E/GX)") || (device == "HARDCOPY IV (E/GX)") || (device == "hardcopy iv (e/gx)") || (device == "HardCopyIV(GX/E)") || (device == "HARDCOPYIV(GX/E)") || (device == "hardcopyiv(gx/e)") || (device == "HardCopyIV(E/GX)") || (device == "HARDCOPYIV(E/GX)") || (device == "hardcopyiv(e/gx)"))
|| ((device == "MAX 10 FPGA") || (device == "max 10 fpga") || (device == "Zippleback") || (device == "ZIPPLEBACK") || (device == "zippleback") || (device == "MAX10FPGA") || (device == "max10fpga") || (device == "MAX 10 FPGA (DA/DF/DC/SF/SC)") || (device == "max 10 fpga (da/df/dc/sf/sc)") || (device == "MAX10FPGA(DA/DF/DC/SF/SC)") || (device == "max10fpga(da/df/dc/sf/sc)") || (device == "MAX 10 FPGA (DA)") || (device == "max 10 fpga (da)") || (device == "MAX10FPGA(DA)") || (device == "max10fpga(da)") || (device == "MAX 10 FPGA (DF)") || (device == "max 10 fpga (df)") || (device == "MAX10FPGA(DF)") || (device == "max10fpga(df)") || (device == "MAX 10 FPGA (DC)") || (device == "max 10 fpga (dc)") || (device == "MAX10FPGA(DC)") || (device == "max10fpga(dc)") || (device == "MAX 10 FPGA (SF)") || (device == "max 10 fpga (sf)") || (device == "MAX10FPGA(SF)") || (device == "max10fpga(sf)") || (device == "MAX 10 FPGA (SC)") || (device == "max 10 fpga (sc)") || (device == "MAX10FPGA(SC)") || (device == "max10fpga(sc)"))
|| ((device == "MAX II") || (device == "max ii") || (device == "MAXII") || (device == "maxii") || (device == "Tsunami") || (device == "TSUNAMI") || (device == "tsunami"))
|| ((device == "MAX V") || (device == "max v") || (device == "MAXV") || (device == "maxv") || (device == "Jade") || (device == "JADE") || (device == "jade"))
|| ((device == "MAX3000A") || (device == "max3000a") || (device == "MAX 3000A") || (device == "max 3000a"))
|| ((device == "MAX7000A") || (device == "max7000a") || (device == "MAX 7000A") || (device == "max 7000a"))
|| ((device == "MAX7000AE") || (device == "max7000ae") || (device == "MAX 7000AE") || (device == "max 7000ae"))
|| ((device == "MAX7000B") || (device == "max7000b") || (device == "MAX 7000B") || (device == "max 7000b"))
|| ((device == "MAX7000S") || (device == "max7000s") || (device == "MAX 7000S") || (device == "max 7000s"))
|| ((device == "Stratix GX") || (device == "STRATIX GX") || (device == "stratix gx") || (device == "Stratix-GX") || (device == "STRATIX-GX") || (device == "stratix-gx") || (device == "StratixGX") || (device == "STRATIXGX") || (device == "stratixgx") || (device == "Aurora") || (device == "AURORA") || (device == "aurora"))
|| ((device == "Stratix II GX") || (device == "STRATIX II GX") || (device == "stratix ii gx") || (device == "StratixIIGX") || (device == "STRATIXIIGX") || (device == "stratixiigx"))
|| ((device == "Stratix II") || (device == "STRATIX II") || (device == "stratix ii") || (device == "StratixII") || (device == "STRATIXII") || (device == "stratixii") || (device == "Armstrong") || (device == "ARMSTRONG") || (device == "armstrong"))
|| ((device == "Stratix III") || (device == "STRATIX III") || (device == "stratix iii") || (device == "StratixIII") || (device == "STRATIXIII") || (device == "stratixiii") || (device == "Titan") || (device == "TITAN") || (device == "titan") || (device == "SIII") || (device == "siii"))
|| ((device == "Stratix IV") || (device == "STRATIX IV") || (device == "stratix iv") || (device == "TGX") || (device == "tgx") || (device == "StratixIV") || (device == "STRATIXIV") || (device == "stratixiv") || (device == "Stratix IV (GT)") || (device == "STRATIX IV (GT)") || (device == "stratix iv (gt)") || (device == "Stratix IV (GX)") || (device == "STRATIX IV (GX)") || (device == "stratix iv (gx)") || (device == "Stratix IV (E)") || (device == "STRATIX IV (E)") || (device == "stratix iv (e)") || (device == "StratixIV(GT)") || (device == "STRATIXIV(GT)") || (device == "stratixiv(gt)") || (device == "StratixIV(GX)") || (device == "STRATIXIV(GX)") || (device == "stratixiv(gx)") || (device == "StratixIV(E)") || (device == "STRATIXIV(E)") || (device == "stratixiv(e)") || (device == "StratixIIIGX") || (device == "STRATIXIIIGX") || (device == "stratixiiigx") || (device == "Stratix IV (GT/GX/E)") || (device == "STRATIX IV (GT/GX/E)") || (device == "stratix iv (gt/gx/e)") || (device == "Stratix IV (GT/E/GX)") || (device == "STRATIX IV (GT/E/GX)") || (device == "stratix iv (gt/e/gx)") || (device == "Stratix IV (E/GT/GX)") || (device == "STRATIX IV (E/GT/GX)") || (device == "stratix iv (e/gt/gx)") || (device == "Stratix IV (E/GX/GT)") || (device == "STRATIX IV (E/GX/GT)") || (device == "stratix iv (e/gx/gt)") || (device == "StratixIV(GT/GX/E)") || (device == "STRATIXIV(GT/GX/E)") || (device == "stratixiv(gt/gx/e)") || (device == "StratixIV(GT/E/GX)") || (device == "STRATIXIV(GT/E/GX)") || (device == "stratixiv(gt/e/gx)") || (device == "StratixIV(E/GX/GT)") || (device == "STRATIXIV(E/GX/GT)") || (device == "stratixiv(e/gx/gt)") || (device == "StratixIV(E/GT/GX)") || (device == "STRATIXIV(E/GT/GX)") || (device == "stratixiv(e/gt/gx)") || (device == "Stratix IV (GX/E)") || (device == "STRATIX IV (GX/E)") || (device == "stratix iv (gx/e)") || (device == "StratixIV(GX/E)") || (device == "STRATIXIV(GX/E)") || (device == "stratixiv(gx/e)"))
|| ((device == "Stratix V") || (device == "STRATIX V") || (device == "stratix v") || (device == "StratixV") || (device == "STRATIXV") || (device == "stratixv") || (device == "Stratix V (GS)") || (device == "STRATIX V (GS)") || (device == "stratix v (gs)") || (device == "StratixV(GS)") || (device == "STRATIXV(GS)") || (device == "stratixv(gs)") || (device == "Stratix V (GT)") || (device == "STRATIX V (GT)") || (device == "stratix v (gt)") || (device == "StratixV(GT)") || (device == "STRATIXV(GT)") || (device == "stratixv(gt)") || (device == "Stratix V (GX)") || (device == "STRATIX V (GX)") || (device == "stratix v (gx)") || (device == "StratixV(GX)") || (device == "STRATIXV(GX)") || (device == "stratixv(gx)") || (device == "Stratix V (GS/GX)") || (device == "STRATIX V (GS/GX)") || (device == "stratix v (gs/gx)") || (device == "StratixV(GS/GX)") || (device == "STRATIXV(GS/GX)") || (device == "stratixv(gs/gx)") || (device == "Stratix V (GS/GT)") || (device == "STRATIX V (GS/GT)") || (device == "stratix v (gs/gt)") || (device == "StratixV(GS/GT)") || (device == "STRATIXV(GS/GT)") || (device == "stratixv(gs/gt)") || (device == "Stratix V (GT/GX)") || (device == "STRATIX V (GT/GX)") || (device == "stratix v (gt/gx)") || (device == "StratixV(GT/GX)") || (device == "STRATIXV(GT/GX)") || (device == "stratixv(gt/gx)") || (device == "Stratix V (GX/GS)") || (device == "STRATIX V (GX/GS)") || (device == "stratix v (gx/gs)") || (device == "StratixV(GX/GS)") || (device == "STRATIXV(GX/GS)") || (device == "stratixv(gx/gs)") || (device == "Stratix V (GT/GS)") || (device == "STRATIX V (GT/GS)") || (device == "stratix v (gt/gs)") || (device == "StratixV(GT/GS)") || (device == "STRATIXV(GT/GS)") || (device == "stratixv(gt/gs)") || (device == "Stratix V (GX/GT)") || (device == "STRATIX V (GX/GT)") || (device == "stratix v (gx/gt)") || (device == "StratixV(GX/GT)") || (device == "STRATIXV(GX/GT)") || (device == "stratixv(gx/gt)") || (device == "Stratix V (GS/GT/GX)") || (device == "STRATIX V (GS/GT/GX)") || (device == "stratix v (gs/gt/gx)") || (device == "Stratix V (GS/GX/GT)") || (device == "STRATIX V (GS/GX/GT)") || (device == "stratix v (gs/gx/gt)") || (device == "Stratix V (GT/GS/GX)") || (device == "STRATIX V (GT/GS/GX)") || (device == "stratix v (gt/gs/gx)") || (device == "Stratix V (GT/GX/GS)") || (device == "STRATIX V (GT/GX/GS)") || (device == "stratix v (gt/gx/gs)") || (device == "Stratix V (GX/GS/GT)") || (device == "STRATIX V (GX/GS/GT)") || (device == "stratix v (gx/gs/gt)") || (device == "Stratix V (GX/GT/GS)") || (device == "STRATIX V (GX/GT/GS)") || (device == "stratix v (gx/gt/gs)") || (device == "StratixV(GS/GT/GX)") || (device == "STRATIXV(GS/GT/GX)") || (device == "stratixv(gs/gt/gx)") || (device == "StratixV(GS/GX/GT)") || (device == "STRATIXV(GS/GX/GT)") || (device == "stratixv(gs/gx/gt)") || (device == "StratixV(GT/GS/GX)") || (device == "STRATIXV(GT/GS/GX)") || (device == "stratixv(gt/gs/gx)") || (device == "StratixV(GT/GX/GS)") || (device == "STRATIXV(GT/GX/GS)") || (device == "stratixv(gt/gx/gs)") || (device == "StratixV(GX/GS/GT)") || (device == "STRATIXV(GX/GS/GT)") || (device == "stratixv(gx/gs/gt)") || (device == "StratixV(GX/GT/GS)") || (device == "STRATIXV(GX/GT/GS)") || (device == "stratixv(gx/gt/gs)") || (device == "Stratix V (GS/GT/GX/E)") || (device == "STRATIX V (GS/GT/GX/E)") || (device == "stratix v (gs/gt/gx/e)") || (device == "StratixV(GS/GT/GX/E)") || (device == "STRATIXV(GS/GT/GX/E)") || (device == "stratixv(gs/gt/gx/e)") || (device == "Stratix V (E)") || (device == "STRATIX V (E)") || (device == "stratix v (e)") || (device == "StratixV(E)") || (device == "STRATIXV(E)") || (device == "stratixv(e)"))
|| ((device == "Stratix") || (device == "STRATIX") || (device == "stratix") || (device == "Yeager") || (device == "YEAGER") || (device == "yeager"))
|| ((device == "eFPGA 28 HPM") || (device == "EFPGA 28 HPM") || (device == "efpga 28 hpm") || (device == "eFPGA28HPM") || (device == "EFPGA28HPM") || (device == "efpga28hpm") || (device == "Bedrock") || (device == "BEDROCK") || (device == "bedrock")))
is_valid = 1;
else
is_valid = 0;
IS_VALID_FAMILY = is_valid;
end
endfunction // IS_VALID_FAMILY
endmodule // LPM_DEVICE_FAMILIES
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_constant
//
// Description : Parameterized constant generator megafunction. lpm_constant
// may be useful for convert a parameter into a constant.
//
// Limitation : n/a
//
// Results expected: Value specified by the argument to LPM_CVALUE.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_constant (
result // Value specified by the argument to LPM_CVALUE. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the result[] port. (Required)
parameter lpm_cvalue = 0; // Constant value to be driven out on the
// result[] port. (Required)
parameter lpm_strength = "UNUSED";
parameter lpm_type = "lpm_constant";
parameter lpm_hint = "UNUSED";
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg[32:0] int_value;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
int_value = lpm_cvalue;
end
// CONTINOUS ASSIGNMENT
assign result = int_value[lpm_width-1:0];
endmodule // lpm_constant
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inv
//
// Description : Parameterized inverter megafunction.
//
// Limitation : n/a
//
// Results expected: Inverted value of input data
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inv (
data, // Data input to the lpm_inv. (Required)
result // inverted result. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. (Required)
parameter lpm_type = "lpm_inv";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
result = ~data;
endmodule // lpm_inv
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_and
//
// Description : Parameterized AND gate. This megafunction takes in data inputs
// for a number of AND gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each AND gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_and (
data, // Data input to the AND gate. (Required)
result // Result of the AND operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[][] and result[] ports. Number of AND gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each AND gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_and";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b1;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] & data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_and
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_or
//
// Description : Parameterized OR gate megafunction. This megafunction takes in
// data inputs for a number of OR gates.
//
// Limitation : n/a
//
// Results expected: Each result[] bit is the result of each OR gate.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_or (
data, // Data input to the OR gates. (Required)
result // Result of OR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of OR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each OR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_or";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] | data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_or
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_xor
//
// Description : Parameterized XOR gate megafunction. This megafunction takes in
// data inputs for a number of XOR gates.
//
// Limitation : n/a.
//
// Results expected: Each result[] bit is the result of each XOR gates.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_xor (
data, // Data input to the XOR gates. (Required)
result // Result of XOR operators. (Required)
);
// GLOBAL PARAMETER DECLARATION
// Width of the data[] and result[] ports. Number of XOR gates. (Required)
parameter lpm_width = 1;
// Number of inputs to each XOR gate. Number of input buses. (Required)
parameter lpm_size = 1;
parameter lpm_type = "lpm_xor";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
// LOCAL INTEGER DECLARATION
integer i;
integer j;
integer k;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 0)
begin
$display("Value of lpm_size parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
for (i=0; i<lpm_width; i=i+1)
begin
result_tmp[i] = 1'b0;
for (j=0; j<lpm_size; j=j+1)
begin
k = (j * lpm_width) + i;
result_tmp[i] = result_tmp[i] ^ data[k];
end
end
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_xor
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bustri
//
// Description : Parameterized tri-state buffer. lpm_bustri is useful for
// controlling both unidirectional and bidirectional I/O bus
// controllers.
//
// Limitation : n/a
//
// Results expected: Belows are the three configurations which are valid:
//
// 1) Only the input ports data[LPM_WIDTH-1..0] and enabledt are
// present, and only the output ports tridata[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabledt | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | DATA[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 2) Only the input ports tridata[LPM_WIDTH-1..0] and enabletr
// are present, and only the output ports result[LPM_WIDTH-1..0]
// are present.
//
// ----------------------------------------------------
// | Input | Output |
// |====================================================|
// | enabletr | result[LPM_WIDTH-1..0] |
// |----------------------------------------------------|
// | 0 | Z |
// |----------------------------------------------------|
// | 1 | tridata[LPM_WIDTH-1..0] |
// ----------------------------------------------------
//
// 3) All ports are present: input ports data[LPM_WIDTH-1..0],
// enabledt, and enabletr; output ports result[LPM_WIDTH-1..0];
// and bidirectional ports tridata[LPM_WIDTH-1..0].
//
// ----------------------------------------------------------------------------
// | Input | Bidirectional | Output |
// |----------------------------------------------------------------------------|
// | enabledt | enabletr | tridata[LPM_WIDTH-1..0] | result[LPM_WIDTH-1..0] |
// |============================================================================|
// | 0 | 0 | Z (input) | Z |
// |----------------------------------------------------------------------------|
// | 0 | 1 | Z (input) | tridata[LPM_WIDTH-1..0] |
// |----------------------------------------------------------------------------|
// | 1 | 0 | data[LPM_WIDTH-1..0] | Z |
// |----------------------------------------------------------------------------|
// | 1 | 1 | data[LPM_WIDTH-1..0] | data[LPM_WIDTH-1..0] |
// ----------------------------------------------------------------------------
//
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bustri (
tridata, // Bidirectional bus signal. (Required)
data, // Data input to the tridata[] bus. (Required)
enabletr, // If high, enables tridata[] onto the result bus.
enabledt, // If high, enables data onto the tridata[] bus.
result // Output from the tridata[] bus.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bustri";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enabletr;
input enabledt;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] tridata;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] result;
// INTERNAL TRI DECLARATION
tri1 enabletr;
tri1 enabledt;
wire i_enabledt;
wire i_enabletr;
buf (i_enabledt, enabledt);
buf (i_enabletr, enabletr);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or tridata or i_enabletr or i_enabledt)
begin
if ((i_enabledt == 1'b0) && (i_enabletr == 1'b1))
begin
result = tridata;
end
else if ((i_enabledt == 1'b1) && (i_enabletr == 1'b1))
begin
result = data;
end
else
begin
result = {lpm_width{1'bz}};
end
end
// CONTINOUS ASSIGNMENT
assign tridata = (i_enabledt == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bustri
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_mux
//
// Description : Parameterized multiplexer megafunctions.
//
// Limitation : n/a
//
// Results expected: Selected input port.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_mux (
data, // Data input. (Required)
sel, // Selects one of the input buses. (Required)
clock, // Clock for pipelined usage
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result // Selected input port. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[][] and result[] ports. (Required)
parameter lpm_size = 2; // Number of input buses to the multiplexer. (Required)
parameter lpm_widths = 1; // Width of the sel[] input port. (Required)
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the result[] output.
parameter lpm_type = "lpm_mux";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [(lpm_size * lpm_width)-1:0] data;
input [lpm_widths-1:0] sel;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [lpm_pipeline+1:0];
reg [lpm_width-1:0] tmp_result;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_size <= 1)
begin
$display("Value of lpm_size parameter must be greater than 1 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widths <= 0)
begin
$display("Value of lpm_widths parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must NOT less than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or sel)
begin
tmp_result = 0;
if (sel < lpm_size)
begin
for (i = 0; i < lpm_width; i = i + 1)
tmp_result[i] = data[(sel * lpm_width) + i];
end
else
tmp_result = {lpm_width{1'bx}};
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
result_pipe[i] <= 1'b0;
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
endmodule // lpm_mux
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_decode
//
// Description : Parameterized decoder megafunction.
//
// Limitation : n/a
//
// Results expected: Decoded output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_decode (
data, // Data input. Treated as an unsigned binary encoded number. (Required)
enable, // Enable. All outputs low when not active.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
eq // Decoded output. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] port, or the
// input value to be decoded. (Required)
parameter lpm_decodes = 1 << lpm_width; // Number of explicit decoder outputs. (Required)
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_decode";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_decodes-1:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_decodes-1:0] eq_pipe [(lpm_pipeline+1):0];
reg [lpm_decodes-1:0] tmp_eq;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 enable;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_clock;
wire i_clken;
wire i_aclr;
wire i_enable;
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
buf (i_enable, enable);
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes <= 0)
begin
$display("Value of lpm_decodes parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_decodes > (1 << lpm_width))
begin
$display("Value of lpm_decodes parameter must be less or equal to 2^lpm_width (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Value of lpm_pipeline parameter must be greater or equal to 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_enable)
begin
tmp_eq = {lpm_decodes{1'b0}};
if (i_enable)
tmp_eq[data] = 1'b1;
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= lpm_pipeline; i = i + 1)
eq_pipe[i] <= {lpm_decodes{1'b0}};
pipe_ptr <= 0;
end
else if (clken == 1'b1)
begin
eq_pipe[pipe_ptr] <= tmp_eq;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign eq = (lpm_pipeline > 0) ? eq_pipe[pipe_ptr] : tmp_eq;
endmodule // lpm_decode
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_clshift
//
// Description : Parameterized combinatorial logic shifter or barrel shifter
// megafunction.
//
// Limitation : n/a
//
// Results expected: Return the shifted data and underflow/overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_clshift (
data, // Data to be shifted. (Required)
distance, // Number of positions to shift data[] in the direction specified
// by the direction port. (Required)
direction, // Direction of shift. Low = left (toward the MSB),
// high = right (toward the LSB).
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // Shifted data. (Required)
underflow, // Logical or arithmetic underflow.
overflow // Logical or arithmetic overflow.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports. Must be
// greater than 0 (Required)
parameter lpm_widthdist = 1; // Width of the distance[] input port. (Required)
parameter lpm_shifttype = "LOGICAL"; // Type of shifting operation to be performed.
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_clshift";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] distance;
input direction;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output underflow;
output overflow;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] ONES;
reg [lpm_width-1:0] ZEROS;
reg [lpm_width-1:0] tmp_result;
reg tmp_underflow;
reg tmp_overflow;
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] overflow_pipe;
reg [(lpm_pipeline+1):0] underflow_pipe;
// LOCAL INTEGER DECLARATION
integer i;
integer i1;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 direction;
tri0 clock;
tri0 aclr;
tri1 clken;
wire i_direction;
wire i_clock;
wire i_clken;
wire i_aclr;
buf (i_direction, direction);
buf (i_clock, clock);
buf (i_clken, clken);
buf (i_aclr, aclr);
// FUNCTON DECLARATION
// Perform logival shift operation
function [lpm_width+1:0] LogicShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if ((direction) && (shift_num > 0)) // shift right
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width)
|| ((data >> (lpm_width-shift_num)) != ZEROS)))
overflow = 1'b1;
end
LogicShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // LogicShift
// Perform Arithmetic shift operation
function [lpm_width+1:0] ArithShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
reg underflow;
reg overflow;
integer i;
integer i1;
begin
tmp_buf = data;
overflow = 1'b0;
underflow = 1'b0;
if (shift_num < lpm_width)
begin
if ((direction) && (shift_num > 0)) // shift right
begin
if (data[lpm_width-1] == 1'b0) // positive number
begin
tmp_buf = data >> shift_num;
if ((data != ZEROS) && ((shift_num >= lpm_width) || (tmp_buf == ZEROS)))
underflow = 1'b1;
end
else // negative number
begin
tmp_buf = (data >> shift_num) | (ONES << (lpm_width - shift_num));
if ((data != ONES) && ((shift_num >= lpm_width-1) || (tmp_buf == ONES)))
underflow = 1'b1;
end
end
else if (shift_num > 0) // shift left
begin
tmp_buf = data << shift_num;
for (i=lpm_width-1; i >= lpm_width-shift_num; i=i-1)
begin
if(data[i-1] != data[lpm_width-1])
overflow = 1'b1;
end
end
end
else // shift_num >= lpm_width
begin
if (direction)
begin
for (i=0; i < lpm_width; i=i+1)
tmp_buf[i] = data[lpm_width-1];
underflow = 1'b1;
end
else
begin
tmp_buf = {lpm_width{1'b0}};
if (data != ZEROS)
begin
overflow = 1'b1;
end
end
end
ArithShift = {overflow,underflow,tmp_buf[lpm_width-1:0]};
end
endfunction // ArithShift
// Perform rotate shift operation
function [lpm_width+1:0] RotateShift;
input [lpm_width-1:0] data;
input [lpm_widthdist-1:0] shift_num;
input direction;
reg [lpm_width-1:0] tmp_buf;
begin
tmp_buf = data;
if ((direction) && (shift_num > 0)) // shift right
tmp_buf = (data >> shift_num) | (data << (lpm_width - shift_num));
else if (shift_num > 0) // shift left
tmp_buf = (data << shift_num) | (data >> (lpm_width - shift_num));
RotateShift = {2'bx, tmp_buf[lpm_width-1:0]};
end
endfunction // RotateShift
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_shifttype != "LOGICAL") &&
(lpm_shifttype != "ARITHMETIC") &&
(lpm_shifttype != "ROTATE") &&
(lpm_shifttype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_SHIFTTYPE value must be \"LOGICAL\", \"ARITHMETIC\", or \"ROTATE\".");
$display("Time: %0t Instance: %m", $time);
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthdist <= 0)
begin
$display("Value of lpm_widthdist parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ONES[i] = 1'b1;
ZEROS[i] = 1'b0;
end
for (i = 0; i <= lpm_pipeline; i = i + 1)
begin
result_pipe[i] = ZEROS;
overflow_pipe[i] = 1'b0;
underflow_pipe[i] = 1'b0;
end
tmp_result = ZEROS;
tmp_underflow = 1'b0;
tmp_overflow = 1'b0;
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(data or i_direction or distance)
begin
if ((lpm_shifttype == "LOGICAL") || (lpm_shifttype == "UNUSED"))
{tmp_overflow, tmp_underflow, tmp_result} = LogicShift(data, distance, i_direction);
else if (lpm_shifttype == "ARITHMETIC")
{tmp_overflow, tmp_underflow, tmp_result} = ArithShift(data, distance, i_direction);
else if (lpm_shifttype == "ROTATE")
{tmp_overflow, tmp_underflow, tmp_result} = RotateShift(data, distance, i_direction);
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i1 = 0; i1 <= lpm_pipeline; i1 = i1 + 1)
begin
result_pipe[i1] <= {lpm_width{1'b0}};
overflow_pipe[i1] <= 1'b0;
underflow_pipe[i1] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1'b1)
begin
result_pipe[pipe_ptr] <= tmp_result;
overflow_pipe[pipe_ptr] <= tmp_overflow;
underflow_pipe[pipe_ptr] <= tmp_underflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign underflow = (lpm_pipeline > 0) ? underflow_pipe[pipe_ptr] : tmp_underflow;
endmodule // lpm_clshift
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_add_sub
//
// Description : Parameterized adder/subtractor megafunction.
//
// Limitation : n/a
//
// Results expected: If performs as adder, the result will be dataa[]+datab[]+cin.
// If performs as subtractor, the result will be dataa[]-datab[]+cin-1.
// Also returns carry out bit and overflow status bit.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_add_sub (
dataa, // Augend/Minuend
datab, // Addend/Subtrahend
cin, // Carry-in to the low-order bit.
add_sub, // If the signal is high, the operation = dataa[]+datab[]+cin.
// If the signal is low, the operation = dataa[]-datab[]+cin-1.
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
result, // dataa[]+datab[]+cin or dataa[]-datab[]+cin-1
cout, // Carry-out (borrow-in) of the MSB.
overflow // Result exceeds available precision.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[],datab[], and result[] ports.
parameter lpm_representation = "SIGNED"; // Type of addition performed
parameter lpm_direction = "UNUSED"; // Specify the operation of the lpm_add_sub function
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_add_sub";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input cin;
input add_sub;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output cout;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_pipe [(lpm_pipeline+1):0];
reg [(lpm_pipeline+1):0] cout_pipe;
reg [(lpm_pipeline+1):0] overflow_pipe;
reg tmp_cout;
reg tmp_overflow;
reg [lpm_width-1:0] tmp_result;
reg i_cin;
// LOCAL INTEGER DECLARATION
integer borrow;
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri1 i_add_sub;
tri0 i_aclr;
tri1 i_clken;
tri0 i_clock;
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "ADD") &&
(lpm_direction != "SUB") &&
(lpm_direction != "UNUSED") && // non-LPM 220 standard
(lpm_direction != "DEFAULT")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"ADD\" or \"SUB\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pipeline < 0)
begin
$display("Error! LPM_PIPELINE must be greater than or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] = 'b0;
cout_pipe[i] = 1'b0;
overflow_pipe[i] = 1'b0;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(cin or dataa or datab or i_add_sub)
begin
i_cin = 1'b0;
borrow = 1'b0;
// cout is the same for both signed and unsign representation.
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 0 : cin;
{tmp_cout, tmp_result} = dataa + datab + i_cin;
tmp_overflow = tmp_cout;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
i_cin = (cin === 1'bz) ? 1 : cin;
borrow = (~i_cin) ? 1 : 0;
{tmp_overflow, tmp_result} = dataa - datab - borrow;
tmp_cout = (dataa >= (datab+borrow))?1:0;
end
if (lpm_representation == "SIGNED")
begin
// perform the addtion or subtraction operation
if ((lpm_direction == "ADD") || ((i_add_sub == 1) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa + datab + i_cin;
tmp_overflow = ((dataa[lpm_width-1] == datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
else if ((lpm_direction == "SUB") || ((i_add_sub == 0) &&
((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) ))
begin
tmp_result = dataa - datab - borrow;
tmp_overflow = ((dataa[lpm_width-1] != datab[lpm_width-1]) &&
(dataa[lpm_width-1] != tmp_result[lpm_width-1])) ?
1 : 0;
end
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
result_pipe[i] <= {lpm_width{1'b0}};
cout_pipe[i] <= 1'b0;
overflow_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
result_pipe[pipe_ptr] <= tmp_result;
cout_pipe[pipe_ptr] <= tmp_cout;
overflow_pipe[pipe_ptr] <= tmp_overflow;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : tmp_result;
assign cout = (lpm_pipeline > 0) ? cout_pipe[pipe_ptr] : tmp_cout;
assign overflow = (lpm_pipeline > 0) ? overflow_pipe[pipe_ptr] : tmp_overflow;
assign i_clock = clock;
assign i_aclr = aclr;
assign i_clken = clken;
assign i_add_sub = add_sub;
endmodule // lpm_add_sub
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_compare
//
// Description : Parameterized comparator megafunction. The comparator will
// compare between data[] and datab[] and return the status of
// comparation for the following operation.
// 1) dataa[] < datab[].
// 2) dataa[] == datab[].
// 3) dataa[] > datab[].
// 4) dataa[] >= datab[].
// 5) dataa[] != datab[].
// 6) dataa[] <= datab[].
//
// Limitation : n/a
//
// Results expected: Return status bits of the comparision between dataa[] and
// datab[].
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_compare (
dataa, // Value to be compared to datab[]. (Required)
datab, // Value to be compared to dataa[]. (Required)
clock, // Clock for pipelined usage.
aclr, // Asynchronous clear for pipelined usage.
clken, // Clock enable for pipelined usage.
// One of the following ports must be present.
alb, // High (1) if dataa[] < datab[].
aeb, // High (1) if dataa[] == datab[].
agb, // High (1) if dataa[] > datab[].
aleb, // High (1) if dataa[] <= datab[].
aneb, // High (1) if dataa[] != datab[].
ageb // High (1) if dataa[] >= datab[].
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the dataa[] and datab[] ports. (Required)
parameter lpm_representation = "UNSIGNED"; // Type of comparison performed:
// "SIGNED", "UNSIGNED"
parameter lpm_pipeline = 0; // Specifies the number of Clock cycles of latency
// associated with the alb, aeb, agb, ageb, aleb,
// or aneb output.
parameter lpm_type = "lpm_compare";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] dataa;
input [lpm_width-1:0] datab;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output alb;
output aeb;
output agb;
output aleb;
output aneb;
output ageb;
// INTERNAL REGISTERS DECLARATION
reg [lpm_pipeline+1:0] alb_pipe;
reg [lpm_pipeline+1:0] aeb_pipe;
reg [lpm_pipeline+1:0] agb_pipe;
reg [lpm_pipeline+1:0] aleb_pipe;
reg [lpm_pipeline+1:0] aneb_pipe;
reg [lpm_pipeline+1:0] ageb_pipe;
reg tmp_alb;
reg tmp_aeb;
reg tmp_agb;
reg tmp_aleb;
reg tmp_aneb;
reg tmp_ageb;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_representation != "SIGNED") &&
(lpm_representation != "UNSIGNED"))
begin
$display("Error! LPM_REPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
// get the status of comparison
always @(dataa or datab)
begin
tmp_aeb = (dataa == datab);
tmp_aneb = (dataa != datab);
if ((lpm_representation == "SIGNED") &&
((dataa[lpm_width-1] ^ datab[lpm_width-1]) == 1))
begin
// create latency
tmp_alb = (dataa > datab);
tmp_agb = (dataa < datab);
tmp_aleb = (dataa >= datab);
tmp_ageb = (dataa <= datab);
end
else
begin
// create latency
tmp_alb = (dataa < datab);
tmp_agb = (dataa > datab);
tmp_aleb = (dataa <= datab);
tmp_ageb = (dataa >= datab);
end
end
// pipelining process
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr) // reset all variables
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
begin
aeb_pipe[i] <= 1'b0;
agb_pipe[i] <= 1'b0;
alb_pipe[i] <= 1'b0;
aleb_pipe[i] <= 1'b0;
aneb_pipe[i] <= 1'b0;
ageb_pipe[i] <= 1'b0;
end
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
alb_pipe[pipe_ptr] <= tmp_alb;
aeb_pipe[pipe_ptr] <= tmp_aeb;
agb_pipe[pipe_ptr] <= tmp_agb;
aleb_pipe[pipe_ptr] <= tmp_aleb;
aneb_pipe[pipe_ptr] <= tmp_aneb;
ageb_pipe[pipe_ptr] <= tmp_ageb;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign alb = (lpm_pipeline > 0) ? alb_pipe[pipe_ptr] : tmp_alb;
assign aeb = (lpm_pipeline > 0) ? aeb_pipe[pipe_ptr] : tmp_aeb;
assign agb = (lpm_pipeline > 0) ? agb_pipe[pipe_ptr] : tmp_agb;
assign aleb = (lpm_pipeline > 0) ? aleb_pipe[pipe_ptr] : tmp_aleb;
assign aneb = (lpm_pipeline > 0) ? aneb_pipe[pipe_ptr] : tmp_aneb;
assign ageb = (lpm_pipeline > 0) ? ageb_pipe[pipe_ptr] : tmp_ageb;
endmodule // lpm_compare
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_mult
//
// Description : Parameterized multiplier megafunction.
//
// Limitation : n/a
//
// Results expected: dataa[] * datab[] + sum[].
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_mult (
dataa, // Multiplicand. (Required)
datab, // Multiplier. (Required)
sum, // Partial sum.
aclr, // Asynchronous clear for pipelined usage.
clock, // Clock for pipelined usage.
clken, // Clock enable for pipelined usage.
result // result = dataa[] * datab[] + sum. The product LSB is aligned with the sum LSB.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widtha = 1; // Width of the dataa[] port. (Required)
parameter lpm_widthb = 1; // Width of the datab[] port. (Required)
parameter lpm_widthp = 1; // Width of the result[] port. (Required)
parameter lpm_widths = 1; // Width of the sum[] port. (Required)
parameter lpm_representation = "UNSIGNED"; // Type of multiplication performed
parameter lpm_pipeline = 0; // Number of clock cycles of latency
parameter lpm_type = "lpm_mult";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_widtha-1:0] dataa;
input [lpm_widthb-1:0] datab;
input [lpm_widths-1:0] sum;
input aclr;
input clock;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthp-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthp-1:0] result_pipe [lpm_pipeline+1:0];
reg [lpm_widthp-1:0] i_prod;
reg [lpm_widthp-1:0] t_p;
reg [lpm_widths-1:0] i_prod_s;
reg [lpm_widths-1:0] t_s;
reg [lpm_widtha+lpm_widthb-1:0] i_prod_ab;
reg [lpm_widtha-1:0] t_a;
reg [lpm_widthb-1:0] t_b;
reg sign_ab;
reg sign_s;
reg [8*5:1] input_a_is_constant;
reg [8*5:1] input_b_is_constant;
reg [8*lpm_widtha:1] input_a_fixed_value;
reg [8*lpm_widthb:1] input_b_fixed_value;
reg [lpm_widtha-1:0] dataa_fixed;
reg [lpm_widthb-1:0] datab_fixed;
// LOCAL INTEGER DECLARATION
integer i;
integer pipe_ptr;
// INTERNAL WIRE DECLARATION
wire [lpm_widtha-1:0] dataa_wire;
wire [lpm_widthb-1:0] datab_wire;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// FUNCTION DECLARATION
// convert string to binary bits.
function integer str2bin;
input [8*256:1] str;
input str_width;
reg [8*256:1] reg_str;
reg [255:0] bin;
reg [8:1] tmp;
integer m;
integer str_width;
begin
reg_str = str;
for (m=0; m < str_width; m=m+1)
begin
tmp = reg_str[8:1];
reg_str = reg_str >> 8;
case (tmp)
"0" : bin[m] = 1'b0;
"1" : bin[m] = 1'b1;
default: bin[m] = 1'bx;
endcase
end
str2bin = bin;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widtha > 0
if (lpm_widtha <= 0)
begin
$display("Error! lpm_widtha must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthb > 0
if (lpm_widthb <= 0)
begin
$display("Error! lpm_widthb must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthp > 0
if (lpm_widthp <= 0)
begin
$display("Error! lpm_widthp must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthp > 0
if (lpm_widths <= 0)
begin
$display("Error! lpm_widths must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_rep value
if ((lpm_representation != "SIGNED") && (lpm_representation != "UNSIGNED"))
begin
$display("Error! lpm_representation value must be \"SIGNED\" or \"UNSIGNED\".", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
input_a_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_IS_CONSTANT");
if (input_a_is_constant == "FIXED")
begin
input_a_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_A_FIXED_VALUE");
dataa_fixed = str2bin(input_a_fixed_value, lpm_widtha);
end
input_b_is_constant = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_IS_CONSTANT");
if (input_b_is_constant == "FIXED")
begin
input_b_fixed_value = eva.GET_PARAMETER_VALUE(lpm_hint, "INPUT_B_FIXED_VALUE");
datab_fixed = str2bin(input_b_fixed_value, lpm_widthb);
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(dataa_wire or datab_wire or sum)
begin
t_a = dataa_wire;
t_b = datab_wire;
t_s = sum;
sign_ab = 1'b0;
sign_s = 1'b0;
// if inputs are sign number
if (lpm_representation == "SIGNED")
begin
sign_ab = dataa_wire[lpm_widtha-1] ^ datab_wire[lpm_widthb-1];
sign_s = sum[lpm_widths-1];
// if negative number, represent them as 2 compliment number.
if (dataa_wire[lpm_widtha-1] == 1)
t_a = (~dataa_wire) + 1;
if (datab_wire[lpm_widthb-1] == 1)
t_b = (~datab_wire) + 1;
if (sum[lpm_widths-1] == 1)
t_s = (~sum) + 1;
end
// if sum port is not used
if (sum === {lpm_widths{1'bz}})
begin
t_s = {lpm_widths{1'b0}};
sign_s = 1'b0;
end
if (sign_ab == sign_s)
begin
i_prod = (t_a * t_b) + t_s;
i_prod_s = (t_a * t_b) + t_s;
i_prod_ab = (t_a * t_b) + t_s;
end
else
begin
i_prod = (t_a * t_b) - t_s;
i_prod_s = (t_a * t_b) - t_s;
i_prod_ab = (t_a * t_b) - t_s;
end
// if dataa[] * datab[] produces negative number, compliment the result
if (sign_ab)
begin
i_prod = (~i_prod) + 1;
i_prod_s = (~i_prod_s) + 1;
i_prod_ab = (~i_prod_ab) + 1;
end
if ((lpm_widthp < lpm_widths) || (lpm_widthp < (lpm_widtha+lpm_widthb)))
for (i = 0; i < lpm_widthp; i = i + 1)
i_prod[lpm_widthp-1-i] = (lpm_widths > lpm_widtha+lpm_widthb)
? i_prod_s[lpm_widths-1-i]
: i_prod_ab[lpm_widtha+lpm_widthb-1-i];
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr) // clear the pipeline for result to 0
begin
for (i = 0; i <= (lpm_pipeline + 1); i = i + 1)
result_pipe[i] <= {lpm_widthp{1'b0}};
pipe_ptr <= 0;
end
else if (i_clken == 1)
begin
result_pipe[pipe_ptr] <= i_prod;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign dataa_wire = (input_a_is_constant == "FIXED") ? dataa_fixed : dataa;
assign datab_wire = (input_b_is_constant == "FIXED") ? datab_fixed : datab;
assign result = (lpm_pipeline > 0) ? result_pipe[pipe_ptr] : i_prod;
endmodule // lpm_mult
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_divide
//
// Description : Parameterized divider megafunction. This function performs a
// divide operation such that denom * quotient + remain = numer
// The function allows for all combinations of signed(two's
// complement) and unsigned inputs. If any of the inputs is
// signed, the output is signed. Otherwise the output is unsigned.
// The function also allows the remainder to be specified as
// always positive (in which case remain >= 0); otherwise remain
// is zero or the same sign as the numerator
// (this parameter is ignored in the case of purely unsigned
// division). Finally the function is also pipelinable.
//
// Limitation : n/a
//
// Results expected: Return quotient and remainder.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_divide (
numer, // The numerator (Required)
denom, // The denominator (Required)
clock, // Clock input for pipelined usage
aclr, // Asynchronous clear signal
clken, // Clock enable for pipelined usage.
quotient, // Quotient (Required)
remain // Remainder (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthn = 1; // Width of the numer[] and quotient[] port. (Required)
parameter lpm_widthd = 1; // Width of the denom[] and remain[] port. (Required)
parameter lpm_nrepresentation = "UNSIGNED"; // The representation of numer
parameter lpm_drepresentation = "UNSIGNED"; // The representation of denom
parameter lpm_pipeline = 0; // Number of Clock cycles of latency
parameter lpm_type = "lpm_divide";
parameter lpm_hint = "LPM_REMAINDERPOSITIVE=TRUE";
// INPUT PORT DECLARATION
input [lpm_widthn-1:0] numer;
input [lpm_widthd-1:0] denom;
input clock;
input aclr;
input clken;
// OUTPUT PORT DECLARATION
output [lpm_widthn-1:0] quotient;
output [lpm_widthd-1:0] remain;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_widthn-1:0] quotient_pipe [lpm_pipeline+1:0];
reg [lpm_widthd-1:0] remain_pipe [lpm_pipeline+1:0];
reg [lpm_widthn-1:0] tmp_quotient;
reg [lpm_widthd-1:0] tmp_remain;
reg [lpm_widthn-1:0] not_numer;
reg [lpm_widthn-1:0] int_numer;
reg [lpm_widthd-1:0] not_denom;
reg [lpm_widthd-1:0] int_denom;
reg [lpm_widthn-1:0] t_numer;
reg [lpm_widthn-1:0] t_q;
reg [lpm_widthd-1:0] t_denom;
reg [lpm_widthd-1:0] t_r;
reg sign_q;
reg sign_r;
reg sign_n;
reg sign_d;
reg [8*5:1] lpm_remainderpositive;
// LOCAL INTEGER DECLARATION
integer i;
integer rsig;
integer pipe_ptr;
// INTERNAL TRI DECLARATION
tri0 aclr;
tri0 clock;
tri1 clken;
wire i_aclr;
wire i_clock;
wire i_clken;
buf (i_aclr, aclr);
buf (i_clock, clock);
buf (i_clken, clken);
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
// check if lpm_widthn > 0
if (lpm_widthn <= 0)
begin
$display("Error! LPM_WIDTHN must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_widthd > 0
if (lpm_widthd <= 0)
begin
$display("Error! LPM_WIDTHD must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_nrepresentation value
if ((lpm_nrepresentation != "SIGNED") && (lpm_nrepresentation != "UNSIGNED"))
begin
$display("Error! LPM_NREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_drepresentation value
if ((lpm_drepresentation != "SIGNED") && (lpm_drepresentation != "UNSIGNED"))
begin
$display("Error! LPM_DREPRESENTATION value must be \"SIGNED\" or \"UNSIGNED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for valid lpm_remainderpositive value
lpm_remainderpositive = eva.GET_PARAMETER_VALUE(lpm_hint, "LPM_REMAINDERPOSITIVE");
if ((lpm_remainderpositive == "TRUE") &&
(lpm_remainderpositive == "FALSE"))
begin
$display("Error! LPM_REMAINDERPOSITIVE value must be \"TRUE\" or \"FALSE\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr = 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(numer or denom or lpm_remainderpositive)
begin
sign_q = 1'b0;
sign_r = 1'b0;
sign_n = 1'b0;
sign_d = 1'b0;
t_numer = numer;
t_denom = denom;
if (lpm_nrepresentation == "SIGNED")
if (numer[lpm_widthn-1] == 1'b1)
begin
t_numer = ~numer + 1; // numer is negative number
sign_n = 1'b1;
end
if (lpm_drepresentation == "SIGNED")
if (denom[lpm_widthd-1] == 1'b1)
begin
t_denom = ~denom + 1; // denom is negative numbrt
sign_d = 1'b1;
end
t_q = t_numer / t_denom; // get quotient
t_r = t_numer % t_denom; // get remainder
sign_q = sign_n ^ sign_d;
sign_r = (t_r != {lpm_widthd{1'b0}}) ? sign_n : 1'b0;
// Pipeline the result
tmp_quotient = (sign_q == 1'b1) ? (~t_q + 1) : t_q;
tmp_remain = (sign_r == 1'b1) ? (~t_r + 1) : t_r;
// Recalculate the quotient and remainder if remainder is negative number
// and LPM_REMAINDERPOSITIVE=TRUE.
if ((sign_r) && (lpm_remainderpositive == "TRUE"))
begin
tmp_quotient = tmp_quotient + ((sign_d == 1'b1) ? 1 : -1 );
tmp_remain = tmp_remain + t_denom;
end
end
always @(posedge i_clock or posedge i_aclr)
begin
if (i_aclr)
begin
for (i = 0; i <= (lpm_pipeline+1); i = i + 1)
begin
quotient_pipe[i] <= {lpm_widthn{1'b0}};
remain_pipe[i] <= {lpm_widthd{1'b0}};
end
pipe_ptr <= 0;
end
else if (i_clken)
begin
quotient_pipe[pipe_ptr] <= tmp_quotient;
remain_pipe[pipe_ptr] <= tmp_remain;
if (lpm_pipeline > 1)
pipe_ptr <= (pipe_ptr + 1) % lpm_pipeline;
end
end
// CONTINOUS ASSIGNMENT
assign quotient = (lpm_pipeline > 0) ? quotient_pipe[pipe_ptr] : tmp_quotient;
assign remain = (lpm_pipeline > 0) ? remain_pipe[pipe_ptr] : tmp_remain;
endmodule // lpm_divide
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_abs
//
// Description : Parameterized absolute value megafunction. This megafunction
// requires the input data to be signed number.
//
// Limitation : n/a
//
// Results expected: Return absolute value of data and the overflow status
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_abs (
data, // Signed number (Required)
result, // Absolute value of data[].
overflow // High if data = -2 ^ (LPM_WIDTH-1).
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and result[] ports.(Required)
parameter lpm_type = "lpm_abs";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
output overflow;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result_tmp;
reg overflow;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
result_tmp = (data[lpm_width-1] == 1) ? (~data) + 1 : data;
overflow = (data[lpm_width-1] == 1) ? (result_tmp == (1<<(lpm_width-1))) : 0;
end
// CONTINOUS ASSIGNMENT
assign result = result_tmp;
endmodule // lpm_abs
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_counter
//
// Description : Parameterized counter megafunction. The lpm_counter
// megafunction is a binary counter that features an up,
// down, or up/down counter with optional synchronous or
// asynchronous clear, set, and load ports.
//
// Limitation : n/a
//
// Results expected: Data output from the counter and carry-out of the MSB.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_counter (
clock, // Positive-edge-triggered clock. (Required)
clk_en, // Clock enable input. Enables all synchronous activities.
cnt_en, // Count enable input. Disables the count when low (0) without
// affecting sload, sset, or sclr.
updown, // Controls the direction of the count. High (1) = count up.
// Low (0) = count down.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the counter with
// the value on the data input.
sclr, // Synchronous clear input. Clears the counter on the next active
// clock edge.
sset, // Synchronous set input. Sets the counter on the next active clock edge.
sload, // Synchronous load input. Loads the counter with data[] on the next
// active clock edge.
data, // Parallel data input to the counter.
cin, // Carry-in to the low-order bit.
q, // Data output from the counter.
cout, // Carry-out of the MSB.
eq // Counter decode output. Active high when the counter reaches the specified
// count value.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; //The number of bits in the count, or the width of the q[]
// and data[] ports, if they are used. (Required)
parameter lpm_direction = "UNUSED"; // Direction of the count.
parameter lpm_modulus = 0; // The maximum count, plus one.
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_port_updown = "PORT_CONNECTIVITY";
parameter lpm_type = "lpm_counter";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input clock;
input clk_en;
input cnt_en;
input updown;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload;
input [lpm_width-1:0] data;
input cin;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output cout;
output [15:0] eq;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_count;
reg [lpm_width-1:0] adata;
reg use_adata;
reg tmp_updown;
reg [lpm_width:0] tmp_modulus;
reg [lpm_width:0] max_modulus;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire w_updown;
wire [lpm_width-1:0] final_count;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 clk_en;
tri1 cnt_en;
tri0 aclr;
tri0 aset;
tri0 aload;
tri0 sclr;
tri0 sset;
tri0 sload;
tri1 cin;
tri1 updown_z;
wire i_clk_en;
wire i_cnt_en;
wire i_aclr;
wire i_aset;
wire i_aload;
wire i_sclr;
wire i_sset;
wire i_sload;
wire i_cin;
wire i_updown;
buf (i_clk_en, clk_en);
buf (i_cnt_en, cnt_en);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_aload, aload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_sload, sload);
buf (i_cin, cin);
buf (i_updown, updown_z);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
max_modulus = 1 << lpm_width;
// check if lpm_width < 0
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH must be greater than 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus < 0
if (lpm_modulus < 0)
begin
$display("Error! LPM_MODULUS must be greater or equal to 0.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check if lpm_modulus > 1<<lpm_width
if (lpm_modulus > max_modulus)
begin
$display("Warning! LPM_MODULUS should be within 1 to 2^LPM_WIDTH. Assuming no modulus input.\n");
$display ("Time: %0t Instance: %m", $time);
end
// check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") &&
(lpm_direction != "UP") && (lpm_direction != "DOWN"))
begin
$display("Error! LPM_DIRECTION must be \"UP\" or \"DOWN\" if used.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_modulus = ((lpm_modulus == 0) || (lpm_modulus > max_modulus))
? max_modulus : lpm_modulus;
tmp_count = pvalue;
use_adata = 1'b0;
end
// NCSIM will only assigns 1'bZ to unconnected port at time 0fs + 1
initial #0
begin
// // check if lpm_direction valid
if ((lpm_direction != "UNUSED") && (lpm_direction != "DEFAULT") && (updown !== 1'bz) &&
(lpm_port_updown == "PORT_CONNECTIVITY"))
begin
$display("Error! LPM_DIRECTION and UPDOWN cannot be used at the same time.\n");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin
if (i_clk_en)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_count <= 0;
else if (i_sset)
tmp_count <= svalue;
else if (i_sload)
tmp_count <= data;
else if (i_cnt_en && i_cin)
begin
if (w_updown)
tmp_count <= (final_count == tmp_modulus-1) ? 0
: final_count+1;
else
tmp_count <= (final_count == 0) ? tmp_modulus-1
: final_count-1;
end
else
tmp_count <= final_count;
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue)
begin
if (i_aclr)
begin
adata <= 0;
end
else if (i_aset)
begin
adata <= avalue;
end
else if (i_aload)
adata <= data;
end
// CONTINOUS ASSIGNMENT
assign q = final_count;
assign final_count = (use_adata == 1'b1) ? adata : tmp_count;
assign cout = (i_cin && (((w_updown==0) && (final_count==0)) ||
((w_updown==1) && ((final_count==tmp_modulus-1) ||
(final_count=={lpm_width{1'b1}}))) ))
? 1'b1 : 1'b0;
assign updown_z = updown;
assign w_updown = (lpm_port_updown == "PORT_USED") ? i_updown :
(lpm_port_updown == "PORT_UNUSED") ? ((lpm_direction == "DOWN") ? 1'b0 : 1'b1) :
((((lpm_direction == "UNUSED") || (lpm_direction == "DEFAULT")) && (i_updown == 1)) ||
(lpm_direction == "UP"))
? 1'b1 : 1'b0;
assign eq = {16{1'b0}};
endmodule // lpm_counter
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_latch
//
// Description : Parameterized latch megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the latch.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_latch (
data, // Data input to the latch.
gate, // Latch enable input. High = flow-through, low = latch. (Required)
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aconst,
q // Data output from the latch.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_latch";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input gate;
input aclr;
input aset;
input aconst;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] q;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL TRI DECLARATION
tri0 [lpm_width-1:0] data;
tri0 aclr;
tri0 aset;
tri0 aconst;
wire i_aclr;
wire i_aset;
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_pvalue != "UNUSED")
begin
string_to_reg(lpm_pvalue, pvalue);
q = pvalue;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
end
// ALWAYS CONSTRUCT BLOCK
always @(data or gate or i_aclr or i_aset or avalue)
begin
if (i_aclr)
q <= {lpm_width{1'b0}};
else if (i_aset)
q <= avalue;
else if (gate)
q <= data;
end
endmodule // lpm_latch
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ff
//
// Description : Parameterized flipflop megafunction. The lpm_ff function
// contains features that are not available in the DFF, DFFE,
// DFFEA, TFF, and TFFE primitives, such as synchronous or
// asynchronous set, clear, and load inputs.
//
// Limitation : n/a
//
// Results expected: Data output from D or T flipflops.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ff (
data, // T-type flipflop: Toggle enable
// D-type flipflop: Data input
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
aload, // Asynchronous load input. Asynchronously loads the flipflop with
// the value on the data input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
sload, // Synchronous load input. Loads the flipflop with the value on the
// data input on the next active clock edge.
q // Data output from D or T flipflops. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_fftype = "DFF"; // Type of flipflop
parameter lpm_type = "lpm_ff";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input aclr;
input aset;
input aload;
input sclr;
input sset;
input sload ;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] adata;
reg use_adata;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] final_q;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri1 [lpm_width-1:0] data;
tri1 enable;
tri0 sload;
tri0 sclr;
tri0 sset;
tri0 aload;
tri0 aclr;
tri0 aset;
wire i_enable;
wire i_sload;
wire i_sclr;
wire i_sset;
wire i_aload;
wire i_aclr;
wire i_aset;
buf (i_enable, enable);
buf (i_sload, sload);
buf (i_sclr, sclr);
buf (i_sset, sset);
buf (i_aload, aload);
buf (i_aclr, aclr);
buf (i_aset, aset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_fftype != "DFF") &&
(lpm_fftype != "TFF") &&
(lpm_fftype != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_FFTYPE value must be \"DFF\" or \"TFF\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
use_adata = 1'b0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_aclr or posedge i_aset or posedge i_aload or posedge clock)
begin // Asynchronous process
if (i_aclr || i_aset || i_aload)
use_adata <= 1'b1;
else if ($time > 0)
begin // Synchronous process
if (i_enable)
begin
use_adata <= 1'b0;
if (i_sclr)
tmp_q <= 0;
else if (i_sset)
tmp_q <= svalue;
else if (i_sload) // Load data
tmp_q <= data;
else
begin
if (lpm_fftype == "TFF") // toggle
begin
for (i = 0; i < lpm_width; i=i+1)
if (data[i] == 1'b1)
tmp_q[i] <= ~final_q[i];
else
tmp_q[i] <= final_q[i];
end
else // DFF, load data
tmp_q <= data;
end
end
end
end
always @(i_aclr or i_aset or i_aload or data or avalue or pvalue)
begin
if (i_aclr === 1'b1)
adata <= {lpm_width{1'b0}};
else if (i_aclr === 1'bx)
adata <= {lpm_width{1'bx}};
else if (i_aset)
adata <= avalue;
else if (i_aload)
adata <= data;
else if ((i_aclr === 1'b0) && ($time == 0))
adata <= pvalue;
end
// CONTINOUS ASSIGNMENT
assign q = final_q;
assign final_q = (use_adata == 1'b1) ? adata : tmp_q;
endmodule // lpm_ff
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_shiftreg
//
// Description : Parameterized shift register megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the shift register and the Serial shift data output.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_shiftreg (
data, // Data input to the shift register.
clock, // Positive-edge-triggered clock. (Required)
enable, // Clock enable input
shiftin, // Serial shift data input.
load, // Synchronous parallel load. High (1): load operation;
// low (0): shift operation.
aclr, // Asynchronous clear input.
aset, // Asynchronous set input.
sclr, // Synchronous clear input.
sset, // Synchronous set input.
q, // Data output from the shift register.
shiftout // Serial shift data output.
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q ports. (Required)
parameter lpm_direction = "LEFT"; // Values are "LEFT", "RIGHT", and "UNUSED".
parameter lpm_avalue = "UNUSED"; // Constant value that is loaded when aset is high.
parameter lpm_svalue = "UNUSED"; // Constant value that is loaded on the rising edge
// of clock when sset is high.
parameter lpm_pvalue = "UNUSED";
parameter lpm_type = "lpm_shiftreg";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input enable;
input shiftin;
input load;
input aclr;
input aset;
input sclr;
input sset;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output shiftout;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] tmp_q;
reg abit;
reg [lpm_width-1:0] svalue;
reg [lpm_width-1:0] avalue;
reg [lpm_width-1:0] pvalue;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL WIRE DECLARATION
wire tmp_shiftout;
// INTERNAL TRI DECLARATION
tri1 enable;
tri1 shiftin;
tri0 load;
tri0 aclr;
tri0 aset;
tri0 sclr;
tri0 sset;
wire i_enable;
wire i_shiftin;
wire i_load;
wire i_aclr;
wire i_aset;
wire i_sclr;
wire i_sset;
buf (i_enable, enable);
buf (i_shiftin, shiftin);
buf (i_load, load);
buf (i_aclr, aclr);
buf (i_aset, aset);
buf (i_sclr, sclr);
buf (i_sset, sset);
// TASK DECLARATION
task string_to_reg;
input [8*40:1] string_value;
output [lpm_width-1:0] value;
reg [8*40:1] reg_s;
reg [8:1] digit;
reg [8:1] tmp;
reg [lpm_width-1:0] ivalue;
integer m;
begin
ivalue = {lpm_width{1'b0}};
reg_s = string_value;
for (m=1; m<=40; m=m+1)
begin
tmp = reg_s[320:313];
digit = tmp & 8'b00001111;
reg_s = reg_s << 8;
ivalue = ivalue * 10 + digit;
end
value = ivalue;
end
endtask
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0 (ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_direction != "LEFT") &&
(lpm_direction != "RIGHT") &&
(lpm_direction != "UNUSED")) // non-LPM 220 standard
begin
$display("Error! LPM_DIRECTION value must be \"LEFT\" or \"RIGHT\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_avalue == "UNUSED")
avalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_avalue, avalue);
if (lpm_svalue == "UNUSED")
svalue = {lpm_width{1'b1}};
else
string_to_reg(lpm_svalue, svalue);
if (lpm_pvalue == "UNUSED")
pvalue = {lpm_width{1'b0}};
else
string_to_reg(lpm_pvalue, pvalue);
tmp_q = pvalue;
end
// ALWAYS CONSTRUCT BLOCK
always @(i_aclr or i_aset or avalue)
begin
if (i_aclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
end
always @(posedge clock)
begin
if (i_aclr)
tmp_q <= (i_aset) ? {lpm_width{1'bx}} : {lpm_width{1'b0}};
else if (i_aset)
tmp_q <= avalue;
else
begin
if (i_enable)
begin
if (i_sclr)
tmp_q <= {lpm_width{1'b0}};
else if (i_sset)
tmp_q <= svalue;
else if (i_load)
tmp_q <= data;
else if (!i_load)
begin
if ((lpm_direction == "LEFT") || (lpm_direction == "UNUSED"))
{abit,tmp_q} <= {tmp_q,i_shiftin};
else if (lpm_direction == "RIGHT")
{tmp_q,abit} <= {i_shiftin,tmp_q};
end
end
end
end
// CONTINOUS ASSIGNMENT
assign tmp_shiftout = (lpm_direction == "RIGHT") ? tmp_q[0]
: tmp_q[lpm_width-1];
assign q = tmp_q;
assign shiftout = tmp_shiftout;
endmodule // lpm_shiftreg
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dq
//
// Description : Parameterized RAM with separate input and output ports megafunction.
// lpm_ram_dq implement asynchronous memory or memory with synchronous
// inputs and/or outputs.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dq (
data, // Data input to the memory. (Required)
address, // Address input to the memory. (Required)
inclock, // Synchronizes memory loading.
outclock, // Synchronizes q outputs from memory.
we, // Write enable input. Enables write operations to the memory when high. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the address port. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Controls whether the data port is registered.
parameter lpm_address_control = "REGISTERED"; // Controls whether the address and we ports are registered.
parameter lpm_outdata = "REGISTERED"; // Controls whether the q ports are registered.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dq";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input we;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdata;
reg [lpm_width-1:0] in_data;
reg [lpm_widthad-1:0] paddress;
reg pwe;
reg [lpm_width-1:0] ZEROS, ONES, UNKNOWN;
reg [8*256:1] ram_initf;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
wire i_inclock;
wire i_outclock;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize the internal data register.
pdata = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
pwe = 1'b0;
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad)) ||
(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i=0; i < lpm_width; i=i+1)
begin
ZEROS[i] = 1'b0;
ONES[i] = 1'b1;
UNKNOWN[i] = 1'bX;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
tmp_q = ZEROS;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
begin
if ((we) && (use_eab != "ON") &&
(lpm_hint != "USE_EAB=ON"))
begin
if (lpm_indata == "REGISTERED")
mem_data[address] <= data;
else
mem_data[address] <= pdata;
end
paddress <= address;
pwe <= we;
end
if (lpm_indata == "REGISTERED")
pdata <= data;
end
always @(data)
begin
if (lpm_indata == "UNREGISTERED")
pdata <= data;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(pdata or paddress or pwe)
begin :UNREGISTERED_INCLOCK
if (ValidAddress(paddress))
begin
if ((lpm_address_control == "UNREGISTERED") && (pwe))
mem_data[paddress] <= pdata;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(paddress))
tmp_q <= mem_data[paddress];
else
tmp_q <= {lpm_width{1'bx}};
end
end
always @(i_inclock or pwe or paddress or pdata)
begin
if ((lpm_address_control == "REGISTERED") && (pwe))
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
if (i_inclock == 1'b0)
mem_data[paddress] = pdata;
end
end
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "UNREGISTERED") ? mem_data[paddress] : tmp_q;
endmodule // lpm_ram_dq
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_dp
//
// Description : Parameterized dual-port RAM megafunction.
//
// Limitation : n/a
//
// Results expected: Data output from the memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_dp (
data, // Data input to the memory. (Required)
rdaddress, // Read address input to the memory. (Required)
wraddress, // Write address input to the memory. (Required)
rdclock, // Positive-edge-triggered clock for read operation.
rdclken, // Clock enable for rdclock.
wrclock, // Positive-edge-triggered clock for write operation.
wrclken, // Clock enable for wrclock.
rden, // Read enable input. Disables reading when low (0).
wren, // Write enable input. (Required)
q // Data output from the memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the data[] and q[] ports. (Required)
parameter lpm_widthad = 1; // Width of the rdaddress[] and wraddress[] ports. (Required)
parameter lpm_numwords = 1 << lpm_widthad; // Number of words stored in memory.
parameter lpm_indata = "REGISTERED"; // Determines the clock used by the data port.
parameter lpm_rdaddress_control = "REGISTERED"; // Determines the clock used by the rdaddress and rden ports.
parameter lpm_wraddress_control = "REGISTERED"; // Determines the clock used by the wraddress and wren ports.
parameter lpm_outdata = "REGISTERED"; // Determines the clock used by the q[] pxort.
parameter lpm_file = "UNUSED"; // Name of the file containing RAM initialization data.
parameter use_eab = "ON"; // Specified whether to use the EAB or not.
parameter rden_used = "TRUE"; // Specified whether to use the rden port or not.
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_ram_dp";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input [lpm_widthad-1:0] rdaddress;
input [lpm_widthad-1:0] wraddress;
input rdclock;
input rdclken;
input wrclock;
input wrclken;
input rden;
input wren;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthad)-1:0];
reg [lpm_width-1:0] i_data_reg, i_data_tmp, i_q_reg, i_q_tmp;
reg [lpm_widthad-1:0] i_wraddress_reg, i_wraddress_tmp;
reg [lpm_widthad-1:0] i_rdaddress_reg, i_rdaddress_tmp;
reg i_wren_reg, i_wren_tmp, i_rden_reg, i_rden_tmp;
reg [8*256:1] ram_initf;
// LOCAL INTEGER DECLARATION
integer i, i_numwords;
// INTERNAL TRI DECLARATION
tri0 wrclock;
tri1 wrclken;
tri0 rdclock;
tri1 rdclken;
tri0 wren;
tri1 rden;
wire i_inclock;
wire i_inclocken;
wire i_outclock;
wire i_outclocken;
wire i_wren;
wire i_rden;
buf (i_inclock, wrclock);
buf (i_inclocken, wrclken);
buf (i_outclock, rdclock);
buf (i_outclocken, rdclken);
buf (i_wren, wren);
buf (i_rden, rden);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error! Invalid address.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error! Address out of bound on RAM.\n", $time);
$display("Time: %0t Instance: %m", $time);
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Check for invalid parameters
if (lpm_width < 1)
begin
$display("Error! lpm_width parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad < 1)
begin
$display("Error! lpm_widthad parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! lpm_indata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! lpm_outdata must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_wraddress_control != "REGISTERED") && (lpm_wraddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_wraddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
end
if ((lpm_rdaddress_control != "REGISTERED") && (lpm_rdaddress_control != "UNREGISTERED"))
begin
$display("Error! lpm_rdaddress_control must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
// Initialize mem_data
i_numwords = (lpm_numwords) ? lpm_numwords : (1<<lpm_widthad);
if (lpm_file == "UNUSED")
for (i=0; i<i_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
// Initialize registers
i_data_reg = {lpm_width{1'b0}};
i_wraddress_reg = {lpm_widthad{1'b0}};
i_rdaddress_reg = {lpm_widthad{1'b0}};
i_wren_reg = 1'b0;
if (rden_used == "TRUE")
i_rden_reg = 1'b0;
else
i_rden_reg = 1'b1;
// Initialize output
i_q_reg = {lpm_width{1'b0}};
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
begin
i_q_tmp = {lpm_width{1'b1}};
end
else
i_q_tmp = {lpm_width{1'b0}};
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
i_data_reg <= data;
if (lpm_wraddress_control == "REGISTERED")
if ((i_inclocken == 1'b1) && ($time > 0))
begin
i_wraddress_reg <= wraddress;
i_wren_reg <= i_wren;
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_q_reg <= i_q_tmp;
end
if (lpm_rdaddress_control == "REGISTERED")
if ((i_outclocken == 1'b1) && ($time > 0))
begin
i_rdaddress_reg <= rdaddress;
i_rden_reg <= i_rden;
end
end
//=========
// Memory
//=========
always @(i_data_tmp or i_wren_tmp or i_wraddress_tmp or negedge i_inclock)
begin
if (i_wren_tmp == 1'b1)
if (ValidAddress(i_wraddress_tmp))
begin
if (((use_eab == "ON") || (lpm_hint == "USE_EAB=ON")) &&
(lpm_wraddress_control == "REGISTERED"))
begin
if (i_inclock == 1'b0)
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
else
mem_data[i_wraddress_tmp] <= i_data_tmp;
end
end
always @(i_rden_tmp or i_rdaddress_tmp or mem_data[i_rdaddress_tmp])
begin
if (i_rden_tmp == 1'b1)
i_q_tmp = (ValidAddress(i_rdaddress_tmp))
? mem_data[i_rdaddress_tmp]
: {lpm_width{1'bx}};
end
//=======
// Sync
//=======
always @(wraddress or i_wraddress_reg)
i_wraddress_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wraddress_reg
: wraddress;
always @(rdaddress or i_rdaddress_reg)
i_rdaddress_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rdaddress_reg
: rdaddress;
always @(i_wren or i_wren_reg)
i_wren_tmp = (lpm_wraddress_control == "REGISTERED")
? i_wren_reg
: i_wren;
always @(i_rden or i_rden_reg)
i_rden_tmp = (lpm_rdaddress_control == "REGISTERED")
? i_rden_reg
: i_rden;
always @(data or i_data_reg)
i_data_tmp = (lpm_indata == "REGISTERED")
? i_data_reg
: data;
// CONTINOUS ASSIGNMENT
assign q = (lpm_outdata == "REGISTERED") ? i_q_reg : i_q_tmp;
endmodule // lpm_ram_dp
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_ram_io
//
// Description : Parameterized RAM with a single I/O port megafunction
//
// Limitation : This megafunction is provided only for backward
// compatibility in Cyclone, Stratix, and Stratix GX designs;
// instead, Altera recommends using the altsyncram
// megafunction
//
// Results expected: Output of RAM content at bi-directional DIO.
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_ram_io ( dio, inclock, outclock, we, memenab, outenab, address );
// PARAMETER DECLARATION
parameter lpm_type = "lpm_ram_io";
parameter lpm_width = 1;
parameter lpm_widthad = 1;
parameter lpm_numwords = 1<< lpm_widthad;
parameter lpm_indata = "REGISTERED";
parameter lpm_address_control = "REGISTERED";
parameter lpm_outdata = "REGISTERED";
parameter lpm_file = "UNUSED";
parameter lpm_hint = "UNUSED";
parameter use_eab = "ON";
parameter intended_device_family = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock, outclock, we;
input memenab;
input outenab;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] dio;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [lpm_numwords-1:0];
reg [lpm_width-1:0] tmp_io;
reg [lpm_width-1:0] tmp_q;
reg [lpm_width-1:0] pdio;
reg [lpm_widthad-1:0] paddress;
reg [lpm_widthad-1:0] paddress_tmp;
reg pwe;
reg [8*256:1] ram_initf;
// INTERNAL WIRE DECLARATION
wire [lpm_width-1:0] read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
wire i_outenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
tri1 outenab;
// INTERNAL BUF DECLARATION
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
buf (i_outenab, outenab);
// FUNCTON DECLARATION
function ValidAddress;
input [lpm_widthad-1:0] paddress;
begin
ValidAddress = 1'b0;
if (^paddress === {lpm_widthad{1'bx}})
begin
$display("%t:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (paddress >= lpm_numwords)
begin
$display("%t:Error: Address out of bound on RAM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// COMPONENT INSTANTIATIONS
LPM_MEMORY_INITIALIZATION mem ();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((lpm_numwords > (1 << lpm_widthad))
||(lpm_numwords <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_indata != "REGISTERED") && (lpm_indata != "UNREGISTERED"))
begin
$display("Error! LPM_INDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") && (lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < lpm_numwords; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// Initialize input/output
pwe = 1'b0;
pdio = {lpm_width{1'b0}};
paddress = {lpm_widthad{1'b0}};
paddress_tmp = {lpm_widthad{1'b0}};
tmp_io = {lpm_width{1'b0}};
tmp_q = {lpm_width{1'b0}};
// load data to the RAM
if (lpm_file != "UNUSED")
begin
mem.convert_to_ver_file(lpm_file, lpm_width, ram_initf);
$readmemh(ram_initf, mem_data);
end
end
// ALWAYS CONSTRUCT BLOCK
always @(dio)
begin
if (lpm_indata == "UNREGISTERED")
pdio <= dio;
end
always @(address)
begin
if (lpm_address_control == "UNREGISTERED")
paddress <= address;
end
always @(we)
begin
if (lpm_address_control == "UNREGISTERED")
pwe <= we;
end
always @(posedge i_inclock)
begin
if (lpm_indata == "REGISTERED")
pdio <= dio;
if (lpm_address_control == "REGISTERED")
begin
paddress <= address;
pwe <= we;
end
end
always @(pdio or paddress or pwe or i_memenab)
begin
if (ValidAddress(paddress))
begin
paddress_tmp <= paddress;
if (lpm_address_control == "UNREGISTERED")
if (pwe && i_memenab)
mem_data[paddress] <= pdio;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= {lpm_width{1'bx}};
end
end
always @(read_data)
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q <= read_data;
end
always @(negedge i_inclock or pdio)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "ON") || (lpm_hint == "USE_EAB=ON"))
if (pwe && i_memenab && (i_inclock == 1'b0))
mem_data[paddress] = pdio;
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
if ((use_eab == "OFF") && pwe && i_memenab)
mem_data[paddress] <= pdio;
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
tmp_q <= mem_data[paddress];
end
always @(i_memenab or i_outenab or tmp_q)
begin
if (i_memenab && i_outenab)
tmp_io = tmp_q;
else if ((!i_memenab) || (i_memenab && (!i_outenab)))
tmp_io = {lpm_width{1'bz}};
end
// CONTINOUS ASSIGNMENT
assign dio = tmp_io;
assign read_data = mem_data[paddress_tmp];
endmodule // lpm_ram_io
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_rom
//
// Description : Parameterized ROM megafunction. This megafunction is provided
// only for backward compatibility in Cyclone, Stratix, and
// Stratix GX designs; instead, Altera recommends using the
// altsyncram megafunction.
//
// Limitation : This option is available for all Altera devices supported by
// the Quartus II software except MAX 3000 and MAX 7000 devices.
//
// Results expected: Output of memory.
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_rom (
address, // Address input to the memory. (Required)
inclock, // Clock for input registers.
outclock, // Clock for output registers.
memenab, // Memory enable input.
q // Output of memory. (Required)
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1; // Width of the q[] port. (Required)
parameter lpm_widthad = 1; // Width of the address[] port. (Required)
parameter lpm_numwords = 0; // Number of words stored in memory.
parameter lpm_address_control = "REGISTERED"; // Indicates whether the address port is registered.
parameter lpm_outdata = "REGISTERED"; // Indicates whether the q and eq ports are registered.
parameter lpm_file = ""; // Name of the memory file containing ROM initialization data
parameter intended_device_family = "Stratix";
parameter lpm_type = "lpm_rom";
parameter lpm_hint = "UNUSED";
// LOCAL_PARAMETERS_BEGIN
parameter NUM_WORDS = (lpm_numwords == 0) ? (1 << lpm_widthad) : lpm_numwords;
// LOCAL_PARAMETERS_END
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] address;
input inclock;
input outclock;
input memenab;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] mem_data [0:NUM_WORDS-1];
reg [lpm_widthad-1:0] address_reg;
reg [lpm_width-1:0] tmp_q_reg;
reg [8*256:1] rom_initf;
// INTERNAL WIRE DECLARATION
wire [lpm_widthad-1:0] w_address;
wire [lpm_width-1:0] w_read_data;
wire i_inclock;
wire i_outclock;
wire i_memenab;
// LOCAL INTEGER DECLARATION
integer i;
// INTERNAL TRI DECLARATION
tri0 inclock;
tri0 outclock;
tri1 memenab;
buf (i_inclock, inclock);
buf (i_outclock, outclock);
buf (i_memenab, memenab);
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_MEMORY_INITIALIZATION mem ();
// FUNCTON DECLARATION
// Check the validity of the address.
function ValidAddress;
input [lpm_widthad-1:0] address;
begin
ValidAddress = 1'b0;
if (^address == {lpm_widthad{1'bx}})
begin
$display("%d:Error: Invalid address.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else if (address >= NUM_WORDS)
begin
$display("%d:Error: Address out of bound on ROM.", $time);
$display("Time: %0t Instance: %m", $time);
$finish;
end
else
ValidAddress = 1'b1;
end
endfunction
// INITIAL CONSTRUCT BLOCK
initial
begin
// Initialize output
tmp_q_reg = {lpm_width{1'b0}};
address_reg = {lpm_widthad{1'b0}};
if (lpm_width <= 0)
begin
$display("Error! LPM_WIDTH parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (lpm_widthad <= 0)
begin
$display("Error! LPM_WIDTHAD parameter must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
// check for number of words out of bound
if ((NUM_WORDS > (1 << lpm_widthad)) ||
(NUM_WORDS <= (1 << (lpm_widthad-1))))
begin
$display("Error! The ceiling of log2(LPM_NUMWORDS) must equal to LPM_WIDTHAD.");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_address_control != "REGISTERED") &&
(lpm_address_control != "UNREGISTERED"))
begin
$display("Error! LPM_ADDRESS_CONTROL must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if ((lpm_outdata != "REGISTERED") && (lpm_outdata != "UNREGISTERED"))
begin
$display("Error! LPM_OUTDATA must be \"REGISTERED\" or \"UNREGISTERED\".");
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
if (dev.FEATURE_FAMILY_MAX(intended_device_family) == 1)
begin
$display ("Error! LPM_ROM megafunction does not support %s devices.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$finish;
end
for (i = 0; i < NUM_WORDS; i=i+1)
mem_data[i] = {lpm_width{1'b0}};
// load data to the ROM
if ((lpm_file == "") || (lpm_file == "UNUSED"))
begin
$display("Warning: LPM_ROM must have data file for initialization.\n");
$display ("Time: %0t Instance: %m", $time);
end
else
begin
mem.convert_to_ver_file(lpm_file, lpm_width, rom_initf);
$readmemh(rom_initf, mem_data);
end
end
always @(posedge i_inclock)
begin
if (lpm_address_control == "REGISTERED")
address_reg <= address; // address port is registered
end
always @(w_address or w_read_data)
begin
if (ValidAddress(w_address))
begin
if (lpm_outdata == "UNREGISTERED")
// Load the output register with the contents of the memory location
// pointed to by address[].
tmp_q_reg <= w_read_data;
end
else
begin
if (lpm_outdata == "UNREGISTERED")
tmp_q_reg <= {lpm_width{1'bx}};
end
end
always @(posedge i_outclock)
begin
if (lpm_outdata == "REGISTERED")
begin
if (ValidAddress(w_address))
tmp_q_reg <= w_read_data;
else
tmp_q_reg <= {lpm_width{1'bx}};
end
end
// CONTINOUS ASSIGNMENT
assign w_address = (lpm_address_control == "REGISTERED") ? address_reg : address;
assign w_read_data = mem_data[w_address];
assign q = (i_memenab) ? tmp_q_reg : {lpm_width{1'bz}};
endmodule // lpm_rom
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
`timescale 1 ps / 1 ps
module lpm_fifo ( data,
clock,
wrreq,
rdreq,
aclr,
sclr,
q,
usedw,
full,
empty );
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter lpm_type = "lpm_fifo";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input clock;
input wrreq;
input rdreq;
input aclr;
input sclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
output [lpm_widthu-1:0] usedw;
output full;
output empty;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu):0];
reg [lpm_width-1:0] tmp_data;
reg [lpm_widthu-1:0] count_id;
reg [lpm_widthu-1:0] read_id;
reg [lpm_widthu-1:0] write_id;
reg write_flag;
reg full_flag;
reg empty_flag;
reg [lpm_width-1:0] tmp_q;
reg [8*5:1] overflow_checking;
reg [8*5:1] underflow_checking;
reg [8*20:1] allow_rwcycle_when_full;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire valid_rreq;
wire valid_wreq;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display ("Error! LPM_WIDTH must be greater than 0.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= 1)
begin
$display ("Error! LPM_NUMWORDS must be greater than or equal to 2.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if ((lpm_widthu !=1) && (lpm_numwords > (1 << lpm_widthu)))
begin
$display ("Error! LPM_NUMWORDS must equal to the ceiling of log2(LPM_WIDTHU).");
$display("Time: %0t Instance: %m", $time);
$stop;
end
if (lpm_numwords <= (1 << (lpm_widthu - 1)))
begin
$display ("Error! LPM_WIDTHU is too big for the specified LPM_NUMWORDS.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if(overflow_checking == "")
overflow_checking = "ON";
else if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(underflow_checking == "")
underflow_checking = "ON";
else if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
allow_rwcycle_when_full = eva.GET_PARAMETER_VALUE(lpm_hint, "ALLOW_RWCYCLE_WHEN_FULL");
if (allow_rwcycle_when_full == "")
allow_rwcycle_when_full = "OFF";
else if ((allow_rwcycle_when_full != "ON") && (allow_rwcycle_when_full != "OFF"))
begin
$display ("Error! ALLOW_RWCYCLE_WHEN_FULL must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1<<lpm_widthu); i = i + 1)
begin
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
mem_data[i] <= {lpm_width{1'bx}};
else
mem_data[i] <= {lpm_width{1'b0}};
end
tmp_data <= 0;
if (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family))
tmp_q <= {lpm_width{1'bx}};
else
tmp_q <= {lpm_width{1'b0}};
write_flag <= 1'b0;
count_id <= 0;
read_id <= 0;
write_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge clock or posedge aclr)
begin
if (aclr)
begin
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= {lpm_width{1'b0}};
end
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq && (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else if (sclr)
begin
if ((lpm_showahead == "ON") || (dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)))
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
count_id <= 0;
full_flag <= 1'b0;
empty_flag <= 1'b1;
if (valid_wreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
end
else
write_id <= 0;
end
else
begin
// Both WRITE and READ operations
if (valid_wreq && valid_rreq)
begin
tmp_data <= data;
write_flag <= 1'b1;
empty_flag <= 1'b0;
if (allow_rwcycle_when_full == "OFF")
begin
full_flag <= 1'b0;
end
if (read_id >= ((1 << lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end
// WRITE operation only
else if (valid_wreq)
begin
tmp_data <= data;
empty_flag <= 1'b0;
write_flag <= 1'b1;
if (count_id >= (1 << lpm_widthu) - 1)
count_id <= 0;
else
count_id <= count_id + 1;
if ((count_id == lpm_numwords - 1) && (empty_flag == 1'b0))
full_flag <= 1'b1;
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id];
end
// READ operation only
else if (valid_rreq)
begin
full_flag <= 1'b0;
if (count_id <= 0)
count_id <= {lpm_widthu{1'b1}};
else
count_id <= count_id - 1;
if ((count_id == 1) && (full_flag == 1'b0))
empty_flag <= 1'b1;
if (read_id >= ((1<<lpm_widthu) - 1))
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[0];
else
tmp_q <= mem_data[read_id];
read_id <= 0;
end
else
begin
if (lpm_showahead == "ON")
tmp_q <= mem_data[read_id + 1];
else
tmp_q <= mem_data[read_id];
read_id <= read_id + 1;
end
end // if Both WRITE and READ operations
end // if aclr
end // @(posedge clock)
always @(negedge clock)
begin
if (write_flag)
begin
write_flag <= 1'b0;
mem_data[write_id] <= tmp_data;
if (sclr || aclr || (write_id >= ((1 << lpm_widthu) - 1)))
write_id <= 0;
else
write_id <= write_id + 1;
end
if ((lpm_showahead == "ON") && ($time > 0))
tmp_q <= ((write_flag == 1'b1) && (write_id == read_id)) ?
tmp_data : mem_data[read_id];
end // @(negedge clock)
// CONTINOUS ASSIGNMENT
assign valid_rreq = (underflow_checking == "OFF") ? rdreq : rdreq && ~empty_flag;
assign valid_wreq = (overflow_checking == "OFF") ? wrreq :
(allow_rwcycle_when_full == "ON") ? wrreq && (!full_flag || rdreq) :
wrreq && !full_flag;
assign q = tmp_q;
assign full = full_flag;
assign empty = empty_flag;
assign usedw = count_id;
endmodule // lpm_fifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_dffpipe
//
// Description : Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_dffpipe (d,
clock,
aclr,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_delay = 1;
parameter lpm_width = 64;
// INPUT PORT DECLARATION
input [lpm_width-1:0] d;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] dffpipe [lpm_delay:0];
reg [lpm_width-1:0] q;
// LOCAL INTEGER DECLARATION
integer delay;
integer i;
// INITIAL CONSTRUCT BLOCK
initial
begin
delay <= lpm_delay - 1;
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr or posedge clock)
begin
if (aclr)
begin
for (i = 0; i <= lpm_delay; i = i + 1)
dffpipe[i] <= 0;
q <= 0;
end
else if (clock)
begin
if ((lpm_delay > 0) && ($time > 0))
begin
if (delay > 0)
begin
for (i = delay; i > 0; i = i - 1)
dffpipe[i] <= dffpipe[i - 1];
q <= dffpipe[delay - 1];
end
else
q <= d;
dffpipe[0] <= d;
end
end
end // @(posedge aclr or posedge clock)
always @(d)
begin
if (lpm_delay == 0)
q <= d;
end // @(d)
endmodule // lpm_fifo_dc_dffpipe
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_fefifo
//
// Description : Dual Clock FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_fefifo ( usedw_in,
wreq,
rreq,
clock,
aclr,
empty,
full);
// GLOBAL PARAMETER DECLARATION
parameter lpm_widthad = 1;
parameter lpm_numwords = 1;
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_mode = "READ";
parameter lpm_hint = "";
// INPUT PORT DECLARATION
input [lpm_widthad-1:0] usedw_in;
input wreq;
input rreq;
input clock;
input aclr;
// OUTPUT PORT DECLARATION
output empty;
output full;
// INTERNAL REGISTERS DECLARATION
reg [1:0] sm_empty;
reg lrreq;
reg i_empty;
reg i_full;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
// LOCAL INTEGER DECLARATION
integer almostfull;
// COMPONENT INSTANTIATIONS
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if ((lpm_mode != "READ") && (lpm_mode != "WRITE"))
begin
$display ("Error! LPM_MODE must be READ or WRITE.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
if (lpm_numwords >= 3)
almostfull <= lpm_numwords - 3;
else
almostfull <= 0;
end
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
sm_empty <= 2'b00;
i_empty <= 1'b1;
i_full <= 1'b0;
lrreq <= 1'b0;
end // @(posedge aclr)
always @(posedge clock)
begin
if (i_underflow_checking == "OFF")
lrreq <= rreq;
else
lrreq <= rreq && ~i_empty;
if (~aclr && ($time > 0))
begin
if (lpm_mode == "READ")
begin
casex (sm_empty)
// state_empty
2'b00:
if (usedw_in != 0)
sm_empty <= 2'b01;
// state_non_empty
2'b01:
if (rreq && (((usedw_in == 1) && !lrreq) || ((usedw_in == 2) && lrreq)))
sm_empty <= 2'b10;
// state_emptywait
2'b10:
if (usedw_in > 1)
sm_empty <= 2'b01;
else
sm_empty <= 2'b00;
default:
begin
$display ("Error! Invalid sm_empty state in read mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "READ")
else if (lpm_mode == "WRITE")
begin
casex (sm_empty)
// state_empty
2'b00:
if (wreq)
sm_empty <= 2'b01;
// state_one
2'b01:
if (!wreq)
sm_empty <= 2'b11;
// state_non_empty
2'b11:
if (wreq)
sm_empty <= 2'b01;
else if (usedw_in == 0)
sm_empty <= 2'b00;
default:
begin
$display ("Error! Invalid sm_empty state in write mode.");
$display("Time: %0t Instance: %m", $time);
end
endcase
end // if (lpm_mode == "WRITE")
if (~aclr && (usedw_in >= almostfull) && ($time > 0))
i_full <= 1'b1;
else
i_full <= 1'b0;
end // if (~aclr && $time > 0)
end // @(posedge clock)
always @(sm_empty)
begin
i_empty <= !sm_empty[0];
end
// @(sm_empty)
// CONTINOUS ASSIGNMENT
assign empty = i_empty;
assign full = i_full;
endmodule // lpm_fifo_dc_fefifo
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc_async
//
// Description : Asynchronous Dual Clocks FIFO
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc_async ( data,
rdclk,
wrclk,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "INTENDED_DEVICE_FAMILY=Stratix";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclk;
input wrclk;
input aclr;
input wrreq;
input rdreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// INTERNAL REGISTERS DECLARATION
reg [lpm_width-1:0] mem_data [(1<<lpm_widthu)-1:0];
reg [lpm_width-1:0] i_data_tmp;
reg [lpm_widthu-1:0] i_rdptr;
reg [lpm_widthu-1:0] i_wrptr;
reg [lpm_widthu-1:0] i_wrptr_tmp;
reg i_rdenclock;
reg i_wren_tmp;
reg [lpm_widthu-1:0] i_wr_udwn;
reg [lpm_widthu-1:0] i_rd_udwn;
reg i_showahead_flag;
reg i_showahead_flag1;
reg [lpm_widthu:0] i_rdusedw;
reg [lpm_widthu-1:0] i_wrusedw;
reg [lpm_width-1:0] i_q_tmp;
reg [8*5:1] i_overflow_checking;
reg [8*5:1] i_underflow_checking;
reg [8*10:1] use_eab;
reg [8*20:1] intended_device_family;
// INTERNAL WIRE DECLARATION
wire w_rden;
wire w_wren;
wire w_rdempty;
wire w_wrempty;
wire w_rdfull;
wire w_wrfull;
wire [lpm_widthu-1:0] w_rdptrrg;
wire [lpm_widthu-1:0] w_wrdelaycycle;
wire [lpm_widthu-1:0] w_ws_nbrp;
wire [lpm_widthu-1:0] w_rs_nbwp;
wire [lpm_widthu-1:0] w_ws_dbrp;
wire [lpm_widthu-1:0] w_rs_dbwp;
wire [lpm_widthu-1:0] w_rd_dbuw;
wire [lpm_widthu-1:0] w_wr_dbuw;
wire [lpm_widthu-1:0] w_rdusedw;
wire [lpm_widthu-1:0] w_wrusedw;
// INTERNAL TRI DECLARATION
tri0 aclr;
// LOCAL INTEGER DECLARATION
integer i;
// COMPONENT INSTANTIATIONS
LPM_DEVICE_FAMILIES dev ();
LPM_HINT_EVALUATION eva();
// INITIAL CONSTRUCT BLOCK
initial
begin
if((lpm_showahead != "ON") && (lpm_showahead != "OFF"))
begin
$display ("Error! lpm_showahead must be ON or OFF.");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_overflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "OVERFLOW_CHECKING");
if (i_overflow_checking == "")
begin
if ((overflow_checking != "ON") && (overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_overflow_checking = overflow_checking;
end
else if ((i_overflow_checking != "ON") && (i_overflow_checking != "OFF"))
begin
$display ("Error! OVERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
i_underflow_checking = eva.GET_PARAMETER_VALUE(lpm_hint, "UNDERFLOW_CHECKING");
if(i_underflow_checking == "")
begin
if ((underflow_checking != "ON") && (underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
else
i_underflow_checking = underflow_checking;
end
else if ((i_underflow_checking != "ON") && (i_underflow_checking != "OFF"))
begin
$display ("Error! UNDERFLOW_CHECKING must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
use_eab = eva.GET_PARAMETER_VALUE(lpm_hint, "USE_EAB");
if(use_eab == "")
use_eab = "ON";
else if ((use_eab != "ON") && (use_eab != "OFF"))
begin
$display ("Error! USE_EAB must equal to either 'ON' or 'OFF'");
$display("Time: %0t Instance: %m", $time);
$stop;
end
intended_device_family = eva.GET_PARAMETER_VALUE(lpm_hint, "INTENDED_DEVICE_FAMILY");
if (intended_device_family == "")
intended_device_family = "Stratix II";
else if (dev.IS_VALID_FAMILY(intended_device_family) == 0)
begin
$display ("Error! Unknown INTENDED_DEVICE_FAMILY=%s.", intended_device_family);
$display("Time: %0t Instance: %m", $time);
$stop;
end
for (i = 0; i < (1 << lpm_widthu); i = i + 1)
mem_data[i] <= 0;
i_data_tmp <= 0;
i_rdptr <= 0;
i_wrptr <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
i_wr_udwn <= 0;
i_rd_udwn <= 0;
i_rdusedw <= 0;
i_wrusedw <= 0;
i_q_tmp <= 0;
end
// COMPONENT INSTANTIATIONS
// Delays & DFF Pipes
lpm_fifo_dc_dffpipe DP_RDPTR_D (
.d (i_rdptr),
.clock (i_rdenclock),
.aclr (aclr),
.q (w_rdptrrg));
lpm_fifo_dc_dffpipe DP_WRPTR_D (
.d (i_wrptr),
.clock (wrclk),
.aclr (aclr),
.q (w_wrdelaycycle));
defparam
DP_RDPTR_D.lpm_delay = 0,
DP_RDPTR_D.lpm_width = lpm_widthu,
DP_WRPTR_D.lpm_delay = 1,
DP_WRPTR_D.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WS_NBRP (
.d (w_rdptrrg),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_nbrp));
lpm_fifo_dc_dffpipe DP_RS_NBWP (
.d (w_wrdelaycycle),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_nbwp));
lpm_fifo_dc_dffpipe DP_WS_DBRP (
.d (w_ws_nbrp),
.clock (wrclk),
.aclr (aclr),
.q (w_ws_dbrp));
lpm_fifo_dc_dffpipe DP_RS_DBWP (
.d (w_rs_nbwp),
.clock (rdclk),
.aclr (aclr),
.q (w_rs_dbwp));
defparam
DP_WS_NBRP.lpm_delay = wrsync_delaypipe,
DP_WS_NBRP.lpm_width = lpm_widthu,
DP_RS_NBWP.lpm_delay = rdsync_delaypipe,
DP_RS_NBWP.lpm_width = lpm_widthu,
DP_WS_DBRP.lpm_delay = 1, // gray_delaypipe
DP_WS_DBRP.lpm_width = lpm_widthu,
DP_RS_DBWP.lpm_delay = 1, // gray_delaypipe
DP_RS_DBWP.lpm_width = lpm_widthu;
lpm_fifo_dc_dffpipe DP_WRUSEDW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wrusedw));
lpm_fifo_dc_dffpipe DP_RDUSEDW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rdusedw));
lpm_fifo_dc_dffpipe DP_WR_DBUW (
.d (i_wr_udwn),
.clock (wrclk),
.aclr (aclr),
.q (w_wr_dbuw));
lpm_fifo_dc_dffpipe DP_RD_DBUW (
.d (i_rd_udwn),
.clock (rdclk),
.aclr (aclr),
.q (w_rd_dbuw));
defparam
DP_WRUSEDW.lpm_delay = delay_wrusedw,
DP_WRUSEDW.lpm_width = lpm_widthu,
DP_RDUSEDW.lpm_delay = delay_rdusedw,
DP_RDUSEDW.lpm_width = lpm_widthu,
DP_WR_DBUW.lpm_delay = 1, // wrusedw_delaypipe
DP_WR_DBUW.lpm_width = lpm_widthu,
DP_RD_DBUW.lpm_delay = 1, // rdusedw_delaypipe
DP_RD_DBUW.lpm_width = lpm_widthu;
// Empty/Full
lpm_fifo_dc_fefifo WR_FE (
.usedw_in (w_wr_dbuw),
.wreq (wrreq),
.rreq (rdreq),
.clock (wrclk),
.aclr (aclr),
.empty (w_wrempty),
.full (w_wrfull));
lpm_fifo_dc_fefifo RD_FE (
.usedw_in (w_rd_dbuw),
.rreq (rdreq),
.wreq(wrreq),
.clock (rdclk),
.aclr (aclr),
.empty (w_rdempty),
.full (w_rdfull));
defparam
WR_FE.lpm_widthad = lpm_widthu,
WR_FE.lpm_numwords = lpm_numwords,
WR_FE.underflow_checking = underflow_checking,
WR_FE.overflow_checking = overflow_checking,
WR_FE.lpm_mode = "WRITE",
WR_FE.lpm_hint = lpm_hint,
RD_FE.lpm_widthad = lpm_widthu,
RD_FE.lpm_numwords = lpm_numwords,
RD_FE.underflow_checking = underflow_checking,
RD_FE.overflow_checking = overflow_checking,
RD_FE.lpm_mode = "READ",
RD_FE.lpm_hint = lpm_hint;
// ALWAYS CONSTRUCT BLOCK
always @(posedge aclr)
begin
i_rdptr <= 0;
i_wrptr <= 0;
if (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF"))
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end // @(posedge aclr)
// FIFOram
always @(posedge wrclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
i_data_tmp <= 0;
i_wrptr_tmp <= 0;
i_wren_tmp <= 0;
end
else if (wrclk && ($time > 0))
begin
i_data_tmp <= data;
i_wrptr_tmp <= i_wrptr;
i_wren_tmp <= w_wren;
if (w_wren)
begin
if (~aclr && ((i_wrptr < (1<<lpm_widthu)-1) || (i_overflow_checking == "OFF")))
i_wrptr <= i_wrptr + 1;
else
i_wrptr <= 0;
if (use_eab == "OFF")
begin
mem_data[i_wrptr] <= data;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end
end
end // @(posedge wrclk)
always @(negedge wrclk)
begin
if ((~wrclk && (use_eab == "ON")) && ($time > 0))
begin
if (i_wren_tmp)
begin
mem_data[i_wrptr_tmp] <= i_data_tmp;
end
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
end
end // @(negedge wrclk)
always @(posedge rdclk)
begin
if (aclr && (!(dev.FEATURE_FAMILY_BASE_STRATIX(intended_device_family) ||
dev.FEATURE_FAMILY_BASE_CYCLONE(intended_device_family)) ||
(use_eab == "OFF")))
begin
if (lpm_showahead == "ON")
i_q_tmp <= mem_data[0];
else
i_q_tmp <= 0;
end
else if (rdclk && w_rden && ($time > 0))
begin
if (~aclr && ((i_rdptr < (1<<lpm_widthu)-1) || (i_underflow_checking == "OFF")))
i_rdptr <= i_rdptr + 1;
else
i_rdptr <= 0;
if (lpm_showahead == "ON")
i_showahead_flag1 <= 1'b1;
else
i_q_tmp <= mem_data[i_rdptr];
end
end // @(rdclk)
always @(posedge i_showahead_flag)
begin
i_q_tmp <= mem_data[i_rdptr];
i_showahead_flag1 <= 1'b0;
end // @(posedge i_showahead_flag)
always @(i_showahead_flag1)
begin
i_showahead_flag <= i_showahead_flag1;
end // @(i_showahead_flag1)
// Delays & DFF Pipes
always @(negedge rdclk)
begin
i_rdenclock <= 0;
end // @(negedge rdclk)
always @(posedge rdclk)
begin
if (w_rden)
i_rdenclock <= 1;
end // @(posedge rdclk)
always @(i_wrptr or w_ws_dbrp)
begin
i_wr_udwn <= i_wrptr - w_ws_dbrp;
end // @(i_wrptr or w_ws_dbrp)
always @(i_rdptr or w_rs_dbwp)
begin
i_rd_udwn <= w_rs_dbwp - i_rdptr;
end // @(i_rdptr or w_rs_dbwp)
// CONTINOUS ASSIGNMENT
assign w_rden = (i_underflow_checking == "OFF") ? rdreq : rdreq && !w_rdempty;
assign w_wren = (i_overflow_checking == "OFF") ? wrreq : wrreq && !w_wrfull;
assign q = i_q_tmp;
assign wrfull = w_wrfull;
assign rdfull = w_rdfull;
assign wrempty = w_wrempty;
assign rdempty = w_rdempty;
assign wrusedw = w_wrusedw;
assign rdusedw = w_rdusedw;
endmodule // lpm_fifo_dc_async
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_fifo_dc
//
// Description :
//
// Limitation :
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_fifo_dc (data,
rdclock,
wrclock,
aclr,
rdreq,
wrreq,
rdfull,
wrfull,
rdempty,
wrempty,
rdusedw,
wrusedw,
q);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_widthu = 1;
parameter lpm_numwords = 2;
parameter lpm_showahead = "OFF";
parameter underflow_checking = "ON";
parameter overflow_checking = "ON";
parameter lpm_hint = "";
parameter lpm_type = "lpm_fifo_dc";
// LOCAL PARAMETER DECLARATION
parameter delay_rdusedw = 1;
parameter delay_wrusedw = 1;
parameter rdsync_delaypipe = 3;
parameter wrsync_delaypipe = 3;
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input rdclock;
input wrclock;
input aclr;
input rdreq;
input wrreq;
// OUTPUT PORT DECLARATION
output rdfull;
output wrfull;
output rdempty;
output wrempty;
output [lpm_widthu-1:0] rdusedw;
output [lpm_widthu-1:0] wrusedw;
output [lpm_width-1:0] q;
// internal reg
wire w_rdfull_s;
wire w_wrfull_s;
wire w_rdempty_s;
wire w_wrempty_s;
wire w_rdfull_a;
wire w_wrfull_a;
wire w_rdempty_a;
wire w_wrempty_a;
wire [lpm_widthu-1:0] w_rdusedw_s;
wire [lpm_widthu-1:0] w_wrusedw_s;
wire [lpm_widthu-1:0] w_rdusedw_a;
wire [lpm_widthu-1:0] w_wrusedw_a;
wire [lpm_width-1:0] w_q_s;
wire [lpm_width-1:0] w_q_a;
wire i_aclr;
// INTERNAL TRI DECLARATION
tri0 aclr;
buf (i_aclr, aclr);
// COMPONENT INSTANTIATIONS
lpm_fifo_dc_async ASYNC (
.data (data),
.rdclk (rdclock),
.wrclk (wrclock),
.aclr (i_aclr),
.rdreq (rdreq),
.wrreq (wrreq),
.rdfull (w_rdfull_a),
.wrfull (w_wrfull_a),
.rdempty (w_rdempty_a),
.wrempty (w_wrempty_a),
.rdusedw (w_rdusedw_a),
.wrusedw (w_wrusedw_a),
.q (w_q_a) );
defparam
ASYNC.lpm_width = lpm_width,
ASYNC.lpm_widthu = lpm_widthu,
ASYNC.lpm_numwords = lpm_numwords,
ASYNC.delay_rdusedw = delay_rdusedw,
ASYNC.delay_wrusedw = delay_wrusedw,
ASYNC.rdsync_delaypipe = rdsync_delaypipe,
ASYNC.wrsync_delaypipe = wrsync_delaypipe,
ASYNC.lpm_showahead = lpm_showahead,
ASYNC.underflow_checking = underflow_checking,
ASYNC.overflow_checking = overflow_checking,
ASYNC.lpm_hint = lpm_hint;
// CONTINOUS ASSIGNMENT
assign rdfull = w_rdfull_a;
assign wrfull = w_wrfull_a;
assign rdempty = w_rdempty_a;
assign wrempty = w_wrempty_a;
assign rdusedw = w_rdusedw_a;
assign wrusedw = w_wrusedw_a;
assign q = w_q_a;
endmodule // lpm_fifo_dc
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_inpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_inpad (
pad,
result
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_inpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] pad;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(pad)
begin
result = pad;
end
endmodule // lpm_inpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_outpad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_outpad (
data,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_outpad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] pad;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data)
begin
pad = data;
end
endmodule // lpm_outpad
// END OF MODULE
//START_MODULE_NAME------------------------------------------------------------
//
// Module Name : lpm_bipad
//
// Description :
//
// Limitation : n/a
//
// Results expected:
//
//END_MODULE_NAME--------------------------------------------------------------
// BEGINNING OF MODULE
`timescale 1 ps / 1 ps
// MODULE DECLARATION
module lpm_bipad (
data,
enable,
result,
pad
);
// GLOBAL PARAMETER DECLARATION
parameter lpm_width = 1;
parameter lpm_type = "lpm_bipad";
parameter lpm_hint = "UNUSED";
// INPUT PORT DECLARATION
input [lpm_width-1:0] data;
input enable;
// OUTPUT PORT DECLARATION
output [lpm_width-1:0] result;
// INPUT/OUTPUT PORT DECLARATION
inout [lpm_width-1:0] pad;
// INTERNAL REGISTER/SIGNAL DECLARATION
reg [lpm_width-1:0] result;
// INITIAL CONSTRUCT BLOCK
initial
begin
if (lpm_width <= 0)
begin
$display("Value of lpm_width parameter must be greater than 0(ERROR)");
$display("Time: %0t Instance: %m", $time);
$finish;
end
end
// ALWAYS CONSTRUCT BLOCK
always @(data or pad or enable)
begin
if (enable == 1)
begin
result = {lpm_width{1'bz}};
end
else if (enable == 0)
begin
result = pad;
end
end
// CONTINOUS ASSIGNMENT
assign pad = (enable == 1) ? data : {lpm_width{1'bz}};
endmodule // lpm_bipad
// END OF MODULE
|
/* -------------------------------------------------------------------------------
* (C)2007 Robert Mullins
* Computer Architecture Group, Computer Laboratory
* University of Cambridge, UK.
* -------------------------------------------------------------------------------
*
* FIFO
* ====
*
* Implementation notes:
*
* - Read and write pointers are simple ring counters
*
* - Number of items held in FIFO is recorded in shift register
* (Full/empty flags are most and least-significant bits of register)
*
* Examples:
*
* fifo_v #(.fifo_elements_t(int), .size(8)) myfifo (.*);
*
* Instantiates a FIFO that can hold up to 8 integers.
/************************************************************************************
*
* FIFO
*
************************************************************************************/
typedef struct packed
{
logic full, empty, nearly_full, nearly_empty;
} fifov_flags_t;
module LAG_fifo_v (push, pop, data_in, data_out, flags, clk, rst_n);
// max no. of entries
parameter size = 8;
input push, pop;
output fifov_flags_t flags;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
logic fifo_push, fifo_pop;
fifo_elements_t fifo_data_out, data_out_tmp;
fifo_buffer #(.size(size))
fifo_buf (push, pop, data_in, data_out_tmp, clk, rst_n);
assign data_out = flags.empty ? '0 : data_out_tmp;
fifo_flags #(.size(size))
gen_flags(push, pop, flags, clk, rst_n);
endmodule // fifo_v
/************************************************************************************
*
* Maintain FIFO flags (full, nearly_full, nearly_empty and empty)
*
* This design uses a shift register to ensure flags are available quickly.
*
************************************************************************************/
module fifo_flags (push, pop, flags, clk, rst_n);
input push, pop;
output fifov_flags_t flags;
input clk, rst_n;
parameter size = 8;
reg [size:0] counter; // counter must hold 1..size + empty state
logic was_push, was_pop;
fifov_flags_t flags_reg;
logic add, sub, same;
/*
* maintain flags
*
*
* maintain shift register as counter to determine if FIFO is full or empty
* full=counter[size-1], empty=counter[0], etc..
* init: counter=1'b1;
* (push & !pop): shift left
* (pop & !push): shift right
*/
always@(posedge clk) begin
if (!rst_n) begin
counter<={{size{1'b0}},1'b1};
was_push<=1'b0;
was_pop<=1'b0;
end else begin
if (add) begin
assert (counter!={1'b1,{size{1'b0}}}) else $fatal;
counter <= {counter[size-1:0], 1'b0};
end else if (sub) begin
assert (counter!={{size{1'b0}},1'b1}) else $fatal;
counter <= {1'b0, counter[size:1]};
end
assert (counter!=0) else $fatal;
was_push<=push;
was_pop<=pop;
assert (push!==1'bx) else $fatal;
assert (pop!==1'bx) else $fatal;
end // else: !if(!rst_n)
end
assign add = was_push && !was_pop;
assign sub = was_pop && !was_push;
assign same = !(add || sub);
assign flags.full = (counter[size] && !sub) || (counter[size-1] && add);
assign flags.empty = (counter[0] && !add) || (counter[1] && sub);
assign flags.nearly_full = (counter[size-1:0] && same) || (counter[size] && sub) || (counter[size-2] && add);
assign flags.nearly_empty = (counter[1] && same) || (counter[0] && add) || (counter[2] && sub);
endmodule // fifo_flags
/************************************************************************************
*
* Simple core FIFO module
*
************************************************************************************/
module fifo_buffer (push, pop, data_in, data_out, clk, rst_n);
// max no. of entries
parameter int unsigned size = 4;
input push, pop;
input fifo_elements_t data_in;
output fifo_elements_t data_out;
input clk, rst_n;
// reg [size-1:0] rd_ptr, wt_ptr;
logic unsigned [size-1:0] rd_ptr, wt_ptr;
fifo_elements_t fifo_mem[0:size-1];
logic select_bypass;
integer i,j;
always@(posedge clk) begin
assert (size>=2) else $fatal();
if (!rst_n) begin
rd_ptr<={{size-1{1'b0}},1'b1};
wt_ptr<={{size-1{1'b0}},1'b1};
end else begin
if (push) begin
// enqueue new data
for (i=0; i<size; i++) begin
if (wt_ptr[i]==1'b1) begin
fifo_mem[i] <= data_in;
end
end
end
if (push) begin
// rotate write pointer
wt_ptr <= {wt_ptr[size-2:0], wt_ptr[size-1]};
end
if (pop) begin
// rotate read pointer
rd_ptr <= {rd_ptr[size-2:0], rd_ptr[size-1]};
end
end // else: !if(!rst_n)
end // always@ (posedge clk)
/*
*
* FIFO output is item pointed to by read pointer
*
*/
always_comb begin
//
// one bit of read pointer is always set, ensure synthesis tool
// doesn't add logic to force a default
//
data_out = 'x;
for (j=0; j<size; j++) begin
if (rd_ptr[j]==1'b1) begin
// output entry pointed to by read pointer
data_out = fifo_mem[j];
end
end
end
endmodule // fifo_buffer
|
// place this file in testBench folder
`timescale 1ns/100ps
`define DEBUG 1
`include "../define.v"
`include "../regfile.v"
`include "../pipeline_CPU.v"
`include "../hilo_reg.v"
`include "../BranchControl.v"
`include "../HazardControl.v"
`include "../ForwardControl.v"
`include "../IF.v"
`include "../IF_ID.v"
`include "../ID.v"
`include "../ID_EX.v"
`include "../EX.v"
`include "../ALU.v"
`include "../decoder.v"
`include "../EX_MEM.v"
`include "../MEM.v"
`include "../RM_ctrl.v"
`include "../WM_ctrl.v"
`include "../MEM_WB.v"
`include "../utilities/dffe.v"
`include "../utilities/mux2x1.v"
`include "../utilities/mux4x1.v"
`include "rom.v"
`include "memory.v"
module SOPC;
reg clk;
reg rst;
wire[`RegDataWidth-1:0] data_from_mem;
wire[`MemAddrWidth-1:0] mem_addr;
wire[3:0] mem_byte_slct;
wire[`RegDataWidth-1:0] data_to_write_mem;
wire mem_we;
wire mem_re;
wire[`InstDataWidth-1:0] inst_from_rom;
wire[`InstAddrWidth-1:0] rom_addr;
wire rom_ce;
supply1 vcc;
supply0 gnd;
pipeline_CPU CPU(
.clk(clk),
.rst(rst),
.data_from_mem(data_from_mem),
.mem_addr(mem_addr),
.mem_byte_slct(mem_byte_slct),
.data_to_write_mem(data_to_write_mem),
.mem_we(mem_we),
.mem_re(mem_re),
.inst_from_rom(inst_from_rom),
.rom_addr(rom_addr),
.rom_ce(rom_ce)
);
rom #(.InstMemNum(32)) ROM(
.rst(gnd),
.ce(rom_ce),
.addr(rom_addr),
.inst(inst_from_rom)
);
memory RAM(
.rst(rst),
.ce(mem_re),
.data_i(data_to_write_mem),
.addr_i(mem_addr),
.we(mem_we),
.byte_slct(mem_byte_slct),
.data_o(data_from_mem)
);
initial begin
clk = 1;
forever #1 clk = ~clk;
end
initial begin
$dumpfile("test_info/logic/logic.vcd");
$dumpvars;
$readmemh("test_info/logic/logic.data", ROM.rom_data, 0, 13);
rst = `RstEnable;
#3 rst = ~`RstEnable;
#70 $finish;
end
endmodule |
// DO NOT EDIT
// This file is automatically generated!
// $ smg.shen rtl/SMG/seq.smg
//
// https://github.com/sam-falvo/smg
module Sequencer(
input take_irq,
input csrok_i,
input trap,
input [7:0] ccr,
input xt4,
input xt3,
input xt2,
input xt1,
input xt0,
input [31:0] ir,
input dack_i,
input iack_i,
input ft0,
input rst,
output mcause_irq_o,
output mepc_pc,
output alub_imm5,
output alua_cdat,
output cdat_alu,
output cdat_imm5,
output cwe_o,
output cdat_rdat,
output coe_o,
output rdat_cdat,
output mpie_1,
output mie_mpie,
output pc_mepc,
output mcause_2,
output mcause_3,
output mcause_11,
output mie_0,
output mpie_mie,
output pc_mtvec,
output mepc_ia,
output trap_o,
output fence_o,
output xt4_o,
output alub_imm12sb,
output ccr_alu,
output dwe_o,
output ddat_rdat,
output rdat_ddat,
output dsiz_fn3,
output dstb_1,
output dcyc_1,
output dadr_alu,
output ia_pc,
output sx32_en,
output pc_alu,
output xt3_o,
output and_en,
output rsh_en,
output xor_en,
output ltu_en,
output lts_en,
output invB_en,
output cflag_i,
output lsh_en,
output sum_en,
output alub_imm20uj,
output alub_imm20u,
output alub_imm12s,
output alub_imm12i,
output alub_rdat,
output alua_ia,
output alua_0,
output alua_rdat,
output rwe_o,
output rdat_pc,
output rdat_alu,
output ra_ird,
output ra_ir2,
output ra_ir1,
output xt2_o,
output xt1_o,
output xt0_o,
output ir_idat,
output pc_pcPlus4,
output istb_o,
output iadr_pc,
output pc_mbvec,
output ft0_o
);
wire isCsrRcI;
wire isCsrRc;
wire isCsrRsI;
wire isCsrRs;
wire isCsrRwI;
wire isCsrRw;
wire isMRet;
wire isEBreak;
wire isECall;
wire isFence;
wire isBr;
wire isJal;
wire isStore;
wire isLoad;
wire isLuiAuipc;
wire useAlu2;
wire useAlu;
wire fn3_is_111;
wire fn3_is_110;
wire fn3_is_101;
wire fn3_is_100;
wire fn3_is_011;
wire fn3_is_010;
wire fn3_is_001;
wire fn3_is_000;
wire isJalr;
wire isOpR;
wire isOpI;
wire R1391 = (|rst) ;
wire R1392 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) ;
wire R1393 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) & ~(|iack_i) ;
wire R1394 = ~(|rst) & (|ft0) & ~(|take_irq) & ~(|trap_o) & (|iack_i) ;
wire R1395 = ~(|rst) & ~(|take_irq) & (|trap) ;
wire R1396 = ~(|rst) & (|ft0) & (|take_irq) ;
wire R1397 = ~(|rst) & ~(|trap) & ~(|ft0) & ~(|xt0) & ~(|xt1) & ~(|xt2) & ~(|xt3) & ~(|xt4) ;
wire R1398 = ( ir[14:12] == 3'b000 ) ;
wire R1399 = ( ir[14:12] == 3'b001 ) ;
wire R1400 = ( ir[14:12] == 3'b010 ) ;
wire R1401 = ( ir[14:12] == 3'b011 ) ;
wire R1402 = ( ir[14:12] == 3'b100 ) ;
wire R1403 = ( ir[14:12] == 3'b101 ) ;
wire R1404 = ( ir[14:12] == 3'b110 ) ;
wire R1405 = ( ir[14:12] == 3'b111 ) ;
wire R1406 = ( ir[6:4] == 3'b001 ) & ( ir[2:0] == 3'b011 ) ;
wire R1407 = ( ir[6:4] == 3'b011 ) & ( ir[2:0] == 3'b011 ) ;
wire R1408 = ~(|rst) & (|xt0) & (|isOpI) ;
wire R1409 = ~(|rst) & (|xt1) & (|isOpI) ;
wire R1410 = ~(|rst) & (|xt2) & (|isOpI) ;
wire R1411 = (|useAlu) & (|fn3_is_000) ;
wire R1412 = (|useAlu) & (|fn3_is_001) ;
wire R1413 = (|useAlu) & (|fn3_is_010) ;
wire R1414 = (|useAlu) & (|fn3_is_011) ;
wire R1415 = (|useAlu) & (|fn3_is_100) ;
wire R1416 = (|useAlu) & (|fn3_is_101) & ~(|ir[30]) ;
wire R1417 = (|useAlu) & (|fn3_is_101) & (|ir[30]) ;
wire R1418 = (|useAlu) & (|fn3_is_110) ;
wire R1419 = (|useAlu) & (|fn3_is_111) ;
wire R1420 = (|useAlu) & (|ir[3]) ;
wire R1421 = ~(|rst) & (|xt0) & (|isOpR) ;
wire R1422 = ~(|rst) & (|xt1) & (|isOpR) ;
wire R1423 = ~(|rst) & (|xt2) & (|isOpR) ;
wire R1424 = ~(|rst) & (|xt3) & (|isOpR) ;
wire R1425 = (|useAlu2) & (|fn3_is_000) & ~(|ir[30]) ;
wire R1426 = (|useAlu2) & (|fn3_is_000) & (|ir[30]) ;
wire R1427 = (|useAlu2) & (|fn3_is_001) ;
wire R1428 = (|useAlu2) & (|fn3_is_010) ;
wire R1429 = (|useAlu2) & (|fn3_is_011) ;
wire R1430 = (|useAlu2) & (|fn3_is_100) ;
wire R1431 = (|useAlu2) & (|fn3_is_101) & ~(|ir[30]) ;
wire R1432 = (|useAlu2) & (|fn3_is_101) & (|ir[30]) ;
wire R1433 = (|useAlu2) & (|fn3_is_110) ;
wire R1434 = (|useAlu2) & (|fn3_is_111) ;
wire R1435 = (|useAlu2) & (|ir[3]) ;
wire R1436 = ( ir[6:0] == 7'b1100111 ) ;
wire R1437 = ( ir[6:0] == 7'b1101111 ) ;
wire R1438 = ~(|rst) & (|xt0) & (|isJalr) ;
wire R1439 = ~(|rst) & (|xt1) & (|isJalr) ;
wire R1440 = ~(|rst) & (|xt2) & (|isJalr) ;
wire R1441 = ~(|rst) & (|xt3) & (|isJalr) ;
wire R1442 = ~(|rst) & (|xt0) & (|isJal) ;
wire R1443 = ~(|rst) & (|xt1) & (|isJal) ;
wire R1444 = ~(|rst) & (|xt2) & (|isJal) ;
wire R1445 = ~(|ir[6]) & ( ir[4:0] == 5'b10111 ) ;
wire R1446 = ~(|rst) & (|xt0) & (|isLuiAuipc) ;
wire R1447 = ~(|rst) & (|xt0) & (|isLuiAuipc) & (|ir[5]) ;
wire R1448 = ~(|rst) & (|xt0) & (|isLuiAuipc) & ~(|ir[5]) ;
wire R1449 = ~(|rst) & (|xt1) & (|isLuiAuipc) ;
wire R1450 = ( ir[6:0] == 7'b0000011 ) ;
wire R1451 = ( ir[6:0] == 7'b0100011 ) ;
wire R1452 = ~(|rst) & (|xt0) & (|isLoad) ;
wire R1453 = ~(|rst) & (|xt1) & (|isLoad) ;
wire R1454 = ~(|rst) & (|xt2) & (|isLoad) & ~(|dack_i) ;
wire R1455 = ~(|rst) & (|xt2) & (|isLoad) & (|dack_i) ;
wire R1456 = ~(|rst) & (|xt0) & (|isStore) ;
wire R1457 = ~(|rst) & (|xt1) & (|isStore) ;
wire R1458 = ~(|rst) & (|xt2) & (|isStore) & ~(|dack_i) ;
wire R1459 = ~(|rst) & (|xt2) & (|isStore) & (|dack_i) ;
wire R1460 = ( ir[6:0] == 7'b1100011 ) ;
wire R1461 = ~(|rst) & (|xt0) & (|isBr) ;
wire R1462 = ~(|rst) & (|xt1) & (|isBr) ;
wire R1463 = ~(|rst) & (|xt2) & (|isBr) ;
wire R1464 = ~(|rst) & (|xt3) & (|isBr) ;
wire R1465 = ~(|rst) & (|xt4) & (|isBr) ;
wire R1466 = (|isBr) & (|xt4) & (|fn3_is_000) & (|ccr[0]) ;
wire R1467 = (|isBr) & (|xt4) & (|fn3_is_001) & (|ccr[1]) ;
wire R1468 = (|isBr) & (|xt4) & (|fn3_is_100) & (|ccr[4]) ;
wire R1469 = (|isBr) & (|xt4) & (|fn3_is_101) & (|ccr[5]) ;
wire R1470 = (|isBr) & (|xt4) & (|fn3_is_110) & (|ccr[6]) ;
wire R1471 = (|isBr) & (|xt4) & (|fn3_is_111) & (|ccr[7]) ;
wire R1472 = ( ir[31:28] == 4'b0000 ) & ( ir[19:0] == 20'h0000F ) ;
wire R1473 = ( ir[31:0] == 32'h0000100F ) ;
wire R1474 = ~(|rst) & (|isFence) & (|xt0) ;
wire R1475 = ~(|rst) & (|isFence) & (|xt1) ;
wire R1476 = ~(|rst) & (|isFence) & (|xt2) ;
wire R1477 = ~(|rst) & (|isFence) & (|xt3) ;
wire R1478 = ( ir[31:0] == 32'b0000_0000_0000_00000_000_00000_1110011 ) ;
wire R1479 = ( ir[31:0] == 32'b0000_0000_0001_00000_000_00000_1110011 ) ;
wire R1480 = ~(|rst) & (|isECall) & (|xt0) ;
wire R1481 = ~(|rst) & (|isEBreak) & (|xt0) ;
wire R1482 = ( ir[31:0] == 32'b0011_0000_0010_00000_000_00000_1110011 ) ;
wire R1483 = ~(|rst) & (|isMRet) & (|xt0) ;
wire R1484 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_001) ;
wire R1485 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_010) ;
wire R1486 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_011) ;
wire R1487 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_101) ;
wire R1488 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_110) ;
wire R1489 = ( ir[6:0] == 7'b1110011 ) & (|fn3_is_111) ;
wire R1490 = ~(|rst) & (|isCsrRw) & (|xt0) & (|csrok_i) ;
wire R1491 = ~(|rst) & (|isCsrRw) & (|xt1) ;
wire R1492 = ~(|rst) & (|isCsrRwI) & (|xt0) & (|csrok_i) ;
wire R1493 = ~(|rst) & (|isCsrRwI) & (|xt1) ;
wire R1494 = ~(|rst) & (|isCsrRs) & (|xt0) & (|csrok_i) ;
wire R1495 = ~(|rst) & (|isCsrRs) & (|xt1) ;
wire R1496 = ~(|rst) & (|isCsrRs) & (|xt2) ;
wire R1497 = ~(|rst) & (|isCsrRsI) & (|xt0) & (|csrok_i) ;
wire R1498 = ~(|rst) & (|isCsrRsI) & (|xt1) ;
wire R1499 = ~(|rst) & (|isCsrRsI) & (|xt2) ;
wire R1500 = ~(|rst) & (|isCsrRc) & (|xt0) & (|csrok_i) ;
wire R1501 = ~(|rst) & (|isCsrRc) & (|xt1) ;
wire R1502 = ~(|rst) & (|isCsrRc) & (|xt2) ;
wire R1503 = ~(|rst) & (|isCsrRcI) & (|xt0) & (|csrok_i) ;
wire R1504 = ~(|rst) & (|isCsrRcI) & (|xt1) ;
wire R1505 = ~(|rst) & (|isCsrRcI) & (|xt2) ;
wire out1506 = R1391 ? 1 : 0 ;
wire out1507 = R1391 ? 1 : 0 ;
wire out1508 = R1391 ? 1 : 0 ;
wire out1509 = R1391 ? 1 : 0 ;
wire out1510 = R1392 ? 1 : 0 ;
wire out1511 = R1392 ? 1 : 0 ;
wire out1512 = R1393 ? 1 : 0 ;
wire out1513 = R1394 ? 1 : 0 ;
wire out1514 = R1394 ? 1 : 0 ;
wire out1515 = R1394 ? 1 : 0 ;
wire out1516 = R1394 ? 1 : 0 ;
wire out1517 = R1395 ? 1 : 0 ;
wire out1518 = R1395 ? 1 : 0 ;
wire out1519 = R1395 ? 1 : 0 ;
wire out1520 = R1395 ? 1 : 0 ;
wire out1521 = R1395 ? 1 : 0 ;
wire out1522 = R1396 ? 1 : 0 ;
wire out1523 = R1396 ? 1 : 0 ;
wire out1524 = R1396 ? 1 : 0 ;
wire out1525 = R1396 ? 1 : 0 ;
wire out1526 = R1396 ? 1 : 0 ;
wire out1527 = R1396 ? 1 : 0 ;
wire out1528 = R1396 ? 1 : 0 ;
wire out1529 = R1397 ? 1 : 0 ;
wire out1530 = R1397 ? 1 : 0 ;
wire out1531 = R1398 ? 1 : 0 ;
wire out1532 = R1399 ? 1 : 0 ;
wire out1533 = R1400 ? 1 : 0 ;
wire out1534 = R1401 ? 1 : 0 ;
wire out1535 = R1402 ? 1 : 0 ;
wire out1536 = R1403 ? 1 : 0 ;
wire out1537 = R1404 ? 1 : 0 ;
wire out1538 = R1405 ? 1 : 0 ;
wire out1539 = R1406 ? 1 : 0 ;
wire out1540 = R1407 ? 1 : 0 ;
wire out1541 = R1408 ? 1 : 0 ;
wire out1542 = R1408 ? 1 : 0 ;
wire out1543 = R1409 ? 1 : 0 ;
wire out1544 = R1409 ? 1 : 0 ;
wire out1545 = R1409 ? 1 : 0 ;
wire out1546 = R1410 ? 1 : 0 ;
wire out1547 = R1410 ? 1 : 0 ;
wire out1548 = R1410 ? 1 : 0 ;
wire out1549 = R1410 ? 1 : 0 ;
wire out1550 = R1410 ? 1 : 0 ;
wire out1551 = R1411 ? 1 : 0 ;
wire out1552 = R1412 ? 1 : 0 ;
wire out1553 = R1413 ? 1 : 0 ;
wire out1554 = R1413 ? 1 : 0 ;
wire out1555 = R1413 ? 1 : 0 ;
wire out1556 = R1414 ? 1 : 0 ;
wire out1557 = R1414 ? 1 : 0 ;
wire out1558 = R1414 ? 1 : 0 ;
wire out1559 = R1415 ? 1 : 0 ;
wire out1560 = R1416 ? 1 : 0 ;
wire out1561 = R1417 ? 1 : 0 ;
wire out1562 = R1417 ? 1 : 0 ;
wire out1563 = R1418 ? 1 : 0 ;
wire out1564 = R1418 ? 1 : 0 ;
wire out1565 = R1419 ? 1 : 0 ;
wire out1566 = R1420 ? 1 : 0 ;
wire out1567 = R1421 ? 1 : 0 ;
wire out1568 = R1421 ? 1 : 0 ;
wire out1569 = R1422 ? 1 : 0 ;
wire out1570 = R1422 ? 1 : 0 ;
wire out1571 = R1422 ? 1 : 0 ;
wire out1572 = R1423 ? 1 : 0 ;
wire out1573 = R1423 ? 1 : 0 ;
wire out1574 = R1424 ? 1 : 0 ;
wire out1575 = R1424 ? 1 : 0 ;
wire out1576 = R1424 ? 1 : 0 ;
wire out1577 = R1424 ? 1 : 0 ;
wire out1578 = R1424 ? 1 : 0 ;
wire out1579 = R1425 ? 1 : 0 ;
wire out1580 = R1426 ? 1 : 0 ;
wire out1581 = R1426 ? 1 : 0 ;
wire out1582 = R1426 ? 1 : 0 ;
wire out1583 = R1427 ? 1 : 0 ;
wire out1584 = R1428 ? 1 : 0 ;
wire out1585 = R1428 ? 1 : 0 ;
wire out1586 = R1428 ? 1 : 0 ;
wire out1587 = R1429 ? 1 : 0 ;
wire out1588 = R1429 ? 1 : 0 ;
wire out1589 = R1429 ? 1 : 0 ;
wire out1590 = R1430 ? 1 : 0 ;
wire out1591 = R1431 ? 1 : 0 ;
wire out1592 = R1432 ? 1 : 0 ;
wire out1593 = R1432 ? 1 : 0 ;
wire out1594 = R1433 ? 1 : 0 ;
wire out1595 = R1433 ? 1 : 0 ;
wire out1596 = R1434 ? 1 : 0 ;
wire out1597 = R1435 ? 1 : 0 ;
wire out1598 = R1436 ? 1 : 0 ;
wire out1599 = R1437 ? 1 : 0 ;
wire out1600 = R1438 ? 1 : 0 ;
wire out1601 = R1438 ? 1 : 0 ;
wire out1602 = R1438 ? 1 : 0 ;
wire out1603 = R1438 ? 1 : 0 ;
wire out1604 = R1439 ? 1 : 0 ;
wire out1605 = R1439 ? 1 : 0 ;
wire out1606 = R1440 ? 1 : 0 ;
wire out1607 = R1440 ? 1 : 0 ;
wire out1608 = R1440 ? 1 : 0 ;
wire out1609 = R1441 ? 1 : 0 ;
wire out1610 = R1441 ? 1 : 0 ;
wire out1611 = R1441 ? 1 : 0 ;
wire out1612 = R1442 ? 1 : 0 ;
wire out1613 = R1442 ? 1 : 0 ;
wire out1614 = R1442 ? 1 : 0 ;
wire out1615 = R1442 ? 1 : 0 ;
wire out1616 = R1443 ? 1 : 0 ;
wire out1617 = R1443 ? 1 : 0 ;
wire out1618 = R1443 ? 1 : 0 ;
wire out1619 = R1444 ? 1 : 0 ;
wire out1620 = R1444 ? 1 : 0 ;
wire out1621 = R1444 ? 1 : 0 ;
wire out1622 = R1445 ? 1 : 0 ;
wire out1623 = R1446 ? 1 : 0 ;
wire out1624 = R1446 ? 1 : 0 ;
wire out1625 = R1447 ? 1 : 0 ;
wire out1626 = R1448 ? 1 : 0 ;
wire out1627 = R1449 ? 1 : 0 ;
wire out1628 = R1449 ? 1 : 0 ;
wire out1629 = R1449 ? 1 : 0 ;
wire out1630 = R1449 ? 1 : 0 ;
wire out1631 = R1449 ? 1 : 0 ;
wire out1632 = R1450 ? 1 : 0 ;
wire out1633 = R1451 ? 1 : 0 ;
wire out1634 = R1452 ? 1 : 0 ;
wire out1635 = R1452 ? 1 : 0 ;
wire out1636 = R1453 ? 1 : 0 ;
wire out1637 = R1453 ? 1 : 0 ;
wire out1638 = R1453 ? 1 : 0 ;
wire out1639 = R1454 ? 1 : 0 ;
wire out1640 = R1454 ? 1 : 0 ;
wire out1641 = R1454 ? 1 : 0 ;
wire out1642 = R1454 ? 1 : 0 ;
wire out1643 = R1454 ? 1 : 0 ;
wire out1644 = R1454 ? 1 : 0 ;
wire out1645 = R1455 ? 1 : 0 ;
wire out1646 = R1455 ? 1 : 0 ;
wire out1647 = R1455 ? 1 : 0 ;
wire out1648 = R1455 ? 1 : 0 ;
wire out1649 = R1455 ? 1 : 0 ;
wire out1650 = R1455 ? 1 : 0 ;
wire out1651 = R1455 ? 1 : 0 ;
wire out1652 = R1455 ? 1 : 0 ;
wire out1653 = R1455 ? 1 : 0 ;
wire out1654 = R1456 ? 1 : 0 ;
wire out1655 = R1456 ? 1 : 0 ;
wire out1656 = R1457 ? 1 : 0 ;
wire out1657 = R1457 ? 1 : 0 ;
wire out1658 = R1457 ? 1 : 0 ;
wire out1659 = R1457 ? 1 : 0 ;
wire out1660 = R1458 ? 1 : 0 ;
wire out1661 = R1458 ? 1 : 0 ;
wire out1662 = R1458 ? 1 : 0 ;
wire out1663 = R1458 ? 1 : 0 ;
wire out1664 = R1458 ? 1 : 0 ;
wire out1665 = R1458 ? 1 : 0 ;
wire out1666 = R1458 ? 1 : 0 ;
wire out1667 = R1458 ? 1 : 0 ;
wire out1668 = R1458 ? 1 : 0 ;
wire out1669 = R1459 ? 1 : 0 ;
wire out1670 = R1459 ? 1 : 0 ;
wire out1671 = R1459 ? 1 : 0 ;
wire out1672 = R1459 ? 1 : 0 ;
wire out1673 = R1459 ? 1 : 0 ;
wire out1674 = R1459 ? 1 : 0 ;
wire out1675 = R1459 ? 1 : 0 ;
wire out1676 = R1459 ? 1 : 0 ;
wire out1677 = R1460 ? 1 : 0 ;
wire out1678 = R1461 ? 1 : 0 ;
wire out1679 = R1461 ? 1 : 0 ;
wire out1680 = R1462 ? 1 : 0 ;
wire out1681 = R1462 ? 1 : 0 ;
wire out1682 = R1462 ? 1 : 0 ;
wire out1683 = R1463 ? 1 : 0 ;
wire out1684 = R1463 ? 1 : 0 ;
wire out1685 = R1464 ? 1 : 0 ;
wire out1686 = R1464 ? 1 : 0 ;
wire out1687 = R1464 ? 1 : 0 ;
wire out1688 = R1464 ? 1 : 0 ;
wire out1689 = R1464 ? 1 : 0 ;
wire out1690 = R1464 ? 1 : 0 ;
wire out1691 = R1464 ? 1 : 0 ;
wire out1692 = R1465 ? 1 : 0 ;
wire out1693 = R1465 ? 1 : 0 ;
wire out1694 = R1466 ? 1 : 0 ;
wire out1695 = R1467 ? 1 : 0 ;
wire out1696 = R1468 ? 1 : 0 ;
wire out1697 = R1469 ? 1 : 0 ;
wire out1698 = R1470 ? 1 : 0 ;
wire out1699 = R1471 ? 1 : 0 ;
wire out1700 = R1472 ? 1 : 0 ;
wire out1701 = R1473 ? 1 : 0 ;
wire out1702 = R1474 ? 1 : 0 ;
wire out1703 = R1474 ? 1 : 0 ;
wire out1704 = R1475 ? 1 : 0 ;
wire out1705 = R1475 ? 1 : 0 ;
wire out1706 = R1476 ? 1 : 0 ;
wire out1707 = R1476 ? 1 : 0 ;
wire out1708 = R1477 ? 1 : 0 ;
wire out1709 = R1477 ? 1 : 0 ;
wire out1710 = R1478 ? 1 : 0 ;
wire out1711 = R1479 ? 1 : 0 ;
wire out1712 = R1480 ? 1 : 0 ;
wire out1713 = R1480 ? 1 : 0 ;
wire out1714 = R1481 ? 1 : 0 ;
wire out1715 = R1481 ? 1 : 0 ;
wire out1716 = R1482 ? 1 : 0 ;
wire out1717 = R1483 ? 1 : 0 ;
wire out1718 = R1483 ? 1 : 0 ;
wire out1719 = R1483 ? 1 : 0 ;
wire out1720 = R1483 ? 1 : 0 ;
wire out1721 = R1484 ? 1 : 0 ;
wire out1722 = R1485 ? 1 : 0 ;
wire out1723 = R1486 ? 1 : 0 ;
wire out1724 = R1487 ? 1 : 0 ;
wire out1725 = R1488 ? 1 : 0 ;
wire out1726 = R1489 ? 1 : 0 ;
wire out1727 = R1490 ? 1 : 0 ;
wire out1728 = R1490 ? 1 : 0 ;
wire out1729 = R1491 ? 1 : 0 ;
wire out1730 = R1491 ? 1 : 0 ;
wire out1731 = R1491 ? 1 : 0 ;
wire out1732 = R1491 ? 1 : 0 ;
wire out1733 = R1491 ? 1 : 0 ;
wire out1734 = R1491 ? 1 : 0 ;
wire out1735 = R1491 ? 1 : 0 ;
wire out1736 = R1492 ? 1 : 0 ;
wire out1737 = R1493 ? 1 : 0 ;
wire out1738 = R1493 ? 1 : 0 ;
wire out1739 = R1493 ? 1 : 0 ;
wire out1740 = R1493 ? 1 : 0 ;
wire out1741 = R1493 ? 1 : 0 ;
wire out1742 = R1493 ? 1 : 0 ;
wire out1743 = R1493 ? 1 : 0 ;
wire out1744 = R1494 ? 1 : 0 ;
wire out1745 = R1494 ? 1 : 0 ;
wire out1746 = R1495 ? 1 : 0 ;
wire out1747 = R1495 ? 1 : 0 ;
wire out1748 = R1495 ? 1 : 0 ;
wire out1749 = R1495 ? 1 : 0 ;
wire out1750 = R1495 ? 1 : 0 ;
wire out1751 = R1495 ? 1 : 0 ;
wire out1752 = R1495 ? 1 : 0 ;
wire out1753 = R1496 ? 1 : 0 ;
wire out1754 = R1496 ? 1 : 0 ;
wire out1755 = R1496 ? 1 : 0 ;
wire out1756 = R1496 ? 1 : 0 ;
wire out1757 = R1496 ? 1 : 0 ;
wire out1758 = R1497 ? 1 : 0 ;
wire out1759 = R1498 ? 1 : 0 ;
wire out1760 = R1498 ? 1 : 0 ;
wire out1761 = R1498 ? 1 : 0 ;
wire out1762 = R1498 ? 1 : 0 ;
wire out1763 = R1498 ? 1 : 0 ;
wire out1764 = R1498 ? 1 : 0 ;
wire out1765 = R1498 ? 1 : 0 ;
wire out1766 = R1499 ? 1 : 0 ;
wire out1767 = R1499 ? 1 : 0 ;
wire out1768 = R1499 ? 1 : 0 ;
wire out1769 = R1499 ? 1 : 0 ;
wire out1770 = R1499 ? 1 : 0 ;
wire out1771 = R1500 ? 1 : 0 ;
wire out1772 = R1500 ? 1 : 0 ;
wire out1773 = R1501 ? 1 : 0 ;
wire out1774 = R1501 ? 1 : 0 ;
wire out1775 = R1501 ? 1 : 0 ;
wire out1776 = R1501 ? 1 : 0 ;
wire out1777 = R1501 ? 1 : 0 ;
wire out1778 = R1501 ? 1 : 0 ;
wire out1779 = R1501 ? 1 : 0 ;
wire out1780 = R1502 ? 1 : 0 ;
wire out1781 = R1502 ? 1 : 0 ;
wire out1782 = R1502 ? 1 : 0 ;
wire out1783 = R1502 ? 1 : 0 ;
wire out1784 = R1502 ? 1 : 0 ;
wire out1785 = R1503 ? 1 : 0 ;
wire out1786 = R1504 ? 1 : 0 ;
wire out1787 = R1504 ? 1 : 0 ;
wire out1788 = R1504 ? 1 : 0 ;
wire out1789 = R1504 ? 1 : 0 ;
wire out1790 = R1504 ? 1 : 0 ;
wire out1791 = R1504 ? 1 : 0 ;
wire out1792 = R1504 ? 1 : 0 ;
wire out1793 = R1505 ? 1 : 0 ;
wire out1794 = R1505 ? 1 : 0 ;
wire out1795 = R1505 ? 1 : 0 ;
wire out1796 = R1505 ? 1 : 0 ;
wire out1797 = R1505 ? 1 : 0 ;
assign dsiz_fn3 = out1673|out1665|out1649|out1644;
assign isBr = out1677;
assign isFence = out1701|out1700;
assign isLoad = out1632;
assign invB_en = out1794|out1781|out1687|out1588|out1585|out1582|out1557|out1554;
assign ia_pc = out1514;
assign cflag_i = out1688|out1593|out1587|out1584|out1581|out1562|out1556|out1553;
assign and_en = out1793|out1780|out1766|out1753|out1596|out1594|out1565|out1563;
assign isJalr = out1598;
assign isCsrRs = out1722;
assign alua_ia = out1690|out1626|out1617;
assign isLuiAuipc = out1622;
assign fn3_is_000 = out1531;
assign isCsrRw = out1721;
assign coe_o = out1789|out1776|out1762|out1749|out1739|out1731;
assign mepc_ia = out1517;
assign fn3_is_001 = out1532;
assign fn3_is_010 = out1533;
assign fn3_is_100 = out1535;
assign fn3_is_011 = out1534;
assign fn3_is_101 = out1536;
assign fn3_is_110 = out1537;
assign fence_o = out1709|out1707|out1705|out1703;
assign fn3_is_111 = out1538;
assign iadr_pc = out1510;
assign useAlu = out1549;
assign ra_ird = out1787|out1774|out1760|out1747|out1737|out1729|out1650|out1627|out1613|out1601|out1574|out1546;
assign cwe_o = out1796|out1783|out1769|out1756|out1742|out1734;
assign dwe_o = out1675|out1668;
assign alua_cdat = out1791|out1778|out1764|out1751;
assign mepc_pc = out1522;
assign pc_mepc = out1718;
assign pc_alu = out1699|out1698|out1697|out1696|out1695|out1694|out1620|out1610;
assign dadr_alu = out1670|out1662|out1646|out1641;
assign ccr_alu = out1689;
assign cdat_alu = out1795|out1782|out1768|out1755;
assign pc_mbvec = out1507;
assign mcause_11 = out1713|out1526;
assign ir_idat = out1515;
assign lsh_en = out1583|out1552;
assign rdat_pc = out1614|out1602;
assign rdat_cdat = out1788|out1775|out1761|out1748|out1738|out1730;
assign cdat_rdat = out1733;
assign rdat_ddat = out1652;
assign ddat_rdat = out1674|out1666;
assign mpie_mie = out1524|out1519;
assign mie_mpie = out1719;
assign rsh_en = out1592|out1591|out1561|out1560;
assign istb_o = out1511;
assign rwe_o = out1790|out1777|out1763|out1750|out1740|out1732|out1651|out1629|out1615|out1603|out1576|out1548;
assign alua_rdat = out1682|out1657|out1637|out1607|out1570|out1544;
assign alub_imm12i = out1638|out1608|out1545;
assign sx32_en = out1597|out1566;
assign alub_rdat = out1779|out1752|out1684|out1573;
assign rdat_alu = out1628|out1575|out1547;
assign trap_o = out1714|out1712|out1529;
assign lts_en = out1586|out1555;
assign isStore = out1633;
assign sum_en = out1693|out1686|out1669|out1661|out1645|out1640|out1630|out1621|out1611|out1580|out1579|out1551;
assign ltu_en = out1589|out1558;
assign pc_mtvec = out1523|out1518;
assign alub_imm12sb = out1691;
assign xor_en = out1767|out1754|out1595|out1590|out1564|out1559;
assign alub_imm12s = out1658;
assign alub_imm20u = out1624;
assign mie_0 = out1525|out1520|out1508;
assign alub_imm20uj = out1618;
assign alua_0 = out1625;
assign dcyc_1 = out1671|out1663|out1647|out1642;
assign isECall = out1710;
assign isCsrRcI = out1726;
assign mpie_1 = out1720|out1509;
assign mcause_irq_o = out1527;
assign ft0_o = out1797|out1784|out1770|out1757|out1743|out1735|out1717|out1708|out1692|out1676|out1653|out1631|out1619|out1609|out1578|out1550|out1528|out1521|out1512|out1506;
assign useAlu2 = out1577;
assign dstb_1 = out1672|out1664|out1648|out1643;
assign ra_ir1 = out1772|out1745|out1728|out1679|out1655|out1635|out1605|out1568|out1542;
assign isEBreak = out1711;
assign ra_ir2 = out1681|out1667|out1659|out1571;
assign mcause_2 = out1530;
assign cdat_imm5 = out1741;
assign isOpI = out1539;
assign mcause_3 = out1715;
assign isCsrRsI = out1725;
assign pc_pcPlus4 = out1513;
assign xt0_o = out1516;
assign isCsrRwI = out1724;
assign xt1_o = out1785|out1771|out1758|out1744|out1736|out1727|out1702|out1678|out1654|out1634|out1623|out1612|out1600|out1567|out1541;
assign alub_imm5 = out1792|out1765;
assign xt2_o = out1786|out1773|out1759|out1746|out1704|out1680|out1660|out1656|out1639|out1636|out1616|out1604|out1569|out1543;
assign isOpR = out1540;
assign xt3_o = out1706|out1683|out1606|out1572;
assign xt4_o = out1685;
assign isMRet = out1716;
assign isCsrRc = out1723;
assign isJal = out1599;
endmodule
|
// Testbench for ltcminer_icarus.v
`timescale 1ns/1ps
`ifdef SIM // Avoids wrong top selected if included in ISE/PlanAhead sources
module test_ltcminer ();
reg clk = 1'b0;
reg [31:0] cycle = 32'd0;
initial begin
clk = 0;
while(1)
begin
#5 clk = 1; #5 clk = 0;
end
end
always @ (posedge clk)
begin
cycle <= cycle + 32'd1;
end
// Running with default zero's for the data1..3 regs.
// tx_hash=553a4b69b43913a61b42013ce210f713eaa7332e48cda1bdf3b93b10161d0876 at 187,990 nS and
// final_hash (if SIM is defined) at 188,000 nS with golden_nonce_match flag NOT set since it is
// not a diff=32 share. To test golden_nonce, just tweak the target eg 31'hffffffff will match everything
// With serial input(at comm_clk_frequency=1_000_000), we get rx_done at t=70,220nS, however there is already a
// PBKDF2_SHA256_80_128 loaded in Xbuf (for nonce=00000001). The first final_hash at 188,000 nS is corrupted as
// the input data has changed from all 0's. The Xbuf starts salsa rom at t=188,000 but the nonce is incorrectly
// taken from the newly loaded data so once salsa in complete it also generates a corrupt final_hash at ~362,000 nS.
// Nonce is incremented then the newly loaded data starts PBKDF2_SHA256_80_128, so we must supply a nonce 1 less
// than the expected golden_nonce. The correct PBKDF2_SHA256_80_128 is ready at ~ 197,000 nS. We get final_hash for
// the corrupted work at ~362,000 nS then our required golden_nonce is at 536,180 nS.
// This is only really a problem for simulation. With live hashing we just lose 2 nonces every time getwork is
// loaded, which isn't a big deal.
wire RxD;
wire TxD;
wire extminer_rxd = 0;
wire extminer_txd;
wire [3:0] dip = 0;
wire [3:0] led;
wire TMP_SCL=1, TMP_SDA=1, TMP_ALERT=1;
parameter comm_clk_frequency = 1_000_000; // Speeds up serial loading enormously rx_done is at t=70,220nS
parameter baud_rate = 115_200;
ltcminer_icarus #(.comm_clk_frequency(comm_clk_frequency)) uut
(clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
// Send serial data - 84 bytes, matches on nonce 318f (included in data)
// NB starting nonce is 381e NOT 381f (see note above)
// NORMAL...
// reg [671:0] data = 672'h000007ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
// DYNPLL...
reg [671:0] data = 672'h55aa07ff0000318e7e71441b141fe951b2b0c7dfc791d4646240fc2a2d1b80900020a24dc501ef1599fc48ed6cbac920af75575618e7b1e8eaf0b62a90d1942ea64d250357e9a09c063a47827c57b44e01000000;
reg serial_send = 0;
wire serial_busy;
reg [31:0] data_32 = 0;
reg [31:0] start_cycle = 0;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(baud_rate)) sertx (.clk(clk), .TxD(RxD), .send(serial_send), .busy(serial_busy), .word(data_32));
// TUNE this according to comm_clk_frequency so we send a single getwork (else it gets overwritten with 0's)
// parameter stop_cycle = 7020; // For comm_clk_frequency=1_000_000
parameter stop_cycle = 0; // Use this to DISABLE sending data
always @ (posedge clk)
begin
serial_send <= 0; // Default
// Send data every time tx goes idle (NB the !serial_send is to prevent serial_send
// going high for two cycles since serial_busy arrives one cycle after serial_send)
if (cycle > 5 && cycle < stop_cycle && !serial_busy && !serial_send)
begin
serial_send <= 1;
data_32 <= data[671:640];
data <= { data[639:0], 32'd0 };
start_cycle <= cycle; // Remember each start cycle (makes debugging easier)
end
end
endmodule
`endif |
module binary_multiplier(
input clock, reset, start,
input [7:0] multiplicand, multiplier,
output [15:0] product,
output Ready
);
wire Load_regs, Decr_P, Add_regs, Shift_regs, Nothing, Zero, Q0;
controller_bm m0(clock, reset, start, Nothing, Zero, Q0, Ready, Load_regs, Decr_P, Add_regs, Shift_regs);
datapath_bm m1(clock, reset, multiplicand, multiplier, Load_regs, Decr_P, Add_regs, Shift_regs,
product, Nothing, Zero, Q0);
endmodule
module controller_bm(
input clock, reset, start, Nothing, Zero, Q0,
output reg Ready, Load_regs, Decr_P, Add_regs, Shift_regs
);
parameter S_idle = 2'b00;
parameter S_add = 2'b01;
parameter S_shift = 2'b10;
reg [1:0] state, next_state;
always @(posedge clock, posedge reset)
if (reset)
state <= S_idle;
else
state <= next_state;
always @(*)
begin
Load_regs = 0;
Decr_P = 0;
Add_regs = 0;
Shift_regs = 0;
Ready = 0;
case (state)
S_idle: begin
if (start) begin
next_state = S_add;
Load_regs = 1;
end else
next_state = S_idle;
Ready = 1;
end
S_add: begin
next_state = S_shift;
Decr_P = 1;
if (Q0) Add_regs = 1;
end
S_shift: begin
next_state = (Zero | Nothing) ? S_idle : S_add;
Shift_regs = 1;
end
default: next_state = S_idle;
endcase
end
endmodule
module datapath_bm(
input clock, reset,
input [7:0] multiplicand, multiplier,
input Load_regs, Decr_P, Add_regs, Shift_regs,
output [15:0] product,
output reg Nothing,
output Zero, Q0
);
parameter m_size = 8;
reg [7:0] A, B, Q;
reg C;
reg [3:0] P;
wire [7:0] M;
always @(posedge clock, posedge reset)
begin
if (reset) begin
A <= 0;
C <= 0;
B <= 0;
Q <= 0;
P <= m_size;
end else begin
if (Load_regs) begin
A = 0;
C = 0;
B = multiplicand;
Q = multiplier;
P = m_size;
end else begin
if (Add_regs) {C, A} = A + B;
if (Shift_regs) {C, A, Q} = {C, A, Q} >> 1;
if (Decr_P) P = P-1;
end
end
end
always @(*)
begin
if (Load_regs) begin
Nothing = ~|{multiplicand, multiplier};
end else begin
Nothing = M == 0 || B == 0;
end
end
assign product = {A, Q} >> P;
assign M = Q << (m_size - P - 1);
assign Zero = P == 4'b0;
assign Q0 = Q[0];
endmodule
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_b2s_wr_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_b2s_wr_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_awready ,
input wire s_awvalid ,
output wire m_awvalid ,
input wire m_awready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
output wire b_push ,
input wire b_full ,
output wire a_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE_WAIT = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] next_state;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
end else begin
state <= next_state;
end
end
// Next state transitions.
always @( * )
begin
next_state = state;
case (state)
SM_IDLE:
if (s_awvalid) begin
next_state = SM_CMD_EN;
end else
next_state = state;
SM_CMD_EN:
if (m_awready & next_pending)
next_state = SM_CMD_ACCEPTED;
else if (m_awready & ~next_pending & b_full)
next_state = SM_DONE_WAIT;
else if (m_awready & ~next_pending & ~b_full)
next_state = SM_IDLE;
else
next_state = state;
SM_CMD_ACCEPTED:
next_state = SM_CMD_EN;
SM_DONE_WAIT:
if (!b_full)
next_state = SM_IDLE;
else
next_state = state;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_awvalid = (state == SM_CMD_EN);
assign next = ((state == SM_CMD_ACCEPTED)
| (((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE))) ;
assign a_push = (state == SM_IDLE);
assign s_awready = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
assign b_push = ((state == SM_CMD_EN) | (state == SM_DONE_WAIT)) & (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
// ==============================================================
// RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.2
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ===========================================================
`timescale 1 ns / 1 ps
(* CORE_GENERATION_INFO="axi_interfaces,hls_ip_2017_2,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc7k160tfbg484-1,HLS_INPUT_CLOCK=4.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=4.162500,HLS_SYN_LAT=5,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=2139,HLS_SYN_LUT=1196}" *)
module axi_interfaces (
ap_clk,
ap_rst_n,
d_o_0_TREADY,
d_o_1_TREADY,
d_o_2_TREADY,
d_o_3_TREADY,
d_o_4_TREADY,
d_o_5_TREADY,
d_o_6_TREADY,
d_o_7_TREADY,
d_o_0_TDATA,
d_o_0_TVALID,
d_o_1_TDATA,
d_o_1_TVALID,
d_o_2_TDATA,
d_o_2_TVALID,
d_o_3_TDATA,
d_o_3_TVALID,
d_o_4_TDATA,
d_o_4_TVALID,
d_o_5_TDATA,
d_o_5_TVALID,
d_o_6_TDATA,
d_o_6_TVALID,
d_o_7_TDATA,
d_o_7_TVALID,
d_i_0_TDATA,
d_i_0_TVALID,
d_i_0_TREADY,
d_i_1_TDATA,
d_i_1_TVALID,
d_i_1_TREADY,
d_i_2_TDATA,
d_i_2_TVALID,
d_i_2_TREADY,
d_i_3_TDATA,
d_i_3_TVALID,
d_i_3_TREADY,
d_i_4_TDATA,
d_i_4_TVALID,
d_i_4_TREADY,
d_i_5_TDATA,
d_i_5_TVALID,
d_i_5_TREADY,
d_i_6_TDATA,
d_i_6_TVALID,
d_i_6_TREADY,
d_i_7_TDATA,
d_i_7_TVALID,
d_i_7_TREADY,
s_axi_AXILiteS_AWVALID,
s_axi_AXILiteS_AWREADY,
s_axi_AXILiteS_AWADDR,
s_axi_AXILiteS_WVALID,
s_axi_AXILiteS_WREADY,
s_axi_AXILiteS_WDATA,
s_axi_AXILiteS_WSTRB,
s_axi_AXILiteS_ARVALID,
s_axi_AXILiteS_ARREADY,
s_axi_AXILiteS_ARADDR,
s_axi_AXILiteS_RVALID,
s_axi_AXILiteS_RREADY,
s_axi_AXILiteS_RDATA,
s_axi_AXILiteS_RRESP,
s_axi_AXILiteS_BVALID,
s_axi_AXILiteS_BREADY,
s_axi_AXILiteS_BRESP,
interrupt
);
parameter ap_ST_fsm_state1 = 2'd1;
parameter ap_ST_fsm_pp0_stage0 = 2'd2;
parameter C_S_AXI_AXILITES_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_ADDR_WIDTH = 4;
parameter C_S_AXI_DATA_WIDTH = 32;
parameter C_S_AXI_AXILITES_WSTRB_WIDTH = (32 / 8);
parameter C_S_AXI_WSTRB_WIDTH = (32 / 8);
input ap_clk;
input ap_rst_n;
input d_o_0_TREADY;
input d_o_1_TREADY;
input d_o_2_TREADY;
input d_o_3_TREADY;
input d_o_4_TREADY;
input d_o_5_TREADY;
input d_o_6_TREADY;
input d_o_7_TREADY;
output [15:0] d_o_0_TDATA;
output d_o_0_TVALID;
output [15:0] d_o_1_TDATA;
output d_o_1_TVALID;
output [15:0] d_o_2_TDATA;
output d_o_2_TVALID;
output [15:0] d_o_3_TDATA;
output d_o_3_TVALID;
output [15:0] d_o_4_TDATA;
output d_o_4_TVALID;
output [15:0] d_o_5_TDATA;
output d_o_5_TVALID;
output [15:0] d_o_6_TDATA;
output d_o_6_TVALID;
output [15:0] d_o_7_TDATA;
output d_o_7_TVALID;
input [15:0] d_i_0_TDATA;
input d_i_0_TVALID;
output d_i_0_TREADY;
input [15:0] d_i_1_TDATA;
input d_i_1_TVALID;
output d_i_1_TREADY;
input [15:0] d_i_2_TDATA;
input d_i_2_TVALID;
output d_i_2_TREADY;
input [15:0] d_i_3_TDATA;
input d_i_3_TVALID;
output d_i_3_TREADY;
input [15:0] d_i_4_TDATA;
input d_i_4_TVALID;
output d_i_4_TREADY;
input [15:0] d_i_5_TDATA;
input d_i_5_TVALID;
output d_i_5_TREADY;
input [15:0] d_i_6_TDATA;
input d_i_6_TVALID;
output d_i_6_TREADY;
input [15:0] d_i_7_TDATA;
input d_i_7_TVALID;
output d_i_7_TREADY;
input s_axi_AXILiteS_AWVALID;
output s_axi_AXILiteS_AWREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_AWADDR;
input s_axi_AXILiteS_WVALID;
output s_axi_AXILiteS_WREADY;
input [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_WDATA;
input [C_S_AXI_AXILITES_WSTRB_WIDTH - 1:0] s_axi_AXILiteS_WSTRB;
input s_axi_AXILiteS_ARVALID;
output s_axi_AXILiteS_ARREADY;
input [C_S_AXI_AXILITES_ADDR_WIDTH - 1:0] s_axi_AXILiteS_ARADDR;
output s_axi_AXILiteS_RVALID;
input s_axi_AXILiteS_RREADY;
output [C_S_AXI_AXILITES_DATA_WIDTH - 1:0] s_axi_AXILiteS_RDATA;
output [1:0] s_axi_AXILiteS_RRESP;
output s_axi_AXILiteS_BVALID;
input s_axi_AXILiteS_BREADY;
output [1:0] s_axi_AXILiteS_BRESP;
output interrupt;
reg ap_rst_n_inv;
wire ap_start;
reg ap_done;
reg ap_idle;
(* fsm_encoding = "none" *) reg [1:0] ap_CS_fsm;
wire ap_CS_fsm_state1;
reg ap_ready;
wire [0:0] exitcond_fu_246_p2;
wire ap_CS_fsm_pp0_stage0;
wire ap_enable_reg_pp0_iter0;
wire ap_block_state2_pp0_stage0_iter0;
wire d_i_0_0_vld_out;
wire d_i_1_0_vld_out;
wire d_i_2_0_vld_out;
wire d_i_3_0_vld_out;
wire d_i_4_0_vld_out;
wire d_i_5_0_vld_out;
wire d_i_6_0_vld_out;
wire d_i_7_0_vld_out;
reg ap_block_state4_pp0_stage0_iter1;
wire d_o_0_1_ack_in;
wire d_o_1_1_ack_in;
wire d_o_2_1_ack_in;
wire d_o_3_1_ack_in;
wire d_o_4_1_ack_in;
wire d_o_5_1_ack_in;
wire d_o_6_1_ack_in;
wire d_o_7_1_ack_in;
reg ap_block_state4_io;
reg ap_enable_reg_pp0_iter1;
reg ap_block_state3_pp0_stage0_iter2;
reg ap_block_state3_io;
reg ap_enable_reg_pp0_iter2;
reg ap_block_pp0_stage0_flag00011001;
reg [15:0] d_o_0_1_data_out;
reg d_o_0_1_vld_in;
wire d_o_0_1_vld_out;
wire d_o_0_1_ack_out;
reg [15:0] d_o_0_1_payload_A;
reg [15:0] d_o_0_1_payload_B;
reg d_o_0_1_sel_rd;
reg d_o_0_1_sel_wr;
wire d_o_0_1_sel;
wire d_o_0_1_load_A;
wire d_o_0_1_load_B;
reg [1:0] d_o_0_1_state;
wire d_o_0_1_state_cmp_full;
reg [15:0] d_o_1_1_data_out;
reg d_o_1_1_vld_in;
wire d_o_1_1_vld_out;
wire d_o_1_1_ack_out;
reg [15:0] d_o_1_1_payload_A;
reg [15:0] d_o_1_1_payload_B;
reg d_o_1_1_sel_rd;
reg d_o_1_1_sel_wr;
wire d_o_1_1_sel;
wire d_o_1_1_load_A;
wire d_o_1_1_load_B;
reg [1:0] d_o_1_1_state;
wire d_o_1_1_state_cmp_full;
reg [15:0] d_o_2_1_data_out;
reg d_o_2_1_vld_in;
wire d_o_2_1_vld_out;
wire d_o_2_1_ack_out;
reg [15:0] d_o_2_1_payload_A;
reg [15:0] d_o_2_1_payload_B;
reg d_o_2_1_sel_rd;
reg d_o_2_1_sel_wr;
wire d_o_2_1_sel;
wire d_o_2_1_load_A;
wire d_o_2_1_load_B;
reg [1:0] d_o_2_1_state;
wire d_o_2_1_state_cmp_full;
reg [15:0] d_o_3_1_data_out;
reg d_o_3_1_vld_in;
wire d_o_3_1_vld_out;
wire d_o_3_1_ack_out;
reg [15:0] d_o_3_1_payload_A;
reg [15:0] d_o_3_1_payload_B;
reg d_o_3_1_sel_rd;
reg d_o_3_1_sel_wr;
wire d_o_3_1_sel;
wire d_o_3_1_load_A;
wire d_o_3_1_load_B;
reg [1:0] d_o_3_1_state;
wire d_o_3_1_state_cmp_full;
reg [15:0] d_o_4_1_data_out;
reg d_o_4_1_vld_in;
wire d_o_4_1_vld_out;
wire d_o_4_1_ack_out;
reg [15:0] d_o_4_1_payload_A;
reg [15:0] d_o_4_1_payload_B;
reg d_o_4_1_sel_rd;
reg d_o_4_1_sel_wr;
wire d_o_4_1_sel;
wire d_o_4_1_load_A;
wire d_o_4_1_load_B;
reg [1:0] d_o_4_1_state;
wire d_o_4_1_state_cmp_full;
reg [15:0] d_o_5_1_data_out;
reg d_o_5_1_vld_in;
wire d_o_5_1_vld_out;
wire d_o_5_1_ack_out;
reg [15:0] d_o_5_1_payload_A;
reg [15:0] d_o_5_1_payload_B;
reg d_o_5_1_sel_rd;
reg d_o_5_1_sel_wr;
wire d_o_5_1_sel;
wire d_o_5_1_load_A;
wire d_o_5_1_load_B;
reg [1:0] d_o_5_1_state;
wire d_o_5_1_state_cmp_full;
reg [15:0] d_o_6_1_data_out;
reg d_o_6_1_vld_in;
wire d_o_6_1_vld_out;
wire d_o_6_1_ack_out;
reg [15:0] d_o_6_1_payload_A;
reg [15:0] d_o_6_1_payload_B;
reg d_o_6_1_sel_rd;
reg d_o_6_1_sel_wr;
wire d_o_6_1_sel;
wire d_o_6_1_load_A;
wire d_o_6_1_load_B;
reg [1:0] d_o_6_1_state;
wire d_o_6_1_state_cmp_full;
reg [15:0] d_o_7_1_data_out;
reg d_o_7_1_vld_in;
wire d_o_7_1_vld_out;
wire d_o_7_1_ack_out;
reg [15:0] d_o_7_1_payload_A;
reg [15:0] d_o_7_1_payload_B;
reg d_o_7_1_sel_rd;
reg d_o_7_1_sel_wr;
wire d_o_7_1_sel;
wire d_o_7_1_load_A;
wire d_o_7_1_load_B;
reg [1:0] d_o_7_1_state;
wire d_o_7_1_state_cmp_full;
reg [15:0] d_i_0_0_data_out;
wire d_i_0_0_vld_in;
wire d_i_0_0_ack_in;
reg d_i_0_0_ack_out;
reg [15:0] d_i_0_0_payload_A;
reg [15:0] d_i_0_0_payload_B;
reg d_i_0_0_sel_rd;
reg d_i_0_0_sel_wr;
wire d_i_0_0_sel;
wire d_i_0_0_load_A;
wire d_i_0_0_load_B;
reg [1:0] d_i_0_0_state;
wire d_i_0_0_state_cmp_full;
reg [15:0] d_i_1_0_data_out;
wire d_i_1_0_vld_in;
wire d_i_1_0_ack_in;
reg d_i_1_0_ack_out;
reg [15:0] d_i_1_0_payload_A;
reg [15:0] d_i_1_0_payload_B;
reg d_i_1_0_sel_rd;
reg d_i_1_0_sel_wr;
wire d_i_1_0_sel;
wire d_i_1_0_load_A;
wire d_i_1_0_load_B;
reg [1:0] d_i_1_0_state;
wire d_i_1_0_state_cmp_full;
reg [15:0] d_i_2_0_data_out;
wire d_i_2_0_vld_in;
wire d_i_2_0_ack_in;
reg d_i_2_0_ack_out;
reg [15:0] d_i_2_0_payload_A;
reg [15:0] d_i_2_0_payload_B;
reg d_i_2_0_sel_rd;
reg d_i_2_0_sel_wr;
wire d_i_2_0_sel;
wire d_i_2_0_load_A;
wire d_i_2_0_load_B;
reg [1:0] d_i_2_0_state;
wire d_i_2_0_state_cmp_full;
reg [15:0] d_i_3_0_data_out;
wire d_i_3_0_vld_in;
wire d_i_3_0_ack_in;
reg d_i_3_0_ack_out;
reg [15:0] d_i_3_0_payload_A;
reg [15:0] d_i_3_0_payload_B;
reg d_i_3_0_sel_rd;
reg d_i_3_0_sel_wr;
wire d_i_3_0_sel;
wire d_i_3_0_load_A;
wire d_i_3_0_load_B;
reg [1:0] d_i_3_0_state;
wire d_i_3_0_state_cmp_full;
reg [15:0] d_i_4_0_data_out;
wire d_i_4_0_vld_in;
wire d_i_4_0_ack_in;
reg d_i_4_0_ack_out;
reg [15:0] d_i_4_0_payload_A;
reg [15:0] d_i_4_0_payload_B;
reg d_i_4_0_sel_rd;
reg d_i_4_0_sel_wr;
wire d_i_4_0_sel;
wire d_i_4_0_load_A;
wire d_i_4_0_load_B;
reg [1:0] d_i_4_0_state;
wire d_i_4_0_state_cmp_full;
reg [15:0] d_i_5_0_data_out;
wire d_i_5_0_vld_in;
wire d_i_5_0_ack_in;
reg d_i_5_0_ack_out;
reg [15:0] d_i_5_0_payload_A;
reg [15:0] d_i_5_0_payload_B;
reg d_i_5_0_sel_rd;
reg d_i_5_0_sel_wr;
wire d_i_5_0_sel;
wire d_i_5_0_load_A;
wire d_i_5_0_load_B;
reg [1:0] d_i_5_0_state;
wire d_i_5_0_state_cmp_full;
reg [15:0] d_i_6_0_data_out;
wire d_i_6_0_vld_in;
wire d_i_6_0_ack_in;
reg d_i_6_0_ack_out;
reg [15:0] d_i_6_0_payload_A;
reg [15:0] d_i_6_0_payload_B;
reg d_i_6_0_sel_rd;
reg d_i_6_0_sel_wr;
wire d_i_6_0_sel;
wire d_i_6_0_load_A;
wire d_i_6_0_load_B;
reg [1:0] d_i_6_0_state;
wire d_i_6_0_state_cmp_full;
reg [15:0] d_i_7_0_data_out;
wire d_i_7_0_vld_in;
wire d_i_7_0_ack_in;
reg d_i_7_0_ack_out;
reg [15:0] d_i_7_0_payload_A;
reg [15:0] d_i_7_0_payload_B;
reg d_i_7_0_sel_rd;
reg d_i_7_0_sel_wr;
wire d_i_7_0_sel;
wire d_i_7_0_load_A;
wire d_i_7_0_load_B;
reg [1:0] d_i_7_0_state;
wire d_i_7_0_state_cmp_full;
reg [31:0] acc_0;
reg [31:0] acc_1;
reg [31:0] acc_2;
reg [31:0] acc_3;
reg [31:0] acc_4;
reg [31:0] acc_5;
reg [31:0] acc_6;
reg [31:0] acc_7;
reg d_o_0_TDATA_blk_n;
wire ap_block_pp0_stage0_flag00000000;
reg d_o_1_TDATA_blk_n;
reg d_o_2_TDATA_blk_n;
reg d_o_3_TDATA_blk_n;
reg d_o_4_TDATA_blk_n;
reg d_o_5_TDATA_blk_n;
reg d_o_6_TDATA_blk_n;
reg d_o_7_TDATA_blk_n;
reg d_i_0_TDATA_blk_n;
reg d_i_1_TDATA_blk_n;
reg d_i_2_TDATA_blk_n;
reg d_i_3_TDATA_blk_n;
reg d_i_4_TDATA_blk_n;
reg d_i_5_TDATA_blk_n;
reg d_i_6_TDATA_blk_n;
reg d_i_7_TDATA_blk_n;
reg [4:0] i1_reg_218;
wire [4:0] tmp_17_fu_242_p1;
reg [4:0] tmp_17_reg_502;
reg [0:0] exitcond_reg_507;
reg [0:0] ap_reg_pp0_iter1_exitcond_reg_507;
wire [15:0] tmp_8_fu_278_p2;
wire [15:0] tmp_2_1_fu_309_p2;
wire [15:0] tmp_2_2_fu_340_p2;
wire [15:0] tmp_2_3_fu_371_p2;
wire [15:0] tmp_2_4_fu_402_p2;
wire [15:0] tmp_2_5_fu_433_p2;
wire [15:0] tmp_2_6_fu_464_p2;
wire [15:0] tmp_2_7_fu_495_p2;
reg ap_block_pp0_stage0_flag00011011;
reg [4:0] i1_phi_fu_222_p6;
wire [31:0] tmp_1_fu_266_p2;
wire [31:0] tmp_1_1_fu_297_p2;
wire [31:0] tmp_1_2_fu_328_p2;
wire [31:0] tmp_1_3_fu_359_p2;
wire [31:0] tmp_1_4_fu_390_p2;
wire [31:0] tmp_1_5_fu_421_p2;
wire [31:0] tmp_1_6_fu_452_p2;
wire [31:0] tmp_1_7_fu_483_p2;
reg ap_block_pp0_stage0_flag00001001;
wire [5:0] i1_cast_fu_232_p1;
wire [5:0] i_1_7_fu_236_p2;
wire signed [31:0] tmp1_fu_258_p1;
wire [15:0] tmp_2_fu_262_p1;
wire signed [31:0] tmp_s_fu_289_p1;
wire [15:0] tmp_10_fu_293_p1;
wire signed [31:0] tmp_9_fu_320_p1;
wire [15:0] tmp_11_fu_324_p1;
wire signed [31:0] tmp_3_fu_351_p1;
wire [15:0] tmp_12_fu_355_p1;
wire signed [31:0] tmp_4_fu_382_p1;
wire [15:0] tmp_13_fu_386_p1;
wire signed [31:0] tmp_5_fu_413_p1;
wire [15:0] tmp_14_fu_417_p1;
wire signed [31:0] tmp_6_fu_444_p1;
wire [15:0] tmp_15_fu_448_p1;
wire signed [31:0] tmp_7_fu_475_p1;
wire [15:0] tmp_16_fu_479_p1;
reg [1:0] ap_NS_fsm;
reg ap_idle_pp0_0to1;
reg ap_reset_idle_pp0;
reg ap_idle_pp0;
wire ap_enable_pp0;
reg ap_condition_1051;
// power-on initialization
initial begin
#0 ap_CS_fsm = 2'd1;
#0 ap_enable_reg_pp0_iter1 = 1'b0;
#0 ap_enable_reg_pp0_iter2 = 1'b0;
#0 d_o_0_1_sel_rd = 1'b0;
#0 d_o_0_1_sel_wr = 1'b0;
#0 d_o_0_1_state = 2'd0;
#0 d_o_1_1_sel_rd = 1'b0;
#0 d_o_1_1_sel_wr = 1'b0;
#0 d_o_1_1_state = 2'd0;
#0 d_o_2_1_sel_rd = 1'b0;
#0 d_o_2_1_sel_wr = 1'b0;
#0 d_o_2_1_state = 2'd0;
#0 d_o_3_1_sel_rd = 1'b0;
#0 d_o_3_1_sel_wr = 1'b0;
#0 d_o_3_1_state = 2'd0;
#0 d_o_4_1_sel_rd = 1'b0;
#0 d_o_4_1_sel_wr = 1'b0;
#0 d_o_4_1_state = 2'd0;
#0 d_o_5_1_sel_rd = 1'b0;
#0 d_o_5_1_sel_wr = 1'b0;
#0 d_o_5_1_state = 2'd0;
#0 d_o_6_1_sel_rd = 1'b0;
#0 d_o_6_1_sel_wr = 1'b0;
#0 d_o_6_1_state = 2'd0;
#0 d_o_7_1_sel_rd = 1'b0;
#0 d_o_7_1_sel_wr = 1'b0;
#0 d_o_7_1_state = 2'd0;
#0 d_i_0_0_sel_rd = 1'b0;
#0 d_i_0_0_sel_wr = 1'b0;
#0 d_i_0_0_state = 2'd0;
#0 d_i_1_0_sel_rd = 1'b0;
#0 d_i_1_0_sel_wr = 1'b0;
#0 d_i_1_0_state = 2'd0;
#0 d_i_2_0_sel_rd = 1'b0;
#0 d_i_2_0_sel_wr = 1'b0;
#0 d_i_2_0_state = 2'd0;
#0 d_i_3_0_sel_rd = 1'b0;
#0 d_i_3_0_sel_wr = 1'b0;
#0 d_i_3_0_state = 2'd0;
#0 d_i_4_0_sel_rd = 1'b0;
#0 d_i_4_0_sel_wr = 1'b0;
#0 d_i_4_0_state = 2'd0;
#0 d_i_5_0_sel_rd = 1'b0;
#0 d_i_5_0_sel_wr = 1'b0;
#0 d_i_5_0_state = 2'd0;
#0 d_i_6_0_sel_rd = 1'b0;
#0 d_i_6_0_sel_wr = 1'b0;
#0 d_i_6_0_state = 2'd0;
#0 d_i_7_0_sel_rd = 1'b0;
#0 d_i_7_0_sel_wr = 1'b0;
#0 d_i_7_0_state = 2'd0;
#0 acc_0 = 32'd0;
#0 acc_1 = 32'd0;
#0 acc_2 = 32'd0;
#0 acc_3 = 32'd0;
#0 acc_4 = 32'd0;
#0 acc_5 = 32'd0;
#0 acc_6 = 32'd0;
#0 acc_7 = 32'd0;
end
axi_interfaces_AXILiteS_s_axi #(
.C_S_AXI_ADDR_WIDTH( C_S_AXI_AXILITES_ADDR_WIDTH ),
.C_S_AXI_DATA_WIDTH( C_S_AXI_AXILITES_DATA_WIDTH ))
axi_interfaces_AXILiteS_s_axi_U(
.AWVALID(s_axi_AXILiteS_AWVALID),
.AWREADY(s_axi_AXILiteS_AWREADY),
.AWADDR(s_axi_AXILiteS_AWADDR),
.WVALID(s_axi_AXILiteS_WVALID),
.WREADY(s_axi_AXILiteS_WREADY),
.WDATA(s_axi_AXILiteS_WDATA),
.WSTRB(s_axi_AXILiteS_WSTRB),
.ARVALID(s_axi_AXILiteS_ARVALID),
.ARREADY(s_axi_AXILiteS_ARREADY),
.ARADDR(s_axi_AXILiteS_ARADDR),
.RVALID(s_axi_AXILiteS_RVALID),
.RREADY(s_axi_AXILiteS_RREADY),
.RDATA(s_axi_AXILiteS_RDATA),
.RRESP(s_axi_AXILiteS_RRESP),
.BVALID(s_axi_AXILiteS_BVALID),
.BREADY(s_axi_AXILiteS_BREADY),
.BRESP(s_axi_AXILiteS_BRESP),
.ACLK(ap_clk),
.ARESET(ap_rst_n_inv),
.ACLK_EN(1'b1),
.ap_start(ap_start),
.interrupt(interrupt),
.ap_ready(ap_ready),
.ap_done(ap_done),
.ap_idle(ap_idle)
);
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_CS_fsm <= ap_ST_fsm_state1;
end else begin
ap_CS_fsm <= ap_NS_fsm;
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end else begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011011 == 1'b0))) begin
ap_enable_reg_pp0_iter1 <= ap_start;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter1 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end else begin
if ((ap_block_pp0_stage0_flag00011011 == 1'b0)) begin
ap_enable_reg_pp0_iter2 <= ap_enable_reg_pp0_iter1;
end else if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_enable_reg_pp0_iter2 <= 1'b0;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_0_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_0_0_ack_out) & (1'b1 == d_i_0_0_vld_out))) begin
d_i_0_0_sel_rd <= ~d_i_0_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_0_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_in))) begin
d_i_0_0_sel_wr <= ~d_i_0_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_0_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_out) & (2'd3 == d_i_0_0_state)) | ((1'b0 == d_i_0_0_vld_in) & (2'd2 == d_i_0_0_state)))) begin
d_i_0_0_state <= 2'd2;
end else if ((((1'b1 == d_i_0_0_vld_in) & (1'b0 == d_i_0_0_ack_out) & (2'd3 == d_i_0_0_state)) | ((1'b0 == d_i_0_0_ack_out) & (2'd1 == d_i_0_0_state)))) begin
d_i_0_0_state <= 2'd1;
end else if ((((1'b1 == d_i_0_0_vld_in) & (2'd2 == d_i_0_0_state)) | ((1'b1 == d_i_0_0_ack_out) & (2'd1 == d_i_0_0_state)) | ((2'd3 == d_i_0_0_state) & ~((1'b1 == d_i_0_0_vld_in) & (1'b0 == d_i_0_0_ack_out)) & ~((1'b0 == d_i_0_0_vld_in) & (1'b1 == d_i_0_0_ack_out))))) begin
d_i_0_0_state <= 2'd3;
end else begin
d_i_0_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_1_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_1_0_ack_out) & (1'b1 == d_i_1_0_vld_out))) begin
d_i_1_0_sel_rd <= ~d_i_1_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_1_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_in))) begin
d_i_1_0_sel_wr <= ~d_i_1_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_1_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_out) & (2'd3 == d_i_1_0_state)) | ((1'b0 == d_i_1_0_vld_in) & (2'd2 == d_i_1_0_state)))) begin
d_i_1_0_state <= 2'd2;
end else if ((((1'b1 == d_i_1_0_vld_in) & (1'b0 == d_i_1_0_ack_out) & (2'd3 == d_i_1_0_state)) | ((1'b0 == d_i_1_0_ack_out) & (2'd1 == d_i_1_0_state)))) begin
d_i_1_0_state <= 2'd1;
end else if ((((1'b1 == d_i_1_0_vld_in) & (2'd2 == d_i_1_0_state)) | ((1'b1 == d_i_1_0_ack_out) & (2'd1 == d_i_1_0_state)) | ((2'd3 == d_i_1_0_state) & ~((1'b1 == d_i_1_0_vld_in) & (1'b0 == d_i_1_0_ack_out)) & ~((1'b0 == d_i_1_0_vld_in) & (1'b1 == d_i_1_0_ack_out))))) begin
d_i_1_0_state <= 2'd3;
end else begin
d_i_1_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_2_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_2_0_ack_out) & (1'b1 == d_i_2_0_vld_out))) begin
d_i_2_0_sel_rd <= ~d_i_2_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_2_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_in))) begin
d_i_2_0_sel_wr <= ~d_i_2_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_2_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_out) & (2'd3 == d_i_2_0_state)) | ((1'b0 == d_i_2_0_vld_in) & (2'd2 == d_i_2_0_state)))) begin
d_i_2_0_state <= 2'd2;
end else if ((((1'b1 == d_i_2_0_vld_in) & (1'b0 == d_i_2_0_ack_out) & (2'd3 == d_i_2_0_state)) | ((1'b0 == d_i_2_0_ack_out) & (2'd1 == d_i_2_0_state)))) begin
d_i_2_0_state <= 2'd1;
end else if ((((1'b1 == d_i_2_0_vld_in) & (2'd2 == d_i_2_0_state)) | ((1'b1 == d_i_2_0_ack_out) & (2'd1 == d_i_2_0_state)) | ((2'd3 == d_i_2_0_state) & ~((1'b1 == d_i_2_0_vld_in) & (1'b0 == d_i_2_0_ack_out)) & ~((1'b0 == d_i_2_0_vld_in) & (1'b1 == d_i_2_0_ack_out))))) begin
d_i_2_0_state <= 2'd3;
end else begin
d_i_2_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_3_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_3_0_ack_out) & (1'b1 == d_i_3_0_vld_out))) begin
d_i_3_0_sel_rd <= ~d_i_3_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_3_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_in))) begin
d_i_3_0_sel_wr <= ~d_i_3_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_3_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_out) & (2'd3 == d_i_3_0_state)) | ((1'b0 == d_i_3_0_vld_in) & (2'd2 == d_i_3_0_state)))) begin
d_i_3_0_state <= 2'd2;
end else if ((((1'b1 == d_i_3_0_vld_in) & (1'b0 == d_i_3_0_ack_out) & (2'd3 == d_i_3_0_state)) | ((1'b0 == d_i_3_0_ack_out) & (2'd1 == d_i_3_0_state)))) begin
d_i_3_0_state <= 2'd1;
end else if ((((1'b1 == d_i_3_0_vld_in) & (2'd2 == d_i_3_0_state)) | ((1'b1 == d_i_3_0_ack_out) & (2'd1 == d_i_3_0_state)) | ((2'd3 == d_i_3_0_state) & ~((1'b1 == d_i_3_0_vld_in) & (1'b0 == d_i_3_0_ack_out)) & ~((1'b0 == d_i_3_0_vld_in) & (1'b1 == d_i_3_0_ack_out))))) begin
d_i_3_0_state <= 2'd3;
end else begin
d_i_3_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_4_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_4_0_ack_out) & (1'b1 == d_i_4_0_vld_out))) begin
d_i_4_0_sel_rd <= ~d_i_4_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_4_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_in))) begin
d_i_4_0_sel_wr <= ~d_i_4_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_4_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_out) & (2'd3 == d_i_4_0_state)) | ((1'b0 == d_i_4_0_vld_in) & (2'd2 == d_i_4_0_state)))) begin
d_i_4_0_state <= 2'd2;
end else if ((((1'b1 == d_i_4_0_vld_in) & (1'b0 == d_i_4_0_ack_out) & (2'd3 == d_i_4_0_state)) | ((1'b0 == d_i_4_0_ack_out) & (2'd1 == d_i_4_0_state)))) begin
d_i_4_0_state <= 2'd1;
end else if ((((1'b1 == d_i_4_0_vld_in) & (2'd2 == d_i_4_0_state)) | ((1'b1 == d_i_4_0_ack_out) & (2'd1 == d_i_4_0_state)) | ((2'd3 == d_i_4_0_state) & ~((1'b1 == d_i_4_0_vld_in) & (1'b0 == d_i_4_0_ack_out)) & ~((1'b0 == d_i_4_0_vld_in) & (1'b1 == d_i_4_0_ack_out))))) begin
d_i_4_0_state <= 2'd3;
end else begin
d_i_4_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_5_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_5_0_ack_out) & (1'b1 == d_i_5_0_vld_out))) begin
d_i_5_0_sel_rd <= ~d_i_5_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_5_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_in))) begin
d_i_5_0_sel_wr <= ~d_i_5_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_5_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_out) & (2'd3 == d_i_5_0_state)) | ((1'b0 == d_i_5_0_vld_in) & (2'd2 == d_i_5_0_state)))) begin
d_i_5_0_state <= 2'd2;
end else if ((((1'b1 == d_i_5_0_vld_in) & (1'b0 == d_i_5_0_ack_out) & (2'd3 == d_i_5_0_state)) | ((1'b0 == d_i_5_0_ack_out) & (2'd1 == d_i_5_0_state)))) begin
d_i_5_0_state <= 2'd1;
end else if ((((1'b1 == d_i_5_0_vld_in) & (2'd2 == d_i_5_0_state)) | ((1'b1 == d_i_5_0_ack_out) & (2'd1 == d_i_5_0_state)) | ((2'd3 == d_i_5_0_state) & ~((1'b1 == d_i_5_0_vld_in) & (1'b0 == d_i_5_0_ack_out)) & ~((1'b0 == d_i_5_0_vld_in) & (1'b1 == d_i_5_0_ack_out))))) begin
d_i_5_0_state <= 2'd3;
end else begin
d_i_5_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_6_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_6_0_ack_out) & (1'b1 == d_i_6_0_vld_out))) begin
d_i_6_0_sel_rd <= ~d_i_6_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_6_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_in))) begin
d_i_6_0_sel_wr <= ~d_i_6_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_6_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_out) & (2'd3 == d_i_6_0_state)) | ((1'b0 == d_i_6_0_vld_in) & (2'd2 == d_i_6_0_state)))) begin
d_i_6_0_state <= 2'd2;
end else if ((((1'b1 == d_i_6_0_vld_in) & (1'b0 == d_i_6_0_ack_out) & (2'd3 == d_i_6_0_state)) | ((1'b0 == d_i_6_0_ack_out) & (2'd1 == d_i_6_0_state)))) begin
d_i_6_0_state <= 2'd1;
end else if ((((1'b1 == d_i_6_0_vld_in) & (2'd2 == d_i_6_0_state)) | ((1'b1 == d_i_6_0_ack_out) & (2'd1 == d_i_6_0_state)) | ((2'd3 == d_i_6_0_state) & ~((1'b1 == d_i_6_0_vld_in) & (1'b0 == d_i_6_0_ack_out)) & ~((1'b0 == d_i_6_0_vld_in) & (1'b1 == d_i_6_0_ack_out))))) begin
d_i_6_0_state <= 2'd3;
end else begin
d_i_6_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_7_0_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_i_7_0_ack_out) & (1'b1 == d_i_7_0_vld_out))) begin
d_i_7_0_sel_rd <= ~d_i_7_0_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_7_0_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_in))) begin
d_i_7_0_sel_wr <= ~d_i_7_0_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_i_7_0_state <= 2'd0;
end else begin
if ((((1'b0 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_out) & (2'd3 == d_i_7_0_state)) | ((1'b0 == d_i_7_0_vld_in) & (2'd2 == d_i_7_0_state)))) begin
d_i_7_0_state <= 2'd2;
end else if ((((1'b1 == d_i_7_0_vld_in) & (1'b0 == d_i_7_0_ack_out) & (2'd3 == d_i_7_0_state)) | ((1'b0 == d_i_7_0_ack_out) & (2'd1 == d_i_7_0_state)))) begin
d_i_7_0_state <= 2'd1;
end else if ((((1'b1 == d_i_7_0_vld_in) & (2'd2 == d_i_7_0_state)) | ((1'b1 == d_i_7_0_ack_out) & (2'd1 == d_i_7_0_state)) | ((2'd3 == d_i_7_0_state) & ~((1'b1 == d_i_7_0_vld_in) & (1'b0 == d_i_7_0_ack_out)) & ~((1'b0 == d_i_7_0_vld_in) & (1'b1 == d_i_7_0_ack_out))))) begin
d_i_7_0_state <= 2'd3;
end else begin
d_i_7_0_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_0_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_0_1_ack_out) & (1'b1 == d_o_0_1_vld_out))) begin
d_o_0_1_sel_rd <= ~d_o_0_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_0_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_in))) begin
d_o_0_1_sel_wr <= ~d_o_0_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_0_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd3)) | ((1'b0 == d_o_0_1_vld_in) & (d_o_0_1_state == 2'd2)))) begin
d_o_0_1_state <= 2'd2;
end else if ((((1'b1 == d_o_0_1_vld_in) & (1'b0 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd3)) | ((1'b0 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd1)))) begin
d_o_0_1_state <= 2'd1;
end else if ((((1'b1 == d_o_0_1_vld_in) & (d_o_0_1_state == 2'd2)) | ((1'b1 == d_o_0_1_ack_out) & (d_o_0_1_state == 2'd1)) | ((d_o_0_1_state == 2'd3) & ~((1'b1 == d_o_0_1_vld_in) & (1'b0 == d_o_0_1_ack_out)) & ~((1'b0 == d_o_0_1_vld_in) & (1'b1 == d_o_0_1_ack_out))))) begin
d_o_0_1_state <= 2'd3;
end else begin
d_o_0_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_1_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_1_1_ack_out) & (1'b1 == d_o_1_1_vld_out))) begin
d_o_1_1_sel_rd <= ~d_o_1_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_1_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_in))) begin
d_o_1_1_sel_wr <= ~d_o_1_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_1_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_out) & (2'd3 == d_o_1_1_state)) | ((1'b0 == d_o_1_1_vld_in) & (2'd2 == d_o_1_1_state)))) begin
d_o_1_1_state <= 2'd2;
end else if ((((1'b1 == d_o_1_1_vld_in) & (1'b0 == d_o_1_1_ack_out) & (2'd3 == d_o_1_1_state)) | ((1'b0 == d_o_1_1_ack_out) & (2'd1 == d_o_1_1_state)))) begin
d_o_1_1_state <= 2'd1;
end else if ((((1'b1 == d_o_1_1_vld_in) & (2'd2 == d_o_1_1_state)) | ((1'b1 == d_o_1_1_ack_out) & (2'd1 == d_o_1_1_state)) | ((2'd3 == d_o_1_1_state) & ~((1'b1 == d_o_1_1_vld_in) & (1'b0 == d_o_1_1_ack_out)) & ~((1'b0 == d_o_1_1_vld_in) & (1'b1 == d_o_1_1_ack_out))))) begin
d_o_1_1_state <= 2'd3;
end else begin
d_o_1_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_2_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_2_1_ack_out) & (1'b1 == d_o_2_1_vld_out))) begin
d_o_2_1_sel_rd <= ~d_o_2_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_2_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_in))) begin
d_o_2_1_sel_wr <= ~d_o_2_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_2_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_out) & (2'd3 == d_o_2_1_state)) | ((1'b0 == d_o_2_1_vld_in) & (2'd2 == d_o_2_1_state)))) begin
d_o_2_1_state <= 2'd2;
end else if ((((1'b1 == d_o_2_1_vld_in) & (1'b0 == d_o_2_1_ack_out) & (2'd3 == d_o_2_1_state)) | ((1'b0 == d_o_2_1_ack_out) & (2'd1 == d_o_2_1_state)))) begin
d_o_2_1_state <= 2'd1;
end else if ((((1'b1 == d_o_2_1_vld_in) & (2'd2 == d_o_2_1_state)) | ((1'b1 == d_o_2_1_ack_out) & (2'd1 == d_o_2_1_state)) | ((2'd3 == d_o_2_1_state) & ~((1'b1 == d_o_2_1_vld_in) & (1'b0 == d_o_2_1_ack_out)) & ~((1'b0 == d_o_2_1_vld_in) & (1'b1 == d_o_2_1_ack_out))))) begin
d_o_2_1_state <= 2'd3;
end else begin
d_o_2_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_3_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_3_1_ack_out) & (1'b1 == d_o_3_1_vld_out))) begin
d_o_3_1_sel_rd <= ~d_o_3_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_3_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_in))) begin
d_o_3_1_sel_wr <= ~d_o_3_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_3_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_out) & (2'd3 == d_o_3_1_state)) | ((1'b0 == d_o_3_1_vld_in) & (2'd2 == d_o_3_1_state)))) begin
d_o_3_1_state <= 2'd2;
end else if ((((1'b1 == d_o_3_1_vld_in) & (1'b0 == d_o_3_1_ack_out) & (2'd3 == d_o_3_1_state)) | ((1'b0 == d_o_3_1_ack_out) & (2'd1 == d_o_3_1_state)))) begin
d_o_3_1_state <= 2'd1;
end else if ((((1'b1 == d_o_3_1_vld_in) & (2'd2 == d_o_3_1_state)) | ((1'b1 == d_o_3_1_ack_out) & (2'd1 == d_o_3_1_state)) | ((2'd3 == d_o_3_1_state) & ~((1'b1 == d_o_3_1_vld_in) & (1'b0 == d_o_3_1_ack_out)) & ~((1'b0 == d_o_3_1_vld_in) & (1'b1 == d_o_3_1_ack_out))))) begin
d_o_3_1_state <= 2'd3;
end else begin
d_o_3_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_4_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_4_1_ack_out) & (1'b1 == d_o_4_1_vld_out))) begin
d_o_4_1_sel_rd <= ~d_o_4_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_4_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_in))) begin
d_o_4_1_sel_wr <= ~d_o_4_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_4_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_out) & (2'd3 == d_o_4_1_state)) | ((1'b0 == d_o_4_1_vld_in) & (2'd2 == d_o_4_1_state)))) begin
d_o_4_1_state <= 2'd2;
end else if ((((1'b1 == d_o_4_1_vld_in) & (1'b0 == d_o_4_1_ack_out) & (2'd3 == d_o_4_1_state)) | ((1'b0 == d_o_4_1_ack_out) & (2'd1 == d_o_4_1_state)))) begin
d_o_4_1_state <= 2'd1;
end else if ((((1'b1 == d_o_4_1_vld_in) & (2'd2 == d_o_4_1_state)) | ((1'b1 == d_o_4_1_ack_out) & (2'd1 == d_o_4_1_state)) | ((2'd3 == d_o_4_1_state) & ~((1'b1 == d_o_4_1_vld_in) & (1'b0 == d_o_4_1_ack_out)) & ~((1'b0 == d_o_4_1_vld_in) & (1'b1 == d_o_4_1_ack_out))))) begin
d_o_4_1_state <= 2'd3;
end else begin
d_o_4_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_5_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_5_1_ack_out) & (1'b1 == d_o_5_1_vld_out))) begin
d_o_5_1_sel_rd <= ~d_o_5_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_5_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_in))) begin
d_o_5_1_sel_wr <= ~d_o_5_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_5_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_out) & (2'd3 == d_o_5_1_state)) | ((1'b0 == d_o_5_1_vld_in) & (2'd2 == d_o_5_1_state)))) begin
d_o_5_1_state <= 2'd2;
end else if ((((1'b1 == d_o_5_1_vld_in) & (1'b0 == d_o_5_1_ack_out) & (2'd3 == d_o_5_1_state)) | ((1'b0 == d_o_5_1_ack_out) & (2'd1 == d_o_5_1_state)))) begin
d_o_5_1_state <= 2'd1;
end else if ((((1'b1 == d_o_5_1_vld_in) & (2'd2 == d_o_5_1_state)) | ((1'b1 == d_o_5_1_ack_out) & (2'd1 == d_o_5_1_state)) | ((2'd3 == d_o_5_1_state) & ~((1'b1 == d_o_5_1_vld_in) & (1'b0 == d_o_5_1_ack_out)) & ~((1'b0 == d_o_5_1_vld_in) & (1'b1 == d_o_5_1_ack_out))))) begin
d_o_5_1_state <= 2'd3;
end else begin
d_o_5_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_6_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_6_1_ack_out) & (1'b1 == d_o_6_1_vld_out))) begin
d_o_6_1_sel_rd <= ~d_o_6_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_6_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_in))) begin
d_o_6_1_sel_wr <= ~d_o_6_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_6_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_out) & (2'd3 == d_o_6_1_state)) | ((1'b0 == d_o_6_1_vld_in) & (2'd2 == d_o_6_1_state)))) begin
d_o_6_1_state <= 2'd2;
end else if ((((1'b1 == d_o_6_1_vld_in) & (1'b0 == d_o_6_1_ack_out) & (2'd3 == d_o_6_1_state)) | ((1'b0 == d_o_6_1_ack_out) & (2'd1 == d_o_6_1_state)))) begin
d_o_6_1_state <= 2'd1;
end else if ((((1'b1 == d_o_6_1_vld_in) & (2'd2 == d_o_6_1_state)) | ((1'b1 == d_o_6_1_ack_out) & (2'd1 == d_o_6_1_state)) | ((2'd3 == d_o_6_1_state) & ~((1'b1 == d_o_6_1_vld_in) & (1'b0 == d_o_6_1_ack_out)) & ~((1'b0 == d_o_6_1_vld_in) & (1'b1 == d_o_6_1_ack_out))))) begin
d_o_6_1_state <= 2'd3;
end else begin
d_o_6_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_7_1_sel_rd <= 1'b0;
end else begin
if (((1'b1 == d_o_7_1_ack_out) & (1'b1 == d_o_7_1_vld_out))) begin
d_o_7_1_sel_rd <= ~d_o_7_1_sel_rd;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_7_1_sel_wr <= 1'b0;
end else begin
if (((1'b1 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_in))) begin
d_o_7_1_sel_wr <= ~d_o_7_1_sel_wr;
end
end
end
always @ (posedge ap_clk) begin
if (ap_rst_n_inv == 1'b1) begin
d_o_7_1_state <= 2'd0;
end else begin
if ((((1'b0 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_out) & (2'd3 == d_o_7_1_state)) | ((1'b0 == d_o_7_1_vld_in) & (2'd2 == d_o_7_1_state)))) begin
d_o_7_1_state <= 2'd2;
end else if ((((1'b1 == d_o_7_1_vld_in) & (1'b0 == d_o_7_1_ack_out) & (2'd3 == d_o_7_1_state)) | ((1'b0 == d_o_7_1_ack_out) & (2'd1 == d_o_7_1_state)))) begin
d_o_7_1_state <= 2'd1;
end else if ((((1'b1 == d_o_7_1_vld_in) & (2'd2 == d_o_7_1_state)) | ((1'b1 == d_o_7_1_ack_out) & (2'd1 == d_o_7_1_state)) | ((2'd3 == d_o_7_1_state) & ~((1'b1 == d_o_7_1_vld_in) & (1'b0 == d_o_7_1_ack_out)) & ~((1'b0 == d_o_7_1_vld_in) & (1'b1 == d_o_7_1_ack_out))))) begin
d_o_7_1_state <= 2'd3;
end else begin
d_o_7_1_state <= 2'd2;
end
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd0 == exitcond_reg_507))) begin
i1_reg_218 <= tmp_17_reg_502;
end else if ((((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd1 == exitcond_reg_507)))) begin
i1_reg_218 <= 5'd0;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
acc_0 <= tmp_1_fu_266_p2;
acc_1 <= tmp_1_1_fu_297_p2;
acc_2 <= tmp_1_2_fu_328_p2;
acc_3 <= tmp_1_3_fu_359_p2;
acc_4 <= tmp_1_4_fu_390_p2;
acc_5 <= tmp_1_5_fu_421_p2;
acc_6 <= tmp_1_6_fu_452_p2;
acc_7 <= tmp_1_7_fu_483_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_reg_pp0_iter1_exitcond_reg_507 <= exitcond_reg_507;
exitcond_reg_507 <= exitcond_fu_246_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_0_0_load_A)) begin
d_i_0_0_payload_A <= d_i_0_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_0_0_load_B)) begin
d_i_0_0_payload_B <= d_i_0_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_1_0_load_A)) begin
d_i_1_0_payload_A <= d_i_1_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_1_0_load_B)) begin
d_i_1_0_payload_B <= d_i_1_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_2_0_load_A)) begin
d_i_2_0_payload_A <= d_i_2_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_2_0_load_B)) begin
d_i_2_0_payload_B <= d_i_2_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_3_0_load_A)) begin
d_i_3_0_payload_A <= d_i_3_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_3_0_load_B)) begin
d_i_3_0_payload_B <= d_i_3_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_4_0_load_A)) begin
d_i_4_0_payload_A <= d_i_4_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_4_0_load_B)) begin
d_i_4_0_payload_B <= d_i_4_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_5_0_load_A)) begin
d_i_5_0_payload_A <= d_i_5_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_5_0_load_B)) begin
d_i_5_0_payload_B <= d_i_5_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_6_0_load_A)) begin
d_i_6_0_payload_A <= d_i_6_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_6_0_load_B)) begin
d_i_6_0_payload_B <= d_i_6_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_7_0_load_A)) begin
d_i_7_0_payload_A <= d_i_7_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_i_7_0_load_B)) begin
d_i_7_0_payload_B <= d_i_7_TDATA;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_0_1_load_A)) begin
d_o_0_1_payload_A <= tmp_8_fu_278_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_0_1_load_B)) begin
d_o_0_1_payload_B <= tmp_8_fu_278_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_1_1_load_A)) begin
d_o_1_1_payload_A <= tmp_2_1_fu_309_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_1_1_load_B)) begin
d_o_1_1_payload_B <= tmp_2_1_fu_309_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_2_1_load_A)) begin
d_o_2_1_payload_A <= tmp_2_2_fu_340_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_2_1_load_B)) begin
d_o_2_1_payload_B <= tmp_2_2_fu_340_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_3_1_load_A)) begin
d_o_3_1_payload_A <= tmp_2_3_fu_371_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_3_1_load_B)) begin
d_o_3_1_payload_B <= tmp_2_3_fu_371_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_4_1_load_A)) begin
d_o_4_1_payload_A <= tmp_2_4_fu_402_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_4_1_load_B)) begin
d_o_4_1_payload_B <= tmp_2_4_fu_402_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_5_1_load_A)) begin
d_o_5_1_payload_A <= tmp_2_5_fu_433_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_5_1_load_B)) begin
d_o_5_1_payload_B <= tmp_2_5_fu_433_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_6_1_load_A)) begin
d_o_6_1_payload_A <= tmp_2_6_fu_464_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_6_1_load_B)) begin
d_o_6_1_payload_B <= tmp_2_6_fu_464_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_7_1_load_A)) begin
d_o_7_1_payload_A <= tmp_2_7_fu_495_p2;
end
end
always @ (posedge ap_clk) begin
if ((1'b1 == d_o_7_1_load_B)) begin
d_o_7_1_payload_B <= tmp_2_7_fu_495_p2;
end
end
always @ (posedge ap_clk) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
tmp_17_reg_502 <= tmp_17_fu_242_p1;
end
end
always @ (*) begin
if (((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00011001 == 1'b0) & (1'd1 == ap_reg_pp0_iter1_exitcond_reg_507))) begin
ap_done = 1'b1;
end else begin
ap_done = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_CS_fsm_state1))) begin
ap_idle = 1'b1;
end else begin
ap_idle = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1) & (1'b0 == ap_enable_reg_pp0_iter2))) begin
ap_idle_pp0 = 1'b1;
end else begin
ap_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_enable_reg_pp0_iter0) & (1'b0 == ap_enable_reg_pp0_iter1))) begin
ap_idle_pp0_0to1 = 1'b1;
end else begin
ap_idle_pp0_0to1 = 1'b0;
end
end
always @ (*) begin
if (((exitcond_fu_246_p2 == 1'd1) & (1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter0) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
ap_ready = 1'b1;
end else begin
ap_ready = 1'b0;
end
end
always @ (*) begin
if (((1'b0 == ap_start) & (1'b1 == ap_idle_pp0_0to1))) begin
ap_reset_idle_pp0 = 1'b1;
end else begin
ap_reset_idle_pp0 = 1'b0;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_0_0_ack_out = 1'b1;
end else begin
d_i_0_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_0_0_sel)) begin
d_i_0_0_data_out = d_i_0_0_payload_B;
end else begin
d_i_0_0_data_out = d_i_0_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_0_TDATA_blk_n = d_i_0_0_state[1'd0];
end else begin
d_i_0_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_1_0_ack_out = 1'b1;
end else begin
d_i_1_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_1_0_sel)) begin
d_i_1_0_data_out = d_i_1_0_payload_B;
end else begin
d_i_1_0_data_out = d_i_1_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_1_TDATA_blk_n = d_i_1_0_state[1'd0];
end else begin
d_i_1_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_2_0_ack_out = 1'b1;
end else begin
d_i_2_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_2_0_sel)) begin
d_i_2_0_data_out = d_i_2_0_payload_B;
end else begin
d_i_2_0_data_out = d_i_2_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_2_TDATA_blk_n = d_i_2_0_state[1'd0];
end else begin
d_i_2_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_3_0_ack_out = 1'b1;
end else begin
d_i_3_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_3_0_sel)) begin
d_i_3_0_data_out = d_i_3_0_payload_B;
end else begin
d_i_3_0_data_out = d_i_3_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_3_TDATA_blk_n = d_i_3_0_state[1'd0];
end else begin
d_i_3_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_4_0_ack_out = 1'b1;
end else begin
d_i_4_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_4_0_sel)) begin
d_i_4_0_data_out = d_i_4_0_payload_B;
end else begin
d_i_4_0_data_out = d_i_4_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_4_TDATA_blk_n = d_i_4_0_state[1'd0];
end else begin
d_i_4_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_5_0_ack_out = 1'b1;
end else begin
d_i_5_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_5_0_sel)) begin
d_i_5_0_data_out = d_i_5_0_payload_B;
end else begin
d_i_5_0_data_out = d_i_5_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_5_TDATA_blk_n = d_i_5_0_state[1'd0];
end else begin
d_i_5_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_6_0_ack_out = 1'b1;
end else begin
d_i_6_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_6_0_sel)) begin
d_i_6_0_data_out = d_i_6_0_payload_B;
end else begin
d_i_6_0_data_out = d_i_6_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_6_TDATA_blk_n = d_i_6_0_state[1'd0];
end else begin
d_i_6_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_i_7_0_ack_out = 1'b1;
end else begin
d_i_7_0_ack_out = 1'b0;
end
end
always @ (*) begin
if ((1'b1 == d_i_7_0_sel)) begin
d_i_7_0_data_out = d_i_7_0_payload_B;
end else begin
d_i_7_0_data_out = d_i_7_0_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0))) begin
d_i_7_TDATA_blk_n = d_i_7_0_state[1'd0];
end else begin
d_i_7_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_0_1_sel)) begin
d_o_0_1_data_out = d_o_0_1_payload_B;
end else begin
d_o_0_1_data_out = d_o_0_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_0_1_vld_in = 1'b1;
end else begin
d_o_0_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_0_TDATA_blk_n = d_o_0_1_state[1'd1];
end else begin
d_o_0_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_1_1_sel)) begin
d_o_1_1_data_out = d_o_1_1_payload_B;
end else begin
d_o_1_1_data_out = d_o_1_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_1_1_vld_in = 1'b1;
end else begin
d_o_1_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_1_TDATA_blk_n = d_o_1_1_state[1'd1];
end else begin
d_o_1_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_2_1_sel)) begin
d_o_2_1_data_out = d_o_2_1_payload_B;
end else begin
d_o_2_1_data_out = d_o_2_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_2_1_vld_in = 1'b1;
end else begin
d_o_2_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_2_TDATA_blk_n = d_o_2_1_state[1'd1];
end else begin
d_o_2_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_3_1_sel)) begin
d_o_3_1_data_out = d_o_3_1_payload_B;
end else begin
d_o_3_1_data_out = d_o_3_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_3_1_vld_in = 1'b1;
end else begin
d_o_3_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_3_TDATA_blk_n = d_o_3_1_state[1'd1];
end else begin
d_o_3_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_4_1_sel)) begin
d_o_4_1_data_out = d_o_4_1_payload_B;
end else begin
d_o_4_1_data_out = d_o_4_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_4_1_vld_in = 1'b1;
end else begin
d_o_4_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_4_TDATA_blk_n = d_o_4_1_state[1'd1];
end else begin
d_o_4_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_5_1_sel)) begin
d_o_5_1_data_out = d_o_5_1_payload_B;
end else begin
d_o_5_1_data_out = d_o_5_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_5_1_vld_in = 1'b1;
end else begin
d_o_5_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_5_TDATA_blk_n = d_o_5_1_state[1'd1];
end else begin
d_o_5_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_6_1_sel)) begin
d_o_6_1_data_out = d_o_6_1_payload_B;
end else begin
d_o_6_1_data_out = d_o_6_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_6_1_vld_in = 1'b1;
end else begin
d_o_6_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_6_TDATA_blk_n = d_o_6_1_state[1'd1];
end else begin
d_o_6_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((1'b1 == d_o_7_1_sel)) begin
d_o_7_1_data_out = d_o_7_1_payload_B;
end else begin
d_o_7_1_data_out = d_o_7_1_payload_A;
end
end
always @ (*) begin
if (((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00011001 == 1'b0))) begin
d_o_7_1_vld_in = 1'b1;
end else begin
d_o_7_1_vld_in = 1'b0;
end
end
always @ (*) begin
if ((((1'b1 == ap_enable_reg_pp0_iter2) & (ap_block_pp0_stage0_flag00000000 == 1'b0)) | ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0)))) begin
d_o_7_TDATA_blk_n = d_o_7_1_state[1'd1];
end else begin
d_o_7_TDATA_blk_n = 1'b1;
end
end
always @ (*) begin
if ((ap_condition_1051 == 1'b1)) begin
if ((1'd1 == exitcond_reg_507)) begin
i1_phi_fu_222_p6 = 5'd0;
end else if ((1'd0 == exitcond_reg_507)) begin
i1_phi_fu_222_p6 = tmp_17_reg_502;
end else begin
i1_phi_fu_222_p6 = i1_reg_218;
end
end else begin
i1_phi_fu_222_p6 = i1_reg_218;
end
end
always @ (*) begin
case (ap_CS_fsm)
ap_ST_fsm_state1 : begin
if (((1'b1 == ap_CS_fsm_state1) & (ap_start == 1'b1))) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else begin
ap_NS_fsm = ap_ST_fsm_state1;
end
end
ap_ST_fsm_pp0_stage0 : begin
if ((ap_reset_idle_pp0 == 1'b0)) begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end else if (((ap_block_pp0_stage0_flag00011011 == 1'b0) & (1'b1 == ap_reset_idle_pp0))) begin
ap_NS_fsm = ap_ST_fsm_state1;
end else begin
ap_NS_fsm = ap_ST_fsm_pp0_stage0;
end
end
default : begin
ap_NS_fsm = 'bx;
end
endcase
end
assign ap_CS_fsm_pp0_stage0 = ap_CS_fsm[32'd1];
assign ap_CS_fsm_state1 = ap_CS_fsm[32'd0];
assign ap_block_pp0_stage0_flag00000000 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_pp0_stage0_flag00001001 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011001 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out) | (1'b1 == ap_block_state4_io)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in) | (1'b1 == ap_block_state3_io)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end
always @ (*) begin
ap_block_pp0_stage0_flag00011011 = ((((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out) | (1'b1 == ap_block_state4_io)) & (1'b1 == ap_enable_reg_pp0_iter1)) | (((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in) | (1'b1 == ap_block_state3_io)) & (1'b1 == ap_enable_reg_pp0_iter2)));
end
assign ap_block_state2_pp0_stage0_iter0 = ~(1'b1 == 1'b1);
always @ (*) begin
ap_block_state3_io = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end
always @ (*) begin
ap_block_state3_pp0_stage0_iter2 = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end
always @ (*) begin
ap_block_state4_io = ((1'b0 == d_o_0_1_ack_in) | (1'b0 == d_o_1_1_ack_in) | (1'b0 == d_o_2_1_ack_in) | (1'b0 == d_o_3_1_ack_in) | (1'b0 == d_o_4_1_ack_in) | (1'b0 == d_o_5_1_ack_in) | (1'b0 == d_o_6_1_ack_in) | (1'b0 == d_o_7_1_ack_in));
end
always @ (*) begin
ap_block_state4_pp0_stage0_iter1 = ((1'b0 == d_i_0_0_vld_out) | (1'b0 == d_i_1_0_vld_out) | (1'b0 == d_i_2_0_vld_out) | (1'b0 == d_i_3_0_vld_out) | (1'b0 == d_i_4_0_vld_out) | (1'b0 == d_i_5_0_vld_out) | (1'b0 == d_i_6_0_vld_out) | (1'b0 == d_i_7_0_vld_out));
end
always @ (*) begin
ap_condition_1051 = ((1'b1 == ap_CS_fsm_pp0_stage0) & (1'b1 == ap_enable_reg_pp0_iter1) & (ap_block_pp0_stage0_flag00000000 == 1'b0));
end
assign ap_enable_pp0 = (ap_idle_pp0 ^ 1'b1);
assign ap_enable_reg_pp0_iter0 = ap_start;
always @ (*) begin
ap_rst_n_inv = ~ap_rst_n;
end
assign d_i_0_0_ack_in = d_i_0_0_state[1'd1];
assign d_i_0_0_load_A = (d_i_0_0_state_cmp_full & ~d_i_0_0_sel_wr);
assign d_i_0_0_load_B = (d_i_0_0_sel_wr & d_i_0_0_state_cmp_full);
assign d_i_0_0_sel = d_i_0_0_sel_rd;
assign d_i_0_0_state_cmp_full = ((d_i_0_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_0_0_vld_in = d_i_0_TVALID;
assign d_i_0_0_vld_out = d_i_0_0_state[1'd0];
assign d_i_0_TREADY = d_i_0_0_state[1'd1];
assign d_i_1_0_ack_in = d_i_1_0_state[1'd1];
assign d_i_1_0_load_A = (d_i_1_0_state_cmp_full & ~d_i_1_0_sel_wr);
assign d_i_1_0_load_B = (d_i_1_0_sel_wr & d_i_1_0_state_cmp_full);
assign d_i_1_0_sel = d_i_1_0_sel_rd;
assign d_i_1_0_state_cmp_full = ((d_i_1_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_1_0_vld_in = d_i_1_TVALID;
assign d_i_1_0_vld_out = d_i_1_0_state[1'd0];
assign d_i_1_TREADY = d_i_1_0_state[1'd1];
assign d_i_2_0_ack_in = d_i_2_0_state[1'd1];
assign d_i_2_0_load_A = (d_i_2_0_state_cmp_full & ~d_i_2_0_sel_wr);
assign d_i_2_0_load_B = (d_i_2_0_sel_wr & d_i_2_0_state_cmp_full);
assign d_i_2_0_sel = d_i_2_0_sel_rd;
assign d_i_2_0_state_cmp_full = ((d_i_2_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_2_0_vld_in = d_i_2_TVALID;
assign d_i_2_0_vld_out = d_i_2_0_state[1'd0];
assign d_i_2_TREADY = d_i_2_0_state[1'd1];
assign d_i_3_0_ack_in = d_i_3_0_state[1'd1];
assign d_i_3_0_load_A = (d_i_3_0_state_cmp_full & ~d_i_3_0_sel_wr);
assign d_i_3_0_load_B = (d_i_3_0_sel_wr & d_i_3_0_state_cmp_full);
assign d_i_3_0_sel = d_i_3_0_sel_rd;
assign d_i_3_0_state_cmp_full = ((d_i_3_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_3_0_vld_in = d_i_3_TVALID;
assign d_i_3_0_vld_out = d_i_3_0_state[1'd0];
assign d_i_3_TREADY = d_i_3_0_state[1'd1];
assign d_i_4_0_ack_in = d_i_4_0_state[1'd1];
assign d_i_4_0_load_A = (d_i_4_0_state_cmp_full & ~d_i_4_0_sel_wr);
assign d_i_4_0_load_B = (d_i_4_0_sel_wr & d_i_4_0_state_cmp_full);
assign d_i_4_0_sel = d_i_4_0_sel_rd;
assign d_i_4_0_state_cmp_full = ((d_i_4_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_4_0_vld_in = d_i_4_TVALID;
assign d_i_4_0_vld_out = d_i_4_0_state[1'd0];
assign d_i_4_TREADY = d_i_4_0_state[1'd1];
assign d_i_5_0_ack_in = d_i_5_0_state[1'd1];
assign d_i_5_0_load_A = (d_i_5_0_state_cmp_full & ~d_i_5_0_sel_wr);
assign d_i_5_0_load_B = (d_i_5_0_sel_wr & d_i_5_0_state_cmp_full);
assign d_i_5_0_sel = d_i_5_0_sel_rd;
assign d_i_5_0_state_cmp_full = ((d_i_5_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_5_0_vld_in = d_i_5_TVALID;
assign d_i_5_0_vld_out = d_i_5_0_state[1'd0];
assign d_i_5_TREADY = d_i_5_0_state[1'd1];
assign d_i_6_0_ack_in = d_i_6_0_state[1'd1];
assign d_i_6_0_load_A = (d_i_6_0_state_cmp_full & ~d_i_6_0_sel_wr);
assign d_i_6_0_load_B = (d_i_6_0_sel_wr & d_i_6_0_state_cmp_full);
assign d_i_6_0_sel = d_i_6_0_sel_rd;
assign d_i_6_0_state_cmp_full = ((d_i_6_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_6_0_vld_in = d_i_6_TVALID;
assign d_i_6_0_vld_out = d_i_6_0_state[1'd0];
assign d_i_6_TREADY = d_i_6_0_state[1'd1];
assign d_i_7_0_ack_in = d_i_7_0_state[1'd1];
assign d_i_7_0_load_A = (d_i_7_0_state_cmp_full & ~d_i_7_0_sel_wr);
assign d_i_7_0_load_B = (d_i_7_0_sel_wr & d_i_7_0_state_cmp_full);
assign d_i_7_0_sel = d_i_7_0_sel_rd;
assign d_i_7_0_state_cmp_full = ((d_i_7_0_state != 2'd1) ? 1'b1 : 1'b0);
assign d_i_7_0_vld_in = d_i_7_TVALID;
assign d_i_7_0_vld_out = d_i_7_0_state[1'd0];
assign d_i_7_TREADY = d_i_7_0_state[1'd1];
assign d_o_0_1_ack_in = d_o_0_1_state[1'd1];
assign d_o_0_1_ack_out = d_o_0_TREADY;
assign d_o_0_1_load_A = (d_o_0_1_state_cmp_full & ~d_o_0_1_sel_wr);
assign d_o_0_1_load_B = (d_o_0_1_sel_wr & d_o_0_1_state_cmp_full);
assign d_o_0_1_sel = d_o_0_1_sel_rd;
assign d_o_0_1_state_cmp_full = ((d_o_0_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_0_1_vld_out = d_o_0_1_state[1'd0];
assign d_o_0_TDATA = d_o_0_1_data_out;
assign d_o_0_TVALID = d_o_0_1_state[1'd0];
assign d_o_1_1_ack_in = d_o_1_1_state[1'd1];
assign d_o_1_1_ack_out = d_o_1_TREADY;
assign d_o_1_1_load_A = (d_o_1_1_state_cmp_full & ~d_o_1_1_sel_wr);
assign d_o_1_1_load_B = (d_o_1_1_sel_wr & d_o_1_1_state_cmp_full);
assign d_o_1_1_sel = d_o_1_1_sel_rd;
assign d_o_1_1_state_cmp_full = ((d_o_1_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_1_1_vld_out = d_o_1_1_state[1'd0];
assign d_o_1_TDATA = d_o_1_1_data_out;
assign d_o_1_TVALID = d_o_1_1_state[1'd0];
assign d_o_2_1_ack_in = d_o_2_1_state[1'd1];
assign d_o_2_1_ack_out = d_o_2_TREADY;
assign d_o_2_1_load_A = (d_o_2_1_state_cmp_full & ~d_o_2_1_sel_wr);
assign d_o_2_1_load_B = (d_o_2_1_sel_wr & d_o_2_1_state_cmp_full);
assign d_o_2_1_sel = d_o_2_1_sel_rd;
assign d_o_2_1_state_cmp_full = ((d_o_2_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_2_1_vld_out = d_o_2_1_state[1'd0];
assign d_o_2_TDATA = d_o_2_1_data_out;
assign d_o_2_TVALID = d_o_2_1_state[1'd0];
assign d_o_3_1_ack_in = d_o_3_1_state[1'd1];
assign d_o_3_1_ack_out = d_o_3_TREADY;
assign d_o_3_1_load_A = (d_o_3_1_state_cmp_full & ~d_o_3_1_sel_wr);
assign d_o_3_1_load_B = (d_o_3_1_sel_wr & d_o_3_1_state_cmp_full);
assign d_o_3_1_sel = d_o_3_1_sel_rd;
assign d_o_3_1_state_cmp_full = ((d_o_3_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_3_1_vld_out = d_o_3_1_state[1'd0];
assign d_o_3_TDATA = d_o_3_1_data_out;
assign d_o_3_TVALID = d_o_3_1_state[1'd0];
assign d_o_4_1_ack_in = d_o_4_1_state[1'd1];
assign d_o_4_1_ack_out = d_o_4_TREADY;
assign d_o_4_1_load_A = (d_o_4_1_state_cmp_full & ~d_o_4_1_sel_wr);
assign d_o_4_1_load_B = (d_o_4_1_sel_wr & d_o_4_1_state_cmp_full);
assign d_o_4_1_sel = d_o_4_1_sel_rd;
assign d_o_4_1_state_cmp_full = ((d_o_4_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_4_1_vld_out = d_o_4_1_state[1'd0];
assign d_o_4_TDATA = d_o_4_1_data_out;
assign d_o_4_TVALID = d_o_4_1_state[1'd0];
assign d_o_5_1_ack_in = d_o_5_1_state[1'd1];
assign d_o_5_1_ack_out = d_o_5_TREADY;
assign d_o_5_1_load_A = (d_o_5_1_state_cmp_full & ~d_o_5_1_sel_wr);
assign d_o_5_1_load_B = (d_o_5_1_sel_wr & d_o_5_1_state_cmp_full);
assign d_o_5_1_sel = d_o_5_1_sel_rd;
assign d_o_5_1_state_cmp_full = ((d_o_5_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_5_1_vld_out = d_o_5_1_state[1'd0];
assign d_o_5_TDATA = d_o_5_1_data_out;
assign d_o_5_TVALID = d_o_5_1_state[1'd0];
assign d_o_6_1_ack_in = d_o_6_1_state[1'd1];
assign d_o_6_1_ack_out = d_o_6_TREADY;
assign d_o_6_1_load_A = (d_o_6_1_state_cmp_full & ~d_o_6_1_sel_wr);
assign d_o_6_1_load_B = (d_o_6_1_sel_wr & d_o_6_1_state_cmp_full);
assign d_o_6_1_sel = d_o_6_1_sel_rd;
assign d_o_6_1_state_cmp_full = ((d_o_6_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_6_1_vld_out = d_o_6_1_state[1'd0];
assign d_o_6_TDATA = d_o_6_1_data_out;
assign d_o_6_TVALID = d_o_6_1_state[1'd0];
assign d_o_7_1_ack_in = d_o_7_1_state[1'd1];
assign d_o_7_1_ack_out = d_o_7_TREADY;
assign d_o_7_1_load_A = (d_o_7_1_state_cmp_full & ~d_o_7_1_sel_wr);
assign d_o_7_1_load_B = (d_o_7_1_sel_wr & d_o_7_1_state_cmp_full);
assign d_o_7_1_sel = d_o_7_1_sel_rd;
assign d_o_7_1_state_cmp_full = ((d_o_7_1_state != 2'd1) ? 1'b1 : 1'b0);
assign d_o_7_1_vld_out = d_o_7_1_state[1'd0];
assign d_o_7_TDATA = d_o_7_1_data_out;
assign d_o_7_TVALID = d_o_7_1_state[1'd0];
assign exitcond_fu_246_p2 = ((i_1_7_fu_236_p2 == 6'd32) ? 1'b1 : 1'b0);
assign i1_cast_fu_232_p1 = i1_phi_fu_222_p6;
assign i_1_7_fu_236_p2 = (6'd8 + i1_cast_fu_232_p1);
assign tmp1_fu_258_p1 = $signed(d_i_0_0_data_out);
assign tmp_10_fu_293_p1 = acc_1[15:0];
assign tmp_11_fu_324_p1 = acc_2[15:0];
assign tmp_12_fu_355_p1 = acc_3[15:0];
assign tmp_13_fu_386_p1 = acc_4[15:0];
assign tmp_14_fu_417_p1 = acc_5[15:0];
assign tmp_15_fu_448_p1 = acc_6[15:0];
assign tmp_16_fu_479_p1 = acc_7[15:0];
assign tmp_17_fu_242_p1 = i_1_7_fu_236_p2[4:0];
assign tmp_1_1_fu_297_p2 = ($signed(tmp_s_fu_289_p1) + $signed(acc_1));
assign tmp_1_2_fu_328_p2 = ($signed(tmp_9_fu_320_p1) + $signed(acc_2));
assign tmp_1_3_fu_359_p2 = ($signed(tmp_3_fu_351_p1) + $signed(acc_3));
assign tmp_1_4_fu_390_p2 = ($signed(tmp_4_fu_382_p1) + $signed(acc_4));
assign tmp_1_5_fu_421_p2 = ($signed(tmp_5_fu_413_p1) + $signed(acc_5));
assign tmp_1_6_fu_452_p2 = ($signed(tmp_6_fu_444_p1) + $signed(acc_6));
assign tmp_1_7_fu_483_p2 = ($signed(tmp_7_fu_475_p1) + $signed(acc_7));
assign tmp_1_fu_266_p2 = ($signed(tmp1_fu_258_p1) + $signed(acc_0));
assign tmp_2_1_fu_309_p2 = (tmp_10_fu_293_p1 + d_i_1_0_data_out);
assign tmp_2_2_fu_340_p2 = (tmp_11_fu_324_p1 + d_i_2_0_data_out);
assign tmp_2_3_fu_371_p2 = (tmp_12_fu_355_p1 + d_i_3_0_data_out);
assign tmp_2_4_fu_402_p2 = (tmp_13_fu_386_p1 + d_i_4_0_data_out);
assign tmp_2_5_fu_433_p2 = (tmp_14_fu_417_p1 + d_i_5_0_data_out);
assign tmp_2_6_fu_464_p2 = (tmp_15_fu_448_p1 + d_i_6_0_data_out);
assign tmp_2_7_fu_495_p2 = (tmp_16_fu_479_p1 + d_i_7_0_data_out);
assign tmp_2_fu_262_p1 = acc_0[15:0];
assign tmp_3_fu_351_p1 = $signed(d_i_3_0_data_out);
assign tmp_4_fu_382_p1 = $signed(d_i_4_0_data_out);
assign tmp_5_fu_413_p1 = $signed(d_i_5_0_data_out);
assign tmp_6_fu_444_p1 = $signed(d_i_6_0_data_out);
assign tmp_7_fu_475_p1 = $signed(d_i_7_0_data_out);
assign tmp_8_fu_278_p2 = (tmp_2_fu_262_p1 + d_i_0_0_data_out);
assign tmp_9_fu_320_p1 = $signed(d_i_2_0_data_out);
assign tmp_s_fu_289_p1 = $signed(d_i_1_0_data_out);
endmodule //axi_interfaces
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always if ( constant) statement else ;
module main ;
reg [3:0] value1 ;
initial
begin
value1 = 0;
# 5 ;
if(value1 != 4'd4)
$display("FAILED - always 3.1.5B always if ( constant) statementelse ;");
else
$display("PASSED");
$finish;
end
always if( 1'b1) begin
# 1;
value1 = value1 + 1;
end
else ;
endmodule
|
/******************************************************************************/
/* Top module of sorting logic Ryohei Kobayashi */
/* 2015-08-01 */
/******************************************************************************/
`default_nettype none
`include "define.vh"
/***** generating a 512-bits data from 128-bits input data from a host PC *****/
/******************************************************************************/
module DATAGEN(input wire CLK,
input wire RST,
input wire dinen,
input wire [`MERGW-1:0] din,
output wire doten,
output wire [`DRAMW-1:0] dot);
reg [1:0] buf_t_cnt; // counter for temporary register
reg data_valid;
reg [`DRAMW-1:0] buf_t;
assign doten = data_valid;
assign dot = buf_t;
always @(posedge CLK) begin
if (dinen) buf_t <= {din, buf_t[`DRAMW-1:`MERGW]};
end
always @(posedge CLK) begin
if (RST) begin
buf_t_cnt <= 0;
end else begin
if (dinen) buf_t_cnt <= buf_t_cnt + 1;
end
end
always @(posedge CLK) data_valid <= (dinen && buf_t_cnt == 3);
endmodule
/******************************************************************************/
module USER_LOGIC #(parameter C_PCI_DATA_WIDTH = 128)
( input wire CLK,
input wire RST,
output wire CHNL_RX_CLK,
(* mark_debug = "true" *) input wire CHNL_RX,
(* mark_debug = "true" *) output wire CHNL_RX_ACK,
(* mark_debug = "true" *) input wire CHNL_RX_LAST,
(* mark_debug = "true" *) input wire [31:0] CHNL_RX_LEN,
(* mark_debug = "true" *) input wire [30:0] CHNL_RX_OFF,
(* mark_debug = "true" *) input wire [C_PCI_DATA_WIDTH-1:0] CHNL_RX_DATA,
(* mark_debug = "true" *) input wire CHNL_RX_DATA_VALID,
(* mark_debug = "true" *) output wire CHNL_RX_DATA_REN,
output wire CHNL_TX_CLK,
(* mark_debug = "true" *) output wire CHNL_TX,
(* mark_debug = "true" *) input wire CHNL_TX_ACK,
(* mark_debug = "true" *) output wire CHNL_TX_LAST,
(* mark_debug = "true" *) output wire [31:0] CHNL_TX_LEN,
(* mark_debug = "true" *) output wire [30:0] CHNL_TX_OFF,
(* mark_debug = "true" *) output wire [C_PCI_DATA_WIDTH-1:0] CHNL_TX_DATA,
(* mark_debug = "true" *) output wire CHNL_TX_DATA_VALID,
(* mark_debug = "true" *) input wire CHNL_TX_DATA_REN,
input wire d_busy, // DRAM busy
output wire [512-1:0] d_din, // DRAM data in
input wire d_w, // DRAM write flag
input wire [512-1:0] d_dout, // DRAM data out
input wire d_douten, // DRAM data out enable
output wire [1:0] d_req, // DRAM REQ access request (read/write)
output wire [31:0] d_initadr, // DRAM REQ initial address for the access
output wire [31:0] d_blocks // DRAM REQ the number of blocks per one access
);
function [`DRAMW-1:0] mux;
input [`DRAMW-1:0] a;
input [`DRAMW-1:0] b;
input sel;
begin
case (sel)
1'b0: mux = a;
1'b1: mux = b;
endcase
end
endfunction
function [1:0] mux2;
input [1:0] a;
input [1:0] b;
input sel;
begin
case (sel)
1'b0: mux2 = a;
1'b1: mux2 = b;
endcase
end
endfunction
function [32-1:0] mux32;
input [32-1:0] a;
input [32-1:0] b;
input sel;
begin
case (sel)
1'b0: mux32 = a;
1'b1: mux32 = b;
endcase
end
endfunction
reg [31:0] rLen;
(* mark_debug = "true" *) reg [31:0] rCount;
(* mark_debug = "true" *) reg [1:0] rState;
reg [31:0] tLen;
(* mark_debug = "true" *) reg [31:0] tCount;
(* mark_debug = "true" *) reg [1:0] tState;
wire [`DRAMW-1:0] idata; // initdata
wire idata_valid; // initdata is valid
wire rx_wait; // wait flag for PCIe
wire [C_PCI_DATA_WIDTH-1:0] core_dot; // sorting result
wire core_rdy; // sorting result is ready
DATAGEN datagen(CLK, RST, (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID), CHNL_RX_DATA, idata_valid, idata);
CORE core(CLK, RST,
d_busy, d_din, d_w, d_dout, d_douten, d_req, d_initadr, d_blocks, // DRAM interface
idata, idata_valid, rx_wait, // Interface for Host -> FPGA
CHNL_TX_DATA_REN, CHNL_TX_DATA_VALID, core_dot, core_rdy // Interface for FPGA -> Host
);
assign CHNL_RX_CLK = CLK;
assign CHNL_RX_ACK = (rState == 2'd1);
assign CHNL_RX_DATA_REN = (rState == 2'd1 && !rx_wait);
assign CHNL_TX_CLK = CLK;
assign CHNL_TX = (tState == 2'd1);
assign CHNL_TX_LAST = 1'd1;
assign CHNL_TX_LEN = tLen; // in words
assign CHNL_TX_OFF = 0;
assign CHNL_TX_DATA = core_dot;
assign CHNL_TX_DATA_VALID = (tState == 2'd1 && core_rdy);
// State machine for Host -> FPGA
always @(posedge CLK) begin
if (RST) begin
rLen <= 0;
rCount <= 0;
rState <= 0;
end else begin
case (rState)
2'd0: begin // Wait for start of RX, save length
if (CHNL_RX) begin
rLen <= CHNL_RX_LEN;
rCount <= 0;
rState <= 2'd1;
end
end
2'd1: begin // Wait for last data in RX, save value
if (CHNL_RX_DATA_REN && CHNL_RX_DATA_VALID) rCount <= rCount + (C_PCI_DATA_WIDTH >> 5);
if (rCount >= rLen) rState <= 2'd0;
end
endcase
end
end
// State machine for FPGA -> Host
always @(posedge CLK) begin
if (RST) begin
tLen <= 0;
tCount <= 0;
tState <= 0;
end else begin
case (tState)
2'd0: begin // Prepare for TX
if (core_rdy) begin
tLen <= rLen;
tCount <= 0;
tState <= 2'd1;
end
end
2'd1: begin // Start TX with save length and data value
if (CHNL_TX_DATA_REN && CHNL_TX_DATA_VALID) tCount <= tCount + (C_PCI_DATA_WIDTH >> 5);
if (tCount >= tLen) tState <= 2'd0;
end
endcase
end
end
endmodule
`default_nettype wire
|
//////////////////////////////////////////////////////////////////
// //
// Generic Asynchronous FIFO //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module afifo
#(
parameter D_WIDTH = 32
)
(
input wr_clk,
input rd_clk,
input [D_WIDTH-1:0] i_data,
output [D_WIDTH-1:0] o_data,
input i_push,
input i_pop,
output o_full,
output o_empty
);
reg [2:0] wr_pointer = 'd0, rd_pointer = 'd0;
reg [2:0] wr_pointer_d1 = 'd0, rd_pointer_d1 = 'd0;
reg [2:0] wr_pointer_d2 = 'd0, rd_pointer_d2 = 'd0;
wire [2:0] wr_pointer_rd, rd_pointer_wr;
reg [D_WIDTH-1:0] data [3:0];
always @( posedge wr_clk )
if ( i_push && !o_full )
begin
wr_pointer <= wr_pointer + 1'd1;
data[wr_pointer[1:0]] <= i_data;
end
always @( posedge wr_clk )
begin
rd_pointer_d1 <= gray8(rd_pointer);
rd_pointer_d2 <= rd_pointer_d1;
end
always @( posedge rd_clk )
if ( i_pop && !o_empty )
rd_pointer <= rd_pointer + 1'd1;
always @( posedge rd_clk )
begin
wr_pointer_d1 <= gray8(wr_pointer);
wr_pointer_d2 <= wr_pointer_d1;
end
assign wr_pointer_rd = ungray8(wr_pointer_d2);
assign rd_pointer_wr = ungray8(rd_pointer_d2);
assign o_data = data[rd_pointer[1:0]];
assign o_full = {~wr_pointer[2], wr_pointer[1:0]} == rd_pointer_wr;
assign o_empty = wr_pointer_rd == rd_pointer;
function [2:0] gray8;
input [2:0] binary;
begin
case(binary)
3'b000 : gray8 = 3'b000;
3'b001 : gray8 = 3'b001;
3'b010 : gray8 = 3'b011;
3'b011 : gray8 = 3'b010;
3'b100 : gray8 = 3'b110;
3'b101 : gray8 = 3'b111;
3'b110 : gray8 = 3'b101;
3'b111 : gray8 = 3'b100;
endcase
end
endfunction
function [2:0] ungray8;
input [2:0] gray;
begin
case(gray)
3'b000 : ungray8 = 3'b000;
3'b001 : ungray8 = 3'b001;
3'b011 : ungray8 = 3'b010;
3'b010 : ungray8 = 3'b011;
3'b110 : ungray8 = 3'b100;
3'b111 : ungray8 = 3'b101;
3'b101 : ungray8 = 3'b110;
3'b100 : ungray8 = 3'b111;
endcase
end
endfunction
endmodule
|
(** * Hoare: Hoare Logic, Part I *)
Require Export Imp.
(** In the past couple of chapters, we've begun applying the
mathematical tools developed in the first part of the course to
studying the theory of a small programming language, Imp.
- We defined a type of _abstract syntax trees_ for Imp, together
with an _evaluation relation_ (a partial function on states)
that specifies the _operational semantics_ of programs.
The language we defined, though small, captures some of the key
features of full-blown languages like C, C++, and Java,
including the fundamental notion of mutable state and some
common control structures.
- We proved a number of _metatheoretic properties_ -- "meta" in
the sense that they are properties of the language as a whole,
rather than properties of particular programs in the language.
These included:
- determinism of evaluation
- equivalence of some different ways of writing down the
definitions (e.g. functional and relational definitions of
arithmetic expression evaluation)
- guaranteed termination of certain classes of programs
- correctness (in the sense of preserving meaning) of a number
of useful program transformations
- behavioral equivalence of programs (in the [Equiv] chapter).
If we stopped here, we would already have something useful: a set
of tools for defining and discussing programming languages and
language features that are mathematically precise, flexible, and
easy to work with, applied to a set of key properties. All of
these properties are things that language designers, compiler
writers, and users might care about knowing. Indeed, many of them
are so fundamental to our understanding of the programming
languages we deal with that we might not consciously recognize
them as "theorems." But properties that seem intuitively obvious
can sometimes be quite subtle (in some cases, even subtly wrong!).
We'll return to the theme of metatheoretic properties of whole
languages later in the course when we discuss _types_ and _type
soundness_. In this chapter, though, we'll turn to a different
set of issues.
Our goal is to see how to carry out some simple examples of
_program verification_ -- i.e., using the precise definition of
Imp to prove formally that particular programs satisfy particular
specifications of their behavior. We'll develop a reasoning system
called _Floyd-Hoare Logic_ -- often shortened to just _Hoare
Logic_ -- in which each of the syntactic constructs of Imp is
equipped with a single, generic "proof rule" that can be used to
reason compositionally about the correctness of programs involving
this construct.
Hoare Logic originates in the 1960s, and it continues to be the
subject of intensive research right up to the present day. It
lies at the core of a multitude of tools that are being used in
academia and industry to specify and verify real software
systems. *)
(* ####################################################### *)
(** * Hoare Logic *)
(** Hoare Logic combines two beautiful ideas: a natural way of
writing down _specifications_ of programs, and a _compositional
proof technique_ for proving that programs are correct with
respect to such specifications -- where by "compositional" we mean
that the structure of proofs directly mirrors the structure of the
programs that they are about. *)
(* ####################################################### *)
(** ** Assertions *)
(** To talk about specifications of programs, the first thing we
need is a way of making _assertions_ about properties that hold at
particular points during a program's execution -- i.e., claims
about the current state of the memory when program execution
reaches that point. Formally, an assertion is just a family of
propositions indexed by a [state]. *)
Definition Assertion := state -> Prop.
(** **** Exercise: 1 star, optional (assertions) *)
Module ExAssertions.
(** Paraphrase the following assertions in English. *)
Definition as1 : Assertion := fun st => st X = 3.
Definition as2 : Assertion := fun st => st X <= st Y.
Definition as3 : Assertion :=
fun st => st X = 3 \/ st X <= st Y.
Definition as4 : Assertion :=
fun st => st Z * st Z <= st X /\
~ (((S (st Z)) * (S (st Z))) <= st X).
Definition as5 : Assertion := fun st => True.
Definition as6 : Assertion := fun st => False.
(* FILL IN HERE *)
End ExAssertions.
(** [] *)
(** This way of writing assertions can be a little bit heavy,
for two reasons: (1) every single assertion that we ever write is
going to begin with [fun st => ]; and (2) this state [st] is the
only one that we ever use to look up variables (we will never need
to talk about two different memory states at the same time). For
discussing examples informally, we'll adopt some simplifying
conventions: we'll drop the initial [fun st =>], and we'll write
just [X] to mean [st X]. Thus, instead of writing *)
(**
fun st => (st Z) * (st Z) <= m /\
~ ((S (st Z)) * (S (st Z)) <= m)
we'll write just
Z * Z <= m /\ ~((S Z) * (S Z) <= m).
*)
(** Given two assertions [P] and [Q], we say that [P] _implies_ [Q],
written [P ->> Q] (in ASCII, [P -][>][> Q]), if, whenever [P]
holds in some state [st], [Q] also holds. *)
Definition assert_implies (P Q : Assertion) : Prop :=
forall st, P st -> Q st.
Notation "P ->> Q" :=
(assert_implies P Q) (at level 80) : hoare_spec_scope.
Open Scope hoare_spec_scope.
(** We'll also have occasion to use the "iff" variant of implication
between assertions: *)
Notation "P <<->> Q" :=
(P ->> Q /\ Q ->> P) (at level 80) : hoare_spec_scope.
(* ####################################################### *)
(** ** Hoare Triples *)
(** Next, we need a way of making formal claims about the
behavior of commands. *)
(** Since the behavior of a command is to transform one state to
another, it is natural to express claims about commands in terms
of assertions that are true before and after the command executes:
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
Such a claim is called a _Hoare Triple_. The property [P] is
called the _precondition_ of [c], while [Q] is the
_postcondition_. Formally: *)
Definition hoare_triple
(P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
(** Since we'll be working a lot with Hoare triples, it's useful to
have a compact notation:
{{P}} c {{Q}}.
*)
(** (The traditional notation is [{P} c {Q}], but single braces
are already used for other things in Coq.) *)
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level)
: hoare_spec_scope.
(** (The [hoare_spec_scope] annotation here tells Coq that this
notation is not global but is intended to be used in particular
contexts. The [Open Scope] tells Coq that this file is one such
context.) *)
(** **** Exercise: 1 star, optional (triples) *)
(** Paraphrase the following Hoare triples in English.
1) {{True}} c {{X = 5}}
2) {{X = m}} c {{X = m + 5)}}
3) {{X <= Y}} c {{Y <= X}}
4) {{True}} c {{False}}
5) {{X = m}}
c
{{Y = real_fact m}}.
6) {{True}}
c
{{(Z * Z) <= m /\ ~ (((S Z) * (S Z)) <= m)}}
*)
(** [] *)
(** **** Exercise: 1 star, optional (valid_triples) *)
(** Which of the following Hoare triples are _valid_ -- i.e., the
claimed relation between [P], [c], and [Q] is true?
1) {{True}} X ::= 5 {{X = 5}}
2) {{X = 2}} X ::= X + 1 {{X = 3}}
3) {{True}} X ::= 5; Y ::= 0 {{X = 5}}
4) {{X = 2 /\ X = 3}} X ::= 5 {{X = 0}}
5) {{True}} SKIP {{False}}
6) {{False}} SKIP {{True}}
7) {{True}} WHILE True DO SKIP END {{False}}
8) {{X = 0}}
WHILE X == 0 DO X ::= X + 1 END
{{X = 1}}
9) {{X = 1}}
WHILE X <> 0 DO X ::= X + 1 END
{{X = 100}}
*)
(* FILL IN HERE *)
(** [] *)
(** (Note that we're using informal mathematical notations for
expressions inside of commands, for readability, rather than their
formal [aexp] and [bexp] encodings. We'll continue doing so
throughout the chapter.) *)
(** To get us warmed up for what's coming, here are two simple
facts about Hoare triples. *)
Theorem hoare_post_true : forall (P Q : Assertion) c,
(forall st, Q st) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
apply H. Qed.
Theorem hoare_pre_false : forall (P Q : Assertion) c,
(forall st, ~(P st)) ->
{{P}} c {{Q}}.
Proof.
intros P Q c H. unfold hoare_triple.
intros st st' Heval HP.
unfold not in H. apply H in HP.
inversion HP. Qed.
(* ####################################################### *)
(** ** Proof Rules *)
(** The goal of Hoare logic is to provide a _compositional_
method for proving the validity of Hoare triples. That is, the
structure of a program's correctness proof should mirror the
structure of the program itself. To this end, in the sections
below, we'll introduce one rule for reasoning about each of the
different syntactic forms of commands in Imp -- one for
assignment, one for sequencing, one for conditionals, etc. -- plus
a couple of "structural" rules that are useful for gluing things
together. We will prove programs correct using these proof rules,
without ever unfolding the definition of [hoare_triple]. *)
(* ####################################################### *)
(** *** Assignment *)
(** The rule for assignment is the most fundamental of the Hoare logic
proof rules. Here's how it works.
Consider this (valid) Hoare triple:
{{ Y = 1 }} X ::= Y {{ X = 1 }}
In English: if we start out in a state where the value of [Y]
is [1] and we assign [Y] to [X], then we'll finish in a
state where [X] is [1]. That is, the property of being equal
to [1] gets transferred from [Y] to [X].
Similarly, in
{{ Y + Z = 1 }} X ::= Y + Z {{ X = 1 }}
the same property (being equal to one) gets transferred to
[X] from the expression [Y + Z] on the right-hand side of
the assignment.
More generally, if [a] is _any_ arithmetic expression, then
{{ a = 1 }} X ::= a {{ X = 1 }}
is a valid Hoare triple.
This can be made even more general. To conclude that an
_arbitrary_ property [Q] holds after [X ::= a], we need to assume
that [Q] holds before [X ::= a], but _with all occurrences of_ [X]
replaced by [a] in [Q]. This leads to the Hoare rule for
assignment
{{ Q [X |-> a] }} X ::= a {{ Q }}
where "[Q [X |-> a]]" is pronounced "[Q] where [a] is substituted
for [X]".
For example, these are valid applications of the assignment
rule:
{{ (X <= 5) [X |-> X + 1]
i.e., X + 1 <= 5 }}
X ::= X + 1
{{ X <= 5 }}
{{ (X = 3) [X |-> 3]
i.e., 3 = 3}}
X ::= 3
{{ X = 3 }}
{{ (0 <= X /\ X <= 5) [X |-> 3]
i.e., (0 <= 3 /\ 3 <= 5)}}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
*)
(** To formalize the rule, we must first formalize the idea of
"substituting an expression for an Imp variable in an assertion."
That is, given a proposition [P], a variable [X], and an
arithmetic expression [a], we want to derive another proposition
[P'] that is just the same as [P] except that, wherever [P]
mentions [X], [P'] should instead mention [a].
Since [P] is an arbitrary Coq proposition, we can't directly
"edit" its text. Instead, we can achieve the effect we want by
evaluating [P] in an updated state: *)
Definition assn_sub X a P : Assertion :=
fun (st : state) =>
P (update st X (aeval st a)).
Notation "P [ X |-> a ]" := (assn_sub X a P) (at level 10).
(** That is, [P [X |-> a]] is an assertion [P'] that is just like [P]
except that, wherever [P] looks up the variable [X] in the current
state, [P'] instead uses the value of the expression [a].
To see how this works, let's calculate what happens with a couple
of examples. First, suppose [P'] is [(X <= 5) [X |-> 3]] -- that
is, more formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (ANum 3))),
which simplifies to
fun st =>
(fun st' => st' X <= 5)
(update st X 3)
and further simplifies to
fun st =>
((update st X 3) X) <= 5)
and by further simplification to
fun st =>
(3 <= 5).
That is, [P'] is the assertion that [3] is less than or equal to
[5] (as expected).
For a more interesting example, suppose [P'] is [(X <= 5) [X |->
X+1]]. Formally, [P'] is the Coq expression
fun st =>
(fun st' => st' X <= 5)
(update st X (aeval st (APlus (AId X) (ANum 1)))),
which simplifies to
fun st =>
(((update st X (aeval st (APlus (AId X) (ANum 1))))) X) <= 5
and further simplifies to
fun st =>
(aeval st (APlus (AId X) (ANum 1))) <= 5.
That is, [P'] is the assertion that [X+1] is at most [5].
*)
(** Now we can give the precise proof rule for assignment:
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X ::= a {{Q}}
*)
(** We can prove formally that this rule is indeed valid. *)
Theorem hoare_asgn : forall Q X a,
{{Q [X |-> a]}} (X ::= a) {{Q}}.
Proof.
unfold hoare_triple.
intros Q X a st st' HE HQ.
inversion HE. subst.
unfold assn_sub in HQ. assumption. Qed.
(** Here's a first formal proof using this rule. *)
Example assn_sub_example :
{{(fun st => st X = 3) [X |-> ANum 3]}}
(X ::= (ANum 3))
{{fun st => st X = 3}}.
Proof.
apply hoare_asgn. Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples) *)
(** Translate these informal Hoare triples...
1) {{ (X <= 5) [X |-> X + 1] }}
X ::= X + 1
{{ X <= 5 }}
2) {{ (0 <= X /\ X <= 5) [X |-> 3] }}
X ::= 3
{{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars (hoare_asgn_wrong) *)
(** The assignment rule looks backward to almost everyone the first
time they see it. If it still seems backward to you, it may help
to think a little about alternative "forward" rules. Here is a
seemingly natural one:
------------------------------ (hoare_asgn_wrong)
{{ True }} X ::= a {{ X = a }}
Give a counterexample showing that this rule is incorrect
(informally). Hint: The rule universally quantifies over the
arithmetic expression [a], and your counterexample needs to
exhibit an [a] for which the rule doesn't work. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, advanced (hoare_asgn_fwd) *)
(** However, using an auxiliary variable [m] to remember the original
value of [X] we can define a Hoare rule for assignment that does,
intuitively, "work forwards" rather than backwards.
------------------------------------------ (hoare_asgn_fwd)
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P st' /\ st X = aeval st' a }}
(where st' = update st X m)
Note that we use the original value of [X] to reconstruct the
state [st'] before the assignment took place. Prove that this rule
is correct (the first hypothesis is the functional extensionality
axiom, which you will need at some point). Also note that this
rule is more complicated than [hoare_asgn].
*)
Theorem hoare_asgn_fwd :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall m a P,
{{fun st => P st /\ st X = m}}
X ::= a
{{fun st => P (update st X m) /\ st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality m a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (hoare_asgn_fwd_exists) *)
(** Another way to define a forward rule for assignment is to
existentially quantify over the previous value of the assigned
variable.
------------------------------------------ (hoare_asgn_fwd_exists)
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}
*)
(* This rule was proposed by Nick Giannarakis and Zoe Paraskevopoulou. *)
Theorem hoare_asgn_fwd_exists :
(forall {X Y: Type} {f g : X -> Y},
(forall (x: X), f x = g x) -> f = g) ->
forall a P,
{{fun st => P st}}
X ::= a
{{fun st => exists m, P (update st X m) /\
st X = aeval (update st X m) a }}.
Proof.
intros functional_extensionality a P.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ####################################################### *)
(** *** Consequence *)
(** Sometimes the preconditions and postconditions we get from the
Hoare rules won't quite be the ones we want in the particular
situation at hand -- they may be logically equivalent but have a
different syntactic form that fails to unify with the goal we are
trying to prove, or they actually may be logically weaker (for
preconditions) or stronger (for postconditions) than what we need.
For instance, while
{{(X = 3) [X |-> 3]}} X ::= 3 {{X = 3}},
follows directly from the assignment rule,
{{True}} X ::= 3 {{X = 3}}.
does not. This triple is valid, but it is not an instance of
[hoare_asgn] because [True] and [(X = 3) [X |-> 3]] are not
syntactically equal assertions. However, they are logically
equivalent, so if one triple is valid, then the other must
certainly be as well. We might capture this observation with the
following rule:
{{P'}} c {{Q}}
P <<->> P'
----------------------------- (hoare_consequence_pre_equiv)
{{P}} c {{Q}}
Taking this line of thought a bit further, we can see that
strengthening the precondition or weakening the postcondition of a
valid triple always produces another valid triple. This
observation is captured by two _Rules of Consequence_.
{{P'}} c {{Q}}
P ->> P'
----------------------------- (hoare_consequence_pre)
{{P}} c {{Q}}
{{P}} c {{Q'}}
Q' ->> Q
----------------------------- (hoare_consequence_post)
{{P}} c {{Q}}
*)
(** Here are the formal versions: *)
Theorem hoare_consequence_pre : forall (P P' Q : Assertion) c,
{{P'}} c {{Q}} ->
P ->> P' ->
{{P}} c {{Q}}.
Proof.
intros P P' Q c Hhoare Himp.
intros st st' Hc HP. apply (Hhoare st st').
assumption. apply Himp. assumption. Qed.
Theorem hoare_consequence_post : forall (P Q Q' : Assertion) c,
{{P}} c {{Q'}} ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P Q Q' c Hhoare Himp.
intros st st' Hc HP.
apply Himp.
apply (Hhoare st st').
assumption. assumption. Qed.
(** For example, we might use the first consequence rule like this:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1
{{ X = 1 }}
Or, formally...
*)
Example hoare_asgn_example1 :
{{fun st => True}} (X ::= (ANum 1)) {{fun st => st X = 1}}.
Proof.
apply hoare_consequence_pre
with (P' := (fun st => st X = 1) [X |-> ANum 1]).
apply hoare_asgn.
intros st H. unfold assn_sub, update. simpl. reflexivity.
Qed.
(** Finally, for convenience in some proofs, we can state a "combined"
rule of consequence that allows us to vary both the precondition
and the postcondition.
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
Theorem hoare_consequence : forall (P P' Q Q' : Assertion) c,
{{P'}} c {{Q'}} ->
P ->> P' ->
Q' ->> Q ->
{{P}} c {{Q}}.
Proof.
intros P P' Q Q' c Hht HPP' HQ'Q.
apply hoare_consequence_pre with (P' := P').
apply hoare_consequence_post with (Q' := Q').
assumption. assumption. assumption. Qed.
(* ####################################################### *)
(** *** Digression: The [eapply] Tactic *)
(** This is a good moment to introduce another convenient feature of
Coq. We had to write "[with (P' := ...)]" explicitly in the proof
of [hoare_asgn_example1] and [hoare_consequence] above, to make
sure that all of the metavariables in the premises to the
[hoare_consequence_pre] rule would be set to specific
values. (Since [P'] doesn't appear in the conclusion of
[hoare_consequence_pre], the process of unifying the conclusion
with the current goal doesn't constrain [P'] to a specific
assertion.)
This is a little annoying, both because the assertion is a bit
long and also because for [hoare_asgn_example1] the very next
thing we are going to do -- applying the [hoare_asgn] rule -- will
tell us exactly what it should be! We can use [eapply] instead of
[apply] to tell Coq, essentially, "Be patient: The missing part is
going to be filled in soon." *)
Example hoare_asgn_example1' :
{{fun st => True}}
(X ::= (ANum 1))
{{fun st => st X = 1}}.
Proof.
eapply hoare_consequence_pre.
apply hoare_asgn.
intros st H. reflexivity. Qed.
(** In general, [eapply H] tactic works just like [apply H] except
that, instead of failing if unifying the goal with the conclusion
of [H] does not determine how to instantiate all of the variables
appearing in the premises of [H], [eapply H] will replace these
variables with so-called _existential variables_ (written [?nnn])
as placeholders for expressions that will be determined (by
further unification) later in the proof. *)
(** In order for [Qed] to succeed, all existential variables need to
be determined by the end of the proof. Otherwise Coq
will (rightly) refuse to accept the proof. Remember that the Coq
tactics build proof objects, and proof objects containing
existential variables are not complete. *)
Lemma silly1 : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(forall x y : nat, P x y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. apply HP.
(** Coq gives a warning after [apply HP]:
No more subgoals but non-instantiated existential variables:
Existential 1 =
?171 : [P : nat -> nat -> Prop
Q : nat -> Prop
HP : forall x y : nat, P x y
HQ : forall x y : nat, P x y -> Q x |- nat]
(dependent evars: ?171 open,)
You can use Grab Existential Variables.
Trying to finish the proof with [Qed] gives an error:
<<
Error: Attempt to save a proof with existential variables still
non-instantiated
>> *)
Abort.
(** An additional constraint is that existential variables cannot be
instantiated with terms containing (ordinary) variables that did
not exist at the time the existential variable was created. *)
Lemma silly2 :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. eapply HQ. destruct HP as [y HP'].
(** Doing [apply HP'] above fails with the following error:
Error: Impossible to unify "?175" with "y".
In this case there is an easy fix:
doing [destruct HP] _before_ doing [eapply HQ].
*)
Abort.
Lemma silly2_fixed :
forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP'].
eapply HQ. apply HP'.
Qed.
(** In the last step we did [apply HP'] which unifies the existential
variable in the goal with the variable [y]. The [assumption]
tactic doesn't work in this case, since it cannot handle
existential variables. However, Coq also provides an [eassumption]
tactic that solves the goal if one of the premises matches the
goal up to instantiations of existential variables. We can use
it instead of [apply HP']. *)
Lemma silly2_eassumption : forall (P : nat -> nat -> Prop) (Q : nat -> Prop),
(exists y, P 42 y) ->
(forall x y : nat, P x y -> Q x) ->
Q 42.
Proof.
intros P Q HP HQ. destruct HP as [y HP']. eapply HQ. eassumption.
Qed.
(** **** Exercise: 2 stars (hoare_asgn_examples_2) *)
(** Translate these informal Hoare triples...
{{ X + 1 <= 5 }} X ::= X + 1 {{ X <= 5 }}
{{ 0 <= 3 /\ 3 <= 5 }} X ::= 3 {{ 0 <= X /\ X <= 5 }}
...into formal statements and use [hoare_asgn] and
[hoare_consequence_pre] to prove them. *)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Skip *)
(** Since [SKIP] doesn't change the state, it preserves any
property P:
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
*)
Theorem hoare_skip : forall P,
{{P}} SKIP {{P}}.
Proof.
intros P st st' H HP. inversion H. subst.
assumption. Qed.
(* ####################################################### *)
(** *** Sequencing *)
(** More interestingly, if the command [c1] takes any state where
[P] holds to a state where [Q] holds, and if [c2] takes any
state where [Q] holds to one where [R] holds, then doing [c1]
followed by [c2] will take any state where [P] holds to one
where [R] holds:
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
*)
Theorem hoare_seq : forall P Q R c1 c2,
{{Q}} c2 {{R}} ->
{{P}} c1 {{Q}} ->
{{P}} c1;;c2 {{R}}.
Proof.
intros P Q R c1 c2 H1 H2 st st' H12 Pre.
inversion H12; subst.
apply (H1 st'0 st'); try assumption.
apply (H2 st st'0); assumption. Qed.
(** Note that, in the formal rule [hoare_seq], the premises are
given in "backwards" order ([c2] before [c1]). This matches the
natural flow of information in many of the situations where we'll
use the rule: the natural way to construct a Hoare-logic proof is
to begin at the end of the program (with the final postcondition)
and push postconditions backwards through commands until we reach
the beginning. *)
(** Informally, a nice way of recording a proof using the sequencing
rule is as a "decorated program" where the intermediate assertion
[Q] is written between [c1] and [c2]:
{{ a = n }}
X ::= a;;
{{ X = n }} <---- decoration for Q
SKIP
{{ X = n }}
*)
Example hoare_asgn_example3 : forall a n,
{{fun st => aeval st a = n}}
(X ::= a;; SKIP)
{{fun st => st X = n}}.
Proof.
intros a n. eapply hoare_seq.
Case "right part of seq".
apply hoare_skip.
Case "left part of seq".
eapply hoare_consequence_pre. apply hoare_asgn.
intros st H. subst. reflexivity. Qed.
(** You will most often use [hoare_seq] and
[hoare_consequence_pre] in conjunction with the [eapply] tactic,
as done above. *)
(** **** Exercise: 2 stars (hoare_asgn_example4) *)
(** Translate this "decorated program" into a formal proof:
{{ True }} ->>
{{ 1 = 1 }}
X ::= 1;;
{{ X = 1 }} ->>
{{ X = 1 /\ 2 = 2 }}
Y ::= 2
{{ X = 1 /\ Y = 2 }}
*)
Example hoare_asgn_example4 :
{{fun st => True}} (X ::= (ANum 1);; Y ::= (ANum 2))
{{fun st => st X = 1 /\ st Y = 2}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (swap_exercise) *)
(** Write an Imp program [c] that swaps the values of [X] and [Y]
and show (in Coq) that it satisfies the following
specification:
{{X <= Y}} c {{Y <= X}}
*)
Definition swap_program : com :=
(* FILL IN HERE *) admit.
Theorem swap_exercise :
{{fun st => st X <= st Y}}
swap_program
{{fun st => st Y <= st X}}.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (hoarestate1) *)
(** Explain why the following proposition can't be proven:
forall (a : aexp) (n : nat),
{{fun st => aeval st a = n}}
(X ::= (ANum 3);; Y ::= a)
{{fun st => st Y = n}}.
*)
(* FILL IN HERE *)
(** [] *)
(* ####################################################### *)
(** *** Conditionals *)
(** What sort of rule do we want for reasoning about conditional
commands? Certainly, if the same assertion [Q] holds after
executing either branch, then it holds after the whole
conditional. So we might be tempted to write:
{{P}} c1 {{Q}}
{{P}} c2 {{Q}}
--------------------------------
{{P}} IFB b THEN c1 ELSE c2 {{Q}}
However, this is rather weak. For example, using this rule,
we cannot show that:
{{ True }}
IFB X == 0
THEN Y ::= 2
ELSE Y ::= X + 1
FI
{{ X <= Y }}
since the rule tells us nothing about the state in which the
assignments take place in the "then" and "else" branches. *)
(** But we can actually say something more precise. In the
"then" branch, we know that the boolean expression [b] evaluates to
[true], and in the "else" branch, we know it evaluates to [false].
Making this information available in the premises of the rule gives
us more information to work with when reasoning about the behavior
of [c1] and [c2] (i.e., the reasons why they establish the
postcondition [Q]). *)
(**
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
*)
(** To interpret this rule formally, we need to do a little work.
Strictly speaking, the assertion we've written, [P /\ b], is the
conjunction of an assertion and a boolean expression -- i.e., it
doesn't typecheck. To fix this, we need a way of formally
"lifting" any bexp [b] to an assertion. We'll write [bassn b] for
the assertion "the boolean expression [b] evaluates to [true] (in
the given state)." *)
Definition bassn b : Assertion :=
fun st => (beval st b = true).
(** A couple of useful facts about [bassn]: *)
Lemma bexp_eval_true : forall b st,
beval st b = true -> (bassn b) st.
Proof.
intros b st Hbe.
unfold bassn. assumption. Qed.
Lemma bexp_eval_false : forall b st,
beval st b = false -> ~ ((bassn b) st).
Proof.
intros b st Hbe contra.
unfold bassn in contra.
rewrite -> contra in Hbe. inversion Hbe. Qed.
(** Now we can formalize the Hoare proof rule for conditionals
and prove it correct. *)
Theorem hoare_if : forall P Q b c1 c2,
{{fun st => P st /\ bassn b st}} c1 {{Q}} ->
{{fun st => P st /\ ~(bassn b st)}} c2 {{Q}} ->
{{P}} (IFB b THEN c1 ELSE c2 FI) {{Q}}.
Proof.
intros P Q b c1 c2 HTrue HFalse st st' HE HP.
inversion HE; subst.
Case "b is true".
apply (HTrue st st').
assumption.
split. assumption.
apply bexp_eval_true. assumption.
Case "b is false".
apply (HFalse st st').
assumption.
split. assumption.
apply bexp_eval_false. assumption. Qed.
(* ####################################################### *)
(** * Hoare Logic: So Far *)
(**
Idea: create a _domain specific logic_ for reasoning about properties of Imp programs.
- This hides the low-level details of the semantics of the program
- Leads to a compositional reasoning process
The basic structure is given by _Hoare triples_ of the form:
{{P}} c {{Q}}
]]
- [P] and [Q] are predicates about the state of the Imp program
- "If command [c] is started in a state satisfying assertion
[P], and if [c] eventually terminates in some final state,
then this final state will satisfy the assertion [Q]."
*)
(** ** Hoare Logic Rules (so far) *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
*)
(** *** Example *)
(** Here is a formal proof that the program we used to motivate the
rule satisfies the specification we gave. *)
Example if_example :
{{fun st => True}}
IFB (BEq (AId X) (ANum 0))
THEN (Y ::= (ANum 2))
ELSE (Y ::= APlus (AId X) (ANum 1))
FI
{{fun st => st X <= st Y}}.
Proof.
(* WORKED IN CLASS *)
apply hoare_if.
Case "Then".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold bassn, assn_sub, update, assert_implies.
simpl. intros st [_ H].
apply beq_nat_true in H.
rewrite H. omega.
Case "Else".
eapply hoare_consequence_pre. apply hoare_asgn.
unfold assn_sub, update, assert_implies.
simpl; intros st _. omega.
Qed.
(** **** Exercise: 2 stars (if_minus_plus) *)
(** Prove the following hoare triple using [hoare_if]: *)
Theorem if_minus_plus :
{{fun st => True}}
IFB (BLe (AId X) (AId Y))
THEN (Z ::= AMinus (AId Y) (AId X))
ELSE (Y ::= APlus (AId X) (AId Z))
FI
{{fun st => st Y = st X + st Z}}.
Proof.
(* FILL IN HERE *) Admitted.
(* ####################################################### *)
(** *** Exercise: One-sided conditionals *)
(** **** Exercise: 4 stars (if1_hoare) *)
(** In this exercise we consider extending Imp with "one-sided
conditionals" of the form [IF1 b THEN c FI]. Here [b] is a
boolean expression, and [c] is a command. If [b] evaluates to
[true], then command [c] is evaluated. If [b] evaluates to
[false], then [IF1 b THEN c FI] does nothing.
We recommend that you do this exercise before the ones that
follow, as it should help solidify your understanding of the
material. *)
(** The first step is to extend the syntax of commands and introduce
the usual notations. (We've done this for you. We use a separate
module to prevent polluting the global name space.) *)
Module If1.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CIf1 : bexp -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "CIF1" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAss X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'IF1' b 'THEN' c 'FI'" :=
(CIf1 b c) (at level 80, right associativity).
(** Next we need to extend the evaluation relation to accommodate
[IF1] branches. This is for you to do... What rule(s) need to be
added to [ceval] to evaluate one-sided conditionals? *)
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
(* FILL IN HERE *)
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** Now we repeat (verbatim) the definition and notation of Hoare triples. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st',
c / st || st' ->
P st ->
Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Finally, we (i.e., you) need to state and prove a theorem,
[hoare_if1], that expresses an appropriate Hoare logic proof rule
for one-sided conditionals. Try to come up with a rule that is
both sound and as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, prove formally that your rule is precise enough
to show the following valid Hoare triple:
{{ X + Y = Z }}
IF1 Y <> 0 THEN
X ::= X + Y
FI
{{ X = Z }}
*)
(** Hint: Your proof of this triple may need to use the other proof
rules also. Because we're working in a separate module, you'll
need to copy here the rules you find necessary. *)
Lemma hoare_if1_good :
{{ fun st => st X + st Y = st Z }}
IF1 BNot (BEq (AId Y) (ANum 0)) THEN
X ::= APlus (AId X) (AId Y)
FI
{{ fun st => st X = st Z }}.
Proof. (* FILL IN HERE *) Admitted.
End If1.
(** [] *)
(* ####################################################### *)
(** *** Loops *)
(** Finally, we need a rule for reasoning about while loops. *)
(** Suppose we have a loop
WHILE b DO c END
and we want to find a pre-condition [P] and a post-condition
[Q] such that
{{P}} WHILE b DO c END {{Q}}
is a valid triple. *)
(** *** *)
(** First of all, let's think about the case where [b] is false at the
beginning -- i.e., let's assume that the loop body never executes
at all. In this case, the loop behaves like [SKIP], so we might
be tempted to write: *)
(**
{{P}} WHILE b DO c END {{P}}.
*)
(**
But, as we remarked above for the conditional, we know a
little more at the end -- not just [P], but also the fact
that [b] is false in the current state. So we can enrich the
postcondition a little:
*)
(**
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
What about the case where the loop body _does_ get executed?
In order to ensure that [P] holds when the loop finally
exits, we certainly need to make sure that the command [c]
guarantees that [P] holds whenever [c] is finished.
Moreover, since [P] holds at the beginning of the first
execution of [c], and since each execution of [c]
re-establishes [P] when it finishes, we can always assume
that [P] holds at the beginning of [c]. This leads us to the
following rule:
*)
(**
{{P}} c {{P}}
-----------------------------------
{{P}} WHILE b DO c END {{P /\ ~b}}
*)
(**
This is almost the rule we want, but again it can be improved a
little: at the beginning of the loop body, we know not only that
[P] holds, but also that the guard [b] is true in the current
state. This gives us a little more information to use in
reasoning about [c] (showing that it establishes the invariant by
the time it finishes). This gives us the final version of the rule:
*)
(**
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
The proposition [P] is called an _invariant_ of the loop.
*)
Lemma hoare_while : forall P b c,
{{fun st => P st /\ bassn b st}} c {{P}} ->
{{P}} WHILE b DO c END {{fun st => P st /\ ~ (bassn b st)}}.
Proof.
intros P b c Hhoare st st' He HP.
(* Like we've seen before, we need to reason by induction
on [He], because, in the "keep looping" case, its hypotheses
talk about the whole loop instead of just [c]. *)
remember (WHILE b DO c END) as wcom eqn:Heqwcom.
ceval_cases (induction He) Case;
try (inversion Heqwcom); subst; clear Heqwcom.
Case "E_WhileEnd".
split. assumption. apply bexp_eval_false. assumption.
Case "E_WhileLoop".
apply IHHe2. reflexivity.
apply (Hhoare st st'). assumption.
split. assumption. apply bexp_eval_true. assumption.
Qed.
(**
One subtlety in the terminology is that calling some assertion [P]
a "loop invariant" doesn't just mean that it is preserved by the
body of the loop in question (i.e., [{{P}} c {{P}}], where [c] is
the loop body), but rather that [P] _together with the fact that
the loop's guard is true_ is a sufficient precondition for [c] to
ensure [P] as a postcondition.
This is a slightly (but significantly) weaker requirement. For
example, if [P] is the assertion [X = 0], then [P] _is_ an
invariant of the loop
WHILE X = 2 DO X := 1 END
although it is clearly _not_ preserved by the body of the
loop.
*)
Example while_example :
{{fun st => st X <= 3}}
WHILE (BLe (AId X) (ANum 2))
DO X ::= APlus (AId X) (ANum 1) END
{{fun st => st X = 3}}.
Proof.
eapply hoare_consequence_post.
apply hoare_while.
eapply hoare_consequence_pre.
apply hoare_asgn.
unfold bassn, assn_sub, assert_implies, update. simpl.
intros st [H1 H2]. apply ble_nat_true in H2. omega.
unfold bassn, assert_implies. intros st [Hle Hb].
simpl in Hb. destruct (ble_nat (st X) 2) eqn : Heqle.
apply ex_falso_quodlibet. apply Hb; reflexivity.
apply ble_nat_false in Heqle. omega.
Qed.
(** *** *)
(** We can use the while rule to prove the following Hoare triple,
which may seem surprising at first... *)
Theorem always_loop_hoare : forall P Q,
{{P}} WHILE BTrue DO SKIP END {{Q}}.
Proof.
(* WORKED IN CLASS *)
intros P Q.
apply hoare_consequence_pre with (P' := fun st : state => True).
eapply hoare_consequence_post.
apply hoare_while.
Case "Loop body preserves invariant".
apply hoare_post_true. intros st. apply I.
Case "Loop invariant and negated guard imply postcondition".
simpl. intros st [Hinv Hguard].
apply ex_falso_quodlibet. apply Hguard. reflexivity.
Case "Precondition implies invariant".
intros st H. constructor. Qed.
(** Of course, this result is not surprising if we remember that
the definition of [hoare_triple] asserts that the postcondition
must hold _only_ when the command terminates. If the command
doesn't terminate, we can prove anything we like about the
post-condition. *)
(** Hoare rules that only talk about terminating commands are
often said to describe a logic of "partial" correctness. It is
also possible to give Hoare rules for "total" correctness, which
build in the fact that the commands terminate. However, in this
course we will only talk about partial correctness. *)
(* ####################################################### *)
(** *** Exercise: [REPEAT] *)
Module RepeatExercise.
(** **** Exercise: 4 stars, advanced (hoare_repeat) *)
(** In this exercise, we'll add a new command to our language of
commands: [REPEAT] c [UNTIL] a [END]. You will write the
evaluation rule for [repeat] and add a new Hoare rule to
the language for programs involving it. *)
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CRepeat : com -> bexp -> com.
(** [REPEAT] behaves like [WHILE], except that the loop guard is
checked _after_ each execution of the body, with the loop
repeating as long as the guard stays _false_. Because of this,
the body will always execute at least once. *)
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE"
| Case_aux c "CRepeat" ].
Notation "'SKIP'" :=
CSkip.
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'REPEAT' e1 'UNTIL' b2 'END'" :=
(CRepeat e1 b2) (at level 80, right associativity).
(** Add new rules for [REPEAT] to [ceval] below. You can use the rules
for [WHILE] as a guide, but remember that the body of a [REPEAT]
should always execute at least once, and that the loop ends when
the guard becomes true. Then update the [ceval_cases] tactic to
handle these added cases. *)
Inductive ceval : state -> com -> state -> Prop :=
| E_Skip : forall st,
ceval st SKIP st
| E_Ass : forall st a1 n X,
aeval st a1 = n ->
ceval st (X ::= a1) (update st X n)
| E_Seq : forall c1 c2 st st' st'',
ceval st c1 st' ->
ceval st' c2 st'' ->
ceval st (c1 ;; c2) st''
| E_IfTrue : forall st st' b1 c1 c2,
beval st b1 = true ->
ceval st c1 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_IfFalse : forall st st' b1 c1 c2,
beval st b1 = false ->
ceval st c2 st' ->
ceval st (IFB b1 THEN c1 ELSE c2 FI) st'
| E_WhileEnd : forall b1 st c1,
beval st b1 = false ->
ceval st (WHILE b1 DO c1 END) st
| E_WhileLoop : forall st st' st'' b1 c1,
beval st b1 = true ->
ceval st c1 st' ->
ceval st' (WHILE b1 DO c1 END) st'' ->
ceval st (WHILE b1 DO c1 END) st''
(* FILL IN HERE *)
.
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass"
| Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
(* FILL IN HERE *)
].
(** A couple of definitions from above, copied here so they use the
new [ceval]. *)
Notation "c1 '/' st '||' st'" := (ceval st c1 st')
(at level 40, st at level 39).
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion)
: Prop :=
forall st st', (c / st || st') -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" :=
(hoare_triple P c Q) (at level 90, c at next level).
(** To make sure you've got the evaluation rules for [REPEAT] right,
prove that [ex1_repeat evaluates correctly. *)
Definition ex1_repeat :=
REPEAT
X ::= ANum 1;;
Y ::= APlus (AId Y) (ANum 1)
UNTIL (BEq (AId X) (ANum 1)) END.
Theorem ex1_repeat_works :
ex1_repeat / empty_state ||
update (update empty_state X 1) Y 1.
Proof.
(* FILL IN HERE *) Admitted.
(** Now state and prove a theorem, [hoare_repeat], that expresses an
appropriate proof rule for [repeat] commands. Use [hoare_while]
as a model, and try to make your rule as precise as possible. *)
(* FILL IN HERE *)
(** For full credit, make sure (informally) that your rule can be used
to prove the following valid Hoare triple:
{{ X > 0 }}
REPEAT
Y ::= X;;
X ::= X - 1
UNTIL X = 0 END
{{ X = 0 /\ Y > 0 }}
*)
End RepeatExercise.
(** [] *)
(* ####################################################### *)
(** ** Exercise: [HAVOC] *)
(** **** Exercise: 3 stars (himp_hoare) *)
(** In this exercise, we will derive proof rules for the [HAVOC] command
which we studied in the last chapter. First, we enclose this work
in a separate module, and recall the syntax and big-step semantics
of Himp commands. *)
Module Himp.
Inductive com : Type :=
| CSkip : com
| CAsgn : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
| CHavoc : id -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "HAVOC" ].
Notation "'SKIP'" :=
CSkip.
Notation "X '::=' a" :=
(CAsgn X a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' e1 'THEN' e2 'ELSE' e3 'FI'" :=
(CIf e1 e2 e3) (at level 80, right associativity).
Notation "'HAVOC' X" := (CHavoc X) (at level 60).
Reserved Notation "c1 '/' st '||' st'" (at level 40, st at level 39).
Inductive ceval : com -> state -> state -> Prop :=
| E_Skip : forall st : state, SKIP / st || st
| E_Ass : forall (st : state) (a1 : aexp) (n : nat) (X : id),
aeval st a1 = n -> (X ::= a1) / st || update st X n
| E_Seq : forall (c1 c2 : com) (st st' st'' : state),
c1 / st || st' -> c2 / st' || st'' -> (c1 ;; c2) / st || st''
| E_IfTrue : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = true ->
c1 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_IfFalse : forall (st st' : state) (b1 : bexp) (c1 c2 : com),
beval st b1 = false ->
c2 / st || st' -> (IFB b1 THEN c1 ELSE c2 FI) / st || st'
| E_WhileEnd : forall (b1 : bexp) (st : state) (c1 : com),
beval st b1 = false -> (WHILE b1 DO c1 END) / st || st
| E_WhileLoop : forall (st st' st'' : state) (b1 : bexp) (c1 : com),
beval st b1 = true ->
c1 / st || st' ->
(WHILE b1 DO c1 END) / st' || st'' ->
(WHILE b1 DO c1 END) / st || st''
| E_Havoc : forall (st : state) (X : id) (n : nat),
(HAVOC X) / st || update st X n
where "c1 '/' st '||' st'" := (ceval c1 st st').
Tactic Notation "ceval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Skip" | Case_aux c "E_Ass" | Case_aux c "E_Seq"
| Case_aux c "E_IfTrue" | Case_aux c "E_IfFalse"
| Case_aux c "E_WhileEnd" | Case_aux c "E_WhileLoop"
| Case_aux c "E_Havoc" ].
(** The definition of Hoare triples is exactly as before. Unlike our
notion of program equivalence, which had subtle consequences with
occassionally nonterminating commands (exercise [havoc_diverge]),
this definition is still fully satisfactory. Convince yourself of
this before proceeding. *)
Definition hoare_triple (P:Assertion) (c:com) (Q:Assertion) : Prop :=
forall st st', c / st || st' -> P st -> Q st'.
Notation "{{ P }} c {{ Q }}" := (hoare_triple P c Q)
(at level 90, c at next level)
: hoare_spec_scope.
(** Complete the Hoare rule for [HAVOC] commands below by defining
[havoc_pre] and prove that the resulting rule is correct. *)
Definition havoc_pre (X : id) (Q : Assertion) : Assertion :=
(* FILL IN HERE *) admit.
Theorem hoare_havoc : forall (Q : Assertion) (X : id),
{{ havoc_pre X Q }} HAVOC X {{ Q }}.
Proof.
(* FILL IN HERE *) Admitted.
End Himp.
(** [] *)
(* ####################################################### *)
(** ** Complete List of Hoare Logic Rules *)
(** Above, we've introduced Hoare Logic as a tool to reasoning
about Imp programs. In the reminder of this chapter we will
explore a systematic way to use Hoare Logic to prove properties
about programs. The rules of Hoare Logic are the following: *)
(**
------------------------------ (hoare_asgn)
{{Q [X |-> a]}} X::=a {{Q}}
-------------------- (hoare_skip)
{{ P }} SKIP {{ P }}
{{ P }} c1 {{ Q }}
{{ Q }} c2 {{ R }}
--------------------- (hoare_seq)
{{ P }} c1;;c2 {{ R }}
{{P /\ b}} c1 {{Q}}
{{P /\ ~b}} c2 {{Q}}
------------------------------------ (hoare_if)
{{P}} IFB b THEN c1 ELSE c2 FI {{Q}}
{{P /\ b}} c {{P}}
----------------------------------- (hoare_while)
{{P}} WHILE b DO c END {{P /\ ~b}}
{{P'}} c {{Q'}}
P ->> P'
Q' ->> Q
----------------------------- (hoare_consequence)
{{P}} c {{Q}}
In the next chapter, we'll see how these rules are used to prove
that programs satisfy specifications of their behavior.
*)
(* $Date: 2014-02-27 16:56:35 -0500 (Thu, 27 Feb 2014) $ *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__BUFINV_8_V
`define SKY130_FD_SC_HS__BUFINV_8_V
/**
* bufinv: Buffer followed by inverter.
*
* Verilog wrapper for bufinv with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__bufinv.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_8 (
Y ,
A ,
VPWR,
VGND
);
output Y ;
input A ;
input VPWR;
input VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__bufinv_8 (
Y,
A
);
output Y;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__bufinv base (
.Y(Y),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__BUFINV_8_V
|
`include "../RF/reg_file2.v"
module test;
reg [4:0] readReg1, readReg2, writeReg;
reg [31:0] writeData;
reg regWrite, clk;
wire [31:0] readData1, readData2;
reg_file rf(.readReg1(readReg1),
.readReg2(readReg2),
.writeReg(writeReg),
.writeData(writeData),
.regWrite(regWrite),
.clk(clk),
.readData1(readData1),
.readData2(readData2));
initial begin
$dumpfile("reg_file_wave.vcd");
$dumpvars(0, test);
//$monitor($time, ": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
// readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
clk = 0;
#5 writeReg = 0; writeData = 10; regWrite = 1;
#5 writeReg = 5;
#5 writeReg = 6;
#5 writeReg = 17;
#5 writeReg = 18;
#5 writeReg = 19;
#5 writeReg = 20;
#5 writeReg = 21;
#5 writeReg = 22;
#5 writeReg = 23;
#5 writeReg = 24;
#5 writeReg = 25;
#5 writeReg = 26;
#5 writeReg = 27;
#5 writeReg = 28;
#5 writeReg = 29;
#5 writeReg = 30;
#5 writeReg = 31;
#5 readReg1 = 0; readReg2 = 2;
#5;
$display(": readReg1=%5d, readReg2=%5d, writeReg=%5d, writeData=%5d, regWrite=%b, readData1=%5d, readData2=%5d",
readReg1, readReg2, writeReg, writeData, regWrite, readData1, readData2);
$finish;
end
always #1 clk = ~clk;
endmodule
|
//bug1061
//typedef logic [7:0] foo_t;
module ptype
(
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input foo_t a, // To b0 of ptype_buf.v, ...
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output foo_t y0, // From b0 of ptype_buf.v
output logic [7:0] y1, // From b1 of ptype_buf.v
output TYPE_T y2 // From b2 of ptype_buf.v
// End of automatics
);
ptype_buf #(.TYPE_T(foo_t)) b0
(// Outputs
.y (y0),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.TYPE_T(logic [7:0])) b1
(// Outputs
.y (y1),
/*AUTOINST*/
// Inputs
.a (a));
ptype_buf #(.WIDTH(8)) b2
(// Outputs
.y (y2),
/*AUTOINST*/
// Inputs
.a (a));
endmodule
module ptype_buf
#(parameter WIDTH = 1,
parameter type TYPE_T = logic [WIDTH-1:0])
(output TYPE_T y,
input TYPE_T a);
assign y = a;
endmodule
///--------------
// Example in docs
module InstModule (o,i);
parameter WIDTH;
input [WIDTH-1:0] i;
parameter type OUT_t;
output OUT_t o;
endmodule
module ExampInst;
/*AUTOINPUT*/
// Beginning of automatic inputs (from unused autoinst inputs)
input [9:0] i; // To instName of InstModule.v
// End of automatics
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output upper_t o; // From instName of InstModule.v
// End of automatics
InstModule
#(.WIDTH(10),
,.OUT_t(upper_t))
instName
(/*AUTOINST*/
// Outputs
.o (o),
// Inputs
.i (i[9:0]));
endmodule
// Local Variables:
// verilog-typedef-regexp: "_[tT]$"
// verilog-auto-inst-param-value:t
// verilog-auto-inst-param-value-type:t
// End:
|
(* This program is free software; you can redistribute it and/or *)
(* modify it under the terms of the GNU Lesser General Public License *)
(* as published by the Free Software Foundation; either version 2.1 *)
(* of the License, or (at your option) any later version. *)
(* *)
(* This program is distributed in the hope that it will be useful, *)
(* but WITHOUT ANY WARRANTY; without even the implied warranty of *)
(* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *)
(* GNU General Public License for more details. *)
(* *)
(* You should have received a copy of the GNU Lesser General Public *)
(* License along with this program; if not, write to the Free *)
(* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA *)
(* 02110-1301 USA *)
(** This file includes random facts about Integers (and natural numbers) which are not found in the standard library. Some of the lemma here are not used in the QArith developement but are rather useful.
*)
Require Export ZArith.
Require Export ZArithRing.
Tactic Notation "ElimCompare" constr(c) constr(d) := elim_compare c d.
Ltac Flip :=
apply Zgt_lt || apply Zlt_gt || apply Zle_ge || apply Zge_le; assumption.
Ltac Falsum :=
try intro; apply False_ind;
repeat
match goal with
| id1:(~ ?X1) |- ?X2 =>
(apply id1; assumption || reflexivity) || clear id1
end.
Ltac Step_l a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X1 with a; [ idtac | try ring ]
end.
Ltac Step_r a :=
match goal with
| |- (?X1 < ?X2)%Z => replace X2 with a; [ idtac | try ring ]
end.
Ltac CaseEq formula :=
generalize (refl_equal formula); pattern formula at -1 in |- *;
case formula.
Lemma pair_1 : forall (A B : Set) (H : A * B), H = pair (fst H) (snd H).
Proof.
intros.
case H.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma pair_2 :
forall (A B : Set) (H1 H2 : A * B),
fst H1 = fst H2 -> snd H1 = snd H2 -> H1 = H2.
Proof.
intros A B H1 H2.
case H1.
case H2.
simpl in |- *.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Section projection.
Variable A : Set.
Variable P : A -> Prop.
Definition projP1 (H : sig P) := let (x, h) := H in x.
Definition projP2 (H : sig P) :=
let (x, h) as H return (P (projP1 H)) := H in h.
End projection.
(*###########################################################################*)
(* Declaring some realtions on natural numbers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma le_stepl: forall x y z, le x y -> x=z -> le z y.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma le_stepr: forall x y z, le x y -> y=z -> le x z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma lt_stepl: forall x y z, lt x y -> x=z -> lt z y.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma lt_stepr: forall x y z, lt x y -> y=z -> lt x z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma neq_stepl:forall (x y z:nat), x<>y -> x=z -> z<>y.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma neq_stepr:forall (x y z:nat), x<>y -> y=z -> x<>z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step le_stepl.
Declare Right Step le_stepr.
Declare Left Step lt_stepl.
Declare Right Step lt_stepr.
Declare Left Step neq_stepl.
Declare Right Step neq_stepr.
(*###########################################################################*)
(** Some random facts about natural numbers, positive numbers and integers *)
(*###########################################################################*)
Lemma not_O_S : forall n : nat, n <> 0 -> {p : nat | n = S p}.
Proof.
intros [| np] Hn; [ exists 0; apply False_ind; apply Hn | exists np ];
reflexivity.
Qed.
Lemma lt_minus_neq : forall m n : nat, m < n -> n - m <> 0.
Proof.
intros.
omega.
Qed.
Lemma lt_minus_eq_0 : forall m n : nat, m < n -> m - n = 0.
Proof.
intros.
omega.
Qed.
Lemma le_plus_Sn_1_SSn : forall n : nat, S n + 1 <= S (S n).
Proof.
intros.
omega.
Qed.
Lemma le_plus_O_l : forall p q : nat, p + q <= 0 -> p = 0.
Proof.
intros; omega.
Qed.
Lemma le_plus_O_r : forall p q : nat, p + q <= 0 -> q = 0.
Proof.
intros; omega.
Qed.
Lemma minus_pred : forall m n : nat, 0 < n -> pred m - pred n = m - n.
Proof.
intros.
omega.
Qed.
(*###########################################################################*)
(* Declaring some realtions on integers for stepl and stepr tactics. *)
(*###########################################################################*)
Lemma Zle_stepl: forall x y z, (x<=y)%Z -> x=z -> (z<=y)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zle_stepr: forall x y z, (x<=y)%Z -> y=z -> (x<=z)%Z.
Proof.
intros x y z H_le H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepl: forall x y z, (x<y)%Z -> x=z -> (z<y)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zlt_stepr: forall x y z, (x<y)%Z -> y=z -> (x<z)%Z.
Proof.
intros x y z H_lt H_eq; subst z; trivial.
Qed.
Lemma Zneq_stepl:forall (x y z:Z), (x<>y)%Z -> x=z -> (z<>y)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Lemma Zneq_stepr:forall (x y z:Z), (x<>y)%Z -> y=z -> (x<>z)%Z.
Proof.
intros x y z H_lt H_eq; subst; assumption.
Qed.
Declare Left Step Zle_stepl.
Declare Right Step Zle_stepr.
Declare Left Step Zlt_stepl.
Declare Right Step Zlt_stepr.
Declare Left Step Zneq_stepl.
Declare Right Step Zneq_stepr.
(*###########################################################################*)
(** Informative case analysis *)
(*###########################################################################*)
Lemma Zlt_cotrans :
forall x y : Z, (x < y)%Z -> forall z : Z, {(x < z)%Z} + {(z < y)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x z).
intro.
left.
assumption.
intro.
right.
apply Zle_lt_trans with (m := x).
apply Zge_le.
assumption.
assumption.
Qed.
Lemma Zlt_cotrans_pos :
forall x y : Z, (0 < x + y)%Z -> {(0 < x)%Z} + {(0 < y)%Z}.
Proof.
intros.
case (Zlt_cotrans 0 (x + y) H x).
intro.
left.
assumption.
intro.
right.
apply Zplus_lt_reg_l with (p := x).
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_cotrans_neg :
forall x y : Z, (x + y < 0)%Z -> {(x < 0)%Z} + {(y < 0)%Z}.
Proof.
intros x y H; case (Zlt_cotrans (x + y) 0 H x); intro Hxy;
[ right; apply Zplus_lt_reg_l with (p := x); rewrite Zplus_0_r | left ];
assumption.
Qed.
Lemma not_Zeq_inf : forall x y : Z, x <> y -> {(x < y)%Z} + {(y < x)%Z}.
Proof.
intros.
case Z_lt_ge_dec with x y.
intro.
left.
assumption.
intro H0.
generalize (Zge_le _ _ H0).
intro.
case (Z_le_lt_eq_dec _ _ H1).
intro.
right.
assumption.
intro.
apply False_rec.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec : forall x y : Z, {(x < y)%Z} + {(x > y)%Z} + {x = y}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro H.
left.
left.
assumption.
intro H.
generalize (Zge_le _ _ H).
intro H0.
case (Z_le_lt_eq_dec y x H0).
intro H1.
left.
right.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
Qed.
Lemma Z_dec' : forall x y : Z, {(x < y)%Z} + {(y < x)%Z} + {x = y}.
Proof.
intros x y.
case (Z_eq_dec x y); intro H;
[ right; assumption | left; apply (not_Zeq_inf _ _ H) ].
Qed.
Lemma Z_lt_le_dec : forall x y : Z, {(x < y)%Z} + {(y <= x)%Z}.
Proof.
intros.
case (Z_lt_ge_dec x y).
intro.
left.
assumption.
intro.
right.
apply Zge_le.
assumption.
Qed.
Lemma Z_le_lt_dec : forall x y : Z, {(x <= y)%Z} + {(y < x)%Z}.
Proof.
intros; case (Z_lt_le_dec y x); [ right | left ]; assumption.
Qed.
Lemma Z_lt_lt_S_eq_dec :
forall x y : Z, (x < y)%Z -> {(x + 1 < y)%Z} + {(x + 1)%Z = y}.
Proof.
intros.
generalize (Zlt_le_succ _ _ H).
unfold Zsucc in |- *.
apply Z_le_lt_eq_dec.
Qed.
Lemma quadro_leq_inf :
forall a b c d : Z,
{(c <= a)%Z /\ (d <= b)%Z} + {~ ((c <= a)%Z /\ (d <= b)%Z)}.
Proof.
intros.
case (Z_lt_le_dec a c).
intro z.
right.
intro.
elim H.
intros.
generalize z.
apply Zle_not_lt.
assumption.
intro.
case (Z_lt_le_dec b d).
intro z0.
right.
intro.
elim H.
intros.
generalize z0.
apply Zle_not_lt.
assumption.
intro.
left.
split.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** General auxiliary lemmata *)
(*###########################################################################*)
Lemma Zminus_eq : forall x y : Z, (x - y)%Z = 0%Z -> x = y.
Proof.
intros.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
unfold Zminus in H.
rewrite Zplus_comm.
assumption.
Qed.
Lemma Zlt_minus : forall a b : Z, (b < a)%Z -> (0 < a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_lt_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zle_minus : forall a b : Z, (b <= a)%Z -> (0 <= a - b)%Z.
Proof.
intros a b.
intros.
apply Zplus_le_reg_l with b.
unfold Zminus in |- *.
rewrite (Zplus_comm a).
rewrite (Zplus_assoc b (- b)).
rewrite Zplus_opp_r.
simpl in |- *.
rewrite <- Zplus_0_r_reverse.
assumption.
Qed.
Lemma Zlt_plus_plus :
forall m n p q : Z, (m < n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
apply Zlt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_lt_compat_l.
assumption.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zgt_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
intros.
apply Zgt_trans with (m := (n + p)%Z).
rewrite Zplus_comm.
rewrite Zplus_comm with (n := n).
apply Zplus_gt_compat_l.
assumption.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zle_lt_plus_plus :
forall m n p q : Z, (m <= n)%Z -> (p < q)%Z -> (m + p < n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq m n).
assumption.
intro.
apply Zlt_plus_plus.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma Zge_gt_plus_plus :
forall m n p q : Z, (m >= n)%Z -> (p > q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
case (Zle_lt_or_eq n m).
apply Zge_le.
assumption.
intro.
apply Zgt_plus_plus.
apply Zlt_gt.
assumption.
assumption.
intro.
rewrite H1.
apply Zplus_gt_compat_l.
assumption.
Qed.
Lemma Zgt_ge_plus_plus :
forall m n p q : Z, (m > n)%Z -> (p >= q)%Z -> (m + p > n + q)%Z.
Proof.
intros.
rewrite Zplus_comm.
replace (n + q)%Z with (q + n)%Z.
apply Zge_gt_plus_plus.
assumption.
assumption.
apply Zplus_comm.
Qed.
Lemma Zlt_resp_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x + y)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zlt_plus_plus; assumption.
Qed.
Lemma Zle_resp_neg :
forall x y : Z, (x <= 0)%Z -> (y <= 0)%Z -> (x + y <= 0)%Z.
Proof.
intros.
rewrite <- Zplus_0_r with 0%Z.
apply Zplus_le_compat; assumption.
Qed.
Lemma Zlt_pos_opp : forall x : Z, (0 < x)%Z -> (- x < 0)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zlt_neg_opp : forall x : Z, (x < 0)%Z -> (0 < - x)%Z.
Proof.
intros.
apply Zplus_lt_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_neg_opp : forall x : Z, (x <= 0)%Z -> (0 <= - x)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zle_pos_opp : forall x : Z, (0 <= x)%Z -> (- x <= 0)%Z.
Proof.
intros.
apply Zplus_le_reg_l with x.
rewrite Zplus_opp_r.
rewrite Zplus_0_r.
assumption.
Qed.
Lemma Zge_opp : forall x y : Z, (x <= y)%Z -> (- x >= - y)%Z.
Proof.
intros.
apply Zle_ge.
apply Zplus_le_reg_l with (p := (x + y)%Z).
ring_simplify (x + y + - y)%Z (x + y + - x)%Z.
assumption.
Qed.
(* Omega can't solve this *)
Lemma Zmult_pos_pos : forall x y : Z, (0 < x)%Z -> (0 < y)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_neg : forall x y : Z, (x < 0)%Z -> (y < 0)%Z -> (0 < x * y)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_neg_pos : forall x y : Z, (x < 0)%Z -> (0 < y)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Lemma Zmult_pos_neg : forall x y : Z, (0 < x)%Z -> (y < 0)%Z -> (x * y < 0)%Z.
Proof.
intros [| px| px] [| py| py] Hx Hy; trivial || constructor.
Qed.
Hint Resolve Zmult_pos_pos Zmult_neg_neg Zmult_neg_pos Zmult_pos_neg: zarith.
Lemma Zle_reg_mult_l :
forall x y a : Z, (0 < a)%Z -> (x <= y)%Z -> (a * x <= a * y)%Z.
Proof.
intros.
apply Zplus_le_reg_l with (p := (- a * x)%Z).
ring_simplify (- a * x + a * x)%Z.
replace (- a * x + a * y)%Z with ((y - x) * a)%Z.
apply Zmult_gt_0_le_0_compat.
apply Zlt_gt.
assumption.
unfold Zminus in |- *.
apply Zle_left.
assumption.
ring.
Qed.
Lemma Zsimpl_plus_l_dep :
forall x y m n : Z, (x + m)%Z = (y + n)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zsimpl_plus_r_dep :
forall x y m n : Z, (m + x)%Z = (n + y)%Z -> x = y -> m = n.
Proof.
intros.
apply Zplus_reg_l with x.
rewrite Zplus_comm.
rewrite Zplus_comm with x n.
rewrite <- H0 in H.
assumption.
Qed.
Lemma Zmult_simpl :
forall n m p q : Z, n = m -> p = q -> (n * p)%Z = (m * q)%Z.
Proof.
intros.
rewrite H.
rewrite H0.
reflexivity.
Qed.
Lemma Zsimpl_mult_l :
forall n m p : Z, n <> 0%Z -> (n * m)%Z = (n * p)%Z -> m = p.
Proof.
intros.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + p)%Z with 0%Z.
apply Zmult_integral_l with (n := n).
assumption.
replace ((- p + m) * n)%Z with (n * m + - (n * p))%Z.
apply Zegal_left.
assumption.
ring.
ring.
Qed.
Lemma Zlt_reg_mult_l :
forall x y z : Z, (x > 0)%Z -> (y < z)%Z -> (x * y < x * z)%Z. (*QA*)
Proof.
intros.
case (Zcompare_Gt_spec x 0).
unfold Zgt in H.
assumption.
intros.
cut (x = Zpos x0).
intro.
rewrite H2.
unfold Zlt in H0.
unfold Zlt in |- *.
cut ((Zpos x0 * y ?= Zpos x0 * z)%Z = (y ?= z)%Z).
intro.
exact (trans_eq H3 H0).
apply Zcompare_mult_compat.
cut (x = (x + - (0))%Z).
intro.
exact (trans_eq H2 H1).
simpl in |- *.
apply (sym_eq (A:=Z)).
exact (Zplus_0_r x).
Qed.
Lemma Zlt_opp : forall x y : Z, (x < y)%Z -> (- x > - y)%Z. (*QA*)
Proof.
intros.
red in |- *.
apply sym_eq.
cut (Datatypes.Gt = (y ?= x)%Z).
intro.
cut ((y ?= x)%Z = (- x ?= - y)%Z).
intro.
exact (trans_eq H0 H1).
exact (Zcompare_opp y x).
apply sym_eq.
exact (Zlt_gt x y H).
Qed.
Lemma Zlt_conv_mult_l :
forall x y z : Z, (x < 0)%Z -> (y < z)%Z -> (x * y > x * z)%Z. (*QA*)
Proof.
intros.
cut (- x > 0)%Z.
intro.
cut (- x * y < - x * z)%Z.
intro.
cut (- (- x * y) > - (- x * z))%Z.
intro.
cut (- - (x * y) > - - (x * z))%Z.
intro.
cut ((- - (x * y))%Z = (x * y)%Z).
intro.
rewrite H5 in H4.
cut ((- - (x * z))%Z = (x * z)%Z).
intro.
rewrite H6 in H4.
assumption.
exact (Zopp_involutive (x * z)).
exact (Zopp_involutive (x * y)).
cut ((- (- x * y))%Z = (- - (x * y))%Z).
intro.
rewrite H4 in H3.
cut ((- (- x * z))%Z = (- - (x * z))%Z).
intro.
rewrite H5 in H3.
assumption.
cut ((- x * z)%Z = (- (x * z))%Z).
intro.
exact (f_equal Zopp H5).
exact (Zopp_mult_distr_l_reverse x z).
cut ((- x * y)%Z = (- (x * y))%Z).
intro.
exact (f_equal Zopp H4).
exact (Zopp_mult_distr_l_reverse x y).
exact (Zlt_opp (- x * y) (- x * z) H2).
exact (Zlt_reg_mult_l (- x) y z H1 H0).
exact (Zlt_opp x 0 H).
Qed.
Lemma Zgt_not_eq : forall x y : Z, (x > y)%Z -> x <> y. (*QA*)
Proof.
intros.
cut (y < x)%Z.
intro.
cut (y <> x).
intro.
red in |- *.
intros.
cut (y = x).
intros.
apply H1.
assumption.
exact (sym_eq H2).
exact (Zorder.Zlt_not_eq y x H0).
exact (Zgt_lt x y H).
Qed.
Lemma Zmult_resp_nonzero :
forall x y : Z, x <> 0%Z -> y <> 0%Z -> (x * y)%Z <> 0%Z.
Proof.
intros x y Hx Hy Hxy.
apply Hx.
apply Zmult_integral_l with y; assumption.
Qed.
Lemma Zopp_app : forall y : Z, y <> 0%Z -> (- y)%Z <> 0%Z.
Proof.
intros.
intro.
apply H.
apply Zplus_reg_l with (- y)%Z.
rewrite Zplus_opp_l.
rewrite H0.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_neq_Zlt : forall a b : Z, (a <= b)%Z -> b <> a -> (a < b)%Z.
Proof.
intros a b H H0.
case (Z_le_lt_eq_dec _ _ H); trivial.
intro; apply False_ind; apply H0; symmetry in |- *; assumption.
Qed.
Lemma not_Zle_lt : forall x y : Z, ~ (y <= x)%Z -> (x < y)%Z.
Proof.
intros; apply Zgt_lt; apply Znot_le_gt; assumption.
Qed.
Lemma not_Zlt : forall x y : Z, ~ (y < x)%Z -> (x <= y)%Z.
Proof.
intros x y H1 H2; apply H1; apply Zgt_lt; assumption.
Qed.
Lemma Zmult_absorb :
forall x y z : Z, x <> 0%Z -> (x * y)%Z = (x * z)%Z -> y = z. (*QA*)
Proof.
intros.
case (dec_eq y z).
intro.
assumption.
intro.
case (not_Zeq y z).
assumption.
intro.
case (not_Zeq x 0).
assumption.
intro.
apply False_ind.
cut (x * y > x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zgt_not_eq (x * y) (x * z) H4).
exact (Zlt_conv_mult_l x y z H3 H2).
intro.
apply False_ind.
cut (x * y < x * z)%Z.
intro.
cut ((x * y)%Z <> (x * z)%Z).
intro.
apply H5.
assumption.
exact (Zorder.Zlt_not_eq (x * y) (x * z) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x y z H4 H2).
exact (Zlt_gt 0 x H3).
intro.
apply False_ind.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H4.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H3).
apply False_ind.
case (not_Zeq x 0).
assumption.
intro.
cut (x * z > x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zgt_not_eq (x * z) (x * y) H4).
exact (Zlt_conv_mult_l x z y H3 H2).
intro.
cut (x * z < x * y)%Z.
intro.
cut ((x * z)%Z <> (x * y)%Z).
intro.
apply H5.
apply (sym_eq (A:=Z)).
assumption.
exact (Zorder.Zlt_not_eq (x * z) (x * y) H4).
cut (x > 0)%Z.
intro.
exact (Zlt_reg_mult_l x z y H4 H2).
exact (Zlt_gt 0 x H3).
Qed.
Lemma Zlt_mult_mult :
forall a b c d : Z,
(0 < a)%Z -> (0 < d)%Z -> (a < b)%Z -> (c < d)%Z -> (a * c < b * d)%Z.
Proof.
intros.
apply Zlt_trans with (a * d)%Z.
apply Zlt_reg_mult_l.
Flip.
assumption.
rewrite Zmult_comm.
rewrite Zmult_comm with b d.
apply Zlt_reg_mult_l.
Flip.
assumption.
Qed.
Lemma Zgt_mult_conv_absorb_l :
forall a x y : Z, (a < 0)%Z -> (a * x > a * y)%Z -> (x < y)%Z. (*QC*)
Proof.
intros.
case (dec_eq x y).
intro.
apply False_ind.
rewrite H1 in H0.
cut ((a * y)%Z = (a * y)%Z).
change ((a * y)%Z <> (a * y)%Z) in |- *.
apply Zgt_not_eq.
assumption.
trivial.
intro.
case (not_Zeq x y H1).
trivial.
intro.
apply False_ind.
cut (a * y > a * x)%Z.
apply Zgt_asym with (m := (a * y)%Z) (n := (a * x)%Z).
assumption.
apply Zlt_conv_mult_l.
assumption.
assumption.
Qed.
Lemma Zgt_mult_reg_absorb_l :
forall a x y : Z, (a > 0)%Z -> (a * x > a * y)%Z -> (x > y)%Z. (*QC*)
Proof.
intros.
cut (- - a > - - (0))%Z.
intro.
cut (- a < - (0))%Z.
simpl in |- *.
intro.
replace x with (- - x)%Z.
replace y with (- - y)%Z.
apply Zlt_opp.
apply Zgt_mult_conv_absorb_l with (a := (- a)%Z) (x := (- x)%Z).
assumption.
rewrite Zmult_opp_opp.
rewrite Zmult_opp_opp.
assumption.
apply Zopp_involutive.
apply Zopp_involutive.
apply Zgt_lt.
apply Zlt_opp.
apply Zgt_lt.
assumption.
simpl in |- *.
rewrite Zopp_involutive.
assumption.
Qed.
Lemma Zopp_Zlt : forall x y : Z, (y < x)%Z -> (- x < - y)%Z.
Proof.
intros x y Hyx.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
Flip.
ring.
ring.
Qed.
Lemma Zmin_cancel_Zlt : forall x y : Z, (- x < - y)%Z -> (y < x)%Z.
Proof.
intros.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
apply Zlt_gt.
assumption.
ring.
ring.
Qed.
Lemma Zmult_cancel_Zle :
forall a x y : Z, (a < 0)%Z -> (a * x <= a * y)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * x)).
apply Zle_lt_trans with (m := (a * y)%Z).
assumption.
apply Zgt_lt.
apply Zlt_conv_mult_l.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zlt_mult_cancel_l :
forall x y z : Z, (0 < x)%Z -> (x * y < x * z)%Z -> (y < z)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with x.
apply Zlt_gt.
assumption.
apply Zlt_gt.
assumption.
Qed.
Lemma Zmin_cancel_Zle : forall x y : Z, (- x <= - y)%Z -> (y <= x)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * y)%Z with (- y)%Z.
replace (-1 * x)%Z with (- x)%Z.
assumption.
ring.
ring.
Qed.
Lemma Zmult_resp_Zle :
forall a x y : Z, (0 < a)%Z -> (a * y <= a * x)%Z -> (y <= x)%Z.
Proof.
intros.
case (Z_le_gt_dec y x).
trivial.
intro.
apply False_ind.
apply (Zlt_irrefl (a * y)).
apply Zle_lt_trans with (m := (a * x)%Z).
assumption.
apply Zlt_reg_mult_l.
apply Zlt_gt.
assumption.
apply Zgt_lt.
assumption.
Qed.
Lemma Zopp_Zle : forall x y : Z, (y <= x)%Z -> (- x <= - y)%Z.
Proof.
intros.
apply Zmult_cancel_Zle with (a := (-1)%Z).
constructor.
replace (-1 * - y)%Z with y.
replace (-1 * - x)%Z with x.
assumption.
clear y H; ring.
clear x H; ring.
Qed.
Lemma Zle_lt_eq_S : forall x y : Z, (x <= y)%Z -> (y < x + 1)%Z -> y = x.
Proof.
intros.
case (Z_le_lt_eq_dec x y H).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H1).
intro.
apply (Zlt_not_le y (x + 1) H0).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
intro H1.
symmetry in |- *.
assumption.
Qed.
Lemma Zlt_le_eq_S :
forall x y : Z, (x < y)%Z -> (y <= x + 1)%Z -> y = (x + 1)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec y (x + 1) H0).
intro H1.
apply False_ind.
generalize (Zlt_le_succ x y H).
intro.
apply (Zlt_not_le y (x + 1) H1).
replace (x + 1)%Z with (Zsucc x).
assumption.
reflexivity.
trivial.
Qed.
Lemma double_not_equal_zero :
forall c d : Z, ~ (c = 0%Z /\ d = 0%Z) -> c <> d \/ c <> 0%Z.
Proof.
intros.
case (Z_zerop c).
intro.
rewrite e.
left.
apply sym_not_eq.
intro.
apply H; repeat split; assumption.
intro; right; assumption.
Qed.
Lemma triple_not_equal_zero :
forall a b c : Z,
~ (a = 0%Z /\ b = 0%Z /\ c = 0%Z) -> a <> 0%Z \/ b <> 0%Z \/ c <> 0%Z.
Proof.
intros a b c H; case (Z_zerop a); intro Ha;
[ case (Z_zerop b); intro Hb;
[ case (Z_zerop c); intro Hc;
[ apply False_ind; apply H; repeat split | right; right ]
| right; left ]
| left ]; assumption.
Qed.
Lemma mediant_1 :
forall m n m' n' : Z, (m' * n < m * n')%Z -> ((m + m') * n < m * (n + n'))%Z.
Proof.
intros.
rewrite Zmult_plus_distr_r.
rewrite Zmult_plus_distr_l.
apply Zplus_lt_compat_l.
assumption.
Qed.
Lemma mediant_2 :
forall m n m' n' : Z,
(m' * n < m * n')%Z -> (m' * (n + n') < (m + m') * n')%Z.
Proof.
intros.
rewrite Zmult_plus_distr_l.
rewrite Zmult_plus_distr_r.
apply Zplus_lt_compat_r.
assumption.
Qed.
Lemma mediant_3 :
forall a b m n m' n' : Z,
(0 <= a * m + b * n)%Z ->
(0 <= a * m' + b * n')%Z -> (0 <= a * (m + m') + b * (n + n'))%Z.
Proof.
intros.
replace (a * (m + m') + b * (n + n'))%Z with
(a * m + b * n + (a * m' + b * n'))%Z.
apply Zplus_le_0_compat.
assumption.
assumption.
ring.
Qed.
Lemma fraction_lt_trans :
forall a b c d e f : Z,
(0 < b)%Z ->
(0 < d)%Z ->
(0 < f)%Z -> (a * d < c * b)%Z -> (c * f < e * d)%Z -> (a * f < e * b)%Z.
Proof.
intros.
apply Zgt_lt.
apply Zgt_mult_reg_absorb_l with d.
Flip.
apply Zgt_trans with (c * b * f)%Z.
replace (d * (e * b))%Z with (b * (e * d))%Z.
replace (c * b * f)%Z with (b * (c * f))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
replace (c * b * f)%Z with (f * (c * b))%Z.
replace (d * (a * f))%Z with (f * (a * d))%Z.
apply Zlt_gt.
apply Zlt_reg_mult_l.
Flip.
assumption.
ring.
ring.
Qed.
Lemma square_pos : forall a : Z, a <> 0%Z -> (0 < a * a)%Z.
Proof.
intros [| p| p]; intros; [ Falsum | constructor | constructor ].
Qed.
Hint Resolve square_pos: zarith.
(*###########################################################################*)
(** Properties of positive numbers, mapping between Z and nat *)
(*###########################################################################*)
Definition Z2positive (z : Z) :=
match z with
| Zpos p => p
| Zneg p => p
| Z0 => 1%positive
end.
Lemma ZL9 : forall p : positive, Z_of_nat (nat_of_P p) = Zpos p. (*QF*)
Proof.
intro.
cut (exists h : nat, nat_of_P p = S h).
intro.
case H.
intros.
unfold Z_of_nat in |- *.
rewrite H0.
apply f_equal with (A := positive) (B := Z) (f := Zpos).
cut (P_of_succ_nat (nat_of_P p) = P_of_succ_nat (S x)).
intro.
rewrite P_of_succ_nat_o_nat_of_P_eq_succ in H1.
cut (Ppred (Psucc p) = Ppred (P_of_succ_nat (S x))).
intro.
rewrite Ppred_succ in H2.
simpl in H2.
rewrite Ppred_succ in H2.
apply sym_eq.
assumption.
apply f_equal with (A := positive) (B := positive) (f := Ppred).
assumption.
apply f_equal with (f := P_of_succ_nat).
assumption.
apply ZL4.
Qed.
Coercion Z_of_nat : nat >-> Z.
Lemma ZERO_lt_POS : forall p : positive, (0 < Zpos p)%Z.
Proof.
intros.
constructor.
Qed.
Lemma POS_neq_ZERO : forall p : positive, Zpos p <> 0%Z.
Proof.
intros.
apply sym_not_eq.
apply Zorder.Zlt_not_eq.
apply ZERO_lt_POS.
Qed.
Lemma NEG_neq_ZERO : forall p : positive, Zneg p <> 0%Z.
Proof.
intros.
apply Zorder.Zlt_not_eq.
unfold Zlt in |- *.
constructor.
Qed.
Lemma POS_resp_eq : forall p0 p1 : positive, Zpos p0 = Zpos p1 -> p0 = p1.
Proof.
intros.
injection H.
trivial.
Qed.
Lemma nat_nat_pos : forall m n : nat, ((m + 1) * (n + 1) > 0)%Z. (*QF*)
Proof.
intros.
apply Zlt_gt.
cut (Z_of_nat m + 1 > 0)%Z.
intro.
cut (0 < Z_of_nat n + 1)%Z.
intro.
cut ((Z_of_nat m + 1) * 0 < (Z_of_nat m + 1) * (Z_of_nat n + 1))%Z.
rewrite Zmult_0_r.
intro.
assumption.
apply Zlt_reg_mult_l.
assumption.
assumption.
change (0 < Zsucc (Z_of_nat n))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat n)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
apply Zlt_gt.
change (0 < Zsucc (Z_of_nat m))%Z in |- *.
apply Zle_lt_succ.
change (Z_of_nat 0 <= Z_of_nat m)%Z in |- *.
apply Znat.inj_le.
apply le_O_n.
Qed.
Theorem S_predn : forall m : nat, m <> 0 -> S (pred m) = m. (*QF*)
Proof.
intros.
case (O_or_S m).
intro.
case s.
intros.
rewrite <- e.
rewrite <- pred_Sn with (n := x).
trivial.
intro.
apply False_ind.
apply H.
apply sym_eq.
assumption.
Qed.
Lemma absolu_1 : forall x : Z, Zabs_nat x = 0 -> x = 0%Z. (*QF*)
Proof.
intros.
case (dec_eq x 0).
intro.
assumption.
intro.
apply False_ind.
cut ((x < 0)%Z \/ (x > 0)%Z).
intro.
ElimCompare x 0%Z.
intro.
cut (x = 0%Z).
assumption.
cut ((x ?= 0)%Z = Datatypes.Eq -> x = 0%Z).
intro.
apply H3.
assumption.
apply proj1 with (B := x = 0%Z -> (x ?= 0)%Z = Datatypes.Eq).
change ((x ?= 0)%Z = Datatypes.Eq <-> x = 0%Z) in |- *.
apply Zcompare_Eq_iff_eq.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
change (x < 0)%Z in H2.
cut (0 > x)%Z.
intro.
cut (exists p : positive, (0 + - x)%Z = Zpos p).
simpl in |- *.
intro.
case H4.
intros.
cut (exists q : positive, x = Zneg q).
intro.
case H6.
intros.
rewrite H7.
unfold Zabs_nat in |- *.
generalize x1.
exact ZL4.
cut (x = (- Zpos x0)%Z).
simpl in |- *.
intro.
exists x0.
assumption.
cut ((- - x)%Z = x).
intro.
rewrite <- H6.
exact (f_equal Zopp H5).
apply Zopp_involutive.
apply Zcompare_Gt_spec.
assumption.
apply Zlt_gt.
assumption.
(***)
intro.
cut (exists h : nat, Zabs_nat x = S h).
intro.
case H3.
rewrite H.
exact O_S.
cut (exists p : positive, (x + - (0))%Z = Zpos p).
simpl in |- *.
rewrite Zplus_0_r.
intro.
case H3.
intros.
rewrite H4.
unfold Zabs_nat in |- *.
generalize x0.
exact ZL4.
apply Zcompare_Gt_spec.
assumption.
(***)
cut ((x < 0)%Z \/ (0 < x)%Z).
intro.
apply
or_ind with (A := (x < 0)%Z) (B := (0 < x)%Z) (P := (x < 0)%Z \/ (x > 0)%Z).
intro.
left.
assumption.
intro.
right.
apply Zlt_gt.
assumption.
assumption.
apply not_Zeq.
assumption.
Qed.
Lemma absolu_2 : forall x : Z, x <> 0%Z -> Zabs_nat x <> 0. (*QF*)
Proof.
intros.
intro.
apply H.
apply absolu_1.
assumption.
Qed.
Lemma absolu_inject_nat : forall n : nat, Zabs_nat (Z_of_nat n) = n.
Proof.
simple induction n; simpl in |- *.
reflexivity.
intros.
apply nat_of_P_o_P_of_succ_nat_eq_succ.
Qed.
Lemma eq_inj : forall m n : nat, m = n :>Z -> m = n.
Proof.
intros.
generalize (f_equal Zabs_nat H).
intro.
rewrite (absolu_inject_nat m) in H0.
rewrite (absolu_inject_nat n) in H0.
assumption.
Qed.
Lemma lt_inj : forall m n : nat, (m < n)%Z -> m < n.
Proof.
intros.
omega.
Qed.
Lemma le_inj : forall m n : nat, (m <= n)%Z -> m <= n.
Proof.
intros.
omega.
Qed.
Lemma inject_nat_S_inf : forall x : Z, (0 < x)%Z -> {n : nat | x = S n}.
Proof.
intros [| p| p] Hp; try discriminate Hp.
exists (pred (nat_of_P p)).
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hp;
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma le_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x <= y)%Z -> Zabs_nat x <= Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy;
apply le_O_n ||
(try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end).
simpl in |- *.
apply le_inj.
do 2 rewrite ZL9.
assumption.
Qed.
Lemma lt_absolu :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> (x < y)%Z -> Zabs_nat x < Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy Hxy; inversion Hxy;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end; simpl in |- *; apply lt_inj; repeat rewrite ZL9;
assumption.
Qed.
Lemma absolu_plus :
forall x y : Z,
(0 <= x)%Z -> (0 <= y)%Z -> Zabs_nat (x + y) = Zabs_nat x + Zabs_nat y.
Proof.
intros [| x| x] [| y| y] Hx Hy; trivial;
try
match goal with
| id1:(0 <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= 0)%Z |- _ =>
apply False_ind; apply id1; constructor
| id1:(Zpos _ <= Zneg _)%Z |- _ =>
apply False_ind; apply id1; constructor
end.
rewrite <- BinInt.Zpos_plus_distr.
unfold Zabs_nat in |- *.
apply nat_of_P_plus_morphism.
Qed.
Lemma pred_absolu :
forall x : Z, (0 < x)%Z -> pred (Zabs_nat x) = Zabs_nat (x - 1).
Proof.
intros x Hx.
generalize (Z_lt_lt_S_eq_dec 0 x Hx); simpl in |- *; intros [H1| H1];
[ replace (Zabs_nat x) with (Zabs_nat (x - 1 + 1));
[ idtac | apply f_equal with Z; auto with zarith ];
rewrite absolu_plus;
[ unfold Zabs_nat at 2, nat_of_P, Piter_op in |- *; omega
| auto with zarith
| intro; discriminate ]
| rewrite <- H1; reflexivity ].
Qed.
Definition pred_nat : forall (x : Z) (Hx : (0 < x)%Z), nat.
intros [| px| px] Hx; try abstract (discriminate Hx).
exact (pred (nat_of_P px)).
Defined.
Lemma pred_nat_equal :
forall (x : Z) (Hx1 Hx2 : (0 < x)%Z), pred_nat x Hx1 = pred_nat x Hx2.
Proof.
intros [| px| px] Hx1 Hx2; try (discriminate Hx1); trivial.
Qed.
Let pred_nat_unfolded_subproof px :
Pos.to_nat px <> 0.
Proof.
apply sym_not_equal; apply lt_O_neq; apply lt_O_nat_of_P.
Qed.
Lemma pred_nat_unfolded :
forall (x : Z) (Hx : (0 < x)%Z), x = S (pred_nat x Hx).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
symmetry in |- *; apply ZL9.
clear Hx; apply pred_nat_unfolded_subproof.
Qed.
Lemma absolu_pred_nat :
forall (m : Z) (Hm : (0 < m)%Z), S (pred_nat m Hm) = Zabs_nat m.
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite S_predn.
reflexivity.
apply pred_nat_unfolded_subproof.
Qed.
Lemma pred_nat_absolu :
forall (m : Z) (Hm : (0 < m)%Z), pred_nat m Hm = Zabs_nat (m - 1).
Proof.
intros [| px| px] Hx; try discriminate Hx.
unfold pred_nat in |- *.
rewrite <- pred_absolu; reflexivity || assumption.
Qed.
Lemma minus_pred_nat :
forall (n m : Z) (Hn : (0 < n)%Z) (Hm : (0 < m)%Z) (Hnm : (0 < n - m)%Z),
S (pred_nat n Hn) - S (pred_nat m Hm) = S (pred_nat (n - m) Hnm).
Proof.
intros.
simpl in |- *.
destruct n; try discriminate Hn.
destruct m; try discriminate Hm.
unfold pred_nat at 1 2 in |- *.
rewrite minus_pred; try apply lt_O_nat_of_P.
apply eq_inj.
rewrite <- pred_nat_unfolded.
rewrite Znat.inj_minus1.
repeat rewrite ZL9.
reflexivity.
apply le_inj.
apply Zlt_le_weak.
repeat rewrite ZL9.
apply Zlt_O_minus_lt.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zsgn *)
(*###########################################################################*)
Lemma Zsgn_1 :
forall x : Z, {Zsgn x = 0%Z} + {Zsgn x = 1%Z} + {Zsgn x = (-1)%Z}. (*QF*)
Proof.
intros.
case x.
left.
left.
unfold Zsgn in |- *.
reflexivity.
intro.
simpl in |- *.
left.
right.
reflexivity.
intro.
right.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_2 : forall x : Z, Zsgn x = 0%Z -> x = 0%Z. (*QF*)
Proof.
intros [| p1| p1]; simpl in |- *; intro H; constructor || discriminate H.
Qed.
Lemma Zsgn_3 : forall x : Z, x <> 0%Z -> Zsgn x <> 0%Z. (*QF*)
Proof.
intro.
case x.
intros.
apply False_ind.
apply H.
reflexivity.
intros.
simpl in |- *.
discriminate.
intros.
simpl in |- *.
discriminate.
Qed.
Theorem Zsgn_4 : forall a : Z, a = (Zsgn a * Zabs_nat a)%Z. (*QF*)
Proof.
intro.
case a.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite Zmult_1_l.
symmetry in |- *.
apply ZL9.
intros.
unfold Zsgn in |- *.
unfold Zabs_nat in |- *.
rewrite ZL9.
constructor.
Qed.
Theorem Zsgn_5 :
forall a b x y : Z,
x <> 0%Z ->
y <> 0%Z ->
(Zsgn a * x)%Z = (Zsgn b * y)%Z -> (Zsgn a * y)%Z = (Zsgn b * x)%Z. (*QF*)
Proof.
intros a b x y H H0.
case a.
case b.
simpl in |- *.
trivial.
intro.
unfold Zsgn in |- *.
intro.
rewrite Zmult_1_l in H1.
simpl in H1.
apply False_ind.
apply H0.
symmetry in |- *.
assumption.
intro.
unfold Zsgn in |- *.
intro.
apply False_ind.
apply H0.
apply Zopp_inj.
simpl in |- *.
transitivity (-1 * y)%Z.
constructor.
transitivity (0 * x)%Z.
symmetry in |- *.
assumption.
simpl in |- *.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity y.
rewrite Zmult_1_l.
reflexivity.
transitivity (Zsgn b * (Zsgn b * y))%Z.
case (Zsgn_1 b).
intro.
case s.
intro.
apply False_ind.
apply H.
rewrite e in H1.
change ((1 * x)%Z = 0%Z) in H1.
rewrite Zmult_1_l in H1.
assumption.
intro.
rewrite e.
rewrite Zmult_1_l.
rewrite Zmult_1_l.
reflexivity.
intro.
rewrite e.
ring.
rewrite Zmult_1_l in H1.
rewrite H1.
reflexivity.
intro.
unfold Zsgn at 1 in |- *.
unfold Zsgn at 2 in |- *.
intro.
transitivity (Zsgn b * (-1 * (Zsgn b * y)))%Z.
case (Zsgn_1 b).
intros.
case s.
intro.
apply False_ind.
apply H.
apply Zopp_inj.
transitivity (-1 * x)%Z.
ring.
unfold Zopp in |- *.
rewrite e in H1.
transitivity (0 * y)%Z.
assumption.
simpl in |- *.
reflexivity.
intro.
rewrite e.
ring.
intro.
rewrite e.
ring.
rewrite <- H1.
ring.
Qed.
Lemma Zsgn_6 : forall x : Z, x = 0%Z -> Zsgn x = 0%Z.
Proof.
intros.
rewrite H.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_7 : forall x : Z, (x > 0)%Z -> Zsgn x = 1%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
Flip.
intros.
simpl in |- *.
reflexivity.
intros.
apply False_ind.
apply (Zlt_irrefl (Zneg p)).
apply Zlt_trans with 0%Z.
constructor.
Flip.
Qed.
Lemma Zsgn_7' : forall x : Z, (0 < x)%Z -> Zsgn x = 1%Z.
Proof.
intros; apply Zsgn_7; Flip.
Qed.
Lemma Zsgn_8 : forall x : Z, (x < 0)%Z -> Zsgn x = (-1)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
apply (Zlt_irrefl 0).
assumption.
intros.
apply False_ind.
apply (Zlt_irrefl 0).
apply Zlt_trans with (Zpos p).
constructor.
assumption.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zsgn_9 : forall x : Z, Zsgn x = 1%Z -> (0 < x)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
simpl in H.
discriminate.
intros.
constructor.
intros.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_10 : forall x : Z, Zsgn x = (-1)%Z -> (x < 0)%Z.
Proof.
intro.
case x.
intro.
apply False_ind.
discriminate.
intros.
apply False_ind.
discriminate.
intros.
constructor.
Qed.
Lemma Zsgn_11 : forall x : Z, (Zsgn x < 0)%Z -> (x < 0)%Z.
Proof.
intros.
apply Zsgn_10.
case (Zsgn_1 x).
intro.
apply False_ind.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply (H0 e).
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
discriminate.
trivial.
Qed.
Lemma Zsgn_12 : forall x : Z, (0 < Zsgn x)%Z -> (0 < x)%Z.
Proof.
intros.
apply Zsgn_9.
case (Zsgn_1 x).
intro.
case s.
intro.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
generalize (sym_eq e).
intro.
apply False_ind.
apply (H0 H1).
trivial.
intro.
rewrite e in H.
generalize (Zorder.Zlt_not_eq _ _ H).
intro.
apply False_ind.
discriminate.
Qed.
Lemma Zsgn_13 : forall x : Z, (0 <= Zsgn x)%Z -> (0 <= x)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec 0 (Zsgn x) H).
intro.
apply Zlt_le_weak.
apply Zsgn_12.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
symmetry in |- *.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_14 : forall x : Z, (Zsgn x <= 0)%Z -> (x <= 0)%Z.
Proof.
intros.
case (Z_le_lt_eq_dec (Zsgn x) 0 H).
intro.
apply Zlt_le_weak.
apply Zsgn_11.
assumption.
intro.
assert (x = 0%Z).
apply Zsgn_2.
assumption.
rewrite H0.
apply Zle_refl.
Qed.
Lemma Zsgn_15 : forall x y : Z, Zsgn (x * y) = (Zsgn x * Zsgn y)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; constructor.
Qed.
Lemma Zsgn_16 :
forall x y : Z,
Zsgn (x * y) = 1%Z -> {(0 < x)%Z /\ (0 < y)%Z} + {(x < 0)%Z /\ (y < 0)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_17 :
forall x y : Z,
Zsgn (x * y) = (-1)%Z -> {(0 < x)%Z /\ (y < 0)%Z} + {(x < 0)%Z /\ (0 < y)%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right ]; repeat split.
Qed.
Lemma Zsgn_18 : forall x y : Z, Zsgn (x * y) = 0%Z -> {x = 0%Z} + {y = 0%Z}.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
try discriminate H; [ left | right | right ]; constructor.
Qed.
Lemma Zsgn_19 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 < x + y)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_12; assumption).
Qed.
Lemma Zsgn_20 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x + y < 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intro H;
discriminate H || (constructor || apply Zsgn_11; assumption).
Qed.
Lemma Zsgn_21 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= x)%Z.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_22 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (x <= 0)%Z.
Proof.
Proof.
intros [y| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *; intros H H0;
discriminate H || discriminate H0.
Qed.
Lemma Zsgn_23 : forall x y : Z, (0 < Zsgn x + Zsgn y)%Z -> (0 <= y)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_24 : forall x y : Z, (Zsgn x + Zsgn y < 0)%Z -> (y <= 0)%Z.
Proof.
intros [[| p2| p2]| p1 [| p2| p2]| p1 [| p2| p2]]; simpl in |- *;
intros H H0; discriminate H || discriminate H0.
Qed.
Lemma Zsgn_25 : forall x : Z, Zsgn (- x) = (- Zsgn x)%Z.
Proof.
intros [| p1| p1]; simpl in |- *; reflexivity.
Qed.
Lemma Zsgn_26 : forall x : Z, (0 < x)%Z -> (0 < Zsgn x)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Lemma Zsgn_27 : forall x : Z, (x < 0)%Z -> (Zsgn x < 0)%Z.
Proof.
intros [| p| p] Hp; trivial.
Qed.
Hint Resolve Zsgn_1 Zsgn_2 Zsgn_3 Zsgn_4 Zsgn_5 Zsgn_6 Zsgn_7 Zsgn_7' Zsgn_8
Zsgn_9 Zsgn_10 Zsgn_11 Zsgn_12 Zsgn_13 Zsgn_14 Zsgn_15 Zsgn_16 Zsgn_17
Zsgn_18 Zsgn_19 Zsgn_20 Zsgn_21 Zsgn_22 Zsgn_23 Zsgn_24 Zsgn_25 Zsgn_26
Zsgn_27: zarith.
(*###########################################################################*)
(** Properties of Zabs *)
(*###########################################################################*)
Lemma Zabs_1 : forall z p : Z, (Zabs z < p)%Z -> (z < p)%Z /\ (- p < z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
split.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
assumption.
intros.
simpl in H.
split.
assumption.
apply Zlt_trans with (m := 0%Z).
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl; trivial.
ring_simplify (-1 * - p)%Z (-1 * 0)%Z.
apply Zlt_gt.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
constructor.
intros.
simpl in H.
split.
apply Zlt_trans with (m := Zpos p0).
constructor.
assumption.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
replace (-1)%Z with (Zpred 0).
apply Zlt_pred.
simpl;trivial.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (- Zneg p0)%Z.
replace (- Zneg p0)%Z with (Zpos p0).
apply Zlt_gt.
assumption.
symmetry in |- *.
apply Zopp_neg.
rewrite Zopp_mult_distr_l_reverse with (n := 1%Z).
simpl in |- *.
constructor.
Qed.
Lemma Zabs_2 : forall z p : Z, (Zabs z > p)%Z -> (z > p)%Z \/ (- p > z)%Z.
Proof.
intros z p.
case z.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
left.
assumption.
intros.
simpl in H.
right.
apply Zlt_gt.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
ring_simplify (-1 * - p)%Z.
replace (-1 * Zneg p0)%Z with (Zpos p0).
assumption.
reflexivity.
Qed.
Lemma Zabs_3 : forall z p : Z, (z < p)%Z /\ (- p < z)%Z -> (Zabs z < p)%Z.
Proof.
intros z p.
case z.
intro.
simpl in |- *.
elim H.
intros.
assumption.
intros.
elim H.
intros.
simpl in |- *.
assumption.
intros.
elim H.
intros.
simpl in |- *.
apply Zgt_mult_conv_absorb_l with (a := (-1)%Z).
constructor.
replace (-1 * Zpos p0)%Z with (Zneg p0).
replace (-1 * p)%Z with (- p)%Z.
apply Zlt_gt.
assumption.
ring.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_4 : forall z p : Z, (Zabs z < p)%Z -> (- p < z < p)%Z.
Proof.
intros.
split.
apply proj2 with (A := (z < p)%Z).
apply Zabs_1.
assumption.
apply proj1 with (B := (- p < z)%Z).
apply Zabs_1.
assumption.
Qed.
Lemma Zabs_5 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z <= p)%Z.
Proof.
intros.
split.
replace (- p)%Z with (Zsucc (- Zsucc p)).
apply Zlt_le_succ.
apply proj2 with (A := (z < Zsucc p)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
unfold Zsucc in |- *.
ring.
apply Zlt_succ_le.
apply proj1 with (B := (- Zsucc p < z)%Z).
apply Zabs_1.
apply Zle_lt_succ.
assumption.
Qed.
Lemma Zabs_6 : forall z p : Z, (Zabs z <= p)%Z -> (z <= p)%Z.
Proof.
intros.
apply proj2 with (A := (- p <= z)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_7 : forall z p : Z, (Zabs z <= p)%Z -> (- p <= z)%Z.
Proof.
intros.
apply proj1 with (B := (z <= p)%Z).
apply Zabs_5.
assumption.
Qed.
Lemma Zabs_8 : forall z p : Z, (- p <= z <= p)%Z -> (Zabs z <= p)%Z.
Proof.
intros.
apply Zlt_succ_le.
apply Zabs_3.
elim H.
intros.
split.
apply Zle_lt_succ.
assumption.
apply Zlt_le_trans with (m := (- p)%Z).
apply Zgt_lt.
apply Zlt_opp.
apply Zlt_succ.
assumption.
Qed.
Lemma Zabs_min : forall z : Z, Zabs z = Zabs (- z).
Proof.
intro.
case z.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
intro.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_9 :
forall z p : Z, (0 <= p)%Z -> (p < z)%Z \/ (z < - p)%Z -> (p < Zabs z)%Z.
Proof.
intros.
case H0.
intro.
replace (Zabs z) with z.
assumption.
symmetry in |- *.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
assumption.
intro.
cut (Zabs z = (- z)%Z).
intro.
rewrite H2.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
rewrite Zabs_min.
apply Zabs_eq.
apply Zlt_le_weak.
apply Zle_lt_trans with (m := p).
assumption.
apply Zmin_cancel_Zlt.
ring_simplify (- - z)%Z.
assumption.
Qed.
Lemma Zabs_10 : forall z : Z, (0 <= Zabs z)%Z.
Proof.
intro.
case (Z_zerop z).
intro.
rewrite e.
simpl in |- *.
apply Zle_refl.
intro.
case (not_Zeq z 0 n).
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
right.
assumption.
intro.
apply Zlt_le_weak.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
left.
assumption.
Qed.
Lemma Zabs_11 : forall z : Z, z <> 0%Z -> (0 < Zabs z)%Z.
Proof.
intros.
apply Zabs_9.
apply Zle_refl.
simpl in |- *.
apply not_Zeq.
intro.
apply H.
symmetry in |- *.
assumption.
Qed.
Lemma Zabs_12 : forall z m : Z, (m < Zabs z)%Z -> {(m < z)%Z} + {(z < - m)%Z}.
Proof.
intros [| p| p] m; simpl in |- *; intros H;
[ left | left | right; apply Zmin_cancel_Zlt; rewrite Zopp_involutive ];
assumption.
Qed.
Lemma Zabs_mult : forall z p : Z, Zabs (z * p) = (Zabs z * Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
reflexivity.
case p.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
case p.
intro.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zabs_plus : forall z p : Z, (Zabs (z + p) <= Zabs z + Zabs p)%Z.
Proof.
intros.
case z.
simpl in |- *.
apply Zle_refl.
case p.
intro.
simpl in |- *.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 - Zneg p0)%Z.
replace (Zpos p1 - Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(- (Zpos p0 + Zneg p0))%Z.
replace (Zpos p1 - Zneg p0 + (Zpos p1 + Zneg p0))%Z with (2 * Zpos p1)%Z.
replace (- (Zpos p0 + Zneg p0))%Z with 0%Z.
apply Zmult_gt_0_le_0_compat.
constructor.
apply Zlt_le_weak.
constructor.
rewrite <- Zopp_neg with p0.
ring.
ring.
ring.
apply Zplus_le_compat.
apply Zle_refl.
apply Zlt_le_weak.
constructor.
case p.
simpl in |- *.
intro.
apply Zle_refl.
intros.
unfold Zabs at 2 in |- *.
unfold Zabs at 2 in |- *.
apply Zabs_8.
split.
apply Zplus_le_reg_l with (Zpos p1 + Zneg p0)%Z.
replace (Zpos p1 + Zneg p0 + - (Zpos p1 + Zpos p0))%Z with
(Zneg p0 - Zpos p0)%Z.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with 0%Z.
apply Zplus_le_reg_l with (Zpos p0).
replace (Zpos p0 + (Zneg p0 - Zpos p0))%Z with (Zneg p0).
simpl in |- *.
apply Zlt_le_weak.
constructor.
ring.
replace (Zpos p1 + Zneg p0 + (Zneg p1 + Zpos p0))%Z with
(Zpos p1 + Zneg p1 + (Zpos p0 + Zneg p0))%Z.
replace 0%Z with (0 + 0)%Z.
apply Zplus_eq_compat.
rewrite <- Zopp_neg with p1.
ring.
rewrite <- Zopp_neg with p0.
ring.
simpl in |- *.
constructor.
ring.
ring.
apply Zplus_le_compat.
apply Zlt_le_weak.
constructor.
apply Zle_refl.
intros.
simpl in |- *.
apply Zle_refl.
Qed.
Lemma Zabs_neg : forall z : Z, (z <= 0)%Z -> Zabs z = (- z)%Z.
Proof.
intro.
case z.
simpl in |- *.
intro.
reflexivity.
intros.
apply False_ind.
apply H.
simpl in |- *.
reflexivity.
intros.
simpl in |- *.
reflexivity.
Qed.
Lemma Zle_Zabs: forall z, (z <= Zabs z)%Z.
Proof.
intros [|z|z]; simpl; auto with zarith; apply Zle_neg_pos.
Qed.
Hint Resolve Zabs_1 Zabs_2 Zabs_3 Zabs_4 Zabs_5 Zabs_6 Zabs_7 Zabs_8 Zabs_9
Zabs_10 Zabs_11 Zabs_12 Zabs_min Zabs_neg Zabs_mult Zabs_plus Zle_Zabs: zarith.
(*###########################################################################*)
(** Induction on Z *)
(*###########################################################################*)
Lemma Zind :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> exists k : nat, q = (p + k)%Z).
intro.
cut (forall k : nat, P (p + k)%Z).
intro.
intros.
cut (exists k : nat, q = (p + Z_of_nat k)%Z).
intro.
case H4.
intros.
rewrite H5.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
ring_simplify (p + 0)%Z.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
ring_simplify (- p + (p + Z_of_nat k))%Z.
apply Znat.inj_le.
apply le_O_n.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (q - p)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (p <= q)%Z -> P q -> P (q + 1)%Z) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (p <= q)%Z -> {k : nat | q = (p + k)%Z}).
intro.
cut (forall k : nat, F (p + k)%Z).
intro.
intros.
cut {k : nat | q = (p + Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
rewrite Zplus_0_r.
assumption.
replace (p + Z_of_nat (S k))%Z with (p + k + 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (Z_of_nat 0).
replace (- p + (p + Z_of_nat k))%Z with (Z_of_nat k).
apply Znat.inj_le.
apply le_O_n.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
apply Zplus_assoc_reverse.
intros.
cut {k : nat | (q - p)%Z = Z_of_nat k}.
intro H2.
case H2.
intro k.
intros.
exists k.
apply Zplus_reg_l with (n := (- p)%Z).
replace (- p + q)%Z with (q - p)%Z.
rewrite e.
rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
unfold Zminus in |- *.
apply Zplus_comm.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_down :
forall (P : Z -> Set) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> {k : nat | q = (p - k)%Z}).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut {k : nat | q = (p - Z_of_nat k)%Z}.
intro.
case H4.
intros.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
unfold Zminus in |- *.
unfold Zopp in |- *.
rewrite Zplus_0_r; reflexivity.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
unfold Zminus in |- *; rewrite Zplus_assoc; rewrite Zplus_opp_l; reflexivity.
rewrite Zplus_opp_l; reflexivity.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
unfold Zminus at 1 2 in |- *.
rewrite Zplus_assoc_reverse.
rewrite <- Zopp_plus_distr.
reflexivity.
intros.
cut {k : nat | (p - q)%Z = Z_of_nat k}.
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- e.
reflexivity.
unfold Zminus in |- *.
rewrite Zopp_plus_distr.
rewrite Zplus_assoc.
rewrite Zplus_opp_r.
rewrite Zopp_involutive.
reflexivity.
apply Z_of_nat_complete_inf.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zind_down :
forall (P : Z -> Prop) (p : Z),
P p ->
(forall q : Z, (q <= p)%Z -> P q -> P (q - 1)%Z) ->
forall q : Z, (q <= p)%Z -> P q.
Proof.
intros F p.
intro.
intro.
cut (forall q : Z, (q <= p)%Z -> exists k : nat, q = (p - k)%Z).
intro.
cut (forall k : nat, F (p - k)%Z).
intro.
intros.
cut (exists k : nat, q = (p - Z_of_nat k)%Z).
intro.
case H4.
intros x e.
rewrite e.
apply H2.
apply H1.
assumption.
intro.
induction k as [| k Hreck].
simpl in |- *.
replace (p - 0)%Z with p.
assumption.
ring.
replace (p - Z_of_nat (S k))%Z with (p - k - 1)%Z.
apply H0.
apply Zplus_le_reg_l with (p := (- p)%Z).
replace (- p + p)%Z with (- Z_of_nat 0)%Z.
replace (- p + (p - Z_of_nat k))%Z with (- Z_of_nat k)%Z.
apply Zge_le.
apply Zge_opp.
apply Znat.inj_le.
apply le_O_n.
ring.
ring_simplify; auto with arith.
assumption.
rewrite (Znat.inj_S k).
unfold Zsucc in |- *.
ring.
intros.
cut (exists k : nat, (p - q)%Z = Z_of_nat k).
intro.
case H2.
intro k.
intros.
exists k.
apply Zopp_inj.
apply Zplus_reg_l with (n := p).
replace (p + - (p - Z_of_nat k))%Z with (Z_of_nat k).
rewrite <- H3.
ring.
ring.
apply Z_of_nat_complete.
unfold Zminus in |- *.
apply Zle_left.
assumption.
Qed.
Lemma Zrec_wf :
forall (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zrec with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zrec_wf2 :
forall (q : Z) (P : Z -> Set) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zrec_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zrec_wf_double :
forall (P : Z -> Z -> Set) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zrec_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zrec_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
Lemma Zind_wf :
forall (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
forall q : Z, (p <= q)%Z -> P q.
Proof.
intros P p WF_ind_step q Hq.
cut (forall x : Z, (p <= x)%Z -> forall y : Z, (p <= y < x)%Z -> P y).
intro.
apply (H (Zsucc q)).
apply Zle_le_succ.
assumption.
split; [ assumption | exact (Zlt_succ q) ].
intros x0 Hx0; generalize Hx0; pattern x0 in |- *.
apply Zind with (p := p).
intros.
absurd (p <= p)%Z.
apply Zgt_not_le.
apply Zgt_le_trans with (m := y).
apply Zlt_gt.
elim H.
intros.
assumption.
elim H.
intros.
assumption.
apply Zle_refl.
intros.
apply WF_ind_step.
intros.
apply (H0 H).
split.
elim H2.
intros.
assumption.
apply Zlt_le_trans with y.
elim H2.
intros.
assumption.
apply Zgt_succ_le.
apply Zlt_gt.
elim H1.
intros.
unfold Zsucc in |- *.
assumption.
assumption.
Qed.
Lemma Zind_wf2 :
forall (q : Z) (P : Z -> Prop) (p : Z),
(forall q : Z, (forall r : Z, (p <= r < q)%Z -> P r) -> P q) ->
(p <= q)%Z -> P q.
Proof.
intros.
apply Zind_wf with (p := p).
assumption.
assumption.
Qed.
Lemma Zind_wf_double :
forall (P : Z -> Z -> Prop) (p0 q0 : Z),
(forall n m : Z,
(forall p q : Z, (q0 <= q)%Z -> (p0 <= p < n)%Z -> P p q) ->
(forall p : Z, (q0 <= p < m)%Z -> P n p) -> P n m) ->
forall p q : Z, (q0 <= q)%Z -> (p0 <= p)%Z -> P p q.
Proof.
intros P p0 q0 Hrec p.
intros.
generalize q H.
pattern p in |- *.
apply Zind_wf with (p := p0).
intros p1 H1.
intros.
pattern q1 in |- *.
apply Zind_wf with (p := q0).
intros q2 H3.
apply Hrec.
intros.
apply H1.
assumption.
assumption.
intros.
apply H3.
assumption.
assumption.
assumption.
Qed.
(*###########################################################################*)
(** Properties of Zmax *)
(*###########################################################################*)
Definition Zmax (n m : Z) := (n + m - Zmin n m)%Z.
Lemma ZmaxSS : forall n m : Z, (Zmax n m + 1)%Z = Zmax (n + 1) (m + 1).
Proof.
intros.
unfold Zmax in |- *.
replace (Zmin (n + 1) (m + 1)) with (Zmin n m + 1)%Z.
ring.
symmetry in |- *.
change (Zmin (Zsucc n) (Zsucc m) = Zsucc (Zmin n m)) in |- *.
symmetry in |- *.
apply Zmin_SS.
Qed.
Lemma Zle_max_l : forall n m : Z, (n <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- n + Zmin n m)%Z).
ring_simplify (- n + Zmin n m + n)%Z.
ring_simplify (- n + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_r.
Qed.
Lemma Zle_max_r : forall n m : Z, (m <= Zmax n m)%Z.
Proof.
intros.
unfold Zmax in |- *.
apply Zplus_le_reg_l with (p := (- m + Zmin n m)%Z).
ring_simplify (- m + Zmin n m + m)%Z.
ring_simplify (- m + Zmin n m + (n + m - Zmin n m))%Z.
apply Zle_min_l.
Qed.
Lemma Zmin_or_informative : forall n m : Z, {Zmin n m = n} + {Zmin n m = m}.
Proof.
intros.
case (Z_lt_ge_dec n m).
unfold Zmin in |- *.
unfold Zlt in |- *.
intro z.
rewrite z.
left.
reflexivity.
intro.
cut ({(n > m)%Z} + {n = m :>Z}).
intro.
case H.
intros z0.
unfold Zmin in |- *.
unfold Zgt in z0.
rewrite z0.
right.
reflexivity.
intro.
rewrite e.
right.
apply Zmin_n_n.
cut ({(m < n)%Z} + {m = n :>Z}).
intro.
elim H.
intro.
left.
apply Zlt_gt.
assumption.
intro.
right.
symmetry in |- *.
assumption.
apply Z_le_lt_eq_dec.
apply Zge_le.
assumption.
Qed.
Lemma Zmax_case : forall (n m : Z) (P : Z -> Set), P n -> P m -> P (Zmax n m).
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
cut ((n + m - n)%Z = m).
intro.
rewrite H1.
assumption.
ring.
intro.
rewrite e.
cut ((n + m - m)%Z = n).
intro.
rewrite H1.
assumption.
ring.
Qed.
Lemma Zmax_or_informative : forall n m : Z, {Zmax n m = n} + {Zmax n m = m}.
Proof.
intros.
unfold Zmax in |- *.
case Zmin_or_informative with (n := n) (m := m).
intro.
rewrite e.
right.
ring.
intro.
rewrite e.
left.
ring.
Qed.
Lemma Zmax_n_n : forall n : Z, Zmax n n = n.
Proof.
intros.
unfold Zmax in |- *.
rewrite (Zmin_n_n n).
ring.
Qed.
Hint Resolve ZmaxSS Zle_max_r Zle_max_l Zmax_n_n: zarith.
(*###########################################################################*)
(** Properties of Arity *)
(*###########################################################################*)
Lemma Zeven_S : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x + 1).
Proof.
exact Zeven.Zeven_Sn.
Qed.
Lemma Zeven_pred : forall x : Z, Zeven.Zodd x -> Zeven.Zeven (x - 1).
Proof.
exact Zeven.Zeven_pred.
Qed.
(* This lemma used to be useful since it was mentioned with an unnecessary premise
`x>=0` as Z_modulo_2 in ZArith, but the ZArith version has been fixed. *)
Definition Z_modulo_2_always :
forall x : Z, {y : Z | x = (2 * y)%Z} + {y : Z | x = (2 * y + 1)%Z} :=
Zeven.Z_modulo_2.
(*###########################################################################*)
(** Properties of Zdiv *)
(*###########################################################################*)
Lemma Z_div_mod_eq_2 :
forall a b : Z, (0 < b)%Z -> (b * (a / b))%Z = (a - a mod b)%Z.
Proof.
intros.
apply Zplus_minus_eq.
rewrite Zplus_comm.
apply Z_div_mod_eq.
Flip.
Qed.
Lemma Z_div_le :
forall a b c : Z, (0 < c)%Z -> (b <= a)%Z -> (b / c <= a / c)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge; Flip; assumption.
Qed.
Lemma Z_div_nonneg :
forall a b : Z, (0 < b)%Z -> (0 <= a)%Z -> (0 <= a / b)%Z.
Proof.
intros.
apply Zge_le.
apply Z_div_ge0; Flip; assumption.
Qed.
Lemma Z_div_neg : forall a b : Z, (0 < b)%Z -> (a < 0)%Z -> (a / b < 0)%Z.
Proof.
intros.
rewrite (Z_div_mod_eq a b) in H0.
elim (Z_mod_lt a b).
intros H1 _.
apply Znot_ge_lt.
intro.
apply (Zlt_not_le (b * (a / b) + a mod b) 0 H0).
apply Zplus_le_0_compat.
apply Zmult_le_0_compat.
apply Zlt_le_weak; assumption.
Flip.
assumption.
Flip.
Flip.
Qed.
Hint Resolve Z_div_mod_eq_2 Z_div_le Z_div_nonneg Z_div_neg: zarith.
(*###########################################################################*)
(** Properties of Zpower *)
(*###########################################################################*)
Lemma Zpower_1 : forall a : Z, (a ^ 1)%Z = a.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
auto with zarith.
Qed.
Lemma Zpower_2 : forall a : Z, (a ^ 2)%Z = (a * a)%Z.
Proof.
intros; unfold Zpower in |- *; unfold Zpower_pos in |- *; simpl in |- *;
ring.
Qed.
Hint Resolve Zpower_1 Zpower_2: zarith.
|
module \$__XILINX_RAM16X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [15:0] INIT = 16'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [3:0] A1ADDR;
output A1DATA;
input [3:0] B1ADDR;
input B1DATA;
input B1EN;
RAM16X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA0(A1ADDR[0]),
.DPRA1(A1ADDR[1]),
.DPRA2(A1ADDR[2]),
.DPRA3(A1ADDR[3]),
.DPO(A1DATA),
.A0(B1ADDR[0]),
.A1(B1ADDR[1]),
.A2(B1ADDR[2]),
.A3(B1ADDR[3]),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM32X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [31:0] INIT = 32'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [4:0] A1ADDR;
output A1DATA;
input [4:0] B1ADDR;
input B1DATA;
input B1EN;
RAM32X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA0(A1ADDR[0]),
.DPRA1(A1ADDR[1]),
.DPRA2(A1ADDR[2]),
.DPRA3(A1ADDR[3]),
.DPRA4(A1ADDR[4]),
.DPO(A1DATA),
.A0(B1ADDR[0]),
.A1(B1ADDR[1]),
.A2(B1ADDR[2]),
.A3(B1ADDR[3]),
.A4(B1ADDR[4]),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM64X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [5:0] A1ADDR;
output A1DATA;
input [5:0] B1ADDR;
input B1DATA;
input B1EN;
RAM64X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA0(A1ADDR[0]),
.DPRA1(A1ADDR[1]),
.DPRA2(A1ADDR[2]),
.DPRA3(A1ADDR[3]),
.DPRA4(A1ADDR[4]),
.DPRA5(A1ADDR[5]),
.DPO(A1DATA),
.A0(B1ADDR[0]),
.A1(B1ADDR[1]),
.A2(B1ADDR[2]),
.A3(B1ADDR[3]),
.A4(B1ADDR[4]),
.A5(B1ADDR[5]),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM128X1D (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [127:0] INIT = 128'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [6:0] A1ADDR;
output A1DATA;
input [6:0] B1ADDR;
input B1DATA;
input B1EN;
RAM128X1D #(
.INIT(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.DPRA(A1ADDR),
.DPO(A1DATA),
.A(B1ADDR),
.D(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM32X6SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [32*6-1:0] INIT = {32*6{1'bx}};
parameter CLKPOL2 = 1;
input CLK1;
input [4:0] A1ADDR;
output [5:0] A1DATA;
input [4:0] B1ADDR;
input [5:0] B1DATA;
input B1EN;
wire [1:0] DOD_unused;
RAM32M #(
.INIT_A({INIT[187:186], INIT[181:180], INIT[175:174], INIT[169:168], INIT[163:162], INIT[157:156], INIT[151:150], INIT[145:144], INIT[139:138], INIT[133:132], INIT[127:126], INIT[121:120], INIT[115:114], INIT[109:108], INIT[103:102], INIT[ 97: 96], INIT[ 91: 90], INIT[ 85: 84], INIT[ 79: 78], INIT[ 73: 72], INIT[ 67: 66], INIT[ 61: 60], INIT[ 55: 54], INIT[ 49: 48], INIT[ 43: 42], INIT[ 37: 36], INIT[ 31: 30], INIT[ 25: 24], INIT[ 19: 18], INIT[ 13: 12], INIT[ 7: 6], INIT[ 1: 0]}),
.INIT_B({INIT[189:188], INIT[183:182], INIT[177:176], INIT[171:170], INIT[165:164], INIT[159:158], INIT[153:152], INIT[147:146], INIT[141:140], INIT[135:134], INIT[129:128], INIT[123:122], INIT[117:116], INIT[111:110], INIT[105:104], INIT[ 99: 98], INIT[ 93: 92], INIT[ 87: 86], INIT[ 81: 80], INIT[ 75: 74], INIT[ 69: 68], INIT[ 63: 62], INIT[ 57: 56], INIT[ 51: 50], INIT[ 45: 44], INIT[ 39: 38], INIT[ 33: 32], INIT[ 27: 26], INIT[ 21: 20], INIT[ 15: 14], INIT[ 9: 8], INIT[ 3: 2]}),
.INIT_C({INIT[191:190], INIT[185:184], INIT[179:178], INIT[173:172], INIT[167:166], INIT[161:160], INIT[155:154], INIT[149:148], INIT[143:142], INIT[137:136], INIT[131:130], INIT[125:124], INIT[119:118], INIT[113:112], INIT[107:106], INIT[101:100], INIT[ 95: 94], INIT[ 89: 88], INIT[ 83: 82], INIT[ 77: 76], INIT[ 71: 70], INIT[ 65: 64], INIT[ 59: 58], INIT[ 53: 52], INIT[ 47: 46], INIT[ 41: 40], INIT[ 35: 34], INIT[ 29: 28], INIT[ 23: 22], INIT[ 17: 16], INIT[ 11: 10], INIT[ 5: 4]}),
.INIT_D(64'bx),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.ADDRA(A1ADDR),
.ADDRB(A1ADDR),
.ADDRC(A1ADDR),
.DOA(A1DATA[1:0]),
.DOB(A1DATA[3:2]),
.DOC(A1DATA[5:4]),
.DOD(DOD_unused),
.ADDRD(B1ADDR),
.DIA(B1DATA[1:0]),
.DIB(B1DATA[3:2]),
.DIC(B1DATA[5:4]),
.DID(2'b00),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM64X3SDP (CLK1, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN);
parameter [64*3-1:0] INIT = {64*3{1'bx}};
parameter CLKPOL2 = 1;
input CLK1;
input [5:0] A1ADDR;
output [2:0] A1DATA;
input [5:0] B1ADDR;
input [2:0] B1DATA;
input B1EN;
wire DOD_unused;
RAM64M #(
.INIT_A({INIT[189], INIT[186], INIT[183], INIT[180], INIT[177], INIT[174], INIT[171], INIT[168], INIT[165], INIT[162], INIT[159], INIT[156], INIT[153], INIT[150], INIT[147], INIT[144], INIT[141], INIT[138], INIT[135], INIT[132], INIT[129], INIT[126], INIT[123], INIT[120], INIT[117], INIT[114], INIT[111], INIT[108], INIT[105], INIT[102], INIT[ 99], INIT[ 96], INIT[ 93], INIT[ 90], INIT[ 87], INIT[ 84], INIT[ 81], INIT[ 78], INIT[ 75], INIT[ 72], INIT[ 69], INIT[ 66], INIT[ 63], INIT[ 60], INIT[ 57], INIT[ 54], INIT[ 51], INIT[ 48], INIT[ 45], INIT[ 42], INIT[ 39], INIT[ 36], INIT[ 33], INIT[ 30], INIT[ 27], INIT[ 24], INIT[ 21], INIT[ 18], INIT[ 15], INIT[ 12], INIT[ 9], INIT[ 6], INIT[ 3], INIT[ 0]}),
.INIT_B({INIT[190], INIT[187], INIT[184], INIT[181], INIT[178], INIT[175], INIT[172], INIT[169], INIT[166], INIT[163], INIT[160], INIT[157], INIT[154], INIT[151], INIT[148], INIT[145], INIT[142], INIT[139], INIT[136], INIT[133], INIT[130], INIT[127], INIT[124], INIT[121], INIT[118], INIT[115], INIT[112], INIT[109], INIT[106], INIT[103], INIT[100], INIT[ 97], INIT[ 94], INIT[ 91], INIT[ 88], INIT[ 85], INIT[ 82], INIT[ 79], INIT[ 76], INIT[ 73], INIT[ 70], INIT[ 67], INIT[ 64], INIT[ 61], INIT[ 58], INIT[ 55], INIT[ 52], INIT[ 49], INIT[ 46], INIT[ 43], INIT[ 40], INIT[ 37], INIT[ 34], INIT[ 31], INIT[ 28], INIT[ 25], INIT[ 22], INIT[ 19], INIT[ 16], INIT[ 13], INIT[ 10], INIT[ 7], INIT[ 4], INIT[ 1]}),
.INIT_C({INIT[191], INIT[188], INIT[185], INIT[182], INIT[179], INIT[176], INIT[173], INIT[170], INIT[167], INIT[164], INIT[161], INIT[158], INIT[155], INIT[152], INIT[149], INIT[146], INIT[143], INIT[140], INIT[137], INIT[134], INIT[131], INIT[128], INIT[125], INIT[122], INIT[119], INIT[116], INIT[113], INIT[110], INIT[107], INIT[104], INIT[101], INIT[ 98], INIT[ 95], INIT[ 92], INIT[ 89], INIT[ 86], INIT[ 83], INIT[ 80], INIT[ 77], INIT[ 74], INIT[ 71], INIT[ 68], INIT[ 65], INIT[ 62], INIT[ 59], INIT[ 56], INIT[ 53], INIT[ 50], INIT[ 47], INIT[ 44], INIT[ 41], INIT[ 38], INIT[ 35], INIT[ 32], INIT[ 29], INIT[ 26], INIT[ 23], INIT[ 20], INIT[ 17], INIT[ 14], INIT[ 11], INIT[ 8], INIT[ 5], INIT[ 2]}),
.INIT_D(64'bx),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.ADDRA(A1ADDR),
.ADDRB(A1ADDR),
.ADDRC(A1ADDR),
.DOA(A1DATA[0]),
.DOB(A1DATA[1]),
.DOC(A1DATA[2]),
.DOD(DOD_unused),
.ADDRD(B1ADDR),
.DIA(B1DATA[0]),
.DIB(B1DATA[1]),
.DIC(B1DATA[2]),
.DID(1'b0),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM32X2Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [4:0] A1ADDR, A2ADDR, A3ADDR;
output [1:0] A1DATA, A2DATA, A3DATA;
input [4:0] B1ADDR;
input [1:0] B1DATA;
input B1EN;
RAM32M #(
.INIT_A(INIT),
.INIT_B(INIT),
.INIT_C(INIT),
.INIT_D(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.ADDRA(A1ADDR),
.ADDRB(A2ADDR),
.ADDRC(A3ADDR),
.DOA(A1DATA),
.DOB(A2DATA),
.DOC(A3DATA),
.ADDRD(B1ADDR),
.DIA(B1DATA),
.DIB(B1DATA),
.DIC(B1DATA),
.DID(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
module \$__XILINX_RAM64X1Q (CLK1, A1ADDR, A1DATA, A2ADDR, A2DATA, A3ADDR, A3DATA, B1ADDR, B1DATA, B1EN);
parameter [63:0] INIT = 64'bx;
parameter CLKPOL2 = 1;
input CLK1;
input [5:0] A1ADDR, A2ADDR, A3ADDR;
output A1DATA, A2DATA, A3DATA;
input [5:0] B1ADDR;
input B1DATA;
input B1EN;
RAM64M #(
.INIT_A(INIT),
.INIT_B(INIT),
.INIT_C(INIT),
.INIT_D(INIT),
.IS_WCLK_INVERTED(!CLKPOL2)
) _TECHMAP_REPLACE_ (
.ADDRA(A1ADDR),
.ADDRB(A2ADDR),
.ADDRC(A3ADDR),
.DOA(A1DATA),
.DOB(A2DATA),
.DOC(A3DATA),
.ADDRD(B1ADDR),
.DIA(B1DATA),
.DIB(B1DATA),
.DIC(B1DATA),
.DID(B1DATA),
.WCLK(CLK1),
.WE(B1EN)
);
endmodule
|
// File: Array8Sorter.v
// Generated by MyHDL 1.0dev
// Date: Sun May 15 11:40:06 2016
`timescale 1ns/10ps
module Array8Sorter (
a0,
a1,
a2,
a3,
a4,
a5,
a6,
a7,
z0,
z1,
z2,
z3,
z4,
z5,
z6,
z7
);
input [3:0] a0;
input [3:0] a1;
input [3:0] a2;
input [3:0] a3;
input [3:0] a4;
input [3:0] a5;
input [3:0] a6;
input [3:0] a7;
output [3:0] z0;
wire [3:0] z0;
output [3:0] z1;
wire [3:0] z1;
output [3:0] z2;
wire [3:0] z2;
output [3:0] z3;
wire [3:0] z3;
output [3:0] z4;
wire [3:0] z4;
output [3:0] z5;
wire [3:0] z5;
output [3:0] z6;
wire [3:0] z6;
output [3:0] z7;
wire [3:0] z7;
wire [3:0] sort_losort_losort_losort_feedthru_32_z;
wire [3:0] sort_losort_losort_hisort_feedthru_33_z;
reg [3:0] sort_losort_losort_merge_comp_24_z1;
reg [3:0] sort_losort_losort_merge_comp_24_z2;
wire [3:0] sort_losort_losort_merge_lomerge_feedthru_34_z;
wire [3:0] sort_losort_losort_merge_hiMerge_feedthru_35_z;
wire [3:0] sort_losort_hisort_losort_feedthru_36_z;
wire [3:0] sort_losort_hisort_hisort_feedthru_37_z;
reg [3:0] sort_losort_hisort_merge_comp_25_z1;
reg [3:0] sort_losort_hisort_merge_comp_25_z2;
wire [3:0] sort_losort_hisort_merge_lomerge_feedthru_38_z;
wire [3:0] sort_losort_hisort_merge_hiMerge_feedthru_39_z;
reg [3:0] sort_losort_merge_comp_26_z1;
reg [3:0] sort_losort_merge_comp_26_z2;
reg [3:0] sort_losort_merge_comp_27_z1;
reg [3:0] sort_losort_merge_comp_27_z2;
reg [3:0] sort_losort_merge_lomerge_comp_28_z1;
reg [3:0] sort_losort_merge_lomerge_comp_28_z2;
wire [3:0] sort_losort_merge_lomerge_lomerge_feedthru_40_z;
wire [3:0] sort_losort_merge_lomerge_hiMerge_feedthru_41_z;
reg [3:0] sort_losort_merge_hiMerge_comp_29_z1;
reg [3:0] sort_losort_merge_hiMerge_comp_29_z2;
wire [3:0] sort_losort_merge_hiMerge_lomerge_feedthru_42_z;
wire [3:0] sort_losort_merge_hiMerge_hiMerge_feedthru_43_z;
wire [3:0] sort_hisort_losort_losort_feedthru_44_z;
wire [3:0] sort_hisort_losort_hisort_feedthru_45_z;
reg [3:0] sort_hisort_losort_merge_comp_30_z1;
reg [3:0] sort_hisort_losort_merge_comp_30_z2;
wire [3:0] sort_hisort_losort_merge_lomerge_feedthru_46_z;
wire [3:0] sort_hisort_losort_merge_hiMerge_feedthru_47_z;
wire [3:0] sort_hisort_hisort_losort_feedthru_48_z;
wire [3:0] sort_hisort_hisort_hisort_feedthru_49_z;
reg [3:0] sort_hisort_hisort_merge_comp_31_z1;
reg [3:0] sort_hisort_hisort_merge_comp_31_z2;
wire [3:0] sort_hisort_hisort_merge_lomerge_feedthru_50_z;
wire [3:0] sort_hisort_hisort_merge_hiMerge_feedthru_51_z;
reg [3:0] sort_hisort_merge_comp_32_z1;
reg [3:0] sort_hisort_merge_comp_32_z2;
reg [3:0] sort_hisort_merge_comp_33_z1;
reg [3:0] sort_hisort_merge_comp_33_z2;
reg [3:0] sort_hisort_merge_lomerge_comp_34_z1;
reg [3:0] sort_hisort_merge_lomerge_comp_34_z2;
wire [3:0] sort_hisort_merge_lomerge_lomerge_feedthru_52_z;
wire [3:0] sort_hisort_merge_lomerge_hiMerge_feedthru_53_z;
reg [3:0] sort_hisort_merge_hiMerge_comp_35_z1;
reg [3:0] sort_hisort_merge_hiMerge_comp_35_z2;
wire [3:0] sort_hisort_merge_hiMerge_lomerge_feedthru_54_z;
wire [3:0] sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z;
reg [3:0] sort_merge_comp_36_z1;
reg [3:0] sort_merge_comp_36_z2;
reg [3:0] sort_merge_comp_37_z1;
reg [3:0] sort_merge_comp_37_z2;
reg [3:0] sort_merge_comp_38_z1;
reg [3:0] sort_merge_comp_38_z2;
reg [3:0] sort_merge_comp_39_z1;
reg [3:0] sort_merge_comp_39_z2;
reg [3:0] sort_merge_lomerge_comp_40_z1;
reg [3:0] sort_merge_lomerge_comp_40_z2;
reg [3:0] sort_merge_lomerge_comp_41_z1;
reg [3:0] sort_merge_lomerge_comp_41_z2;
reg [3:0] sort_merge_lomerge_lomerge_comp_42_z1;
reg [3:0] sort_merge_lomerge_lomerge_comp_42_z2;
reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z1;
reg [3:0] sort_merge_lomerge_hiMerge_comp_43_z2;
reg [3:0] sort_merge_hiMerge_comp_44_z1;
reg [3:0] sort_merge_hiMerge_comp_44_z2;
reg [3:0] sort_merge_hiMerge_comp_45_z1;
reg [3:0] sort_merge_hiMerge_comp_45_z2;
reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z1;
reg [3:0] sort_merge_hiMerge_lomerge_comp_46_z2;
reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z1;
reg [3:0] sort_merge_hiMerge_hiMerge_comp_47_z2;
assign sort_losort_losort_losort_feedthru_32_z = a0;
assign sort_losort_losort_hisort_feedthru_33_z = a1;
always @(sort_losort_losort_losort_feedthru_32_z, sort_losort_losort_hisort_feedthru_33_z) begin: ARRAY8SORTER_SORT_LOSORT_LOSORT_MERGE_COMP_24_LOGIC
sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_losort_feedthru_32_z;
sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_hisort_feedthru_33_z;
if ((1'b1 == (sort_losort_losort_losort_feedthru_32_z > sort_losort_losort_hisort_feedthru_33_z))) begin
sort_losort_losort_merge_comp_24_z1 = sort_losort_losort_hisort_feedthru_33_z;
sort_losort_losort_merge_comp_24_z2 = sort_losort_losort_losort_feedthru_32_z;
end
end
assign sort_losort_losort_merge_lomerge_feedthru_34_z = sort_losort_losort_merge_comp_24_z1;
assign sort_losort_losort_merge_hiMerge_feedthru_35_z = sort_losort_losort_merge_comp_24_z2;
assign sort_losort_hisort_losort_feedthru_36_z = a2;
assign sort_losort_hisort_hisort_feedthru_37_z = a3;
always @(sort_losort_hisort_losort_feedthru_36_z, sort_losort_hisort_hisort_feedthru_37_z) begin: ARRAY8SORTER_SORT_LOSORT_HISORT_MERGE_COMP_25_LOGIC
sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_losort_feedthru_36_z;
sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_hisort_feedthru_37_z;
if ((1'b0 == (sort_losort_hisort_losort_feedthru_36_z > sort_losort_hisort_hisort_feedthru_37_z))) begin
sort_losort_hisort_merge_comp_25_z1 = sort_losort_hisort_hisort_feedthru_37_z;
sort_losort_hisort_merge_comp_25_z2 = sort_losort_hisort_losort_feedthru_36_z;
end
end
assign sort_losort_hisort_merge_lomerge_feedthru_38_z = sort_losort_hisort_merge_comp_25_z1;
assign sort_losort_hisort_merge_hiMerge_feedthru_39_z = sort_losort_hisort_merge_comp_25_z2;
always @(sort_losort_losort_merge_lomerge_feedthru_34_z, sort_losort_hisort_merge_lomerge_feedthru_38_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_26_LOGIC
sort_losort_merge_comp_26_z1 = sort_losort_losort_merge_lomerge_feedthru_34_z;
sort_losort_merge_comp_26_z2 = sort_losort_hisort_merge_lomerge_feedthru_38_z;
if ((1'b1 == (sort_losort_losort_merge_lomerge_feedthru_34_z > sort_losort_hisort_merge_lomerge_feedthru_38_z))) begin
sort_losort_merge_comp_26_z1 = sort_losort_hisort_merge_lomerge_feedthru_38_z;
sort_losort_merge_comp_26_z2 = sort_losort_losort_merge_lomerge_feedthru_34_z;
end
end
always @(sort_losort_losort_merge_hiMerge_feedthru_35_z, sort_losort_hisort_merge_hiMerge_feedthru_39_z) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_COMP_27_LOGIC
sort_losort_merge_comp_27_z1 = sort_losort_losort_merge_hiMerge_feedthru_35_z;
sort_losort_merge_comp_27_z2 = sort_losort_hisort_merge_hiMerge_feedthru_39_z;
if ((1'b1 == (sort_losort_losort_merge_hiMerge_feedthru_35_z > sort_losort_hisort_merge_hiMerge_feedthru_39_z))) begin
sort_losort_merge_comp_27_z1 = sort_losort_hisort_merge_hiMerge_feedthru_39_z;
sort_losort_merge_comp_27_z2 = sort_losort_losort_merge_hiMerge_feedthru_35_z;
end
end
always @(sort_losort_merge_comp_26_z1, sort_losort_merge_comp_27_z1) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_LOMERGE_COMP_28_LOGIC
sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_26_z1;
sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_27_z1;
if ((1'b1 == (sort_losort_merge_comp_26_z1 > sort_losort_merge_comp_27_z1))) begin
sort_losort_merge_lomerge_comp_28_z1 = sort_losort_merge_comp_27_z1;
sort_losort_merge_lomerge_comp_28_z2 = sort_losort_merge_comp_26_z1;
end
end
assign sort_losort_merge_lomerge_lomerge_feedthru_40_z = sort_losort_merge_lomerge_comp_28_z1;
assign sort_losort_merge_lomerge_hiMerge_feedthru_41_z = sort_losort_merge_lomerge_comp_28_z2;
always @(sort_losort_merge_comp_26_z2, sort_losort_merge_comp_27_z2) begin: ARRAY8SORTER_SORT_LOSORT_MERGE_HIMERGE_COMP_29_LOGIC
sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_26_z2;
sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_27_z2;
if ((1'b1 == (sort_losort_merge_comp_26_z2 > sort_losort_merge_comp_27_z2))) begin
sort_losort_merge_hiMerge_comp_29_z1 = sort_losort_merge_comp_27_z2;
sort_losort_merge_hiMerge_comp_29_z2 = sort_losort_merge_comp_26_z2;
end
end
assign sort_losort_merge_hiMerge_lomerge_feedthru_42_z = sort_losort_merge_hiMerge_comp_29_z1;
assign sort_losort_merge_hiMerge_hiMerge_feedthru_43_z = sort_losort_merge_hiMerge_comp_29_z2;
assign sort_hisort_losort_losort_feedthru_44_z = a4;
assign sort_hisort_losort_hisort_feedthru_45_z = a5;
always @(sort_hisort_losort_losort_feedthru_44_z, sort_hisort_losort_hisort_feedthru_45_z) begin: ARRAY8SORTER_SORT_HISORT_LOSORT_MERGE_COMP_30_LOGIC
sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_losort_feedthru_44_z;
sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_hisort_feedthru_45_z;
if ((1'b1 == (sort_hisort_losort_losort_feedthru_44_z > sort_hisort_losort_hisort_feedthru_45_z))) begin
sort_hisort_losort_merge_comp_30_z1 = sort_hisort_losort_hisort_feedthru_45_z;
sort_hisort_losort_merge_comp_30_z2 = sort_hisort_losort_losort_feedthru_44_z;
end
end
assign sort_hisort_losort_merge_lomerge_feedthru_46_z = sort_hisort_losort_merge_comp_30_z1;
assign sort_hisort_losort_merge_hiMerge_feedthru_47_z = sort_hisort_losort_merge_comp_30_z2;
assign sort_hisort_hisort_losort_feedthru_48_z = a6;
assign sort_hisort_hisort_hisort_feedthru_49_z = a7;
always @(sort_hisort_hisort_losort_feedthru_48_z, sort_hisort_hisort_hisort_feedthru_49_z) begin: ARRAY8SORTER_SORT_HISORT_HISORT_MERGE_COMP_31_LOGIC
sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_losort_feedthru_48_z;
sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_hisort_feedthru_49_z;
if ((1'b0 == (sort_hisort_hisort_losort_feedthru_48_z > sort_hisort_hisort_hisort_feedthru_49_z))) begin
sort_hisort_hisort_merge_comp_31_z1 = sort_hisort_hisort_hisort_feedthru_49_z;
sort_hisort_hisort_merge_comp_31_z2 = sort_hisort_hisort_losort_feedthru_48_z;
end
end
assign sort_hisort_hisort_merge_lomerge_feedthru_50_z = sort_hisort_hisort_merge_comp_31_z1;
assign sort_hisort_hisort_merge_hiMerge_feedthru_51_z = sort_hisort_hisort_merge_comp_31_z2;
always @(sort_hisort_losort_merge_lomerge_feedthru_46_z, sort_hisort_hisort_merge_lomerge_feedthru_50_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_32_LOGIC
sort_hisort_merge_comp_32_z1 = sort_hisort_losort_merge_lomerge_feedthru_46_z;
sort_hisort_merge_comp_32_z2 = sort_hisort_hisort_merge_lomerge_feedthru_50_z;
if ((1'b0 == (sort_hisort_losort_merge_lomerge_feedthru_46_z > sort_hisort_hisort_merge_lomerge_feedthru_50_z))) begin
sort_hisort_merge_comp_32_z1 = sort_hisort_hisort_merge_lomerge_feedthru_50_z;
sort_hisort_merge_comp_32_z2 = sort_hisort_losort_merge_lomerge_feedthru_46_z;
end
end
always @(sort_hisort_losort_merge_hiMerge_feedthru_47_z, sort_hisort_hisort_merge_hiMerge_feedthru_51_z) begin: ARRAY8SORTER_SORT_HISORT_MERGE_COMP_33_LOGIC
sort_hisort_merge_comp_33_z1 = sort_hisort_losort_merge_hiMerge_feedthru_47_z;
sort_hisort_merge_comp_33_z2 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z;
if ((1'b0 == (sort_hisort_losort_merge_hiMerge_feedthru_47_z > sort_hisort_hisort_merge_hiMerge_feedthru_51_z))) begin
sort_hisort_merge_comp_33_z1 = sort_hisort_hisort_merge_hiMerge_feedthru_51_z;
sort_hisort_merge_comp_33_z2 = sort_hisort_losort_merge_hiMerge_feedthru_47_z;
end
end
always @(sort_hisort_merge_comp_32_z1, sort_hisort_merge_comp_33_z1) begin: ARRAY8SORTER_SORT_HISORT_MERGE_LOMERGE_COMP_34_LOGIC
sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_32_z1;
sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_33_z1;
if ((1'b0 == (sort_hisort_merge_comp_32_z1 > sort_hisort_merge_comp_33_z1))) begin
sort_hisort_merge_lomerge_comp_34_z1 = sort_hisort_merge_comp_33_z1;
sort_hisort_merge_lomerge_comp_34_z2 = sort_hisort_merge_comp_32_z1;
end
end
assign sort_hisort_merge_lomerge_lomerge_feedthru_52_z = sort_hisort_merge_lomerge_comp_34_z1;
assign sort_hisort_merge_lomerge_hiMerge_feedthru_53_z = sort_hisort_merge_lomerge_comp_34_z2;
always @(sort_hisort_merge_comp_32_z2, sort_hisort_merge_comp_33_z2) begin: ARRAY8SORTER_SORT_HISORT_MERGE_HIMERGE_COMP_35_LOGIC
sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_32_z2;
sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_33_z2;
if ((1'b0 == (sort_hisort_merge_comp_32_z2 > sort_hisort_merge_comp_33_z2))) begin
sort_hisort_merge_hiMerge_comp_35_z1 = sort_hisort_merge_comp_33_z2;
sort_hisort_merge_hiMerge_comp_35_z2 = sort_hisort_merge_comp_32_z2;
end
end
assign sort_hisort_merge_hiMerge_lomerge_feedthru_54_z = sort_hisort_merge_hiMerge_comp_35_z1;
assign sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z = sort_hisort_merge_hiMerge_comp_35_z2;
always @(sort_losort_merge_lomerge_lomerge_feedthru_40_z, sort_hisort_merge_lomerge_lomerge_feedthru_52_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_36_LOGIC
sort_merge_comp_36_z1 = sort_losort_merge_lomerge_lomerge_feedthru_40_z;
sort_merge_comp_36_z2 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z;
if ((1'b1 == (sort_losort_merge_lomerge_lomerge_feedthru_40_z > sort_hisort_merge_lomerge_lomerge_feedthru_52_z))) begin
sort_merge_comp_36_z1 = sort_hisort_merge_lomerge_lomerge_feedthru_52_z;
sort_merge_comp_36_z2 = sort_losort_merge_lomerge_lomerge_feedthru_40_z;
end
end
always @(sort_losort_merge_lomerge_hiMerge_feedthru_41_z, sort_hisort_merge_lomerge_hiMerge_feedthru_53_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_37_LOGIC
sort_merge_comp_37_z1 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z;
sort_merge_comp_37_z2 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z;
if ((1'b1 == (sort_losort_merge_lomerge_hiMerge_feedthru_41_z > sort_hisort_merge_lomerge_hiMerge_feedthru_53_z))) begin
sort_merge_comp_37_z1 = sort_hisort_merge_lomerge_hiMerge_feedthru_53_z;
sort_merge_comp_37_z2 = sort_losort_merge_lomerge_hiMerge_feedthru_41_z;
end
end
always @(sort_losort_merge_hiMerge_lomerge_feedthru_42_z, sort_hisort_merge_hiMerge_lomerge_feedthru_54_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_38_LOGIC
sort_merge_comp_38_z1 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z;
sort_merge_comp_38_z2 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z;
if ((1'b1 == (sort_losort_merge_hiMerge_lomerge_feedthru_42_z > sort_hisort_merge_hiMerge_lomerge_feedthru_54_z))) begin
sort_merge_comp_38_z1 = sort_hisort_merge_hiMerge_lomerge_feedthru_54_z;
sort_merge_comp_38_z2 = sort_losort_merge_hiMerge_lomerge_feedthru_42_z;
end
end
always @(sort_losort_merge_hiMerge_hiMerge_feedthru_43_z, sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z) begin: ARRAY8SORTER_SORT_MERGE_COMP_39_LOGIC
sort_merge_comp_39_z1 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z;
sort_merge_comp_39_z2 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z;
if ((1'b1 == (sort_losort_merge_hiMerge_hiMerge_feedthru_43_z > sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z))) begin
sort_merge_comp_39_z1 = sort_hisort_merge_hiMerge_hiMerge_feedthru_55_z;
sort_merge_comp_39_z2 = sort_losort_merge_hiMerge_hiMerge_feedthru_43_z;
end
end
always @(sort_merge_comp_36_z1, sort_merge_comp_38_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_40_LOGIC
sort_merge_lomerge_comp_40_z1 = sort_merge_comp_36_z1;
sort_merge_lomerge_comp_40_z2 = sort_merge_comp_38_z1;
if ((1'b1 == (sort_merge_comp_36_z1 > sort_merge_comp_38_z1))) begin
sort_merge_lomerge_comp_40_z1 = sort_merge_comp_38_z1;
sort_merge_lomerge_comp_40_z2 = sort_merge_comp_36_z1;
end
end
always @(sort_merge_comp_37_z1, sort_merge_comp_39_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_COMP_41_LOGIC
sort_merge_lomerge_comp_41_z1 = sort_merge_comp_37_z1;
sort_merge_lomerge_comp_41_z2 = sort_merge_comp_39_z1;
if ((1'b1 == (sort_merge_comp_37_z1 > sort_merge_comp_39_z1))) begin
sort_merge_lomerge_comp_41_z1 = sort_merge_comp_39_z1;
sort_merge_lomerge_comp_41_z2 = sort_merge_comp_37_z1;
end
end
always @(sort_merge_lomerge_comp_40_z1, sort_merge_lomerge_comp_41_z1) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_LOMERGE_COMP_42_LOGIC
sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_40_z1;
sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_41_z1;
if ((1'b1 == (sort_merge_lomerge_comp_40_z1 > sort_merge_lomerge_comp_41_z1))) begin
sort_merge_lomerge_lomerge_comp_42_z1 = sort_merge_lomerge_comp_41_z1;
sort_merge_lomerge_lomerge_comp_42_z2 = sort_merge_lomerge_comp_40_z1;
end
end
assign z0 = sort_merge_lomerge_lomerge_comp_42_z1;
assign z1 = sort_merge_lomerge_lomerge_comp_42_z2;
always @(sort_merge_lomerge_comp_40_z2, sort_merge_lomerge_comp_41_z2) begin: ARRAY8SORTER_SORT_MERGE_LOMERGE_HIMERGE_COMP_43_LOGIC
sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_40_z2;
sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_41_z2;
if ((1'b1 == (sort_merge_lomerge_comp_40_z2 > sort_merge_lomerge_comp_41_z2))) begin
sort_merge_lomerge_hiMerge_comp_43_z1 = sort_merge_lomerge_comp_41_z2;
sort_merge_lomerge_hiMerge_comp_43_z2 = sort_merge_lomerge_comp_40_z2;
end
end
assign z2 = sort_merge_lomerge_hiMerge_comp_43_z1;
assign z3 = sort_merge_lomerge_hiMerge_comp_43_z2;
always @(sort_merge_comp_36_z2, sort_merge_comp_38_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_44_LOGIC
sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_36_z2;
sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_38_z2;
if ((1'b1 == (sort_merge_comp_36_z2 > sort_merge_comp_38_z2))) begin
sort_merge_hiMerge_comp_44_z1 = sort_merge_comp_38_z2;
sort_merge_hiMerge_comp_44_z2 = sort_merge_comp_36_z2;
end
end
always @(sort_merge_comp_37_z2, sort_merge_comp_39_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_COMP_45_LOGIC
sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_37_z2;
sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_39_z2;
if ((1'b1 == (sort_merge_comp_37_z2 > sort_merge_comp_39_z2))) begin
sort_merge_hiMerge_comp_45_z1 = sort_merge_comp_39_z2;
sort_merge_hiMerge_comp_45_z2 = sort_merge_comp_37_z2;
end
end
always @(sort_merge_hiMerge_comp_44_z1, sort_merge_hiMerge_comp_45_z1) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_LOMERGE_COMP_46_LOGIC
sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_44_z1;
sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_45_z1;
if ((1'b1 == (sort_merge_hiMerge_comp_44_z1 > sort_merge_hiMerge_comp_45_z1))) begin
sort_merge_hiMerge_lomerge_comp_46_z1 = sort_merge_hiMerge_comp_45_z1;
sort_merge_hiMerge_lomerge_comp_46_z2 = sort_merge_hiMerge_comp_44_z1;
end
end
assign z4 = sort_merge_hiMerge_lomerge_comp_46_z1;
assign z5 = sort_merge_hiMerge_lomerge_comp_46_z2;
always @(sort_merge_hiMerge_comp_44_z2, sort_merge_hiMerge_comp_45_z2) begin: ARRAY8SORTER_SORT_MERGE_HIMERGE_HIMERGE_COMP_47_LOGIC
sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_44_z2;
sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_45_z2;
if ((1'b1 == (sort_merge_hiMerge_comp_44_z2 > sort_merge_hiMerge_comp_45_z2))) begin
sort_merge_hiMerge_hiMerge_comp_47_z1 = sort_merge_hiMerge_comp_45_z2;
sort_merge_hiMerge_hiMerge_comp_47_z2 = sort_merge_hiMerge_comp_44_z2;
end
end
assign z6 = sort_merge_hiMerge_hiMerge_comp_47_z1;
assign z7 = sort_merge_hiMerge_hiMerge_comp_47_z2;
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: data_prbs_gen.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:19 $
// \ \ / \ Date Created: Fri Sep 01 2006
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module is used LFSR to generate random data for memory
// data write or memory data read comparison.The first data is
// seeded by the input prbs_seed_i which is connected to memory address.
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_data_prbs_gen #
(
parameter TCQ = 100,
parameter EYE_TEST = "FALSE",
parameter PRBS_WIDTH = 32, // "SEQUENTIAL_BUrst_i"
parameter SEED_WIDTH = 32
)
(
input clk_i,
input clk_en,
input rst_i,
input prbs_seed_init, // when high the prbs_x_seed will be loaded
input [PRBS_WIDTH - 1:0] prbs_seed_i,
output [PRBS_WIDTH - 1:0] prbs_o // generated address
);
reg [PRBS_WIDTH - 1 :0] prbs;
reg [PRBS_WIDTH :1] lfsr_q;
integer i;
always @ (posedge clk_i)
begin
if (prbs_seed_init && EYE_TEST == "FALSE" || rst_i ) //reset it to a known good state to prevent it locks up
// if (rst_i ) //reset it to a known good state to prevent it locks up
begin
lfsr_q[4:1] <= #TCQ prbs_seed_i[3:0] | 4'h5;
// lfsr_q[PRBS_WIDTH-1:4] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
lfsr_q[PRBS_WIDTH:5] <= #TCQ prbs_seed_i[PRBS_WIDTH-1:4] ;
end
else if (clk_en) begin
lfsr_q[32:9] <= #TCQ lfsr_q[31:8];
lfsr_q[8] <= #TCQ lfsr_q[32] ^ lfsr_q[7];
lfsr_q[7] <= #TCQ lfsr_q[32] ^ lfsr_q[6];
lfsr_q[6:4] <= #TCQ lfsr_q[5:3];
lfsr_q[3] <= #TCQ lfsr_q[32] ^ lfsr_q[2];
lfsr_q[2] <= #TCQ lfsr_q[1] ;
lfsr_q[1] <= #TCQ lfsr_q[32];
end
end
always @ (lfsr_q[PRBS_WIDTH:1]) begin
prbs = lfsr_q[PRBS_WIDTH:1];
end
assign prbs_o = prbs;
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txethmac.v ////
/// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/projects/ethmac/ ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: eth_txethmac.v,v $
// Revision 1.9 2005/02/21 11:25:28 igorm
// Delayed CRC fixed.
//
// Revision 1.8 2003/01/30 13:33:24 mohor
// When padding was enabled and crc disabled, frame was not ended correctly.
//
// Revision 1.7 2002/02/26 16:24:01 mohor
// RetryCntLatched was unused and removed from design
//
// Revision 1.6 2002/02/22 12:56:35 mohor
// Retry is not activated when a Tx Underrun occured
//
// Revision 1.5 2002/02/11 09:18:22 mohor
// Tx status is written back to the BD.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.3 2001/06/19 18:16:40 mohor
// TxClk changed to MTxClk (as discribed in the documentation).
// Crc changed so only one file can be used instead of two.
//
// Revision 1.2 2001/06/19 10:38:08 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:58 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txethmac (MTxClk, Reset, TxStartFrm, TxEndFrm, TxUnderRun, TxData, CarrierSense,
Collision, Pad, CrcEn, FullD, HugEn, DlyCrcEn, MinFL, MaxFL, IPGT,
IPGR1, IPGR2, CollValid, MaxRet, NoBckof, ExDfrEn,
MTxD, MTxEn, MTxErr, TxDone, TxRetry, TxAbort, TxUsedData, WillTransmit,
ResetCollision, RetryCnt, StartTxDone, StartTxAbort, MaxCollisionOccured,
LateCollision, DeferIndication, StatePreamble, StateData
);
parameter Tp = 1;
input MTxClk; // Transmit clock (from PHY)
input Reset; // Reset
input TxStartFrm; // Transmit packet start frame
input TxEndFrm; // Transmit packet end frame
input TxUnderRun; // Transmit packet under-run
input [7:0] TxData; // Transmit packet data byte
input CarrierSense; // Carrier sense (synchronized)
input Collision; // Collision (synchronized)
input Pad; // Pad enable (from register)
input CrcEn; // Crc enable (from register)
input FullD; // Full duplex (from register)
input HugEn; // Huge packets enable (from register)
input DlyCrcEn; // Delayed Crc enabled (from register)
input [15:0] MinFL; // Minimum frame length (from register)
input [15:0] MaxFL; // Maximum frame length (from register)
input [6:0] IPGT; // Back to back transmit inter packet gap parameter (from register)
input [6:0] IPGR1; // Non back to back transmit inter packet gap parameter IPGR1 (from register)
input [6:0] IPGR2; // Non back to back transmit inter packet gap parameter IPGR2 (from register)
input [5:0] CollValid; // Valid collision window (from register)
input [3:0] MaxRet; // Maximum retry number (from register)
input NoBckof; // No backoff (from register)
input ExDfrEn; // Excessive defferal enable (from register)
output [3:0] MTxD; // Transmit nibble (to PHY)
output MTxEn; // Transmit enable (to PHY)
output MTxErr; // Transmit error (to PHY)
output TxDone; // Transmit packet done (to RISC)
output TxRetry; // Transmit packet retry (to RISC)
output TxAbort; // Transmit packet abort (to RISC)
output TxUsedData; // Transmit packet used data (to RISC)
output WillTransmit; // Will transmit (to RxEthMAC)
output ResetCollision; // Reset Collision (for synchronizing collision)
output [3:0] RetryCnt; // Latched Retry Counter for tx status purposes
output StartTxDone;
output StartTxAbort;
output MaxCollisionOccured;
output LateCollision;
output DeferIndication;
output StatePreamble;
output [1:0] StateData;
reg [3:0] MTxD;
reg MTxEn;
reg MTxErr;
reg TxDone;
reg TxRetry;
reg TxAbort;
reg TxUsedData;
reg WillTransmit;
reg ColWindow;
reg StopExcessiveDeferOccured;
reg [3:0] RetryCnt;
reg [3:0] MTxD_d;
reg StatusLatch;
reg PacketFinished_q;
reg PacketFinished;
wire ExcessiveDeferOccured;
wire StartIPG;
wire StartPreamble;
wire [1:0] StartData;
wire StartFCS;
wire StartJam;
wire StartDefer;
wire StartBackoff;
wire StateDefer;
wire StateIPG;
wire StateIdle;
wire StatePAD;
wire StateFCS;
wire StateJam;
wire StateJam_q;
wire StateBackOff;
wire StateSFD;
wire StartTxRetry;
wire UnderRun;
wire TooBig;
wire [31:0] Crc;
wire CrcError;
wire [2:0] DlyCrcCnt;
wire [15:0] NibCnt;
wire NibCntEq7;
wire NibCntEq15;
wire NibbleMinFl;
wire ExcessiveDefer;
wire [15:0] ByteCnt;
wire MaxFrame;
wire RetryMax;
wire RandomEq0;
wire RandomEqByteCnt;
wire PacketFinished_d;
assign ResetCollision = ~(StatePreamble | (|StateData) | StatePAD | StateFCS);
assign ExcessiveDeferOccured = TxStartFrm & StateDefer & ExcessiveDefer & ~StopExcessiveDeferOccured;
assign StartTxDone = ~Collision & (StateFCS & NibCntEq7 | StateData[1] & TxEndFrm & (~Pad | Pad & NibbleMinFl) & ~CrcEn);
assign UnderRun = StateData[0] & TxUnderRun & ~Collision;
assign TooBig = ~Collision & MaxFrame & (StateData[0] & ~TxUnderRun | StateFCS);
// assign StartTxRetry = StartJam & (ColWindow & ~RetryMax);
assign StartTxRetry = StartJam & (ColWindow & ~RetryMax) & ~UnderRun;
assign LateCollision = StartJam & ~ColWindow & ~UnderRun;
assign MaxCollisionOccured = StartJam & ColWindow & RetryMax;
assign StateSFD = StatePreamble & NibCntEq15;
assign StartTxAbort = TooBig | UnderRun | ExcessiveDeferOccured | LateCollision | MaxCollisionOccured;
// StopExcessiveDeferOccured
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StopExcessiveDeferOccured <= #Tp 1'b0;
else
if(ExcessiveDeferOccured)
StopExcessiveDeferOccured <= #Tp 1'b1;
end
end
// Collision Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ColWindow <= #Tp 1'b1;
else
begin
if(~Collision & ByteCnt[5:0] == CollValid[5:0] & (StateData[1] | StatePAD & NibCnt[0] | StateFCS & NibCnt[0]))
ColWindow <= #Tp 1'b0;
else
if(StateIdle | StateIPG)
ColWindow <= #Tp 1'b1;
end
end
// Start Window
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
StatusLatch <= #Tp 1'b0;
else
begin
if(~TxStartFrm)
StatusLatch <= #Tp 1'b0;
else
if(ExcessiveDeferOccured | StateIdle)
StatusLatch <= #Tp 1'b1;
end
end
// Transmit packet used data
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxUsedData <= #Tp 1'b0;
else
TxUsedData <= #Tp |StartData;
end
// Transmit packet done
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxDone <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxDone <= #Tp 1'b0;
else
if(StartTxDone)
TxDone <= #Tp 1'b1;
end
end
// Transmit packet retry
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxRetry <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch)
TxRetry <= #Tp 1'b0;
else
if(StartTxRetry)
TxRetry <= #Tp 1'b1;
end
end
// Transmit packet abort
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
TxAbort <= #Tp 1'b0;
else
begin
if(TxStartFrm & ~StatusLatch & ~ExcessiveDeferOccured)
TxAbort <= #Tp 1'b0;
else
if(StartTxAbort)
TxAbort <= #Tp 1'b1;
end
end
// Retry counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
RetryCnt[3:0] <= #Tp 4'h0;
else
begin
if(ExcessiveDeferOccured | UnderRun | TooBig | StartTxDone | TxUnderRun
| StateJam & NibCntEq7 & (~ColWindow | RetryMax))
RetryCnt[3:0] <= #Tp 4'h0;
else
if(StateJam & NibCntEq7 & ColWindow & (RandomEq0 | NoBckof) | StateBackOff & RandomEqByteCnt)
RetryCnt[3:0] <= #Tp RetryCnt[3:0] + 1'b1;
end
end
assign RetryMax = RetryCnt[3:0] == MaxRet[3:0];
// Transmit nibble
always @ (StatePreamble or StateData or StateData or StateFCS or StateJam or StateSFD or TxData or
Crc or NibCntEq15)
begin
if(StateData[0])
MTxD_d[3:0] = TxData[3:0]; // Lower nibble
else
if(StateData[1])
MTxD_d[3:0] = TxData[7:4]; // Higher nibble
else
if(StateFCS)
MTxD_d[3:0] = {~Crc[28], ~Crc[29], ~Crc[30], ~Crc[31]}; // Crc
else
if(StateJam)
MTxD_d[3:0] = 4'h9; // Jam pattern
else
if(StatePreamble)
if(NibCntEq15)
MTxD_d[3:0] = 4'hd; // SFD
else
MTxD_d[3:0] = 4'h5; // Preamble
else
MTxD_d[3:0] = 4'h0;
end
// Transmit Enable
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxEn <= #Tp 1'b0;
else
MTxEn <= #Tp StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
// Transmit nibble
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxD[3:0] <= #Tp 4'h0;
else
MTxD[3:0] <= #Tp MTxD_d[3:0];
end
// Transmit error
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
MTxErr <= #Tp 1'b0;
else
MTxErr <= #Tp TooBig | UnderRun;
end
// WillTransmit
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
WillTransmit <= #Tp 1'b0;
else
WillTransmit <= #Tp StartPreamble | StatePreamble | (|StateData) | StatePAD | StateFCS | StateJam;
end
assign PacketFinished_d = StartTxDone | TooBig | UnderRun | LateCollision | MaxCollisionOccured | ExcessiveDeferOccured;
// Packet finished
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
begin
PacketFinished <= #Tp 1'b0;
PacketFinished_q <= #Tp 1'b0;
end
else
begin
PacketFinished <= #Tp PacketFinished_d;
PacketFinished_q <= #Tp PacketFinished;
end
end
// Connecting module Counters
eth_txcounters txcounters1 (.StatePreamble(StatePreamble), .StateIPG(StateIPG), .StateData(StateData),
.StatePAD(StatePAD), .StateFCS(StateFCS), .StateJam(StateJam), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StateIdle(StateIdle), .StartDefer(StartDefer), .StartIPG(StartIPG),
.StartFCS(StartFCS), .StartJam(StartJam), .TxStartFrm(TxStartFrm), .MTxClk(MTxClk),
.Reset(Reset), .MinFL(MinFL), .MaxFL(MaxFL), .HugEn(HugEn), .ExDfrEn(ExDfrEn),
.PacketFinished_q(PacketFinished_q), .DlyCrcEn(DlyCrcEn), .StartBackoff(StartBackoff),
.StateSFD(StateSFD), .ByteCnt(ByteCnt), .NibCnt(NibCnt), .ExcessiveDefer(ExcessiveDefer),
.NibCntEq7(NibCntEq7), .NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .NibbleMinFl(NibbleMinFl),
.DlyCrcCnt(DlyCrcCnt)
);
// Connecting module StateM
eth_txstatem txstatem1 (.MTxClk(MTxClk), .Reset(Reset), .ExcessiveDefer(ExcessiveDefer), .CarrierSense(CarrierSense),
.NibCnt(NibCnt[6:0]), .IPGT(IPGT), .IPGR1(IPGR1), .IPGR2(IPGR2), .FullD(FullD),
.TxStartFrm(TxStartFrm), .TxEndFrm(TxEndFrm), .TxUnderRun(TxUnderRun), .Collision(Collision),
.UnderRun(UnderRun), .StartTxDone(StartTxDone), .TooBig(TooBig), .NibCntEq7(NibCntEq7),
.NibCntEq15(NibCntEq15), .MaxFrame(MaxFrame), .Pad(Pad), .CrcEn(CrcEn),
.NibbleMinFl(NibbleMinFl), .RandomEq0(RandomEq0), .ColWindow(ColWindow), .RetryMax(RetryMax),
.NoBckof(NoBckof), .RandomEqByteCnt(RandomEqByteCnt), .StateIdle(StateIdle),
.StateIPG(StateIPG), .StatePreamble(StatePreamble), .StateData(StateData), .StatePAD(StatePAD),
.StateFCS(StateFCS), .StateJam(StateJam), .StateJam_q(StateJam_q), .StateBackOff(StateBackOff),
.StateDefer(StateDefer), .StartFCS(StartFCS), .StartJam(StartJam), .StartBackoff(StartBackoff),
.StartDefer(StartDefer), .DeferIndication(DeferIndication), .StartPreamble(StartPreamble), .StartData(StartData), .StartIPG(StartIPG)
);
wire Enable_Crc;
wire [3:0] Data_Crc;
wire Initialize_Crc;
assign Enable_Crc = ~StateFCS;
assign Data_Crc[0] = StateData[0]? TxData[3] : StateData[1]? TxData[7] : 1'b0;
assign Data_Crc[1] = StateData[0]? TxData[2] : StateData[1]? TxData[6] : 1'b0;
assign Data_Crc[2] = StateData[0]? TxData[1] : StateData[1]? TxData[5] : 1'b0;
assign Data_Crc[3] = StateData[0]? TxData[0] : StateData[1]? TxData[4] : 1'b0;
assign Initialize_Crc = StateIdle | StatePreamble | (|DlyCrcCnt);
// Connecting module Crc
eth_crc txcrc (.Clk(MTxClk), .Reset(Reset), .Data(Data_Crc), .Enable(Enable_Crc), .Initialize(Initialize_Crc),
.Crc(Crc), .CrcError(CrcError)
);
// Connecting module Random
eth_random random1 (.MTxClk(MTxClk), .Reset(Reset), .StateJam(StateJam), .StateJam_q(StateJam_q), .RetryCnt(RetryCnt),
.NibCnt(NibCnt), .ByteCnt(ByteCnt[9:0]), .RandomEq0(RandomEq0), .RandomEqByteCnt(RandomEqByteCnt));
endmodule
|
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: upd77c25_pgmrom.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 20.1.1 Build 720 11/11/2020 SJ Lite Edition
// ************************************************************
//Copyright (C) 2020 Intel Corporation. All rights reserved.
//Your use of Intel Corporation's design tools, logic functions
//and other software and tools, and any partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Intel Program License
//Subscription Agreement, the Intel Quartus Prime License Agreement,
//the Intel FPGA IP License Agreement, or other applicable license
//agreement, including, without limitation, that your use is for
//the sole purpose of programming logic devices manufactured by
//Intel and sold by Intel or its authorized distributors. Please
//refer to the applicable agreement for further details, at
//https://fpgasoftware.intel.com/eula.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module upd77c25_pgmrom (
clock,
data,
rdaddress,
wraddress,
wren,
q);
input clock;
input [23:0] data;
input [10:0] rdaddress;
input [10:0] wraddress;
input wren;
output [23:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
tri0 wren;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [23:0] sub_wire0;
wire [23:0] q = sub_wire0[23:0];
altsyncram altsyncram_component (
.address_a (wraddress),
.address_b (rdaddress),
.clock0 (clock),
.data_a (data),
.wren_a (wren),
.q_b (sub_wire0),
.aclr0 (1'b0),
.aclr1 (1'b0),
.addressstall_a (1'b0),
.addressstall_b (1'b0),
.byteena_a (1'b1),
.byteena_b (1'b1),
.clock1 (1'b1),
.clocken0 (1'b1),
.clocken1 (1'b1),
.clocken2 (1'b1),
.clocken3 (1'b1),
.data_b ({24{1'b1}}),
.eccstatus (),
.q_a (),
.rden_a (1'b1),
.rden_b (1'b1),
.wren_b (1'b0));
defparam
altsyncram_component.address_aclr_b = "NONE",
altsyncram_component.address_reg_b = "CLOCK0",
altsyncram_component.clock_enable_input_a = "BYPASS",
altsyncram_component.clock_enable_input_b = "BYPASS",
altsyncram_component.clock_enable_output_b = "BYPASS",
altsyncram_component.intended_device_family = "Cyclone IV E",
altsyncram_component.lpm_type = "altsyncram",
altsyncram_component.numwords_a = 2048,
altsyncram_component.numwords_b = 2048,
altsyncram_component.operation_mode = "DUAL_PORT",
altsyncram_component.outdata_aclr_b = "NONE",
altsyncram_component.outdata_reg_b = "UNREGISTERED",
altsyncram_component.power_up_uninitialized = "FALSE",
altsyncram_component.read_during_write_mode_mixed_ports = "DONT_CARE",
altsyncram_component.widthad_a = 11,
altsyncram_component.widthad_b = 11,
altsyncram_component.width_a = 24,
altsyncram_component.width_b = 24,
altsyncram_component.width_byteena_a = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "1"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0"
// Retrieval info: PRIVATE: CLRdata NUMERIC "0"
// Retrieval info: PRIVATE: CLRq NUMERIC "0"
// Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRrren NUMERIC "0"
// Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
// Retrieval info: PRIVATE: CLRwren NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Clock_A NUMERIC "0"
// Retrieval info: PRIVATE: Clock_B NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_B"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MEMSIZE NUMERIC "49152"
// Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING ""
// Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "2"
// Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "3"
// Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "3"
// Retrieval info: PRIVATE: REGdata NUMERIC "1"
// Retrieval info: PRIVATE: REGq NUMERIC "1"
// Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
// Retrieval info: PRIVATE: REGrren NUMERIC "1"
// Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
// Retrieval info: PRIVATE: REGwren NUMERIC "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0"
// Retrieval info: PRIVATE: UseDPRAM NUMERIC "1"
// Retrieval info: PRIVATE: VarWidth NUMERIC "0"
// Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "24"
// Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "24"
// Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
// Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
// Retrieval info: PRIVATE: enable NUMERIC "0"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK0"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV E"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "2048"
// Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "2048"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "DUAL_PORT"
// Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
// Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
// Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_MIXED_PORTS STRING "DONT_CARE"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "11"
// Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "11"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_B NUMERIC "24"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: data 0 0 24 0 INPUT NODEFVAL "data[23..0]"
// Retrieval info: USED_PORT: q 0 0 24 0 OUTPUT NODEFVAL "q[23..0]"
// Retrieval info: USED_PORT: rdaddress 0 0 11 0 INPUT NODEFVAL "rdaddress[10..0]"
// Retrieval info: USED_PORT: wraddress 0 0 11 0 INPUT NODEFVAL "wraddress[10..0]"
// Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND "wren"
// Retrieval info: CONNECT: @address_a 0 0 11 0 wraddress 0 0 11 0
// Retrieval info: CONNECT: @address_b 0 0 11 0 rdaddress 0 0 11 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: @data_a 0 0 24 0 data 0 0 24 0
// Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
// Retrieval info: CONNECT: q 0 0 24 0 @q_b 0 0 24 0
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_inst.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL upd77c25_pgmrom_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36,
parameter C_M_AXI_DATA_WIDTH = 64
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [2:0] pcie_max_payload_size,
input [2:0] pcie_max_read_req_size,
input pcie_rcb,
output [7:0] hcmd_prp_rd_addr,
input [44:0] hcmd_prp_rd_data,
output hcmd_nlb_wr1_en,
output [6:0] hcmd_nlb_wr1_addr,
output [18:0] hcmd_nlb_wr1_data,
input hcmd_nlb_wr1_rdy_n,
output [6:0] hcmd_nlb_rd_addr,
input [18:0] hcmd_nlb_rd_data,
output dev_rx_cmd_wr_en,
output [29:0] dev_rx_cmd_wr_data,
input dev_rx_cmd_full_n,
output dev_tx_cmd_wr_en,
output [29:0] dev_tx_cmd_wr_data,
input dev_tx_cmd_full_n,
output tx_prp_mrd_req,
output [7:0] tx_prp_mrd_tag,
output [11:2] tx_prp_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_prp_mrd_addr,
input tx_prp_mrd_req_ack,
input [7:0] cpld_prp_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_prp_fifo_wr_data,
input cpld_prp_fifo_wr_en,
input cpld_prp_fifo_tag_last,
output tx_dma_mrd_req,
output [7:0] tx_dma_mrd_tag,
output [11:2] tx_dma_mrd_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mrd_addr,
input tx_dma_mrd_req_ack,
input [7:0] cpld_dma_fifo_tag,
input [C_PCIE_DATA_WIDTH-1:0] cpld_dma_fifo_wr_data,
input cpld_dma_fifo_wr_en,
input cpld_dma_fifo_tag_last,
output tx_dma_mwr_req,
output [7:0] tx_dma_mwr_tag,
output [11:2] tx_dma_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_dma_mwr_addr,
input tx_dma_mwr_req_ack,
input tx_dma_mwr_data_last,
input pcie_tx_dma_fifo_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] pcie_tx_dma_fifo_rd_data,
output hcmd_cq_wr0_en,
output [34:0] hcmd_cq_wr0_data0,
output [34:0] hcmd_cq_wr0_data1,
input hcmd_cq_wr0_rdy_n,
input cpu_bus_clk,
input cpu_bus_rst_n,
input dma_cmd_wr_en,
input [49:0] dma_cmd_wr_data0,
input [49:0] dma_cmd_wr_data1,
output dma_cmd_wr_rdy_n,
output [7:0] dma_rx_direct_done_cnt,
output [7:0] dma_tx_direct_done_cnt,
output [7:0] dma_rx_done_cnt,
output [7:0] dma_tx_done_cnt,
input dma_bus_clk,
input dma_bus_rst_n,
input pcie_rx_fifo_rd_en,
output [C_M_AXI_DATA_WIDTH-1:0] pcie_rx_fifo_rd_data,
input pcie_rx_fifo_free_en,
input [9:4] pcie_rx_fifo_free_len,
output pcie_rx_fifo_empty_n,
input pcie_tx_fifo_alloc_en,
input [9:4] pcie_tx_fifo_alloc_len,
input pcie_tx_fifo_wr_en,
input [C_M_AXI_DATA_WIDTH-1:0] pcie_tx_fifo_wr_data,
output pcie_tx_fifo_full_n,
input dma_rx_done_wr_en,
input [20:0] dma_rx_done_wr_data,
output dma_rx_done_wr_rdy_n
);
wire w_pcie_rx_cmd_wr_en;
wire [33:0] w_pcie_rx_cmd_wr_data;
wire w_pcie_rx_cmd_full_n;
wire w_pcie_tx_cmd_wr_en;
wire [33:0] w_pcie_tx_cmd_wr_data;
wire w_pcie_tx_cmd_full_n;
wire w_dma_tx_done_wr_en;
wire [20:0] w_dma_tx_done_wr_data;
wire w_dma_tx_done_wr_rdy_n;
dma_cmd
dma_cmd_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_rcb (pcie_rcb),
.hcmd_prp_rd_addr (hcmd_prp_rd_addr),
.hcmd_prp_rd_data (hcmd_prp_rd_data),
.hcmd_nlb_wr1_en (hcmd_nlb_wr1_en),
.hcmd_nlb_wr1_addr (hcmd_nlb_wr1_addr),
.hcmd_nlb_wr1_data (hcmd_nlb_wr1_data),
.hcmd_nlb_wr1_rdy_n (hcmd_nlb_wr1_rdy_n),
.hcmd_nlb_rd_addr (hcmd_nlb_rd_addr),
.hcmd_nlb_rd_data (hcmd_nlb_rd_data),
.dev_rx_cmd_wr_en (dev_rx_cmd_wr_en),
.dev_rx_cmd_wr_data (dev_rx_cmd_wr_data),
.dev_rx_cmd_full_n (dev_rx_cmd_full_n),
.dev_tx_cmd_wr_en (dev_tx_cmd_wr_en),
.dev_tx_cmd_wr_data (dev_tx_cmd_wr_data),
.dev_tx_cmd_full_n (dev_tx_cmd_full_n),
.tx_prp_mrd_req (tx_prp_mrd_req),
.tx_prp_mrd_tag (tx_prp_mrd_tag),
.tx_prp_mrd_len (tx_prp_mrd_len),
.tx_prp_mrd_addr (tx_prp_mrd_addr),
.tx_prp_mrd_req_ack (tx_prp_mrd_req_ack),
.cpld_prp_fifo_tag (cpld_prp_fifo_tag),
.cpld_prp_fifo_wr_data (cpld_prp_fifo_wr_data),
.cpld_prp_fifo_wr_en (cpld_prp_fifo_wr_en),
.cpld_prp_fifo_tag_last (cpld_prp_fifo_tag_last),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.hcmd_cq_wr0_en (hcmd_cq_wr0_en),
.hcmd_cq_wr0_data0 (hcmd_cq_wr0_data0),
.hcmd_cq_wr0_data1 (hcmd_cq_wr0_data1),
.hcmd_cq_wr0_rdy_n (hcmd_cq_wr0_rdy_n),
.cpu_bus_clk (cpu_bus_clk),
.cpu_bus_rst_n (cpu_bus_rst_n),
.dma_cmd_wr_en (dma_cmd_wr_en),
.dma_cmd_wr_data0 (dma_cmd_wr_data0),
.dma_cmd_wr_data1 (dma_cmd_wr_data1),
.dma_cmd_wr_rdy_n (dma_cmd_wr_rdy_n),
.dma_rx_direct_done_cnt (dma_rx_direct_done_cnt),
.dma_tx_direct_done_cnt (dma_tx_direct_done_cnt),
.dma_rx_done_cnt (dma_rx_done_cnt),
.dma_tx_done_cnt (dma_tx_done_cnt),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.dma_rx_done_wr_en (dma_rx_done_wr_en),
.dma_rx_done_wr_data (dma_rx_done_wr_data),
.dma_rx_done_wr_rdy_n (dma_rx_done_wr_rdy_n)
);
pcie_rx_dma
pcie_rx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_read_req_size (pcie_max_read_req_size),
.pcie_rx_cmd_wr_en (w_pcie_rx_cmd_wr_en),
.pcie_rx_cmd_wr_data (w_pcie_rx_cmd_wr_data),
.pcie_rx_cmd_full_n (w_pcie_rx_cmd_full_n),
.tx_dma_mrd_req (tx_dma_mrd_req),
.tx_dma_mrd_tag (tx_dma_mrd_tag),
.tx_dma_mrd_len (tx_dma_mrd_len),
.tx_dma_mrd_addr (tx_dma_mrd_addr),
.tx_dma_mrd_req_ack (tx_dma_mrd_req_ack),
.cpld_dma_fifo_tag (cpld_dma_fifo_tag),
.cpld_dma_fifo_wr_data (cpld_dma_fifo_wr_data),
.cpld_dma_fifo_wr_en (cpld_dma_fifo_wr_en),
.cpld_dma_fifo_tag_last (cpld_dma_fifo_tag_last),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_rx_fifo_rd_en (pcie_rx_fifo_rd_en),
.pcie_rx_fifo_rd_data (pcie_rx_fifo_rd_data),
.pcie_rx_fifo_free_en (pcie_rx_fifo_free_en),
.pcie_rx_fifo_free_len (pcie_rx_fifo_free_len),
.pcie_rx_fifo_empty_n (pcie_rx_fifo_empty_n)
);
pcie_tx_dma
pcie_tx_dma_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_max_payload_size (pcie_max_payload_size),
.pcie_tx_cmd_wr_en (w_pcie_tx_cmd_wr_en),
.pcie_tx_cmd_wr_data (w_pcie_tx_cmd_wr_data),
.pcie_tx_cmd_full_n (w_pcie_tx_cmd_full_n),
.tx_dma_mwr_req (tx_dma_mwr_req),
.tx_dma_mwr_tag (tx_dma_mwr_tag),
.tx_dma_mwr_len (tx_dma_mwr_len),
.tx_dma_mwr_addr (tx_dma_mwr_addr),
.tx_dma_mwr_req_ack (tx_dma_mwr_req_ack),
.tx_dma_mwr_data_last (tx_dma_mwr_data_last),
.pcie_tx_dma_fifo_rd_en (pcie_tx_dma_fifo_rd_en),
.pcie_tx_dma_fifo_rd_data (pcie_tx_dma_fifo_rd_data),
.dma_tx_done_wr_en (w_dma_tx_done_wr_en),
.dma_tx_done_wr_data (w_dma_tx_done_wr_data),
.dma_tx_done_wr_rdy_n (w_dma_tx_done_wr_rdy_n),
.dma_bus_clk (dma_bus_clk),
.dma_bus_rst_n (dma_bus_rst_n),
.pcie_tx_fifo_alloc_en (pcie_tx_fifo_alloc_en),
.pcie_tx_fifo_alloc_len (pcie_tx_fifo_alloc_len),
.pcie_tx_fifo_wr_en (pcie_tx_fifo_wr_en),
.pcie_tx_fifo_wr_data (pcie_tx_fifo_wr_data),
.pcie_tx_fifo_full_n (pcie_tx_fifo_full_n)
);
endmodule |
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// button_debounce.v
// Created: 4.5.2012
// Modified: 4.5.2012
//
// Testbench for button_debounce.v.
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_button_debounce();
parameter
CLK_FREQUENCY = 66000000,
DEBOUNCE_HZ = 2;
reg clk, reset_n, button;
wire debounce;
button_debounce
#(
.CLK_FREQUENCY(CLK_FREQUENCY),
.DEBOUNCE_HZ(DEBOUNCE_HZ)
)
button_debounce
(
.clk(clk),
.reset_n(reset_n),
.button(button),
.debounce(debounce)
);
initial begin
clk = 1'bx; reset_n = 1'bx; button = 1'bx;
#10 reset_n = 1;
#10 reset_n = 0; clk = 0;
#10 reset_n = 1;
#10 button = 0;
end
always
#5 clk = ~clk;
always begin
#100 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
#0.1 button = ~button;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
`define SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
/**
* sdfbbn: Scan delay flop, inverted set, inverted reset, inverted
* clock, complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__sdfbbn (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
input SET_B ,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK_N ,
//# {{power|Power}}
input VPB ,
input VPWR ,
input VGND ,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFBBN_PP_SYMBOL_V
|
//
// Generated by Bluespec Compiler, version 2019.05.beta2 (build a88bf40db, 2019-05-24)
//
//
//
//
// Ports:
// Name I/O size props
// RDY_reset O 1
// RDY_set_verbosity O 1 const
// v_from_masters_0_awready O 1 reg
// v_from_masters_0_wready O 1 reg
// v_from_masters_0_bvalid O 1 reg
// v_from_masters_0_bid O 16 reg
// v_from_masters_0_bresp O 2 reg
// v_from_masters_0_arready O 1 reg
// v_from_masters_0_rvalid O 1 reg
// v_from_masters_0_rid O 16 reg
// v_from_masters_0_rdata O 64 reg
// v_from_masters_0_rresp O 2 reg
// v_from_masters_0_rlast O 1 reg
// v_to_slaves_0_awvalid O 1 reg
// v_to_slaves_0_awid O 16 reg
// v_to_slaves_0_awaddr O 64 reg
// v_to_slaves_0_awlen O 8 reg
// v_to_slaves_0_awsize O 3 reg
// v_to_slaves_0_awburst O 2 reg
// v_to_slaves_0_awlock O 1 reg
// v_to_slaves_0_awcache O 4 reg
// v_to_slaves_0_awprot O 3 reg
// v_to_slaves_0_awqos O 4 reg
// v_to_slaves_0_awregion O 4 reg
// v_to_slaves_0_wvalid O 1 reg
// v_to_slaves_0_wdata O 64 reg
// v_to_slaves_0_wstrb O 8 reg
// v_to_slaves_0_wlast O 1 reg
// v_to_slaves_0_bready O 1 reg
// v_to_slaves_0_arvalid O 1 reg
// v_to_slaves_0_arid O 16 reg
// v_to_slaves_0_araddr O 64 reg
// v_to_slaves_0_arlen O 8 reg
// v_to_slaves_0_arsize O 3 reg
// v_to_slaves_0_arburst O 2 reg
// v_to_slaves_0_arlock O 1 reg
// v_to_slaves_0_arcache O 4 reg
// v_to_slaves_0_arprot O 3 reg
// v_to_slaves_0_arqos O 4 reg
// v_to_slaves_0_arregion O 4 reg
// v_to_slaves_0_rready O 1 reg
// v_to_slaves_1_awvalid O 1 reg
// v_to_slaves_1_awid O 16 reg
// v_to_slaves_1_awaddr O 64 reg
// v_to_slaves_1_awlen O 8 reg
// v_to_slaves_1_awsize O 3 reg
// v_to_slaves_1_awburst O 2 reg
// v_to_slaves_1_awlock O 1 reg
// v_to_slaves_1_awcache O 4 reg
// v_to_slaves_1_awprot O 3 reg
// v_to_slaves_1_awqos O 4 reg
// v_to_slaves_1_awregion O 4 reg
// v_to_slaves_1_wvalid O 1 reg
// v_to_slaves_1_wdata O 64 reg
// v_to_slaves_1_wstrb O 8 reg
// v_to_slaves_1_wlast O 1 reg
// v_to_slaves_1_bready O 1 reg
// v_to_slaves_1_arvalid O 1 reg
// v_to_slaves_1_arid O 16 reg
// v_to_slaves_1_araddr O 64 reg
// v_to_slaves_1_arlen O 8 reg
// v_to_slaves_1_arsize O 3 reg
// v_to_slaves_1_arburst O 2 reg
// v_to_slaves_1_arlock O 1 reg
// v_to_slaves_1_arcache O 4 reg
// v_to_slaves_1_arprot O 3 reg
// v_to_slaves_1_arqos O 4 reg
// v_to_slaves_1_arregion O 4 reg
// v_to_slaves_1_rready O 1 reg
// v_to_slaves_2_awvalid O 1 reg
// v_to_slaves_2_awid O 16 reg
// v_to_slaves_2_awaddr O 64 reg
// v_to_slaves_2_awlen O 8 reg
// v_to_slaves_2_awsize O 3 reg
// v_to_slaves_2_awburst O 2 reg
// v_to_slaves_2_awlock O 1 reg
// v_to_slaves_2_awcache O 4 reg
// v_to_slaves_2_awprot O 3 reg
// v_to_slaves_2_awqos O 4 reg
// v_to_slaves_2_awregion O 4 reg
// v_to_slaves_2_wvalid O 1 reg
// v_to_slaves_2_wdata O 64 reg
// v_to_slaves_2_wstrb O 8 reg
// v_to_slaves_2_wlast O 1 reg
// v_to_slaves_2_bready O 1 reg
// v_to_slaves_2_arvalid O 1 reg
// v_to_slaves_2_arid O 16 reg
// v_to_slaves_2_araddr O 64 reg
// v_to_slaves_2_arlen O 8 reg
// v_to_slaves_2_arsize O 3 reg
// v_to_slaves_2_arburst O 2 reg
// v_to_slaves_2_arlock O 1 reg
// v_to_slaves_2_arcache O 4 reg
// v_to_slaves_2_arprot O 3 reg
// v_to_slaves_2_arqos O 4 reg
// v_to_slaves_2_arregion O 4 reg
// v_to_slaves_2_rready O 1 reg
// CLK I 1 clock
// RST_N I 1 reset
// set_verbosity_verbosity I 4 reg
// v_from_masters_0_awvalid I 1
// v_from_masters_0_awid I 16 reg
// v_from_masters_0_awaddr I 64 reg
// v_from_masters_0_awlen I 8 reg
// v_from_masters_0_awsize I 3 reg
// v_from_masters_0_awburst I 2 reg
// v_from_masters_0_awlock I 1 reg
// v_from_masters_0_awcache I 4 reg
// v_from_masters_0_awprot I 3 reg
// v_from_masters_0_awqos I 4 reg
// v_from_masters_0_awregion I 4 reg
// v_from_masters_0_wvalid I 1
// v_from_masters_0_wdata I 64 reg
// v_from_masters_0_wstrb I 8 reg
// v_from_masters_0_wlast I 1 reg
// v_from_masters_0_bready I 1
// v_from_masters_0_arvalid I 1
// v_from_masters_0_arid I 16 reg
// v_from_masters_0_araddr I 64 reg
// v_from_masters_0_arlen I 8 reg
// v_from_masters_0_arsize I 3 reg
// v_from_masters_0_arburst I 2 reg
// v_from_masters_0_arlock I 1 reg
// v_from_masters_0_arcache I 4 reg
// v_from_masters_0_arprot I 3 reg
// v_from_masters_0_arqos I 4 reg
// v_from_masters_0_arregion I 4 reg
// v_from_masters_0_rready I 1
// v_to_slaves_0_awready I 1
// v_to_slaves_0_wready I 1
// v_to_slaves_0_bvalid I 1
// v_to_slaves_0_bid I 16 reg
// v_to_slaves_0_bresp I 2 reg
// v_to_slaves_0_arready I 1
// v_to_slaves_0_rvalid I 1
// v_to_slaves_0_rid I 16 reg
// v_to_slaves_0_rdata I 64 reg
// v_to_slaves_0_rresp I 2 reg
// v_to_slaves_0_rlast I 1 reg
// v_to_slaves_1_awready I 1
// v_to_slaves_1_wready I 1
// v_to_slaves_1_bvalid I 1
// v_to_slaves_1_bid I 16 reg
// v_to_slaves_1_bresp I 2 reg
// v_to_slaves_1_arready I 1
// v_to_slaves_1_rvalid I 1
// v_to_slaves_1_rid I 16 reg
// v_to_slaves_1_rdata I 64 reg
// v_to_slaves_1_rresp I 2 reg
// v_to_slaves_1_rlast I 1 reg
// v_to_slaves_2_awready I 1
// v_to_slaves_2_wready I 1
// v_to_slaves_2_bvalid I 1
// v_to_slaves_2_bid I 16 reg
// v_to_slaves_2_bresp I 2 reg
// v_to_slaves_2_arready I 1
// v_to_slaves_2_rvalid I 1
// v_to_slaves_2_rid I 16 reg
// v_to_slaves_2_rdata I 64 reg
// v_to_slaves_2_rresp I 2 reg
// v_to_slaves_2_rlast I 1 reg
// EN_reset I 1
// EN_set_verbosity I 1
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkFabric_1x3(CLK,
RST_N,
EN_reset,
RDY_reset,
set_verbosity_verbosity,
EN_set_verbosity,
RDY_set_verbosity,
v_from_masters_0_awvalid,
v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion,
v_from_masters_0_awready,
v_from_masters_0_wvalid,
v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast,
v_from_masters_0_wready,
v_from_masters_0_bvalid,
v_from_masters_0_bid,
v_from_masters_0_bresp,
v_from_masters_0_bready,
v_from_masters_0_arvalid,
v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion,
v_from_masters_0_arready,
v_from_masters_0_rvalid,
v_from_masters_0_rid,
v_from_masters_0_rdata,
v_from_masters_0_rresp,
v_from_masters_0_rlast,
v_from_masters_0_rready,
v_to_slaves_0_awvalid,
v_to_slaves_0_awid,
v_to_slaves_0_awaddr,
v_to_slaves_0_awlen,
v_to_slaves_0_awsize,
v_to_slaves_0_awburst,
v_to_slaves_0_awlock,
v_to_slaves_0_awcache,
v_to_slaves_0_awprot,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_0_awready,
v_to_slaves_0_wvalid,
v_to_slaves_0_wdata,
v_to_slaves_0_wstrb,
v_to_slaves_0_wlast,
v_to_slaves_0_wready,
v_to_slaves_0_bvalid,
v_to_slaves_0_bid,
v_to_slaves_0_bresp,
v_to_slaves_0_bready,
v_to_slaves_0_arvalid,
v_to_slaves_0_arid,
v_to_slaves_0_araddr,
v_to_slaves_0_arlen,
v_to_slaves_0_arsize,
v_to_slaves_0_arburst,
v_to_slaves_0_arlock,
v_to_slaves_0_arcache,
v_to_slaves_0_arprot,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_arready,
v_to_slaves_0_rvalid,
v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast,
v_to_slaves_0_rready,
v_to_slaves_1_awvalid,
v_to_slaves_1_awid,
v_to_slaves_1_awaddr,
v_to_slaves_1_awlen,
v_to_slaves_1_awsize,
v_to_slaves_1_awburst,
v_to_slaves_1_awlock,
v_to_slaves_1_awcache,
v_to_slaves_1_awprot,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_1_awready,
v_to_slaves_1_wvalid,
v_to_slaves_1_wdata,
v_to_slaves_1_wstrb,
v_to_slaves_1_wlast,
v_to_slaves_1_wready,
v_to_slaves_1_bvalid,
v_to_slaves_1_bid,
v_to_slaves_1_bresp,
v_to_slaves_1_bready,
v_to_slaves_1_arvalid,
v_to_slaves_1_arid,
v_to_slaves_1_araddr,
v_to_slaves_1_arlen,
v_to_slaves_1_arsize,
v_to_slaves_1_arburst,
v_to_slaves_1_arlock,
v_to_slaves_1_arcache,
v_to_slaves_1_arprot,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_arready,
v_to_slaves_1_rvalid,
v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast,
v_to_slaves_1_rready,
v_to_slaves_2_awvalid,
v_to_slaves_2_awid,
v_to_slaves_2_awaddr,
v_to_slaves_2_awlen,
v_to_slaves_2_awsize,
v_to_slaves_2_awburst,
v_to_slaves_2_awlock,
v_to_slaves_2_awcache,
v_to_slaves_2_awprot,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion,
v_to_slaves_2_awready,
v_to_slaves_2_wvalid,
v_to_slaves_2_wdata,
v_to_slaves_2_wstrb,
v_to_slaves_2_wlast,
v_to_slaves_2_wready,
v_to_slaves_2_bvalid,
v_to_slaves_2_bid,
v_to_slaves_2_bresp,
v_to_slaves_2_bready,
v_to_slaves_2_arvalid,
v_to_slaves_2_arid,
v_to_slaves_2_araddr,
v_to_slaves_2_arlen,
v_to_slaves_2_arsize,
v_to_slaves_2_arburst,
v_to_slaves_2_arlock,
v_to_slaves_2_arcache,
v_to_slaves_2_arprot,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_arready,
v_to_slaves_2_rvalid,
v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast,
v_to_slaves_2_rready);
input CLK;
input RST_N;
// action method reset
input EN_reset;
output RDY_reset;
// action method set_verbosity
input [3 : 0] set_verbosity_verbosity;
input EN_set_verbosity;
output RDY_set_verbosity;
// action method v_from_masters_0_m_awvalid
input v_from_masters_0_awvalid;
input [15 : 0] v_from_masters_0_awid;
input [63 : 0] v_from_masters_0_awaddr;
input [7 : 0] v_from_masters_0_awlen;
input [2 : 0] v_from_masters_0_awsize;
input [1 : 0] v_from_masters_0_awburst;
input v_from_masters_0_awlock;
input [3 : 0] v_from_masters_0_awcache;
input [2 : 0] v_from_masters_0_awprot;
input [3 : 0] v_from_masters_0_awqos;
input [3 : 0] v_from_masters_0_awregion;
// value method v_from_masters_0_m_awready
output v_from_masters_0_awready;
// action method v_from_masters_0_m_wvalid
input v_from_masters_0_wvalid;
input [63 : 0] v_from_masters_0_wdata;
input [7 : 0] v_from_masters_0_wstrb;
input v_from_masters_0_wlast;
// value method v_from_masters_0_m_wready
output v_from_masters_0_wready;
// value method v_from_masters_0_m_bvalid
output v_from_masters_0_bvalid;
// value method v_from_masters_0_m_bid
output [15 : 0] v_from_masters_0_bid;
// value method v_from_masters_0_m_bresp
output [1 : 0] v_from_masters_0_bresp;
// value method v_from_masters_0_m_buser
// action method v_from_masters_0_m_bready
input v_from_masters_0_bready;
// action method v_from_masters_0_m_arvalid
input v_from_masters_0_arvalid;
input [15 : 0] v_from_masters_0_arid;
input [63 : 0] v_from_masters_0_araddr;
input [7 : 0] v_from_masters_0_arlen;
input [2 : 0] v_from_masters_0_arsize;
input [1 : 0] v_from_masters_0_arburst;
input v_from_masters_0_arlock;
input [3 : 0] v_from_masters_0_arcache;
input [2 : 0] v_from_masters_0_arprot;
input [3 : 0] v_from_masters_0_arqos;
input [3 : 0] v_from_masters_0_arregion;
// value method v_from_masters_0_m_arready
output v_from_masters_0_arready;
// value method v_from_masters_0_m_rvalid
output v_from_masters_0_rvalid;
// value method v_from_masters_0_m_rid
output [15 : 0] v_from_masters_0_rid;
// value method v_from_masters_0_m_rdata
output [63 : 0] v_from_masters_0_rdata;
// value method v_from_masters_0_m_rresp
output [1 : 0] v_from_masters_0_rresp;
// value method v_from_masters_0_m_rlast
output v_from_masters_0_rlast;
// value method v_from_masters_0_m_ruser
// action method v_from_masters_0_m_rready
input v_from_masters_0_rready;
// value method v_to_slaves_0_m_awvalid
output v_to_slaves_0_awvalid;
// value method v_to_slaves_0_m_awid
output [15 : 0] v_to_slaves_0_awid;
// value method v_to_slaves_0_m_awaddr
output [63 : 0] v_to_slaves_0_awaddr;
// value method v_to_slaves_0_m_awlen
output [7 : 0] v_to_slaves_0_awlen;
// value method v_to_slaves_0_m_awsize
output [2 : 0] v_to_slaves_0_awsize;
// value method v_to_slaves_0_m_awburst
output [1 : 0] v_to_slaves_0_awburst;
// value method v_to_slaves_0_m_awlock
output v_to_slaves_0_awlock;
// value method v_to_slaves_0_m_awcache
output [3 : 0] v_to_slaves_0_awcache;
// value method v_to_slaves_0_m_awprot
output [2 : 0] v_to_slaves_0_awprot;
// value method v_to_slaves_0_m_awqos
output [3 : 0] v_to_slaves_0_awqos;
// value method v_to_slaves_0_m_awregion
output [3 : 0] v_to_slaves_0_awregion;
// value method v_to_slaves_0_m_awuser
// action method v_to_slaves_0_m_awready
input v_to_slaves_0_awready;
// value method v_to_slaves_0_m_wvalid
output v_to_slaves_0_wvalid;
// value method v_to_slaves_0_m_wdata
output [63 : 0] v_to_slaves_0_wdata;
// value method v_to_slaves_0_m_wstrb
output [7 : 0] v_to_slaves_0_wstrb;
// value method v_to_slaves_0_m_wlast
output v_to_slaves_0_wlast;
// value method v_to_slaves_0_m_wuser
// action method v_to_slaves_0_m_wready
input v_to_slaves_0_wready;
// action method v_to_slaves_0_m_bvalid
input v_to_slaves_0_bvalid;
input [15 : 0] v_to_slaves_0_bid;
input [1 : 0] v_to_slaves_0_bresp;
// value method v_to_slaves_0_m_bready
output v_to_slaves_0_bready;
// value method v_to_slaves_0_m_arvalid
output v_to_slaves_0_arvalid;
// value method v_to_slaves_0_m_arid
output [15 : 0] v_to_slaves_0_arid;
// value method v_to_slaves_0_m_araddr
output [63 : 0] v_to_slaves_0_araddr;
// value method v_to_slaves_0_m_arlen
output [7 : 0] v_to_slaves_0_arlen;
// value method v_to_slaves_0_m_arsize
output [2 : 0] v_to_slaves_0_arsize;
// value method v_to_slaves_0_m_arburst
output [1 : 0] v_to_slaves_0_arburst;
// value method v_to_slaves_0_m_arlock
output v_to_slaves_0_arlock;
// value method v_to_slaves_0_m_arcache
output [3 : 0] v_to_slaves_0_arcache;
// value method v_to_slaves_0_m_arprot
output [2 : 0] v_to_slaves_0_arprot;
// value method v_to_slaves_0_m_arqos
output [3 : 0] v_to_slaves_0_arqos;
// value method v_to_slaves_0_m_arregion
output [3 : 0] v_to_slaves_0_arregion;
// value method v_to_slaves_0_m_aruser
// action method v_to_slaves_0_m_arready
input v_to_slaves_0_arready;
// action method v_to_slaves_0_m_rvalid
input v_to_slaves_0_rvalid;
input [15 : 0] v_to_slaves_0_rid;
input [63 : 0] v_to_slaves_0_rdata;
input [1 : 0] v_to_slaves_0_rresp;
input v_to_slaves_0_rlast;
// value method v_to_slaves_0_m_rready
output v_to_slaves_0_rready;
// value method v_to_slaves_1_m_awvalid
output v_to_slaves_1_awvalid;
// value method v_to_slaves_1_m_awid
output [15 : 0] v_to_slaves_1_awid;
// value method v_to_slaves_1_m_awaddr
output [63 : 0] v_to_slaves_1_awaddr;
// value method v_to_slaves_1_m_awlen
output [7 : 0] v_to_slaves_1_awlen;
// value method v_to_slaves_1_m_awsize
output [2 : 0] v_to_slaves_1_awsize;
// value method v_to_slaves_1_m_awburst
output [1 : 0] v_to_slaves_1_awburst;
// value method v_to_slaves_1_m_awlock
output v_to_slaves_1_awlock;
// value method v_to_slaves_1_m_awcache
output [3 : 0] v_to_slaves_1_awcache;
// value method v_to_slaves_1_m_awprot
output [2 : 0] v_to_slaves_1_awprot;
// value method v_to_slaves_1_m_awqos
output [3 : 0] v_to_slaves_1_awqos;
// value method v_to_slaves_1_m_awregion
output [3 : 0] v_to_slaves_1_awregion;
// value method v_to_slaves_1_m_awuser
// action method v_to_slaves_1_m_awready
input v_to_slaves_1_awready;
// value method v_to_slaves_1_m_wvalid
output v_to_slaves_1_wvalid;
// value method v_to_slaves_1_m_wdata
output [63 : 0] v_to_slaves_1_wdata;
// value method v_to_slaves_1_m_wstrb
output [7 : 0] v_to_slaves_1_wstrb;
// value method v_to_slaves_1_m_wlast
output v_to_slaves_1_wlast;
// value method v_to_slaves_1_m_wuser
// action method v_to_slaves_1_m_wready
input v_to_slaves_1_wready;
// action method v_to_slaves_1_m_bvalid
input v_to_slaves_1_bvalid;
input [15 : 0] v_to_slaves_1_bid;
input [1 : 0] v_to_slaves_1_bresp;
// value method v_to_slaves_1_m_bready
output v_to_slaves_1_bready;
// value method v_to_slaves_1_m_arvalid
output v_to_slaves_1_arvalid;
// value method v_to_slaves_1_m_arid
output [15 : 0] v_to_slaves_1_arid;
// value method v_to_slaves_1_m_araddr
output [63 : 0] v_to_slaves_1_araddr;
// value method v_to_slaves_1_m_arlen
output [7 : 0] v_to_slaves_1_arlen;
// value method v_to_slaves_1_m_arsize
output [2 : 0] v_to_slaves_1_arsize;
// value method v_to_slaves_1_m_arburst
output [1 : 0] v_to_slaves_1_arburst;
// value method v_to_slaves_1_m_arlock
output v_to_slaves_1_arlock;
// value method v_to_slaves_1_m_arcache
output [3 : 0] v_to_slaves_1_arcache;
// value method v_to_slaves_1_m_arprot
output [2 : 0] v_to_slaves_1_arprot;
// value method v_to_slaves_1_m_arqos
output [3 : 0] v_to_slaves_1_arqos;
// value method v_to_slaves_1_m_arregion
output [3 : 0] v_to_slaves_1_arregion;
// value method v_to_slaves_1_m_aruser
// action method v_to_slaves_1_m_arready
input v_to_slaves_1_arready;
// action method v_to_slaves_1_m_rvalid
input v_to_slaves_1_rvalid;
input [15 : 0] v_to_slaves_1_rid;
input [63 : 0] v_to_slaves_1_rdata;
input [1 : 0] v_to_slaves_1_rresp;
input v_to_slaves_1_rlast;
// value method v_to_slaves_1_m_rready
output v_to_slaves_1_rready;
// value method v_to_slaves_2_m_awvalid
output v_to_slaves_2_awvalid;
// value method v_to_slaves_2_m_awid
output [15 : 0] v_to_slaves_2_awid;
// value method v_to_slaves_2_m_awaddr
output [63 : 0] v_to_slaves_2_awaddr;
// value method v_to_slaves_2_m_awlen
output [7 : 0] v_to_slaves_2_awlen;
// value method v_to_slaves_2_m_awsize
output [2 : 0] v_to_slaves_2_awsize;
// value method v_to_slaves_2_m_awburst
output [1 : 0] v_to_slaves_2_awburst;
// value method v_to_slaves_2_m_awlock
output v_to_slaves_2_awlock;
// value method v_to_slaves_2_m_awcache
output [3 : 0] v_to_slaves_2_awcache;
// value method v_to_slaves_2_m_awprot
output [2 : 0] v_to_slaves_2_awprot;
// value method v_to_slaves_2_m_awqos
output [3 : 0] v_to_slaves_2_awqos;
// value method v_to_slaves_2_m_awregion
output [3 : 0] v_to_slaves_2_awregion;
// value method v_to_slaves_2_m_awuser
// action method v_to_slaves_2_m_awready
input v_to_slaves_2_awready;
// value method v_to_slaves_2_m_wvalid
output v_to_slaves_2_wvalid;
// value method v_to_slaves_2_m_wdata
output [63 : 0] v_to_slaves_2_wdata;
// value method v_to_slaves_2_m_wstrb
output [7 : 0] v_to_slaves_2_wstrb;
// value method v_to_slaves_2_m_wlast
output v_to_slaves_2_wlast;
// value method v_to_slaves_2_m_wuser
// action method v_to_slaves_2_m_wready
input v_to_slaves_2_wready;
// action method v_to_slaves_2_m_bvalid
input v_to_slaves_2_bvalid;
input [15 : 0] v_to_slaves_2_bid;
input [1 : 0] v_to_slaves_2_bresp;
// value method v_to_slaves_2_m_bready
output v_to_slaves_2_bready;
// value method v_to_slaves_2_m_arvalid
output v_to_slaves_2_arvalid;
// value method v_to_slaves_2_m_arid
output [15 : 0] v_to_slaves_2_arid;
// value method v_to_slaves_2_m_araddr
output [63 : 0] v_to_slaves_2_araddr;
// value method v_to_slaves_2_m_arlen
output [7 : 0] v_to_slaves_2_arlen;
// value method v_to_slaves_2_m_arsize
output [2 : 0] v_to_slaves_2_arsize;
// value method v_to_slaves_2_m_arburst
output [1 : 0] v_to_slaves_2_arburst;
// value method v_to_slaves_2_m_arlock
output v_to_slaves_2_arlock;
// value method v_to_slaves_2_m_arcache
output [3 : 0] v_to_slaves_2_arcache;
// value method v_to_slaves_2_m_arprot
output [2 : 0] v_to_slaves_2_arprot;
// value method v_to_slaves_2_m_arqos
output [3 : 0] v_to_slaves_2_arqos;
// value method v_to_slaves_2_m_arregion
output [3 : 0] v_to_slaves_2_arregion;
// value method v_to_slaves_2_m_aruser
// action method v_to_slaves_2_m_arready
input v_to_slaves_2_arready;
// action method v_to_slaves_2_m_rvalid
input v_to_slaves_2_rvalid;
input [15 : 0] v_to_slaves_2_rid;
input [63 : 0] v_to_slaves_2_rdata;
input [1 : 0] v_to_slaves_2_rresp;
input v_to_slaves_2_rlast;
// value method v_to_slaves_2_m_rready
output v_to_slaves_2_rready;
// signals for module outputs
wire [63 : 0] v_from_masters_0_rdata,
v_to_slaves_0_araddr,
v_to_slaves_0_awaddr,
v_to_slaves_0_wdata,
v_to_slaves_1_araddr,
v_to_slaves_1_awaddr,
v_to_slaves_1_wdata,
v_to_slaves_2_araddr,
v_to_slaves_2_awaddr,
v_to_slaves_2_wdata;
wire [15 : 0] v_from_masters_0_bid,
v_from_masters_0_rid,
v_to_slaves_0_arid,
v_to_slaves_0_awid,
v_to_slaves_1_arid,
v_to_slaves_1_awid,
v_to_slaves_2_arid,
v_to_slaves_2_awid;
wire [7 : 0] v_to_slaves_0_arlen,
v_to_slaves_0_awlen,
v_to_slaves_0_wstrb,
v_to_slaves_1_arlen,
v_to_slaves_1_awlen,
v_to_slaves_1_wstrb,
v_to_slaves_2_arlen,
v_to_slaves_2_awlen,
v_to_slaves_2_wstrb;
wire [3 : 0] v_to_slaves_0_arcache,
v_to_slaves_0_arqos,
v_to_slaves_0_arregion,
v_to_slaves_0_awcache,
v_to_slaves_0_awqos,
v_to_slaves_0_awregion,
v_to_slaves_1_arcache,
v_to_slaves_1_arqos,
v_to_slaves_1_arregion,
v_to_slaves_1_awcache,
v_to_slaves_1_awqos,
v_to_slaves_1_awregion,
v_to_slaves_2_arcache,
v_to_slaves_2_arqos,
v_to_slaves_2_arregion,
v_to_slaves_2_awcache,
v_to_slaves_2_awqos,
v_to_slaves_2_awregion;
wire [2 : 0] v_to_slaves_0_arprot,
v_to_slaves_0_arsize,
v_to_slaves_0_awprot,
v_to_slaves_0_awsize,
v_to_slaves_1_arprot,
v_to_slaves_1_arsize,
v_to_slaves_1_awprot,
v_to_slaves_1_awsize,
v_to_slaves_2_arprot,
v_to_slaves_2_arsize,
v_to_slaves_2_awprot,
v_to_slaves_2_awsize;
wire [1 : 0] v_from_masters_0_bresp,
v_from_masters_0_rresp,
v_to_slaves_0_arburst,
v_to_slaves_0_awburst,
v_to_slaves_1_arburst,
v_to_slaves_1_awburst,
v_to_slaves_2_arburst,
v_to_slaves_2_awburst;
wire RDY_reset,
RDY_set_verbosity,
v_from_masters_0_arready,
v_from_masters_0_awready,
v_from_masters_0_bvalid,
v_from_masters_0_rlast,
v_from_masters_0_rvalid,
v_from_masters_0_wready,
v_to_slaves_0_arlock,
v_to_slaves_0_arvalid,
v_to_slaves_0_awlock,
v_to_slaves_0_awvalid,
v_to_slaves_0_bready,
v_to_slaves_0_rready,
v_to_slaves_0_wlast,
v_to_slaves_0_wvalid,
v_to_slaves_1_arlock,
v_to_slaves_1_arvalid,
v_to_slaves_1_awlock,
v_to_slaves_1_awvalid,
v_to_slaves_1_bready,
v_to_slaves_1_rready,
v_to_slaves_1_wlast,
v_to_slaves_1_wvalid,
v_to_slaves_2_arlock,
v_to_slaves_2_arvalid,
v_to_slaves_2_awlock,
v_to_slaves_2_awvalid,
v_to_slaves_2_bready,
v_to_slaves_2_rready,
v_to_slaves_2_wlast,
v_to_slaves_2_wvalid;
// register fabric_cfg_verbosity
reg [3 : 0] fabric_cfg_verbosity;
wire [3 : 0] fabric_cfg_verbosity$D_IN;
wire fabric_cfg_verbosity$EN;
// register fabric_rg_reset
reg fabric_rg_reset;
wire fabric_rg_reset$D_IN, fabric_rg_reset$EN;
// register fabric_v_rg_r_beat_count_0
reg [7 : 0] fabric_v_rg_r_beat_count_0;
wire [7 : 0] fabric_v_rg_r_beat_count_0$D_IN;
wire fabric_v_rg_r_beat_count_0$EN;
// register fabric_v_rg_r_beat_count_1
reg [7 : 0] fabric_v_rg_r_beat_count_1;
wire [7 : 0] fabric_v_rg_r_beat_count_1$D_IN;
wire fabric_v_rg_r_beat_count_1$EN;
// register fabric_v_rg_r_beat_count_2
reg [7 : 0] fabric_v_rg_r_beat_count_2;
wire [7 : 0] fabric_v_rg_r_beat_count_2$D_IN;
wire fabric_v_rg_r_beat_count_2$EN;
// register fabric_v_rg_r_err_beat_count_0
reg [7 : 0] fabric_v_rg_r_err_beat_count_0;
wire [7 : 0] fabric_v_rg_r_err_beat_count_0$D_IN;
wire fabric_v_rg_r_err_beat_count_0$EN;
// register fabric_v_rg_wd_beat_count_0
reg [7 : 0] fabric_v_rg_wd_beat_count_0;
wire [7 : 0] fabric_v_rg_wd_beat_count_0$D_IN;
wire fabric_v_rg_wd_beat_count_0$EN;
// ports of submodule fabric_v_f_rd_err_info_0
wire [23 : 0] fabric_v_f_rd_err_info_0$D_IN, fabric_v_f_rd_err_info_0$D_OUT;
wire fabric_v_f_rd_err_info_0$CLR,
fabric_v_f_rd_err_info_0$DEQ,
fabric_v_f_rd_err_info_0$EMPTY_N,
fabric_v_f_rd_err_info_0$ENQ;
// ports of submodule fabric_v_f_rd_mis_0
wire [8 : 0] fabric_v_f_rd_mis_0$D_IN, fabric_v_f_rd_mis_0$D_OUT;
wire fabric_v_f_rd_mis_0$CLR,
fabric_v_f_rd_mis_0$DEQ,
fabric_v_f_rd_mis_0$EMPTY_N,
fabric_v_f_rd_mis_0$ENQ,
fabric_v_f_rd_mis_0$FULL_N;
// ports of submodule fabric_v_f_rd_mis_1
wire [8 : 0] fabric_v_f_rd_mis_1$D_IN, fabric_v_f_rd_mis_1$D_OUT;
wire fabric_v_f_rd_mis_1$CLR,
fabric_v_f_rd_mis_1$DEQ,
fabric_v_f_rd_mis_1$EMPTY_N,
fabric_v_f_rd_mis_1$ENQ,
fabric_v_f_rd_mis_1$FULL_N;
// ports of submodule fabric_v_f_rd_mis_2
wire [8 : 0] fabric_v_f_rd_mis_2$D_IN, fabric_v_f_rd_mis_2$D_OUT;
wire fabric_v_f_rd_mis_2$CLR,
fabric_v_f_rd_mis_2$DEQ,
fabric_v_f_rd_mis_2$EMPTY_N,
fabric_v_f_rd_mis_2$ENQ,
fabric_v_f_rd_mis_2$FULL_N;
// ports of submodule fabric_v_f_rd_sjs_0
reg [1 : 0] fabric_v_f_rd_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_rd_sjs_0$D_OUT;
wire fabric_v_f_rd_sjs_0$CLR,
fabric_v_f_rd_sjs_0$DEQ,
fabric_v_f_rd_sjs_0$EMPTY_N,
fabric_v_f_rd_sjs_0$ENQ,
fabric_v_f_rd_sjs_0$FULL_N;
// ports of submodule fabric_v_f_wd_tasks_0
reg [9 : 0] fabric_v_f_wd_tasks_0$D_IN;
wire [9 : 0] fabric_v_f_wd_tasks_0$D_OUT;
wire fabric_v_f_wd_tasks_0$CLR,
fabric_v_f_wd_tasks_0$DEQ,
fabric_v_f_wd_tasks_0$EMPTY_N,
fabric_v_f_wd_tasks_0$ENQ,
fabric_v_f_wd_tasks_0$FULL_N;
// ports of submodule fabric_v_f_wr_err_info_0
wire [15 : 0] fabric_v_f_wr_err_info_0$D_IN, fabric_v_f_wr_err_info_0$D_OUT;
wire fabric_v_f_wr_err_info_0$CLR,
fabric_v_f_wr_err_info_0$DEQ,
fabric_v_f_wr_err_info_0$EMPTY_N,
fabric_v_f_wr_err_info_0$ENQ;
// ports of submodule fabric_v_f_wr_mis_0
wire fabric_v_f_wr_mis_0$CLR,
fabric_v_f_wr_mis_0$DEQ,
fabric_v_f_wr_mis_0$D_IN,
fabric_v_f_wr_mis_0$D_OUT,
fabric_v_f_wr_mis_0$EMPTY_N,
fabric_v_f_wr_mis_0$ENQ,
fabric_v_f_wr_mis_0$FULL_N;
// ports of submodule fabric_v_f_wr_mis_1
wire fabric_v_f_wr_mis_1$CLR,
fabric_v_f_wr_mis_1$DEQ,
fabric_v_f_wr_mis_1$D_IN,
fabric_v_f_wr_mis_1$D_OUT,
fabric_v_f_wr_mis_1$EMPTY_N,
fabric_v_f_wr_mis_1$ENQ,
fabric_v_f_wr_mis_1$FULL_N;
// ports of submodule fabric_v_f_wr_mis_2
wire fabric_v_f_wr_mis_2$CLR,
fabric_v_f_wr_mis_2$DEQ,
fabric_v_f_wr_mis_2$D_IN,
fabric_v_f_wr_mis_2$D_OUT,
fabric_v_f_wr_mis_2$EMPTY_N,
fabric_v_f_wr_mis_2$ENQ,
fabric_v_f_wr_mis_2$FULL_N;
// ports of submodule fabric_v_f_wr_sjs_0
reg [1 : 0] fabric_v_f_wr_sjs_0$D_IN;
wire [1 : 0] fabric_v_f_wr_sjs_0$D_OUT;
wire fabric_v_f_wr_sjs_0$CLR,
fabric_v_f_wr_sjs_0$DEQ,
fabric_v_f_wr_sjs_0$EMPTY_N,
fabric_v_f_wr_sjs_0$ENQ,
fabric_v_f_wr_sjs_0$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_rd_addr$D_IN,
fabric_xactors_from_masters_0_f_rd_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_addr$CLR,
fabric_xactors_from_masters_0_f_rd_addr$DEQ,
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_addr$ENQ,
fabric_xactors_from_masters_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_rd_data
reg [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_IN;
wire [82 : 0] fabric_xactors_from_masters_0_f_rd_data$D_OUT;
wire fabric_xactors_from_masters_0_f_rd_data$CLR,
fabric_xactors_from_masters_0_f_rd_data$DEQ,
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N,
fabric_xactors_from_masters_0_f_rd_data$ENQ,
fabric_xactors_from_masters_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_addr
wire [108 : 0] fabric_xactors_from_masters_0_f_wr_addr$D_IN,
fabric_xactors_from_masters_0_f_wr_addr$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_addr$CLR,
fabric_xactors_from_masters_0_f_wr_addr$DEQ,
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_addr$ENQ,
fabric_xactors_from_masters_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_data
wire [72 : 0] fabric_xactors_from_masters_0_f_wr_data$D_IN,
fabric_xactors_from_masters_0_f_wr_data$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_data$CLR,
fabric_xactors_from_masters_0_f_wr_data$DEQ,
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_data$ENQ,
fabric_xactors_from_masters_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_from_masters_0_f_wr_resp
reg [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_IN;
wire [17 : 0] fabric_xactors_from_masters_0_f_wr_resp$D_OUT;
wire fabric_xactors_from_masters_0_f_wr_resp$CLR,
fabric_xactors_from_masters_0_f_wr_resp$DEQ,
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N,
fabric_xactors_from_masters_0_f_wr_resp$ENQ,
fabric_xactors_from_masters_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_rd_addr$D_IN,
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_addr$CLR,
fabric_xactors_to_slaves_0_f_rd_addr$DEQ,
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_addr$ENQ,
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_0_f_rd_data$D_IN,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_rd_data$CLR,
fabric_xactors_to_slaves_0_f_rd_data$DEQ,
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_rd_data$ENQ,
fabric_xactors_to_slaves_0_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_0_f_wr_addr$D_IN,
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_addr$CLR,
fabric_xactors_to_slaves_0_f_wr_addr$DEQ,
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_addr$ENQ,
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_0_f_wr_data$D_IN,
fabric_xactors_to_slaves_0_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_data$CLR,
fabric_xactors_to_slaves_0_f_wr_data$DEQ,
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_data$ENQ,
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_0_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_0_f_wr_resp$D_IN,
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_0_f_wr_resp$CLR,
fabric_xactors_to_slaves_0_f_wr_resp$DEQ,
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_0_f_wr_resp$ENQ,
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_rd_addr$D_IN,
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_addr$CLR,
fabric_xactors_to_slaves_1_f_rd_addr$DEQ,
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_addr$ENQ,
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_1_f_rd_data$D_IN,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_rd_data$CLR,
fabric_xactors_to_slaves_1_f_rd_data$DEQ,
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_rd_data$ENQ,
fabric_xactors_to_slaves_1_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_1_f_wr_addr$D_IN,
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_addr$CLR,
fabric_xactors_to_slaves_1_f_wr_addr$DEQ,
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_addr$ENQ,
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_1_f_wr_data$D_IN,
fabric_xactors_to_slaves_1_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_data$CLR,
fabric_xactors_to_slaves_1_f_wr_data$DEQ,
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_data$ENQ,
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_1_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_1_f_wr_resp$D_IN,
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_1_f_wr_resp$CLR,
fabric_xactors_to_slaves_1_f_wr_resp$DEQ,
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_1_f_wr_resp$ENQ,
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_rd_addr$D_IN,
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_addr$CLR,
fabric_xactors_to_slaves_2_f_rd_addr$DEQ,
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_addr$ENQ,
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_rd_data
wire [82 : 0] fabric_xactors_to_slaves_2_f_rd_data$D_IN,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_rd_data$CLR,
fabric_xactors_to_slaves_2_f_rd_data$DEQ,
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_rd_data$ENQ,
fabric_xactors_to_slaves_2_f_rd_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_addr
wire [108 : 0] fabric_xactors_to_slaves_2_f_wr_addr$D_IN,
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_addr$CLR,
fabric_xactors_to_slaves_2_f_wr_addr$DEQ,
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_addr$ENQ,
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_data
wire [72 : 0] fabric_xactors_to_slaves_2_f_wr_data$D_IN,
fabric_xactors_to_slaves_2_f_wr_data$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_data$CLR,
fabric_xactors_to_slaves_2_f_wr_data$DEQ,
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_data$ENQ,
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
// ports of submodule fabric_xactors_to_slaves_2_f_wr_resp
wire [17 : 0] fabric_xactors_to_slaves_2_f_wr_resp$D_IN,
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
wire fabric_xactors_to_slaves_2_f_wr_resp$CLR,
fabric_xactors_to_slaves_2_f_wr_resp$DEQ,
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N,
fabric_xactors_to_slaves_2_f_wr_resp$ENQ,
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N;
// ports of submodule soc_map
wire [63 : 0] soc_map$m_is_IO_addr_addr,
soc_map$m_is_mem_addr_addr,
soc_map$m_is_near_mem_IO_addr_addr,
soc_map$m_near_mem_io_addr_base,
soc_map$m_near_mem_io_addr_lim,
soc_map$m_plic_addr_base,
soc_map$m_plic_addr_lim;
// rule scheduling signals
wire CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_reset,
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
CAN_FIRE_reset,
CAN_FIRE_set_verbosity,
CAN_FIRE_v_from_masters_0_m_arvalid,
CAN_FIRE_v_from_masters_0_m_awvalid,
CAN_FIRE_v_from_masters_0_m_bready,
CAN_FIRE_v_from_masters_0_m_rready,
CAN_FIRE_v_from_masters_0_m_wvalid,
CAN_FIRE_v_to_slaves_0_m_arready,
CAN_FIRE_v_to_slaves_0_m_awready,
CAN_FIRE_v_to_slaves_0_m_bvalid,
CAN_FIRE_v_to_slaves_0_m_rvalid,
CAN_FIRE_v_to_slaves_0_m_wready,
CAN_FIRE_v_to_slaves_1_m_arready,
CAN_FIRE_v_to_slaves_1_m_awready,
CAN_FIRE_v_to_slaves_1_m_bvalid,
CAN_FIRE_v_to_slaves_1_m_rvalid,
CAN_FIRE_v_to_slaves_1_m_wready,
CAN_FIRE_v_to_slaves_2_m_arready,
CAN_FIRE_v_to_slaves_2_m_awready,
CAN_FIRE_v_to_slaves_2_m_bvalid,
CAN_FIRE_v_to_slaves_2_m_rvalid,
CAN_FIRE_v_to_slaves_2_m_wready,
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_reset,
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1,
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2,
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data,
WILL_FIRE_reset,
WILL_FIRE_set_verbosity,
WILL_FIRE_v_from_masters_0_m_arvalid,
WILL_FIRE_v_from_masters_0_m_awvalid,
WILL_FIRE_v_from_masters_0_m_bready,
WILL_FIRE_v_from_masters_0_m_rready,
WILL_FIRE_v_from_masters_0_m_wvalid,
WILL_FIRE_v_to_slaves_0_m_arready,
WILL_FIRE_v_to_slaves_0_m_awready,
WILL_FIRE_v_to_slaves_0_m_bvalid,
WILL_FIRE_v_to_slaves_0_m_rvalid,
WILL_FIRE_v_to_slaves_0_m_wready,
WILL_FIRE_v_to_slaves_1_m_arready,
WILL_FIRE_v_to_slaves_1_m_awready,
WILL_FIRE_v_to_slaves_1_m_bvalid,
WILL_FIRE_v_to_slaves_1_m_rvalid,
WILL_FIRE_v_to_slaves_1_m_wready,
WILL_FIRE_v_to_slaves_2_m_arready,
WILL_FIRE_v_to_slaves_2_m_awready,
WILL_FIRE_v_to_slaves_2_m_bvalid,
WILL_FIRE_v_to_slaves_2_m_rvalid,
WILL_FIRE_v_to_slaves_2_m_wready;
// inputs to muxes for submodule ports
wire [82 : 0] MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3,
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
wire [17 : 0] MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
wire [9 : 0] MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2,
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
wire [7 : 0] MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2,
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2,
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2;
// declarations used by system tasks
// synopsys translate_off
reg [31 : 0] v__h7091;
reg [31 : 0] v__h7466;
reg [31 : 0] v__h7841;
reg [31 : 0] v__h8601;
reg [31 : 0] v__h8847;
reg [31 : 0] v__h9224;
reg [31 : 0] v__h9516;
reg [31 : 0] v__h9808;
reg [31 : 0] v__h10072;
reg [31 : 0] v__h10501;
reg [31 : 0] v__h10857;
reg [31 : 0] v__h11213;
reg [31 : 0] v__h11950;
reg [31 : 0] v__h12201;
reg [31 : 0] v__h12576;
reg [31 : 0] v__h12817;
reg [31 : 0] v__h13192;
reg [31 : 0] v__h13433;
reg [31 : 0] v__h13919;
reg [31 : 0] v__h4678;
reg [31 : 0] v__h4672;
reg [31 : 0] v__h7085;
reg [31 : 0] v__h7460;
reg [31 : 0] v__h7835;
reg [31 : 0] v__h8595;
reg [31 : 0] v__h8841;
reg [31 : 0] v__h9218;
reg [31 : 0] v__h9510;
reg [31 : 0] v__h9802;
reg [31 : 0] v__h10066;
reg [31 : 0] v__h10495;
reg [31 : 0] v__h10851;
reg [31 : 0] v__h11207;
reg [31 : 0] v__h11944;
reg [31 : 0] v__h12195;
reg [31 : 0] v__h12570;
reg [31 : 0] v__h12811;
reg [31 : 0] v__h13186;
reg [31 : 0] v__h13427;
reg [31 : 0] v__h13913;
// synopsys translate_on
// remaining internal signals
reg CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1;
wire [7 : 0] x__h12087, x__h12713, x__h13329, x__h13851, x__h8752;
wire [1 : 0] IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249,
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288,
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327,
x1_avValue_rresp__h12065,
x1_avValue_rresp__h12691,
x1_avValue_rresp__h13307;
wire fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82,
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222,
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262,
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301,
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342,
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172,
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22,
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170,
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175,
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26;
// action method reset
assign RDY_reset = !fabric_rg_reset ;
assign CAN_FIRE_reset = !fabric_rg_reset ;
assign WILL_FIRE_reset = EN_reset ;
// action method set_verbosity
assign RDY_set_verbosity = 1'd1 ;
assign CAN_FIRE_set_verbosity = 1'd1 ;
assign WILL_FIRE_set_verbosity = EN_set_verbosity ;
// action method v_from_masters_0_m_awvalid
assign CAN_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_awvalid = 1'd1 ;
// value method v_from_masters_0_m_awready
assign v_from_masters_0_awready =
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
// action method v_from_masters_0_m_wvalid
assign CAN_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_wvalid = 1'd1 ;
// value method v_from_masters_0_m_wready
assign v_from_masters_0_wready =
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
// value method v_from_masters_0_m_bvalid
assign v_from_masters_0_bvalid =
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
// value method v_from_masters_0_m_bid
assign v_from_masters_0_bid =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[17:2] ;
// value method v_from_masters_0_m_bresp
assign v_from_masters_0_bresp =
fabric_xactors_from_masters_0_f_wr_resp$D_OUT[1:0] ;
// action method v_from_masters_0_m_bready
assign CAN_FIRE_v_from_masters_0_m_bready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_bready = 1'd1 ;
// action method v_from_masters_0_m_arvalid
assign CAN_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_arvalid = 1'd1 ;
// value method v_from_masters_0_m_arready
assign v_from_masters_0_arready =
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
// value method v_from_masters_0_m_rvalid
assign v_from_masters_0_rvalid =
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
// value method v_from_masters_0_m_rid
assign v_from_masters_0_rid =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[82:67] ;
// value method v_from_masters_0_m_rdata
assign v_from_masters_0_rdata =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[66:3] ;
// value method v_from_masters_0_m_rresp
assign v_from_masters_0_rresp =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[2:1] ;
// value method v_from_masters_0_m_rlast
assign v_from_masters_0_rlast =
fabric_xactors_from_masters_0_f_rd_data$D_OUT[0] ;
// action method v_from_masters_0_m_rready
assign CAN_FIRE_v_from_masters_0_m_rready = 1'd1 ;
assign WILL_FIRE_v_from_masters_0_m_rready = 1'd1 ;
// value method v_to_slaves_0_m_awvalid
assign v_to_slaves_0_awvalid =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_0_m_awid
assign v_to_slaves_0_awid =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_awaddr
assign v_to_slaves_0_awaddr =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_awlen
assign v_to_slaves_0_awlen =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_awsize
assign v_to_slaves_0_awsize =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_awburst
assign v_to_slaves_0_awburst =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_awlock
assign v_to_slaves_0_awlock =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_awcache
assign v_to_slaves_0_awcache =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_awprot
assign v_to_slaves_0_awprot =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_awqos
assign v_to_slaves_0_awqos =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_awregion
assign v_to_slaves_0_awregion =
fabric_xactors_to_slaves_0_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_awready
assign CAN_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_awready = 1'd1 ;
// value method v_to_slaves_0_m_wvalid
assign v_to_slaves_0_wvalid = fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N ;
// value method v_to_slaves_0_m_wdata
assign v_to_slaves_0_wdata =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_0_m_wstrb
assign v_to_slaves_0_wstrb =
fabric_xactors_to_slaves_0_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_0_m_wlast
assign v_to_slaves_0_wlast = fabric_xactors_to_slaves_0_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_0_m_wready
assign CAN_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_wready = 1'd1 ;
// action method v_to_slaves_0_m_bvalid
assign CAN_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_bvalid = 1'd1 ;
// value method v_to_slaves_0_m_bready
assign v_to_slaves_0_bready = fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
// value method v_to_slaves_0_m_arvalid
assign v_to_slaves_0_arvalid =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_0_m_arid
assign v_to_slaves_0_arid =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_0_m_araddr
assign v_to_slaves_0_araddr =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_0_m_arlen
assign v_to_slaves_0_arlen =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_0_m_arsize
assign v_to_slaves_0_arsize =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_0_m_arburst
assign v_to_slaves_0_arburst =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_0_m_arlock
assign v_to_slaves_0_arlock =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_0_m_arcache
assign v_to_slaves_0_arcache =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_0_m_arprot
assign v_to_slaves_0_arprot =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_0_m_arqos
assign v_to_slaves_0_arqos =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_0_m_arregion
assign v_to_slaves_0_arregion =
fabric_xactors_to_slaves_0_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_0_m_arready
assign CAN_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_arready = 1'd1 ;
// action method v_to_slaves_0_m_rvalid
assign CAN_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_0_m_rvalid = 1'd1 ;
// value method v_to_slaves_0_m_rready
assign v_to_slaves_0_rready = fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
// value method v_to_slaves_1_m_awvalid
assign v_to_slaves_1_awvalid =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_1_m_awid
assign v_to_slaves_1_awid =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_awaddr
assign v_to_slaves_1_awaddr =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_awlen
assign v_to_slaves_1_awlen =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_awsize
assign v_to_slaves_1_awsize =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_awburst
assign v_to_slaves_1_awburst =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_awlock
assign v_to_slaves_1_awlock =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_awcache
assign v_to_slaves_1_awcache =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_awprot
assign v_to_slaves_1_awprot =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_awqos
assign v_to_slaves_1_awqos =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_awregion
assign v_to_slaves_1_awregion =
fabric_xactors_to_slaves_1_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_awready
assign CAN_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_awready = 1'd1 ;
// value method v_to_slaves_1_m_wvalid
assign v_to_slaves_1_wvalid = fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N ;
// value method v_to_slaves_1_m_wdata
assign v_to_slaves_1_wdata =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_1_m_wstrb
assign v_to_slaves_1_wstrb =
fabric_xactors_to_slaves_1_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_1_m_wlast
assign v_to_slaves_1_wlast = fabric_xactors_to_slaves_1_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_1_m_wready
assign CAN_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_wready = 1'd1 ;
// action method v_to_slaves_1_m_bvalid
assign CAN_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_bvalid = 1'd1 ;
// value method v_to_slaves_1_m_bready
assign v_to_slaves_1_bready = fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
// value method v_to_slaves_1_m_arvalid
assign v_to_slaves_1_arvalid =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_1_m_arid
assign v_to_slaves_1_arid =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_1_m_araddr
assign v_to_slaves_1_araddr =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_1_m_arlen
assign v_to_slaves_1_arlen =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_1_m_arsize
assign v_to_slaves_1_arsize =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_1_m_arburst
assign v_to_slaves_1_arburst =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_1_m_arlock
assign v_to_slaves_1_arlock =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_1_m_arcache
assign v_to_slaves_1_arcache =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_1_m_arprot
assign v_to_slaves_1_arprot =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_1_m_arqos
assign v_to_slaves_1_arqos =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_1_m_arregion
assign v_to_slaves_1_arregion =
fabric_xactors_to_slaves_1_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_1_m_arready
assign CAN_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_arready = 1'd1 ;
// action method v_to_slaves_1_m_rvalid
assign CAN_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_1_m_rvalid = 1'd1 ;
// value method v_to_slaves_1_m_rready
assign v_to_slaves_1_rready = fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
// value method v_to_slaves_2_m_awvalid
assign v_to_slaves_2_awvalid =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N ;
// value method v_to_slaves_2_m_awid
assign v_to_slaves_2_awid =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_awaddr
assign v_to_slaves_2_awaddr =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_awlen
assign v_to_slaves_2_awlen =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_awsize
assign v_to_slaves_2_awsize =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_awburst
assign v_to_slaves_2_awburst =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_awlock
assign v_to_slaves_2_awlock =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_awcache
assign v_to_slaves_2_awcache =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_awprot
assign v_to_slaves_2_awprot =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_awqos
assign v_to_slaves_2_awqos =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_awregion
assign v_to_slaves_2_awregion =
fabric_xactors_to_slaves_2_f_wr_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_awready
assign CAN_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_awready = 1'd1 ;
// value method v_to_slaves_2_m_wvalid
assign v_to_slaves_2_wvalid = fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N ;
// value method v_to_slaves_2_m_wdata
assign v_to_slaves_2_wdata =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[72:9] ;
// value method v_to_slaves_2_m_wstrb
assign v_to_slaves_2_wstrb =
fabric_xactors_to_slaves_2_f_wr_data$D_OUT[8:1] ;
// value method v_to_slaves_2_m_wlast
assign v_to_slaves_2_wlast = fabric_xactors_to_slaves_2_f_wr_data$D_OUT[0] ;
// action method v_to_slaves_2_m_wready
assign CAN_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_wready = 1'd1 ;
// action method v_to_slaves_2_m_bvalid
assign CAN_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_bvalid = 1'd1 ;
// value method v_to_slaves_2_m_bready
assign v_to_slaves_2_bready = fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
// value method v_to_slaves_2_m_arvalid
assign v_to_slaves_2_arvalid =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N ;
// value method v_to_slaves_2_m_arid
assign v_to_slaves_2_arid =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[108:93] ;
// value method v_to_slaves_2_m_araddr
assign v_to_slaves_2_araddr =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[92:29] ;
// value method v_to_slaves_2_m_arlen
assign v_to_slaves_2_arlen =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[28:21] ;
// value method v_to_slaves_2_m_arsize
assign v_to_slaves_2_arsize =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[20:18] ;
// value method v_to_slaves_2_m_arburst
assign v_to_slaves_2_arburst =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[17:16] ;
// value method v_to_slaves_2_m_arlock
assign v_to_slaves_2_arlock =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[15] ;
// value method v_to_slaves_2_m_arcache
assign v_to_slaves_2_arcache =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[14:11] ;
// value method v_to_slaves_2_m_arprot
assign v_to_slaves_2_arprot =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[10:8] ;
// value method v_to_slaves_2_m_arqos
assign v_to_slaves_2_arqos =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[7:4] ;
// value method v_to_slaves_2_m_arregion
assign v_to_slaves_2_arregion =
fabric_xactors_to_slaves_2_f_rd_addr$D_OUT[3:0] ;
// action method v_to_slaves_2_m_arready
assign CAN_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_arready = 1'd1 ;
// action method v_to_slaves_2_m_rvalid
assign CAN_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
assign WILL_FIRE_v_to_slaves_2_m_rvalid = 1'd1 ;
// value method v_to_slaves_2_m_rready
assign v_to_slaves_2_rready = fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
// submodule fabric_v_f_rd_err_info_0
SizedFIFO #(.p1width(32'd24),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_err_info_0$D_IN),
.ENQ(fabric_v_f_rd_err_info_0$ENQ),
.DEQ(fabric_v_f_rd_err_info_0$DEQ),
.CLR(fabric_v_f_rd_err_info_0$CLR),
.D_OUT(fabric_v_f_rd_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_rd_err_info_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_0
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_0$D_IN),
.ENQ(fabric_v_f_rd_mis_0$ENQ),
.DEQ(fabric_v_f_rd_mis_0$DEQ),
.CLR(fabric_v_f_rd_mis_0$CLR),
.D_OUT(fabric_v_f_rd_mis_0$D_OUT),
.FULL_N(fabric_v_f_rd_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_0$EMPTY_N));
// submodule fabric_v_f_rd_mis_1
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_1$D_IN),
.ENQ(fabric_v_f_rd_mis_1$ENQ),
.DEQ(fabric_v_f_rd_mis_1$DEQ),
.CLR(fabric_v_f_rd_mis_1$CLR),
.D_OUT(fabric_v_f_rd_mis_1$D_OUT),
.FULL_N(fabric_v_f_rd_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_1$EMPTY_N));
// submodule fabric_v_f_rd_mis_2
SizedFIFO #(.p1width(32'd9),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_mis_2$D_IN),
.ENQ(fabric_v_f_rd_mis_2$ENQ),
.DEQ(fabric_v_f_rd_mis_2$DEQ),
.CLR(fabric_v_f_rd_mis_2$CLR),
.D_OUT(fabric_v_f_rd_mis_2$D_OUT),
.FULL_N(fabric_v_f_rd_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_rd_mis_2$EMPTY_N));
// submodule fabric_v_f_rd_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_rd_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_rd_sjs_0$D_IN),
.ENQ(fabric_v_f_rd_sjs_0$ENQ),
.DEQ(fabric_v_f_rd_sjs_0$DEQ),
.CLR(fabric_v_f_rd_sjs_0$CLR),
.D_OUT(fabric_v_f_rd_sjs_0$D_OUT),
.FULL_N(fabric_v_f_rd_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_rd_sjs_0$EMPTY_N));
// submodule fabric_v_f_wd_tasks_0
FIFO2 #(.width(32'd10), .guarded(32'd1)) fabric_v_f_wd_tasks_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wd_tasks_0$D_IN),
.ENQ(fabric_v_f_wd_tasks_0$ENQ),
.DEQ(fabric_v_f_wd_tasks_0$DEQ),
.CLR(fabric_v_f_wd_tasks_0$CLR),
.D_OUT(fabric_v_f_wd_tasks_0$D_OUT),
.FULL_N(fabric_v_f_wd_tasks_0$FULL_N),
.EMPTY_N(fabric_v_f_wd_tasks_0$EMPTY_N));
// submodule fabric_v_f_wr_err_info_0
SizedFIFO #(.p1width(32'd16),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_err_info_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_err_info_0$D_IN),
.ENQ(fabric_v_f_wr_err_info_0$ENQ),
.DEQ(fabric_v_f_wr_err_info_0$DEQ),
.CLR(fabric_v_f_wr_err_info_0$CLR),
.D_OUT(fabric_v_f_wr_err_info_0$D_OUT),
.FULL_N(),
.EMPTY_N(fabric_v_f_wr_err_info_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_0
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_0$D_IN),
.ENQ(fabric_v_f_wr_mis_0$ENQ),
.DEQ(fabric_v_f_wr_mis_0$DEQ),
.CLR(fabric_v_f_wr_mis_0$CLR),
.D_OUT(fabric_v_f_wr_mis_0$D_OUT),
.FULL_N(fabric_v_f_wr_mis_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_0$EMPTY_N));
// submodule fabric_v_f_wr_mis_1
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_1(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_1$D_IN),
.ENQ(fabric_v_f_wr_mis_1$ENQ),
.DEQ(fabric_v_f_wr_mis_1$DEQ),
.CLR(fabric_v_f_wr_mis_1$CLR),
.D_OUT(fabric_v_f_wr_mis_1$D_OUT),
.FULL_N(fabric_v_f_wr_mis_1$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_1$EMPTY_N));
// submodule fabric_v_f_wr_mis_2
SizedFIFO #(.p1width(32'd1),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_mis_2(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_mis_2$D_IN),
.ENQ(fabric_v_f_wr_mis_2$ENQ),
.DEQ(fabric_v_f_wr_mis_2$DEQ),
.CLR(fabric_v_f_wr_mis_2$CLR),
.D_OUT(fabric_v_f_wr_mis_2$D_OUT),
.FULL_N(fabric_v_f_wr_mis_2$FULL_N),
.EMPTY_N(fabric_v_f_wr_mis_2$EMPTY_N));
// submodule fabric_v_f_wr_sjs_0
SizedFIFO #(.p1width(32'd2),
.p2depth(32'd8),
.p3cntr_width(32'd3),
.guarded(32'd1)) fabric_v_f_wr_sjs_0(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_v_f_wr_sjs_0$D_IN),
.ENQ(fabric_v_f_wr_sjs_0$ENQ),
.DEQ(fabric_v_f_wr_sjs_0$DEQ),
.CLR(fabric_v_f_wr_sjs_0$CLR),
.D_OUT(fabric_v_f_wr_sjs_0$D_OUT),
.FULL_N(fabric_v_f_wr_sjs_0$FULL_N),
.EMPTY_N(fabric_v_f_wr_sjs_0$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_rd_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_data$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_from_masters_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_from_masters_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_from_masters_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_from_masters_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_from_masters_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_from_masters_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_from_masters_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_from_masters_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_0_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_0_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_0_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_0_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_0_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_0_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_0_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_0_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_1_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_1_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_1_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_1_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_1_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_1_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_1_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_1_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_rd_data
FIFO2 #(.width(32'd83),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_rd_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_rd_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_rd_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_rd_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_rd_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_rd_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_rd_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_addr
FIFO2 #(.width(32'd109),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_addr(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_addr$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_addr$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_addr$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_addr$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_addr$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_addr$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_data
FIFO2 #(.width(32'd73),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_data(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_data$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_data$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_data$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_data$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_data$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_data$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N));
// submodule fabric_xactors_to_slaves_2_f_wr_resp
FIFO2 #(.width(32'd18),
.guarded(32'd1)) fabric_xactors_to_slaves_2_f_wr_resp(.RST(RST_N),
.CLK(CLK),
.D_IN(fabric_xactors_to_slaves_2_f_wr_resp$D_IN),
.ENQ(fabric_xactors_to_slaves_2_f_wr_resp$ENQ),
.DEQ(fabric_xactors_to_slaves_2_f_wr_resp$DEQ),
.CLR(fabric_xactors_to_slaves_2_f_wr_resp$CLR),
.D_OUT(fabric_xactors_to_slaves_2_f_wr_resp$D_OUT),
.FULL_N(fabric_xactors_to_slaves_2_f_wr_resp$FULL_N),
.EMPTY_N(fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N));
// submodule soc_map
mkSoC_Map soc_map(.CLK(CLK),
.RST_N(RST_N),
.m_is_IO_addr_addr(soc_map$m_is_IO_addr_addr),
.m_is_mem_addr_addr(soc_map$m_is_mem_addr_addr),
.m_is_near_mem_IO_addr_addr(soc_map$m_is_near_mem_IO_addr_addr),
.m_plic_addr_base(soc_map$m_plic_addr_base),
.m_plic_addr_size(),
.m_plic_addr_lim(soc_map$m_plic_addr_lim),
.m_near_mem_io_addr_base(soc_map$m_near_mem_io_addr_base),
.m_near_mem_io_addr_size(),
.m_near_mem_io_addr_lim(soc_map$m_near_mem_io_addr_lim),
.m_flash_mem_addr_base(),
.m_flash_mem_addr_size(),
.m_flash_mem_addr_lim(),
.m_ethernet_0_addr_base(),
.m_ethernet_0_addr_size(),
.m_ethernet_0_addr_lim(),
.m_dma_0_addr_base(),
.m_dma_0_addr_size(),
.m_dma_0_addr_lim(),
.m_uart16550_0_addr_base(),
.m_uart16550_0_addr_size(),
.m_uart16550_0_addr_lim(),
.m_gpio_0_addr_base(),
.m_gpio_0_addr_size(),
.m_gpio_0_addr_lim(),
.m_boot_rom_addr_base(),
.m_boot_rom_addr_size(),
.m_boot_rom_addr_lim(),
.m_ddr4_0_uncached_addr_base(),
.m_ddr4_0_uncached_addr_size(),
.m_ddr4_0_uncached_addr_lim(),
.m_ddr4_0_cached_addr_base(),
.m_ddr4_0_cached_addr_size(),
.m_ddr4_0_cached_addr_lim(),
.m_is_mem_addr(),
.m_is_IO_addr(),
.m_is_near_mem_IO_addr(),
.m_pc_reset_value(),
.m_mtvec_reset_value(),
.m_nmivec_reset_value());
// rule RL_fabric_rl_wr_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_addr$FULL_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_mis_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29) ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_wr_addr$EMPTY_N &&
fabric_v_f_wd_tasks_0$FULL_N &&
fabric_v_f_wr_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_wr_addr$FULL_N &&
fabric_v_f_wr_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 ||
!fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 &&
fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_wr_xaction_master_to_slave_data
assign CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
fabric_xactors_from_masters_0_f_wr_data$EMPTY_N &&
fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82 ;
assign WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
// rule RL_fabric_rl_wr_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
fabric_v_f_wr_mis_0$EMPTY_N && fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_wr_resp$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
!fabric_v_f_wr_mis_0$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
// rule RL_fabric_rl_wr_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_1$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
// rule RL_fabric_rl_wr_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_wr_resp$EMPTY_N &&
!fabric_v_f_wr_mis_2$D_OUT &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
// rule RL_fabric_rl_wr_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master =
fabric_v_f_wr_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_wr_resp$FULL_N &&
fabric_v_f_wr_err_info_0$EMPTY_N &&
fabric_v_f_wr_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
// rule RL_fabric_rl_rd_xaction_master_to_slave
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_0$FULL_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172) &&
(!soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177) ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_1
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_1_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_1$FULL_N &&
soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
// rule RL_fabric_rl_rd_xaction_master_to_slave_2
assign CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
fabric_xactors_from_masters_0_f_rd_addr$EMPTY_N &&
fabric_v_f_rd_sjs_0$FULL_N &&
fabric_xactors_to_slaves_2_f_rd_addr$FULL_N &&
fabric_v_f_rd_mis_2$FULL_N &&
(!soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 ||
!fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172) &&
soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 &&
fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177 ;
assign WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
// rule RL_fabric_rl_rd_resp_slave_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
fabric_v_f_rd_mis_0$EMPTY_N &&
fabric_xactors_to_slaves_0_f_rd_data$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
(fabric_v_f_rd_mis_0$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_0$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd0 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
// rule RL_fabric_rl_rd_resp_slave_to_master_1
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_1$EMPTY_N &&
fabric_xactors_to_slaves_1_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_1$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_1$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd1 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
// rule RL_fabric_rl_rd_resp_slave_to_master_2
assign CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_mis_2$EMPTY_N &&
fabric_xactors_to_slaves_2_f_rd_data$EMPTY_N &&
(fabric_v_f_rd_mis_2$D_OUT[8] || fabric_v_f_rd_sjs_0$EMPTY_N) &&
(!fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ||
fabric_v_f_rd_sjs_0$EMPTY_N) &&
!fabric_v_f_rd_mis_2$D_OUT[8] &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd2 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
// rule RL_fabric_rl_rd_resp_err_to_master
assign CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master =
fabric_v_f_rd_sjs_0$EMPTY_N &&
fabric_xactors_from_masters_0_f_rd_data$FULL_N &&
fabric_v_f_rd_err_info_0$EMPTY_N &&
fabric_v_f_rd_sjs_0$D_OUT == 2'd3 ;
assign WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// rule RL_fabric_rl_reset
assign CAN_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
assign WILL_FIRE_RL_fabric_rl_reset = fabric_rg_reset ;
// inputs to muxes for submodule ports
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 =
{ 2'd0, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 =
{ 2'd1, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3 =
{ 2'd2, fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21] } ;
assign MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 =
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ?
8'd0 :
x__h12087 ;
assign MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 =
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ?
8'd0 :
x__h12713 ;
assign MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 =
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ?
8'd0 :
x__h13329 ;
assign MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 =
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 ?
8'd0 :
x__h8752 ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 =
{ fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249,
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 =
{ fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288,
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 =
{ fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:3],
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327,
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0] } ;
assign MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4 =
{ fabric_v_f_rd_err_info_0$D_OUT[15:0],
66'd3,
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 } ;
assign MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4 =
{ fabric_v_f_wr_err_info_0$D_OUT, 2'd3 } ;
// register fabric_cfg_verbosity
assign fabric_cfg_verbosity$D_IN = set_verbosity_verbosity ;
assign fabric_cfg_verbosity$EN = EN_set_verbosity ;
// register fabric_rg_reset
assign fabric_rg_reset$D_IN = !fabric_rg_reset ;
assign fabric_rg_reset$EN = fabric_rg_reset || EN_reset ;
// register fabric_v_rg_r_beat_count_0
assign fabric_v_rg_r_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_1
assign fabric_v_rg_r_beat_count_1$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_1$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_1$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
fabric_rg_reset ;
// register fabric_v_rg_r_beat_count_2
assign fabric_v_rg_r_beat_count_2$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_r_beat_count_2$write_1__VAL_2 ;
assign fabric_v_rg_r_beat_count_2$EN =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
fabric_rg_reset ;
// register fabric_v_rg_r_err_beat_count_0
assign fabric_v_rg_r_err_beat_count_0$D_IN =
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ?
8'd0 :
x__h13851 ;
assign fabric_v_rg_r_err_beat_count_0$EN =
CAN_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
// register fabric_v_rg_wd_beat_count_0
assign fabric_v_rg_wd_beat_count_0$D_IN =
fabric_rg_reset ?
8'd0 :
MUX_fabric_v_rg_wd_beat_count_0$write_1__VAL_2 ;
assign fabric_v_rg_wd_beat_count_0$EN =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ||
fabric_rg_reset ;
// submodule fabric_v_f_rd_err_info_0
assign fabric_v_f_rd_err_info_0$D_IN = 24'h0 ;
assign fabric_v_f_rd_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_rd_err_info_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ;
assign fabric_v_f_rd_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_0
assign fabric_v_f_rd_mis_0$D_IN =
{ 1'd0, fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21] } ;
assign fabric_v_f_rd_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_v_f_rd_mis_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ;
assign fabric_v_f_rd_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_1
assign fabric_v_f_rd_mis_1$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_v_f_rd_mis_1$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ;
assign fabric_v_f_rd_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_mis_2
assign fabric_v_f_rd_mis_2$D_IN = fabric_v_f_rd_mis_0$D_IN ;
assign fabric_v_f_rd_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_mis_2$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ;
assign fabric_v_f_rd_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_rd_sjs_0
always@(WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave:
fabric_v_f_rd_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1:
fabric_v_f_rd_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2:
fabric_v_f_rd_sjs_0$D_IN = 2'd2;
default: fabric_v_f_rd_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_rd_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_v_f_rd_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 ;
assign fabric_v_f_rd_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wd_tasks_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 or
MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wd_tasks_0$D_IN = MUX_fabric_v_f_wd_tasks_0$enq_1__VAL_3;
default: fabric_v_f_wd_tasks_0$D_IN =
10'b1010101010 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wd_tasks_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wd_tasks_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 ;
assign fabric_v_f_wd_tasks_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_err_info_0
assign fabric_v_f_wr_err_info_0$D_IN = 16'h0 ;
assign fabric_v_f_wr_err_info_0$ENQ = 1'b0 ;
assign fabric_v_f_wr_err_info_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_v_f_wr_err_info_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_0
assign fabric_v_f_wr_mis_0$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_0$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_v_f_wr_mis_0$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_mis_0$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_1
assign fabric_v_f_wr_mis_1$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_1$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_v_f_wr_mis_1$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_v_f_wr_mis_1$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_mis_2
assign fabric_v_f_wr_mis_2$D_IN = 1'd0 ;
assign fabric_v_f_wr_mis_2$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_mis_2$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_v_f_wr_mis_2$CLR = fabric_rg_reset ;
// submodule fabric_v_f_wr_sjs_0
always@(WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 or
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave:
fabric_v_f_wr_sjs_0$D_IN = 2'd0;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1:
fabric_v_f_wr_sjs_0$D_IN = 2'd1;
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2:
fabric_v_f_wr_sjs_0$D_IN = 2'd2;
default: fabric_v_f_wr_sjs_0$D_IN = 2'b10 /* unspecified value */ ;
endcase
end
assign fabric_v_f_wr_sjs_0$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_v_f_wr_sjs_0$DEQ =
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_v_f_wr_sjs_0$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_addr
assign fabric_xactors_from_masters_0_f_rd_addr$D_IN =
{ v_from_masters_0_arid,
v_from_masters_0_araddr,
v_from_masters_0_arlen,
v_from_masters_0_arsize,
v_from_masters_0_arburst,
v_from_masters_0_arlock,
v_from_masters_0_arcache,
v_from_masters_0_arprot,
v_from_masters_0_arqos,
v_from_masters_0_arregion } ;
assign fabric_xactors_from_masters_0_f_rd_addr$ENQ =
v_from_masters_0_arvalid &&
fabric_xactors_from_masters_0_f_rd_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_rd_addr$DEQ =
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_rd_data
always@(WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2 or
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3 or
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_1;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_2;
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_3;
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master:
fabric_xactors_from_masters_0_f_rd_data$D_IN =
MUX_fabric_xactors_from_masters_0_f_rd_data$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_rd_data$D_IN =
83'h2AAAAAAAAAAAAAAAAAAAA /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_rd_data$ENQ =
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_rd_data$DEQ =
v_from_masters_0_rready &&
fabric_xactors_from_masters_0_f_rd_data$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_addr
assign fabric_xactors_from_masters_0_f_wr_addr$D_IN =
{ v_from_masters_0_awid,
v_from_masters_0_awaddr,
v_from_masters_0_awlen,
v_from_masters_0_awsize,
v_from_masters_0_awburst,
v_from_masters_0_awlock,
v_from_masters_0_awcache,
v_from_masters_0_awprot,
v_from_masters_0_awqos,
v_from_masters_0_awregion } ;
assign fabric_xactors_from_masters_0_f_wr_addr$ENQ =
v_from_masters_0_awvalid &&
fabric_xactors_from_masters_0_f_wr_addr$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_addr$DEQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ||
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_from_masters_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_data
assign fabric_xactors_from_masters_0_f_wr_data$D_IN =
{ v_from_masters_0_wdata,
v_from_masters_0_wstrb,
v_from_masters_0_wlast } ;
assign fabric_xactors_from_masters_0_f_wr_data$ENQ =
v_from_masters_0_wvalid &&
fabric_xactors_from_masters_0_f_wr_data$FULL_N ;
assign fabric_xactors_from_masters_0_f_wr_data$DEQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data ;
assign fabric_xactors_from_masters_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_from_masters_0_f_wr_resp
always@(WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 or
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master or
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 or
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT or
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master or
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4)
begin
case (1'b1) // synopsys parallel_case
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_1_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_0_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
fabric_xactors_to_slaves_2_f_wr_resp$D_OUT;
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master:
fabric_xactors_from_masters_0_f_wr_resp$D_IN =
MUX_fabric_xactors_from_masters_0_f_wr_resp$enq_1__VAL_4;
default: fabric_xactors_from_masters_0_f_wr_resp$D_IN =
18'b101010101010101010 /* unspecified value */ ;
endcase
end
assign fabric_xactors_from_masters_0_f_wr_resp$ENQ =
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master ||
WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ||
WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master ;
assign fabric_xactors_from_masters_0_f_wr_resp$DEQ =
v_from_masters_0_bready &&
fabric_xactors_from_masters_0_f_wr_resp$EMPTY_N ;
assign fabric_xactors_from_masters_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_addr
assign fabric_xactors_to_slaves_0_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_rd_addr$DEQ =
fabric_xactors_to_slaves_0_f_rd_addr$EMPTY_N &&
v_to_slaves_0_arready ;
assign fabric_xactors_to_slaves_0_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_rd_data
assign fabric_xactors_to_slaves_0_f_rd_data$D_IN =
{ v_to_slaves_0_rid,
v_to_slaves_0_rdata,
v_to_slaves_0_rresp,
v_to_slaves_0_rlast } ;
assign fabric_xactors_to_slaves_0_f_rd_data$ENQ =
v_to_slaves_0_rvalid &&
fabric_xactors_to_slaves_0_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_0_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_addr
assign fabric_xactors_to_slaves_0_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave ;
assign fabric_xactors_to_slaves_0_f_wr_addr$DEQ =
fabric_xactors_to_slaves_0_f_wr_addr$EMPTY_N &&
v_to_slaves_0_awready ;
assign fabric_xactors_to_slaves_0_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_data
assign fabric_xactors_to_slaves_0_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_0_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd0 ;
assign fabric_xactors_to_slaves_0_f_wr_data$DEQ =
fabric_xactors_to_slaves_0_f_wr_data$EMPTY_N &&
v_to_slaves_0_wready ;
assign fabric_xactors_to_slaves_0_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_0_f_wr_resp
assign fabric_xactors_to_slaves_0_f_wr_resp$D_IN =
{ v_to_slaves_0_bid, v_to_slaves_0_bresp } ;
assign fabric_xactors_to_slaves_0_f_wr_resp$ENQ =
v_to_slaves_0_bvalid &&
fabric_xactors_to_slaves_0_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_0_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master ;
assign fabric_xactors_to_slaves_0_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_addr
assign fabric_xactors_to_slaves_1_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_rd_addr$DEQ =
fabric_xactors_to_slaves_1_f_rd_addr$EMPTY_N &&
v_to_slaves_1_arready ;
assign fabric_xactors_to_slaves_1_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_rd_data
assign fabric_xactors_to_slaves_1_f_rd_data$D_IN =
{ v_to_slaves_1_rid,
v_to_slaves_1_rdata,
v_to_slaves_1_rresp,
v_to_slaves_1_rlast } ;
assign fabric_xactors_to_slaves_1_f_rd_data$ENQ =
v_to_slaves_1_rvalid &&
fabric_xactors_to_slaves_1_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_1_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_addr
assign fabric_xactors_to_slaves_1_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 ;
assign fabric_xactors_to_slaves_1_f_wr_addr$DEQ =
fabric_xactors_to_slaves_1_f_wr_addr$EMPTY_N &&
v_to_slaves_1_awready ;
assign fabric_xactors_to_slaves_1_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_data
assign fabric_xactors_to_slaves_1_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_1_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd1 ;
assign fabric_xactors_to_slaves_1_f_wr_data$DEQ =
fabric_xactors_to_slaves_1_f_wr_data$EMPTY_N &&
v_to_slaves_1_wready ;
assign fabric_xactors_to_slaves_1_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_1_f_wr_resp
assign fabric_xactors_to_slaves_1_f_wr_resp$D_IN =
{ v_to_slaves_1_bid, v_to_slaves_1_bresp } ;
assign fabric_xactors_to_slaves_1_f_wr_resp$ENQ =
v_to_slaves_1_bvalid &&
fabric_xactors_to_slaves_1_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_1_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 ;
assign fabric_xactors_to_slaves_1_f_wr_resp$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_addr
assign fabric_xactors_to_slaves_2_f_rd_addr$D_IN =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_rd_addr$ENQ =
CAN_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_rd_addr$DEQ =
fabric_xactors_to_slaves_2_f_rd_addr$EMPTY_N &&
v_to_slaves_2_arready ;
assign fabric_xactors_to_slaves_2_f_rd_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_rd_data
assign fabric_xactors_to_slaves_2_f_rd_data$D_IN =
{ v_to_slaves_2_rid,
v_to_slaves_2_rdata,
v_to_slaves_2_rresp,
v_to_slaves_2_rlast } ;
assign fabric_xactors_to_slaves_2_f_rd_data$ENQ =
v_to_slaves_2_rvalid &&
fabric_xactors_to_slaves_2_f_rd_data$FULL_N ;
assign fabric_xactors_to_slaves_2_f_rd_data$DEQ =
CAN_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_rd_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_addr
assign fabric_xactors_to_slaves_2_f_wr_addr$D_IN =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_addr$ENQ =
CAN_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 ;
assign fabric_xactors_to_slaves_2_f_wr_addr$DEQ =
fabric_xactors_to_slaves_2_f_wr_addr$EMPTY_N &&
v_to_slaves_2_awready ;
assign fabric_xactors_to_slaves_2_f_wr_addr$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_data
assign fabric_xactors_to_slaves_2_f_wr_data$D_IN =
fabric_xactors_from_masters_0_f_wr_data$D_OUT ;
assign fabric_xactors_to_slaves_2_f_wr_data$ENQ =
WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_f_wd_tasks_0$D_OUT[9:8] == 2'd2 ;
assign fabric_xactors_to_slaves_2_f_wr_data$DEQ =
fabric_xactors_to_slaves_2_f_wr_data$EMPTY_N &&
v_to_slaves_2_wready ;
assign fabric_xactors_to_slaves_2_f_wr_data$CLR = fabric_rg_reset ;
// submodule fabric_xactors_to_slaves_2_f_wr_resp
assign fabric_xactors_to_slaves_2_f_wr_resp$D_IN =
{ v_to_slaves_2_bid, v_to_slaves_2_bresp } ;
assign fabric_xactors_to_slaves_2_f_wr_resp$ENQ =
v_to_slaves_2_bvalid &&
fabric_xactors_to_slaves_2_f_wr_resp$FULL_N ;
assign fabric_xactors_to_slaves_2_f_wr_resp$DEQ =
CAN_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 ;
assign fabric_xactors_to_slaves_2_f_wr_resp$CLR = fabric_rg_reset ;
// submodule soc_map
assign soc_map$m_is_IO_addr_addr = 64'h0 ;
assign soc_map$m_is_mem_addr_addr = 64'h0 ;
assign soc_map$m_is_near_mem_IO_addr_addr = 64'h0 ;
// remaining internal signals
assign IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249 =
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 ?
x1_avValue_rresp__h12065 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288 =
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 ?
x1_avValue_rresp__h12691 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327 =
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 ?
x1_avValue_rresp__h13307 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign fabric_v_f_wd_tasks_0_i_notEmpty__3_AND_fabric_ETC___d82 =
fabric_v_f_wd_tasks_0$EMPTY_N &&
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 ;
assign fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 =
fabric_v_rg_r_beat_count_0 == fabric_v_f_rd_mis_0$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 =
fabric_v_rg_r_beat_count_1 == fabric_v_f_rd_mis_1$D_OUT[7:0] ;
assign fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 =
fabric_v_rg_r_beat_count_2 == fabric_v_f_rd_mis_2$D_OUT[7:0] ;
assign fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342 =
fabric_v_rg_r_err_beat_count_0 ==
fabric_v_f_rd_err_info_0$D_OUT[23:16] ;
assign fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 =
fabric_v_rg_wd_beat_count_0 == fabric_v_f_wd_tasks_0$D_OUT[7:0] ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d172 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_rd_addr_first__ETC___d177 =
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d22 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_near_mem_io_addr_lim ;
assign fabric_xactors_from_masters_0_f_wr_addr_first__ETC___d29 =
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] <
soc_map$m_plic_addr_lim ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d170 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_near_mem_io_addr_base__6_ULE_fabric__ETC___d19 =
soc_map$m_near_mem_io_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d175 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29] ;
assign soc_map_m_plic_addr_base__5_ULE_fabric_xactors_ETC___d26 =
soc_map$m_plic_addr_base <=
fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29] ;
assign x1_avValue_rresp__h12065 =
(fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h12691 =
(fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] ;
assign x1_avValue_rresp__h13307 =
(fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0]) ?
2'b10 :
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] ;
assign x__h12087 = fabric_v_rg_r_beat_count_0 + 8'd1 ;
assign x__h12713 = fabric_v_rg_r_beat_count_1 + 8'd1 ;
assign x__h13329 = fabric_v_rg_r_beat_count_2 + 8'd1 ;
assign x__h13851 = fabric_v_rg_r_err_beat_count_0 + 8'd1 ;
assign x__h8752 = fabric_v_rg_wd_beat_count_0 + 8'd1 ;
always@(fabric_v_f_wd_tasks_0$D_OUT or
fabric_xactors_to_slaves_0_f_wr_data$FULL_N or
fabric_xactors_to_slaves_1_f_wr_data$FULL_N or
fabric_xactors_to_slaves_2_f_wr_data$FULL_N)
begin
case (fabric_v_f_wd_tasks_0$D_OUT[9:8])
2'd0:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_0_f_wr_data$FULL_N;
2'd1:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_1_f_wr_data$FULL_N;
2'd2:
CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 =
fabric_xactors_to_slaves_2_f_wr_data$FULL_N;
2'd3: CASE_fabric_v_f_wd_tasks_0D_OUT_BITS_9_TO_8_0_ETC__q1 = 1'd1;
endcase
end
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY 4'd0;
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY 1'd1;
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY 8'd0;
end
else
begin
if (fabric_cfg_verbosity$EN)
fabric_cfg_verbosity <= `BSV_ASSIGNMENT_DELAY
fabric_cfg_verbosity$D_IN;
if (fabric_rg_reset$EN)
fabric_rg_reset <= `BSV_ASSIGNMENT_DELAY fabric_rg_reset$D_IN;
if (fabric_v_rg_r_beat_count_0$EN)
fabric_v_rg_r_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_0$D_IN;
if (fabric_v_rg_r_beat_count_1$EN)
fabric_v_rg_r_beat_count_1 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_1$D_IN;
if (fabric_v_rg_r_beat_count_2$EN)
fabric_v_rg_r_beat_count_2 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_beat_count_2$D_IN;
if (fabric_v_rg_r_err_beat_count_0$EN)
fabric_v_rg_r_err_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_r_err_beat_count_0$D_IN;
if (fabric_v_rg_wd_beat_count_0$EN)
fabric_v_rg_wd_beat_count_0 <= `BSV_ASSIGNMENT_DELAY
fabric_v_rg_wd_beat_count_0$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
fabric_cfg_verbosity = 4'hA;
fabric_rg_reset = 1'h0;
fabric_v_rg_r_beat_count_0 = 8'hAA;
fabric_v_rg_r_beat_count_1 = 8'hAA;
fabric_v_rg_r_beat_count_2 = 8'hAA;
fabric_v_rg_r_err_beat_count_0 = 8'hAA;
fabric_v_rg_wd_beat_count_0 = 8'hAA;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7091 = $stime;
#0;
end
v__h7085 = v__h7091 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7085,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7466 = $stime;
#0;
end
v__h7460 = v__h7466 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7460,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h7841 = $stime;
#0;
end
v__h7835 = v__h7841 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave: m%0d -> s%0d",
v__h7835,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Addr { ", "awid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awaddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "awuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
begin
v__h8601 = $stime;
#0;
end
v__h8595 = v__h8601 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: m%0d -> s%0d, beat %0d/%0d",
v__h8595,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8],
fabric_v_rg_wd_beat_count_0,
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
begin
v__h8847 = $stime;
#0;
end
v__h8841 = v__h8847 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display("%0d: %m.rl_wr_xaction_master_to_slave_data: ERROR: m%0d -> s%0d",
v__h8841,
$signed(32'd0),
fabric_v_f_wd_tasks_0$D_OUT[9:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$display(" WLAST not set on final data beat (awlen = %0d)",
fabric_v_f_wd_tasks_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("AXI4_Wr_Data { ", "wdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[72:9]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wstrb: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", fabric_xactors_from_masters_0_f_wr_data$D_OUT[8:1]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write(", ", "wuser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_xaction_master_to_slave_data &&
fabric_v_rg_wd_beat_count_0_0_EQ_fabric_v_f_wd_ETC___d98 &&
!fabric_xactors_from_masters_0_f_wr_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9224 = $stime;
#0;
end
v__h9218 = v__h9224 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9218,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9516 = $stime;
#0;
end
v__h9510 = v__h9516 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9510,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h9808 = $stime;
#0;
end
v__h9802 = v__h9808 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_slave_to_master: m%0d <- s%0d",
v__h9802,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[17:2]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_wr_resp$D_OUT[1:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10072 = $stime;
#0;
end
v__h10066 = v__h10072 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_wr_resp_err_to_master: m%0d <- err",
v__h10066,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Wr_Resp { ", "bid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_wr_err_info_0$D_OUT);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "bresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "buser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_wr_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10501 = $stime;
#0;
end
v__h10495 = v__h10501 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10495,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h10857 = $stime;
#0;
end
v__h10851 = v__h10857 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h10851,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h11213 = $stime;
#0;
end
v__h11207 = v__h11213 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_xaction_master_to_slave: m%0d -> s%0d",
v__h11207,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Addr { ", "arid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[108:93]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "araddr: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[92:29]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlen: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[28:21]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arsize: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[20:18]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arburst: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[17:16]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arlock: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[15]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arcache: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[14:11]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arprot: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[10:8]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arqos: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[7:4]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "arregion: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_from_masters_0_f_rd_addr$D_OUT[3:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "aruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_xaction_master_to_slave_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
begin
v__h11950 = $stime;
#0;
end
v__h11944 = v__h11950 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h11944,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_0$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_rd_ETC___d222 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12201 = $stime;
#0;
end
v__h12195 = v__h12201 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12195,
$signed(32'd0),
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_0_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_0_20_EQ_fabric_v_f_ETC___d249);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_0_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
begin
v__h12576 = $stime;
#0;
end
v__h12570 = v__h12576 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h12570,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_1$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_rd_ETC___d262 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h12817 = $stime;
#0;
end
v__h12811 = v__h12817 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h12811,
$signed(32'd0),
$signed(32'd1));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_1_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_1_60_EQ_fabric_v_f_ETC___d288);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_1_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_1 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
begin
v__h13192 = $stime;
#0;
end
v__h13186 = v__h13192 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display("%0d: %m.rl_rd_resp_slave_to_master: ERROR: m%0d <- s%0d",
v__h13186,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$display(" RLAST not set on final data beat (arlen = %0d)",
fabric_v_f_rd_mis_2$D_OUT[7:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(" ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 2'b10);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_rd_ETC___d301 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[2:1] == 2'b0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13433 = $stime;
#0;
end
v__h13427 = v__h13433 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_slave_to_master: m%0d <- s%0d",
v__h13427,
$signed(32'd0),
$signed(32'd2));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[82:67]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_xactors_to_slaves_2_f_rd_data$D_OUT[66:3]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h",
IF_fabric_v_rg_r_beat_count_2_99_EQ_fabric_v_f_ETC___d327);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_xactors_to_slaves_2_f_rd_data$D_OUT[0])
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_slave_to_master_2 &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
begin
v__h13919 = $stime;
#0;
end
v__h13913 = v__h13919 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_rd_resp_err_to_master: m%0d <- err",
v__h13913,
$signed(32'd0));
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(" r: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("AXI4_Rd_Data { ", "rid: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", fabric_v_f_rd_err_info_0$D_OUT[15:0]);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rdata: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 64'd0);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rresp: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 2'b11);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "rlast: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342)
$write("True");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0 &&
!fabric_v_rg_r_err_beat_count_0_40_EQ_fabric_v__ETC___d342)
$write("False");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write(", ", "ruser: ");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("'h%h", 1'd0, " }");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_fabric_rl_rd_resp_err_to_master &&
fabric_cfg_verbosity != 4'd0)
$write("\n");
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
begin
v__h4678 = $stime;
#0;
end
v__h4672 = v__h4678 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (fabric_rg_reset && fabric_cfg_verbosity != 4'd0)
$display("%0d: %m.rl_reset", v__h4672);
end
// synopsys translate_on
endmodule // mkFabric_1x3
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef enum logic [4:0]
{
BIT0 = 5'd0,
BIT1 = 5'd1,
BIT2 = 5'd2
} three_t;
module t (/*AUTOARG*/);
localparam FIVE = 5;
enum { e0,
e1,
e3=3,
e5=FIVE,
e10_[2] = 10,
e20_[5:7] = 25,
e20_z,
e30_[7:5] = 30,
e30_z
} EN;
enum {
z5 = e5
} ZN;
typedef enum [2:0] { ONES=~0 } three_t;
three_t three = ONES;
var logic [ONES:0] sized_based_on_enum;
var enum logic [3:0] { QINVALID='1, QSEND={2'b0,2'h0}, QOP={2'b0,2'h1}, QCL={2'b0,2'h2},
QPR={2'b0,2'h3 }, QACK, QRSP } inv;
initial begin
if (e0 !== 0) $stop;
if (e1 !== 1) $stop;
if (e3 !== 3) $stop;
if (e5 !== 5) $stop;
if (e10_0 !== 10) $stop;
if (e10_1 !== 11) $stop;
if (e20_5 !== 25) $stop;
if (e20_6 !== 26) $stop;
if (e20_7 !== 27) $stop;
if (e20_z !== 28) $stop;
if (e30_7 !== 30) $stop;
if (e30_6 !== 31) $stop;
if (e30_5 !== 32) $stop;
if (e30_z !== 33) $stop;
if (z5 !== 5) $stop;
if (three != 3'b111) $stop;
if ($bits(sized_based_on_enum) != 8) $stop;
if ($bits(three_t) != 3) $stop;
if (FIVE[BIT0] != 1'b1) $stop;
if (FIVE[BIT1] != 1'b0) $stop;
if (FIVE[BIT2] != 1'b1) $stop;
if (QINVALID != 15) $stop;
if (QSEND != 0) $stop;
if (QOP != 1) $stop;
if (QCL != 2) $stop;
if (QPR != 3) $stop;
if (QACK != 4) $stop;
if (QRSP != 5) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SDFSBP_1_V
`define SKY130_FD_SC_HDLL__SDFSBP_1_V
/**
* sdfsbp: Scan delay flop, inverted set, non-inverted clock,
* complementary outputs.
*
* Verilog wrapper for sdfsbp with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__sdfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__sdfsbp_1 (
Q ,
Q_N ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__sdfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SDFSBP_1_V
|
/*
*
* Copyright (c) 2011-2013 [email protected]
*
*
*
* This program is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*
*/
`timescale 1ns/1ps
module fpgaminer_top (
input sys_clk_p,
input sys_clk_n,
input uart_rx,
output uart_tx
);
//-----------------------------------------------------------------------------
// Clock Multiplier
//-----------------------------------------------------------------------------
wire hash_clk;
wire comm_clk;
`ifndef SIM
hashing_clock_multiplier hashing_clock_multiplier_blk (
.clk_in1_p (sys_clk_p),
.clk_in1_n (sys_clk_n),
.tx_hash_clk (hash_clk),
.tx_comm_clk (comm_clk)
);
`else
reg hash_clk_sim = 1'b0;
assign hash_clk = hash_clk_sim;
assign comm_clk = hash_clk_sim;
initial begin
hash_clk_sim = 1'b0;
while (1)
begin
#5 hash_clk_sim = 1'b1; #5 hash_clk_sim = 1'b0;
end
end
`endif
//-----------------------------------------------------------------------------
// DSP48E1 Hasher ---- /*ZTEX Hashers*/
//-----------------------------------------------------------------------------
reg [31:0] nonce = 32'd253, nonce2 = 32'd0;
wire [255:0] comm_midstate;
wire [95:0] comm_data;
wire [255:0] hash;
wire [31:0] hash2_w;
sha256_dsp48e1_rounds hasher (
.clk (hash_clk),
.rx_data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, comm_data}),
.rx_state (comm_midstate),
.tx_hash (hash),
.tx_midhash ()
);
sha256_dsp48e1_rounds hasher2 (
.clk (hash_clk),
.rx_data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.rx_state (256'h5be0cd191f83d9ab9b05688c510e527fa54ff53a3c6ef372bb67ae856a09e667),
.tx_hash (),
.tx_midhash (hash2_w)
);
/*sha256_pipe130 p1 (
.clk (hash_clk),
.state (midstate),
.state2 (midstate),
.data ({384'h000002800000000000000000000000000000000000000000000000000000000000000000000000000000000080000000, nonce, data}),
.hash (hash)
);
sha256_pipe123 p2 (
.clk (hash_clk),
.data ({256'h0000010000000000000000000000000000000000000000000000000080000000, hash}),
.hash (hash2_w)
);*/
//-----------------------------------------------------------------------------
// Dummy Hasher
//-----------------------------------------------------------------------------
/*reg [31:0] hash2_w;
always @ (posedge hash_clk)
begin
hash2_w <= midstate[31:0] ^ midstate[63:32] ^ midstate[95:64] ^ midstate[127:96] ^ midstate[159:128] ^ midstate[191:160] ^ midstate[223:192] ^ midstate[255:224] ^ data[31:0] ^ data[63:32] ^ data[95:64] ^ nonce;
end*/
`ifdef SIM
reg fake_uart = 1'b1;
reg [15:0] timer = 16'd0;
reg [21:0] sequence = 22'b1100010011010010100001;
always @ (posedge comm_clk)
begin
timer <= timer + 16'd1;
if (timer == 16'd867)
begin
timer <= 0;
{fake_uart, sequence} <= {sequence, 1'b1};
end
end
`endif
//-----------------------------------------------------------------------------
// Communication Module
//-----------------------------------------------------------------------------
wire comm_new_work;
reg is_golden_ticket = 1'b0, buf_is_golden_ticket = 1'b0, buf2_is_golden_ticket = 1'b0;
reg [31:0] golden_ticket, buf_golden_ticket, buf2_golden_ticket;
comm_uart # (
.comm_clk_frequency (100000000),
.baud_rate (115200)
) comm_uart_blk (
.comm_clk (comm_clk),
`ifdef SIM
.uart_rx (fake_uart),
`else
.uart_rx (uart_rx),
`endif
.uart_tx (uart_tx),
.hash_clk (hash_clk),
.rx_new_golden_ticket (buf2_is_golden_ticket),
.rx_golden_ticket (buf2_golden_ticket),
.tx_new_work (comm_new_work),
.tx_midstate (comm_midstate),
.tx_blockdata (comm_data)
);
//-----------------------------------------------------------------------------
// Control Unit
//-----------------------------------------------------------------------------
// NOTE: When the hashers first start churning on new work, results
// will be invalid for ~253 cycles. Since returning invalid results is
// not very detrimental (controlling software double checks results)
// we sacrifice a small amount of accuracy in exchange for simple
// logic.
// TODO: No longer 253 cycles on DSP based design ... need to update.
reg reset = 1'b1;
always @ (posedge hash_clk)
begin
// Counters
if (reset | comm_new_work)
begin
nonce <= 32'd503;
nonce2 <= 32'd0;
end
else
begin
nonce <= nonce + 32'd1;
nonce2 <= nonce2 + 32'd1;
end
// Clear the reset signal when we get new work
if (comm_new_work)
reset <= 1'b0;
// Stop hashing if we've run out of nonces to check
else if (nonce2 == 32'hFFFFFFFF)
reset <= 1'b1;
// Check to see if the last hash generated is valid.
is_golden_ticket <= hash2_w == 32'hA41F32E7;
if (hash2_w == 32'hA41F32E7)
golden_ticket <= nonce2;
buf_is_golden_ticket <= is_golden_ticket;
buf_golden_ticket <= golden_ticket;
{buf2_is_golden_ticket, buf2_golden_ticket} <= {buf_is_golden_ticket, buf_golden_ticket};
end
endmodule
|
// -- (c) Copyright 2010 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Interface outputs are synchronized using ordinary flops for improved timing.
//--------------------------------------------------------------------------
// Structure:
// axic_reg_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_reg_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg m_valid_i;
reg s_ready_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
reg [C_FIFO_WIDTH-1:0] storage_data1;
wire [C_FIFO_WIDTH-1:0] storage_data2; // Intermediate SRL data
reg load_s1;
wire load_s1_from_s2;
reg [1:0] state;
localparam [1:0]
ZERO = 2'b10,
ONE = 2'b11,
TWO = 2'b01;
assign M_VALID = m_valid_i;
assign S_READY = C_USE_FULL ? s_ready_i : 1'b1;
assign push = (S_VALID & (C_USE_FULL ? s_ready_i : 1'b1) & (state == TWO)) | (~M_READY & S_VALID & (state == ONE));
assign pop = M_READY & (state == TWO);
assign M_MESG = storage_data1;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
// Load storage1 with either slave side data or from storage2
always @(posedge ACLK)
begin
if (load_s1)
if (load_s1_from_s2)
storage_data1 <= storage_data2;
else
storage_data1 <= S_MESG;
end
// Loading s1
always @ *
begin
if ( ((state == ZERO) && (S_VALID == 1)) || // Load when empty on slave transaction
// Load when ONE if we both have read and write at the same time
((state == ONE) && (S_VALID == 1) && (M_READY == 1)) ||
// Load when TWO and we have a transaction on Master side
((state == TWO) && (M_READY == 1)))
load_s1 = 1'b1;
else
load_s1 = 1'b0;
end // always @ *
assign load_s1_from_s2 = (state == TWO);
// State Machine for handling output signals
always @(posedge ACLK)
begin
if (areset_d1) begin
state <= ZERO;
m_valid_i <= 1'b0;
end else begin
case (state)
// No transaction stored locally
ZERO: begin
if (S_VALID) begin
state <= ONE; // Got one so move to ONE
m_valid_i <= 1'b1;
end
end
// One transaction stored locally
ONE: begin
if (M_READY & ~S_VALID) begin
state <= ZERO; // Read out one so move to ZERO
m_valid_i <= 1'b0;
end else if (~M_READY & S_VALID) begin
state <= TWO; // Got another one so move to TWO
m_valid_i <= 1'b1;
end
end
// TWO transaction stored locally
TWO: begin
if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
state <= ONE; // Read out one so move to ONE
m_valid_i <= 1'b1;
end
end
endcase // case (state)
end
end // always @ (posedge ACLK)
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
always @(posedge ACLK) begin
if (ARESET) begin
s_ready_i <= 1'b0;
end else if (areset_d1) begin
s_ready_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
s_ready_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
s_ready_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (storage_data2[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
// Copyright (c) 2015 CERN
// Maciej Suminski <[email protected]>
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
// Test for generics without a default value.
module vhdl_generic_default_test;
logic a;
vhdl_generic_default #(.\value (1'b1))dut(a);
initial begin
if(a !== 1'b1) begin
$display("FAILED");
$finish();
end
$display("PASSED");
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A22O_4_V
`define SKY130_FD_SC_HS__A22O_4_V
/**
* a22o: 2-input AND into both inputs of 2-input OR.
*
* X = ((A1 & A2) | (B1 & B2))
*
* Verilog wrapper for a22o with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__a22o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1 ,
A2 ,
B1 ,
B2 ,
VPWR,
VGND
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input B2 ;
input VPWR;
input VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__a22o_4 (
X ,
A1,
A2,
B1,
B2
);
output X ;
input A1;
input A2;
input B1;
input B2;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__a22o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.B2(B2)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__A22O_4_V
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:16:18 05/22/2016
// Design Name:
// Module Name: MUX_DECO_FF
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
///////
module MUX_DECO_FF(
input rst,
input clk,
input listo,
input listo_lee,
input listo_escribe,
input [7:0]seleccion,
input [7:0]tecla,
input [7:0]tecla2,
input [7:0] tecla3,
input [7:0]RG1,
input [7:0]RG2,
input [7:0]RG3,
output [7:0]salida_picoblaze
);
wire [7:0]salida_mux_deco;
MUX_DECO MUX_DECO (
.seleccion(seleccion),
.listo(listo),
.listo_lee(listo_lee),
.listo_escribe(listo_escribe),
.salida_mux_deco(salida_mux_deco),
.tecla(tecla),
.tecla2(tecla2),
.tecla3(tecla3),
.RG1(RG1),
.RG2(RG2),
.RG3(RG3)
);
FFD FFD (
.rst(rst),
.clk(clk),
.dato_mux(salida_mux_deco),
.salida_picoblaze(salida_picoblaze)
);
endmodule
|
module signed_logic_operators_bug();
reg [7:0] a, b;
wire [15:0] yuu, yus, ysu, yss;
wire [15:0] zuu, zus, zsu, zss;
initial begin
// Example vector
a = 8'b10110110;
b = 8'b10010010;
// Wait for results to be calculated
#1;
// Display results
$display("a = %b", a);
$display("b = %b", b);
$display("yuu = %b", yuu);
$display("zuu = %b", zuu);
$display("yus = %b", yus);
$display("zus = %b", zus);
$display("ysu = %b", ysu);
$display("zsu = %b", zsu);
$display("yss = %b", yss);
$display("zss = %b", zss);
// Finished
$finish;
end
// Calculate signed logical OR
manually_extended_logical_or INST1(.a(a), .b(b), .yuu(yuu), .yus(yus), .ysu(ysu), .yss(yss));
signed_logical_or INST2(.a(a), .b(b), .yuu(zuu), .yus(zus), .ysu(zsu), .yss(zss));
endmodule
module manually_extended_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Manually zero or sign extend operands before logic OR
// - Note the operands are zero extended in "yuu", "yus" and "ysu"
// - The operands are sign extended in "yss"
assign yuu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yus = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign ysu = {{8{1'b0}}, a} | {{8{1'b0}}, b};
assign yss = {{8{a[7]}}, a} | {{8{b[7]}}, b};
endmodule
module signed_logical_or(a, b, yuu, yus, ysu, yss);
input [7:0] a, b;
output [15:0] yuu, yus, ysu, yss;
// Note that the operation is only consider signed if ALL data operands are signed
// - Therefore $signed(a) does NOT sign extend "a" in expression "ysu"
// - But "a" and "b" are both sign extended before the OR in expression "yss"
assign yuu = a | b ;
assign yus = a | $signed(b);
assign ysu = $signed(a) | b ;
assign yss = $signed(a) | $signed(b);
endmodule
|
//
// Copyright (c) 2002 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: Synth of basic latch form
//
//
module basiclatch ( clk, d, q);
input clk, d;
output q;
reg q;
always @ (clk or d)
if(~clk)
q = d;
endmodule
module tbench ;
reg clk, d;
basiclatch u_reg (clk,d,q);
initial
begin
clk = 0;
d = 0;
#1 ;
if(q !== 0)
begin
$display("FAILED - initial value not 0");
$finish;
end
#1 ;
clk = 1;
# 1;
d = 1;
# 1;
if(q !== 0)
begin
$display("FAILED - Didn't latch initial 0");
$finish;
end
#1
clk = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn't pass 1 after latch dropped");
$finish;
end
#1
clk = 1;
# 1;
d = 0;
# 1;
if(q !== 1)
begin
$display("FAILED - Didn't latch 1 after latch dropped");
$finish;
end
$display("PASSED");
end
endmodule
|
//wishbone master interconnect testbench
/*
Distributed under the MIT licesnse.
Copyright (c) 2011 Dave McCoy ([email protected])
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
/* Log
04/16/2013
-implement naming convention
08/30/2012
-Major overhall of the testbench
-modfied the way reads and writes happen, now each write requires the
number of 32-bit data packets even if the user sends only 1
-there is no more streaming as the data_count will implicity declare
that a read/write is streaming
-added the ih_reset which has not been formally defined within the
system, but will more than likely reset the entire statemachine
11/12/2011
-overhauled the design to behave more similar to a real I/O handler
-changed the timeout to 40 seconds to allow the wishbone master to catch
nacks
11/08/2011
-added interrupt support
*/
`timescale 1 ns/1 ps
`define TIMEOUT_COUNT 40
`define INPUT_FILE "sim/master_input_test_data.txt"
`define OUTPUT_FILE "sim/master_output_test_data.txt"
`define CLK_HALF_PERIOD 10
`define CLK_PERIOD (2 * `CLK_HALF_PERIOD)
`define SLEEP_HALF_CLK #(`CLK_HALF_PERIOD)
`define SLEEP_FULL_CLK #(`CLK_PERIOD)
//Sleep a number of clock cycles
`define SLEEP_CLK(x) #(x * `CLK_PERIOD)
//`define VERBOSE
module wishbone_master_tb (
);
//Virtual Host Interface Signals
reg clk = 0;
reg rst = 0;
wire w_master_ready;
reg r_in_ready = 0;
reg [31:0] r_in_command = 32'h00000000;
reg [31:0] r_in_address = 32'h00000000;
reg [31:0] r_in_data = 32'h00000000;
reg [27:0] r_in_data_count = 0;
reg r_out_ready = 0;
wire w_out_en;
wire [31:0] w_out_status;
wire [31:0] w_out_address;
wire [31:0] w_out_data;
wire [27:0] w_out_data_count;
reg r_ih_reset = 0;
//wishbone signals
wire w_wbp_we;
wire w_wbp_cyc;
wire w_wbp_stb;
wire [3:0] w_wbp_sel;
wire [31:0] w_wbp_adr;
wire [31:0] w_wbp_dat_o;
wire [31:0] w_wbp_dat_i;
wire w_wbp_ack;
wire w_wbp_int;
//Wishbone master mem bus
wire w_wbm_we;
wire w_wbm_cyc;
wire w_wbm_stb;
wire [3:0] w_wbm_sel;
wire [31:0] w_wbm_adr;
wire [31:0] w_wbm_dat_o;
wire [31:0] w_wbm_dat_i;
wire w_wbm_ack;
wire w_wbm_int;
//Wishbone Slave 0 (DRT) signals
wire w_wbs0_we;
wire w_wbs0_cyc;
wire [31:0] w_wbs0_dat_o;
wire w_wbs0_stb;
wire [3:0] w_wbs0_sel;
wire w_wbs0_ack;
wire [31:0] w_wbs0_dat_i;
wire [31:0] w_wbs0_adr;
wire w_wbs0_int;
//wishbone slave 1 (Unit Under Test) signals
wire w_wbs1_we;
wire w_wbs1_cyc;
wire w_wbs1_stb;
wire [3:0] w_wbs1_sel;
wire w_wbs1_ack;
wire [31:0] w_wbs1_dat_i;
wire [31:0] w_wbs1_dat_o;
wire [31:0] w_wbs1_adr;
wire w_wbs1_int;
//wishbone slave 0 signals
wire mem0_we_o;
wire mem0_cyc_o;
wire [31:0] mem0_dat_o;
wire mem0_stb_o;
wire [3:0] mem0_sel_o;
wire mem0_ack_i;
wire [31:0] mem0_dat_i;
wire [31:0] mem0_adr_o;
wire mem0_int_i;
wire w_arb0_i_wbs_stb;
wire w_arb0_i_wbs_cyc;
wire w_arb0_i_wbs_we;
wire [3:0] w_arb0_i_wbs_sel;
wire [31:0] w_arb0_i_wbs_dat;
wire [31:0] w_arb0_o_wbs_dat;
wire [31:0] w_arb0_i_wbs_adr;
wire w_arb0_o_wbs_ack;
wire w_arb0_o_wbs_int;
wire vga_mem_o_stb;
wire vga_mem_o_cyc;
wire vga_mem_o_we;
wire [3:0] vga_mem_o_sel;
wire [31:0] vga_mem_o_dat;
wire [31:0] vga_mem_o_adr;
wire [31:0] vga_mem_i_dat;
wire vga_mem_i_ack;
wire vga_mem_i_int;
//Local Parameters
localparam WAIT_FOR_SDRAM = 8'h00;
localparam IDLE = 8'h01;
localparam SEND_COMMAND = 8'h02;
localparam MASTER_READ_COMMAND = 8'h03;
localparam RESET = 8'h04;
localparam PING_RESPONSE = 8'h05;
localparam WRITE_DATA = 8'h06;
localparam WRITE_RESPONSE = 8'h07;
localparam GET_WRITE_DATA = 8'h08;
localparam READ_RESPONSE = 8'h09;
localparam READ_MORE_DATA = 8'h0A;
localparam FINISHED = 8'h0B;
//Registers/Wires/Simulation Integers
integer fd_in;
integer fd_out;
integer read_count;
integer timeout_count;
integer ch;
integer data_count;
reg [3:0] state = IDLE;
reg prev_int = 0;
reg execute_command;
reg command_finished;
reg request_more_data;
reg request_more_data_ack;
reg [27:0] data_write_count;
reg [27:0] data_read_count;
//mem slave 0
wire w_sm0_i_wbs_we;
wire w_sm0_i_wbs_cyc;
wire [31:0] w_sm0_i_wbs_dat;
wire [31:0] w_sm0_o_wbs_dat;
wire [31:0] w_sm0_i_wbs_adr;
wire w_sm0_i_wbs_stb;
wire [3:0] w_sm0_i_wbs_sel;
wire w_sm0_o_wbs_ack;
wire w_sm0_o_wbs_int;
wire w_mem_we_o;
wire w_mem_cyc_o;
wire w_mem_stb_o;
wire [3:0] w_mem_sel_o;
wire [31:0] w_mem_adr_o;
wire [31:0] w_mem_dat_i;
wire [31:0] w_mem_dat_o;
wire w_mem_ack_i;
wire w_mem_int_i;
wire w_cam_rst;
wire w_flash;
wire w_cam_in_clk;
wire w_pix_clk;
wire w_flash_strobe;
wire w_vsync;
wire w_hsync;
wire [7:0] w_pix_data;
wire start;
assign w_wbs0_int = 0;
//Submodules
wishbone_master wm (
.clk (clk ),
.rst (rst ),
.i_ih_rst (r_ih_reset ),
.i_ready (r_in_ready ),
.i_command (r_in_command ),
.i_address (r_in_address ),
.i_data (r_in_data ),
.i_data_count (r_in_data_count ),
.i_out_ready (r_out_ready ),
.o_en (w_out_en ),
.o_status (w_out_status ),
.o_address (w_out_address ),
.o_data (w_out_data ),
.o_data_count (w_out_data_count ),
.o_master_ready (w_master_ready ),
.o_per_we (w_wbp_we ),
.o_per_adr (w_wbp_adr ),
.o_per_dat (w_wbp_dat_i ),
.i_per_dat (w_wbp_dat_o ),
.o_per_stb (w_wbp_stb ),
.o_per_cyc (w_wbp_cyc ),
.o_per_sel (w_wbp_sel ),
.i_per_ack (w_wbp_ack ),
.i_per_int (w_wbp_int ),
//memory interconnect signals
.o_mem_we (w_mem_we_o ),
.o_mem_adr (w_mem_adr_o ),
.o_mem_dat (w_mem_dat_o ),
.i_mem_dat (w_mem_dat_i ),
.o_mem_stb (w_mem_stb_o ),
.o_mem_cyc (w_mem_cyc_o ),
.o_mem_sel (w_mem_sel_o ),
.i_mem_ack (w_mem_ack_i ),
.i_mem_int (w_mem_int_i )
);
//slave 1
wb_fpga_nes s1 (
.clk (clk ),
.rst (rst ),
.i_wbs_we (w_wbs1_we ),
.i_wbs_cyc (w_wbs1_cyc ),
.i_wbs_dat (w_wbs1_dat_i ),
.i_wbs_stb (w_wbs1_stb ),
.o_wbs_ack (w_wbs1_ack ),
.o_wbs_dat (w_wbs1_dat_o ),
.i_wbs_adr (w_wbs1_adr ),
.o_wbs_int (w_wbs1_int ),
.mem_o_cyc (vga_mem_o_cyc ),
.mem_o_stb (vga_mem_o_stb ),
.mem_o_we (vga_mem_o_we ),
.mem_i_ack (vga_mem_i_ack ),
.mem_o_sel (vga_mem_o_sel ),
.mem_o_adr (vga_mem_o_adr ),
.mem_o_dat (vga_mem_o_dat ),
.mem_i_dat (vga_mem_i_dat ),
.mem_i_int (vga_mem_i_int )
);
wishbone_interconnect wi (
.clk (clk ),
.rst (rst ),
.i_m_we (w_wbp_we ),
.i_m_cyc (w_wbp_cyc ),
.i_m_stb (w_wbp_stb ),
.o_m_ack (w_wbp_ack ),
.i_m_dat (w_wbp_dat_i ),
.o_m_dat (w_wbp_dat_o ),
.i_m_adr (w_wbp_adr ),
.o_m_int (w_wbp_int ),
.o_s0_we (w_wbs0_we ),
.o_s0_cyc (w_wbs0_cyc ),
.o_s0_stb (w_wbs0_stb ),
.i_s0_ack (w_wbs0_ack ),
.o_s0_dat (w_wbs0_dat_i ),
.i_s0_dat (w_wbs0_dat_o ),
.o_s0_adr (w_wbs0_adr ),
.i_s0_int (w_wbs0_int ),
.o_s1_we (w_wbs1_we ),
.o_s1_cyc (w_wbs1_cyc ),
.o_s1_stb (w_wbs1_stb ),
.i_s1_ack (w_wbs1_ack ),
.o_s1_dat (w_wbs1_dat_i ),
.i_s1_dat (w_wbs1_dat_o ),
.o_s1_adr (w_wbs1_adr ),
.i_s1_int (w_wbs1_int )
);
wishbone_mem_interconnect wmi (
.clk (clk ),
.rst (rst ),
//master
.i_m_we (w_mem_we_o ),
.i_m_cyc (w_mem_cyc_o ),
.i_m_stb (w_mem_stb_o ),
.i_m_sel (w_mem_sel_o ),
.o_m_ack (w_mem_ack_i ),
.i_m_dat (w_mem_dat_o ),
.o_m_dat (w_mem_dat_i ),
.i_m_adr (w_mem_adr_o ),
.o_m_int (w_mem_int_i ),
//slave 0
.o_s0_we (w_sm0_i_wbs_we ),
.o_s0_cyc (w_sm0_i_wbs_cyc ),
.o_s0_stb (w_sm0_i_wbs_stb ),
.o_s0_sel (w_sm0_i_wbs_sel ),
.i_s0_ack (w_sm0_o_wbs_ack ),
.o_s0_dat (w_sm0_i_wbs_dat ),
.i_s0_dat (w_sm0_o_wbs_dat ),
.o_s0_adr (w_sm0_i_wbs_adr ),
.i_s0_int (w_sm0_o_wbs_int )
);
//mem 0
wb_bram m0 (
.clk(clk),
.rst(rst),
.i_wbs_cyc (w_arb0_i_wbs_cyc ),
.i_wbs_dat (w_arb0_i_wbs_dat ),
.i_wbs_we (w_arb0_i_wbs_we ),
.i_wbs_stb (w_arb0_i_wbs_stb ),
.i_wbs_sel (w_arb0_i_wbs_sel ),
.i_wbs_adr (w_arb0_i_wbs_adr ),
.o_wbs_dat (w_arb0_o_wbs_dat ),
.o_wbs_ack (w_arb0_o_wbs_ack ),
.o_wbs_int (w_arb0_o_wbs_int )
);
arbiter_2_masters arb0 (
.clk (clk ),
.rst (rst ),
//masters
.i_m0_we (vga_mem_o_we ),
.i_m0_stb (vga_mem_o_stb ),
.i_m0_cyc (vga_mem_o_cyc ),
.i_m0_sel (vga_mem_o_sel ),
.i_m0_dat (vga_mem_o_dat ),
.i_m0_adr (vga_mem_o_adr ),
.o_m0_dat (vga_mem_i_dat ),
.o_m0_ack (vga_mem_i_ack ),
.o_m0_int (vga_mem_i_int ),
.i_m1_we (w_sm0_i_wbs_we ),
.i_m1_stb (w_sm0_i_wbs_stb ),
.i_m1_cyc (w_sm0_i_wbs_cyc ),
.i_m1_sel (w_sm0_i_wbs_sel ),
.i_m1_dat (w_sm0_i_wbs_dat ),
.i_m1_adr (w_sm0_i_wbs_adr ),
.o_m1_dat (w_sm0_o_wbs_dat ),
.o_m1_ack (w_sm0_o_wbs_ack ),
.o_m1_int (w_sm0_o_wbs_int ),
//slave
.o_s_we (w_arb0_i_wbs_we ),
.o_s_stb (w_arb0_i_wbs_stb ),
.o_s_cyc (w_arb0_i_wbs_cyc ),
.o_s_sel (w_arb0_i_wbs_sel ),
.o_s_dat (w_arb0_i_wbs_dat ),
.o_s_adr (w_arb0_i_wbs_adr ),
.i_s_dat (w_arb0_o_wbs_dat ),
.i_s_ack (w_arb0_o_wbs_ack ),
.i_s_int (w_arb0_o_wbs_int )
);
assign w_wbs0_ack = 0;
assign w_wbs0_dat_o = 0;
assign start = 1;
always #`CLK_HALF_PERIOD clk = ~clk;
initial begin
fd_out = 0;
read_count = 0;
data_count = 0;
timeout_count = 0;
request_more_data_ack <= 0;
execute_command <= 0;
$dumpfile ("design.vcd");
$dumpvars (0, wishbone_master_tb);
fd_in = $fopen(`INPUT_FILE, "r");
fd_out = $fopen(`OUTPUT_FILE, "w");
`SLEEP_HALF_CLK;
rst <= 0;
`SLEEP_CLK(100);
rst <= 1;
//clear the handler signals
r_in_ready <= 0;
r_in_command <= 0;
r_in_address <= 32'h0;
r_in_data <= 32'h0;
r_in_data_count <= 0;
r_out_ready <= 0;
//clear wishbone signals
`SLEEP_CLK(10);
rst <= 0;
r_out_ready <= 1;
if (fd_in == 0) begin
$display ("TB: input stimulus file was not found");
end
else begin
//while there is still data to be read from the file
while (!$feof(fd_in)) begin
//read in a command
read_count = $fscanf (fd_in, "%h:%h:%h:%h\n",
r_in_data_count,
r_in_command,
r_in_address,
r_in_data);
//Handle Frindge commands/comments
if (read_count != 4) begin
if (read_count == 0) begin
ch = $fgetc(fd_in);
if (ch == "\#") begin
//$display ("Eat a comment");
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
`ifdef VERBOSE $display (""); `endif
end
else begin
`ifdef VERBOSE $display ("Error unrecognized line: %h" % ch); `endif
//Eat the line
while (ch != "\n") begin
ch = $fgetc(fd_in);
end
end
end
else if (read_count == 1) begin
`ifdef VERBOSE $display ("Sleep for %h Clock cycles", r_in_data_count); `endif
`SLEEP_CLK(r_in_data_count);
`ifdef VERBOSE $display ("Sleep Finished"); `endif
end
else begin
`ifdef VERBOSE $display ("Error: read_count = %h != 4", read_count); `endif
`ifdef VERBOSE $display ("Character: %h", ch); `endif
end
end
else begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Executing PING commad");
1: $display ("TB: Executing WRITE command");
2: $display ("TB: Executing READ command");
3: $display ("TB: Executing RESET command");
endcase
`endif
`ifdef VERBOSE $display ("Execute Command"); `endif
execute_command <= 1;
`SLEEP_CLK(1);
while (~command_finished) begin
request_more_data_ack <= 0;
if ((r_in_command & 32'h0000FFFF) == 1) begin
if (request_more_data && ~request_more_data_ack) begin
read_count = $fscanf(fd_in, "%h\n", r_in_data);
`ifdef VERBOSE $display ("TB: reading a new double word: %h", r_in_data); `endif
request_more_data_ack <= 1;
end
end
//so time porgresses wait a tick
`SLEEP_CLK(1);
//this doesn't need to be here, but there is a weird behavior in iverilog
//that wont allow me to put a delay in right before an 'end' statement
//execute_command <= 1;
end //while command is not finished
execute_command <= 0;
while (command_finished) begin
`ifdef VERBOSE $display ("Command Finished"); `endif
`SLEEP_CLK(1);
execute_command <= 0;
end
`SLEEP_CLK(50);
`ifdef VERBOSE $display ("TB: finished command"); `endif
end //end read_count == 4
end //end while ! eof
end //end not reset
`SLEEP_CLK(50);
$fclose (fd_in);
$fclose (fd_out);
$finish();
end
//initial begin
// $monitor("%t, state: %h", $time, state);
//end
//initial begin
// $monitor("%t, data: %h, state: %h, execute command: %h", $time, w_wbm_dat_o, state, execute_command);
//end
//initial begin
//$monitor("%t, state: %h, execute: %h, cmd_fin: %h", $time, state, execute_command, command_finished);
//$monitor("%t, state: %h, write_size: %d, write_count: %d, execute: %h", $time, state, r_in_data_count, data_write_count, execute_command);
//end
always @ (posedge clk) begin
if (rst) begin
state <= WAIT_FOR_SDRAM;
request_more_data <= 0;
timeout_count <= 0;
prev_int <= 0;
r_ih_reset <= 0;
data_write_count <= 0;
data_read_count <= 1;
command_finished <= 0;
end
else begin
r_ih_reset <= 0;
r_in_ready <= 0;
r_out_ready <= 1;
command_finished <= 0;
//Countdown the NACK timeout
if (execute_command && timeout_count < `TIMEOUT_COUNT) begin
timeout_count <= timeout_count + 1;
end
if (execute_command && timeout_count >= `TIMEOUT_COUNT) begin
`ifdef VERBOSE
case (r_in_command)
0: $display ("TB: Master timed out while executing PING commad");
1: $display ("TB: Master timed out while executing WRITE command");
2: $display ("TB: Master timed out while executing READ command");
3: $display ("TB: Master timed out while executing RESET command");
endcase
`endif
command_finished <= 1;
state <= IDLE;
timeout_count <= 0;
end //end reached the end of a timeout
case (state)
WAIT_FOR_SDRAM: begin
timeout_count <= 0;
r_in_ready <= 0;
//Uncomment 'start' conditional to wait for SDRAM to finish starting
//up
if (start) begin
// `ifdef VERBOSE $display ("TB: sdram is ready"); `endif
state <= IDLE;
end
end
IDLE: begin
timeout_count <= 0;
command_finished <= 0;
data_write_count <= 1;
if (execute_command && !command_finished) begin
state <= SEND_COMMAND;
end
data_read_count <= 1;
end
SEND_COMMAND: begin
timeout_count <= 0;
if (w_master_ready) begin
r_in_ready <= 1;
state <= MASTER_READ_COMMAND;
end
end
MASTER_READ_COMMAND: begin
r_in_ready <= 1;
if (!w_master_ready) begin
r_in_ready <= 0;
case (r_in_command & 32'h0000FFFF)
0: begin
state <= PING_RESPONSE;
end
1: begin
if (r_in_data_count > 1) begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
if (data_write_count < r_in_data_count) begin
state <= WRITE_DATA;
timeout_count <= 0;
data_write_count<= data_write_count + 1;
end
else begin
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
else begin
`ifdef VERBOSE $display ("TB:\tWrote Double Word %d: %h", data_write_count, r_in_data); `endif
`ifdef VERBOSE $display ("TB: Finished Writing: %d 32bit words of %d size", r_in_data_count, data_write_count); `endif
state <= WRITE_RESPONSE;
end
end
2: begin
state <= READ_RESPONSE;
end
3: begin
state <= RESET;
end
endcase
end
end
RESET: begin
r_ih_reset <= 1;
state <= RESET;
end
PING_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == 8'hFF) begin
`ifdef VERBOSE $display ("TB: Ping Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Ping Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
WRITE_DATA: begin
if (!r_in_ready && w_master_ready) begin
state <= GET_WRITE_DATA;
request_more_data <= 1;
end
end
WRITE_RESPONSE: begin
`ifdef VERBOSE $display ("In Write Response"); `endif
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h01))) begin
`ifdef VERBOSE $display ("TB: Write Response Good"); `endif
end
else begin
`ifdef VERBOSE $display ("TB: Write Response Bad (Malformed response: %h)", w_out_status); `endif
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
state <= FINISHED;
end
end
GET_WRITE_DATA: begin
if (request_more_data_ack) begin
request_more_data <= 0;
r_in_ready <= 1;
state <= SEND_COMMAND;
end
end
READ_RESPONSE: begin
if (w_out_en) begin
if (w_out_status[7:0] == (~(8'h02))) begin
`ifdef VERBOSE $display ("TB: Read Response Good"); `endif
if (w_out_data_count > 0) begin
if (data_read_count < w_out_data_count) begin
state <= READ_MORE_DATA;
timeout_count <= 0;
data_read_count <= data_read_count + 1;
end
else begin
state <= FINISHED;
end
end
end
else begin
`ifdef VERBOSE $display ("TB: Read Response Bad (Malformed response: %h)", w_out_status); `endif
state <= FINISHED;
end
`ifdef VERBOSE $display ("TB: \tS:A:D = %h:%h:%h\n", w_out_status, w_out_address, w_out_data); `endif
end
end
READ_MORE_DATA: begin
if (w_out_en) begin
timeout_count <= 0;
r_out_ready <= 0;
`ifdef VERBOSE $display ("TB: Read a 32bit data packet"); `endif
`ifdef VERBOSE $display ("TB: \tRead Data: %h", w_out_data); `endif
data_read_count <= data_read_count + 1;
end
if (data_read_count >= r_in_data_count) begin
state <= FINISHED;
end
end
FINISHED: begin
command_finished <= 1;
if (!execute_command) begin
`ifdef VERBOSE $display ("Execute Command is low"); `endif
command_finished <= 0;
state <= IDLE;
end
end
endcase
if (w_out_en && w_out_status == `PERIPH_INTERRUPT) begin
`ifdef VERBOSE $display("TB: Output Handler Recieved interrupt"); `endif
`ifdef VERBOSE $display("TB:\tcommand: %h", w_out_status); `endif
`ifdef VERBOSE $display("TB:\taddress: %h", w_out_address); `endif
`ifdef VERBOSE $display("TB:\tdata: %h", w_out_data); `endif
end
end//not reset
end
endmodule
|
(** * MoreStlc: More on the Simply Typed Lambda-Calculus *)
Require Export Stlc.
(* ###################################################################### *)
(** * Simple Extensions to STLC *)
(** The simply typed lambda-calculus has enough structure to make its
theoretical properties interesting, but it is not much of a
programming language. In this chapter, we begin to close the gap
with real-world languages by introducing a number of familiar
features that have straightforward treatments at the level of
typing. *)
(** ** Numbers *)
(** Adding types, constants, and primitive operations for numbers is
easy -- just a matter of combining the [Types] and [Stlc]
chapters. *)
(** ** [let]-bindings *)
(** When writing a complex expression, it is often useful to give
names to some of its subexpressions: this avoids repetition and
often increases readability. Most languages provide one or more
ways of doing this. In OCaml (and Coq), for example, we can write
[let x=t1 in t2] to mean ``evaluate the expression [t1] and bind
the name [x] to the resulting value while evaluating [t2].''
Our [let]-binder follows OCaml's in choosing a call-by-value
evaluation order, where the [let]-bound term must be fully
evaluated before evaluation of the [let]-body can begin. The
typing rule [T_Let] tells us that the type of a [let] can be
calculated by calculating the type of the [let]-bound term,
extending the context with a binding with this type, and in this
enriched context calculating the type of the body, which is then
the type of the whole [let] expression.
At this point in the course, it's probably easier simply to look
at the rules defining this new feature as to wade through a lot of
english text conveying the same information. Here they are: *)
(** Syntax:
<<
t ::= Terms
| ... (other terms same as before)
| let x=t in t let-binding
>>
*)
(**
Reduction:
t1 ==> t1'
---------------------------------- (ST_Let1)
let x=t1 in t2 ==> let x=t1' in t2
---------------------------- (ST_LetValue)
let x=v1 in t2 ==> [x:=v1]t2
Typing:
Gamma |- t1 : T1 Gamma , x:T1 |- t2 : T2
-------------------------------------------- (T_Let)
Gamma |- let x=t1 in t2 : T2
*)
(** ** Pairs *)
(** Our functional programming examples in Coq have made
frequent use of _pairs_ of values. The type of such pairs is
called a _product type_.
The formalization of pairs is almost too simple to be worth
discussing. However, let's look briefly at the various parts of
the definition to emphasize the common pattern. *)
(** In Coq, the primitive way of extracting the components of a pair
is _pattern matching_. An alternative style is to take [fst] and
[snd] -- the first- and second-projection operators -- as
primitives. Just for fun, let's do our products this way. For
example, here's how we'd write a function that takes a pair of
numbers and returns the pair of their sum and difference:
<<
\x:Nat*Nat.
let sum = x.fst + x.snd in
let diff = x.fst - x.snd in
(sum,diff)
>>
*)
(** Adding pairs to the simply typed lambda-calculus, then, involves
adding two new forms of term -- pairing, written [(t1,t2)], and
projection, written [t.fst] for the first projection from [t] and
[t.snd] for the second projection -- plus one new type constructor,
[T1*T2], called the _product_ of [T1] and [T2]. *)
(** Syntax:
<<
t ::= Terms
| ...
| (t,t) pair
| t.fst first projection
| t.snd second projection
v ::= Values
| ...
| (v,v) pair value
T ::= Types
| ...
| T * T product type
>>
*)
(** For evaluation, we need several new rules specifying how pairs and
projection behave.
t1 ==> t1'
-------------------- (ST_Pair1)
(t1,t2) ==> (t1',t2)
t2 ==> t2'
-------------------- (ST_Pair2)
(v1,t2) ==> (v1,t2')
t1 ==> t1'
------------------ (ST_Fst1)
t1.fst ==> t1'.fst
------------------ (ST_FstPair)
(v1,v2).fst ==> v1
t1 ==> t1'
------------------ (ST_Snd1)
t1.snd ==> t1'.snd
------------------ (ST_SndPair)
(v1,v2).snd ==> v2
*)
(**
Rules [ST_FstPair] and [ST_SndPair] specify that, when a fully
evaluated pair meets a first or second projection, the result is
the appropriate component. The congruence rules [ST_Fst1] and
[ST_Snd1] allow reduction to proceed under projections, when the
term being projected from has not yet been fully evaluated.
[ST_Pair1] and [ST_Pair2] evaluate the parts of pairs: first the
left part, and then -- when a value appears on the left -- the right
part. The ordering arising from the use of the metavariables [v]
and [t] in these rules enforces a left-to-right evaluation
strategy for pairs. (Note the implicit convention that
metavariables like [v] and [v1] can only denote values.) We've
also added a clause to the definition of values, above, specifying
that [(v1,v2)] is a value. The fact that the components of a pair
value must themselves be values ensures that a pair passed as an
argument to a function will be fully evaluated before the function
body starts executing. *)
(** The typing rules for pairs and projections are straightforward.
Gamma |- t1 : T1 Gamma |- t2 : T2
--------------------------------------- (T_Pair)
Gamma |- (t1,t2) : T1*T2
Gamma |- t1 : T11*T12
--------------------- (T_Fst)
Gamma |- t1.fst : T11
Gamma |- t1 : T11*T12
--------------------- (T_Snd)
Gamma |- t1.snd : T12
*)
(** The rule [T_Pair] says that [(t1,t2)] has type [T1*T2] if [t1] has
type [T1] and [t2] has type [T2]. Conversely, the rules [T_Fst]
and [T_Snd] tell us that, if [t1] has a product type
[T11*T12] (i.e., if it will evaluate to a pair), then the types of
the projections from this pair are [T11] and [T12]. *)
(** ** Unit *)
(** Another handy base type, found especially in languages in
the ML family, is the singleton type [Unit]. *)
(** It has a single element -- the term constant [unit] (with a small
[u]) -- and a typing rule making [unit] an element of [Unit]. We
also add [unit] to the set of possible result values of
computations -- indeed, [unit] is the _only_ possible result of
evaluating an expression of type [Unit]. *)
(** Syntax:
<<
t ::= Terms
| ...
| unit unit value
v ::= Values
| ...
| unit unit
T ::= Types
| ...
| Unit Unit type
>>
Typing:
-------------------- (T_Unit)
Gamma |- unit : Unit
*)
(** It may seem a little strange to bother defining a type that
has just one element -- after all, wouldn't every computation
living in such a type be trivial?
This is a fair question, and indeed in the STLC the [Unit] type is
not especially critical (though we'll see two uses for it below).
Where [Unit] really comes in handy is in richer languages with
various sorts of _side effects_ -- e.g., assignment statements
that mutate variables or pointers, exceptions and other sorts of
nonlocal control structures, etc. In such languages, it is
convenient to have a type for the (trivial) result of an
expression that is evaluated only for its effect. *)
(** ** Sums *)
(** Many programs need to deal with values that can take two distinct
forms. For example, we might identify employees in an accounting
application using using _either_ their name _or_ their id number.
A search function might return _either_ a matching value _or_ an
error code.
These are specific examples of a binary _sum type_,
which describes a set of values drawn from exactly two given types, e.g.
<<
Nat + Bool
>>
*)
(** We create elements of these types by _tagging_ elements of
the component types. For example, if [n] is a [Nat] then [inl v]
is an element of [Nat+Bool]; similarly, if [b] is a [Bool] then
[inr b] is a [Nat+Bool]. The names of the tags [inl] and [inr]
arise from thinking of them as functions
<<
inl : Nat -> Nat + Bool
inr : Bool -> Nat + Bool
>>
that "inject" elements of [Nat] or [Bool] into the left and right
components of the sum type [Nat+Bool]. (But note that we don't
actually treat them as functions in the way we formalize them:
[inl] and [inr] are keywords, and [inl t] and [inr t] are primitive
syntactic forms, not function applications. This allows us to give
them their own special typing rules.) *)
(** In general, the elements of a type [T1 + T2] consist of the
elements of [T1] tagged with the token [inl], plus the elements of
[T2] tagged with [inr]. *)
(** One important usage of sums is signaling errors:
<<
div : Nat -> Nat -> (Nat + Unit) =
div =
\x:Nat. \y:Nat.
if iszero y then
inr unit
else
inl ...
>>
The type [Nat + Unit] above is in fact isomorphic to [option nat]
in Coq, and we've already seen how to signal errors with options. *)
(** To _use_ elements of sum types, we introduce a [case]
construct (a very simplified form of Coq's [match]) to destruct
them. For example, the following procedure converts a [Nat+Bool]
into a [Nat]: *)
(**
<<
getNat =
\x:Nat+Bool.
case x of
inl n => n
| inr b => if b then 1 else 0
>>
*)
(** More formally... *)
(** Syntax:
<<
t ::= Terms
| ...
| inl T t tagging (left)
| inr T t tagging (right)
| case t of case
inl x => t
| inr x => t
v ::= Values
| ...
| inl T v tagged value (left)
| inr T v tagged value (right)
T ::= Types
| ...
| T + T sum type
>>
*)
(** Evaluation:
t1 ==> t1'
---------------------- (ST_Inl)
inl T t1 ==> inl T t1'
t1 ==> t1'
---------------------- (ST_Inr)
inr T t1 ==> inr T t1'
t0 ==> t0'
------------------------------------------- (ST_Case)
case t0 of inl x1 => t1 | inr x2 => t2 ==>
case t0' of inl x1 => t1 | inr x2 => t2
---------------------------------------------- (ST_CaseInl)
case (inl T v0) of inl x1 => t1 | inr x2 => t2
==> [x1:=v0]t1
---------------------------------------------- (ST_CaseInr)
case (inr T v0) of inl x1 => t1 | inr x2 => t2
==> [x2:=v0]t2
*)
(** Typing:
Gamma |- t1 : T1
---------------------------- (T_Inl)
Gamma |- inl T2 t1 : T1 + T2
Gamma |- t1 : T2
---------------------------- (T_Inr)
Gamma |- inr T1 t1 : T1 + T2
Gamma |- t0 : T1+T2
Gamma , x1:T1 |- t1 : T
Gamma , x2:T2 |- t2 : T
--------------------------------------------------- (T_Case)
Gamma |- case t0 of inl x1 => t1 | inr x2 => t2 : T
We use the type annotation in [inl] and [inr] to make the typing
simpler, similarly to what we did for functions. *)
(** Without this extra
information, the typing rule [T_Inl], for example, would have to
say that, once we have shown that [t1] is an element of type [T1],
we can derive that [inl t1] is an element of [T1 + T2] for _any_
type T2. For example, we could derive both [inl 5 : Nat + Nat]
and [inl 5 : Nat + Bool] (and infinitely many other types).
This failure of uniqueness of types would mean that we cannot
build a typechecking algorithm simply by "reading the rules from
bottom to top" as we could for all the other features seen so far.
There are various ways to deal with this difficulty. One simple
one -- which we've adopted here -- forces the programmer to
explicitly annotate the "other side" of a sum type when performing
an injection. This is rather heavyweight for programmers (and so
real languages adopt other solutions), but it is easy to
understand and formalize. *)
(** ** Lists *)
(** The typing features we have seen can be classified into _base
types_ like [Bool], and _type constructors_ like [->] and [*] that
build new types from old ones. Another useful type constructor is
[List]. For every type [T], the type [List T] describes
finite-length lists whose elements are drawn from [T].
In principle, we could encode lists using pairs, sums and
_recursive_ types. But giving semantics to recursive types is
non-trivial. Instead, we'll just discuss the special case of lists
directly.
Below we give the syntax, semantics, and typing rules for lists.
Except for the fact that explicit type annotations are mandatory
on [nil] and cannot appear on [cons], these lists are essentially
identical to those we built in Coq. We use [lcase] to destruct
lists, to avoid dealing with questions like "what is the [head] of
the empty list?" *)
(** For example, here is a function that calculates the sum of
the first two elements of a list of numbers:
<<
\x:List Nat.
lcase x of nil -> 0
| a::x' -> lcase x' of nil -> a
| b::x'' -> a+b
>>
*)
(**
Syntax:
<<
t ::= Terms
| ...
| nil T
| cons t t
| lcase t of nil -> t | x::x -> t
v ::= Values
| ...
| nil T nil value
| cons v v cons value
T ::= Types
| ...
| List T list of Ts
>>
*)
(** Reduction:
t1 ==> t1'
-------------------------- (ST_Cons1)
cons t1 t2 ==> cons t1' t2
t2 ==> t2'
-------------------------- (ST_Cons2)
cons v1 t2 ==> cons v1 t2'
t1 ==> t1'
---------------------------------------- (ST_Lcase1)
(lcase t1 of nil -> t2 | xh::xt -> t3) ==>
(lcase t1' of nil -> t2 | xh::xt -> t3)
----------------------------------------- (ST_LcaseNil)
(lcase nil T of nil -> t2 | xh::xt -> t3)
==> t2
----------------------------------------------- (ST_LcaseCons)
(lcase (cons vh vt) of nil -> t2 | xh::xt -> t3)
==> [xh:=vh,xt:=vt]t3
*)
(** Typing:
----------------------- (T_Nil)
Gamma |- nil T : List T
Gamma |- t1 : T Gamma |- t2 : List T
----------------------------------------- (T_Cons)
Gamma |- cons t1 t2: List T
Gamma |- t1 : List T1
Gamma |- t2 : T
Gamma , h:T1, t:List T1 |- t3 : T
------------------------------------------------- (T_Lcase)
Gamma |- (lcase t1 of nil -> t2 | h::t -> t3) : T
*)
(** ** General Recursion *)
(** Another facility found in most programming languages (including
Coq) is the ability to define recursive functions. For example,
we might like to be able to define the factorial function like
this:
<<
fact = \x:Nat.
if x=0 then 1 else x * (fact (pred x)))
>>
But this would require quite a bit of work to formalize: we'd have
to introduce a notion of "function definitions" and carry around an
"environment" of such definitions in the definition of the [step]
relation. *)
(** Here is another way that is straightforward to formalize: instead
of writing recursive definitions where the right-hand side can
contain the identifier being defined, we can define a _fixed-point
operator_ that performs the "unfolding" of the recursive definition
in the right-hand side lazily during reduction.
<<
fact =
fix
(\f:Nat->Nat.
\x:Nat.
if x=0 then 1 else x * (f (pred x)))
>>
*)
(** The intuition is that the higher-order function [f] passed
to [fix] is a _generator_ for the [fact] function: if [fact] is
applied to a function that approximates the desired behavior of
[fact] up to some number [n] (that is, a function that returns
correct results on inputs less than or equal to [n]), then it
returns a better approximation to [fact] -- a function that returns
correct results for inputs up to [n+1]. Applying [fix] to this
generator returns its _fixed point_ -- a function that gives the
desired behavior for all inputs [n].
(The term "fixed point" has exactly the same sense as in ordinary
mathematics, where a fixed point of a function [f] is an input [x]
such that [f(x) = x]. Here, a fixed point of a function [F] of
type (say) [(Nat->Nat)->(Nat->Nat)] is a function [f] such that [F
f] is behaviorally equivalent to [f].) *)
(** Syntax:
<<
t ::= Terms
| ...
| fix t fixed-point operator
>>
Reduction:
t1 ==> t1'
------------------ (ST_Fix1)
fix t1 ==> fix t1'
F = \xf:T1.t2
----------------------- (ST_FixAbs)
fix F ==> [xf:=fix F]t2
Typing:
Gamma |- t1 : T1->T1
-------------------- (T_Fix)
Gamma |- fix t1 : T1
*)
(** Let's see how [ST_FixAbs] works by reducing [fact 3 = fix F 3],
where [F = (\f. \x. if x=0 then 1 else x * (f (pred x)))] (we are
omitting type annotations for brevity here).
<<
fix F 3
>>
[==>] [ST_FixAbs]
<<
(\x. if x=0 then 1 else x * (fix F (pred x))) 3
>>
[==>] [ST_AppAbs]
<<
if 3=0 then 1 else 3 * (fix F (pred 3))
>>
[==>] [ST_If0_Nonzero]
<<
3 * (fix F (pred 3))
>>
[==>] [ST_FixAbs + ST_Mult2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 3))
>>
[==>] [ST_PredNat + ST_Mult2 + ST_App2]
<<
3 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 2)
>>
[==>] [ST_AppAbs + ST_Mult2]
<<
3 * (if 2=0 then 1 else 2 * (fix F (pred 2)))
>>
[==>] [ST_If0_Nonzero + ST_Mult2]
<<
3 * (2 * (fix F (pred 2)))
>>
[==>] [ST_FixAbs + 2 x ST_Mult2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 2)))
>>
[==>] [ST_PredNat + 2 x ST_Mult2 + ST_App2]
<<
3 * (2 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 1))
>>
[==>] [ST_AppAbs + 2 x ST_Mult2]
<<
3 * (2 * (if 1=0 then 1 else 1 * (fix F (pred 1))))
>>
[==>] [ST_If0_Nonzero + 2 x ST_Mult2]
<<
3 * (2 * (1 * (fix F (pred 1))))
>>
[==>] [ST_FixAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) (pred 1))))
>>
[==>] [ST_PredNat + 3 x ST_Mult2 + ST_App2]
<<
3 * (2 * (1 * ((\x. if x=0 then 1 else x * (fix F (pred x))) 0)))
>>
[==>] [ST_AppAbs + 3 x ST_Mult2]
<<
3 * (2 * (1 * (if 0=0 then 1 else 0 * (fix F (pred 0)))))
>>
[==>] [ST_If0Zero + 3 x ST_Mult2]
<<
3 * (2 * (1 * 1))
>>
[==>] [ST_MultNats + 2 x ST_Mult2]
<<
3 * (2 * 1)
>>
[==>] [ST_MultNats + ST_Mult2]
<<
3 * 2
>>
[==>] [ST_MultNats]
<<
6
>>
*)
(** **** Exercise: 1 star, optional (halve_fix) *)
(** Translate this informal recursive definition into one using [fix]:
<<
halve =
\x:Nat.
if x=0 then 0
else if (pred x)=0 then 0
else 1 + (halve (pred (pred x))))
>>
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional (fact_steps) *)
(** Write down the sequence of steps that the term [fact 1] goes
through to reduce to a normal form (assuming the usual reduction
rules for arithmetic operations).
(* FILL IN HERE *)
[]
*)
(** The ability to form the fixed point of a function of type [T->T]
for any [T] has some surprising consequences. In particular, it
implies that _every_ type is inhabited by some term. To see this,
observe that, for every type [T], we can define the term
fix (\x:T.x)
By [T_Fix] and [T_Abs], this term has type [T]. By [ST_FixAbs]
it reduces to itself, over and over again. Thus it is an
_undefined element_ of [T].
More usefully, here's an example using [fix] to define a
two-argument recursive function:
<<
equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if m=0 then iszero n
else if n=0 then false
else eq (pred m) (pred n))
>>
And finally, here is an example where [fix] is used to define a
_pair_ of recursive functions (illustrating the fact that the type
[T1] in the rule [T_Fix] need not be a function type):
<<
evenodd =
fix
(\eo: (Nat->Bool * Nat->Bool).
let e = \n:Nat. if n=0 then true else eo.snd (pred n) in
let o = \n:Nat. if n=0 then false else eo.fst (pred n) in
(e,o))
even = evenodd.fst
odd = evenodd.snd
>>
*)
(* ###################################################################### *)
(** ** Records *)
(** As a final example of a basic extension of the STLC, let's
look briefly at how to define _records_ and their types.
Intuitively, records can be obtained from pairs by two kinds of
generalization: they are n-ary products (rather than just binary)
and their fields are accessed by _label_ (rather than position).
Conceptually, this extension is a straightforward generalization
of pairs and product types, but notationally it becomes a little
heavier; for this reason, we postpone its formal treatment to a
separate chapter ([Records]). *)
(** Records are not included in the extended exercise below, but
they will be useful to motivate the [Sub] chapter. *)
(** Syntax:
<<
t ::= Terms
| ...
| {i1=t1, ..., in=tn} record
| t.i projection
v ::= Values
| ...
| {i1=v1, ..., in=vn} record value
T ::= Types
| ...
| {i1:T1, ..., in:Tn} record type
>>
Intuitively, the generalization is pretty obvious. But it's worth
noticing that what we've actually written is rather informal: in
particular, we've written "[...]" in several places to mean "any
number of these," and we've omitted explicit mention of the usual
side-condition that the labels of a record should not contain
repetitions. *)
(** It is possible to devise informal notations that are
more precise, but these tend to be quite heavy and to obscure the
main points of the definitions. So we'll leave these a bit loose
here (they are informal anyway, after all) and do the work of
tightening things up elsewhere (in chapter [Records]). *)
(**
Reduction:
ti ==> ti'
------------------------------------ (ST_Rcd)
{i1=v1, ..., im=vm, in=ti, ...}
==> {i1=v1, ..., im=vm, in=ti', ...}
t1 ==> t1'
-------------- (ST_Proj1)
t1.i ==> t1'.i
------------------------- (ST_ProjRcd)
{..., i=vi, ...}.i ==> vi
Again, these rules are a bit informal. For example, the first rule
is intended to be read "if [ti] is the leftmost field that is not a
value and if [ti] steps to [ti'], then the whole record steps..."
In the last rule, the intention is that there should only be one
field called i, and that all the other fields must contain values. *)
(**
Typing:
Gamma |- t1 : T1 ... Gamma |- tn : Tn
-------------------------------------------------- (T_Rcd)
Gamma |- {i1=t1, ..., in=tn} : {i1:T1, ..., in:Tn}
Gamma |- t : {..., i:Ti, ...}
----------------------------- (T_Proj)
Gamma |- t.i : Ti
*)
(* ###################################################################### *)
(** *** Encoding Records (Optional) *)
(** There are several ways to make the above definitions precise.
- We can directly formalize the syntactic forms and inference
rules, staying as close as possible to the form we've given
them above. This is conceptually straightforward, and it's
probably what we'd want to do if we were building a real
compiler -- in particular, it will allow is to print error
messages in the form that programmers will find easy to
understand. But the formal versions of the rules will not be
pretty at all!
- We could look for a smoother way of presenting records -- for
example, a binary presentation with one constructor for the
empty record and another constructor for adding a single field
to an existing record, instead of a single monolithic
constructor that builds a whole record at once. This is the
right way to go if we are primarily interested in studying the
metatheory of the calculi with records, since it leads to
clean and elegant definitions and proofs. Chapter [Records]
shows how this can be done.
- Alternatively, if we like, we can avoid formalizing records
altogether, by stipulating that record notations are just
informal shorthands for more complex expressions involving
pairs and product types. We sketch this approach here.
First, observe that we can encode arbitrary-size tuples using
nested pairs and the [unit] value. To avoid overloading the pair
notation [(t1,t2)], we'll use curly braces without labels to write
down tuples, so [{}] is the empty tuple, [{5}] is a singleton
tuple, [{5,6}] is a 2-tuple (morally the same as a pair),
[{5,6,7}] is a triple, etc.
<<
{} ----> unit
{t1, t2, ..., tn} ----> (t1, trest)
where {t2, ..., tn} ----> trest
>>
Similarly, we can encode tuple types using nested product types:
<<
{} ----> Unit
{T1, T2, ..., Tn} ----> T1 * TRest
where {T2, ..., Tn} ----> TRest
>>
The operation of projecting a field from a tuple can be encoded
using a sequence of second projections followed by a first projection:
<<
t.0 ----> t.fst
t.(n+1) ----> (t.snd).n
>>
Next, suppose that there is some total ordering on record labels,
so that we can associate each label with a unique natural number.
This number is called the _position_ of the label. For example,
we might assign positions like this:
<<
LABEL POSITION
a 0
b 1
c 2
... ...
foo 1004
... ...
bar 10562
... ...
>>
We use these positions to encode record values as tuples (i.e., as
nested pairs) by sorting the fields according to their positions.
For example:
<<
{a=5, b=6} ----> {5,6}
{a=5, c=7} ----> {5,unit,7}
{c=7, a=5} ----> {5,unit,7}
{c=5, b=3} ----> {unit,3,5}
{f=8,c=5,a=7} ----> {7,unit,5,unit,unit,8}
{f=8,c=5} ----> {unit,unit,5,unit,unit,8}
>>
Note that each field appears in the position associated with its
label, that the size of the tuple is determined by the label with
the highest position, and that we fill in unused positions with
[unit].
We do exactly the same thing with record types:
<<
{a:Nat, b:Nat} ----> {Nat,Nat}
{c:Nat, a:Nat} ----> {Nat,Unit,Nat}
{f:Nat,c:Nat} ----> {Unit,Unit,Nat,Unit,Unit,Nat}
>>
Finally, record projection is encoded as a tuple projection from
the appropriate position:
<<
t.l ----> t.(position of l)
>>
It is not hard to check that all the typing rules for the original
"direct" presentation of records are validated by this
encoding. (The reduction rules are "almost validated" -- not
quite, because the encoding reorders fields.) *)
(** Of course, this encoding will not be very efficient if we
happen to use a record with label [bar]! But things are not
actually as bad as they might seem: for example, if we assume that
our compiler can see the whole program at the same time, we can
_choose_ the numbering of labels so that we assign small positions
to the most frequently used labels. Indeed, there are industrial
compilers that essentially do this! *)
(** *** Variants (Optional Reading) *)
(** Just as products can be generalized to records, sums can be
generalized to n-ary labeled types called _variants_. Instead of
[T1+T2], we can write something like [<l1:T1,l2:T2,...ln:Tn>]
where [l1],[l2],... are field labels which are used both to build
instances and as case arm labels.
These n-ary variants give us almost enough mechanism to build
arbitrary inductive data types like lists and trees from
scratch -- the only thing missing is a way to allow _recursion_ in
type definitions. We won't cover this here, but detailed
treatments can be found in many textbooks -- e.g., Types and
Programming Languages. *)
(* ###################################################################### *)
(** * Exercise: Formalizing the Extensions *)
(** **** Exercise: 4 stars, optional (STLC_extensions) *)
(** In this problem you will formalize a couple of the extensions
described above. We've provided the necessary additions to the
syntax of terms and types, and we've included a few examples that
you can test your definitions with to make sure they are working
as expected. You'll fill in the rest of the definitions and
extend all the proofs accordingly.
To get you started, we've provided implementations for:
- numbers
- pairs and units
- sums
- lists
You need to complete the implementations for:
- let (which involves binding)
- [fix]
A good strategy is to work on the extensions one at a time, in
multiple passes, rather than trying to work through the file from
start to finish in a single pass. For each definition or proof,
begin by reading carefully through the parts that are provided for
you, referring to the text in the [Stlc] chapter for high-level
intuitions and the embedded comments for detailed mechanics.
*)
Module STLCExtended.
(* ###################################################################### *)
(** *** Syntax and Operational Semantics *)
Inductive ty : Type :=
| TArrow : ty -> ty -> ty
| TNat : ty
| TUnit : ty
| TProd : ty -> ty -> ty
| TSum : ty -> ty -> ty
| TList : ty -> ty.
Tactic Notation "T_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "TArrow" | Case_aux c "TNat"
| Case_aux c "TProd" | Case_aux c "TUnit"
| Case_aux c "TSum" | Case_aux c "TList" ].
Inductive tm : Type :=
(* pure STLC *)
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
(* numbers *)
| tnat : nat -> tm
| tsucc : tm -> tm
| tpred : tm -> tm
| tmult : tm -> tm -> tm
| tif0 : tm -> tm -> tm -> tm
(* pairs *)
| tpair : tm -> tm -> tm
| tfst : tm -> tm
| tsnd : tm -> tm
(* units *)
| tunit : tm
(* let *)
| tlet : id -> tm -> tm -> tm
(* i.e., [let x = t1 in t2] *)
(* sums *)
| tinl : ty -> tm -> tm
| tinr : ty -> tm -> tm
| tcase : tm -> id -> tm -> id -> tm -> tm
(* i.e., [case t0 of inl x1 => t1 | inr x2 => t2] *)
(* lists *)
| tnil : ty -> tm
| tcons : tm -> tm -> tm
| tlcase : tm -> tm -> id -> id -> tm -> tm
(* i.e., [lcase t1 of | nil -> t2 | x::y -> t3] *)
(* fix *)
| tfix : tm -> tm.
(** Note that, for brevity, we've omitted booleans and instead
provided a single [if0] form combining a zero test and a
conditional. That is, instead of writing
<<
if x = 0 then ... else ...
>>
we'll write this:
<<
if0 x then ... else ...
>>
*)
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp" | Case_aux c "tabs"
| Case_aux c "tnat" | Case_aux c "tsucc" | Case_aux c "tpred"
| Case_aux c "tmult" | Case_aux c "tif0"
| Case_aux c "tpair" | Case_aux c "tfst" | Case_aux c "tsnd"
| Case_aux c "tunit" | Case_aux c "tlet"
| Case_aux c "tinl" | Case_aux c "tinr" | Case_aux c "tcase"
| Case_aux c "tnil" | Case_aux c "tcons" | Case_aux c "tlcase"
| Case_aux c "tfix" ].
(* ###################################################################### *)
(** *** Substitution *)
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar y =>
if eq_id_dec x y then s else t
| tabs y T t1 =>
tabs y T (if eq_id_dec x y then t1 else (subst x s t1))
| tapp t1 t2 =>
tapp (subst x s t1) (subst x s t2)
| tnat n =>
tnat n
| tsucc t1 =>
tsucc (subst x s t1)
| tpred t1 =>
tpred (subst x s t1)
| tmult t1 t2 =>
tmult (subst x s t1) (subst x s t2)
| tif0 t1 t2 t3 =>
tif0 (subst x s t1) (subst x s t2) (subst x s t3)
| tpair t1 t2 =>
tpair (subst x s t1) (subst x s t2)
| tfst t1 =>
tfst (subst x s t1)
| tsnd t1 =>
tsnd (subst x s t1)
| tunit => tunit
(* FILL IN HERE *)
| tinl T t1 =>
tinl T (subst x s t1)
| tinr T t1 =>
tinr T (subst x s t1)
| tcase t0 y1 t1 y2 t2 =>
tcase (subst x s t0)
y1 (if eq_id_dec x y1 then t1 else (subst x s t1))
y2 (if eq_id_dec x y2 then t2 else (subst x s t2))
| tnil T =>
tnil T
| tcons t1 t2 =>
tcons (subst x s t1) (subst x s t2)
| tlcase t1 t2 y1 y2 t3 =>
tlcase (subst x s t1) (subst x s t2) y1 y2
(if eq_id_dec x y1 then
t3
else if eq_id_dec x y2 then t3
else (subst x s t3))
(* FILL IN HERE *)
| _ => t (* ... and delete this line *)
end.
Notation "'[' x ':=' s ']' t" := (subst x s t) (at level 20).
(* ###################################################################### *)
(** *** Reduction *)
(** Next we define the values of our language. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T11 t12,
value (tabs x T11 t12)
(* Numbers are values: *)
| v_nat : forall n1,
value (tnat n1)
(* A pair is a value if both components are: *)
| v_pair : forall v1 v2,
value v1 ->
value v2 ->
value (tpair v1 v2)
(* A unit is always a value *)
| v_unit : value tunit
(* A tagged value is a value: *)
| v_inl : forall v T,
value v ->
value (tinl T v)
| v_inr : forall v T,
value v ->
value (tinr T v)
(* A list is a value iff its head and tail are values: *)
| v_lnil : forall T, value (tnil T)
| v_lcons : forall v1 vl,
value v1 ->
value vl ->
value (tcons v1 vl)
.
Hint Constructors value.
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T11 t12 v2,
value v2 ->
(tapp (tabs x T11 t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
(tapp t1 t2) ==> (tapp t1' t2)
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tapp v1 t2) ==> (tapp v1 t2')
(* nats *)
| ST_Succ1 : forall t1 t1',
t1 ==> t1' ->
(tsucc t1) ==> (tsucc t1')
| ST_SuccNat : forall n1,
(tsucc (tnat n1)) ==> (tnat (S n1))
| ST_Pred : forall t1 t1',
t1 ==> t1' ->
(tpred t1) ==> (tpred t1')
| ST_PredNat : forall n1,
(tpred (tnat n1)) ==> (tnat (pred n1))
| ST_Mult1 : forall t1 t1' t2,
t1 ==> t1' ->
(tmult t1 t2) ==> (tmult t1' t2)
| ST_Mult2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tmult v1 t2) ==> (tmult v1 t2')
| ST_MultNats : forall n1 n2,
(tmult (tnat n1) (tnat n2)) ==> (tnat (mult n1 n2))
| ST_If01 : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif0 t1 t2 t3) ==> (tif0 t1' t2 t3)
| ST_If0Zero : forall t2 t3,
(tif0 (tnat 0) t2 t3) ==> t2
| ST_If0Nonzero : forall n t2 t3,
(tif0 (tnat (S n)) t2 t3) ==> t3
(* pairs *)
| ST_Pair1 : forall t1 t1' t2,
t1 ==> t1' ->
(tpair t1 t2) ==> (tpair t1' t2)
| ST_Pair2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tpair v1 t2) ==> (tpair v1 t2')
| ST_Fst1 : forall t1 t1',
t1 ==> t1' ->
(tfst t1) ==> (tfst t1')
| ST_FstPair : forall v1 v2,
value v1 ->
value v2 ->
(tfst (tpair v1 v2)) ==> v1
| ST_Snd1 : forall t1 t1',
t1 ==> t1' ->
(tsnd t1) ==> (tsnd t1')
| ST_SndPair : forall v1 v2,
value v1 ->
value v2 ->
(tsnd (tpair v1 v2)) ==> v2
(* let *)
(* FILL IN HERE *)
(* sums *)
| ST_Inl : forall t1 t1' T,
t1 ==> t1' ->
(tinl T t1) ==> (tinl T t1')
| ST_Inr : forall t1 t1' T,
t1 ==> t1' ->
(tinr T t1) ==> (tinr T t1')
| ST_Case : forall t0 t0' x1 t1 x2 t2,
t0 ==> t0' ->
(tcase t0 x1 t1 x2 t2) ==> (tcase t0' x1 t1 x2 t2)
| ST_CaseInl : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinl T v0) x1 t1 x2 t2) ==> [x1:=v0]t1
| ST_CaseInr : forall v0 x1 t1 x2 t2 T,
value v0 ->
(tcase (tinr T v0) x1 t1 x2 t2) ==> [x2:=v0]t2
(* lists *)
| ST_Cons1 : forall t1 t1' t2,
t1 ==> t1' ->
(tcons t1 t2) ==> (tcons t1' t2)
| ST_Cons2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
(tcons v1 t2) ==> (tcons v1 t2')
| ST_Lcase1 : forall t1 t1' t2 x1 x2 t3,
t1 ==> t1' ->
(tlcase t1 t2 x1 x2 t3) ==> (tlcase t1' t2 x1 x2 t3)
| ST_LcaseNil : forall T t2 x1 x2 t3,
(tlcase (tnil T) t2 x1 x2 t3) ==> t2
| ST_LcaseCons : forall v1 vl t2 x1 x2 t3,
value v1 ->
value vl ->
(tlcase (tcons v1 vl) t2 x1 x2 t3) ==> (subst x2 vl (subst x1 v1 t3))
(* fix *)
(* FILL IN HERE *)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1" | Case_aux c "ST_App2"
| Case_aux c "ST_Succ1" | Case_aux c "ST_SuccNat"
| Case_aux c "ST_Pred1" | Case_aux c "ST_PredNat"
| Case_aux c "ST_Mult1" | Case_aux c "ST_Mult2"
| Case_aux c "ST_MultNats" | Case_aux c "ST_If01"
| Case_aux c "ST_If0Zero" | Case_aux c "ST_If0Nonzero"
| Case_aux c "ST_Pair1" | Case_aux c "ST_Pair2"
| Case_aux c "ST_Fst1" | Case_aux c "ST_FstPair"
| Case_aux c "ST_Snd1" | Case_aux c "ST_SndPair"
(* FILL IN HERE *)
| Case_aux c "ST_Inl" | Case_aux c "ST_Inr" | Case_aux c "ST_Case"
| Case_aux c "ST_CaseInl" | Case_aux c "ST_CaseInr"
| Case_aux c "ST_Cons1" | Case_aux c "ST_Cons2" | Case_aux c "ST_Lcase1"
| Case_aux c "ST_LcaseNil" | Case_aux c "ST_LcaseCons"
(* FILL IN HERE *)
].
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
Hint Constructors step.
(* ###################################################################### *)
(** *** Typing *)
Definition context := partial_map ty.
(** Next we define the typing rules. These are nearly direct
transcriptions of the inference rules shown above. *)
Reserved Notation "Gamma '|-' t '\in' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
(* Typing rules for proper terms *)
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma |- (tvar x) \in T
| T_Abs : forall Gamma x T11 T12 t12,
(extend Gamma x T11) |- t12 \in T12 ->
Gamma |- (tabs x T11 t12) \in (TArrow T11 T12)
| T_App : forall T1 T2 Gamma t1 t2,
Gamma |- t1 \in (TArrow T1 T2) ->
Gamma |- t2 \in T1 ->
Gamma |- (tapp t1 t2) \in T2
(* nats *)
| T_Nat : forall Gamma n1,
Gamma |- (tnat n1) \in TNat
| T_Succ : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tsucc t1) \in TNat
| T_Pred : forall Gamma t1,
Gamma |- t1 \in TNat ->
Gamma |- (tpred t1) \in TNat
| T_Mult : forall Gamma t1 t2,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in TNat ->
Gamma |- (tmult t1 t2) \in TNat
| T_If0 : forall Gamma t1 t2 t3 T1,
Gamma |- t1 \in TNat ->
Gamma |- t2 \in T1 ->
Gamma |- t3 \in T1 ->
Gamma |- (tif0 t1 t2 t3) \in T1
(* pairs *)
| T_Pair : forall Gamma t1 t2 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in T2 ->
Gamma |- (tpair t1 t2) \in (TProd T1 T2)
| T_Fst : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tfst t) \in T1
| T_Snd : forall Gamma t T1 T2,
Gamma |- t \in (TProd T1 T2) ->
Gamma |- (tsnd t) \in T2
(* unit *)
| T_Unit : forall Gamma,
Gamma |- tunit \in TUnit
(* let *)
(* FILL IN HERE *)
(* sums *)
| T_Inl : forall Gamma t1 T1 T2,
Gamma |- t1 \in T1 ->
Gamma |- (tinl T2 t1) \in (TSum T1 T2)
| T_Inr : forall Gamma t2 T1 T2,
Gamma |- t2 \in T2 ->
Gamma |- (tinr T1 t2) \in (TSum T1 T2)
| T_Case : forall Gamma t0 x1 T1 t1 x2 T2 t2 T,
Gamma |- t0 \in (TSum T1 T2) ->
(extend Gamma x1 T1) |- t1 \in T ->
(extend Gamma x2 T2) |- t2 \in T ->
Gamma |- (tcase t0 x1 t1 x2 t2) \in T
(* lists *)
| T_Nil : forall Gamma T,
Gamma |- (tnil T) \in (TList T)
| T_Cons : forall Gamma t1 t2 T1,
Gamma |- t1 \in T1 ->
Gamma |- t2 \in (TList T1) ->
Gamma |- (tcons t1 t2) \in (TList T1)
| T_Lcase : forall Gamma t1 T1 t2 x1 x2 t3 T2,
Gamma |- t1 \in (TList T1) ->
Gamma |- t2 \in T2 ->
(extend (extend Gamma x2 (TList T1)) x1 T1) |- t3 \in T2 ->
Gamma |- (tlcase t1 t2 x1 x2 t3) \in T2
(* fix *)
(* FILL IN HERE *)
where "Gamma '|-' t '\in' T" := (has_type Gamma t T).
Hint Constructors has_type.
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs" | Case_aux c "T_App"
| Case_aux c "T_Nat" | Case_aux c "T_Succ" | Case_aux c "T_Pred"
| Case_aux c "T_Mult" | Case_aux c "T_If0"
| Case_aux c "T_Pair" | Case_aux c "T_Fst" | Case_aux c "T_Snd"
| Case_aux c "T_Unit"
(* let *)
(* FILL IN HERE *)
| Case_aux c "T_Inl" | Case_aux c "T_Inr" | Case_aux c "T_Case"
| Case_aux c "T_Nil" | Case_aux c "T_Cons" | Case_aux c "T_Lcase"
(* fix *)
(* FILL IN HERE *)
].
(* ###################################################################### *)
(** ** Examples *)
(** This section presents formalized versions of the examples from
above (plus several more). The ones at the beginning focus on
specific features; you can use these to make sure your definition
of a given feature is reasonable before moving on to extending the
proofs later in the file with the cases relating to this feature.
The later examples require all the features together, so you'll
need to come back to these when you've got all the definitions
filled in. *)
Module Examples.
(** *** Preliminaries *)
(** First, let's define a few variable names: *)
Notation a := (Id 0).
Notation f := (Id 1).
Notation g := (Id 2).
Notation l := (Id 3).
Notation k := (Id 6).
Notation i1 := (Id 7).
Notation i2 := (Id 8).
Notation x := (Id 9).
Notation y := (Id 10).
Notation processSum := (Id 11).
Notation n := (Id 12).
Notation eq := (Id 13).
Notation m := (Id 14).
Notation evenodd := (Id 15).
Notation even := (Id 16).
Notation odd := (Id 17).
Notation eo := (Id 18).
(** Next, a bit of Coq hackery to automate searching for typing
derivations. You don't need to understand this bit in detail --
just have a look over it so that you'll know what to look for if
you ever find yourself needing to make custom extensions to
[auto].
The following [Hint] declarations say that, whenever [auto]
arrives at a goal of the form [(Gamma |- (tapp e1 e1) \in T)], it
should consider [eapply T_App], leaving an existential variable
for the middle type T1, and similar for [lcase]. That variable
will then be filled in during the search for type derivations for
[e1] and [e2]. We also include a hint to "try harder" when
solving equality goals; this is useful to automate uses of
[T_Var] (which includes an equality as a precondition). *)
Hint Extern 2 (has_type _ (tapp _ _) _) =>
eapply T_App; auto.
(* You'll want to uncomment the following line once
you've defined the [T_Lcase] constructor for the typing
relation: *)
(*
Hint Extern 2 (has_type _ (tlcase _ _ _ _ _) _) =>
eapply T_Lcase; auto.
*)
Hint Extern 2 (_ = _) => compute; reflexivity.
(** *** Numbers *)
Module Numtest.
(* if0 (pred (succ (pred (2 * 0))) then 5 else 6 *)
Definition test :=
tif0
(tpred
(tsucc
(tpred
(tmult
(tnat 2)
(tnat 0)))))
(tnat 5)
(tnat 6).
(** Remove the comment braces once you've implemented enough of the
definitions that you think this should work. *)
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof.
unfold test.
(* This typing derivation is quite deep, so we need to increase the
max search depth of [auto] from the default 5 to 10. *)
auto 10.
Qed.
Example numtest_reduces :
test ==>* tnat 5.
Proof.
unfold test. normalize.
Qed.
*)
End Numtest.
(** *** Products *)
Module Prodtest.
(* ((5,6),7).fst.snd *)
Definition test :=
tsnd
(tfst
(tpair
(tpair
(tnat 5)
(tnat 6))
(tnat 7))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End Prodtest.
(** *** [let] *)
Module LetTest.
(* let x = pred 6 in succ x *)
Definition test :=
tlet
x
(tpred (tnat 6))
(tsucc (tvar x)).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* tnat 6.
Proof. unfold test. normalize. Qed.
*)
End LetTest.
(** *** Sums *)
Module Sumtest1.
(* case (inl Nat 5) of
inl x => x
| inr y => y *)
Definition test :=
tcase (tinl TNat (tnat 5))
x (tvar x)
y (tvar y).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tnat 5).
Proof. unfold test. normalize. Qed.
*)
End Sumtest1.
Module Sumtest2.
(* let processSum =
\x:Nat+Nat.
case x of
inl n => n
inr n => if0 n then 1 else 0 in
(processSum (inl Nat 5), processSum (inr Nat 5)) *)
Definition test :=
tlet
processSum
(tabs x (TSum TNat TNat)
(tcase (tvar x)
n (tvar n)
n (tif0 (tvar n) (tnat 1) (tnat 0))))
(tpair
(tapp (tvar processSum) (tinl TNat (tnat 5)))
(tapp (tvar processSum) (tinr TNat (tnat 5)))).
(*
Example typechecks :
(@empty ty) |- test \in (TProd TNat TNat).
Proof. unfold test. eauto 15. Qed.
Example reduces :
test ==>* (tpair (tnat 5) (tnat 0)).
Proof. unfold test. normalize. Qed.
*)
End Sumtest2.
(** *** Lists *)
Module ListTest.
(* let l = cons 5 (cons 6 (nil Nat)) in
lcase l of
nil => 0
| x::y => x*x *)
Definition test :=
tlet l
(tcons (tnat 5) (tcons (tnat 6) (tnil TNat)))
(tlcase (tvar l)
(tnat 0)
x y (tmult (tvar x) (tvar x))).
(*
Example typechecks :
(@empty ty) |- test \in TNat.
Proof. unfold test. eauto 20. Qed.
Example reduces :
test ==>* (tnat 25).
Proof. unfold test. normalize. Qed.
*)
End ListTest.
(** *** [fix] *)
Module FixTest1.
(* fact := fix
(\f:nat->nat.
\a:nat.
if a=0 then 1 else a * (f (pred a))) *)
Definition fact :=
tfix
(tabs f (TArrow TNat TNat)
(tabs a TNat
(tif0
(tvar a)
(tnat 1)
(tmult
(tvar a)
(tapp (tvar f) (tpred (tvar a))))))).
(** (Warning: you may be able to typecheck [fact] but still have some
rules wrong!) *)
(*
Example fact_typechecks :
(@empty ty) |- fact \in (TArrow TNat TNat).
Proof. unfold fact. auto 10.
Qed.
*)
(*
Example fact_example:
(tapp fact (tnat 4)) ==>* (tnat 24).
Proof. unfold fact. normalize. Qed.
*)
End FixTest1.
Module FixTest2.
(* map :=
\g:nat->nat.
fix
(\f:[nat]->[nat].
\l:[nat].
case l of
| [] -> []
| x::l -> (g x)::(f l)) *)
Definition map :=
tabs g (TArrow TNat TNat)
(tfix
(tabs f (TArrow (TList TNat) (TList TNat))
(tabs l (TList TNat)
(tlcase (tvar l)
(tnil TNat)
a l (tcons (tapp (tvar g) (tvar a))
(tapp (tvar f) (tvar l))))))).
(*
(* Make sure you've uncommented the last [Hint Extern] above... *)
Example map_typechecks :
empty |- map \in
(TArrow (TArrow TNat TNat)
(TArrow (TList TNat)
(TList TNat))).
Proof. unfold map. auto 10. Qed.
Example map_example :
tapp (tapp map (tabs a TNat (tsucc (tvar a))))
(tcons (tnat 1) (tcons (tnat 2) (tnil TNat)))
==>* (tcons (tnat 2) (tcons (tnat 3) (tnil TNat))).
Proof. unfold map. normalize. Qed.
*)
End FixTest2.
Module FixTest3.
(* equal =
fix
(\eq:Nat->Nat->Bool.
\m:Nat. \n:Nat.
if0 m then (if0 n then 1 else 0)
else if0 n then 0
else eq (pred m) (pred n)) *)
Definition equal :=
tfix
(tabs eq (TArrow TNat (TArrow TNat TNat))
(tabs m TNat
(tabs n TNat
(tif0 (tvar m)
(tif0 (tvar n) (tnat 1) (tnat 0))
(tif0 (tvar n)
(tnat 0)
(tapp (tapp (tvar eq)
(tpred (tvar m)))
(tpred (tvar n)))))))).
(*
Example equal_typechecks :
(@empty ty) |- equal \in (TArrow TNat (TArrow TNat TNat)).
Proof. unfold equal. auto 10.
Qed.
*)
(*
Example equal_example1:
(tapp (tapp equal (tnat 4)) (tnat 4)) ==>* (tnat 1).
Proof. unfold equal. normalize. Qed.
*)
(*
Example equal_example2:
(tapp (tapp equal (tnat 4)) (tnat 5)) ==>* (tnat 0).
Proof. unfold equal. normalize. Qed.
*)
End FixTest3.
Module FixTest4.
(* let evenodd =
fix
(\eo: (Nat->Nat * Nat->Nat).
let e = \n:Nat. if0 n then 1 else eo.snd (pred n) in
let o = \n:Nat. if0 n then 0 else eo.fst (pred n) in
(e,o)) in
let even = evenodd.fst in
let odd = evenodd.snd in
(even 3, even 4)
*)
Definition eotest :=
tlet evenodd
(tfix
(tabs eo (TProd (TArrow TNat TNat) (TArrow TNat TNat))
(tpair
(tabs n TNat
(tif0 (tvar n)
(tnat 1)
(tapp (tsnd (tvar eo)) (tpred (tvar n)))))
(tabs n TNat
(tif0 (tvar n)
(tnat 0)
(tapp (tfst (tvar eo)) (tpred (tvar n))))))))
(tlet even (tfst (tvar evenodd))
(tlet odd (tsnd (tvar evenodd))
(tpair
(tapp (tvar even) (tnat 3))
(tapp (tvar even) (tnat 4))))).
(*
Example eotest_typechecks :
(@empty ty) |- eotest \in (TProd TNat TNat).
Proof. unfold eotest. eauto 30.
Qed.
*)
(*
Example eotest_example1:
eotest ==>* (tpair (tnat 0) (tnat 1)).
Proof. unfold eotest. normalize. Qed.
*)
End FixTest4.
End Examples.
(* ###################################################################### *)
(** ** Properties of Typing *)
(** The proofs of progress and preservation for this system are
essentially the same (though of course somewhat longer) as for the
pure simply typed lambda-calculus. *)
(* ###################################################################### *)
(** *** Progress *)
Theorem progress : forall t T,
empty |- t \in T ->
value t \/ exists t', t ==> t'.
Proof with eauto.
(* Theorem: Suppose empty |- t : T. Then either
1. t is a value, or
2. t ==> t' for some t'.
Proof: By induction on the given typing derivation. *)
intros t T Ht.
remember (@empty ty) as Gamma.
generalize dependent HeqGamma.
has_type_cases (induction Ht) Case; intros HeqGamma; subst.
Case "T_Var".
(* The final rule in the given typing derivation cannot be [T_Var],
since it can never be the case that [empty |- x : T] (since the
context is empty). *)
inversion H.
Case "T_Abs".
(* If the [T_Abs] rule was the last used, then [t = tabs x T11 t12],
which is a value. *)
left...
Case "T_App".
(* If the last rule applied was T_App, then [t = t1 t2], and we know
from the form of the rule that
[empty |- t1 : T1 -> T2]
[empty |- t2 : T1]
By the induction hypothesis, each of t1 and t2 either is a value
or can take a step. *)
right.
destruct IHHt1; subst...
SCase "t1 is a value".
destruct IHHt2; subst...
SSCase "t2 is a value".
(* If both [t1] and [t2] are values, then we know that
[t1 = tabs x T11 t12], since abstractions are the only values
that can have an arrow type. But
[(tabs x T11 t12) t2 ==> [x:=t2]t12] by [ST_AppAbs]. *)
inversion H; subst; try (solve by inversion).
exists (subst x t2 t12)...
SSCase "t2 steps".
(* If [t1] is a value and [t2 ==> t2'], then [t1 t2 ==> t1 t2']
by [ST_App2]. *)
inversion H0 as [t2' Hstp]. exists (tapp t1 t2')...
SCase "t1 steps".
(* Finally, If [t1 ==> t1'], then [t1 t2 ==> t1' t2] by [ST_App1]. *)
inversion H as [t1' Hstp]. exists (tapp t1' t2)...
Case "T_Nat".
left...
Case "T_Succ".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (S n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsucc t1')...
Case "T_Pred".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists (tnat (pred n1))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tpred t1')...
Case "T_Mult".
right.
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 is a value".
inversion H; subst; try solve by inversion.
inversion H0; subst; try solve by inversion.
exists (tnat (mult n1 n0))...
SSCase "t2 steps".
inversion H0 as [t2' Hstp].
exists (tmult t1 t2')...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tmult t1' t2)...
Case "T_If0".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
destruct n1 as [|n1'].
SSCase "n1=0".
exists t2...
SSCase "n1<>0".
exists t3...
SCase "t1 steps".
inversion H as [t1' H0].
exists (tif0 t1' t2 t3)...
Case "T_Pair".
destruct IHHt1...
SCase "t1 is a value".
destruct IHHt2...
SSCase "t2 steps".
right. inversion H0 as [t2' Hstp].
exists (tpair t1 t2')...
SCase "t1 steps".
right. inversion H as [t1' Hstp].
exists (tpair t1' t2)...
Case "T_Fst".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v1...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tfst t1')...
Case "T_Snd".
right.
destruct IHHt...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
exists v2...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tsnd t1')...
Case "T_Unit".
left...
(* let *)
(* FILL IN HERE *)
Case "T_Inl".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinl _ t1')... *)
Case "T_Inr".
destruct IHHt...
SCase "t1 steps".
right. inversion H as [t1' Hstp]...
(* exists (tinr _ t1')... *)
Case "T_Case".
right.
destruct IHHt1...
SCase "t0 is a value".
inversion H; subst; try solve by inversion.
SSCase "t0 is inl".
exists ([x1:=v]t1)...
SSCase "t0 is inr".
exists ([x2:=v]t2)...
SCase "t0 steps".
inversion H as [t0' Hstp].
exists (tcase t0' x1 t1 x2 t2)...
Case "T_Nil".
left...
Case "T_Cons".
destruct IHHt1...
SCase "head is a value".
destruct IHHt2...
SSCase "tail steps".
right. inversion H0 as [t2' Hstp].
exists (tcons t1 t2')...
SCase "head steps".
right. inversion H as [t1' Hstp].
exists (tcons t1' t2)...
Case "T_Lcase".
right.
destruct IHHt1...
SCase "t1 is a value".
inversion H; subst; try solve by inversion.
SSCase "t1=tnil".
exists t2...
SSCase "t1=tcons v1 vl".
exists ([x2:=vl]([x1:=v1]t3))...
SCase "t1 steps".
inversion H as [t1' Hstp].
exists (tlcase t1' t2 x1 x2 t3)...
(* fix *)
(* FILL IN HERE *)
Qed.
(* ###################################################################### *)
(** *** Context Invariance *)
Inductive appears_free_in : id -> tm -> Prop :=
| afi_var : forall x,
appears_free_in x (tvar x)
| afi_app1 : forall x t1 t2,
appears_free_in x t1 -> appears_free_in x (tapp t1 t2)
| afi_app2 : forall x t1 t2,
appears_free_in x t2 -> appears_free_in x (tapp t1 t2)
| afi_abs : forall x y T11 t12,
y <> x ->
appears_free_in x t12 ->
appears_free_in x (tabs y T11 t12)
(* nats *)
| afi_succ : forall x t,
appears_free_in x t ->
appears_free_in x (tsucc t)
| afi_pred : forall x t,
appears_free_in x t ->
appears_free_in x (tpred t)
| afi_mult1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tmult t1 t2)
| afi_mult2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tmult t1 t2)
| afi_if01 : forall x t1 t2 t3,
appears_free_in x t1 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if02 : forall x t1 t2 t3,
appears_free_in x t2 ->
appears_free_in x (tif0 t1 t2 t3)
| afi_if03 : forall x t1 t2 t3,
appears_free_in x t3 ->
appears_free_in x (tif0 t1 t2 t3)
(* pairs *)
| afi_pair1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tpair t1 t2)
| afi_pair2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tpair t1 t2)
| afi_fst : forall x t,
appears_free_in x t ->
appears_free_in x (tfst t)
| afi_snd : forall x t,
appears_free_in x t ->
appears_free_in x (tsnd t)
(* let *)
(* FILL IN HERE *)
(* sums *)
| afi_inl : forall x t T,
appears_free_in x t ->
appears_free_in x (tinl T t)
| afi_inr : forall x t T,
appears_free_in x t ->
appears_free_in x (tinr T t)
| afi_case0 : forall x t0 x1 t1 x2 t2,
appears_free_in x t0 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case1 : forall x t0 x1 t1 x2 t2,
x1 <> x ->
appears_free_in x t1 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
| afi_case2 : forall x t0 x1 t1 x2 t2,
x2 <> x ->
appears_free_in x t2 ->
appears_free_in x (tcase t0 x1 t1 x2 t2)
(* lists *)
| afi_cons1 : forall x t1 t2,
appears_free_in x t1 ->
appears_free_in x (tcons t1 t2)
| afi_cons2 : forall x t1 t2,
appears_free_in x t2 ->
appears_free_in x (tcons t1 t2)
| afi_lcase1 : forall x t1 t2 y1 y2 t3,
appears_free_in x t1 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase2 : forall x t1 t2 y1 y2 t3,
appears_free_in x t2 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
| afi_lcase3 : forall x t1 t2 y1 y2 t3,
y1 <> x ->
y2 <> x ->
appears_free_in x t3 ->
appears_free_in x (tlcase t1 t2 y1 y2 t3)
(* fix *)
(* FILL IN HERE *)
.
Hint Constructors appears_free_in.
Lemma context_invariance : forall Gamma Gamma' t S,
Gamma |- t \in S ->
(forall x, appears_free_in x t -> Gamma x = Gamma' x) ->
Gamma' |- t \in S.
Proof with eauto.
intros. generalize dependent Gamma'.
has_type_cases (induction H) Case;
intros Gamma' Heqv...
Case "T_Var".
apply T_Var... rewrite <- Heqv...
Case "T_Abs".
apply T_Abs... apply IHhas_type. intros y Hafi.
unfold extend.
destruct (eq_id_dec x y)...
Case "T_Mult".
apply T_Mult...
Case "T_If0".
apply T_If0...
Case "T_Pair".
apply T_Pair...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
eapply T_Case...
apply IHhas_type2. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x2 y)...
Case "T_Cons".
apply T_Cons...
Case "T_Lcase".
eapply T_Lcase... apply IHhas_type3. intros y Hafi.
unfold extend.
destruct (eq_id_dec x1 y)...
destruct (eq_id_dec x2 y)...
Qed.
Lemma free_in_context : forall x t T Gamma,
appears_free_in x t ->
Gamma |- t \in T ->
exists T', Gamma x = Some T'.
Proof with eauto.
intros x t T Gamma Hafi Htyp.
has_type_cases (induction Htyp) Case; inversion Hafi; subst...
Case "T_Abs".
destruct IHHtyp as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "left".
destruct IHHtyp2 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
SCase "right".
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx...
Case "T_Lcase".
clear Htyp1 IHHtyp1 Htyp2 IHHtyp2.
destruct IHHtyp3 as [T' Hctx]... exists T'.
unfold extend in Hctx.
rewrite neq_id in Hctx... rewrite neq_id in Hctx...
Qed.
(* ###################################################################### *)
(** *** Substitution *)
Lemma substitution_preserves_typing : forall Gamma x U v t S,
(extend Gamma x U) |- t \in S ->
empty |- v \in U ->
Gamma |- ([x:=v]t) \in S.
Proof with eauto.
(* Theorem: If Gamma,x:U |- t : S and empty |- v : U, then
Gamma |- [x:=v]t : S. *)
intros Gamma x U v t S Htypt Htypv.
generalize dependent Gamma. generalize dependent S.
(* Proof: By induction on the term t. Most cases follow directly
from the IH, with the exception of tvar and tabs.
The former aren't automatic because we must reason about how the
variables interact. *)
t_cases (induction t) Case;
intros S Gamma Htypt; simpl; inversion Htypt; subst...
Case "tvar".
simpl. rename i into y.
(* If t = y, we know that
[empty |- v : U] and
[Gamma,x:U |- y : S]
and, by inversion, [extend Gamma x U y = Some S]. We want to
show that [Gamma |- [x:=v]y : S].
There are two cases to consider: either [x=y] or [x<>y]. *)
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then we know that [U = S], and that [[x:=v]y = v].
So what we really must show is that if [empty |- v : U] then
[Gamma |- v : U]. We have already proven a more general version
of this theorem, called context invariance. *)
subst.
unfold extend in H1. rewrite eq_id in H1.
inversion H1; subst. clear H1.
eapply context_invariance...
intros x Hcontra.
destruct (free_in_context _ _ S empty Hcontra) as [T' HT']...
inversion HT'.
SCase "x<>y".
(* If [x <> y], then [Gamma y = Some S] and the substitution has no
effect. We can show that [Gamma |- y : S] by [T_Var]. *)
apply T_Var... unfold extend in H1. rewrite neq_id in H1...
Case "tabs".
rename i into y. rename t into T11.
(* If [t = tabs y T11 t0], then we know that
[Gamma,x:U |- tabs y T11 t0 : T11->T12]
[Gamma,x:U,y:T11 |- t0 : T12]
[empty |- v : U]
As our IH, we know that forall S Gamma,
[Gamma,x:U |- t0 : S -> Gamma |- [x:=v]t0 : S].
We can calculate that
[x:=v]t = tabs y T11 (if beq_id x y then t0 else [x:=v]t0)
And we must show that [Gamma |- [x:=v]t : T11->T12]. We know
we will do so using [T_Abs], so it remains to be shown that:
[Gamma,y:T11 |- if beq_id x y then t0 else [x:=v]t0 : T12]
We consider two cases: [x = y] and [x <> y].
*)
apply T_Abs...
destruct (eq_id_dec x y).
SCase "x=y".
(* If [x = y], then the substitution has no effect. Context
invariance shows that [Gamma,y:U,y:T11] and [Gamma,y:T11] are
equivalent. Since the former context shows that [t0 : T12], so
does the latter. *)
eapply context_invariance...
subst.
intros x Hafi. unfold extend.
destruct (eq_id_dec y x)...
SCase "x<>y".
(* If [x <> y], then the IH and context invariance allow us to show that
[Gamma,x:U,y:T11 |- t0 : T12] =>
[Gamma,y:T11,x:U |- t0 : T12] =>
[Gamma,y:T11 |- [x:=v]t0 : T12] *)
apply IHt. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y z)...
subst. rewrite neq_id...
(* let *)
(* FILL IN HERE *)
Case "tcase".
rename i into x1. rename i0 into x2.
eapply T_Case...
SCase "left arm".
destruct (eq_id_dec x x1).
SSCase "x = x1".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
SSCase "x <> x1".
apply IHt2. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x1 z)...
subst. rewrite neq_id...
SCase "right arm".
destruct (eq_id_dec x x2).
SSCase "x = x2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
SSCase "x <> x2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec x2 z)...
subst. rewrite neq_id...
Case "tlcase".
rename i into y1. rename i0 into y2.
eapply T_Lcase...
destruct (eq_id_dec x y1).
SCase "x=y1".
simpl.
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
SCase "x<>y1".
destruct (eq_id_dec x y2).
SSCase "x=y2".
eapply context_invariance...
subst.
intros z Hafi. unfold extend.
destruct (eq_id_dec y2 z)...
SSCase "x<>y2".
apply IHt3. eapply context_invariance...
intros z Hafi. unfold extend.
destruct (eq_id_dec y1 z)...
subst. rewrite neq_id...
destruct (eq_id_dec y2 z)...
subst. rewrite neq_id...
Qed.
(* ###################################################################### *)
(** *** Preservation *)
Theorem preservation : forall t t' T,
empty |- t \in T ->
t ==> t' ->
empty |- t' \in T.
Proof with eauto.
intros t t' T HT.
(* Theorem: If [empty |- t : T] and [t ==> t'], then [empty |- t' : T]. *)
remember (@empty ty) as Gamma. generalize dependent HeqGamma.
generalize dependent t'.
(* Proof: By induction on the given typing derivation. Many cases are
contradictory ([T_Var], [T_Abs]). We show just the interesting ones. *)
has_type_cases (induction HT) Case;
intros t' HeqGamma HE; subst; inversion HE; subst...
Case "T_App".
(* If the last rule used was [T_App], then [t = t1 t2], and three rules
could have been used to show [t ==> t']: [ST_App1], [ST_App2], and
[ST_AppAbs]. In the first two cases, the result follows directly from
the IH. *)
inversion HE; subst...
SCase "ST_AppAbs".
(* For the third case, suppose
[t1 = tabs x T11 t12]
and
[t2 = v2].
We must show that [empty |- [x:=v2]t12 : T2].
We know by assumption that
[empty |- tabs x T11 t12 : T1->T2]
and by inversion
[x:T1 |- t12 : T2]
We have already proven that substitution_preserves_typing and
[empty |- v2 : T1]
by assumption, so we are done. *)
apply substitution_preserves_typing with T1...
inversion HT1...
Case "T_Fst".
inversion HT...
Case "T_Snd".
inversion HT...
(* let *)
(* FILL IN HERE *)
Case "T_Case".
SCase "ST_CaseInl".
inversion HT1; subst.
eapply substitution_preserves_typing...
SCase "ST_CaseInr".
inversion HT1; subst.
eapply substitution_preserves_typing...
Case "T_Lcase".
SCase "ST_LcaseCons".
inversion HT1; subst.
apply substitution_preserves_typing with (TList T1)...
apply substitution_preserves_typing with T1...
(* fix *)
(* FILL IN HERE *)
Qed.
(** [] *)
End STLCExtended.
(* $Date: 2014-12-01 15:15:02 -0500 (Mon, 01 Dec 2014) $ *)
|
// megafunction wizard: %Altera PLL v14.1%
// GENERATION: XML
// pll.v
// Generated using ACDS version 14.1 186 at 2014.12.24.17:11:16
`timescale 1 ps / 1 ps
module pll (
input wire refclk, // refclk.clk
input wire rst, // reset.reset
output wire outclk_0 // outclk0.clk
);
pll_0002 pll_inst (
.refclk (refclk), // refclk.clk
.rst (rst), // reset.reset
.outclk_0 (outclk_0), // outclk0.clk
.locked () // (terminated)
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2014 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_pll" version="14.1" >
// Retrieval info: <generic name="debug_print_output" value="false" />
// Retrieval info: <generic name="debug_use_rbc_taf_method" value="false" />
// Retrieval info: <generic name="device_family" value="Cyclone V" />
// Retrieval info: <generic name="device" value="Unknown" />
// Retrieval info: <generic name="gui_device_speed_grade" value="1" />
// Retrieval info: <generic name="gui_pll_mode" value="Integer-N PLL" />
// Retrieval info: <generic name="gui_reference_clock_frequency" value="50.0" />
// Retrieval info: <generic name="gui_channel_spacing" value="0.0" />
// Retrieval info: <generic name="gui_operation_mode" value="normal" />
// Retrieval info: <generic name="gui_feedback_clock" value="Global Clock" />
// Retrieval info: <generic name="gui_fractional_cout" value="32" />
// Retrieval info: <generic name="gui_dsm_out_sel" value="1st_order" />
// Retrieval info: <generic name="gui_use_locked" value="false" />
// Retrieval info: <generic name="gui_en_adv_params" value="false" />
// Retrieval info: <generic name="gui_number_of_clocks" value="1" />
// Retrieval info: <generic name="gui_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_frac_multiply_factor" value="1" />
// Retrieval info: <generic name="gui_divide_factor_n" value="1" />
// Retrieval info: <generic name="gui_cascade_counter0" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency0" value="5.0" />
// Retrieval info: <generic name="gui_divide_factor_c0" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency0" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units0" value="ps" />
// Retrieval info: <generic name="gui_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg0" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift0" value="0" />
// Retrieval info: <generic name="gui_duty_cycle0" value="50" />
// Retrieval info: <generic name="gui_cascade_counter1" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency1" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c1" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency1" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units1" value="ps" />
// Retrieval info: <generic name="gui_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg1" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift1" value="0" />
// Retrieval info: <generic name="gui_duty_cycle1" value="50" />
// Retrieval info: <generic name="gui_cascade_counter2" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency2" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c2" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency2" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units2" value="ps" />
// Retrieval info: <generic name="gui_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg2" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift2" value="0" />
// Retrieval info: <generic name="gui_duty_cycle2" value="50" />
// Retrieval info: <generic name="gui_cascade_counter3" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency3" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c3" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency3" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units3" value="ps" />
// Retrieval info: <generic name="gui_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg3" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift3" value="0" />
// Retrieval info: <generic name="gui_duty_cycle3" value="50" />
// Retrieval info: <generic name="gui_cascade_counter4" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency4" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c4" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency4" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units4" value="ps" />
// Retrieval info: <generic name="gui_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg4" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift4" value="0" />
// Retrieval info: <generic name="gui_duty_cycle4" value="50" />
// Retrieval info: <generic name="gui_cascade_counter5" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency5" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c5" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency5" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units5" value="ps" />
// Retrieval info: <generic name="gui_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg5" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift5" value="0" />
// Retrieval info: <generic name="gui_duty_cycle5" value="50" />
// Retrieval info: <generic name="gui_cascade_counter6" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency6" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c6" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency6" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units6" value="ps" />
// Retrieval info: <generic name="gui_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg6" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift6" value="0" />
// Retrieval info: <generic name="gui_duty_cycle6" value="50" />
// Retrieval info: <generic name="gui_cascade_counter7" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency7" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c7" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency7" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units7" value="ps" />
// Retrieval info: <generic name="gui_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg7" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift7" value="0" />
// Retrieval info: <generic name="gui_duty_cycle7" value="50" />
// Retrieval info: <generic name="gui_cascade_counter8" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency8" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c8" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency8" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units8" value="ps" />
// Retrieval info: <generic name="gui_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg8" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift8" value="0" />
// Retrieval info: <generic name="gui_duty_cycle8" value="50" />
// Retrieval info: <generic name="gui_cascade_counter9" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency9" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c9" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency9" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units9" value="ps" />
// Retrieval info: <generic name="gui_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg9" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift9" value="0" />
// Retrieval info: <generic name="gui_duty_cycle9" value="50" />
// Retrieval info: <generic name="gui_cascade_counter10" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency10" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c10" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency10" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units10" value="ps" />
// Retrieval info: <generic name="gui_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg10" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift10" value="0" />
// Retrieval info: <generic name="gui_duty_cycle10" value="50" />
// Retrieval info: <generic name="gui_cascade_counter11" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency11" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c11" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency11" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units11" value="ps" />
// Retrieval info: <generic name="gui_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg11" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift11" value="0" />
// Retrieval info: <generic name="gui_duty_cycle11" value="50" />
// Retrieval info: <generic name="gui_cascade_counter12" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency12" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c12" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency12" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units12" value="ps" />
// Retrieval info: <generic name="gui_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg12" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift12" value="0" />
// Retrieval info: <generic name="gui_duty_cycle12" value="50" />
// Retrieval info: <generic name="gui_cascade_counter13" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency13" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c13" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency13" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units13" value="ps" />
// Retrieval info: <generic name="gui_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg13" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift13" value="0" />
// Retrieval info: <generic name="gui_duty_cycle13" value="50" />
// Retrieval info: <generic name="gui_cascade_counter14" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency14" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c14" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency14" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units14" value="ps" />
// Retrieval info: <generic name="gui_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg14" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift14" value="0" />
// Retrieval info: <generic name="gui_duty_cycle14" value="50" />
// Retrieval info: <generic name="gui_cascade_counter15" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency15" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c15" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency15" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units15" value="ps" />
// Retrieval info: <generic name="gui_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg15" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift15" value="0" />
// Retrieval info: <generic name="gui_duty_cycle15" value="50" />
// Retrieval info: <generic name="gui_cascade_counter16" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency16" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c16" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency16" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units16" value="ps" />
// Retrieval info: <generic name="gui_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg16" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift16" value="0" />
// Retrieval info: <generic name="gui_duty_cycle16" value="50" />
// Retrieval info: <generic name="gui_cascade_counter17" value="false" />
// Retrieval info: <generic name="gui_output_clock_frequency17" value="100.0" />
// Retrieval info: <generic name="gui_divide_factor_c17" value="1" />
// Retrieval info: <generic name="gui_actual_output_clock_frequency17" value="0 MHz" />
// Retrieval info: <generic name="gui_ps_units17" value="ps" />
// Retrieval info: <generic name="gui_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_phase_shift_deg17" value="0.0" />
// Retrieval info: <generic name="gui_actual_phase_shift17" value="0" />
// Retrieval info: <generic name="gui_duty_cycle17" value="50" />
// Retrieval info: <generic name="gui_pll_auto_reset" value="Off" />
// Retrieval info: <generic name="gui_pll_bandwidth_preset" value="Auto" />
// Retrieval info: <generic name="gui_en_reconf" value="false" />
// Retrieval info: <generic name="gui_en_dps_ports" value="false" />
// Retrieval info: <generic name="gui_en_phout_ports" value="false" />
// Retrieval info: <generic name="gui_phout_division" value="1" />
// Retrieval info: <generic name="gui_en_lvds_ports" value="false" />
// Retrieval info: <generic name="gui_mif_generate" value="false" />
// Retrieval info: <generic name="gui_enable_mif_dps" value="false" />
// Retrieval info: <generic name="gui_dps_cntr" value="C0" />
// Retrieval info: <generic name="gui_dps_num" value="1" />
// Retrieval info: <generic name="gui_dps_dir" value="Positive" />
// Retrieval info: <generic name="gui_refclk_switch" value="false" />
// Retrieval info: <generic name="gui_refclk1_frequency" value="100.0" />
// Retrieval info: <generic name="gui_switchover_mode" value="Automatic Switchover" />
// Retrieval info: <generic name="gui_switchover_delay" value="0" />
// Retrieval info: <generic name="gui_active_clk" value="false" />
// Retrieval info: <generic name="gui_clk_bad" value="false" />
// Retrieval info: <generic name="gui_enable_cascade_out" value="false" />
// Retrieval info: <generic name="gui_cascade_outclk_index" value="0" />
// Retrieval info: <generic name="gui_enable_cascade_in" value="false" />
// Retrieval info: <generic name="gui_pll_cascading_mode" value="Create an adjpllin signal to connect with an upstream PLL" />
// Retrieval info: </instance>
// IPFS_FILES : pll.vo
// RELATED_FILES: pll.v, pll_0002.v
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module barrier_fifo(
// Global signals
clock,
resetn, // use resetn to flush the fifo.
// User I/O
pull,
push,
in_data,
out_data,
valid,
fifo_ready,
// OpenCL runtime parameters
work_group_size);
parameter DATA_WIDTH = 32;
parameter MAXIMUM_WORK_GROUP_SIZE = 1024;
input clock;
input resetn;
input pull;
input push;
input [DATA_WIDTH-1:0] in_data;
output [DATA_WIDTH-1:0] out_data;
output valid;
output fifo_ready;
input [15:0] work_group_size;
function integer my_local_log;
input [31:0] value;
for (my_local_log=0; value>1; my_local_log=my_local_log+1)
value = value>>1;
endfunction
localparam LOG_MAX_WORK_GROUP_SIZE = my_local_log(MAXIMUM_WORK_GROUP_SIZE);
wire empty_signal, full_signal;
wire [LOG_MAX_WORK_GROUP_SIZE:0] used_words;
wire reset;
reg [LOG_MAX_WORK_GROUP_SIZE:0] elements_left_in_current_workgroup;
intermediate_data_fifo my_local_fifo(
.clock(clock),
.data(in_data),
.rdreq(pull & ~empty_signal & (|elements_left_in_current_workgroup)),
.sclr(reset),
.wrreq(push & ~full_signal),
.empty(empty_signal),
.full(full_signal),
.q(out_data),
.usedw(used_words[LOG_MAX_WORK_GROUP_SIZE-1:0]));
defparam my_local_fifo.DATA_WIDTH = DATA_WIDTH;
defparam my_local_fifo.NUM_WORDS = MAXIMUM_WORK_GROUP_SIZE;
defparam my_local_fifo.LOG_NUM_WORDS = LOG_MAX_WORK_GROUP_SIZE;
assign valid = ~empty_signal;
assign used_words[LOG_MAX_WORK_GROUP_SIZE] = full_signal;
always@(posedge clock)
begin
if (reset)
begin
elements_left_in_current_workgroup <= 'd0;
end
else
if ((~(|elements_left_in_current_workgroup)) && (
({1'b0, used_words} + {1'b0, push}) >= {1'b0, work_group_size}))
begin
// If the fifo contains more elements than the work group size (or is about to after this push),
// then at the next positive edge of the clock the fifo is ready to produce data.
elements_left_in_current_workgroup <= work_group_size[LOG_MAX_WORK_GROUP_SIZE:0];
end
if (pull & (|elements_left_in_current_workgroup))
begin
if ((~(|elements_left_in_current_workgroup[LOG_MAX_WORK_GROUP_SIZE:1])) && (elements_left_in_current_workgroup[0] == 1'b1) && (
({1'b0, used_words} + {1'b0, push} - {1'b0, pull}) >= {1'b0, work_group_size}))
begin
// If the fifo contains more elements than the work group size (or is about to after this push),
// then at the next positive edge of the clock the fifo is ready to produce data.
elements_left_in_current_workgroup <= work_group_size[LOG_MAX_WORK_GROUP_SIZE:0];
end
else
begin
// subtract 1 from the number of elements left for processing in the current workgroup.
elements_left_in_current_workgroup <= elements_left_in_current_workgroup - 1'b1;
end
end
end
assign fifo_ready = |elements_left_in_current_workgroup;
reg [3:0] synched_reset_n;
// Converting a resetn into a synchronous reset
always@(posedge clock or negedge resetn)
begin
if (~resetn)
synched_reset_n[0] <= 1'b0;
else
synched_reset_n[0] <= 1'b1;
end
always@(posedge clock)
synched_reset_n[3:1] <= synched_reset_n[2:0];
assign reset = ~synched_reset_n[3];
endmodule
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: scfifo
// ============================================================
// File Name: intermediate_data_fifo.v
// Megafunction Name(s):
// scfifo
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module intermediate_data_fifo (
clock,
data,
rdreq,
sclr,
wrreq,
empty,
full,
q,
usedw);
parameter DATA_WIDTH = 32;
parameter NUM_WORDS = 1024;
parameter LOG_NUM_WORDS = 10;
input clock;
input [DATA_WIDTH-1:0] data;
input rdreq;
input sclr;
input wrreq;
output empty;
output full;
output [DATA_WIDTH-1:0] q;
output [LOG_NUM_WORDS-1:0] usedw;
wire [LOG_NUM_WORDS-1:0] sub_wire0;
wire sub_wire1;
wire [DATA_WIDTH-1:0] sub_wire2;
wire sub_wire3;
wire [LOG_NUM_WORDS-1:0] usedw = sub_wire0[LOG_NUM_WORDS-1:0];
wire empty = sub_wire1;
wire [DATA_WIDTH-1:0] q = sub_wire2[DATA_WIDTH-1:0];
wire full = sub_wire3;
scfifo scfifo_component (
.rdreq (rdreq),
.sclr (sclr),
.clock (clock),
.wrreq (wrreq),
.data (data),
.usedw (sub_wire0),
.empty (sub_wire1),
.q (sub_wire2),
.full (sub_wire3)
// synopsys translate_off
,
.aclr (),
.almost_empty (),
.almost_full ()
// synopsys translate_on
);
defparam
scfifo_component.add_ram_output_register = "OFF",
scfifo_component.intended_device_family = "Cyclone II",
scfifo_component.lpm_numwords = NUM_WORDS,
scfifo_component.lpm_showahead = "ON",
scfifo_component.lpm_type = "scfifo",
scfifo_component.lpm_width = DATA_WIDTH,
scfifo_component.lpm_widthu = LOG_NUM_WORDS,
scfifo_component.overflow_checking = "OFF",
scfifo_component.underflow_checking = "OFF",
scfifo_component.use_eab = "ON";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "1"
// Retrieval info: PRIVATE: Clock NUMERIC "0"
// Retrieval info: PRIVATE: Depth NUMERIC "1024"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "1"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "8"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "8"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "1"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "1"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "OFF"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL data[7..0]
// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0]
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
// Retrieval info: USED_PORT: sclr 0 0 0 0 INPUT NODEFVAL sclr
// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
// Retrieval info: CONNECT: @sclr 0 0 0 0 sclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo_waveforms.html TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL intermediate_data_fifo_wave*.jpg FALSE
// Retrieval info: LIB_FILE: altera_mf
|
//////////////////////////////////////////////////////////////////////
//// ////
//// uart_wb_utilities.v ////
//// ////
//// This file is part of the "uart16550" project ////
//// http://www.opencores.org/projects/uart16550/ ////
//// ////
//// Author(s): ////
//// - [email protected] (Tadej Markovic) ////
//// ////
//// All additional information is avaliable in the README.txt ////
//// file. ////
//// ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 - 2004 authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
//
//
`include "uart_defines.v"
`include "uart_testbench_defines.v"
`include "wb_model_defines.v"
`include "timescale.v"
module uart_wb_utilities;
// Single read/write TASKs
//########################
// SINGLE_READ
task single_read;
input [`UART_ADDR_WIDTH-1:0] read_adr_i;
reg [3:0] read_sel_i;
reg `WBM_MODEL_READ_IN_TYPE read_stim;
reg `WBM_MODEL_READ_OUT_TYPE read_result;
integer master_waits;
integer slave_waits;
integer num_of_reads;
reg fast_b2b;
begin
read_sel_i = 4'hF;
testbench.i_wb_master_model.next_read_adr = read_adr_i;
testbench.i_wb_master_model.next_read_sel = read_sel_i;
testbench.i_wb_master_model.next_read_cti = 3'b000; // Clasic WB
testbench.i_wb_master_model.next_read_bte = $random; // Don't care hwen Clasic WB
master_waits = {$random} % 13;
slave_waits = 4;
num_of_reads = 1;
fast_b2b = 1'b0;
read_stim`WBM_MODEL_READ_WAITS = master_waits;
read_stim`WBM_MODEL_READ_ALLOWED_SLAVE_WAITS = slave_waits;
read_stim`WBM_MODEL_READ_LAST = (num_of_reads == 1);
read_stim`WBM_MODEL_READ_FAST_B2B = fast_b2b;
// Start read
testbench.i_wb_master_model.start_read(read_stim, read_result);
// ACK response
if (read_result`WBM_MODEL_READ_SLAVE_ACK !== 1'b1)
begin
`TC_ERROR("Wishbone master model did not receive expected transfer termination from the design.");
end
//
if (read_result`WBM_MODEL_READ_STIM_ERR !== 1'b0)
begin
`TC_ERROR("No reads done since design's wishbone slave interface responded with an error.");
end
//
if (read_result`WBM_MODEL_READ_DESIGN_ERR !== 1'b0)
begin
`TC_ERROR("Wishbone master model detected a design response error during single read access.");
end
end
endtask // single_read
// SINGLE_WRITE
task single_write;
input [`UART_ADDR_WIDTH-1:0] write_adr_i;
input [`UART_DATA_WIDTH-1:0] write_dat_i;
reg [3:0] write_sel_i;
reg `WBM_MODEL_WRITE_IN_TYPE write_stim;
reg `WBM_MODEL_WRITE_OUT_TYPE write_result;
integer master_waits;
integer slave_waits;
integer num_of_writes;
reg fast_b2b;
begin
write_sel_i = 4'hF;
testbench.i_wb_master_model.next_write_adr = write_adr_i;
testbench.i_wb_master_model.next_write_sel = write_sel_i;
testbench.i_wb_master_model.next_write_dat = write_dat_i;
testbench.i_wb_master_model.next_write_cti = 3'b000; // Clasic WB
testbench.i_wb_master_model.next_write_bte = $random; // Don't care hwen Clasic WB
master_waits = {$random} % 13;
slave_waits = 4;
num_of_writes = 1;
fast_b2b = 1'b0;
write_stim`WBM_MODEL_WRITE_WAITS = master_waits;
write_stim`WBM_MODEL_WRITE_ALLOWED_SLAVE_WAITS = slave_waits;
write_stim`WBM_MODEL_WRITE_LAST = (num_of_writes == 1);
write_stim`WBM_MODEL_WRITE_FAST_B2B = fast_b2b;
// Start write
testbench.i_wb_master_model.start_write(write_stim, write_result);
// ACK response
if (write_result`WBM_MODEL_WRITE_SLAVE_ACK !== 1'b1)
begin
`TC_ERROR("Wishbone master model did not receive expected transfer termination from the design.");
end
//
if (write_result`WBM_MODEL_WRITE_STIM_ERR !== 1'b0)
begin
`TC_ERROR("No writes done since wishbone master model reported an error.");
end
//
if (write_result`WBM_MODEL_WRITE_DESIGN_ERR !== 1'b0)
begin
`TC_ERROR("Wishbone master model detected a design response error during single write access.");
end
end
endtask // single_write
// Char read/write TASKs
//######################
// READ_CHAR
task read_char;
begin
if (testbench.lcr_reg[7] === 1'b1) // dlab == 1
begin
`UTILS_ERROR("READING of CHAR from RB Register NOT possible, since DLAB in LC Register is set.");
end
else
begin
`UTILS_MSG("READING of CHAR from UART's RB Register.");
single_read(`UART_REG_RB);
`UTILS_VAL1("Read RBR =", testbench.i_wb_master_model.read_dat);
end
end
endtask // read_char
// WRITE_CHAR
task write_char;
input [7:0] char_i;
begin
if (testbench.lcr_reg[7] === 1'b1) // dlab == 1
begin
`UTILS_ERROR("WRITING CHAR to TR Register NOT possible, since DLAB in LC Register is set.");
end
else
begin
`UTILS_MSG("WRITING CHAR to UART's TR Register.");
single_write(`UART_REG_TR, char_i);
`UTILS_VAL1("Write TRR =", testbench.i_wb_master_model.write_dat);
end
end
endtask // write_char
// Register read/write TASKs
//##########################
// READ_IER - adr 1
task read_ier;
begin
if (testbench.lcr_reg[7] === 1'b1) // dlab == 1
begin
`UTILS_ERROR("READING of IE Register NOT possible, since DLAB in LC Register is set.");
end
else
begin
`UTILS_MSG("READING UART's IE Register.");
single_read(`UART_REG_IE);
`UTILS_VAL1("Read IER =", testbench.i_wb_master_model.read_dat);
end
end
endtask // read_ier
// WRITE_IER - adr 1
task write_ier;
input [7:0] data_i;
begin
if (testbench.lcr_reg[7] === 1'b1) // dlab == 1
begin
`UTILS_ERROR("WRITING to IE Register NOT possible, since DLAB in LC Register is set.");
end
else
begin
`UTILS_MSG("WRITING UART's IE Register.");
single_write(`UART_REG_IE, data_i);
`UTILS_VAL1("Write IER =", testbench.i_wb_master_model.write_dat);
end
end
endtask // write_ier
// READ_IIR - adr 2
task read_iir;
begin
`UTILS_MSG("READING UART's II Register.");
single_read(`UART_REG_II);
`UTILS_VAL1("Read IIR =", testbench.i_wb_master_model.read_dat);
end
endtask // read_iir
// WRITE_FCR - adr 2
task write_fcr;
input [7:0] data_i;
begin
`UTILS_MSG("WRITING UART's FC Register.");
single_write(`UART_REG_FC, data_i);
`UTILS_VAL1("Write FCR =", testbench.i_wb_master_model.write_dat);
end
endtask // write_fcr
// READ_LCR - adr 3
task read_lcr;
begin
`UTILS_MSG("READING UART's LC Register.");
single_read(`UART_REG_LC);
`UTILS_VAL1("Read LCR =", testbench.i_wb_master_model.read_dat);
end
endtask // read_lcr
// WRITE_LCR - adr 3
task write_lcr;
input [7:0] data_i;
begin
`UTILS_MSG("WRITING UART's LC Register.");
single_write(`UART_REG_LC, data_i);
`UTILS_VAL1("Write LCR =", testbench.i_wb_master_model.write_dat);
end
endtask // write_lcr
// WRITE_MCR - adr 4
task write_mcr;
input [7:0] data_i;
begin
`UTILS_MSG("WRITING UART's MC Register.");
single_write(`UART_REG_MC, data_i);
`UTILS_VAL1("Write MCR =", testbench.i_wb_master_model.write_dat);
end
endtask // write_mcr
// READ_LSR - adr 5
task read_lsr;
begin
`UTILS_MSG("READING UART's LS Register.");
single_read(`UART_REG_LS);
`UTILS_VAL1("Read LSR =", testbench.i_wb_master_model.read_dat);
end
endtask // read_lsr
// READ_MSR - adr 6
task read_msr;
begin
`UTILS_MSG("READING UART's MS Register.");
single_read(`UART_REG_MS);
`UTILS_VAL1("Read MSR =", testbench.i_wb_master_model.read_dat);
end
endtask // read_msr
// READ_DLR - adr 0, 1
task read_dlr;
begin
if (testbench.lcr_reg[7] === 1'b0) // dlab == 0
begin
// Setting DLAB
`UTILS_MSG("DLAB in LC Register is going to be 1.");
`UTILS_VAL1("Current LCR =", testbench.lcr_reg);
write_lcr(testbench.lcr_reg | 8'h80);
// Reading DL Register
`UTILS_MSG("READING UART's DL Register [15:8].");
single_read(`UART_REG_DL2);
`UTILS_VAL1("Read DLR [15:8] =", testbench.i_wb_master_model.read_dat);
`UTILS_MSG("READING UART's DL Register [ 7:0].");
single_read(`UART_REG_DL1);
`UTILS_VAL1("Read DLR [ 7:0] =", testbench.i_wb_master_model.read_dat);
// Resetting DLAB
`UTILS_MSG("DLAB in LC Register is going to be 0.");
write_lcr(testbench.lcr_reg & 8'h7F);
end
else
begin
`UTILS_MSG("DLAB in LC Register is already 1.");
`UTILS_VAL1("Current LCR =", testbench.lcr_reg);
// Reading DL Register
`UTILS_MSG("READING UART's DL Register [15:8].");
single_read(`UART_REG_DL2);
`UTILS_VAL1("Read DLR [15:8] =", testbench.i_wb_master_model.read_dat);
`UTILS_MSG("READING UART's DL Register [ 7:0].");
single_read(`UART_REG_DL1);
`UTILS_VAL1("Read DLR [ 7:0] =", testbench.i_wb_master_model.read_dat);
end
end
endtask // read_dlr
// WRITE_DLR - adr 0, 1
task write_dlr;
input [15:0] data_i;
begin
if (testbench.lcr_reg[7] === 1'b0) // dlab == 0
begin
// Setting DLAB
`UTILS_MSG("DLAB in LC Register is going to be 1.");
`UTILS_VAL1("Current LCR =", testbench.lcr_reg);
write_lcr(testbench.lcr_reg | 8'h80);
// Writing DL Register
`UTILS_MSG("WRITING UART's DL Register [15:8].");
single_write(`UART_REG_DL2, data_i[15:8]);
`UTILS_VAL1("Write DLR [15:8] =", testbench.i_wb_master_model.write_dat);
`UTILS_MSG("WRITING UART's DL Register [ 7:0].");
single_write(`UART_REG_DL1, data_i[ 7:0]);
`UTILS_VAL1("Write DLR [ 7:0] =", testbench.i_wb_master_model.write_dat);
// Resetting DLAB
`UTILS_MSG("DLAB in LC Register is going to be 0.");
write_lcr(testbench.lcr_reg & 8'h7F);
end
else
begin
`UTILS_MSG("DLAB in LC Register is already 1.");
`UTILS_VAL1("Current LCR =", testbench.lcr_reg);
// Writing DL Register
`UTILS_MSG("WRITING UART's DL Register [15:8].");
single_write(`UART_REG_DL2, data_i[15:8]);
`UTILS_VAL1("Write DLR [15:8] =", testbench.i_wb_master_model.write_dat);
`UTILS_MSG("WRITING UART's DL Register [ 7:0].");
single_write(`UART_REG_DL1, data_i[ 7:0]);
`UTILS_VAL1("Write DLR [ 7:0] =", testbench.i_wb_master_model.write_dat);
end
end
endtask // write_dlr
endmodule |
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: ACP Transaction Checker
//
// Check for optimized ACP transactions and flag if they are broken.
//
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// atc
// aw_atc
// w_atc
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
module processing_system7_v5_5_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI side of checker.
// Range: 32.
parameter integer C_AXI_DATA_WIDTH = 64,
// Width of all DATA signals on SI and MI side of checker.
// Range: 64.
parameter integer C_AXI_AWUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_AXI_ARUSER_WIDTH = 1,
// Width of ARUSER signals.
// Range: >= 1.
parameter integer C_AXI_WUSER_WIDTH = 1,
// Width of WUSER signals.
// Range: >= 1.
parameter integer C_AXI_RUSER_WIDTH = 1,
// Width of RUSER signals.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1
// Width of BUSER signals.
// Range: >= 1.
)
(
// Global Signals
input wire ACLK,
input wire ARESETN,
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_AWADDR,
input wire [4-1:0] S_AXI_AWLEN,
input wire [3-1:0] S_AXI_AWSIZE,
input wire [2-1:0] S_AXI_AWBURST,
input wire [2-1:0] S_AXI_AWLOCK,
input wire [4-1:0] S_AXI_AWCACHE,
input wire [3-1:0] S_AXI_AWPROT,
input wire [C_AXI_AWUSER_WIDTH-1:0] S_AXI_AWUSER,
input wire S_AXI_AWVALID,
output wire S_AXI_AWREADY,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_WID,
input wire [C_AXI_DATA_WIDTH-1:0] S_AXI_WDATA,
input wire [C_AXI_DATA_WIDTH/8-1:0] S_AXI_WSTRB,
input wire S_AXI_WLAST,
input wire [C_AXI_WUSER_WIDTH-1:0] S_AXI_WUSER,
input wire S_AXI_WVALID,
output wire S_AXI_WREADY,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output wire [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
input wire [C_AXI_ADDR_WIDTH-1:0] S_AXI_ARADDR,
input wire [4-1:0] S_AXI_ARLEN,
input wire [3-1:0] S_AXI_ARSIZE,
input wire [2-1:0] S_AXI_ARBURST,
input wire [2-1:0] S_AXI_ARLOCK,
input wire [4-1:0] S_AXI_ARCACHE,
input wire [3-1:0] S_AXI_ARPROT,
input wire [C_AXI_ARUSER_WIDTH-1:0] S_AXI_ARUSER,
input wire S_AXI_ARVALID,
output wire S_AXI_ARREADY,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID,
output wire [C_AXI_DATA_WIDTH-1:0] S_AXI_RDATA,
output wire [2-1:0] S_AXI_RRESP,
output wire S_AXI_RLAST,
output wire [C_AXI_RUSER_WIDTH-1:0] S_AXI_RUSER,
output wire S_AXI_RVALID,
input wire S_AXI_RREADY,
// Master Interface Write Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_AWID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_AWADDR,
output wire [4-1:0] M_AXI_AWLEN,
output wire [3-1:0] M_AXI_AWSIZE,
output wire [2-1:0] M_AXI_AWBURST,
output wire [2-1:0] M_AXI_AWLOCK,
output wire [4-1:0] M_AXI_AWCACHE,
output wire [3-1:0] M_AXI_AWPROT,
output wire [C_AXI_AWUSER_WIDTH-1:0] M_AXI_AWUSER,
output wire M_AXI_AWVALID,
input wire M_AXI_AWREADY,
// Master Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_WID,
output wire [C_AXI_DATA_WIDTH-1:0] M_AXI_WDATA,
output wire [C_AXI_DATA_WIDTH/8-1:0] M_AXI_WSTRB,
output wire M_AXI_WLAST,
output wire [C_AXI_WUSER_WIDTH-1:0] M_AXI_WUSER,
output wire M_AXI_WVALID,
input wire M_AXI_WREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Master Interface Read Address Port
output wire [C_AXI_ID_WIDTH-1:0] M_AXI_ARID,
output wire [C_AXI_ADDR_WIDTH-1:0] M_AXI_ARADDR,
output wire [4-1:0] M_AXI_ARLEN,
output wire [3-1:0] M_AXI_ARSIZE,
output wire [2-1:0] M_AXI_ARBURST,
output wire [2-1:0] M_AXI_ARLOCK,
output wire [4-1:0] M_AXI_ARCACHE,
output wire [3-1:0] M_AXI_ARPROT,
output wire [C_AXI_ARUSER_WIDTH-1:0] M_AXI_ARUSER,
output wire M_AXI_ARVALID,
input wire M_AXI_ARREADY,
// Master Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_RID,
input wire [C_AXI_DATA_WIDTH-1:0] M_AXI_RDATA,
input wire [2-1:0] M_AXI_RRESP,
input wire M_AXI_RLAST,
input wire [C_AXI_RUSER_WIDTH-1:0] M_AXI_RUSER,
input wire M_AXI_RVALID,
output wire M_AXI_RREADY,
output wire ERROR_TRIGGER,
output wire [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
localparam C_FIFO_DEPTH_LOG = 4;
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Internal reset.
reg ARESET;
// AW->W command queue signals.
wire cmd_w_valid;
wire cmd_w_check;
wire [C_AXI_ID_WIDTH-1:0] cmd_w_id;
wire cmd_w_ready;
// W->B command queue signals.
wire cmd_b_push;
wire cmd_b_error;
wire [C_AXI_ID_WIDTH-1:0] cmd_b_id;
wire cmd_b_full;
wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr;
wire cmd_b_ready;
/////////////////////////////////////////////////////////////////////////////
// Handle Internal Reset
/////////////////////////////////////////////////////////////////////////////
always @ (posedge ACLK) begin
ARESET <= !ARESETN;
end
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
// Write Address Channel.
processing_system7_v5_5_aw_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_AWUSER_WIDTH (C_AXI_AWUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (Out)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Address Ports
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWADDR (S_AXI_AWADDR),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWLOCK (S_AXI_AWLOCK),
.S_AXI_AWCACHE (S_AXI_AWCACHE),
.S_AXI_AWPROT (S_AXI_AWPROT),
.S_AXI_AWUSER (S_AXI_AWUSER),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
// Master Interface Write Address Port
.M_AXI_AWID (M_AXI_AWID),
.M_AXI_AWADDR (M_AXI_AWADDR),
.M_AXI_AWLEN (M_AXI_AWLEN),
.M_AXI_AWSIZE (M_AXI_AWSIZE),
.M_AXI_AWBURST (M_AXI_AWBURST),
.M_AXI_AWLOCK (M_AXI_AWLOCK),
.M_AXI_AWCACHE (M_AXI_AWCACHE),
.M_AXI_AWPROT (M_AXI_AWPROT),
.M_AXI_AWUSER (M_AXI_AWUSER),
.M_AXI_AWVALID (M_AXI_AWVALID),
.M_AXI_AWREADY (M_AXI_AWREADY)
);
// Write Data channel.
processing_system7_v5_5_w_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_DATA_WIDTH (C_AXI_DATA_WIDTH),
.C_AXI_WUSER_WIDTH (C_AXI_WUSER_WIDTH)
) write_data_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_w_valid (cmd_w_valid),
.cmd_w_check (cmd_w_check),
.cmd_w_id (cmd_w_id),
.cmd_w_ready (cmd_w_ready),
// Command Interface (Out)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
// Slave Interface Write Data Ports
.S_AXI_WID (S_AXI_WID),
.S_AXI_WDATA (S_AXI_WDATA),
.S_AXI_WSTRB (S_AXI_WSTRB),
.S_AXI_WLAST (S_AXI_WLAST),
.S_AXI_WUSER (S_AXI_WUSER),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
// Master Interface Write Data Ports
.M_AXI_WID (M_AXI_WID),
.M_AXI_WDATA (M_AXI_WDATA),
.M_AXI_WSTRB (M_AXI_WSTRB),
.M_AXI_WLAST (M_AXI_WLAST),
.M_AXI_WUSER (M_AXI_WUSER),
.M_AXI_WVALID (M_AXI_WVALID),
.M_AXI_WREADY (M_AXI_WREADY)
);
// Write Response channel.
processing_system7_v5_5_b_atc #
(
.C_FAMILY (C_FAMILY),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_AXI_BUSER_WIDTH (C_AXI_BUSER_WIDTH),
.C_FIFO_DEPTH_LOG (C_FIFO_DEPTH_LOG)
) write_response_inst
(
// Global Signals
.ARESET (ARESET),
.ACLK (ACLK),
// Command Interface (In)
.cmd_b_push (cmd_b_push),
.cmd_b_error (cmd_b_error),
.cmd_b_id (cmd_b_id),
.cmd_b_full (cmd_b_full),
.cmd_b_addr (cmd_b_addr),
.cmd_b_ready (cmd_b_ready),
// Slave Interface Write Response Ports
.S_AXI_BID (S_AXI_BID),
.S_AXI_BRESP (S_AXI_BRESP),
.S_AXI_BUSER (S_AXI_BUSER),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
// Master Interface Write Response Ports
.M_AXI_BID (M_AXI_BID),
.M_AXI_BRESP (M_AXI_BRESP),
.M_AXI_BUSER (M_AXI_BUSER),
.M_AXI_BVALID (M_AXI_BVALID),
.M_AXI_BREADY (M_AXI_BREADY),
// Trigger detection
.ERROR_TRIGGER (ERROR_TRIGGER),
.ERROR_TRANSACTION_ID (ERROR_TRANSACTION_ID)
);
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
// Read Address Port
assign M_AXI_ARID = S_AXI_ARID;
assign M_AXI_ARADDR = S_AXI_ARADDR;
assign M_AXI_ARLEN = S_AXI_ARLEN;
assign M_AXI_ARSIZE = S_AXI_ARSIZE;
assign M_AXI_ARBURST = S_AXI_ARBURST;
assign M_AXI_ARLOCK = S_AXI_ARLOCK;
assign M_AXI_ARCACHE = S_AXI_ARCACHE;
assign M_AXI_ARPROT = S_AXI_ARPROT;
assign M_AXI_ARUSER = S_AXI_ARUSER;
assign M_AXI_ARVALID = S_AXI_ARVALID;
assign S_AXI_ARREADY = M_AXI_ARREADY;
// Read Data Port
assign S_AXI_RID = M_AXI_RID;
assign S_AXI_RDATA = M_AXI_RDATA;
assign S_AXI_RRESP = M_AXI_RRESP;
assign S_AXI_RLAST = M_AXI_RLAST;
assign S_AXI_RUSER = M_AXI_RUSER;
assign S_AXI_RVALID = M_AXI_RVALID;
assign M_AXI_RREADY = S_AXI_RREADY;
endmodule
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module system_top (
ddr_addr,
ddr_ba,
ddr_cas_n,
ddr_ck_n,
ddr_ck_p,
ddr_cke,
ddr_cs_n,
ddr_dm,
ddr_dq,
ddr_dqs_n,
ddr_dqs_p,
ddr_odt,
ddr_ras_n,
ddr_reset_n,
ddr_we_n,
fixed_io_ddr_vrn,
fixed_io_ddr_vrp,
fixed_io_mio,
fixed_io_ps_clk,
fixed_io_ps_porb,
fixed_io_ps_srstb,
gpio_bd,
hdmi_out_clk,
hdmi_vsync,
hdmi_hsync,
hdmi_data_e,
hdmi_data,
i2s_mclk,
i2s_bclk,
i2s_lrclk,
i2s_sdata_out,
i2s_sdata_in,
spdif,
iic_scl,
iic_sda,
iic_mux_scl,
iic_mux_sda,
otg_vbusoc);
inout [14:0] ddr_addr;
inout [ 2:0] ddr_ba;
inout ddr_cas_n;
inout ddr_ck_n;
inout ddr_ck_p;
inout ddr_cke;
inout ddr_cs_n;
inout [ 3:0] ddr_dm;
inout [31:0] ddr_dq;
inout [ 3:0] ddr_dqs_n;
inout [ 3:0] ddr_dqs_p;
inout ddr_odt;
inout ddr_ras_n;
inout ddr_reset_n;
inout ddr_we_n;
inout fixed_io_ddr_vrn;
inout fixed_io_ddr_vrp;
inout [53:0] fixed_io_mio;
inout fixed_io_ps_clk;
inout fixed_io_ps_porb;
inout fixed_io_ps_srstb;
inout [31:0] gpio_bd;
output hdmi_out_clk;
output hdmi_vsync;
output hdmi_hsync;
output hdmi_data_e;
output [15:0] hdmi_data;
output spdif;
output i2s_mclk;
output i2s_bclk;
output i2s_lrclk;
output i2s_sdata_out;
input i2s_sdata_in;
inout iic_scl;
inout iic_sda;
inout [ 1:0] iic_mux_scl;
inout [ 1:0] iic_mux_sda;
input otg_vbusoc;
// internal signals
wire [63:0] gpio_i;
wire [63:0] gpio_o;
wire [63:0] gpio_t;
wire [ 1:0] iic_mux_scl_i_s;
wire [ 1:0] iic_mux_scl_o_s;
wire iic_mux_scl_t_s;
wire [ 1:0] iic_mux_sda_i_s;
wire [ 1:0] iic_mux_sda_o_s;
wire iic_mux_sda_t_s;
// instantiations
ad_iobuf #(
.DATA_WIDTH(32)
) i_iobuf (
.dio_t(gpio_t[31:0]),
.dio_i(gpio_o[31:0]),
.dio_o(gpio_i[31:0]),
.dio_p(gpio_bd));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_scl (
.dio_t({iic_mux_scl_t_s, iic_mux_scl_t_s}),
.dio_i(iic_mux_scl_o_s),
.dio_o(iic_mux_scl_i_s),
.dio_p(iic_mux_scl));
ad_iobuf #(
.DATA_WIDTH(2)
) i_iic_mux_sda (
.dio_t({iic_mux_sda_t_s, iic_mux_sda_t_s}),
.dio_i(iic_mux_sda_o_s),
.dio_o(iic_mux_sda_i_s),
.dio_p(iic_mux_sda));
system_wrapper i_system_wrapper (
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_cas_n (ddr_cas_n),
.ddr_ck_n (ddr_ck_n),
.ddr_ck_p (ddr_ck_p),
.ddr_cke (ddr_cke),
.ddr_cs_n (ddr_cs_n),
.ddr_dm (ddr_dm),
.ddr_dq (ddr_dq),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dqs_p (ddr_dqs_p),
.ddr_odt (ddr_odt),
.ddr_ras_n (ddr_ras_n),
.ddr_reset_n (ddr_reset_n),
.ddr_we_n (ddr_we_n),
.fixed_io_ddr_vrn (fixed_io_ddr_vrn),
.fixed_io_ddr_vrp (fixed_io_ddr_vrp),
.fixed_io_mio (fixed_io_mio),
.fixed_io_ps_clk (fixed_io_ps_clk),
.fixed_io_ps_porb (fixed_io_ps_porb),
.fixed_io_ps_srstb (fixed_io_ps_srstb),
.gpio_i (gpio_i),
.gpio_o (gpio_o),
.gpio_t (gpio_t),
.hdmi_data (hdmi_data),
.hdmi_data_e (hdmi_data_e),
.hdmi_hsync (hdmi_hsync),
.hdmi_out_clk (hdmi_out_clk),
.hdmi_vsync (hdmi_vsync),
.i2s_bclk (i2s_bclk),
.i2s_lrclk (i2s_lrclk),
.i2s_mclk (i2s_mclk),
.i2s_sdata_in (i2s_sdata_in),
.i2s_sdata_out (i2s_sdata_out),
.iic_fmc_scl_io (iic_scl),
.iic_fmc_sda_io (iic_sda),
.iic_mux_scl_i (iic_mux_scl_i_s),
.iic_mux_scl_o (iic_mux_scl_o_s),
.iic_mux_scl_t (iic_mux_scl_t_s),
.iic_mux_sda_i (iic_mux_sda_i_s),
.iic_mux_sda_o (iic_mux_sda_o_s),
.iic_mux_sda_t (iic_mux_sda_t_s),
.ps_intr_00 (1'b0),
.ps_intr_01 (1'b0),
.ps_intr_02 (1'b0),
.ps_intr_03 (1'b0),
.ps_intr_04 (1'b0),
.ps_intr_05 (1'b0),
.ps_intr_06 (1'b0),
.ps_intr_07 (1'b0),
.ps_intr_08 (1'b0),
.ps_intr_09 (1'b0),
.ps_intr_10 (1'b0),
.ps_intr_12 (1'b0),
.ps_intr_13 (1'b0),
.otg_vbusoc (otg_vbusoc),
.spdif (spdif));
endmodule
// ***************************************************************************
// ***************************************************************************
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012 by Jeremy Bennett.
// SPDX-License-Identifier: CC0-1.0
// see bug 591
package pkg1;
parameter PARAM2 = 16;
parameter PARAM3 = 16;
endpackage : pkg1
package pkg10;
import pkg1::*;
import pkg1::*; // Ignore if already
`ifdef T_PACKAGE_EXPORT
export *::*; // Not supported on all simulators
`endif
parameter PARAM1 = 8;
endpackage
package pkg11;
import pkg10::*;
endpackage
package pkg20;
import pkg1::*;
`ifdef T_PACKAGE_EXPORT
export pkg1::*;
`endif
parameter PARAM1 = 8;
endpackage
package pkg21;
import pkg20::*;
endpackage
package pkg30;
import pkg1::*;
`ifdef T_PACKAGE_EXPORT
export pkg1::PARAM2;
export pkg1::PARAM3;
`endif
`ifdef T_PACKAGE_EXPORT_BAD
export pkg1::BAD_DOES_NOT_EXIST;
`endif
parameter PARAM1 = 8;
endpackage
package pkg31;
import pkg30::*;
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [pkg11::PARAM1 : 0] bus11;
reg [pkg11::PARAM2 : 0] bus12;
reg [pkg11::PARAM3 : 0] bus13;
reg [pkg21::PARAM1 : 0] bus21;
reg [pkg21::PARAM2 : 0] bus22;
reg [pkg21::PARAM3 : 0] bus23;
reg [pkg31::PARAM1 : 0] bus31;
reg [pkg31::PARAM2 : 0] bus32;
reg [pkg31::PARAM3 : 0] bus33;
initial begin
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// $Id: c_extractor.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// module for extracting a set of bits from an input word (result is
// concatenation of these bits)
module c_extractor
(data_in, data_out);
// width of input word
parameter width = 32;
function integer pop_count(input [0:width-1] argument);
integer i;
begin
pop_count = 0;
for(i = 0; i < width; i = i + 1)
pop_count = pop_count + argument[i];
end
endfunction
// mask specifying which bits to extract
parameter [0:width-1] mask = {width{1'b1}};
// width of result
localparam new_width = pop_count(mask);
// input word
input [0:width-1] data_in;
// result
output [0:new_width-1] data_out;
reg [0:new_width-1] data_out;
reg unused;
integer idx1, idx2;
always @(data_in)
begin
unused = 1'b0;
idx2 = 0;
for(idx1 = 0; idx1 < width; idx1 = idx1 + 1)
if(mask[idx1] == 1'b1)
begin
data_out[idx2] = data_in[idx1];
idx2 = idx2 + 1;
end
else
begin
unused = unused | data_in[idx1];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__OR4BB_4_V
`define SKY130_FD_SC_LS__OR4BB_4_V
/**
* or4bb: 4-input OR, first two inputs inverted.
*
* Verilog wrapper for or4bb with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__or4bb.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_4 (
X ,
A ,
B ,
C_N ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input C_N ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__or4bb_4 (
X ,
A ,
B ,
C_N,
D_N
);
output X ;
input A ;
input B ;
input C_N;
input D_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__or4bb base (
.X(X),
.A(A),
.B(B),
.C_N(C_N),
.D_N(D_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__OR4BB_4_V
|
`timescale 1ns/1ns
// TODO: clean this up. it's pretty old.
module i2c_master
#(parameter LENWIDTH = 4)
( input c, // clock
// user interface
input req,
input [6:0] addr,
input [LENWIDTH-1:0] len, // # of bytes to xfer
input we,
output ack,
output err,
input [31:0] din,
output din_ack,
output [31:0] dout,
output dout_dv,
output dout_eop,
// i2c interface
inout sda,
inout scl
);
`include "clog2.inc"
localparam integer SCL_QUAD = 125000 / (4 * 400); // 78125
localparam integer SCL_WIDTH = 17;
// generate scl
wire [SCL_WIDTH-1:0] scl_cnt;
wire scl_match = (scl_cnt == (SCL_QUAD-1));
wire [SCL_WIDTH-1:0] scl_cnt_p1 = scl_match ? 0 : scl_cnt + 1;
wire pause_scl;
r #(SCL_WIDTH) scl_cnt_r
(.c(c), .rst(pause_scl), .d(scl_cnt_p1), .q(scl_cnt));
wire [1:0] scl_q; // quadrant of the SCL waveform that we're in
r #(2) scl_r
(.c(c), rst(1'b0), .en(scl_match & ~pause_scl), .d(scl_q + 2'h1), .q(scl_q));
// generate a pulse on the rising and falling edges of SCL
wire scl_0 = scl_match & scl_q == 2'b01;
wire scl_180 = scl_match & scl_q == 2'b11;
wire scl_270 = scl_match & scl_q == 2'b00;
wire scl_90_int = scl_match & scl_q == 2'b10;
wire scl_90 = scl_90_int & scl;
assign pause_scl = scl_90_int & ~scl;
localparam SW = 4;
localparam CTRL_BITS = 9;
localparam ST_IDLE = 4'd0;
localparam ST_START = 4'd1;
localparam ST_ADDR = 4'd2;
localparam ST_AACK = 4'd3;
localparam ST_TXD = 4'd4;
localparam ST_TXACK = 4'd5;
localparam ST_RXD = 4'd6;
localparam ST_RXACK = 4'd7;
localparam ST_STOP = 4'd8;
localparam ST_ERROR = 4'd9;
// ctrl[0] = sda state, 0 = drive it low, 1 = let float high
// ctrl[1] = clear state counter
// ctrl[2] = increment state counter
// ctrl[3] = unused
// ctrl[4] = decrement word counter
// ctrl[5] = read sda into rx_data
// ctrl[7:6] = next_shift sel
// ctrl[8] = clear shift
reg [SW+CTRL_BITS-1:0] ctrl;
wire [SW-1:0] state;
wire [SW-1:0] next_state = ctrl[SW+CTRL_BITS-1:CTRL_BITS];
r #(SW) state_r(.c(c), rst(1'b0), .en(1'b1), .d(next_state), .q(state));
wire next_ack = (next_state == ST_STOP); // probably could be earlier?
r #(1) ack_r(.c(clk), .rst(1'b1), .en(1'b1), .d(next_ack), .q(ack));
assign sda = ctrl[0] ? 1'bz : 1'b0;
wire [3:0] cnt; // generic state counter, use for a bit count, status, etc.
r #(4) cnt_r(.c(c), .rst(ctrl[1]), .d(ctrl[2] ? cnt+4'h1 : cnt), .q(cnt));
// latch whether we are doing a read or write
wire we_reg_w;
r #(1) we_reg(.c(c), .rst(1'b0), .d(we), .en(req && !ack), .q(we_reg_w));
assign err = state == ST_ERROR;
wire [LENWIDTH-1:0] word, word_next;
assign word_next = word + 1;
r #(LENWIDTH) word_r
(.c(c), .d(word_next), .rst(state == ST_IDLE), .en(ctrl[4]), .q(word));
wire last_word = (word == len);
wire [0:31] tx_data;
wire new_tx_data = (state == ST_IDLE) | (word[1:0] == 2'h3);
wire [0:31] next_tx_data = new_tx_data ? din : {tx_data[8:31], 8'b0};
r #(32) tx_data_reg
(.c(c), .d(next_tx_data), .rst(1'b0), .en(ctrl[4]), .q(tx_data));
assign din_ack = new_tx_data & ctrl[4] & (we | we_reg_w);
wire [31:0] rx_data;
r #(32) rx_data_reg
(.c(c), .d({rx_data[30:0], sda}), .rst(1'b0), .en(ctrl[5]), .q(rx_data));
assign dout = rx_data;
wire next_dout_dv = (word[1:0] == 2'h3) & ctrl[4] & (state == ST_RXD);
wire dout_dv_int;
r #(1) dout_dv_reg
(.c(c), .d(next_dout_dv), .rst(1'b0), .en(1'b1), .q(dout_dv_int));
wire last_word_d1;
r #(1) lw_reg(.c(c), .d(last_word), .rst(1'b0), .en(1'b1), .q(last_word_d1));
wire last_dout = last_word & ~last_word_d1 & ~we_reg_w;
assign dout_dv = dout_dv_int | last_dout;
assign dout_eop = last_word;
wire [7:0] shift, shift_next;
gmux #(.DWIDTH(8), .SELWIDTH(2)) shift_sel
(.d({addr, ~we_reg_w, tx_data[0:7], shift[6:0], 1'b0, shift}),
.sel(ctrl[7:6]), .z(shift_next));
r #(8) shift_r(.c(c), .d(shift_next), .rst(ctrl[8]), .en(1'b1), .q(shift));
always @* begin
case (state)
ST_IDLE:
if (req) ctrl = {ST_START, 3'b100, 6'b010011};
else ctrl = {ST_IDLE , 3'b100, 6'b000001};
ST_ERROR:
if (req) ctrl = {ST_START, 3'b100, 6'b000011};
else ctrl = {ST_ERROR, 3'b100, 6'b000001};
ST_START:
if (~cnt[0]) // haven't triggered the pulldown yet
if (scl_90) ctrl = {ST_START, 3'b000, 6'b000100}; // start hold down
else ctrl = {ST_START, 3'b000, 6'b000001}; // wait for 90 degrees
else
if (scl_270) ctrl = {ST_ADDR, 3'b011, 6'b000010}; // done. move along.
else ctrl = {ST_START, 3'b000, 6'b000000}; // keep it down
ST_ADDR:
if (scl_270)
if (&cnt[2:0]) ctrl = {ST_AACK, 3'b001, 6'b000001};
else ctrl = {ST_ADDR, 3'b001, 5'b00010, shift[7]};
else ctrl = {ST_ADDR, 3'b000, 5'b00000, shift[7]};
ST_AACK: // in the address phase, we are the transmitter; check for rx ack
if (scl_90)
if (sda) ctrl = {ST_ERROR, 3'b000, 6'b000001}; // rx should pull down
else ctrl = {ST_AACK , 3'b010, 6'b000001};
else if (scl_270) ctrl = {(we_reg_w ? ST_TXD : ST_RXD), 3'b000, 6'b000011};
else ctrl = {ST_AACK , 3'b000, 6'b000001};
ST_TXD:
if (scl_270)
if (&cnt[2:0]) ctrl = {ST_TXACK, 3'b001, 6'b000001};
else ctrl = {ST_TXD , 3'b001, 5'b00010, shift[7]};
else ctrl = {ST_TXD , 3'b000, 5'b00000, shift[7]};
ST_TXACK:
if (scl_90)
if (sda) ctrl = {ST_ERROR, 3'b000, 6'b000001}; // rx should pull down
else ctrl = {ST_TXACK, 3'b000, 6'b010001};
else if (scl_270) ctrl = {last_word ? ST_STOP : ST_TXD, 3'b010, 6'b000011};
else ctrl = {ST_TXACK, 3'b000, 6'b000001};
ST_RXD:
if (scl_90) // sample midway through the clock high time
if (&cnt[2:0]) ctrl = {ST_RXACK, 3'b000, 6'b110011};
else ctrl = {ST_RXD , 3'b000, 6'b100101};
else ctrl = {ST_RXD , 3'b000, 6'b000001};
ST_RXACK:
if (~cnt[0])
if (scl_270) ctrl = {ST_RXACK, 3'b000, 5'b00010, last_word};
else ctrl = {ST_RXACK, 3'b000, 6'b000001}; // wait for clk phase
else
if (scl_270) ctrl = {last_word ? ST_STOP : ST_RXD, 3'b000, 6'b000011};
else ctrl = {ST_RXACK, 3'b000, 5'b00000, last_word}; // hold down
ST_STOP:
if (scl_90) ctrl = {ST_IDLE , 3'b000, 6'b000001};
else ctrl = {ST_STOP , 3'b000, 6'b000000};
default: ctrl = {ST_IDLE , 3'b000, 6'b000001};
endcase
end
assign scl = ((state == ST_IDLE | (state == ST_START & ctrl[0])) ?
1'bz : (scl_q[1] ? 1'bz : 1'b0));
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_table_prp # (
parameter P_DATA_WIDTH = 45,
parameter P_ADDR_WIDTH = 8
)
(
input clk,
input wr_en,
input [P_ADDR_WIDTH-1:0] wr_addr,
input [P_DATA_WIDTH-1:0] wr_data,
input [P_ADDR_WIDTH-1:0] rd_addr,
output [P_DATA_WIDTH-1:0] rd_data
);
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "36Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 8;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_ADDR_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : CALC_ADDR
assign rdaddr = rd_addr[P_ADDR_WIDTH-1:0];
assign wraddr = wr_addr[P_ADDR_WIDTH-1:0];
end
else begin
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
assign rdaddr = {zero_padding, rd_addr[P_ADDR_WIDTH-1:0]};
assign wraddr = {zero_padding, wr_addr[P_ADDR_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb36sdp_0(
.DO (rd_data),
.DI (wr_data),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (wr_en)
);
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ae_e
//
// Generated
// by: wig
// on: Mon Jun 26 08:25:04 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ae_e.v,v 1.3 2006/06/26 08:39:43 wig Exp $
// $Date: 2006/06/26 08:39:43 $
// $Log: inst_ae_e.v,v $
// Revision 1.3 2006/06/26 08:39:43 wig
// Update more testcases (up to generic)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
//
// Generator: mix_0.pl Revision: 1.46 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ae_e
//
// No `defines in this module
module inst_ae_e
//
// Generated Module inst_ae
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
//
// Generated Signal Assignments
//
//
// Generated Instances and Port Mappings
//
endmodule
//
// End of Generated Module rtl of inst_ae_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
//////////////////////////////////////////////////////////////////////
//// ////
//// fpu_post_norm_div ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://opencores.org/project,or1k ////
//// ////
//// Description ////
//// post-normalization entity for the division unit ////
//// ////
//// To Do: ////
//// ////
//// ////
//// Author(s): ////
//// - Original design (FPU100) - ////
//// Jidan Al-eryani, [email protected] ////
//// - Conv. to Verilog and inclusion in OR1200 - ////
//// Julius Baxter, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Copyright (C) 2006, 2010
//
// This source file may be used and distributed without
// restriction provided that this copyright statement is not
// removed from the file and that any derivative work contains
// the original copyright notice and the associated disclaimer.
//
// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
module fpu_post_norm_div
(
clk,
rst,
opa_i,
opb_i,
qutnt_i,
rmndr_i,
exp_10_i,
sign_i,
rmode_i,
output_o,
ine_o
);
parameter FP_WIDTH = 32;
parameter MUL_SERIAL = 0; // 0 for parallel multiplier, 1 for serial
parameter MUL_COUNT = 11; //11 for parallel multiplier, 34 for serial
parameter FRAC_WIDTH = 23;
parameter EXP_WIDTH = 8;
parameter ZERO_VECTOR = 31'd0;
parameter INF = 31'b1111111100000000000000000000000;
parameter QNAN = 31'b1111111110000000000000000000000;
parameter SNAN = 31'b1111111100000000000000000000001;
input clk;
input rst;
input [FP_WIDTH-1:0] opa_i;
input [FP_WIDTH-1:0] opb_i;
input [FRAC_WIDTH+3:0] qutnt_i;
input [FRAC_WIDTH+3:0] rmndr_i;
input [EXP_WIDTH+1:0] exp_10_i;
input sign_i;
input [1:0] rmode_i;
output reg [FP_WIDTH-1:0] output_o;
output reg ine_o;
// input&output register wires
reg [FP_WIDTH-1:0] s_opa_i;
reg [FP_WIDTH-1:0] s_opb_i;
reg [EXP_WIDTH-1:0] s_expa;
reg [EXP_WIDTH-1:0] s_expb;
reg [FRAC_WIDTH+3:0] s_qutnt_i;
reg [FRAC_WIDTH+3:0] s_rmndr_i;
reg [5:0] s_r_zeros;
reg [EXP_WIDTH+1:0] s_exp_10_i;
reg s_sign_i;
reg [1:0] s_rmode_i;
wire [FP_WIDTH-1:0] s_output_o;
wire s_ine_o, s_overflow;
wire s_opa_dn, s_opb_dn;
wire s_qutdn;
wire [9:0] s_exp_10b;
reg [5:0] s_shr1;
reg [5:0] s_shl1;
wire s_shr2;
reg [8:0] s_expo1;
wire [8:0] s_expo2;
reg [8:0] s_expo3;
reg [26:0] s_fraco1;
wire [24:0] s_frac_rnd;
reg [24:0] s_fraco2;
wire s_guard, s_round, s_sticky, s_roundup;
wire s_lost;
wire s_op_0, s_opab_0, s_opb_0;
wire s_infa, s_infb;
wire s_nan_in, s_nan_op, s_nan_a, s_nan_b;
wire s_inf_result;
always @(posedge clk or posedge rst)
if (rst)
begin
s_opa_i <= 'd0;
s_opb_i <= 'd0;
s_expa <= 'd0;
s_expb <= 'd0;
s_qutnt_i <= 1'b0;
s_rmndr_i <= 1'b0;
s_exp_10_i <= 1'b0;
s_sign_i <= 1'b0;
s_rmode_i <= 1'b0;
end
else
begin
s_opa_i <= opa_i;
s_opb_i <= opb_i;
s_expa <= opa_i[30:23];
s_expb <= opb_i[30:23];
s_qutnt_i <= qutnt_i;
s_rmndr_i <= rmndr_i;
s_exp_10_i <= exp_10_i;
s_sign_i <= sign_i;
s_rmode_i <= rmode_i;
end
// Output Register
always @(posedge clk or posedge rst)
if (rst)
begin
output_o <= 'd0;
ine_o <= 1'b0;
end
else
begin
output_o <= s_output_o;
ine_o <= s_ine_o;
end
// qutnt_i
// 26 25 3
// | | |
// h fffffffffffffffffffffff grs
//*** Stage 1 ****
// figure out the exponent and how far the fraction has to be shifted
// right or left
assign s_opa_dn = !(|s_expa) & (|opa_i[22:0]);
assign s_opb_dn = !(|s_expb) & (|opb_i[22:0]);
assign s_qutdn = !s_qutnt_i[26];
assign s_exp_10b = s_exp_10_i - {9'd0,s_qutdn};
wire [9:0] v_shr;
wire [9:0] v_shl;
assign v_shr = (s_exp_10b[9] | !(|s_exp_10b)) ?
(10'd1 - s_exp_10b) - {9'd0,s_qutdn} : 6'd0;
assign v_shl = (s_exp_10b[9] | !(|s_exp_10b)) ?
10'd0 :
s_exp_10b[8] ?
10'd0 : {9'd0,s_qutdn};
always @(posedge clk or posedge rst)
if (rst)
s_expo1 <= 'd0;
else
if (s_exp_10b[9] | !(|s_exp_10b))
s_expo1 <= 9'd1;
else
s_expo1 <= s_exp_10b[8:0];
always @(posedge clk or posedge rst)
if (rst)
s_shr1 <= 'd0;
else
s_shr1 <= v_shr[6] ? 6'b111111 : v_shr[5:0];
always @(posedge clk or posedge rst)
if (rst)
s_shl1 <= 'd0;
else
s_shl1 <= v_shl[5:0];
// *** Stage 2 ***
// Shifting the fraction and rounding
// shift the fraction
always @(posedge clk or posedge rst)
if (rst)
s_fraco1 <= 'd0;
else
if (|s_shr1)
s_fraco1 <= s_qutnt_i >> s_shr1;
else
s_fraco1 <= s_qutnt_i << s_shl1;
assign s_expo2 = s_fraco1[26] ? s_expo1 : s_expo1 - 9'd1;
//s_r_zeros <= count_r_zeros(s_qutnt_i);
always @(s_qutnt_i)
casez(s_qutnt_i) // synopsys full_case parallel_case
27'b??????????????????????????1: s_r_zeros = 0;
27'b?????????????????????????10: s_r_zeros = 1;
27'b????????????????????????100: s_r_zeros = 2;
27'b???????????????????????1000: s_r_zeros = 3;
27'b??????????????????????10000: s_r_zeros = 4;
27'b?????????????????????100000: s_r_zeros = 5;
27'b????????????????????1000000: s_r_zeros = 6;
27'b???????????????????10000000: s_r_zeros = 7;
27'b??????????????????100000000: s_r_zeros = 8;
27'b?????????????????1000000000: s_r_zeros = 9;
27'b????????????????10000000000: s_r_zeros = 10;
27'b???????????????100000000000: s_r_zeros = 11;
27'b??????????????1000000000000: s_r_zeros = 12;
27'b?????????????10000000000000: s_r_zeros = 13;
27'b????????????100000000000000: s_r_zeros = 14;
27'b???????????1000000000000000: s_r_zeros = 15;
27'b??????????10000000000000000: s_r_zeros = 16;
27'b?????????100000000000000000: s_r_zeros = 17;
27'b????????1000000000000000000: s_r_zeros = 18;
27'b???????10000000000000000000: s_r_zeros = 19;
27'b??????100000000000000000000: s_r_zeros = 20;
27'b?????1000000000000000000000: s_r_zeros = 21;
27'b????10000000000000000000000: s_r_zeros = 22;
27'b???100000000000000000000000: s_r_zeros = 23;
27'b??1000000000000000000000000: s_r_zeros = 24;
27'b?10000000000000000000000000: s_r_zeros = 25;
27'b100000000000000000000000000: s_r_zeros = 26;
27'b000000000000000000000000000: s_r_zeros = 27;
endcase // casex (s_qutnt_i)
assign s_lost = (s_shr1+{5'd0,s_shr2}) > s_r_zeros;
// ***Stage 3***
// Rounding
assign s_guard = s_fraco1[2];
assign s_round = s_fraco1[1];
assign s_sticky = s_fraco1[0] | (|s_rmndr_i);
assign s_roundup = s_rmode_i==2'b00 ? // round to nearest even
s_guard & ((s_round | s_sticky) | s_fraco1[3]) :
s_rmode_i==2'b10 ? // round up
(s_guard | s_round | s_sticky) & !s_sign_i :
s_rmode_i==2'b11 ? // round down
(s_guard | s_round | s_sticky) & s_sign_i :
1'b0; // round to zero(truncate = no rounding)
assign s_frac_rnd = s_roundup ?{1'b0,s_fraco1[26:3]} + 25'd1 :
{1'b0,s_fraco1[26:3]};
assign s_shr2 = s_frac_rnd[24];
always @(posedge clk or posedge rst)
if (rst)
begin
s_expo3 <= 1'b0;
s_fraco2 <= 'd0;
end
else
begin
s_expo3 <= s_shr2 ? s_expo2 + "1" : s_expo2;
s_fraco2 <= s_shr2 ? {1'b0,s_frac_rnd[24:1]} : s_frac_rnd;
end
//
// ***Stage 4****
// Output
assign s_op_0 = !((|s_opa_i[30:0]) & (|s_opb_i[30:0]));
assign s_opab_0 = !((|s_opa_i[30:0]) | (|s_opb_i[30:0]));
assign s_opb_0 = !(|s_opb_i[30:0]);
assign s_infa = &s_expa;
assign s_infb = &s_expb;
assign s_nan_a = s_infa & (|s_opa_i[22:0]);
assign s_nan_b = s_infb & (|s_opb_i[22:0]);
assign s_nan_in = s_nan_a | s_nan_b;
assign s_nan_op = (s_infa & s_infb) | s_opab_0; // 0 / 0, inf / inf
assign s_inf_result = (&s_expo3[7:0]) | s_expo3[8] | s_opb_0;
assign s_overflow = s_inf_result & !(s_infa) & !s_opb_0;
assign s_ine_o = !s_op_0 &
(s_lost | (|s_fraco1[2:0]) | s_overflow | (|s_rmndr_i));
assign s_output_o = (s_nan_in | s_nan_op) ?
{s_sign_i,QNAN} :
s_infa | s_overflow | s_inf_result ?
{s_sign_i,INF} :
s_op_0 | s_infb ?
{s_sign_i,ZERO_VECTOR} :
{s_sign_i,s_expo3[7:0],s_fraco2[22:0]};
endmodule // fpu_post_norm_div
|
//----------------------------------------------------------------------------
// DCR_IF Controller - DCR Bus Interface
//-----------------------------------------------------------------------------
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS"
// SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
// XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
// AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
// OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
// IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
// AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
// FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY
// WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
// IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
// REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
// INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
// FOR A PARTICULAR PURPOSE.
//
// (c) Copyright 2004 Xilinx, Inc.
// All rights reserved.
//
//----------------------------------------------------------------------------
// Filename: dcr_if.v
//
// Description:
//
//
// Design Notes:
//
//-----------------------------------------------------------------------------
// Structure:
//
// -- dcr_if.v
//
//-----------------------------------------------------------------------------
// Author: CJN
// History:
// CJN
//-----------------------------------------------------------------------------
`timescale 1 ns / 100 ps
///////////////////////////////////////////////////////////////////////////////
// Module Declaration
///////////////////////////////////////////////////////////////////////////////
module dcr_if(
// DCR BUS
clk, // I
rst, // I
DCR_ABus, // I [0:9]
DCR_DBusIn, // I [0:31]
DCR_Read, // I
DCR_Write, // I
DCR_Ack, // O
DCR_DBusOut, // O [0:31]
// Registers
tft_base_addr, // O [0:10]
tft_dps_reg, // O
tft_on_reg // O
);
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input clk;
input rst;
input [0:9] DCR_ABus;
input [0:31] DCR_DBusIn;
input DCR_Read;
input DCR_Write;
output DCR_Ack;
output [0:31] DCR_DBusOut;
output [0:10] tft_base_addr;
output tft_dps_reg;
output tft_on_reg;
wire [0:31] DCR_DBusOut;
reg DCR_Ack;
///////////////////////////////////////////////////////////////////////////////
// Parameter Declarations
///////////////////////////////////////////////////////////////////////////////
parameter C_DCR_BASE_ADDR = 10'b00_0000_0000;
parameter C_DEFAULT_TFT_BASE_ADDR = 11'b000_0000_0000;
parameter C_DPS_INIT = 1'b1;
parameter C_ON_INIT = 1'b1;
///////////////////////////////////////////////////////////////////////////////
// Signal Declaration
///////////////////////////////////////////////////////////////////////////////
wire dcr_addr_hit;
wire [0:9] dcr_base_addr;
reg dcr_read_access;
reg [0:31] read_data;
reg [0:10] tft_base_addr;
reg tft_dps_reg;
reg tft_on_reg;
///////////////////////////////////////////////////////////////////////////////
// DCR Register Interface
///////////////////////////////////////////////////////////////////////////////
assign dcr_base_addr = C_DCR_BASE_ADDR;
assign dcr_addr_hit = (DCR_ABus[0:8] == dcr_base_addr[0:8]);
always @(posedge clk)
begin
dcr_read_access <= DCR_Read & dcr_addr_hit;
DCR_Ack <= (DCR_Read | DCR_Write) & dcr_addr_hit;
end
always @(posedge clk)
if (rst)
tft_base_addr <= C_DEFAULT_TFT_BASE_ADDR;
else if (DCR_Write & ~DCR_Ack & dcr_addr_hit & (DCR_ABus[9] == 1'b0))
tft_base_addr <= DCR_DBusIn[0:10];
always @(posedge clk)
if (rst) begin
tft_dps_reg <= C_DPS_INIT;
tft_on_reg <= C_ON_INIT;
end
else if (DCR_Write & ~DCR_Ack & dcr_addr_hit & (DCR_ABus[9] == 1'b1)) begin
tft_dps_reg <= DCR_DBusIn[30];
tft_on_reg <= DCR_DBusIn[31];
end
always @(posedge clk)
if (DCR_Read & dcr_addr_hit & ~DCR_Ack)
read_data <= (DCR_ABus[9] == 1'b0)? {tft_base_addr, 21'b0} :
{30'b0, tft_dps_reg, tft_on_reg};
assign DCR_DBusOut = (dcr_read_access)? read_data : DCR_DBusIn;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V
/**
* a31oi: 3-input AND into first input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a31oi (
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
and and0 (and0_out , A3, A1, A2 );
nor nor0 (nor0_out_Y , B1, and0_out );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A31OI_FUNCTIONAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_edge.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Detects and stores edges as the test pattern is scanned via
// manipulating the phaser out stage 3 taps.
//
// Scanning always proceeds from the left to the right. For more
// on the scanning algorithm, see the _po_cntlr block.
//
// Four scan results are reported. The edges at fuzz2zero,
// zero2fuzz, fuzz2oneeighty, and oneeighty2fuzz. Each edge
// has a 6 bit stg3 tap value and a valid bit. The valid bits
// are reset before the scan starts.
//
// Once reset_scan is set low, this block waits for the first
// samp_done while scanning_right. This marks the left end
// of the scan, and initializes prev_samp_r with samp_result and
// sets the prev_samp_r valid bit to one.
//
// At each subesquent samp_done, the previous samp is compared
// to the current samp_result. The case statement details how
// edges are identified.
//
// Original design assumed fuzz between valid regions. Design
// has been updated to tolerate transitions from zero to oneeight
// and vice-versa without fuzz in between.
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_edge #
(parameter TCQ = 100)
(/*AUTOARG*/
// Outputs
scan_right, z2f, f2z, o2f, f2o, zero2fuzz, fuzz2zero,
oneeighty2fuzz, fuzz2oneeighty,
// Inputs
clk, samp_done, phy_rddata_en_2, reset_scan, scanning_right,
samp_result, stg3
);
localparam [1:0] NULL = 2'b11,
FUZZ = 2'b00,
ONEEIGHTY = 2'b10,
ZERO = 2'b01;
input clk;
input samp_done;
input phy_rddata_en_2;
wire samp_valid = samp_done && phy_rddata_en_2;
input reset_scan;
input scanning_right;
reg prev_samp_valid_ns, prev_samp_valid_r;
always @(posedge clk) prev_samp_valid_r <= #TCQ prev_samp_valid_ns;
always @(*) begin
prev_samp_valid_ns = prev_samp_valid_r;
if (reset_scan) prev_samp_valid_ns = 1'b0;
else if (samp_valid) prev_samp_valid_ns = 1'b1;
end
input [1:0] samp_result;
reg [1:0] prev_samp_ns, prev_samp_r;
always @(posedge clk) prev_samp_r <= #TCQ prev_samp_ns;
always @(*)
if (samp_valid) prev_samp_ns = samp_result;
else prev_samp_ns = prev_samp_r;
reg scan_right_ns, scan_right_r;
always @(posedge clk) scan_right_r <= #TCQ scan_right_ns;
output scan_right;
assign scan_right = scan_right_r;
input [5:0] stg3;
reg z2f_ns, z2f_r, f2z_ns, f2z_r, o2f_ns, o2f_r, f2o_ns, f2o_r;
always @(posedge clk) z2f_r <= #TCQ z2f_ns;
always @(posedge clk) f2z_r <= #TCQ f2z_ns;
always @(posedge clk) o2f_r <= #TCQ o2f_ns;
always @(posedge clk) f2o_r <= #TCQ f2o_ns;
output z2f, f2z, o2f, f2o;
assign z2f = z2f_r;
assign f2z = f2z_r;
assign o2f = o2f_r;
assign f2o = f2o_r;
reg [5:0] zero2fuzz_ns, zero2fuzz_r, fuzz2zero_ns, fuzz2zero_r,
oneeighty2fuzz_ns, oneeighty2fuzz_r, fuzz2oneeighty_ns, fuzz2oneeighty_r;
always @(posedge clk) zero2fuzz_r <= #TCQ zero2fuzz_ns;
always @(posedge clk) fuzz2zero_r <= #TCQ fuzz2zero_ns;
always @(posedge clk) oneeighty2fuzz_r <= #TCQ oneeighty2fuzz_ns;
always @(posedge clk) fuzz2oneeighty_r <= #TCQ fuzz2oneeighty_ns;
output [5:0] zero2fuzz, fuzz2zero, oneeighty2fuzz, fuzz2oneeighty;
assign zero2fuzz = zero2fuzz_r;
assign fuzz2zero = fuzz2zero_r;
assign oneeighty2fuzz = oneeighty2fuzz_r;
assign fuzz2oneeighty = fuzz2oneeighty_r;
always @(*) begin
z2f_ns = z2f_r;
f2z_ns = f2z_r;
o2f_ns = o2f_r;
f2o_ns = f2o_r;
zero2fuzz_ns = zero2fuzz_r;
fuzz2zero_ns = fuzz2zero_r;
oneeighty2fuzz_ns = oneeighty2fuzz_r;
fuzz2oneeighty_ns = fuzz2oneeighty_r;
scan_right_ns = 1'b0;
if (reset_scan) begin
z2f_ns = 1'b0;
f2z_ns = 1'b0;
o2f_ns = 1'b0;
f2o_ns = 1'b0;
end
else if (samp_valid && prev_samp_valid_r)
case (prev_samp_r)
FUZZ :
if (scanning_right) begin
if (samp_result == ZERO) begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
ZERO : begin
if (samp_result == FUZZ || samp_result == ONEEIGHTY) scan_right_ns = !scanning_right;
if (scanning_right) begin
if (samp_result == FUZZ) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
end
if (samp_result == ONEEIGHTY) begin
zero2fuzz_ns = stg3 - 6'b1;
z2f_ns = 1'b1;
fuzz2oneeighty_ns = stg3;
f2o_ns = 1'b1;
end
end
end
ONEEIGHTY :
if (scanning_right) begin
if (samp_result == FUZZ) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end
if (samp_result == ZERO)
if (f2o_r) begin
oneeighty2fuzz_ns = stg3 - 6'b1;
o2f_ns = 1'b1;
end else begin
fuzz2zero_ns = stg3;
f2z_ns = 1'b1;
end
end // if (scanning_right)
// NULL : // Should never happen
endcase
end
endmodule // mig_7series_v2_3_ddr_phy_ocd_edge
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Wed Mar 01 09:54:28 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// C:/ZyboIP/examples/ov7670_fusion/ov7670_fusion.srcs/sources_1/bd/system/ip/system_zybo_hdmi_0_0/system_zybo_hdmi_0_0_sim_netlist.v
// Design : system_zybo_hdmi_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z010clg400-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "system_zybo_hdmi_0_0,zybo_hdmi,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "zybo_hdmi,Vivado 2016.4" *)
(* NotValidForBitStream *)
module system_zybo_hdmi_0_0
(clk_125,
clk_25,
hsync,
vsync,
active,
rgb,
tmds,
tmdsb,
hdmi_cec,
hdmi_hpd,
hdmi_out_en);
input clk_125;
input clk_25;
input hsync;
input vsync;
input active;
input [23:0]rgb;
output [3:0]tmds;
output [3:0]tmdsb;
input hdmi_cec;
input hdmi_hpd;
output hdmi_out_en;
wire \<const1> ;
wire active;
wire clk_125;
wire clk_25;
wire hsync;
wire [23:0]rgb;
(* SLEW = "SLOW" *) wire [3:0]tmds;
(* SLEW = "SLOW" *) wire [3:0]tmdsb;
wire vsync;
assign hdmi_out_en = \<const1> ;
system_zybo_hdmi_0_0_zybo_hdmi U0
(.active(active),
.clk_125(clk_125),
.clk_25(clk_25),
.hsync(hsync),
.rgb(rgb),
.tmds(tmds),
.tmdsb(tmdsb),
.vsync(vsync));
VCC VCC
(.P(\<const1> ));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder
(SR,
D,
Q,
rgb,
active,
hsync,
vsync,
shift_blue,
\shift_clock_reg[5] ,
clk_25);
output [0:0]SR;
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input hsync;
input vsync;
input [7:0]shift_blue;
input \shift_clock_reg[5] ;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire \dc_bias[0]_i_1__1_n_0 ;
wire \dc_bias[0]_i_2__1_n_0 ;
wire \dc_bias[0]_i_3__1_n_0 ;
wire \dc_bias[0]_i_4__1_n_0 ;
wire \dc_bias[0]_i_5__0_n_0 ;
wire \dc_bias[1]_i_1__0_n_0 ;
wire \dc_bias[1]_i_2__1_n_0 ;
wire \dc_bias[1]_i_3__1_n_0 ;
wire \dc_bias[1]_i_4__1_n_0 ;
wire \dc_bias[1]_i_5__1_n_0 ;
wire \dc_bias[1]_i_6__0_n_0 ;
wire \dc_bias[1]_i_7__1_n_0 ;
wire \dc_bias[1]_i_8_n_0 ;
wire \dc_bias[1]_i_9__0_n_0 ;
wire \dc_bias[2]_i_10_n_0 ;
wire \dc_bias[2]_i_11__1_n_0 ;
wire \dc_bias[2]_i_12__0_n_0 ;
wire \dc_bias[2]_i_13__0_n_0 ;
wire \dc_bias[2]_i_14__0_n_0 ;
wire \dc_bias[2]_i_15__0_n_0 ;
wire \dc_bias[2]_i_1__1_n_0 ;
wire \dc_bias[2]_i_2__0_n_0 ;
wire \dc_bias[2]_i_3__1_n_0 ;
wire \dc_bias[2]_i_4__1_n_0 ;
wire \dc_bias[2]_i_5__1_n_0 ;
wire \dc_bias[2]_i_6__1_n_0 ;
wire \dc_bias[2]_i_7__0_n_0 ;
wire \dc_bias[2]_i_8__1_n_0 ;
wire \dc_bias[2]_i_9__0_n_0 ;
wire \dc_bias[3]_i_10__1_n_0 ;
wire \dc_bias[3]_i_11__1_n_0 ;
wire \dc_bias[3]_i_12__1_n_0 ;
wire \dc_bias[3]_i_13__0_n_0 ;
wire \dc_bias[3]_i_14__0_n_0 ;
wire \dc_bias[3]_i_15__1_n_0 ;
wire \dc_bias[3]_i_16__0_n_0 ;
wire \dc_bias[3]_i_17__0_n_0 ;
wire \dc_bias[3]_i_18__0_n_0 ;
wire \dc_bias[3]_i_19__1_n_0 ;
wire \dc_bias[3]_i_1__1_n_0 ;
wire \dc_bias[3]_i_20__0_n_0 ;
wire \dc_bias[3]_i_21_n_0 ;
wire \dc_bias[3]_i_22__1_n_0 ;
wire \dc_bias[3]_i_23__0_n_0 ;
wire \dc_bias[3]_i_24__1_n_0 ;
wire \dc_bias[3]_i_25__1_n_0 ;
wire \dc_bias[3]_i_26__1_n_0 ;
wire \dc_bias[3]_i_27__1_n_0 ;
wire \dc_bias[3]_i_28__0_n_0 ;
wire \dc_bias[3]_i_29__0_n_0 ;
wire \dc_bias[3]_i_2__1_n_0 ;
wire \dc_bias[3]_i_30__0_n_0 ;
wire \dc_bias[3]_i_31__0_n_0 ;
wire \dc_bias[3]_i_32__0_n_0 ;
wire \dc_bias[3]_i_33__0_n_0 ;
wire \dc_bias[3]_i_3__1_n_0 ;
wire \dc_bias[3]_i_4__1_n_0 ;
wire \dc_bias[3]_i_5_n_0 ;
wire \dc_bias[3]_i_6__1_n_0 ;
wire \dc_bias[3]_i_7__1_n_0 ;
wire \dc_bias[3]_i_8__1_n_0 ;
wire \dc_bias[3]_i_9__1_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire \encoded[0]_i_1__1_n_0 ;
wire \encoded[1]_i_1__1_n_0 ;
wire \encoded[1]_i_2_n_0 ;
wire \encoded[2]_i_1__1_n_0 ;
wire \encoded[2]_i_2_n_0 ;
wire \encoded[3]_i_1__1_n_0 ;
wire \encoded[3]_i_2_n_0 ;
wire \encoded[4]_i_1__1_n_0 ;
wire \encoded[4]_i_2_n_0 ;
wire \encoded[5]_i_1__1_n_0 ;
wire \encoded[5]_i_2_n_0 ;
wire \encoded[6]_i_1__1_n_0 ;
wire \encoded[6]_i_2__1_n_0 ;
wire \encoded[7]_i_1__1_n_0 ;
wire \encoded[7]_i_2__1_n_0 ;
wire \encoded[8]_i_1__1_n_0 ;
wire \encoded[9]_i_1__1_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire hsync;
wire p_1_in;
wire [7:0]rgb;
wire [7:0]shift_blue;
wire \shift_clock_reg[5] ;
wire vsync;
LUT6 #(
.INIT(64'h9F90909F909F9F90))
\dc_bias[0]_i_1__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[2]_i_2__0_n_0 ),
.I4(\dc_bias[0]_i_3__1_n_0 ),
.I5(\dc_bias[0]_i_4__1_n_0 ),
.O(\dc_bias[0]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_2__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(\dc_bias[0]_i_5__0_n_0 ),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[0]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3__1
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4__1
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[0]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'h6696969999696966))
\dc_bias[0]_i_5__0
(.I0(rgb[6]),
.I1(rgb[4]),
.I2(\dc_bias[2]_i_13__0_n_0 ),
.I3(\dc_bias[3]_i_13__0_n_0 ),
.I4(\dc_bias[2]_i_12__0_n_0 ),
.I5(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[0]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'hC5C0CFCACFCAC5C0))
\dc_bias[1]_i_1__0
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[1]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[1]_i_3__1_n_0 ),
.I4(\dc_bias[1]_i_4__1_n_0 ),
.I5(\dc_bias[1]_i_5__1_n_0 ),
.O(\dc_bias[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[1]_i_2__1
(.I0(\dc_bias[1]_i_6__0_n_0 ),
.I1(\dc_bias[1]_i_7__1_n_0 ),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\dc_bias[1]_i_8_n_0 ),
.I4(\dc_bias[1]_i_9__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[1]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'h5695))
\dc_bias[1]_i_3__1
(.I0(\dc_bias[1]_i_7__1_n_0 ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[1]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hD7BE2841))
\dc_bias[1]_i_4__1
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(\dc_bias[2]_i_10_n_0 ),
.O(\dc_bias[1]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'hEB7D7DEB7D14147D))
\dc_bias[1]_i_5__1
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[3]_i_2_n_0 ),
.I5(\dc_bias[0]_i_4__1_n_0 ),
.O(\dc_bias[1]_i_5__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'hE))
\dc_bias[1]_i_6__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__1_n_0 ),
.O(\dc_bias[1]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[1]_i_7__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_25__1_n_0 ),
.O(\dc_bias[1]_i_7__1_n_0 ));
LUT6 #(
.INIT(64'h14D782BE82BE14D7))
\dc_bias[1]_i_8
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(\dc_bias[3]_i_31__0_n_0 ),
.I3(\dc_bias[0]_i_5__0_n_0 ),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\dc_bias[1]_i_8_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h6A56566A))
\dc_bias[1]_i_9__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(\encoded[7]_i_2__1_n_0 ),
.O(\dc_bias[1]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'h9A5965A665A69A59))
\dc_bias[2]_i_10
(.I0(\dc_bias[2]_i_8__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[7]),
.I3(\encoded[6]_i_2__1_n_0 ),
.I4(\dc_bias_reg_n_0_[1] ),
.I5(\dc_bias[2]_i_14__0_n_0 ),
.O(\dc_bias[2]_i_10_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT5 #(
.INIT(32'h82EBEB82))
\dc_bias[2]_i_11__1
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[2]_i_11__1_n_0 ));
LUT5 #(
.INIT(32'h022BBFFF))
\dc_bias[2]_i_12__0
(.I0(\dc_bias[2]_i_15__0_n_0 ),
.I1(rgb[0]),
.I2(rgb[7]),
.I3(\dc_bias[3]_i_29__0_n_0 ),
.I4(\dc_bias[3]_i_12__1_n_0 ),
.O(\dc_bias[2]_i_12__0_n_0 ));
LUT6 #(
.INIT(64'h79E9EF7FFFFFFFFF))
\dc_bias[2]_i_13__0
(.I0(rgb[7]),
.I1(\dc_bias[3]_i_29__0_n_0 ),
.I2(\encoded[3]_i_2_n_0 ),
.I3(\dc_bias[2]_i_15__0_n_0 ),
.I4(\dc_bias[3]_i_12__1_n_0 ),
.I5(rgb[0]),
.O(\dc_bias[2]_i_13__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h8))
\dc_bias[2]_i_14__0
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_14__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[2]_i_15__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[2]_i_15__0_n_0 ));
LUT6 #(
.INIT(64'hC5C0CFCACFCAC5C0))
\dc_bias[2]_i_1__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[2]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(\dc_bias[2]_i_4__1_n_0 ),
.I4(\dc_bias[2]_i_5__1_n_0 ),
.I5(\dc_bias[2]_i_6__1_n_0 ),
.O(\dc_bias[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h999999A999A9AAAA))
\dc_bias[2]_i_2__0
(.I0(p_1_in),
.I1(\dc_bias[3]_i_21_n_0 ),
.I2(\dc_bias[3]_i_20__0_n_0 ),
.I3(\dc_bias[3]_i_19__1_n_0 ),
.I4(\dc_bias[3]_i_18__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[2]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6699A5A566995A5A))
\dc_bias[2]_i_3__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_14__0_n_0 ),
.I2(\dc_bias[3]_i_9__1_n_0 ),
.I3(\dc_bias[3]_i_15__1_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[3]_i_8__1_n_0 ),
.O(\dc_bias[2]_i_3__1_n_0 ));
LUT5 #(
.INIT(32'h4BB4B44B))
\dc_bias[2]_i_4__1
(.I0(\dc_bias[3]_i_25__1_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias[3]_i_14__0_n_0 ),
.I4(\dc_bias[3]_i_26__1_n_0 ),
.O(\dc_bias[2]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'h75F710518A08EFAE))
\dc_bias[2]_i_5__1
(.I0(\dc_bias[2]_i_7__0_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[7]),
.I3(\encoded[6]_i_2__1_n_0 ),
.I4(\dc_bias[2]_i_8__1_n_0 ),
.I5(\dc_bias[2]_i_9__0_n_0 ),
.O(\dc_bias[2]_i_5__1_n_0 ));
LUT6 #(
.INIT(64'h177E777777777E17))
\dc_bias[2]_i_6__1
(.I0(\dc_bias[2]_i_10_n_0 ),
.I1(\dc_bias[2]_i_11__1_n_0 ),
.I2(\dc_bias[0]_i_3__1_n_0 ),
.I3(\encoded[1]_i_2_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(rgb[2]),
.O(\dc_bias[2]_i_6__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'h6A))
\dc_bias[2]_i_7__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.O(\dc_bias[2]_i_7__0_n_0 ));
LUT6 #(
.INIT(64'h2DB4B4B42D2D2DB4))
\dc_bias[2]_i_8__1
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(\encoded[3]_i_2_n_0 ),
.I3(\dc_bias[2]_i_12__0_n_0 ),
.I4(\dc_bias[3]_i_13__0_n_0 ),
.I5(\dc_bias[2]_i_13__0_n_0 ),
.O(\dc_bias[2]_i_8__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hAA95))
\dc_bias[2]_i_9__0
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[2]_i_9__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\dc_bias[3]_i_1
(.I0(active),
.O(SR));
LUT6 #(
.INIT(64'h69FFFF69FF6969FF))
\dc_bias[3]_i_10__1
(.I0(rgb[1]),
.I1(rgb[2]),
.I2(rgb[3]),
.I3(rgb[0]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_29__0_n_0 ),
.O(\dc_bias[3]_i_10__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT5 #(
.INIT(32'h17717117))
\dc_bias[3]_i_11__1
(.I0(rgb[0]),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\dc_bias[3]_i_11__1_n_0 ));
LUT6 #(
.INIT(64'h171717E817E8E8E8))
\dc_bias[3]_i_12__1
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(rgb[6]),
.O(\dc_bias[3]_i_12__1_n_0 ));
LUT6 #(
.INIT(64'h171717FF17FFFFFF))
\dc_bias[3]_i_13__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(rgb[6]),
.O(\dc_bias[3]_i_13__0_n_0 ));
LUT6 #(
.INIT(64'h4DDD444D444D2444))
\dc_bias[3]_i_14__0
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(\dc_bias[3]_i_30__0_n_0 ),
.I2(\dc_bias[0]_i_5__0_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_31__0_n_0 ),
.I5(\dc_bias[3]_i_19__1_n_0 ),
.O(\dc_bias[3]_i_14__0_n_0 ));
LUT6 #(
.INIT(64'hECFE8FC88FC8ECFE))
\dc_bias[3]_i_15__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[3]_i_19__1_n_0 ),
.I3(\dc_bias[3]_i_20__0_n_0 ),
.I4(\dc_bias[3]_i_18__0_n_0 ),
.I5(\dc_bias[3]_i_17__0_n_0 ),
.O(\dc_bias[3]_i_15__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'h0001))
\dc_bias[3]_i_16__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_16__0_n_0 ));
LUT6 #(
.INIT(64'hD22D4BB42DD2B44B))
\dc_bias[3]_i_17__0
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_17__0_n_0 ));
LUT6 #(
.INIT(64'h1D8B8B1D8B1D1D8B))
\dc_bias[3]_i_18__0
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(rgb[0]),
.I3(rgb[6]),
.I4(rgb[4]),
.I5(\encoded[3]_i_2_n_0 ),
.O(\dc_bias[3]_i_18__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_19__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_19__1_n_0 ));
LUT6 #(
.INIT(64'h1DFF1D001DFF1DFF))
\dc_bias[3]_i_1__1
(.I0(\dc_bias[3]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_4__1_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\dc_bias[3]_i_6__1_n_0 ),
.I5(\dc_bias[3]_i_7__1_n_0 ),
.O(\dc_bias[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[3]_i_20__0
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[6]),
.I3(\encoded[7]_i_2__1_n_0 ),
.I4(rgb[0]),
.O(\dc_bias[3]_i_20__0_n_0 ));
LUT6 #(
.INIT(64'hA20808A2208A8A20))
\dc_bias[3]_i_21
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[1]),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_21_n_0 ));
LUT6 #(
.INIT(64'hBBBABA22BA22BA22))
\dc_bias[3]_i_22__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_32__0_n_0 ),
.I2(\dc_bias[3]_i_33__0_n_0 ),
.I3(\dc_bias_reg_n_0_[1] ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_22__1_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFEFFFFEF))
\dc_bias[3]_i_23__0
(.I0(\dc_bias[2]_i_10_n_0 ),
.I1(\dc_bias[0]_i_3__1_n_0 ),
.I2(\encoded[1]_i_2_n_0 ),
.I3(\dc_bias[3]_i_3__1_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[2]_i_11__1_n_0 ),
.O(\dc_bias[3]_i_23__0_n_0 ));
LUT6 #(
.INIT(64'hFFE7810081000000))
\dc_bias[3]_i_24__1
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\encoded[1]_i_2_n_0 ),
.I3(\dc_bias[0]_i_3__1_n_0 ),
.I4(\dc_bias[2]_i_11__1_n_0 ),
.I5(\dc_bias[2]_i_10_n_0 ),
.O(\dc_bias[3]_i_24__1_n_0 ));
LUT6 #(
.INIT(64'h188EE771E771188E))
\dc_bias[3]_i_25__1
(.I0(\dc_bias[3]_i_19__1_n_0 ),
.I1(\dc_bias[3]_i_31__0_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias[0]_i_5__0_n_0 ),
.I4(\dc_bias[3]_i_30__0_n_0 ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_25__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h9990F999))
\dc_bias[3]_i_26__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_25__1_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__1_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_26__1_n_0 ));
LUT6 #(
.INIT(64'hAA696955559696AA))
\dc_bias[3]_i_27__1
(.I0(\dc_bias[3]_i_28__0_n_0 ),
.I1(\encoded[7]_i_2__1_n_0 ),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_27__1_n_0 ));
LUT6 #(
.INIT(64'h28882228BEEEBBBE))
\dc_bias[3]_i_28__0
(.I0(\encoded[4]_i_2_n_0 ),
.I1(\encoded[5]_i_2_n_0 ),
.I2(\dc_bias[2]_i_12__0_n_0 ),
.I3(\dc_bias[3]_i_13__0_n_0 ),
.I4(\dc_bias[2]_i_13__0_n_0 ),
.I5(\encoded[6]_i_2__1_n_0 ),
.O(\dc_bias[3]_i_28__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_29__0
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\dc_bias[3]_i_29__0_n_0 ));
LUT4 #(
.INIT(16'h24DB))
\dc_bias[3]_i_2__1
(.I0(\dc_bias[3]_i_8__1_n_0 ),
.I1(\dc_bias[3]_i_9__1_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'h2BD400FFFF002BD4))
\dc_bias[3]_i_30__0
(.I0(\dc_bias[2]_i_13__0_n_0 ),
.I1(\dc_bias[3]_i_13__0_n_0 ),
.I2(\dc_bias[2]_i_12__0_n_0 ),
.I3(\encoded[1]_i_2_n_0 ),
.I4(rgb[2]),
.I5(rgb[3]),
.O(\dc_bias[3]_i_30__0_n_0 ));
LUT6 #(
.INIT(64'h55F5F5FFAE8A8A08))
\dc_bias[3]_i_31__0
(.I0(\dc_bias[3]_i_13__0_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_12__1_n_0 ),
.I3(\dc_bias[3]_i_11__1_n_0 ),
.I4(\dc_bias[3]_i_10__1_n_0 ),
.I5(\encoded[7]_i_2__1_n_0 ),
.O(\dc_bias[3]_i_31__0_n_0 ));
LUT6 #(
.INIT(64'h01B00071B20001B0))
\dc_bias[3]_i_32__0
(.I0(rgb[6]),
.I1(rgb[7]),
.I2(\dc_bias[3]_i_3__1_n_0 ),
.I3(\encoded[3]_i_2_n_0 ),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_32__0_n_0 ));
LUT6 #(
.INIT(64'h9208000059591049))
\dc_bias[3]_i_33__0
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_3__1_n_0 ),
.O(\dc_bias[3]_i_33__0_n_0 ));
LUT6 #(
.INIT(64'h2B023F03FFBFFFFF))
\dc_bias[3]_i_3__1
(.I0(\encoded[7]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_10__1_n_0 ),
.I2(\dc_bias[3]_i_11__1_n_0 ),
.I3(\dc_bias[3]_i_12__1_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_13__0_n_0 ),
.O(\dc_bias[3]_i_3__1_n_0 ));
LUT4 #(
.INIT(16'h65A6))
\dc_bias[3]_i_4__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(\dc_bias[3]_i_14__0_n_0 ),
.I3(\dc_bias[3]_i_15__1_n_0 ),
.O(\dc_bias[3]_i_4__1_n_0 ));
LUT6 #(
.INIT(64'hAAAAEAAAAABEABAA))
\dc_bias[3]_i_5
(.I0(\dc_bias[3]_i_16__0_n_0 ),
.I1(\dc_bias[3]_i_17__0_n_0 ),
.I2(\dc_bias[3]_i_18__0_n_0 ),
.I3(\dc_bias[3]_i_19__1_n_0 ),
.I4(\dc_bias[3]_i_20__0_n_0 ),
.I5(\dc_bias[3]_i_21_n_0 ),
.O(\dc_bias[3]_i_5_n_0 ));
LUT6 #(
.INIT(64'h8228822828288228))
\dc_bias[3]_i_6__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(p_1_in),
.I2(\dc_bias[3]_i_22__1_n_0 ),
.I3(\dc_bias[3]_i_23__0_n_0 ),
.I4(\dc_bias[2]_i_5__1_n_0 ),
.I5(\dc_bias[3]_i_24__1_n_0 ),
.O(\dc_bias[3]_i_6__1_n_0 ));
LUT6 #(
.INIT(64'hFFF4F4F0FBFFFFF4))
\dc_bias[3]_i_7__1
(.I0(\dc_bias[3]_i_25__1_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_26__1_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_14__0_n_0 ),
.O(\dc_bias[3]_i_7__1_n_0 ));
LUT6 #(
.INIT(64'h08A28A20AEFBEFBA))
\dc_bias[3]_i_8__1
(.I0(\dc_bias[3]_i_27__1_n_0 ),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(\encoded[1]_i_2_n_0 ),
.I4(\dc_bias[3]_i_3__1_n_0 ),
.I5(\dc_bias[1]_i_8_n_0 ),
.O(\dc_bias[3]_i_8__1_n_0 ));
LUT6 #(
.INIT(64'h0000099F099FFFFF))
\dc_bias[3]_i_9__1
(.I0(\encoded[7]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(\dc_bias_reg_n_0_[1] ),
.I5(\dc_bias[3]_i_28__0_n_0 ),
.O(\dc_bias[3]_i_9__1_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1__1_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[1]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1__1_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_1__1_n_0 ),
.Q(p_1_in),
.R(SR));
LUT6 #(
.INIT(64'h6F6FAF5F6060A050))
\encoded[0]_i_1__1
(.I0(rgb[0]),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(active),
.I3(\dc_bias[2]_i_2__0_n_0 ),
.I4(\dc_bias[3]_i_5_n_0 ),
.I5(hsync),
.O(\encoded[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFF7B33B7CC480084))
\encoded[1]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[1]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT2 #(
.INIT(4'h6))
\encoded[1]_i_2
(.I0(rgb[0]),
.I1(rgb[1]),
.O(\encoded[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'h880C44C0BB3F77F3))
\encoded[2]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[2]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h69))
\encoded[2]_i_2
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\encoded[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h33B7FF7B0084CC48))
\encoded[3]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[3]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h9669))
\encoded[3]_i_2
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h44C0880C77F3BB3F))
\encoded[4]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[4]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h96696996))
\encoded[4]_i_2
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\encoded[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'h33B7FF7B0084CC48))
\encoded[5]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[5]_i_2_n_0 ),
.I5(hsync),
.O(\encoded[5]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\encoded[5]_i_2
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(rgb[3]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\encoded[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'h880C44C0BB3F77F3))
\encoded[6]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5_n_0 ),
.I4(\encoded[6]_i_2__1_n_0 ),
.I5(hsync),
.O(\encoded[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT4 #(
.INIT(16'h6996))
\encoded[6]_i_2__1
(.I0(\encoded[3]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.O(\encoded[6]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'hFF337BB7CC004884))
\encoded[7]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(\dc_bias[2]_i_2__0_n_0 ),
.I3(\encoded[7]_i_2__1_n_0 ),
.I4(\dc_bias[3]_i_5_n_0 ),
.I5(hsync),
.O(\encoded[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h69969669))
\encoded[7]_i_2__1
(.I0(rgb[7]),
.I1(rgb[6]),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[3]_i_2_n_0 ),
.O(\encoded[7]_i_2__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h47))
\encoded[8]_i_1__1
(.I0(\dc_bias[3]_i_3__1_n_0 ),
.I1(active),
.I2(hsync),
.O(\encoded[8]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hC5FFC500C500C5FF))
\encoded[9]_i_1__1
(.I0(\dc_bias[2]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_3__1_n_0 ),
.I2(\dc_bias[3]_i_5_n_0 ),
.I3(active),
.I4(hsync),
.I5(vsync),
.O(\encoded[9]_i_1__1_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[0]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[1]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[2]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[3]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[4]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[5]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[6]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[7]_i_1__1_n_0 ),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1__1_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1__1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[0]_i_1
(.I0(shift_blue[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[1]_i_1
(.I0(shift_blue[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[2]_i_1
(.I0(shift_blue[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[3]_i_1
(.I0(shift_blue[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[4]_i_1
(.I0(shift_blue[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[5]_i_1
(.I0(shift_blue[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[6]_i_1
(.I0(shift_blue[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hB8))
\shift_blue[7]_i_1
(.I0(shift_blue[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder_0
(D,
Q,
rgb,
active,
shift_green,
\shift_clock_reg[5] ,
SR,
clk_25);
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input [7:0]shift_green;
input \shift_clock_reg[5] ;
input [0:0]SR;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire \dc_bias[0]_i_1__0_n_0 ;
wire \dc_bias[0]_i_2__0_n_0 ;
wire \dc_bias[0]_i_3__0_n_0 ;
wire \dc_bias[0]_i_4__0_n_0 ;
wire \dc_bias[0]_i_5__1_n_0 ;
wire \dc_bias[0]_i_6_n_0 ;
wire \dc_bias[0]_i_7_n_0 ;
wire \dc_bias[1]_i_1_n_0 ;
wire \dc_bias[1]_i_2__0_n_0 ;
wire \dc_bias[1]_i_3__0_n_0 ;
wire \dc_bias[1]_i_4__0_n_0 ;
wire \dc_bias[1]_i_5_n_0 ;
wire \dc_bias[1]_i_6__1_n_0 ;
wire \dc_bias[1]_i_7__0_n_0 ;
wire \dc_bias[1]_i_8__0_n_0 ;
wire \dc_bias[1]_i_9_n_0 ;
wire \dc_bias[2]_i_10__1_n_0 ;
wire \dc_bias[2]_i_11__0_n_0 ;
wire \dc_bias[2]_i_1__0_n_0 ;
wire \dc_bias[2]_i_2__1_n_0 ;
wire \dc_bias[2]_i_3__0_n_0 ;
wire \dc_bias[2]_i_4_n_0 ;
wire \dc_bias[2]_i_5__0_n_0 ;
wire \dc_bias[2]_i_6__0_n_0 ;
wire \dc_bias[2]_i_7_n_0 ;
wire \dc_bias[2]_i_8__0_n_0 ;
wire \dc_bias[2]_i_9_n_0 ;
wire \dc_bias[3]_i_10__0_n_0 ;
wire \dc_bias[3]_i_11__0_n_0 ;
wire \dc_bias[3]_i_12__0_n_0 ;
wire \dc_bias[3]_i_13__1_n_0 ;
wire \dc_bias[3]_i_14__1_n_0 ;
wire \dc_bias[3]_i_15__0_n_0 ;
wire \dc_bias[3]_i_16_n_0 ;
wire \dc_bias[3]_i_17_n_0 ;
wire \dc_bias[3]_i_18__1_n_0 ;
wire \dc_bias[3]_i_19__0_n_0 ;
wire \dc_bias[3]_i_1__0_n_0 ;
wire \dc_bias[3]_i_20_n_0 ;
wire \dc_bias[3]_i_21__1_n_0 ;
wire \dc_bias[3]_i_22__0_n_0 ;
wire \dc_bias[3]_i_23__1_n_0 ;
wire \dc_bias[3]_i_24__0_n_0 ;
wire \dc_bias[3]_i_25__0_n_0 ;
wire \dc_bias[3]_i_26__0_n_0 ;
wire \dc_bias[3]_i_27__0_n_0 ;
wire \dc_bias[3]_i_28_n_0 ;
wire \dc_bias[3]_i_29_n_0 ;
wire \dc_bias[3]_i_2__0_n_0 ;
wire \dc_bias[3]_i_30_n_0 ;
wire \dc_bias[3]_i_31_n_0 ;
wire \dc_bias[3]_i_32_n_0 ;
wire \dc_bias[3]_i_33_n_0 ;
wire \dc_bias[3]_i_34_n_0 ;
wire \dc_bias[3]_i_3__0_n_0 ;
wire \dc_bias[3]_i_4__0_n_0 ;
wire \dc_bias[3]_i_5__1_n_0 ;
wire \dc_bias[3]_i_6__0_n_0 ;
wire \dc_bias[3]_i_7__0_n_0 ;
wire \dc_bias[3]_i_8__0_n_0 ;
wire \dc_bias[3]_i_9__0_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire \encoded[0]_i_1__0_n_0 ;
wire \encoded[1]_i_1__0_n_0 ;
wire \encoded[2]_i_1__0_n_0 ;
wire \encoded[3]_i_1__0_n_0 ;
wire \encoded[4]_i_1__0_n_0 ;
wire \encoded[5]_i_1__0_n_0 ;
wire \encoded[6]_i_1__0_n_0 ;
wire \encoded[6]_i_2__0_n_0 ;
wire \encoded[7]_i_1__0_n_0 ;
wire \encoded[7]_i_2_n_0 ;
wire \encoded[7]_i_3__0_n_0 ;
wire \encoded[8]_i_1__0_n_0 ;
wire \encoded[8]_i_2_n_0 ;
wire \encoded[8]_i_3_n_0 ;
wire \encoded[8]_i_4_n_0 ;
wire \encoded[8]_i_5_n_0 ;
wire \encoded[8]_i_6_n_0 ;
wire \encoded[8]_i_7_n_0 ;
wire \encoded[9]_i_1_n_0 ;
wire \encoded[9]_i_2__0_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire p_1_in;
wire [7:0]rgb;
wire \shift_clock_reg[5] ;
wire [7:0]shift_green;
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[0]_i_1__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\dc_bias[3]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[0]_i_3__0_n_0 ),
.I5(\dc_bias[0]_i_4__0_n_0 ),
.O(\dc_bias[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_2__0
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_6_n_0 ),
.I3(\dc_bias[0]_i_7_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[0]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3__0
(.I0(\encoded[6]_i_2__0_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4__0
(.I0(rgb[2]),
.I1(\encoded[8]_i_2_n_0 ),
.O(\dc_bias[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[0]_i_5__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[0]_i_5__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_6
(.I0(rgb[7]),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\dc_bias[0]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[0]_i_7
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[0]_i_7_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\dc_bias[1]_i_1
(.I0(\dc_bias[1]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[1]_i_3__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[1]_i_4__0_n_0 ),
.O(\dc_bias[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h960096FF96FF9600))
\dc_bias[1]_i_2__0
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\dc_bias[1]_i_6__1_n_0 ),
.I2(\dc_bias[1]_i_7__0_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[1]_i_8__0_n_0 ),
.I5(\dc_bias[2]_i_10__1_n_0 ),
.O(\dc_bias[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT4 #(
.INIT(16'h5965))
\dc_bias[1]_i_3__0
(.I0(\dc_bias[2]_i_10__1_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(\dc_bias[0]_i_2__0_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h56955965A96AA69A))
\dc_bias[1]_i_4__0
(.I0(\dc_bias[3]_i_11__0_n_0 ),
.I1(\dc_bias[0]_i_3__0_n_0 ),
.I2(rgb[2]),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[2]_i_11__0_n_0 ),
.I5(\dc_bias[3]_i_12__0_n_0 ),
.O(\dc_bias[1]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'h066090096FF6F99F))
\dc_bias[1]_i_5
(.I0(rgb[6]),
.I1(\dc_bias[0]_i_7_n_0 ),
.I2(\dc_bias[1]_i_9_n_0 ),
.I3(\dc_bias[0]_i_6_n_0 ),
.I4(\encoded[8]_i_2_n_0 ),
.I5(\dc_bias[0]_i_5__1_n_0 ),
.O(\dc_bias[1]_i_5_n_0 ));
LUT6 #(
.INIT(64'h556969AAAA969655))
\dc_bias[1]_i_6__1
(.I0(\dc_bias[3]_i_27__0_n_0 ),
.I1(\dc_bias[0]_i_6_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[1]_i_6__1_n_0 ));
LUT6 #(
.INIT(64'h9C3939399C9C9C39))
\dc_bias[1]_i_7__0
(.I0(rgb[2]),
.I1(\dc_bias[2]_i_11__0_n_0 ),
.I2(rgb[3]),
.I3(\dc_bias[3]_i_30_n_0 ),
.I4(\encoded[8]_i_6_n_0 ),
.I5(\dc_bias[3]_i_31_n_0 ),
.O(\dc_bias[1]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT2 #(
.INIT(4'hB))
\dc_bias[1]_i_8__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[1]_i_8__0_n_0 ));
LUT2 #(
.INIT(4'h6))
\dc_bias[1]_i_9
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[1]_i_9_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[2]_i_10__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_10__0_n_0 ),
.O(\dc_bias[2]_i_10__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_11__0
(.I0(rgb[0]),
.I1(rgb[1]),
.O(\dc_bias[2]_i_11__0_n_0 ));
LUT6 #(
.INIT(64'hB888B8BBB8BBB888))
\dc_bias[2]_i_1__0
(.I0(\dc_bias[2]_i_2__1_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[2]_i_3__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[2]_i_4_n_0 ),
.I5(\dc_bias[2]_i_5__0_n_0 ),
.O(\dc_bias[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h96FF9600960096FF))
\dc_bias[2]_i_2__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_6__0_n_0 ),
.I2(\dc_bias[2]_i_7_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(\dc_bias[2]_i_8__0_n_0 ),
.I5(\dc_bias[2]_i_9_n_0 ),
.O(\dc_bias[2]_i_2__1_n_0 ));
LUT6 #(
.INIT(64'h04DFFB20FB2004DF))
\dc_bias[2]_i_3__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias[2]_i_10__1_n_0 ),
.I4(\dc_bias[3]_i_23__1_n_0 ),
.I5(\dc_bias[2]_i_8__0_n_0 ),
.O(\dc_bias[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h711818188EE7E7E7))
\dc_bias[2]_i_4
(.I0(\dc_bias[3]_i_16_n_0 ),
.I1(\dc_bias[3]_i_17_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hBB2BB2BBBBBDDBBB))
\dc_bias[2]_i_5__0
(.I0(\dc_bias[3]_i_11__0_n_0 ),
.I1(\dc_bias[3]_i_12__0_n_0 ),
.I2(\dc_bias[2]_i_11__0_n_0 ),
.I3(\encoded[8]_i_2_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[0]_i_3__0_n_0 ),
.O(\dc_bias[2]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h01151501577F7F57))
\dc_bias[2]_i_6__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_6_n_0 ),
.I4(\encoded[8]_i_2_n_0 ),
.I5(\dc_bias[3]_i_27__0_n_0 ),
.O(\dc_bias[2]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'h802AA802EABFFEAB))
\dc_bias[2]_i_7
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(rgb[3]),
.I3(\dc_bias[2]_i_11__0_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[1]_i_6__1_n_0 ),
.O(\dc_bias[2]_i_7_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_8__0
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_9__0_n_0 ),
.O(\dc_bias[2]_i_8__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT4 #(
.INIT(16'h2B22))
\dc_bias[2]_i_9
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[2]_i_9_n_0 ));
LUT6 #(
.INIT(64'h188EE771E771188E))
\dc_bias[3]_i_10__0
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(\dc_bias[3]_i_29_n_0 ),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_28_n_0 ),
.I4(\dc_bias[3]_i_27__0_n_0 ),
.I5(\dc_bias[1]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_10__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT5 #(
.INIT(32'h96696969))
\dc_bias[3]_i_11__0
(.I0(\dc_bias[3]_i_16_n_0 ),
.I1(\dc_bias[3]_i_17_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.O(\dc_bias[3]_i_11__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT5 #(
.INIT(32'h82EBEB82))
\dc_bias[3]_i_12__0
(.I0(rgb[7]),
.I1(\dc_bias_reg_n_0_[0] ),
.I2(rgb[0]),
.I3(rgb[5]),
.I4(\encoded[6]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_12__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT5 #(
.INIT(32'h96669996))
\dc_bias[3]_i_13__1
(.I0(rgb[1]),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_30_n_0 ),
.I3(\encoded[8]_i_6_n_0 ),
.I4(\dc_bias[3]_i_31_n_0 ),
.O(\dc_bias[3]_i_13__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_14__1
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_14__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT2 #(
.INIT(4'h8))
\dc_bias[3]_i_15__0
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[3]_i_15__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT4 #(
.INIT(16'hB42D))
\dc_bias[3]_i_16
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2__0_n_0 ),
.I3(rgb[5]),
.O(\dc_bias[3]_i_16_n_0 ));
LUT6 #(
.INIT(64'h1771711771171771))
\dc_bias[3]_i_17
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[7]),
.I2(\encoded[6]_i_2__0_n_0 ),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h14414114))
\dc_bias[3]_i_18__1
(.I0(\dc_bias[0]_i_5__1_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_6_n_0 ),
.I3(\dc_bias[0]_i_7_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[3]_i_18__1_n_0 ));
LUT6 #(
.INIT(64'h82BE14D714D782BE))
\dc_bias[3]_i_19__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(rgb[7]),
.I2(\encoded[7]_i_2_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[0]_i_7_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[3]_i_19__0_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFFAAEB))
\dc_bias[3]_i_1__0
(.I0(\dc_bias[3]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_3__0_n_0 ),
.I2(\dc_bias[3]_i_4__0_n_0 ),
.I3(\dc_bias[3]_i_5__1_n_0 ),
.I4(\dc_bias[3]_i_6__0_n_0 ),
.I5(\dc_bias[3]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h42BDBD42BD4242BD))
\dc_bias[3]_i_20
(.I0(rgb[6]),
.I1(\encoded[8]_i_2_n_0 ),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[6]_i_2__0_n_0 ),
.I5(\dc_bias[1]_i_7__0_n_0 ),
.O(\dc_bias[3]_i_20_n_0 ));
LUT6 #(
.INIT(64'hBAAEEFFBEFFBBAAE))
\dc_bias[3]_i_21__1
(.I0(\dc_bias[1]_i_7__0_n_0 ),
.I1(rgb[6]),
.I2(\encoded[8]_i_2_n_0 ),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[6]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_21__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT5 #(
.INIT(32'h99F99099))
\dc_bias[3]_i_22__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_10__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.I4(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[3]_i_22__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'hB))
\dc_bias[3]_i_23__1
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_23__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hDF))
\dc_bias[3]_i_24__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2__0_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.O(\dc_bias[3]_i_24__0_n_0 ));
LUT6 #(
.INIT(64'h002BD400FFD42BFF))
\dc_bias[3]_i_25__0
(.I0(\dc_bias[1]_i_5_n_0 ),
.I1(\dc_bias[1]_i_7__0_n_0 ),
.I2(\dc_bias[1]_i_6__1_n_0 ),
.I3(\dc_bias[2]_i_6__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(p_1_in),
.O(\dc_bias[3]_i_25__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFD4DDD4DD0000))
\dc_bias[3]_i_26__0
(.I0(\dc_bias[3]_i_10__0_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_9__0_n_0 ),
.O(\dc_bias[3]_i_26__0_n_0 ));
LUT6 #(
.INIT(64'hEBBBEEEB82228882))
\dc_bias[3]_i_27__0
(.I0(\dc_bias[0]_i_7_n_0 ),
.I1(\dc_bias[3]_i_32_n_0 ),
.I2(\dc_bias[3]_i_30_n_0 ),
.I3(\encoded[8]_i_6_n_0 ),
.I4(\dc_bias[3]_i_31_n_0 ),
.I5(\encoded[7]_i_2_n_0 ),
.O(\dc_bias[3]_i_27__0_n_0 ));
LUT6 #(
.INIT(64'h8E71718E718E8E71))
\dc_bias[3]_i_28
(.I0(\dc_bias[3]_i_30_n_0 ),
.I1(\encoded[8]_i_6_n_0 ),
.I2(\dc_bias[3]_i_31_n_0 ),
.I3(rgb[4]),
.I4(\encoded[6]_i_2__0_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[3]_i_28_n_0 ));
LUT6 #(
.INIT(64'hBAFB5D45BAFB4504))
\dc_bias[3]_i_29
(.I0(\encoded[8]_i_6_n_0 ),
.I1(\encoded[8]_i_5_n_0 ),
.I2(\encoded[8]_i_4_n_0 ),
.I3(\encoded[8]_i_3_n_0 ),
.I4(\dc_bias[0]_i_6_n_0 ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_29_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT4 #(
.INIT(16'hAAAE))
\dc_bias[3]_i_2__0
(.I0(\dc_bias[3]_i_8__0_n_0 ),
.I1(\dc_bias[3]_i_9__0_n_0 ),
.I2(\dc_bias[3]_i_10__0_n_0 ),
.I3(\dc_bias[0]_i_2__0_n_0 ),
.O(\dc_bias[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h0000F6606000FFF6))
\dc_bias[3]_i_30
(.I0(\dc_bias[3]_i_33_n_0 ),
.I1(rgb[6]),
.I2(rgb[7]),
.I3(rgb[0]),
.I4(\encoded[8]_i_5_n_0 ),
.I5(\dc_bias[3]_i_34_n_0 ),
.O(\dc_bias[3]_i_30_n_0 ));
LUT6 #(
.INIT(64'h4008000029610000))
\dc_bias[3]_i_31
(.I0(rgb[7]),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(\encoded[8]_i_7_n_0 ),
.I3(\dc_bias[3]_i_34_n_0 ),
.I4(rgb[0]),
.I5(\encoded[8]_i_5_n_0 ),
.O(\dc_bias[3]_i_31_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\dc_bias[3]_i_32
(.I0(rgb[5]),
.I1(rgb[4]),
.I2(rgb[2]),
.I3(rgb[1]),
.I4(rgb[0]),
.I5(rgb[3]),
.O(\dc_bias[3]_i_32_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[3]_i_33
(.I0(rgb[4]),
.I1(rgb[5]),
.O(\dc_bias[3]_i_33_n_0 ));
LUT3 #(
.INIT(8'h69))
\dc_bias[3]_i_34
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[3]_i_34_n_0 ));
LUT6 #(
.INIT(64'h8A088A8A8A8AAE8A))
\dc_bias[3]_i_3__0
(.I0(\dc_bias[2]_i_4_n_0 ),
.I1(\dc_bias[3]_i_11__0_n_0 ),
.I2(\dc_bias[3]_i_12__0_n_0 ),
.I3(\dc_bias[3]_i_13__1_n_0 ),
.I4(\dc_bias[3]_i_14__1_n_0 ),
.I5(\dc_bias[0]_i_3__0_n_0 ),
.O(\dc_bias[3]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'h56555555AA6A6A56))
\dc_bias[3]_i_4__0
(.I0(p_1_in),
.I1(\dc_bias[3]_i_15__0_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias[3]_i_16_n_0 ),
.I4(\dc_bias[3]_i_17_n_0 ),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[3]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hA6655555))
\dc_bias[3]_i_5__1
(.I0(p_1_in),
.I1(\dc_bias[3]_i_18__1_n_0 ),
.I2(\dc_bias[3]_i_19__0_n_0 ),
.I3(\dc_bias[3]_i_20_n_0 ),
.I4(\dc_bias[3]_i_21__1_n_0 ),
.O(\dc_bias[3]_i_5__1_n_0 ));
LUT6 #(
.INIT(64'h000C40404040CCC0))
\dc_bias[3]_i_6__0
(.I0(\dc_bias[3]_i_22__0_n_0 ),
.I1(\dc_bias[3]_i_5__1_n_0 ),
.I2(\dc_bias[3]_i_23__1_n_0 ),
.I3(\dc_bias[3]_i_24__0_n_0 ),
.I4(\dc_bias[3]_i_9__0_n_0 ),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[3]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'hB08080B0))
\dc_bias[3]_i_7__0
(.I0(\dc_bias[3]_i_25__0_n_0 ),
.I1(\encoded[8]_i_2_n_0 ),
.I2(\dc_bias[3]_i_2__0_n_0 ),
.I3(\dc_bias[3]_i_26__0_n_0 ),
.I4(\dc_bias[3]_i_5__1_n_0 ),
.O(\dc_bias[3]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'h0001))
\dc_bias[3]_i_8__0
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias_reg_n_0_[2] ),
.I2(p_1_in),
.I3(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_8__0_n_0 ));
LUT6 #(
.INIT(64'hD444DDD4DDD4BDDD))
\dc_bias[3]_i_9__0
(.I0(\dc_bias[1]_i_7__0_n_0 ),
.I1(\dc_bias[3]_i_27__0_n_0 ),
.I2(\dc_bias[3]_i_28_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_29_n_0 ),
.I5(\dc_bias[0]_i_5__1_n_0 ),
.O(\dc_bias[3]_i_9__0_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[1]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1__0_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_1__0_n_0 ),
.Q(p_1_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'h82))
\encoded[0]_i_1__0
(.I0(active),
.I1(rgb[0]),
.I2(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT4 #(
.INIT(16'h2882))
\encoded[1]_i_1__0
(.I0(active),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hD77D7DD7))
\encoded[2]_i_1__0
(.I0(active),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.I4(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h2882822882282882))
\encoded[3]_i_1__0
(.I0(active),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.I5(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT4 #(
.INIT(16'hD77D))
\encoded[4]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[4]),
.I3(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h28828228))
\encoded[5]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[4]),
.I3(rgb[5]),
.I4(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[5]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hD77D7DD77DD7D77D))
\encoded[6]_i_1__0
(.I0(active),
.I1(\encoded[6]_i_2__0_n_0 ),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT4 #(
.INIT(16'h9669))
\encoded[6]_i_2__0
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[6]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT4 #(
.INIT(16'h2882))
\encoded[7]_i_1__0
(.I0(active),
.I1(\encoded[7]_i_2_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_3__0_n_0 ),
.O(\encoded[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT4 #(
.INIT(16'h9669))
\encoded[7]_i_2
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(rgb[6]),
.I3(\encoded[6]_i_2__0_n_0 ),
.O(\encoded[7]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hBE))
\encoded[7]_i_3__0
(.I0(\dc_bias[3]_i_2__0_n_0 ),
.I1(\dc_bias[3]_i_5__1_n_0 ),
.I2(\encoded[8]_i_2_n_0 ),
.O(\encoded[7]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT2 #(
.INIT(4'hB))
\encoded[8]_i_1__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(active),
.O(\encoded[8]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h00200000F2FF20F2))
\encoded[8]_i_2
(.I0(rgb[0]),
.I1(\dc_bias[0]_i_6_n_0 ),
.I2(\encoded[8]_i_3_n_0 ),
.I3(\encoded[8]_i_4_n_0 ),
.I4(\encoded[8]_i_5_n_0 ),
.I5(\encoded[8]_i_6_n_0 ),
.O(\encoded[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFF6969FF69FFFF69))
\encoded[8]_i_3
(.I0(rgb[1]),
.I1(rgb[2]),
.I2(rgb[3]),
.I3(rgb[0]),
.I4(rgb[7]),
.I5(\encoded[8]_i_7_n_0 ),
.O(\encoded[8]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT5 #(
.INIT(32'hE88E8EE8))
\encoded[8]_i_4
(.I0(rgb[0]),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.O(\encoded[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'hE8E8E817E8171717))
\encoded[8]_i_5
(.I0(rgb[2]),
.I1(rgb[3]),
.I2(rgb[1]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\encoded[8]_i_5_n_0 ));
LUT6 #(
.INIT(64'hE8E8E800E8000000))
\encoded[8]_i_6
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.I3(rgb[2]),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\encoded[8]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'h69))
\encoded[8]_i_7
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\encoded[8]_i_7_n_0 ));
LUT2 #(
.INIT(4'h7))
\encoded[9]_i_1
(.I0(active),
.I1(\encoded[9]_i_2__0_n_0 ),
.O(\encoded[9]_i_1_n_0 ));
LUT3 #(
.INIT(8'h8B))
\encoded[9]_i_2__0
(.I0(\encoded[8]_i_2_n_0 ),
.I1(\dc_bias[3]_i_2__0_n_0 ),
.I2(\dc_bias[3]_i_5__1_n_0 ),
.O(\encoded[9]_i_2__0_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[0]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[1]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[2]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[3]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[4]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[5]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[6]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[7]_i_1__0_n_0 ),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[0]_i_1
(.I0(shift_green[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[1]_i_1
(.I0(shift_green[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[2]_i_1
(.I0(shift_green[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[3]_i_1
(.I0(shift_green[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[4]_i_1
(.I0(shift_green[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[5]_i_1
(.I0(shift_green[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[6]_i_1
(.I0(shift_green[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\shift_green[7]_i_1
(.I0(shift_green[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "TMDS_encoder" *)
module system_zybo_hdmi_0_0_TMDS_encoder_1
(D,
Q,
rgb,
active,
data1,
\shift_clock_reg[5] ,
SR,
clk_25);
output [7:0]D;
output [1:0]Q;
input [7:0]rgb;
input active;
input [7:0]data1;
input \shift_clock_reg[5] ;
input [0:0]SR;
input clk_25;
wire [7:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire active;
wire clk_25;
wire [7:0]data1;
wire \dc_bias[0]_i_1_n_0 ;
wire \dc_bias[0]_i_2_n_0 ;
wire \dc_bias[0]_i_3_n_0 ;
wire \dc_bias[0]_i_4_n_0 ;
wire \dc_bias[0]_i_5_n_0 ;
wire \dc_bias[0]_i_6__0_n_0 ;
wire \dc_bias[1]_i_2_n_0 ;
wire \dc_bias[1]_i_3_n_0 ;
wire \dc_bias[1]_i_4_n_0 ;
wire \dc_bias[1]_i_5__0_n_0 ;
wire \dc_bias[1]_i_6_n_0 ;
wire \dc_bias[1]_i_7_n_0 ;
wire \dc_bias[2]_i_10__0_n_0 ;
wire \dc_bias[2]_i_11_n_0 ;
wire \dc_bias[2]_i_12_n_0 ;
wire \dc_bias[2]_i_13_n_0 ;
wire \dc_bias[2]_i_14_n_0 ;
wire \dc_bias[2]_i_15_n_0 ;
wire \dc_bias[2]_i_16_n_0 ;
wire \dc_bias[2]_i_17_n_0 ;
wire \dc_bias[2]_i_18_n_0 ;
wire \dc_bias[2]_i_19_n_0 ;
wire \dc_bias[2]_i_1_n_0 ;
wire \dc_bias[2]_i_20_n_0 ;
wire \dc_bias[2]_i_21_n_0 ;
wire \dc_bias[2]_i_22_n_0 ;
wire \dc_bias[2]_i_2_n_0 ;
wire \dc_bias[2]_i_3_n_0 ;
wire \dc_bias[2]_i_4__0_n_0 ;
wire \dc_bias[2]_i_5_n_0 ;
wire \dc_bias[2]_i_6_n_0 ;
wire \dc_bias[2]_i_7__1_n_0 ;
wire \dc_bias[2]_i_8_n_0 ;
wire \dc_bias[2]_i_9__1_n_0 ;
wire \dc_bias[3]_i_10_n_0 ;
wire \dc_bias[3]_i_11_n_0 ;
wire \dc_bias[3]_i_12_n_0 ;
wire \dc_bias[3]_i_13_n_0 ;
wire \dc_bias[3]_i_14_n_0 ;
wire \dc_bias[3]_i_15_n_0 ;
wire \dc_bias[3]_i_16__1_n_0 ;
wire \dc_bias[3]_i_17__1_n_0 ;
wire \dc_bias[3]_i_18_n_0 ;
wire \dc_bias[3]_i_19_n_0 ;
wire \dc_bias[3]_i_20__1_n_0 ;
wire \dc_bias[3]_i_21__0_n_0 ;
wire \dc_bias[3]_i_22_n_0 ;
wire \dc_bias[3]_i_23_n_0 ;
wire \dc_bias[3]_i_24_n_0 ;
wire \dc_bias[3]_i_25_n_0 ;
wire \dc_bias[3]_i_26_n_0 ;
wire \dc_bias[3]_i_27_n_0 ;
wire \dc_bias[3]_i_2_n_0 ;
wire \dc_bias[3]_i_3_n_0 ;
wire \dc_bias[3]_i_4_n_0 ;
wire \dc_bias[3]_i_5__0_n_0 ;
wire \dc_bias[3]_i_6_n_0 ;
wire \dc_bias[3]_i_7_n_0 ;
wire \dc_bias[3]_i_8_n_0 ;
wire \dc_bias[3]_i_9_n_0 ;
wire \dc_bias_reg[1]_i_1_n_0 ;
wire \dc_bias_reg_n_0_[0] ;
wire \dc_bias_reg_n_0_[1] ;
wire \dc_bias_reg_n_0_[2] ;
wire [7:0]encoded;
wire \encoded[6]_i_2_n_0 ;
wire \encoded[7]_i_2__0_n_0 ;
wire \encoded[7]_i_3_n_0 ;
wire \encoded[8]_i_1_n_0 ;
wire \encoded[9]_i_1__0_n_0 ;
wire \encoded[9]_i_2_n_0 ;
wire \encoded_reg_n_0_[0] ;
wire \encoded_reg_n_0_[1] ;
wire \encoded_reg_n_0_[2] ;
wire \encoded_reg_n_0_[3] ;
wire \encoded_reg_n_0_[4] ;
wire \encoded_reg_n_0_[5] ;
wire \encoded_reg_n_0_[6] ;
wire \encoded_reg_n_0_[7] ;
wire p_1_in;
wire [7:0]rgb;
wire \shift_clock_reg[5] ;
LUT6 #(
.INIT(64'h6F60606F606F6F60))
\dc_bias[0]_i_1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2_n_0 ),
.I2(\dc_bias[3]_i_6_n_0 ),
.I3(\dc_bias[2]_i_4__0_n_0 ),
.I4(\dc_bias[0]_i_3_n_0 ),
.I5(\dc_bias[0]_i_4_n_0 ),
.O(\dc_bias[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT4 #(
.INIT(16'h6996))
\dc_bias[0]_i_2
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias[0]_i_6__0_n_0 ),
.O(\dc_bias[0]_i_2_n_0 ));
LUT5 #(
.INIT(32'h69969669))
\dc_bias[0]_i_3
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[5]),
.I2(rgb[0]),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[7]),
.O(\dc_bias[0]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h9))
\dc_bias[0]_i_4
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[0]_i_4_n_0 ));
LUT6 #(
.INIT(64'h9669699669969669))
\dc_bias[0]_i_5
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.I4(rgb[7]),
.I5(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[0]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h9669))
\dc_bias[0]_i_6__0
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(rgb[6]),
.O(\dc_bias[0]_i_6__0_n_0 ));
LUT6 #(
.INIT(64'hCC3CC3CC55555555))
\dc_bias[1]_i_2
(.I0(\dc_bias[1]_i_4_n_0 ),
.I1(\dc_bias[1]_i_5__0_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.I3(\dc_bias[0]_i_2_n_0 ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(\dc_bias[2]_i_4__0_n_0 ),
.O(\dc_bias[1]_i_2_n_0 ));
LUT6 #(
.INIT(64'hF00F0FF099999999))
\dc_bias[1]_i_3
(.I0(\dc_bias[3]_i_16__1_n_0 ),
.I1(\dc_bias[1]_i_5__0_n_0 ),
.I2(\dc_bias[1]_i_6_n_0 ),
.I3(\dc_bias[1]_i_7_n_0 ),
.I4(\dc_bias[2]_i_12_n_0 ),
.I5(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h95A9A96A569595A9))
\dc_bias[1]_i_4
(.I0(\dc_bias[2]_i_18_n_0 ),
.I1(\dc_bias[2]_i_16_n_0 ),
.I2(\dc_bias[2]_i_17_n_0 ),
.I3(\dc_bias[2]_i_19_n_0 ),
.I4(\dc_bias[2]_i_20_n_0 ),
.I5(rgb[7]),
.O(\dc_bias[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h9996699969996669))
\dc_bias[1]_i_5__0
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_26_n_0 ),
.I2(\dc_bias[0]_i_6__0_n_0 ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_25_n_0 ),
.O(\dc_bias[1]_i_5__0_n_0 ));
LUT6 #(
.INIT(64'h5CC5355335535CC5))
\dc_bias[1]_i_6
(.I0(\dc_bias[0]_i_6__0_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[3]),
.I5(rgb[1]),
.O(\dc_bias[1]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'hA665599A))
\dc_bias[1]_i_7
(.I0(\dc_bias[2]_i_13_n_0 ),
.I1(\dc_bias[0]_i_5_n_0 ),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(rgb[0]),
.I4(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hB888B8BBB8BBB888))
\dc_bias[2]_i_1
(.I0(\dc_bias[2]_i_2_n_0 ),
.I1(\dc_bias[3]_i_6_n_0 ),
.I2(\dc_bias[2]_i_3_n_0 ),
.I3(\dc_bias[2]_i_4__0_n_0 ),
.I4(\dc_bias[2]_i_5_n_0 ),
.I5(\dc_bias[2]_i_6_n_0 ),
.O(\dc_bias[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h90060690))
\dc_bias[2]_i_10__0
(.I0(\dc_bias[0]_i_5_n_0 ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_10__0_n_0 ));
LUT6 #(
.INIT(64'h3AA3ACCAACCA3AA3))
\dc_bias[2]_i_11
(.I0(rgb[0]),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_2__0_n_0 ),
.I4(\dc_bias[2]_i_22_n_0 ),
.I5(rgb[6]),
.O(\dc_bias[2]_i_11_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT5 #(
.INIT(32'h2DD2B44B))
\dc_bias[2]_i_12
(.I0(rgb[2]),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_12_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT5 #(
.INIT(32'hA59669A5))
\dc_bias[2]_i_13
(.I0(rgb[4]),
.I1(rgb[5]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(rgb[6]),
.O(\dc_bias[2]_i_13_n_0 ));
LUT6 #(
.INIT(64'h1771711771171771))
\dc_bias[2]_i_14
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[7]),
.I2(rgb[6]),
.I3(rgb[5]),
.I4(rgb[4]),
.I5(\encoded[6]_i_2_n_0 ),
.O(\dc_bias[2]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT4 #(
.INIT(16'h4BD2))
\dc_bias[2]_i_15
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(rgb[4]),
.I2(\encoded[6]_i_2_n_0 ),
.I3(rgb[5]),
.O(\dc_bias[2]_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'h69))
\dc_bias[2]_i_16
(.I0(rgb[2]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[2]_i_16_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[2]_i_17
(.I0(rgb[1]),
.I1(rgb[0]),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[2]_i_17_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT5 #(
.INIT(32'h69969696))
\dc_bias[2]_i_18
(.I0(\dc_bias[2]_i_15_n_0 ),
.I1(\dc_bias[2]_i_14_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.O(\dc_bias[2]_i_18_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_19
(.I0(rgb[5]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_19_n_0 ));
LUT5 #(
.INIT(32'h6F60606F))
\dc_bias[2]_i_2
(.I0(\dc_bias[2]_i_7__1_n_0 ),
.I1(\dc_bias[3]_i_9_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.I3(\dc_bias[2]_i_8_n_0 ),
.I4(\dc_bias[2]_i_9__1_n_0 ),
.O(\dc_bias[2]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_20
(.I0(rgb[0]),
.I1(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_20_n_0 ));
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_21
(.I0(rgb[6]),
.I1(\dc_bias[2]_i_22_n_0 ),
.I2(\encoded[7]_i_2__0_n_0 ),
.I3(rgb[7]),
.I4(rgb[0]),
.O(\dc_bias[2]_i_21_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT5 #(
.INIT(32'h96696996))
\dc_bias[2]_i_22
(.I0(rgb[4]),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.O(\dc_bias[2]_i_22_n_0 ));
LUT6 #(
.INIT(64'h56569556566A5656))
\dc_bias[2]_i_3
(.I0(\dc_bias[2]_i_8_n_0 ),
.I1(\dc_bias_reg_n_0_[1] ),
.I2(\dc_bias[3]_i_17__1_n_0 ),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(\dc_bias[0]_i_2_n_0 ),
.I5(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_3_n_0 ));
LUT5 #(
.INIT(32'h5556566A))
\dc_bias[2]_i_4__0
(.I0(p_1_in),
.I1(\dc_bias[2]_i_10__0_n_0 ),
.I2(\dc_bias[2]_i_11_n_0 ),
.I3(\dc_bias[2]_i_12_n_0 ),
.I4(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[2]_i_4__0_n_0 ));
LUT6 #(
.INIT(64'hD44242422BBDBDBD))
\dc_bias[2]_i_5
(.I0(\dc_bias[2]_i_14_n_0 ),
.I1(\dc_bias[2]_i_15_n_0 ),
.I2(\dc_bias_reg_n_0_[1] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[2] ),
.O(\dc_bias[2]_i_5_n_0 ));
LUT6 #(
.INIT(64'hF7F1F170EFF7F7F1))
\dc_bias[2]_i_6
(.I0(\dc_bias[2]_i_16_n_0 ),
.I1(\dc_bias[2]_i_17_n_0 ),
.I2(\dc_bias[2]_i_18_n_0 ),
.I3(\dc_bias[2]_i_19_n_0 ),
.I4(\dc_bias[2]_i_20_n_0 ),
.I5(rgb[7]),
.O(\dc_bias[2]_i_6_n_0 ));
LUT6 #(
.INIT(64'h5565656666A6A6AA))
\dc_bias[2]_i_7__1
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_13_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(rgb[0]),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[2]_i_7__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT2 #(
.INIT(4'h6))
\dc_bias[2]_i_8
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[3]_i_15_n_0 ),
.O(\dc_bias[2]_i_8_n_0 ));
LUT6 #(
.INIT(64'h41141414417D7D14))
\dc_bias[2]_i_9__1
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(\dc_bias[3]_i_26_n_0 ),
.I2(\dc_bias[2]_i_11_n_0 ),
.I3(\dc_bias[2]_i_21_n_0 ),
.I4(\dc_bias[3]_i_25_n_0 ),
.I5(\dc_bias_reg_n_0_[0] ),
.O(\dc_bias[2]_i_9__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT5 #(
.INIT(32'h15017F57))
\dc_bias[3]_i_10
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(rgb[0]),
.I2(\dc_bias_reg_n_0_[0] ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_10_n_0 ));
LUT6 #(
.INIT(64'h171717FF17FFFFFF))
\dc_bias[3]_i_11
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_12
(.I0(rgb[6]),
.I1(rgb[5]),
.I2(rgb[4]),
.O(\dc_bias[3]_i_12_n_0 ));
LUT6 #(
.INIT(64'h171717E817E8E8E8))
\dc_bias[3]_i_13
(.I0(rgb[1]),
.I1(rgb[3]),
.I2(rgb[2]),
.I3(rgb[6]),
.I4(rgb[5]),
.I5(rgb[4]),
.O(\dc_bias[3]_i_13_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_14
(.I0(rgb[3]),
.I1(rgb[2]),
.I2(rgb[1]),
.O(\dc_bias[3]_i_14_n_0 ));
LUT6 #(
.INIT(64'hEEE78EEE8EEE888E))
\dc_bias[3]_i_15
(.I0(\dc_bias[2]_i_13_n_0 ),
.I1(\dc_bias[2]_i_12_n_0 ),
.I2(\dc_bias[0]_i_6__0_n_0 ),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(rgb[0]),
.I5(\dc_bias[3]_i_25_n_0 ),
.O(\dc_bias[3]_i_15_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT5 #(
.INIT(32'hEBBEBEEB))
\dc_bias[3]_i_16__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(rgb[3]),
.I4(rgb[1]),
.O(\dc_bias[3]_i_16__1_n_0 ));
LUT6 #(
.INIT(64'h90F6F66F6F090990))
\dc_bias[3]_i_17__1
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[0]_i_5_n_0 ),
.I4(\dc_bias[0]_i_6__0_n_0 ),
.I5(\dc_bias[3]_i_26_n_0 ),
.O(\dc_bias[3]_i_17__1_n_0 ));
LUT6 #(
.INIT(64'hEFFF799E799EFFF7))
\dc_bias[3]_i_18
(.I0(\dc_bias[3]_i_25_n_0 ),
.I1(rgb[0]),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(\dc_bias[0]_i_6__0_n_0 ),
.I4(\dc_bias[2]_i_12_n_0 ),
.I5(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_18_n_0 ));
LUT6 #(
.INIT(64'hE00E0EE00EE0E00E))
\dc_bias[3]_i_19
(.I0(\dc_bias[3]_i_16__1_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(\dc_bias[2]_i_10__0_n_0 ),
.I3(\dc_bias[2]_i_11_n_0 ),
.I4(\dc_bias[3]_i_26_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_19_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8FFB8FFB800))
\dc_bias[3]_i_2
(.I0(\dc_bias[3]_i_3_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(\dc_bias[3]_i_5__0_n_0 ),
.I3(\dc_bias[3]_i_6_n_0 ),
.I4(\dc_bias[3]_i_7_n_0 ),
.I5(\dc_bias[3]_i_8_n_0 ),
.O(\dc_bias[3]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hDF))
\dc_bias[3]_i_20__1
(.I0(\dc_bias_reg_n_0_[0] ),
.I1(\dc_bias[0]_i_2_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\dc_bias[3]_i_20__1_n_0 ));
LUT6 #(
.INIT(64'hA96A6A5600000000))
\dc_bias[3]_i_21__0
(.I0(\dc_bias[3]_i_26_n_0 ),
.I1(\dc_bias[0]_i_6__0_n_0 ),
.I2(\dc_bias[0]_i_5_n_0 ),
.I3(rgb[0]),
.I4(\dc_bias[3]_i_25_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_21__0_n_0 ));
LUT6 #(
.INIT(64'hEFAEAE8AAE8AAE8A))
\dc_bias[3]_i_22
(.I0(\dc_bias_reg_n_0_[2] ),
.I1(\dc_bias[2]_i_15_n_0 ),
.I2(\dc_bias[2]_i_14_n_0 ),
.I3(\dc_bias_reg_n_0_[1] ),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[0]),
.O(\dc_bias[3]_i_22_n_0 ));
LUT6 #(
.INIT(64'h02BF002B002B0002))
\dc_bias[3]_i_23
(.I0(rgb[7]),
.I1(\dc_bias[2]_i_20_n_0 ),
.I2(\dc_bias[2]_i_19_n_0 ),
.I3(\dc_bias[2]_i_18_n_0 ),
.I4(\dc_bias[2]_i_17_n_0 ),
.I5(\dc_bias[2]_i_16_n_0 ),
.O(\dc_bias[3]_i_23_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF5775D55D))
\dc_bias[3]_i_24
(.I0(\dc_bias[2]_i_18_n_0 ),
.I1(\dc_bias[3]_i_4_n_0 ),
.I2(rgb[0]),
.I3(rgb[1]),
.I4(rgb[2]),
.I5(\dc_bias[3]_i_27_n_0 ),
.O(\dc_bias[3]_i_24_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'h96))
\dc_bias[3]_i_25
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.O(\dc_bias[3]_i_25_n_0 ));
LUT6 #(
.INIT(64'h963CC39669C33C69))
\dc_bias[3]_i_26
(.I0(rgb[3]),
.I1(rgb[1]),
.I2(rgb[0]),
.I3(\dc_bias[3]_i_4_n_0 ),
.I4(rgb[2]),
.I5(\dc_bias[2]_i_13_n_0 ),
.O(\dc_bias[3]_i_26_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFBEBEFF))
\dc_bias[3]_i_27
(.I0(\dc_bias[0]_i_4_n_0 ),
.I1(\encoded[6]_i_2_n_0 ),
.I2(rgb[5]),
.I3(rgb[0]),
.I4(\dc_bias_reg_n_0_[0] ),
.I5(rgb[7]),
.O(\dc_bias[3]_i_27_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hE718))
\dc_bias[3]_i_3
(.I0(\dc_bias[3]_i_9_n_0 ),
.I1(\dc_bias[3]_i_10_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(p_1_in),
.O(\dc_bias[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0022AAAA32EAAAAA))
\dc_bias[3]_i_4
(.I0(\dc_bias[3]_i_11_n_0 ),
.I1(\dc_bias[3]_i_12_n_0 ),
.I2(rgb[0]),
.I3(rgb[7]),
.I4(\dc_bias[3]_i_13_n_0 ),
.I5(\dc_bias[3]_i_14_n_0 ),
.O(\dc_bias[3]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5656566A566A6A6A))
\dc_bias[3]_i_5__0
(.I0(\dc_bias[2]_i_4__0_n_0 ),
.I1(\dc_bias[3]_i_15_n_0 ),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias[3]_i_16__1_n_0 ),
.I4(\dc_bias[3]_i_17__1_n_0 ),
.I5(\dc_bias_reg_n_0_[1] ),
.O(\dc_bias[3]_i_5__0_n_0 ));
LUT5 #(
.INIT(32'h0001FFFF))
\dc_bias[3]_i_6
(.I0(\dc_bias_reg_n_0_[1] ),
.I1(p_1_in),
.I2(\dc_bias_reg_n_0_[2] ),
.I3(\dc_bias_reg_n_0_[0] ),
.I4(\dc_bias[3]_i_18_n_0 ),
.O(\dc_bias[3]_i_6_n_0 ));
LUT6 #(
.INIT(64'h0C0000400040C0CC))
\dc_bias[3]_i_7
(.I0(\dc_bias[3]_i_19_n_0 ),
.I1(\dc_bias[2]_i_4__0_n_0 ),
.I2(\dc_bias[3]_i_20__1_n_0 ),
.I3(\dc_bias[3]_i_21__0_n_0 ),
.I4(\dc_bias_reg_n_0_[2] ),
.I5(\dc_bias[3]_i_15_n_0 ),
.O(\dc_bias[3]_i_7_n_0 ));
LUT6 #(
.INIT(64'h0000000096969996))
\dc_bias[3]_i_8
(.I0(p_1_in),
.I1(\dc_bias[3]_i_22_n_0 ),
.I2(\dc_bias[3]_i_23_n_0 ),
.I3(\dc_bias[3]_i_24_n_0 ),
.I4(\dc_bias[2]_i_5_n_0 ),
.I5(\dc_bias[2]_i_4__0_n_0 ),
.O(\dc_bias[3]_i_8_n_0 ));
LUT3 #(
.INIT(8'h17))
\dc_bias[3]_i_9
(.I0(\dc_bias[1]_i_6_n_0 ),
.I1(\dc_bias[2]_i_12_n_0 ),
.I2(\dc_bias[1]_i_7_n_0 ),
.O(\dc_bias[3]_i_9_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[0]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[0] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias_reg[1]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[1] ),
.R(SR));
MUXF7 \dc_bias_reg[1]_i_1
(.I0(\dc_bias[1]_i_2_n_0 ),
.I1(\dc_bias[1]_i_3_n_0 ),
.O(\dc_bias_reg[1]_i_1_n_0 ),
.S(\dc_bias[3]_i_6_n_0 ));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[2]_i_1_n_0 ),
.Q(\dc_bias_reg_n_0_[2] ),
.R(SR));
FDRE #(
.INIT(1'b0))
\dc_bias_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(\dc_bias[3]_i_2_n_0 ),
.Q(p_1_in),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'h28))
\encoded[0]_i_1
(.I0(active),
.I1(rgb[0]),
.I2(\encoded[9]_i_2_n_0 ),
.O(encoded[0]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT4 #(
.INIT(16'h8228))
\encoded[1]_i_1
(.I0(active),
.I1(\encoded[7]_i_3_n_0 ),
.I2(rgb[1]),
.I3(rgb[0]),
.O(encoded[1]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT5 #(
.INIT(32'h7DD7D77D))
\encoded[2]_i_1
(.I0(active),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.I4(\encoded[9]_i_2_n_0 ),
.O(encoded[2]));
LUT6 #(
.INIT(64'h8228288228828228))
\encoded[3]_i_1
(.I0(active),
.I1(rgb[2]),
.I2(rgb[1]),
.I3(rgb[0]),
.I4(rgb[3]),
.I5(\encoded[7]_i_3_n_0 ),
.O(encoded[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'h7DD7))
\encoded[4]_i_1
(.I0(active),
.I1(\encoded[6]_i_2_n_0 ),
.I2(rgb[4]),
.I3(\encoded[9]_i_2_n_0 ),
.O(encoded[4]));
LUT5 #(
.INIT(32'h82282882))
\encoded[5]_i_1
(.I0(active),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(\encoded[6]_i_2_n_0 ),
.I4(\encoded[7]_i_3_n_0 ),
.O(encoded[5]));
LUT6 #(
.INIT(64'h7DD7D77DD77D7DD7))
\encoded[6]_i_1
(.I0(active),
.I1(rgb[6]),
.I2(rgb[5]),
.I3(rgb[4]),
.I4(\encoded[6]_i_2_n_0 ),
.I5(\encoded[9]_i_2_n_0 ),
.O(encoded[6]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT4 #(
.INIT(16'h9669))
\encoded[6]_i_2
(.I0(rgb[3]),
.I1(rgb[0]),
.I2(rgb[1]),
.I3(rgb[2]),
.O(\encoded[6]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT4 #(
.INIT(16'h8228))
\encoded[7]_i_1
(.I0(active),
.I1(\encoded[7]_i_2__0_n_0 ),
.I2(rgb[7]),
.I3(\encoded[7]_i_3_n_0 ),
.O(encoded[7]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'h9669))
\encoded[7]_i_2__0
(.I0(\encoded[6]_i_2_n_0 ),
.I1(rgb[4]),
.I2(rgb[5]),
.I3(rgb[6]),
.O(\encoded[7]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h41))
\encoded[7]_i_3
(.I0(\dc_bias[3]_i_6_n_0 ),
.I1(\dc_bias[2]_i_4__0_n_0 ),
.I2(\dc_bias[3]_i_4_n_0 ),
.O(\encoded[7]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'hB))
\encoded[8]_i_1
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(active),
.O(\encoded[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT2 #(
.INIT(4'hB))
\encoded[9]_i_1__0
(.I0(\encoded[9]_i_2_n_0 ),
.I1(active),
.O(\encoded[9]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'h74))
\encoded[9]_i_2
(.I0(\dc_bias[3]_i_4_n_0 ),
.I1(\dc_bias[3]_i_6_n_0 ),
.I2(\dc_bias[2]_i_4__0_n_0 ),
.O(\encoded[9]_i_2_n_0 ));
FDRE \encoded_reg[0]
(.C(clk_25),
.CE(1'b1),
.D(encoded[0]),
.Q(\encoded_reg_n_0_[0] ),
.R(1'b0));
FDRE \encoded_reg[1]
(.C(clk_25),
.CE(1'b1),
.D(encoded[1]),
.Q(\encoded_reg_n_0_[1] ),
.R(1'b0));
FDRE \encoded_reg[2]
(.C(clk_25),
.CE(1'b1),
.D(encoded[2]),
.Q(\encoded_reg_n_0_[2] ),
.R(1'b0));
FDRE \encoded_reg[3]
(.C(clk_25),
.CE(1'b1),
.D(encoded[3]),
.Q(\encoded_reg_n_0_[3] ),
.R(1'b0));
FDRE \encoded_reg[4]
(.C(clk_25),
.CE(1'b1),
.D(encoded[4]),
.Q(\encoded_reg_n_0_[4] ),
.R(1'b0));
FDRE \encoded_reg[5]
(.C(clk_25),
.CE(1'b1),
.D(encoded[5]),
.Q(\encoded_reg_n_0_[5] ),
.R(1'b0));
FDRE \encoded_reg[6]
(.C(clk_25),
.CE(1'b1),
.D(encoded[6]),
.Q(\encoded_reg_n_0_[6] ),
.R(1'b0));
FDRE \encoded_reg[7]
(.C(clk_25),
.CE(1'b1),
.D(encoded[7]),
.Q(\encoded_reg_n_0_[7] ),
.R(1'b0));
FDRE \encoded_reg[8]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[8]_i_1_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \encoded_reg[9]
(.C(clk_25),
.CE(1'b1),
.D(\encoded[9]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[0]_i_1
(.I0(data1[0]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[0] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[1]_i_1
(.I0(data1[1]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[1] ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[2]_i_1
(.I0(data1[2]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[2] ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[3]_i_1
(.I0(data1[3]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[3] ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[4]_i_1
(.I0(data1[4]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[4] ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[5]_i_1
(.I0(data1[5]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[5] ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[6]_i_1
(.I0(data1[6]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[6] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\shift_red[7]_i_1
(.I0(data1[7]),
.I1(\shift_clock_reg[5] ),
.I2(\encoded_reg_n_0_[7] ),
.O(D[7]));
endmodule
(* ORIG_REF_NAME = "dvid" *)
module system_zybo_hdmi_0_0_dvid
(red_s,
green_s,
blue_s,
clock_s,
clk_125,
rgb,
active,
hsync,
vsync,
clk_25);
output red_s;
output green_s;
output blue_s;
output clock_s;
input clk_125;
input [23:0]rgb;
input active;
input hsync;
input vsync;
input clk_25;
wire D0;
wire D1;
wire TMDS_encoder_BLUE_n_0;
wire TMDS_encoder_BLUE_n_10;
wire TMDS_encoder_BLUE_n_9;
wire TMDS_encoder_GREEN_n_8;
wire TMDS_encoder_GREEN_n_9;
wire TMDS_encoder_RED_n_8;
wire TMDS_encoder_RED_n_9;
wire active;
wire blue_s;
wire clk_125;
wire clk_25;
wire clk_dvin;
wire clock_s;
wire [7:0]data1;
wire green_s;
wire hsync;
wire red_s;
wire [23:0]rgb;
wire [9:2]shift_blue;
wire [7:0]shift_blue_0;
wire \shift_blue_reg_n_0_[0] ;
wire \shift_blue_reg_n_0_[1] ;
wire [1:0]shift_clock;
wire \shift_clock_reg_n_0_[2] ;
wire \shift_clock_reg_n_0_[3] ;
wire \shift_clock_reg_n_0_[4] ;
wire \shift_clock_reg_n_0_[5] ;
wire \shift_clock_reg_n_0_[6] ;
wire \shift_clock_reg_n_0_[7] ;
wire \shift_clock_reg_n_0_[8] ;
wire \shift_clock_reg_n_0_[9] ;
wire [9:2]shift_green;
wire [7:0]shift_green_1;
wire \shift_green_reg_n_0_[0] ;
wire \shift_green_reg_n_0_[1] ;
wire [7:0]shift_red;
wire \shift_red[9]_i_1_n_0 ;
wire \shift_red[9]_i_2_n_0 ;
wire vsync;
wire NLW_ODDR2_BLUE_R_UNCONNECTED;
wire NLW_ODDR2_BLUE_S_UNCONNECTED;
wire NLW_ODDR2_CLK_R_UNCONNECTED;
wire NLW_ODDR2_CLK_S_UNCONNECTED;
wire NLW_ODDR2_GREEN_R_UNCONNECTED;
wire NLW_ODDR2_GREEN_S_UNCONNECTED;
wire NLW_ODDR2_RED_R_UNCONNECTED;
wire NLW_ODDR2_RED_S_UNCONNECTED;
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_BLUE
(.C(clk_125),
.CE(1'b1),
.D1(\shift_blue_reg_n_0_[0] ),
.D2(\shift_blue_reg_n_0_[1] ),
.Q(blue_s),
.R(NLW_ODDR2_BLUE_R_UNCONNECTED),
.S(NLW_ODDR2_BLUE_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_CLK
(.C(clk_125),
.CE(1'b1),
.D1(shift_clock[0]),
.D2(shift_clock[1]),
.Q(clock_s),
.R(NLW_ODDR2_CLK_R_UNCONNECTED),
.S(NLW_ODDR2_CLK_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_GREEN
(.C(clk_125),
.CE(1'b1),
.D1(\shift_green_reg_n_0_[0] ),
.D2(\shift_green_reg_n_0_[1] ),
.Q(green_s),
.R(NLW_ODDR2_GREEN_R_UNCONNECTED),
.S(NLW_ODDR2_GREEN_S_UNCONNECTED));
(* XILINX_LEGACY_PRIM = "ODDR2" *)
(* XILINX_TRANSFORM_PINMAP = "D0:D1 D1:D2 C0:C" *)
(* __SRVAL = "TRUE" *)
(* box_type = "PRIMITIVE" *)
ODDR #(
.DDR_CLK_EDGE("SAME_EDGE"),
.INIT(1'b0),
.SRTYPE("ASYNC"))
ODDR2_RED
(.C(clk_125),
.CE(1'b1),
.D1(D0),
.D2(D1),
.Q(red_s),
.R(NLW_ODDR2_RED_R_UNCONNECTED),
.S(NLW_ODDR2_RED_S_UNCONNECTED));
LUT1 #(
.INIT(2'h1))
ODDR2_RED_i_1
(.I0(clk_125),
.O(clk_dvin));
system_zybo_hdmi_0_0_TMDS_encoder TMDS_encoder_BLUE
(.D(shift_blue_0),
.Q({TMDS_encoder_BLUE_n_9,TMDS_encoder_BLUE_n_10}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.hsync(hsync),
.rgb(rgb[7:0]),
.shift_blue(shift_blue),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ),
.vsync(vsync));
system_zybo_hdmi_0_0_TMDS_encoder_0 TMDS_encoder_GREEN
(.D(shift_green_1),
.Q({TMDS_encoder_GREEN_n_8,TMDS_encoder_GREEN_n_9}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.rgb(rgb[15:8]),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ),
.shift_green(shift_green));
system_zybo_hdmi_0_0_TMDS_encoder_1 TMDS_encoder_RED
(.D(shift_red),
.Q({TMDS_encoder_RED_n_8,TMDS_encoder_RED_n_9}),
.SR(TMDS_encoder_BLUE_n_0),
.active(active),
.clk_25(clk_25),
.data1(data1),
.rgb(rgb[23:16]),
.\shift_clock_reg[5] (\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[0]),
.Q(\shift_blue_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[1]),
.Q(\shift_blue_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[2]),
.Q(shift_blue[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[3]),
.Q(shift_blue[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[4]),
.Q(shift_blue[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[5]),
.Q(shift_blue[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[6]),
.Q(shift_blue[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_blue_0[7]),
.Q(shift_blue[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_BLUE_n_10),
.Q(shift_blue[8]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_blue_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_BLUE_n_9),
.Q(shift_blue[9]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[2] ),
.Q(shift_clock[0]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[3] ),
.Q(shift_clock[1]),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[4] ),
.Q(\shift_clock_reg_n_0_[2] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[5] ),
.Q(\shift_clock_reg_n_0_[3] ),
.R(1'b0));
FDRE #(
.INIT(1'b1))
\shift_clock_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[6] ),
.Q(\shift_clock_reg_n_0_[4] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[7] ),
.Q(\shift_clock_reg_n_0_[5] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[8] ),
.Q(\shift_clock_reg_n_0_[6] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(\shift_clock_reg_n_0_[9] ),
.Q(\shift_clock_reg_n_0_[7] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(shift_clock[0]),
.Q(\shift_clock_reg_n_0_[8] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_clock_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(shift_clock[1]),
.Q(\shift_clock_reg_n_0_[9] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[0]),
.Q(\shift_green_reg_n_0_[0] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[1]),
.Q(\shift_green_reg_n_0_[1] ),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[2]),
.Q(shift_green[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[3]),
.Q(shift_green[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[4]),
.Q(shift_green[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[5]),
.Q(shift_green[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[6]),
.Q(shift_green[6]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_green_1[7]),
.Q(shift_green[7]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_green_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_GREEN_n_9),
.Q(shift_green[8]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_green_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_GREEN_n_8),
.Q(shift_green[9]),
.R(\shift_red[9]_i_1_n_0 ));
LUT5 #(
.INIT(32'hEFFFFFFF))
\shift_red[9]_i_1
(.I0(\shift_red[9]_i_2_n_0 ),
.I1(\shift_clock_reg_n_0_[5] ),
.I2(\shift_clock_reg_n_0_[4] ),
.I3(\shift_clock_reg_n_0_[2] ),
.I4(\shift_clock_reg_n_0_[3] ),
.O(\shift_red[9]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFEFFFFFFFFFFFF))
\shift_red[9]_i_2
(.I0(\shift_clock_reg_n_0_[8] ),
.I1(\shift_clock_reg_n_0_[9] ),
.I2(\shift_clock_reg_n_0_[6] ),
.I3(\shift_clock_reg_n_0_[7] ),
.I4(shift_clock[1]),
.I5(shift_clock[0]),
.O(\shift_red[9]_i_2_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_red_reg[0]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[0]),
.Q(D0),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[1]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[1]),
.Q(D1),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[2]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[2]),
.Q(data1[0]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[3]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[3]),
.Q(data1[1]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[4]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[4]),
.Q(data1[2]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[5]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[5]),
.Q(data1[3]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[6]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[6]),
.Q(data1[4]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[7]
(.C(clk_125),
.CE(1'b1),
.D(shift_red[7]),
.Q(data1[5]),
.R(1'b0));
FDRE #(
.INIT(1'b0))
\shift_red_reg[8]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_RED_n_9),
.Q(data1[6]),
.R(\shift_red[9]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\shift_red_reg[9]
(.C(clk_125),
.CE(1'b1),
.D(TMDS_encoder_RED_n_8),
.Q(data1[7]),
.R(\shift_red[9]_i_1_n_0 ));
endmodule
(* ORIG_REF_NAME = "zybo_hdmi" *)
module system_zybo_hdmi_0_0_zybo_hdmi
(tmds,
tmdsb,
rgb,
active,
hsync,
vsync,
clk_125,
clk_25);
output [3:0]tmds;
output [3:0]tmdsb;
input [23:0]rgb;
input active;
input hsync;
input vsync;
input clk_125;
input clk_25;
wire active;
wire blue_s;
wire clk_125;
wire clk_25;
wire clock_s;
wire green_s;
wire hsync;
wire red_s;
wire [23:0]rgb;
wire [3:0]tmds;
wire [3:0]tmdsb;
wire vsync;
system_zybo_hdmi_0_0_dvid DVID
(.active(active),
.blue_s(blue_s),
.clk_125(clk_125),
.clk_25(clk_25),
.clock_s(clock_s),
.green_s(green_s),
.hsync(hsync),
.red_s(red_s),
.rgb(rgb),
.vsync(vsync));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_blue
(.I(blue_s),
.O(tmds[0]),
.OB(tmdsb[0]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_clock
(.I(clock_s),
.O(tmds[3]),
.OB(tmdsb[3]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_green
(.I(red_s),
.O(tmds[2]),
.OB(tmdsb[2]));
(* CAPACITANCE = "DONT_CARE" *)
(* XILINX_LEGACY_PRIM = "OBUFDS" *)
(* box_type = "PRIMITIVE" *)
OBUFDS #(
.IOSTANDARD("DEFAULT"))
OBUFDS_red
(.I(green_s),
.O(tmds[1]),
.OB(tmdsb[1]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:26:13 AM
// Design Name:
// Module Name: Mux_8x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_8x1
(
//Input Signals
input wire [2:0] select,
input wire [7:0] ch_0,
input wire [7:0] ch_1,
input wire [7:0] ch_2,
input wire [7:0] ch_3,
input wire [7:0] ch_4,
input wire [7:0] ch_5,
input wire [7:0] ch_6,
input wire [7:0] ch_7,
//Output Signals
output reg [7:0] data_out
);
always @*
begin
case(select)
3'b111: data_out = ch_0;
3'b110: data_out = ch_1;
3'b101: data_out = ch_2;
3'b100: data_out = ch_3;
3'b011: data_out = ch_4;
3'b010: data_out = ch_5;
3'b001: data_out = ch_6;
3'b000: data_out = ch_7;
default : data_out = ch_0;
endcase
end
endmodule
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Tue Oct 25 17:51:47 2016
/////////////////////////////////////////////////////////////
module FSM_Mult_Function ( clk, rst, beg_FSM, ack_FSM, zero_flag_i,
Mult_shift_i, round_flag_i, Add_Overflow_i, load_0_o, load_1_o,
load_2_o, load_3_o, load_4_o, load_5_o, load_6_o, ctrl_select_a_o,
ctrl_select_b_o, selector_b_o, ctrl_select_c_o, exp_op_o,
shift_value_o, rst_int, ready );
output [1:0] selector_b_o;
input clk, rst, beg_FSM, ack_FSM, zero_flag_i, Mult_shift_i, round_flag_i,
Add_Overflow_i;
output load_0_o, load_1_o, load_2_o, load_3_o, load_4_o, load_5_o, load_6_o,
ctrl_select_a_o, ctrl_select_b_o, ctrl_select_c_o, exp_op_o,
shift_value_o, rst_int, ready;
wire n28, n29, n30, n31, n21, n22, n26, n24, n25, n27, n32, n33, n34, n35,
n36, n37, n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49,
n50;
wire [3:0] state_reg;
assign ctrl_select_a_o = load_1_o;
DFFRXLTS state_reg_reg_0_ ( .D(n31), .CK(clk), .RN(n26), .Q(state_reg[0]),
.QN(n49) );
DFFRXLTS state_reg_reg_2_ ( .D(n28), .CK(clk), .RN(n26), .Q(n50), .QN(n22)
);
DFFRXLTS state_reg_reg_1_ ( .D(n29), .CK(clk), .RN(n26), .Q(n48), .QN(n21)
);
DFFRXLTS state_reg_reg_3_ ( .D(n30), .CK(clk), .RN(n26), .Q(state_reg[3]),
.QN(n47) );
NAND2X1TS U3 ( .A(n21), .B(n47), .Y(n37) );
NAND2BXLTS U4 ( .AN(n32), .B(Add_Overflow_i), .Y(n36) );
NOR2X1TS U5 ( .A(state_reg[3]), .B(n40), .Y(load_1_o) );
OR2X2TS U6 ( .A(load_1_o), .B(load_3_o), .Y(load_2_o) );
NOR2X1TS U7 ( .A(n48), .B(n44), .Y(exp_op_o) );
NOR2X1TS U8 ( .A(n21), .B(n34), .Y(n25) );
NAND3X1TS U9 ( .A(n50), .B(n47), .C(n49), .Y(n44) );
NAND2BXLTS U10 ( .AN(ack_FSM), .B(ready), .Y(n38) );
OAI21XLTS U11 ( .A0(beg_FSM), .A1(n33), .B0(n38), .Y(n42) );
NAND4XLTS U12 ( .A(n21), .B(state_reg[0]), .C(n47), .D(n50), .Y(n39) );
NAND3XLTS U13 ( .A(n21), .B(n22), .C(state_reg[3]), .Y(n41) );
NAND3XLTS U14 ( .A(n22), .B(state_reg[0]), .C(n48), .Y(n40) );
NOR2XLTS U15 ( .A(n49), .B(n41), .Y(load_4_o) );
NOR2XLTS U16 ( .A(n47), .B(n40), .Y(load_5_o) );
OAI31X1TS U17 ( .A0(n21), .A1(n22), .A2(state_reg[3]), .B0(n32), .Y(load_6_o) );
NAND2X1TS U18 ( .A(n22), .B(n49), .Y(n34) );
NAND2X1TS U19 ( .A(state_reg[3]), .B(n25), .Y(n32) );
NOR4XLTS U20 ( .A(state_reg[3]), .B(n50), .C(n48), .D(n49), .Y(n24) );
CLKBUFX2TS U21 ( .A(n24), .Y(load_0_o) );
AOI31XLTS U22 ( .A0(n22), .A1(n21), .A2(state_reg[0]), .B0(n25), .Y(n27) );
OAI211XLTS U23 ( .A0(round_flag_i), .A1(n41), .B0(n27), .C0(n39), .Y(n29) );
NAND2X1TS U24 ( .A(n44), .B(n36), .Y(load_3_o) );
NOR3X1TS U25 ( .A(state_reg[3]), .B(n48), .C(n34), .Y(rst_int) );
NOR4XLTS U26 ( .A(n22), .B(state_reg[0]), .C(n48), .D(n47), .Y(ready) );
INVX2TS U27 ( .A(zero_flag_i), .Y(n43) );
AOI2BB2XLTS U28 ( .B0(exp_op_o), .B1(n43), .A0N(Mult_shift_i), .A1N(n39),
.Y(n35) );
INVX2TS U29 ( .A(rst_int), .Y(n33) );
AOI21X1TS U30 ( .A0(n35), .A1(n34), .B0(n42), .Y(n31) );
OAI21XLTS U31 ( .A0(n21), .A1(n44), .B0(n36), .Y(shift_value_o) );
AOI32X1TS U32 ( .A0(n38), .A1(n40), .A2(n37), .B0(n22), .B1(n40), .Y(n28) );
NOR2BX1TS U33 ( .AN(Mult_shift_i), .B(n39), .Y(selector_b_o[1]) );
OR2X1TS U34 ( .A(load_1_o), .B(load_4_o), .Y(selector_b_o[0]) );
OR2X1TS U35 ( .A(selector_b_o[1]), .B(selector_b_o[0]), .Y(ctrl_select_b_o)
);
NOR3BXLTS U36 ( .AN(round_flag_i), .B(n41), .C(state_reg[0]), .Y(
ctrl_select_c_o) );
INVX2TS U37 ( .A(n41), .Y(n46) );
OAI2BB2XLTS U38 ( .B0(n44), .B1(n43), .A0N(state_reg[3]), .A1N(n42), .Y(n45)
);
OR4X2TS U39 ( .A(n46), .B(load_5_o), .C(load_6_o), .D(n45), .Y(n30) );
INVX2TS U40 ( .A(rst), .Y(n26) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module First_Phase_M_W64 ( clk, rst, load, Data_MX, Data_MY, Op_MX, Op_MY );
input [63:0] Data_MX;
input [63:0] Data_MY;
output [63:0] Op_MX;
output [63:0] Op_MY;
input clk, rst, load;
wire n3, n5, n7, n9, n11, n13, n15, n17, n19, n21, n23, n25, n27, n29, n31,
n33, n35, n37, n39, n41, n43, n45, n47, n49, n51, n53, n55, n57, n59,
n61, n63, n65, n67, n69, n71, n73, n75, n77, n79, n81, n83, n85, n87,
n89, n91, n93, n95, n97, n99, n101, n103, n105, n107, n109, n111,
n113, n115, n117, n119, n121, n123, n125, n127, n129, n131, n133,
n135, n137, n139, n141, n143, n145, n147, n149, n151, n153, n155,
n157, n159, n161, n163, n165, n167, n169, n171, n173, n175, n177,
n179, n181, n183, n185, n187, n189, n191, n193, n195, n197, n199,
n201, n203, n205, n207, n209, n211, n213, n215, n217, n219, n221,
n223, n225, n227, n229, n231, n233, n235, n237, n239, n241, n243,
n245, n247, n249, n251, n253, n255, n257, n1, n2, n4, n6, n8, n10,
n12, n14, n16, n18, n20, n22, n24, n26, n28, n30, n32, n34, n36, n38,
n40, n42, n44, n46, n48, n50, n52, n54, n56, n58, n60, n62, n64, n66,
n68, n70, n72, n74, n76, n78, n80, n82;
DFFRX4TS XMRegister_Q_reg_11_ ( .D(n235), .CK(clk), .RN(n70), .Q(Op_MX[11])
);
DFFRX4TS XMRegister_Q_reg_14_ ( .D(n229), .CK(clk), .RN(n70), .Q(Op_MX[14])
);
DFFRX4TS XMRegister_Q_reg_17_ ( .D(n223), .CK(clk), .RN(n68), .Q(Op_MX[17])
);
DFFRX4TS XMRegister_Q_reg_20_ ( .D(n217), .CK(clk), .RN(n68), .Q(Op_MX[20])
);
DFFRX4TS XMRegister_Q_reg_23_ ( .D(n211), .CK(clk), .RN(n68), .Q(Op_MX[23])
);
DFFRX4TS XMRegister_Q_reg_26_ ( .D(n205), .CK(clk), .RN(n66), .Q(Op_MX[26])
);
DFFRX4TS XMRegister_Q_reg_41_ ( .D(n175), .CK(clk), .RN(n64), .Q(Op_MX[41])
);
DFFRX4TS XMRegister_Q_reg_47_ ( .D(n163), .CK(clk), .RN(n62), .Q(Op_MX[47])
);
DFFRXLTS XMRegister_Q_reg_63_ ( .D(n131), .CK(clk), .RN(n60), .Q(Op_MX[63])
);
DFFRX4TS YMRegister_Q_reg_11_ ( .D(n107), .CK(clk), .RN(n80), .Q(Op_MY[11])
);
DFFRX4TS YMRegister_Q_reg_14_ ( .D(n101), .CK(clk), .RN(n80), .Q(Op_MY[14])
);
DFFRX4TS YMRegister_Q_reg_30_ ( .D(n69), .CK(clk), .RN(n76), .Q(Op_MY[30])
);
DFFRX4TS YMRegister_Q_reg_38_ ( .D(n53), .CK(clk), .RN(n74), .Q(Op_MY[38])
);
DFFRXLTS YMRegister_Q_reg_63_ ( .D(n3), .CK(clk), .RN(n62), .Q(Op_MY[63]) );
DFFRXLTS XMRegister_Q_reg_52_ ( .D(n153), .CK(clk), .RN(n58), .Q(Op_MX[52])
);
DFFRXLTS XMRegister_Q_reg_53_ ( .D(n151), .CK(clk), .RN(n58), .Q(Op_MX[53])
);
DFFRXLTS XMRegister_Q_reg_54_ ( .D(n149), .CK(clk), .RN(n58), .Q(Op_MX[54])
);
DFFRXLTS XMRegister_Q_reg_55_ ( .D(n147), .CK(clk), .RN(n58), .Q(Op_MX[55])
);
DFFRXLTS XMRegister_Q_reg_56_ ( .D(n145), .CK(clk), .RN(n58), .Q(Op_MX[56])
);
DFFRXLTS XMRegister_Q_reg_57_ ( .D(n143), .CK(clk), .RN(n58), .Q(Op_MX[57])
);
DFFRXLTS XMRegister_Q_reg_58_ ( .D(n141), .CK(clk), .RN(n58), .Q(Op_MX[58])
);
DFFRXLTS XMRegister_Q_reg_59_ ( .D(n139), .CK(clk), .RN(n58), .Q(Op_MX[59])
);
DFFRXLTS XMRegister_Q_reg_60_ ( .D(n137), .CK(clk), .RN(n58), .Q(Op_MX[60])
);
DFFRXLTS XMRegister_Q_reg_61_ ( .D(n135), .CK(clk), .RN(n58), .Q(Op_MX[61])
);
DFFRXLTS XMRegister_Q_reg_62_ ( .D(n133), .CK(clk), .RN(n60), .Q(Op_MX[62])
);
DFFRXLTS YMRegister_Q_reg_52_ ( .D(n25), .CK(clk), .RN(n60), .Q(Op_MY[52])
);
DFFRXLTS YMRegister_Q_reg_53_ ( .D(n23), .CK(clk), .RN(n60), .Q(Op_MY[53])
);
DFFRXLTS YMRegister_Q_reg_54_ ( .D(n21), .CK(clk), .RN(n60), .Q(Op_MY[54])
);
DFFRXLTS YMRegister_Q_reg_55_ ( .D(n19), .CK(clk), .RN(n60), .Q(Op_MY[55])
);
DFFRXLTS YMRegister_Q_reg_56_ ( .D(n17), .CK(clk), .RN(n60), .Q(Op_MY[56])
);
DFFRXLTS YMRegister_Q_reg_57_ ( .D(n15), .CK(clk), .RN(n60), .Q(Op_MY[57])
);
DFFRXLTS YMRegister_Q_reg_58_ ( .D(n13), .CK(clk), .RN(n60), .Q(Op_MY[58])
);
DFFRXLTS YMRegister_Q_reg_59_ ( .D(n11), .CK(clk), .RN(n60), .Q(Op_MY[59])
);
DFFRXLTS YMRegister_Q_reg_60_ ( .D(n9), .CK(clk), .RN(n62), .Q(Op_MY[60]) );
DFFRXLTS YMRegister_Q_reg_61_ ( .D(n7), .CK(clk), .RN(n62), .Q(Op_MY[61]) );
DFFRXLTS YMRegister_Q_reg_62_ ( .D(n5), .CK(clk), .RN(n62), .Q(Op_MY[62]) );
DFFRXLTS YMRegister_Q_reg_0_ ( .D(n129), .CK(clk), .RN(n82), .Q(Op_MY[0]) );
DFFRXLTS YMRegister_Q_reg_28_ ( .D(n73), .CK(clk), .RN(n76), .Q(Op_MY[28])
);
DFFRXLTS YMRegister_Q_reg_31_ ( .D(n67), .CK(clk), .RN(n76), .Q(Op_MY[31])
);
DFFRXLTS YMRegister_Q_reg_35_ ( .D(n59), .CK(clk), .RN(n76), .Q(Op_MY[35])
);
DFFRXLTS XMRegister_Q_reg_29_ ( .D(n199), .CK(clk), .RN(n66), .Q(Op_MX[29])
);
DFFRXLTS XMRegister_Q_reg_1_ ( .D(n255), .CK(clk), .RN(n72), .Q(Op_MX[1]) );
DFFRXLTS XMRegister_Q_reg_28_ ( .D(n201), .CK(clk), .RN(n66), .Q(Op_MX[28])
);
DFFRXLTS XMRegister_Q_reg_34_ ( .D(n189), .CK(clk), .RN(n66), .Q(Op_MX[34])
);
DFFRX1TS XMRegister_Q_reg_12_ ( .D(n233), .CK(clk), .RN(n70), .Q(Op_MX[12])
);
DFFRX1TS XMRegister_Q_reg_30_ ( .D(n197), .CK(clk), .RN(n66), .Q(Op_MX[30])
);
DFFRXLTS YMRegister_Q_reg_25_ ( .D(n79), .CK(clk), .RN(n78), .Q(Op_MY[25])
);
DFFRXLTS YMRegister_Q_reg_24_ ( .D(n81), .CK(clk), .RN(n78), .Q(Op_MY[24])
);
DFFRXLTS YMRegister_Q_reg_26_ ( .D(n77), .CK(clk), .RN(n78), .Q(Op_MY[26])
);
DFFRXLTS YMRegister_Q_reg_51_ ( .D(n27), .CK(clk), .RN(n72), .Q(Op_MY[51])
);
DFFRXLTS XMRegister_Q_reg_32_ ( .D(n193), .CK(clk), .RN(n66), .Q(Op_MX[32])
);
DFFRXLTS YMRegister_Q_reg_50_ ( .D(n29), .CK(clk), .RN(n72), .Q(Op_MY[50])
);
DFFRXLTS XMRegister_Q_reg_0_ ( .D(n257), .CK(clk), .RN(n72), .Q(Op_MX[0]) );
DFFRXLTS XMRegister_Q_reg_2_ ( .D(n253), .CK(clk), .RN(n72), .Q(Op_MX[2]) );
DFFRX1TS XMRegister_Q_reg_3_ ( .D(n251), .CK(clk), .RN(n72), .Q(Op_MX[3]) );
DFFRX1TS XMRegister_Q_reg_4_ ( .D(n249), .CK(clk), .RN(n72), .Q(Op_MX[4]) );
DFFRXLTS XMRegister_Q_reg_8_ ( .D(n241), .CK(clk), .RN(n70), .Q(Op_MX[8]) );
DFFRX1TS XMRegister_Q_reg_9_ ( .D(n239), .CK(clk), .RN(n70), .Q(Op_MX[9]) );
DFFRX1TS XMRegister_Q_reg_10_ ( .D(n237), .CK(clk), .RN(n70), .Q(Op_MX[10])
);
DFFRXLTS XMRegister_Q_reg_13_ ( .D(n231), .CK(clk), .RN(n70), .Q(Op_MX[13])
);
DFFRX1TS XMRegister_Q_reg_15_ ( .D(n227), .CK(clk), .RN(n70), .Q(Op_MX[15])
);
DFFRX1TS XMRegister_Q_reg_16_ ( .D(n225), .CK(clk), .RN(n68), .Q(Op_MX[16])
);
DFFRX1TS XMRegister_Q_reg_19_ ( .D(n219), .CK(clk), .RN(n68), .Q(Op_MX[19])
);
DFFRX1TS XMRegister_Q_reg_21_ ( .D(n215), .CK(clk), .RN(n68), .Q(Op_MX[21])
);
DFFRX1TS XMRegister_Q_reg_22_ ( .D(n213), .CK(clk), .RN(n68), .Q(Op_MX[22])
);
DFFRX1TS XMRegister_Q_reg_25_ ( .D(n207), .CK(clk), .RN(n68), .Q(Op_MX[25])
);
DFFRXLTS XMRegister_Q_reg_27_ ( .D(n203), .CK(clk), .RN(n66), .Q(Op_MX[27])
);
DFFRX1TS XMRegister_Q_reg_31_ ( .D(n195), .CK(clk), .RN(n66), .Q(Op_MX[31])
);
DFFRX1TS XMRegister_Q_reg_33_ ( .D(n191), .CK(clk), .RN(n66), .Q(Op_MX[33])
);
DFFRX1TS XMRegister_Q_reg_36_ ( .D(n185), .CK(clk), .RN(n64), .Q(Op_MX[36])
);
DFFRX1TS XMRegister_Q_reg_37_ ( .D(n183), .CK(clk), .RN(n64), .Q(Op_MX[37])
);
DFFRXLTS XMRegister_Q_reg_38_ ( .D(n181), .CK(clk), .RN(n64), .Q(Op_MX[38])
);
DFFRX1TS XMRegister_Q_reg_39_ ( .D(n179), .CK(clk), .RN(n64), .Q(Op_MX[39])
);
DFFRX1TS XMRegister_Q_reg_43_ ( .D(n171), .CK(clk), .RN(n64), .Q(Op_MX[43])
);
DFFRX1TS XMRegister_Q_reg_45_ ( .D(n167), .CK(clk), .RN(n64), .Q(Op_MX[45])
);
DFFRX1TS XMRegister_Q_reg_46_ ( .D(n165), .CK(clk), .RN(n62), .Q(Op_MX[46])
);
DFFRX1TS XMRegister_Q_reg_49_ ( .D(n159), .CK(clk), .RN(n62), .Q(Op_MX[49])
);
DFFRXLTS XMRegister_Q_reg_50_ ( .D(n157), .CK(clk), .RN(n62), .Q(Op_MX[50])
);
DFFRXLTS YMRegister_Q_reg_7_ ( .D(n115), .CK(clk), .RN(n82), .Q(Op_MY[7]) );
DFFRXLTS YMRegister_Q_reg_13_ ( .D(n103), .CK(clk), .RN(n80), .Q(Op_MY[13])
);
DFFRXLTS YMRegister_Q_reg_16_ ( .D(n97), .CK(clk), .RN(n80), .Q(Op_MY[16])
);
DFFRXLTS YMRegister_Q_reg_27_ ( .D(n75), .CK(clk), .RN(n78), .Q(Op_MY[27])
);
DFFRX2TS YMRegister_Q_reg_32_ ( .D(n65), .CK(clk), .RN(n76), .Q(Op_MY[32])
);
DFFRX1TS YMRegister_Q_reg_33_ ( .D(n63), .CK(clk), .RN(n76), .Q(Op_MY[33])
);
DFFRXLTS YMRegister_Q_reg_34_ ( .D(n61), .CK(clk), .RN(n76), .Q(Op_MY[34])
);
DFFRXLTS YMRegister_Q_reg_41_ ( .D(n47), .CK(clk), .RN(n74), .Q(Op_MY[41])
);
DFFRXLTS YMRegister_Q_reg_43_ ( .D(n43), .CK(clk), .RN(n74), .Q(Op_MY[43])
);
DFFRXLTS XMRegister_Q_reg_24_ ( .D(n209), .CK(clk), .RN(n68), .Q(Op_MX[24])
);
DFFRXLTS XMRegister_Q_reg_51_ ( .D(n155), .CK(clk), .RN(n62), .Q(Op_MX[51])
);
DFFRXLTS XMRegister_Q_reg_7_ ( .D(n243), .CK(clk), .RN(n70), .Q(Op_MX[7]) );
DFFRXLTS XMRegister_Q_reg_40_ ( .D(n177), .CK(clk), .RN(n64), .Q(Op_MX[40])
);
DFFRXLTS YMRegister_Q_reg_48_ ( .D(n33), .CK(clk), .RN(n72), .Q(Op_MY[48])
);
DFFRXLTS YMRegister_Q_reg_49_ ( .D(n31), .CK(clk), .RN(n72), .Q(Op_MY[49])
);
DFFRXLTS YMRegister_Q_reg_23_ ( .D(n83), .CK(clk), .RN(n78), .Q(Op_MY[23])
);
DFFRXLTS YMRegister_Q_reg_21_ ( .D(n87), .CK(clk), .RN(n78), .Q(Op_MY[21])
);
DFFRXLTS YMRegister_Q_reg_20_ ( .D(n89), .CK(clk), .RN(n78), .Q(Op_MY[20])
);
DFFRXLTS YMRegister_Q_reg_19_ ( .D(n91), .CK(clk), .RN(n78), .Q(Op_MY[19])
);
DFFRXLTS YMRegister_Q_reg_10_ ( .D(n109), .CK(clk), .RN(n80), .Q(Op_MY[10])
);
DFFRXLTS YMRegister_Q_reg_9_ ( .D(n111), .CK(clk), .RN(n80), .Q(Op_MY[9]) );
DFFRXLTS YMRegister_Q_reg_8_ ( .D(n113), .CK(clk), .RN(n80), .Q(Op_MY[8]) );
DFFRXLTS YMRegister_Q_reg_1_ ( .D(n127), .CK(clk), .RN(n82), .Q(Op_MY[1]) );
DFFRXLTS XMRegister_Q_reg_44_ ( .D(n169), .CK(clk), .RN(n64), .Q(Op_MX[44])
);
DFFRXLTS XMRegister_Q_reg_35_ ( .D(n187), .CK(clk), .RN(n66), .Q(Op_MX[35])
);
DFFRXLTS YMRegister_Q_reg_47_ ( .D(n35), .CK(clk), .RN(n74), .Q(Op_MY[47])
);
DFFRXLTS YMRegister_Q_reg_46_ ( .D(n37), .CK(clk), .RN(n74), .Q(Op_MY[46])
);
DFFRXLTS YMRegister_Q_reg_44_ ( .D(n41), .CK(clk), .RN(n74), .Q(Op_MY[44])
);
DFFRXLTS YMRegister_Q_reg_37_ ( .D(n55), .CK(clk), .RN(n76), .Q(Op_MY[37])
);
DFFRXLTS YMRegister_Q_reg_36_ ( .D(n57), .CK(clk), .RN(n76), .Q(Op_MY[36])
);
DFFRXLTS YMRegister_Q_reg_17_ ( .D(n95), .CK(clk), .RN(n80), .Q(Op_MY[17])
);
DFFRXLTS YMRegister_Q_reg_15_ ( .D(n99), .CK(clk), .RN(n80), .Q(Op_MY[15])
);
DFFRXLTS YMRegister_Q_reg_3_ ( .D(n123), .CK(clk), .RN(n82), .Q(Op_MY[3]) );
DFFRXLTS YMRegister_Q_reg_42_ ( .D(n45), .CK(clk), .RN(n74), .Q(Op_MY[42])
);
DFFRX2TS XMRegister_Q_reg_42_ ( .D(n173), .CK(clk), .RN(n64), .Q(Op_MX[42])
);
DFFRX4TS XMRegister_Q_reg_5_ ( .D(n247), .CK(clk), .RN(n72), .Q(Op_MX[5]) );
DFFRX1TS YMRegister_Q_reg_4_ ( .D(n121), .CK(clk), .RN(n82), .Q(Op_MY[4]) );
DFFRXLTS YMRegister_Q_reg_5_ ( .D(n119), .CK(clk), .RN(n82), .Q(Op_MY[5]) );
DFFRXLTS YMRegister_Q_reg_45_ ( .D(n39), .CK(clk), .RN(n74), .Q(Op_MY[45])
);
DFFRXLTS XMRegister_Q_reg_18_ ( .D(n221), .CK(clk), .RN(n68), .Q(Op_MX[18])
);
DFFRXLTS XMRegister_Q_reg_48_ ( .D(n161), .CK(clk), .RN(n62), .Q(Op_MX[48])
);
DFFRXLTS YMRegister_Q_reg_22_ ( .D(n85), .CK(clk), .RN(n78), .Q(Op_MY[22])
);
DFFRX2TS YMRegister_Q_reg_29_ ( .D(n71), .CK(clk), .RN(n76), .Q(Op_MY[29])
);
DFFRX2TS YMRegister_Q_reg_2_ ( .D(n125), .CK(clk), .RN(n82), .Q(Op_MY[2]) );
DFFRX2TS YMRegister_Q_reg_12_ ( .D(n105), .CK(clk), .RN(n80), .Q(Op_MY[12])
);
DFFRX2TS YMRegister_Q_reg_39_ ( .D(n51), .CK(clk), .RN(n74), .Q(Op_MY[39])
);
DFFRX2TS YMRegister_Q_reg_40_ ( .D(n49), .CK(clk), .RN(n74), .Q(Op_MY[40])
);
DFFRX2TS YMRegister_Q_reg_6_ ( .D(n117), .CK(clk), .RN(n82), .Q(Op_MY[6]) );
DFFRX2TS YMRegister_Q_reg_18_ ( .D(n93), .CK(clk), .RN(n78), .Q(Op_MY[18])
);
DFFRX2TS XMRegister_Q_reg_6_ ( .D(n245), .CK(clk), .RN(n70), .Q(Op_MX[6]) );
INVX2TS U1 ( .A(n50), .Y(n52) );
CLKBUFX2TS U2 ( .A(n46), .Y(n48) );
CLKBUFX2TS U3 ( .A(n46), .Y(n50) );
CLKBUFX2TS U4 ( .A(n50), .Y(n54) );
INVX2TS U5 ( .A(rst), .Y(n38) );
CLKBUFX2TS U6 ( .A(n38), .Y(n1) );
CLKBUFX2TS U7 ( .A(n1), .Y(n74) );
CLKBUFX2TS U8 ( .A(n1), .Y(n82) );
CLKBUFX2TS U9 ( .A(n1), .Y(n64) );
CLKBUFX2TS U10 ( .A(n1), .Y(n76) );
CLKBUFX2TS U11 ( .A(n1), .Y(n72) );
CLKBUFX2TS U12 ( .A(n1), .Y(n78) );
CLKBUFX2TS U13 ( .A(n1), .Y(n62) );
INVX2TS U14 ( .A(load), .Y(n46) );
INVX2TS U15 ( .A(n48), .Y(n56) );
MX2X1TS U16 ( .A(Op_MX[51]), .B(Data_MX[51]), .S0(n56), .Y(n155) );
MX2X1TS U17 ( .A(Op_MX[50]), .B(Data_MX[50]), .S0(n56), .Y(n157) );
MX2X1TS U18 ( .A(Op_MX[49]), .B(Data_MX[49]), .S0(n56), .Y(n159) );
MX2X1TS U19 ( .A(Op_MX[48]), .B(Data_MX[48]), .S0(n56), .Y(n161) );
INVX2TS U20 ( .A(n54), .Y(n24) );
MX2X1TS U21 ( .A(Op_MY[51]), .B(Data_MY[51]), .S0(n24), .Y(n27) );
MX2X1TS U22 ( .A(Op_MY[50]), .B(Data_MY[50]), .S0(n24), .Y(n29) );
INVX2TS U23 ( .A(n48), .Y(n2) );
MX2X1TS U24 ( .A(Op_MY[49]), .B(Data_MY[49]), .S0(n2), .Y(n31) );
MX2X1TS U25 ( .A(Op_MY[48]), .B(Data_MY[48]), .S0(n2), .Y(n33) );
MX2X1TS U26 ( .A(Op_MY[47]), .B(Data_MY[47]), .S0(n2), .Y(n35) );
MX2X1TS U27 ( .A(Op_MY[46]), .B(Data_MY[46]), .S0(n2), .Y(n37) );
MX2X1TS U28 ( .A(Op_MY[45]), .B(Data_MY[45]), .S0(n2), .Y(n39) );
MX2X1TS U29 ( .A(Op_MY[44]), .B(Data_MY[44]), .S0(n2), .Y(n41) );
MX2X1TS U30 ( .A(Op_MY[43]), .B(Data_MY[43]), .S0(n2), .Y(n43) );
MX2X1TS U31 ( .A(Op_MY[42]), .B(Data_MY[42]), .S0(n2), .Y(n45) );
MX2X1TS U32 ( .A(Op_MY[41]), .B(Data_MY[41]), .S0(n2), .Y(n47) );
MX2X1TS U33 ( .A(Op_MY[40]), .B(Data_MY[40]), .S0(n2), .Y(n49) );
INVX2TS U34 ( .A(n54), .Y(n4) );
MX2X1TS U35 ( .A(Op_MX[47]), .B(Data_MX[47]), .S0(n4), .Y(n163) );
MX2X1TS U36 ( .A(Op_MX[46]), .B(Data_MX[46]), .S0(n4), .Y(n165) );
MX2X1TS U37 ( .A(Op_MX[45]), .B(Data_MX[45]), .S0(n4), .Y(n167) );
MX2X1TS U38 ( .A(Op_MX[44]), .B(Data_MX[44]), .S0(n4), .Y(n169) );
MX2X1TS U39 ( .A(Op_MX[43]), .B(Data_MX[43]), .S0(n4), .Y(n171) );
MX2X1TS U40 ( .A(Op_MX[42]), .B(Data_MX[42]), .S0(n4), .Y(n173) );
MX2X1TS U41 ( .A(Op_MX[41]), .B(Data_MX[41]), .S0(n4), .Y(n175) );
MX2X1TS U42 ( .A(Op_MX[40]), .B(Data_MX[40]), .S0(n4), .Y(n177) );
MX2X1TS U43 ( .A(Op_MX[39]), .B(Data_MX[39]), .S0(n4), .Y(n179) );
MX2X1TS U44 ( .A(Op_MX[38]), .B(Data_MX[38]), .S0(n4), .Y(n181) );
INVX2TS U45 ( .A(n54), .Y(n34) );
MX2X1TS U46 ( .A(Op_MX[37]), .B(Data_MX[37]), .S0(n34), .Y(n183) );
MX2X1TS U47 ( .A(Op_MX[36]), .B(Data_MX[36]), .S0(n34), .Y(n185) );
MX2X1TS U48 ( .A(Op_MX[34]), .B(Data_MX[34]), .S0(n34), .Y(n189) );
MX2X1TS U49 ( .A(Op_MX[33]), .B(Data_MX[33]), .S0(n34), .Y(n191) );
MX2X1TS U50 ( .A(Op_MX[32]), .B(Data_MX[32]), .S0(n34), .Y(n193) );
MX2X1TS U51 ( .A(Op_MX[31]), .B(Data_MX[31]), .S0(n34), .Y(n195) );
MX2X1TS U52 ( .A(Op_MX[30]), .B(Data_MX[30]), .S0(n34), .Y(n197) );
MX2X1TS U53 ( .A(Op_MX[28]), .B(Data_MX[28]), .S0(n34), .Y(n201) );
MX2X1TS U54 ( .A(Op_MX[27]), .B(Data_MX[27]), .S0(n44), .Y(n203) );
MX2X1TS U55 ( .A(Op_MX[26]), .B(Data_MX[26]), .S0(n44), .Y(n205) );
MX2X1TS U56 ( .A(Op_MX[25]), .B(Data_MX[25]), .S0(load), .Y(n207) );
MX2X1TS U57 ( .A(Op_MX[24]), .B(Data_MX[24]), .S0(load), .Y(n209) );
MX2X1TS U58 ( .A(Op_MX[23]), .B(Data_MX[23]), .S0(load), .Y(n211) );
MX2X1TS U59 ( .A(Op_MX[22]), .B(Data_MX[22]), .S0(load), .Y(n213) );
MX2X1TS U60 ( .A(Op_MX[21]), .B(Data_MX[21]), .S0(load), .Y(n215) );
MX2X1TS U61 ( .A(Op_MX[20]), .B(Data_MX[20]), .S0(load), .Y(n217) );
MX2X1TS U62 ( .A(Op_MX[19]), .B(Data_MX[19]), .S0(load), .Y(n219) );
MX2X1TS U63 ( .A(Op_MX[18]), .B(Data_MX[18]), .S0(load), .Y(n221) );
MX2X1TS U64 ( .A(Op_MX[7]), .B(Data_MX[7]), .S0(n24), .Y(n243) );
MX2X1TS U65 ( .A(Op_MX[6]), .B(Data_MX[6]), .S0(n24), .Y(n245) );
MX2X1TS U66 ( .A(Op_MX[5]), .B(Data_MX[5]), .S0(n24), .Y(n247) );
MX2X1TS U67 ( .A(Op_MX[4]), .B(Data_MX[4]), .S0(n24), .Y(n249) );
MX2X1TS U68 ( .A(Op_MX[3]), .B(Data_MX[3]), .S0(n24), .Y(n251) );
MX2X1TS U69 ( .A(Op_MX[1]), .B(Data_MX[1]), .S0(n24), .Y(n255) );
MX2X1TS U70 ( .A(Op_MX[0]), .B(Data_MX[0]), .S0(n24), .Y(n257) );
INVX2TS U71 ( .A(n50), .Y(n10) );
MX2X1TS U72 ( .A(Op_MX[17]), .B(Data_MX[17]), .S0(n10), .Y(n223) );
MX2X1TS U73 ( .A(Op_MX[16]), .B(Data_MX[16]), .S0(n10), .Y(n225) );
MX2X1TS U74 ( .A(Op_MX[15]), .B(Data_MX[15]), .S0(n10), .Y(n227) );
MX2X1TS U75 ( .A(Op_MX[14]), .B(Data_MX[14]), .S0(n10), .Y(n229) );
MX2X1TS U76 ( .A(Op_MX[13]), .B(Data_MX[13]), .S0(n10), .Y(n231) );
MX2X1TS U77 ( .A(Op_MX[12]), .B(Data_MX[12]), .S0(n10), .Y(n233) );
MX2X1TS U78 ( .A(Op_MX[11]), .B(Data_MX[11]), .S0(n10), .Y(n235) );
MX2X1TS U79 ( .A(Op_MX[10]), .B(Data_MX[10]), .S0(n10), .Y(n237) );
MX2X1TS U80 ( .A(Op_MX[9]), .B(Data_MX[9]), .S0(n10), .Y(n239) );
INVX2TS U81 ( .A(n48), .Y(n14) );
MX2X1TS U82 ( .A(Op_MY[39]), .B(Data_MY[39]), .S0(n14), .Y(n51) );
MX2X1TS U83 ( .A(Op_MY[38]), .B(Data_MY[38]), .S0(n14), .Y(n53) );
MX2X1TS U84 ( .A(Op_MY[37]), .B(Data_MY[37]), .S0(n14), .Y(n55) );
MX2X1TS U85 ( .A(Op_MY[36]), .B(Data_MY[36]), .S0(n14), .Y(n57) );
MX2X1TS U86 ( .A(Op_MY[34]), .B(Data_MY[34]), .S0(n14), .Y(n61) );
MX2X1TS U87 ( .A(Op_MY[33]), .B(Data_MY[33]), .S0(n14), .Y(n63) );
MX2X1TS U88 ( .A(Op_MY[32]), .B(Data_MY[32]), .S0(n14), .Y(n65) );
MX2X1TS U89 ( .A(Op_MY[30]), .B(Data_MY[30]), .S0(n14), .Y(n69) );
INVX2TS U90 ( .A(n48), .Y(n30) );
MX2X1TS U91 ( .A(Op_MY[29]), .B(Data_MY[29]), .S0(n30), .Y(n71) );
MX2X1TS U92 ( .A(Op_MY[26]), .B(Data_MY[26]), .S0(n30), .Y(n77) );
MX2X1TS U93 ( .A(Op_MY[25]), .B(Data_MY[25]), .S0(n30), .Y(n79) );
MX2X1TS U94 ( .A(Op_MY[24]), .B(Data_MY[24]), .S0(n30), .Y(n81) );
MX2X1TS U95 ( .A(Op_MY[23]), .B(Data_MY[23]), .S0(n30), .Y(n83) );
MX2X1TS U96 ( .A(Op_MY[22]), .B(Data_MY[22]), .S0(n30), .Y(n85) );
MX2X1TS U97 ( .A(Op_MY[21]), .B(Data_MY[21]), .S0(n30), .Y(n87) );
MX2X1TS U98 ( .A(Op_MY[20]), .B(Data_MY[20]), .S0(n30), .Y(n89) );
INVX2TS U99 ( .A(n48), .Y(n6) );
MX2X1TS U100 ( .A(Op_MY[19]), .B(Data_MY[19]), .S0(n6), .Y(n91) );
MX2X1TS U101 ( .A(Op_MY[18]), .B(Data_MY[18]), .S0(n6), .Y(n93) );
MX2X1TS U102 ( .A(Op_MY[17]), .B(Data_MY[17]), .S0(n6), .Y(n95) );
MX2X1TS U103 ( .A(Op_MY[16]), .B(Data_MY[16]), .S0(n6), .Y(n97) );
MX2X1TS U104 ( .A(Op_MY[15]), .B(Data_MY[15]), .S0(n6), .Y(n99) );
MX2X1TS U105 ( .A(Op_MY[14]), .B(Data_MY[14]), .S0(n6), .Y(n101) );
MX2X1TS U106 ( .A(Op_MY[13]), .B(Data_MY[13]), .S0(n6), .Y(n103) );
MX2X1TS U107 ( .A(Op_MY[12]), .B(Data_MY[12]), .S0(n6), .Y(n105) );
MX2X1TS U108 ( .A(Op_MY[11]), .B(Data_MY[11]), .S0(n6), .Y(n107) );
MX2X1TS U109 ( .A(Op_MY[10]), .B(Data_MY[10]), .S0(n6), .Y(n109) );
INVX2TS U110 ( .A(n48), .Y(n40) );
MX2X1TS U111 ( .A(Op_MY[9]), .B(Data_MY[9]), .S0(n40), .Y(n111) );
MX2X1TS U112 ( .A(Op_MY[8]), .B(Data_MY[8]), .S0(n40), .Y(n113) );
MX2X1TS U113 ( .A(Op_MY[7]), .B(Data_MY[7]), .S0(n40), .Y(n115) );
MX2X1TS U114 ( .A(Op_MY[6]), .B(Data_MY[6]), .S0(n40), .Y(n117) );
MX2X1TS U115 ( .A(Op_MY[5]), .B(Data_MY[5]), .S0(n40), .Y(n119) );
MX2X1TS U116 ( .A(Op_MY[3]), .B(Data_MY[3]), .S0(n40), .Y(n123) );
MX2X1TS U117 ( .A(Op_MY[2]), .B(Data_MY[2]), .S0(n40), .Y(n125) );
CLKBUFX2TS U118 ( .A(Op_MY[35]), .Y(n8) );
MX2X1TS U119 ( .A(n8), .B(Data_MY[35]), .S0(n14), .Y(n59) );
CLKBUFX2TS U120 ( .A(Op_MX[8]), .Y(n12) );
MX2X1TS U121 ( .A(n12), .B(Data_MX[8]), .S0(n10), .Y(n241) );
CLKBUFX2TS U122 ( .A(Op_MY[31]), .Y(n16) );
MX2X1TS U123 ( .A(n16), .B(Data_MY[31]), .S0(n14), .Y(n67) );
CLKBUFX2TS U124 ( .A(Op_MX[35]), .Y(n18) );
MX2X1TS U125 ( .A(n18), .B(Data_MX[35]), .S0(n34), .Y(n187) );
CLKBUFX2TS U126 ( .A(Op_MY[1]), .Y(n20) );
MX2X1TS U127 ( .A(n20), .B(Data_MY[1]), .S0(n40), .Y(n127) );
CLKBUFX2TS U128 ( .A(Op_MY[28]), .Y(n22) );
MX2X1TS U129 ( .A(n22), .B(Data_MY[28]), .S0(n30), .Y(n73) );
CLKBUFX2TS U130 ( .A(Op_MX[2]), .Y(n26) );
MX2X1TS U131 ( .A(n26), .B(Data_MX[2]), .S0(n24), .Y(n253) );
CLKBUFX2TS U132 ( .A(Op_MY[0]), .Y(n28) );
MX2X1TS U133 ( .A(n28), .B(Data_MY[0]), .S0(n40), .Y(n129) );
CLKBUFX2TS U134 ( .A(Op_MY[27]), .Y(n32) );
MX2X1TS U135 ( .A(n32), .B(Data_MY[27]), .S0(n30), .Y(n75) );
CLKBUFX2TS U136 ( .A(Op_MX[29]), .Y(n36) );
MX2X1TS U137 ( .A(n36), .B(Data_MX[29]), .S0(n34), .Y(n199) );
CLKBUFX2TS U138 ( .A(n38), .Y(n58) );
CLKBUFX2TS U139 ( .A(n38), .Y(n60) );
CLKBUFX2TS U140 ( .A(n38), .Y(n66) );
CLKBUFX2TS U141 ( .A(n38), .Y(n68) );
CLKBUFX2TS U142 ( .A(n38), .Y(n70) );
CLKBUFX2TS U143 ( .A(n38), .Y(n80) );
CLKBUFX2TS U144 ( .A(Op_MY[4]), .Y(n42) );
MX2X1TS U145 ( .A(n42), .B(Data_MY[4]), .S0(n40), .Y(n121) );
INVX2TS U146 ( .A(n54), .Y(n44) );
AO22XLTS U147 ( .A0(n44), .A1(Data_MX[52]), .B0(n48), .B1(Op_MX[52]), .Y(
n153) );
AO22XLTS U148 ( .A0(n44), .A1(Data_MX[53]), .B0(n50), .B1(Op_MX[53]), .Y(
n151) );
AO22XLTS U149 ( .A0(n44), .A1(Data_MX[54]), .B0(n54), .B1(Op_MX[54]), .Y(
n149) );
AO22XLTS U150 ( .A0(n44), .A1(Data_MX[55]), .B0(n46), .B1(Op_MX[55]), .Y(
n147) );
AO22XLTS U151 ( .A0(n44), .A1(Data_MX[56]), .B0(n46), .B1(Op_MX[56]), .Y(
n145) );
AO22XLTS U152 ( .A0(n44), .A1(Data_MX[57]), .B0(n46), .B1(Op_MX[57]), .Y(
n143) );
AO22XLTS U153 ( .A0(n44), .A1(Data_MX[58]), .B0(n46), .B1(Op_MX[58]), .Y(
n141) );
AO22XLTS U154 ( .A0(n44), .A1(Data_MX[59]), .B0(n46), .B1(Op_MX[59]), .Y(
n139) );
AO22XLTS U155 ( .A0(n52), .A1(Data_MX[60]), .B0(n46), .B1(Op_MX[60]), .Y(
n137) );
AO22XLTS U156 ( .A0(n52), .A1(Data_MX[61]), .B0(n46), .B1(Op_MX[61]), .Y(
n135) );
AO22XLTS U157 ( .A0(n52), .A1(Data_MX[62]), .B0(n46), .B1(Op_MX[62]), .Y(
n133) );
AO22XLTS U158 ( .A0(n52), .A1(Data_MX[63]), .B0(n50), .B1(Op_MX[63]), .Y(
n131) );
AO22XLTS U159 ( .A0(n52), .A1(Data_MY[52]), .B0(n48), .B1(Op_MY[52]), .Y(n25) );
AO22XLTS U160 ( .A0(n52), .A1(Data_MY[53]), .B0(n48), .B1(Op_MY[53]), .Y(n23) );
AO22XLTS U161 ( .A0(n52), .A1(Data_MY[54]), .B0(n48), .B1(Op_MY[54]), .Y(n21) );
AO22XLTS U162 ( .A0(n52), .A1(Data_MY[55]), .B0(n50), .B1(Op_MY[55]), .Y(n19) );
AO22XLTS U163 ( .A0(n52), .A1(Data_MY[56]), .B0(n54), .B1(Op_MY[56]), .Y(n17) );
AO22XLTS U164 ( .A0(n52), .A1(Data_MY[57]), .B0(n50), .B1(Op_MY[57]), .Y(n15) );
AO22XLTS U165 ( .A0(n56), .A1(Data_MY[58]), .B0(n54), .B1(Op_MY[58]), .Y(n13) );
AO22XLTS U166 ( .A0(n56), .A1(Data_MY[59]), .B0(n54), .B1(Op_MY[59]), .Y(n11) );
AO22XLTS U167 ( .A0(n56), .A1(Data_MY[60]), .B0(n54), .B1(Op_MY[60]), .Y(n9)
);
AO22XLTS U168 ( .A0(n56), .A1(Data_MY[61]), .B0(n50), .B1(Op_MY[61]), .Y(n7)
);
AO22XLTS U169 ( .A0(n56), .A1(Data_MY[62]), .B0(n50), .B1(Op_MY[62]), .Y(n5)
);
AO22XLTS U170 ( .A0(n56), .A1(Data_MY[63]), .B0(n50), .B1(Op_MY[63]), .Y(n3)
);
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module add_sub_carry_out_W12 ( op_mode, Data_A, Data_B, Data_S );
input [11:0] Data_A;
input [11:0] Data_B;
output [12:0] Data_S;
input op_mode;
wire n2, n3, n4, n5, n6, n7, n8, n9, n10, n11, n12, n13, n14, n15, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26;
CMPR32X2TS U1 ( .A(Data_A[0]), .B(n26), .C(n25), .CO(n23), .S(Data_S[0]) );
INVX2TS U2 ( .A(n26), .Y(n2) );
XOR2XLTS U3 ( .A(n26), .B(Data_B[2]), .Y(n22) );
XOR2XLTS U4 ( .A(n26), .B(Data_B[5]), .Y(n16) );
XOR2XLTS U5 ( .A(op_mode), .B(Data_B[8]), .Y(n10) );
XOR2XLTS U6 ( .A(n26), .B(Data_B[0]), .Y(n25) );
XOR2XLTS U7 ( .A(n26), .B(Data_B[3]), .Y(n20) );
XOR2XLTS U8 ( .A(n26), .B(Data_B[6]), .Y(n14) );
XOR2XLTS U9 ( .A(op_mode), .B(Data_B[9]), .Y(n8) );
XOR2XLTS U10 ( .A(n26), .B(Data_B[1]), .Y(n24) );
XOR2XLTS U11 ( .A(n26), .B(Data_B[4]), .Y(n18) );
XOR2XLTS U12 ( .A(n26), .B(Data_B[7]), .Y(n12) );
XOR2XLTS U13 ( .A(op_mode), .B(Data_B[10]), .Y(n6) );
CLKBUFX2TS U14 ( .A(op_mode), .Y(n26) );
XNOR2X1TS U15 ( .A(n3), .B(n2), .Y(Data_S[12]) );
CMPR32X2TS U16 ( .A(op_mode), .B(Data_A[11]), .C(n4), .CO(n3), .S(Data_S[11]) );
CMPR32X2TS U17 ( .A(n6), .B(Data_A[10]), .C(n5), .CO(n4), .S(Data_S[10]) );
CMPR32X2TS U18 ( .A(n8), .B(Data_A[9]), .C(n7), .CO(n5), .S(Data_S[9]) );
CMPR32X2TS U19 ( .A(n10), .B(Data_A[8]), .C(n9), .CO(n7), .S(Data_S[8]) );
CMPR32X2TS U20 ( .A(n12), .B(Data_A[7]), .C(n11), .CO(n9), .S(Data_S[7]) );
CMPR32X2TS U21 ( .A(n14), .B(Data_A[6]), .C(n13), .CO(n11), .S(Data_S[6]) );
CMPR32X2TS U22 ( .A(n16), .B(Data_A[5]), .C(n15), .CO(n13), .S(Data_S[5]) );
CMPR32X2TS U23 ( .A(n18), .B(Data_A[4]), .C(n17), .CO(n15), .S(Data_S[4]) );
CMPR32X2TS U24 ( .A(n20), .B(Data_A[3]), .C(n19), .CO(n17), .S(Data_S[3]) );
CMPR32X2TS U25 ( .A(n22), .B(Data_A[2]), .C(n21), .CO(n19), .S(Data_S[2]) );
CMPR32X2TS U26 ( .A(n24), .B(Data_A[1]), .C(n23), .CO(n21), .S(Data_S[1]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module RegisterMult_W12 ( clk, rst, load, D, Q );
input [11:0] D;
output [11:0] Q;
input clk, rst, load;
wire n2, n3, n5, n7, n9, n11, n13, n15, n17, n19, n21, n23, n25, n1, n4,
n6, n8;
DFFRXLTS Q_reg_10_ ( .D(n23), .CK(clk), .RN(n6), .Q(Q[10]) );
DFFRXLTS Q_reg_9_ ( .D(n21), .CK(clk), .RN(n6), .Q(Q[9]) );
DFFRXLTS Q_reg_8_ ( .D(n19), .CK(clk), .RN(n6), .Q(Q[8]) );
DFFRXLTS Q_reg_7_ ( .D(n17), .CK(clk), .RN(n6), .Q(Q[7]) );
DFFRXLTS Q_reg_6_ ( .D(n15), .CK(clk), .RN(n6), .Q(Q[6]) );
DFFRXLTS Q_reg_5_ ( .D(n13), .CK(clk), .RN(n6), .Q(Q[5]) );
DFFRXLTS Q_reg_4_ ( .D(n11), .CK(clk), .RN(n2), .Q(Q[4]) );
DFFRXLTS Q_reg_3_ ( .D(n9), .CK(clk), .RN(n2), .Q(Q[3]) );
DFFRXLTS Q_reg_2_ ( .D(n7), .CK(clk), .RN(n2), .Q(Q[2]) );
DFFRXLTS Q_reg_1_ ( .D(n5), .CK(clk), .RN(n2), .Q(Q[1]) );
DFFRXLTS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]) );
DFFRXLTS Q_reg_11_ ( .D(n25), .CK(clk), .RN(n2), .Q(Q[11]) );
AO22XLTS U2 ( .A0(load), .A1(D[7]), .B0(n8), .B1(Q[7]), .Y(n17) );
AO22XLTS U3 ( .A0(load), .A1(D[10]), .B0(n8), .B1(Q[10]), .Y(n23) );
AO22XLTS U4 ( .A0(load), .A1(D[11]), .B0(n4), .B1(Q[11]), .Y(n25) );
AO22XLTS U5 ( .A0(load), .A1(D[5]), .B0(n8), .B1(Q[5]), .Y(n13) );
AO22XLTS U6 ( .A0(load), .A1(D[6]), .B0(n4), .B1(Q[6]), .Y(n15) );
AO22XLTS U7 ( .A0(load), .A1(D[8]), .B0(n8), .B1(Q[8]), .Y(n19) );
AO22XLTS U8 ( .A0(load), .A1(D[9]), .B0(n8), .B1(Q[9]), .Y(n21) );
INVX2TS U9 ( .A(n8), .Y(n1) );
INVX2TS U10 ( .A(n1), .Y(n4) );
INVX2TS U11 ( .A(rst), .Y(n6) );
INVX2TS U12 ( .A(load), .Y(n8) );
AO22XLTS U13 ( .A0(load), .A1(D[4]), .B0(n4), .B1(Q[4]), .Y(n11) );
AO22XLTS U14 ( .A0(n1), .A1(D[3]), .B0(n4), .B1(Q[3]), .Y(n9) );
AO22XLTS U15 ( .A0(n1), .A1(D[2]), .B0(n4), .B1(Q[2]), .Y(n7) );
AO22XLTS U16 ( .A0(load), .A1(D[1]), .B0(n4), .B1(Q[1]), .Y(n5) );
INVX2TS U17 ( .A(rst), .Y(n2) );
AO22XLTS U18 ( .A0(n1), .A1(D[0]), .B0(n4), .B1(Q[0]), .Y(n3) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module RegisterMult_W1_1 ( clk, rst, load, D, Q );
input [0:0] D;
output [0:0] Q;
input clk, rst, load;
wire n2, n3, n1;
DFFRXLTS Q_reg_0_ ( .D(n3), .CK(clk), .RN(n2), .Q(Q[0]) );
INVX2TS U2 ( .A(load), .Y(n1) );
INVX2TS U3 ( .A(rst), .Y(n2) );
AO22XLTS U4 ( .A0(n1), .A1(Q[0]), .B0(load), .B1(D[0]), .Y(n3) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module Exp_Operation_m_EW11 ( clk, rst, load_a_i, load_b_i, load_c_i, Data_A_i,
Data_B_i, Add_Subt_i, Data_Result_o, Overflow_flag_o, Underflow_flag_o
);
input [11:0] Data_A_i;
input [11:0] Data_B_i;
output [11:0] Data_Result_o;
input clk, rst, load_a_i, load_b_i, load_c_i, Add_Subt_i;
output Overflow_flag_o, Underflow_flag_o;
wire Overflow_A, Overflow_flag_A, underflow_exp_reg, n4, n5, n2;
wire [11:0] Data_S;
add_sub_carry_out_W12 exp_add_subt_m ( .op_mode(Add_Subt_i), .Data_A(
Data_A_i), .Data_B({1'b0, Data_B_i[10:0]}), .Data_S({Overflow_A,
Data_S}) );
RegisterMult_W12 exp_result_m ( .clk(clk), .rst(rst), .load(load_c_i), .D(
Data_S), .Q(Data_Result_o) );
Comparator_Less Exp_unflow_Comparator_m ( .Data_A(Data_S), .Data_B({1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b1,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .less(underflow_exp_reg)
);
RegisterMult_W1_1 Underflow_m ( .clk(clk), .rst(rst), .load(load_a_i), .D(
underflow_exp_reg), .Q(Underflow_flag_o) );
DFFRXLTS Oflow_A_m_Q_reg_0_ ( .D(n5), .CK(clk), .RN(n4), .Q(Overflow_flag_A),
.QN(n2) );
OR2X1TS U3 ( .A(Data_Result_o[11]), .B(Overflow_flag_A), .Y(Overflow_flag_o)
);
INVX2TS U5 ( .A(rst), .Y(n4) );
OAI2BB2XLTS U6 ( .B0(load_b_i), .B1(n2), .A0N(load_b_i), .A1N(Overflow_A),
.Y(n5) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module XOR_M ( Sgn_X, Sgn_Y, Sgn_Info );
input Sgn_X, Sgn_Y;
output Sgn_Info;
XOR2XLTS U1 ( .A(Sgn_X), .B(Sgn_Y), .Y(Sgn_Info) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module substractor_W56_1 ( Data_A_i, Data_B_i, Data_S_o );
input [55:0] Data_A_i;
input [55:0] Data_B_i;
output [55:0] Data_S_o;
wire intadd_10_B_50_, intadd_10_B_49_, intadd_10_B_48_, intadd_10_B_47_,
intadd_10_B_46_, intadd_10_B_45_, intadd_10_B_44_, intadd_10_B_43_,
intadd_10_B_42_, intadd_10_B_41_, intadd_10_B_40_, intadd_10_B_39_,
intadd_10_B_38_, intadd_10_B_37_, intadd_10_B_36_, intadd_10_B_35_,
intadd_10_B_34_, intadd_10_B_33_, intadd_10_B_32_, intadd_10_B_31_,
intadd_10_B_30_, intadd_10_B_29_, intadd_10_B_28_, intadd_10_B_27_,
intadd_10_B_26_, intadd_10_B_25_, intadd_10_B_24_, intadd_10_B_23_,
intadd_10_B_22_, intadd_10_B_21_, intadd_10_B_20_, intadd_10_B_19_,
intadd_10_B_18_, intadd_10_B_17_, intadd_10_B_16_, intadd_10_B_15_,
intadd_10_B_14_, intadd_10_B_13_, intadd_10_B_12_, intadd_10_B_11_,
intadd_10_B_10_, intadd_10_B_9_, intadd_10_B_8_, intadd_10_B_7_,
intadd_10_B_6_, intadd_10_B_5_, intadd_10_B_4_, intadd_10_B_3_,
intadd_10_B_2_, intadd_10_B_1_, intadd_10_B_0_, intadd_10_CI,
intadd_10_SUM_50_, intadd_10_SUM_49_, intadd_10_SUM_48_,
intadd_10_SUM_47_, intadd_10_SUM_46_, intadd_10_SUM_45_,
intadd_10_SUM_44_, intadd_10_SUM_43_, intadd_10_SUM_42_,
intadd_10_SUM_41_, intadd_10_SUM_40_, intadd_10_SUM_39_,
intadd_10_SUM_38_, intadd_10_SUM_37_, intadd_10_SUM_36_,
intadd_10_SUM_35_, intadd_10_SUM_34_, intadd_10_SUM_33_,
intadd_10_SUM_32_, intadd_10_SUM_31_, intadd_10_SUM_30_,
intadd_10_SUM_29_, intadd_10_SUM_28_, intadd_10_SUM_27_,
intadd_10_SUM_26_, intadd_10_SUM_25_, intadd_10_SUM_24_,
intadd_10_SUM_23_, intadd_10_SUM_22_, intadd_10_SUM_21_,
intadd_10_SUM_20_, intadd_10_SUM_19_, intadd_10_SUM_18_,
intadd_10_SUM_17_, intadd_10_SUM_16_, intadd_10_SUM_15_,
intadd_10_SUM_14_, intadd_10_SUM_13_, intadd_10_SUM_12_,
intadd_10_SUM_11_, intadd_10_SUM_10_, intadd_10_SUM_9_,
intadd_10_SUM_8_, intadd_10_SUM_7_, intadd_10_SUM_6_,
intadd_10_SUM_5_, intadd_10_SUM_4_, intadd_10_SUM_3_,
intadd_10_SUM_2_, intadd_10_SUM_1_, intadd_10_SUM_0_, intadd_10_n51,
intadd_10_n50, intadd_10_n49, intadd_10_n48, intadd_10_n47,
intadd_10_n46, intadd_10_n45, intadd_10_n44, intadd_10_n43,
intadd_10_n42, intadd_10_n41, intadd_10_n40, intadd_10_n39,
intadd_10_n38, intadd_10_n37, intadd_10_n36, intadd_10_n35,
intadd_10_n34, intadd_10_n33, intadd_10_n32, intadd_10_n31,
intadd_10_n30, intadd_10_n29, intadd_10_n28, intadd_10_n27,
intadd_10_n26, intadd_10_n25, intadd_10_n24, intadd_10_n23,
intadd_10_n22, intadd_10_n21, intadd_10_n20, intadd_10_n19,
intadd_10_n18, intadd_10_n17, intadd_10_n16, intadd_10_n15,
intadd_10_n14, intadd_10_n13, intadd_10_n12, intadd_10_n11,
intadd_10_n10, intadd_10_n9, intadd_10_n8, intadd_10_n7, intadd_10_n6,
intadd_10_n5, intadd_10_n4, intadd_10_n3, intadd_10_n2, intadd_10_n1,
n5, n6, n7, n8, n9;
CMPR32X2TS intadd_10_U52 ( .A(Data_B_i[1]), .B(intadd_10_B_0_), .C(
intadd_10_CI), .CO(intadd_10_n51), .S(intadd_10_SUM_0_) );
CMPR32X2TS intadd_10_U51 ( .A(Data_B_i[2]), .B(intadd_10_B_1_), .C(
intadd_10_n51), .CO(intadd_10_n50), .S(intadd_10_SUM_1_) );
CMPR32X2TS intadd_10_U50 ( .A(Data_B_i[3]), .B(intadd_10_B_2_), .C(
intadd_10_n50), .CO(intadd_10_n49), .S(intadd_10_SUM_2_) );
CMPR32X2TS intadd_10_U49 ( .A(Data_B_i[4]), .B(intadd_10_B_3_), .C(
intadd_10_n49), .CO(intadd_10_n48), .S(intadd_10_SUM_3_) );
CMPR32X2TS intadd_10_U48 ( .A(Data_B_i[5]), .B(intadd_10_B_4_), .C(
intadd_10_n48), .CO(intadd_10_n47), .S(intadd_10_SUM_4_) );
CMPR32X2TS intadd_10_U47 ( .A(Data_B_i[6]), .B(intadd_10_B_5_), .C(
intadd_10_n47), .CO(intadd_10_n46), .S(intadd_10_SUM_5_) );
CMPR32X2TS intadd_10_U46 ( .A(Data_B_i[7]), .B(intadd_10_B_6_), .C(
intadd_10_n46), .CO(intadd_10_n45), .S(intadd_10_SUM_6_) );
CMPR32X2TS intadd_10_U45 ( .A(Data_B_i[8]), .B(intadd_10_B_7_), .C(
intadd_10_n45), .CO(intadd_10_n44), .S(intadd_10_SUM_7_) );
CMPR32X2TS intadd_10_U44 ( .A(Data_B_i[9]), .B(intadd_10_B_8_), .C(
intadd_10_n44), .CO(intadd_10_n43), .S(intadd_10_SUM_8_) );
CMPR32X2TS intadd_10_U43 ( .A(Data_B_i[10]), .B(intadd_10_B_9_), .C(
intadd_10_n43), .CO(intadd_10_n42), .S(intadd_10_SUM_9_) );
CMPR32X2TS intadd_10_U42 ( .A(Data_B_i[11]), .B(intadd_10_B_10_), .C(
intadd_10_n42), .CO(intadd_10_n41), .S(intadd_10_SUM_10_) );
CMPR32X2TS intadd_10_U41 ( .A(Data_B_i[12]), .B(intadd_10_B_11_), .C(
intadd_10_n41), .CO(intadd_10_n40), .S(intadd_10_SUM_11_) );
CMPR32X2TS intadd_10_U40 ( .A(Data_B_i[13]), .B(intadd_10_B_12_), .C(
intadd_10_n40), .CO(intadd_10_n39), .S(intadd_10_SUM_12_) );
CMPR32X2TS intadd_10_U39 ( .A(Data_B_i[14]), .B(intadd_10_B_13_), .C(
intadd_10_n39), .CO(intadd_10_n38), .S(intadd_10_SUM_13_) );
CMPR32X2TS intadd_10_U38 ( .A(Data_B_i[15]), .B(intadd_10_B_14_), .C(
intadd_10_n38), .CO(intadd_10_n37), .S(intadd_10_SUM_14_) );
CMPR32X2TS intadd_10_U37 ( .A(Data_B_i[16]), .B(intadd_10_B_15_), .C(
intadd_10_n37), .CO(intadd_10_n36), .S(intadd_10_SUM_15_) );
CMPR32X2TS intadd_10_U36 ( .A(Data_B_i[17]), .B(intadd_10_B_16_), .C(
intadd_10_n36), .CO(intadd_10_n35), .S(intadd_10_SUM_16_) );
CMPR32X2TS intadd_10_U35 ( .A(Data_B_i[18]), .B(intadd_10_B_17_), .C(
intadd_10_n35), .CO(intadd_10_n34), .S(intadd_10_SUM_17_) );
CMPR32X2TS intadd_10_U34 ( .A(Data_B_i[19]), .B(intadd_10_B_18_), .C(
intadd_10_n34), .CO(intadd_10_n33), .S(intadd_10_SUM_18_) );
CMPR32X2TS intadd_10_U33 ( .A(Data_B_i[20]), .B(intadd_10_B_19_), .C(
intadd_10_n33), .CO(intadd_10_n32), .S(intadd_10_SUM_19_) );
CMPR32X2TS intadd_10_U32 ( .A(Data_B_i[21]), .B(intadd_10_B_20_), .C(
intadd_10_n32), .CO(intadd_10_n31), .S(intadd_10_SUM_20_) );
CMPR32X2TS intadd_10_U31 ( .A(Data_B_i[22]), .B(intadd_10_B_21_), .C(
intadd_10_n31), .CO(intadd_10_n30), .S(intadd_10_SUM_21_) );
CMPR32X2TS intadd_10_U30 ( .A(Data_B_i[23]), .B(intadd_10_B_22_), .C(
intadd_10_n30), .CO(intadd_10_n29), .S(intadd_10_SUM_22_) );
CMPR32X2TS intadd_10_U29 ( .A(Data_B_i[24]), .B(intadd_10_B_23_), .C(
intadd_10_n29), .CO(intadd_10_n28), .S(intadd_10_SUM_23_) );
CMPR32X2TS intadd_10_U28 ( .A(Data_B_i[25]), .B(intadd_10_B_24_), .C(
intadd_10_n28), .CO(intadd_10_n27), .S(intadd_10_SUM_24_) );
CMPR32X2TS intadd_10_U27 ( .A(Data_B_i[26]), .B(intadd_10_B_25_), .C(
intadd_10_n27), .CO(intadd_10_n26), .S(intadd_10_SUM_25_) );
CMPR32X2TS intadd_10_U26 ( .A(Data_B_i[27]), .B(intadd_10_B_26_), .C(
intadd_10_n26), .CO(intadd_10_n25), .S(intadd_10_SUM_26_) );
CMPR32X2TS intadd_10_U25 ( .A(Data_B_i[28]), .B(intadd_10_B_27_), .C(
intadd_10_n25), .CO(intadd_10_n24), .S(intadd_10_SUM_27_) );
CMPR32X2TS intadd_10_U24 ( .A(Data_B_i[29]), .B(intadd_10_B_28_), .C(
intadd_10_n24), .CO(intadd_10_n23), .S(intadd_10_SUM_28_) );
CMPR32X2TS intadd_10_U23 ( .A(Data_B_i[30]), .B(intadd_10_B_29_), .C(
intadd_10_n23), .CO(intadd_10_n22), .S(intadd_10_SUM_29_) );
CMPR32X2TS intadd_10_U22 ( .A(Data_B_i[31]), .B(intadd_10_B_30_), .C(
intadd_10_n22), .CO(intadd_10_n21), .S(intadd_10_SUM_30_) );
CMPR32X2TS intadd_10_U21 ( .A(Data_B_i[32]), .B(intadd_10_B_31_), .C(
intadd_10_n21), .CO(intadd_10_n20), .S(intadd_10_SUM_31_) );
CMPR32X2TS intadd_10_U20 ( .A(Data_B_i[33]), .B(intadd_10_B_32_), .C(
intadd_10_n20), .CO(intadd_10_n19), .S(intadd_10_SUM_32_) );
CMPR32X2TS intadd_10_U19 ( .A(Data_B_i[34]), .B(intadd_10_B_33_), .C(
intadd_10_n19), .CO(intadd_10_n18), .S(intadd_10_SUM_33_) );
CMPR32X2TS intadd_10_U18 ( .A(Data_B_i[35]), .B(intadd_10_B_34_), .C(
intadd_10_n18), .CO(intadd_10_n17), .S(intadd_10_SUM_34_) );
CMPR32X2TS intadd_10_U17 ( .A(Data_B_i[36]), .B(intadd_10_B_35_), .C(
intadd_10_n17), .CO(intadd_10_n16), .S(intadd_10_SUM_35_) );
CMPR32X2TS intadd_10_U16 ( .A(Data_B_i[37]), .B(intadd_10_B_36_), .C(
intadd_10_n16), .CO(intadd_10_n15), .S(intadd_10_SUM_36_) );
CMPR32X2TS intadd_10_U15 ( .A(Data_B_i[38]), .B(intadd_10_B_37_), .C(
intadd_10_n15), .CO(intadd_10_n14), .S(intadd_10_SUM_37_) );
CMPR32X2TS intadd_10_U14 ( .A(Data_B_i[39]), .B(intadd_10_B_38_), .C(
intadd_10_n14), .CO(intadd_10_n13), .S(intadd_10_SUM_38_) );
CMPR32X2TS intadd_10_U13 ( .A(Data_B_i[40]), .B(intadd_10_B_39_), .C(
intadd_10_n13), .CO(intadd_10_n12), .S(intadd_10_SUM_39_) );
CMPR32X2TS intadd_10_U12 ( .A(Data_B_i[41]), .B(intadd_10_B_40_), .C(
intadd_10_n12), .CO(intadd_10_n11), .S(intadd_10_SUM_40_) );
CMPR32X2TS intadd_10_U11 ( .A(Data_B_i[42]), .B(intadd_10_B_41_), .C(
intadd_10_n11), .CO(intadd_10_n10), .S(intadd_10_SUM_41_) );
CMPR32X2TS intadd_10_U10 ( .A(Data_B_i[43]), .B(intadd_10_B_42_), .C(
intadd_10_n10), .CO(intadd_10_n9), .S(intadd_10_SUM_42_) );
CMPR32X2TS intadd_10_U9 ( .A(Data_B_i[44]), .B(intadd_10_B_43_), .C(
intadd_10_n9), .CO(intadd_10_n8), .S(intadd_10_SUM_43_) );
CMPR32X2TS intadd_10_U8 ( .A(Data_B_i[45]), .B(intadd_10_B_44_), .C(
intadd_10_n8), .CO(intadd_10_n7), .S(intadd_10_SUM_44_) );
CMPR32X2TS intadd_10_U7 ( .A(Data_B_i[46]), .B(intadd_10_B_45_), .C(
intadd_10_n7), .CO(intadd_10_n6), .S(intadd_10_SUM_45_) );
CMPR32X2TS intadd_10_U6 ( .A(Data_B_i[47]), .B(intadd_10_B_46_), .C(
intadd_10_n6), .CO(intadd_10_n5), .S(intadd_10_SUM_46_) );
CMPR32X2TS intadd_10_U5 ( .A(Data_B_i[48]), .B(intadd_10_B_47_), .C(
intadd_10_n5), .CO(intadd_10_n4), .S(intadd_10_SUM_47_) );
CMPR32X2TS intadd_10_U4 ( .A(Data_B_i[49]), .B(intadd_10_B_48_), .C(
intadd_10_n4), .CO(intadd_10_n3), .S(intadd_10_SUM_48_) );
CMPR32X2TS intadd_10_U3 ( .A(Data_B_i[50]), .B(intadd_10_B_49_), .C(
intadd_10_n3), .CO(intadd_10_n2), .S(intadd_10_SUM_49_) );
CMPR32X2TS intadd_10_U2 ( .A(Data_B_i[51]), .B(intadd_10_B_50_), .C(
intadd_10_n2), .CO(intadd_10_n1), .S(intadd_10_SUM_50_) );
INVX2TS U1 ( .A(Data_A_i[7]), .Y(intadd_10_B_6_) );
INVX2TS U2 ( .A(Data_A_i[22]), .Y(intadd_10_B_21_) );
INVX2TS U3 ( .A(Data_A_i[37]), .Y(intadd_10_B_36_) );
INVX2TS U4 ( .A(intadd_10_SUM_9_), .Y(Data_S_o[10]) );
INVX2TS U5 ( .A(intadd_10_SUM_24_), .Y(Data_S_o[25]) );
INVX2TS U6 ( .A(intadd_10_SUM_39_), .Y(Data_S_o[40]) );
INVX2TS U7 ( .A(intadd_10_SUM_38_), .Y(Data_S_o[39]) );
INVX2TS U8 ( .A(intadd_10_SUM_50_), .Y(Data_S_o[51]) );
INVX2TS U9 ( .A(intadd_10_SUM_49_), .Y(Data_S_o[50]) );
INVX2TS U10 ( .A(Data_A_i[1]), .Y(intadd_10_B_0_) );
INVX2TS U11 ( .A(Data_A_i[2]), .Y(intadd_10_B_1_) );
INVX2TS U12 ( .A(Data_A_i[3]), .Y(intadd_10_B_2_) );
INVX2TS U13 ( .A(Data_A_i[4]), .Y(intadd_10_B_3_) );
INVX2TS U14 ( .A(Data_A_i[5]), .Y(intadd_10_B_4_) );
INVX2TS U15 ( .A(Data_A_i[6]), .Y(intadd_10_B_5_) );
INVX2TS U16 ( .A(Data_A_i[8]), .Y(intadd_10_B_7_) );
INVX2TS U17 ( .A(Data_A_i[9]), .Y(intadd_10_B_8_) );
INVX2TS U18 ( .A(Data_A_i[10]), .Y(intadd_10_B_9_) );
INVX2TS U19 ( .A(Data_A_i[11]), .Y(intadd_10_B_10_) );
INVX2TS U20 ( .A(Data_A_i[12]), .Y(intadd_10_B_11_) );
INVX2TS U21 ( .A(Data_A_i[13]), .Y(intadd_10_B_12_) );
INVX2TS U22 ( .A(intadd_10_SUM_48_), .Y(Data_S_o[49]) );
INVX2TS U23 ( .A(Data_A_i[14]), .Y(intadd_10_B_13_) );
INVX2TS U24 ( .A(intadd_10_SUM_47_), .Y(Data_S_o[48]) );
INVX2TS U25 ( .A(intadd_10_SUM_46_), .Y(Data_S_o[47]) );
INVX2TS U26 ( .A(Data_A_i[15]), .Y(intadd_10_B_14_) );
INVX2TS U27 ( .A(Data_A_i[16]), .Y(intadd_10_B_15_) );
INVX2TS U28 ( .A(Data_A_i[17]), .Y(intadd_10_B_16_) );
INVX2TS U29 ( .A(Data_A_i[18]), .Y(intadd_10_B_17_) );
INVX2TS U30 ( .A(Data_A_i[19]), .Y(intadd_10_B_18_) );
INVX2TS U31 ( .A(Data_A_i[20]), .Y(intadd_10_B_19_) );
INVX2TS U32 ( .A(Data_A_i[21]), .Y(intadd_10_B_20_) );
INVX2TS U33 ( .A(intadd_10_SUM_45_), .Y(Data_S_o[46]) );
INVX2TS U34 ( .A(Data_A_i[23]), .Y(intadd_10_B_22_) );
INVX2TS U35 ( .A(Data_A_i[24]), .Y(intadd_10_B_23_) );
INVX2TS U36 ( .A(intadd_10_SUM_44_), .Y(Data_S_o[45]) );
INVX2TS U37 ( .A(Data_A_i[25]), .Y(intadd_10_B_24_) );
INVX2TS U38 ( .A(Data_A_i[26]), .Y(intadd_10_B_25_) );
INVX2TS U39 ( .A(intadd_10_SUM_43_), .Y(Data_S_o[44]) );
INVX2TS U40 ( .A(intadd_10_SUM_42_), .Y(Data_S_o[43]) );
INVX2TS U41 ( .A(intadd_10_SUM_41_), .Y(Data_S_o[42]) );
INVX2TS U42 ( .A(intadd_10_SUM_40_), .Y(Data_S_o[41]) );
INVX2TS U43 ( .A(Data_A_i[27]), .Y(intadd_10_B_26_) );
INVX2TS U44 ( .A(Data_A_i[28]), .Y(intadd_10_B_27_) );
INVX2TS U45 ( .A(intadd_10_SUM_37_), .Y(Data_S_o[38]) );
INVX2TS U46 ( .A(intadd_10_SUM_36_), .Y(Data_S_o[37]) );
INVX2TS U47 ( .A(intadd_10_SUM_35_), .Y(Data_S_o[36]) );
INVX2TS U48 ( .A(Data_A_i[29]), .Y(intadd_10_B_28_) );
INVX2TS U49 ( .A(Data_A_i[30]), .Y(intadd_10_B_29_) );
INVX2TS U50 ( .A(intadd_10_SUM_34_), .Y(Data_S_o[35]) );
INVX2TS U51 ( .A(intadd_10_SUM_33_), .Y(Data_S_o[34]) );
INVX2TS U52 ( .A(intadd_10_SUM_32_), .Y(Data_S_o[33]) );
INVX2TS U53 ( .A(intadd_10_SUM_31_), .Y(Data_S_o[32]) );
INVX2TS U54 ( .A(Data_A_i[31]), .Y(intadd_10_B_30_) );
INVX2TS U55 ( .A(Data_A_i[32]), .Y(intadd_10_B_31_) );
INVX2TS U56 ( .A(Data_A_i[52]), .Y(n7) );
NAND2X1TS U57 ( .A(n7), .B(intadd_10_n1), .Y(n6) );
NOR2XLTS U58 ( .A(Data_A_i[53]), .B(n6), .Y(n9) );
AO21XLTS U59 ( .A0(Data_A_i[53]), .A1(n6), .B0(n9), .Y(Data_S_o[53]) );
INVX2TS U60 ( .A(intadd_10_SUM_30_), .Y(Data_S_o[31]) );
INVX2TS U61 ( .A(intadd_10_SUM_29_), .Y(Data_S_o[30]) );
INVX2TS U62 ( .A(intadd_10_SUM_28_), .Y(Data_S_o[29]) );
INVX2TS U63 ( .A(intadd_10_SUM_27_), .Y(Data_S_o[28]) );
INVX2TS U64 ( .A(Data_A_i[33]), .Y(intadd_10_B_32_) );
INVX2TS U65 ( .A(Data_A_i[34]), .Y(intadd_10_B_33_) );
INVX2TS U66 ( .A(intadd_10_SUM_26_), .Y(Data_S_o[27]) );
INVX2TS U67 ( .A(intadd_10_SUM_25_), .Y(Data_S_o[26]) );
INVX2TS U68 ( .A(intadd_10_SUM_23_), .Y(Data_S_o[24]) );
INVX2TS U69 ( .A(Data_A_i[35]), .Y(intadd_10_B_34_) );
INVX2TS U70 ( .A(Data_A_i[36]), .Y(intadd_10_B_35_) );
INVX2TS U71 ( .A(intadd_10_SUM_22_), .Y(Data_S_o[23]) );
INVX2TS U72 ( .A(intadd_10_SUM_21_), .Y(Data_S_o[22]) );
INVX2TS U73 ( .A(intadd_10_SUM_20_), .Y(Data_S_o[21]) );
INVX2TS U74 ( .A(intadd_10_SUM_19_), .Y(Data_S_o[20]) );
INVX2TS U75 ( .A(Data_A_i[38]), .Y(intadd_10_B_37_) );
INVX2TS U76 ( .A(intadd_10_SUM_18_), .Y(Data_S_o[19]) );
INVX2TS U77 ( .A(intadd_10_SUM_17_), .Y(Data_S_o[18]) );
INVX2TS U78 ( .A(intadd_10_SUM_16_), .Y(Data_S_o[17]) );
INVX2TS U79 ( .A(intadd_10_SUM_15_), .Y(Data_S_o[16]) );
INVX2TS U80 ( .A(Data_A_i[39]), .Y(intadd_10_B_38_) );
INVX2TS U81 ( .A(Data_A_i[40]), .Y(intadd_10_B_39_) );
INVX2TS U82 ( .A(intadd_10_SUM_14_), .Y(Data_S_o[15]) );
INVX2TS U83 ( .A(intadd_10_SUM_13_), .Y(Data_S_o[14]) );
INVX2TS U84 ( .A(intadd_10_SUM_12_), .Y(Data_S_o[13]) );
INVX2TS U85 ( .A(intadd_10_SUM_11_), .Y(Data_S_o[12]) );
INVX2TS U86 ( .A(Data_A_i[41]), .Y(intadd_10_B_40_) );
INVX2TS U87 ( .A(Data_A_i[42]), .Y(intadd_10_B_41_) );
INVX2TS U88 ( .A(intadd_10_SUM_10_), .Y(Data_S_o[11]) );
INVX2TS U89 ( .A(intadd_10_SUM_8_), .Y(Data_S_o[9]) );
INVX2TS U90 ( .A(intadd_10_SUM_7_), .Y(Data_S_o[8]) );
INVX2TS U91 ( .A(Data_A_i[43]), .Y(intadd_10_B_42_) );
INVX2TS U92 ( .A(Data_A_i[44]), .Y(intadd_10_B_43_) );
INVX2TS U93 ( .A(intadd_10_SUM_6_), .Y(Data_S_o[7]) );
INVX2TS U94 ( .A(intadd_10_SUM_5_), .Y(Data_S_o[6]) );
INVX2TS U95 ( .A(intadd_10_SUM_4_), .Y(Data_S_o[5]) );
INVX2TS U96 ( .A(intadd_10_SUM_3_), .Y(Data_S_o[4]) );
INVX2TS U97 ( .A(Data_A_i[45]), .Y(intadd_10_B_44_) );
INVX2TS U98 ( .A(Data_A_i[46]), .Y(intadd_10_B_45_) );
INVX2TS U99 ( .A(intadd_10_SUM_2_), .Y(Data_S_o[3]) );
INVX2TS U100 ( .A(intadd_10_SUM_1_), .Y(Data_S_o[2]) );
INVX2TS U101 ( .A(intadd_10_SUM_0_), .Y(Data_S_o[1]) );
INVX2TS U102 ( .A(Data_A_i[47]), .Y(intadd_10_B_46_) );
INVX2TS U103 ( .A(Data_A_i[48]), .Y(intadd_10_B_47_) );
INVX2TS U104 ( .A(Data_A_i[49]), .Y(intadd_10_B_48_) );
INVX2TS U105 ( .A(Data_A_i[50]), .Y(intadd_10_B_49_) );
INVX2TS U106 ( .A(Data_A_i[51]), .Y(intadd_10_B_50_) );
INVX2TS U107 ( .A(Data_B_i[0]), .Y(n5) );
NOR2XLTS U108 ( .A(n5), .B(Data_A_i[0]), .Y(intadd_10_CI) );
AO21XLTS U109 ( .A0(Data_A_i[0]), .A1(n5), .B0(intadd_10_CI), .Y(Data_S_o[0]) );
OAI21XLTS U110 ( .A0(intadd_10_n1), .A1(n7), .B0(n6), .Y(Data_S_o[52]) );
NOR2BX1TS U111 ( .AN(n9), .B(Data_A_i[54]), .Y(n8) );
XOR2XLTS U112 ( .A(n8), .B(Data_A_i[55]), .Y(Data_S_o[55]) );
XOR2XLTS U113 ( .A(Data_A_i[54]), .B(n9), .Y(Data_S_o[54]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module substractor_W56_0 ( Data_A_i, Data_B_i, Data_S_o );
input [55:0] Data_A_i;
input [55:0] Data_B_i;
output [55:0] Data_S_o;
wire intadd_11_B_52_, intadd_11_B_51_, intadd_11_B_50_, intadd_11_B_49_,
intadd_11_B_48_, intadd_11_B_47_, intadd_11_B_46_, intadd_11_B_45_,
intadd_11_B_44_, intadd_11_B_43_, intadd_11_B_42_, intadd_11_B_41_,
intadd_11_B_40_, intadd_11_B_39_, intadd_11_B_38_, intadd_11_B_37_,
intadd_11_B_36_, intadd_11_B_35_, intadd_11_B_34_, intadd_11_B_33_,
intadd_11_B_32_, intadd_11_B_31_, intadd_11_B_30_, intadd_11_B_29_,
intadd_11_B_28_, intadd_11_B_27_, intadd_11_B_26_, intadd_11_B_25_,
intadd_11_B_24_, intadd_11_B_23_, intadd_11_B_22_, intadd_11_B_21_,
intadd_11_B_20_, intadd_11_B_19_, intadd_11_B_18_, intadd_11_B_17_,
intadd_11_B_16_, intadd_11_B_15_, intadd_11_B_14_, intadd_11_B_13_,
intadd_11_B_12_, intadd_11_B_11_, intadd_11_B_10_, intadd_11_B_9_,
intadd_11_B_8_, intadd_11_B_7_, intadd_11_B_6_, intadd_11_B_5_,
intadd_11_B_4_, intadd_11_B_3_, intadd_11_B_2_, intadd_11_B_1_,
intadd_11_B_0_, intadd_11_CI, intadd_11_SUM_52_, intadd_11_SUM_51_,
intadd_11_SUM_50_, intadd_11_SUM_49_, intadd_11_SUM_48_,
intadd_11_SUM_47_, intadd_11_SUM_46_, intadd_11_SUM_45_,
intadd_11_SUM_44_, intadd_11_SUM_43_, intadd_11_SUM_42_,
intadd_11_SUM_41_, intadd_11_SUM_40_, intadd_11_SUM_39_,
intadd_11_SUM_38_, intadd_11_SUM_37_, intadd_11_SUM_36_,
intadd_11_SUM_35_, intadd_11_SUM_34_, intadd_11_SUM_33_,
intadd_11_SUM_32_, intadd_11_SUM_31_, intadd_11_SUM_30_,
intadd_11_SUM_29_, intadd_11_SUM_28_, intadd_11_SUM_27_,
intadd_11_SUM_26_, intadd_11_SUM_25_, intadd_11_SUM_24_,
intadd_11_SUM_23_, intadd_11_SUM_22_, intadd_11_SUM_21_,
intadd_11_SUM_20_, intadd_11_SUM_19_, intadd_11_SUM_18_,
intadd_11_SUM_17_, intadd_11_SUM_16_, intadd_11_SUM_15_,
intadd_11_SUM_14_, intadd_11_SUM_13_, intadd_11_SUM_12_,
intadd_11_SUM_11_, intadd_11_SUM_10_, intadd_11_SUM_9_,
intadd_11_SUM_8_, intadd_11_SUM_7_, intadd_11_SUM_6_,
intadd_11_SUM_5_, intadd_11_SUM_4_, intadd_11_SUM_3_,
intadd_11_SUM_2_, intadd_11_SUM_1_, intadd_11_SUM_0_, intadd_11_n53,
intadd_11_n52, intadd_11_n51, intadd_11_n50, intadd_11_n49,
intadd_11_n48, intadd_11_n47, intadd_11_n46, intadd_11_n45,
intadd_11_n44, intadd_11_n43, intadd_11_n42, intadd_11_n41,
intadd_11_n40, intadd_11_n39, intadd_11_n38, intadd_11_n37,
intadd_11_n36, intadd_11_n35, intadd_11_n34, intadd_11_n33,
intadd_11_n32, intadd_11_n31, intadd_11_n30, intadd_11_n29,
intadd_11_n28, intadd_11_n27, intadd_11_n26, intadd_11_n25,
intadd_11_n24, intadd_11_n23, intadd_11_n22, intadd_11_n21,
intadd_11_n20, intadd_11_n19, intadd_11_n18, intadd_11_n17,
intadd_11_n16, intadd_11_n15, intadd_11_n14, intadd_11_n13,
intadd_11_n12, intadd_11_n11, intadd_11_n10, intadd_11_n9,
intadd_11_n8, intadd_11_n7, intadd_11_n6, intadd_11_n5, intadd_11_n4,
intadd_11_n3, intadd_11_n2, intadd_11_n1, n3, n4;
CMPR32X2TS intadd_11_U54 ( .A(Data_B_i[1]), .B(intadd_11_B_0_), .C(
intadd_11_CI), .CO(intadd_11_n53), .S(intadd_11_SUM_0_) );
CMPR32X2TS intadd_11_U53 ( .A(Data_B_i[2]), .B(intadd_11_B_1_), .C(
intadd_11_n53), .CO(intadd_11_n52), .S(intadd_11_SUM_1_) );
CMPR32X2TS intadd_11_U52 ( .A(Data_B_i[3]), .B(intadd_11_B_2_), .C(
intadd_11_n52), .CO(intadd_11_n51), .S(intadd_11_SUM_2_) );
CMPR32X2TS intadd_11_U51 ( .A(Data_B_i[4]), .B(intadd_11_B_3_), .C(
intadd_11_n51), .CO(intadd_11_n50), .S(intadd_11_SUM_3_) );
CMPR32X2TS intadd_11_U50 ( .A(Data_B_i[5]), .B(intadd_11_B_4_), .C(
intadd_11_n50), .CO(intadd_11_n49), .S(intadd_11_SUM_4_) );
CMPR32X2TS intadd_11_U49 ( .A(Data_B_i[6]), .B(intadd_11_B_5_), .C(
intadd_11_n49), .CO(intadd_11_n48), .S(intadd_11_SUM_5_) );
CMPR32X2TS intadd_11_U48 ( .A(Data_B_i[7]), .B(intadd_11_B_6_), .C(
intadd_11_n48), .CO(intadd_11_n47), .S(intadd_11_SUM_6_) );
CMPR32X2TS intadd_11_U47 ( .A(Data_B_i[8]), .B(intadd_11_B_7_), .C(
intadd_11_n47), .CO(intadd_11_n46), .S(intadd_11_SUM_7_) );
CMPR32X2TS intadd_11_U46 ( .A(Data_B_i[9]), .B(intadd_11_B_8_), .C(
intadd_11_n46), .CO(intadd_11_n45), .S(intadd_11_SUM_8_) );
CMPR32X2TS intadd_11_U45 ( .A(Data_B_i[10]), .B(intadd_11_B_9_), .C(
intadd_11_n45), .CO(intadd_11_n44), .S(intadd_11_SUM_9_) );
CMPR32X2TS intadd_11_U44 ( .A(Data_B_i[11]), .B(intadd_11_B_10_), .C(
intadd_11_n44), .CO(intadd_11_n43), .S(intadd_11_SUM_10_) );
CMPR32X2TS intadd_11_U43 ( .A(Data_B_i[12]), .B(intadd_11_B_11_), .C(
intadd_11_n43), .CO(intadd_11_n42), .S(intadd_11_SUM_11_) );
CMPR32X2TS intadd_11_U42 ( .A(Data_B_i[13]), .B(intadd_11_B_12_), .C(
intadd_11_n42), .CO(intadd_11_n41), .S(intadd_11_SUM_12_) );
CMPR32X2TS intadd_11_U41 ( .A(Data_B_i[14]), .B(intadd_11_B_13_), .C(
intadd_11_n41), .CO(intadd_11_n40), .S(intadd_11_SUM_13_) );
CMPR32X2TS intadd_11_U40 ( .A(Data_B_i[15]), .B(intadd_11_B_14_), .C(
intadd_11_n40), .CO(intadd_11_n39), .S(intadd_11_SUM_14_) );
CMPR32X2TS intadd_11_U39 ( .A(Data_B_i[16]), .B(intadd_11_B_15_), .C(
intadd_11_n39), .CO(intadd_11_n38), .S(intadd_11_SUM_15_) );
CMPR32X2TS intadd_11_U38 ( .A(Data_B_i[17]), .B(intadd_11_B_16_), .C(
intadd_11_n38), .CO(intadd_11_n37), .S(intadd_11_SUM_16_) );
CMPR32X2TS intadd_11_U37 ( .A(Data_B_i[18]), .B(intadd_11_B_17_), .C(
intadd_11_n37), .CO(intadd_11_n36), .S(intadd_11_SUM_17_) );
CMPR32X2TS intadd_11_U36 ( .A(Data_B_i[19]), .B(intadd_11_B_18_), .C(
intadd_11_n36), .CO(intadd_11_n35), .S(intadd_11_SUM_18_) );
CMPR32X2TS intadd_11_U35 ( .A(Data_B_i[20]), .B(intadd_11_B_19_), .C(
intadd_11_n35), .CO(intadd_11_n34), .S(intadd_11_SUM_19_) );
CMPR32X2TS intadd_11_U34 ( .A(Data_B_i[21]), .B(intadd_11_B_20_), .C(
intadd_11_n34), .CO(intadd_11_n33), .S(intadd_11_SUM_20_) );
CMPR32X2TS intadd_11_U33 ( .A(Data_B_i[22]), .B(intadd_11_B_21_), .C(
intadd_11_n33), .CO(intadd_11_n32), .S(intadd_11_SUM_21_) );
CMPR32X2TS intadd_11_U32 ( .A(Data_B_i[23]), .B(intadd_11_B_22_), .C(
intadd_11_n32), .CO(intadd_11_n31), .S(intadd_11_SUM_22_) );
CMPR32X2TS intadd_11_U31 ( .A(Data_B_i[24]), .B(intadd_11_B_23_), .C(
intadd_11_n31), .CO(intadd_11_n30), .S(intadd_11_SUM_23_) );
CMPR32X2TS intadd_11_U30 ( .A(Data_B_i[25]), .B(intadd_11_B_24_), .C(
intadd_11_n30), .CO(intadd_11_n29), .S(intadd_11_SUM_24_) );
CMPR32X2TS intadd_11_U29 ( .A(Data_B_i[26]), .B(intadd_11_B_25_), .C(
intadd_11_n29), .CO(intadd_11_n28), .S(intadd_11_SUM_25_) );
CMPR32X2TS intadd_11_U28 ( .A(Data_B_i[27]), .B(intadd_11_B_26_), .C(
intadd_11_n28), .CO(intadd_11_n27), .S(intadd_11_SUM_26_) );
CMPR32X2TS intadd_11_U27 ( .A(Data_B_i[28]), .B(intadd_11_B_27_), .C(
intadd_11_n27), .CO(intadd_11_n26), .S(intadd_11_SUM_27_) );
CMPR32X2TS intadd_11_U26 ( .A(Data_B_i[29]), .B(intadd_11_B_28_), .C(
intadd_11_n26), .CO(intadd_11_n25), .S(intadd_11_SUM_28_) );
CMPR32X2TS intadd_11_U25 ( .A(Data_B_i[30]), .B(intadd_11_B_29_), .C(
intadd_11_n25), .CO(intadd_11_n24), .S(intadd_11_SUM_29_) );
CMPR32X2TS intadd_11_U24 ( .A(Data_B_i[31]), .B(intadd_11_B_30_), .C(
intadd_11_n24), .CO(intadd_11_n23), .S(intadd_11_SUM_30_) );
CMPR32X2TS intadd_11_U23 ( .A(Data_B_i[32]), .B(intadd_11_B_31_), .C(
intadd_11_n23), .CO(intadd_11_n22), .S(intadd_11_SUM_31_) );
CMPR32X2TS intadd_11_U22 ( .A(Data_B_i[33]), .B(intadd_11_B_32_), .C(
intadd_11_n22), .CO(intadd_11_n21), .S(intadd_11_SUM_32_) );
CMPR32X2TS intadd_11_U21 ( .A(Data_B_i[34]), .B(intadd_11_B_33_), .C(
intadd_11_n21), .CO(intadd_11_n20), .S(intadd_11_SUM_33_) );
CMPR32X2TS intadd_11_U20 ( .A(Data_B_i[35]), .B(intadd_11_B_34_), .C(
intadd_11_n20), .CO(intadd_11_n19), .S(intadd_11_SUM_34_) );
CMPR32X2TS intadd_11_U19 ( .A(Data_B_i[36]), .B(intadd_11_B_35_), .C(
intadd_11_n19), .CO(intadd_11_n18), .S(intadd_11_SUM_35_) );
CMPR32X2TS intadd_11_U18 ( .A(Data_B_i[37]), .B(intadd_11_B_36_), .C(
intadd_11_n18), .CO(intadd_11_n17), .S(intadd_11_SUM_36_) );
CMPR32X2TS intadd_11_U17 ( .A(Data_B_i[38]), .B(intadd_11_B_37_), .C(
intadd_11_n17), .CO(intadd_11_n16), .S(intadd_11_SUM_37_) );
CMPR32X2TS intadd_11_U16 ( .A(Data_B_i[39]), .B(intadd_11_B_38_), .C(
intadd_11_n16), .CO(intadd_11_n15), .S(intadd_11_SUM_38_) );
CMPR32X2TS intadd_11_U15 ( .A(Data_B_i[40]), .B(intadd_11_B_39_), .C(
intadd_11_n15), .CO(intadd_11_n14), .S(intadd_11_SUM_39_) );
CMPR32X2TS intadd_11_U14 ( .A(Data_B_i[41]), .B(intadd_11_B_40_), .C(
intadd_11_n14), .CO(intadd_11_n13), .S(intadd_11_SUM_40_) );
CMPR32X2TS intadd_11_U13 ( .A(Data_B_i[42]), .B(intadd_11_B_41_), .C(
intadd_11_n13), .CO(intadd_11_n12), .S(intadd_11_SUM_41_) );
CMPR32X2TS intadd_11_U12 ( .A(Data_B_i[43]), .B(intadd_11_B_42_), .C(
intadd_11_n12), .CO(intadd_11_n11), .S(intadd_11_SUM_42_) );
CMPR32X2TS intadd_11_U11 ( .A(Data_B_i[44]), .B(intadd_11_B_43_), .C(
intadd_11_n11), .CO(intadd_11_n10), .S(intadd_11_SUM_43_) );
CMPR32X2TS intadd_11_U10 ( .A(Data_B_i[45]), .B(intadd_11_B_44_), .C(
intadd_11_n10), .CO(intadd_11_n9), .S(intadd_11_SUM_44_) );
CMPR32X2TS intadd_11_U9 ( .A(Data_B_i[46]), .B(intadd_11_B_45_), .C(
intadd_11_n9), .CO(intadd_11_n8), .S(intadd_11_SUM_45_) );
CMPR32X2TS intadd_11_U8 ( .A(Data_B_i[47]), .B(intadd_11_B_46_), .C(
intadd_11_n8), .CO(intadd_11_n7), .S(intadd_11_SUM_46_) );
CMPR32X2TS intadd_11_U7 ( .A(Data_B_i[48]), .B(intadd_11_B_47_), .C(
intadd_11_n7), .CO(intadd_11_n6), .S(intadd_11_SUM_47_) );
CMPR32X2TS intadd_11_U6 ( .A(Data_B_i[49]), .B(intadd_11_B_48_), .C(
intadd_11_n6), .CO(intadd_11_n5), .S(intadd_11_SUM_48_) );
CMPR32X2TS intadd_11_U5 ( .A(Data_B_i[50]), .B(intadd_11_B_49_), .C(
intadd_11_n5), .CO(intadd_11_n4), .S(intadd_11_SUM_49_) );
CMPR32X2TS intadd_11_U4 ( .A(Data_B_i[51]), .B(intadd_11_B_50_), .C(
intadd_11_n4), .CO(intadd_11_n3), .S(intadd_11_SUM_50_) );
CMPR32X2TS intadd_11_U3 ( .A(Data_B_i[52]), .B(intadd_11_B_51_), .C(
intadd_11_n3), .CO(intadd_11_n2), .S(intadd_11_SUM_51_) );
CMPR32X2TS intadd_11_U2 ( .A(Data_B_i[53]), .B(intadd_11_B_52_), .C(
intadd_11_n2), .CO(intadd_11_n1), .S(intadd_11_SUM_52_) );
NOR2XLTS U1 ( .A(n3), .B(Data_A_i[0]), .Y(intadd_11_CI) );
INVX2TS U2 ( .A(intadd_11_SUM_1_), .Y(Data_S_o[2]) );
INVX2TS U3 ( .A(intadd_11_SUM_16_), .Y(Data_S_o[17]) );
INVX2TS U4 ( .A(intadd_11_SUM_31_), .Y(Data_S_o[32]) );
INVX2TS U5 ( .A(intadd_11_SUM_46_), .Y(Data_S_o[47]) );
INVX2TS U6 ( .A(Data_B_i[0]), .Y(n3) );
INVX2TS U7 ( .A(Data_A_i[39]), .Y(intadd_11_B_38_) );
INVX2TS U8 ( .A(Data_A_i[52]), .Y(intadd_11_B_51_) );
INVX2TS U9 ( .A(Data_A_i[51]), .Y(intadd_11_B_50_) );
INVX2TS U10 ( .A(Data_A_i[50]), .Y(intadd_11_B_49_) );
INVX2TS U11 ( .A(Data_A_i[49]), .Y(intadd_11_B_48_) );
INVX2TS U12 ( .A(Data_A_i[48]), .Y(intadd_11_B_47_) );
INVX2TS U13 ( .A(Data_A_i[47]), .Y(intadd_11_B_46_) );
INVX2TS U14 ( .A(Data_A_i[46]), .Y(intadd_11_B_45_) );
INVX2TS U15 ( .A(Data_A_i[45]), .Y(intadd_11_B_44_) );
INVX2TS U16 ( .A(Data_A_i[44]), .Y(intadd_11_B_43_) );
INVX2TS U17 ( .A(Data_A_i[43]), .Y(intadd_11_B_42_) );
INVX2TS U18 ( .A(Data_A_i[42]), .Y(intadd_11_B_41_) );
INVX2TS U19 ( .A(Data_A_i[41]), .Y(intadd_11_B_40_) );
INVX2TS U20 ( .A(Data_A_i[40]), .Y(intadd_11_B_39_) );
INVX2TS U21 ( .A(Data_A_i[38]), .Y(intadd_11_B_37_) );
INVX2TS U22 ( .A(Data_A_i[37]), .Y(intadd_11_B_36_) );
INVX2TS U23 ( .A(Data_A_i[36]), .Y(intadd_11_B_35_) );
INVX2TS U24 ( .A(Data_A_i[35]), .Y(intadd_11_B_34_) );
INVX2TS U25 ( .A(Data_A_i[34]), .Y(intadd_11_B_33_) );
INVX2TS U26 ( .A(Data_A_i[33]), .Y(intadd_11_B_32_) );
INVX2TS U27 ( .A(Data_A_i[32]), .Y(intadd_11_B_31_) );
INVX2TS U28 ( .A(Data_A_i[53]), .Y(intadd_11_B_52_) );
INVX2TS U29 ( .A(Data_A_i[31]), .Y(intadd_11_B_30_) );
INVX2TS U30 ( .A(Data_A_i[30]), .Y(intadd_11_B_29_) );
INVX2TS U31 ( .A(Data_A_i[29]), .Y(intadd_11_B_28_) );
INVX2TS U32 ( .A(Data_A_i[28]), .Y(intadd_11_B_27_) );
INVX2TS U33 ( .A(Data_A_i[27]), .Y(intadd_11_B_26_) );
INVX2TS U34 ( .A(Data_A_i[26]), .Y(intadd_11_B_25_) );
INVX2TS U35 ( .A(Data_A_i[25]), .Y(intadd_11_B_24_) );
INVX2TS U36 ( .A(Data_A_i[24]), .Y(intadd_11_B_23_) );
INVX2TS U37 ( .A(Data_A_i[23]), .Y(intadd_11_B_22_) );
INVX2TS U38 ( .A(Data_A_i[22]), .Y(intadd_11_B_21_) );
INVX2TS U39 ( .A(Data_A_i[21]), .Y(intadd_11_B_20_) );
INVX2TS U40 ( .A(Data_A_i[20]), .Y(intadd_11_B_19_) );
INVX2TS U41 ( .A(Data_A_i[19]), .Y(intadd_11_B_18_) );
INVX2TS U42 ( .A(Data_A_i[18]), .Y(intadd_11_B_17_) );
INVX2TS U43 ( .A(Data_A_i[17]), .Y(intadd_11_B_16_) );
INVX2TS U44 ( .A(Data_A_i[16]), .Y(intadd_11_B_15_) );
INVX2TS U45 ( .A(Data_A_i[15]), .Y(intadd_11_B_14_) );
INVX2TS U46 ( .A(Data_A_i[14]), .Y(intadd_11_B_13_) );
INVX2TS U47 ( .A(Data_A_i[13]), .Y(intadd_11_B_12_) );
INVX2TS U48 ( .A(Data_A_i[12]), .Y(intadd_11_B_11_) );
INVX2TS U49 ( .A(Data_A_i[11]), .Y(intadd_11_B_10_) );
INVX2TS U50 ( .A(Data_A_i[10]), .Y(intadd_11_B_9_) );
INVX2TS U51 ( .A(Data_A_i[9]), .Y(intadd_11_B_8_) );
INVX2TS U52 ( .A(Data_A_i[8]), .Y(intadd_11_B_7_) );
INVX2TS U53 ( .A(Data_A_i[7]), .Y(intadd_11_B_6_) );
INVX2TS U54 ( .A(Data_A_i[6]), .Y(intadd_11_B_5_) );
INVX2TS U55 ( .A(Data_A_i[5]), .Y(intadd_11_B_4_) );
INVX2TS U56 ( .A(Data_A_i[4]), .Y(intadd_11_B_3_) );
INVX2TS U57 ( .A(Data_A_i[3]), .Y(intadd_11_B_2_) );
INVX2TS U58 ( .A(Data_A_i[2]), .Y(intadd_11_B_1_) );
INVX2TS U59 ( .A(Data_A_i[1]), .Y(intadd_11_B_0_) );
INVX2TS U60 ( .A(intadd_11_SUM_52_), .Y(Data_S_o[53]) );
INVX2TS U61 ( .A(intadd_11_SUM_51_), .Y(Data_S_o[52]) );
INVX2TS U62 ( .A(intadd_11_SUM_50_), .Y(Data_S_o[51]) );
INVX2TS U63 ( .A(intadd_11_SUM_49_), .Y(Data_S_o[50]) );
INVX2TS U64 ( .A(intadd_11_SUM_48_), .Y(Data_S_o[49]) );
INVX2TS U65 ( .A(intadd_11_SUM_47_), .Y(Data_S_o[48]) );
INVX2TS U66 ( .A(intadd_11_SUM_45_), .Y(Data_S_o[46]) );
INVX2TS U67 ( .A(intadd_11_SUM_44_), .Y(Data_S_o[45]) );
INVX2TS U68 ( .A(intadd_11_SUM_43_), .Y(Data_S_o[44]) );
INVX2TS U69 ( .A(intadd_11_SUM_42_), .Y(Data_S_o[43]) );
INVX2TS U70 ( .A(intadd_11_SUM_41_), .Y(Data_S_o[42]) );
INVX2TS U71 ( .A(intadd_11_SUM_40_), .Y(Data_S_o[41]) );
INVX2TS U72 ( .A(intadd_11_SUM_39_), .Y(Data_S_o[40]) );
INVX2TS U73 ( .A(intadd_11_SUM_38_), .Y(Data_S_o[39]) );
INVX2TS U74 ( .A(intadd_11_SUM_37_), .Y(Data_S_o[38]) );
INVX2TS U75 ( .A(intadd_11_SUM_36_), .Y(Data_S_o[37]) );
INVX2TS U76 ( .A(intadd_11_SUM_35_), .Y(Data_S_o[36]) );
INVX2TS U77 ( .A(intadd_11_SUM_34_), .Y(Data_S_o[35]) );
INVX2TS U78 ( .A(intadd_11_SUM_33_), .Y(Data_S_o[34]) );
INVX2TS U79 ( .A(intadd_11_SUM_32_), .Y(Data_S_o[33]) );
INVX2TS U80 ( .A(intadd_11_SUM_30_), .Y(Data_S_o[31]) );
INVX2TS U81 ( .A(intadd_11_SUM_29_), .Y(Data_S_o[30]) );
INVX2TS U82 ( .A(intadd_11_SUM_28_), .Y(Data_S_o[29]) );
INVX2TS U83 ( .A(intadd_11_SUM_27_), .Y(Data_S_o[28]) );
INVX2TS U84 ( .A(intadd_11_SUM_26_), .Y(Data_S_o[27]) );
INVX2TS U85 ( .A(intadd_11_SUM_25_), .Y(Data_S_o[26]) );
INVX2TS U86 ( .A(intadd_11_SUM_24_), .Y(Data_S_o[25]) );
INVX2TS U87 ( .A(intadd_11_SUM_23_), .Y(Data_S_o[24]) );
INVX2TS U88 ( .A(intadd_11_SUM_22_), .Y(Data_S_o[23]) );
INVX2TS U89 ( .A(intadd_11_SUM_21_), .Y(Data_S_o[22]) );
INVX2TS U90 ( .A(intadd_11_SUM_20_), .Y(Data_S_o[21]) );
INVX2TS U91 ( .A(intadd_11_SUM_19_), .Y(Data_S_o[20]) );
INVX2TS U92 ( .A(intadd_11_SUM_18_), .Y(Data_S_o[19]) );
INVX2TS U93 ( .A(intadd_11_SUM_17_), .Y(Data_S_o[18]) );
INVX2TS U94 ( .A(intadd_11_SUM_15_), .Y(Data_S_o[16]) );
INVX2TS U95 ( .A(intadd_11_SUM_14_), .Y(Data_S_o[15]) );
INVX2TS U96 ( .A(intadd_11_SUM_13_), .Y(Data_S_o[14]) );
INVX2TS U97 ( .A(intadd_11_SUM_12_), .Y(Data_S_o[13]) );
INVX2TS U98 ( .A(intadd_11_SUM_11_), .Y(Data_S_o[12]) );
INVX2TS U99 ( .A(intadd_11_SUM_10_), .Y(Data_S_o[11]) );
INVX2TS U100 ( .A(intadd_11_SUM_9_), .Y(Data_S_o[10]) );
INVX2TS U101 ( .A(intadd_11_SUM_8_), .Y(Data_S_o[9]) );
INVX2TS U102 ( .A(intadd_11_SUM_7_), .Y(Data_S_o[8]) );
INVX2TS U103 ( .A(intadd_11_SUM_6_), .Y(Data_S_o[7]) );
INVX2TS U104 ( .A(intadd_11_SUM_5_), .Y(Data_S_o[6]) );
INVX2TS U105 ( .A(intadd_11_SUM_4_), .Y(Data_S_o[5]) );
INVX2TS U106 ( .A(intadd_11_SUM_3_), .Y(Data_S_o[4]) );
INVX2TS U107 ( .A(intadd_11_SUM_2_), .Y(Data_S_o[3]) );
INVX2TS U108 ( .A(intadd_11_SUM_0_), .Y(Data_S_o[1]) );
AO21XLTS U109 ( .A0(Data_A_i[0]), .A1(n3), .B0(intadd_11_CI), .Y(Data_S_o[0]) );
XOR2XLTS U110 ( .A(Data_A_i[54]), .B(intadd_11_n1), .Y(Data_S_o[54]) );
NAND2BXLTS U111 ( .AN(Data_A_i[54]), .B(intadd_11_n1), .Y(n4) );
XNOR2X1TS U112 ( .A(Data_A_i[55]), .B(n4), .Y(Data_S_o[55]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module Sgf_Multiplication_SW53 ( clk, rst, load_b_i, Data_A_i, Data_B_i,
sgf_result_o );
input [52:0] Data_A_i;
input [52:0] Data_B_i;
output [105:0] sgf_result_o;
input clk, rst, load_b_i;
wire result_A_adder_2_, genblk1_middle_N55, genblk1_middle_N54,
genblk1_middle_N53, genblk1_middle_N52, genblk1_middle_N51,
genblk1_middle_N50, genblk1_middle_N49, genblk1_middle_N48,
genblk1_middle_N47, genblk1_middle_N46, genblk1_middle_N45,
genblk1_middle_N44, genblk1_middle_N43, genblk1_middle_N42,
genblk1_middle_N41, genblk1_middle_N40, genblk1_middle_N39,
genblk1_middle_N38, genblk1_middle_N37, genblk1_middle_N36,
genblk1_middle_N35, genblk1_middle_N34, genblk1_middle_N33,
genblk1_middle_N32, genblk1_middle_N31, genblk1_middle_N30,
genblk1_middle_N29, genblk1_middle_N28, genblk1_middle_N27,
genblk1_middle_N26, genblk1_middle_N25, genblk1_middle_N24,
genblk1_middle_N23, genblk1_middle_N22, genblk1_middle_N21,
genblk1_middle_N20, genblk1_middle_N19, genblk1_middle_N18,
genblk1_middle_N17, genblk1_middle_N16, genblk1_middle_N15,
genblk1_middle_N14, genblk1_middle_N13, genblk1_middle_N12,
genblk1_middle_N11, genblk1_middle_N10, genblk1_middle_N9,
genblk1_middle_N8, genblk1_middle_N7, genblk1_middle_N6,
genblk1_middle_N5, genblk1_middle_N4, genblk1_middle_N3,
genblk1_middle_N2, genblk1_middle_N1, genblk1_middle_N0,
genblk1_right_N53, genblk1_right_N52, genblk1_right_N51,
genblk1_right_N50, genblk1_right_N49, genblk1_right_N48,
genblk1_right_N47, genblk1_right_N46, genblk1_right_N45,
genblk1_right_N44, genblk1_right_N43, genblk1_right_N42,
genblk1_right_N41, genblk1_right_N40, genblk1_right_N39,
genblk1_right_N38, genblk1_right_N37, genblk1_right_N36,
genblk1_right_N35, genblk1_right_N34, genblk1_right_N33,
genblk1_right_N32, genblk1_right_N31, genblk1_right_N30,
genblk1_right_N29, genblk1_right_N28, genblk1_right_N27,
genblk1_right_N26, genblk1_right_N25, genblk1_right_N24,
genblk1_right_N23, genblk1_right_N22, genblk1_right_N21,
genblk1_right_N20, genblk1_right_N19, genblk1_right_N18,
genblk1_right_N17, genblk1_right_N16, genblk1_right_N15,
genblk1_right_N14, genblk1_right_N13, genblk1_right_N12,
genblk1_right_N11, genblk1_right_N10, genblk1_right_N9,
genblk1_right_N8, genblk1_right_N7, genblk1_right_N6,
genblk1_right_N5, genblk1_right_N4, genblk1_right_N3,
genblk1_right_N2, genblk1_right_N1, genblk1_right_N0,
genblk1_left_N51, genblk1_left_N50, genblk1_left_N49,
genblk1_left_N48, genblk1_left_N47, genblk1_left_N46,
genblk1_left_N45, genblk1_left_N44, genblk1_left_N43,
genblk1_left_N42, genblk1_left_N41, genblk1_left_N40,
genblk1_left_N39, genblk1_left_N38, genblk1_left_N37,
genblk1_left_N36, genblk1_left_N35, genblk1_left_N34,
genblk1_left_N33, genblk1_left_N32, genblk1_left_N31,
genblk1_left_N30, genblk1_left_N29, genblk1_left_N28,
genblk1_left_N27, genblk1_left_N26, genblk1_left_N25,
genblk1_left_N24, genblk1_left_N23, genblk1_left_N22,
genblk1_left_N21, genblk1_left_N20, genblk1_left_N19,
genblk1_left_N18, genblk1_left_N17, genblk1_left_N16,
genblk1_left_N15, genblk1_left_N14, genblk1_left_N13,
genblk1_left_N12, genblk1_left_N11, genblk1_left_N10, genblk1_left_N9,
genblk1_left_N8, genblk1_left_N7, genblk1_left_N6, genblk1_left_N5,
genblk1_left_N4, genblk1_left_N3, genblk1_left_N2, genblk1_left_N1,
genblk1_left_mult_x_1_n1787, genblk1_left_mult_x_1_n1331,
genblk1_left_mult_x_1_n1330, genblk1_left_mult_x_1_n1329,
genblk1_left_mult_x_1_n1328, genblk1_left_mult_x_1_n1327,
genblk1_left_mult_x_1_n1326, genblk1_left_mult_x_1_n1325,
genblk1_left_mult_x_1_n1324, genblk1_left_mult_x_1_n1323,
genblk1_left_mult_x_1_n1322, genblk1_left_mult_x_1_n1321,
genblk1_left_mult_x_1_n1320, genblk1_left_mult_x_1_n1319,
genblk1_left_mult_x_1_n1318, genblk1_left_mult_x_1_n1317,
genblk1_left_mult_x_1_n1316, genblk1_left_mult_x_1_n1315,
genblk1_left_mult_x_1_n1314, genblk1_left_mult_x_1_n1313,
genblk1_left_mult_x_1_n1305, genblk1_left_mult_x_1_n1304,
genblk1_left_mult_x_1_n1303, genblk1_left_mult_x_1_n1302,
genblk1_left_mult_x_1_n1300, genblk1_left_mult_x_1_n1299,
genblk1_left_mult_x_1_n1298, genblk1_left_mult_x_1_n1297,
genblk1_left_mult_x_1_n1296, genblk1_left_mult_x_1_n1295,
genblk1_left_mult_x_1_n1294, genblk1_left_mult_x_1_n1293,
genblk1_left_mult_x_1_n1292, genblk1_left_mult_x_1_n1291,
genblk1_left_mult_x_1_n1290, genblk1_left_mult_x_1_n1289,
genblk1_left_mult_x_1_n1288, genblk1_left_mult_x_1_n1287,
genblk1_left_mult_x_1_n1286, genblk1_left_mult_x_1_n1285,
genblk1_left_mult_x_1_n1284, genblk1_left_mult_x_1_n1279,
genblk1_left_mult_x_1_n1278, genblk1_left_mult_x_1_n1277,
genblk1_left_mult_x_1_n1276, genblk1_left_mult_x_1_n1275,
genblk1_left_mult_x_1_n1273, genblk1_left_mult_x_1_n1272,
genblk1_left_mult_x_1_n1271, genblk1_left_mult_x_1_n1270,
genblk1_left_mult_x_1_n1269, genblk1_left_mult_x_1_n1268,
genblk1_left_mult_x_1_n1267, genblk1_left_mult_x_1_n1266,
genblk1_left_mult_x_1_n1265, genblk1_left_mult_x_1_n1264,
genblk1_left_mult_x_1_n1263, genblk1_left_mult_x_1_n1262,
genblk1_left_mult_x_1_n1261, genblk1_left_mult_x_1_n1260,
genblk1_left_mult_x_1_n1259, genblk1_left_mult_x_1_n1258,
genblk1_left_mult_x_1_n1257, genblk1_left_mult_x_1_n1256,
genblk1_left_mult_x_1_n1255, genblk1_left_mult_x_1_n1247,
genblk1_left_mult_x_1_n1246, genblk1_left_mult_x_1_n1245,
genblk1_left_mult_x_1_n1244, genblk1_left_mult_x_1_n1242,
genblk1_left_mult_x_1_n1241, genblk1_left_mult_x_1_n1240,
genblk1_left_mult_x_1_n1239, genblk1_left_mult_x_1_n1238,
genblk1_left_mult_x_1_n1237, genblk1_left_mult_x_1_n1236,
genblk1_left_mult_x_1_n1235, genblk1_left_mult_x_1_n1234,
genblk1_left_mult_x_1_n1233, genblk1_left_mult_x_1_n1232,
genblk1_left_mult_x_1_n1231, genblk1_left_mult_x_1_n1230,
genblk1_left_mult_x_1_n1229, genblk1_left_mult_x_1_n1228,
genblk1_left_mult_x_1_n1221, genblk1_left_mult_x_1_n1220,
genblk1_left_mult_x_1_n1219, genblk1_left_mult_x_1_n1218,
genblk1_left_mult_x_1_n1217, genblk1_left_mult_x_1_n1215,
genblk1_left_mult_x_1_n1214, genblk1_left_mult_x_1_n1213,
genblk1_left_mult_x_1_n1212, genblk1_left_mult_x_1_n1211,
genblk1_left_mult_x_1_n1210, genblk1_left_mult_x_1_n1209,
genblk1_left_mult_x_1_n1208, genblk1_left_mult_x_1_n1207,
genblk1_left_mult_x_1_n1206, genblk1_left_mult_x_1_n1205,
genblk1_left_mult_x_1_n1204, genblk1_left_mult_x_1_n1203,
genblk1_left_mult_x_1_n1202, genblk1_left_mult_x_1_n1201,
genblk1_left_mult_x_1_n1200, genblk1_left_mult_x_1_n1199,
genblk1_left_mult_x_1_n1198, genblk1_left_mult_x_1_n1197,
genblk1_left_mult_x_1_n1189, genblk1_left_mult_x_1_n1188,
genblk1_left_mult_x_1_n1187, genblk1_left_mult_x_1_n1186,
genblk1_left_mult_x_1_n1184, genblk1_left_mult_x_1_n1183,
genblk1_left_mult_x_1_n1182, genblk1_left_mult_x_1_n1181,
genblk1_left_mult_x_1_n1180, genblk1_left_mult_x_1_n1179,
genblk1_left_mult_x_1_n1178, genblk1_left_mult_x_1_n1177,
genblk1_left_mult_x_1_n1176, genblk1_left_mult_x_1_n1175,
genblk1_left_mult_x_1_n1174, genblk1_left_mult_x_1_n1173,
genblk1_left_mult_x_1_n1172, genblk1_left_mult_x_1_n1171,
genblk1_left_mult_x_1_n1170, genblk1_left_mult_x_1_n1163,
genblk1_left_mult_x_1_n1162, genblk1_left_mult_x_1_n1161,
genblk1_left_mult_x_1_n1160, genblk1_left_mult_x_1_n1159,
genblk1_left_mult_x_1_n1155, genblk1_left_mult_x_1_n1154,
genblk1_left_mult_x_1_n1153, genblk1_left_mult_x_1_n1152,
genblk1_left_mult_x_1_n1151, genblk1_left_mult_x_1_n1150,
genblk1_left_mult_x_1_n1149, genblk1_left_mult_x_1_n1148,
genblk1_left_mult_x_1_n1147, genblk1_left_mult_x_1_n1146,
genblk1_left_mult_x_1_n1145, genblk1_left_mult_x_1_n1144,
genblk1_left_mult_x_1_n1143, genblk1_left_mult_x_1_n1142,
genblk1_left_mult_x_1_n1141, genblk1_left_mult_x_1_n1140,
genblk1_left_mult_x_1_n1139, genblk1_left_mult_x_1_n1138,
genblk1_left_mult_x_1_n1130, genblk1_left_mult_x_1_n1127,
genblk1_left_mult_x_1_n1126, genblk1_left_mult_x_1_n1125,
genblk1_left_mult_x_1_n1124, genblk1_left_mult_x_1_n1123,
genblk1_left_mult_x_1_n1121, genblk1_left_mult_x_1_n1120,
genblk1_left_mult_x_1_n1119, genblk1_left_mult_x_1_n1117,
genblk1_left_mult_x_1_n1115, genblk1_left_mult_x_1_n1114,
genblk1_left_mult_x_1_n1113, genblk1_left_mult_x_1_n1102,
genblk1_left_mult_x_1_n1101, genblk1_left_mult_x_1_n1099,
genblk1_left_mult_x_1_n1098, genblk1_left_mult_x_1_n1097,
genblk1_left_mult_x_1_n1096, genblk1_left_mult_x_1_n1095,
genblk1_left_mult_x_1_n1094, genblk1_left_mult_x_1_n810,
genblk1_left_mult_x_1_n807, genblk1_left_mult_x_1_n805,
genblk1_left_mult_x_1_n804, genblk1_left_mult_x_1_n803,
genblk1_left_mult_x_1_n802, genblk1_left_mult_x_1_n800,
genblk1_left_mult_x_1_n799, genblk1_left_mult_x_1_n798,
genblk1_left_mult_x_1_n797, genblk1_left_mult_x_1_n795,
genblk1_left_mult_x_1_n794, genblk1_left_mult_x_1_n793,
genblk1_left_mult_x_1_n790, genblk1_left_mult_x_1_n789,
genblk1_left_mult_x_1_n788, genblk1_left_mult_x_1_n787,
genblk1_left_mult_x_1_n786, genblk1_left_mult_x_1_n783,
genblk1_left_mult_x_1_n782, genblk1_left_mult_x_1_n781,
genblk1_left_mult_x_1_n780, genblk1_left_mult_x_1_n779,
genblk1_left_mult_x_1_n777, genblk1_left_mult_x_1_n776,
genblk1_left_mult_x_1_n775, genblk1_left_mult_x_1_n774,
genblk1_left_mult_x_1_n773, genblk1_left_mult_x_1_n772,
genblk1_left_mult_x_1_n771, genblk1_left_mult_x_1_n769,
genblk1_left_mult_x_1_n768, genblk1_left_mult_x_1_n767,
genblk1_left_mult_x_1_n766, genblk1_left_mult_x_1_n765,
genblk1_left_mult_x_1_n764, genblk1_left_mult_x_1_n763,
genblk1_left_mult_x_1_n761, genblk1_left_mult_x_1_n760,
genblk1_left_mult_x_1_n759, genblk1_left_mult_x_1_n758,
genblk1_left_mult_x_1_n757, genblk1_left_mult_x_1_n756,
genblk1_left_mult_x_1_n755, genblk1_left_mult_x_1_n753,
genblk1_left_mult_x_1_n752, genblk1_left_mult_x_1_n751,
genblk1_left_mult_x_1_n750, genblk1_left_mult_x_1_n749,
genblk1_left_mult_x_1_n748, genblk1_left_mult_x_1_n745,
genblk1_left_mult_x_1_n744, genblk1_left_mult_x_1_n743,
genblk1_left_mult_x_1_n742, genblk1_left_mult_x_1_n741,
genblk1_left_mult_x_1_n740, genblk1_left_mult_x_1_n739,
genblk1_left_mult_x_1_n738, genblk1_left_mult_x_1_n735,
genblk1_left_mult_x_1_n734, genblk1_left_mult_x_1_n733,
genblk1_left_mult_x_1_n732, genblk1_left_mult_x_1_n731,
genblk1_left_mult_x_1_n730, genblk1_left_mult_x_1_n729,
genblk1_left_mult_x_1_n728, genblk1_left_mult_x_1_n726,
genblk1_left_mult_x_1_n725, genblk1_left_mult_x_1_n724,
genblk1_left_mult_x_1_n723, genblk1_left_mult_x_1_n722,
genblk1_left_mult_x_1_n721, genblk1_left_mult_x_1_n720,
genblk1_left_mult_x_1_n719, genblk1_left_mult_x_1_n718,
genblk1_left_mult_x_1_n717, genblk1_left_mult_x_1_n715,
genblk1_left_mult_x_1_n714, genblk1_left_mult_x_1_n713,
genblk1_left_mult_x_1_n712, genblk1_left_mult_x_1_n711,
genblk1_left_mult_x_1_n710, genblk1_left_mult_x_1_n709,
genblk1_left_mult_x_1_n708, genblk1_left_mult_x_1_n707,
genblk1_left_mult_x_1_n706, genblk1_left_mult_x_1_n704,
genblk1_left_mult_x_1_n703, genblk1_left_mult_x_1_n702,
genblk1_left_mult_x_1_n701, genblk1_left_mult_x_1_n700,
genblk1_left_mult_x_1_n699, genblk1_left_mult_x_1_n698,
genblk1_left_mult_x_1_n697, genblk1_left_mult_x_1_n696,
genblk1_left_mult_x_1_n695, genblk1_left_mult_x_1_n693,
genblk1_left_mult_x_1_n692, genblk1_left_mult_x_1_n691,
genblk1_left_mult_x_1_n690, genblk1_left_mult_x_1_n689,
genblk1_left_mult_x_1_n688, genblk1_left_mult_x_1_n687,
genblk1_left_mult_x_1_n686, genblk1_left_mult_x_1_n685,
genblk1_left_mult_x_1_n684, genblk1_left_mult_x_1_n683,
genblk1_left_mult_x_1_n682, genblk1_left_mult_x_1_n681,
genblk1_left_mult_x_1_n680, genblk1_left_mult_x_1_n679,
genblk1_left_mult_x_1_n678, genblk1_left_mult_x_1_n677,
genblk1_left_mult_x_1_n676, genblk1_left_mult_x_1_n675,
genblk1_left_mult_x_1_n674, genblk1_left_mult_x_1_n673,
genblk1_left_mult_x_1_n672, genblk1_left_mult_x_1_n671,
genblk1_left_mult_x_1_n670, genblk1_left_mult_x_1_n669,
genblk1_left_mult_x_1_n668, genblk1_left_mult_x_1_n667,
genblk1_left_mult_x_1_n666, genblk1_left_mult_x_1_n665,
genblk1_left_mult_x_1_n664, genblk1_left_mult_x_1_n663,
genblk1_left_mult_x_1_n662, genblk1_left_mult_x_1_n661,
genblk1_left_mult_x_1_n660, genblk1_left_mult_x_1_n659,
genblk1_left_mult_x_1_n658, genblk1_left_mult_x_1_n657,
genblk1_left_mult_x_1_n656, genblk1_left_mult_x_1_n655,
genblk1_left_mult_x_1_n654, genblk1_left_mult_x_1_n653,
genblk1_left_mult_x_1_n652, genblk1_left_mult_x_1_n651,
genblk1_left_mult_x_1_n650, genblk1_left_mult_x_1_n649,
genblk1_left_mult_x_1_n648, genblk1_left_mult_x_1_n647,
genblk1_left_mult_x_1_n646, genblk1_left_mult_x_1_n645,
genblk1_left_mult_x_1_n644, genblk1_left_mult_x_1_n643,
genblk1_left_mult_x_1_n642, genblk1_left_mult_x_1_n641,
genblk1_left_mult_x_1_n640, genblk1_left_mult_x_1_n639,
genblk1_left_mult_x_1_n638, genblk1_left_mult_x_1_n637,
genblk1_left_mult_x_1_n636, genblk1_left_mult_x_1_n635,
genblk1_left_mult_x_1_n634, genblk1_left_mult_x_1_n633,
genblk1_left_mult_x_1_n632, genblk1_left_mult_x_1_n631,
genblk1_left_mult_x_1_n630, genblk1_left_mult_x_1_n629,
genblk1_left_mult_x_1_n628, genblk1_left_mult_x_1_n627,
genblk1_left_mult_x_1_n626, genblk1_left_mult_x_1_n625,
genblk1_left_mult_x_1_n624, genblk1_left_mult_x_1_n623,
genblk1_left_mult_x_1_n622, genblk1_left_mult_x_1_n621,
genblk1_left_mult_x_1_n620, genblk1_left_mult_x_1_n619,
genblk1_left_mult_x_1_n618, genblk1_left_mult_x_1_n617,
genblk1_left_mult_x_1_n616, genblk1_left_mult_x_1_n615,
genblk1_left_mult_x_1_n614, genblk1_left_mult_x_1_n613,
genblk1_left_mult_x_1_n612, genblk1_left_mult_x_1_n611,
genblk1_left_mult_x_1_n610, genblk1_left_mult_x_1_n609,
genblk1_left_mult_x_1_n608, genblk1_left_mult_x_1_n607,
genblk1_left_mult_x_1_n606, genblk1_left_mult_x_1_n605,
genblk1_left_mult_x_1_n604, genblk1_left_mult_x_1_n603,
genblk1_left_mult_x_1_n602, genblk1_left_mult_x_1_n601,
genblk1_left_mult_x_1_n600, genblk1_left_mult_x_1_n599,
genblk1_left_mult_x_1_n598, genblk1_left_mult_x_1_n597,
genblk1_left_mult_x_1_n596, genblk1_left_mult_x_1_n595,
genblk1_left_mult_x_1_n594, genblk1_left_mult_x_1_n593,
genblk1_left_mult_x_1_n592, genblk1_left_mult_x_1_n591,
genblk1_left_mult_x_1_n590, genblk1_left_mult_x_1_n589,
genblk1_left_mult_x_1_n588, genblk1_left_mult_x_1_n587,
genblk1_left_mult_x_1_n585, genblk1_left_mult_x_1_n584,
genblk1_left_mult_x_1_n583, genblk1_left_mult_x_1_n582,
genblk1_left_mult_x_1_n581, genblk1_left_mult_x_1_n580,
genblk1_left_mult_x_1_n579, genblk1_left_mult_x_1_n578,
genblk1_left_mult_x_1_n577, genblk1_left_mult_x_1_n576,
genblk1_left_mult_x_1_n575, genblk1_left_mult_x_1_n574,
genblk1_left_mult_x_1_n573, genblk1_left_mult_x_1_n572,
genblk1_left_mult_x_1_n571, genblk1_left_mult_x_1_n570,
genblk1_left_mult_x_1_n569, genblk1_left_mult_x_1_n568,
genblk1_left_mult_x_1_n567, genblk1_left_mult_x_1_n564,
genblk1_left_mult_x_1_n563, genblk1_left_mult_x_1_n562,
genblk1_left_mult_x_1_n561, genblk1_left_mult_x_1_n560,
genblk1_left_mult_x_1_n559, genblk1_left_mult_x_1_n558,
genblk1_left_mult_x_1_n557, genblk1_left_mult_x_1_n554,
genblk1_left_mult_x_1_n553, genblk1_left_mult_x_1_n552,
genblk1_left_mult_x_1_n551, genblk1_left_mult_x_1_n550,
genblk1_left_mult_x_1_n549, genblk1_left_mult_x_1_n548,
genblk1_left_mult_x_1_n547, genblk1_left_mult_x_1_n546,
genblk1_left_mult_x_1_n545, genblk1_left_mult_x_1_n544,
genblk1_left_mult_x_1_n543, genblk1_left_mult_x_1_n542,
genblk1_left_mult_x_1_n541, genblk1_left_mult_x_1_n540,
genblk1_left_mult_x_1_n539, genblk1_left_mult_x_1_n538,
genblk1_left_mult_x_1_n537, genblk1_left_mult_x_1_n536,
genblk1_left_mult_x_1_n535, genblk1_left_mult_x_1_n534,
genblk1_left_mult_x_1_n533, genblk1_left_mult_x_1_n532,
genblk1_left_mult_x_1_n530, genblk1_left_mult_x_1_n529,
genblk1_left_mult_x_1_n528, genblk1_left_mult_x_1_n527,
genblk1_left_mult_x_1_n526, genblk1_left_mult_x_1_n525,
genblk1_left_mult_x_1_n524, genblk1_left_mult_x_1_n523,
genblk1_left_mult_x_1_n522, genblk1_left_mult_x_1_n521,
genblk1_left_mult_x_1_n520, genblk1_left_mult_x_1_n519,
genblk1_left_mult_x_1_n518, genblk1_left_mult_x_1_n517,
genblk1_left_mult_x_1_n515, genblk1_left_mult_x_1_n514,
genblk1_left_mult_x_1_n513, genblk1_left_mult_x_1_n512,
genblk1_left_mult_x_1_n511, genblk1_left_mult_x_1_n508,
genblk1_left_mult_x_1_n507, genblk1_left_mult_x_1_n506,
genblk1_left_mult_x_1_n505, genblk1_left_mult_x_1_n504,
genblk1_left_mult_x_1_n503, genblk1_left_mult_x_1_n502,
genblk1_left_mult_x_1_n501, genblk1_left_mult_x_1_n500,
genblk1_left_mult_x_1_n499, genblk1_left_mult_x_1_n498,
genblk1_left_mult_x_1_n497, genblk1_left_mult_x_1_n496,
genblk1_left_mult_x_1_n495, genblk1_left_mult_x_1_n493,
genblk1_left_mult_x_1_n492, genblk1_left_mult_x_1_n491,
genblk1_left_mult_x_1_n490, genblk1_left_mult_x_1_n489,
genblk1_left_mult_x_1_n488, genblk1_left_mult_x_1_n487,
genblk1_right_mult_x_1_n1483, genblk1_right_mult_x_1_n1482,
genblk1_right_mult_x_1_n1481, genblk1_right_mult_x_1_n1480,
genblk1_right_mult_x_1_n1478, genblk1_right_mult_x_1_n1477,
genblk1_right_mult_x_1_n1476, genblk1_right_mult_x_1_n1475,
genblk1_right_mult_x_1_n1474, genblk1_right_mult_x_1_n1473,
genblk1_right_mult_x_1_n1472, genblk1_right_mult_x_1_n1471,
genblk1_right_mult_x_1_n1470, genblk1_right_mult_x_1_n1469,
genblk1_right_mult_x_1_n1468, genblk1_right_mult_x_1_n1467,
genblk1_right_mult_x_1_n1466, genblk1_right_mult_x_1_n1465,
genblk1_right_mult_x_1_n1464, genblk1_right_mult_x_1_n1456,
genblk1_right_mult_x_1_n1455, genblk1_right_mult_x_1_n1454,
genblk1_right_mult_x_1_n1453, genblk1_right_mult_x_1_n1452,
genblk1_right_mult_x_1_n1451, genblk1_right_mult_x_1_n1450,
genblk1_right_mult_x_1_n1449, genblk1_right_mult_x_1_n1448,
genblk1_right_mult_x_1_n1447, genblk1_right_mult_x_1_n1446,
genblk1_right_mult_x_1_n1445, genblk1_right_mult_x_1_n1444,
genblk1_right_mult_x_1_n1443, genblk1_right_mult_x_1_n1442,
genblk1_right_mult_x_1_n1441, genblk1_right_mult_x_1_n1440,
genblk1_right_mult_x_1_n1439, genblk1_right_mult_x_1_n1438,
genblk1_right_mult_x_1_n1437, genblk1_right_mult_x_1_n1436,
genblk1_right_mult_x_1_n1435, genblk1_right_mult_x_1_n1434,
genblk1_right_mult_x_1_n1429, genblk1_right_mult_x_1_n1428,
genblk1_right_mult_x_1_n1427, genblk1_right_mult_x_1_n1426,
genblk1_right_mult_x_1_n1425, genblk1_right_mult_x_1_n1423,
genblk1_right_mult_x_1_n1422, genblk1_right_mult_x_1_n1421,
genblk1_right_mult_x_1_n1420, genblk1_right_mult_x_1_n1418,
genblk1_right_mult_x_1_n1417, genblk1_right_mult_x_1_n1416,
genblk1_right_mult_x_1_n1415, genblk1_right_mult_x_1_n1414,
genblk1_right_mult_x_1_n1413, genblk1_right_mult_x_1_n1412,
genblk1_right_mult_x_1_n1411, genblk1_right_mult_x_1_n1410,
genblk1_right_mult_x_1_n1409, genblk1_right_mult_x_1_n1408,
genblk1_right_mult_x_1_n1407, genblk1_right_mult_x_1_n1406,
genblk1_right_mult_x_1_n1405, genblk1_right_mult_x_1_n1404,
genblk1_right_mult_x_1_n1396, genblk1_right_mult_x_1_n1395,
genblk1_right_mult_x_1_n1394, genblk1_right_mult_x_1_n1393,
genblk1_right_mult_x_1_n1392, genblk1_right_mult_x_1_n1391,
genblk1_right_mult_x_1_n1390, genblk1_right_mult_x_1_n1389,
genblk1_right_mult_x_1_n1388, genblk1_right_mult_x_1_n1387,
genblk1_right_mult_x_1_n1386, genblk1_right_mult_x_1_n1385,
genblk1_right_mult_x_1_n1384, genblk1_right_mult_x_1_n1383,
genblk1_right_mult_x_1_n1382, genblk1_right_mult_x_1_n1381,
genblk1_right_mult_x_1_n1380, genblk1_right_mult_x_1_n1379,
genblk1_right_mult_x_1_n1378, genblk1_right_mult_x_1_n1377,
genblk1_right_mult_x_1_n1376, genblk1_right_mult_x_1_n1375,
genblk1_right_mult_x_1_n1374, genblk1_right_mult_x_1_n1369,
genblk1_right_mult_x_1_n1368, genblk1_right_mult_x_1_n1367,
genblk1_right_mult_x_1_n1366, genblk1_right_mult_x_1_n1365,
genblk1_right_mult_x_1_n1363, genblk1_right_mult_x_1_n1362,
genblk1_right_mult_x_1_n1361, genblk1_right_mult_x_1_n1360,
genblk1_right_mult_x_1_n1359, genblk1_right_mult_x_1_n1358,
genblk1_right_mult_x_1_n1357, genblk1_right_mult_x_1_n1356,
genblk1_right_mult_x_1_n1355, genblk1_right_mult_x_1_n1354,
genblk1_right_mult_x_1_n1353, genblk1_right_mult_x_1_n1352,
genblk1_right_mult_x_1_n1351, genblk1_right_mult_x_1_n1350,
genblk1_right_mult_x_1_n1349, genblk1_right_mult_x_1_n1348,
genblk1_right_mult_x_1_n1347, genblk1_right_mult_x_1_n1346,
genblk1_right_mult_x_1_n1345, genblk1_right_mult_x_1_n1336,
genblk1_right_mult_x_1_n1335, genblk1_right_mult_x_1_n1334,
genblk1_right_mult_x_1_n1333, genblk1_right_mult_x_1_n1331,
genblk1_right_mult_x_1_n1330, genblk1_right_mult_x_1_n1329,
genblk1_right_mult_x_1_n1328, genblk1_right_mult_x_1_n1327,
genblk1_right_mult_x_1_n1326, genblk1_right_mult_x_1_n1325,
genblk1_right_mult_x_1_n1324, genblk1_right_mult_x_1_n1323,
genblk1_right_mult_x_1_n1322, genblk1_right_mult_x_1_n1321,
genblk1_right_mult_x_1_n1320, genblk1_right_mult_x_1_n1319,
genblk1_right_mult_x_1_n1318, genblk1_right_mult_x_1_n1317,
genblk1_right_mult_x_1_n1316, genblk1_right_mult_x_1_n1315,
genblk1_right_mult_x_1_n1314, genblk1_right_mult_x_1_n1309,
genblk1_right_mult_x_1_n1308, genblk1_right_mult_x_1_n1307,
genblk1_right_mult_x_1_n1306, genblk1_right_mult_x_1_n1305,
genblk1_right_mult_x_1_n1303, genblk1_right_mult_x_1_n1302,
genblk1_right_mult_x_1_n1301, genblk1_right_mult_x_1_n1300,
genblk1_right_mult_x_1_n1299, genblk1_right_mult_x_1_n1298,
genblk1_right_mult_x_1_n1297, genblk1_right_mult_x_1_n1296,
genblk1_right_mult_x_1_n1295, genblk1_right_mult_x_1_n1294,
genblk1_right_mult_x_1_n1293, genblk1_right_mult_x_1_n1292,
genblk1_right_mult_x_1_n1291, genblk1_right_mult_x_1_n1290,
genblk1_right_mult_x_1_n1289, genblk1_right_mult_x_1_n1288,
genblk1_right_mult_x_1_n1287, genblk1_right_mult_x_1_n1286,
genblk1_right_mult_x_1_n1276, genblk1_right_mult_x_1_n1275,
genblk1_right_mult_x_1_n1274, genblk1_right_mult_x_1_n1273,
genblk1_right_mult_x_1_n1272, genblk1_right_mult_x_1_n1271,
genblk1_right_mult_x_1_n1270, genblk1_right_mult_x_1_n1269,
genblk1_right_mult_x_1_n1268, genblk1_right_mult_x_1_n1267,
genblk1_right_mult_x_1_n1266, genblk1_right_mult_x_1_n1265,
genblk1_right_mult_x_1_n1264, genblk1_right_mult_x_1_n1263,
genblk1_right_mult_x_1_n1262, genblk1_right_mult_x_1_n1261,
genblk1_right_mult_x_1_n1260, genblk1_right_mult_x_1_n1259,
genblk1_right_mult_x_1_n1258, genblk1_right_mult_x_1_n1257,
genblk1_right_mult_x_1_n1256, genblk1_right_mult_x_1_n1255,
genblk1_right_mult_x_1_n1254, genblk1_right_mult_x_1_n1253,
genblk1_right_mult_x_1_n1249, genblk1_right_mult_x_1_n1248,
genblk1_right_mult_x_1_n1247, genblk1_right_mult_x_1_n1246,
genblk1_right_mult_x_1_n1245, genblk1_right_mult_x_1_n1244,
genblk1_right_mult_x_1_n1241, genblk1_right_mult_x_1_n1240,
genblk1_right_mult_x_1_n1239, genblk1_right_mult_x_1_n1238,
genblk1_right_mult_x_1_n1236, genblk1_right_mult_x_1_n1235,
genblk1_right_mult_x_1_n1234, genblk1_right_mult_x_1_n1233,
genblk1_right_mult_x_1_n1232, genblk1_right_mult_x_1_n1231,
genblk1_right_mult_x_1_n1230, genblk1_right_mult_x_1_n1229,
genblk1_right_mult_x_1_n1228, genblk1_right_mult_x_1_n1227,
genblk1_right_mult_x_1_n1226, genblk1_right_mult_x_1_n935,
genblk1_right_mult_x_1_n934, genblk1_right_mult_x_1_n933,
genblk1_right_mult_x_1_n932, genblk1_right_mult_x_1_n931,
genblk1_right_mult_x_1_n930, genblk1_right_mult_x_1_n926,
genblk1_right_mult_x_1_n925, genblk1_right_mult_x_1_n924,
genblk1_right_mult_x_1_n920, genblk1_right_mult_x_1_n919,
genblk1_right_mult_x_1_n918, genblk1_right_mult_x_1_n914,
genblk1_right_mult_x_1_n913, genblk1_right_mult_x_1_n912,
genblk1_right_mult_x_1_n893, genblk1_right_mult_x_1_n890,
genblk1_right_mult_x_1_n888, genblk1_right_mult_x_1_n887,
genblk1_right_mult_x_1_n886, genblk1_right_mult_x_1_n885,
genblk1_right_mult_x_1_n883, genblk1_right_mult_x_1_n882,
genblk1_right_mult_x_1_n881, genblk1_right_mult_x_1_n880,
genblk1_right_mult_x_1_n878, genblk1_right_mult_x_1_n877,
genblk1_right_mult_x_1_n876, genblk1_right_mult_x_1_n873,
genblk1_right_mult_x_1_n872, genblk1_right_mult_x_1_n871,
genblk1_right_mult_x_1_n870, genblk1_right_mult_x_1_n869,
genblk1_right_mult_x_1_n866, genblk1_right_mult_x_1_n865,
genblk1_right_mult_x_1_n864, genblk1_right_mult_x_1_n863,
genblk1_right_mult_x_1_n862, genblk1_right_mult_x_1_n860,
genblk1_right_mult_x_1_n859, genblk1_right_mult_x_1_n858,
genblk1_right_mult_x_1_n857, genblk1_right_mult_x_1_n856,
genblk1_right_mult_x_1_n855, genblk1_right_mult_x_1_n854,
genblk1_right_mult_x_1_n852, genblk1_right_mult_x_1_n851,
genblk1_right_mult_x_1_n850, genblk1_right_mult_x_1_n849,
genblk1_right_mult_x_1_n848, genblk1_right_mult_x_1_n847,
genblk1_right_mult_x_1_n846, genblk1_right_mult_x_1_n844,
genblk1_right_mult_x_1_n843, genblk1_right_mult_x_1_n842,
genblk1_right_mult_x_1_n841, genblk1_right_mult_x_1_n840,
genblk1_right_mult_x_1_n839, genblk1_right_mult_x_1_n838,
genblk1_right_mult_x_1_n836, genblk1_right_mult_x_1_n835,
genblk1_right_mult_x_1_n834, genblk1_right_mult_x_1_n833,
genblk1_right_mult_x_1_n832, genblk1_right_mult_x_1_n831,
genblk1_right_mult_x_1_n828, genblk1_right_mult_x_1_n827,
genblk1_right_mult_x_1_n826, genblk1_right_mult_x_1_n825,
genblk1_right_mult_x_1_n824, genblk1_right_mult_x_1_n823,
genblk1_right_mult_x_1_n822, genblk1_right_mult_x_1_n821,
genblk1_right_mult_x_1_n818, genblk1_right_mult_x_1_n817,
genblk1_right_mult_x_1_n816, genblk1_right_mult_x_1_n815,
genblk1_right_mult_x_1_n814, genblk1_right_mult_x_1_n813,
genblk1_right_mult_x_1_n812, genblk1_right_mult_x_1_n811,
genblk1_right_mult_x_1_n809, genblk1_right_mult_x_1_n808,
genblk1_right_mult_x_1_n807, genblk1_right_mult_x_1_n806,
genblk1_right_mult_x_1_n805, genblk1_right_mult_x_1_n804,
genblk1_right_mult_x_1_n803, genblk1_right_mult_x_1_n802,
genblk1_right_mult_x_1_n801, genblk1_right_mult_x_1_n800,
genblk1_right_mult_x_1_n798, genblk1_right_mult_x_1_n797,
genblk1_right_mult_x_1_n796, genblk1_right_mult_x_1_n795,
genblk1_right_mult_x_1_n794, genblk1_right_mult_x_1_n793,
genblk1_right_mult_x_1_n792, genblk1_right_mult_x_1_n791,
genblk1_right_mult_x_1_n790, genblk1_right_mult_x_1_n789,
genblk1_right_mult_x_1_n787, genblk1_right_mult_x_1_n786,
genblk1_right_mult_x_1_n785, genblk1_right_mult_x_1_n784,
genblk1_right_mult_x_1_n783, genblk1_right_mult_x_1_n782,
genblk1_right_mult_x_1_n781, genblk1_right_mult_x_1_n780,
genblk1_right_mult_x_1_n779, genblk1_right_mult_x_1_n778,
genblk1_right_mult_x_1_n776, genblk1_right_mult_x_1_n775,
genblk1_right_mult_x_1_n774, genblk1_right_mult_x_1_n773,
genblk1_right_mult_x_1_n772, genblk1_right_mult_x_1_n771,
genblk1_right_mult_x_1_n770, genblk1_right_mult_x_1_n769,
genblk1_right_mult_x_1_n768, genblk1_right_mult_x_1_n765,
genblk1_right_mult_x_1_n764, genblk1_right_mult_x_1_n763,
genblk1_right_mult_x_1_n762, genblk1_right_mult_x_1_n761,
genblk1_right_mult_x_1_n760, genblk1_right_mult_x_1_n759,
genblk1_right_mult_x_1_n758, genblk1_right_mult_x_1_n757,
genblk1_right_mult_x_1_n756, genblk1_right_mult_x_1_n755,
genblk1_right_mult_x_1_n752, genblk1_right_mult_x_1_n751,
genblk1_right_mult_x_1_n750, genblk1_right_mult_x_1_n749,
genblk1_right_mult_x_1_n748, genblk1_right_mult_x_1_n747,
genblk1_right_mult_x_1_n746, genblk1_right_mult_x_1_n745,
genblk1_right_mult_x_1_n744, genblk1_right_mult_x_1_n743,
genblk1_right_mult_x_1_n742, genblk1_right_mult_x_1_n740,
genblk1_right_mult_x_1_n739, genblk1_right_mult_x_1_n738,
genblk1_right_mult_x_1_n737, genblk1_right_mult_x_1_n736,
genblk1_right_mult_x_1_n735, genblk1_right_mult_x_1_n734,
genblk1_right_mult_x_1_n733, genblk1_right_mult_x_1_n732,
genblk1_right_mult_x_1_n731, genblk1_right_mult_x_1_n730,
genblk1_right_mult_x_1_n729, genblk1_right_mult_x_1_n728,
genblk1_right_mult_x_1_n727, genblk1_right_mult_x_1_n726,
genblk1_right_mult_x_1_n725, genblk1_right_mult_x_1_n724,
genblk1_right_mult_x_1_n723, genblk1_right_mult_x_1_n722,
genblk1_right_mult_x_1_n721, genblk1_right_mult_x_1_n720,
genblk1_right_mult_x_1_n719, genblk1_right_mult_x_1_n718,
genblk1_right_mult_x_1_n717, genblk1_right_mult_x_1_n716,
genblk1_right_mult_x_1_n715, genblk1_right_mult_x_1_n714,
genblk1_right_mult_x_1_n713, genblk1_right_mult_x_1_n712,
genblk1_right_mult_x_1_n711, genblk1_right_mult_x_1_n710,
genblk1_right_mult_x_1_n709, genblk1_right_mult_x_1_n708,
genblk1_right_mult_x_1_n707, genblk1_right_mult_x_1_n706,
genblk1_right_mult_x_1_n705, genblk1_right_mult_x_1_n704,
genblk1_right_mult_x_1_n703, genblk1_right_mult_x_1_n702,
genblk1_right_mult_x_1_n701, genblk1_right_mult_x_1_n700,
genblk1_right_mult_x_1_n699, genblk1_right_mult_x_1_n698,
genblk1_right_mult_x_1_n697, genblk1_right_mult_x_1_n696,
genblk1_right_mult_x_1_n695, genblk1_right_mult_x_1_n694,
genblk1_right_mult_x_1_n693, genblk1_right_mult_x_1_n692,
genblk1_right_mult_x_1_n691, genblk1_right_mult_x_1_n690,
genblk1_right_mult_x_1_n689, genblk1_right_mult_x_1_n688,
genblk1_right_mult_x_1_n687, genblk1_right_mult_x_1_n686,
genblk1_right_mult_x_1_n685, genblk1_right_mult_x_1_n684,
genblk1_right_mult_x_1_n683, genblk1_right_mult_x_1_n682,
genblk1_right_mult_x_1_n681, genblk1_right_mult_x_1_n680,
genblk1_right_mult_x_1_n679, genblk1_right_mult_x_1_n678,
genblk1_right_mult_x_1_n677, genblk1_right_mult_x_1_n676,
genblk1_right_mult_x_1_n675, genblk1_right_mult_x_1_n674,
genblk1_right_mult_x_1_n673, genblk1_right_mult_x_1_n672,
genblk1_right_mult_x_1_n671, genblk1_right_mult_x_1_n670,
genblk1_right_mult_x_1_n669, genblk1_right_mult_x_1_n668,
genblk1_right_mult_x_1_n667, genblk1_right_mult_x_1_n666,
genblk1_right_mult_x_1_n665, genblk1_right_mult_x_1_n664,
genblk1_right_mult_x_1_n663, genblk1_right_mult_x_1_n662,
genblk1_right_mult_x_1_n661, genblk1_right_mult_x_1_n660,
genblk1_right_mult_x_1_n659, genblk1_right_mult_x_1_n658,
genblk1_right_mult_x_1_n657, genblk1_right_mult_x_1_n655,
genblk1_right_mult_x_1_n654, genblk1_right_mult_x_1_n653,
genblk1_right_mult_x_1_n652, genblk1_right_mult_x_1_n651,
genblk1_right_mult_x_1_n650, genblk1_right_mult_x_1_n649,
genblk1_right_mult_x_1_n648, genblk1_right_mult_x_1_n647,
genblk1_right_mult_x_1_n646, genblk1_right_mult_x_1_n645,
genblk1_right_mult_x_1_n643, genblk1_right_mult_x_1_n642,
genblk1_right_mult_x_1_n641, genblk1_right_mult_x_1_n640,
genblk1_right_mult_x_1_n639, genblk1_right_mult_x_1_n638,
genblk1_right_mult_x_1_n637, genblk1_right_mult_x_1_n636,
genblk1_right_mult_x_1_n635, genblk1_right_mult_x_1_n634,
genblk1_right_mult_x_1_n633, genblk1_right_mult_x_1_n632,
genblk1_right_mult_x_1_n631, genblk1_right_mult_x_1_n630,
genblk1_right_mult_x_1_n629, genblk1_right_mult_x_1_n628,
genblk1_right_mult_x_1_n627, genblk1_right_mult_x_1_n626,
genblk1_right_mult_x_1_n625, genblk1_right_mult_x_1_n624,
genblk1_right_mult_x_1_n623, genblk1_right_mult_x_1_n622,
genblk1_right_mult_x_1_n621, genblk1_right_mult_x_1_n620,
genblk1_right_mult_x_1_n619, genblk1_right_mult_x_1_n618,
genblk1_right_mult_x_1_n617, genblk1_right_mult_x_1_n616,
genblk1_right_mult_x_1_n615, genblk1_right_mult_x_1_n614,
genblk1_right_mult_x_1_n613, genblk1_right_mult_x_1_n612,
genblk1_right_mult_x_1_n610, genblk1_right_mult_x_1_n609,
genblk1_right_mult_x_1_n608, genblk1_right_mult_x_1_n607,
genblk1_right_mult_x_1_n606, genblk1_right_mult_x_1_n605,
genblk1_right_mult_x_1_n604, genblk1_right_mult_x_1_n603,
genblk1_right_mult_x_1_n602, genblk1_right_mult_x_1_n601,
genblk1_right_mult_x_1_n600, genblk1_right_mult_x_1_n599,
genblk1_right_mult_x_1_n598, genblk1_right_mult_x_1_n597,
genblk1_right_mult_x_1_n596, genblk1_right_mult_x_1_n595,
genblk1_right_mult_x_1_n594, genblk1_right_mult_x_1_n593,
genblk1_right_mult_x_1_n591, genblk1_right_mult_x_1_n590,
genblk1_right_mult_x_1_n589, genblk1_right_mult_x_1_n588,
genblk1_right_mult_x_1_n587, genblk1_right_mult_x_1_n586,
genblk1_right_mult_x_1_n585, genblk1_right_mult_x_1_n584,
genblk1_right_mult_x_1_n582, genblk1_right_mult_x_1_n581,
genblk1_right_mult_x_1_n580, genblk1_right_mult_x_1_n579,
genblk1_right_mult_x_1_n578, genblk1_right_mult_x_1_n577,
genblk1_right_mult_x_1_n576, genblk1_right_mult_x_1_n575,
genblk1_right_mult_x_1_n574, genblk1_right_mult_x_1_n573,
genblk1_right_mult_x_1_n572, genblk1_right_mult_x_1_n571,
genblk1_right_mult_x_1_n570, genblk1_right_mult_x_1_n569,
genblk1_right_mult_x_1_n568, genblk1_right_mult_x_1_n567,
genblk1_right_mult_x_1_n566, genblk1_right_mult_x_1_n565,
genblk1_right_mult_x_1_n564, genblk1_right_mult_x_1_n563,
genblk1_right_mult_x_1_n562, genblk1_right_mult_x_1_n561,
genblk1_right_mult_x_1_n560, genblk1_right_mult_x_1_n558,
genblk1_right_mult_x_1_n557, genblk1_right_mult_x_1_n556,
genblk1_right_mult_x_1_n555, genblk1_right_mult_x_1_n554,
genblk1_right_mult_x_1_n553, genblk1_right_mult_x_1_n552,
genblk1_right_mult_x_1_n551, genblk1_right_mult_x_1_n550,
genblk1_right_mult_x_1_n549, genblk1_right_mult_x_1_n548,
genblk1_right_mult_x_1_n547, genblk1_right_mult_x_1_n545,
genblk1_right_mult_x_1_n544, genblk1_right_mult_x_1_n543,
genblk1_right_mult_x_1_n542, genblk1_right_mult_x_1_n541,
genblk1_right_mult_x_1_n539, genblk1_right_mult_x_1_n538,
genblk1_right_mult_x_1_n537, genblk1_right_mult_x_1_n536,
genblk1_right_mult_x_1_n535, genblk1_right_mult_x_1_n534,
genblk1_right_mult_x_1_n533, genblk1_right_mult_x_1_n532,
genblk1_right_mult_x_1_n531, genblk1_right_mult_x_1_n530,
genblk1_right_mult_x_1_n529, genblk1_right_mult_x_1_n528,
genblk1_right_mult_x_1_n527, genblk1_right_mult_x_1_n526,
genblk1_right_mult_x_1_n524, genblk1_right_mult_x_1_n523,
genblk1_right_mult_x_1_n522, genblk1_right_mult_x_1_n521,
genblk1_right_mult_x_1_n520, genblk1_right_mult_x_1_n519,
genblk1_middle_mult_x_1_n1572, genblk1_middle_mult_x_1_n1571,
genblk1_middle_mult_x_1_n1570, genblk1_middle_mult_x_1_n1569,
genblk1_middle_mult_x_1_n1568, genblk1_middle_mult_x_1_n1567,
genblk1_middle_mult_x_1_n1566, genblk1_middle_mult_x_1_n1565,
genblk1_middle_mult_x_1_n1564, genblk1_middle_mult_x_1_n1563,
genblk1_middle_mult_x_1_n1562, genblk1_middle_mult_x_1_n1561,
genblk1_middle_mult_x_1_n1560, genblk1_middle_mult_x_1_n1559,
genblk1_middle_mult_x_1_n1558, genblk1_middle_mult_x_1_n1557,
genblk1_middle_mult_x_1_n1556, genblk1_middle_mult_x_1_n1555,
genblk1_middle_mult_x_1_n1554, genblk1_middle_mult_x_1_n1553,
genblk1_middle_mult_x_1_n1552, genblk1_middle_mult_x_1_n1544,
genblk1_middle_mult_x_1_n1543, genblk1_middle_mult_x_1_n1542,
genblk1_middle_mult_x_1_n1541, genblk1_middle_mult_x_1_n1540,
genblk1_middle_mult_x_1_n1539, genblk1_middle_mult_x_1_n1538,
genblk1_middle_mult_x_1_n1537, genblk1_middle_mult_x_1_n1536,
genblk1_middle_mult_x_1_n1535, genblk1_middle_mult_x_1_n1534,
genblk1_middle_mult_x_1_n1533, genblk1_middle_mult_x_1_n1532,
genblk1_middle_mult_x_1_n1531, genblk1_middle_mult_x_1_n1530,
genblk1_middle_mult_x_1_n1529, genblk1_middle_mult_x_1_n1528,
genblk1_middle_mult_x_1_n1527, genblk1_middle_mult_x_1_n1526,
genblk1_middle_mult_x_1_n1525, genblk1_middle_mult_x_1_n1524,
genblk1_middle_mult_x_1_n1523, genblk1_middle_mult_x_1_n1522,
genblk1_middle_mult_x_1_n1521, genblk1_middle_mult_x_1_n1516,
genblk1_middle_mult_x_1_n1515, genblk1_middle_mult_x_1_n1510,
genblk1_middle_mult_x_1_n1509, genblk1_middle_mult_x_1_n1508,
genblk1_middle_mult_x_1_n1507, genblk1_middle_mult_x_1_n1506,
genblk1_middle_mult_x_1_n1505, genblk1_middle_mult_x_1_n1504,
genblk1_middle_mult_x_1_n1503, genblk1_middle_mult_x_1_n1502,
genblk1_middle_mult_x_1_n1501, genblk1_middle_mult_x_1_n1500,
genblk1_middle_mult_x_1_n1499, genblk1_middle_mult_x_1_n1498,
genblk1_middle_mult_x_1_n1497, genblk1_middle_mult_x_1_n1496,
genblk1_middle_mult_x_1_n1495, genblk1_middle_mult_x_1_n1494,
genblk1_middle_mult_x_1_n1493, genblk1_middle_mult_x_1_n1492,
genblk1_middle_mult_x_1_n1491, genblk1_middle_mult_x_1_n1490,
genblk1_middle_mult_x_1_n1482, genblk1_middle_mult_x_1_n1481,
genblk1_middle_mult_x_1_n1480, genblk1_middle_mult_x_1_n1478,
genblk1_middle_mult_x_1_n1477, genblk1_middle_mult_x_1_n1476,
genblk1_middle_mult_x_1_n1475, genblk1_middle_mult_x_1_n1474,
genblk1_middle_mult_x_1_n1473, genblk1_middle_mult_x_1_n1472,
genblk1_middle_mult_x_1_n1471, genblk1_middle_mult_x_1_n1470,
genblk1_middle_mult_x_1_n1469, genblk1_middle_mult_x_1_n1468,
genblk1_middle_mult_x_1_n1467, genblk1_middle_mult_x_1_n1466,
genblk1_middle_mult_x_1_n1465, genblk1_middle_mult_x_1_n1464,
genblk1_middle_mult_x_1_n1463, genblk1_middle_mult_x_1_n1462,
genblk1_middle_mult_x_1_n1461, genblk1_middle_mult_x_1_n1460,
genblk1_middle_mult_x_1_n1459, genblk1_middle_mult_x_1_n1454,
genblk1_middle_mult_x_1_n1448, genblk1_middle_mult_x_1_n1447,
genblk1_middle_mult_x_1_n1446, genblk1_middle_mult_x_1_n1445,
genblk1_middle_mult_x_1_n1444, genblk1_middle_mult_x_1_n1443,
genblk1_middle_mult_x_1_n1442, genblk1_middle_mult_x_1_n1441,
genblk1_middle_mult_x_1_n1440, genblk1_middle_mult_x_1_n1439,
genblk1_middle_mult_x_1_n1438, genblk1_middle_mult_x_1_n1437,
genblk1_middle_mult_x_1_n1436, genblk1_middle_mult_x_1_n1435,
genblk1_middle_mult_x_1_n1434, genblk1_middle_mult_x_1_n1433,
genblk1_middle_mult_x_1_n1432, genblk1_middle_mult_x_1_n1431,
genblk1_middle_mult_x_1_n1430, genblk1_middle_mult_x_1_n1429,
genblk1_middle_mult_x_1_n1428, genblk1_middle_mult_x_1_n1423,
genblk1_middle_mult_x_1_n1420, genblk1_middle_mult_x_1_n1419,
genblk1_middle_mult_x_1_n1416, genblk1_middle_mult_x_1_n1415,
genblk1_middle_mult_x_1_n1414, genblk1_middle_mult_x_1_n1413,
genblk1_middle_mult_x_1_n1412, genblk1_middle_mult_x_1_n1411,
genblk1_middle_mult_x_1_n1410, genblk1_middle_mult_x_1_n1409,
genblk1_middle_mult_x_1_n1408, genblk1_middle_mult_x_1_n1407,
genblk1_middle_mult_x_1_n1406, genblk1_middle_mult_x_1_n1405,
genblk1_middle_mult_x_1_n1404, genblk1_middle_mult_x_1_n1403,
genblk1_middle_mult_x_1_n1402, genblk1_middle_mult_x_1_n1401,
genblk1_middle_mult_x_1_n1400, genblk1_middle_mult_x_1_n1399,
genblk1_middle_mult_x_1_n1398, genblk1_middle_mult_x_1_n1397,
genblk1_middle_mult_x_1_n1392, genblk1_middle_mult_x_1_n1391,
genblk1_middle_mult_x_1_n1386, genblk1_middle_mult_x_1_n1385,
genblk1_middle_mult_x_1_n1384, genblk1_middle_mult_x_1_n1383,
genblk1_middle_mult_x_1_n1382, genblk1_middle_mult_x_1_n1381,
genblk1_middle_mult_x_1_n1380, genblk1_middle_mult_x_1_n1379,
genblk1_middle_mult_x_1_n1378, genblk1_middle_mult_x_1_n1377,
genblk1_middle_mult_x_1_n1376, genblk1_middle_mult_x_1_n1375,
genblk1_middle_mult_x_1_n1374, genblk1_middle_mult_x_1_n1373,
genblk1_middle_mult_x_1_n1372, genblk1_middle_mult_x_1_n1371,
genblk1_middle_mult_x_1_n1370, genblk1_middle_mult_x_1_n1369,
genblk1_middle_mult_x_1_n1368, genblk1_middle_mult_x_1_n1367,
genblk1_middle_mult_x_1_n1362, genblk1_middle_mult_x_1_n1361,
genblk1_middle_mult_x_1_n1358, genblk1_middle_mult_x_1_n1357,
genblk1_middle_mult_x_1_n1356, genblk1_middle_mult_x_1_n1355,
genblk1_middle_mult_x_1_n1354, genblk1_middle_mult_x_1_n1353,
genblk1_middle_mult_x_1_n1352, genblk1_middle_mult_x_1_n1350,
genblk1_middle_mult_x_1_n1349, genblk1_middle_mult_x_1_n1348,
genblk1_middle_mult_x_1_n1347, genblk1_middle_mult_x_1_n1346,
genblk1_middle_mult_x_1_n1345, genblk1_middle_mult_x_1_n1344,
genblk1_middle_mult_x_1_n1343, genblk1_middle_mult_x_1_n1342,
genblk1_middle_mult_x_1_n1341, genblk1_middle_mult_x_1_n1340,
genblk1_middle_mult_x_1_n1338, genblk1_middle_mult_x_1_n1337,
genblk1_middle_mult_x_1_n1336, genblk1_middle_mult_x_1_n1335,
genblk1_middle_mult_x_1_n1330, genblk1_middle_mult_x_1_n1329,
genblk1_middle_mult_x_1_n1328, genblk1_middle_mult_x_1_n1327,
genblk1_middle_mult_x_1_n1326, genblk1_middle_mult_x_1_n1325,
genblk1_middle_mult_x_1_n1324, genblk1_middle_mult_x_1_n1323,
genblk1_middle_mult_x_1_n1321, genblk1_middle_mult_x_1_n1320,
genblk1_middle_mult_x_1_n1319, genblk1_middle_mult_x_1_n1318,
genblk1_middle_mult_x_1_n1315, genblk1_middle_mult_x_1_n1314,
genblk1_middle_mult_x_1_n1313, genblk1_middle_mult_x_1_n1312,
genblk1_middle_mult_x_1_n1311, genblk1_middle_mult_x_1_n1310,
genblk1_middle_mult_x_1_n1309, genblk1_middle_mult_x_1_n1308,
genblk1_middle_mult_x_1_n1307, genblk1_middle_mult_x_1_n1306,
genblk1_middle_mult_x_1_n1027, genblk1_middle_mult_x_1_n1026,
genblk1_middle_mult_x_1_n1025, genblk1_middle_mult_x_1_n1024,
genblk1_middle_mult_x_1_n1023, genblk1_middle_mult_x_1_n1022,
genblk1_middle_mult_x_1_n1021, genblk1_middle_mult_x_1_n1017,
genblk1_middle_mult_x_1_n1016, genblk1_middle_mult_x_1_n1015,
genblk1_middle_mult_x_1_n1011, genblk1_middle_mult_x_1_n1010,
genblk1_middle_mult_x_1_n1009, genblk1_middle_mult_x_1_n1005,
genblk1_middle_mult_x_1_n1004, genblk1_middle_mult_x_1_n1003,
genblk1_middle_mult_x_1_n983, genblk1_middle_mult_x_1_n980,
genblk1_middle_mult_x_1_n978, genblk1_middle_mult_x_1_n977,
genblk1_middle_mult_x_1_n976, genblk1_middle_mult_x_1_n975,
genblk1_middle_mult_x_1_n974, genblk1_middle_mult_x_1_n973,
genblk1_middle_mult_x_1_n972, genblk1_middle_mult_x_1_n971,
genblk1_middle_mult_x_1_n970, genblk1_middle_mult_x_1_n969,
genblk1_middle_mult_x_1_n968, genblk1_middle_mult_x_1_n967,
genblk1_middle_mult_x_1_n966, genblk1_middle_mult_x_1_n963,
genblk1_middle_mult_x_1_n962, genblk1_middle_mult_x_1_n961,
genblk1_middle_mult_x_1_n960, genblk1_middle_mult_x_1_n959,
genblk1_middle_mult_x_1_n956, genblk1_middle_mult_x_1_n955,
genblk1_middle_mult_x_1_n954, genblk1_middle_mult_x_1_n953,
genblk1_middle_mult_x_1_n952, genblk1_middle_mult_x_1_n950,
genblk1_middle_mult_x_1_n949, genblk1_middle_mult_x_1_n948,
genblk1_middle_mult_x_1_n947, genblk1_middle_mult_x_1_n946,
genblk1_middle_mult_x_1_n945, genblk1_middle_mult_x_1_n944,
genblk1_middle_mult_x_1_n943, genblk1_middle_mult_x_1_n942,
genblk1_middle_mult_x_1_n941, genblk1_middle_mult_x_1_n940,
genblk1_middle_mult_x_1_n939, genblk1_middle_mult_x_1_n938,
genblk1_middle_mult_x_1_n937, genblk1_middle_mult_x_1_n936,
genblk1_middle_mult_x_1_n935, genblk1_middle_mult_x_1_n934,
genblk1_middle_mult_x_1_n933, genblk1_middle_mult_x_1_n932,
genblk1_middle_mult_x_1_n931, genblk1_middle_mult_x_1_n930,
genblk1_middle_mult_x_1_n929, genblk1_middle_mult_x_1_n928,
genblk1_middle_mult_x_1_n927, genblk1_middle_mult_x_1_n926,
genblk1_middle_mult_x_1_n925, genblk1_middle_mult_x_1_n924,
genblk1_middle_mult_x_1_n923, genblk1_middle_mult_x_1_n922,
genblk1_middle_mult_x_1_n921, genblk1_middle_mult_x_1_n918,
genblk1_middle_mult_x_1_n917, genblk1_middle_mult_x_1_n916,
genblk1_middle_mult_x_1_n915, genblk1_middle_mult_x_1_n914,
genblk1_middle_mult_x_1_n913, genblk1_middle_mult_x_1_n912,
genblk1_middle_mult_x_1_n911, genblk1_middle_mult_x_1_n908,
genblk1_middle_mult_x_1_n907, genblk1_middle_mult_x_1_n906,
genblk1_middle_mult_x_1_n905, genblk1_middle_mult_x_1_n904,
genblk1_middle_mult_x_1_n903, genblk1_middle_mult_x_1_n902,
genblk1_middle_mult_x_1_n901, genblk1_middle_mult_x_1_n899,
genblk1_middle_mult_x_1_n898, genblk1_middle_mult_x_1_n897,
genblk1_middle_mult_x_1_n896, genblk1_middle_mult_x_1_n895,
genblk1_middle_mult_x_1_n894, genblk1_middle_mult_x_1_n893,
genblk1_middle_mult_x_1_n892, genblk1_middle_mult_x_1_n891,
genblk1_middle_mult_x_1_n890, genblk1_middle_mult_x_1_n888,
genblk1_middle_mult_x_1_n887, genblk1_middle_mult_x_1_n886,
genblk1_middle_mult_x_1_n885, genblk1_middle_mult_x_1_n884,
genblk1_middle_mult_x_1_n883, genblk1_middle_mult_x_1_n882,
genblk1_middle_mult_x_1_n881, genblk1_middle_mult_x_1_n880,
genblk1_middle_mult_x_1_n879, genblk1_middle_mult_x_1_n878,
genblk1_middle_mult_x_1_n877, genblk1_middle_mult_x_1_n876,
genblk1_middle_mult_x_1_n875, genblk1_middle_mult_x_1_n874,
genblk1_middle_mult_x_1_n873, genblk1_middle_mult_x_1_n872,
genblk1_middle_mult_x_1_n871, genblk1_middle_mult_x_1_n870,
genblk1_middle_mult_x_1_n869, genblk1_middle_mult_x_1_n868,
genblk1_middle_mult_x_1_n867, genblk1_middle_mult_x_1_n866,
genblk1_middle_mult_x_1_n865, genblk1_middle_mult_x_1_n864,
genblk1_middle_mult_x_1_n863, genblk1_middle_mult_x_1_n862,
genblk1_middle_mult_x_1_n861, genblk1_middle_mult_x_1_n860,
genblk1_middle_mult_x_1_n859, genblk1_middle_mult_x_1_n858,
genblk1_middle_mult_x_1_n855, genblk1_middle_mult_x_1_n854,
genblk1_middle_mult_x_1_n853, genblk1_middle_mult_x_1_n852,
genblk1_middle_mult_x_1_n851, genblk1_middle_mult_x_1_n850,
genblk1_middle_mult_x_1_n849, genblk1_middle_mult_x_1_n848,
genblk1_middle_mult_x_1_n847, genblk1_middle_mult_x_1_n846,
genblk1_middle_mult_x_1_n845, genblk1_middle_mult_x_1_n842,
genblk1_middle_mult_x_1_n841, genblk1_middle_mult_x_1_n840,
genblk1_middle_mult_x_1_n839, genblk1_middle_mult_x_1_n838,
genblk1_middle_mult_x_1_n837, genblk1_middle_mult_x_1_n836,
genblk1_middle_mult_x_1_n835, genblk1_middle_mult_x_1_n834,
genblk1_middle_mult_x_1_n833, genblk1_middle_mult_x_1_n832,
genblk1_middle_mult_x_1_n830, genblk1_middle_mult_x_1_n829,
genblk1_middle_mult_x_1_n828, genblk1_middle_mult_x_1_n827,
genblk1_middle_mult_x_1_n826, genblk1_middle_mult_x_1_n825,
genblk1_middle_mult_x_1_n824, genblk1_middle_mult_x_1_n823,
genblk1_middle_mult_x_1_n822, genblk1_middle_mult_x_1_n821,
genblk1_middle_mult_x_1_n820, genblk1_middle_mult_x_1_n819,
genblk1_middle_mult_x_1_n818, genblk1_middle_mult_x_1_n817,
genblk1_middle_mult_x_1_n816, genblk1_middle_mult_x_1_n815,
genblk1_middle_mult_x_1_n814, genblk1_middle_mult_x_1_n813,
genblk1_middle_mult_x_1_n812, genblk1_middle_mult_x_1_n811,
genblk1_middle_mult_x_1_n810, genblk1_middle_mult_x_1_n809,
genblk1_middle_mult_x_1_n808, genblk1_middle_mult_x_1_n807,
genblk1_middle_mult_x_1_n806, genblk1_middle_mult_x_1_n805,
genblk1_middle_mult_x_1_n804, genblk1_middle_mult_x_1_n803,
genblk1_middle_mult_x_1_n802, genblk1_middle_mult_x_1_n801,
genblk1_middle_mult_x_1_n800, genblk1_middle_mult_x_1_n799,
genblk1_middle_mult_x_1_n798, genblk1_middle_mult_x_1_n797,
genblk1_middle_mult_x_1_n796, genblk1_middle_mult_x_1_n795,
genblk1_middle_mult_x_1_n794, genblk1_middle_mult_x_1_n793,
genblk1_middle_mult_x_1_n792, genblk1_middle_mult_x_1_n791,
genblk1_middle_mult_x_1_n790, genblk1_middle_mult_x_1_n789,
genblk1_middle_mult_x_1_n788, genblk1_middle_mult_x_1_n787,
genblk1_middle_mult_x_1_n786, genblk1_middle_mult_x_1_n785,
genblk1_middle_mult_x_1_n784, genblk1_middle_mult_x_1_n783,
genblk1_middle_mult_x_1_n782, genblk1_middle_mult_x_1_n781,
genblk1_middle_mult_x_1_n780, genblk1_middle_mult_x_1_n779,
genblk1_middle_mult_x_1_n778, genblk1_middle_mult_x_1_n777,
genblk1_middle_mult_x_1_n776, genblk1_middle_mult_x_1_n775,
genblk1_middle_mult_x_1_n774, genblk1_middle_mult_x_1_n773,
genblk1_middle_mult_x_1_n772, genblk1_middle_mult_x_1_n771,
genblk1_middle_mult_x_1_n770, genblk1_middle_mult_x_1_n769,
genblk1_middle_mult_x_1_n768, genblk1_middle_mult_x_1_n767,
genblk1_middle_mult_x_1_n766, genblk1_middle_mult_x_1_n765,
genblk1_middle_mult_x_1_n764, genblk1_middle_mult_x_1_n763,
genblk1_middle_mult_x_1_n762, genblk1_middle_mult_x_1_n761,
genblk1_middle_mult_x_1_n760, genblk1_middle_mult_x_1_n759,
genblk1_middle_mult_x_1_n758, genblk1_middle_mult_x_1_n757,
genblk1_middle_mult_x_1_n756, genblk1_middle_mult_x_1_n755,
genblk1_middle_mult_x_1_n754, genblk1_middle_mult_x_1_n753,
genblk1_middle_mult_x_1_n752, genblk1_middle_mult_x_1_n751,
genblk1_middle_mult_x_1_n750, genblk1_middle_mult_x_1_n749,
genblk1_middle_mult_x_1_n748, genblk1_middle_mult_x_1_n747,
genblk1_middle_mult_x_1_n746, genblk1_middle_mult_x_1_n745,
genblk1_middle_mult_x_1_n744, genblk1_middle_mult_x_1_n743,
genblk1_middle_mult_x_1_n742, genblk1_middle_mult_x_1_n741,
genblk1_middle_mult_x_1_n740, genblk1_middle_mult_x_1_n739,
genblk1_middle_mult_x_1_n738, genblk1_middle_mult_x_1_n737,
genblk1_middle_mult_x_1_n736, genblk1_middle_mult_x_1_n735,
genblk1_middle_mult_x_1_n733, genblk1_middle_mult_x_1_n732,
genblk1_middle_mult_x_1_n731, genblk1_middle_mult_x_1_n730,
genblk1_middle_mult_x_1_n729, genblk1_middle_mult_x_1_n728,
genblk1_middle_mult_x_1_n727, genblk1_middle_mult_x_1_n726,
genblk1_middle_mult_x_1_n725, genblk1_middle_mult_x_1_n724,
genblk1_middle_mult_x_1_n723, genblk1_middle_mult_x_1_n721,
genblk1_middle_mult_x_1_n720, genblk1_middle_mult_x_1_n719,
genblk1_middle_mult_x_1_n718, genblk1_middle_mult_x_1_n717,
genblk1_middle_mult_x_1_n716, genblk1_middle_mult_x_1_n715,
genblk1_middle_mult_x_1_n714, genblk1_middle_mult_x_1_n713,
genblk1_middle_mult_x_1_n712, genblk1_middle_mult_x_1_n711,
genblk1_middle_mult_x_1_n710, genblk1_middle_mult_x_1_n709,
genblk1_middle_mult_x_1_n708, genblk1_middle_mult_x_1_n707,
genblk1_middle_mult_x_1_n706, genblk1_middle_mult_x_1_n705,
genblk1_middle_mult_x_1_n704, genblk1_middle_mult_x_1_n703,
genblk1_middle_mult_x_1_n702, genblk1_middle_mult_x_1_n701,
genblk1_middle_mult_x_1_n700, genblk1_middle_mult_x_1_n699,
genblk1_middle_mult_x_1_n698, genblk1_middle_mult_x_1_n697,
genblk1_middle_mult_x_1_n696, genblk1_middle_mult_x_1_n695,
genblk1_middle_mult_x_1_n694, genblk1_middle_mult_x_1_n693,
genblk1_middle_mult_x_1_n692, genblk1_middle_mult_x_1_n691,
genblk1_middle_mult_x_1_n690, genblk1_middle_mult_x_1_n689,
genblk1_middle_mult_x_1_n688, genblk1_middle_mult_x_1_n687,
genblk1_middle_mult_x_1_n686, genblk1_middle_mult_x_1_n685,
genblk1_middle_mult_x_1_n684, genblk1_middle_mult_x_1_n683,
genblk1_middle_mult_x_1_n682, genblk1_middle_mult_x_1_n681,
genblk1_middle_mult_x_1_n680, genblk1_middle_mult_x_1_n679,
genblk1_middle_mult_x_1_n678, genblk1_middle_mult_x_1_n677,
genblk1_middle_mult_x_1_n676, genblk1_middle_mult_x_1_n675,
genblk1_middle_mult_x_1_n674, genblk1_middle_mult_x_1_n673,
genblk1_middle_mult_x_1_n672, genblk1_middle_mult_x_1_n671,
genblk1_middle_mult_x_1_n669, genblk1_middle_mult_x_1_n668,
genblk1_middle_mult_x_1_n667, genblk1_middle_mult_x_1_n666,
genblk1_middle_mult_x_1_n665, genblk1_middle_mult_x_1_n664,
genblk1_middle_mult_x_1_n663, genblk1_middle_mult_x_1_n662,
genblk1_middle_mult_x_1_n660, genblk1_middle_mult_x_1_n659,
genblk1_middle_mult_x_1_n658, genblk1_middle_mult_x_1_n657,
genblk1_middle_mult_x_1_n656, genblk1_middle_mult_x_1_n655,
genblk1_middle_mult_x_1_n654, genblk1_middle_mult_x_1_n653,
genblk1_middle_mult_x_1_n652, genblk1_middle_mult_x_1_n651,
genblk1_middle_mult_x_1_n650, genblk1_middle_mult_x_1_n649,
genblk1_middle_mult_x_1_n648, genblk1_middle_mult_x_1_n647,
genblk1_middle_mult_x_1_n646, genblk1_middle_mult_x_1_n645,
genblk1_middle_mult_x_1_n644, genblk1_middle_mult_x_1_n643,
genblk1_middle_mult_x_1_n642, genblk1_middle_mult_x_1_n641,
genblk1_middle_mult_x_1_n640, genblk1_middle_mult_x_1_n639,
genblk1_middle_mult_x_1_n638, genblk1_middle_mult_x_1_n636,
genblk1_middle_mult_x_1_n635, genblk1_middle_mult_x_1_n634,
genblk1_middle_mult_x_1_n633, genblk1_middle_mult_x_1_n632,
genblk1_middle_mult_x_1_n631, genblk1_middle_mult_x_1_n630,
genblk1_middle_mult_x_1_n629, genblk1_middle_mult_x_1_n628,
genblk1_middle_mult_x_1_n627, genblk1_middle_mult_x_1_n626,
genblk1_middle_mult_x_1_n625, genblk1_middle_mult_x_1_n623,
genblk1_middle_mult_x_1_n622, genblk1_middle_mult_x_1_n621,
genblk1_middle_mult_x_1_n620, genblk1_middle_mult_x_1_n619,
genblk1_middle_mult_x_1_n617, genblk1_middle_mult_x_1_n616,
genblk1_middle_mult_x_1_n615, genblk1_middle_mult_x_1_n614,
genblk1_middle_mult_x_1_n613, genblk1_middle_mult_x_1_n612,
genblk1_middle_mult_x_1_n611, genblk1_middle_mult_x_1_n610,
genblk1_middle_mult_x_1_n609, genblk1_middle_mult_x_1_n608,
genblk1_middle_mult_x_1_n607, genblk1_middle_mult_x_1_n606,
genblk1_middle_mult_x_1_n605, genblk1_middle_mult_x_1_n604,
genblk1_middle_mult_x_1_n602, genblk1_middle_mult_x_1_n601,
genblk1_middle_mult_x_1_n600, genblk1_middle_mult_x_1_n599,
genblk1_middle_mult_x_1_n598, genblk1_middle_mult_x_1_n597, n3, n16,
n17, n18, n19, n20, n21, n22, n23, n24, n25, n26, n27, n28, n29, n30,
n31, n32, n33, n34, n35, n36, n37, n38, n39, n40, n41, n42, n43, n44,
n45, n46, n47, n48, n49, n50, n51, n52, n53, n54, n55, n56, n57, n58,
n59, n60, n61, n62, n63, n64, n65, n66, n67, n68, n69, n70, n71, n72,
n73, n74, n75, n76, n77, n78, n79, n80, n81, n82, n83, n84, n85, n86,
n87, n88, n89, n90, n91, n92, n93, n94, n95, n96, n97, n98, n99, n100,
n101, n102, n103, n104, n105, n106, n107, n108, n109, n110, n111,
n112, n113, n114, n115, n116, n117, n118, n119, n120, n121, n122,
n123, n124, n125, n126, n127, n128, n129, n130, n131, n132, n133,
n134, n135, n136, n137, n138, n139, n140, n141, n142, n143, n144,
n145, n146, n147, n148, n149, n150, n151, n152, n153, n154, n155,
n156, n157, n158, n159, n160, n161, n162, n163, n164, n165, n166,
n167, n168, n169, n170, n171, n172, n173, n174, n175, n176, n177,
n178, n179, n180, n181, n182, n183, n184, n185, n186, n187, n188,
n189, n190, n191, n192, n193, n194, n195, n196, n197, n198, n199,
n200, n201, n202, n203, n204, n205, n206, n207, n208, n209, n210,
n211, n212, n213, n214, n215, n216, n217, n218, n219, n220, n221,
n222, n223, n224, n225, n226, n227, n228, n229, n230, n231, n232,
n233, n234, n235, n236, n237, n238, n239, n240, n241, n242, n243,
n244, n245, n246, n247, n248, n249, n250, n251, n252, n253, n254,
n255, n256, n257, n258, n259, n260, n261, n262, n263, n264, n265,
n266, n267, n268, n269, n270, n271, n272, n273, n274, n275, n276,
n277, n278, n279, n280, n281, n282, n283, n284, n285, n286, n287,
n288, n289, n290, n291, n292, n293, n294, n295, n296, n297, n298,
n299, n300, n301, n302, n303, n304, n305, n306, n307, n308, n309,
n310, n311, n312, n313, n314, n315, n316, n317, n318, n319, n320,
n321, n322, n323, n324, n325, n326, n327, n328, n329, n330, n331,
n332, n333, n334, n335, n336, n337, n338, n339, n340, n341, n342,
n343, n344, n345, n346, n347, n348, n349, n350, n351, n352, n353,
n354, n355, n356, n357, n358, n359, n360, n361, n362, n363, n364,
n365, n366, n367, n368, n369, n370, n371, n372, n373, n374, n375,
n376, n377, n378, n379, n380, n381, n382, n383, n384, n385, n386,
n387, n388, n389, n390, n391, n392, n393, n394, n395, n396, n397,
n398, n399, n400, n401, n402, n403, n404, n405, n406, n407, n408,
n409, n410, n411, n412, n413, n414, n415, n416, n417, n418, n419,
n420, n421, n422, n423, n424, n425, n426, n427, n428, n429, n430,
n431, n432, n433, n434, n435, n436, n437, n438, n439, n440, n441,
n442, n443, n444, n445, n446, n447, n448, n449, n450, n451, n452,
n453, n454, n455, n456, n457, n458, n459, n460, n461, n462, n463,
n464, n465, n466, n467, n468, n469, n470, n471, n472, n473, n474,
n475, n476, n477, n478, n479, n480, n481, n482, n483, n484, n485,
n486, n487, n488, n489, n490, n491, n492, n493, n494, n495, n496,
n497, n498, n499, n500, n501, n502, n503, n504, n505, n506, n507,
n508, n509, n510, n511, n512, n513, n514, n515, n516, n517, n518,
n519, n520, n521, n522, n523, n524, n525, n526, n527, n528, n529,
n530, n531, n532, n533, n534, n535, n536, n537, n538, n539, n540,
n541, n542, n543, n544, n545, n546, n547, n548, n549, n550, n551,
n552, n553, n554, n555, n556, n557, n558, n559, n560, n561, n562,
n563, n564, n565, n566, n567, n568, n569, n570, n571, n572, n573,
n574, n575, n576, n577, n578, n579, n580, n581, n582, n583, n584,
n585, n586, n587, n588, n589, n590, n591, n592, n593, n594, n595,
n596, n597, n598, n599, n600, n601, n602, n603, n604, n605, n606,
n607, n608, n609, n610, n611, n612, n613, n614, n615, n616, n617,
n618, n619, n620, n621, n622, n623, n624, n625, n626, n627, n628,
n629, n630, n631, n632, n633, n634, n635, n636, n637, n638, n639,
n640, n641, n642, n643, n644, n645, n646, n647, n648, n649, n650,
n651, n652, n653, n654, n655, n656, n657, n658, n659, n660, n661,
n662, n663, n664, n665, n666, n667, n668, n669, n670, n671, n672,
n673, n674, n675, n676, n677, n678, n679, n680, n681, n682, n683,
n684, n685, n686, n687, n688, n689, n690, n691, n692, n693, n694,
n695, n696, n697, n698, n699, n700, n701, n702, n703, n704, n705,
n706, n707, n708, n709, n710, n711, n712, n713, n714, n715, n716,
n717, n718, n719, n720, n721, n722, n723, n724, n725, n726, n727,
n728, n729, n730, n731, n732, n733, n734, n735, n736, n737, n738,
n739, n740, n741, n742, n743, n744, n745, n746, n747, n748, n749,
n750, n751, n752, n753, n754, n755, n756, n757, n758, n759, n760,
n761, n762, n763, n764, n765, n766, n767, n768, n769, n770, n771,
n772, n773, n774, n775, n776, n777, n778, n779, n780, n781, n782,
n783, n784, n785, n786, n787, n788, n789, n790, n791, n792, n793,
n794, n795, n796, n797, n798, n799, n800, n801, n802, n803, n804,
n805, n806, n807, n808, n809, n810, n811, n812, n813, n814, n815,
n816, n817, n818, n819, n820, n821, n822, n823, n824, n825, n826,
n827, n828, n829, n830, n831, n832, n833, n834, n835, n836, n837,
n838, n839, n840, n841, n842, n843, n844, n845, n846, n847, n848,
n849, n850, n851, n852, n853, n854, n855, n856, n857, n858, n859,
n860, n861, n862, n863, n864, n865, n866, n867, n868, n869, n870,
n871, n872, n873, n874, n875, n876, n877, n878, n879, n880, n881,
n882, n883, n884, n885, n886, n887, n888, n889, n890, n891, n892,
n893, n894, n895, n896, n897, n898, n899, n900, n901, n902, n903,
n904, n905, n906, n907, n908, n909, n910, n911, n912, n913, n914,
n915, n916, n917, n918, n919, n920, n921, n922, n923, n924, n925,
n926, n927, n928, n929, n930, n931, n932, n933, n934, n935, n936,
n937, n938, n939, n940, n941, n942, n943, n944, n945, n946, n947,
n948, n949, n950, n951, n952, n953, n954, n955, n956, n957, n958,
n959, n960, n961, n962, n963, n964, n965, n966, n967, n968, n969,
n970, n971, n972, n973, n974, n975, n976, n977, n978, n979, n980,
n981, n982, n983, n984, n985, n986, n987, n988, n989, n990, n991,
n992, n993, n994, n995, n996, n997, n998, n999, n1000, n1001, n1002,
n1003, n1004, n1005, n1006, n1007, n1008, n1009, n1010, n1011, n1012,
n1013, n1014, n1015, n1016, n1017, n1018, n1019, n1020, n1021, n1022,
n1023, n1024, n1025, n1026, n1027, n1028, n1029, n1030, n1031, n1032,
n1033, n1034, n1035, n1036, n1037, n1038, n1039, n1040, n1041, n1042,
n1043, n1044, n1045, n1046, n1047, n1048, n1049, n1050, n1051, n1052,
n1053, n1054, n1055, n1056, n1057, n1058, n1059, n1060, n1061, n1062,
n1063, n1064, n1065, n1066, n1067, n1068, n1069, n1070, n1071, n1072,
n1073, n1074, n1075, n1076, n1077, n1078, n1079, n1080, n1081, n1082,
n1083, n1084, n1085, n1086, n1087, n1088, n1089, n1090, n1091, n1092,
n1093, n1094, n1095, n1096, n1097, n1098, n1099, n1100, n1101, n1102,
n1103, n1104, n1105, n1106, n1107, n1108, n1109, n1110, n1111, n1112,
n1113, n1114, n1115, n1116, n1117, n1118, n1119, n1120, n1121, n1122,
n1123, n1124, n1125, n1126, n1127, n1128, n1129, n1130, n1131, n1132,
n1133, n1134, n1135, n1136, n1137, n1138, n1139, n1140, n1141, n1142,
n1143, n1144, n1145, n1146, n1147, n1148, n1149, n1150, n1151, n1152,
n1153, n1154, n1155, n1156, n1157, n1158, n1159, n1160, n1161, n1162,
n1163, n1164, n1165, n1166, n1167, n1168, n1169, n1170, n1171, n1172,
n1173, n1174, n1175, n1176, n1177, n1178, n1179, n1180, n1181, n1182,
n1183, n1184, n1185, n1186, n1187, n1188, n1189, n1190, n1191, n1192,
n1193, n1194, n1195, n1196, n1197, n1198, n1199, n1200, n1201, n1202,
n1203, n1204, n1205, n1206, n1207, n1208, n1209, n1210, n1211, n1212,
n1213, n1214, n1215, n1216, n1217, n1218, n1219, n1220, n1221, n1222,
n1223, n1224, n1225, n1226, n1227, n1228, n1229, n1230, n1231, n1232,
n1233, n1234, n1235, n1236, n1237, n1238, n1239, n1240, n1241, n1242,
n1243, n1244, n1245, n1246, n1247, n1248, n1249, n1250, n1251, n1252,
n1253, n1254, n1255, n1256, n1257, n1258, n1259, n1260, n1261, n1262,
n1263, n1264, n1265, n1266, n1267, n1268, n1269, n1270, n1271, n1272,
n1273, n1274, n1275, n1276, n1277, n1278, n1279, n1280, n1281, n1282,
n1283, n1284, n1285, n1286, n1287, n1288, n1289, n1290, n1291, n1292,
n1293, n1294, n1295, n1296, n1297, n1298, n1299, n1300, n1301, n1302,
n1303, n1304, n1305, n1306, n1307, n1308, n1309, n1310, n1311, n1312,
n1313, n1314, n1315, n1316, n1317, n1318, n1319, n1320, n1321, n1322,
n1323, n1324, n1325, n1326, n1327, n1328, n1329, n1330, n1331, n1332,
n1333, n1334, n1335, n1336, n1337, n1338, n1339, n1340, n1341, n1342,
n1343, n1344, n1345, n1346, n1347, n1348, n1349, n1350, n1351, n1352,
n1353, n1354, n1355, n1356, n1357, n1358, n1359, n1360, n1361, n1362,
n1363, n1364, n1365, n1366, n1367, n1368, n1369, n1370, n1371, n1372,
n1373, n1374, n1375, n1376, n1377, n1378, n1379, n1380, n1381, n1382,
n1383, n1384, n1385, n1386, n1387, n1388, n1389, n1390, n1391, n1392,
n1393, n1394, n1395, n1396, n1397, n1398, n1399, n1400, n1401, n1402,
n1403, n1404, n1405, n1406, n1407, n1408, n1409, n1410, n1411, n1412,
n1413, n1414, n1415, n1416, n1417, n1418, n1419, n1420, n1421, n1422,
n1423, n1424, n1425, n1426, n1427, n1428, n1429, n1430, n1431, n1432,
n1433, n1434, n1435, n1436, n1437, n1438, n1439, n1440, n1441, n1442,
n1443, n1444, n1445, n1446, n1447, n1448, n1449, n1450, n1451, n1452,
n1453, n1454, n1455, n1456, n1457, n1458, n1459, n1460, n1461, n1462,
n1463, n1464, n1465, n1466, n1467, n1468, n1469, n1470, n1471, n1472,
n1473, n1474, n1475, n1476, n1477, n1478, n1479, n1480, n1481, n1482,
n1483, n1484, n1485, n1486, n1487, n1488, n1489, n1490, n1491, n1492,
n1493, n1494, n1495, n1496, n1497, n1498, n1499, n1500, n1501, n1502,
n1503, n1504, n1505, n1506, n1507, n1508, n1509, n1510, n1511, n1512,
n1513, n1514, n1515, n1516, n1517, n1518, n1519, n1520, n1521, n1522,
n1523, n1524, n1525, n1526, n1527, n1528, n1529, n1530, n1531, n1532,
n1533, n1534, n1535, n1536, n1537, n1538, n1539, n1540, n1541, n1542,
n1543, n1544, n1545, n1546, n1547, n1548, n1549, n1550, n1551, n1552,
n1553, n1554, n1555, n1556, n1557, n1558, n1559, n1560, n1561, n1562,
n1563, n1564, n1565, n1566, n1567, n1568, n1569, n1570, n1571, n1572,
n1573, n1574, n1575, n1576, n1577, n1578, n1579, n1580, n1581, n1582,
n1583, n1584, n1585, n1586, n1587, n1588, n1589, n1590, n1591, n1592,
n1593, n1594, n1595, n1596, n1597, n1598, n1599, n1600, n1601, n1602,
n1603, n1604, n1605, n1606, n1607, n1608, n1609, n1610, n1611, n1612,
n1613, n1614, n1615, n1616, n1617, n1618, n1619, n1620, n1621, n1622,
n1623, n1624, n1625, n1626, n1627, n1628, n1629, n1630, n1631, n1632,
n1633, n1634, n1635, n1636, n1637, n1638, n1639, n1640, n1641, n1642,
n1643, n1644, n1645, n1646, n1647, n1648, n1649, n1650, n1651, n1652,
n1653, n1654, n1655, n1656, n1657, n1658, n1659, n1660, n1661, n1662,
n1663, n1664, n1665, n1666, n1667, n1668, n1669, n1670, n1671, n1672,
n1673, n1674, n1675, n1676, n1677, n1678, n1679, n1680, n1681, n1682,
n1683, n1684, n1685, n1686, n1687, n1688, n1689, n1690, n1691, n1692,
n1693, n1694, n1695, n1696, n1697, n1698, n1699, n1700, n1701, n1702,
n1703, n1704, n1705, n1706, n1707, n1708, n1709, n1710, n1711, n1712,
n1713, n1714, n1715, n1716, n1717, n1718, n1719, n1720, n1721, n1722,
n1723, n1724, n1725, n1726, n1727, n1728, n1729, n1730, n1731, n1732,
n1733, n1734, n1735, n1736, n1737, n1738, n1739, n1740, n1741, n1742,
n1743, n1744, n1745, n1746, n1747, n1748, n1749, n1750, n1751, n1752,
n1753, n1754, n1755, n1756, n1757, n1758, n1759, n1760, n1761, n1762,
n1763, n1764, n1765, n1766, n1767, n1768, n1769, n1770, n1771, n1772,
n1773, n1774, n1775, n1776, n1777, n1778, n1779, n1780, n1781, n1782,
n1783, n1784, n1785, n1786, n1787, n1788, n1789, n1790, n1791, n1792,
n1793, n1794, n1795, n1796, n1797, n1798, n1799, n1800, n1801, n1802,
n1803, n1804, n1805, n1806, n1807, n1808, n1809, n1810, n1811, n1812,
n1813, n1814, n1815, n1816, n1817, n1818, n1819, n1820, n1821, n1822,
n1823, n1824, n1825, n1826, n1827, n1828, n1829, n1830, n1831, n1832,
n1833, n1834, n1835, n1836, n1837, n1838, n1839, n1840, n1841, n1842,
n1843, n1844, n1845, n1846, n1847, n1848, n1849, n1850, n1851, n1852,
n1853, n1854, n1855, n1856, n1857, n1858, n1859, n1860, n1861, n1862,
n1863, n1864, n1865, n1866, n1867, n1868, n1869, n1870, n1871, n1872,
n1873, n1874, n1875, n1876, n1877, n1878, n1879, n1880, n1881, n1882,
n1883, n1884, n1885, n1886, n1887, n1888, n1889, n1890, n1891, n1892,
n1893, n1894, n1895, n1896, n1897, n1898, n1899, n1900, n1901, n1902,
n1903, n1904, n1905, n1906, n1907, n1908, n1909, n1910, n1911, n1912,
n1913, n1914, n1915, n1916, n1917, n1918, n1919, n1920, n1921, n1922,
n1923, n1924, n1925, n1926, n1927, n1928, n1929, n1930, n1931, n1932,
n1933, n1934, n1935, n1936, n1937, n1938, n1939, n1940, n1941, n1942,
n1943, n1944, n1945, n1946, n1947, n1948, n1949, n1950, n1951, n1952,
n1953, n1954, n1955, n1956, n1957, n1958, n1959, n1960, n1961, n1962,
n1963, n1964, n1965, n1966, n1967, n1968, n1969, n1970, n1971, n1972,
n1973, n1974, n1975, n1976, n1977, n1978, n1979, n1980, n1981, n1982,
n1983, n1984, n1985, n1986, n1987, n1988, n1989, n1990, n1991, n1992,
n1993, n1994, n1995, n1996, n1997, n1998, n1999, n2000, n2001, n2002,
n2003, n2004, n2005, n2006, n2007, n2008, n2009, n2010, n2011, n2012,
n2013, n2014, n2015, n2016, n2017, n2018, n2019, n2020, n2021, n2022,
n2023, n2024, n2025, n2026, n2027, n2028, n2029, n2030, n2031, n2032,
n2033, n2034, n2035, n2036, n2037, n2038, n2039, n2040, n2041, n2042,
n2043, n2044, n2045, n2046, n2047, n2048, n2049, n2050, n2051, n2052,
n2053, n2054, n2055, n2056, n2057, n2058, n2059, n2060, n2061, n2062,
n2063, n2064, n2065, n2066, n2067, n2068, n2069, n2070, n2071, n2072,
n2073, n2074, n2075, n2076, n2077, n2078, n2079, n2080, n2081, n2082,
n2083, n2084, n2085, n2086, n2087, n2088, n2089, n2090, n2091, n2092,
n2093, n2094, n2095, n2096, n2097, n2098, n2099, n2100, n2101, n2102,
n2103, n2104, n2105, n2106, n2107, n2108, n2109, n2110, n2111, n2112,
n2113, n2114, n2115, n2116, n2117, n2118, n2119, n2120, n2121, n2122,
n2123, n2124, n2125, n2126, n2127, n2128, n2129, n2130, n2131, n2132,
n2133, n2134, n2135, n2136, n2137, n2138, n2139, n2140, n2141, n2142,
n2143, n2144, n2145, n2146, n2147, n2148, n2149, n2150, n2151, n2152,
n2153, n2154, n2155, n2156, n2157, n2158, n2159, n2160, n2161, n2162,
n2163, n2164, n2165, n2166, n2167, n2168, n2169, n2170, n2171, n2172,
n2173, n2174, n2175, n2176, n2177, n2178, n2179, n2180, n2181, n2182,
n2183, n2184, n2185, n2186, n2187, n2188, n2189, n2190, n2191, n2192,
n2193, n2194, n2195, n2196, n2197, n2198, n2199, n2200, n2201, n2202,
n2203, n2204, n2205, n2206, n2207, n2208, n2209, n2210, n2211, n2212,
n2213, n2214, n2215, n2216, n2217, n2218, n2219, n2220, n2221, n2222,
n2223, n2224, n2225, n2226, n2227, n2228, n2229, n2230, n2231, n2232,
n2233, n2234, n2235, n2236, n2237, n2238, n2239, n2240, n2241, n2242,
n2243, n2244, n2245, n2246, n2247, n2248, n2249, n2250, n2251, n2252,
n2253, n2254, n2255, n2256, n2257, n2258, n2259, n2260, n2261, n2262,
n2263, n2264, n2265, n2266, n2267, n2268, n2269, n2270, n2271, n2272,
n2273, n2274, n2275, n2276, n2277, n2278, n2279, n2280, n2281, n2282,
n2283, n2284, n2285, n2286, n2287, n2288, n2289, n2290, n2291, n2292,
n2293, n2294, n2295, n2296, n2297, n2298, n2299, n2300, n2301, n2302,
n2303, n2304, n2305, n2306, n2307, n2308, n2309, n2310, n2311, n2312,
n2313, n2314, n2315, n2316, n2317, n2318, n2319, n2320, n2321, n2322,
n2323, n2324, n2325, n2326, n2327, n2328, n2329, n2330, n2331, n2332,
n2333, n2334, n2335, n2336, n2337, n2338, n2339, n2340, n2341, n2342,
n2343, n2344, n2345, n2346, n2347, n2348, n2349, n2350, n2351, n2352,
n2353, n2354, n2355, n2356, n2357, n2358, n2359, n2360, n2361, n2362,
n2363, n2364, n2365, n2366, n2367, n2368, n2369, n2370, n2371, n2372,
n2373, n2374, n2375, n2376, n2377, n2378, n2379, n2380, n2381, n2382,
n2383, n2384, n2385, n2386, n2387, n2388, n2389, n2390, n2391, n2392,
n2393, n2394, n2395, n2396, n2397, n2398, n2399, n2400, n2401, n2402,
n2403, n2404, n2405, n2406, n2407, n2408, n2409, n2410, n2411, n2412,
n2413, n2414, n2415, n2416, n2417, n2418, n2419, n2420, n2421, n2422,
n2423, n2424, n2425, n2426, n2427, n2428, n2429, n2430, n2431, n2432,
n2433, n2434, n2435, n2436, n2437, n2438, n2439, n2440, n2441, n2442,
n2443, n2444, n2445, n2446, n2447, n2448, n2449, n2450, n2451, n2452,
n2453, n2454, n2455, n2456, n2457, n2458, n2459, n2460, n2461, n2462,
n2463, n2464, n2465, n2466, n2467, n2468, n2469, n2470, n2471, n2472,
n2473, n2474, n2475, n2476, n2477, n2478, n2479, n2480, n2481, n2482,
n2483, n2484, n2485, n2486, n2487, n2488, n2489, n2490, n2491, n2492,
n2493, n2494, n2495, n2496, n2497, n2498, n2499, n2500, n2501, n2502,
n2503, n2504, n2505, n2506, n2507, n2508, n2509, n2510, n2511, n2512,
n2513, n2514, n2515, n2516, n2517, n2518, n2519, n2520, n2521, n2522,
n2523, n2524, n2525, n2526, n2527, n2528, n2529, n2530, n2531, n2532,
n2533, n2534, n2535, n2536, n2537, n2538, n2539, n2540, n2541, n2542,
n2543, n2544, n2545, n2546, n2547, n2548, n2549, n2550, n2551, n2552,
n2553, n2554, n2555, n2556, n2557, n2558, n2559, n2560, n2561, n2562,
n2563, n2564, n2565, n2566, n2567, n2568, n2569, n2570, n2571, n2572,
n2573, n2574, n2575, n2576, n2577, n2578, n2579, n2580, n2581, n2582,
n2583, n2584, n2585, n2586, n2587, n2588, n2589, n2590, n2591, n2592,
n2593, n2594, n2595, n2596, n2597, n2598, n2599, n2600, n2601, n2602,
n2603, n2604, n2605, n2606, n2607, n2608, n2609, n2610, n2611, n2612,
n2613, n2614, n2615, n2616, n2617, n2618, n2619, n2620, n2621, n2622,
n2623, n2624, n2625, n2626, n2627, n2628, n2629, n2630, n2631, n2632,
n2633, n2634, n2635, n2636, n2637, n2638, n2639, n2640, n2641, n2642,
n2643, n2644, n2645, n2646, n2647, n2648, n2649, n2650, n2651, n2652,
n2653, n2654, n2655, n2656, n2657, n2658, n2659, n2660, n2661, n2662,
n2663, n2664, n2665, n2666, n2667, n2668, n2669, n2670, n2671, n2672,
n2673, n2674, n2675, n2676, n2677, n2678, n2679, n2680, n2681, n2682,
n2683, n2684, n2685, n2686, n2687, n2688, n2689, n2690, n2691, n2692,
n2693, n2694, n2695, n2696, n2697, n2698, n2699, n2700, n2701, n2702,
n2703, n2704, n2705, n2706, n2707, n2708, n2709, n2710, n2711, n2712,
n2713, n2714, n2715, n2716, n2717, n2718, n2719, n2720, n2721, n2722,
n2723, n2724, n2725, n2726, n2727, n2728, n2729, n2730, n2731, n2732,
n2733, n2734, n2735, n2736, n2737, n2738, n2739, n2740, n2741, n2742,
n2743, n2744, n2745, n2746, n2747, n2748, n2749, n2750, n2751, n2752,
n2753, n2754, n2755, n2756, n2757, n2758, n2759, n2760, n2761, n2762,
n2763, n2764, n2765, n2766, n2767, n2768, n2769, n2770, n2771, n2772,
n2773, n2774, n2775, n2776, n2777, n2778, n2779, n2780, n2781, n2782,
n2783, n2784, n2785, n2786, n2787, n2788, n2789, n2790, n2791, n2792,
n2793, n2794, n2795, n2796, n2797, n2798, n2799, n2800, n2801, n2802,
n2803, n2804, n2805, n2806, n2807, n2808, n2809, n2810, n2811, n2812,
n2813, n2814, n2815, n2816, n2817, n2818, n2819, n2820, n2821, n2822,
n2823, n2824, n2825, n2826, n2827, n2828, n2829, n2830, n2831, n2832,
n2833, n2834, n2835, n2836, n2837, n2838, n2839, n2840, n2841, n2842,
n2843, n2844, n2845, n2846, n2847, n2848, n2849, n2850, n2851, n2852,
n2853, n2854, n2855, n2856, n2857, n2858, n2859, n2860, n2861, n2862,
n2863, n2864, n2865, n2866, n2867, n2868, n2869, n2870, n2871, n2872,
n2873, n2874, n2875, n2876, n2877, n2878, n2879, n2880, n2881, n2882,
n2883, n2884, n2885, n2886, n2887, n2888, n2889, n2890, n2891, n2892,
n2893, n2894, n2895, n2896, n2897, n2898, n2899, n2900, n2901, n2902,
n2903, n2904, n2905, n2906, n2907, n2908, n2909, n2910, n2911, n2912,
n2913, n2914, n2915, n2916, n2917, n2918, n2919, n2920, n2921, n2922,
n2923, n2924, n2925, n2926, n2927, n2928, n2929, n2930, n2931, n2932,
n2933, n2934, n2935, n2936, n2937, n2938, n2939, n2940, n2941, n2942,
n2943, n2944, n2945, n2946, n2947, n2948, n2949, n2950, n2951, n2952,
n2953, n2954, n2955, n2956, n2957, n2958, n2959, n2960, n2961, n2962,
n2963, n2964, n2965, n2966, n2967, n2968, n2969, n2970, n2971, n2972,
n2973, n2974, n2975, n2976, n2977, n2978, n2979, n2980, n2981, n2982,
n2983, n2984, n2985, n2986, n2987, n2988, n2989, n2990, n2991, n2992,
n2993, n2994, n2995, n2996, n2997, n2998, n2999, n3000, n3001, n3002,
n3003, n3004, n3005, n3006, n3007, n3008, n3009, n3010, n3011, n3012,
n3013, n3014, n3015, n3016, n3017, n3018, n3019, n3020, n3021, n3022,
n3023, n3024, n3025, n3026, n3027, n3028, n3029, n3030, n3031, n3032,
n3033, n3034, n3035, n3036, n3037, n3038, n3039, n3040, n3041, n3042,
n3043, n3044, n3045, n3046, n3047, n3048, n3049, n3050, n3051, n3052,
n3053, n3054, n3055, n3056, n3057, n3058, n3059, n3060, n3061, n3062,
n3063, n3064, n3065, n3066, n3067, n3068, n3069, n3070, n3071, n3072,
n3073, n3074, n3075, n3076, n3077, n3078, n3079, n3080, n3081, n3082,
n3083, n3084, n3085, n3086, n3087, n3088, n3089, n3090, n3091, n3092,
n3093, n3094, n3095, n3096, n3097, n3098, n3099, n3100, n3101, n3102,
n3103, n3104, n3105, n3106, n3107, n3108, n3109, n3110, n3111, n3112,
n3113, n3114, n3115, n3116, n3117, n3118, n3119, n3120, n3121, n3122,
n3123, n3124, n3125, n3126, n3127, n3128, n3129, n3130, n3131, n3132,
n3133, n3134, n3135, n3136, n3137, n3138, n3139, n3140, n3141, n3142,
n3143, n3144, n3145, n3146, n3147, n3148, n3149, n3150, n3151, n3152,
n3153, n3154, n3155, n3156, n3157, n3158, n3159, n3160, n3161, n3162,
n3163, n3164, n3165, n3166, n3167, n3168, n3169, n3170, n3171, n3172,
n3173, n3174, n3175, n3176, n3177, n3178, n3179, n3180, n3181, n3182,
n3183, n3184, n3185, n3186, n3187, n3188, n3189, n3190, n3191, n3192,
n3193, n3194, n3195, n3196, n3197, n3198, n3199, n3200, n3201, n3202,
n3203, n3204, n3205, n3206, n3207, n3208, n3209, n3210, n3211, n3212,
n3213, n3214, n3215, n3216, n3217, n3218, n3219, n3220, n3221, n3222,
n3223, n3224, n3225, n3226, n3227, n3228, n3229, n3230, n3231, n3232,
n3233, n3234, n3235, n3236, n3237, n3238, n3239, n3240, n3241, n3242,
n3243, n3244, n3245, n3246, n3247, n3248, n3249, n3250, n3251, n3252,
n3253, n3254, n3255, n3256, n3257, n3258, n3259, n3260, n3261, n3262,
n3263, n3264, n3265, n3266, n3267, n3268, n3269, n3270, n3271, n3272,
n3273, n3274, n3275, n3276, n3277, n3278, n3279, n3280, n3281, n3282,
n3283, n3284, n3285, n3286, n3287, n3288, n3289, n3290, n3291, n3292,
n3293, n3294, n3295, n3296, n3297, n3298, n3299, n3300, n3301, n3302,
n3303, n3304, n3305, n3306, n3307, n3308, n3309, n3310, n3311, n3312,
n3313, n3314, n3315, n3316, n3317, n3318, n3319, n3320, n3321, n3322,
n3323, n3324, n3325, n3326, n3327, n3328, n3329, n3330, n3331, n3332,
n3333, n3334, n3335, n3336, n3337, n3338, n3339, n3340, n3341, n3342,
n3343, n3344, n3345, n3346, n3347, n3348, n3349, n3350, n3351, n3352,
n3353, n3354, n3355, n3356, n3357, n3358, n3359, n3360, n3361, n3362,
n3363, n3364, n3365, n3366, n3367, n3368, n3369, n3370, n3371, n3372,
n3373, n3374, n3375, n3376, n3377, n3378, n3379, n3380, n3381, n3382,
n3383, n3384, n3385, n3386, n3387, n3388, n3389, n3390, n3391, n3392,
n3393, n3394, n3395, n3396, n3397, n3398, n3399, n3400, n3401, n3402,
n3403, n3404, n3405, n3406, n3407, n3408, n3409, n3410, n3411, n3412,
n3413, n3414, n3415, n3416, n3417, n3418, n3419, n3420, n3421, n3422,
n3423, n3424, n3425, n3426, n3427, n3428, n3429, n3430, n3431, n3432,
n3433, n3434, n3435, n3436, n3437, n3438, n3439, n3440, n3441, n3442,
n3443, n3444, n3445, n3446, n3447, n3448, n3449, n3450, n3451, n3452,
n3453, n3454, n3455, n3456, n3457, n3458, n3459, n3460, n3461, n3462,
n3463, n3464, n3465, n3466, n3467, n3468, n3469, n3470, n3471, n3472,
n3473, n3474, n3475, n3476, n3477, n3478, n3479, n3480, n3481, n3482,
n3483, n3484, n3485, n3486, n3487, n3488, n3489, n3490, n3491, n3492,
n3493, n3494, n3495, n3496, n3497, n3498, n3499, n3500, n3501, n3502,
n3503, n3504, n3505, n3506, n3507, n3508, n3509, n3510, n3511, n3512,
n3513, n3514, n3515, n3516, n3517, n3518, n3519, n3520, n3521, n3522,
n3523, n3524, n3525, n3526, n3527, n3528, n3529, n3530, n3531, n3532,
n3533, n3534, n3535, n3536, n3537, n3538, n3539, n3540, n3541, n3542,
n3543, n3544, n3545, n3546, n3547, n3548, n3549, n3550, n3551, n3552,
n3553, n3554, n3555, n3556, n3557, n3558, n3559, n3560, n3561, n3562,
n3563, n3564, n3565, n3566, n3567, n3568, n3569, n3570, n3571, n3572,
n3573, n3574, n3575, n3576, n3577, n3578, n3579, n3580, n3581, n3582,
n3583, n3584, n3585, n3586, n3587, n3588, n3589, n3590, n3591, n3592,
n3593, n3594, n3595, n3596, n3597, n3598, n3599, n3600, n3601, n3602,
n3603, n3604, n3605, n3606, n3607, n3608, n3609, n3610, n3611, n3612,
n3613, n3614, n3615, n3616, n3617, n3618, n3619, n3620, n3621, n3622,
n3623, n3624, n3625, n3626, n3627, n3628, n3629, n3630, n3631, n3632,
n3633, n3634, n3635, n3636, n3637, n3638, n3639, n3640, n3641, n3642,
n3643, n3644, n3645, n3646, n3647, n3648, n3649, n3650, n3651, n3652,
n3653, n3654, n3655, n3656, n3657, n3658, n3659, n3660, n3661, n3662,
n3663, n3664, n3665, n3666, n3667, n3668, n3669, n3670, n3671, n3672,
n3673, n3674, n3675, n3676, n3677, n3678, n3679, n3680, n3681, n3682,
n3683, n3684, n3685, n3686, n3687, n3688, n3689, n3690, n3691, n3692,
n3693, n3694, n3695, n3696, n3697, n3698, n3699, n3700, n3701, n3702,
n3703, n3704, n3705, n3706, n3707, n3708, n3709, n3710, n3711, n3712,
n3713, n3714, n3715, n3716, n3717, n3718, n3719, n3720, n3721, n3722,
n3723, n3724, n3725, n3726, n3727, n3728, n3729, n3730, n3731, n3732,
n3733, n3734, n3735, n3736, n3737, n3738, n3739, n3740, n3741, n3742,
n3743, n3744, n3745, n3746, n3747, n3748, n3749, n3750, n3751, n3752,
n3753, n3754, n3755, n3756, n3757, n3758, n3759, n3760, n3761, n3762,
n3763, n3764, n3765, n3766, n3767, n3768, n3769, n3770, n3771, n3772,
n3773, n3774, n3775, n3776, n3777, n3778, n3779, n3780, n3781, n3782,
n3783, n3784, n3785, n3786, n3787, n3788, n3789, n3790, n3791, n3792,
n3793, n3794, n3795, n3796, n3797, n3798, n3799, n3800, n3801, n3802,
n3803, n3804, n3805, n3806, n3807, n3808, n3809, n3810, n3811, n3812,
n3813, n3814, n3815, n3816, n3817, n3818, n3819, n3820, n3821, n3822,
n3823, n3824, n3825, n3826, n3827, n3828, n3829, n3830, n3831, n3832,
n3833, n3834, n3835, n3836, n3837, n3838, n3839, n3840, n3841, n3842,
n3843, n3844, n3845, n3846, n3847, n3848, n3849, n3850, n3851, n3852,
n3853, n3854, n3855, n3856, n3857, n3858, n3859, n3860, n3861, n3862,
n3863, n3864, n3865, n3866, n3867, n3868, n3869, n3870, n3871, n3872,
n3873, n3874, n3875, n3876, n3877, n3878, n3879, n3880, n3881, n3882,
n3883, n3884, n3885, n3886, n3887, n3888, n3889, n3890, n3891, n3892,
n3893, n3894, n3895, n3896, n3897, n3898, n3899, n3900, n3901, n3902,
n3903, n3904, n3905, n3906, n3907, n3908, n3909, n3910, n3911, n3912,
n3913, n3914, n3915, n3916, n3917, n3918, n3919, n3920, n3921, n3922,
n3923, n3924, n3925, n3926, n3927, n3928, n3929, n3930, n3931, n3932,
n3933, n3934, n3935, n3936, n3937, n3938, n3939, n3940, n3941, n3942,
n3943, n3944, n3945, n3946, n3947, n3948, n3949, n3950, n3951, n3952,
n3953, n3954, n3955, n3956, n3957, n3958, n3959, n3960, n3961, n3962,
n3963, n3964, n3965, n3966, n3967, n3968, n3969, n3970, n3971, n3972,
n3973, n3974, n3975, n3976, n3977, n3978, n3979, n3980, n3981, n3982,
n3983, n3984, n3985, n3986, n3987, n3988, n3989, n3990, n3991, n3992,
n3993, n3994, n3995, n3996, n3997, n3998, n3999, n4000, n4001, n4002,
n4003, n4004, n4005, n4006, n4007, n4008, n4009, n4010, n4011, n4012,
n4013, n4014, n4015, n4016, n4017, n4018, n4019, n4020, n4021, n4022,
n4023, n4024, n4025, n4026, n4027, n4028, n4029, n4030, n4031, n4032,
n4033, n4034, n4035, n4036, n4037, n4038, n4039, n4040, n4041, n4042,
n4043, n4044, n4045, n4046, n4047, n4048, n4049, n4050, n4051, n4052,
n4053, n4054, n4055, n4056, n4057, n4058, n4059, n4060, n4061, n4062,
n4063, n4064, n4065, n4066, n4067, n4068, n4069, n4070, n4071, n4072,
n4073, n4074, n4075, n4076, n4077, n4078, n4079, n4080, n4081, n4082,
n4083, n4084, n4085, n4086, n4087, n4088, n4089, n4090, n4091, n4092,
n4093, n4094, n4095, n4096, n4097, n4098, n4099, n4100, n4101, n4102,
n4103, n4104, n4105, n4106, n4107, n4108, n4109, n4110, n4111, n4112,
n4113, n4114, n4115, n4116, n4117, n4118, n4119, n4120, n4121, n4122,
n4123, n4124, n4125, n4126, n4127, n4128, n4129, n4130, n4131, n4132,
n4133, n4134, n4135, n4136, n4137, n4138, n4139, n4140, n4141, n4142,
n4143, n4144, n4145, n4146, n4147, n4148, n4149, n4150, n4151, n4152,
n4153, n4154, n4155, n4156, n4157, n4158, n4159, n4160, n4161, n4162,
n4163, n4164, n4165, n4166, n4167, n4168, n4169, n4170, n4171, n4172,
n4173, n4174, n4175, n4176, n4177, n4178, n4179, n4180, n4181, n4182,
n4183, n4184, n4185, n4186, n4187, n4188, n4189, n4190, n4191, n4192,
n4193, n4194, n4195, n4196, n4197, n4198, n4199, n4200, n4201, n4202,
n4203, n4204, n4205, n4206, n4207, n4208, n4209, n4210, n4211, n4212,
n4213, n4214, n4215, n4216, n4217, n4218, n4219, n4220, n4221, n4222,
n4223, n4224, n4225, n4226, n4227, n4228, n4229, n4230, n4231, n4232,
n4233, n4234, n4235, n4236, n4237, n4238, n4239, n4240, n4241, n4242,
n4243, n4244, n4245, n4246, n4247, n4248, n4249, n4250, n4251, n4252,
n4253, n4254, n4255, n4256, n4257, n4258, n4259, n4260, n4261, n4262,
n4263, n4264, n4265, n4266, n4267, n4268, n4269, n4270, n4271, n4272,
n4273, n4274, n4275, n4276, n4277, n4278, n4279, n4280, n4281, n4282,
n4283, n4284, n4285, n4286, n4287, n4288, n4289, n4290, n4291, n4292,
n4293, n4294, n4295, n4296, n4297, n4298, n4299, n4300, n4301, n4302,
n4303, n4304, n4305, n4306, n4307, n4308, n4309, n4310, n4311, n4312,
n4313, n4314, n4315, n4316, n4317, n4318, n4319, n4320, n4321, n4322,
n4323, n4324, n4325, n4326, n4327, n4328, n4329, n4330, n4331, n4332,
n4333, n4334, n4335, n4336, n4337, n4338, n4339, n4340, n4341, n4342,
n4343, n4344, n4345, n4346, n4347, n4348, n4349, n4350, n4351, n4352,
n4353, n4354, n4355, n4356, n4357, n4358, n4359, n4360, n4361, n4362,
n4363, n4364, n4365, n4366, n4367, n4368, n4369, n4370, n4371, n4372,
n4373, n4374, n4375, n4376, n4377, n4378, n4379, n4380, n4381, n4382,
n4383, n4384, n4385, n4386, n4387, n4388, n4389, n4390, n4391, n4392,
n4393, n4394, n4395, n4396, n4397, n4398, n4399, n4400, n4401, n4402,
n4403, n4404, n4405, n4406, n4407, n4408, n4409, n4410, n4411, n4412,
n4413, n4414, n4415, n4416, n4417, n4418, n4419, n4420, n4421, n4422,
n4423, n4424, n4425, n4426, n4427, n4428, n4429, n4430, n4431, n4432,
n4433, n4434, n4435, n4436, n4437, n4438, n4439, n4440, n4441, n4442,
n4443, n4444, n4445, n4446, n4447, n4448, n4449, n4450, n4451, n4452,
n4453, n4454, n4455, n4456, n4457, n4458, n4459, n4460, n4461, n4462,
n4463, n4464, n4465, n4466, n4467, n4468, n4469, n4470, n4471, n4472,
n4473, n4474, n4475, n4476, n4477, n4478, n4479, n4480, n4481, n4482,
n4483, n4484, n4485, n4486, n4487, n4488, n4489, n4490, n4491, n4492,
n4493, n4494, n4495, n4496, n4497, n4498, n4499, n4500, n4501, n4502,
n4503, n4504, n4505, n4506, n4507, n4508, n4509, n4510, n4511, n4512,
n4513, n4514, n4515, n4516, n4517, n4518, n4519, n4520, n4521, n4522,
n4523, n4524, n4525, n4526, n4527, n4528, n4529, n4530, n4531, n4532,
n4533, n4534, n4535, n4536, n4537, n4538, n4539, n4540, n4541, n4542,
n4543, n4544, n4545, n4546, n4547, n4548, n4549, n4550, n4551, n4552,
n4553, n4554, n4555, n4556, n4557, n4558, n4559, n4560, n4561, n4562,
n4563, n4564, n4565, n4566, n4567, n4568, n4569, n4570, n4571, n4572,
n4573, n4574, n4575, n4576, n4577, n4578, n4579, n4580, n4581, n4582,
n4583, n4584, n4585, n4586, n4587, n4588, n4589, n4590, n4591, n4592,
n4593, n4594, n4595, n4596, n4597, n4598, n4599, n4600, n4601, n4602,
n4603, n4604, n4605, n4606, n4607, n4608, n4609, n4610, n4611, n4612,
n4613, n4614, n4615, n4616, n4617, n4618, n4619, n4620, n4621, n4622,
n4623, n4624, n4625, n4626, n4627, n4628, n4629, n4630, n4631, n4632,
n4633, n4634, n4635, n4636, n4637, n4638, n4639, n4640, n4641, n4642,
n4643, n4644, n4645, n4646, n4647, n4648, n4649, n4650, n4651, n4652,
n4653, n4654, n4655, n4656, n4657, n4658, n4659, n4660, n4661, n4662,
n4663, n4664, n4665, n4666, n4667, n4668, n4669, n4670, n4671, n4672,
n4673, n4674, n4675, n4676, n4677, n4678, n4679, n4680, n4681, n4682,
n4683, n4684, n4685, n4686, n4687, n4688, n4689, n4690, n4691, n4692,
n4693, n4694, n4695, n4696, n4697, n4698, n4699, n4700, n4701, n4702,
n4703, n4704, n4705, n4706, n4707, n4708, n4709, n4710, n4711, n4712,
n4713, n4714, n4715, n4716, n4717, n4718, n4719, n4720, n4721, n4722,
n4723, n4724, n4725, n4726, n4727, n4728, n4729, n4730, n4731, n4732,
n4733, n4734, n4735, n4736, n4737, n4738, n4739, n4740, n4741, n4742,
n4743, n4744, n4745, n4746, n4747, n4748, n4749, n4750, n4751, n4752,
n4753, n4754, n4755, n4756, n4757, n4758, n4759, n4760, n4761, n4762,
n4763, n4764, n4765, n4766, n4767, n4768, n4769, n4770, n4771, n4772,
n4773, n4774, n4775, n4776, n4777, n4778, n4779, n4780, n4781, n4782,
n4783, n4784, n4785, n4786, n4787, n4788, n4789, n4790, n4791, n4792,
n4793, n4794, n4795, n4796, n4797, n4798, n4799, n4800, n4801, n4802,
n4803, n4804, n4805, n4806, n4807, n4808, n4809, n4810, n4811, n4812,
n4813, n4814, n4815, n4816, n4817, n4818, n4819, n4820, n4821, n4822,
n4823, n4824, n4825, n4826, n4827, n4828, n4829, n4830, n4831, n4832,
n4833, n4834, n4835, n4836, n4837, n4838, n4839, n4840, n4841, n4842,
n4843, n4844, n4845, n4846, n4847, n4848, n4849, n4850, n4851, n4852,
n4853, n4854, n4855, n4856, n4857, n4858, n4859, n4860, n4861, n4862,
n4863, n4864, n4865, n4866, n4867, n4868, n4869, n4870, n4871, n4872,
n4873, n4874, n4875, n4876, n4877, n4878, n4879, n4880, n4881, n4882,
n4883, n4884, n4885, n4886, n4887, n4888, n4889, n4890, n4891, n4892,
n4893, n4894, n4895, n4896, n4897, n4898, n4899, n4900, n4901, n4902,
n4903, n4904, n4905, n4906, n4907, n4908, n4909, n4910, n4911, n4912,
n4913, n4914, n4915, n4916, n4917, n4918, n4919, n4920, n4921, n4922,
n4923, n4924, n4925, n4926, n4927, n4928, n4929, n4930, n4931, n4932,
n4933, n4934, n4935, n4936, n4937, n4938, n4939, n4940, n4941, n4942,
n4943, n4944, n4945, n4946, n4947, n4948, n4949, n4950, n4951, n4952,
n4953, n4954, n4955, n4956, n4957, n4958, n4959, n4960, n4961, n4962,
n4963, n4964, n4965, n4966, n4967, n4968, n4969, n4970, n4971, n4972,
n4973, n4974, n4975, n4976, n4977, n4978, n4979, n4980, n4981, n4982,
n4983, SYNOPSYS_UNCONNECTED_1;
wire [51:0] Q_left;
wire [53:0] Q_right;
wire [55:0] Q_middle;
wire [55:0] S_A;
wire [55:0] S_B;
wire [105:0] Result;
substractor_W56_1 genblk1_Subtr_1 ( .Data_A_i(Q_middle), .Data_B_i({1'b0,
1'b0, 1'b0, 1'b0, Q_left}), .Data_S_o(S_A) );
substractor_W56_0 genblk1_Subtr_2 ( .Data_A_i(S_A), .Data_B_i({1'b0, 1'b0,
Q_right}), .Data_S_o(S_B) );
adder genblk1_Final ( .Data_A_i({Q_left, Q_right}), .Data_B_i({S_B, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0}), .Data_S_o({SYNOPSYS_UNCONNECTED_1, Result}) );
RegisterAdd genblk1_finalreg ( .clk(clk), .rst(rst), .load(load_b_i), .D(
Result), .Q(sgf_result_o) );
DFFQX1TS genblk1_middle_pdt_int_reg_0_ ( .D(genblk1_middle_N0), .CK(clk),
.Q(Q_middle[0]) );
DFFQX1TS genblk1_middle_pdt_int_reg_1_ ( .D(genblk1_middle_N1), .CK(clk),
.Q(Q_middle[1]) );
DFFQX1TS genblk1_middle_pdt_int_reg_2_ ( .D(genblk1_middle_N2), .CK(clk),
.Q(Q_middle[2]) );
DFFQX1TS genblk1_middle_pdt_int_reg_3_ ( .D(genblk1_middle_N3), .CK(clk),
.Q(Q_middle[3]) );
DFFQX1TS genblk1_middle_pdt_int_reg_4_ ( .D(genblk1_middle_N4), .CK(clk),
.Q(Q_middle[4]) );
DFFQX1TS genblk1_middle_pdt_int_reg_5_ ( .D(genblk1_middle_N5), .CK(clk),
.Q(Q_middle[5]) );
DFFQX1TS genblk1_middle_pdt_int_reg_6_ ( .D(genblk1_middle_N6), .CK(clk),
.Q(Q_middle[6]) );
DFFQX1TS genblk1_middle_pdt_int_reg_7_ ( .D(genblk1_middle_N7), .CK(clk),
.Q(Q_middle[7]) );
DFFQX1TS genblk1_middle_pdt_int_reg_8_ ( .D(genblk1_middle_N8), .CK(clk),
.Q(Q_middle[8]) );
DFFQX1TS genblk1_middle_pdt_int_reg_9_ ( .D(genblk1_middle_N9), .CK(clk),
.Q(Q_middle[9]) );
DFFQX1TS genblk1_middle_pdt_int_reg_10_ ( .D(genblk1_middle_N10), .CK(clk),
.Q(Q_middle[10]) );
DFFQX1TS genblk1_middle_pdt_int_reg_11_ ( .D(genblk1_middle_N11), .CK(clk),
.Q(Q_middle[11]) );
DFFQX1TS genblk1_middle_pdt_int_reg_12_ ( .D(genblk1_middle_N12), .CK(clk),
.Q(Q_middle[12]) );
DFFQX1TS genblk1_middle_pdt_int_reg_13_ ( .D(genblk1_middle_N13), .CK(clk),
.Q(Q_middle[13]) );
DFFQX1TS genblk1_middle_pdt_int_reg_14_ ( .D(genblk1_middle_N14), .CK(clk),
.Q(Q_middle[14]) );
DFFQX1TS genblk1_middle_pdt_int_reg_15_ ( .D(genblk1_middle_N15), .CK(clk),
.Q(Q_middle[15]) );
DFFQX1TS genblk1_middle_pdt_int_reg_16_ ( .D(genblk1_middle_N16), .CK(clk),
.Q(Q_middle[16]) );
DFFQX1TS genblk1_middle_pdt_int_reg_17_ ( .D(genblk1_middle_N17), .CK(clk),
.Q(Q_middle[17]) );
DFFQX1TS genblk1_middle_pdt_int_reg_18_ ( .D(genblk1_middle_N18), .CK(clk),
.Q(Q_middle[18]) );
DFFQX1TS genblk1_middle_pdt_int_reg_19_ ( .D(genblk1_middle_N19), .CK(clk),
.Q(Q_middle[19]) );
DFFQX1TS genblk1_middle_pdt_int_reg_20_ ( .D(genblk1_middle_N20), .CK(clk),
.Q(Q_middle[20]) );
DFFQX1TS genblk1_middle_pdt_int_reg_21_ ( .D(genblk1_middle_N21), .CK(clk),
.Q(Q_middle[21]) );
DFFQX1TS genblk1_middle_pdt_int_reg_22_ ( .D(genblk1_middle_N22), .CK(clk),
.Q(Q_middle[22]) );
DFFQX1TS genblk1_middle_pdt_int_reg_23_ ( .D(genblk1_middle_N23), .CK(clk),
.Q(Q_middle[23]) );
DFFQX1TS genblk1_middle_pdt_int_reg_24_ ( .D(genblk1_middle_N24), .CK(clk),
.Q(Q_middle[24]) );
DFFQX1TS genblk1_middle_pdt_int_reg_25_ ( .D(genblk1_middle_N25), .CK(clk),
.Q(Q_middle[25]) );
DFFQX1TS genblk1_middle_pdt_int_reg_26_ ( .D(genblk1_middle_N26), .CK(clk),
.Q(Q_middle[26]) );
DFFQX1TS genblk1_middle_pdt_int_reg_27_ ( .D(genblk1_middle_N27), .CK(clk),
.Q(Q_middle[27]) );
DFFQX1TS genblk1_middle_pdt_int_reg_28_ ( .D(genblk1_middle_N28), .CK(clk),
.Q(Q_middle[28]) );
DFFQX1TS genblk1_middle_pdt_int_reg_29_ ( .D(genblk1_middle_N29), .CK(clk),
.Q(Q_middle[29]) );
DFFQX1TS genblk1_middle_pdt_int_reg_30_ ( .D(genblk1_middle_N30), .CK(clk),
.Q(Q_middle[30]) );
DFFQX1TS genblk1_middle_pdt_int_reg_31_ ( .D(genblk1_middle_N31), .CK(clk),
.Q(Q_middle[31]) );
DFFQX1TS genblk1_middle_pdt_int_reg_32_ ( .D(genblk1_middle_N32), .CK(clk),
.Q(Q_middle[32]) );
DFFQX1TS genblk1_middle_pdt_int_reg_33_ ( .D(genblk1_middle_N33), .CK(clk),
.Q(Q_middle[33]) );
DFFQX1TS genblk1_middle_pdt_int_reg_34_ ( .D(genblk1_middle_N34), .CK(clk),
.Q(Q_middle[34]) );
DFFQX1TS genblk1_middle_pdt_int_reg_35_ ( .D(genblk1_middle_N35), .CK(clk),
.Q(Q_middle[35]) );
DFFQX1TS genblk1_middle_pdt_int_reg_36_ ( .D(genblk1_middle_N36), .CK(clk),
.Q(Q_middle[36]) );
DFFQX1TS genblk1_middle_pdt_int_reg_37_ ( .D(genblk1_middle_N37), .CK(clk),
.Q(Q_middle[37]) );
DFFQX1TS genblk1_middle_pdt_int_reg_38_ ( .D(genblk1_middle_N38), .CK(clk),
.Q(Q_middle[38]) );
DFFQX1TS genblk1_middle_pdt_int_reg_40_ ( .D(genblk1_middle_N40), .CK(clk),
.Q(Q_middle[40]) );
DFFQX1TS genblk1_middle_pdt_int_reg_42_ ( .D(genblk1_middle_N42), .CK(clk),
.Q(Q_middle[42]) );
DFFQX1TS genblk1_middle_pdt_int_reg_43_ ( .D(genblk1_middle_N43), .CK(clk),
.Q(Q_middle[43]) );
DFFQX1TS genblk1_middle_pdt_int_reg_44_ ( .D(genblk1_middle_N44), .CK(clk),
.Q(Q_middle[44]) );
DFFQX1TS genblk1_middle_pdt_int_reg_45_ ( .D(genblk1_middle_N45), .CK(clk),
.Q(Q_middle[45]) );
DFFQX1TS genblk1_middle_pdt_int_reg_46_ ( .D(genblk1_middle_N46), .CK(clk),
.Q(Q_middle[46]) );
DFFQX1TS genblk1_middle_pdt_int_reg_48_ ( .D(genblk1_middle_N48), .CK(clk),
.Q(Q_middle[48]) );
DFFQX1TS genblk1_middle_pdt_int_reg_50_ ( .D(genblk1_middle_N50), .CK(clk),
.Q(Q_middle[50]) );
DFFQX1TS genblk1_middle_pdt_int_reg_54_ ( .D(genblk1_middle_N54), .CK(clk),
.Q(Q_middle[54]) );
DFFQX1TS genblk1_right_pdt_int_reg_0_ ( .D(genblk1_right_N0), .CK(clk), .Q(
Q_right[0]) );
DFFQX1TS genblk1_right_pdt_int_reg_1_ ( .D(genblk1_right_N1), .CK(clk), .Q(
Q_right[1]) );
DFFQX1TS genblk1_right_pdt_int_reg_2_ ( .D(genblk1_right_N2), .CK(clk), .Q(
Q_right[2]) );
DFFQX1TS genblk1_right_pdt_int_reg_3_ ( .D(genblk1_right_N3), .CK(clk), .Q(
Q_right[3]) );
DFFQX1TS genblk1_right_pdt_int_reg_4_ ( .D(genblk1_right_N4), .CK(clk), .Q(
Q_right[4]) );
DFFQX1TS genblk1_right_pdt_int_reg_5_ ( .D(genblk1_right_N5), .CK(clk), .Q(
Q_right[5]) );
DFFQX1TS genblk1_right_pdt_int_reg_6_ ( .D(genblk1_right_N6), .CK(clk), .Q(
Q_right[6]) );
DFFQX1TS genblk1_right_pdt_int_reg_7_ ( .D(genblk1_right_N7), .CK(clk), .Q(
Q_right[7]) );
DFFQX1TS genblk1_right_pdt_int_reg_8_ ( .D(genblk1_right_N8), .CK(clk), .Q(
Q_right[8]) );
DFFQX1TS genblk1_right_pdt_int_reg_9_ ( .D(genblk1_right_N9), .CK(clk), .Q(
Q_right[9]) );
DFFQX1TS genblk1_right_pdt_int_reg_10_ ( .D(genblk1_right_N10), .CK(clk),
.Q(Q_right[10]) );
DFFQX1TS genblk1_right_pdt_int_reg_11_ ( .D(genblk1_right_N11), .CK(clk),
.Q(Q_right[11]) );
DFFQX1TS genblk1_right_pdt_int_reg_12_ ( .D(genblk1_right_N12), .CK(clk),
.Q(Q_right[12]) );
DFFQX1TS genblk1_right_pdt_int_reg_13_ ( .D(genblk1_right_N13), .CK(clk),
.Q(Q_right[13]) );
DFFQX1TS genblk1_right_pdt_int_reg_14_ ( .D(genblk1_right_N14), .CK(clk),
.Q(Q_right[14]) );
DFFQX1TS genblk1_right_pdt_int_reg_15_ ( .D(genblk1_right_N15), .CK(clk),
.Q(Q_right[15]) );
DFFQX1TS genblk1_right_pdt_int_reg_16_ ( .D(genblk1_right_N16), .CK(clk),
.Q(Q_right[16]) );
DFFQX1TS genblk1_right_pdt_int_reg_17_ ( .D(genblk1_right_N17), .CK(clk),
.Q(Q_right[17]) );
DFFQX1TS genblk1_right_pdt_int_reg_18_ ( .D(genblk1_right_N18), .CK(clk),
.Q(Q_right[18]) );
DFFQX1TS genblk1_right_pdt_int_reg_19_ ( .D(genblk1_right_N19), .CK(clk),
.Q(Q_right[19]) );
DFFQX1TS genblk1_right_pdt_int_reg_20_ ( .D(genblk1_right_N20), .CK(clk),
.Q(Q_right[20]) );
DFFQX1TS genblk1_right_pdt_int_reg_21_ ( .D(genblk1_right_N21), .CK(clk),
.Q(Q_right[21]) );
DFFQX1TS genblk1_right_pdt_int_reg_22_ ( .D(genblk1_right_N22), .CK(clk),
.Q(Q_right[22]) );
DFFQX1TS genblk1_right_pdt_int_reg_23_ ( .D(genblk1_right_N23), .CK(clk),
.Q(Q_right[23]) );
DFFQX1TS genblk1_right_pdt_int_reg_24_ ( .D(genblk1_right_N24), .CK(clk),
.Q(Q_right[24]) );
DFFQX1TS genblk1_right_pdt_int_reg_25_ ( .D(genblk1_right_N25), .CK(clk),
.Q(Q_right[25]) );
DFFQX1TS genblk1_right_pdt_int_reg_26_ ( .D(genblk1_right_N26), .CK(clk),
.Q(Q_right[26]) );
DFFQX1TS genblk1_right_pdt_int_reg_27_ ( .D(genblk1_right_N27), .CK(clk),
.Q(Q_right[27]) );
DFFQX1TS genblk1_right_pdt_int_reg_28_ ( .D(genblk1_right_N28), .CK(clk),
.Q(Q_right[28]) );
DFFQX1TS genblk1_right_pdt_int_reg_29_ ( .D(genblk1_right_N29), .CK(clk),
.Q(Q_right[29]) );
DFFQX1TS genblk1_right_pdt_int_reg_30_ ( .D(genblk1_right_N30), .CK(clk),
.Q(Q_right[30]) );
DFFQX1TS genblk1_right_pdt_int_reg_31_ ( .D(genblk1_right_N31), .CK(clk),
.Q(Q_right[31]) );
DFFQX1TS genblk1_right_pdt_int_reg_32_ ( .D(genblk1_right_N32), .CK(clk),
.Q(Q_right[32]) );
DFFQX1TS genblk1_right_pdt_int_reg_33_ ( .D(genblk1_right_N33), .CK(clk),
.Q(Q_right[33]) );
DFFQX1TS genblk1_right_pdt_int_reg_34_ ( .D(genblk1_right_N34), .CK(clk),
.Q(Q_right[34]) );
DFFQX1TS genblk1_right_pdt_int_reg_35_ ( .D(genblk1_right_N35), .CK(clk),
.Q(Q_right[35]) );
DFFQX1TS genblk1_right_pdt_int_reg_36_ ( .D(genblk1_right_N36), .CK(clk),
.Q(Q_right[36]) );
DFFQX1TS genblk1_right_pdt_int_reg_37_ ( .D(genblk1_right_N37), .CK(clk),
.Q(Q_right[37]) );
DFFQX1TS genblk1_right_pdt_int_reg_38_ ( .D(genblk1_right_N38), .CK(clk),
.Q(Q_right[38]) );
DFFQX1TS genblk1_right_pdt_int_reg_39_ ( .D(genblk1_right_N39), .CK(clk),
.Q(Q_right[39]) );
DFFQX1TS genblk1_right_pdt_int_reg_40_ ( .D(genblk1_right_N40), .CK(clk),
.Q(Q_right[40]) );
DFFQX1TS genblk1_right_pdt_int_reg_41_ ( .D(genblk1_right_N41), .CK(clk),
.Q(Q_right[41]) );
DFFQX1TS genblk1_right_pdt_int_reg_42_ ( .D(genblk1_right_N42), .CK(clk),
.Q(Q_right[42]) );
DFFQX1TS genblk1_right_pdt_int_reg_43_ ( .D(genblk1_right_N43), .CK(clk),
.Q(Q_right[43]) );
DFFQX1TS genblk1_right_pdt_int_reg_44_ ( .D(genblk1_right_N44), .CK(clk),
.Q(Q_right[44]) );
DFFQX1TS genblk1_right_pdt_int_reg_45_ ( .D(genblk1_right_N45), .CK(clk),
.Q(Q_right[45]) );
DFFQX1TS genblk1_right_pdt_int_reg_46_ ( .D(genblk1_right_N46), .CK(clk),
.Q(Q_right[46]) );
DFFQX1TS genblk1_right_pdt_int_reg_47_ ( .D(genblk1_right_N47), .CK(clk),
.Q(Q_right[47]) );
DFFQX1TS genblk1_right_pdt_int_reg_48_ ( .D(genblk1_right_N48), .CK(clk),
.Q(Q_right[48]) );
DFFQX1TS genblk1_right_pdt_int_reg_49_ ( .D(genblk1_right_N49), .CK(clk),
.Q(Q_right[49]) );
DFFQX1TS genblk1_right_pdt_int_reg_50_ ( .D(genblk1_right_N50), .CK(clk),
.Q(Q_right[50]) );
DFFQX1TS genblk1_right_pdt_int_reg_51_ ( .D(genblk1_right_N51), .CK(clk),
.Q(Q_right[51]) );
DFFQX1TS genblk1_right_pdt_int_reg_52_ ( .D(genblk1_right_N52), .CK(clk),
.Q(Q_right[52]) );
DFFQX1TS genblk1_right_pdt_int_reg_53_ ( .D(genblk1_right_N53), .CK(clk),
.Q(Q_right[53]) );
DFFQX1TS genblk1_left_pdt_int_reg_0_ ( .D(genblk1_left_mult_x_1_n1787), .CK(
clk), .Q(Q_left[0]) );
DFFQX1TS genblk1_left_pdt_int_reg_1_ ( .D(genblk1_left_N1), .CK(clk), .Q(
Q_left[1]) );
DFFQX1TS genblk1_left_pdt_int_reg_2_ ( .D(genblk1_left_N2), .CK(clk), .Q(
Q_left[2]) );
DFFQX1TS genblk1_left_pdt_int_reg_3_ ( .D(genblk1_left_N3), .CK(clk), .Q(
Q_left[3]) );
DFFQX1TS genblk1_left_pdt_int_reg_4_ ( .D(genblk1_left_N4), .CK(clk), .Q(
Q_left[4]) );
DFFQX1TS genblk1_left_pdt_int_reg_5_ ( .D(genblk1_left_N5), .CK(clk), .Q(
Q_left[5]) );
DFFQX1TS genblk1_left_pdt_int_reg_6_ ( .D(genblk1_left_N6), .CK(clk), .Q(
Q_left[6]) );
DFFQX1TS genblk1_left_pdt_int_reg_7_ ( .D(genblk1_left_N7), .CK(clk), .Q(
Q_left[7]) );
DFFQX1TS genblk1_left_pdt_int_reg_8_ ( .D(genblk1_left_N8), .CK(clk), .Q(
Q_left[8]) );
DFFQX1TS genblk1_left_pdt_int_reg_9_ ( .D(genblk1_left_N9), .CK(clk), .Q(
Q_left[9]) );
DFFQX1TS genblk1_left_pdt_int_reg_10_ ( .D(genblk1_left_N10), .CK(clk), .Q(
Q_left[10]) );
DFFQX1TS genblk1_left_pdt_int_reg_11_ ( .D(genblk1_left_N11), .CK(clk), .Q(
Q_left[11]) );
DFFQX1TS genblk1_left_pdt_int_reg_12_ ( .D(genblk1_left_N12), .CK(clk), .Q(
Q_left[12]) );
DFFQX1TS genblk1_left_pdt_int_reg_13_ ( .D(genblk1_left_N13), .CK(clk), .Q(
Q_left[13]) );
DFFQX1TS genblk1_left_pdt_int_reg_14_ ( .D(genblk1_left_N14), .CK(clk), .Q(
Q_left[14]) );
DFFQX1TS genblk1_left_pdt_int_reg_15_ ( .D(genblk1_left_N15), .CK(clk), .Q(
Q_left[15]) );
DFFQX1TS genblk1_left_pdt_int_reg_16_ ( .D(genblk1_left_N16), .CK(clk), .Q(
Q_left[16]) );
DFFQX1TS genblk1_left_pdt_int_reg_17_ ( .D(genblk1_left_N17), .CK(clk), .Q(
Q_left[17]) );
DFFQX1TS genblk1_left_pdt_int_reg_18_ ( .D(genblk1_left_N18), .CK(clk), .Q(
Q_left[18]) );
DFFQX1TS genblk1_left_pdt_int_reg_19_ ( .D(genblk1_left_N19), .CK(clk), .Q(
Q_left[19]) );
DFFQX1TS genblk1_left_pdt_int_reg_20_ ( .D(genblk1_left_N20), .CK(clk), .Q(
Q_left[20]) );
DFFQX1TS genblk1_left_pdt_int_reg_21_ ( .D(genblk1_left_N21), .CK(clk), .Q(
Q_left[21]) );
DFFQX1TS genblk1_left_pdt_int_reg_22_ ( .D(genblk1_left_N22), .CK(clk), .Q(
Q_left[22]) );
DFFQX1TS genblk1_left_pdt_int_reg_23_ ( .D(genblk1_left_N23), .CK(clk), .Q(
Q_left[23]) );
DFFQX1TS genblk1_left_pdt_int_reg_24_ ( .D(genblk1_left_N24), .CK(clk), .Q(
Q_left[24]) );
DFFQX1TS genblk1_left_pdt_int_reg_25_ ( .D(genblk1_left_N25), .CK(clk), .Q(
Q_left[25]) );
DFFQX1TS genblk1_left_pdt_int_reg_26_ ( .D(genblk1_left_N26), .CK(clk), .Q(
Q_left[26]) );
DFFQX1TS genblk1_left_pdt_int_reg_27_ ( .D(genblk1_left_N27), .CK(clk), .Q(
Q_left[27]) );
DFFQX1TS genblk1_left_pdt_int_reg_28_ ( .D(genblk1_left_N28), .CK(clk), .Q(
Q_left[28]) );
DFFQX1TS genblk1_left_pdt_int_reg_29_ ( .D(genblk1_left_N29), .CK(clk), .Q(
Q_left[29]) );
DFFQX1TS genblk1_left_pdt_int_reg_30_ ( .D(genblk1_left_N30), .CK(clk), .Q(
Q_left[30]) );
DFFQX1TS genblk1_left_pdt_int_reg_31_ ( .D(genblk1_left_N31), .CK(clk), .Q(
Q_left[31]) );
DFFQX1TS genblk1_left_pdt_int_reg_32_ ( .D(genblk1_left_N32), .CK(clk), .Q(
Q_left[32]) );
DFFQX1TS genblk1_left_pdt_int_reg_33_ ( .D(genblk1_left_N33), .CK(clk), .Q(
Q_left[33]) );
DFFQX1TS genblk1_left_pdt_int_reg_34_ ( .D(genblk1_left_N34), .CK(clk), .Q(
Q_left[34]) );
DFFQX1TS genblk1_left_pdt_int_reg_35_ ( .D(genblk1_left_N35), .CK(clk), .Q(
Q_left[35]) );
DFFQX1TS genblk1_left_pdt_int_reg_36_ ( .D(genblk1_left_N36), .CK(clk), .Q(
Q_left[36]) );
DFFQX1TS genblk1_left_pdt_int_reg_37_ ( .D(genblk1_left_N37), .CK(clk), .Q(
Q_left[37]) );
DFFQX1TS genblk1_left_pdt_int_reg_38_ ( .D(genblk1_left_N38), .CK(clk), .Q(
Q_left[38]) );
DFFQX1TS genblk1_left_pdt_int_reg_39_ ( .D(genblk1_left_N39), .CK(clk), .Q(
Q_left[39]) );
DFFQX1TS genblk1_left_pdt_int_reg_40_ ( .D(genblk1_left_N40), .CK(clk), .Q(
Q_left[40]) );
DFFQX1TS genblk1_left_pdt_int_reg_41_ ( .D(genblk1_left_N41), .CK(clk), .Q(
Q_left[41]) );
DFFQX1TS genblk1_left_pdt_int_reg_42_ ( .D(genblk1_left_N42), .CK(clk), .Q(
Q_left[42]) );
DFFQX1TS genblk1_left_pdt_int_reg_43_ ( .D(genblk1_left_N43), .CK(clk), .Q(
Q_left[43]) );
DFFQX1TS genblk1_left_pdt_int_reg_44_ ( .D(genblk1_left_N44), .CK(clk), .Q(
Q_left[44]) );
DFFQX1TS genblk1_left_pdt_int_reg_45_ ( .D(genblk1_left_N45), .CK(clk), .Q(
Q_left[45]) );
DFFQX1TS genblk1_left_pdt_int_reg_46_ ( .D(genblk1_left_N46), .CK(clk), .Q(
Q_left[46]) );
DFFQX1TS genblk1_left_pdt_int_reg_47_ ( .D(genblk1_left_N47), .CK(clk), .Q(
Q_left[47]) );
DFFQX1TS genblk1_left_pdt_int_reg_48_ ( .D(genblk1_left_N48), .CK(clk), .Q(
Q_left[48]) );
DFFQX1TS genblk1_left_pdt_int_reg_49_ ( .D(genblk1_left_N49), .CK(clk), .Q(
Q_left[49]) );
DFFQX1TS genblk1_left_pdt_int_reg_50_ ( .D(genblk1_left_N50), .CK(clk), .Q(
Q_left[50]) );
CMPR42X1TS genblk1_left_mult_x_1_U646 ( .A(genblk1_left_mult_x_1_n802), .B(
genblk1_left_mult_x_1_n1278), .C(genblk1_left_mult_x_1_n1330), .D(
genblk1_left_mult_x_1_n1304), .ICI(genblk1_left_mult_x_1_n803), .S(
genblk1_left_mult_x_1_n800), .ICO(genblk1_left_mult_x_1_n798), .CO(
genblk1_left_mult_x_1_n799) );
CMPR42X1TS genblk1_left_mult_x_1_U644 ( .A(genblk1_left_mult_x_1_n797), .B(
genblk1_left_mult_x_1_n1303), .C(genblk1_left_mult_x_1_n1277), .D(
genblk1_left_mult_x_1_n1329), .ICI(genblk1_left_mult_x_1_n798), .S(
genblk1_left_mult_x_1_n795), .ICO(genblk1_left_mult_x_1_n793), .CO(
genblk1_left_mult_x_1_n794) );
CMPR42X1TS genblk1_left_mult_x_1_U641 ( .A(genblk1_left_mult_x_1_n1276), .B(
genblk1_left_mult_x_1_n1328), .C(genblk1_left_mult_x_1_n1302), .D(
genblk1_left_mult_x_1_n790), .ICI(genblk1_left_mult_x_1_n793), .S(
genblk1_left_mult_x_1_n788), .ICO(genblk1_left_mult_x_1_n786), .CO(
genblk1_left_mult_x_1_n787) );
CMPR42X1TS genblk1_left_mult_x_1_U638 ( .A(genblk1_left_mult_x_1_n1275), .B(
genblk1_left_mult_x_1_n789), .C(genblk1_left_mult_x_1_n1327), .D(
genblk1_left_mult_x_1_n786), .ICI(genblk1_left_mult_x_1_n783), .S(
genblk1_left_mult_x_1_n781), .ICO(genblk1_left_mult_x_1_n779), .CO(
genblk1_left_mult_x_1_n780) );
CMPR42X1TS genblk1_left_mult_x_1_U633 ( .A(genblk1_left_mult_x_1_n771), .B(
genblk1_left_mult_x_1_n1221), .C(genblk1_left_mult_x_1_n777), .D(
genblk1_left_mult_x_1_n1247), .ICI(genblk1_left_mult_x_1_n1273), .S(
genblk1_left_mult_x_1_n769), .ICO(genblk1_left_mult_x_1_n767), .CO(
genblk1_left_mult_x_1_n768) );
CMPR42X2TS genblk1_left_mult_x_1_U632 ( .A(genblk1_left_mult_x_1_n1299), .B(
genblk1_left_mult_x_1_n1325), .C(genblk1_left_mult_x_1_n775), .D(
genblk1_left_mult_x_1_n772), .ICI(genblk1_left_mult_x_1_n769), .S(
genblk1_left_mult_x_1_n766), .ICO(genblk1_left_mult_x_1_n764), .CO(
genblk1_left_mult_x_1_n765) );
CMPR42X1TS genblk1_left_mult_x_1_U630 ( .A(genblk1_left_mult_x_1_n763), .B(
genblk1_left_mult_x_1_n1220), .C(genblk1_left_mult_x_1_n1272), .D(
genblk1_left_mult_x_1_n1324), .ICI(genblk1_left_mult_x_1_n1298), .S(
genblk1_left_mult_x_1_n761), .ICO(genblk1_left_mult_x_1_n759), .CO(
genblk1_left_mult_x_1_n760) );
CMPR42X1TS genblk1_left_mult_x_1_U627 ( .A(genblk1_left_mult_x_1_n755), .B(
genblk1_left_mult_x_1_n1245), .C(genblk1_left_mult_x_1_n1219), .D(
genblk1_left_mult_x_1_n1297), .ICI(genblk1_left_mult_x_1_n759), .S(
genblk1_left_mult_x_1_n753), .ICO(genblk1_left_mult_x_1_n751), .CO(
genblk1_left_mult_x_1_n752) );
CMPR42X1TS genblk1_left_mult_x_1_U623 ( .A(genblk1_left_mult_x_1_n1218), .B(
genblk1_left_mult_x_1_n1270), .C(genblk1_left_mult_x_1_n1244), .D(
genblk1_left_mult_x_1_n745), .ICI(genblk1_left_mult_x_1_n1296), .S(
genblk1_left_mult_x_1_n743), .ICO(genblk1_left_mult_x_1_n741), .CO(
genblk1_left_mult_x_1_n742) );
CMPR42X1TS genblk1_left_mult_x_1_U622 ( .A(genblk1_left_mult_x_1_n1322), .B(
genblk1_left_mult_x_1_n751), .C(genblk1_left_mult_x_1_n752), .D(
genblk1_left_mult_x_1_n743), .ICI(genblk1_left_mult_x_1_n748), .S(
genblk1_left_mult_x_1_n740), .ICO(genblk1_left_mult_x_1_n738), .CO(
genblk1_left_mult_x_1_n739) );
CMPR42X1TS genblk1_left_mult_x_1_U619 ( .A(genblk1_left_mult_x_1_n1295), .B(
genblk1_left_mult_x_1_n1217), .C(genblk1_left_mult_x_1_n744), .D(
genblk1_left_mult_x_1_n1269), .ICI(genblk1_left_mult_x_1_n1321), .S(
genblk1_left_mult_x_1_n733), .ICO(genblk1_left_mult_x_1_n731), .CO(
genblk1_left_mult_x_1_n732) );
CMPR42X1TS genblk1_left_mult_x_1_U615 ( .A(genblk1_left_mult_x_1_n1268), .B(
genblk1_left_mult_x_1_n1320), .C(genblk1_left_mult_x_1_n734), .D(
genblk1_left_mult_x_1_n1242), .ICI(genblk1_left_mult_x_1_n731), .S(
genblk1_left_mult_x_1_n723), .ICO(genblk1_left_mult_x_1_n721), .CO(
genblk1_left_mult_x_1_n722) );
CMPR42X1TS genblk1_left_mult_x_1_U614 ( .A(genblk1_left_mult_x_1_n1294), .B(
genblk1_left_mult_x_1_n725), .C(genblk1_left_mult_x_1_n732), .D(
genblk1_left_mult_x_1_n723), .ICI(genblk1_left_mult_x_1_n728), .S(
genblk1_left_mult_x_1_n720), .ICO(genblk1_left_mult_x_1_n718), .CO(
genblk1_left_mult_x_1_n719) );
CMPR42X1TS genblk1_left_mult_x_1_U612 ( .A(genblk1_left_mult_x_1_n717), .B(
genblk1_left_mult_x_1_n1163), .C(genblk1_left_mult_x_1_n726), .D(
genblk1_left_mult_x_1_n1189), .ICI(genblk1_left_mult_x_1_n1241), .S(
genblk1_left_mult_x_1_n715), .ICO(genblk1_left_mult_x_1_n713), .CO(
genblk1_left_mult_x_1_n714) );
CMPR42X1TS genblk1_left_mult_x_1_U611 ( .A(genblk1_left_mult_x_1_n1215), .B(
genblk1_left_mult_x_1_n1293), .C(genblk1_left_mult_x_1_n1267), .D(
genblk1_left_mult_x_1_n724), .ICI(genblk1_left_mult_x_1_n721), .S(
genblk1_left_mult_x_1_n712), .ICO(genblk1_left_mult_x_1_n710), .CO(
genblk1_left_mult_x_1_n711) );
CMPR42X1TS genblk1_left_mult_x_1_U608 ( .A(genblk1_left_mult_x_1_n706), .B(
genblk1_left_mult_x_1_n1162), .C(genblk1_left_mult_x_1_n1214), .D(
genblk1_left_mult_x_1_n1188), .ICI(genblk1_left_mult_x_1_n1240), .S(
genblk1_left_mult_x_1_n704), .ICO(genblk1_left_mult_x_1_n702), .CO(
genblk1_left_mult_x_1_n703) );
CMPR42X1TS genblk1_left_mult_x_1_U607 ( .A(genblk1_left_mult_x_1_n1266), .B(
genblk1_left_mult_x_1_n713), .C(genblk1_left_mult_x_1_n1318), .D(
genblk1_left_mult_x_1_n1292), .ICI(genblk1_left_mult_x_1_n714), .S(
genblk1_left_mult_x_1_n701), .ICO(genblk1_left_mult_x_1_n699), .CO(
genblk1_left_mult_x_1_n700) );
CMPR42X1TS genblk1_left_mult_x_1_U606 ( .A(genblk1_left_mult_x_1_n710), .B(
genblk1_left_mult_x_1_n704), .C(genblk1_left_mult_x_1_n711), .D(
genblk1_left_mult_x_1_n701), .ICI(genblk1_left_mult_x_1_n707), .S(
genblk1_left_mult_x_1_n698), .ICO(genblk1_left_mult_x_1_n696), .CO(
genblk1_left_mult_x_1_n697) );
CMPR42X1TS genblk1_left_mult_x_1_U603 ( .A(genblk1_left_mult_x_1_n1291), .B(
genblk1_left_mult_x_1_n1213), .C(genblk1_left_mult_x_1_n1265), .D(
genblk1_left_mult_x_1_n702), .ICI(genblk1_left_mult_x_1_n693), .S(
genblk1_left_mult_x_1_n690), .ICO(genblk1_left_mult_x_1_n688), .CO(
genblk1_left_mult_x_1_n689) );
CMPR42X1TS genblk1_left_mult_x_1_U600 ( .A(genblk1_left_mult_x_1_n1160), .B(
genblk1_left_mult_x_1_n1212), .C(genblk1_left_mult_x_1_n1186), .D(
genblk1_left_mult_x_1_n684), .ICI(genblk1_left_mult_x_1_n688), .S(
genblk1_left_mult_x_1_n682), .ICO(genblk1_left_mult_x_1_n680), .CO(
genblk1_left_mult_x_1_n681) );
CMPR42X1TS genblk1_left_mult_x_1_U599 ( .A(genblk1_left_mult_x_1_n1264), .B(
genblk1_left_mult_x_1_n1316), .C(genblk1_left_mult_x_1_n691), .D(
genblk1_left_mult_x_1_n1238), .ICI(genblk1_left_mult_x_1_n692), .S(
genblk1_left_mult_x_1_n679), .ICO(genblk1_left_mult_x_1_n677), .CO(
genblk1_left_mult_x_1_n678) );
CMPR42X1TS genblk1_left_mult_x_1_U596 ( .A(genblk1_left_mult_x_1_n1237), .B(
genblk1_left_mult_x_1_n1159), .C(genblk1_left_mult_x_1_n683), .D(
genblk1_left_mult_x_1_n1289), .ICI(genblk1_left_mult_x_1_n677), .S(
genblk1_left_mult_x_1_n671), .ICO(genblk1_left_mult_x_1_n669), .CO(
genblk1_left_mult_x_1_n670) );
CMPR42X1TS genblk1_left_mult_x_1_U595 ( .A(genblk1_left_mult_x_1_n1211), .B(
genblk1_left_mult_x_1_n680), .C(genblk1_left_mult_x_1_n673), .D(
genblk1_left_mult_x_1_n1263), .ICI(genblk1_left_mult_x_1_n681), .S(
genblk1_left_mult_x_1_n668), .ICO(genblk1_left_mult_x_1_n666), .CO(
genblk1_left_mult_x_1_n667) );
CMPR42X1TS genblk1_left_mult_x_1_U594 ( .A(genblk1_left_mult_x_1_n1315), .B(
genblk1_left_mult_x_1_n671), .C(genblk1_left_mult_x_1_n678), .D(
genblk1_left_mult_x_1_n668), .ICI(genblk1_left_mult_x_1_n674), .S(
genblk1_left_mult_x_1_n665), .ICO(genblk1_left_mult_x_1_n663), .CO(
genblk1_left_mult_x_1_n664) );
CMPR42X1TS genblk1_left_mult_x_1_U588 ( .A(genblk1_left_mult_x_1_n1183), .B(
genblk1_left_mult_x_1_n1313), .C(genblk1_left_mult_x_1_n1235), .D(
genblk1_left_mult_x_1_n1287), .ICI(genblk1_left_mult_x_1_n655), .S(
genblk1_left_mult_x_1_n649), .ICO(genblk1_left_mult_x_1_n647), .CO(
genblk1_left_mult_x_1_n648) );
CMPR42X1TS genblk1_left_mult_x_1_U587 ( .A(genblk1_left_mult_x_1_n1209), .B(
genblk1_left_mult_x_1_n661), .C(genblk1_left_mult_x_1_n651), .D(
genblk1_left_mult_x_1_n1261), .ICI(genblk1_left_mult_x_1_n658), .S(
genblk1_left_mult_x_1_n646), .ICO(genblk1_left_mult_x_1_n644), .CO(
genblk1_left_mult_x_1_n645) );
CMPR42X1TS genblk1_left_mult_x_1_U584 ( .A(genblk1_left_mult_x_1_n1208), .B(
genblk1_left_mult_x_1_n1130), .C(genblk1_left_mult_x_1_n1260), .D(
genblk1_left_mult_x_1_n1182), .ICI(genblk1_left_mult_x_1_n644), .S(
genblk1_left_mult_x_1_n638), .ICO(genblk1_left_mult_x_1_n636), .CO(
genblk1_left_mult_x_1_n637) );
CMPR42X1TS genblk1_left_mult_x_1_U583 ( .A(genblk1_left_mult_x_1_n650), .B(
genblk1_left_mult_x_1_n640), .C(genblk1_left_mult_x_1_n1234), .D(
genblk1_left_mult_x_1_n1286), .ICI(genblk1_left_mult_x_1_n647), .S(
genblk1_left_mult_x_1_n635), .ICO(genblk1_left_mult_x_1_n633), .CO(
genblk1_left_mult_x_1_n634) );
CMPR42X1TS genblk1_left_mult_x_1_U578 ( .A(genblk1_left_mult_x_1_n637), .B(
genblk1_left_mult_x_1_n627), .C(genblk1_left_mult_x_1_n634), .D(
genblk1_left_mult_x_1_n624), .ICI(genblk1_left_mult_x_1_n630), .S(
genblk1_left_mult_x_1_n621), .ICO(genblk1_left_mult_x_1_n619), .CO(
genblk1_left_mult_x_1_n620) );
CMPR42X2TS genblk1_left_mult_x_1_U574 ( .A(genblk1_left_mult_x_1_n626), .B(
genblk1_left_mult_x_1_n616), .C(genblk1_left_mult_x_1_n623), .D(
genblk1_left_mult_x_1_n613), .ICI(genblk1_left_mult_x_1_n619), .S(
genblk1_left_mult_x_1_n610), .ICO(genblk1_left_mult_x_1_n608), .CO(
genblk1_left_mult_x_1_n609) );
CMPR42X1TS genblk1_left_mult_x_1_U572 ( .A(genblk1_left_mult_x_1_n1127), .B(
genblk1_left_mult_x_1_n1179), .C(genblk1_left_mult_x_1_n607), .D(
genblk1_left_mult_x_1_n1231), .ICI(genblk1_left_mult_x_1_n611), .S(
genblk1_left_mult_x_1_n605), .ICO(genblk1_left_mult_x_1_n603), .CO(
genblk1_left_mult_x_1_n604) );
CMPR42X1TS genblk1_left_mult_x_1_U571 ( .A(genblk1_left_mult_x_1_n617), .B(
genblk1_left_mult_x_1_n1153), .C(genblk1_left_mult_x_1_n1257), .D(
genblk1_left_mult_x_1_n1205), .ICI(genblk1_left_mult_x_1_n614), .S(
genblk1_left_mult_x_1_n602), .ICO(genblk1_left_mult_x_1_n600), .CO(
genblk1_left_mult_x_1_n601) );
CMPR42X1TS genblk1_left_mult_x_1_U566 ( .A(genblk1_left_mult_x_1_n604), .B(
genblk1_left_mult_x_1_n595), .C(genblk1_left_mult_x_1_n601), .D(
genblk1_left_mult_x_1_n592), .ICI(genblk1_left_mult_x_1_n597), .S(
genblk1_left_mult_x_1_n589), .ICO(genblk1_left_mult_x_1_n587), .CO(
genblk1_left_mult_x_1_n588) );
CMPR42X1TS genblk1_left_mult_x_1_U560 ( .A(genblk1_left_mult_x_1_n1124), .B(
genblk1_left_mult_x_1_n582), .C(genblk1_left_mult_x_1_n1176), .D(
genblk1_left_mult_x_1_n1228), .ICI(genblk1_left_mult_x_1_n575), .S(
genblk1_left_mult_x_1_n572), .ICO(genblk1_left_mult_x_1_n570), .CO(
genblk1_left_mult_x_1_n571) );
CMPR42X1TS genblk1_left_mult_x_1_U559 ( .A(genblk1_left_mult_x_1_n579), .B(
genblk1_left_mult_x_1_n583), .C(genblk1_left_mult_x_1_n580), .D(
genblk1_left_mult_x_1_n572), .ICI(genblk1_left_mult_x_1_n576), .S(
genblk1_left_mult_x_1_n569), .ICO(genblk1_left_mult_x_1_n567), .CO(
genblk1_left_mult_x_1_n568) );
CMPR42X1TS genblk1_left_mult_x_1_U555 ( .A(genblk1_left_mult_x_1_n564), .B(
genblk1_left_mult_x_1_n574), .C(genblk1_left_mult_x_1_n571), .D(
genblk1_left_mult_x_1_n562), .ICI(genblk1_left_mult_x_1_n567), .S(
genblk1_left_mult_x_1_n559), .ICO(genblk1_left_mult_x_1_n557), .CO(
genblk1_left_mult_x_1_n558) );
CMPR42X1TS genblk1_left_mult_x_1_U549 ( .A(genblk1_left_mult_x_1_n1099), .B(
genblk1_left_mult_x_1_n1173), .C(genblk1_left_mult_x_1_n546), .D(
genblk1_left_mult_x_1_n553), .ICI(genblk1_left_mult_x_1_n550), .S(
genblk1_left_mult_x_1_n544), .ICO(genblk1_left_mult_x_1_n542), .CO(
genblk1_left_mult_x_1_n543) );
CMPR42X1TS genblk1_left_mult_x_1_U548 ( .A(genblk1_left_mult_x_1_n1199), .B(
genblk1_left_mult_x_1_n1147), .C(genblk1_left_mult_x_1_n551), .D(
genblk1_left_mult_x_1_n544), .ICI(genblk1_left_mult_x_1_n547), .S(
genblk1_left_mult_x_1_n541), .ICO(genblk1_left_mult_x_1_n539), .CO(
genblk1_left_mult_x_1_n540) );
CMPR42X1TS genblk1_left_mult_x_1_U543 ( .A(genblk1_left_mult_x_1_n538), .B(
genblk1_left_mult_x_1_n1098), .C(genblk1_left_mult_x_1_n1197), .D(
genblk1_left_mult_x_1_n1120), .ICI(genblk1_left_mult_x_1_n535), .S(
genblk1_left_mult_x_1_n529), .ICO(genblk1_left_mult_x_1_n527), .CO(
genblk1_left_mult_x_1_n528) );
CMPR42X2TS genblk1_left_mult_x_1_U542 ( .A(genblk1_left_mult_x_1_n1171), .B(
genblk1_left_mult_x_1_n1145), .C(genblk1_left_mult_x_1_n536), .D(
genblk1_left_mult_x_1_n529), .ICI(genblk1_left_mult_x_1_n532), .S(
genblk1_left_mult_x_1_n526), .ICO(genblk1_left_mult_x_1_n524), .CO(
genblk1_left_mult_x_1_n525) );
CMPR42X1TS genblk1_left_mult_x_1_U540 ( .A(genblk1_left_mult_x_1_n1170), .B(
genblk1_left_mult_x_1_n1119), .C(genblk1_left_mult_x_1_n528), .D(
genblk1_left_mult_x_1_n523), .ICI(genblk1_left_mult_x_1_n524), .S(
genblk1_left_mult_x_1_n520), .ICO(genblk1_left_mult_x_1_n518), .CO(
genblk1_left_mult_x_1_n519) );
CMPR42X1TS genblk1_left_mult_x_1_U537 ( .A(genblk1_left_mult_x_1_n517), .B(
genblk1_left_mult_x_1_n1143), .C(genblk1_left_mult_x_1_n515), .D(
genblk1_left_mult_x_1_n522), .ICI(genblk1_left_mult_x_1_n518), .S(
genblk1_left_mult_x_1_n513), .ICO(genblk1_left_mult_x_1_n511), .CO(
genblk1_left_mult_x_1_n512) );
CMPR42X1TS genblk1_left_mult_x_1_U534 ( .A(genblk1_left_mult_x_1_n1142), .B(
genblk1_left_mult_x_1_n1117), .C(genblk1_left_mult_x_1_n508), .D(
genblk1_left_mult_x_1_n514), .ICI(genblk1_left_mult_x_1_n511), .S(
genblk1_left_mult_x_1_n506), .ICO(genblk1_left_mult_x_1_n504), .CO(
genblk1_left_mult_x_1_n505) );
CMPR42X1TS genblk1_left_mult_x_1_U532 ( .A(genblk1_left_mult_x_1_n1096), .B(
genblk1_left_mult_x_1_n1141), .C(genblk1_left_mult_x_1_n507), .D(
genblk1_left_mult_x_1_n503), .ICI(genblk1_left_mult_x_1_n504), .S(
genblk1_left_mult_x_1_n501), .ICO(genblk1_left_mult_x_1_n499), .CO(
genblk1_left_mult_x_1_n500) );
CMPR42X1TS genblk1_left_mult_x_1_U530 ( .A(genblk1_left_mult_x_1_n498), .B(
genblk1_left_mult_x_1_n1140), .C(genblk1_left_mult_x_1_n502), .D(
genblk1_left_mult_x_1_n1115), .ICI(genblk1_left_mult_x_1_n499), .S(
genblk1_left_mult_x_1_n497), .ICO(genblk1_left_mult_x_1_n495), .CO(
genblk1_left_mult_x_1_n496) );
CMPR42X1TS genblk1_left_mult_x_1_U528 ( .A(genblk1_left_mult_x_1_n498), .B(
genblk1_left_mult_x_1_n1139), .C(genblk1_left_mult_x_1_n1114), .D(
genblk1_left_mult_x_1_n1095), .ICI(genblk1_left_mult_x_1_n495), .S(
genblk1_left_mult_x_1_n492), .ICO(genblk1_left_mult_x_1_n490), .CO(
genblk1_left_mult_x_1_n491) );
CMPR42X1TS genblk1_left_mult_x_1_U527 ( .A(genblk1_left_mult_x_1_n1138), .B(
genblk1_left_mult_x_1_n493), .C(genblk1_left_mult_x_1_n1094), .D(
genblk1_left_mult_x_1_n1113), .ICI(genblk1_left_mult_x_1_n490), .S(
genblk1_left_mult_x_1_n489), .ICO(genblk1_left_mult_x_1_n487), .CO(
genblk1_left_mult_x_1_n488) );
CMPR42X1TS genblk1_right_mult_x_1_U707 ( .A(genblk1_right_mult_x_1_n890),
.B(genblk1_right_mult_x_1_n1429), .C(genblk1_right_mult_x_1_n893), .D(
genblk1_right_mult_x_1_n1456), .ICI(genblk1_right_mult_x_1_n1483), .S(
genblk1_right_mult_x_1_n888), .ICO(genblk1_right_mult_x_1_n886), .CO(
genblk1_right_mult_x_1_n887) );
CMPR42X1TS genblk1_right_mult_x_1_U705 ( .A(genblk1_right_mult_x_1_n885),
.B(genblk1_right_mult_x_1_n1428), .C(genblk1_right_mult_x_1_n1482),
.D(genblk1_right_mult_x_1_n1455), .ICI(genblk1_right_mult_x_1_n886),
.S(genblk1_right_mult_x_1_n883), .ICO(genblk1_right_mult_x_1_n881),
.CO(genblk1_right_mult_x_1_n882) );
CMPR42X1TS genblk1_right_mult_x_1_U703 ( .A(genblk1_right_mult_x_1_n880),
.B(genblk1_right_mult_x_1_n1454), .C(genblk1_right_mult_x_1_n1427),
.D(genblk1_right_mult_x_1_n1481), .ICI(genblk1_right_mult_x_1_n881),
.S(genblk1_right_mult_x_1_n878), .ICO(genblk1_right_mult_x_1_n876),
.CO(genblk1_right_mult_x_1_n877) );
CMPR42X1TS genblk1_right_mult_x_1_U700 ( .A(genblk1_right_mult_x_1_n1426),
.B(genblk1_right_mult_x_1_n1480), .C(genblk1_right_mult_x_1_n1453),
.D(genblk1_right_mult_x_1_n873), .ICI(genblk1_right_mult_x_1_n876),
.S(genblk1_right_mult_x_1_n871), .ICO(genblk1_right_mult_x_1_n869),
.CO(genblk1_right_mult_x_1_n870) );
CMPR42X1TS genblk1_right_mult_x_1_U697 ( .A(genblk1_right_mult_x_1_n1452),
.B(genblk1_right_mult_x_1_n1425), .C(genblk1_right_mult_x_1_n872), .D(
genblk1_right_mult_x_1_n869), .ICI(genblk1_right_mult_x_1_n866), .S(
genblk1_right_mult_x_1_n864), .ICO(genblk1_right_mult_x_1_n862), .CO(
genblk1_right_mult_x_1_n863) );
CMPR42X1TS genblk1_right_mult_x_1_U692 ( .A(genblk1_right_mult_x_1_n854),
.B(genblk1_right_mult_x_1_n1369), .C(genblk1_right_mult_x_1_n860), .D(
genblk1_right_mult_x_1_n1396), .ICI(genblk1_right_mult_x_1_n1423), .S(
genblk1_right_mult_x_1_n852), .ICO(genblk1_right_mult_x_1_n850), .CO(
genblk1_right_mult_x_1_n851) );
CMPR42X1TS genblk1_right_mult_x_1_U689 ( .A(genblk1_right_mult_x_1_n846),
.B(genblk1_right_mult_x_1_n1368), .C(genblk1_right_mult_x_1_n1449),
.D(genblk1_right_mult_x_1_n1422), .ICI(genblk1_right_mult_x_1_n850),
.S(genblk1_right_mult_x_1_n844), .ICO(genblk1_right_mult_x_1_n842),
.CO(genblk1_right_mult_x_1_n843) );
CMPR42X1TS genblk1_right_mult_x_1_U686 ( .A(genblk1_right_mult_x_1_n838),
.B(genblk1_right_mult_x_1_n1394), .C(genblk1_right_mult_x_1_n1367),
.D(genblk1_right_mult_x_1_n1421), .ICI(genblk1_right_mult_x_1_n842),
.S(genblk1_right_mult_x_1_n836), .ICO(genblk1_right_mult_x_1_n834),
.CO(genblk1_right_mult_x_1_n835) );
CMPR42X1TS genblk1_right_mult_x_1_U685 ( .A(genblk1_right_mult_x_1_n1448),
.B(genblk1_right_mult_x_1_n1475), .C(genblk1_right_mult_x_1_n843), .D(
genblk1_right_mult_x_1_n839), .ICI(genblk1_right_mult_x_1_n836), .S(
genblk1_right_mult_x_1_n833), .ICO(genblk1_right_mult_x_1_n831), .CO(
genblk1_right_mult_x_1_n832) );
CMPR42X1TS genblk1_right_mult_x_1_U682 ( .A(genblk1_right_mult_x_1_n1366),
.B(genblk1_right_mult_x_1_n1420), .C(genblk1_right_mult_x_1_n1447),
.D(genblk1_right_mult_x_1_n1393), .ICI(genblk1_right_mult_x_1_n834),
.S(genblk1_right_mult_x_1_n826), .ICO(genblk1_right_mult_x_1_n824),
.CO(genblk1_right_mult_x_1_n825) );
CMPR42X1TS genblk1_right_mult_x_1_U681 ( .A(genblk1_right_mult_x_1_n828),
.B(genblk1_right_mult_x_1_n1474), .C(genblk1_right_mult_x_1_n835), .D(
genblk1_right_mult_x_1_n826), .ICI(genblk1_right_mult_x_1_n831), .S(
genblk1_right_mult_x_1_n823), .ICO(genblk1_right_mult_x_1_n821), .CO(
genblk1_right_mult_x_1_n822) );
CMPR42X1TS genblk1_right_mult_x_1_U678 ( .A(genblk1_right_mult_x_1_n1392),
.B(genblk1_right_mult_x_1_n1365), .C(genblk1_right_mult_x_1_n827), .D(
genblk1_right_mult_x_1_n1473), .ICI(genblk1_right_mult_x_1_n818), .S(
genblk1_right_mult_x_1_n816), .ICO(genblk1_right_mult_x_1_n814), .CO(
genblk1_right_mult_x_1_n815) );
CMPR42X1TS genblk1_right_mult_x_1_U677 ( .A(genblk1_right_mult_x_1_n1446),
.B(genblk1_right_mult_x_1_n824), .C(genblk1_right_mult_x_1_n825), .D(
genblk1_right_mult_x_1_n816), .ICI(genblk1_right_mult_x_1_n821), .S(
genblk1_right_mult_x_1_n813), .ICO(genblk1_right_mult_x_1_n811), .CO(
genblk1_right_mult_x_1_n812) );
CMPR42X1TS genblk1_right_mult_x_1_U674 ( .A(genblk1_right_mult_x_1_n1418),
.B(genblk1_right_mult_x_1_n1391), .C(genblk1_right_mult_x_1_n1445),
.D(genblk1_right_mult_x_1_n1472), .ICI(genblk1_right_mult_x_1_n814),
.S(genblk1_right_mult_x_1_n806), .ICO(genblk1_right_mult_x_1_n804),
.CO(genblk1_right_mult_x_1_n805) );
CMPR42X1TS genblk1_right_mult_x_1_U673 ( .A(genblk1_right_mult_x_1_n817),
.B(genblk1_right_mult_x_1_n808), .C(genblk1_right_mult_x_1_n815), .D(
genblk1_right_mult_x_1_n806), .ICI(genblk1_right_mult_x_1_n811), .S(
genblk1_right_mult_x_1_n803), .ICO(genblk1_right_mult_x_1_n801), .CO(
genblk1_right_mult_x_1_n802) );
CMPR42X1TS genblk1_right_mult_x_1_U671 ( .A(genblk1_right_mult_x_1_n800),
.B(genblk1_right_mult_x_1_n1309), .C(genblk1_right_mult_x_1_n809), .D(
genblk1_right_mult_x_1_n1336), .ICI(genblk1_right_mult_x_1_n1363), .S(
genblk1_right_mult_x_1_n798), .ICO(genblk1_right_mult_x_1_n796), .CO(
genblk1_right_mult_x_1_n797) );
CMPR42X1TS genblk1_right_mult_x_1_U670 ( .A(genblk1_right_mult_x_1_n1417),
.B(genblk1_right_mult_x_1_n1390), .C(genblk1_right_mult_x_1_n1444),
.D(genblk1_right_mult_x_1_n1471), .ICI(genblk1_right_mult_x_1_n804),
.S(genblk1_right_mult_x_1_n795), .ICO(genblk1_right_mult_x_1_n793),
.CO(genblk1_right_mult_x_1_n794) );
CMPR42X1TS genblk1_right_mult_x_1_U669 ( .A(genblk1_right_mult_x_1_n807),
.B(genblk1_right_mult_x_1_n798), .C(genblk1_right_mult_x_1_n805), .D(
genblk1_right_mult_x_1_n795), .ICI(genblk1_right_mult_x_1_n801), .S(
genblk1_right_mult_x_1_n792), .ICO(genblk1_right_mult_x_1_n790), .CO(
genblk1_right_mult_x_1_n791) );
CMPR42X1TS genblk1_right_mult_x_1_U667 ( .A(genblk1_right_mult_x_1_n789),
.B(genblk1_right_mult_x_1_n1308), .C(genblk1_right_mult_x_1_n1362),
.D(genblk1_right_mult_x_1_n1389), .ICI(genblk1_right_mult_x_1_n1443),
.S(genblk1_right_mult_x_1_n787), .ICO(genblk1_right_mult_x_1_n785),
.CO(genblk1_right_mult_x_1_n786) );
CMPR42X1TS genblk1_right_mult_x_1_U665 ( .A(genblk1_right_mult_x_1_n793),
.B(genblk1_right_mult_x_1_n787), .C(genblk1_right_mult_x_1_n794), .D(
genblk1_right_mult_x_1_n784), .ICI(genblk1_right_mult_x_1_n790), .S(
genblk1_right_mult_x_1_n781), .ICO(genblk1_right_mult_x_1_n779), .CO(
genblk1_right_mult_x_1_n780) );
CMPR42X1TS genblk1_right_mult_x_1_U662 ( .A(genblk1_right_mult_x_1_n1361),
.B(genblk1_right_mult_x_1_n1442), .C(genblk1_right_mult_x_1_n1469),
.D(genblk1_right_mult_x_1_n1415), .ICI(genblk1_right_mult_x_1_n785),
.S(genblk1_right_mult_x_1_n773), .ICO(genblk1_right_mult_x_1_n771),
.CO(genblk1_right_mult_x_1_n772) );
CMPR42X1TS genblk1_right_mult_x_1_U661 ( .A(genblk1_right_mult_x_1_n786),
.B(genblk1_right_mult_x_1_n776), .C(genblk1_right_mult_x_1_n783), .D(
genblk1_right_mult_x_1_n773), .ICI(genblk1_right_mult_x_1_n779), .S(
genblk1_right_mult_x_1_n770), .ICO(genblk1_right_mult_x_1_n768), .CO(
genblk1_right_mult_x_1_n769) );
CMPR42X1TS genblk1_right_mult_x_1_U658 ( .A(genblk1_right_mult_x_1_n1306),
.B(genblk1_right_mult_x_1_n1387), .C(genblk1_right_mult_x_1_n1333),
.D(genblk1_right_mult_x_1_n1360), .ICI(genblk1_right_mult_x_1_n771),
.S(genblk1_right_mult_x_1_n763), .ICO(genblk1_right_mult_x_1_n761),
.CO(genblk1_right_mult_x_1_n762) );
CMPR42X1TS genblk1_right_mult_x_1_U657 ( .A(genblk1_right_mult_x_1_n765),
.B(genblk1_right_mult_x_1_n1468), .C(genblk1_right_mult_x_1_n1414),
.D(genblk1_right_mult_x_1_n774), .ICI(genblk1_right_mult_x_1_n775),
.S(genblk1_right_mult_x_1_n760), .ICO(genblk1_right_mult_x_1_n758),
.CO(genblk1_right_mult_x_1_n759) );
CMPR42X1TS genblk1_right_mult_x_1_U656 ( .A(genblk1_right_mult_x_1_n1441),
.B(genblk1_right_mult_x_1_n763), .C(genblk1_right_mult_x_1_n772), .D(
genblk1_right_mult_x_1_n760), .ICI(genblk1_right_mult_x_1_n768), .S(
genblk1_right_mult_x_1_n757), .ICO(genblk1_right_mult_x_1_n755), .CO(
genblk1_right_mult_x_1_n756) );
CMPR42X1TS genblk1_right_mult_x_1_U653 ( .A(genblk1_right_mult_x_1_n1359),
.B(genblk1_right_mult_x_1_n1305), .C(genblk1_right_mult_x_1_n764), .D(
genblk1_right_mult_x_1_n1467), .ICI(genblk1_right_mult_x_1_n758), .S(
genblk1_right_mult_x_1_n750), .ICO(genblk1_right_mult_x_1_n748), .CO(
genblk1_right_mult_x_1_n749) );
CMPR42X1TS genblk1_right_mult_x_1_U652 ( .A(genblk1_right_mult_x_1_n1386),
.B(genblk1_right_mult_x_1_n1440), .C(genblk1_right_mult_x_1_n1413),
.D(genblk1_right_mult_x_1_n761), .ICI(genblk1_right_mult_x_1_n752),
.S(genblk1_right_mult_x_1_n747), .ICO(genblk1_right_mult_x_1_n745),
.CO(genblk1_right_mult_x_1_n746) );
CMPR42X1TS genblk1_right_mult_x_1_U651 ( .A(genblk1_right_mult_x_1_n762),
.B(genblk1_right_mult_x_1_n750), .C(genblk1_right_mult_x_1_n759), .D(
genblk1_right_mult_x_1_n747), .ICI(genblk1_right_mult_x_1_n755), .S(
genblk1_right_mult_x_1_n744), .ICO(genblk1_right_mult_x_1_n742), .CO(
genblk1_right_mult_x_1_n743) );
CMPR42X1TS genblk1_right_mult_x_1_U648 ( .A(genblk1_right_mult_x_1_n1358),
.B(genblk1_right_mult_x_1_n1331), .C(genblk1_right_mult_x_1_n1385),
.D(genblk1_right_mult_x_1_n1466), .ICI(genblk1_right_mult_x_1_n745),
.S(genblk1_right_mult_x_1_n737), .ICO(genblk1_right_mult_x_1_n735),
.CO(genblk1_right_mult_x_1_n736) );
CMPR42X1TS genblk1_right_mult_x_1_U646 ( .A(genblk1_right_mult_x_1_n749),
.B(genblk1_right_mult_x_1_n737), .C(genblk1_right_mult_x_1_n746), .D(
genblk1_right_mult_x_1_n734), .ICI(genblk1_right_mult_x_1_n742), .S(
genblk1_right_mult_x_1_n731), .ICO(genblk1_right_mult_x_1_n729), .CO(
genblk1_right_mult_x_1_n730) );
CMPR42X1TS genblk1_right_mult_x_1_U645 ( .A(genblk1_right_mult_x_1_n935),
.B(genblk1_right_mult_x_1_n1249), .C(genblk1_right_mult_x_1_n740), .D(
genblk1_right_mult_x_1_n1276), .ICI(genblk1_right_mult_x_1_n1303), .S(
genblk1_right_mult_x_1_n728), .ICO(genblk1_right_mult_x_1_n726), .CO(
genblk1_right_mult_x_1_n727) );
CMPR42X1TS genblk1_right_mult_x_1_U644 ( .A(genblk1_right_mult_x_1_n1357),
.B(genblk1_right_mult_x_1_n1330), .C(genblk1_right_mult_x_1_n1384),
.D(genblk1_right_mult_x_1_n1465), .ICI(genblk1_right_mult_x_1_n732),
.S(genblk1_right_mult_x_1_n725), .ICO(genblk1_right_mult_x_1_n723),
.CO(genblk1_right_mult_x_1_n724) );
CMPR42X1TS genblk1_right_mult_x_1_U642 ( .A(genblk1_right_mult_x_1_n736),
.B(genblk1_right_mult_x_1_n725), .C(genblk1_right_mult_x_1_n733), .D(
genblk1_right_mult_x_1_n722), .ICI(genblk1_right_mult_x_1_n729), .S(
genblk1_right_mult_x_1_n719), .ICO(genblk1_right_mult_x_1_n717), .CO(
genblk1_right_mult_x_1_n718) );
CMPR42X1TS genblk1_right_mult_x_1_U641 ( .A(genblk1_right_mult_x_1_n934),
.B(genblk1_right_mult_x_1_n1248), .C(genblk1_right_mult_x_1_n1329),
.D(genblk1_right_mult_x_1_n1302), .ICI(genblk1_right_mult_x_1_n1275),
.S(genblk1_right_mult_x_1_n716), .ICO(genblk1_right_mult_x_1_n714),
.CO(genblk1_right_mult_x_1_n715) );
CMPR42X1TS genblk1_right_mult_x_1_U640 ( .A(genblk1_right_mult_x_1_n1464),
.B(genblk1_right_mult_x_1_n1356), .C(genblk1_right_mult_x_1_n1437),
.D(genblk1_right_mult_x_1_n1410), .ICI(genblk1_right_mult_x_1_n727),
.S(genblk1_right_mult_x_1_n713), .ICO(genblk1_right_mult_x_1_n711),
.CO(genblk1_right_mult_x_1_n712) );
CMPR42X1TS genblk1_right_mult_x_1_U639 ( .A(genblk1_right_mult_x_1_n726),
.B(genblk1_right_mult_x_1_n1383), .C(genblk1_right_mult_x_1_n723), .D(
genblk1_right_mult_x_1_n720), .ICI(genblk1_right_mult_x_1_n716), .S(
genblk1_right_mult_x_1_n710), .ICO(genblk1_right_mult_x_1_n708), .CO(
genblk1_right_mult_x_1_n709) );
CMPR42X1TS genblk1_right_mult_x_1_U636 ( .A(genblk1_right_mult_x_1_n1301),
.B(genblk1_right_mult_x_1_n1436), .C(genblk1_right_mult_x_1_n1382),
.D(genblk1_right_mult_x_1_n1409), .ICI(genblk1_right_mult_x_1_n711),
.S(genblk1_right_mult_x_1_n701), .ICO(genblk1_right_mult_x_1_n699),
.CO(genblk1_right_mult_x_1_n700) );
CMPR42X1TS genblk1_right_mult_x_1_U635 ( .A(genblk1_right_mult_x_1_n1355),
.B(genblk1_right_mult_x_1_n714), .C(genblk1_right_mult_x_1_n708), .D(
genblk1_right_mult_x_1_n704), .ICI(genblk1_right_mult_x_1_n715), .S(
genblk1_right_mult_x_1_n698), .ICO(genblk1_right_mult_x_1_n696), .CO(
genblk1_right_mult_x_1_n697) );
CMPR42X1TS genblk1_right_mult_x_1_U634 ( .A(genblk1_right_mult_x_1_n712),
.B(genblk1_right_mult_x_1_n701), .C(genblk1_right_mult_x_1_n709), .D(
genblk1_right_mult_x_1_n705), .ICI(genblk1_right_mult_x_1_n698), .S(
genblk1_right_mult_x_1_n695), .ICO(genblk1_right_mult_x_1_n693), .CO(
genblk1_right_mult_x_1_n694) );
CMPR42X1TS genblk1_right_mult_x_1_U632 ( .A(genblk1_right_mult_x_1_n1300),
.B(genblk1_right_mult_x_1_n702), .C(genblk1_right_mult_x_1_n1354), .D(
genblk1_right_mult_x_1_n1435), .ICI(genblk1_right_mult_x_1_n703), .S(
genblk1_right_mult_x_1_n689), .ICO(genblk1_right_mult_x_1_n687), .CO(
genblk1_right_mult_x_1_n688) );
CMPR42X1TS genblk1_right_mult_x_1_U631 ( .A(genblk1_right_mult_x_1_n1408),
.B(genblk1_right_mult_x_1_n1381), .C(genblk1_right_mult_x_1_n699), .D(
genblk1_right_mult_x_1_n692), .ICI(genblk1_right_mult_x_1_n696), .S(
genblk1_right_mult_x_1_n686), .ICO(genblk1_right_mult_x_1_n684), .CO(
genblk1_right_mult_x_1_n685) );
CMPR42X2TS genblk1_right_mult_x_1_U630 ( .A(genblk1_right_mult_x_1_n700),
.B(genblk1_right_mult_x_1_n689), .C(genblk1_right_mult_x_1_n697), .D(
genblk1_right_mult_x_1_n693), .ICI(genblk1_right_mult_x_1_n686), .S(
genblk1_right_mult_x_1_n683), .ICO(genblk1_right_mult_x_1_n681), .CO(
genblk1_right_mult_x_1_n682) );
CMPR42X1TS genblk1_right_mult_x_1_U628 ( .A(genblk1_right_mult_x_1_n1434),
.B(genblk1_right_mult_x_1_n1326), .C(genblk1_right_mult_x_1_n1407),
.D(genblk1_right_mult_x_1_n690), .ICI(genblk1_right_mult_x_1_n691),
.S(genblk1_right_mult_x_1_n677), .ICO(genblk1_right_mult_x_1_n675),
.CO(genblk1_right_mult_x_1_n676) );
CMPR42X1TS genblk1_right_mult_x_1_U625 ( .A(n273), .B(n282), .C(
genblk1_right_mult_x_1_n930), .D(genblk1_right_mult_x_1_n1244), .ICI(
genblk1_right_mult_x_1_n1298), .S(genblk1_right_mult_x_1_n668), .ICO(
genblk1_right_mult_x_1_n666), .CO(genblk1_right_mult_x_1_n667) );
CMPR42X1TS genblk1_right_mult_x_1_U624 ( .A(genblk1_right_mult_x_1_n1271),
.B(genblk1_right_mult_x_1_n1406), .C(genblk1_right_mult_x_1_n1352),
.D(genblk1_right_mult_x_1_n1379), .ICI(genblk1_right_mult_x_1_n675),
.S(genblk1_right_mult_x_1_n665), .ICO(genblk1_right_mult_x_1_n663),
.CO(genblk1_right_mult_x_1_n664) );
CMPR42X1TS genblk1_right_mult_x_1_U623 ( .A(genblk1_right_mult_x_1_n1325),
.B(genblk1_right_mult_x_1_n678), .C(genblk1_right_mult_x_1_n668), .D(
genblk1_right_mult_x_1_n679), .ICI(genblk1_right_mult_x_1_n672), .S(
genblk1_right_mult_x_1_n662), .ICO(genblk1_right_mult_x_1_n660), .CO(
genblk1_right_mult_x_1_n661) );
CMPR42X2TS genblk1_right_mult_x_1_U622 ( .A(genblk1_right_mult_x_1_n676),
.B(genblk1_right_mult_x_1_n665), .C(genblk1_right_mult_x_1_n673), .D(
genblk1_right_mult_x_1_n662), .ICI(genblk1_right_mult_x_1_n669), .S(
genblk1_right_mult_x_1_n659), .ICO(genblk1_right_mult_x_1_n657), .CO(
genblk1_right_mult_x_1_n658) );
CMPR42X1TS genblk1_right_mult_x_1_U619 ( .A(genblk1_right_mult_x_1_n1297),
.B(genblk1_right_mult_x_1_n1270), .C(genblk1_right_mult_x_1_n1324),
.D(genblk1_right_mult_x_1_n1405), .ICI(genblk1_right_mult_x_1_n667),
.S(genblk1_right_mult_x_1_n653), .ICO(genblk1_right_mult_x_1_n651),
.CO(genblk1_right_mult_x_1_n652) );
CMPR42X1TS genblk1_right_mult_x_1_U618 ( .A(genblk1_right_mult_x_1_n1378),
.B(genblk1_right_mult_x_1_n1351), .C(genblk1_right_mult_x_1_n655), .D(
genblk1_right_mult_x_1_n663), .ICI(genblk1_right_mult_x_1_n660), .S(
genblk1_right_mult_x_1_n650), .ICO(genblk1_right_mult_x_1_n648), .CO(
genblk1_right_mult_x_1_n649) );
CMPR42X1TS genblk1_right_mult_x_1_U614 ( .A(genblk1_right_mult_x_1_n1269),
.B(genblk1_right_mult_x_1_n1404), .C(genblk1_right_mult_x_1_n1296),
.D(genblk1_right_mult_x_1_n1377), .ICI(genblk1_right_mult_x_1_n648),
.S(genblk1_right_mult_x_1_n641), .ICO(genblk1_right_mult_x_1_n639),
.CO(genblk1_right_mult_x_1_n640) );
CMPR42X2TS genblk1_right_mult_x_1_U612 ( .A(genblk1_right_mult_x_1_n652),
.B(genblk1_right_mult_x_1_n641), .C(genblk1_right_mult_x_1_n638), .D(
genblk1_right_mult_x_1_n649), .ICI(genblk1_right_mult_x_1_n645), .S(
genblk1_right_mult_x_1_n635), .ICO(genblk1_right_mult_x_1_n633), .CO(
genblk1_right_mult_x_1_n634) );
CMPR42X1TS genblk1_right_mult_x_1_U610 ( .A(genblk1_right_mult_x_1_n632),
.B(genblk1_right_mult_x_1_n1268), .C(genblk1_right_mult_x_1_n1241),
.D(genblk1_right_mult_x_1_n1376), .ICI(genblk1_right_mult_x_1_n1295),
.S(genblk1_right_mult_x_1_n630), .ICO(genblk1_right_mult_x_1_n628),
.CO(genblk1_right_mult_x_1_n629) );
CMPR42X1TS genblk1_right_mult_x_1_U605 ( .A(genblk1_right_mult_x_1_n1375),
.B(genblk1_right_mult_x_1_n1294), .C(genblk1_right_mult_x_1_n1348),
.D(genblk1_right_mult_x_1_n628), .ICI(genblk1_right_mult_x_1_n620),
.S(genblk1_right_mult_x_1_n617), .ICO(genblk1_right_mult_x_1_n615),
.CO(genblk1_right_mult_x_1_n616) );
CMPR42X1TS genblk1_right_mult_x_1_U602 ( .A(genblk1_right_mult_x_1_n925),
.B(genblk1_right_mult_x_1_n621), .C(genblk1_right_mult_x_1_n1239), .D(
genblk1_right_mult_x_1_n1374), .ICI(genblk1_right_mult_x_1_n1266), .S(
genblk1_right_mult_x_1_n610), .ICO(genblk1_right_mult_x_1_n608), .CO(
genblk1_right_mult_x_1_n609) );
CMPR42X1TS genblk1_right_mult_x_1_U601 ( .A(genblk1_right_mult_x_1_n1347),
.B(genblk1_right_mult_x_1_n1293), .C(genblk1_right_mult_x_1_n1320),
.D(genblk1_right_mult_x_1_n618), .ICI(genblk1_right_mult_x_1_n610),
.S(genblk1_right_mult_x_1_n607), .ICO(genblk1_right_mult_x_1_n605),
.CO(genblk1_right_mult_x_1_n606) );
CMPR42X2TS genblk1_right_mult_x_1_U600 ( .A(genblk1_right_mult_x_1_n615),
.B(genblk1_right_mult_x_1_n619), .C(genblk1_right_mult_x_1_n616), .D(
genblk1_right_mult_x_1_n607), .ICI(genblk1_right_mult_x_1_n612), .S(
genblk1_right_mult_x_1_n604), .ICO(genblk1_right_mult_x_1_n602), .CO(
genblk1_right_mult_x_1_n603) );
CMPR42X1TS genblk1_right_mult_x_1_U599 ( .A(n265), .B(
genblk1_right_mult_x_1_n926), .C(genblk1_right_mult_x_1_n924), .D(
genblk1_right_mult_x_1_n1238), .ICI(genblk1_right_mult_x_1_n1292), .S(
genblk1_right_mult_x_1_n601), .ICO(genblk1_right_mult_x_1_n599), .CO(
genblk1_right_mult_x_1_n600) );
CMPR42X1TS genblk1_right_mult_x_1_U598 ( .A(genblk1_right_mult_x_1_n1346),
.B(genblk1_right_mult_x_1_n1265), .C(genblk1_right_mult_x_1_n1319),
.D(genblk1_right_mult_x_1_n608), .ICI(genblk1_right_mult_x_1_n601),
.S(genblk1_right_mult_x_1_n598), .ICO(genblk1_right_mult_x_1_n596),
.CO(genblk1_right_mult_x_1_n597) );
CMPR42X1TS genblk1_right_mult_x_1_U597 ( .A(genblk1_right_mult_x_1_n605),
.B(genblk1_right_mult_x_1_n609), .C(genblk1_right_mult_x_1_n606), .D(
genblk1_right_mult_x_1_n598), .ICI(genblk1_right_mult_x_1_n602), .S(
genblk1_right_mult_x_1_n595), .ICO(genblk1_right_mult_x_1_n593), .CO(
genblk1_right_mult_x_1_n594) );
CMPR42X1TS genblk1_right_mult_x_1_U590 ( .A(genblk1_right_mult_x_1_n1236),
.B(genblk1_right_mult_x_1_n1263), .C(genblk1_right_mult_x_1_n1290),
.D(genblk1_right_mult_x_1_n590), .ICI(genblk1_right_mult_x_1_n587),
.S(genblk1_right_mult_x_1_n580), .ICO(genblk1_right_mult_x_1_n578),
.CO(genblk1_right_mult_x_1_n579) );
CMPR42X1TS genblk1_right_mult_x_1_U587 ( .A(genblk1_right_mult_x_1_n574),
.B(genblk1_right_mult_x_1_n1316), .C(genblk1_right_mult_x_1_n1289),
.D(genblk1_right_mult_x_1_n1235), .ICI(genblk1_right_mult_x_1_n1262),
.S(genblk1_right_mult_x_1_n572), .ICO(genblk1_right_mult_x_1_n570),
.CO(genblk1_right_mult_x_1_n571) );
CMPR42X1TS genblk1_right_mult_x_1_U586 ( .A(genblk1_right_mult_x_1_n581),
.B(genblk1_right_mult_x_1_n578), .C(genblk1_right_mult_x_1_n579), .D(
genblk1_right_mult_x_1_n572), .ICI(genblk1_right_mult_x_1_n575), .S(
genblk1_right_mult_x_1_n569), .ICO(genblk1_right_mult_x_1_n567), .CO(
genblk1_right_mult_x_1_n568) );
CMPR42X1TS genblk1_right_mult_x_1_U584 ( .A(genblk1_right_mult_x_1_n566),
.B(genblk1_right_mult_x_1_n573), .C(genblk1_right_mult_x_1_n1315), .D(
genblk1_right_mult_x_1_n1261), .ICI(genblk1_right_mult_x_1_n1288), .S(
genblk1_right_mult_x_1_n565), .ICO(genblk1_right_mult_x_1_n563), .CO(
genblk1_right_mult_x_1_n564) );
CMPR42X1TS genblk1_right_mult_x_1_U583 ( .A(genblk1_right_mult_x_1_n1234),
.B(genblk1_right_mult_x_1_n570), .C(genblk1_right_mult_x_1_n565), .D(
genblk1_right_mult_x_1_n571), .ICI(genblk1_right_mult_x_1_n567), .S(
genblk1_right_mult_x_1_n562), .ICO(genblk1_right_mult_x_1_n560), .CO(
genblk1_right_mult_x_1_n561) );
CMPR42X1TS genblk1_right_mult_x_1_U580 ( .A(genblk1_right_mult_x_1_n1233),
.B(genblk1_right_mult_x_1_n563), .C(genblk1_right_mult_x_1_n564), .D(
genblk1_right_mult_x_1_n558), .ICI(genblk1_right_mult_x_1_n560), .S(
genblk1_right_mult_x_1_n555), .ICO(genblk1_right_mult_x_1_n553), .CO(
genblk1_right_mult_x_1_n554) );
CMPR42X1TS genblk1_right_mult_x_1_U579 ( .A(n257), .B(
genblk1_right_mult_x_1_n920), .C(genblk1_right_mult_x_1_n918), .D(
genblk1_right_mult_x_1_n1259), .ICI(genblk1_right_mult_x_1_n1286), .S(
genblk1_right_mult_x_1_n552), .ICO(genblk1_right_mult_x_1_n550), .CO(
genblk1_right_mult_x_1_n551) );
CMPR42X1TS genblk1_right_mult_x_1_U572 ( .A(genblk1_right_mult_x_1_n1257),
.B(genblk1_right_mult_x_1_n1230), .C(genblk1_right_mult_x_1_n539), .D(
genblk1_right_mult_x_1_n544), .ICI(genblk1_right_mult_x_1_n541), .S(
genblk1_right_mult_x_1_n537), .ICO(genblk1_right_mult_x_1_n535), .CO(
genblk1_right_mult_x_1_n536) );
CMPR42X1TS genblk1_right_mult_x_1_U570 ( .A(genblk1_right_mult_x_1_n534),
.B(genblk1_right_mult_x_1_n1256), .C(genblk1_right_mult_x_1_n1229),
.D(genblk1_right_mult_x_1_n538), .ICI(genblk1_right_mult_x_1_n535),
.S(genblk1_right_mult_x_1_n532), .ICO(genblk1_right_mult_x_1_n530),
.CO(genblk1_right_mult_x_1_n531) );
CMPR42X1TS genblk1_right_mult_x_1_U568 ( .A(genblk1_right_mult_x_1_n529),
.B(genblk1_right_mult_x_1_n533), .C(genblk1_right_mult_x_1_n1255), .D(
genblk1_right_mult_x_1_n1228), .ICI(genblk1_right_mult_x_1_n530), .S(
genblk1_right_mult_x_1_n528), .ICO(genblk1_right_mult_x_1_n526), .CO(
genblk1_right_mult_x_1_n527) );
CMPR42X1TS genblk1_right_mult_x_1_U565 ( .A(genblk1_right_mult_x_1_n1253),
.B(genblk1_right_mult_x_1_n914), .C(genblk1_right_mult_x_1_n912), .D(
genblk1_right_mult_x_1_n1226), .ICI(genblk1_right_mult_x_1_n522), .S(
genblk1_right_mult_x_1_n521), .ICO(genblk1_right_mult_x_1_n519), .CO(
genblk1_right_mult_x_1_n520) );
CMPR42X1TS genblk1_middle_mult_x_1_U795 ( .A(genblk1_middle_mult_x_1_n980),
.B(genblk1_middle_mult_x_1_n1516), .C(genblk1_middle_mult_x_1_n1544),
.D(genblk1_middle_mult_x_1_n983), .ICI(genblk1_middle_mult_x_1_n1572),
.S(genblk1_middle_mult_x_1_n978), .ICO(genblk1_middle_mult_x_1_n976),
.CO(genblk1_middle_mult_x_1_n977) );
CMPR42X2TS genblk1_middle_mult_x_1_U782 ( .A(genblk1_middle_mult_x_1_n955),
.B(genblk1_middle_mult_x_1_n1539), .C(genblk1_middle_mult_x_1_n1567),
.D(genblk1_middle_mult_x_1_n949), .ICI(genblk1_middle_mult_x_1_n952),
.S(genblk1_middle_mult_x_1_n947), .ICO(genblk1_middle_mult_x_1_n945),
.CO(genblk1_middle_mult_x_1_n946) );
CMPR42X1TS genblk1_middle_mult_x_1_U779 ( .A(genblk1_middle_mult_x_1_n1510),
.B(genblk1_middle_mult_x_1_n1566), .C(genblk1_middle_mult_x_1_n948),
.D(genblk1_middle_mult_x_1_n945), .ICI(genblk1_middle_mult_x_1_n942),
.S(genblk1_middle_mult_x_1_n939), .ICO(genblk1_middle_mult_x_1_n937),
.CO(genblk1_middle_mult_x_1_n938) );
CMPR42X1TS genblk1_middle_mult_x_1_U770 ( .A(genblk1_middle_mult_x_1_n1423),
.B(genblk1_middle_mult_x_1_n927), .C(genblk1_middle_mult_x_1_n1535),
.D(genblk1_middle_mult_x_1_n1563), .ICI(genblk1_middle_mult_x_1_n924),
.S(genblk1_middle_mult_x_1_n916), .ICO(genblk1_middle_mult_x_1_n914),
.CO(genblk1_middle_mult_x_1_n915) );
CMPR42X1TS genblk1_middle_mult_x_1_U766 ( .A(genblk1_middle_mult_x_1_n1506),
.B(genblk1_middle_mult_x_1_n1478), .C(genblk1_middle_mult_x_1_n1562),
.D(genblk1_middle_mult_x_1_n908), .ICI(genblk1_middle_mult_x_1_n914),
.S(genblk1_middle_mult_x_1_n906), .ICO(genblk1_middle_mult_x_1_n904),
.CO(genblk1_middle_mult_x_1_n905) );
CMPR42X2TS genblk1_middle_mult_x_1_U757 ( .A(genblk1_middle_mult_x_1_n897),
.B(genblk1_middle_mult_x_1_n888), .C(genblk1_middle_mult_x_1_n895),
.D(genblk1_middle_mult_x_1_n885), .ICI(genblk1_middle_mult_x_1_n891),
.S(genblk1_middle_mult_x_1_n882), .ICO(genblk1_middle_mult_x_1_n880),
.CO(genblk1_middle_mult_x_1_n881) );
CMPR42X2TS genblk1_middle_mult_x_1_U754 ( .A(genblk1_middle_mult_x_1_n1447),
.B(genblk1_middle_mult_x_1_n886), .C(genblk1_middle_mult_x_1_n1503),
.D(genblk1_middle_mult_x_1_n1531), .ICI(genblk1_middle_mult_x_1_n887),
.S(genblk1_middle_mult_x_1_n874), .ICO(genblk1_middle_mult_x_1_n872),
.CO(genblk1_middle_mult_x_1_n873) );
CMPR42X2TS genblk1_middle_mult_x_1_U753 ( .A(genblk1_middle_mult_x_1_n1559),
.B(genblk1_middle_mult_x_1_n877), .C(genblk1_middle_mult_x_1_n884),
.D(genblk1_middle_mult_x_1_n874), .ICI(genblk1_middle_mult_x_1_n880),
.S(genblk1_middle_mult_x_1_n871), .ICO(genblk1_middle_mult_x_1_n869),
.CO(genblk1_middle_mult_x_1_n870) );
CMPR42X2TS genblk1_middle_mult_x_1_U750 ( .A(genblk1_middle_mult_x_1_n1502),
.B(genblk1_middle_mult_x_1_n1474), .C(genblk1_middle_mult_x_1_n875),
.D(genblk1_middle_mult_x_1_n1530), .ICI(genblk1_middle_mult_x_1_n876),
.S(genblk1_middle_mult_x_1_n863), .ICO(genblk1_middle_mult_x_1_n861),
.CO(genblk1_middle_mult_x_1_n862) );
CMPR42X1TS genblk1_middle_mult_x_1_U740 ( .A(genblk1_middle_mult_x_1_n1472),
.B(genblk1_middle_mult_x_1_n1500), .C(genblk1_middle_mult_x_1_n1556),
.D(genblk1_middle_mult_x_1_n1528), .ICI(genblk1_middle_mult_x_1_n851),
.S(genblk1_middle_mult_x_1_n837), .ICO(genblk1_middle_mult_x_1_n835),
.CO(genblk1_middle_mult_x_1_n836) );
CMPR42X1TS genblk1_middle_mult_x_1_U736 ( .A(genblk1_middle_mult_x_1_n1415),
.B(genblk1_middle_mult_x_1_n1471), .C(genblk1_middle_mult_x_1_n1499),
.D(genblk1_middle_mult_x_1_n841), .ICI(genblk1_middle_mult_x_1_n835),
.S(genblk1_middle_mult_x_1_n827), .ICO(genblk1_middle_mult_x_1_n825),
.CO(genblk1_middle_mult_x_1_n826) );
CMPR42X1TS genblk1_middle_mult_x_1_U735 ( .A(genblk1_middle_mult_x_1_n1443),
.B(genblk1_middle_mult_x_1_n829), .C(genblk1_middle_mult_x_1_n1555),
.D(genblk1_middle_mult_x_1_n1527), .ICI(genblk1_middle_mult_x_1_n838),
.S(genblk1_middle_mult_x_1_n824), .ICO(genblk1_middle_mult_x_1_n822),
.CO(genblk1_middle_mult_x_1_n823) );
CMPR42X1TS genblk1_middle_mult_x_1_U731 ( .A(genblk1_middle_mult_x_1_n1470),
.B(genblk1_middle_mult_x_1_n1554), .C(genblk1_middle_mult_x_1_n1526),
.D(genblk1_middle_mult_x_1_n825), .ICI(genblk1_middle_mult_x_1_n822),
.S(genblk1_middle_mult_x_1_n812), .ICO(genblk1_middle_mult_x_1_n810),
.CO(genblk1_middle_mult_x_1_n811) );
CMPR42X1TS genblk1_middle_mult_x_1_U729 ( .A(genblk1_middle_mult_x_1_n1026),
.B(genblk1_middle_mult_x_1_n1329), .C(genblk1_middle_mult_x_1_n1357),
.D(genblk1_middle_mult_x_1_n1413), .ICI(genblk1_middle_mult_x_1_n1385),
.S(genblk1_middle_mult_x_1_n806), .ICO(genblk1_middle_mult_x_1_n804),
.CO(genblk1_middle_mult_x_1_n805) );
CMPR42X2TS genblk1_middle_mult_x_1_U726 ( .A(genblk1_middle_mult_x_1_n814),
.B(genblk1_middle_mult_x_1_n803), .C(genblk1_middle_mult_x_1_n811),
.D(genblk1_middle_mult_x_1_n800), .ICI(genblk1_middle_mult_x_1_n807),
.S(genblk1_middle_mult_x_1_n797), .ICO(genblk1_middle_mult_x_1_n795),
.CO(genblk1_middle_mult_x_1_n796) );
CMPR42X1TS genblk1_middle_mult_x_1_U725 ( .A(genblk1_middle_mult_x_1_n1025),
.B(genblk1_middle_mult_x_1_n1328), .C(genblk1_middle_mult_x_1_n1356),
.D(genblk1_middle_mult_x_1_n1384), .ICI(genblk1_middle_mult_x_1_n804),
.S(genblk1_middle_mult_x_1_n794), .ICO(genblk1_middle_mult_x_1_n792),
.CO(genblk1_middle_mult_x_1_n793) );
CMPR42X2TS genblk1_middle_mult_x_1_U723 ( .A(genblk1_middle_mult_x_1_n1524),
.B(genblk1_middle_mult_x_1_n1496), .C(genblk1_middle_mult_x_1_n801),
.D(genblk1_middle_mult_x_1_n805), .ICI(genblk1_middle_mult_x_1_n802),
.S(genblk1_middle_mult_x_1_n788), .ICO(genblk1_middle_mult_x_1_n786),
.CO(genblk1_middle_mult_x_1_n787) );
CMPR42X1TS genblk1_middle_mult_x_1_U716 ( .A(genblk1_middle_mult_x_1_n780),
.B(genblk1_middle_mult_x_1_n1410), .C(genblk1_middle_mult_x_1_n1438),
.D(genblk1_middle_mult_x_1_n1494), .ICI(genblk1_middle_mult_x_1_n774),
.S(genblk1_middle_mult_x_1_n767), .ICO(genblk1_middle_mult_x_1_n765),
.CO(genblk1_middle_mult_x_1_n766) );
CMPR42X1TS genblk1_middle_mult_x_1_U715 ( .A(genblk1_middle_mult_x_1_n1466),
.B(genblk1_middle_mult_x_1_n1522), .C(genblk1_middle_mult_x_1_n777),
.D(genblk1_middle_mult_x_1_n781), .ICI(genblk1_middle_mult_x_1_n770),
.S(genblk1_middle_mult_x_1_n764), .ICO(genblk1_middle_mult_x_1_n762),
.CO(genblk1_middle_mult_x_1_n763) );
CMPR42X1TS genblk1_middle_mult_x_1_U713 ( .A(result_A_adder_2_), .B(
genblk1_middle_mult_x_1_n1022), .C(genblk1_middle_mult_x_1_n1325), .D(
genblk1_middle_mult_x_1_n1353), .ICI(genblk1_middle_mult_x_1_n768),
.S(genblk1_middle_mult_x_1_n758), .ICO(genblk1_middle_mult_x_1_n756),
.CO(genblk1_middle_mult_x_1_n757) );
CMPR42X2TS genblk1_middle_mult_x_1_U711 ( .A(genblk1_middle_mult_x_1_n1493),
.B(genblk1_middle_mult_x_1_n1465), .C(genblk1_middle_mult_x_1_n765),
.D(genblk1_middle_mult_x_1_n769), .ICI(genblk1_middle_mult_x_1_n766),
.S(genblk1_middle_mult_x_1_n752), .ICO(genblk1_middle_mult_x_1_n750),
.CO(genblk1_middle_mult_x_1_n751) );
CMPR42X2TS genblk1_middle_mult_x_1_U710 ( .A(genblk1_middle_mult_x_1_n758),
.B(genblk1_middle_mult_x_1_n755), .C(genblk1_middle_mult_x_1_n763),
.D(genblk1_middle_mult_x_1_n752), .ICI(genblk1_middle_mult_x_1_n759),
.S(genblk1_middle_mult_x_1_n749), .ICO(genblk1_middle_mult_x_1_n747),
.CO(genblk1_middle_mult_x_1_n748) );
CMPR42X2TS genblk1_middle_mult_x_1_U709 ( .A(n1182), .B(n1181), .C(
genblk1_middle_mult_x_1_n1021), .D(genblk1_middle_mult_x_1_n1324),
.ICI(genblk1_middle_mult_x_1_n756), .S(genblk1_middle_mult_x_1_n746),
.ICO(genblk1_middle_mult_x_1_n744), .CO(genblk1_middle_mult_x_1_n745)
);
CMPR42X1TS genblk1_middle_mult_x_1_U708 ( .A(genblk1_middle_mult_x_1_n1380),
.B(genblk1_middle_mult_x_1_n1408), .C(genblk1_middle_mult_x_1_n1352),
.D(genblk1_middle_mult_x_1_n1436), .ICI(genblk1_middle_mult_x_1_n750),
.S(genblk1_middle_mult_x_1_n743), .ICO(genblk1_middle_mult_x_1_n741),
.CO(genblk1_middle_mult_x_1_n742) );
CMPR42X2TS genblk1_middle_mult_x_1_U706 ( .A(genblk1_middle_mult_x_1_n754),
.B(genblk1_middle_mult_x_1_n743), .C(genblk1_middle_mult_x_1_n751),
.D(genblk1_middle_mult_x_1_n740), .ICI(genblk1_middle_mult_x_1_n747),
.S(genblk1_middle_mult_x_1_n737), .ICO(genblk1_middle_mult_x_1_n735),
.CO(genblk1_middle_mult_x_1_n736) );
CMPR42X1TS genblk1_middle_mult_x_1_U702 ( .A(genblk1_middle_mult_x_1_n1435),
.B(genblk1_middle_mult_x_1_n1463), .C(genblk1_middle_mult_x_1_n1491),
.D(genblk1_middle_mult_x_1_n745), .ICI(genblk1_middle_mult_x_1_n741),
.S(genblk1_middle_mult_x_1_n728), .ICO(genblk1_middle_mult_x_1_n726),
.CO(genblk1_middle_mult_x_1_n727) );
CMPR42X1TS genblk1_middle_mult_x_1_U701 ( .A(genblk1_middle_mult_x_1_n742),
.B(genblk1_middle_mult_x_1_n731), .C(genblk1_middle_mult_x_1_n739),
.D(genblk1_middle_mult_x_1_n728), .ICI(genblk1_middle_mult_x_1_n735),
.S(genblk1_middle_mult_x_1_n725), .ICO(genblk1_middle_mult_x_1_n723),
.CO(genblk1_middle_mult_x_1_n724) );
CMPR42X2TS genblk1_middle_mult_x_1_U698 ( .A(genblk1_middle_mult_x_1_n1378),
.B(genblk1_middle_mult_x_1_n1406), .C(genblk1_middle_mult_x_1_n1490),
.D(genblk1_middle_mult_x_1_n732), .ICI(genblk1_middle_mult_x_1_n726),
.S(genblk1_middle_mult_x_1_n719), .ICO(genblk1_middle_mult_x_1_n717),
.CO(genblk1_middle_mult_x_1_n718) );
CMPR42X1TS genblk1_middle_mult_x_1_U697 ( .A(genblk1_middle_mult_x_1_n1350),
.B(genblk1_middle_mult_x_1_n1462), .C(genblk1_middle_mult_x_1_n1434),
.D(genblk1_middle_mult_x_1_n721), .ICI(genblk1_middle_mult_x_1_n729),
.S(genblk1_middle_mult_x_1_n716), .ICO(genblk1_middle_mult_x_1_n714),
.CO(genblk1_middle_mult_x_1_n715) );
CMPR42X1TS genblk1_middle_mult_x_1_U696 ( .A(genblk1_middle_mult_x_1_n730),
.B(genblk1_middle_mult_x_1_n719), .C(genblk1_middle_mult_x_1_n727),
.D(genblk1_middle_mult_x_1_n716), .ICI(genblk1_middle_mult_x_1_n723),
.S(genblk1_middle_mult_x_1_n713), .ICO(genblk1_middle_mult_x_1_n711),
.CO(genblk1_middle_mult_x_1_n712) );
CMPR42X1TS genblk1_middle_mult_x_1_U694 ( .A(genblk1_middle_mult_x_1_n710),
.B(genblk1_middle_mult_x_1_n1349), .C(genblk1_middle_mult_x_1_n1377),
.D(genblk1_middle_mult_x_1_n1321), .ICI(genblk1_middle_mult_x_1_n1433),
.S(genblk1_middle_mult_x_1_n708), .ICO(genblk1_middle_mult_x_1_n706),
.CO(genblk1_middle_mult_x_1_n707) );
CMPR42X1TS genblk1_middle_mult_x_1_U693 ( .A(genblk1_middle_mult_x_1_n1405),
.B(genblk1_middle_mult_x_1_n720), .C(genblk1_middle_mult_x_1_n1461),
.D(genblk1_middle_mult_x_1_n717), .ICI(genblk1_middle_mult_x_1_n714),
.S(genblk1_middle_mult_x_1_n705), .ICO(genblk1_middle_mult_x_1_n703),
.CO(genblk1_middle_mult_x_1_n704) );
CMPR42X1TS genblk1_middle_mult_x_1_U692 ( .A(genblk1_middle_mult_x_1_n718),
.B(genblk1_middle_mult_x_1_n708), .C(genblk1_middle_mult_x_1_n715),
.D(genblk1_middle_mult_x_1_n705), .ICI(genblk1_middle_mult_x_1_n711),
.S(genblk1_middle_mult_x_1_n702), .ICO(genblk1_middle_mult_x_1_n700),
.CO(genblk1_middle_mult_x_1_n701) );
CMPR42X1TS genblk1_middle_mult_x_1_U690 ( .A(genblk1_middle_mult_x_1_n699),
.B(genblk1_middle_mult_x_1_n709), .C(genblk1_middle_mult_x_1_n1320),
.D(genblk1_middle_mult_x_1_n1348), .ICI(genblk1_middle_mult_x_1_n1376),
.S(genblk1_middle_mult_x_1_n698), .ICO(genblk1_middle_mult_x_1_n696),
.CO(genblk1_middle_mult_x_1_n697) );
CMPR42X1TS genblk1_middle_mult_x_1_U689 ( .A(genblk1_middle_mult_x_1_n1432),
.B(genblk1_middle_mult_x_1_n1404), .C(genblk1_middle_mult_x_1_n1460),
.D(genblk1_middle_mult_x_1_n706), .ICI(genblk1_middle_mult_x_1_n707),
.S(genblk1_middle_mult_x_1_n695), .ICO(genblk1_middle_mult_x_1_n693),
.CO(genblk1_middle_mult_x_1_n694) );
CMPR42X1TS genblk1_middle_mult_x_1_U686 ( .A(genblk1_middle_mult_x_1_n1017),
.B(genblk1_middle_mult_x_1_n689), .C(genblk1_middle_mult_x_1_n1347),
.D(genblk1_middle_mult_x_1_n1319), .ICI(genblk1_middle_mult_x_1_n1375),
.S(genblk1_middle_mult_x_1_n688), .ICO(genblk1_middle_mult_x_1_n686),
.CO(genblk1_middle_mult_x_1_n687) );
CMPR42X1TS genblk1_middle_mult_x_1_U684 ( .A(genblk1_middle_mult_x_1_n693),
.B(genblk1_middle_mult_x_1_n688), .C(genblk1_middle_mult_x_1_n685),
.D(genblk1_middle_mult_x_1_n694), .ICI(genblk1_middle_mult_x_1_n690),
.S(genblk1_middle_mult_x_1_n682), .ICO(genblk1_middle_mult_x_1_n680),
.CO(genblk1_middle_mult_x_1_n681) );
CMPR42X1TS genblk1_middle_mult_x_1_U683 ( .A(n1340), .B(
genblk1_middle_mult_x_1_n1016), .C(genblk1_middle_mult_x_1_n1015), .D(
genblk1_middle_mult_x_1_n1318), .ICI(genblk1_middle_mult_x_1_n1346),
.S(genblk1_middle_mult_x_1_n679), .ICO(genblk1_middle_mult_x_1_n677),
.CO(genblk1_middle_mult_x_1_n678) );
CMPR42X1TS genblk1_middle_mult_x_1_U681 ( .A(genblk1_middle_mult_x_1_n683),
.B(genblk1_middle_mult_x_1_n687), .C(genblk1_middle_mult_x_1_n684),
.D(genblk1_middle_mult_x_1_n676), .ICI(genblk1_middle_mult_x_1_n680),
.S(genblk1_middle_mult_x_1_n673), .ICO(genblk1_middle_mult_x_1_n671),
.CO(genblk1_middle_mult_x_1_n672) );
CMPR42X1TS genblk1_middle_mult_x_1_U678 ( .A(genblk1_middle_mult_x_1_n1345),
.B(genblk1_middle_mult_x_1_n1373), .C(genblk1_middle_mult_x_1_n1401),
.D(genblk1_middle_mult_x_1_n1429), .ICI(genblk1_middle_mult_x_1_n678),
.S(genblk1_middle_mult_x_1_n667), .ICO(genblk1_middle_mult_x_1_n665),
.CO(genblk1_middle_mult_x_1_n666) );
CMPR42X2TS genblk1_middle_mult_x_1_U674 ( .A(genblk1_middle_mult_x_1_n1344),
.B(genblk1_middle_mult_x_1_n1428), .C(genblk1_middle_mult_x_1_n1372),
.D(genblk1_middle_mult_x_1_n668), .ICI(genblk1_middle_mult_x_1_n665),
.S(genblk1_middle_mult_x_1_n658), .ICO(genblk1_middle_mult_x_1_n656),
.CO(genblk1_middle_mult_x_1_n657) );
CMPR42X1TS genblk1_middle_mult_x_1_U673 ( .A(genblk1_middle_mult_x_1_n1400),
.B(genblk1_middle_mult_x_1_n660), .C(genblk1_middle_mult_x_1_n658),
.D(genblk1_middle_mult_x_1_n666), .ICI(genblk1_middle_mult_x_1_n662),
.S(genblk1_middle_mult_x_1_n655), .ICO(genblk1_middle_mult_x_1_n653),
.CO(genblk1_middle_mult_x_1_n654) );
CMPR42X1TS genblk1_middle_mult_x_1_U671 ( .A(genblk1_middle_mult_x_1_n652),
.B(genblk1_middle_mult_x_1_n1315), .C(genblk1_middle_mult_x_1_n1343),
.D(genblk1_middle_mult_x_1_n1371), .ICI(genblk1_middle_mult_x_1_n659),
.S(genblk1_middle_mult_x_1_n650), .ICO(genblk1_middle_mult_x_1_n648),
.CO(genblk1_middle_mult_x_1_n649) );
CMPR42X2TS genblk1_middle_mult_x_1_U670 ( .A(genblk1_middle_mult_x_1_n1399),
.B(genblk1_middle_mult_x_1_n656), .C(genblk1_middle_mult_x_1_n657),
.D(genblk1_middle_mult_x_1_n650), .ICI(genblk1_middle_mult_x_1_n653),
.S(genblk1_middle_mult_x_1_n647), .ICO(genblk1_middle_mult_x_1_n645),
.CO(genblk1_middle_mult_x_1_n646) );
CMPR42X1TS genblk1_middle_mult_x_1_U668 ( .A(genblk1_middle_mult_x_1_n644),
.B(genblk1_middle_mult_x_1_n651), .C(genblk1_middle_mult_x_1_n1314),
.D(genblk1_middle_mult_x_1_n1370), .ICI(genblk1_middle_mult_x_1_n1342),
.S(genblk1_middle_mult_x_1_n643), .ICO(genblk1_middle_mult_x_1_n641),
.CO(genblk1_middle_mult_x_1_n642) );
CMPR42X2TS genblk1_middle_mult_x_1_U667 ( .A(genblk1_middle_mult_x_1_n1398),
.B(genblk1_middle_mult_x_1_n648), .C(genblk1_middle_mult_x_1_n649),
.D(genblk1_middle_mult_x_1_n643), .ICI(genblk1_middle_mult_x_1_n645),
.S(genblk1_middle_mult_x_1_n640), .ICO(genblk1_middle_mult_x_1_n638),
.CO(genblk1_middle_mult_x_1_n639) );
CMPR42X1TS genblk1_middle_mult_x_1_U665 ( .A(genblk1_middle_mult_x_1_n1010),
.B(genblk1_middle_mult_x_1_n644), .C(genblk1_middle_mult_x_1_n1313),
.D(genblk1_middle_mult_x_1_n1397), .ICI(genblk1_middle_mult_x_1_n1369),
.S(genblk1_middle_mult_x_1_n636), .ICO(genblk1_middle_mult_x_1_n634),
.CO(genblk1_middle_mult_x_1_n635) );
CMPR42X1TS genblk1_middle_mult_x_1_U664 ( .A(genblk1_middle_mult_x_1_n1341),
.B(genblk1_middle_mult_x_1_n641), .C(genblk1_middle_mult_x_1_n642),
.D(genblk1_middle_mult_x_1_n636), .ICI(genblk1_middle_mult_x_1_n638),
.S(genblk1_middle_mult_x_1_n633), .ICO(genblk1_middle_mult_x_1_n631),
.CO(genblk1_middle_mult_x_1_n632) );
CMPR42X1TS genblk1_middle_mult_x_1_U662 ( .A(genblk1_middle_mult_x_1_n1340),
.B(genblk1_middle_mult_x_1_n634), .C(genblk1_middle_mult_x_1_n635),
.D(genblk1_middle_mult_x_1_n630), .ICI(genblk1_middle_mult_x_1_n631),
.S(genblk1_middle_mult_x_1_n627), .ICO(genblk1_middle_mult_x_1_n625),
.CO(genblk1_middle_mult_x_1_n626) );
CMPR42X1TS genblk1_middle_mult_x_1_U654 ( .A(genblk1_middle_mult_x_1_n612),
.B(genblk1_middle_mult_x_1_n1337), .C(genblk1_middle_mult_x_1_n1309),
.D(genblk1_middle_mult_x_1_n616), .ICI(genblk1_middle_mult_x_1_n613),
.S(genblk1_middle_mult_x_1_n610), .ICO(genblk1_middle_mult_x_1_n608),
.CO(genblk1_middle_mult_x_1_n609) );
CMPR42X1TS genblk1_middle_mult_x_1_U649 ( .A(n408), .B(
genblk1_middle_mult_x_1_n1005), .C(genblk1_middle_mult_x_1_n1003), .D(
genblk1_middle_mult_x_1_n1306), .ICI(genblk1_middle_mult_x_1_n600),
.S(genblk1_middle_mult_x_1_n599), .ICO(genblk1_middle_mult_x_1_n597),
.CO(genblk1_middle_mult_x_1_n598) );
CMPR42X2TS genblk1_middle_mult_x_1_U762 ( .A(genblk1_middle_mult_x_1_n1477),
.B(genblk1_middle_mult_x_1_n1505), .C(genblk1_middle_mult_x_1_n907),
.D(genblk1_middle_mult_x_1_n1561), .ICI(genblk1_middle_mult_x_1_n904),
.S(genblk1_middle_mult_x_1_n896), .ICO(genblk1_middle_mult_x_1_n894),
.CO(genblk1_middle_mult_x_1_n895) );
CMPR42X2TS genblk1_middle_mult_x_1_U788 ( .A(genblk1_middle_mult_x_1_n969),
.B(genblk1_middle_mult_x_1_n1541), .C(genblk1_middle_mult_x_1_n963),
.D(genblk1_middle_mult_x_1_n966), .ICI(genblk1_middle_mult_x_1_n1569),
.S(genblk1_middle_mult_x_1_n961), .ICO(genblk1_middle_mult_x_1_n959),
.CO(genblk1_middle_mult_x_1_n960) );
CMPR42X2TS genblk1_middle_mult_x_1_U741 ( .A(genblk1_middle_mult_x_1_n1444),
.B(genblk1_middle_mult_x_1_n1416), .C(genblk1_middle_mult_x_1_n854),
.D(genblk1_middle_mult_x_1_n842), .ICI(genblk1_middle_mult_x_1_n848),
.S(genblk1_middle_mult_x_1_n840), .ICO(genblk1_middle_mult_x_1_n838),
.CO(genblk1_middle_mult_x_1_n839) );
CMPR42X2TS genblk1_middle_mult_x_1_U744 ( .A(genblk1_middle_mult_x_1_n1529),
.B(genblk1_middle_mult_x_1_n853), .C(genblk1_middle_mult_x_1_n862),
.D(genblk1_middle_mult_x_1_n850), .ICI(genblk1_middle_mult_x_1_n858),
.S(genblk1_middle_mult_x_1_n847), .ICO(genblk1_middle_mult_x_1_n845),
.CO(genblk1_middle_mult_x_1_n846) );
CMPR42X2TS genblk1_middle_mult_x_1_U732 ( .A(genblk1_middle_mult_x_1_n1442),
.B(genblk1_middle_mult_x_1_n1414), .C(genblk1_middle_mult_x_1_n828),
.D(genblk1_middle_mult_x_1_n1498), .ICI(genblk1_middle_mult_x_1_n818),
.S(genblk1_middle_mult_x_1_n815), .ICO(genblk1_middle_mult_x_1_n813),
.CO(genblk1_middle_mult_x_1_n814) );
CMPR42X2TS genblk1_middle_mult_x_1_U739 ( .A(genblk1_middle_mult_x_1_n852),
.B(genblk1_middle_mult_x_1_n840), .C(genblk1_middle_mult_x_1_n849),
.D(genblk1_middle_mult_x_1_n837), .ICI(genblk1_middle_mult_x_1_n845),
.S(genblk1_middle_mult_x_1_n834), .ICO(genblk1_middle_mult_x_1_n832),
.CO(genblk1_middle_mult_x_1_n833) );
CMPR42X2TS genblk1_middle_mult_x_1_U734 ( .A(genblk1_middle_mult_x_1_n839),
.B(genblk1_middle_mult_x_1_n827), .C(genblk1_middle_mult_x_1_n836),
.D(genblk1_middle_mult_x_1_n824), .ICI(genblk1_middle_mult_x_1_n832),
.S(genblk1_middle_mult_x_1_n821), .ICO(genblk1_middle_mult_x_1_n819),
.CO(genblk1_middle_mult_x_1_n820) );
CMPR42X2TS genblk1_middle_mult_x_1_U749 ( .A(genblk1_middle_mult_x_1_n1558),
.B(genblk1_middle_mult_x_1_n866), .C(genblk1_middle_mult_x_1_n873),
.D(genblk1_middle_mult_x_1_n863), .ICI(genblk1_middle_mult_x_1_n869),
.S(genblk1_middle_mult_x_1_n860), .ICO(genblk1_middle_mult_x_1_n858),
.CO(genblk1_middle_mult_x_1_n859) );
CMPR42X2TS genblk1_middle_mult_x_1_U765 ( .A(genblk1_middle_mult_x_1_n917),
.B(genblk1_middle_mult_x_1_n1534), .C(genblk1_middle_mult_x_1_n915),
.D(genblk1_middle_mult_x_1_n911), .ICI(genblk1_middle_mult_x_1_n906),
.S(genblk1_middle_mult_x_1_n903), .ICO(genblk1_middle_mult_x_1_n901),
.CO(genblk1_middle_mult_x_1_n902) );
CMPR42X2TS genblk1_middle_mult_x_1_U774 ( .A(genblk1_middle_mult_x_1_n1480),
.B(genblk1_middle_mult_x_1_n935), .C(genblk1_middle_mult_x_1_n928),
.D(genblk1_middle_mult_x_1_n1508), .ICI(genblk1_middle_mult_x_1_n1536),
.S(genblk1_middle_mult_x_1_n926), .ICO(genblk1_middle_mult_x_1_n924),
.CO(genblk1_middle_mult_x_1_n925) );
CMPR42X2TS genblk1_middle_mult_x_1_U727 ( .A(genblk1_middle_mult_x_1_n1497),
.B(genblk1_middle_mult_x_1_n1553), .C(genblk1_middle_mult_x_1_n813),
.D(genblk1_middle_mult_x_1_n817), .ICI(genblk1_middle_mult_x_1_n806),
.S(genblk1_middle_mult_x_1_n800), .ICO(genblk1_middle_mult_x_1_n798),
.CO(genblk1_middle_mult_x_1_n799) );
CMPR42X2TS genblk1_middle_mult_x_1_U761 ( .A(genblk1_middle_mult_x_1_n1533),
.B(genblk1_middle_mult_x_1_n898), .C(genblk1_middle_mult_x_1_n905),
.D(genblk1_middle_mult_x_1_n896), .ICI(genblk1_middle_mult_x_1_n901),
.S(genblk1_middle_mult_x_1_n893), .ICO(genblk1_middle_mult_x_1_n891),
.CO(genblk1_middle_mult_x_1_n892) );
CMPR42X2TS genblk1_middle_mult_x_1_U685 ( .A(genblk1_middle_mult_x_1_n1459),
.B(genblk1_middle_mult_x_1_n696), .C(genblk1_middle_mult_x_1_n1431),
.D(genblk1_middle_mult_x_1_n1403), .ICI(genblk1_middle_mult_x_1_n697),
.S(genblk1_middle_mult_x_1_n685), .ICO(genblk1_middle_mult_x_1_n683),
.CO(genblk1_middle_mult_x_1_n684) );
CMPR42X2TS genblk1_middle_mult_x_1_U745 ( .A(genblk1_middle_mult_x_1_n1445),
.B(genblk1_middle_mult_x_1_n855), .C(genblk1_middle_mult_x_1_n864),
.D(genblk1_middle_mult_x_1_n1557), .ICI(genblk1_middle_mult_x_1_n865),
.S(genblk1_middle_mult_x_1_n850), .ICO(genblk1_middle_mult_x_1_n848),
.CO(genblk1_middle_mult_x_1_n849) );
CMPR42X2TS genblk1_left_mult_x_1_U626 ( .A(genblk1_left_mult_x_1_n1271), .B(
genblk1_left_mult_x_1_n1323), .C(genblk1_left_mult_x_1_n760), .D(
genblk1_left_mult_x_1_n756), .ICI(genblk1_left_mult_x_1_n753), .S(
genblk1_left_mult_x_1_n750), .ICO(genblk1_left_mult_x_1_n748), .CO(
genblk1_left_mult_x_1_n749) );
CMPR42X2TS genblk1_middle_mult_x_1_U769 ( .A(genblk1_middle_mult_x_1_n918),
.B(genblk1_middle_mult_x_1_n1507), .C(genblk1_middle_mult_x_1_n925),
.D(genblk1_middle_mult_x_1_n921), .ICI(genblk1_middle_mult_x_1_n916),
.S(genblk1_middle_mult_x_1_n913), .ICO(genblk1_middle_mult_x_1_n911),
.CO(genblk1_middle_mult_x_1_n912) );
CMPR42X2TS genblk1_middle_mult_x_1_U719 ( .A(genblk1_middle_mult_x_1_n1523),
.B(genblk1_middle_mult_x_1_n1495), .C(genblk1_middle_mult_x_1_n789),
.D(genblk1_middle_mult_x_1_n782), .ICI(genblk1_middle_mult_x_1_n793),
.S(genblk1_middle_mult_x_1_n776), .ICO(genblk1_middle_mult_x_1_n774),
.CO(genblk1_middle_mult_x_1_n775) );
CMPR42X2TS genblk1_middle_mult_x_1_U776 ( .A(genblk1_middle_mult_x_1_n1537),
.B(genblk1_middle_mult_x_1_n1509), .C(genblk1_middle_mult_x_1_n937),
.D(genblk1_middle_mult_x_1_n941), .ICI(genblk1_middle_mult_x_1_n934),
.S(genblk1_middle_mult_x_1_n931), .ICO(genblk1_middle_mult_x_1_n929),
.CO(genblk1_middle_mult_x_1_n930) );
CMPR42X2TS genblk1_middle_mult_x_1_U722 ( .A(genblk1_middle_mult_x_1_n794),
.B(genblk1_middle_mult_x_1_n791), .C(genblk1_middle_mult_x_1_n799),
.D(genblk1_middle_mult_x_1_n788), .ICI(genblk1_middle_mult_x_1_n795),
.S(genblk1_middle_mult_x_1_n785), .ICO(genblk1_middle_mult_x_1_n783),
.CO(genblk1_middle_mult_x_1_n784) );
CMPR42X2TS genblk1_middle_mult_x_1_U730 ( .A(genblk1_middle_mult_x_1_n826),
.B(genblk1_middle_mult_x_1_n815), .C(genblk1_middle_mult_x_1_n823),
.D(genblk1_middle_mult_x_1_n812), .ICI(genblk1_middle_mult_x_1_n819),
.S(genblk1_middle_mult_x_1_n809), .ICO(genblk1_middle_mult_x_1_n807),
.CO(genblk1_middle_mult_x_1_n808) );
DFFQX1TS genblk1_middle_pdt_int_reg_52_ ( .D(genblk1_middle_N52), .CK(clk),
.Q(Q_middle[52]) );
DFFQX1TS genblk1_middle_pdt_int_reg_39_ ( .D(genblk1_middle_N39), .CK(clk),
.Q(Q_middle[39]) );
DFFQX1TS genblk1_middle_pdt_int_reg_49_ ( .D(genblk1_middle_N49), .CK(clk),
.Q(Q_middle[49]) );
DFFQX1TS genblk1_middle_pdt_int_reg_47_ ( .D(genblk1_middle_N47), .CK(clk),
.Q(Q_middle[47]) );
DFFQX1TS genblk1_middle_pdt_int_reg_53_ ( .D(genblk1_middle_N53), .CK(clk),
.Q(Q_middle[53]) );
DFFQX1TS genblk1_left_pdt_int_reg_51_ ( .D(genblk1_left_N51), .CK(clk), .Q(
Q_left[51]) );
DFFQX1TS genblk1_middle_pdt_int_reg_55_ ( .D(genblk1_middle_N55), .CK(clk),
.Q(Q_middle[55]) );
DFFQX1TS genblk1_middle_pdt_int_reg_41_ ( .D(genblk1_middle_N41), .CK(clk),
.Q(Q_middle[41]) );
CMPR42X1TS genblk1_right_mult_x_1_U691 ( .A(genblk1_right_mult_x_1_n1477),
.B(genblk1_right_mult_x_1_n1450), .C(genblk1_right_mult_x_1_n858), .D(
genblk1_right_mult_x_1_n855), .ICI(genblk1_right_mult_x_1_n852), .S(
genblk1_right_mult_x_1_n849), .ICO(genblk1_right_mult_x_1_n847), .CO(
genblk1_right_mult_x_1_n848) );
CMPR42X1TS genblk1_left_mult_x_1_U604 ( .A(genblk1_left_mult_x_1_n695), .B(
genblk1_left_mult_x_1_n1187), .C(genblk1_left_mult_x_1_n1161), .D(
genblk1_left_mult_x_1_n1239), .ICI(genblk1_left_mult_x_1_n699), .S(
genblk1_left_mult_x_1_n693), .ICO(genblk1_left_mult_x_1_n691), .CO(
genblk1_left_mult_x_1_n692) );
CMPR42X1TS genblk1_left_mult_x_1_U545 ( .A(genblk1_left_mult_x_1_n1121), .B(
genblk1_left_mult_x_1_n542), .C(genblk1_left_mult_x_1_n537), .D(
genblk1_left_mult_x_1_n543), .ICI(genblk1_left_mult_x_1_n539), .S(
genblk1_left_mult_x_1_n534), .ICO(genblk1_left_mult_x_1_n532), .CO(
genblk1_left_mult_x_1_n533) );
CMPR42X1TS genblk1_right_mult_x_1_U578 ( .A(genblk1_right_mult_x_1_n1232),
.B(genblk1_right_mult_x_1_n556), .C(genblk1_right_mult_x_1_n557), .D(
genblk1_right_mult_x_1_n552), .ICI(genblk1_right_mult_x_1_n553), .S(
genblk1_right_mult_x_1_n549), .ICO(genblk1_right_mult_x_1_n547), .CO(
genblk1_right_mult_x_1_n548) );
CMPR42X1TS genblk1_middle_mult_x_1_U663 ( .A(n572), .B(
genblk1_middle_mult_x_1_n1011), .C(genblk1_middle_mult_x_1_n1009), .D(
genblk1_middle_mult_x_1_n1312), .ICI(genblk1_middle_mult_x_1_n1368),
.S(genblk1_middle_mult_x_1_n630), .ICO(genblk1_middle_mult_x_1_n628),
.CO(genblk1_middle_mult_x_1_n629) );
CMPR42X1TS genblk1_right_mult_x_1_U617 ( .A(genblk1_right_mult_x_1_n653),
.B(genblk1_right_mult_x_1_n664), .C(genblk1_right_mult_x_1_n650), .D(
genblk1_right_mult_x_1_n661), .ICI(genblk1_right_mult_x_1_n657), .S(
genblk1_right_mult_x_1_n647), .ICO(genblk1_right_mult_x_1_n645), .CO(
genblk1_right_mult_x_1_n646) );
CMPR42X1TS genblk1_middle_mult_x_1_U777 ( .A(genblk1_middle_mult_x_1_n1481),
.B(genblk1_middle_mult_x_1_n943), .C(genblk1_middle_mult_x_1_n936),
.D(genblk1_middle_mult_x_1_n940), .ICI(genblk1_middle_mult_x_1_n1565),
.S(genblk1_middle_mult_x_1_n934), .ICO(genblk1_middle_mult_x_1_n932),
.CO(genblk1_middle_mult_x_1_n933) );
CMPR42X1TS genblk1_middle_mult_x_1_U751 ( .A(genblk1_middle_mult_x_1_n1362),
.B(genblk1_middle_mult_x_1_n878), .C(genblk1_middle_mult_x_1_n868),
.D(genblk1_middle_mult_x_1_n1446), .ICI(genblk1_middle_mult_x_1_n872),
.S(genblk1_middle_mult_x_1_n866), .ICO(genblk1_middle_mult_x_1_n864),
.CO(genblk1_middle_mult_x_1_n865) );
CMPR42X1TS genblk1_left_mult_x_1_U562 ( .A(genblk1_left_mult_x_1_n594), .B(
genblk1_left_mult_x_1_n584), .C(genblk1_left_mult_x_1_n591), .D(
genblk1_left_mult_x_1_n581), .ICI(genblk1_left_mult_x_1_n587), .S(
genblk1_left_mult_x_1_n578), .ICO(genblk1_left_mult_x_1_n576), .CO(
genblk1_left_mult_x_1_n577) );
CMPR42X1TS genblk1_left_mult_x_1_U590 ( .A(genblk1_left_mult_x_1_n670), .B(
genblk1_left_mult_x_1_n660), .C(genblk1_left_mult_x_1_n667), .D(
genblk1_left_mult_x_1_n657), .ICI(genblk1_left_mult_x_1_n663), .S(
genblk1_left_mult_x_1_n654), .ICO(genblk1_left_mult_x_1_n652), .CO(
genblk1_left_mult_x_1_n653) );
CMPR42X1TS genblk1_right_mult_x_1_U626 ( .A(genblk1_right_mult_x_1_n677),
.B(genblk1_right_mult_x_1_n688), .C(genblk1_right_mult_x_1_n685), .D(
genblk1_right_mult_x_1_n674), .ICI(genblk1_right_mult_x_1_n681), .S(
genblk1_right_mult_x_1_n671), .ICO(genblk1_right_mult_x_1_n669), .CO(
genblk1_right_mult_x_1_n670) );
CMPR42X1TS genblk1_right_mult_x_1_U638 ( .A(genblk1_right_mult_x_1_n724),
.B(genblk1_right_mult_x_1_n713), .C(genblk1_right_mult_x_1_n721), .D(
genblk1_right_mult_x_1_n710), .ICI(genblk1_right_mult_x_1_n717), .S(
genblk1_right_mult_x_1_n707), .ICO(genblk1_right_mult_x_1_n705), .CO(
genblk1_right_mult_x_1_n706) );
CMPR42X1TS genblk1_middle_mult_x_1_U688 ( .A(genblk1_middle_mult_x_1_n703),
.B(genblk1_middle_mult_x_1_n698), .C(genblk1_middle_mult_x_1_n704),
.D(genblk1_middle_mult_x_1_n695), .ICI(genblk1_middle_mult_x_1_n700),
.S(genblk1_middle_mult_x_1_n692), .ICO(genblk1_middle_mult_x_1_n690),
.CO(genblk1_middle_mult_x_1_n691) );
DFFQX1TS genblk1_middle_pdt_int_reg_51_ ( .D(genblk1_middle_N51), .CK(clk),
.Q(Q_middle[51]) );
XOR2XLTS U2 ( .A(n1490), .B(n334), .Y(genblk1_middle_N51) );
XOR2XLTS U3 ( .A(n1615), .B(n331), .Y(genblk1_middle_N41) );
XOR2X2TS U4 ( .A(n1475), .B(n332), .Y(genblk1_middle_N49) );
CMPR32X2TS U5 ( .A(n1443), .B(n1442), .C(n1441), .CO(n1447), .S(n2820) );
CMPR32X2TS U6 ( .A(n1659), .B(n1658), .C(n1657), .CO(n1660), .S(n1665) );
OAI21X1TS U7 ( .A0(n2257), .A1(n1638), .B0(n1651), .Y(n1669) );
CMPR32X2TS U8 ( .A(n1442), .B(genblk1_right_mult_x_1_n519), .C(n1438), .CO(
n2819), .S(n1439) );
CMPR32X2TS U9 ( .A(n816), .B(n815), .C(n814), .CO(n4302), .S(n824) );
CMPR32X2TS U10 ( .A(n804), .B(n803), .C(genblk1_left_mult_x_1_n487), .CO(
n825), .S(n4304) );
NOR2X1TS U11 ( .A(n1607), .B(n1612), .Y(n1393) );
NOR2X1TS U12 ( .A(genblk1_middle_mult_x_1_n773), .B(
genblk1_middle_mult_x_1_n784), .Y(n2298) );
NAND2X1TS U13 ( .A(genblk1_middle_mult_x_1_n797), .B(
genblk1_middle_mult_x_1_n808), .Y(n2294) );
OR2X2TS U14 ( .A(genblk1_middle_mult_x_1_n893), .B(
genblk1_middle_mult_x_1_n902), .Y(n356) );
AOI21X2TS U15 ( .A0(n1311), .A1(n1721), .B0(n1310), .Y(n2602) );
CMPR42X1TS U16 ( .A(genblk1_middle_mult_x_1_n669), .B(
genblk1_middle_mult_x_1_n674), .C(genblk1_middle_mult_x_1_n675), .D(
genblk1_middle_mult_x_1_n667), .ICI(genblk1_middle_mult_x_1_n671), .S(
genblk1_middle_mult_x_1_n664), .ICO(genblk1_middle_mult_x_1_n662),
.CO(genblk1_middle_mult_x_1_n663) );
NOR2X1TS U17 ( .A(genblk1_right_mult_x_1_n671), .B(
genblk1_right_mult_x_1_n682), .Y(n2874) );
OAI21X2TS U18 ( .A0(n1309), .A1(n1727), .B0(n1308), .Y(n1721) );
NOR2X1TS U19 ( .A(genblk1_left_mult_x_1_n643), .B(genblk1_left_mult_x_1_n653), .Y(n4348) );
OR2X2TS U20 ( .A(genblk1_right_mult_x_1_n719), .B(
genblk1_right_mult_x_1_n730), .Y(n3876) );
CMPR32X2TS U21 ( .A(n2655), .B(n2654), .C(n2656), .CO(
genblk1_middle_mult_x_1_n709), .S(genblk1_middle_mult_x_1_n710) );
CMPR42X1TS U22 ( .A(genblk1_middle_mult_x_1_n1338), .B(
genblk1_middle_mult_x_1_n1310), .C(genblk1_middle_mult_x_1_n617), .D(
genblk1_middle_mult_x_1_n622), .ICI(genblk1_middle_mult_x_1_n619), .S(
genblk1_middle_mult_x_1_n615), .ICO(genblk1_middle_mult_x_1_n613),
.CO(genblk1_middle_mult_x_1_n614) );
CMPR32X2TS U23 ( .A(n2166), .B(genblk1_middle_mult_x_1_n677), .C(n1171),
.CO(genblk1_middle_mult_x_1_n668), .S(genblk1_middle_mult_x_1_n669) );
CMPR32X2TS U24 ( .A(n2757), .B(n2756), .C(n2755), .CO(
genblk1_middle_mult_x_1_n854), .S(genblk1_middle_mult_x_1_n855) );
CMPR42X1TS U25 ( .A(n4983), .B(genblk1_middle_mult_x_1_n1023), .C(
genblk1_middle_mult_x_1_n1326), .D(genblk1_middle_mult_x_1_n1382),
.ICI(genblk1_middle_mult_x_1_n1354), .S(genblk1_middle_mult_x_1_n770),
.ICO(genblk1_middle_mult_x_1_n768), .CO(genblk1_middle_mult_x_1_n769)
);
CMPR42X1TS U26 ( .A(genblk1_middle_mult_x_1_n1440), .B(
genblk1_middle_mult_x_1_n1412), .C(genblk1_middle_mult_x_1_n1468), .D(
genblk1_middle_mult_x_1_n1552), .ICI(genblk1_middle_mult_x_1_n798),
.S(genblk1_middle_mult_x_1_n791), .ICO(genblk1_middle_mult_x_1_n789),
.CO(genblk1_middle_mult_x_1_n790) );
CMPR42X1TS U27 ( .A(genblk1_middle_mult_x_1_n1419), .B(
genblk1_middle_mult_x_1_n1391), .C(genblk1_middle_mult_x_1_n879), .D(
genblk1_middle_mult_x_1_n1475), .ICI(genblk1_middle_mult_x_1_n883),
.S(genblk1_middle_mult_x_1_n877), .ICO(genblk1_middle_mult_x_1_n875),
.CO(genblk1_middle_mult_x_1_n876) );
CMPR42X1TS U28 ( .A(genblk1_middle_mult_x_1_n890), .B(
genblk1_middle_mult_x_1_n1420), .C(genblk1_middle_mult_x_1_n1392), .D(
genblk1_middle_mult_x_1_n1448), .ICI(genblk1_middle_mult_x_1_n1560),
.S(genblk1_middle_mult_x_1_n888), .ICO(genblk1_middle_mult_x_1_n886),
.CO(genblk1_middle_mult_x_1_n887) );
CMPR42X1TS U29 ( .A(genblk1_middle_mult_x_1_n974), .B(
genblk1_middle_mult_x_1_n1542), .C(genblk1_middle_mult_x_1_n970), .D(
genblk1_middle_mult_x_1_n971), .ICI(genblk1_middle_mult_x_1_n1570),
.S(genblk1_middle_mult_x_1_n968), .ICO(genblk1_middle_mult_x_1_n966),
.CO(genblk1_middle_mult_x_1_n967) );
AOI222XLTS U30 ( .A0(n2330), .A1(n2700), .B0(n2660), .B1(n2359), .C0(n309),
.C1(n2709), .Y(n1921) );
AOI222XLTS U31 ( .A0(n2348), .A1(n2556), .B0(n295), .B1(n2747), .C0(n2391),
.C1(n2582), .Y(n2183) );
AOI222XLTS U32 ( .A0(n2711), .A1(n2700), .B0(n2710), .B1(n2359), .C0(n2708),
.C1(n2709), .Y(n2237) );
AOI222XLTS U33 ( .A0(n2564), .A1(n2747), .B0(n2807), .B1(n2746), .C0(n2562),
.C1(n2669), .Y(n2015) );
AOI222XLTS U34 ( .A0(n293), .A1(n2659), .B0(n2738), .B1(n2780), .C0(n305),
.C1(n2779), .Y(n2235) );
CLKBUFX2TS U35 ( .A(n25), .Y(n2679) );
AOI222XLTS U36 ( .A0(n2749), .A1(n2671), .B0(n2748), .B1(n2670), .C0(n1961),
.C1(n2108), .Y(n2672) );
AOI222XLTS U37 ( .A0(n2711), .A1(n2729), .B0(n2710), .B1(n2709), .C0(n2708),
.C1(n2806), .Y(n2712) );
AOI222XLTS U38 ( .A0(n2740), .A1(n2761), .B0(n2674), .B1(n2228), .C0(n2736),
.C1(n2729), .Y(n1941) );
AOI222XLTS U39 ( .A0(n2703), .A1(n2737), .B0(n2702), .B1(n2803), .C0(n2701),
.C1(n2700), .Y(n2704) );
CLKBUFX2TS U40 ( .A(n1823), .Y(n2664) );
CLKBUFX2TS U41 ( .A(n1943), .Y(n2713) );
CLKBUFX2TS U42 ( .A(n1964), .Y(n2710) );
OA21XLTS U43 ( .A0(n297), .A1(n1435), .B0(n1434), .Y(n3665) );
CLKBUFX2TS U44 ( .A(n2415), .Y(n2674) );
CLKBUFX2TS U45 ( .A(n2550), .Y(n2702) );
CLKBUFX2TS U46 ( .A(n2443), .Y(n2728) );
AND3X2TS U47 ( .A(n1062), .B(n1061), .C(n1060), .Y(n1961) );
CLKBUFX2TS U48 ( .A(n1988), .Y(n2811) );
OAI21X1TS U49 ( .A0(n4066), .A1(n632), .B0(n631), .Y(n4951) );
CLKBUFX2TS U50 ( .A(n1989), .Y(n2564) );
CLKBUFX2TS U51 ( .A(n1067), .Y(n2740) );
AND3X2TS U52 ( .A(n1238), .B(n1237), .C(n1236), .Y(n2426) );
NOR2X1TS U53 ( .A(n1936), .B(n2475), .Y(n1554) );
NOR2X1TS U54 ( .A(n2030), .B(n1931), .Y(n1861) );
NOR2X1TS U55 ( .A(n2326), .B(n2454), .Y(n1840) );
CLKBUFX2TS U56 ( .A(n4706), .Y(n4766) );
CLKBUFX2TS U57 ( .A(n2355), .Y(n2454) );
CLKBUFX2TS U58 ( .A(n2456), .Y(n2222) );
XOR2X1TS U59 ( .A(n1550), .B(n1121), .Y(n2563) );
BUFX3TS U60 ( .A(n538), .Y(n1099) );
CLKBUFX2TS U61 ( .A(n4818), .Y(n4883) );
OAI21X1TS U62 ( .A0(n1550), .A1(n1549), .B0(n1548), .Y(n1553) );
CLKBUFX2TS U63 ( .A(n4886), .Y(n4922) );
CLKBUFX2TS U64 ( .A(n4947), .Y(n4928) );
CLKBUFX2TS U65 ( .A(n3773), .Y(n3579) );
NOR2X1TS U66 ( .A(n870), .B(n869), .Y(n3659) );
NOR2X1TS U67 ( .A(n278), .B(n197), .Y(n474) );
NOR2X1TS U68 ( .A(n1512), .B(n1529), .Y(n1514) );
NOR2X1TS U69 ( .A(n1153), .B(n1148), .Y(n1504) );
NOR2X1TS U70 ( .A(n1032), .B(n1360), .Y(n379) );
NOR2X1TS U71 ( .A(n1213), .B(n1224), .Y(n1184) );
NAND2X1TS U72 ( .A(n29), .B(n448), .Y(n453) );
NAND2X1TS U73 ( .A(n1120), .B(n33), .Y(n1148) );
NOR2X1TS U74 ( .A(n516), .B(n217), .Y(n1129) );
NAND2X1TS U75 ( .A(n516), .B(n217), .Y(n1128) );
NOR2X1TS U76 ( .A(n262), .B(n190), .Y(n573) );
CLKBUFX2TS U77 ( .A(Data_B_i[31]), .Y(n439) );
NAND2X1TS U78 ( .A(n834), .B(n422), .Y(n435) );
NAND2X1TS U79 ( .A(n419), .B(n245), .Y(n434) );
OR2X2TS U80 ( .A(n150), .B(n97), .Y(n1503) );
OR2X2TS U81 ( .A(n142), .B(n89), .Y(n30) );
OR2X2TS U82 ( .A(n134), .B(n81), .Y(n1091) );
NOR2X2TS U83 ( .A(n419), .B(n245), .Y(n436) );
CLKBUFX2TS U84 ( .A(Data_B_i[28]), .Y(n419) );
NAND2X1TS U85 ( .A(n241), .B(n45), .Y(n447) );
NAND2X1TS U86 ( .A(n213), .B(n65), .Y(n1134) );
NAND2X1TS U87 ( .A(n134), .B(n81), .Y(n1142) );
NAND2X1TS U88 ( .A(n142), .B(n89), .Y(n1160) );
NAND2X1TS U89 ( .A(n237), .B(n49), .Y(n444) );
INVX2TS U90 ( .A(n588), .Y(n574) );
INVX2TS U91 ( .A(n472), .Y(n464) );
INVX2TS U92 ( .A(n473), .Y(n463) );
INVX2TS U93 ( .A(n412), .Y(n402) );
INVX2TS U94 ( .A(n409), .Y(n403) );
INVX2TS U95 ( .A(n1541), .Y(n1517) );
OAI21XLTS U96 ( .A0(n1045), .A1(n576), .B0(n575), .Y(n577) );
INVX2TS U97 ( .A(n1194), .Y(n1196) );
INVX2TS U98 ( .A(n3203), .Y(n2959) );
NOR2X1TS U99 ( .A(n573), .B(n579), .Y(n594) );
OAI21XLTS U100 ( .A0(n524), .A1(n600), .B0(n601), .Y(n525) );
INVX2TS U101 ( .A(n1881), .Y(n1871) );
OR2X2TS U102 ( .A(n213), .B(n65), .Y(n17) );
INVX2TS U103 ( .A(n1074), .Y(n499) );
NOR2XLTS U104 ( .A(n249), .B(n150), .Y(n3168) );
NOR2XLTS U105 ( .A(n134), .B(n138), .Y(n3206) );
NOR2XLTS U106 ( .A(n213), .B(n209), .Y(n2980) );
NOR2X1TS U107 ( .A(n258), .B(Data_A_i[44]), .Y(n531) );
INVX2TS U108 ( .A(n1827), .Y(n1828) );
INVX2TS U109 ( .A(n1861), .Y(n1863) );
INVX2TS U110 ( .A(n1874), .Y(n1876) );
NAND2X1TS U111 ( .A(n205), .B(n73), .Y(n1122) );
NOR2XLTS U112 ( .A(n85), .B(n90), .Y(n4143) );
INVX2TS U113 ( .A(n4096), .Y(n4098) );
INVX2TS U114 ( .A(n4125), .Y(n664) );
INVX2TS U115 ( .A(n3172), .Y(n3174) );
INVX2TS U116 ( .A(n145), .Y(n146) );
OAI21XLTS U117 ( .A0(n1045), .A1(n528), .B0(n527), .Y(n529) );
AND3X2TS U118 ( .A(n1369), .B(n1368), .C(n1367), .Y(n2442) );
AOI222XLTS U119 ( .A0(n1067), .A1(n2737), .B0(n2674), .B1(n2719), .C0(n2736),
.C1(n2700), .Y(n2675) );
OAI21XLTS U120 ( .A0(n1356), .A1(n1360), .B0(n1361), .Y(n1030) );
NOR2XLTS U121 ( .A(Data_A_i[34]), .B(Data_A_i[7]), .Y(n1026) );
INVX2TS U122 ( .A(n1101), .Y(n519) );
INVX2TS U123 ( .A(n1006), .Y(n1008) );
CLKBUFX2TS U124 ( .A(n1820), .Y(n2762) );
INVX2TS U125 ( .A(n401), .Y(n396) );
NOR2XLTS U126 ( .A(n95), .B(n99), .Y(n4069) );
CLKBUFX2TS U127 ( .A(n4185), .Y(n4857) );
OAI21XLTS U128 ( .A0(n4156), .A1(n4140), .B0(n4139), .Y(n4182) );
NOR2XLTS U129 ( .A(n672), .B(n674), .Y(n692) );
OAI21XLTS U130 ( .A0(n3227), .A1(n1408), .B0(n1407), .Y(n1409) );
NOR2XLTS U131 ( .A(n3101), .B(n3105), .Y(n3091) );
OAI21XLTS U132 ( .A0(n3719), .A1(n3263), .B0(n2995), .Y(n2996) );
OAI21XLTS U133 ( .A0(n3719), .A1(n3329), .B0(n3318), .Y(n3319) );
OAI21XLTS U134 ( .A0(n3243), .A1(n3228), .B0(n3227), .Y(n3232) );
AOI222XLTS U135 ( .A0(n293), .A1(n2489), .B0(n2738), .B1(n2661), .C0(n304),
.C1(n2573), .Y(n1939) );
AOI222XLTS U136 ( .A0(n2740), .A1(n2780), .B0(n2738), .B1(n2528), .C0(n305),
.C1(n2653), .Y(n2241) );
CLKBUFX2TS U137 ( .A(n1943), .Y(n2751) );
OAI21XLTS U138 ( .A0(n2362), .A1(n423), .B0(n369), .Y(n1068) );
OAI21XLTS U139 ( .A0(n2713), .A1(n2810), .B0(n2693), .Y(n2694) );
OAI21XLTS U140 ( .A0(n1223), .A1(n1177), .B0(n1176), .Y(n1180) );
INVX2TS U141 ( .A(n3987), .Y(n639) );
XOR2X1TS U142 ( .A(n4176), .B(n4175), .Y(n4917) );
OAI21XLTS U143 ( .A0(n4963), .A1(n4599), .B0(n4615), .Y(n4616) );
OAI21XLTS U144 ( .A0(n4954), .A1(n4706), .B0(n4714), .Y(n4715) );
OAI21XLTS U145 ( .A0(n22), .A1(n4706), .B0(n4720), .Y(n4721) );
OAI21XLTS U146 ( .A0(n4954), .A1(n4818), .B0(n4826), .Y(n4827) );
OAI21XLTS U147 ( .A0(n4917), .A1(n4766), .B0(n4732), .Y(n4733) );
OAI21XLTS U148 ( .A0(n4954), .A1(n4958), .B0(n4953), .Y(n4956) );
OAI21XLTS U149 ( .A0(n3665), .A1(n3402), .B0(n3384), .Y(n3385) );
OAI21XLTS U150 ( .A0(n362), .A1(n3402), .B0(n3389), .Y(n3390) );
OAI21XLTS U151 ( .A0(n3665), .A1(n3508), .B0(n3490), .Y(n3491) );
OAI21XLTS U152 ( .A0(n3686), .A1(n3402), .B0(n3401), .Y(n3403) );
OAI21XLTS U153 ( .A0(n3689), .A1(n3416), .B0(n3404), .Y(n3405) );
OAI21XLTS U154 ( .A0(n3665), .A1(n3621), .B0(n3603), .Y(n3604) );
OAI21XLTS U155 ( .A0(n362), .A1(n3621), .B0(n3608), .Y(n3609) );
OAI21XLTS U156 ( .A0(n3665), .A1(n3685), .B0(n3664), .Y(n3666) );
OAI21XLTS U157 ( .A0(n3695), .A1(n3522), .B0(n3515), .Y(n3516) );
CLKBUFX2TS U158 ( .A(n1823), .Y(n2648) );
OAI21XLTS U159 ( .A0(n2547), .A1(n302), .B0(n1169), .Y(n1170) );
OAI21XLTS U160 ( .A0(n2357), .A1(n2506), .B0(n2338), .Y(n2339) );
OAI21XLTS U161 ( .A0(n2403), .A1(n2811), .B0(n1992), .Y(n1993) );
OAI21XLTS U162 ( .A0(n2389), .A1(n2328), .B0(n2023), .Y(n2024) );
OAI21XLTS U163 ( .A0(n2486), .A1(n2515), .B0(n2485), .Y(n2487) );
OAI21XLTS U164 ( .A0(n2318), .A1(n303), .B0(n1602), .Y(n1603) );
NOR2XLTS U165 ( .A(n629), .B(n3988), .Y(n805) );
OAI21XLTS U166 ( .A0(n4066), .A1(n4025), .B0(n4024), .Y(n4207) );
OAI21XLTS U167 ( .A0(n323), .A1(n4492), .B0(n4149), .Y(
genblk1_left_mult_x_1_n1098) );
OAI21XLTS U168 ( .A0(n23), .A1(n4466), .B0(n4151), .Y(
genblk1_left_mult_x_1_n585) );
INVX2TS U169 ( .A(n181), .Y(n183) );
OAI21XLTS U170 ( .A0(n297), .A1(n3127), .B0(n3126), .Y(n3132) );
OA21XLTS U171 ( .A0(n2116), .A1(n1631), .B0(n1630), .Y(n1632) );
OAI21XLTS U172 ( .A0(n2389), .A1(n2648), .B0(n1847), .Y(n1848) );
ADDHXLTS U173 ( .A(n2753), .B(n606), .CO(genblk1_middle_mult_x_1_n943), .S(
genblk1_middle_mult_x_1_n944) );
OAI21XLTS U174 ( .A0(n2665), .A1(n2594), .B0(n2100), .Y(n2101) );
CLKBUFX2TS U175 ( .A(n2727), .Y(n2808) );
OAI21XLTS U176 ( .A0(n1645), .A1(n1644), .B0(n1643), .Y(n1646) );
OAI21XLTS U177 ( .A0(n4066), .A1(n808), .B0(n807), .Y(n820) );
OAI21XLTS U178 ( .A0(n24), .A1(n4492), .B0(n4075), .Y(n4297) );
INVX2TS U179 ( .A(n4312), .Y(n795) );
OAI21XLTS U180 ( .A0(n4061), .A1(n4341), .B0(n4062), .Y(n781) );
NAND2X1TS U181 ( .A(n4548), .B(n4539), .Y(n702) );
OAI21XLTS U182 ( .A0(n2831), .A1(n2833), .B0(n2834), .Y(n993) );
OAI21XLTS U183 ( .A0(n2862), .A1(n984), .B0(n983), .Y(n985) );
OAI21XLTS U184 ( .A0(n2874), .A1(n3860), .B0(n2875), .Y(n977) );
CMPR42X1TS U185 ( .A(genblk1_right_mult_x_1_n1335), .B(
genblk1_right_mult_x_1_n1416), .C(genblk1_right_mult_x_1_n796), .D(
genblk1_right_mult_x_1_n1470), .ICI(genblk1_right_mult_x_1_n797), .S(
genblk1_right_mult_x_1_n784), .ICO(genblk1_right_mult_x_1_n782), .CO(
genblk1_right_mult_x_1_n783) );
NOR2X1TS U186 ( .A(n1695), .B(n2293), .Y(n1325) );
NOR2XLTS U187 ( .A(genblk1_middle_mult_x_1_n609), .B(
genblk1_middle_mult_x_1_n606), .Y(n1481) );
OAI21XLTS U188 ( .A0(n1498), .A1(n2142), .B0(n1497), .Y(n1499) );
OAI21XLTS U189 ( .A0(n4911), .A1(n4492), .B0(n4209), .Y(n4292) );
NOR2XLTS U190 ( .A(genblk1_left_mult_x_1_n501), .B(
genblk1_left_mult_x_1_n505), .Y(n4168) );
NOR2XLTS U191 ( .A(genblk1_left_mult_x_1_n610), .B(
genblk1_left_mult_x_1_n620), .Y(n4044) );
NOR2XLTS U192 ( .A(genblk1_left_mult_x_1_n795), .B(
genblk1_left_mult_x_1_n799), .Y(n3970) );
NOR2XLTS U193 ( .A(genblk1_right_mult_x_1_n542), .B(
genblk1_right_mult_x_1_n537), .Y(n2833) );
INVX2TS U194 ( .A(n3884), .Y(n971) );
CLKBUFX2TS U195 ( .A(n2223), .Y(n2795) );
NOR2X1TS U196 ( .A(genblk1_middle_mult_x_1_n664), .B(
genblk1_middle_mult_x_1_n672), .Y(n1607) );
OAI21XLTS U197 ( .A0(n367), .A1(n4505), .B0(n823), .Y(n827) );
OAI21XLTS U198 ( .A0(n4900), .A1(n4505), .B0(n3949), .Y(
genblk1_left_mult_x_1_n1094) );
OAI21XLTS U199 ( .A0(n4117), .A1(n799), .B0(n798), .Y(n4077) );
NOR2XLTS U200 ( .A(genblk1_left_mult_x_1_n534), .B(
genblk1_left_mult_x_1_n540), .Y(n4320) );
INVX2TS U201 ( .A(n4085), .Y(n4087) );
OAI21XLTS U202 ( .A0(n4347), .A1(n4043), .B0(n4042), .Y(n4049) );
INVX2TS U203 ( .A(n2839), .Y(n2840) );
INVX2TS U204 ( .A(n2849), .Y(n2851) );
NOR2XLTS U205 ( .A(genblk1_right_mult_x_1_n659), .B(
genblk1_right_mult_x_1_n670), .Y(n3854) );
INVX2TS U206 ( .A(n2893), .Y(n2895) );
OR2X1TS U207 ( .A(n949), .B(n948), .Y(n3930) );
INVX2TS U208 ( .A(n1494), .Y(n1495) );
OR2X1TS U209 ( .A(genblk1_middle_mult_x_1_n647), .B(
genblk1_middle_mult_x_1_n654), .Y(n1667) );
INVX2TS U210 ( .A(n1616), .Y(n1673) );
INVX2TS U211 ( .A(n1681), .Y(n1684) );
INVX2TS U212 ( .A(n2303), .Y(n2304) );
INVX2TS U213 ( .A(n2629), .Y(n2631) );
INVX2TS U214 ( .A(n4307), .Y(n4315) );
OAI21XLTS U215 ( .A0(n4108), .A1(n4107), .B0(n4106), .Y(n4340) );
INVX2TS U216 ( .A(n3998), .Y(n4367) );
OAI21XLTS U217 ( .A0(n3965), .A1(n3968), .B0(n3966), .Y(n4399) );
OAI21XLTS U218 ( .A0(n3816), .A1(n3812), .B0(n3813), .Y(n2853) );
OAI21XLTS U219 ( .A0(n3858), .A1(n3854), .B0(n3855), .Y(n2870) );
OAI21XLTS U220 ( .A0(n3887), .A1(n2886), .B0(n3884), .Y(n2889) );
OAI21XLTS U221 ( .A0(n2302), .A1(n2298), .B0(n2299), .Y(n1691) );
OAI21XLTS U222 ( .A0(n2382), .A1(n1704), .B0(n1703), .Y(n2366) );
XNOR2X1TS U223 ( .A(n1626), .B(n1625), .Y(genblk1_middle_N37) );
OR2X2TS U224 ( .A(n225), .B(n57), .Y(n3) );
INVX2TS U225 ( .A(n1462), .Y(n1463) );
INVX2TS U226 ( .A(n1644), .Y(n1605) );
INVX2TS U227 ( .A(n2272), .Y(n1654) );
OAI21XLTS U228 ( .A0(n2618), .A1(n2614), .B0(n2615), .Y(n1735) );
INVX2TS U229 ( .A(n1498), .Y(n1489) );
OAI21XLTS U230 ( .A0(n3883), .A1(n3879), .B0(n3880), .Y(n2897) );
AOI21X1TS U231 ( .A0(n357), .A1(n2603), .B0(n1307), .Y(n1308) );
AOI21X1TS U232 ( .A0(n1737), .A1(n1738), .B0(n1304), .Y(n2622) );
OAI21X1TS U233 ( .A0(n2318), .A1(n2684), .B0(n1927), .Y(n1928) );
INVX2TS U234 ( .A(n2799), .Y(n2285) );
OAI21X1TS U235 ( .A0(n2389), .A1(n2491), .B0(n2377), .Y(n2378) );
OAI21XLTS U236 ( .A0(n2685), .A1(n302), .B0(n1634), .Y(n1635) );
INVX2TS U237 ( .A(n4341), .Y(n4060) );
XOR2X1TS U238 ( .A(n1799), .B(n1798), .Y(n2389) );
OAI21X1TS U239 ( .A0(n2123), .A1(n1829), .B0(n1828), .Y(n1830) );
INVX2TS U240 ( .A(n4165), .Y(n4166) );
OAI21X1TS U241 ( .A0(n4111), .A1(n4337), .B0(n4112), .Y(n783) );
INVX2TS U242 ( .A(n4083), .Y(n4334) );
INVX2TS U243 ( .A(n3825), .Y(n3818) );
INVX2TS U244 ( .A(n4046), .Y(n4047) );
INVX2TS U245 ( .A(n4337), .Y(n4110) );
OAI21X1TS U246 ( .A0(n4328), .A1(n4325), .B0(n4329), .Y(n789) );
INVX2TS U247 ( .A(n3820), .Y(n3822) );
INVX2TS U248 ( .A(n4079), .Y(n800) );
INVX2TS U249 ( .A(n292), .Y(n293) );
INVX2TS U250 ( .A(n294), .Y(n295) );
CLKBUFX2TS U251 ( .A(n1925), .Y(n2362) );
CLKAND2X2TS U252 ( .A(n2511), .B(n2802), .Y(n2170) );
CLKAND2X2TS U253 ( .A(n2544), .B(n2802), .Y(genblk1_middle_mult_x_1_n1011)
);
CLKBUFX2TS U254 ( .A(n1925), .Y(n2742) );
CLKBUFX2TS U255 ( .A(n1943), .Y(n2524) );
BUFX3TS U256 ( .A(n2223), .Y(n2771) );
BUFX4TS U257 ( .A(n2006), .Y(n2475) );
XOR2XLTS U258 ( .A(n4666), .B(n196), .Y(genblk1_left_mult_x_1_n1174) );
BUFX3TS U259 ( .A(n2559), .Y(n2573) );
CLKBUFX2TS U260 ( .A(n1988), .Y(n2445) );
XOR2XLTS U261 ( .A(n3571), .B(n272), .Y(genblk1_right_mult_x_1_n1415) );
XOR2XLTS U262 ( .A(n3288), .B(n256), .Y(genblk1_right_mult_x_1_n1261) );
CLKBUFX2TS U263 ( .A(n1988), .Y(n2566) );
INVX2TS U264 ( .A(n4292), .Y(n4296) );
OAI21XLTS U265 ( .A0(n26), .A1(n3291), .B0(n3275), .Y(n3276) );
OAI21XLTS U266 ( .A0(n362), .A1(n3291), .B0(n3277), .Y(n3278) );
INVX2TS U267 ( .A(n828), .Y(n816) );
XNOR2X1TS U268 ( .A(n1545), .B(n1544), .Y(n1931) );
OAI21XLTS U269 ( .A0(n3665), .A1(n3345), .B0(n2943), .Y(n2944) );
OAI21XLTS U270 ( .A0(n3665), .A1(n3291), .B0(n3272), .Y(n3273) );
XOR2X1TS U271 ( .A(n4038), .B(n4037), .Y(n4963) );
INVX2TS U272 ( .A(n1088), .Y(n1133) );
XOR2XLTS U273 ( .A(n658), .B(n183), .Y(n701) );
INVX2TS U274 ( .A(n3113), .Y(n3114) );
OAI21XLTS U275 ( .A0(n4541), .A1(n4766), .B0(n4232), .Y(n4233) );
XOR2X1TS U276 ( .A(n1223), .B(n565), .Y(result_A_adder_2_) );
INVX2TS U277 ( .A(n3136), .Y(n3122) );
INVX2TS U278 ( .A(n459), .Y(n450) );
CLKBUFX2TS U279 ( .A(n3578), .Y(n3599) );
CLKBUFX2TS U280 ( .A(n3524), .Y(n3522) );
NAND2X1TS U281 ( .A(n31), .B(n1539), .Y(n1568) );
CLKBUFX2TS U282 ( .A(n3602), .Y(n3636) );
NAND2BX1TS U283 ( .AN(n2970), .B(n2971), .Y(n2983) );
NAND3X1TS U284 ( .A(n2971), .B(n2970), .C(n1425), .Y(n3265) );
CLKBUFX2TS U285 ( .A(n3659), .Y(n3642) );
NAND2BXLTS U286 ( .AN(n838), .B(n839), .Y(n3578) );
NOR2X1TS U287 ( .A(n241), .B(n45), .Y(n443) );
CLKBUFX2TS U288 ( .A(n423), .Y(n424) );
NAND2BXLTS U289 ( .AN(n869), .B(n870), .Y(n3602) );
OAI21X2TS U290 ( .A0(n436), .A1(n435), .B0(n434), .Y(n459) );
NOR2X2TS U291 ( .A(n439), .B(n233), .Y(n456) );
INVX2TS U292 ( .A(n2990), .Y(n2992) );
NOR2X1TS U293 ( .A(n162), .B(n109), .Y(n1576) );
INVX2TS U294 ( .A(n261), .Y(n262) );
INVX2TS U295 ( .A(n133), .Y(n134) );
INVX2TS U296 ( .A(n410), .Y(n411) );
INVX2TS U297 ( .A(n567), .Y(n569) );
INVX2TS U298 ( .A(n539), .Y(n540) );
INVX2TS U299 ( .A(n834), .Y(n3079) );
INVX2TS U300 ( .A(Data_A_i[11]), .Y(n265) );
NOR2X2TS U301 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n1213) );
NAND2X4TS U302 ( .A(Data_A_i[30]), .B(Data_A_i[3]), .Y(n1217) );
NOR2X2TS U303 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n579) );
NAND2X2TS U304 ( .A(Data_A_i[27]), .B(Data_A_i[0]), .Y(n570) );
BUFX3TS U305 ( .A(Data_B_i[0]), .Y(n834) );
XNOR2X1TS U306 ( .A(n1662), .B(n1661), .Y(genblk1_middle_N55) );
XOR2XLTS U307 ( .A(n1454), .B(n1453), .Y(genblk1_middle_N43) );
AOI21X1TS U308 ( .A0(n1669), .A1(n1667), .B0(n1450), .Y(n1454) );
INVX6TS U309 ( .A(n1390), .Y(n2257) );
OAI21X1TS U310 ( .A0(n2382), .A1(n1707), .B0(n2379), .Y(n1711) );
INVX2TS U311 ( .A(n1636), .Y(n1502) );
INVX1TS U312 ( .A(n1651), .Y(n1397) );
INVX1TS U313 ( .A(n1648), .Y(n1478) );
CLKINVX2TS U314 ( .A(n1712), .Y(n2468) );
INVX1TS U315 ( .A(n1609), .Y(n1610) );
INVX1TS U316 ( .A(n1608), .Y(n1611) );
OAI21X1TS U317 ( .A0(n2589), .A1(n2585), .B0(n2586), .Y(n1720) );
INVX2TS U318 ( .A(n2275), .Y(n2276) );
INVX1TS U319 ( .A(n1468), .Y(n1395) );
OAI21X1TS U320 ( .A0(n1622), .A1(n1672), .B0(n1623), .Y(n1382) );
NOR2X1TS U321 ( .A(n1461), .B(n1467), .Y(n1637) );
AOI21X1TS U322 ( .A0(n1452), .A1(n1450), .B0(n1394), .Y(n1468) );
OAI21X1TS U323 ( .A0(n4327), .A1(n4326), .B0(n4325), .Y(n4332) );
INVX2TS U324 ( .A(n1612), .Y(n1614) );
INVX1TS U325 ( .A(n2379), .Y(n1318) );
OAI21X1TS U326 ( .A0(n4347), .A1(n4346), .B0(n4345), .Y(n4352) );
OAI21X1TS U327 ( .A0(n1716), .A1(n2586), .B0(n1717), .Y(n1312) );
AOI21X2TS U328 ( .A0(n1730), .A1(n1306), .B0(n1305), .Y(n1727) );
NAND2X1TS U329 ( .A(genblk1_middle_mult_x_1_n913), .B(
genblk1_middle_mult_x_1_n922), .Y(n2586) );
OAI21X1TS U330 ( .A0(n2318), .A1(n2811), .B0(n2196), .Y(n2197) );
OAI21X1TS U331 ( .A0(n2318), .A1(n2524), .B0(n1945), .Y(n1946) );
OAI21X1TS U332 ( .A0(n2389), .A1(n2362), .B0(n1929), .Y(n1930) );
INVX1TS U333 ( .A(n3854), .Y(n3856) );
OAI21X1TS U334 ( .A0(n2535), .A1(n2713), .B0(n1962), .Y(n1963) );
INVX1TS U335 ( .A(n2866), .Y(n2868) );
XOR2X1TS U336 ( .A(n1830), .B(n344), .Y(n2799) );
AOI21X1TS U337 ( .A0(n978), .A1(n2872), .B0(n977), .Y(n979) );
OAI21X1TS U338 ( .A0(n2685), .A1(n2393), .B0(n1824), .Y(n1825) );
INVX1TS U339 ( .A(n3859), .Y(n3861) );
XOR2X1TS U340 ( .A(n1903), .B(n1902), .Y(n2535) );
XOR2X1TS U341 ( .A(n1168), .B(n1167), .Y(n2547) );
OAI21X1TS U342 ( .A0(n2685), .A1(n2445), .B0(n2200), .Y(n2201) );
AOI21X1TS U343 ( .A0(n3844), .A1(n3841), .B0(n987), .Y(n2846) );
NOR2X1TS U344 ( .A(n4346), .B(n4348), .Y(n4055) );
INVX1TS U345 ( .A(n4326), .Y(n4092) );
INVX1TS U346 ( .A(n3812), .Y(n3814) );
INVX1TS U347 ( .A(n4050), .Y(n4052) );
INVX1TS U348 ( .A(n3864), .Y(n3865) );
NOR2X1TS U349 ( .A(n4050), .B(n4044), .Y(n4104) );
OAI21XLTS U350 ( .A0(n19), .A1(n2664), .B0(n1919), .Y(n1920) );
INVX1TS U351 ( .A(n3868), .Y(n3870) );
INVX1TS U352 ( .A(n4328), .Y(n4330) );
INVX1TS U353 ( .A(n4320), .Y(n4322) );
NOR2X1TS U354 ( .A(n4326), .B(n4328), .Y(n790) );
INVX1TS U355 ( .A(n4333), .Y(n4084) );
NOR2X1TS U356 ( .A(genblk1_left_mult_x_1_n569), .B(
genblk1_left_mult_x_1_n577), .Y(n4083) );
AOI21X1TS U357 ( .A0(n353), .A1(n2923), .B0(n954), .Y(n2920) );
OAI21X1TS U358 ( .A0(n2901), .A1(n3898), .B0(n2902), .Y(n964) );
BUFX4TS U359 ( .A(n291), .Y(n2778) );
XOR2XLTS U360 ( .A(n1341), .B(n2706), .Y(n2179) );
OAI21X1TS U361 ( .A0(n952), .A1(n2926), .B0(n951), .Y(n2923) );
CLKBUFX2TS U362 ( .A(n1823), .Y(n2393) );
XOR2XLTS U363 ( .A(n1209), .B(n2724), .Y(n1285) );
INVX2TS U364 ( .A(n1840), .Y(n1842) );
OAI21XLTS U365 ( .A0(n2328), .A1(n2810), .B0(n1208), .Y(n1209) );
INVX1TS U366 ( .A(n1813), .Y(n1815) );
INVX2TS U367 ( .A(n1849), .Y(n1851) );
CLKBUFX2TS U368 ( .A(n1925), .Y(n2684) );
BUFX3TS U369 ( .A(n1980), .Y(n2491) );
BUFX3TS U370 ( .A(n1961), .Y(n2708) );
NOR2X1TS U371 ( .A(n2454), .B(n2222), .Y(n1791) );
BUFX3TS U372 ( .A(n2479), .Y(n2701) );
XOR2XLTS U373 ( .A(n1447), .B(n1446), .Y(n1448) );
NOR2X1TS U374 ( .A(n2345), .B(n1953), .Y(n1813) );
BUFX4TS U375 ( .A(n2479), .Y(n2549) );
XNOR2X1TS U376 ( .A(n427), .B(n426), .Y(n558) );
BUFX3TS U377 ( .A(n2442), .Y(n2726) );
XOR2X1TS U378 ( .A(n3609), .B(n275), .Y(genblk1_right_mult_x_1_n1436) );
INVX2TS U379 ( .A(n4297), .Y(genblk1_left_mult_x_1_n517) );
BUFX3TS U380 ( .A(n1931), .Y(n2680) );
NOR2X1TS U381 ( .A(n1904), .B(n1936), .Y(n1899) );
XOR2XLTS U382 ( .A(n4908), .B(n179), .Y(genblk1_left_mult_x_1_n1292) );
XOR2XLTS U383 ( .A(n4833), .B(n183), .Y(genblk1_left_mult_x_1_n1261) );
XOR2XLTS U384 ( .A(n4476), .B(n198), .Y(n4477) );
XNOR2X1TS U385 ( .A(n1591), .B(n175), .Y(n2456) );
XOR2X1TS U386 ( .A(n418), .B(n286), .Y(n1100) );
XNOR2X2TS U387 ( .A(n1553), .B(n1552), .Y(n2243) );
XNOR2X1TS U388 ( .A(n1536), .B(n1535), .Y(n1953) );
OAI21X1TS U389 ( .A0(n320), .A1(n4505), .B0(n4034), .Y(
genblk1_left_mult_x_1_n1096) );
INVX2TS U390 ( .A(n399), .Y(n408) );
XOR2XLTS U391 ( .A(n3523), .B(n267), .Y(genblk1_right_mult_x_1_n1388) );
XOR2XLTS U392 ( .A(n4496), .B(n195), .Y(n4497) );
XOR2X1TS U393 ( .A(n415), .B(Data_A_i[25]), .Y(n427) );
OAI21X1TS U394 ( .A0(n333), .A1(n4505), .B0(n650), .Y(n803) );
OAI21X1TS U395 ( .A0(n22), .A1(n4505), .B0(n3997), .Y(
genblk1_left_mult_x_1_n1095) );
XNOR2X1TS U396 ( .A(n1093), .B(n1092), .Y(n1904) );
XOR2XLTS U397 ( .A(n4937), .B(n180), .Y(genblk1_left_mult_x_1_n1302) );
XOR2XLTS U398 ( .A(n4454), .B(n202), .Y(n4455) );
XNOR2X2TS U399 ( .A(n1156), .B(n1155), .Y(n2006) );
OAI21X1TS U400 ( .A0(n326), .A1(n4505), .B0(n4103), .Y(
genblk1_left_mult_x_1_n1099) );
XNOR2X1TS U401 ( .A(n1580), .B(n1579), .Y(n1950) );
NOR2X2TS U402 ( .A(n1591), .B(n176), .Y(n1592) );
XOR2X1TS U403 ( .A(n1424), .B(n41), .Y(n26) );
ADDHXLTS U404 ( .A(n3063), .B(n3062), .CO(n3059), .S(
genblk1_right_mult_x_1_n838) );
XOR2X1TS U405 ( .A(n478), .B(n477), .Y(n547) );
OAI21X1TS U406 ( .A0(n4917), .A1(n4492), .B0(n4178), .Y(
genblk1_left_mult_x_1_n1097) );
OAI21X1TS U407 ( .A0(n1550), .A1(n1162), .B0(n1161), .Y(n1165) );
OAI21X1TS U408 ( .A0(n1550), .A1(n1148), .B0(n1154), .Y(n1093) );
OAI21X1TS U409 ( .A0(n1550), .A1(n1145), .B0(n1144), .Y(n1147) );
XOR2X1TS U410 ( .A(n398), .B(n397), .Y(n399) );
XOR2X1TS U411 ( .A(n3164), .B(n3163), .Y(n3686) );
XNOR2X1TS U412 ( .A(n2567), .B(n1051), .Y(n1054) );
ADDHX1TS U413 ( .A(n4510), .B(n4509), .CO(n4511), .S(
genblk1_left_mult_x_1_n695) );
OAI21X1TS U414 ( .A0(n4954), .A1(n4505), .B0(n811), .Y(n828) );
AOI21X1TS U415 ( .A0(n1572), .A1(n1571), .B0(n1570), .Y(n1577) );
AOI21X2TS U416 ( .A0(n1133), .A1(n503), .B0(n506), .Y(n497) );
OAI21X1TS U417 ( .A0(n297), .A1(n3115), .B0(n3114), .Y(n3119) );
XOR2X1TS U418 ( .A(n4423), .B(n4422), .Y(n18) );
OAI21X1TS U419 ( .A0(n296), .A1(n3182), .B0(n3181), .Y(n3186) );
INVX6TS U420 ( .A(n1572), .Y(n1550) );
XOR2X1TS U421 ( .A(n1041), .B(n1040), .Y(n1051) );
OAI21X1TS U422 ( .A0(n4066), .A1(n3988), .B0(n3987), .Y(n4038) );
OAI21X1TS U423 ( .A0(n4156), .A1(n4133), .B0(n4135), .Y(n4423) );
BUFX3TS U424 ( .A(n1359), .Y(n1200) );
INVX2TS U425 ( .A(n28), .Y(n296) );
INVX2TS U426 ( .A(n28), .Y(n297) );
NOR2XLTS U427 ( .A(n1095), .B(n286), .Y(n1098) );
OAI21X1TS U428 ( .A0(n1114), .A1(n1130), .B0(n1113), .Y(n1115) );
INVX2TS U429 ( .A(n806), .Y(n807) );
INVX2TS U430 ( .A(n805), .Y(n808) );
INVX2TS U431 ( .A(n1515), .Y(n1530) );
INVX2TS U432 ( .A(n522), .Y(n1359) );
OAI21XLTS U433 ( .A0(n4541), .A1(n4883), .B0(n657), .Y(n658) );
XNOR2X1TS U434 ( .A(n442), .B(n441), .Y(n1078) );
INVX1TS U435 ( .A(n1356), .Y(n1357) );
XNOR2X1TS U436 ( .A(n1180), .B(n1179), .Y(n2336) );
XNOR2X1TS U437 ( .A(n446), .B(n445), .Y(n1023) );
NOR2X1TS U438 ( .A(n1521), .B(n1568), .Y(n1581) );
OAI21X1TS U439 ( .A0(n450), .A1(n453), .B0(n455), .Y(n442) );
NOR2X1TS U440 ( .A(n1355), .B(n1360), .Y(n1031) );
OAI21XLTS U441 ( .A0(n3079), .A1(n3765), .B0(n3067), .Y(n3068) );
NAND2X1TS U442 ( .A(n1509), .B(n1506), .Y(n1164) );
OAI21X1TS U443 ( .A0(n450), .A1(n443), .B0(n447), .Y(n446) );
INVX1TS U444 ( .A(n4152), .Y(n4155) );
OAI21X1TS U445 ( .A0(n585), .A1(n387), .B0(n386), .Y(n388) );
OAI21XLTS U446 ( .A0(n4541), .A1(n4654), .B0(n4246), .Y(n4247) );
OAI21X1TS U447 ( .A0(n1128), .A1(n1083), .B0(n1082), .Y(n1084) );
AOI21X1TS U448 ( .A0(n1509), .A1(n1508), .B0(n1507), .Y(n1528) );
AOI21X1TS U449 ( .A0(n34), .A1(n1151), .B0(n1150), .Y(n1152) );
AOI21X1TS U450 ( .A0(n379), .A1(n1028), .B0(n378), .Y(n380) );
OAI21X1TS U451 ( .A0(n1223), .A1(n1193), .B0(n1192), .Y(n1198) );
NAND2X1TS U452 ( .A(n1505), .B(n1573), .Y(n1521) );
NAND2X1TS U453 ( .A(n1203), .B(n1345), .Y(n1204) );
NOR2X2TS U454 ( .A(n1129), .B(n1083), .Y(n1085) );
INVX2TS U455 ( .A(n3139), .Y(n3141) );
NOR2X1TS U456 ( .A(n644), .B(n642), .Y(n627) );
NAND2X2TS U457 ( .A(n1091), .B(n34), .Y(n1153) );
NOR2X1TS U458 ( .A(n4094), .B(n4096), .Y(n4137) );
NOR2X1TS U459 ( .A(n3206), .B(n2965), .Y(n1406) );
INVX1TS U460 ( .A(n593), .Y(n524) );
AOI21X2TS U461 ( .A0(n33), .A1(n1090), .B0(n1089), .Y(n1154) );
NOR2X1TS U462 ( .A(n4141), .B(n4143), .Y(n619) );
NAND2X1TS U463 ( .A(n1091), .B(n1142), .Y(n1092) );
INVX2TS U464 ( .A(n3189), .Y(n3191) );
INVX1TS U465 ( .A(n2989), .Y(n853) );
INVX1TS U466 ( .A(n1211), .Y(n1220) );
NOR2X1TS U467 ( .A(n147), .B(n150), .Y(n3189) );
NAND2BX1TS U468 ( .AN(n3007), .B(n3008), .Y(n3047) );
NOR2X1TS U469 ( .A(n4026), .B(n4028), .Y(n625) );
OR2X4TS U470 ( .A(n237), .B(n49), .Y(n29) );
INVX2TS U471 ( .A(n1241), .Y(n1242) );
OAI21X1TS U472 ( .A0(n531), .A1(n601), .B0(n532), .Y(n384) );
NOR2X1TS U473 ( .A(n130), .B(n134), .Y(n3219) );
NAND2X1TS U474 ( .A(n33), .B(n1124), .Y(n1125) );
NOR2X2TS U475 ( .A(n146), .B(n93), .Y(n1163) );
NAND2BXLTS U476 ( .AN(n3070), .B(n3071), .Y(n3524) );
NOR2X1TS U477 ( .A(n142), .B(n146), .Y(n3196) );
NOR2X1TS U478 ( .A(n62), .B(n4857), .Y(n4125) );
NAND2X2TS U479 ( .A(n17), .B(n35), .Y(n1083) );
NOR2X1TS U480 ( .A(n1188), .B(n1194), .Y(n373) );
NOR2X2TS U481 ( .A(Data_A_i[8]), .B(n182), .Y(n1346) );
NAND2X1TS U482 ( .A(n30), .B(n1160), .Y(n1155) );
NAND2X1TS U483 ( .A(n34), .B(n1149), .Y(n1146) );
INVX2TS U484 ( .A(n3168), .Y(n3184) );
NOR2X1TS U485 ( .A(n130), .B(n205), .Y(n3213) );
NOR2X1TS U486 ( .A(n142), .B(n138), .Y(n2965) );
INVX2TS U487 ( .A(n232), .Y(n233) );
INVX2TS U488 ( .A(n216), .Y(n218) );
NAND2X1TS U489 ( .A(n130), .B(n77), .Y(n1124) );
NOR2X1TS U490 ( .A(n225), .B(n229), .Y(n913) );
INVX2TS U491 ( .A(n220), .Y(n221) );
INVX2TS U492 ( .A(n165), .Y(n166) );
XOR2X1TS U493 ( .A(n571), .B(n570), .Y(n1241) );
INVX2TS U494 ( .A(n108), .Y(n109) );
NOR2X1TS U495 ( .A(n67), .B(n71), .Y(n4157) );
INVX2TS U496 ( .A(n236), .Y(n237) );
INVX1TS U497 ( .A(n1186), .Y(n1189) );
BUFX3TS U498 ( .A(n439), .Y(n4944) );
INVX2TS U499 ( .A(n236), .Y(n239) );
XOR2X1TS U500 ( .A(n197), .B(Data_A_i[46]), .Y(n4260) );
XOR2X1TS U501 ( .A(n278), .B(Data_A_i[19]), .Y(n3008) );
INVX2TS U502 ( .A(Data_A_i[38]), .Y(n185) );
XOR2X1TS U503 ( .A(Data_A_i[44]), .B(Data_A_i[43]), .Y(n4250) );
OAI21X1TS U504 ( .A0(n1224), .A1(n1217), .B0(n1225), .Y(n1186) );
INVX2TS U505 ( .A(Data_A_i[28]), .Y(n667) );
NAND2X1TS U506 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n539) );
OR2X2TS U507 ( .A(Data_A_i[51]), .B(Data_A_i[24]), .Y(n365) );
INVX2TS U508 ( .A(Data_A_i[0]), .Y(n855) );
INVX2TS U509 ( .A(Data_A_i[1]), .Y(n856) );
NOR2X1TS U510 ( .A(Data_A_i[28]), .B(Data_A_i[1]), .Y(n567) );
XOR2XLTS U511 ( .A(n1401), .B(n1400), .Y(genblk1_middle_N45) );
XOR2XLTS U512 ( .A(n1606), .B(n343), .Y(genblk1_middle_N52) );
OAI2BB1X2TS U513 ( .A0N(n2151), .A1N(n2153), .B0(n2150), .Y(n1615) );
OAI2BB1X2TS U514 ( .A0N(n2143), .A1N(n2145), .B0(n2142), .Y(n1490) );
XOR2XLTS U515 ( .A(n1335), .B(n1334), .Y(genblk1_middle_N35) );
OAI21X1TS U516 ( .A0(n2257), .A1(n1496), .B0(n1495), .Y(n2139) );
XOR2XLTS U517 ( .A(n833), .B(n832), .Y(genblk1_left_N51) );
NOR2X1TS U518 ( .A(n1636), .B(n1644), .Y(n1647) );
INVX1TS U519 ( .A(n1379), .Y(n1331) );
OAI21X1TS U520 ( .A0(n1651), .A1(n1479), .B0(n1478), .Y(n1494) );
NOR2X1TS U521 ( .A(n1638), .B(n1479), .Y(n1493) );
NAND2X1TS U522 ( .A(n1492), .B(n1500), .Y(n1636) );
AOI21X1TS U523 ( .A0(n1329), .A1(n1682), .B0(n1328), .Y(n1386) );
INVX1TS U524 ( .A(n1682), .Y(n1683) );
INVX1TS U525 ( .A(n1687), .Y(n1689) );
OAI21X1TS U526 ( .A0(n1468), .A1(n1467), .B0(n1466), .Y(n1648) );
OAI21X1TS U527 ( .A0(n2275), .A1(n2279), .B0(n2280), .Y(n1328) );
INVX1TS U528 ( .A(n1670), .Y(n2264) );
OAI21X1TS U529 ( .A0(n2299), .A1(n1687), .B0(n1688), .Y(n1682) );
INVX1TS U530 ( .A(n1618), .Y(n1619) );
INVX1TS U531 ( .A(n2262), .Y(n2263) );
INVX1TS U532 ( .A(n1617), .Y(n1620) );
OAI21X1TS U533 ( .A0(n4307), .A1(n4306), .B0(n4312), .Y(n4311) );
OAI21X1TS U534 ( .A0(n3850), .A1(n2830), .B0(n2829), .Y(n3819) );
INVX1TS U535 ( .A(n2265), .Y(n2267) );
NOR2X2TS U536 ( .A(genblk1_middle_mult_x_1_n761), .B(
genblk1_middle_mult_x_1_n772), .Y(n1687) );
INVX1TS U537 ( .A(n1378), .Y(n1677) );
INVX1TS U538 ( .A(n1676), .Y(n1332) );
CLKAND2X2TS U539 ( .A(n1614), .B(n1613), .Y(n331) );
INVX1TS U540 ( .A(n1461), .Y(n1396) );
AOI21X2TS U541 ( .A0(n1709), .A1(n1318), .B0(n1317), .Y(n1703) );
OAI21X1TS U542 ( .A0(n4161), .A1(n4320), .B0(n4321), .Y(n4319) );
NOR2X1TS U543 ( .A(n1476), .B(n1481), .Y(n1483) );
INVX1TS U544 ( .A(n1700), .Y(n2305) );
NOR2X2TS U545 ( .A(genblk1_middle_mult_x_1_n785), .B(
genblk1_middle_mult_x_1_n796), .Y(n1695) );
OAI21X1TS U546 ( .A0(n3858), .A1(n2861), .B0(n2860), .Y(n3836) );
NOR2X1TS U547 ( .A(genblk1_middle_mult_x_1_n725), .B(
genblk1_middle_mult_x_1_n736), .Y(n1378) );
NAND2X1TS U548 ( .A(n1667), .B(n1452), .Y(n1461) );
INVX1TS U549 ( .A(n1481), .Y(n1474) );
CLKAND2X2TS U550 ( .A(n1489), .B(n1497), .Y(n334) );
INVX1TS U551 ( .A(n2136), .Y(n1469) );
NOR2X2TS U552 ( .A(genblk1_middle_mult_x_1_n655), .B(
genblk1_middle_mult_x_1_n663), .Y(n1612) );
OAI21X2TS U553 ( .A0(n980), .A1(n2871), .B0(n979), .Y(n2824) );
OR2X2TS U554 ( .A(genblk1_middle_mult_x_1_n640), .B(
genblk1_middle_mult_x_1_n646), .Y(n1452) );
NOR2X1TS U555 ( .A(genblk1_middle_mult_x_1_n602), .B(
genblk1_middle_mult_x_1_n605), .Y(n1491) );
NOR2X1TS U556 ( .A(genblk1_middle_mult_x_1_n621), .B(
genblk1_middle_mult_x_1_n626), .Y(n1477) );
OAI21X1TS U557 ( .A0(n4347), .A1(n4058), .B0(n4057), .Y(n4344) );
NOR2X1TS U558 ( .A(genblk1_middle_mult_x_1_n598), .B(n1604), .Y(n1644) );
NOR2X2TS U559 ( .A(genblk1_middle_mult_x_1_n923), .B(
genblk1_middle_mult_x_1_n930), .Y(n2598) );
NAND2X1TS U560 ( .A(genblk1_middle_mult_x_1_n893), .B(
genblk1_middle_mult_x_1_n902), .Y(n1713) );
NOR2X1TS U561 ( .A(genblk1_middle_mult_x_1_n599), .B(
genblk1_middle_mult_x_1_n601), .Y(n1498) );
INVX1TS U562 ( .A(n1731), .Y(n1733) );
XOR2XLTS U563 ( .A(n2212), .B(n2686), .Y(genblk1_middle_mult_x_1_n1368) );
INVX1TS U564 ( .A(n2900), .Y(n3901) );
INVX3TS U565 ( .A(n2774), .Y(n2318) );
NAND2X1TS U566 ( .A(genblk1_middle_mult_x_1_n968), .B(
genblk1_middle_mult_x_1_n972), .Y(n2615) );
XNOR2X2TS U567 ( .A(n563), .B(n1336), .Y(genblk1_middle_mult_x_1_n829) );
XOR2XLTS U568 ( .A(n2253), .B(n2424), .Y(genblk1_middle_mult_x_1_n1375) );
INVX1TS U569 ( .A(n2859), .Y(n2860) );
INVX1TS U570 ( .A(n2858), .Y(n2861) );
XOR2XLTS U571 ( .A(n2536), .B(n2800), .Y(genblk1_middle_mult_x_1_n1536) );
XOR2XLTS U572 ( .A(n2404), .B(n2507), .Y(genblk1_middle_mult_x_1_n1433) );
AOI21X1TS U573 ( .A0(n963), .A1(n2906), .B0(n962), .Y(n3906) );
INVX1TS U574 ( .A(n2828), .Y(n2829) );
INVX1TS U575 ( .A(n2827), .Y(n2830) );
ADDFX1TS U576 ( .A(n2789), .B(n2788), .CI(n2787), .CO(
genblk1_middle_mult_x_1_n720), .S(genblk1_middle_mult_x_1_n721) );
INVX1TS U577 ( .A(n4117), .Y(n4118) );
OAI21X1TS U578 ( .A0(n991), .A1(n2846), .B0(n990), .Y(n2828) );
ADDFHX1TS U579 ( .A(n1017), .B(n1016), .CI(n1015), .CO(
genblk1_middle_mult_x_1_n841), .S(genblk1_middle_mult_x_1_n842) );
OAI21X1TS U580 ( .A0(n2516), .A1(n2445), .B0(n1998), .Y(n1999) );
NOR2X1TS U581 ( .A(n974), .B(n2883), .Y(n976) );
OAI21X1TS U582 ( .A0(n2403), .A1(n2768), .B0(n2049), .Y(n2050) );
OAI21X1TS U583 ( .A0(n769), .A1(n3978), .B0(n768), .Y(n3984) );
OAI21X1TS U584 ( .A0(n2516), .A1(n2506), .B0(n2499), .Y(n2500) );
INVX1TS U585 ( .A(n4056), .Y(n4057) );
INVX1TS U586 ( .A(n4055), .Y(n4058) );
OAI21X1TS U587 ( .A0(n3855), .A1(n2866), .B0(n2867), .Y(n2859) );
NOR2X1TS U588 ( .A(n3854), .B(n2866), .Y(n2858) );
XOR2XLTS U589 ( .A(n2447), .B(n2446), .Y(genblk1_middle_mult_x_1_n1467) );
ADDFX1TS U590 ( .A(n1377), .B(n1376), .CI(n1375), .CO(
genblk1_middle_mult_x_1_n948), .S(genblk1_middle_mult_x_1_n949) );
XOR2X2TS U591 ( .A(n1012), .B(n2214), .Y(n1016) );
XOR2XLTS U592 ( .A(n2584), .B(n2596), .Y(genblk1_middle_mult_x_1_n1572) );
NOR2X1TS U593 ( .A(n4164), .B(n4168), .Y(n797) );
NOR2X1TS U594 ( .A(n2874), .B(n3859), .Y(n978) );
XOR2X1TS U595 ( .A(n1080), .B(n2214), .Y(genblk1_middle_mult_x_1_n1358) );
NOR2X1TS U596 ( .A(n4059), .B(n4061), .Y(n782) );
ADDFHX1TS U597 ( .A(n1071), .B(n1070), .CI(n1069), .CO(
genblk1_middle_mult_x_1_n907), .S(genblk1_middle_mult_x_1_n908) );
XOR2X1TS U598 ( .A(n1844), .B(n1843), .Y(n2403) );
XOR2X1TS U599 ( .A(n1913), .B(n1912), .Y(n2575) );
XOR2X1TS U600 ( .A(n1878), .B(n1877), .Y(n2525) );
XOR2X1TS U601 ( .A(n1920), .B(n2214), .Y(genblk1_middle_mult_x_1_n1357) );
INVX1TS U602 ( .A(n4105), .Y(n4106) );
INVX1TS U603 ( .A(n4104), .Y(n4107) );
XOR2X2TS U604 ( .A(n1817), .B(n1816), .Y(n2495) );
XOR2X2TS U605 ( .A(n1806), .B(n1805), .Y(n2410) );
XOR2X1TS U606 ( .A(n1865), .B(n1864), .Y(n2516) );
OAI21X1TS U607 ( .A0(n2685), .A1(n2684), .B0(n2683), .Y(n2687) );
OAI21X1TS U608 ( .A0(n4348), .A1(n4345), .B0(n4349), .Y(n4056) );
XOR2X1TS U609 ( .A(n2149), .B(n2766), .Y(genblk1_middle_mult_x_1_n1327) );
OAI21X1TS U610 ( .A0(n2123), .A1(n1849), .B0(n1850), .Y(n1806) );
NOR2X1TS U611 ( .A(n3812), .B(n2849), .Y(n989) );
OAI21X1TS U612 ( .A0(n2849), .A1(n3813), .B0(n2850), .Y(n988) );
XOR2XLTS U613 ( .A(n1288), .B(n2596), .Y(n1298) );
OAI21X1TS U614 ( .A0(n2099), .A1(n1159), .B0(n1158), .Y(n1168) );
NOR2X1TS U615 ( .A(n3817), .B(n3820), .Y(n2838) );
OAI21X1TS U616 ( .A0(n4050), .A1(n4046), .B0(n4051), .Y(n4105) );
OAI21X1TS U617 ( .A0(n957), .A1(n2920), .B0(n956), .Y(n2918) );
XNOR2X1TS U618 ( .A(n1975), .B(n1974), .Y(n2595) );
ADDHXLTS U619 ( .A(n2179), .B(n2178), .CO(n1377), .S(n2180) );
ADDHX2TS U620 ( .A(n2785), .B(n2745), .CO(n1013), .S(n2756) );
XOR2XLTS U621 ( .A(n431), .B(n2766), .Y(n1014) );
XOR2X1TS U622 ( .A(n1025), .B(n2766), .Y(genblk1_middle_mult_x_1_n1330) );
NOR2X1TS U623 ( .A(genblk1_right_mult_x_1_n707), .B(
genblk1_right_mult_x_1_n718), .Y(n2879) );
OAI21X1TS U624 ( .A0(n4368), .A1(n4365), .B0(n4369), .Y(n775) );
NOR2X1TS U625 ( .A(genblk1_right_mult_x_1_n561), .B(
genblk1_right_mult_x_1_n555), .Y(n3817) );
NOR2X1TS U626 ( .A(genblk1_right_mult_x_1_n770), .B(
genblk1_right_mult_x_1_n780), .Y(n2893) );
AOI222X1TS U627 ( .A0(n293), .A1(n2729), .B0(n2674), .B1(n2709), .C0(n2736),
.C1(n2806), .Y(n1760) );
INVX3TS U628 ( .A(n1564), .Y(n2099) );
ADDFX1TS U629 ( .A(n1291), .B(n1290), .CI(n1289), .CO(n1292), .S(n1281) );
NOR2X1TS U630 ( .A(genblk1_right_mult_x_1_n757), .B(
genblk1_right_mult_x_1_n769), .Y(n2886) );
NOR2X1TS U631 ( .A(genblk1_right_mult_x_1_n781), .B(
genblk1_right_mult_x_1_n791), .Y(n3879) );
NOR2X1TS U632 ( .A(genblk1_right_mult_x_1_n803), .B(
genblk1_right_mult_x_1_n812), .Y(n2898) );
AO21XLTS U633 ( .A0(n2772), .A1(n2771), .B0(n2770), .Y(n2773) );
NOR2X1TS U634 ( .A(genblk1_left_mult_x_1_n698), .B(
genblk1_left_mult_x_1_n708), .Y(n4008) );
OAI21X1TS U635 ( .A0(n2648), .A1(n424), .B0(n347), .Y(n2644) );
NOR2X1TS U636 ( .A(n1272), .B(n1271), .Y(n2634) );
XOR2X1TS U637 ( .A(n1064), .B(n2714), .Y(n1070) );
BUFX4TS U638 ( .A(n2662), .Y(n2330) );
NOR2X1TS U639 ( .A(genblk1_left_mult_x_1_n519), .B(
genblk1_left_mult_x_1_n513), .Y(n4306) );
INVX3TS U640 ( .A(n2658), .Y(n308) );
XOR2XLTS U641 ( .A(n1759), .B(n2714), .Y(n1766) );
OAI21XLTS U642 ( .A0(n2491), .A1(n2810), .B0(n339), .Y(n1341) );
NOR2X1TS U643 ( .A(genblk1_right_mult_x_1_n823), .B(
genblk1_right_mult_x_1_n832), .Y(n3897) );
INVX1TS U644 ( .A(n1837), .Y(n1796) );
INVX1TS U645 ( .A(n1890), .Y(n1891) );
NOR2X1TS U646 ( .A(genblk1_right_mult_x_1_n833), .B(
genblk1_right_mult_x_1_n840), .Y(n3902) );
BUFX3TS U647 ( .A(n2148), .Y(n2765) );
XOR2XLTS U648 ( .A(n1252), .B(n2576), .Y(n1274) );
XOR2XLTS U649 ( .A(n1371), .B(n2812), .Y(n1779) );
NOR2X1TS U650 ( .A(genblk1_left_mult_x_1_n758), .B(
genblk1_left_mult_x_1_n765), .Y(n4378) );
INVX2TS U651 ( .A(n2759), .Y(n290) );
OAI21XLTS U652 ( .A0(n2491), .A1(n424), .B0(n338), .Y(n1342) );
BUFX3TS U653 ( .A(n304), .Y(n2736) );
ADDHXLTS U654 ( .A(n1276), .B(n1275), .CO(n1277), .S(n1272) );
XOR2XLTS U655 ( .A(n1235), .B(n2080), .Y(n1789) );
INVX1TS U656 ( .A(n1870), .Y(n1855) );
NOR2X1TS U657 ( .A(genblk1_right_mult_x_1_n849), .B(
genblk1_right_mult_x_1_n856), .Y(n3914) );
INVX1TS U658 ( .A(n1107), .Y(n1002) );
OAI21XLTS U659 ( .A0(n20), .A1(n2566), .B0(n1370), .Y(n1371) );
XOR2XLTS U660 ( .A(genblk1_right_mult_x_1_n520), .B(n1439), .Y(n1429) );
OAI21XLTS U661 ( .A0(n2811), .A1(n424), .B0(n316), .Y(n2805) );
INVX1TS U662 ( .A(n2095), .Y(n2097) );
INVX1TS U663 ( .A(n1893), .Y(n1157) );
NAND2BX1TS U664 ( .AN(n491), .B(n490), .Y(n1823) );
NAND2BX2TS U665 ( .AN(n559), .B(n560), .Y(n2148) );
CLKAND2X2TS U666 ( .A(n2432), .B(n2802), .Y(n2167) );
ADDHXLTS U667 ( .A(n2800), .B(n1270), .CO(n1271), .S(n1265) );
AND3X4TS U668 ( .A(n560), .B(n559), .C(n558), .Y(n2759) );
NOR2X1TS U669 ( .A(genblk1_left_mult_x_1_n788), .B(
genblk1_left_mult_x_1_n794), .Y(n4390) );
CLKAND2X2TS U670 ( .A(n2641), .B(n2679), .Y(genblk1_middle_mult_x_1_n1009)
);
INVX1TS U671 ( .A(n1102), .Y(n1000) );
NOR2X1TS U672 ( .A(genblk1_left_mult_x_1_n805), .B(n763), .Y(n3965) );
INVX1TS U673 ( .A(n1899), .Y(n1901) );
NOR2X1TS U674 ( .A(n758), .B(n757), .Y(n4403) );
NOR2X1TS U675 ( .A(n1874), .B(n1861), .Y(n1560) );
XOR2XLTS U676 ( .A(n1173), .B(n1172), .Y(n1174) );
XOR2XLTS U677 ( .A(n825), .B(n824), .Y(n813) );
CLKAND2X2TS U678 ( .A(n2653), .B(n25), .Y(n2655) );
CLKAND2X2TS U679 ( .A(n2776), .B(n25), .Y(n2789) );
XOR2X1TS U680 ( .A(n319), .B(n1100), .Y(n25) );
INVX4TS U681 ( .A(n408), .Y(n2666) );
XNOR2X1TS U682 ( .A(n489), .B(n547), .Y(n491) );
XOR2XLTS U683 ( .A(n3336), .B(n280), .Y(genblk1_right_mult_x_1_n1288) );
BUFX3TS U684 ( .A(n2400), .Y(n2326) );
XOR2XLTS U685 ( .A(n1259), .B(n2080), .Y(n1264) );
XOR2X1TS U686 ( .A(n3390), .B(n259), .Y(genblk1_right_mult_x_1_n1316) );
XOR2X2TS U687 ( .A(n427), .B(n1100), .Y(n560) );
NAND2BX1TS U688 ( .AN(n1054), .B(n1055), .Y(n1980) );
ADDFX1TS U689 ( .A(n717), .B(n716), .CI(n715), .CO(n763), .S(n760) );
XOR2XLTS U690 ( .A(n3413), .B(n259), .Y(genblk1_right_mult_x_1_n1327) );
XNOR2X2TS U691 ( .A(n1588), .B(n1587), .Y(n2400) );
XOR2X1TS U692 ( .A(n471), .B(n470), .Y(n489) );
XNOR2X2TS U693 ( .A(n1126), .B(n1125), .Y(n2559) );
XOR2X1TS U694 ( .A(n487), .B(n486), .Y(n488) );
XNOR2X2TS U695 ( .A(n1147), .B(n1146), .Y(n1936) );
OAI21XLTS U696 ( .A0(n2768), .A1(n423), .B0(n329), .Y(n1259) );
XNOR2X2TS U697 ( .A(n1165), .B(n1164), .Y(n1956) );
XOR2X2TS U698 ( .A(n407), .B(n406), .Y(n426) );
XOR2X1TS U699 ( .A(n635), .B(n203), .Y(n815) );
XOR2X1TS U700 ( .A(n3098), .B(n3097), .Y(n362) );
OAI21X1TS U701 ( .A0(n1550), .A1(n1533), .B0(n1532), .Y(n1536) );
XOR2X1TS U702 ( .A(n3109), .B(n3108), .Y(n3673) );
OAI21X1TS U703 ( .A0(n4963), .A1(n4505), .B0(n4041), .Y(
genblk1_left_mult_x_1_n493) );
XNOR2X1TS U704 ( .A(n1366), .B(n1354), .Y(n1367) );
OAI21X2TS U705 ( .A0(n1550), .A1(n1527), .B0(n1530), .Y(n1156) );
AOI21X1TS U706 ( .A0(n1099), .A1(n482), .B0(n481), .Y(n487) );
INVX1TS U707 ( .A(n1005), .Y(n1022) );
OAI21X1TS U708 ( .A0(n4900), .A1(n4668), .B0(n4663), .Y(n4664) );
OAI21X2TS U709 ( .A0(n1550), .A1(n1123), .B0(n1122), .Y(n1126) );
XOR2X1TS U710 ( .A(n2567), .B(n1365), .Y(n1369) );
OAI21X1TS U711 ( .A0(n4923), .A1(n4492), .B0(n4184), .Y(
genblk1_left_mult_x_1_n530) );
AOI21X1TS U712 ( .A0(n1099), .A1(n405), .B0(n404), .Y(n407) );
OAI21X1TS U713 ( .A0(n1577), .A1(n1576), .B0(n1575), .Y(n1580) );
AOI21X1TS U714 ( .A0(n1572), .A1(n1526), .B0(n1525), .Y(n1590) );
OAI21XLTS U715 ( .A0(n313), .A1(n4492), .B0(n4451), .Y(n4456) );
XNOR2X1TS U716 ( .A(n538), .B(n537), .Y(n548) );
XOR2X1TS U717 ( .A(n3946), .B(n3945), .Y(n4900) );
XOR2X1TS U718 ( .A(n1364), .B(n1363), .Y(n1365) );
XOR2X2TS U719 ( .A(n1205), .B(n1204), .Y(n1354) );
OAI21X1TS U720 ( .A0(n4951), .A1(n4569), .B0(n634), .Y(n635) );
AOI21X1TS U721 ( .A0(n538), .A1(n395), .B0(n394), .Y(n398) );
INVX1TS U722 ( .A(n1018), .Y(n1020) );
XOR2X2TS U723 ( .A(n1036), .B(n1035), .Y(n2567) );
XOR2X1TS U724 ( .A(n1353), .B(n1352), .Y(n1366) );
OAI21X1TS U725 ( .A0(n1045), .A1(n597), .B0(n596), .Y(n598) );
NOR2X1TS U726 ( .A(n1042), .B(n528), .Y(n530) );
INVX1TS U727 ( .A(n1096), .Y(n417) );
NOR2X1TS U728 ( .A(n1527), .B(n1529), .Y(n1546) );
OAI21X1TS U729 ( .A0(n1530), .A1(n1529), .B0(n1528), .Y(n1547) );
OAI21XLTS U730 ( .A0(n4884), .A1(n4492), .B0(n4472), .Y(n4479) );
AND3X2TS U731 ( .A(n1233), .B(n1232), .C(n1231), .Y(n2793) );
AOI21X2TS U732 ( .A0(n1359), .A1(n1202), .B0(n1201), .Y(n1205) );
NAND3X1TS U733 ( .A(n1243), .B(n1242), .C(n566), .Y(n2540) );
OAI21XLTS U734 ( .A0(n3746), .A1(n3707), .B0(n922), .Y(n923) );
INVX1TS U735 ( .A(n1094), .Y(n1095) );
NAND2X1TS U736 ( .A(n1504), .B(n30), .Y(n1162) );
XOR2XLTS U737 ( .A(n901), .B(n276), .Y(n933) );
NAND2X1TS U738 ( .A(n2808), .B(n2804), .Y(n556) );
NAND2X1TS U739 ( .A(n1581), .B(n32), .Y(n1524) );
XOR2XLTS U740 ( .A(n841), .B(n271), .Y(n3089) );
NAND2X2TS U741 ( .A(n1085), .B(n1109), .Y(n1087) );
NOR2X1TS U742 ( .A(n416), .B(Data_A_i[25]), .Y(n1096) );
OAI21X2TS U743 ( .A0(n456), .A1(n455), .B0(n454), .Y(n457) );
NOR2X2TS U744 ( .A(n456), .B(n453), .Y(n458) );
OAI21X1TS U745 ( .A0(n1528), .A1(n1512), .B0(n1511), .Y(n1513) );
OAI21X1TS U746 ( .A0(n671), .A1(n614), .B0(n613), .Y(n663) );
OAI21X1TS U747 ( .A0(n480), .A1(n414), .B0(n413), .Y(n416) );
OAI21X1TS U748 ( .A0(n3159), .A1(n1418), .B0(n1417), .Y(n3113) );
INVX1TS U749 ( .A(n3227), .Y(n3216) );
OAI21X1TS U750 ( .A0(n3987), .A1(n629), .B0(n628), .Y(n806) );
OAI21X2TS U751 ( .A0(n1154), .A1(n1153), .B0(n1152), .Y(n1515) );
NAND2X1TS U752 ( .A(n1141), .B(n1091), .Y(n1145) );
INVX1TS U753 ( .A(n4133), .Y(n4134) );
XNOR2X1TS U754 ( .A(result_A_adder_2_), .B(n1229), .Y(n1231) );
OAI21XLTS U755 ( .A0(n3746), .A1(n3636), .B0(n900), .Y(n901) );
OAI21X1TS U756 ( .A0(n375), .A1(n1211), .B0(n374), .Y(n376) );
AOI21X1TS U757 ( .A0(n27), .A1(n610), .B0(n609), .Y(n671) );
NAND2X1TS U758 ( .A(n440), .B(n454), .Y(n441) );
AOI21X1TS U759 ( .A0(n612), .A1(n691), .B0(n611), .Y(n613) );
NOR2X1TS U760 ( .A(n387), .B(n584), .Y(n389) );
NAND2X2TS U761 ( .A(n379), .B(n1029), .Y(n381) );
NOR2X1TS U762 ( .A(n523), .B(n600), .Y(n526) );
NAND2X1TS U763 ( .A(n420), .B(n434), .Y(n421) );
OAI21X1TS U764 ( .A0(n401), .A1(n484), .B0(n400), .Y(n412) );
INVX2TS U765 ( .A(n1149), .Y(n1150) );
NOR2X1TS U766 ( .A(n3989), .B(n3991), .Y(n638) );
INVX1TS U767 ( .A(n1575), .Y(n1519) );
NAND2X1TS U768 ( .A(n594), .B(n385), .Y(n387) );
AOI21X1TS U769 ( .A0(n31), .A1(n1517), .B0(n1516), .Y(n1567) );
INVX1TS U770 ( .A(n674), .Y(n676) );
NAND2X1TS U771 ( .A(n29), .B(n444), .Y(n445) );
INVX1TS U772 ( .A(n479), .Y(n482) );
INVX1TS U773 ( .A(n480), .Y(n481) );
OAI21X1TS U774 ( .A0(n1345), .A1(n1349), .B0(n1350), .Y(n1028) );
OAI21X1TS U775 ( .A0(n480), .A1(n483), .B0(n484), .Y(n394) );
INVX1TS U776 ( .A(n694), .Y(n696) );
NAND2X1TS U777 ( .A(n1503), .B(n1551), .Y(n1552) );
INVX1TS U778 ( .A(n3128), .Y(n3130) );
NOR2X1TS U779 ( .A(n4067), .B(n4069), .Y(n4022) );
AOI21X1TS U780 ( .A0(n373), .A1(n1186), .B0(n372), .Y(n374) );
NOR2X1TS U781 ( .A(n162), .B(n166), .Y(n3139) );
OAI21X1TS U782 ( .A0(n1187), .A1(n1194), .B0(n1195), .Y(n372) );
NOR2X1TS U783 ( .A(n126), .B(n171), .Y(n3101) );
NAND2BX1TS U784 ( .AN(n3024), .B(n3025), .Y(n3383) );
INVX1TS U785 ( .A(n3146), .Y(n3162) );
NOR2X1TS U786 ( .A(n174), .B(n43), .Y(n3094) );
NOR2X1TS U787 ( .A(n126), .B(n174), .Y(n3105) );
OAI21X1TS U788 ( .A0(n1032), .A1(n1361), .B0(n1033), .Y(n378) );
INVX1TS U789 ( .A(n3152), .Y(n3154) );
NAND2BX1TS U790 ( .AN(n3437), .B(n3066), .Y(n3469) );
NOR2X1TS U791 ( .A(n111), .B(n115), .Y(n642) );
NOR2X1TS U792 ( .A(n119), .B(n114), .Y(n644) );
NOR2X1TS U793 ( .A(n107), .B(n110), .Y(n3991) );
NOR2X1TS U794 ( .A(n82), .B(n86), .Y(n4141) );
OR2X2TS U795 ( .A(n166), .B(n113), .Y(n1505) );
NOR2X1TS U796 ( .A(Data_B_i[42]), .B(n93), .Y(n4067) );
NOR2X1TS U797 ( .A(n55), .B(n58), .Y(n724) );
INVX1TS U798 ( .A(n4192), .Y(n4194) );
XOR2X1TS U799 ( .A(n262), .B(Data_A_i[13]), .Y(n3066) );
CLKAND2X2TS U800 ( .A(n288), .B(n238), .Y(genblk1_right_mult_x_1_n932) );
CLKAND2X2TS U801 ( .A(n37), .B(n210), .Y(genblk1_right_mult_x_1_n925) );
NAND2BX1TS U802 ( .AN(n666), .B(n668), .Y(n4958) );
OAI21X1TS U803 ( .A0(n475), .A1(n467), .B0(n468), .Y(n392) );
NOR2X1TS U804 ( .A(n75), .B(n78), .Y(n4094) );
XOR2X1TS U805 ( .A(n190), .B(Data_A_i[40]), .Y(n4267) );
NOR2X1TS U806 ( .A(n98), .B(n123), .Y(n4026) );
NAND2BX1TS U807 ( .AN(n4259), .B(n4260), .Y(n4599) );
NOR2X1TS U808 ( .A(n124), .B(n103), .Y(n4028) );
NOR2X1TS U809 ( .A(n102), .B(n106), .Y(n3989) );
NAND2X1TS U810 ( .A(n469), .B(n468), .Y(n470) );
INVX2TS U811 ( .A(n282), .Y(n283) );
AOI21X1TS U812 ( .A0(n359), .A1(n383), .B0(n382), .Y(n585) );
OAI21X1TS U813 ( .A0(n542), .A1(n539), .B0(n543), .Y(n472) );
OAI21X1TS U814 ( .A0(n567), .A1(n570), .B0(n568), .Y(n564) );
INVX1TS U815 ( .A(n600), .Y(n602) );
XOR2X1TS U816 ( .A(Data_A_i[8]), .B(Data_A_i[7]), .Y(n839) );
INVX1TS U817 ( .A(n483), .Y(n485) );
INVX1TS U818 ( .A(n467), .Y(n469) );
INVX1TS U819 ( .A(n542), .Y(n544) );
OR2X2TS U820 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n359) );
NOR2X1TS U821 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n600) );
NOR2X1TS U822 ( .A(Data_A_i[33]), .B(Data_A_i[6]), .Y(n1194) );
NOR2X1TS U823 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n542) );
NOR2X1TS U824 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n467) );
AOI222X1TS U825 ( .A0(n2749), .A1(n2419), .B0(n2710), .B1(n2719), .C0(n2708),
.C1(n2700), .Y(n1758) );
OAI21X1TS U826 ( .A0(n2318), .A1(n2328), .B0(n2192), .Y(n2194) );
OAI21X1TS U827 ( .A0(n1569), .A1(n1524), .B0(n1523), .Y(n1525) );
AOI21X2TS U828 ( .A0(n1515), .A1(n1514), .B0(n1513), .Y(n1569) );
AOI21X2TS U829 ( .A0(n1325), .A1(n1693), .B0(n1324), .Y(n1326) );
AOI222X1TS U830 ( .A0(n2762), .A1(n2761), .B0(n2760), .B1(n2790), .C0(n291),
.C1(n2758), .Y(n2763) );
AO21X1TS U831 ( .A0(n1702), .A1(n1323), .B0(n1322), .Y(n16) );
OAI21XLTS U832 ( .A0(n1338), .A1(n1339), .B0(n1336), .Y(n1337) );
AOI222X1TS U833 ( .A0(n2762), .A1(n2729), .B0(n2760), .B1(n2727), .C0(n2759),
.C1(n2806), .Y(n561) );
XOR2X1TS U834 ( .A(n258), .B(Data_A_i[16]), .Y(n3025) );
OAI21X1TS U835 ( .A0(n2685), .A1(n2506), .B0(n2134), .Y(n2135) );
OAI21X1TS U836 ( .A0(n1585), .A1(n1542), .B0(n1541), .Y(n1545) );
OAI21X1TS U837 ( .A0(n296), .A1(n3093), .B0(n3092), .Y(n3098) );
XOR2X1TS U838 ( .A(n2519), .B(n2753), .Y(genblk1_middle_mult_x_1_n1415) );
CMPR42X2TS U839 ( .A(n4983), .B(genblk1_middle_mult_x_1_n1024), .C(
genblk1_middle_mult_x_1_n1327), .D(genblk1_middle_mult_x_1_n1355),
.ICI(genblk1_middle_mult_x_1_n792), .S(genblk1_middle_mult_x_1_n782),
.ICO(genblk1_middle_mult_x_1_n780), .CO(genblk1_middle_mult_x_1_n781)
);
NOR2X2TS U840 ( .A(n3013), .B(n3012), .Y(n3327) );
ADDHX1TS U841 ( .A(n3770), .B(n3769), .CO(genblk1_right_mult_x_1_n860), .S(
n3785) );
ACHCINX2TS U842 ( .CIN(n1175), .A(n1173), .B(n1172), .CO(n833) );
NAND2BX1TS U843 ( .AN(n1367), .B(n1369), .Y(n1988) );
XNOR2X1TS U844 ( .A(n1366), .B(n1365), .Y(n1368) );
ADDHX1TS U845 ( .A(n2678), .B(n2677), .CO(genblk1_middle_mult_x_1_n867), .S(
genblk1_middle_mult_x_1_n868) );
CMPR42X2TS U846 ( .A(genblk1_middle_mult_x_1_n1027), .B(
genblk1_middle_mult_x_1_n1358), .C(genblk1_middle_mult_x_1_n1330), .D(
genblk1_middle_mult_x_1_n1386), .ICI(genblk1_middle_mult_x_1_n830),
.S(genblk1_middle_mult_x_1_n818), .ICO(genblk1_middle_mult_x_1_n816),
.CO(genblk1_middle_mult_x_1_n817) );
AND3X4TS U847 ( .A(n492), .B(n491), .C(n490), .Y(n2391) );
AOI222X1TS U848 ( .A0(n2695), .A1(n2228), .B0(n2702), .B1(n2227), .C0(n2701),
.C1(n2709), .Y(n2229) );
CMPR42X2TS U849 ( .A(genblk1_middle_mult_x_1_n962), .B(
genblk1_middle_mult_x_1_n1568), .C(genblk1_middle_mult_x_1_n1540), .D(
genblk1_middle_mult_x_1_n956), .ICI(genblk1_middle_mult_x_1_n959), .S(
genblk1_middle_mult_x_1_n954), .ICO(genblk1_middle_mult_x_1_n952),
.CO(genblk1_middle_mult_x_1_n953) );
NAND2X1TS U850 ( .A(n2498), .B(n2804), .Y(n338) );
XOR2X2TS U851 ( .A(n591), .B(n590), .Y(n1754) );
NAND2BX1TS U852 ( .AN(n551), .B(n552), .Y(n1925) );
NOR2X1TS U853 ( .A(n991), .B(n2847), .Y(n2827) );
XOR2X1TS U854 ( .A(n1922), .B(n399), .Y(genblk1_middle_mult_x_1_n1361) );
CMPR42X2TS U855 ( .A(genblk1_middle_mult_x_1_n1361), .B(
genblk1_middle_mult_x_1_n867), .C(genblk1_middle_mult_x_1_n1473), .D(
genblk1_middle_mult_x_1_n1501), .ICI(genblk1_middle_mult_x_1_n861),
.S(genblk1_middle_mult_x_1_n853), .ICO(genblk1_middle_mult_x_1_n851),
.CO(genblk1_middle_mult_x_1_n852) );
OAI2BB1X2TS U856 ( .A0N(n1502), .A1N(n2139), .B0(n1645), .Y(n1606) );
ACHCINX2TS U857 ( .CIN(n826), .A(n825), .B(n824), .CO(n4300) );
NOR2X1TS U858 ( .A(n760), .B(n759), .Y(n4404) );
OAI21X1TS U859 ( .A0(n3820), .A1(n3825), .B0(n3821), .Y(n2839) );
OAI21X1TS U860 ( .A0(n296), .A1(n1423), .B0(n1422), .Y(n1424) );
AOI21X2TS U861 ( .A0(n1107), .A1(n1106), .B0(n1105), .Y(n1770) );
XOR2X2TS U862 ( .A(n497), .B(n496), .Y(n2791) );
OAI21X1TS U863 ( .A0(n2069), .A1(n2065), .B0(n2066), .Y(n1913) );
AOI21X1TS U864 ( .A0(n762), .A1(n3963), .B0(n761), .Y(n3968) );
OAI21X1TS U865 ( .A0(n3957), .A1(n3960), .B0(n3958), .Y(n3963) );
NOR2X1TS U866 ( .A(n756), .B(n755), .Y(n3957) );
XOR2X1TS U867 ( .A(n4955), .B(Data_A_i[28]), .Y(n668) );
OR2X4TS U868 ( .A(n1791), .B(n2124), .Y(n1597) );
AOI21X2TS U869 ( .A0(n1595), .A1(n1837), .B0(n1594), .Y(n2116) );
OAI21X1TS U870 ( .A0(n2285), .A1(n2328), .B0(n2189), .Y(n2190) );
INVX2TS U871 ( .A(n1506), .Y(n1507) );
OAI21X1TS U872 ( .A0(n2099), .A1(n1882), .B0(n1881), .Y(n1886) );
NOR2X1TS U873 ( .A(n229), .B(n53), .Y(n460) );
CMPR42X2TS U874 ( .A(genblk1_middle_mult_x_1_n778), .B(
genblk1_middle_mult_x_1_n767), .C(genblk1_middle_mult_x_1_n775), .D(
genblk1_middle_mult_x_1_n764), .ICI(genblk1_middle_mult_x_1_n771), .S(
genblk1_middle_mult_x_1_n761), .ICO(genblk1_middle_mult_x_1_n759),
.CO(genblk1_middle_mult_x_1_n760) );
OAI21XLTS U875 ( .A0(n345), .A1(n2148), .B0(n2147), .Y(n2149) );
AOI222X1TS U876 ( .A0(n2564), .A1(n2670), .B0(n2807), .B1(n2669), .C0(n2562),
.C1(n2419), .Y(n2017) );
AOI222X1TS U877 ( .A0(n2695), .A1(n2359), .B0(n2702), .B1(n2709), .C0(n2701),
.C1(n2806), .Y(n1373) );
AOI21X1TS U878 ( .A0(n1099), .A1(n466), .B0(n465), .Y(n471) );
ADDHX1TS U879 ( .A(n2735), .B(n2734), .CO(genblk1_middle_mult_x_1_n969), .S(
genblk1_middle_mult_x_1_n970) );
NOR2X2TS U880 ( .A(genblk1_middle_mult_x_1_n749), .B(
genblk1_middle_mult_x_1_n760), .Y(n1685) );
AOI222X1TS U881 ( .A0(n2330), .A1(n2761), .B0(n2660), .B1(n2228), .C0(n308),
.C1(n2758), .Y(n1011) );
NAND2X2TS U882 ( .A(genblk1_middle_mult_x_1_n749), .B(
genblk1_middle_mult_x_1_n760), .Y(n2275) );
AOI21X4TS U883 ( .A0(n2824), .A1(n998), .B0(n997), .Y(n2823) );
NOR2X1TS U884 ( .A(n213), .B(n218), .Y(n2990) );
OAI21X1TS U885 ( .A0(n296), .A1(n3160), .B0(n3159), .Y(n3164) );
NOR2X1TS U886 ( .A(n2989), .B(n2990), .Y(n3236) );
NAND2BX1TS U887 ( .AN(n1060), .B(n1062), .Y(n1943) );
AOI21X2TS U888 ( .A0(n2368), .A1(n2364), .B0(n1319), .Y(n1320) );
AOI222X1TS U889 ( .A0(n2330), .A1(n2729), .B0(n295), .B1(n2727), .C0(n309),
.C1(n2806), .Y(n1923) );
ACHCINX2TS U890 ( .CIN(n1402), .A(genblk1_right_mult_x_1_n524), .B(
genblk1_right_mult_x_1_n527), .CO(n2821) );
OR2X2TS U891 ( .A(genblk1_right_mult_x_1_n646), .B(
genblk1_right_mult_x_1_n635), .Y(n363) );
OAI21X2TS U892 ( .A0(n4076), .A1(n802), .B0(n801), .Y(n4305) );
OAI21XLTS U893 ( .A0(n18), .A1(n4759), .B0(n4741), .Y(n4742) );
NOR2X1TS U894 ( .A(genblk1_middle_mult_x_1_n610), .B(
genblk1_middle_mult_x_1_n614), .Y(n1476) );
XOR2X1TS U895 ( .A(n2172), .B(n2394), .Y(n2173) );
OAI21X1TS U896 ( .A0(n2357), .A1(n2393), .B0(n2171), .Y(n2172) );
OAI21X1TS U897 ( .A0(n1695), .A1(n2294), .B0(n1696), .Y(n1324) );
AOI222X1TS U898 ( .A0(n2348), .A1(n2582), .B0(n295), .B1(n2739), .C0(n308),
.C1(n2642), .Y(n1919) );
CMPR42X2TS U899 ( .A(genblk1_middle_mult_x_1_n790), .B(
genblk1_middle_mult_x_1_n779), .C(genblk1_middle_mult_x_1_n787), .D(
genblk1_middle_mult_x_1_n776), .ICI(genblk1_middle_mult_x_1_n783), .S(
genblk1_middle_mult_x_1_n773), .ICO(genblk1_middle_mult_x_1_n771),
.CO(genblk1_middle_mult_x_1_n772) );
NOR2X2TS U900 ( .A(Data_A_i[31]), .B(Data_A_i[4]), .Y(n1224) );
OR2X4TS U901 ( .A(genblk1_middle_mult_x_1_n860), .B(
genblk1_middle_mult_x_1_n870), .Y(n1709) );
NOR2X1TS U902 ( .A(n3160), .B(n1418), .Y(n3112) );
NOR2X1TS U903 ( .A(n1378), .B(n1381), .Y(n1617) );
NOR2X1TS U904 ( .A(n1953), .B(n2030), .Y(n1874) );
NAND2X2TS U905 ( .A(genblk1_middle_mult_x_1_n725), .B(
genblk1_middle_mult_x_1_n736), .Y(n1676) );
OAI21X4TS U906 ( .A0(n515), .A1(n514), .B0(n513), .Y(n1110) );
AOI21X4TS U907 ( .A0(n3), .A1(n506), .B0(n505), .Y(n515) );
XOR2X1TS U908 ( .A(n903), .B(n274), .Y(n927) );
OAI21X1TS U909 ( .A0(n3079), .A1(n3636), .B0(n902), .Y(n903) );
NOR2X2TS U910 ( .A(genblk1_middle_mult_x_1_n903), .B(
genblk1_middle_mult_x_1_n912), .Y(n1716) );
OAI21X1TS U911 ( .A0(n1621), .A1(n1620), .B0(n1619), .Y(n1675) );
NOR2X2TS U912 ( .A(n371), .B(n283), .Y(n1212) );
OAI21XLTS U913 ( .A0(n2629), .A1(n2632), .B0(n2630), .Y(n1741) );
NAND2BX1TS U914 ( .AN(n1231), .B(n1233), .Y(n1257) );
NOR2X2TS U915 ( .A(n1367), .B(n1369), .Y(n1989) );
OAI21X1TS U916 ( .A0(n1585), .A1(n1584), .B0(n1583), .Y(n1588) );
OAI21X1TS U917 ( .A0(n2318), .A1(n2491), .B0(n2317), .Y(n2319) );
NOR2BX2TS U918 ( .AN(n1836), .B(n1840), .Y(n1595) );
CMPR42X2TS U919 ( .A(genblk1_middle_mult_x_1_n932), .B(
genblk1_middle_mult_x_1_n1564), .C(genblk1_middle_mult_x_1_n933), .D(
genblk1_middle_mult_x_1_n929), .ICI(genblk1_middle_mult_x_1_n926), .S(
genblk1_middle_mult_x_1_n923), .ICO(genblk1_middle_mult_x_1_n921),
.CO(genblk1_middle_mult_x_1_n922) );
NOR2X2TS U920 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n1349) );
NOR2X2TS U921 ( .A(n1346), .B(n1349), .Y(n1029) );
OAI21X2TS U922 ( .A0(n522), .A1(n391), .B0(n390), .Y(n538) );
AOI222X1TS U923 ( .A0(n2330), .A1(n2433), .B0(n295), .B1(n2489), .C0(n308),
.C1(n2533), .Y(n1897) );
NOR2X2TS U924 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n1360) );
INVX2TS U925 ( .A(n1546), .Y(n1549) );
OAI21X1TS U926 ( .A0(n1381), .A1(n1676), .B0(n1380), .Y(n1618) );
NOR2X2TS U927 ( .A(genblk1_middle_mult_x_1_n713), .B(
genblk1_middle_mult_x_1_n724), .Y(n1381) );
OAI2BB1X2TS U928 ( .A0N(n2155), .A1N(n2157), .B0(n2154), .Y(n1475) );
AOI222X1TS U929 ( .A0(n2564), .A1(n2737), .B0(n2728), .B1(n2803), .C0(n2726),
.C1(n2790), .Y(n1370) );
AOI21X1TS U930 ( .A0(n2114), .A1(n2112), .B0(n1464), .Y(n1401) );
CMPR42X2TS U931 ( .A(genblk1_middle_mult_x_1_n1492), .B(
genblk1_middle_mult_x_1_n1464), .C(genblk1_middle_mult_x_1_n753), .D(
genblk1_middle_mult_x_1_n746), .ICI(genblk1_middle_mult_x_1_n757), .S(
genblk1_middle_mult_x_1_n740), .ICO(genblk1_middle_mult_x_1_n738),
.CO(genblk1_middle_mult_x_1_n739) );
OA21X2TS U932 ( .A0(n2123), .A1(n1633), .B0(n1632), .Y(n2685) );
OAI21X1TS U933 ( .A0(n2257), .A1(n1473), .B0(n1472), .Y(n2157) );
XNOR2X2TS U934 ( .A(n1600), .B(n2102), .Y(n2774) );
NOR2X2TS U935 ( .A(n2222), .B(n2771), .Y(n2124) );
OAI21X1TS U936 ( .A0(n1567), .A1(n1521), .B0(n1520), .Y(n1582) );
OAI21X1TS U937 ( .A0(n1651), .A1(n1650), .B0(n1649), .Y(n2270) );
XOR2X1TS U938 ( .A(n2687), .B(n2686), .Y(n2688) );
NOR2X1TS U939 ( .A(n1477), .B(n1486), .Y(n1492) );
NOR2X2TS U940 ( .A(n1849), .B(n1802), .Y(n1833) );
NOR2X2TS U941 ( .A(n2680), .B(n2484), .Y(n1849) );
NOR2X1TS U942 ( .A(n2484), .B(n2405), .Y(n1802) );
NOR2X2TS U943 ( .A(n221), .B(n61), .Y(n514) );
OAI21XLTS U944 ( .A0(n3756), .A1(n3379), .B0(n3359), .Y(n3360) );
XOR2XLTS U945 ( .A(n3420), .B(n260), .Y(genblk1_right_mult_x_1_n1329) );
OAI21XLTS U946 ( .A0(n3756), .A1(n3807), .B0(n3419), .Y(n3420) );
CLKBUFX2TS U947 ( .A(n3271), .Y(n3329) );
XOR2XLTS U948 ( .A(n3002), .B(n37), .Y(n3020) );
OAI21XLTS U949 ( .A0(n3746), .A1(n3269), .B0(n3001), .Y(n3002) );
CLKBUFX2TS U950 ( .A(n3469), .Y(n3801) );
XOR2XLTS U951 ( .A(n266), .B(Data_A_i[10]), .Y(n3071) );
INVX2TS U952 ( .A(Data_A_i[14]), .Y(n261) );
NAND2X1TS U953 ( .A(n17), .B(n1134), .Y(n1135) );
AOI21X1TS U954 ( .A0(n1133), .A1(n1132), .B0(n1131), .Y(n1136) );
NOR2XLTS U955 ( .A(n1129), .B(n1127), .Y(n1132) );
INVX2TS U956 ( .A(n188), .Y(n4430) );
XOR2XLTS U957 ( .A(n4428), .B(n203), .Y(n4429) );
OAI21XLTS U958 ( .A0(n4942), .A1(n4466), .B0(n4448), .Y(n4449) );
XOR2XLTS U959 ( .A(n4508), .B(n203), .Y(n4512) );
OAI21XLTS U960 ( .A0(n4884), .A1(n4452), .B0(n4507), .Y(n4508) );
XOR2XLTS U961 ( .A(n4646), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1161)
);
XOR2XLTS U962 ( .A(n4795), .B(n187), .Y(genblk1_left_mult_x_1_n1239) );
XOR2XLTS U963 ( .A(n4696), .B(n194), .Y(genblk1_left_mult_x_1_n1187) );
INVX2TS U964 ( .A(n4143), .Y(n4145) );
XOR2XLTS U965 ( .A(n4282), .B(n191), .Y(n4537) );
INVX2TS U966 ( .A(Data_A_i[32]), .Y(n177) );
CLKAND2X2TS U967 ( .A(n36), .B(n143), .Y(genblk1_right_mult_x_1_n920) );
CLKBUFX2TS U968 ( .A(n3469), .Y(n3454) );
CLKBUFX2TS U969 ( .A(n3524), .Y(n3508) );
INVX2TS U970 ( .A(n547), .Y(n2169) );
NOR2BX2TS U971 ( .AN(n491), .B(n492), .Y(n2660) );
CLKAND2X2TS U972 ( .A(n4446), .B(Data_B_i[43]), .Y(n4074) );
XOR2XLTS U973 ( .A(n4276), .B(n195), .Y(n4280) );
XOR2XLTS U974 ( .A(n4278), .B(n203), .Y(n4279) );
OAI21XLTS U975 ( .A0(n4951), .A1(n4668), .B0(n4275), .Y(n4276) );
XOR2X1TS U976 ( .A(n820), .B(n809), .Y(n4954) );
XOR2XLTS U977 ( .A(n4545), .B(n187), .Y(n4555) );
OAI21XLTS U978 ( .A0(n4884), .A1(n4780), .B0(n4544), .Y(n4545) );
NOR2BX1TS U979 ( .AN(n666), .B(n667), .Y(n4961) );
XOR2XLTS U980 ( .A(n3075), .B(n267), .Y(n3085) );
OAI21XLTS U981 ( .A0(n314), .A1(n3522), .B0(n3074), .Y(n3075) );
CLKBUFX2TS U982 ( .A(n2025), .Y(n2723) );
CLKBUFX2TS U983 ( .A(n1257), .Y(n2571) );
XOR2XLTS U984 ( .A(n4213), .B(Data_A_i[50]), .Y(n4214) );
OAI21XLTS U985 ( .A0(n4900), .A1(n4569), .B0(n4212), .Y(n4213) );
NOR2XLTS U986 ( .A(n4380), .B(n4378), .Y(n771) );
CLKBUFX2TS U987 ( .A(n4753), .Y(n4764) );
INVX2TS U988 ( .A(Data_B_i[35]), .Y(n615) );
XOR2XLTS U989 ( .A(n3366), .B(n280), .Y(genblk1_right_mult_x_1_n1302) );
OAI21XLTS U990 ( .A0(n3715), .A1(n3379), .B0(n3365), .Y(n3366) );
XOR2XLTS U991 ( .A(n3330), .B(n255), .Y(genblk1_right_mult_x_1_n1276) );
OAI21XLTS U992 ( .A0(n352), .A1(n3329), .B0(n3328), .Y(n3330) );
XOR2XLTS U993 ( .A(n3000), .B(n37), .Y(n3006) );
OAI21XLTS U994 ( .A0(n314), .A1(n3269), .B0(n2999), .Y(n3000) );
CLKBUFX2TS U995 ( .A(n3047), .Y(n3379) );
CLKBUFX2TS U996 ( .A(n3375), .Y(n3742) );
OAI21XLTS U997 ( .A0(n3243), .A1(n3218), .B0(n3217), .Y(n3223) );
INVX2TS U998 ( .A(n3219), .Y(n3221) );
CLKBUFX2TS U999 ( .A(n3799), .Y(n3725) );
NAND3X1TS U1000 ( .A(n552), .B(n551), .C(n550), .Y(n2682) );
NAND2X1TS U1001 ( .A(n358), .B(n1534), .Y(n1535) );
NAND2X1TS U1002 ( .A(n1546), .B(n1503), .Y(n1533) );
CLKAND2X2TS U1003 ( .A(n2746), .B(n25), .Y(n2656) );
INVX2TS U1004 ( .A(n1754), .Y(n2162) );
NAND2X1TS U1005 ( .A(n503), .B(n495), .Y(n461) );
CLKAND2X2TS U1006 ( .A(n4490), .B(n82), .Y(n4183) );
OAI21XLTS U1007 ( .A0(n4551), .A1(n4492), .B0(n4491), .Y(n4499) );
XOR2XLTS U1008 ( .A(n4494), .B(n202), .Y(n4498) );
XOR2XLTS U1009 ( .A(n4262), .B(n198), .Y(n4517) );
OAI21XLTS U1010 ( .A0(n21), .A1(n4654), .B0(n4261), .Y(n4262) );
XOR2XLTS U1011 ( .A(n4525), .B(n194), .Y(n4533) );
XOR2XLTS U1012 ( .A(n4227), .B(n4981), .Y(genblk1_left_mult_x_1_n1324) );
OAI21XLTS U1013 ( .A0(n4917), .A1(n4971), .B0(n4226), .Y(n4227) );
XOR2X1TS U1014 ( .A(n4191), .B(n4158), .Y(n4860) );
XOR2XLTS U1015 ( .A(n3286), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1260) );
OAI21XLTS U1016 ( .A0(n325), .A1(n3291), .B0(n3285), .Y(n3286) );
CLKAND2X2TS U1017 ( .A(n289), .B(n140), .Y(n2953) );
OAI21XLTS U1018 ( .A0(n340), .A1(n3508), .B0(n3501), .Y(n3502) );
CLKBUFX2TS U1019 ( .A(n3799), .Y(n3763) );
CLKBUFX2TS U1020 ( .A(n3469), .Y(n3765) );
XOR2XLTS U1021 ( .A(n3022), .B(n255), .Y(n3029) );
XOR2XLTS U1022 ( .A(n3027), .B(Data_A_i[17]), .Y(n3028) );
OAI21XLTS U1023 ( .A0(n3751), .A1(n3329), .B0(n3021), .Y(n3022) );
XOR2XLTS U1024 ( .A(n3427), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1333) );
OAI21XLTS U1025 ( .A0(n3719), .A1(n3807), .B0(n3426), .Y(n3427) );
XOR2XLTS U1026 ( .A(n3055), .B(n260), .Y(n3065) );
OAI21XLTS U1027 ( .A0(n3746), .A1(n3416), .B0(n3054), .Y(n3055) );
OAI21XLTS U1028 ( .A0(n3243), .A1(n3242), .B0(n3241), .Y(n3248) );
INVX2TS U1029 ( .A(n3244), .Y(n3246) );
OAI21XLTS U1030 ( .A0(n2595), .A1(n302), .B0(n2291), .Y(n2292) );
CLKAND2X2TS U1031 ( .A(n2791), .B(n25), .Y(genblk1_middle_mult_x_1_n1021) );
OAI21XLTS U1032 ( .A0(n2752), .A1(n303), .B0(n2185), .Y(n2186) );
OAI21XLTS U1033 ( .A0(n327), .A1(n303), .B0(n2289), .Y(n2290) );
OAI21XLTS U1034 ( .A0(n327), .A1(n2664), .B0(n1917), .Y(n1918) );
CLKAND2X2TS U1035 ( .A(n2679), .B(n2804), .Y(genblk1_middle_mult_x_1_n1027)
);
OAI21XLTS U1036 ( .A0(n2752), .A1(n2751), .B0(n2750), .Y(n2754) );
OAI21XLTS U1037 ( .A0(n2752), .A1(n2705), .B0(n2250), .Y(n2251) );
INVX2TS U1038 ( .A(n2169), .Y(n2743) );
INVX2TS U1039 ( .A(n2162), .Y(n2552) );
XOR2XLTS U1040 ( .A(n4664), .B(n195), .Y(genblk1_left_mult_x_1_n1173) );
XOR2XLTS U1041 ( .A(n4770), .B(n188), .Y(genblk1_left_mult_x_1_n1228) );
XOR2XLTS U1042 ( .A(n4744), .B(n192), .Y(genblk1_left_mult_x_1_n1213) );
XOR2XLTS U1043 ( .A(n4843), .B(n183), .Y(genblk1_left_mult_x_1_n1265) );
XOR2XLTS U1044 ( .A(n4849), .B(n183), .Y(genblk1_left_mult_x_1_n1268) );
XOR2XLTS U1045 ( .A(n4804), .B(n188), .Y(genblk1_left_mult_x_1_n1242) );
CLKBUFX2TS U1046 ( .A(n4818), .Y(n4875) );
XOR2X1TS U1047 ( .A(n698), .B(n697), .Y(n4942) );
OAI21XLTS U1048 ( .A0(n728), .A1(n724), .B0(n725), .Y(n698) );
CLKBUFX2TS U1049 ( .A(n4958), .Y(n4980) );
CLKBUFX2TS U1050 ( .A(n4947), .Y(n4925) );
XOR2X1TS U1051 ( .A(n693), .B(n688), .Y(n4876) );
CLKAND2X2TS U1052 ( .A(n288), .B(n251), .Y(n2942) );
CLKAND2X2TS U1053 ( .A(n37), .B(n152), .Y(genblk1_right_mult_x_1_n918) );
XOR2XLTS U1054 ( .A(n3332), .B(n280), .Y(genblk1_right_mult_x_1_n1286) );
XOR2XLTS U1055 ( .A(n3284), .B(n255), .Y(genblk1_right_mult_x_1_n1259) );
XOR2X1TS U1056 ( .A(n3176), .B(n3175), .Y(n3689) );
CLKBUFX2TS U1057 ( .A(n2983), .Y(n3269) );
XOR2XLTS U1058 ( .A(n3452), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1351) );
OAI21XLTS U1059 ( .A0(n3676), .A1(n3508), .B0(n3499), .Y(n3500) );
XOR2XLTS U1060 ( .A(n3555), .B(n271), .Y(genblk1_right_mult_x_1_n1408) );
XOR2XLTS U1061 ( .A(n3506), .B(n266), .Y(genblk1_right_mult_x_1_n1381) );
OAI21XLTS U1062 ( .A0(n3676), .A1(n3563), .B0(n3554), .Y(n3555) );
XOR2XLTS U1063 ( .A(n3569), .B(n270), .Y(genblk1_right_mult_x_1_n1414) );
OAI21XLTS U1064 ( .A0(n3692), .A1(n3599), .B0(n3568), .Y(n3569) );
XOR2XLTS U1065 ( .A(n3536), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1393) );
XOR2XLTS U1066 ( .A(n3632), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1447) );
XOR2XLTS U1067 ( .A(n3483), .B(n264), .Y(genblk1_right_mult_x_1_n1366) );
CLKBUFX2TS U1068 ( .A(n3578), .Y(n3775) );
XOR2XLTS U1069 ( .A(n3077), .B(Data_A_i[11]), .Y(n3087) );
OAI21XLTS U1070 ( .A0(n3746), .A1(n3522), .B0(n3076), .Y(n3077) );
OAI21XLTS U1071 ( .A0(n314), .A1(n3599), .B0(n840), .Y(n841) );
CLKBUFX2TS U1072 ( .A(n3602), .Y(n3661) );
INVX2TS U1073 ( .A(n863), .Y(n865) );
CLKBUFX2TS U1074 ( .A(n3663), .Y(n3737) );
INVX2TS U1075 ( .A(n644), .Y(n646) );
CLKAND2X2TS U1076 ( .A(n4039), .B(n101), .Y(n4040) );
XOR2XLTS U1077 ( .A(n4606), .B(n199), .Y(genblk1_left_mult_x_1_n1141) );
XOR2XLTS U1078 ( .A(n4660), .B(n195), .Y(genblk1_left_mult_x_1_n1171) );
XOR2XLTS U1079 ( .A(n4614), .B(n197), .Y(genblk1_left_mult_x_1_n1145) );
OAI21XLTS U1080 ( .A0(n4954), .A1(n4668), .B0(n4659), .Y(n4660) );
XOR2XLTS U1081 ( .A(n4201), .B(n4955), .Y(genblk1_left_mult_x_1_n1315) );
OAI21XLTS U1082 ( .A0(n367), .A1(n4958), .B0(n4200), .Y(n4201) );
NOR2XLTS U1083 ( .A(n4366), .B(n4368), .Y(n776) );
XOR2XLTS U1084 ( .A(n4218), .B(n371), .Y(genblk1_left_mult_x_1_n1322) );
OAI21XLTS U1085 ( .A0(n4911), .A1(n4958), .B0(n4217), .Y(n4218) );
XOR2XLTS U1086 ( .A(n4930), .B(n180), .Y(genblk1_left_mult_x_1_n1299) );
XOR2XLTS U1087 ( .A(n4972), .B(n4981), .Y(genblk1_left_mult_x_1_n1325) );
OAI21XLTS U1088 ( .A0(n18), .A1(n4886), .B0(n4929), .Y(n4930) );
INVX2TS U1089 ( .A(n3105), .Y(n3107) );
NOR2XLTS U1090 ( .A(n2901), .B(n3897), .Y(n965) );
XOR2XLTS U1091 ( .A(n3541), .B(n267), .Y(genblk1_right_mult_x_1_n1395) );
XOR2XLTS U1092 ( .A(n3698), .B(n284), .Y(genblk1_right_mult_x_1_n1476) );
OAI21XLTS U1093 ( .A0(n3655), .A1(n3781), .B0(n3540), .Y(n3541) );
XOR2XLTS U1094 ( .A(n2062), .B(n2411), .Y(genblk1_middle_mult_x_1_n1534) );
OAI21XLTS U1095 ( .A0(n2547), .A1(n2409), .B0(n2061), .Y(n2062) );
XOR2XLTS U1096 ( .A(n2044), .B(n2193), .Y(genblk1_middle_mult_x_1_n1509) );
XOR2XLTS U1097 ( .A(n2249), .B(n2800), .Y(genblk1_middle_mult_x_1_n1537) );
OAI21XLTS U1098 ( .A0(n2595), .A1(n2723), .B0(n2043), .Y(n2044) );
XOR2XLTS U1099 ( .A(n2577), .B(n2576), .Y(genblk1_middle_mult_x_1_n1569) );
XOR2XLTS U1100 ( .A(n2074), .B(n2800), .Y(genblk1_middle_mult_x_1_n1541) );
OAI21XLTS U1101 ( .A0(n2575), .A1(n2594), .B0(n2574), .Y(n2577) );
NAND2X1TS U1102 ( .A(n592), .B(n589), .Y(n576) );
INVX2TS U1103 ( .A(n1038), .Y(n1045) );
INVX2TS U1104 ( .A(n1043), .Y(n383) );
INVX2TS U1105 ( .A(n1037), .Y(n1042) );
NAND2X1TS U1106 ( .A(n359), .B(n1039), .Y(n584) );
INVX2TS U1107 ( .A(n1110), .Y(n1130) );
XOR2XLTS U1108 ( .A(n3321), .B(n255), .Y(genblk1_right_mult_x_1_n1274) );
OAI21XLTS U1109 ( .A0(n322), .A1(n3329), .B0(n3320), .Y(n3321) );
CLKBUFX2TS U1110 ( .A(n3663), .Y(n3685) );
AOI21X1TS U1111 ( .A0(n358), .A1(n1531), .B0(n1510), .Y(n1511) );
NAND2X1TS U1112 ( .A(n1504), .B(n1514), .Y(n1566) );
OAI21XLTS U1113 ( .A0(n2665), .A1(n2742), .B0(n2233), .Y(n2234) );
NAND2X1TS U1114 ( .A(n476), .B(n475), .Y(n477) );
AOI21X1TS U1115 ( .A0(n538), .A1(n473), .B0(n472), .Y(n478) );
INVX2TS U1116 ( .A(n474), .Y(n476) );
OAI21XLTS U1117 ( .A0(n2665), .A1(n2751), .B0(n2239), .Y(n2240) );
NOR2X1TS U1118 ( .A(n1566), .B(n1568), .Y(n1571) );
OAI21X1TS U1119 ( .A0(n1569), .A1(n1568), .B0(n1567), .Y(n1570) );
NAND2X1TS U1120 ( .A(n1108), .B(n17), .Y(n1114) );
NOR2XLTS U1121 ( .A(n1072), .B(n499), .Y(n500) );
CLKBUFX2TS U1122 ( .A(n4595), .Y(n4582) );
CLKBUFX2TS U1123 ( .A(n4642), .Y(n4652) );
CLKAND2X2TS U1124 ( .A(n4446), .B(n63), .Y(n4150) );
OAI21XLTS U1125 ( .A0(n4923), .A1(n4518), .B0(n4682), .Y(n4683) );
XOR2XLTS U1126 ( .A(n4461), .B(n203), .Y(n4462) );
OAI21XLTS U1127 ( .A0(n342), .A1(n4466), .B0(n4459), .Y(n4463) );
OAI21XLTS U1128 ( .A0(n4876), .A1(n4466), .B0(n4465), .Y(n4470) );
OAI21XLTS U1129 ( .A0(n4900), .A1(n4818), .B0(n4830), .Y(n4831) );
XOR2XLTS U1130 ( .A(n4503), .B(n203), .Y(n4515) );
OAI21XLTS U1131 ( .A0(n4551), .A1(n4569), .B0(n4502), .Y(n4503) );
XOR2XLTS U1132 ( .A(n4747), .B(n192), .Y(genblk1_left_mult_x_1_n1214) );
OAI21XLTS U1133 ( .A0(n4860), .A1(n4759), .B0(n4746), .Y(n4747) );
OAI21XLTS U1134 ( .A0(n4911), .A1(n4922), .B0(n4910), .Y(n4912) );
XOR2XLTS U1135 ( .A(n4918), .B(n179), .Y(genblk1_left_mult_x_1_n1295) );
INVX2TS U1136 ( .A(n4023), .Y(n4024) );
INVX2TS U1137 ( .A(n4022), .Y(n4025) );
XOR2XLTS U1138 ( .A(n4523), .B(n196), .Y(n4530) );
OAI21XLTS U1139 ( .A0(n4884), .A1(n4668), .B0(n4522), .Y(n4523) );
OAI21XLTS U1140 ( .A0(n4923), .A1(n4922), .B0(n4921), .Y(n4924) );
INVX2TS U1141 ( .A(n4153), .Y(n4154) );
XOR2XLTS U1142 ( .A(n4527), .B(n196), .Y(n4535) );
OAI21XLTS U1143 ( .A0(n4551), .A1(n4518), .B0(n4526), .Y(n4527) );
XOR2XLTS U1144 ( .A(n4231), .B(n192), .Y(n4284) );
OAI21XLTS U1145 ( .A0(n4551), .A1(n4766), .B0(n4230), .Y(n4231) );
XOR2XLTS U1146 ( .A(n178), .B(Data_A_i[31]), .Y(n681) );
OAI21XLTS U1147 ( .A0(n3692), .A1(n3791), .B0(n3349), .Y(n3350) );
CLKAND2X2TS U1148 ( .A(n288), .B(n219), .Y(n2976) );
XOR2XLTS U1149 ( .A(n3549), .B(n271), .Y(genblk1_right_mult_x_1_n1405) );
CLKAND2X2TS U1150 ( .A(n3753), .B(Data_B_i[26]), .Y(n3547) );
XOR2XLTS U1151 ( .A(n3324), .B(n256), .Y(genblk1_right_mult_x_1_n1275) );
XOR2XLTS U1152 ( .A(n3264), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1248) );
CLKAND2X2TS U1153 ( .A(n288), .B(n3723), .Y(genblk1_right_mult_x_1_n935) );
XOR2XLTS U1154 ( .A(n3368), .B(n280), .Y(genblk1_right_mult_x_1_n1303) );
XOR2XLTS U1155 ( .A(n3270), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1249) );
XOR2XLTS U1156 ( .A(n3514), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1384) );
OAI21XLTS U1157 ( .A0(n3692), .A1(n3522), .B0(n3513), .Y(n3514) );
CLKBUFX2TS U1158 ( .A(n3578), .Y(n3563) );
OAI21XLTS U1159 ( .A0(n352), .A1(n3379), .B0(n3373), .Y(n3374) );
XOR2XLTS U1160 ( .A(n3622), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1442) );
XOR2XLTS U1161 ( .A(n3037), .B(n256), .Y(n3046) );
OAI21XLTS U1162 ( .A0(n3746), .A1(n3305), .B0(n3036), .Y(n3037) );
OAI21XLTS U1163 ( .A0(n352), .A1(n3807), .B0(n3434), .Y(n3435) );
XOR2XLTS U1164 ( .A(n3747), .B(n279), .Y(n3794) );
OAI21XLTS U1165 ( .A0(n3746), .A1(n3791), .B0(n3745), .Y(n3747) );
CLKBUFX2TS U1166 ( .A(n3805), .Y(n3749) );
CLKBUFX2TS U1167 ( .A(n3383), .Y(n3416) );
XOR2X1TS U1168 ( .A(n3193), .B(n3192), .Y(n3695) );
OAI21XLTS U1169 ( .A0(n352), .A1(n3781), .B0(n3543), .Y(n3544) );
XOR2XLTS U1170 ( .A(n3728), .B(n263), .Y(n3768) );
OAI21XLTS U1171 ( .A0(n3746), .A1(n3765), .B0(n3727), .Y(n3728) );
XOR2X1TS U1172 ( .A(n2994), .B(n2993), .Y(n3719) );
CLKBUFX2TS U1173 ( .A(n3773), .Y(n3754) );
CLKBUFX2TS U1174 ( .A(n3703), .Y(n3733) );
INVX2TS U1175 ( .A(Data_B_i[3]), .Y(n236) );
OAI21XLTS U1176 ( .A0(n2665), .A1(n303), .B0(n2287), .Y(n2288) );
OAI21XLTS U1177 ( .A0(n2525), .A1(n2684), .B0(n2244), .Y(n2245) );
OAI21XLTS U1178 ( .A0(n2575), .A1(n302), .B0(n2322), .Y(n2323) );
INVX2TS U1179 ( .A(n2169), .Y(n2424) );
OAI21XLTS U1180 ( .A0(n2575), .A1(n2664), .B0(n1914), .Y(n1915) );
OAI21XLTS U1181 ( .A0(n2486), .A1(n2506), .B0(n2481), .Y(n2482) );
OAI21XLTS U1182 ( .A0(n2784), .A1(n2664), .B0(n2204), .Y(n2205) );
OAI21XLTS U1183 ( .A0(n2525), .A1(n2506), .B0(n2505), .Y(n2508) );
OAI21XLTS U1184 ( .A0(n2575), .A1(n2742), .B0(n2235), .Y(n2236) );
OAI21XLTS U1185 ( .A0(n2784), .A1(n2742), .B0(n2241), .Y(n2242) );
OAI21XLTS U1186 ( .A0(n2575), .A1(n2751), .B0(n1965), .Y(n1966) );
OAI21XLTS U1187 ( .A0(n2784), .A1(n2751), .B0(n2518), .Y(n2519) );
XNOR2X1TS U1188 ( .A(n1338), .B(n1339), .Y(n563) );
OAI21XLTS U1189 ( .A0(n2575), .A1(n2705), .B0(n2537), .Y(n2538) );
AOI22X1TS U1190 ( .A0(n2646), .A1(n2691), .B0(n2662), .B1(n2645), .Y(n2647)
);
INVX2TS U1191 ( .A(n564), .Y(n1223) );
OAI21XLTS U1192 ( .A0(n345), .A1(n2751), .B0(n1978), .Y(n1979) );
OAI21XLTS U1193 ( .A0(n2575), .A1(n2566), .B0(n2565), .Y(n2568) );
OAI21XLTS U1194 ( .A0(n2784), .A1(n2566), .B0(n2246), .Y(n2247) );
OAI21XLTS U1195 ( .A0(n2362), .A1(n2810), .B0(n1065), .Y(n1066) );
INVX2TS U1196 ( .A(n572), .Y(n2714) );
INVX2TS U1197 ( .A(n2162), .Y(n2706) );
OAI21XLTS U1198 ( .A0(n345), .A1(n2566), .B0(n2019), .Y(n2020) );
CLKBUFX2TS U1199 ( .A(n2791), .Y(n2108) );
NAND2X1TS U1200 ( .A(n1108), .B(n1128), .Y(n517) );
OAI21XLTS U1201 ( .A0(n1022), .A1(n1018), .B0(n1019), .Y(n1010) );
CLKAND2X2TS U1202 ( .A(n2405), .B(n2679), .Y(genblk1_middle_mult_x_1_n1005)
);
OAI21XLTS U1203 ( .A0(n22), .A1(n4569), .B0(n4568), .Y(n4570) );
XOR2XLTS U1204 ( .A(n4707), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1197) );
XOR2XLTS U1205 ( .A(n4575), .B(Data_A_i[50]), .Y(genblk1_left_mult_x_1_n1120) );
CLKBUFX2TS U1206 ( .A(n4599), .Y(n4654) );
XOR2XLTS U1207 ( .A(n4776), .B(n188), .Y(genblk1_left_mult_x_1_n1231) );
XOR2XLTS U1208 ( .A(n4735), .B(n192), .Y(genblk1_left_mult_x_1_n1209) );
OAI21XLTS U1209 ( .A0(n323), .A1(n4766), .B0(n4734), .Y(n4735) );
XOR2XLTS U1210 ( .A(n4896), .B(Data_A_i[32]), .Y(genblk1_left_mult_x_1_n1287) );
XOR2XLTS U1211 ( .A(n4225), .B(n4955), .Y(genblk1_left_mult_x_1_n1313) );
CLKBUFX2TS U1212 ( .A(n4538), .Y(n4816) );
XOR2XLTS U1213 ( .A(n4552), .B(Data_A_i[38]), .Y(n4560) );
OAI21XLTS U1214 ( .A0(n4551), .A1(n4538), .B0(n4550), .Y(n4552) );
ADDHXLTS U1215 ( .A(n1460), .B(n1459), .CO(genblk1_left_mult_x_1_n810), .S(
n717) );
NOR2BX1TS U1216 ( .AN(n685), .B(n662), .Y(n1459) );
XOR2XLTS U1217 ( .A(n656), .B(n183), .Y(n1460) );
INVX2TS U1218 ( .A(Data_A_i[23]), .Y(n253) );
NAND2BXLTS U1219 ( .AN(n3012), .B(n3013), .Y(n3271) );
INVX2TS U1220 ( .A(n3094), .Y(n3096) );
CLKAND2X2TS U1221 ( .A(n289), .B(n136), .Y(n2958) );
XOR2XLTS U1222 ( .A(n2956), .B(n263), .Y(n2957) );
OAI21XLTS U1223 ( .A0(n3665), .A1(n3454), .B0(n2955), .Y(n2956) );
CLKBUFX2TS U1224 ( .A(n3271), .Y(n3305) );
XOR2XLTS U1225 ( .A(n3403), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1322) );
XOR2XLTS U1226 ( .A(n3448), .B(n263), .Y(genblk1_right_mult_x_1_n1349) );
XOR2XLTS U1227 ( .A(n3458), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1353) );
XOR2XLTS U1228 ( .A(n3504), .B(n267), .Y(genblk1_right_mult_x_1_n1380) );
OAI21XLTS U1229 ( .A0(n3689), .A1(n3765), .B0(n3457), .Y(n3458) );
XOR2XLTS U1230 ( .A(n3481), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1365) );
XOR2XLTS U1231 ( .A(n3690), .B(n285), .Y(genblk1_right_mult_x_1_n1473) );
XOR2XLTS U1232 ( .A(n3534), .B(n268), .Y(genblk1_right_mult_x_1_n1392) );
XOR2XLTS U1233 ( .A(n3487), .B(n263), .Y(genblk1_right_mult_x_1_n1368) );
XOR2XLTS U1234 ( .A(n3585), .B(n271), .Y(genblk1_right_mult_x_1_n1422) );
XOR2XLTS U1235 ( .A(n3641), .B(n276), .Y(genblk1_right_mult_x_1_n1449) );
OAI21XLTS U1236 ( .A0(n917), .A1(n913), .B0(n914), .Y(n887) );
OAI21XLTS U1237 ( .A0(n352), .A1(n3775), .B0(n3590), .Y(n3591) );
XOR2XLTS U1238 ( .A(n3073), .B(n268), .Y(n3082) );
OAI21XLTS U1239 ( .A0(n3600), .A1(n3522), .B0(n3072), .Y(n3073) );
XOR2XLTS U1240 ( .A(n3080), .B(n266), .Y(n3722) );
OAI21XLTS U1241 ( .A0(n3079), .A1(n3522), .B0(n3078), .Y(n3080) );
OAI21XLTS U1242 ( .A0(n352), .A1(n3661), .B0(n3660), .Y(n3662) );
XOR2XLTS U1243 ( .A(n844), .B(n272), .Y(n874) );
OAI21XLTS U1244 ( .A0(n3746), .A1(n3599), .B0(n843), .Y(n844) );
XOR2X1TS U1245 ( .A(n882), .B(n877), .Y(n3751) );
AO21XLTS U1246 ( .A0(n1099), .A1(n1098), .B0(n1097), .Y(n319) );
OAI21XLTS U1247 ( .A0(n2595), .A1(n2751), .B0(n1976), .Y(n1977) );
XOR2XLTS U1248 ( .A(n2548), .B(n4983), .Y(genblk1_middle_mult_x_1_n1565) );
OAI21XLTS U1249 ( .A0(n2547), .A1(n2546), .B0(n2545), .Y(n2548) );
OAI21XLTS U1250 ( .A0(n2361), .A1(n2445), .B0(n1781), .Y(n1782) );
OAI21XLTS U1251 ( .A0(n2328), .A1(n2732), .B0(n1239), .Y(n1240) );
INVX2TS U1252 ( .A(n1181), .Y(n2800) );
INVX2TS U1253 ( .A(n817), .Y(n818) );
CLKAND2X2TS U1254 ( .A(n4039), .B(n118), .Y(n810) );
CLKAND2X2TS U1255 ( .A(n4466), .B(Data_A_i[51]), .Y(n3948) );
XOR2XLTS U1256 ( .A(n4610), .B(n198), .Y(genblk1_left_mult_x_1_n1143) );
OAI21XLTS U1257 ( .A0(n333), .A1(n4599), .B0(n4609), .Y(n4610) );
XOR2XLTS U1258 ( .A(n4578), .B(Data_A_i[50]), .Y(genblk1_left_mult_x_1_n1121) );
OAI21XLTS U1259 ( .A0(n24), .A1(n4452), .B0(n4577), .Y(n4578) );
XOR2XLTS U1260 ( .A(n4903), .B(n180), .Y(genblk1_left_mult_x_1_n1290) );
OAI21XLTS U1261 ( .A0(n22), .A1(n4905), .B0(n4902), .Y(n4903) );
XOR2XLTS U1262 ( .A(n4203), .B(n4955), .Y(genblk1_left_mult_x_1_n1319) );
OAI21XLTS U1263 ( .A0(n22), .A1(n4958), .B0(n4202), .Y(n4203) );
XOR2XLTS U1264 ( .A(n4856), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1271) );
XOR2XLTS U1265 ( .A(n4967), .B(n371), .Y(genblk1_left_mult_x_1_n1323) );
OAI21XLTS U1266 ( .A0(n328), .A1(n4875), .B0(n4855), .Y(n4856) );
AOI21X1TS U1267 ( .A0(n766), .A1(n3975), .B0(n765), .Y(n3978) );
OAI21XLTS U1268 ( .A0(n4392), .A1(n4389), .B0(n4393), .Y(n765) );
XOR2XLTS U1269 ( .A(n4866), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1275) );
XOR2XLTS U1270 ( .A(n4975), .B(n4981), .Y(genblk1_left_mult_x_1_n1327) );
OAI21XLTS U1271 ( .A0(n4942), .A1(n4875), .B0(n4865), .Y(n4866) );
OAI21X1TS U1272 ( .A0(n3973), .A1(n3970), .B0(n3971), .Y(n3975) );
XOR2XLTS U1273 ( .A(n700), .B(n4959), .Y(n718) );
XOR2XLTS U1274 ( .A(n690), .B(Data_A_i[32]), .Y(n719) );
XOR2XLTS U1275 ( .A(n685), .B(n684), .Y(n720) );
XOR2XLTS U1276 ( .A(n708), .B(Data_A_i[32]), .Y(n722) );
OAI21XLTS U1277 ( .A0(n4884), .A1(n4922), .B0(n707), .Y(n708) );
XOR2X1TS U1278 ( .A(n3119), .B(n3118), .Y(n3676) );
XOR2XLTS U1279 ( .A(n2950), .B(n281), .Y(n2951) );
CLKAND2X2TS U1280 ( .A(n37), .B(n155), .Y(n2946) );
XOR2XLTS U1281 ( .A(n2944), .B(n281), .Y(n2945) );
XOR2XLTS U1282 ( .A(n3178), .B(n36), .Y(genblk1_right_mult_x_1_n1233) );
OAI21XLTS U1283 ( .A0(n3689), .A1(n3269), .B0(n3177), .Y(n3178) );
XOR2XLTS U1284 ( .A(n3693), .B(n285), .Y(genblk1_right_mult_x_1_n1474) );
OAI21XLTS U1285 ( .A0(n3692), .A1(n3707), .B0(n3691), .Y(n3693) );
XOR2XLTS U1286 ( .A(n3702), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1477) );
XOR2XLTS U1287 ( .A(n3644), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1450) );
OAI21XLTS U1288 ( .A0(n3701), .A1(n3707), .B0(n3700), .Y(n3702) );
CMPR42X1TS U1289 ( .A(genblk1_right_mult_x_1_n1478), .B(
genblk1_right_mult_x_1_n1451), .C(genblk1_right_mult_x_1_n865), .D(
genblk1_right_mult_x_1_n859), .ICI(genblk1_right_mult_x_1_n862), .S(
genblk1_right_mult_x_1_n857), .ICO(genblk1_right_mult_x_1_n855), .CO(
genblk1_right_mult_x_1_n856) );
XOR2XLTS U1290 ( .A(n3709), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1478) );
XOR2XLTS U1291 ( .A(n3646), .B(n275), .Y(genblk1_right_mult_x_1_n1451) );
OAI21XLTS U1292 ( .A0(n3708), .A1(n3707), .B0(n3706), .Y(n3709) );
XOR2XLTS U1293 ( .A(n3593), .B(n270), .Y(genblk1_right_mult_x_1_n1427) );
XOR2XLTS U1294 ( .A(n3713), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1481) );
XOR2XLTS U1295 ( .A(n3652), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1454) );
NAND2BXLTS U1296 ( .AN(n855), .B(n857), .Y(n3663) );
XOR2XLTS U1297 ( .A(n2042), .B(n1354), .Y(genblk1_middle_mult_x_1_n1507) );
OAI21XLTS U1298 ( .A0(n2575), .A1(n2723), .B0(n2041), .Y(n2042) );
XOR2XLTS U1299 ( .A(n2558), .B(n2193), .Y(genblk1_middle_mult_x_1_n1510) );
XOR2XLTS U1300 ( .A(n2092), .B(n4983), .Y(genblk1_middle_mult_x_1_n1566) );
XOR2XLTS U1301 ( .A(n2581), .B(n2596), .Y(genblk1_middle_mult_x_1_n1570) );
XOR2XLTS U1302 ( .A(n4603), .B(n197), .Y(genblk1_left_mult_x_1_n1140) );
XOR2XLTS U1303 ( .A(n4567), .B(n202), .Y(genblk1_left_mult_x_1_n1115) );
OAI21XLTS U1304 ( .A0(n4951), .A1(n4599), .B0(n4602), .Y(n4603) );
CLKAND2X2TS U1305 ( .A(n289), .B(Data_B_i[22]), .Y(
genblk1_right_mult_x_1_n913) );
XOR2XLTS U1306 ( .A(n3273), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1254) );
XOR2XLTS U1307 ( .A(n3111), .B(n288), .Y(genblk1_right_mult_x_1_n1227) );
INVX2TS U1308 ( .A(n1355), .Y(n1358) );
NAND2X1TS U1309 ( .A(Data_A_i[46]), .B(Data_A_i[19]), .Y(n543) );
NOR2X1TS U1310 ( .A(n531), .B(n600), .Y(n385) );
INVX2TS U1311 ( .A(n1044), .Y(n1039) );
NOR2X1TS U1312 ( .A(n401), .B(n483), .Y(n409) );
NAND2X1TS U1313 ( .A(Data_A_i[51]), .B(Data_A_i[24]), .Y(n410) );
NAND2X1TS U1314 ( .A(n541), .B(n539), .Y(n537) );
AOI21X1TS U1315 ( .A0(n595), .A1(n594), .B0(n593), .Y(n596) );
NOR2XLTS U1316 ( .A(n1042), .B(n597), .Y(n599) );
NAND2X1TS U1317 ( .A(Data_A_i[43]), .B(Data_A_i[16]), .Y(n601) );
NOR2XLTS U1318 ( .A(n1042), .B(n576), .Y(n578) );
AOI21X1TS U1319 ( .A0(n595), .A1(n589), .B0(n574), .Y(n575) );
NAND2X1TS U1320 ( .A(Data_A_i[42]), .B(Data_A_i[15]), .Y(n580) );
AOI21X1TS U1321 ( .A0(n385), .A1(n593), .B0(n384), .Y(n386) );
INVX2TS U1322 ( .A(n1213), .Y(n1219) );
AOI21X1TS U1323 ( .A0(n1220), .A1(n1219), .B0(n1218), .Y(n1221) );
INVX2TS U1324 ( .A(n1217), .Y(n1218) );
NAND2X1TS U1325 ( .A(n1216), .B(n1219), .Y(n1222) );
NAND2X1TS U1326 ( .A(Data_A_i[31]), .B(Data_A_i[4]), .Y(n1225) );
INVX2TS U1327 ( .A(n1134), .Y(n1111) );
OAI21XLTS U1328 ( .A0(n313), .A1(n4597), .B0(n4473), .Y(n4474) );
OAI21XLTS U1329 ( .A0(n4923), .A1(n4538), .B0(n4794), .Y(n4795) );
CLKAND2X2TS U1330 ( .A(n36), .B(n132), .Y(n2954) );
OAI21XLTS U1331 ( .A0(n3686), .A1(n3345), .B0(n3344), .Y(n3346) );
XOR2XLTS U1332 ( .A(n3212), .B(n37), .Y(genblk1_right_mult_x_1_n1238) );
OAI21XLTS U1333 ( .A0(n3708), .A1(n3269), .B0(n3211), .Y(n3212) );
CLKAND2X2TS U1334 ( .A(n287), .B(n214), .Y(genblk1_right_mult_x_1_n926) );
CLKAND2X2TS U1335 ( .A(n36), .B(n226), .Y(n2977) );
OAI21XLTS U1336 ( .A0(n3701), .A1(n3416), .B0(n3412), .Y(n3413) );
OAI21XLTS U1337 ( .A0(n322), .A1(n3379), .B0(n3009), .Y(n3010) );
OAI21XLTS U1338 ( .A0(n3057), .A1(n3269), .B0(n3003), .Y(n3004) );
OAI21XLTS U1339 ( .A0(n2437), .A1(n302), .B0(n2187), .Y(n2188) );
OAI21XLTS U1340 ( .A0(n2765), .A1(n2361), .B0(n1024), .Y(n1025) );
OAI21XLTS U1341 ( .A0(n2765), .A1(n2732), .B0(n561), .Y(n562) );
OAI21XLTS U1342 ( .A0(n2765), .A1(n2810), .B0(n430), .Y(n431) );
NOR2XLTS U1343 ( .A(n1555), .B(n1554), .Y(n1558) );
XOR2X1TS U1344 ( .A(n1207), .B(n1354), .Y(n1238) );
CLKAND2X2TS U1345 ( .A(n4446), .B(n90), .Y(n4177) );
OAI21XLTS U1346 ( .A0(n4900), .A1(n4599), .B0(n4611), .Y(n4612) );
OAI21XLTS U1347 ( .A0(n4911), .A1(n4452), .B0(n4574), .Y(n4575) );
OAI21XLTS U1348 ( .A0(n4951), .A1(n4706), .B0(n4709), .Y(n4710) );
CLKAND2X2TS U1349 ( .A(n4446), .B(n75), .Y(n4424) );
OAI21XLTS U1350 ( .A0(n4911), .A1(n4654), .B0(n4620), .Y(n4621) );
OAI21XLTS U1351 ( .A0(n323), .A1(n4452), .B0(n4580), .Y(n4581) );
CLKAND2X2TS U1352 ( .A(n4446), .B(n67), .Y(n4159) );
OAI21XLTS U1353 ( .A0(n4900), .A1(n4706), .B0(n4718), .Y(n4719) );
OAI21XLTS U1354 ( .A0(n24), .A1(n4654), .B0(n4623), .Y(n4624) );
OAI21XLTS U1355 ( .A0(n4951), .A1(n4780), .B0(n4440), .Y(n4441) );
CLKAND2X2TS U1356 ( .A(n4446), .B(n70), .Y(n4437) );
OAI21XLTS U1357 ( .A0(n18), .A1(n4597), .B0(n4586), .Y(n4587) );
CLKAND2X2TS U1358 ( .A(n4446), .B(n4857), .Y(n4131) );
OAI21XLTS U1359 ( .A0(n4887), .A1(n4818), .B0(n4820), .Y(n4819) );
OAI21XLTS U1360 ( .A0(n4911), .A1(n4518), .B0(n4673), .Y(n4674) );
OAI21XLTS U1361 ( .A0(n367), .A1(n4818), .B0(n4824), .Y(n4825) );
AO21XLTS U1362 ( .A0(n4864), .A1(Data_B_i[51]), .B0(n4852), .Y(n4823) );
OAI21XLTS U1363 ( .A0(n320), .A1(n4766), .B0(n4724), .Y(n4725) );
OAI21XLTS U1364 ( .A0(n326), .A1(n4648), .B0(n4631), .Y(n4632) );
OAI21XLTS U1365 ( .A0(n22), .A1(n4780), .B0(n4777), .Y(n4778) );
OAI21XLTS U1366 ( .A0(n323), .A1(n4518), .B0(n4680), .Y(n4681) );
AO21XLTS U1367 ( .A0(n4940), .A1(n630), .B0(n4928), .Y(n4892) );
OAI21XLTS U1368 ( .A0(n320), .A1(n4538), .B0(n4782), .Y(n4783) );
OAI21XLTS U1369 ( .A0(n4942), .A1(n4597), .B0(n4596), .Y(n4598) );
OAI21XLTS U1370 ( .A0(n22), .A1(n4818), .B0(n4832), .Y(n4833) );
OAI21XLTS U1371 ( .A0(n4911), .A1(n4538), .B0(n4785), .Y(n4786) );
OAI21XLTS U1372 ( .A0(n18), .A1(n4704), .B0(n4688), .Y(n4689) );
OAI21XLTS U1373 ( .A0(n21), .A1(n4492), .B0(n4482), .Y(n4489) );
XOR2XLTS U1374 ( .A(n4486), .B(Data_A_i[50]), .Y(n4487) );
OAI21XLTS U1375 ( .A0(n24), .A1(n4538), .B0(n4788), .Y(n4789) );
OAI21XLTS U1376 ( .A0(n328), .A1(n4704), .B0(n4691), .Y(n4692) );
OAI21XLTS U1377 ( .A0(n4951), .A1(n4958), .B0(n4950), .Y(n4952) );
OAI21XLTS U1378 ( .A0(n4923), .A1(n4766), .B0(n4736), .Y(n4737) );
OAI21XLTS U1379 ( .A0(n4936), .A1(n4704), .B0(n4693), .Y(n4694) );
OAI21XLTS U1380 ( .A0(n313), .A1(n4648), .B0(n4643), .Y(n4644) );
OAI21XLTS U1381 ( .A0(n4911), .A1(n4883), .B0(n4839), .Y(n4840) );
OAI21XLTS U1382 ( .A0(n4876), .A1(n4648), .B0(n4647), .Y(n4649) );
OAI21XLTS U1383 ( .A0(n326), .A1(n4816), .B0(n4797), .Y(n4798) );
OAI21XLTS U1384 ( .A0(n4942), .A1(n4704), .B0(n4698), .Y(n4699) );
OAI21XLTS U1385 ( .A0(n4884), .A1(n4654), .B0(n4653), .Y(n4655) );
OAI21XLTS U1386 ( .A0(n313), .A1(n4704), .B0(n4703), .Y(n4705) );
OAI21XLTS U1387 ( .A0(n4541), .A1(n4452), .B0(n4298), .Y(n4299) );
OAI21XLTS U1388 ( .A0(n23), .A1(n4759), .B0(n4268), .Y(n4269) );
OAI21XLTS U1389 ( .A0(n4923), .A1(n4883), .B0(n4848), .Y(n4849) );
OAI21XLTS U1390 ( .A0(n326), .A1(n4875), .B0(n4850), .Y(n4851) );
OAI21XLTS U1391 ( .A0(n320), .A1(n4958), .B0(n4215), .Y(n4216) );
OAI21XLTS U1392 ( .A0(n4942), .A1(n4759), .B0(n4751), .Y(n4752) );
XOR2XLTS U1393 ( .A(n4245), .B(n199), .Y(n4264) );
OAI21XLTS U1394 ( .A0(n4551), .A1(n4654), .B0(n4244), .Y(n4245) );
OAI21XLTS U1395 ( .A0(n4876), .A1(n4704), .B0(n4251), .Y(n4252) );
OAI21XLTS U1396 ( .A0(n313), .A1(n4759), .B0(n4754), .Y(n4755) );
OAI21XLTS U1397 ( .A0(n4936), .A1(n4816), .B0(n4805), .Y(n4806) );
OAI21XLTS U1398 ( .A0(n323), .A1(n4922), .B0(n4919), .Y(n4920) );
OAI21XLTS U1399 ( .A0(n18), .A1(n4875), .B0(n4853), .Y(n4854) );
OAI21XLTS U1400 ( .A0(n4860), .A1(n4875), .B0(n4859), .Y(n4861) );
OAI21XLTS U1401 ( .A0(n4876), .A1(n4759), .B0(n4758), .Y(n4760) );
OAI21XLTS U1402 ( .A0(n4884), .A1(n4766), .B0(n4765), .Y(n4767) );
OAI21XLTS U1403 ( .A0(n313), .A1(n4816), .B0(n4815), .Y(n4817) );
OAI21XLTS U1404 ( .A0(n4936), .A1(n4875), .B0(n4862), .Y(n4863) );
OAI21XLTS U1405 ( .A0(n4541), .A1(n4518), .B0(n4519), .Y(n4520) );
INVX2TS U1406 ( .A(n4141), .Y(n4180) );
OAI21XLTS U1407 ( .A0(n23), .A1(n4875), .B0(n4285), .Y(n4286) );
OAI21XLTS U1408 ( .A0(n4876), .A1(n4816), .B0(n4237), .Y(n4238) );
XOR2XLTS U1409 ( .A(n4233), .B(n191), .Y(n4543) );
CLKBUFX2TS U1410 ( .A(n4814), .Y(n4796) );
CLKBUFX2TS U1411 ( .A(n4185), .Y(n4934) );
CLKBUFX2TS U1412 ( .A(n4867), .Y(n4852) );
OAI21XLTS U1413 ( .A0(n340), .A1(n3291), .B0(n3283), .Y(n3284) );
OAI21XLTS U1414 ( .A0(n3673), .A1(n3345), .B0(n3333), .Y(n3334) );
OAI21XLTS U1415 ( .A0(n3676), .A1(n3345), .B0(n3335), .Y(n3336) );
OAI21XLTS U1416 ( .A0(n3686), .A1(n3291), .B0(n3290), .Y(n3292) );
OAI21XLTS U1417 ( .A0(n3676), .A1(n3402), .B0(n3393), .Y(n3394) );
OAI21XLTS U1418 ( .A0(n340), .A1(n3402), .B0(n3395), .Y(n3396) );
OAI21XLTS U1419 ( .A0(n354), .A1(n3263), .B0(n3234), .Y(n3235) );
OAI21XLTS U1420 ( .A0(n3701), .A1(n3305), .B0(n3301), .Y(n3302) );
OAI21XLTS U1421 ( .A0(n336), .A1(n3402), .B0(n3399), .Y(n3400) );
OAI21XLTS U1422 ( .A0(n337), .A1(n3263), .B0(n3249), .Y(n3250) );
OAI21XLTS U1423 ( .A0(n3695), .A1(n3791), .B0(n3351), .Y(n3352) );
OAI21XLTS U1424 ( .A0(n3756), .A1(n3329), .B0(n3309), .Y(n3310) );
OAI21XLTS U1425 ( .A0(n324), .A1(n3791), .B0(n3353), .Y(n3354) );
OAI21XLTS U1426 ( .A0(n3673), .A1(n3508), .B0(n3497), .Y(n3498) );
OAI21XLTS U1427 ( .A0(n3692), .A1(n3416), .B0(n3406), .Y(n3407) );
OAI21XLTS U1428 ( .A0(n354), .A1(n3329), .B0(n3312), .Y(n3313) );
OAI21XLTS U1429 ( .A0(n3701), .A1(n3791), .B0(n3355), .Y(n3356) );
CLKAND2X2TS U1430 ( .A(n289), .B(n230), .Y(genblk1_right_mult_x_1_n930) );
XOR2XLTS U1431 ( .A(n3358), .B(n279), .Y(genblk1_right_mult_x_1_n1298) );
CLKAND2X2TS U1432 ( .A(n36), .B(n235), .Y(genblk1_right_mult_x_1_n931) );
XOR2XLTS U1433 ( .A(n3255), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1245) );
XOR2XLTS U1434 ( .A(n3317), .B(n255), .Y(genblk1_right_mult_x_1_n1272) );
OAI21XLTS U1435 ( .A0(n3673), .A1(n3563), .B0(n3552), .Y(n3553) );
OAI21XLTS U1436 ( .A0(n324), .A1(n3416), .B0(n3410), .Y(n3411) );
OAI21XLTS U1437 ( .A0(n354), .A1(n3379), .B0(n3361), .Y(n3362) );
OAI21XLTS U1438 ( .A0(n26), .A1(n3621), .B0(n3606), .Y(n3607) );
CLKAND2X2TS U1439 ( .A(n3638), .B(Data_B_i[26]), .Y(n3605) );
CLKAND2X2TS U1440 ( .A(n37), .B(n243), .Y(genblk1_right_mult_x_1_n933) );
XOR2XLTS U1441 ( .A(n3417), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1328) );
XOR2XLTS U1442 ( .A(n3261), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1247) );
OAI21XLTS U1443 ( .A0(n325), .A1(n3563), .B0(n3558), .Y(n3559) );
OAI21XLTS U1444 ( .A0(n324), .A1(n3765), .B0(n3463), .Y(n3464) );
OAI21XLTS U1445 ( .A0(n354), .A1(n3807), .B0(n3422), .Y(n3423) );
OAI21XLTS U1446 ( .A0(n26), .A1(n3685), .B0(n3668), .Y(n3669) );
CLKAND2X2TS U1447 ( .A(n3734), .B(Data_B_i[26]), .Y(n3667) );
OAI21XLTS U1448 ( .A0(n362), .A1(n3685), .B0(n3670), .Y(n3671) );
OAI21XLTS U1449 ( .A0(n3708), .A1(n3765), .B0(n3467), .Y(n3468) );
OAI21XLTS U1450 ( .A0(n337), .A1(n3807), .B0(n3424), .Y(n3425) );
XOR2XLTS U1451 ( .A(n3516), .B(n267), .Y(genblk1_right_mult_x_1_n1385) );
OAI21XLTS U1452 ( .A0(n340), .A1(n3621), .B0(n3614), .Y(n3615) );
OAI21XLTS U1453 ( .A0(n3701), .A1(n3522), .B0(n3519), .Y(n3520) );
OAI21XLTS U1454 ( .A0(n354), .A1(n3801), .B0(n3472), .Y(n3473) );
OAI21XLTS U1455 ( .A0(n3708), .A1(n3522), .B0(n3521), .Y(n3523) );
OAI21XLTS U1456 ( .A0(n3756), .A1(n3781), .B0(n3526), .Y(n3527) );
OAI21XLTS U1457 ( .A0(n3751), .A1(n3379), .B0(n3378), .Y(n3380) );
OAI21XLTS U1458 ( .A0(n3689), .A1(n3636), .B0(n3623), .Y(n3624) );
XOR2XLTS U1459 ( .A(n3477), .B(n263), .Y(genblk1_right_mult_x_1_n1362) );
OAI21XLTS U1460 ( .A0(n3715), .A1(n3801), .B0(n3476), .Y(n3477) );
XOR2XLTS U1461 ( .A(n3039), .B(n254), .Y(n3724) );
OAI21XLTS U1462 ( .A0(n3057), .A1(n3305), .B0(n3038), .Y(n3039) );
OAI21XLTS U1463 ( .A0(n3600), .A1(n3791), .B0(n3381), .Y(n3382) );
OAI21XLTS U1464 ( .A0(n3719), .A1(n3801), .B0(n3478), .Y(n3479) );
OAI21XLTS U1465 ( .A0(n3692), .A1(n3636), .B0(n3625), .Y(n3626) );
OAI21XLTS U1466 ( .A0(n3701), .A1(n3599), .B0(n3574), .Y(n3575) );
OAI21XLTS U1467 ( .A0(n3708), .A1(n3599), .B0(n3576), .Y(n3577) );
OAI21XLTS U1468 ( .A0(n337), .A1(n3781), .B0(n3531), .Y(n3532) );
OAI21XLTS U1469 ( .A0(n3686), .A1(n3685), .B0(n3684), .Y(n3687) );
XOR2XLTS U1470 ( .A(n3628), .B(n275), .Y(genblk1_right_mult_x_1_n1445) );
OAI21XLTS U1471 ( .A0(n3695), .A1(n3636), .B0(n3627), .Y(n3628) );
OAI21XLTS U1472 ( .A0(n322), .A1(n3801), .B0(n3800), .Y(n3802) );
XOR2XLTS U1473 ( .A(n3792), .B(n280), .Y(n3796) );
OAI21XLTS U1474 ( .A0(n314), .A1(n3791), .B0(n3790), .Y(n3792) );
XOR2XLTS U1475 ( .A(n3049), .B(n278), .Y(n3748) );
OAI21XLTS U1476 ( .A0(n3079), .A1(n3791), .B0(n3048), .Y(n3049) );
OAI21XLTS U1477 ( .A0(n3701), .A1(n3636), .B0(n3631), .Y(n3632) );
OAI21XLTS U1478 ( .A0(n322), .A1(n3781), .B0(n3537), .Y(n3538) );
OAI21XLTS U1479 ( .A0(n321), .A1(n3801), .B0(n3484), .Y(n3485) );
XOR2XLTS U1480 ( .A(n3053), .B(n260), .Y(n3063) );
OAI21XLTS U1481 ( .A0(n3600), .A1(n3765), .B0(n3488), .Y(n3489) );
XOR2X1TS U1482 ( .A(n3058), .B(n258), .Y(n3721) );
OAI21XLTS U1483 ( .A0(n3057), .A1(n3416), .B0(n3056), .Y(n3058) );
OAI21XLTS U1484 ( .A0(n322), .A1(n3775), .B0(n3774), .Y(n3776) );
XOR2XLTS U1485 ( .A(n3766), .B(n263), .Y(n3770) );
OAI21XLTS U1486 ( .A0(n314), .A1(n3765), .B0(n3764), .Y(n3766) );
OAI21XLTS U1487 ( .A0(n3756), .A1(n3737), .B0(n3736), .Y(n3738) );
XOR2XLTS U1488 ( .A(n3068), .B(n262), .Y(n3729) );
INVX2TS U1489 ( .A(n2682), .Y(n305) );
NAND2X1TS U1490 ( .A(n533), .B(n532), .Y(n534) );
AOI21X1TS U1491 ( .A0(n1359), .A1(n530), .B0(n529), .Y(n535) );
INVX2TS U1492 ( .A(n531), .Y(n533) );
NOR2XLTS U1493 ( .A(n1566), .B(n1524), .Y(n1526) );
OAI21XLTS U1494 ( .A0(n2477), .A1(n2393), .B0(n1887), .Y(n1888) );
CLKAND2X2TS U1495 ( .A(n2779), .B(n25), .Y(genblk1_middle_mult_x_1_n1017) );
OAI21XLTS U1496 ( .A0(n2477), .A1(n2684), .B0(n1934), .Y(n1935) );
OAI21XLTS U1497 ( .A0(n2547), .A1(n2684), .B0(n1937), .Y(n1938) );
OAI21XLTS U1498 ( .A0(n2495), .A1(n2524), .B0(n1957), .Y(n1958) );
OAI21XLTS U1499 ( .A0(n2437), .A1(n2742), .B0(n2430), .Y(n2431) );
INVX2TS U1500 ( .A(n1188), .Y(n1178) );
OAI21XLTS U1501 ( .A0(n2547), .A1(n2524), .B0(n1959), .Y(n1960) );
INVX2TS U1502 ( .A(n572), .Y(n2526) );
XOR2XLTS U1503 ( .A(n2350), .B(n2666), .Y(genblk1_middle_mult_x_1_n1354) );
OAI21XLTS U1504 ( .A0(n2477), .A1(n2506), .B0(n2448), .Y(n2449) );
OAI21XLTS U1505 ( .A0(n20), .A1(n302), .B0(n1821), .Y(n1822) );
OAI21XLTS U1506 ( .A0(n2547), .A1(n2506), .B0(n1983), .Y(n1984) );
XOR2XLTS U1507 ( .A(n2502), .B(n547), .Y(genblk1_middle_mult_x_1_n1385) );
OAI21XLTS U1508 ( .A0(n2437), .A1(n2506), .B0(n2434), .Y(n2435) );
OAI21XLTS U1509 ( .A0(n2535), .A1(n2491), .B0(n2490), .Y(n2492) );
OAI21XLTS U1510 ( .A0(n2547), .A1(n2445), .B0(n2007), .Y(n2008) );
NAND2X1TS U1511 ( .A(n1539), .B(n1541), .Y(n1540) );
OAI21XLTS U1512 ( .A0(n2437), .A1(n2445), .B0(n2009), .Y(n2010) );
OAI21XLTS U1513 ( .A0(n2648), .A1(n2361), .B0(n1921), .Y(n1922) );
NAND2X1TS U1514 ( .A(n32), .B(n1586), .Y(n1587) );
INVX2TS U1515 ( .A(n1581), .Y(n1584) );
OAI21XLTS U1516 ( .A0(n2477), .A1(n2464), .B0(n2033), .Y(n2034) );
NAND2X1TS U1517 ( .A(n31), .B(n1543), .Y(n1544) );
NAND2X1TS U1518 ( .A(n1505), .B(n1578), .Y(n1579) );
NAND2X1TS U1519 ( .A(n1573), .B(n1575), .Y(n1574) );
OAI21XLTS U1520 ( .A0(n2547), .A1(n2464), .B0(n2035), .Y(n2036) );
OAI21XLTS U1521 ( .A0(n2362), .A1(n2361), .B0(n2360), .Y(n2363) );
NAND2X1TS U1522 ( .A(n589), .B(n588), .Y(n590) );
AOI21X1TS U1523 ( .A0(n1359), .A1(n587), .B0(n586), .Y(n591) );
AO21X1TS U1524 ( .A0(n1038), .A1(n592), .B0(n595), .Y(n586) );
OAI21XLTS U1525 ( .A0(n20), .A1(n2751), .B0(n1758), .Y(n1759) );
NAND2X1TS U1526 ( .A(n1120), .B(n1122), .Y(n1121) );
NAND2X1TS U1527 ( .A(n35), .B(n1117), .Y(n1118) );
AOI21X1TS U1528 ( .A0(n1133), .A1(n1116), .B0(n1115), .Y(n1119) );
NOR2XLTS U1529 ( .A(n1114), .B(n1127), .Y(n1116) );
OAI21XLTS U1530 ( .A0(n2713), .A1(n2361), .B0(n2237), .Y(n2238) );
OAI21XLTS U1531 ( .A0(n2784), .A1(n2723), .B0(n2529), .Y(n2530) );
AOI222XLTS U1532 ( .A0(n2721), .A1(n2780), .B0(n2555), .B1(n2528), .C0(n2554), .C1(n2777), .Y(n2529) );
OAI21XLTS U1533 ( .A0(n2713), .A1(n2732), .B0(n2712), .Y(n2715) );
AOI222XLTS U1534 ( .A0(n2730), .A1(n2700), .B0(n2728), .B1(n2227), .C0(n2726), .C1(n2645), .Y(n1781) );
CLKBUFX2TS U1535 ( .A(n2025), .Y(n2464) );
INVX2TS U1536 ( .A(n1340), .Y(n2815) );
INVX2TS U1537 ( .A(n1340), .Y(n2812) );
NAND2X1TS U1538 ( .A(n509), .B(n513), .Y(n510) );
AOI21X1TS U1539 ( .A0(n1133), .A1(n508), .B0(n507), .Y(n511) );
NAND2X1TS U1540 ( .A(n3), .B(n504), .Y(n496) );
INVX2TS U1541 ( .A(n3988), .Y(n636) );
CLKAND2X2TS U1542 ( .A(n4490), .B(n98), .Y(n4208) );
INVX2TS U1543 ( .A(n3989), .Y(n4036) );
INVX2TS U1544 ( .A(n4035), .Y(n3990) );
OAI21XLTS U1545 ( .A0(n22), .A1(n4599), .B0(n4613), .Y(n4614) );
XOR2XLTS U1546 ( .A(n4630), .B(n198), .Y(genblk1_left_mult_x_1_n1152) );
XOR2XLTS U1547 ( .A(n4822), .B(n184), .Y(genblk1_left_mult_x_1_n1256) );
OAI21XLTS U1548 ( .A0(n4923), .A1(n4654), .B0(n4629), .Y(n4630) );
XOR2XLTS U1549 ( .A(n4589), .B(n202), .Y(genblk1_left_mult_x_1_n1126) );
XOR2XLTS U1550 ( .A(n4677), .B(n194), .Y(genblk1_left_mult_x_1_n1178) );
XOR2XLTS U1551 ( .A(n4638), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1155) );
XOR2XLTS U1552 ( .A(n4731), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1207) );
XOR2XLTS U1553 ( .A(n4829), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1259) );
XOR2XLTS U1554 ( .A(n4891), .B(n180), .Y(genblk1_left_mult_x_1_n1285) );
XOR2XLTS U1555 ( .A(n4641), .B(n198), .Y(genblk1_left_mult_x_1_n1159) );
XOR2XLTS U1556 ( .A(n4901), .B(Data_A_i[32]), .Y(genblk1_left_mult_x_1_n1289) );
XOR2XLTS U1557 ( .A(n4837), .B(n184), .Y(genblk1_left_mult_x_1_n1263) );
OAI21XLTS U1558 ( .A0(n326), .A1(n4759), .B0(n4738), .Y(n4739) );
XOR2XLTS U1559 ( .A(n4749), .B(n191), .Y(genblk1_left_mult_x_1_n1215) );
XOR2XLTS U1560 ( .A(n4847), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1267) );
XOR2XLTS U1561 ( .A(n4924), .B(n180), .Y(genblk1_left_mult_x_1_n1297) );
XOR2XLTS U1562 ( .A(n4757), .B(n191), .Y(genblk1_left_mult_x_1_n1219) );
OAI21XLTS U1563 ( .A0(n313), .A1(n4875), .B0(n4868), .Y(n4869) );
OAI21XLTS U1564 ( .A0(n4876), .A1(n4875), .B0(n4874), .Y(n4877) );
OAI21XLTS U1565 ( .A0(n4860), .A1(n4980), .B0(n4222), .Y(n4223) );
OAI21XLTS U1566 ( .A0(n4942), .A1(n4886), .B0(n4941), .Y(n4943) );
OAI21XLTS U1567 ( .A0(n313), .A1(n4886), .B0(n4948), .Y(n4949) );
XOR2XLTS U1568 ( .A(n4542), .B(n187), .Y(n4553) );
OAI21XLTS U1569 ( .A0(n4541), .A1(n4538), .B0(n4540), .Y(n4542) );
CLKBUFX2TS U1570 ( .A(n3047), .Y(n3345) );
CLKBUFX2TS U1571 ( .A(n3383), .Y(n3402) );
XOR2XLTS U1572 ( .A(n3446), .B(n263), .Y(genblk1_right_mult_x_1_n1348) );
XOR2XLTS U1573 ( .A(n3350), .B(n281), .Y(genblk1_right_mult_x_1_n1294) );
CMPR42X1TS U1574 ( .A(genblk1_right_mult_x_1_n1350), .B(
genblk1_right_mult_x_1_n1323), .C(genblk1_right_mult_x_1_n654), .D(
genblk1_right_mult_x_1_n643), .ICI(genblk1_right_mult_x_1_n651), .S(
genblk1_right_mult_x_1_n638), .ICO(genblk1_right_mult_x_1_n636), .CO(
genblk1_right_mult_x_1_n637) );
XOR2XLTS U1575 ( .A(n3405), .B(n260), .Y(genblk1_right_mult_x_1_n1323) );
XOR2XLTS U1576 ( .A(n3502), .B(n268), .Y(genblk1_right_mult_x_1_n1379) );
XOR2XLTS U1577 ( .A(n3315), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1271) );
XOR2XLTS U1578 ( .A(n3455), .B(n263), .Y(genblk1_right_mult_x_1_n1352) );
XOR2XLTS U1579 ( .A(n3557), .B(n271), .Y(genblk1_right_mult_x_1_n1409) );
XOR2XLTS U1580 ( .A(n3364), .B(n281), .Y(genblk1_right_mult_x_1_n1301) );
XOR2XLTS U1581 ( .A(n3509), .B(n268), .Y(genblk1_right_mult_x_1_n1382) );
XOR2XLTS U1582 ( .A(n3512), .B(n268), .Y(genblk1_right_mult_x_1_n1383) );
OAI21XLTS U1583 ( .A0(n3689), .A1(n3522), .B0(n3511), .Y(n3512) );
XOR2XLTS U1584 ( .A(n3567), .B(n271), .Y(genblk1_right_mult_x_1_n1413) );
XOR2XLTS U1585 ( .A(n3518), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1386) );
CLKBUFX2TS U1586 ( .A(n3524), .Y(n3781) );
OAI21XLTS U1587 ( .A0(n354), .A1(n3737), .B0(n3710), .Y(n3711) );
OAI21XLTS U1588 ( .A0(n3719), .A1(n3661), .B0(n3649), .Y(n3650) );
OAI21XLTS U1589 ( .A0(n3600), .A1(n3599), .B0(n3598), .Y(n3601) );
OAI21XLTS U1590 ( .A0(n3719), .A1(n3737), .B0(n3718), .Y(n3720) );
OAI21XLTS U1591 ( .A0(n322), .A1(n3737), .B0(n858), .Y(n859) );
INVX2TS U1592 ( .A(n913), .Y(n915) );
AOI21X1TS U1593 ( .A0(n1099), .A1(n1094), .B0(n417), .Y(n418) );
INVX2TS U1594 ( .A(n2169), .Y(n2686) );
CLKAND2X2TS U1595 ( .A(n2748), .B(n2315), .Y(n1944) );
XOR2XLTS U1596 ( .A(n2395), .B(n2394), .Y(genblk1_middle_mult_x_1_n1342) );
INVX2TS U1597 ( .A(n572), .Y(n2753) );
XOR2XLTS U1598 ( .A(n2050), .B(n2411), .Y(genblk1_middle_mult_x_1_n1526) );
OAI21XLTS U1599 ( .A0(n2784), .A1(n2705), .B0(n2551), .Y(n2553) );
CLKBUFX2TS U1600 ( .A(n2082), .Y(n2515) );
XOR2X1TS U1601 ( .A(n1970), .B(n1772), .Y(n2752) );
AOI222XLTS U1602 ( .A0(n2569), .A1(n2578), .B0(n2777), .B1(n2794), .C0(n2772), .C1(n2671), .Y(n2570) );
OAI21XLTS U1603 ( .A0(n2764), .A1(n2546), .B0(n1267), .Y(n1268) );
OAI21XLTS U1604 ( .A0(n367), .A1(n4569), .B0(n4562), .Y(n4563) );
AO21XLTS U1605 ( .A0(n4594), .A1(n630), .B0(n4585), .Y(n4561) );
CLKAND2X2TS U1606 ( .A(n4039), .B(n111), .Y(n3947) );
XOR2XLTS U1607 ( .A(n4608), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1142) );
XOR2XLTS U1608 ( .A(n4570), .B(n203), .Y(genblk1_left_mult_x_1_n1117) );
OAI21XLTS U1609 ( .A0(n4954), .A1(n4599), .B0(n4607), .Y(n4608) );
XOR2XLTS U1610 ( .A(n4572), .B(n202), .Y(genblk1_left_mult_x_1_n1119) );
XOR2XLTS U1611 ( .A(n4658), .B(n196), .Y(genblk1_left_mult_x_1_n1170) );
OAI21XLTS U1612 ( .A0(n320), .A1(n4452), .B0(n4571), .Y(n4572) );
XOR2XLTS U1613 ( .A(n4618), .B(n199), .Y(genblk1_left_mult_x_1_n1147) );
XOR2XLTS U1614 ( .A(n4713), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1199) );
OAI21XLTS U1615 ( .A0(n320), .A1(n4654), .B0(n4617), .Y(n4618) );
XOR2XLTS U1616 ( .A(n4960), .B(n4959), .Y(genblk1_left_mult_x_1_n1317) );
OAI21XLTS U1617 ( .A0(n333), .A1(n4958), .B0(n4957), .Y(n4960) );
XOR2XLTS U1618 ( .A(n4915), .B(n179), .Y(genblk1_left_mult_x_1_n1294) );
XOR2XLTS U1619 ( .A(n4811), .B(n188), .Y(genblk1_left_mult_x_1_n1246) );
OAI21XLTS U1620 ( .A0(n4942), .A1(n4816), .B0(n4810), .Y(n4811) );
XOR2XLTS U1621 ( .A(n4220), .B(n4981), .Y(genblk1_left_mult_x_1_n1326) );
XOR2XLTS U1622 ( .A(n4933), .B(Data_A_i[32]), .Y(genblk1_left_mult_x_1_n1300) );
OAI21XLTS U1623 ( .A0(n4923), .A1(n4971), .B0(n4219), .Y(n4220) );
XOR2XLTS U1624 ( .A(n4872), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1277) );
XOR2XLTS U1625 ( .A(n4939), .B(n179), .Y(genblk1_left_mult_x_1_n1303) );
XOR2XLTS U1626 ( .A(n4198), .B(n4981), .Y(genblk1_left_mult_x_1_n1329) );
CMPR42X1TS U1627 ( .A(genblk1_left_mult_x_1_n807), .B(
genblk1_left_mult_x_1_n1279), .C(genblk1_left_mult_x_1_n810), .D(
genblk1_left_mult_x_1_n1305), .ICI(genblk1_left_mult_x_1_n1331), .S(
genblk1_left_mult_x_1_n805), .ICO(genblk1_left_mult_x_1_n803), .CO(
genblk1_left_mult_x_1_n804) );
XOR2XLTS U1628 ( .A(n4187), .B(n4959), .Y(genblk1_left_mult_x_1_n1331) );
XOR2XLTS U1629 ( .A(n4949), .B(n179), .Y(genblk1_left_mult_x_1_n1305) );
XOR2XLTS U1630 ( .A(n4885), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1279) );
XOR2XLTS U1631 ( .A(n683), .B(Data_A_i[32]), .Y(n715) );
XOR2XLTS U1632 ( .A(n670), .B(n4959), .Y(n716) );
XOR2XLTS U1633 ( .A(n730), .B(n4959), .Y(n755) );
XOR2XLTS U1634 ( .A(n712), .B(Data_A_i[32]), .Y(n745) );
XOR2XLTS U1635 ( .A(n743), .B(n4959), .Y(n747) );
NAND2X1TS U1636 ( .A(n659), .B(n702), .Y(n4551) );
OR2X1TS U1637 ( .A(n4548), .B(n4539), .Y(n659) );
CLKBUFX2TS U1638 ( .A(n4961), .Y(n4977) );
NOR2X1TS U1639 ( .A(n668), .B(n666), .Y(n4221) );
CLKAND2X2TS U1640 ( .A(n3091), .B(n1431), .Y(n1433) );
CLKAND2X2TS U1641 ( .A(n3224), .B(n42), .Y(n1426) );
XOR2XLTS U1642 ( .A(n3167), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1232) );
XOR2XLTS U1643 ( .A(n3188), .B(n287), .Y(genblk1_right_mult_x_1_n1234) );
OAI21XLTS U1644 ( .A0(n3692), .A1(n3269), .B0(n3187), .Y(n3188) );
XOR2XLTS U1645 ( .A(n3296), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1264) );
XOR2XLTS U1646 ( .A(n3619), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1441) );
NOR2XLTS U1647 ( .A(n2898), .B(n3892), .Y(n2892) );
XOR2XLTS U1648 ( .A(n3630), .B(n276), .Y(genblk1_right_mult_x_1_n1446) );
OAI21XLTS U1649 ( .A0(n324), .A1(n3636), .B0(n3629), .Y(n3630) );
XOR2XLTS U1650 ( .A(n3637), .B(n275), .Y(genblk1_right_mult_x_1_n1448) );
XOR2XLTS U1651 ( .A(n3696), .B(n283), .Y(genblk1_right_mult_x_1_n1475) );
OAI21XLTS U1652 ( .A0(n3708), .A1(n3636), .B0(n3635), .Y(n3637) );
XOR2XLTS U1653 ( .A(n3589), .B(n272), .Y(genblk1_right_mult_x_1_n1425) );
XOR2XLTS U1654 ( .A(n3648), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1452) );
OAI21XLTS U1655 ( .A0(n3655), .A1(n3775), .B0(n3588), .Y(n3589) );
XOR2XLTS U1656 ( .A(n3595), .B(n272), .Y(genblk1_right_mult_x_1_n1428) );
XOR2XLTS U1657 ( .A(n3656), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1455) );
XOR2XLTS U1658 ( .A(n3716), .B(n284), .Y(genblk1_right_mult_x_1_n1482) );
XOR2XLTS U1659 ( .A(n879), .B(n276), .Y(n908) );
XOR2XLTS U1660 ( .A(n889), .B(n284), .Y(n907) );
OAI21XLTS U1661 ( .A0(n3751), .A1(n3661), .B0(n878), .Y(n879) );
OAI21XLTS U1662 ( .A0(n3600), .A1(n3636), .B0(n896), .Y(n897) );
XOR2XLTS U1663 ( .A(n938), .B(n285), .Y(n942) );
OAI21XLTS U1664 ( .A0(n321), .A1(n3737), .B0(n937), .Y(n938) );
OAI21XLTS U1665 ( .A0(n3600), .A1(n3707), .B0(n925), .Y(n926) );
XOR2XLTS U1666 ( .A(n1603), .B(n2225), .Y(n1639) );
CLKAND2X2TS U1667 ( .A(n2222), .B(n2679), .Y(n1657) );
AOI21X1TS U1668 ( .A0(n1680), .A1(n1331), .B0(n1330), .Y(n1621) );
OAI21XLTS U1669 ( .A0(n2477), .A1(n2409), .B0(n2059), .Y(n2060) );
OAI21XLTS U1670 ( .A0(n2477), .A1(n2546), .B0(n2089), .Y(n2090) );
OAI21XLTS U1671 ( .A0(n2784), .A1(n2571), .B0(n2071), .Y(n2072) );
XOR2XLTS U1672 ( .A(n2597), .B(n2596), .Y(genblk1_middle_mult_x_1_n1571) );
OAI21XLTS U1673 ( .A0(n19), .A1(n2594), .B0(n1287), .Y(n1288) );
OAI21XLTS U1674 ( .A0(n20), .A1(n2594), .B0(n1251), .Y(n1252) );
OAI21XLTS U1675 ( .A0(n2361), .A1(n2546), .B0(n1255), .Y(n1256) );
NAND2X1TS U1676 ( .A(n425), .B(n556), .Y(n2810) );
OR2X1TS U1677 ( .A(n2808), .B(n2804), .Y(n425) );
CLKBUFX2TS U1678 ( .A(n2082), .Y(n2546) );
NAND2BX1TS U1679 ( .AN(n566), .B(n1243), .Y(n2082) );
CLKAND2X2TS U1680 ( .A(n4490), .B(n39), .Y(n822) );
INVX2TS U1681 ( .A(n815), .Y(n804) );
XOR2XLTS U1682 ( .A(n4600), .B(n199), .Y(genblk1_left_mult_x_1_n1139) );
XOR2XLTS U1683 ( .A(n4565), .B(n203), .Y(genblk1_left_mult_x_1_n1114) );
OAI21XLTS U1684 ( .A0(n4165), .A1(n4168), .B0(n4169), .Y(n796) );
OR2X1TS U1685 ( .A(genblk1_left_mult_x_1_n500), .B(
genblk1_left_mult_x_1_n497), .Y(n4080) );
OR2X1TS U1686 ( .A(genblk1_left_mult_x_1_n512), .B(
genblk1_left_mult_x_1_n506), .Y(n4309) );
AOI21X1TS U1687 ( .A0(n4399), .A1(n4398), .B0(n764), .Y(n3973) );
OR2X1TS U1688 ( .A(genblk1_left_mult_x_1_n800), .B(
genblk1_left_mult_x_1_n804), .Y(n4398) );
OAI21XLTS U1689 ( .A0(n4404), .A1(n4401), .B0(n4405), .Y(n761) );
NOR2XLTS U1690 ( .A(n4403), .B(n4404), .Y(n762) );
OAI21XLTS U1691 ( .A0(n3956), .A1(n3952), .B0(n3953), .Y(n4411) );
NOR2XLTS U1692 ( .A(n747), .B(n746), .Y(n3952) );
NOR2XLTS U1693 ( .A(n3951), .B(n3950), .Y(n4415) );
INVX2TS U1694 ( .A(genblk1_left_mult_x_1_n1787), .Y(n735) );
INVX2TS U1695 ( .A(Data_B_i[27]), .Y(n4506) );
CLKBUFX2TS U1696 ( .A(n4221), .Y(n4978) );
CLKAND2X2TS U1697 ( .A(n37), .B(n172), .Y(genblk1_right_mult_x_1_n912) );
XOR2XLTS U1698 ( .A(n3100), .B(n36), .Y(genblk1_right_mult_x_1_n1226) );
XOR2XLTS U1699 ( .A(n3121), .B(Data_A_i[26]), .Y(
genblk1_right_mult_x_1_n1228) );
XOR2XLTS U1700 ( .A(n3276), .B(n255), .Y(genblk1_right_mult_x_1_n1255) );
OAI21XLTS U1701 ( .A0(n3676), .A1(n3166), .B0(n3120), .Y(n3121) );
XOR2XLTS U1702 ( .A(n3280), .B(n255), .Y(genblk1_right_mult_x_1_n1257) );
XOR2XLTS U1703 ( .A(n3145), .B(n288), .Y(genblk1_right_mult_x_1_n1230) );
OAI21XLTS U1704 ( .A0(n3673), .A1(n3291), .B0(n3279), .Y(n3280) );
NOR2XLTS U1705 ( .A(n2907), .B(n3914), .Y(n963) );
OAI21XLTS U1706 ( .A0(n2907), .A1(n3915), .B0(n2908), .Y(n962) );
OR2X1TS U1707 ( .A(genblk1_right_mult_x_1_n857), .B(
genblk1_right_mult_x_1_n863), .Y(n3911) );
OR2X1TS U1708 ( .A(genblk1_right_mult_x_1_n864), .B(
genblk1_right_mult_x_1_n870), .Y(n3908) );
OR2X1TS U1709 ( .A(genblk1_right_mult_x_1_n883), .B(
genblk1_right_mult_x_1_n887), .Y(n3920) );
NOR2XLTS U1710 ( .A(n942), .B(n941), .Y(n3933) );
NOR2XLTS U1711 ( .A(n929), .B(n928), .Y(n3938) );
OAI21XLTS U1712 ( .A0(n314), .A1(n3707), .B0(n920), .Y(n921) );
INVX2TS U1713 ( .A(genblk1_right_N0), .Y(n924) );
CLKBUFX2TS U1714 ( .A(n3663), .Y(n3707) );
OAI21X1TS U1715 ( .A0(n2257), .A1(n1399), .B0(n1398), .Y(n2114) );
INVX2TS U1716 ( .A(genblk1_middle_N0), .Y(n1263) );
XOR2XLTS U1717 ( .A(n1458), .B(n1457), .Y(genblk1_left_N46) );
XNOR2X1TS U1718 ( .A(genblk1_left_mult_x_1_n489), .B(
genblk1_left_mult_x_1_n491), .Y(n1457) );
OAI21XLTS U1719 ( .A0(n1027), .A1(n1346), .B0(n1345), .Y(n1347) );
NOR2XLTS U1720 ( .A(n1026), .B(n1346), .Y(n1348) );
NOR2XLTS U1721 ( .A(n1185), .B(n1188), .Y(n1191) );
INVX2TS U1722 ( .A(n1184), .Y(n1185) );
INVX2TS U1723 ( .A(n536), .Y(n541) );
NOR2X1TS U1724 ( .A(Data_A_i[45]), .B(Data_A_i[18]), .Y(n536) );
NOR2X1TS U1725 ( .A(Data_A_i[39]), .B(Data_A_i[12]), .Y(n1044) );
NOR2XLTS U1726 ( .A(n1042), .B(n1044), .Y(n1047) );
NAND2X1TS U1727 ( .A(Data_A_i[39]), .B(Data_A_i[12]), .Y(n1043) );
NAND2X1TS U1728 ( .A(Data_A_i[36]), .B(Data_A_i[9]), .Y(n1350) );
NAND2X1TS U1729 ( .A(n1362), .B(n1361), .Y(n1363) );
AOI21X1TS U1730 ( .A0(n1359), .A1(n1358), .B0(n1357), .Y(n1364) );
NAND2X1TS U1731 ( .A(n1351), .B(n1350), .Y(n1352) );
AOI21X1TS U1732 ( .A0(n1359), .A1(n1348), .B0(n1347), .Y(n1353) );
INVX2TS U1733 ( .A(n1349), .Y(n1351) );
AOI21X1TS U1734 ( .A0(n1220), .A1(n1191), .B0(n1190), .Y(n1192) );
OAI21XLTS U1735 ( .A0(n1189), .A1(n1188), .B0(n1187), .Y(n1190) );
NAND2X1TS U1736 ( .A(n1216), .B(n1191), .Y(n1193) );
NAND2X1TS U1737 ( .A(Data_A_i[33]), .B(Data_A_i[6]), .Y(n1195) );
NOR2XLTS U1738 ( .A(n2980), .B(n3244), .Y(n1404) );
XOR2X1TS U1739 ( .A(n546), .B(n545), .Y(n549) );
NAND2X1TS U1740 ( .A(n544), .B(n543), .Y(n545) );
AOI21X1TS U1741 ( .A0(n1099), .A1(n541), .B0(n540), .Y(n546) );
OAI21XLTS U1742 ( .A0(n464), .A1(n474), .B0(n475), .Y(n465) );
NOR2XLTS U1743 ( .A(n463), .B(n474), .Y(n466) );
NAND2X1TS U1744 ( .A(Data_A_i[48]), .B(Data_A_i[21]), .Y(n468) );
AOI21X1TS U1745 ( .A0(n1547), .A1(n1503), .B0(n1531), .Y(n1532) );
OAI21X1TS U1746 ( .A0(n588), .A1(n579), .B0(n580), .Y(n593) );
INVX2TS U1747 ( .A(n594), .Y(n523) );
NAND2X1TS U1748 ( .A(n526), .B(n592), .Y(n528) );
NAND2X1TS U1749 ( .A(n249), .B(n121), .Y(n1534) );
NAND2X2TS U1750 ( .A(n358), .B(n1503), .Y(n1512) );
AOI21X1TS U1751 ( .A0(n1099), .A1(n1094), .B0(n416), .Y(n415) );
NAND2X1TS U1752 ( .A(n365), .B(n410), .Y(n406) );
NOR2XLTS U1753 ( .A(n479), .B(n403), .Y(n405) );
NOR2X1TS U1754 ( .A(n536), .B(n542), .Y(n473) );
NAND2X1TS U1755 ( .A(n278), .B(n197), .Y(n475) );
OAI21XLTS U1756 ( .A0(n327), .A1(n2742), .B0(n553), .Y(n554) );
AOI21X1TS U1757 ( .A0(n393), .A1(n472), .B0(n392), .Y(n480) );
NAND2X1TS U1758 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n484) );
NOR2X1TS U1759 ( .A(Data_A_i[49]), .B(Data_A_i[22]), .Y(n483) );
AOI21X1TS U1760 ( .A0(n1505), .A1(n1519), .B0(n1518), .Y(n1520) );
INVX2TS U1761 ( .A(n1578), .Y(n1518) );
INVX2TS U1762 ( .A(n1543), .Y(n1516) );
AOI21X1TS U1763 ( .A0(n1201), .A1(n1029), .B0(n1028), .Y(n1356) );
NAND2X1TS U1764 ( .A(n1202), .B(n1029), .Y(n1355) );
AOI21X1TS U1765 ( .A0(n35), .A1(n1111), .B0(n1081), .Y(n1082) );
INVX2TS U1766 ( .A(n1117), .Y(n1081) );
OAI21XLTS U1767 ( .A0(n1856), .A1(n1874), .B0(n1875), .Y(n1857) );
INVX2TS U1768 ( .A(n1869), .Y(n1856) );
XOR2X1TS U1769 ( .A(n1050), .B(n1049), .Y(n1052) );
NAND2X1TS U1770 ( .A(n359), .B(n1048), .Y(n1049) );
AOI21X1TS U1771 ( .A0(n1200), .A1(n1047), .B0(n1046), .Y(n1050) );
OAI21XLTS U1772 ( .A0(n1045), .A1(n1044), .B0(n1043), .Y(n1046) );
NAND2X1TS U1773 ( .A(n1039), .B(n1043), .Y(n1040) );
AOI21X1TS U1774 ( .A0(n1359), .A1(n1037), .B0(n1038), .Y(n1041) );
NAND2X1TS U1775 ( .A(Data_A_i[37]), .B(Data_A_i[10]), .Y(n1361) );
INVX2TS U1776 ( .A(n1142), .Y(n1151) );
INVX2TS U1777 ( .A(n1883), .Y(n1810) );
INVX2TS U1778 ( .A(n1160), .Y(n1508) );
INVX2TS U1779 ( .A(n1124), .Y(n1089) );
OAI21XLTS U1780 ( .A0(n1130), .A1(n1129), .B0(n1128), .Y(n1131) );
INVX2TS U1781 ( .A(n504), .Y(n505) );
NAND2X1TS U1782 ( .A(n503), .B(n3), .Y(n512) );
XNOR2X1TS U1783 ( .A(n1200), .B(n1199), .Y(n1207) );
XNOR2X1TS U1784 ( .A(n1198), .B(n1197), .Y(n1206) );
NAND2X1TS U1785 ( .A(n1196), .B(n1195), .Y(n1197) );
NAND2X1TS U1786 ( .A(n229), .B(n53), .Y(n495) );
INVX2TS U1787 ( .A(n444), .Y(n437) );
NAND2X1TS U1788 ( .A(n439), .B(n233), .Y(n454) );
NOR2XLTS U1789 ( .A(n4157), .B(n4192), .Y(n617) );
CLKAND2X2TS U1790 ( .A(n4446), .B(n59), .Y(n4447) );
CLKAND2X2TS U1791 ( .A(n4490), .B(n54), .Y(n4450) );
CLKAND2X2TS U1792 ( .A(n4490), .B(n4944), .Y(n4457) );
CLKAND2X2TS U1793 ( .A(n4490), .B(n51), .Y(n4464) );
OAI21XLTS U1794 ( .A0(n4860), .A1(n4648), .B0(n4467), .Y(n4468) );
OAI21XLTS U1795 ( .A0(n4936), .A1(n4648), .B0(n4475), .Y(n4476) );
CLKAND2X2TS U1796 ( .A(n4490), .B(Data_B_i[29]), .Y(n4471) );
OAI21XLTS U1797 ( .A0(n342), .A1(n4597), .B0(n4485), .Y(n4486) );
CLKAND2X2TS U1798 ( .A(n4490), .B(n4548), .Y(n4480) );
OAI21XLTS U1799 ( .A0(n4876), .A1(n4597), .B0(n4493), .Y(n4494) );
OAI21XLTS U1800 ( .A0(n4860), .A1(n4704), .B0(n4495), .Y(n4496) );
OAI21XLTS U1801 ( .A0(n23), .A1(n4704), .B0(n4695), .Y(n4696) );
OAI21XLTS U1802 ( .A0(n342), .A1(n4648), .B0(n4645), .Y(n4646) );
NOR2XLTS U1803 ( .A(n4125), .B(n4126), .Y(n4152) );
INVX2TS U1804 ( .A(n4179), .Y(n4142) );
INVX2TS U1805 ( .A(n4420), .Y(n4095) );
OAI21XLTS U1806 ( .A0(n322), .A1(n3263), .B0(n3251), .Y(n3252) );
OAI21XLTS U1807 ( .A0(n3715), .A1(n3329), .B0(n3316), .Y(n3317) );
OAI21XLTS U1808 ( .A0(n352), .A1(n3263), .B0(n3257), .Y(n3258) );
OAI21XLTS U1809 ( .A0(n321), .A1(n3263), .B0(n3260), .Y(n3261) );
OAI21XLTS U1810 ( .A0(n3751), .A1(n3263), .B0(n3262), .Y(n3264) );
OAI21XLTS U1811 ( .A0(n3655), .A1(n3329), .B0(n3323), .Y(n3324) );
OAI21XLTS U1812 ( .A0(n3600), .A1(n3269), .B0(n3268), .Y(n3270) );
OAI21XLTS U1813 ( .A0(n3715), .A1(n3807), .B0(n3026), .Y(n3027) );
INVX2TS U1814 ( .A(n253), .Y(n254) );
CLKBUFX2TS U1815 ( .A(n3375), .Y(n3789) );
INVX2TS U1816 ( .A(Data_B_i[14]), .Y(n137) );
INVX2TS U1817 ( .A(n3237), .Y(n3238) );
INVX2TS U1818 ( .A(n2980), .Y(n3239) );
INVX2TS U1819 ( .A(n3236), .Y(n2979) );
NOR2XLTS U1820 ( .A(n861), .B(n863), .Y(n881) );
AOI21X1TS U1821 ( .A0(n351), .A1(n848), .B0(n847), .Y(n860) );
NAND2X1TS U1822 ( .A(n393), .B(n473), .Y(n479) );
NAND2X1TS U1823 ( .A(n409), .B(n365), .Y(n414) );
AOI21X1TS U1824 ( .A0(n412), .A1(n365), .B0(n411), .Y(n413) );
NAND2X1TS U1825 ( .A(n485), .B(n484), .Y(n486) );
AOI21X1TS U1826 ( .A0(n526), .A1(n595), .B0(n525), .Y(n527) );
CLKAND2X2TS U1827 ( .A(n2115), .B(n344), .Y(n1593) );
AOI21X1TS U1828 ( .A0(n1200), .A1(n599), .B0(n598), .Y(n604) );
NAND2X1TS U1829 ( .A(n581), .B(n580), .Y(n582) );
AOI21X1TS U1830 ( .A0(n1200), .A1(n578), .B0(n577), .Y(n583) );
INVX2TS U1831 ( .A(n579), .Y(n581) );
AOI21X1TS U1832 ( .A0(n1582), .A1(n32), .B0(n1522), .Y(n1523) );
INVX2TS U1833 ( .A(n1586), .Y(n1522) );
CLKAND2X2TS U1834 ( .A(n2488), .B(n2679), .Y(n2161) );
NOR2X2TS U1835 ( .A(n274), .B(n178), .Y(n1188) );
AOI21X1TS U1836 ( .A0(n1220), .A1(n1184), .B0(n1186), .Y(n1176) );
NAND2X1TS U1837 ( .A(n1216), .B(n1184), .Y(n1177) );
NAND2X1TS U1838 ( .A(n274), .B(n178), .Y(n1187) );
OAI21XLTS U1839 ( .A0(n19), .A1(n302), .B0(n2109), .Y(n2110) );
OAI21XLTS U1840 ( .A0(n2595), .A1(n2664), .B0(n2349), .Y(n2350) );
CLKBUFX2TS U1841 ( .A(n1820), .Y(n2781) );
OAI21XLTS U1842 ( .A0(n2595), .A1(n2742), .B0(n2501), .Y(n2502) );
AOI222XLTS U1843 ( .A0(n293), .A1(n2528), .B0(n2738), .B1(n2556), .C0(n305),
.C1(n2776), .Y(n2501) );
OAI21XLTS U1844 ( .A0(n2752), .A1(n2742), .B0(n2220), .Y(n2221) );
AOI222XLTS U1845 ( .A0(n2740), .A1(n2556), .B0(n2738), .B1(n2747), .C0(n305),
.C1(n2746), .Y(n2220) );
INVX2TS U1846 ( .A(n1542), .Y(n1539) );
NOR2X1TS U1847 ( .A(n254), .B(n201), .Y(n401) );
NOR2XLTS U1848 ( .A(n479), .B(n483), .Y(n395) );
NAND2X1TS U1849 ( .A(n1037), .B(n389), .Y(n391) );
AOI21X1TS U1850 ( .A0(n1038), .A1(n389), .B0(n388), .Y(n390) );
OAI21XLTS U1851 ( .A0(n327), .A1(n2751), .B0(n2672), .Y(n2673) );
NAND2X1TS U1852 ( .A(n170), .B(n117), .Y(n1586) );
INVX2TS U1853 ( .A(n1582), .Y(n1583) );
NOR2X1TS U1854 ( .A(n154), .B(n101), .Y(n1542) );
NAND2X1TS U1855 ( .A(n154), .B(n101), .Y(n1541) );
NAND2X1TS U1856 ( .A(Data_B_i[20]), .B(n105), .Y(n1543) );
AOI21X1TS U1857 ( .A0(n1572), .A1(n1538), .B0(n1537), .Y(n1585) );
INVX2TS U1858 ( .A(n1569), .Y(n1537) );
NAND2X1TS U1859 ( .A(n166), .B(n113), .Y(n1578) );
NAND2X1TS U1860 ( .A(n162), .B(n109), .Y(n1575) );
INVX2TS U1861 ( .A(n1576), .Y(n1573) );
NOR2X2TS U1862 ( .A(n266), .B(n186), .Y(n1032) );
NAND2X1TS U1863 ( .A(n266), .B(n186), .Y(n1033) );
NAND2X2TS U1864 ( .A(n1509), .B(n30), .Y(n1529) );
NAND2X1TS U1865 ( .A(n262), .B(n190), .Y(n588) );
NOR2X1TS U1866 ( .A(n1042), .B(n584), .Y(n587) );
INVX2TS U1867 ( .A(n573), .Y(n589) );
OAI21X2TS U1868 ( .A0(n1027), .A1(n381), .B0(n380), .Y(n1038) );
OAI21XLTS U1869 ( .A0(n2362), .A1(n2732), .B0(n1760), .Y(n1761) );
XNOR2X1TS U1870 ( .A(n1215), .B(n1214), .Y(n1229) );
NAND2X1TS U1871 ( .A(n1219), .B(n1217), .Y(n1214) );
OAI21XLTS U1872 ( .A0(n1223), .A1(n1212), .B0(n1211), .Y(n1215) );
XNOR2X1TS U1873 ( .A(n1228), .B(n1227), .Y(n1230) );
NAND2X1TS U1874 ( .A(n1226), .B(n1225), .Y(n1227) );
OAI21XLTS U1875 ( .A0(n1223), .A1(n1222), .B0(n1221), .Y(n1228) );
NAND2X1TS U1876 ( .A(n138), .B(Data_B_i[41]), .Y(n1149) );
AOI21X1TS U1877 ( .A0(n1143), .A1(n1091), .B0(n1151), .Y(n1144) );
INVX2TS U1878 ( .A(n1154), .Y(n1143) );
AOI21X2TS U1879 ( .A0(n564), .A1(n377), .B0(n376), .Y(n522) );
NOR2X1TS U1880 ( .A(n1212), .B(n375), .Y(n377) );
NAND2X1TS U1881 ( .A(n373), .B(n1184), .Y(n375) );
INVX2TS U1882 ( .A(n1123), .Y(n1120) );
NAND2X1TS U1883 ( .A(n209), .B(n69), .Y(n1117) );
INVX2TS U1884 ( .A(n1109), .Y(n1127) );
AOI21X1TS U1885 ( .A0(n1112), .A1(n17), .B0(n1111), .Y(n1113) );
OAI21XLTS U1886 ( .A0(n20), .A1(n2705), .B0(n2704), .Y(n2707) );
NAND2X1TS U1887 ( .A(n146), .B(n93), .Y(n1506) );
AOI21X1TS U1888 ( .A0(n1515), .A1(n30), .B0(n1508), .Y(n1161) );
INVX2TS U1889 ( .A(n1504), .Y(n1527) );
NOR2X1TS U1890 ( .A(n205), .B(n73), .Y(n1123) );
INVX2TS U1891 ( .A(n1889), .Y(n1892) );
NOR2XLTS U1892 ( .A(n2070), .B(n1916), .Y(n1771) );
INVX2TS U1893 ( .A(n515), .Y(n507) );
INVX2TS U1894 ( .A(n512), .Y(n508) );
NAND2X1TS U1895 ( .A(n221), .B(n61), .Y(n513) );
INVX2TS U1896 ( .A(n1129), .Y(n1108) );
NAND2X1TS U1897 ( .A(n225), .B(n57), .Y(n504) );
INVX2TS U1898 ( .A(n495), .Y(n506) );
INVX2TS U1899 ( .A(n460), .Y(n503) );
NOR2XLTS U1900 ( .A(n1006), .B(n1018), .Y(n452) );
NOR2XLTS U1901 ( .A(n1078), .B(n1023), .Y(n1006) );
CLKAND2X2TS U1902 ( .A(n4490), .B(n86), .Y(n4148) );
OAI21XLTS U1903 ( .A0(n4887), .A1(n4706), .B0(n4708), .Y(n4707) );
CLKAND2X2TS U1904 ( .A(n4446), .B(n78), .Y(n4102) );
INVX2TS U1905 ( .A(n4204), .Y(n4027) );
OAI21XLTS U1906 ( .A0(n333), .A1(n4706), .B0(n4716), .Y(n4717) );
OAI21XLTS U1907 ( .A0(n4963), .A1(n4668), .B0(n4667), .Y(n4669) );
OAI21XLTS U1908 ( .A0(n320), .A1(n4518), .B0(n4670), .Y(n4671) );
AO21XLTS U1909 ( .A0(n4809), .A1(n630), .B0(n4799), .Y(n4768) );
OAI21XLTS U1910 ( .A0(n326), .A1(n4597), .B0(n4583), .Y(n4584) );
OAI21XLTS U1911 ( .A0(n4954), .A1(n4780), .B0(n4771), .Y(n4772) );
OAI21XLTS U1912 ( .A0(n323), .A1(n4654), .B0(n4627), .Y(n4628) );
OAI21XLTS U1913 ( .A0(n24), .A1(n4518), .B0(n4676), .Y(n4677) );
OAI21XLTS U1914 ( .A0(n4963), .A1(n4706), .B0(n4722), .Y(n4723) );
OAI21XLTS U1915 ( .A0(n328), .A1(n4597), .B0(n4588), .Y(n4589) );
XOR2XLTS U1916 ( .A(n4774), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1230) );
OAI21XLTS U1917 ( .A0(n333), .A1(n4780), .B0(n4773), .Y(n4774) );
OAI21XLTS U1918 ( .A0(n4917), .A1(n4518), .B0(n4678), .Y(n4679) );
OAI21XLTS U1919 ( .A0(n4900), .A1(n4780), .B0(n4775), .Y(n4776) );
OAI21XLTS U1920 ( .A0(n4860), .A1(n4597), .B0(n4591), .Y(n4592) );
OAI21XLTS U1921 ( .A0(n18), .A1(n4648), .B0(n4634), .Y(n4635) );
OAI21XLTS U1922 ( .A0(n4887), .A1(n4905), .B0(n4889), .Y(n4888) );
OAI21XLTS U1923 ( .A0(n333), .A1(n4818), .B0(n4828), .Y(n4829) );
OAI21XLTS U1924 ( .A0(n24), .A1(n4766), .B0(n4730), .Y(n4731) );
OAI21XLTS U1925 ( .A0(n328), .A1(n4648), .B0(n4637), .Y(n4638) );
OAI21XLTS U1926 ( .A0(n4963), .A1(n4780), .B0(n4779), .Y(n4781) );
OAI21XLTS U1927 ( .A0(n4951), .A1(n4905), .B0(n4890), .Y(n4891) );
OAI21XLTS U1928 ( .A0(n4887), .A1(n4980), .B0(n4224), .Y(n4225) );
OAI21XLTS U1929 ( .A0(n4954), .A1(n4905), .B0(n4895), .Y(n4896) );
OAI21XLTS U1930 ( .A0(n4917), .A1(n4538), .B0(n4790), .Y(n4791) );
OAI21XLTS U1931 ( .A0(n4900), .A1(n4905), .B0(n4899), .Y(n4901) );
OAI21XLTS U1932 ( .A0(n4942), .A1(n4648), .B0(n4640), .Y(n4641) );
OAI21XLTS U1933 ( .A0(n320), .A1(n4883), .B0(n4836), .Y(n4837) );
OAI21XLTS U1934 ( .A0(n4963), .A1(n4905), .B0(n4904), .Y(n4906) );
OAI21XLTS U1935 ( .A0(n328), .A1(n4759), .B0(n4743), .Y(n4744) );
OAI21XLTS U1936 ( .A0(n320), .A1(n4922), .B0(n4907), .Y(n4908) );
OAI21XLTS U1937 ( .A0(n4900), .A1(n4958), .B0(n4228), .Y(n4229) );
OAI21XLTS U1938 ( .A0(n4917), .A1(n4883), .B0(n4844), .Y(n4845) );
OAI21XLTS U1939 ( .A0(n323), .A1(n4883), .B0(n4846), .Y(n4847) );
OAI21XLTS U1940 ( .A0(n4936), .A1(n4759), .B0(n4748), .Y(n4749) );
INVX2TS U1941 ( .A(n4067), .Y(n4174) );
INVX2TS U1942 ( .A(n4173), .Y(n4068) );
OAI21XLTS U1943 ( .A0(n4963), .A1(n4980), .B0(n4962), .Y(n4964) );
OAI21XLTS U1944 ( .A0(n328), .A1(n4816), .B0(n4803), .Y(n4804) );
OAI21XLTS U1945 ( .A0(n23), .A1(n4816), .B0(n4807), .Y(n4808) );
OAI21XLTS U1946 ( .A0(n342), .A1(n4759), .B0(n4756), .Y(n4757) );
INVX2TS U1947 ( .A(n4157), .Y(n4190) );
INVX2TS U1948 ( .A(n4188), .Y(n4189) );
XOR2XLTS U1949 ( .A(n186), .B(Data_A_i[37]), .Y(n4236) );
INVX2TS U1950 ( .A(n4094), .Y(n4421) );
OAI21XLTS U1951 ( .A0(n21), .A1(n4883), .B0(n655), .Y(n656) );
INVX2TS U1952 ( .A(n686), .Y(n673) );
INVX2TS U1953 ( .A(n672), .Y(n687) );
INVX2TS U1954 ( .A(n3183), .Y(n3169) );
OAI21XLTS U1955 ( .A0(n26), .A1(n3402), .B0(n3387), .Y(n3388) );
CLKAND2X2TS U1956 ( .A(n3418), .B(n43), .Y(n3386) );
OAI21XLTS U1957 ( .A0(n336), .A1(n3291), .B0(n3287), .Y(n3288) );
OAI21XLTS U1958 ( .A0(n3689), .A1(n3305), .B0(n3293), .Y(n3294) );
OAI21XLTS U1959 ( .A0(n325), .A1(n3345), .B0(n3339), .Y(n3340) );
OAI21XLTS U1960 ( .A0(n324), .A1(n3269), .B0(n3200), .Y(n3201) );
OAI21XLTS U1961 ( .A0(n26), .A1(n3454), .B0(n3439), .Y(n3440) );
CLKAND2X2TS U1962 ( .A(n3726), .B(n1431), .Y(n3438) );
OAI21XLTS U1963 ( .A0(n3756), .A1(n3263), .B0(n3225), .Y(n3226) );
OAI21XLTS U1964 ( .A0(n324), .A1(n3305), .B0(n3299), .Y(n3300) );
XOR2XLTS U1965 ( .A(n3491), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1374) );
CLKAND2X2TS U1966 ( .A(n37), .B(n206), .Y(genblk1_right_mult_x_1_n924) );
XOR2XLTS U1967 ( .A(n3346), .B(n279), .Y(genblk1_right_mult_x_1_n1292) );
OAI21XLTS U1968 ( .A0(n362), .A1(n3454), .B0(n3441), .Y(n3442) );
OAI21XLTS U1969 ( .A0(n3695), .A1(n3305), .B0(n3297), .Y(n3298) );
OAI21XLTS U1970 ( .A0(n3673), .A1(n3454), .B0(n3443), .Y(n3444) );
OAI21XLTS U1971 ( .A0(n325), .A1(n3402), .B0(n3397), .Y(n3398) );
OAI21XLTS U1972 ( .A0(n26), .A1(n3508), .B0(n3493), .Y(n3494) );
CLKAND2X2TS U1973 ( .A(n3525), .B(n42), .Y(n3492) );
OAI21XLTS U1974 ( .A0(n3676), .A1(n3454), .B0(n3445), .Y(n3446) );
OAI21XLTS U1975 ( .A0(n340), .A1(n3454), .B0(n3447), .Y(n3448) );
OAI21XLTS U1976 ( .A0(n325), .A1(n3454), .B0(n3449), .Y(n3450) );
CLKAND2X2TS U1977 ( .A(n36), .B(n222), .Y(n2987) );
XOR2XLTS U1978 ( .A(n2985), .B(n288), .Y(n2986) );
OAI21XLTS U1979 ( .A0(n3715), .A1(n3263), .B0(n2984), .Y(n2985) );
OAI21XLTS U1980 ( .A0(n336), .A1(n3454), .B0(n3451), .Y(n3452) );
XOR2XLTS U1981 ( .A(n2996), .B(Data_A_i[26]), .Y(n2997) );
OAI21XLTS U1982 ( .A0(n3686), .A1(n3454), .B0(n3453), .Y(n3455) );
OAI21XLTS U1983 ( .A0(n337), .A1(n3329), .B0(n3314), .Y(n3315) );
XOR2XLTS U1984 ( .A(n3551), .B(n271), .Y(genblk1_right_mult_x_1_n1406) );
OAI21XLTS U1985 ( .A0(n362), .A1(n3563), .B0(n3550), .Y(n3551) );
OAI21XLTS U1986 ( .A0(n325), .A1(n3508), .B0(n3503), .Y(n3504) );
OAI21XLTS U1987 ( .A0(n336), .A1(n3508), .B0(n3505), .Y(n3506) );
OAI21XLTS U1988 ( .A0(n3686), .A1(n3508), .B0(n3507), .Y(n3509) );
OAI21XLTS U1989 ( .A0(n337), .A1(n3379), .B0(n3363), .Y(n3364) );
OAI21XLTS U1990 ( .A0(n340), .A1(n3563), .B0(n3556), .Y(n3557) );
OAI21XLTS U1991 ( .A0(n336), .A1(n3563), .B0(n3560), .Y(n3561) );
XOR2XLTS U1992 ( .A(n3015), .B(n256), .Y(n3016) );
XOR2XLTS U1993 ( .A(n3010), .B(n281), .Y(n3017) );
OAI21XLTS U1994 ( .A0(n321), .A1(n3329), .B0(n3014), .Y(n3015) );
OAI21XLTS U1995 ( .A0(n325), .A1(n3621), .B0(n3616), .Y(n3617) );
OAI21XLTS U1996 ( .A0(n3689), .A1(n3599), .B0(n3566), .Y(n3567) );
OAI21XLTS U1997 ( .A0(n3756), .A1(n3801), .B0(n3470), .Y(n3471) );
OAI21XLTS U1998 ( .A0(n3673), .A1(n3685), .B0(n3672), .Y(n3674) );
OAI21XLTS U1999 ( .A0(n3655), .A1(n3379), .B0(n3370), .Y(n3371) );
INVX2TS U2000 ( .A(n3161), .Y(n3148) );
OAI21XLTS U2001 ( .A0(n3676), .A1(n3685), .B0(n3675), .Y(n3677) );
XOR2XLTS U2002 ( .A(n3033), .B(n256), .Y(n3041) );
OAI21XLTS U2003 ( .A0(n322), .A1(n3807), .B0(n3428), .Y(n3429) );
OAI21XLTS U2004 ( .A0(n321), .A1(n3379), .B0(n3376), .Y(n3377) );
OAI21XLTS U2005 ( .A0(n3695), .A1(n3599), .B0(n3570), .Y(n3571) );
OAI21XLTS U2006 ( .A0(n337), .A1(n3801), .B0(n3474), .Y(n3475) );
OAI21XLTS U2007 ( .A0(n324), .A1(n3599), .B0(n3572), .Y(n3573) );
OAI21XLTS U2008 ( .A0(n3655), .A1(n3807), .B0(n3431), .Y(n3432) );
OAI21XLTS U2009 ( .A0(n325), .A1(n3685), .B0(n3680), .Y(n3681) );
OAI21XLTS U2010 ( .A0(n354), .A1(n3781), .B0(n3529), .Y(n3530) );
XOR2XLTS U2011 ( .A(n3683), .B(n284), .Y(genblk1_right_mult_x_1_n1471) );
OAI21XLTS U2012 ( .A0(n3715), .A1(n3781), .B0(n3533), .Y(n3534) );
OAI21XLTS U2013 ( .A0(n3689), .A1(n3707), .B0(n3688), .Y(n3690) );
OAI21XLTS U2014 ( .A0(n3655), .A1(n3801), .B0(n3480), .Y(n3481) );
OAI21XLTS U2015 ( .A0(n352), .A1(n3801), .B0(n3482), .Y(n3483) );
OAI21XLTS U2016 ( .A0(n3719), .A1(n3781), .B0(n3535), .Y(n3536) );
XOR2XLTS U2017 ( .A(n3581), .B(n271), .Y(genblk1_right_mult_x_1_n1420) );
OAI21XLTS U2018 ( .A0(n354), .A1(n3775), .B0(n3580), .Y(n3581) );
OAI21XLTS U2019 ( .A0(n3756), .A1(n3661), .B0(n3640), .Y(n3641) );
OAI21XLTS U2020 ( .A0(n3715), .A1(n3775), .B0(n3584), .Y(n3585) );
OAI21XLTS U2021 ( .A0(n3751), .A1(n3801), .B0(n3486), .Y(n3487) );
INVX2TS U2022 ( .A(n875), .Y(n862) );
INVX2TS U2023 ( .A(n861), .Y(n876) );
NOR2X1TS U2024 ( .A(n479), .B(n414), .Y(n1094) );
OAI21XLTS U2025 ( .A0(n2285), .A1(n2362), .B0(n2211), .Y(n2212) );
INVX2TS U2026 ( .A(n1834), .Y(n1835) );
OAI21XLTS U2027 ( .A0(n2410), .A1(n2393), .B0(n2392), .Y(n2395) );
OAI21XLTS U2028 ( .A0(n2495), .A1(n302), .B0(n1818), .Y(n1819) );
OAI21XLTS U2029 ( .A0(n2486), .A1(n2393), .B0(n1853), .Y(n1854) );
OAI21XLTS U2030 ( .A0(n2403), .A1(n2362), .B0(n2218), .Y(n2219) );
OAI21XLTS U2031 ( .A0(n2516), .A1(n2393), .B0(n1866), .Y(n1867) );
INVX2TS U2032 ( .A(n2117), .Y(n2118) );
CLKAND2X2TS U2033 ( .A(n2503), .B(n2315), .Y(n2316) );
OAI21XLTS U2034 ( .A0(n2357), .A1(n2524), .B0(n2356), .Y(n2358) );
OAI21XLTS U2035 ( .A0(n2525), .A1(n2393), .B0(n1879), .Y(n1880) );
CLKAND2X2TS U2036 ( .A(n2573), .B(n25), .Y(genblk1_middle_mult_x_1_n1015) );
XOR2XLTS U2037 ( .A(n2332), .B(n2394), .Y(genblk1_middle_mult_x_1_n1346) );
XOR2XLTS U2038 ( .A(n2188), .B(n2766), .Y(genblk1_middle_mult_x_1_n1318) );
AOI222XLTS U2039 ( .A0(n2695), .A1(n2315), .B0(n2503), .B1(n2223), .C0(n2479), .C1(n2792), .Y(n2103) );
OAI21XLTS U2040 ( .A0(n2486), .A1(n2684), .B0(n2417), .Y(n2418) );
OAI21XLTS U2041 ( .A0(n2403), .A1(n2713), .B0(n2372), .Y(n2373) );
OAI21XLTS U2042 ( .A0(n2535), .A1(n2765), .B0(n2202), .Y(n2203) );
CLKAND2X2TS U2043 ( .A(n2579), .B(n25), .Y(genblk1_middle_mult_x_1_n1016) );
OAI21XLTS U2044 ( .A0(n2460), .A1(n2491), .B0(n2320), .Y(n2321) );
OAI21XLTS U2045 ( .A0(n2389), .A1(n2713), .B0(n2231), .Y(n2232) );
AOI222XLTS U2046 ( .A0(n2692), .A1(n2387), .B0(n1964), .B1(n2397), .C0(n2708), .C1(n2451), .Y(n2231) );
OAI21XLTS U2047 ( .A0(n2410), .A1(n2524), .B0(n1951), .Y(n1952) );
CLKAND2X2TS U2048 ( .A(n2443), .B(n2315), .Y(n2195) );
OAI21XLTS U2049 ( .A0(n2495), .A1(n2684), .B0(n2423), .Y(n2425) );
AOI222XLTS U2050 ( .A0(n2740), .A1(n2521), .B0(n2738), .B1(n2509), .C0(n2736), .C1(n2422), .Y(n2423) );
OAI21XLTS U2051 ( .A0(n2403), .A1(n2491), .B0(n2402), .Y(n2404) );
OAI21XLTS U2052 ( .A0(n2460), .A1(n2811), .B0(n2132), .Y(n2133) );
AOI222XLTS U2053 ( .A0(n2498), .A1(n2376), .B0(n2503), .B1(n1950), .C0(n2701), .C1(n2451), .Y(n2377) );
OAI21XLTS U2054 ( .A0(n2535), .A1(n2648), .B0(n1905), .Y(n1906) );
OAI21XLTS U2055 ( .A0(n2410), .A1(n2506), .B0(n2398), .Y(n2399) );
CLKAND2X2TS U2056 ( .A(n2427), .B(n2315), .Y(n2191) );
OAI21XLTS U2057 ( .A0(n2357), .A1(n2811), .B0(n1990), .Y(n1991) );
AOI222XLTS U2058 ( .A0(n2462), .A1(n2796), .B0(n2427), .B1(n2457), .C0(n2426), .C1(n2222), .Y(n2189) );
OAI21XLTS U2059 ( .A0(n2460), .A1(n2328), .B0(n2128), .Y(n2129) );
CLKAND2X2TS U2060 ( .A(n2796), .B(n2769), .Y(n2770) );
AOI222XLTS U2061 ( .A0(n1258), .A1(n2796), .B0(n2795), .B1(n2794), .C0(n2793), .C1(n2792), .Y(n2797) );
OAI21XLTS U2062 ( .A0(n2495), .A1(n2506), .B0(n1981), .Y(n1982) );
OAI21XLTS U2063 ( .A0(n2437), .A1(n2751), .B0(n2436), .Y(n2438) );
OAI21XLTS U2064 ( .A0(n2486), .A1(n2445), .B0(n2444), .Y(n2447) );
OAI21XLTS U2065 ( .A0(n2460), .A1(n2768), .B0(n2130), .Y(n2131) );
OAI21XLTS U2066 ( .A0(n2318), .A1(n2515), .B0(n2106), .Y(n2107) );
CLKAND2X2TS U2067 ( .A(n2315), .B(n2351), .Y(n2105) );
OAI21XLTS U2068 ( .A0(n2285), .A1(n2515), .B0(n2284), .Y(n2286) );
OAI21XLTS U2069 ( .A0(n2495), .A1(n2445), .B0(n2002), .Y(n2003) );
OAI21XLTS U2070 ( .A0(n2357), .A1(n2515), .B0(n2083), .Y(n2084) );
OAI21XLTS U2071 ( .A0(n2410), .A1(n2409), .B0(n2408), .Y(n2412) );
OAI21XLTS U2072 ( .A0(n2525), .A1(n2464), .B0(n2031), .Y(n2032) );
OAI21XLTS U2073 ( .A0(n2665), .A1(n2705), .B0(n2413), .Y(n2414) );
OAI21XLTS U2074 ( .A0(n2535), .A1(n2811), .B0(n2011), .Y(n2012) );
INVX2TS U2075 ( .A(n1833), .Y(n1797) );
OAI21XLTS U2076 ( .A0(n2595), .A1(n2705), .B0(n1986), .Y(n1987) );
OAI21XLTS U2077 ( .A0(n2525), .A1(n2409), .B0(n2055), .Y(n2056) );
OAI21XLTS U2078 ( .A0(n19), .A1(n2751), .B0(n2420), .Y(n2421) );
OAI21XLTS U2079 ( .A0(n2362), .A1(n2764), .B0(n1941), .Y(n1942) );
OAI21XLTS U2080 ( .A0(n2665), .A1(n2566), .B0(n2473), .Y(n2474) );
NAND2X1TS U2081 ( .A(n371), .B(n283), .Y(n1211) );
INVX2TS U2082 ( .A(n1212), .Y(n1216) );
OAI21XLTS U2083 ( .A0(n2437), .A1(n2464), .B0(n2037), .Y(n2038) );
NAND2X1TS U2084 ( .A(n1034), .B(n1033), .Y(n1035) );
AOI21X1TS U2085 ( .A0(n1359), .A1(n1031), .B0(n1030), .Y(n1036) );
INVX2TS U2086 ( .A(n1032), .Y(n1034) );
NAND2X1TS U2087 ( .A(n150), .B(n97), .Y(n1551) );
INVX2TS U2088 ( .A(n1547), .Y(n1548) );
OAI21XLTS U2089 ( .A0(n2535), .A1(n2328), .B0(n2039), .Y(n2040) );
OAI21XLTS U2090 ( .A0(n2595), .A1(n2566), .B0(n2013), .Y(n2014) );
OAI21XLTS U2091 ( .A0(n2525), .A1(n2515), .B0(n2512), .Y(n2513) );
AOI222XLTS U2092 ( .A0(n2511), .A1(n2592), .B0(n2510), .B1(n2541), .C0(n2509), .C1(n2590), .Y(n2512) );
OAI21XLTS U2093 ( .A0(n2665), .A1(n2723), .B0(n2440), .Y(n2441) );
XOR2X1TS U2094 ( .A(n1057), .B(n2706), .Y(n1071) );
OAI21XLTS U2095 ( .A0(n19), .A1(n2705), .B0(n1056), .Y(n1057) );
INVX2TS U2096 ( .A(n1027), .Y(n1201) );
INVX2TS U2097 ( .A(n1026), .Y(n1202) );
NAND2X2TS U2098 ( .A(Data_A_i[8]), .B(n182), .Y(n1345) );
OAI21XLTS U2099 ( .A0(n327), .A1(n2566), .B0(n2015), .Y(n2016) );
OAI21XLTS U2100 ( .A0(n2535), .A1(n2768), .B0(n2534), .Y(n2536) );
OAI21XLTS U2101 ( .A0(n19), .A1(n2566), .B0(n2017), .Y(n2018) );
NOR2XLTS U2102 ( .A(n2070), .B(n1985), .Y(n1971) );
INVX2TS U2103 ( .A(n1967), .Y(n1968) );
OAI21XLTS U2104 ( .A0(n345), .A1(n2723), .B0(n1783), .Y(n1784) );
ADDHXLTS U2105 ( .A(n2552), .B(n1780), .CO(n2178), .S(n1787) );
XOR2XLTS U2106 ( .A(n1342), .B(n2706), .Y(n1780) );
AOI222XLTS U2107 ( .A0(n2721), .A1(n2737), .B0(n2720), .B1(n2719), .C0(n2718), .C1(n2790), .Y(n2722) );
OAI21XLTS U2108 ( .A0(n2811), .A1(n2732), .B0(n2731), .Y(n2733) );
AOI222XLTS U2109 ( .A0(n2462), .A1(n2359), .B0(n2720), .B1(n2709), .C0(n2718), .C1(n2806), .Y(n1239) );
OAI21XLTS U2110 ( .A0(n20), .A1(n2571), .B0(n1234), .Y(n1235) );
NOR2XLTS U2111 ( .A(n1286), .B(n1916), .Y(n1101) );
NAND2X1TS U2112 ( .A(n569), .B(n568), .Y(n571) );
INVX2TS U2113 ( .A(n3943), .Y(n643) );
INVX2TS U2114 ( .A(n642), .Y(n3944) );
CLKAND2X2TS U2115 ( .A(n4446), .B(n123), .Y(n4033) );
OAI21XLTS U2116 ( .A0(n367), .A1(n4599), .B0(n4605), .Y(n4606) );
AO21XLTS U2117 ( .A0(n4639), .A1(Data_B_i[51]), .B0(n4633), .Y(n4604) );
XOR2XLTS U2118 ( .A(n4294), .B(n196), .Y(n4295) );
OAI21XLTS U2119 ( .A0(n4887), .A1(n4668), .B0(n4293), .Y(n4294) );
OAI21XLTS U2120 ( .A0(n367), .A1(n4668), .B0(n4657), .Y(n4658) );
AO21XLTS U2121 ( .A0(n4697), .A1(n630), .B0(n4687), .Y(n4656) );
XOR2XLTS U2122 ( .A(n4612), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1144) );
XOR2XLTS U2123 ( .A(n4710), .B(n191), .Y(genblk1_left_mult_x_1_n1198) );
XOR2XLTS U2124 ( .A(n4662), .B(n195), .Y(genblk1_left_mult_x_1_n1172) );
XOR2XLTS U2125 ( .A(n4616), .B(n198), .Y(genblk1_left_mult_x_1_n1146) );
OAI21XLTS U2126 ( .A0(n367), .A1(n4706), .B0(n4712), .Y(n4713) );
AO21XLTS U2127 ( .A0(n4750), .A1(Data_B_i[51]), .B0(n4740), .Y(n4711) );
XOR2XLTS U2128 ( .A(n4434), .B(Data_A_i[38]), .Y(n4435) );
OAI21XLTS U2129 ( .A0(n4887), .A1(n4780), .B0(n4439), .Y(n4434) );
XOR2XLTS U2130 ( .A(n4581), .B(n203), .Y(genblk1_left_mult_x_1_n1123) );
XOR2XLTS U2131 ( .A(n4715), .B(n191), .Y(genblk1_left_mult_x_1_n1200) );
XOR2XLTS U2132 ( .A(n4621), .B(n199), .Y(genblk1_left_mult_x_1_n1148) );
XOR2XLTS U2133 ( .A(n4719), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1202) );
OAI21XLTS U2134 ( .A0(n4860), .A1(n4466), .B0(n4160), .Y(
genblk1_left_mult_x_1_n1101) );
XOR2XLTS U2135 ( .A(n4626), .B(n199), .Y(genblk1_left_mult_x_1_n1150) );
CMPR42X1TS U2136 ( .A(genblk1_left_mult_x_1_n573), .B(
genblk1_left_mult_x_1_n1175), .C(genblk1_left_mult_x_1_n1149), .D(
genblk1_left_mult_x_1_n1201), .ICI(genblk1_left_mult_x_1_n570), .S(
genblk1_left_mult_x_1_n562), .ICO(genblk1_left_mult_x_1_n560), .CO(
genblk1_left_mult_x_1_n561) );
XOR2XLTS U2137 ( .A(n4669), .B(n194), .Y(genblk1_left_mult_x_1_n1175) );
XOR2XLTS U2138 ( .A(n4717), .B(n191), .Y(genblk1_left_mult_x_1_n1201) );
XOR2XLTS U2139 ( .A(n4624), .B(n199), .Y(genblk1_left_mult_x_1_n1149) );
OAI21XLTS U2140 ( .A0(n328), .A1(n4466), .B0(n4438), .Y(n4445) );
XOR2XLTS U2141 ( .A(n4441), .B(n187), .Y(n4444) );
XOR2XLTS U2142 ( .A(n4819), .B(n183), .Y(genblk1_left_mult_x_1_n1255) );
OAI21XLTS U2143 ( .A0(n4936), .A1(n4466), .B0(n4132), .Y(
genblk1_left_mult_x_1_n1102) );
XOR2XLTS U2144 ( .A(n4587), .B(n203), .Y(genblk1_left_mult_x_1_n1125) );
CMPR42X1TS U2145 ( .A(genblk1_left_mult_x_1_n1177), .B(
genblk1_left_mult_x_1_n1229), .C(genblk1_left_mult_x_1_n1151), .D(
genblk1_left_mult_x_1_n1203), .ICI(genblk1_left_mult_x_1_n590), .S(
genblk1_left_mult_x_1_n581), .ICO(genblk1_left_mult_x_1_n579), .CO(
genblk1_left_mult_x_1_n580) );
XOR2XLTS U2146 ( .A(n4628), .B(n198), .Y(genblk1_left_mult_x_1_n1151) );
XOR2XLTS U2147 ( .A(n4772), .B(n187), .Y(genblk1_left_mult_x_1_n1229) );
XOR2XLTS U2148 ( .A(n4674), .B(n196), .Y(genblk1_left_mult_x_1_n1177) );
XOR2XLTS U2149 ( .A(n4632), .B(n199), .Y(genblk1_left_mult_x_1_n1153) );
XOR2XLTS U2150 ( .A(n4725), .B(n191), .Y(genblk1_left_mult_x_1_n1205) );
XOR2XLTS U2151 ( .A(n4825), .B(n184), .Y(genblk1_left_mult_x_1_n1257) );
CMPR42X1TS U2152 ( .A(genblk1_left_mult_x_1_n1154), .B(
genblk1_left_mult_x_1_n1284), .C(genblk1_left_mult_x_1_n628), .D(
genblk1_left_mult_x_1_n1206), .ICI(genblk1_left_mult_x_1_n622), .S(
genblk1_left_mult_x_1_n616), .ICO(genblk1_left_mult_x_1_n614), .CO(
genblk1_left_mult_x_1_n615) );
XOR2XLTS U2153 ( .A(n4728), .B(n192), .Y(genblk1_left_mult_x_1_n1206) );
XOR2XLTS U2154 ( .A(n4888), .B(Data_A_i[32]), .Y(genblk1_left_mult_x_1_n1284) );
XOR2XLTS U2155 ( .A(n4635), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1154) );
XOR2XLTS U2156 ( .A(n4681), .B(n194), .Y(genblk1_left_mult_x_1_n1180) );
XOR2XLTS U2157 ( .A(n4827), .B(n183), .Y(genblk1_left_mult_x_1_n1258) );
XOR2XLTS U2158 ( .A(n4778), .B(n187), .Y(genblk1_left_mult_x_1_n1232) );
XOR2XLTS U2159 ( .A(n4894), .B(Data_A_i[32]), .Y(genblk1_left_mult_x_1_n1286) );
XOR2XLTS U2160 ( .A(n4783), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1234) );
OAI21XLTS U2161 ( .A0(n367), .A1(n4905), .B0(n4893), .Y(n4894) );
XOR2XLTS U2162 ( .A(n4598), .B(Data_A_i[50]), .Y(genblk1_left_mult_x_1_n1130) );
XOR2XLTS U2163 ( .A(n4686), .B(n194), .Y(genblk1_left_mult_x_1_n1182) );
XOR2XLTS U2164 ( .A(n4831), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1260) );
XOR2XLTS U2165 ( .A(n4898), .B(n178), .Y(genblk1_left_mult_x_1_n1288) );
XOR2XLTS U2166 ( .A(n4692), .B(n196), .Y(genblk1_left_mult_x_1_n1184) );
XOR2XLTS U2167 ( .A(n4789), .B(n188), .Y(genblk1_left_mult_x_1_n1236) );
XOR2XLTS U2168 ( .A(n4737), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1210) );
XOR2XLTS U2169 ( .A(n4952), .B(n4959), .Y(genblk1_left_mult_x_1_n1314) );
XOR2XLTS U2170 ( .A(n4835), .B(n184), .Y(genblk1_left_mult_x_1_n1262) );
OAI21XLTS U2171 ( .A0(n4356), .A1(n4353), .B0(n4357), .Y(n777) );
AO21XLTS U2172 ( .A0(n4977), .A1(n630), .B0(n4978), .Y(n4199) );
XOR2XLTS U2173 ( .A(n4644), .B(n199), .Y(genblk1_left_mult_x_1_n1160) );
XOR2XLTS U2174 ( .A(n4694), .B(n196), .Y(genblk1_left_mult_x_1_n1186) );
XOR2XLTS U2175 ( .A(n4742), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1212) );
XOR2XLTS U2176 ( .A(n4793), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1238) );
XOR2XLTS U2177 ( .A(n4956), .B(n4955), .Y(genblk1_left_mult_x_1_n1316) );
XOR2XLTS U2178 ( .A(n4840), .B(n184), .Y(genblk1_left_mult_x_1_n1264) );
XOR2XLTS U2179 ( .A(n4699), .B(n196), .Y(genblk1_left_mult_x_1_n1188) );
XOR2XLTS U2180 ( .A(n4798), .B(n186), .Y(genblk1_left_mult_x_1_n1240) );
XOR2XLTS U2181 ( .A(n4649), .B(n198), .Y(genblk1_left_mult_x_1_n1162) );
XOR2XLTS U2182 ( .A(n4705), .B(n195), .Y(genblk1_left_mult_x_1_n1189) );
XOR2XLTS U2183 ( .A(n4801), .B(n187), .Y(genblk1_left_mult_x_1_n1241) );
XOR2XLTS U2184 ( .A(n4655), .B(Data_A_i[47]), .Y(genblk1_left_mult_x_1_n1163) );
XOR2XLTS U2185 ( .A(n4271), .B(n194), .Y(n4272) );
XOR2XLTS U2186 ( .A(n4269), .B(n192), .Y(n4273) );
OAI21XLTS U2187 ( .A0(n342), .A1(n4704), .B0(n4270), .Y(n4271) );
XOR2XLTS U2188 ( .A(n4752), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1217) );
XOR2XLTS U2189 ( .A(n4216), .B(n371), .Y(genblk1_left_mult_x_1_n1321) );
XOR2XLTS U2190 ( .A(n4851), .B(n183), .Y(genblk1_left_mult_x_1_n1269) );
XOR2XLTS U2191 ( .A(n4254), .B(n187), .Y(n4255) );
XOR2XLTS U2192 ( .A(n4252), .B(n195), .Y(n4256) );
OAI21XLTS U2193 ( .A0(n4860), .A1(n4816), .B0(n4253), .Y(n4254) );
XOR2X1TS U2194 ( .A(n4207), .B(n4206), .Y(n4911) );
XOR2XLTS U2195 ( .A(n4920), .B(n180), .Y(genblk1_left_mult_x_1_n1296) );
XOR2XLTS U2196 ( .A(n4806), .B(n187), .Y(genblk1_left_mult_x_1_n1244) );
XOR2XLTS U2197 ( .A(n4755), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1218) );
OAI21XLTS U2198 ( .A0(n24), .A1(n4971), .B0(n4966), .Y(n4967) );
XOR2XLTS U2199 ( .A(n4927), .B(n179), .Y(genblk1_left_mult_x_1_n1298) );
XOR2XLTS U2200 ( .A(n4760), .B(n192), .Y(genblk1_left_mult_x_1_n1220) );
XOR2XLTS U2201 ( .A(n4861), .B(n183), .Y(genblk1_left_mult_x_1_n1272) );
XOR2XLTS U2202 ( .A(n4863), .B(n184), .Y(genblk1_left_mult_x_1_n1273) );
XOR2XLTS U2203 ( .A(n4817), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1247) );
XOR2XLTS U2204 ( .A(n4767), .B(n192), .Y(genblk1_left_mult_x_1_n1221) );
XOR2X1TS U2205 ( .A(n4182), .B(n4181), .Y(n4923) );
XOR2XLTS U2206 ( .A(n4288), .B(n188), .Y(n4289) );
XOR2XLTS U2207 ( .A(n4286), .B(n184), .Y(n4290) );
OAI21XLTS U2208 ( .A0(n328), .A1(n4886), .B0(n4932), .Y(n4933) );
XOR2XLTS U2209 ( .A(n4240), .B(n179), .Y(n4241) );
XOR2XLTS U2210 ( .A(n4238), .B(n187), .Y(n4242) );
OAI21XLTS U2211 ( .A0(n4860), .A1(n4905), .B0(n4239), .Y(n4240) );
OAI21XLTS U2212 ( .A0(n326), .A1(n4980), .B0(n4974), .Y(n4975) );
OAI21XLTS U2213 ( .A0(n18), .A1(n4980), .B0(n4979), .Y(n4982) );
OAI21XLTS U2214 ( .A0(n328), .A1(n4980), .B0(n4197), .Y(n4198) );
OAI21XLTS U2215 ( .A0(n23), .A1(n4886), .B0(n4938), .Y(n4939) );
OAI21XLTS U2216 ( .A0(n342), .A1(n4875), .B0(n4871), .Y(n4872) );
XOR2XLTS U2217 ( .A(n4547), .B(Data_A_i[38]), .Y(n4558) );
OAI21XLTS U2218 ( .A0(n21), .A1(n4780), .B0(n4546), .Y(n4547) );
OAI21XLTS U2219 ( .A0(n4884), .A1(n4883), .B0(n4882), .Y(n4885) );
OAI21XLTS U2220 ( .A0(n4936), .A1(n4980), .B0(n4186), .Y(n4187) );
OAI21XLTS U2221 ( .A0(n23), .A1(n4980), .B0(n669), .Y(n670) );
XOR2XLTS U2222 ( .A(n661), .B(n184), .Y(n684) );
OAI21XLTS U2223 ( .A0(n4876), .A1(n4905), .B0(n689), .Y(n690) );
INVX2TS U2224 ( .A(n724), .Y(n726) );
INVX2TS U2225 ( .A(n4541), .Y(n4539) );
INVX2TS U2226 ( .A(Data_A_i[27]), .Y(n666) );
AO21XLTS U2227 ( .A0(n3090), .A1(n1431), .B0(n1430), .Y(n1432) );
INVX2TS U2228 ( .A(n3095), .Y(n1430) );
INVX2TS U2229 ( .A(n3090), .Y(n1419) );
INVX2TS U2230 ( .A(n3091), .Y(n1412) );
INVX2TS U2231 ( .A(n3101), .Y(n3117) );
CLKAND2X2TS U2232 ( .A(n3744), .B(n43), .Y(n2948) );
INVX2TS U2233 ( .A(n3135), .Y(n3123) );
CLKAND2X2TS U2234 ( .A(n288), .B(n148), .Y(genblk1_right_mult_x_1_n919) );
XOR2XLTS U2235 ( .A(n3334), .B(n279), .Y(genblk1_right_mult_x_1_n1287) );
XOR2XLTS U2236 ( .A(n3385), .B(n259), .Y(genblk1_right_mult_x_1_n1314) );
XOR2XLTS U2237 ( .A(n3292), .B(n255), .Y(genblk1_right_mult_x_1_n1262) );
XOR2XLTS U2238 ( .A(n3338), .B(n279), .Y(genblk1_right_mult_x_1_n1289) );
XOR2XLTS U2239 ( .A(n3195), .B(n287), .Y(genblk1_right_mult_x_1_n1235) );
XOR2XLTS U2240 ( .A(n3400), .B(n260), .Y(genblk1_right_mult_x_1_n1321) );
XOR2XLTS U2241 ( .A(n3302), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1267) );
XOR2XLTS U2242 ( .A(n3235), .B(n287), .Y(genblk1_right_mult_x_1_n1240) );
XOR2XLTS U2243 ( .A(n3352), .B(n281), .Y(genblk1_right_mult_x_1_n1295) );
XOR2XLTS U2244 ( .A(n3250), .B(n289), .Y(genblk1_right_mult_x_1_n1241) );
XOR2XLTS U2245 ( .A(n3306), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1268) );
XOR2XLTS U2246 ( .A(n3498), .B(n267), .Y(genblk1_right_mult_x_1_n1377) );
XOR2XLTS U2247 ( .A(n3354), .B(n279), .Y(genblk1_right_mult_x_1_n1296) );
XOR2XLTS U2248 ( .A(n3310), .B(n256), .Y(genblk1_right_mult_x_1_n1269) );
XOR2XLTS U2249 ( .A(n3356), .B(n281), .Y(genblk1_right_mult_x_1_n1297) );
XOR2XLTS U2250 ( .A(n3313), .B(n256), .Y(genblk1_right_mult_x_1_n1270) );
XOR2XLTS U2251 ( .A(n3407), .B(n260), .Y(genblk1_right_mult_x_1_n1324) );
XOR2XLTS U2252 ( .A(n3409), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1325) );
OAI21XLTS U2253 ( .A0(n3695), .A1(n3416), .B0(n3408), .Y(n3409) );
XOR2XLTS U2254 ( .A(n3411), .B(n259), .Y(genblk1_right_mult_x_1_n1326) );
XOR2XLTS U2255 ( .A(n3553), .B(n270), .Y(genblk1_right_mult_x_1_n1407) );
XOR2XLTS U2256 ( .A(n3604), .B(n276), .Y(genblk1_right_mult_x_1_n1434) );
XOR2XLTS U2257 ( .A(n3607), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1435) );
XOR2XLTS U2258 ( .A(n3362), .B(n281), .Y(genblk1_right_mult_x_1_n1300) );
XOR2XLTS U2259 ( .A(n3460), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1354) );
XOR2XLTS U2260 ( .A(n3462), .B(n264), .Y(genblk1_right_mult_x_1_n1355) );
OAI21XLTS U2261 ( .A0(n3695), .A1(n3765), .B0(n3461), .Y(n3462) );
XOR2XLTS U2262 ( .A(n3464), .B(n264), .Y(genblk1_right_mult_x_1_n1356) );
XOR2XLTS U2263 ( .A(n3611), .B(n275), .Y(genblk1_right_mult_x_1_n1437) );
XOR2XLTS U2264 ( .A(n3559), .B(n270), .Y(genblk1_right_mult_x_1_n1410) );
XOR2XLTS U2265 ( .A(n3669), .B(n284), .Y(genblk1_right_mult_x_1_n1465) );
XOR2XLTS U2266 ( .A(n3423), .B(n260), .Y(genblk1_right_mult_x_1_n1330) );
XOR2XLTS U2267 ( .A(n3466), .B(n264), .Y(genblk1_right_mult_x_1_n1357) );
XOR2XLTS U2268 ( .A(n3425), .B(n259), .Y(genblk1_right_mult_x_1_n1331) );
XOR2XLTS U2269 ( .A(n3468), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1358) );
XOR2XLTS U2270 ( .A(n3671), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1466) );
CMPR42X1TS U2271 ( .A(genblk1_right_mult_x_1_n1439), .B(
genblk1_right_mult_x_1_n1412), .C(genblk1_right_mult_x_1_n751), .D(
genblk1_right_mult_x_1_n739), .ICI(genblk1_right_mult_x_1_n748), .S(
genblk1_right_mult_x_1_n734), .ICO(genblk1_right_mult_x_1_n732), .CO(
genblk1_right_mult_x_1_n733) );
XOR2XLTS U2272 ( .A(n3564), .B(n272), .Y(genblk1_right_mult_x_1_n1412) );
XOR2XLTS U2273 ( .A(n3615), .B(n276), .Y(genblk1_right_mult_x_1_n1439) );
OAI21XLTS U2274 ( .A0(n3686), .A1(n3563), .B0(n3562), .Y(n3564) );
OAI21XLTS U2275 ( .A0(n2893), .A1(n3880), .B0(n2894), .Y(n966) );
XOR2XLTS U2276 ( .A(n3473), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1360) );
XOR2XLTS U2277 ( .A(n3374), .B(n279), .Y(genblk1_right_mult_x_1_n1306) );
XOR2XLTS U2278 ( .A(n3520), .B(n267), .Y(genblk1_right_mult_x_1_n1387) );
CLKBUFX2TS U2279 ( .A(n3602), .Y(n3621) );
XOR2XLTS U2280 ( .A(n3624), .B(n276), .Y(genblk1_right_mult_x_1_n1443) );
XOR2XLTS U2281 ( .A(n3380), .B(n280), .Y(genblk1_right_mult_x_1_n1308) );
XOR2XLTS U2282 ( .A(n3527), .B(n268), .Y(genblk1_right_mult_x_1_n1389) );
XOR2XLTS U2283 ( .A(n3479), .B(n263), .Y(genblk1_right_mult_x_1_n1363) );
XOR2XLTS U2284 ( .A(n3435), .B(n259), .Y(genblk1_right_mult_x_1_n1336) );
XOR2XLTS U2285 ( .A(n3382), .B(n279), .Y(genblk1_right_mult_x_1_n1309) );
XOR2XLTS U2286 ( .A(n3752), .B(n260), .Y(n3759) );
XOR2XLTS U2287 ( .A(n3757), .B(n270), .Y(n3758) );
OAI21XLTS U2288 ( .A0(n3751), .A1(n3807), .B0(n3750), .Y(n3752) );
XOR2XLTS U2289 ( .A(n3687), .B(n285), .Y(genblk1_right_mult_x_1_n1472) );
XOR2XLTS U2290 ( .A(n3532), .B(n268), .Y(genblk1_right_mult_x_1_n1391) );
XOR2XLTS U2291 ( .A(n3577), .B(n272), .Y(genblk1_right_mult_x_1_n1418) );
XOR2XLTS U2292 ( .A(n3808), .B(n259), .Y(n3809) );
XOR2XLTS U2293 ( .A(n3802), .B(n264), .Y(n3810) );
OAI21XLTS U2294 ( .A0(n321), .A1(n3807), .B0(n3806), .Y(n3808) );
XOR2XLTS U2295 ( .A(n3051), .B(n260), .Y(n3060) );
OAI21XLTS U2296 ( .A0(n3600), .A1(n3416), .B0(n3050), .Y(n3051) );
XOR2X1TS U2297 ( .A(n3186), .B(n3185), .Y(n3692) );
INVX2TS U2298 ( .A(n3180), .Y(n3181) );
XOR2XLTS U2299 ( .A(n3485), .B(n264), .Y(genblk1_right_mult_x_1_n1367) );
XOR2XLTS U2300 ( .A(n3583), .B(n270), .Y(genblk1_right_mult_x_1_n1421) );
XOR2XLTS U2301 ( .A(n3538), .B(n267), .Y(genblk1_right_mult_x_1_n1394) );
OAI21XLTS U2302 ( .A0(n324), .A1(n3707), .B0(n3697), .Y(n3698) );
XOR2X1TS U2303 ( .A(n2969), .B(n2968), .Y(n3701) );
OAI21XLTS U2304 ( .A0(n3243), .A1(n2964), .B0(n2963), .Y(n2969) );
INVX2TS U2305 ( .A(n2965), .Y(n2967) );
OAI21XLTS U2306 ( .A0(n354), .A1(n3661), .B0(n3643), .Y(n3644) );
XOR2XLTS U2307 ( .A(n3587), .B(n272), .Y(genblk1_right_mult_x_1_n1423) );
XOR2XLTS U2308 ( .A(n3544), .B(n267), .Y(genblk1_right_mult_x_1_n1396) );
XOR2XLTS U2309 ( .A(n3489), .B(n264), .Y(genblk1_right_mult_x_1_n1369) );
OAI21XLTS U2310 ( .A0(n337), .A1(n3661), .B0(n3645), .Y(n3646) );
XOR2XLTS U2311 ( .A(n3782), .B(n268), .Y(n3783) );
XOR2XLTS U2312 ( .A(n3776), .B(n271), .Y(n3784) );
OAI21XLTS U2313 ( .A0(n321), .A1(n3781), .B0(n3780), .Y(n3782) );
XOR2X1TS U2314 ( .A(n3210), .B(n3209), .Y(n3708) );
OAI21XLTS U2315 ( .A0(n3243), .A1(n3205), .B0(n3204), .Y(n3210) );
INVX2TS U2316 ( .A(n3206), .Y(n3208) );
XOR2XLTS U2317 ( .A(n3732), .B(Data_A_i[11]), .Y(n3740) );
XOR2XLTS U2318 ( .A(n3738), .B(n285), .Y(n3739) );
OAI21XLTS U2319 ( .A0(n3751), .A1(n3781), .B0(n3731), .Y(n3732) );
OAI21XLTS U2320 ( .A0(n3715), .A1(n3661), .B0(n3647), .Y(n3648) );
OAI21XLTS U2321 ( .A0(n322), .A1(n3661), .B0(n3651), .Y(n3652) );
OAI21XLTS U2322 ( .A0(n321), .A1(n3775), .B0(n3592), .Y(n3593) );
OAI21XLTS U2323 ( .A0(n3715), .A1(n3737), .B0(n3714), .Y(n3716) );
OAI21XLTS U2324 ( .A0(n3655), .A1(n3661), .B0(n3654), .Y(n3656) );
OAI21XLTS U2325 ( .A0(n3751), .A1(n3775), .B0(n3594), .Y(n3595) );
XOR2XLTS U2326 ( .A(n846), .B(n272), .Y(n890) );
OAI21XLTS U2327 ( .A0(n3079), .A1(n3599), .B0(n845), .Y(n846) );
INVX2TS U2328 ( .A(n273), .Y(n276) );
XOR2XLTS U2329 ( .A(n283), .B(Data_A_i[1]), .Y(n857) );
NAND2X1TS U2330 ( .A(n1833), .B(n1595), .Y(n1790) );
INVX2TS U2331 ( .A(n2102), .Y(n1629) );
INVX2TS U2332 ( .A(n2124), .Y(n1627) );
CLKAND2X2TS U2333 ( .A(n2760), .B(n2315), .Y(n1601) );
OAI21XLTS U2334 ( .A0(n2460), .A1(n2765), .B0(n2459), .Y(n2461) );
OAI21XLTS U2335 ( .A0(n2318), .A1(n2393), .B0(n2207), .Y(n2208) );
CLKAND2X2TS U2336 ( .A(n2646), .B(n2315), .Y(n2206) );
CLKAND2X2TS U2337 ( .A(n2484), .B(n2679), .Y(n2168) );
OAI21XLTS U2338 ( .A0(n2460), .A1(n2648), .B0(n2213), .Y(n2215) );
CLKAND2X2TS U2339 ( .A(n2680), .B(n2679), .Y(n2690) );
CLKAND2X2TS U2340 ( .A(n2415), .B(n2315), .Y(n1926) );
INVX2TS U2341 ( .A(n1451), .Y(n1394) );
CLKBUFX2TS U2342 ( .A(n2643), .Y(n2662) );
CLKBUFX2TS U2343 ( .A(n2396), .Y(n2484) );
CLKAND2X2TS U2344 ( .A(n2345), .B(n2802), .Y(genblk1_middle_mult_x_1_n1010)
);
XOR2XLTS U2345 ( .A(n2217), .B(n2424), .Y(genblk1_middle_mult_x_1_n1369) );
XOR2XLTS U2346 ( .A(n2344), .B(n2343), .Y(genblk1_middle_mult_x_1_n1397) );
XOR2XLTS U2347 ( .A(n2245), .B(n2424), .Y(genblk1_middle_mult_x_1_n1376) );
XOR2XLTS U2348 ( .A(n2288), .B(n2785), .Y(genblk1_middle_mult_x_1_n1320) );
XOR2XLTS U2349 ( .A(n2199), .B(n2815), .Y(genblk1_middle_mult_x_1_n1461) );
XOR2XLTS U2350 ( .A(n2453), .B(n2526), .Y(genblk1_middle_mult_x_1_n1405) );
XOR2XLTS U2351 ( .A(n2527), .B(n2526), .Y(genblk1_middle_mult_x_1_n1407) );
XOR2XLTS U2352 ( .A(n2292), .B(n2785), .Y(genblk1_middle_mult_x_1_n1323) );
XOR2XLTS U2353 ( .A(n2482), .B(n2507), .Y(genblk1_middle_mult_x_1_n1436) );
XOR2XLTS U2354 ( .A(n1915), .B(n2666), .Y(genblk1_middle_mult_x_1_n1352) );
XOR2XLTS U2355 ( .A(n1958), .B(n2526), .Y(genblk1_middle_mult_x_1_n1408) );
XOR2XLTS U2356 ( .A(n2337), .B(n2336), .Y(genblk1_middle_mult_x_1_n1521) );
XOR2XLTS U2357 ( .A(n2500), .B(n2507), .Y(genblk1_middle_mult_x_1_n1437) );
XOR2XLTS U2358 ( .A(n1940), .B(n2686), .Y(genblk1_middle_mult_x_1_n1381) );
CLKAND2X2TS U2359 ( .A(n2642), .B(n25), .Y(genblk1_middle_mult_x_1_n1022) );
XOR2XLTS U2360 ( .A(n2205), .B(n2666), .Y(genblk1_middle_mult_x_1_n1353) );
XOR2XLTS U2361 ( .A(n2290), .B(n2785), .Y(genblk1_middle_mult_x_1_n1325) );
XOR2XLTS U2362 ( .A(n2508), .B(n2507), .Y(genblk1_middle_mult_x_1_n1438) );
XOR2XLTS U2363 ( .A(n2329), .B(n2465), .Y(genblk1_middle_mult_x_1_n1494) );
XOR2XLTS U2364 ( .A(n2325), .B(result_A_adder_2_), .Y(
genblk1_middle_mult_x_1_n1552) );
XOR2XLTS U2365 ( .A(n1963), .B(n2753), .Y(genblk1_middle_mult_x_1_n1412) );
XOR2XLTS U2366 ( .A(n1999), .B(n2446), .Y(genblk1_middle_mult_x_1_n1468) );
CLKAND2X2TS U2367 ( .A(n2758), .B(n2802), .Y(genblk1_middle_mult_x_1_n1025)
);
XOR2XLTS U2368 ( .A(n2242), .B(n2686), .Y(genblk1_middle_mult_x_1_n1384) );
XOR2XLTS U2369 ( .A(n1918), .B(n2214), .Y(genblk1_middle_mult_x_1_n1356) );
CMPR42X1TS U2370 ( .A(genblk1_middle_mult_x_1_n816), .B(
genblk1_middle_mult_x_1_n1441), .C(genblk1_middle_mult_x_1_n1469), .D(
genblk1_middle_mult_x_1_n1525), .ICI(genblk1_middle_mult_x_1_n810),
.S(genblk1_middle_mult_x_1_n803), .ICO(genblk1_middle_mult_x_1_n801),
.CO(genblk1_middle_mult_x_1_n802) );
XOR2XLTS U2371 ( .A(n2001), .B(n2446), .Y(genblk1_middle_mult_x_1_n1469) );
XOR2XLTS U2372 ( .A(n2341), .B(n2411), .Y(genblk1_middle_mult_x_1_n1525) );
XOR2XLTS U2373 ( .A(n2429), .B(n2465), .Y(genblk1_middle_mult_x_1_n1498) );
XOR2XLTS U2374 ( .A(n2435), .B(n2706), .Y(genblk1_middle_mult_x_1_n1442) );
XOR2XLTS U2375 ( .A(n1966), .B(n2753), .Y(genblk1_middle_mult_x_1_n1414) );
XOR2XLTS U2376 ( .A(n2029), .B(n2465), .Y(genblk1_middle_mult_x_1_n1499) );
XOR2XLTS U2377 ( .A(n2492), .B(n2552), .Y(genblk1_middle_mult_x_1_n1443) );
XOR2XLTS U2378 ( .A(n2390), .B(n2411), .Y(genblk1_middle_mult_x_1_n1527) );
XOR2XLTS U2379 ( .A(n2159), .B(n2596), .Y(genblk1_middle_mult_x_1_n1555) );
XOR2XLTS U2380 ( .A(n2354), .B(n2596), .Y(genblk1_middle_mult_x_1_n1557) );
XOR2XLTS U2381 ( .A(n2538), .B(n2552), .Y(genblk1_middle_mult_x_1_n1445) );
OAI21XLTS U2382 ( .A0(n2403), .A1(n2515), .B0(n2353), .Y(n2354) );
XOR2XLTS U2383 ( .A(n2466), .B(n2465), .Y(genblk1_middle_mult_x_1_n1501) );
XOR2XLTS U2384 ( .A(n2010), .B(n2812), .Y(genblk1_middle_mult_x_1_n1473) );
NAND2X1TS U2385 ( .A(n1216), .B(n1211), .Y(n565) );
XOR2XLTS U2386 ( .A(n2487), .B(n4983), .Y(genblk1_middle_mult_x_1_n1560) );
XOR2XLTS U2387 ( .A(n2251), .B(n2552), .Y(genblk1_middle_mult_x_1_n1448) );
XOR2XLTS U2388 ( .A(n2363), .B(n2743), .Y(genblk1_middle_mult_x_1_n1392) );
CMPR42X1TS U2389 ( .A(genblk1_middle_mult_x_1_n899), .B(
genblk1_middle_mult_x_1_n1504), .C(genblk1_middle_mult_x_1_n1532), .D(
genblk1_middle_mult_x_1_n1476), .ICI(genblk1_middle_mult_x_1_n894),
.S(genblk1_middle_mult_x_1_n885), .ICO(genblk1_middle_mult_x_1_n883),
.CO(genblk1_middle_mult_x_1_n884) );
XOR2XLTS U2390 ( .A(n2568), .B(n2567), .Y(genblk1_middle_mult_x_1_n1476) );
XOR2XLTS U2391 ( .A(n2038), .B(n2724), .Y(genblk1_middle_mult_x_1_n1504) );
XOR2XLTS U2392 ( .A(n2058), .B(n2411), .Y(genblk1_middle_mult_x_1_n1532) );
XOR2XLTS U2393 ( .A(n1755), .B(n1754), .Y(n1764) );
INVX2TS U2394 ( .A(n1555), .Y(n1166) );
CLKBUFX2TS U2395 ( .A(n2426), .Y(n2554) );
XOR2XLTS U2396 ( .A(n2238), .B(n2714), .Y(genblk1_middle_mult_x_1_n1423) );
XOR2XLTS U2397 ( .A(n2496), .B(n4983), .Y(genblk1_middle_mult_x_1_n1563) );
XOR2XLTS U2398 ( .A(n2064), .B(n2080), .Y(genblk1_middle_mult_x_1_n1535) );
XOR2XLTS U2399 ( .A(n1774), .B(n2815), .Y(n1775) );
XOR2XLTS U2400 ( .A(n1769), .B(n2706), .Y(n1776) );
OAI21XLTS U2401 ( .A0(n2752), .A1(n2566), .B0(n1773), .Y(n1774) );
XOR2X1TS U2402 ( .A(n1886), .B(n1885), .Y(n2477) );
OAI21XLTS U2403 ( .A0(n2665), .A1(n2571), .B0(n2248), .Y(n2249) );
CMPR42X1TS U2404 ( .A(genblk1_middle_mult_x_1_n1454), .B(
genblk1_middle_mult_x_1_n944), .C(genblk1_middle_mult_x_1_n1482), .D(
genblk1_middle_mult_x_1_n950), .ICI(genblk1_middle_mult_x_1_n1538),
.S(genblk1_middle_mult_x_1_n942), .ICO(genblk1_middle_mult_x_1_n940),
.CO(genblk1_middle_mult_x_1_n941) );
XOR2XLTS U2405 ( .A(n2561), .B(n2800), .Y(genblk1_middle_mult_x_1_n1538) );
XOR2XLTS U2406 ( .A(n2020), .B(n2812), .Y(genblk1_middle_mult_x_1_n1482) );
OAI21XLTS U2407 ( .A0(n2437), .A1(n2546), .B0(n2091), .Y(n2092) );
OAI21XLTS U2408 ( .A0(n2535), .A1(n2546), .B0(n2093), .Y(n2094) );
XOR2XLTS U2409 ( .A(n1344), .B(n2193), .Y(n1376) );
OAI21XLTS U2410 ( .A0(n327), .A1(n2723), .B0(n1343), .Y(n1344) );
AOI222XLTS U2411 ( .A0(n2721), .A1(n2747), .B0(n2555), .B1(n2670), .C0(n2554), .C1(n2669), .Y(n1343) );
INVX2TS U2412 ( .A(n1909), .Y(n1911) );
OAI21XLTS U2413 ( .A0(n2752), .A1(n2571), .B0(n2073), .Y(n2074) );
XNOR2X1TS U2414 ( .A(n2069), .B(n2068), .Y(n2784) );
INVX2TS U2415 ( .A(n2065), .Y(n2067) );
OAI21XLTS U2416 ( .A0(n327), .A1(n2571), .B0(n2075), .Y(n2076) );
OAI21XLTS U2417 ( .A0(n2764), .A1(n2723), .B0(n2045), .Y(n2046) );
OAI21XLTS U2418 ( .A0(n19), .A1(n2571), .B0(n2077), .Y(n2078) );
OAI21XLTS U2419 ( .A0(n2595), .A1(n2594), .B0(n2593), .Y(n2597) );
ADDHXLTS U2420 ( .A(n2817), .B(n2816), .CO(genblk1_middle_mult_x_1_n974),
.S(genblk1_middle_mult_x_1_n975) );
XOR2XLTS U2421 ( .A(n2813), .B(n2812), .Y(n2817) );
OAI21XLTS U2422 ( .A0(n2811), .A1(n2810), .B0(n2809), .Y(n2813) );
OAI21XLTS U2423 ( .A0(n2361), .A1(n2464), .B0(n2047), .Y(n2048) );
OAI21XLTS U2424 ( .A0(n345), .A1(n2571), .B0(n2079), .Y(n2081) );
OAI21XLTS U2425 ( .A0(n2752), .A1(n2594), .B0(n2583), .Y(n2584) );
OAI21XLTS U2426 ( .A0(n2764), .A1(n2571), .B0(n1282), .Y(n1283) );
NAND2X1TS U2427 ( .A(n448), .B(n447), .Y(n449) );
CLKAND2X2TS U2428 ( .A(n2454), .B(n2679), .Y(genblk1_middle_mult_x_1_n1003)
);
XOR2XLTS U2429 ( .A(n2226), .B(n2225), .Y(genblk1_middle_mult_x_1_n1306) );
OAI21XLTS U2430 ( .A0(n2285), .A1(n2765), .B0(n2224), .Y(n2226) );
CLKAND2X2TS U2431 ( .A(n4039), .B(n114), .Y(n649) );
OAI21XLTS U2432 ( .A0(n333), .A1(n4569), .B0(n4566), .Y(n4567) );
INVX2TS U2433 ( .A(n3991), .Y(n3993) );
CLKAND2X2TS U2434 ( .A(n4039), .B(n105), .Y(n3996) );
OAI21XLTS U2435 ( .A0(n4954), .A1(n4569), .B0(n4564), .Y(n4565) );
OAI21XLTS U2436 ( .A0(n4887), .A1(n4599), .B0(n4601), .Y(n4600) );
XOR2XLTS U2437 ( .A(n4943), .B(n180), .Y(genblk1_left_mult_x_1_n1304) );
XOR2XLTS U2438 ( .A(n4223), .B(n4981), .Y(genblk1_left_mult_x_1_n1330) );
XOR2XLTS U2439 ( .A(n4877), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1278) );
XOR2XLTS U2440 ( .A(n749), .B(n4959), .Y(n753) );
XOR2XLTS U2441 ( .A(n710), .B(n179), .Y(n751) );
OAI21XLTS U2442 ( .A0(n21), .A1(n4922), .B0(n709), .Y(n710) );
XOR2XLTS U2443 ( .A(n737), .B(n4959), .Y(n740) );
XOR2XLTS U2444 ( .A(n714), .B(n180), .Y(n738) );
OAI21XLTS U2445 ( .A0(n4541), .A1(n4922), .B0(n713), .Y(n714) );
CLKBUFX2TS U2446 ( .A(n4961), .Y(n4969) );
CLKBUFX2TS U2447 ( .A(n4221), .Y(n4973) );
INVX2TS U2448 ( .A(n607), .Y(n4955) );
CLKAND2X2TS U2449 ( .A(n37), .B(n162), .Y(genblk1_right_mult_x_1_n914) );
CLKAND2X2TS U2450 ( .A(n3307), .B(Data_B_i[26]), .Y(n3274) );
CLKAND2X2TS U2451 ( .A(n36), .B(n158), .Y(n2941) );
XOR2XLTS U2452 ( .A(n3282), .B(n256), .Y(genblk1_right_mult_x_1_n1258) );
XOR2XLTS U2453 ( .A(n3158), .B(n289), .Y(genblk1_right_mult_x_1_n1231) );
OAI21XLTS U2454 ( .A0(n3676), .A1(n3291), .B0(n3281), .Y(n3282) );
CMPR42X1TS U2455 ( .A(genblk1_right_mult_x_1_n1317), .B(
genblk1_right_mult_x_1_n582), .C(genblk1_right_mult_x_1_n588), .D(
genblk1_right_mult_x_1_n580), .ICI(genblk1_right_mult_x_1_n584), .S(
genblk1_right_mult_x_1_n577), .ICO(genblk1_right_mult_x_1_n575), .CO(
genblk1_right_mult_x_1_n576) );
XOR2XLTS U2456 ( .A(n3392), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1317) );
OAI21XLTS U2457 ( .A0(n3673), .A1(n3402), .B0(n3391), .Y(n3392) );
XOR2XLTS U2458 ( .A(n3591), .B(n270), .Y(genblk1_right_mult_x_1_n1426) );
XOR2XLTS U2459 ( .A(n3650), .B(n275), .Y(genblk1_right_mult_x_1_n1453) );
XOR2XLTS U2460 ( .A(n3711), .B(n284), .Y(genblk1_right_mult_x_1_n1480) );
XOR2XLTS U2461 ( .A(n3720), .B(n284), .Y(genblk1_right_mult_x_1_n1483) );
XOR2XLTS U2462 ( .A(n3601), .B(n270), .Y(genblk1_right_mult_x_1_n1429) );
XOR2XLTS U2463 ( .A(n3662), .B(n275), .Y(genblk1_right_mult_x_1_n1456) );
XOR2XLTS U2464 ( .A(n872), .B(n275), .Y(n904) );
XOR2XLTS U2465 ( .A(n859), .B(n285), .Y(n905) );
OAI21XLTS U2466 ( .A0(n321), .A1(n3661), .B0(n871), .Y(n872) );
XOR2XLTS U2467 ( .A(n919), .B(n285), .Y(n943) );
OAI21XLTS U2468 ( .A0(n352), .A1(n3737), .B0(n918), .Y(n919) );
XOR2XLTS U2469 ( .A(n899), .B(n275), .Y(n940) );
OAI21XLTS U2470 ( .A0(n314), .A1(n3636), .B0(n898), .Y(n899) );
XOR2XLTS U2471 ( .A(n931), .B(Data_A_i[2]), .Y(n935) );
OAI21XLTS U2472 ( .A0(n3751), .A1(n3737), .B0(n930), .Y(n931) );
CLKBUFX2TS U2473 ( .A(n3703), .Y(n3699) );
NAND2X1TS U2474 ( .A(n842), .B(n891), .Y(n3746) );
CLKBUFX2TS U2475 ( .A(n25), .Y(n2802) );
CMPR42X1TS U2476 ( .A(genblk1_middle_mult_x_1_n1004), .B(
genblk1_middle_mult_x_1_n607), .C(genblk1_middle_mult_x_1_n1335), .D(
genblk1_middle_mult_x_1_n1307), .ICI(genblk1_middle_mult_x_1_n604),
.S(genblk1_middle_mult_x_1_n602), .ICO(genblk1_middle_mult_x_1_n600),
.CO(genblk1_middle_mult_x_1_n601) );
CLKAND2X2TS U2477 ( .A(n2326), .B(n2679), .Y(genblk1_middle_mult_x_1_n1004)
);
XOR2XLTS U2478 ( .A(n1825), .B(n2666), .Y(genblk1_middle_mult_x_1_n1335) );
XOR2XLTS U2479 ( .A(n2461), .B(n1100), .Y(genblk1_middle_mult_x_1_n1307) );
CMPR42X1TS U2480 ( .A(genblk1_middle_mult_x_1_n607), .B(
genblk1_middle_mult_x_1_n611), .C(genblk1_middle_mult_x_1_n1308), .D(
genblk1_middle_mult_x_1_n1336), .ICI(genblk1_middle_mult_x_1_n608),
.S(genblk1_middle_mult_x_1_n606), .ICO(genblk1_middle_mult_x_1_n604),
.CO(genblk1_middle_mult_x_1_n605) );
XOR2XLTS U2481 ( .A(n1795), .B(n2225), .Y(genblk1_middle_mult_x_1_n1308) );
XOR2XLTS U2482 ( .A(n2208), .B(n2214), .Y(genblk1_middle_mult_x_1_n1336) );
OAI21XLTS U2483 ( .A0(n2357), .A1(n302), .B0(n1794), .Y(n1795) );
CMPR42X1TS U2484 ( .A(genblk1_middle_mult_x_1_n1311), .B(
genblk1_middle_mult_x_1_n1367), .C(genblk1_middle_mult_x_1_n623), .D(
genblk1_middle_mult_x_1_n629), .ICI(genblk1_middle_mult_x_1_n625), .S(
genblk1_middle_mult_x_1_n621), .ICO(genblk1_middle_mult_x_1_n619),
.CO(genblk1_middle_mult_x_1_n620) );
XOR2XLTS U2485 ( .A(n1808), .B(n2225), .Y(genblk1_middle_mult_x_1_n1311) );
XOR2XLTS U2486 ( .A(n1928), .B(n2686), .Y(genblk1_middle_mult_x_1_n1367) );
OAI21XLTS U2487 ( .A0(n2410), .A1(n303), .B0(n1807), .Y(n1808) );
INVX2TS U2488 ( .A(n1638), .Y(n1391) );
XOR2XLTS U2489 ( .A(n1946), .B(n2753), .Y(genblk1_middle_mult_x_1_n1398) );
XOR2XLTS U2490 ( .A(n2385), .B(n2753), .Y(genblk1_middle_mult_x_1_n1400) );
OAI21XLTS U2491 ( .A0(n2460), .A1(n2713), .B0(n2384), .Y(n2385) );
XOR2XLTS U2492 ( .A(n2086), .B(n2576), .Y(genblk1_middle_mult_x_1_n1558) );
OAI21XLTS U2493 ( .A0(n2389), .A1(n2515), .B0(n2085), .Y(n2086) );
XOR2XLTS U2494 ( .A(n2572), .B(n2800), .Y(genblk1_middle_mult_x_1_n1540) );
XOR2XLTS U2495 ( .A(n2101), .B(n2576), .Y(genblk1_middle_mult_x_1_n1568) );
OAI21XLTS U2496 ( .A0(n2595), .A1(n2571), .B0(n2570), .Y(n2572) );
XOR2XLTS U2497 ( .A(n1245), .B(n2596), .Y(n1295) );
OAI21XLTS U2498 ( .A0(n327), .A1(n2594), .B0(n1244), .Y(n1245) );
XOR2XLTS U2499 ( .A(n1250), .B(n2596), .Y(n1289) );
XOR2XLTS U2500 ( .A(n1248), .B(n2080), .Y(n1290) );
OAI21XLTS U2501 ( .A0(n345), .A1(n2546), .B0(n1249), .Y(n1250) );
XOR2XLTS U2502 ( .A(n1269), .B(n2080), .Y(n1275) );
XOR2XLTS U2503 ( .A(n1268), .B(n2576), .Y(n1276) );
OAI21XLTS U2504 ( .A0(n2768), .A1(n2810), .B0(n330), .Y(n1269) );
INVX2TS U2505 ( .A(n1182), .Y(n4983) );
NAND2X1TS U2506 ( .A(n318), .B(n435), .Y(n423) );
XOR2XLTS U2507 ( .A(n812), .B(Data_A_i[50]), .Y(n814) );
XOR2XLTS U2508 ( .A(n4563), .B(Data_A_i[50]), .Y(genblk1_left_mult_x_1_n1113) );
XOR2XLTS U2509 ( .A(n734), .B(n4981), .Y(n4417) );
OAI21XLTS U2510 ( .A0(n4551), .A1(n4971), .B0(n733), .Y(n734) );
CLKAND2X2TS U2511 ( .A(n287), .B(n127), .Y(n1444) );
XOR2XLTS U2512 ( .A(n1437), .B(n36), .Y(n1441) );
OAI21XLTS U2513 ( .A0(n3665), .A1(n3166), .B0(n1436), .Y(n1437) );
XOR2XLTS U2514 ( .A(n1428), .B(Data_A_i[26]), .Y(n1438) );
XOR2XLTS U2515 ( .A(n3134), .B(n287), .Y(genblk1_right_mult_x_1_n1229) );
XOR2XLTS U2516 ( .A(n3278), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1256) );
OR2X1TS U2517 ( .A(genblk1_right_mult_x_1_n543), .B(
genblk1_right_mult_x_1_n548), .Y(n2843) );
INVX2TS U2518 ( .A(n2838), .Y(n2841) );
OR2X1TS U2519 ( .A(genblk1_right_mult_x_1_n871), .B(
genblk1_right_mult_x_1_n877), .Y(n2916) );
OAI21XLTS U2520 ( .A0(n3936), .A1(n3933), .B0(n3934), .Y(n2930) );
CLKAND2X2TS U2521 ( .A(n2795), .B(n2679), .Y(n1642) );
XOR2XLTS U2522 ( .A(n1635), .B(n2225), .Y(n1640) );
CLKAND2X2TS U2523 ( .A(n2796), .B(n2802), .Y(n1658) );
AOI21X1TS U2524 ( .A0(n2255), .A1(n2259), .B0(n1484), .Y(n1472) );
XOR2XLTS U2525 ( .A(n1262), .B(n2576), .Y(n1750) );
OAI21XLTS U2526 ( .A0(n2810), .A1(n2546), .B0(n341), .Y(n1262) );
CLKAND2X2TS U2527 ( .A(n1605), .B(n1643), .Y(n343) );
XOR2XLTS U2528 ( .A(n1172), .B(n831), .Y(n832) );
XOR2XLTS U2529 ( .A(n2274), .B(n2273), .Y(genblk1_middle_N53) );
XOR2XLTS U2530 ( .A(n2261), .B(n2260), .Y(genblk1_middle_N47) );
AOI2BB1X1TS U2531 ( .A0N(n2257), .A1N(n2256), .B0(n2255), .Y(n2261) );
INVX2TS U2532 ( .A(n1660), .Y(n1661) );
CLKAND2X2TS U2533 ( .A(n1474), .B(n1480), .Y(n332) );
XOR2XLTS U2534 ( .A(n2269), .B(n2268), .Y(genblk1_middle_N39) );
XOR2XLTS U2535 ( .A(n4082), .B(n4081), .Y(genblk1_left_N44) );
XOR2XLTS U2536 ( .A(n4172), .B(n4171), .Y(genblk1_left_N43) );
XOR2XLTS U2537 ( .A(n4123), .B(n4122), .Y(genblk1_left_N40) );
XOR2XLTS U2538 ( .A(n4327), .B(n4093), .Y(genblk1_left_N36) );
XOR2XLTS U2539 ( .A(n4089), .B(n4088), .Y(genblk1_left_N35) );
XOR2XLTS U2540 ( .A(n4115), .B(n4114), .Y(genblk1_left_N33) );
INVX2TS U2541 ( .A(n4111), .Y(n4113) );
XOR2XLTS U2542 ( .A(n4054), .B(n4053), .Y(genblk1_left_N31) );
XOR2XLTS U2543 ( .A(n4108), .B(n4045), .Y(genblk1_left_N30) );
XOR2XLTS U2544 ( .A(n4065), .B(n4064), .Y(genblk1_left_N29) );
INVX2TS U2545 ( .A(n4061), .Y(n4063) );
XOR2XLTS U2546 ( .A(n4347), .B(n4021), .Y(genblk1_left_N26) );
INVX2TS U2547 ( .A(n4346), .Y(n4020) );
INVX2TS U2548 ( .A(n4356), .Y(n4358) );
XOR2XLTS U2549 ( .A(n4355), .B(n4018), .Y(genblk1_left_N24) );
INVX2TS U2550 ( .A(n4354), .Y(n4017) );
XOR2XLTS U2551 ( .A(n4014), .B(n4013), .Y(genblk1_left_N23) );
INVX2TS U2552 ( .A(n4010), .Y(n4012) );
OAI21XLTS U2553 ( .A0(n4367), .A1(n4366), .B0(n4365), .Y(n4372) );
INVX2TS U2554 ( .A(n4368), .Y(n4370) );
XOR2XLTS U2555 ( .A(n4367), .B(n4000), .Y(genblk1_left_N20) );
INVX2TS U2556 ( .A(n4366), .Y(n3999) );
XOR2XLTS U2557 ( .A(n4006), .B(n4005), .Y(genblk1_left_N19) );
INVX2TS U2558 ( .A(n4380), .Y(n4382) );
XOR2XLTS U2559 ( .A(n4379), .B(n3986), .Y(genblk1_left_N16) );
INVX2TS U2560 ( .A(n4378), .Y(n3985) );
XOR2XLTS U2561 ( .A(n3983), .B(n3982), .Y(genblk1_left_N15) );
OAI21XLTS U2562 ( .A0(n4391), .A1(n4390), .B0(n4389), .Y(n4396) );
XOR2XLTS U2563 ( .A(n4391), .B(n3977), .Y(genblk1_left_N12) );
XOR2XLTS U2564 ( .A(n3974), .B(n3973), .Y(genblk1_left_N11) );
XOR2XLTS U2565 ( .A(n3969), .B(n3968), .Y(genblk1_left_N9) );
OAI21XLTS U2566 ( .A0(n4403), .A1(n4402), .B0(n4401), .Y(n4408) );
XOR2XLTS U2567 ( .A(n3964), .B(n4402), .Y(genblk1_left_N7) );
XOR2XLTS U2568 ( .A(n3961), .B(n3960), .Y(genblk1_left_N6) );
XOR2XLTS U2569 ( .A(n3956), .B(n3955), .Y(genblk1_left_N4) );
XOR2XLTS U2570 ( .A(n3951), .B(n3950), .Y(genblk1_left_N2) );
OAI21XLTS U2571 ( .A0(n4506), .A1(n4971), .B0(n608), .Y(
genblk1_left_mult_x_1_n1787) );
XOR2XLTS U2572 ( .A(n1402), .B(n999), .Y(genblk1_right_N49) );
XOR2XLTS U2573 ( .A(n3824), .B(n3823), .Y(genblk1_right_N44) );
XOR2XLTS U2574 ( .A(n3828), .B(n3827), .Y(genblk1_right_N43) );
XOR2XLTS U2575 ( .A(n3816), .B(n3815), .Y(genblk1_right_N41) );
XOR2XLTS U2576 ( .A(n3846), .B(n3845), .Y(genblk1_right_N39) );
XOR2XLTS U2577 ( .A(n3850), .B(n3849), .Y(genblk1_right_N38) );
XOR2XLTS U2578 ( .A(n3834), .B(n3833), .Y(genblk1_right_N37) );
XOR2XLTS U2579 ( .A(n3840), .B(n3839), .Y(genblk1_right_N35) );
XOR2XLTS U2580 ( .A(n3853), .B(n3852), .Y(genblk1_right_N34) );
XOR2XLTS U2581 ( .A(n3858), .B(n3857), .Y(genblk1_right_N32) );
OAI21XLTS U2582 ( .A0(n3863), .A1(n3859), .B0(n3860), .Y(n2878) );
INVX2TS U2583 ( .A(n2874), .Y(n2876) );
XOR2XLTS U2584 ( .A(n3863), .B(n3862), .Y(genblk1_right_N30) );
XOR2XLTS U2585 ( .A(n3872), .B(n3871), .Y(genblk1_right_N29) );
XOR2XLTS U2586 ( .A(n3878), .B(n3877), .Y(genblk1_right_N27) );
XOR2XLTS U2587 ( .A(n3887), .B(n3886), .Y(genblk1_right_N24) );
XOR2XLTS U2588 ( .A(n3883), .B(n3882), .Y(genblk1_right_N22) );
INVX2TS U2589 ( .A(n3879), .Y(n3881) );
XOR2XLTS U2590 ( .A(n3896), .B(n3895), .Y(genblk1_right_N21) );
INVX2TS U2591 ( .A(n3892), .Y(n3894) );
INVX2TS U2592 ( .A(n2901), .Y(n2903) );
XOR2XLTS U2593 ( .A(n3901), .B(n3900), .Y(genblk1_right_N18) );
INVX2TS U2594 ( .A(n3897), .Y(n3899) );
XOR2XLTS U2595 ( .A(n3906), .B(n3905), .Y(genblk1_right_N17) );
INVX2TS U2596 ( .A(n3902), .Y(n3904) );
OAI21XLTS U2597 ( .A0(n3918), .A1(n3914), .B0(n3915), .Y(n2911) );
XOR2XLTS U2598 ( .A(n3918), .B(n3917), .Y(genblk1_right_N15) );
XOR2XLTS U2599 ( .A(n3913), .B(n3912), .Y(genblk1_right_N14) );
XOR2XLTS U2600 ( .A(n3925), .B(n3924), .Y(genblk1_right_N11) );
XOR2XLTS U2601 ( .A(n3932), .B(n3931), .Y(genblk1_right_N8) );
XOR2XLTS U2602 ( .A(n3937), .B(n3936), .Y(genblk1_right_N5) );
XOR2XLTS U2603 ( .A(n3942), .B(n3941), .Y(genblk1_right_N3) );
INVX2TS U2604 ( .A(n2936), .Y(n2938) );
XOR2XLTS U2605 ( .A(n2940), .B(n2939), .Y(genblk1_right_N1) );
OAI21XLTS U2606 ( .A0(n3079), .A1(n3707), .B0(n835), .Y(genblk1_right_N0) );
INVX2TS U2607 ( .A(n1622), .Y(n1624) );
AOI21X1TS U2608 ( .A0(n1679), .A1(n1677), .B0(n1332), .Y(n1335) );
INVX2TS U2609 ( .A(n1381), .Y(n1333) );
XOR2XLTS U2610 ( .A(n2283), .B(n2282), .Y(genblk1_middle_N33) );
INVX2TS U2611 ( .A(n2279), .Y(n2281) );
XOR2XLTS U2612 ( .A(n2302), .B(n2301), .Y(genblk1_middle_N30) );
INVX2TS U2613 ( .A(n2298), .Y(n2300) );
OAI21XLTS U2614 ( .A0(n2297), .A1(n2293), .B0(n2294), .Y(n1699) );
INVX2TS U2615 ( .A(n1695), .Y(n1697) );
XOR2XLTS U2616 ( .A(n2297), .B(n2296), .Y(genblk1_middle_N28) );
INVX2TS U2617 ( .A(n2293), .Y(n2295) );
XOR2XLTS U2618 ( .A(n2310), .B(n2309), .Y(genblk1_middle_N27) );
INVX2TS U2619 ( .A(n2306), .Y(n2308) );
XOR2XLTS U2620 ( .A(n2370), .B(n2369), .Y(genblk1_middle_N25) );
XOR2XLTS U2621 ( .A(n2382), .B(n2381), .Y(genblk1_middle_N22) );
XOR2XLTS U2622 ( .A(n2472), .B(n2471), .Y(genblk1_middle_N21) );
INVX2TS U2623 ( .A(n1716), .Y(n1718) );
XOR2XLTS U2624 ( .A(n2589), .B(n2588), .Y(genblk1_middle_N18) );
INVX2TS U2625 ( .A(n2585), .Y(n2587) );
XOR2XLTS U2626 ( .A(n2602), .B(n2601), .Y(genblk1_middle_N17) );
INVX2TS U2627 ( .A(n2598), .Y(n2600) );
INVX2TS U2628 ( .A(n1722), .Y(n1724) );
XOR2XLTS U2629 ( .A(n2613), .B(n2612), .Y(genblk1_middle_N15) );
INVX2TS U2630 ( .A(n2609), .Y(n2611) );
XOR2XLTS U2631 ( .A(n2608), .B(n2607), .Y(genblk1_middle_N14) );
XOR2XLTS U2632 ( .A(n2618), .B(n2617), .Y(genblk1_middle_N11) );
INVX2TS U2633 ( .A(n2614), .Y(n2616) );
XOR2XLTS U2634 ( .A(n2623), .B(n2622), .Y(genblk1_middle_N10) );
INVX2TS U2635 ( .A(n2619), .Y(n2621) );
XOR2XLTS U2636 ( .A(n2628), .B(n2627), .Y(genblk1_middle_N8) );
XOR2XLTS U2637 ( .A(n2633), .B(n2632), .Y(genblk1_middle_N6) );
XOR2XLTS U2638 ( .A(n2638), .B(n2637), .Y(genblk1_middle_N4) );
XOR2XLTS U2639 ( .A(n2640), .B(n2639), .Y(genblk1_middle_N2) );
OAI21XLTS U2640 ( .A0(n2594), .A1(n424), .B0(n312), .Y(genblk1_middle_N0) );
OAI21XLTS U2641 ( .A0(n21), .A1(n4668), .B0(n4524), .Y(n4525) );
OAI21X2TS U2642 ( .A0(n4001), .A1(n774), .B0(n773), .Y(n3998) );
AOI21X2TS U2643 ( .A0(n965), .A1(n2900), .B0(n964), .Y(n2890) );
OAI21XLTS U2644 ( .A0(n21), .A1(n4569), .B0(n4500), .Y(n4501) );
XNOR2X1TS U2645 ( .A(n197), .B(Data_A_i[48]), .Y(n4210) );
OAI21X4TS U2646 ( .A0(n1712), .A1(n1316), .B0(n1315), .Y(n1702) );
AOI21X4TS U2647 ( .A0(n1313), .A1(n1715), .B0(n1312), .Y(n1712) );
AOI21X2TS U2648 ( .A0(n2470), .A1(n2467), .B0(n1314), .Y(n1315) );
XOR2X2TS U2649 ( .A(n287), .B(Data_A_i[25]), .Y(n2971) );
OAI21X1TS U2650 ( .A0(n3868), .A1(n3864), .B0(n3869), .Y(n2872) );
AOI21X4TS U2651 ( .A0(n1702), .A1(n1323), .B0(n1322), .Y(n1692) );
OR2X4TS U2652 ( .A(genblk1_middle_mult_x_1_n947), .B(
genblk1_middle_mult_x_1_n953), .Y(n357) );
OAI21XLTS U2653 ( .A0(n2491), .A1(n2361), .B0(n2229), .Y(n2230) );
ADDHX1TS U2654 ( .A(n2717), .B(n2716), .CO(genblk1_middle_mult_x_1_n927),
.S(genblk1_middle_mult_x_1_n928) );
AOI21X4TS U2655 ( .A0(n1609), .A1(n1393), .B0(n1392), .Y(n1651) );
OAI21X1TS U2656 ( .A0(n1651), .A1(n1471), .B0(n1470), .Y(n2255) );
OAI21XLTS U2657 ( .A0(n2535), .A1(n2362), .B0(n1939), .Y(n1940) );
NOR2X2TS U2658 ( .A(n1026), .B(n381), .Y(n1037) );
NAND2X1TS U2659 ( .A(Data_A_i[28]), .B(Data_A_i[1]), .Y(n568) );
INVX2TS U2660 ( .A(Data_A_i[8]), .Y(n269) );
INVX2TS U2661 ( .A(n2660), .Y(n294) );
XNOR2X1TS U2662 ( .A(n1002), .B(n1001), .Y(n19) );
XOR2X1TS U2663 ( .A(n1073), .B(n462), .Y(n20) );
XNOR2X1TS U2664 ( .A(n651), .B(n702), .Y(n21) );
XNOR2X1TS U2665 ( .A(n3995), .B(n3994), .Y(n22) );
XNOR2X1TS U2666 ( .A(n4156), .B(n665), .Y(n23) );
XNOR2X1TS U2667 ( .A(n4073), .B(n4072), .Y(n24) );
NOR2BX2TS U2668 ( .AN(n1060), .B(n1061), .Y(n1964) );
OR2X1TS U2669 ( .A(n45), .B(n50), .Y(n27) );
AO21X2TS U2670 ( .A0(n1411), .A1(n1410), .B0(n1409), .Y(n28) );
INVX2TS U2671 ( .A(n429), .Y(n2760) );
INVX2TS U2672 ( .A(n585), .Y(n595) );
OR2X2TS U2673 ( .A(Data_B_i[20]), .B(n105), .Y(n31) );
INVX2TS U2674 ( .A(n290), .Y(n291) );
OR2X1TS U2675 ( .A(n170), .B(n117), .Y(n32) );
OR2X4TS U2676 ( .A(n130), .B(n77), .Y(n33) );
OR2X2TS U2677 ( .A(n138), .B(Data_B_i[41]), .Y(n34) );
OR2X4TS U2678 ( .A(n209), .B(n69), .Y(n35) );
INVX2TS U2679 ( .A(n41), .Y(n1431) );
INVX2TS U2680 ( .A(n615), .Y(n516) );
INVX2TS U2681 ( .A(n38), .Y(n630) );
INVX2TS U2682 ( .A(Data_A_i[44]), .Y(n193) );
INVX2TS U2683 ( .A(Data_A_i[20]), .Y(n277) );
INVX2TS U2684 ( .A(n286), .Y(n36) );
INVX2TS U2685 ( .A(n286), .Y(n37) );
INVX2TS U2686 ( .A(Data_B_i[51]), .Y(n38) );
INVX2TS U2687 ( .A(n38), .Y(n39) );
INVX2TS U2688 ( .A(n38), .Y(n40) );
INVX2TS U2689 ( .A(Data_B_i[26]), .Y(n41) );
INVX2TS U2690 ( .A(n41), .Y(n42) );
INVX2TS U2691 ( .A(n41), .Y(n43) );
INVX2TS U2692 ( .A(Data_B_i[29]), .Y(n44) );
INVX2TS U2693 ( .A(n44), .Y(n45) );
INVX2TS U2694 ( .A(n44), .Y(n46) );
INVX2TS U2695 ( .A(n44), .Y(n47) );
INVX2TS U2696 ( .A(Data_B_i[30]), .Y(n48) );
INVX2TS U2697 ( .A(n48), .Y(n49) );
INVX2TS U2698 ( .A(n48), .Y(n50) );
INVX2TS U2699 ( .A(n48), .Y(n51) );
INVX2TS U2700 ( .A(Data_B_i[32]), .Y(n52) );
INVX2TS U2701 ( .A(n52), .Y(n53) );
INVX2TS U2702 ( .A(n52), .Y(n54) );
INVX2TS U2703 ( .A(n52), .Y(n55) );
INVX2TS U2704 ( .A(Data_B_i[33]), .Y(n56) );
INVX2TS U2705 ( .A(n56), .Y(n57) );
INVX2TS U2706 ( .A(n56), .Y(n58) );
INVX2TS U2707 ( .A(n56), .Y(n59) );
INVX2TS U2708 ( .A(Data_B_i[34]), .Y(n60) );
INVX2TS U2709 ( .A(n60), .Y(n61) );
INVX2TS U2710 ( .A(n60), .Y(n62) );
INVX2TS U2711 ( .A(n60), .Y(n63) );
INVX2TS U2712 ( .A(Data_B_i[36]), .Y(n64) );
INVX2TS U2713 ( .A(n64), .Y(n65) );
INVX2TS U2714 ( .A(n64), .Y(n66) );
INVX2TS U2715 ( .A(n64), .Y(n67) );
INVX2TS U2716 ( .A(Data_B_i[37]), .Y(n68) );
INVX2TS U2717 ( .A(n68), .Y(n69) );
INVX2TS U2718 ( .A(n68), .Y(n70) );
INVX2TS U2719 ( .A(n68), .Y(n71) );
INVX2TS U2720 ( .A(Data_B_i[38]), .Y(n72) );
INVX2TS U2721 ( .A(n72), .Y(n73) );
INVX2TS U2722 ( .A(n72), .Y(n74) );
INVX2TS U2723 ( .A(n72), .Y(n75) );
INVX2TS U2724 ( .A(Data_B_i[39]), .Y(n76) );
INVX2TS U2725 ( .A(n76), .Y(n77) );
INVX2TS U2726 ( .A(n76), .Y(n78) );
INVX2TS U2727 ( .A(n76), .Y(n79) );
INVX2TS U2728 ( .A(Data_B_i[40]), .Y(n80) );
INVX2TS U2729 ( .A(n80), .Y(n81) );
INVX2TS U2730 ( .A(n80), .Y(n82) );
INVX2TS U2731 ( .A(n80), .Y(n83) );
INVX2TS U2732 ( .A(Data_B_i[41]), .Y(n84) );
INVX2TS U2733 ( .A(n84), .Y(n85) );
INVX2TS U2734 ( .A(n84), .Y(n86) );
INVX2TS U2735 ( .A(n84), .Y(n87) );
INVX2TS U2736 ( .A(Data_B_i[42]), .Y(n88) );
INVX2TS U2737 ( .A(n88), .Y(n89) );
INVX2TS U2738 ( .A(n88), .Y(n90) );
INVX2TS U2739 ( .A(n88), .Y(n91) );
INVX2TS U2740 ( .A(Data_B_i[43]), .Y(n92) );
INVX2TS U2741 ( .A(n92), .Y(n93) );
INVX2TS U2742 ( .A(n92), .Y(n94) );
INVX2TS U2743 ( .A(n92), .Y(n95) );
INVX2TS U2744 ( .A(Data_B_i[44]), .Y(n96) );
INVX2TS U2745 ( .A(n96), .Y(n97) );
INVX2TS U2746 ( .A(n96), .Y(n98) );
INVX2TS U2747 ( .A(n96), .Y(n99) );
INVX2TS U2748 ( .A(Data_B_i[46]), .Y(n100) );
INVX2TS U2749 ( .A(n100), .Y(n101) );
INVX2TS U2750 ( .A(n100), .Y(n102) );
INVX2TS U2751 ( .A(n100), .Y(n103) );
INVX2TS U2752 ( .A(Data_B_i[47]), .Y(n104) );
INVX2TS U2753 ( .A(n104), .Y(n105) );
INVX2TS U2754 ( .A(n104), .Y(n106) );
INVX2TS U2755 ( .A(n104), .Y(n107) );
INVX2TS U2756 ( .A(Data_B_i[48]), .Y(n108) );
INVX2TS U2757 ( .A(n108), .Y(n110) );
INVX2TS U2758 ( .A(n108), .Y(n111) );
INVX2TS U2759 ( .A(Data_B_i[49]), .Y(n112) );
INVX2TS U2760 ( .A(n112), .Y(n113) );
INVX2TS U2761 ( .A(n112), .Y(n114) );
INVX2TS U2762 ( .A(n112), .Y(n115) );
INVX2TS U2763 ( .A(Data_B_i[50]), .Y(n116) );
INVX2TS U2764 ( .A(n116), .Y(n117) );
INVX2TS U2765 ( .A(n116), .Y(n118) );
INVX2TS U2766 ( .A(n116), .Y(n119) );
INVX2TS U2767 ( .A(Data_B_i[45]), .Y(n120) );
INVX2TS U2768 ( .A(n120), .Y(n121) );
INVX2TS U2769 ( .A(n120), .Y(n122) );
INVX2TS U2770 ( .A(n120), .Y(n123) );
INVX2TS U2771 ( .A(n120), .Y(n124) );
INVX2TS U2772 ( .A(Data_B_i[24]), .Y(n125) );
INVX2TS U2773 ( .A(n125), .Y(n126) );
INVX2TS U2774 ( .A(n125), .Y(n127) );
INVX2TS U2775 ( .A(n125), .Y(n128) );
INVX2TS U2776 ( .A(Data_B_i[12]), .Y(n129) );
INVX2TS U2777 ( .A(n129), .Y(n130) );
INVX2TS U2778 ( .A(n129), .Y(n131) );
INVX2TS U2779 ( .A(n129), .Y(n132) );
INVX2TS U2780 ( .A(Data_B_i[13]), .Y(n133) );
INVX2TS U2781 ( .A(n133), .Y(n135) );
INVX2TS U2782 ( .A(n133), .Y(n136) );
INVX2TS U2783 ( .A(n137), .Y(n138) );
INVX2TS U2784 ( .A(n137), .Y(n139) );
INVX2TS U2785 ( .A(n137), .Y(n140) );
INVX2TS U2786 ( .A(Data_B_i[15]), .Y(n141) );
INVX2TS U2787 ( .A(n141), .Y(n142) );
INVX2TS U2788 ( .A(n141), .Y(n143) );
INVX2TS U2789 ( .A(n141), .Y(n144) );
INVX2TS U2790 ( .A(Data_B_i[16]), .Y(n145) );
INVX2TS U2791 ( .A(n145), .Y(n147) );
INVX2TS U2792 ( .A(n145), .Y(n148) );
INVX2TS U2793 ( .A(Data_B_i[17]), .Y(n149) );
INVX2TS U2794 ( .A(n149), .Y(n150) );
INVX2TS U2795 ( .A(n149), .Y(n151) );
INVX2TS U2796 ( .A(n149), .Y(n152) );
INVX2TS U2797 ( .A(Data_B_i[19]), .Y(n153) );
INVX2TS U2798 ( .A(n153), .Y(n154) );
INVX2TS U2799 ( .A(n153), .Y(n155) );
INVX2TS U2800 ( .A(n153), .Y(n156) );
INVX2TS U2801 ( .A(Data_B_i[20]), .Y(n157) );
INVX2TS U2802 ( .A(n157), .Y(n158) );
INVX2TS U2803 ( .A(n157), .Y(n159) );
INVX2TS U2804 ( .A(n157), .Y(n160) );
INVX2TS U2805 ( .A(Data_B_i[21]), .Y(n161) );
INVX2TS U2806 ( .A(n161), .Y(n162) );
INVX2TS U2807 ( .A(n161), .Y(n163) );
INVX2TS U2808 ( .A(n161), .Y(n164) );
INVX2TS U2809 ( .A(Data_B_i[22]), .Y(n165) );
INVX2TS U2810 ( .A(n165), .Y(n167) );
INVX2TS U2811 ( .A(n165), .Y(n168) );
INVX2TS U2812 ( .A(Data_B_i[23]), .Y(n169) );
INVX2TS U2813 ( .A(n169), .Y(n170) );
INVX2TS U2814 ( .A(n169), .Y(n171) );
INVX2TS U2815 ( .A(n169), .Y(n172) );
INVX2TS U2816 ( .A(Data_B_i[25]), .Y(n173) );
INVX2TS U2817 ( .A(n173), .Y(n174) );
INVX2TS U2818 ( .A(n173), .Y(n175) );
INVX2TS U2819 ( .A(n173), .Y(n176) );
INVX2TS U2820 ( .A(n177), .Y(n178) );
INVX2TS U2821 ( .A(n177), .Y(n179) );
INVX2TS U2822 ( .A(n177), .Y(n180) );
INVX2TS U2823 ( .A(Data_A_i[35]), .Y(n181) );
INVX2TS U2824 ( .A(n181), .Y(n182) );
INVX2TS U2825 ( .A(n181), .Y(n184) );
INVX2TS U2826 ( .A(n185), .Y(n186) );
INVX2TS U2827 ( .A(n185), .Y(n187) );
INVX2TS U2828 ( .A(n185), .Y(n188) );
INVX2TS U2829 ( .A(Data_A_i[41]), .Y(n189) );
INVX2TS U2830 ( .A(n189), .Y(n190) );
INVX2TS U2831 ( .A(n189), .Y(n191) );
INVX2TS U2832 ( .A(n189), .Y(n192) );
INVX2TS U2833 ( .A(n193), .Y(n194) );
INVX2TS U2834 ( .A(n193), .Y(n195) );
INVX2TS U2835 ( .A(n193), .Y(n196) );
CLKBUFX2TS U2836 ( .A(Data_A_i[47]), .Y(n197) );
CLKBUFX2TS U2837 ( .A(Data_A_i[47]), .Y(n198) );
CLKBUFX2TS U2838 ( .A(Data_A_i[47]), .Y(n199) );
INVX2TS U2839 ( .A(Data_A_i[50]), .Y(n200) );
INVX2TS U2840 ( .A(n200), .Y(n201) );
INVX2TS U2841 ( .A(n200), .Y(n202) );
INVX2TS U2842 ( .A(n200), .Y(n203) );
INVX2TS U2843 ( .A(Data_B_i[11]), .Y(n204) );
INVX2TS U2844 ( .A(n204), .Y(n205) );
INVX2TS U2845 ( .A(n204), .Y(n206) );
INVX2TS U2846 ( .A(n204), .Y(n207) );
INVX2TS U2847 ( .A(Data_B_i[10]), .Y(n208) );
INVX2TS U2848 ( .A(n208), .Y(n209) );
INVX2TS U2849 ( .A(n208), .Y(n210) );
INVX2TS U2850 ( .A(n208), .Y(n211) );
INVX2TS U2851 ( .A(Data_B_i[9]), .Y(n212) );
INVX2TS U2852 ( .A(n212), .Y(n213) );
INVX2TS U2853 ( .A(n212), .Y(n214) );
INVX2TS U2854 ( .A(n212), .Y(n215) );
INVX2TS U2855 ( .A(Data_B_i[8]), .Y(n216) );
INVX2TS U2856 ( .A(n216), .Y(n217) );
INVX2TS U2857 ( .A(n216), .Y(n219) );
INVX2TS U2858 ( .A(Data_B_i[7]), .Y(n220) );
INVX2TS U2859 ( .A(n220), .Y(n222) );
INVX2TS U2860 ( .A(n220), .Y(n223) );
INVX2TS U2861 ( .A(Data_B_i[6]), .Y(n224) );
INVX2TS U2862 ( .A(n224), .Y(n225) );
INVX2TS U2863 ( .A(n224), .Y(n226) );
INVX2TS U2864 ( .A(n224), .Y(n227) );
INVX2TS U2865 ( .A(Data_B_i[5]), .Y(n228) );
INVX2TS U2866 ( .A(n228), .Y(n229) );
INVX2TS U2867 ( .A(n228), .Y(n230) );
INVX2TS U2868 ( .A(n228), .Y(n231) );
INVX2TS U2869 ( .A(Data_B_i[4]), .Y(n232) );
INVX2TS U2870 ( .A(n232), .Y(n234) );
INVX2TS U2871 ( .A(n232), .Y(n235) );
INVX2TS U2872 ( .A(n236), .Y(n238) );
INVX2TS U2873 ( .A(Data_B_i[2]), .Y(n240) );
INVX2TS U2874 ( .A(n240), .Y(n241) );
INVX2TS U2875 ( .A(n240), .Y(n242) );
INVX2TS U2876 ( .A(n240), .Y(n243) );
INVX2TS U2877 ( .A(Data_B_i[1]), .Y(n244) );
INVX2TS U2878 ( .A(n244), .Y(n245) );
INVX2TS U2879 ( .A(n244), .Y(n246) );
INVX2TS U2880 ( .A(n244), .Y(n247) );
INVX2TS U2881 ( .A(Data_B_i[18]), .Y(n248) );
INVX2TS U2882 ( .A(n248), .Y(n249) );
INVX2TS U2883 ( .A(n248), .Y(n250) );
INVX2TS U2884 ( .A(n248), .Y(n251) );
INVX2TS U2885 ( .A(n248), .Y(n252) );
INVX2TS U2886 ( .A(n253), .Y(n255) );
INVX2TS U2887 ( .A(n253), .Y(n256) );
INVX2TS U2888 ( .A(Data_A_i[17]), .Y(n257) );
INVX2TS U2889 ( .A(n257), .Y(n258) );
INVX2TS U2890 ( .A(n257), .Y(n259) );
INVX2TS U2891 ( .A(n257), .Y(n260) );
INVX2TS U2892 ( .A(n261), .Y(n263) );
INVX2TS U2893 ( .A(n261), .Y(n264) );
INVX2TS U2894 ( .A(n265), .Y(n266) );
INVX2TS U2895 ( .A(n265), .Y(n267) );
INVX2TS U2896 ( .A(n265), .Y(n268) );
INVX2TS U2897 ( .A(n269), .Y(n270) );
INVX2TS U2898 ( .A(n269), .Y(n271) );
INVX2TS U2899 ( .A(n269), .Y(n272) );
INVX2TS U2900 ( .A(Data_A_i[5]), .Y(n273) );
INVX2TS U2901 ( .A(n273), .Y(n274) );
INVX2TS U2902 ( .A(n273), .Y(n275) );
INVX2TS U2903 ( .A(n277), .Y(n278) );
INVX2TS U2904 ( .A(n277), .Y(n279) );
INVX2TS U2905 ( .A(n277), .Y(n280) );
INVX2TS U2906 ( .A(n277), .Y(n281) );
INVX2TS U2907 ( .A(Data_A_i[2]), .Y(n282) );
INVX2TS U2908 ( .A(n282), .Y(n284) );
INVX2TS U2909 ( .A(n282), .Y(n285) );
INVX2TS U2910 ( .A(Data_A_i[26]), .Y(n286) );
INVX2TS U2911 ( .A(n286), .Y(n287) );
INVX2TS U2912 ( .A(n286), .Y(n288) );
INVX2TS U2913 ( .A(n286), .Y(n289) );
INVX2TS U2914 ( .A(n198), .Y(genblk1_left_mult_x_1_n1138) );
INVX2TS U2915 ( .A(n256), .Y(genblk1_right_mult_x_1_n1253) );
NOR2XLTS U2916 ( .A(n2893), .B(n3879), .Y(n967) );
OAI21XLTS U2917 ( .A0(n2713), .A1(n2764), .B0(n1063), .Y(n1064) );
OAI21XLTS U2918 ( .A0(n2516), .A1(n2684), .B0(n2252), .Y(n2253) );
OAI21XLTS U2919 ( .A0(n2516), .A1(n2409), .B0(n2053), .Y(n2054) );
OAI21XLTS U2920 ( .A0(n2516), .A1(n2515), .B0(n2514), .Y(n2517) );
OAI21XLTS U2921 ( .A0(n2516), .A1(n2464), .B0(n2028), .Y(n2029) );
OAI21XLTS U2922 ( .A0(n2516), .A1(n2524), .B0(n1954), .Y(n1955) );
OAI21XLTS U2923 ( .A0(n2516), .A1(n303), .B0(n2313), .Y(n2314) );
AOI21X1TS U2924 ( .A0(n1133), .A1(n1109), .B0(n1110), .Y(n518) );
XNOR2X2TS U2925 ( .A(n1449), .B(n1448), .Y(genblk1_right_N53) );
NOR2XLTS U2926 ( .A(n3868), .B(n2879), .Y(n2873) );
CMPR42X2TS U2927 ( .A(genblk1_middle_mult_x_1_n1374), .B(
genblk1_middle_mult_x_1_n1430), .C(genblk1_middle_mult_x_1_n1402), .D(
genblk1_middle_mult_x_1_n686), .ICI(genblk1_middle_mult_x_1_n679), .S(
genblk1_middle_mult_x_1_n676), .ICO(genblk1_middle_mult_x_1_n674),
.CO(genblk1_middle_mult_x_1_n675) );
CLKBUFX2TS U2928 ( .A(n2415), .Y(n2738) );
INVX2TS U2929 ( .A(n2740), .Y(n292) );
NAND2X1TS U2930 ( .A(Data_A_i[34]), .B(Data_A_i[7]), .Y(n1027) );
AOI222XLTS U2931 ( .A0(n4867), .A1(n47), .B0(n4880), .B1(n4878), .C0(n4879),
.C1(n422), .Y(n655) );
CLKBUFX2TS U2932 ( .A(n4867), .Y(n4881) );
OAI21XLTS U2933 ( .A0(n297), .A1(n3171), .B0(n3170), .Y(n3176) );
OAI21XLTS U2934 ( .A0(n296), .A1(n3196), .B0(n3197), .Y(n3193) );
OAI21XLTS U2935 ( .A0(n296), .A1(n3151), .B0(n3150), .Y(n3156) );
OAI21XLTS U2936 ( .A0(n297), .A1(n3138), .B0(n3137), .Y(n3143) );
INVX2TS U2937 ( .A(n1659), .Y(n2785) );
INVX2TS U2938 ( .A(n1100), .Y(n1659) );
INVX2TS U2939 ( .A(n3265), .Y(n298) );
INVX2TS U2940 ( .A(n3265), .Y(n299) );
INVX2TS U2941 ( .A(n2540), .Y(n300) );
INVX2TS U2942 ( .A(n2540), .Y(n301) );
AOI222XLTS U2943 ( .A0(n2484), .A1(n2543), .B0(n2483), .B1(n2541), .C0(n2504), .C1(n301), .Y(n2485) );
AOI222XLTS U2944 ( .A0(n2680), .A1(n2543), .B0(n2522), .B1(n2541), .C0(n2521), .C1(n300), .Y(n2514) );
AOI222XLTS U2945 ( .A0(n2796), .A1(n2543), .B0(n2795), .B1(n2351), .C0(n2383), .C1(n301), .Y(n2284) );
AOI222XLTS U2946 ( .A0(n2641), .A1(n2592), .B0(n2520), .B1(n2591), .C0(n2493), .C1(n301), .Y(n2494) );
INVX2TS U2947 ( .A(n2148), .Y(n2783) );
INVX2TS U2948 ( .A(n2783), .Y(n302) );
INVX2TS U2949 ( .A(n2783), .Y(n303) );
INVX2TS U2950 ( .A(n2682), .Y(n304) );
INVX2TS U2951 ( .A(n3705), .Y(n3735) );
INVX2TS U2952 ( .A(n3735), .Y(n306) );
INVX2TS U2953 ( .A(n3735), .Y(n307) );
INVX2TS U2954 ( .A(n2391), .Y(n2658) );
INVX2TS U2955 ( .A(n2658), .Y(n309) );
INVX2TS U2956 ( .A(n429), .Y(n310) );
INVX2TS U2957 ( .A(n429), .Y(n311) );
NAND2X1TS U2958 ( .A(n2352), .B(n2691), .Y(n312) );
XNOR2X1TS U2959 ( .A(n728), .B(n727), .Y(n313) );
XNOR2X1TS U2960 ( .A(n836), .B(n891), .Y(n314) );
OR2X1TS U2961 ( .A(n1293), .B(n1292), .Y(n315) );
NAND2X1TS U2962 ( .A(n2564), .B(n2804), .Y(n316) );
OR2X1TS U2963 ( .A(n4548), .B(Data_B_i[29]), .Y(n317) );
OR2X1TS U2964 ( .A(n834), .B(n422), .Y(n318) );
XNOR2X1TS U2965 ( .A(n4032), .B(n4031), .Y(n320) );
XNOR2X1TS U2966 ( .A(n867), .B(n866), .Y(n321) );
XNOR2X1TS U2967 ( .A(n3243), .B(n854), .Y(n322) );
XNOR2X1TS U2968 ( .A(n4147), .B(n4146), .Y(n323) );
XNOR2X1TS U2969 ( .A(n297), .B(n3199), .Y(n324) );
XOR2X1TS U2970 ( .A(n3143), .B(n3142), .Y(n325) );
XNOR2X1TS U2971 ( .A(n4100), .B(n4099), .Y(n326) );
XOR2X1TS U2972 ( .A(n521), .B(n520), .Y(n327) );
XNOR2X1TS U2973 ( .A(n4196), .B(n4195), .Y(n328) );
NAND2X1TS U2974 ( .A(n2407), .B(n2804), .Y(n329) );
AOI22X1TS U2975 ( .A0(n2407), .A1(n2808), .B0(n2769), .B1(n2691), .Y(n330)
);
XNOR2X1TS U2976 ( .A(n648), .B(n647), .Y(n333) );
INVX2TS U2977 ( .A(n584), .Y(n592) );
OR2X1TS U2978 ( .A(n2758), .B(n2808), .Y(n335) );
XOR2X1TS U2979 ( .A(n3156), .B(n3155), .Y(n336) );
XOR2X1TS U2980 ( .A(n3248), .B(n3247), .Y(n337) );
AOI22X1TS U2981 ( .A0(n2503), .A1(n2691), .B0(n2498), .B1(n2645), .Y(n339)
);
XOR2X1TS U2982 ( .A(n3132), .B(n3131), .Y(n340) );
AOI22X1TS U2983 ( .A0(n2592), .A1(n2808), .B0(n2351), .B1(n2806), .Y(n341)
);
XNOR2X1TS U2984 ( .A(n678), .B(n677), .Y(n342) );
OR2X1TS U2985 ( .A(n2771), .B(n2681), .Y(n344) );
XNOR2X1TS U2986 ( .A(n1077), .B(n1076), .Y(n345) );
OR2X1TS U2987 ( .A(n2642), .B(n1078), .Y(n346) );
INVX2TS U2988 ( .A(n1354), .Y(n2654) );
NAND2X1TS U2989 ( .A(n2643), .B(n2804), .Y(n347) );
OR2X1TS U2990 ( .A(Data_A_i[27]), .B(Data_A_i[0]), .Y(n348) );
NAND2X1TS U2991 ( .A(n348), .B(n570), .Y(n566) );
NAND2X1TS U2992 ( .A(n1949), .B(n2804), .Y(n349) );
OR2X1TS U2993 ( .A(n245), .B(n241), .Y(n350) );
OR2X1TS U2994 ( .A(n241), .B(n237), .Y(n351) );
XNOR2X1TS U2995 ( .A(n917), .B(n916), .Y(n352) );
OR2X1TS U2996 ( .A(genblk1_right_mult_x_1_n888), .B(n953), .Y(n353) );
XOR2X1TS U2997 ( .A(n3232), .B(n3231), .Y(n354) );
CLKBUFX2TS U2998 ( .A(n4506), .Y(n4541) );
OR2X1TS U2999 ( .A(n1278), .B(n1277), .Y(n355) );
OR2X1TS U3000 ( .A(n249), .B(n121), .Y(n358) );
INVX2TS U3001 ( .A(Data_A_i[29]), .Y(n607) );
INVX2TS U3002 ( .A(n607), .Y(n371) );
OR2X1TS U3003 ( .A(genblk1_right_mult_x_1_n731), .B(
genblk1_right_mult_x_1_n743), .Y(n360) );
OR2X1TS U3004 ( .A(genblk1_right_mult_x_1_n744), .B(
genblk1_right_mult_x_1_n756), .Y(n361) );
OR2X1TS U3005 ( .A(genblk1_right_mult_x_1_n604), .B(
genblk1_right_mult_x_1_n613), .Y(n364) );
OR2X1TS U3006 ( .A(n1653), .B(n1652), .Y(n366) );
INVX2TS U3007 ( .A(n2681), .Y(n2102) );
XNOR2X1TS U3008 ( .A(n821), .B(n40), .Y(n367) );
CLKBUFX2TS U3009 ( .A(n4886), .Y(n4905) );
NAND2X1TS U3010 ( .A(n2439), .B(n2804), .Y(n368) );
NAND2X1TS U3011 ( .A(n1067), .B(n2691), .Y(n369) );
CLKBUFX2TS U3012 ( .A(n1950), .Y(n2405) );
OR2X1TS U3013 ( .A(genblk1_left_mult_x_1_n520), .B(
genblk1_left_mult_x_1_n525), .Y(n370) );
NAND2X1TS U3014 ( .A(n592), .B(n594), .Y(n597) );
INVX2TS U3015 ( .A(n1534), .Y(n1510) );
NAND2X1TS U3016 ( .A(Data_A_i[40]), .B(Data_A_i[13]), .Y(n1048) );
INVX2TS U3017 ( .A(n1122), .Y(n1090) );
INVX2TS U3018 ( .A(n3202), .Y(n2960) );
INVX2TS U3019 ( .A(n3229), .Y(n3215) );
INVX2TS U3020 ( .A(n1551), .Y(n1531) );
NAND2X1TS U3021 ( .A(n602), .B(n601), .Y(n603) );
NAND2X1TS U3022 ( .A(n1202), .B(n1027), .Y(n1199) );
NAND2X1TS U3023 ( .A(n254), .B(n201), .Y(n400) );
INVX2TS U3024 ( .A(n4135), .Y(n4138) );
NOR2XLTS U3025 ( .A(n913), .B(n883), .Y(n850) );
INVX2TS U3026 ( .A(n3196), .Y(n3198) );
INVX2TS U3027 ( .A(n3213), .Y(n3230) );
OAI21XLTS U3028 ( .A0(n480), .A1(n403), .B0(n402), .Y(n404) );
NOR2X2TS U3029 ( .A(n512), .B(n514), .Y(n1109) );
INVX2TS U3030 ( .A(n1566), .Y(n1538) );
INVX2TS U3031 ( .A(n1163), .Y(n1509) );
INVX2TS U3032 ( .A(n2116), .Y(n2120) );
INVX2TS U3033 ( .A(n1346), .Y(n1203) );
NAND2X1TS U3034 ( .A(n396), .B(n400), .Y(n397) );
INVX2TS U3035 ( .A(n4069), .Y(n4071) );
CLKBUFX2TS U3036 ( .A(n4753), .Y(n4740) );
CLKBUFX2TS U3037 ( .A(n4702), .Y(n4684) );
INVX2TS U3038 ( .A(n4126), .Y(n4128) );
NAND2X1TS U3039 ( .A(n3236), .B(n1404), .Y(n3228) );
NOR2XLTS U3040 ( .A(n3122), .B(n3139), .Y(n3125) );
INVX2TS U3041 ( .A(n3179), .Y(n3182) );
INVX2TS U3042 ( .A(n3240), .Y(n2978) );
INVX2TS U3043 ( .A(n883), .Y(n885) );
NOR2XLTS U3044 ( .A(n1096), .B(n286), .Y(n1097) );
NAND2X1TS U3045 ( .A(n258), .B(Data_A_i[44]), .Y(n532) );
OAI21X1TS U3046 ( .A0(n2765), .A1(n424), .B0(n432), .Y(n433) );
INVX2TS U3047 ( .A(n1802), .Y(n1804) );
AOI222XLTS U3048 ( .A0(n2703), .A1(n2670), .B0(n2550), .B1(n2108), .C0(n2549), .C1(n2642), .Y(n1056) );
INVX2TS U3049 ( .A(n1971), .Y(n1973) );
INVX2TS U3050 ( .A(n502), .Y(n1073) );
INVX2TS U3051 ( .A(n4028), .Y(n4030) );
OAI21XLTS U3052 ( .A0(n4936), .A1(n4597), .B0(n4453), .Y(n4454) );
OAI21XLTS U3053 ( .A0(n23), .A1(n4597), .B0(n4460), .Y(n4461) );
CLKBUFX2TS U3054 ( .A(n4452), .Y(n4597) );
OAI21XLTS U3055 ( .A0(n23), .A1(n4648), .B0(n4483), .Y(n4484) );
CLKBUFX2TS U3056 ( .A(n4599), .Y(n4648) );
CLKBUFX2TS U3057 ( .A(n4518), .Y(n4704) );
CLKBUFX2TS U3058 ( .A(n4706), .Y(n4759) );
OAI21XLTS U3059 ( .A0(n21), .A1(n4766), .B0(n4281), .Y(n4282) );
NAND2X1TS U3060 ( .A(n3179), .B(n1414), .Y(n3160) );
INVX2TS U3061 ( .A(n3116), .Y(n3102) );
CLKBUFX2TS U3062 ( .A(n3805), .Y(n3421) );
CLKBUFX2TS U3063 ( .A(n2983), .Y(n3263) );
OAI21XLTS U3064 ( .A0(n3708), .A1(n3791), .B0(n3357), .Y(n3358) );
OAI21XLTS U3065 ( .A0(n3655), .A1(n3263), .B0(n3254), .Y(n3255) );
OAI21XLTS U3066 ( .A0(n3708), .A1(n3416), .B0(n3415), .Y(n3417) );
OAI21XLTS U3067 ( .A0(n3719), .A1(n3379), .B0(n3367), .Y(n3368) );
OAI21XLTS U3068 ( .A0(n3600), .A1(n3305), .B0(n3032), .Y(n3033) );
OAI21XLTS U3069 ( .A0(n314), .A1(n3305), .B0(n3034), .Y(n3035) );
CLKBUFX2TS U3070 ( .A(n3047), .Y(n3791) );
CLKBUFX2TS U3071 ( .A(n3383), .Y(n3807) );
OAI21XLTS U3072 ( .A0(n314), .A1(n3416), .B0(n3052), .Y(n3053) );
XOR2X1TS U3073 ( .A(n3223), .B(n3222), .Y(n3756) );
OAI21XLTS U3074 ( .A0(n3243), .A1(n2989), .B0(n2988), .Y(n2994) );
CLKBUFX2TS U3075 ( .A(n3659), .Y(n3639) );
NOR2X1TS U3076 ( .A(n474), .B(n467), .Y(n393) );
CLKBUFX2TS U3077 ( .A(n2355), .Y(n2401) );
CLKBUFX2TS U3078 ( .A(n2223), .Y(n2457) );
OAI21XLTS U3079 ( .A0(n2495), .A1(n2393), .B0(n2331), .Y(n2332) );
OAI21XLTS U3080 ( .A0(n2665), .A1(n2664), .B0(n2663), .Y(n2667) );
NAND2X1TS U3081 ( .A(n1178), .B(n1187), .Y(n1179) );
OAI21XLTS U3082 ( .A0(n2752), .A1(n2664), .B0(n2183), .Y(n2184) );
AOI222XLTS U3083 ( .A0(n2407), .A1(n2795), .B0(n2792), .B1(n2532), .C0(n2793), .C1(n2401), .Y(n2130) );
OAI21XLTS U3084 ( .A0(n2765), .A1(n2764), .B0(n2763), .Y(n2767) );
CLKBUFX2TS U3085 ( .A(n1980), .Y(n2506) );
OAI21XLTS U3086 ( .A0(n19), .A1(n2742), .B0(n1003), .Y(n1004) );
OAI21XLTS U3087 ( .A0(n20), .A1(n2742), .B0(n2675), .Y(n2676) );
OAI21XLTS U3088 ( .A0(n2648), .A1(n2810), .B0(n2647), .Y(n2649) );
CLKBUFX2TS U3089 ( .A(n1980), .Y(n2705) );
OAI21XLTS U3090 ( .A0(n2764), .A1(n2705), .B0(n2696), .Y(n2697) );
OAI21XLTS U3091 ( .A0(n2491), .A1(n2732), .B0(n1373), .Y(n1374) );
AOI222XLTS U3092 ( .A0(n2730), .A1(n2729), .B0(n2728), .B1(n2727), .C0(n2726), .C1(n2691), .Y(n2731) );
NAND2BX1TS U3093 ( .AN(n1237), .B(n1238), .Y(n2025) );
NAND2X1TS U3094 ( .A(n4152), .B(n617), .Y(n4133) );
INVX2TS U3095 ( .A(n4026), .Y(n4205) );
OAI21XLTS U3096 ( .A0(n4963), .A1(n4569), .B0(n4277), .Y(n4278) );
OAI21XLTS U3097 ( .A0(n333), .A1(n4668), .B0(n4661), .Y(n4662) );
OAI21XLTS U3098 ( .A0(n22), .A1(n4668), .B0(n4665), .Y(n4666) );
OAI21XLTS U3099 ( .A0(n367), .A1(n4780), .B0(n4769), .Y(n4770) );
OAI21XLTS U3100 ( .A0(n4951), .A1(n4818), .B0(n4821), .Y(n4822) );
OAI21XLTS U3101 ( .A0(n4911), .A1(n4766), .B0(n4727), .Y(n4728) );
OAI21XLTS U3102 ( .A0(n326), .A1(n4704), .B0(n4685), .Y(n4686) );
OAI21XLTS U3103 ( .A0(n323), .A1(n4538), .B0(n4792), .Y(n4793) );
OAI21XLTS U3104 ( .A0(n24), .A1(n4883), .B0(n4842), .Y(n4843) );
OAI21XLTS U3105 ( .A0(n18), .A1(n4816), .B0(n4800), .Y(n4801) );
OAI21XLTS U3106 ( .A0(n4917), .A1(n4922), .B0(n4916), .Y(n4918) );
OAI21XLTS U3107 ( .A0(n326), .A1(n4886), .B0(n4926), .Y(n4927) );
OAI21XLTS U3108 ( .A0(n342), .A1(n4816), .B0(n4287), .Y(n4288) );
XOR2X1TS U3109 ( .A(n4130), .B(n4129), .Y(n4936) );
OAI21XLTS U3110 ( .A0(n4551), .A1(n4883), .B0(n660), .Y(n661) );
INVX2TS U3111 ( .A(n3112), .Y(n3115) );
OAI21XLTS U3112 ( .A0(n3695), .A1(n3269), .B0(n3194), .Y(n3195) );
OAI21XLTS U3113 ( .A0(n336), .A1(n3345), .B0(n3341), .Y(n3342) );
OAI21XLTS U3114 ( .A0(n3689), .A1(n3791), .B0(n3347), .Y(n3348) );
OAI21XLTS U3115 ( .A0(n26), .A1(n3563), .B0(n3548), .Y(n3549) );
OAI21XLTS U3116 ( .A0(n3692), .A1(n3765), .B0(n3459), .Y(n3460) );
OAI21XLTS U3117 ( .A0(n3701), .A1(n3765), .B0(n3465), .Y(n3466) );
OAI21XLTS U3118 ( .A0(n324), .A1(n3522), .B0(n3517), .Y(n3518) );
OAI21XLTS U3119 ( .A0(n340), .A1(n3685), .B0(n3678), .Y(n3679) );
OAI21XLTS U3120 ( .A0(n336), .A1(n3685), .B0(n3682), .Y(n3683) );
OAI21XLTS U3121 ( .A0(n3756), .A1(n3775), .B0(n3755), .Y(n3757) );
OAI21XLTS U3122 ( .A0(n337), .A1(n3775), .B0(n3582), .Y(n3583) );
OAI21XLTS U3123 ( .A0(n3719), .A1(n3775), .B0(n3586), .Y(n3587) );
XOR2X1TS U3124 ( .A(n2982), .B(n2981), .Y(n3715) );
XOR2X1TS U3125 ( .A(n887), .B(n886), .Y(n3655) );
AND3X1TS U3126 ( .A(n857), .B(n856), .C(n855), .Y(n3703) );
OAI21XLTS U3127 ( .A0(n2486), .A1(n303), .B0(n2333), .Y(n2334) );
OAI21XLTS U3128 ( .A0(n2525), .A1(n302), .B0(n2346), .Y(n2347) );
OAI21XLTS U3129 ( .A0(n2547), .A1(n2393), .B0(n2311), .Y(n2312) );
OAI21XLTS U3130 ( .A0(n2685), .A1(n2464), .B0(n2140), .Y(n2141) );
INVX2TS U3131 ( .A(n2654), .Y(n2193) );
OAI21XLTS U3132 ( .A0(n2403), .A1(n2328), .B0(n2021), .Y(n2022) );
INVX2TS U3133 ( .A(n1659), .Y(n2766) );
OAI21XLTS U3134 ( .A0(n2477), .A1(n2445), .B0(n2004), .Y(n2005) );
OAI21XLTS U3135 ( .A0(n2648), .A1(n2732), .B0(n1923), .Y(n1924) );
OAI21XLTS U3136 ( .A0(n2495), .A1(n2409), .B0(n2057), .Y(n2058) );
OAI21XLTS U3137 ( .A0(n327), .A1(n2705), .B0(n1753), .Y(n1755) );
OAI21XLTS U3138 ( .A0(n345), .A1(n2705), .B0(n1768), .Y(n1769) );
OAI21XLTS U3139 ( .A0(n2575), .A1(n2571), .B0(n2560), .Y(n2561) );
OAI21XLTS U3140 ( .A0(n2764), .A1(n2566), .B0(n2174), .Y(n2175) );
OAI21XLTS U3141 ( .A0(n20), .A1(n2723), .B0(n2722), .Y(n2725) );
CLKBUFX2TS U3142 ( .A(n1257), .Y(n2409) );
CLKBUFX2TS U3143 ( .A(n2227), .Y(n2758) );
INVX2TS U3144 ( .A(n4442), .Y(n4443) );
OAI21XLTS U3145 ( .A0(n24), .A1(n4922), .B0(n4914), .Y(n4915) );
OAI21XLTS U3146 ( .A0(n323), .A1(n4971), .B0(n4970), .Y(n4972) );
OAI21XLTS U3147 ( .A0(n4936), .A1(n4886), .B0(n4935), .Y(n4937) );
OAI21XLTS U3148 ( .A0(n342), .A1(n4886), .B0(n682), .Y(n683) );
OAI21XLTS U3149 ( .A0(n4551), .A1(n4922), .B0(n711), .Y(n712) );
OAI21XLTS U3150 ( .A0(n296), .A1(n3104), .B0(n3103), .Y(n3109) );
OAI21XLTS U3151 ( .A0(n3686), .A1(n3166), .B0(n3165), .Y(n3167) );
OAI21XLTS U3152 ( .A0(n3692), .A1(n3305), .B0(n3295), .Y(n3296) );
OAI21XLTS U3153 ( .A0(n3695), .A1(n3707), .B0(n3694), .Y(n3696) );
OAI21XLTS U3154 ( .A0(n337), .A1(n3737), .B0(n3712), .Y(n3713) );
OAI21XLTS U3155 ( .A0(n3655), .A1(n3737), .B0(n888), .Y(n889) );
XOR2X1TS U3156 ( .A(n895), .B(n894), .Y(n3600) );
OAI21XLTS U3157 ( .A0(n2403), .A1(n2765), .B0(n2374), .Y(n2375) );
OAI21XLTS U3158 ( .A0(n2752), .A1(n2723), .B0(n2557), .Y(n2558) );
OAI21XLTS U3159 ( .A0(n2784), .A1(n2594), .B0(n2580), .Y(n2581) );
CLKBUFX2TS U3160 ( .A(n1257), .Y(n2768) );
AOI21X1TS U3161 ( .A0(n663), .A1(n623), .B0(n622), .Y(n4066) );
CMPR42X1TS U3162 ( .A(genblk1_left_mult_x_1_n1258), .B(
genblk1_left_mult_x_1_n1180), .C(genblk1_left_mult_x_1_n618), .D(
genblk1_left_mult_x_1_n1232), .ICI(genblk1_left_mult_x_1_n625), .S(
genblk1_left_mult_x_1_n613), .ICO(genblk1_left_mult_x_1_n611), .CO(
genblk1_left_mult_x_1_n612) );
NOR2XLTS U3163 ( .A(n4356), .B(n4354), .Y(n778) );
OAI21XLTS U3164 ( .A0(n26), .A1(n3345), .B0(n2949), .Y(n2950) );
CLKBUFX2TS U3165 ( .A(n3271), .Y(n3291) );
CMPR42X1TS U3166 ( .A(genblk1_right_mult_x_1_n1291), .B(
genblk1_right_mult_x_1_n1345), .C(genblk1_right_mult_x_1_n1318), .D(
genblk1_right_mult_x_1_n591), .ICI(genblk1_right_mult_x_1_n600), .S(
genblk1_right_mult_x_1_n589), .ICO(genblk1_right_mult_x_1_n587), .CO(
genblk1_right_mult_x_1_n588) );
CMPR42X1TS U3167 ( .A(genblk1_right_mult_x_1_n1438), .B(
genblk1_right_mult_x_1_n1411), .C(genblk1_right_mult_x_1_n738), .D(
genblk1_right_mult_x_1_n735), .ICI(genblk1_right_mult_x_1_n728), .S(
genblk1_right_mult_x_1_n722), .ICO(genblk1_right_mult_x_1_n720), .CO(
genblk1_right_mult_x_1_n721) );
CMPR42X1TS U3168 ( .A(genblk1_middle_mult_x_1_n1323), .B(
genblk1_middle_mult_x_1_n1379), .C(genblk1_middle_mult_x_1_n1407), .D(
genblk1_middle_mult_x_1_n733), .ICI(genblk1_middle_mult_x_1_n738), .S(
genblk1_middle_mult_x_1_n731), .ICO(genblk1_middle_mult_x_1_n729),
.CO(genblk1_middle_mult_x_1_n730) );
NOR2X1TS U3169 ( .A(genblk1_middle_mult_x_1_n673), .B(
genblk1_middle_mult_x_1_n681), .Y(n2265) );
OAI21XLTS U3170 ( .A0(n4380), .A1(n4377), .B0(n4381), .Y(n770) );
NOR2XLTS U3171 ( .A(n4392), .B(n4390), .Y(n766) );
OAI21XLTS U3172 ( .A0(n26), .A1(n3166), .B0(n1427), .Y(n1428) );
CMPR42X1TS U3173 ( .A(genblk1_right_mult_x_1_n640), .B(
genblk1_right_mult_x_1_n630), .C(genblk1_right_mult_x_1_n637), .D(
genblk1_right_mult_x_1_n627), .ICI(genblk1_right_mult_x_1_n633), .S(
genblk1_right_mult_x_1_n624), .ICO(genblk1_right_mult_x_1_n622), .CO(
genblk1_right_mult_x_1_n623) );
CMPR42X1TS U3174 ( .A(genblk1_right_mult_x_1_n1395), .B(
genblk1_right_mult_x_1_n1476), .C(genblk1_right_mult_x_1_n847), .D(
genblk1_right_mult_x_1_n851), .ICI(genblk1_right_mult_x_1_n844), .S(
genblk1_right_mult_x_1_n841), .ICO(genblk1_right_mult_x_1_n839), .CO(
genblk1_right_mult_x_1_n840) );
CLKBUFX2TS U3175 ( .A(n3079), .Y(n3057) );
OR2X1TS U3176 ( .A(genblk1_left_mult_x_1_n533), .B(
genblk1_left_mult_x_1_n526), .Y(n4317) );
INVX2TS U3177 ( .A(n4348), .Y(n4350) );
AOI21X1TS U3178 ( .A0(n771), .A1(n3984), .B0(n770), .Y(n4001) );
OR2X1TS U3179 ( .A(n740), .B(n739), .Y(n4414) );
OR2X1TS U3180 ( .A(genblk1_right_mult_x_1_n595), .B(
genblk1_right_mult_x_1_n603), .Y(n3848) );
OR2X1TS U3181 ( .A(n944), .B(n943), .Y(n2929) );
INVX2TS U3182 ( .A(n1493), .Y(n1496) );
INVX2TS U3183 ( .A(n1685), .Y(n2277) );
NOR2XLTS U3184 ( .A(n1281), .B(n1280), .Y(n2629) );
OR2X1TS U3185 ( .A(n1265), .B(n1264), .Y(n1747) );
OAI21XLTS U3186 ( .A0(n4355), .A1(n4354), .B0(n4353), .Y(n4360) );
OAI21XLTS U3187 ( .A0(n4379), .A1(n4378), .B0(n4377), .Y(n4384) );
XNOR2X1TS U3188 ( .A(genblk1_right_mult_x_1_n524), .B(
genblk1_right_mult_x_1_n527), .Y(n999) );
OAI21XLTS U3189 ( .A0(n3887), .A1(n2883), .B0(n2882), .Y(n3874) );
OAI21XLTS U3190 ( .A0(n3901), .A1(n3897), .B0(n3898), .Y(n2905) );
OAI21XLTS U3191 ( .A0(n3941), .A1(n3938), .B0(n3939), .Y(n2934) );
OAI2BB1X2TS U3192 ( .A0N(n1673), .A1N(n1675), .B0(n1672), .Y(n1626) );
OAI21XLTS U3193 ( .A0(n2613), .A1(n2609), .B0(n2610), .Y(n1726) );
CLKBUFX2TS U3194 ( .A(n2082), .Y(n2594) );
INVX2TS U3195 ( .A(n1048), .Y(n382) );
XNOR2X4TS U3196 ( .A(n426), .B(n2666), .Y(n559) );
INVX2TS U3197 ( .A(n436), .Y(n420) );
INVX2TS U3198 ( .A(n4506), .Y(n422) );
XOR2X1TS U3199 ( .A(n421), .B(n435), .Y(n2727) );
INVX2TS U3200 ( .A(n424), .Y(n2804) );
INVX2TS U3201 ( .A(n558), .Y(n428) );
NAND2X1TS U3202 ( .A(n559), .B(n428), .Y(n429) );
INVX2TS U3203 ( .A(n424), .Y(n2691) );
NOR2X2TS U3204 ( .A(n560), .B(n559), .Y(n1820) );
BUFX3TS U3205 ( .A(n1820), .Y(n2458) );
CLKBUFX2TS U3206 ( .A(n2727), .Y(n2645) );
AOI22X1TS U3207 ( .A0(n2760), .A1(n2691), .B0(n2458), .B1(n2645), .Y(n430)
);
NAND2X1TS U3208 ( .A(n1820), .B(n2804), .Y(n432) );
XOR2X1TS U3209 ( .A(n433), .B(n2766), .Y(n2745) );
INVX2TS U3210 ( .A(n443), .Y(n448) );
INVX2TS U3211 ( .A(n447), .Y(n438) );
AOI21X4TS U3212 ( .A0(n29), .A1(n438), .B0(n437), .Y(n455) );
INVX2TS U3213 ( .A(n456), .Y(n440) );
XOR2X1TS U3214 ( .A(n450), .B(n449), .Y(n2227) );
NOR2X1TS U3215 ( .A(n1023), .B(n2758), .Y(n1018) );
NAND2X1TS U3216 ( .A(n2758), .B(n2808), .Y(n555) );
NAND2X1TS U3217 ( .A(n555), .B(n556), .Y(n1005) );
NAND2X1TS U3218 ( .A(n1078), .B(n1023), .Y(n1007) );
NAND2X1TS U3219 ( .A(n1023), .B(n2758), .Y(n1019) );
NAND2X1TS U3220 ( .A(n1007), .B(n1019), .Y(n451) );
AOI21X1TS U3221 ( .A0(n452), .A1(n1005), .B0(n451), .Y(n502) );
AOI21X4TS U3222 ( .A0(n459), .A1(n458), .B0(n457), .Y(n1088) );
XNOR2X4TS U3223 ( .A(n1133), .B(n461), .Y(n2146) );
BUFX3TS U3224 ( .A(n2146), .Y(n2642) );
NAND2X1TS U3225 ( .A(n2642), .B(n1078), .Y(n498) );
NAND2X1TS U3226 ( .A(n346), .B(n498), .Y(n462) );
XOR2X2TS U3227 ( .A(n2666), .B(n488), .Y(n490) );
NOR2X1TS U3228 ( .A(n491), .B(n490), .Y(n2643) );
CLKBUFX2TS U3229 ( .A(n2643), .Y(n2348) );
CLKBUFX2TS U3230 ( .A(n2146), .Y(n2419) );
XNOR2X1TS U3231 ( .A(n489), .B(n488), .Y(n492) );
CLKBUFX2TS U3232 ( .A(n1078), .Y(n2719) );
CLKBUFX2TS U3233 ( .A(n1023), .Y(n2790) );
AOI222X1TS U3234 ( .A0(n2348), .A1(n2419), .B0(n295), .B1(n2719), .C0(n308),
.C1(n2790), .Y(n493) );
OAI21X1TS U3235 ( .A0(n20), .A1(n2664), .B0(n493), .Y(n494) );
XOR2X1TS U3236 ( .A(n494), .B(n2214), .Y(n1339) );
OR2X2TS U3237 ( .A(n2791), .B(n2642), .Y(n1075) );
NAND2X1TS U3238 ( .A(n1075), .B(n346), .Y(n501) );
INVX2TS U3239 ( .A(n498), .Y(n1072) );
NAND2X1TS U3240 ( .A(n2791), .B(n2642), .Y(n1074) );
OAI21X1TS U3241 ( .A0(n502), .A1(n501), .B0(n500), .Y(n1107) );
INVX2TS U3242 ( .A(n514), .Y(n509) );
XOR2X1TS U3243 ( .A(n511), .B(n510), .Y(n1286) );
NOR2X1TS U3244 ( .A(n1286), .B(n2108), .Y(n1102) );
NAND2X1TS U3245 ( .A(n1286), .B(n2108), .Y(n1103) );
OAI21X1TS U3246 ( .A0(n1002), .A1(n1102), .B0(n1103), .Y(n521) );
XOR2X1TS U3247 ( .A(n518), .B(n517), .Y(n1916) );
NAND2X1TS U3248 ( .A(n1286), .B(n1916), .Y(n1104) );
NAND2X1TS U3249 ( .A(n519), .B(n1104), .Y(n520) );
XOR2X1TS U3250 ( .A(n535), .B(n534), .Y(n2343) );
XNOR2X1TS U3251 ( .A(n2343), .B(n548), .Y(n551) );
XOR2X1TS U3252 ( .A(n549), .B(n547), .Y(n552) );
NOR2X1TS U3253 ( .A(n552), .B(n551), .Y(n1067) );
CLKBUFX2TS U3254 ( .A(n1916), .Y(n2747) );
XNOR2X1TS U3255 ( .A(n549), .B(n548), .Y(n550) );
NOR2BX2TS U3256 ( .AN(n551), .B(n550), .Y(n2415) );
CLKBUFX2TS U3257 ( .A(n1286), .Y(n2670) );
CLKBUFX2TS U3258 ( .A(n2791), .Y(n2669) );
AOI222X1TS U3259 ( .A0(n2416), .A1(n2747), .B0(n2674), .B1(n2670), .C0(n304),
.C1(n2739), .Y(n553) );
XOR2X1TS U3260 ( .A(n554), .B(n2686), .Y(n1456) );
NAND2X1TS U3261 ( .A(n335), .B(n555), .Y(n557) );
XNOR2X1TS U3262 ( .A(n557), .B(n556), .Y(n2732) );
CLKBUFX2TS U3263 ( .A(n2227), .Y(n2729) );
INVX2TS U3264 ( .A(n424), .Y(n2806) );
XOR2X1TS U3265 ( .A(n562), .B(n2766), .Y(n1455) );
XOR2X1TS U3266 ( .A(result_A_adder_2_), .B(n1241), .Y(n1243) );
NOR2X1TS U3267 ( .A(n1243), .B(n566), .Y(n2543) );
CLKBUFX2TS U3268 ( .A(n2543), .Y(n2352) );
INVX2TS U3269 ( .A(n2343), .Y(n572) );
XOR2X1TS U3270 ( .A(n583), .B(n582), .Y(n1058) );
XNOR2X1TS U3271 ( .A(n1058), .B(n1754), .Y(n1060) );
XOR2X1TS U3272 ( .A(n604), .B(n603), .Y(n1059) );
XOR2X1TS U3273 ( .A(n2343), .B(n1059), .Y(n1062) );
NOR2X1TS U3274 ( .A(n1062), .B(n1060), .Y(n1949) );
OAI21X1TS U3275 ( .A0(n2713), .A1(n423), .B0(n349), .Y(n605) );
XOR2X1TS U3276 ( .A(n605), .B(n2714), .Y(n606) );
CLKBUFX2TS U3277 ( .A(n4958), .Y(n4971) );
INVX2TS U3278 ( .A(n4541), .Y(n4549) );
NAND2X1TS U3279 ( .A(n4978), .B(n4549), .Y(n608) );
BUFX3TS U3280 ( .A(n419), .Y(n4548) );
INVX2TS U3281 ( .A(n702), .Y(n610) );
NAND2X1TS U3282 ( .A(n46), .B(n49), .Y(n704) );
NAND2X1TS U3283 ( .A(n4548), .B(n47), .Y(n703) );
NAND2X1TS U3284 ( .A(n704), .B(n703), .Y(n609) );
NOR2XLTS U3285 ( .A(n51), .B(n4944), .Y(n672) );
NOR2XLTS U3286 ( .A(n4944), .B(n54), .Y(n674) );
NOR2XLTS U3287 ( .A(n59), .B(n63), .Y(n694) );
NOR2X1TS U3288 ( .A(n724), .B(n694), .Y(n612) );
NAND2X1TS U3289 ( .A(n692), .B(n612), .Y(n614) );
NAND2X1TS U3290 ( .A(n4944), .B(Data_B_i[32]), .Y(n675) );
NAND2X1TS U3291 ( .A(n50), .B(n4944), .Y(n686) );
NAND2X1TS U3292 ( .A(n675), .B(n686), .Y(n691) );
NAND2X1TS U3293 ( .A(n58), .B(n62), .Y(n695) );
NAND2X1TS U3294 ( .A(n55), .B(Data_B_i[33]), .Y(n725) );
NAND2X1TS U3295 ( .A(n695), .B(n725), .Y(n611) );
INVX2TS U3296 ( .A(n615), .Y(n4185) );
NOR2XLTS U3297 ( .A(n4857), .B(n66), .Y(n4126) );
NOR2XLTS U3298 ( .A(n70), .B(n74), .Y(n4192) );
NOR2XLTS U3299 ( .A(n79), .B(n83), .Y(n4096) );
NAND2X1TS U3300 ( .A(n4137), .B(n619), .Y(n621) );
NOR2X1TS U3301 ( .A(n4133), .B(n621), .Y(n623) );
NAND2X1TS U3302 ( .A(n4857), .B(Data_B_i[36]), .Y(n4127) );
NAND2X1TS U3303 ( .A(n61), .B(n4857), .Y(n4124) );
NAND2X1TS U3304 ( .A(n4127), .B(n4124), .Y(n4153) );
NAND2X1TS U3305 ( .A(n71), .B(Data_B_i[38]), .Y(n4193) );
NAND2X1TS U3306 ( .A(n67), .B(Data_B_i[37]), .Y(n4188) );
NAND2X1TS U3307 ( .A(n4193), .B(n4188), .Y(n616) );
AOI21X1TS U3308 ( .A0(n617), .A1(n4153), .B0(n616), .Y(n4135) );
NAND2X1TS U3309 ( .A(n78), .B(n81), .Y(n4097) );
NAND2X1TS U3310 ( .A(n74), .B(Data_B_i[39]), .Y(n4420) );
NAND2X1TS U3311 ( .A(n4097), .B(n4420), .Y(n4136) );
NAND2X1TS U3312 ( .A(n85), .B(n91), .Y(n4144) );
NAND2X1TS U3313 ( .A(n83), .B(n87), .Y(n4179) );
NAND2X1TS U3314 ( .A(n4144), .B(n4179), .Y(n618) );
AOI21X1TS U3315 ( .A0(n619), .A1(n4136), .B0(n618), .Y(n620) );
OAI21X1TS U3316 ( .A0(n4135), .A1(n621), .B0(n620), .Y(n622) );
NAND2X1TS U3317 ( .A(n627), .B(n638), .Y(n629) );
NAND2X1TS U3318 ( .A(n4022), .B(n625), .Y(n3988) );
OR2X1TS U3319 ( .A(n40), .B(n119), .Y(n819) );
NAND2X1TS U3320 ( .A(n805), .B(n819), .Y(n632) );
NAND2X1TS U3321 ( .A(n95), .B(Data_B_i[44]), .Y(n4070) );
NAND2X1TS U3322 ( .A(n90), .B(n94), .Y(n4173) );
NAND2X1TS U3323 ( .A(n4070), .B(n4173), .Y(n4023) );
NAND2X1TS U3324 ( .A(n124), .B(n103), .Y(n4029) );
NAND2X1TS U3325 ( .A(n98), .B(n122), .Y(n4204) );
NAND2X1TS U3326 ( .A(n4029), .B(n4204), .Y(n624) );
AOI21X1TS U3327 ( .A0(n625), .A1(n4023), .B0(n624), .Y(n3987) );
NAND2X1TS U3328 ( .A(n106), .B(n109), .Y(n3992) );
NAND2X1TS U3329 ( .A(Data_B_i[46]), .B(Data_B_i[47]), .Y(n4035) );
NAND2X1TS U3330 ( .A(n3992), .B(n4035), .Y(n637) );
NAND2X1TS U3331 ( .A(n118), .B(n115), .Y(n645) );
NAND2X1TS U3332 ( .A(n110), .B(n113), .Y(n3943) );
NAND2X1TS U3333 ( .A(n645), .B(n3943), .Y(n626) );
AOI21X1TS U3334 ( .A0(n627), .A1(n637), .B0(n626), .Y(n628) );
AOI21X1TS U3335 ( .A0(n806), .A1(n819), .B0(n630), .Y(n631) );
XOR2X1TS U3336 ( .A(n201), .B(Data_A_i[49]), .Y(n4211) );
NAND2BX1TS U3337 ( .AN(n4210), .B(n4211), .Y(n4452) );
CLKBUFX2TS U3338 ( .A(n4452), .Y(n4569) );
XNOR2X1TS U3339 ( .A(Data_A_i[48]), .B(Data_A_i[49]), .Y(n633) );
AND3X1TS U3340 ( .A(n4211), .B(n4210), .C(n633), .Y(n4590) );
INVX2TS U3341 ( .A(n4590), .Y(n4426) );
INVX2TS U3342 ( .A(n4426), .Y(n4576) );
NOR2BX1TS U3343 ( .AN(n4210), .B(n633), .Y(n4573) );
CLKBUFX2TS U3344 ( .A(n4573), .Y(n4594) );
AOI21X1TS U3345 ( .A0(n4576), .A1(n40), .B0(n4594), .Y(n634) );
NAND2X1TS U3346 ( .A(n636), .B(n638), .Y(n641) );
AOI21X1TS U3347 ( .A0(n639), .A1(n638), .B0(n637), .Y(n640) );
OAI21X1TS U3348 ( .A0(n4066), .A1(n641), .B0(n640), .Y(n3946) );
AOI21X1TS U3349 ( .A0(n3946), .A1(n3944), .B0(n643), .Y(n648) );
NAND2X1TS U3350 ( .A(n646), .B(n645), .Y(n647) );
XNOR2X1TS U3351 ( .A(n201), .B(Data_A_i[51]), .Y(n830) );
CLKBUFX2TS U3352 ( .A(n830), .Y(n4505) );
CLKBUFX2TS U3353 ( .A(n830), .Y(n4466) );
NOR2BX1TS U3354 ( .AN(n4466), .B(Data_A_i[51]), .Y(n4039) );
AOI21X1TS U3355 ( .A0(n3948), .A1(n110), .B0(n649), .Y(n650) );
NOR2X1TS U3356 ( .A(genblk1_left_mult_x_1_n632), .B(
genblk1_left_mult_x_1_n642), .Y(n4059) );
NOR2X1TS U3357 ( .A(genblk1_left_mult_x_1_n621), .B(
genblk1_left_mult_x_1_n631), .Y(n4061) );
NOR2X1TS U3358 ( .A(genblk1_left_mult_x_1_n654), .B(
genblk1_left_mult_x_1_n664), .Y(n4346) );
NAND2X1TS U3359 ( .A(n782), .B(n4055), .Y(n4043) );
NOR2X1TS U3360 ( .A(genblk1_left_mult_x_1_n599), .B(
genblk1_left_mult_x_1_n609), .Y(n4050) );
NOR2X1TS U3361 ( .A(genblk1_left_mult_x_1_n589), .B(
genblk1_left_mult_x_1_n598), .Y(n4109) );
NOR2X1TS U3362 ( .A(genblk1_left_mult_x_1_n578), .B(
genblk1_left_mult_x_1_n588), .Y(n4111) );
NOR2X1TS U3363 ( .A(n4109), .B(n4111), .Y(n784) );
NAND2X1TS U3364 ( .A(n4104), .B(n784), .Y(n786) );
NOR2X1TS U3365 ( .A(n4043), .B(n786), .Y(n788) );
NOR2X1TS U3366 ( .A(genblk1_left_mult_x_1_n665), .B(
genblk1_left_mult_x_1_n675), .Y(n4356) );
NOR2X1TS U3367 ( .A(genblk1_left_mult_x_1_n676), .B(
genblk1_left_mult_x_1_n686), .Y(n4354) );
NOR2X1TS U3368 ( .A(genblk1_left_mult_x_1_n687), .B(
genblk1_left_mult_x_1_n697), .Y(n4010) );
NOR2X1TS U3369 ( .A(n4008), .B(n4010), .Y(n4016) );
NAND2X1TS U3370 ( .A(n778), .B(n4016), .Y(n780) );
NOR2X1TS U3371 ( .A(genblk1_left_mult_x_1_n750), .B(
genblk1_left_mult_x_1_n757), .Y(n4380) );
OR2X2TS U3372 ( .A(genblk1_left_mult_x_1_n766), .B(
genblk1_left_mult_x_1_n773), .Y(n3981) );
OR2X2TS U3373 ( .A(genblk1_left_mult_x_1_n774), .B(
genblk1_left_mult_x_1_n780), .Y(n4386) );
NAND2X1TS U3374 ( .A(n3981), .B(n4386), .Y(n769) );
NOR2X1TS U3375 ( .A(genblk1_left_mult_x_1_n781), .B(
genblk1_left_mult_x_1_n787), .Y(n4392) );
NAND2X1TS U3376 ( .A(n317), .B(n703), .Y(n651) );
XNOR2X1TS U3377 ( .A(n178), .B(Data_A_i[33]), .Y(n653) );
XOR2X1TS U3378 ( .A(n182), .B(Data_A_i[34]), .Y(n654) );
NAND2BX1TS U3379 ( .AN(n653), .B(n654), .Y(n4818) );
NOR2X1TS U3380 ( .A(n654), .B(n653), .Y(n4867) );
XNOR2X1TS U3381 ( .A(Data_A_i[33]), .B(Data_A_i[34]), .Y(n652) );
NOR2BX1TS U3382 ( .AN(n653), .B(n652), .Y(n4838) );
CLKBUFX2TS U3383 ( .A(n4838), .Y(n4880) );
CLKBUFX2TS U3384 ( .A(n419), .Y(n4878) );
AND3X1TS U3385 ( .A(n654), .B(n653), .C(n652), .Y(n4858) );
INVX2TS U3386 ( .A(n4858), .Y(n4820) );
INVX2TS U3387 ( .A(n4820), .Y(n4879) );
NAND2X1TS U3388 ( .A(n4852), .B(n4539), .Y(n657) );
CLKBUFX2TS U3389 ( .A(n4838), .Y(n4864) );
AOI22X1TS U3390 ( .A0(n4864), .A1(n4549), .B0(n4852), .B1(n4548), .Y(n660)
);
INVX2TS U3391 ( .A(n684), .Y(n662) );
INVX2TS U3392 ( .A(n663), .Y(n4156) );
NAND2X1TS U3393 ( .A(n664), .B(n4124), .Y(n665) );
AND3X1TS U3394 ( .A(n668), .B(n667), .C(n666), .Y(n4976) );
INVX2TS U3395 ( .A(n4976), .Y(n4224) );
INVX2TS U3396 ( .A(n4224), .Y(n4968) );
AOI222XLTS U3397 ( .A0(n4221), .A1(n516), .B0(n4969), .B1(Data_B_i[34]),
.C0(n4968), .C1(Data_B_i[33]), .Y(n669) );
INVX2TS U3398 ( .A(n607), .Y(n4959) );
INVX2TS U3399 ( .A(n671), .Y(n693) );
AOI21X1TS U3400 ( .A0(n693), .A1(n687), .B0(n673), .Y(n678) );
NAND2X1TS U3401 ( .A(n676), .B(n675), .Y(n677) );
XNOR2X1TS U3402 ( .A(n4955), .B(Data_A_i[30]), .Y(n680) );
NAND2BX1TS U3403 ( .AN(n680), .B(n681), .Y(n4886) );
NOR2X1TS U3404 ( .A(n681), .B(n680), .Y(n4947) );
XNOR2X1TS U3405 ( .A(Data_A_i[30]), .B(Data_A_i[31]), .Y(n679) );
NOR2BX1TS U3406 ( .AN(n680), .B(n679), .Y(n4909) );
CLKBUFX2TS U3407 ( .A(n4909), .Y(n4946) );
CLKBUFX2TS U3408 ( .A(n439), .Y(n4870) );
AND3X1TS U3409 ( .A(n681), .B(n680), .C(n679), .Y(n4931) );
INVX2TS U3410 ( .A(n4931), .Y(n4889) );
INVX2TS U3411 ( .A(n4889), .Y(n4945) );
AOI222XLTS U3412 ( .A0(n4925), .A1(n55), .B0(n4946), .B1(n4870), .C0(n4945),
.C1(n50), .Y(n682) );
NAND2X1TS U3413 ( .A(n687), .B(n686), .Y(n688) );
CLKBUFX2TS U3414 ( .A(n439), .Y(n4873) );
AOI222XLTS U3415 ( .A0(n4925), .A1(n4873), .B0(n4946), .B1(Data_B_i[30]),
.C0(n4945), .C1(n46), .Y(n689) );
AOI21X1TS U3416 ( .A0(n693), .A1(n692), .B0(n691), .Y(n728) );
NAND2X1TS U3417 ( .A(n696), .B(n695), .Y(n697) );
AOI222XLTS U3418 ( .A0(n4221), .A1(Data_B_i[34]), .B0(n4977), .B1(n59), .C0(
n4968), .C1(n55), .Y(n699) );
OAI21XLTS U3419 ( .A0(n4942), .A1(n4980), .B0(n699), .Y(n700) );
ADDHXLTS U3420 ( .A(n183), .B(n701), .CO(n685), .S(n723) );
NAND2X1TS U3421 ( .A(n703), .B(n702), .Y(n706) );
NAND2X1TS U3422 ( .A(n27), .B(n704), .Y(n705) );
XOR2X1TS U3423 ( .A(n706), .B(n705), .Y(n4884) );
CLKBUFX2TS U3424 ( .A(n419), .Y(n4761) );
AOI222XLTS U3425 ( .A0(n4925), .A1(n50), .B0(n4946), .B1(n47), .C0(n4945),
.C1(n4761), .Y(n707) );
AOI222XLTS U3426 ( .A0(n4925), .A1(Data_B_i[29]), .B0(n4946), .B1(n4878),
.C0(n4945), .C1(n422), .Y(n709) );
CLKBUFX2TS U3427 ( .A(n4909), .Y(n4940) );
AOI22X1TS U3428 ( .A0(n4940), .A1(n4549), .B0(n4928), .B1(n4548), .Y(n711)
);
NAND2X1TS U3429 ( .A(n4928), .B(n4549), .Y(n713) );
CMPR32X2TS U3430 ( .A(n720), .B(n719), .C(n718), .CO(n759), .S(n758) );
CMPR32X2TS U3431 ( .A(n723), .B(n722), .C(n721), .CO(n757), .S(n756) );
NAND2X1TS U3432 ( .A(n726), .B(n725), .Y(n727) );
AOI222XLTS U3433 ( .A0(n4221), .A1(n59), .B0(n4969), .B1(n55), .C0(n4968),
.C1(n4873), .Y(n729) );
OAI21XLTS U3434 ( .A0(n313), .A1(n4980), .B0(n729), .Y(n730) );
AOI222XLTS U3435 ( .A0(n4973), .A1(n46), .B0(n4969), .B1(n4878), .C0(n4968),
.C1(n422), .Y(n731) );
OAI21XLTS U3436 ( .A0(n21), .A1(n4971), .B0(n731), .Y(n732) );
INVX2TS U3437 ( .A(n607), .Y(n4981) );
XNOR2X1TS U3438 ( .A(n732), .B(n4981), .Y(n3951) );
AOI22X1TS U3439 ( .A0(n4978), .A1(n4548), .B0(n4977), .B1(n4549), .Y(n733)
);
CLKAND2X2TS U3440 ( .A(n735), .B(n4955), .Y(n4418) );
NAND2X1TS U3441 ( .A(n4417), .B(n4418), .Y(n3950) );
AOI222XLTS U3442 ( .A0(n4973), .A1(n51), .B0(n4969), .B1(n46), .C0(n4968),
.C1(n4761), .Y(n736) );
OAI21XLTS U3443 ( .A0(n4884), .A1(n4971), .B0(n736), .Y(n737) );
ADDHXLTS U3444 ( .A(n179), .B(n738), .CO(n744), .S(n739) );
NAND2X1TS U3445 ( .A(n740), .B(n739), .Y(n4413) );
INVX2TS U3446 ( .A(n4413), .Y(n741) );
AOI21X1TS U3447 ( .A0(n4415), .A1(n4414), .B0(n741), .Y(n3956) );
AOI222XLTS U3448 ( .A0(n4973), .A1(n4873), .B0(n4969), .B1(n51), .C0(n4968),
.C1(n46), .Y(n742) );
OAI21XLTS U3449 ( .A0(n4876), .A1(n4971), .B0(n742), .Y(n743) );
ADDHXLTS U3450 ( .A(n745), .B(n744), .CO(n750), .S(n746) );
NAND2X1TS U3451 ( .A(n747), .B(n746), .Y(n3953) );
AOI222XLTS U3452 ( .A0(n4973), .A1(n54), .B0(n4969), .B1(n4870), .C0(n4968),
.C1(Data_B_i[30]), .Y(n748) );
OAI21XLTS U3453 ( .A0(n342), .A1(n4971), .B0(n748), .Y(n749) );
ADDHXLTS U3454 ( .A(n751), .B(n750), .CO(n721), .S(n752) );
OR2X1TS U3455 ( .A(n753), .B(n752), .Y(n4410) );
NAND2X1TS U3456 ( .A(n753), .B(n752), .Y(n4409) );
INVX2TS U3457 ( .A(n4409), .Y(n754) );
AOI21X1TS U3458 ( .A0(n4411), .A1(n4410), .B0(n754), .Y(n3960) );
NAND2X1TS U3459 ( .A(n756), .B(n755), .Y(n3958) );
NAND2X1TS U3460 ( .A(n758), .B(n757), .Y(n4401) );
NAND2X1TS U3461 ( .A(n760), .B(n759), .Y(n4405) );
NAND2X1TS U3462 ( .A(genblk1_left_mult_x_1_n805), .B(n763), .Y(n3966) );
NAND2X1TS U3463 ( .A(genblk1_left_mult_x_1_n800), .B(
genblk1_left_mult_x_1_n804), .Y(n4397) );
INVX2TS U3464 ( .A(n4397), .Y(n764) );
NAND2X1TS U3465 ( .A(genblk1_left_mult_x_1_n795), .B(
genblk1_left_mult_x_1_n799), .Y(n3971) );
NAND2X1TS U3466 ( .A(genblk1_left_mult_x_1_n788), .B(
genblk1_left_mult_x_1_n794), .Y(n4389) );
NAND2X1TS U3467 ( .A(genblk1_left_mult_x_1_n781), .B(
genblk1_left_mult_x_1_n787), .Y(n4393) );
NAND2X1TS U3468 ( .A(genblk1_left_mult_x_1_n774), .B(
genblk1_left_mult_x_1_n780), .Y(n4385) );
INVX2TS U3469 ( .A(n4385), .Y(n3979) );
NAND2X1TS U3470 ( .A(genblk1_left_mult_x_1_n766), .B(
genblk1_left_mult_x_1_n773), .Y(n3980) );
INVX2TS U3471 ( .A(n3980), .Y(n767) );
AOI21X1TS U3472 ( .A0(n3981), .A1(n3979), .B0(n767), .Y(n768) );
NAND2X1TS U3473 ( .A(genblk1_left_mult_x_1_n758), .B(
genblk1_left_mult_x_1_n765), .Y(n4377) );
NAND2X1TS U3474 ( .A(genblk1_left_mult_x_1_n750), .B(
genblk1_left_mult_x_1_n757), .Y(n4381) );
OR2X2TS U3475 ( .A(genblk1_left_mult_x_1_n730), .B(
genblk1_left_mult_x_1_n739), .Y(n4004) );
OR2X2TS U3476 ( .A(genblk1_left_mult_x_1_n740), .B(
genblk1_left_mult_x_1_n749), .Y(n4374) );
NAND2X1TS U3477 ( .A(n4004), .B(n4374), .Y(n774) );
NAND2X1TS U3478 ( .A(genblk1_left_mult_x_1_n740), .B(
genblk1_left_mult_x_1_n749), .Y(n4373) );
INVX2TS U3479 ( .A(n4373), .Y(n4002) );
NAND2X1TS U3480 ( .A(genblk1_left_mult_x_1_n730), .B(
genblk1_left_mult_x_1_n739), .Y(n4003) );
INVX2TS U3481 ( .A(n4003), .Y(n772) );
AOI21X1TS U3482 ( .A0(n4004), .A1(n4002), .B0(n772), .Y(n773) );
NOR2X1TS U3483 ( .A(genblk1_left_mult_x_1_n720), .B(
genblk1_left_mult_x_1_n729), .Y(n4366) );
NOR2X1TS U3484 ( .A(genblk1_left_mult_x_1_n709), .B(
genblk1_left_mult_x_1_n719), .Y(n4368) );
NAND2X1TS U3485 ( .A(genblk1_left_mult_x_1_n720), .B(
genblk1_left_mult_x_1_n729), .Y(n4365) );
NAND2X1TS U3486 ( .A(genblk1_left_mult_x_1_n709), .B(
genblk1_left_mult_x_1_n719), .Y(n4369) );
AOI21X2TS U3487 ( .A0(n3998), .A1(n776), .B0(n775), .Y(n4007) );
NAND2X1TS U3488 ( .A(genblk1_left_mult_x_1_n698), .B(
genblk1_left_mult_x_1_n708), .Y(n4361) );
NAND2X1TS U3489 ( .A(genblk1_left_mult_x_1_n687), .B(
genblk1_left_mult_x_1_n697), .Y(n4011) );
OAI21X1TS U3490 ( .A0(n4010), .A1(n4361), .B0(n4011), .Y(n4015) );
NAND2X1TS U3491 ( .A(genblk1_left_mult_x_1_n676), .B(
genblk1_left_mult_x_1_n686), .Y(n4353) );
NAND2X1TS U3492 ( .A(genblk1_left_mult_x_1_n665), .B(
genblk1_left_mult_x_1_n675), .Y(n4357) );
AOI21X1TS U3493 ( .A0(n778), .A1(n4015), .B0(n777), .Y(n779) );
OAI21X2TS U3494 ( .A0(n780), .A1(n4007), .B0(n779), .Y(n4019) );
NAND2X1TS U3495 ( .A(genblk1_left_mult_x_1_n654), .B(
genblk1_left_mult_x_1_n664), .Y(n4345) );
NAND2X1TS U3496 ( .A(genblk1_left_mult_x_1_n643), .B(
genblk1_left_mult_x_1_n653), .Y(n4349) );
NAND2X1TS U3497 ( .A(genblk1_left_mult_x_1_n632), .B(
genblk1_left_mult_x_1_n642), .Y(n4341) );
NAND2X1TS U3498 ( .A(genblk1_left_mult_x_1_n621), .B(
genblk1_left_mult_x_1_n631), .Y(n4062) );
AOI21X1TS U3499 ( .A0(n782), .A1(n4056), .B0(n781), .Y(n4042) );
NAND2X1TS U3500 ( .A(genblk1_left_mult_x_1_n610), .B(
genblk1_left_mult_x_1_n620), .Y(n4046) );
NAND2X1TS U3501 ( .A(genblk1_left_mult_x_1_n599), .B(
genblk1_left_mult_x_1_n609), .Y(n4051) );
NAND2X1TS U3502 ( .A(genblk1_left_mult_x_1_n589), .B(
genblk1_left_mult_x_1_n598), .Y(n4337) );
NAND2X1TS U3503 ( .A(genblk1_left_mult_x_1_n578), .B(
genblk1_left_mult_x_1_n588), .Y(n4112) );
AOI21X1TS U3504 ( .A0(n4105), .A1(n784), .B0(n783), .Y(n785) );
OAI21X1TS U3505 ( .A0(n4042), .A1(n786), .B0(n785), .Y(n787) );
AOI21X2TS U3506 ( .A0(n788), .A1(n4019), .B0(n787), .Y(n4076) );
NOR2X1TS U3507 ( .A(genblk1_left_mult_x_1_n559), .B(
genblk1_left_mult_x_1_n568), .Y(n4085) );
NOR2X1TS U3508 ( .A(n4083), .B(n4085), .Y(n4091) );
NOR2X1TS U3509 ( .A(genblk1_left_mult_x_1_n549), .B(
genblk1_left_mult_x_1_n558), .Y(n4326) );
NOR2X1TS U3510 ( .A(genblk1_left_mult_x_1_n541), .B(
genblk1_left_mult_x_1_n548), .Y(n4328) );
NAND2X1TS U3511 ( .A(n4091), .B(n790), .Y(n4116) );
NAND2X1TS U3512 ( .A(n4317), .B(n370), .Y(n793) );
NOR2X1TS U3513 ( .A(n793), .B(n4320), .Y(n4163) );
INVX2TS U3514 ( .A(n4306), .Y(n4313) );
NAND2X1TS U3515 ( .A(n4313), .B(n4309), .Y(n4164) );
NAND2X1TS U3516 ( .A(n4163), .B(n797), .Y(n799) );
NOR2X1TS U3517 ( .A(n4116), .B(n799), .Y(n4078) );
NAND2X1TS U3518 ( .A(n4078), .B(n4080), .Y(n802) );
NAND2X1TS U3519 ( .A(genblk1_left_mult_x_1_n569), .B(
genblk1_left_mult_x_1_n577), .Y(n4333) );
NAND2X1TS U3520 ( .A(genblk1_left_mult_x_1_n559), .B(
genblk1_left_mult_x_1_n568), .Y(n4086) );
OAI21X1TS U3521 ( .A0(n4085), .A1(n4333), .B0(n4086), .Y(n4090) );
NAND2X1TS U3522 ( .A(genblk1_left_mult_x_1_n549), .B(
genblk1_left_mult_x_1_n558), .Y(n4325) );
NAND2X1TS U3523 ( .A(genblk1_left_mult_x_1_n541), .B(
genblk1_left_mult_x_1_n548), .Y(n4329) );
AOI21X1TS U3524 ( .A0(n4090), .A1(n790), .B0(n789), .Y(n4117) );
NAND2X1TS U3525 ( .A(genblk1_left_mult_x_1_n534), .B(
genblk1_left_mult_x_1_n540), .Y(n4321) );
NAND2X1TS U3526 ( .A(genblk1_left_mult_x_1_n533), .B(
genblk1_left_mult_x_1_n526), .Y(n4316) );
INVX2TS U3527 ( .A(n4316), .Y(n4120) );
NAND2X1TS U3528 ( .A(genblk1_left_mult_x_1_n520), .B(
genblk1_left_mult_x_1_n525), .Y(n4121) );
INVX2TS U3529 ( .A(n4121), .Y(n791) );
AOI21X1TS U3530 ( .A0(n370), .A1(n4120), .B0(n791), .Y(n792) );
OAI21X1TS U3531 ( .A0(n793), .A1(n4321), .B0(n792), .Y(n4162) );
NAND2X1TS U3532 ( .A(genblk1_left_mult_x_1_n519), .B(
genblk1_left_mult_x_1_n513), .Y(n4312) );
NAND2X1TS U3533 ( .A(genblk1_left_mult_x_1_n512), .B(
genblk1_left_mult_x_1_n506), .Y(n4308) );
INVX2TS U3534 ( .A(n4308), .Y(n794) );
AOI21X1TS U3535 ( .A0(n795), .A1(n4309), .B0(n794), .Y(n4165) );
NAND2X1TS U3536 ( .A(genblk1_left_mult_x_1_n501), .B(
genblk1_left_mult_x_1_n505), .Y(n4169) );
AOI21X1TS U3537 ( .A0(n4162), .A1(n797), .B0(n796), .Y(n798) );
NAND2X1TS U3538 ( .A(genblk1_left_mult_x_1_n500), .B(
genblk1_left_mult_x_1_n497), .Y(n4079) );
AOI21X1TS U3539 ( .A0(n4077), .A1(n4080), .B0(n800), .Y(n801) );
ACHCINX2TS U3540 ( .CIN(n1458), .A(genblk1_left_mult_x_1_n489), .B(
genblk1_left_mult_x_1_n491), .CO(n4303) );
NAND2X1TS U3541 ( .A(n40), .B(n117), .Y(n817) );
NAND2X1TS U3542 ( .A(n819), .B(n817), .Y(n809) );
AOI21X1TS U3543 ( .A0(n3948), .A1(n115), .B0(n810), .Y(n811) );
INVX2TS U3544 ( .A(n4951), .Y(n4887) );
OAI21XLTS U3545 ( .A0(n4887), .A1(n4569), .B0(n4426), .Y(n812) );
XNOR2X1TS U3546 ( .A(n826), .B(n813), .Y(genblk1_left_N48) );
AOI21X1TS U3547 ( .A0(n820), .A1(n819), .B0(n818), .Y(n821) );
CLKBUFX2TS U3548 ( .A(n4039), .Y(n4490) );
AOI21X1TS U3549 ( .A0(n3948), .A1(Data_B_i[50]), .B0(n822), .Y(n823) );
CMPR32X2TS U3550 ( .A(n200), .B(n828), .C(n827), .CO(n1173), .S(n4301) );
AOI21X1TS U3551 ( .A0(n3948), .A1(Data_B_i[51]), .B0(n4039), .Y(n829) );
OA21XLTS U3552 ( .A0(n4951), .A1(n4505), .B0(n829), .Y(n1172) );
CLKBUFX2TS U3553 ( .A(n830), .Y(n4492) );
INVX2TS U3554 ( .A(n3948), .Y(n4101) );
OAI21XLTS U3555 ( .A0(n4887), .A1(n4492), .B0(n4101), .Y(n831) );
NOR2X1TS U3556 ( .A(n857), .B(n855), .Y(n3705) );
INVX2TS U3557 ( .A(n3057), .Y(n3723) );
NAND2X1TS U3558 ( .A(n306), .B(n3723), .Y(n835) );
NOR2X1TS U3559 ( .A(genblk1_right_mult_x_1_n683), .B(
genblk1_right_mult_x_1_n694), .Y(n3859) );
NOR2X1TS U3560 ( .A(genblk1_right_mult_x_1_n695), .B(
genblk1_right_mult_x_1_n706), .Y(n3868) );
NAND2X1TS U3561 ( .A(n978), .B(n2873), .Y(n980) );
NOR2X1TS U3562 ( .A(genblk1_right_mult_x_1_n792), .B(
genblk1_right_mult_x_1_n802), .Y(n3892) );
NAND2X1TS U3563 ( .A(n967), .B(n2892), .Y(n969) );
NOR2X1TS U3564 ( .A(genblk1_right_mult_x_1_n813), .B(
genblk1_right_mult_x_1_n822), .Y(n2901) );
NOR2X1TS U3565 ( .A(genblk1_right_mult_x_1_n841), .B(
genblk1_right_mult_x_1_n848), .Y(n2907) );
OR2X2TS U3566 ( .A(genblk1_right_mult_x_1_n878), .B(
genblk1_right_mult_x_1_n882), .Y(n3923) );
NAND2X1TS U3567 ( .A(n3923), .B(n3920), .Y(n957) );
NAND2X1TS U3568 ( .A(n246), .B(n243), .Y(n892) );
NAND2X1TS U3569 ( .A(n350), .B(n892), .Y(n836) );
NAND2X1TS U3570 ( .A(n245), .B(n3723), .Y(n891) );
XNOR2X1TS U3571 ( .A(n274), .B(Data_A_i[6]), .Y(n838) );
NOR2X1TS U3572 ( .A(n839), .B(n838), .Y(n3773) );
XNOR2X1TS U3573 ( .A(Data_A_i[6]), .B(Data_A_i[7]), .Y(n837) );
NOR2BX1TS U3574 ( .AN(n838), .B(n837), .Y(n3772) );
CLKBUFX2TS U3575 ( .A(n3772), .Y(n3597) );
AND3X1TS U3576 ( .A(n839), .B(n838), .C(n837), .Y(n3565) );
CLKBUFX2TS U3577 ( .A(n3565), .Y(n3596) );
INVX2TS U3578 ( .A(n3057), .Y(n3786) );
AOI222XLTS U3579 ( .A0(n3754), .A1(n242), .B0(n3597), .B1(Data_B_i[1]), .C0(
n3596), .C1(n3786), .Y(n840) );
OR2X1TS U3580 ( .A(n247), .B(n3723), .Y(n842) );
CLKBUFX2TS U3581 ( .A(n3772), .Y(n3753) );
INVX2TS U3582 ( .A(n3057), .Y(n3743) );
AOI22X1TS U3583 ( .A0(n3753), .A1(n3743), .B0(n3579), .B1(n246), .Y(n843) );
NAND2X1TS U3584 ( .A(n3579), .B(n3723), .Y(n845) );
INVX2TS U3585 ( .A(n891), .Y(n848) );
NAND2X1TS U3586 ( .A(n242), .B(n239), .Y(n893) );
NAND2X1TS U3587 ( .A(n893), .B(n892), .Y(n847) );
NOR2XLTS U3588 ( .A(n237), .B(n233), .Y(n861) );
NOR2XLTS U3589 ( .A(n233), .B(n229), .Y(n863) );
NOR2XLTS U3590 ( .A(n225), .B(n221), .Y(n883) );
NAND2X1TS U3591 ( .A(n881), .B(n850), .Y(n852) );
NAND2X1TS U3592 ( .A(n234), .B(n230), .Y(n864) );
NAND2X1TS U3593 ( .A(n238), .B(n235), .Y(n875) );
NAND2X1TS U3594 ( .A(n864), .B(n875), .Y(n880) );
NAND2X1TS U3595 ( .A(n227), .B(n223), .Y(n884) );
NAND2X1TS U3596 ( .A(n226), .B(n231), .Y(n914) );
NAND2X1TS U3597 ( .A(n884), .B(n914), .Y(n849) );
AOI21X1TS U3598 ( .A0(n850), .A1(n880), .B0(n849), .Y(n851) );
OAI21X2TS U3599 ( .A0(n860), .A1(n852), .B0(n851), .Y(n1411) );
INVX2TS U3600 ( .A(n1411), .Y(n3243) );
NOR2XLTS U3601 ( .A(n221), .B(n217), .Y(n2989) );
NAND2X1TS U3602 ( .A(n222), .B(n217), .Y(n2988) );
NAND2X1TS U3603 ( .A(n853), .B(n2988), .Y(n854) );
NOR2BX1TS U3604 ( .AN(n855), .B(n856), .Y(n3704) );
CLKBUFX2TS U3605 ( .A(n3704), .Y(n3717) );
AOI222XLTS U3606 ( .A0(n306), .A1(n219), .B0(n3717), .B1(n222), .C0(n3733),
.C1(n227), .Y(n858) );
INVX2TS U3607 ( .A(n860), .Y(n882) );
AOI21X1TS U3608 ( .A0(n882), .A1(n876), .B0(n862), .Y(n867) );
NAND2X1TS U3609 ( .A(n865), .B(n864), .Y(n866) );
XNOR2X1TS U3610 ( .A(n283), .B(Data_A_i[3]), .Y(n869) );
XOR2X1TS U3611 ( .A(n274), .B(Data_A_i[4]), .Y(n870) );
XNOR2X1TS U3612 ( .A(Data_A_i[3]), .B(Data_A_i[4]), .Y(n868) );
NOR2BX1TS U3613 ( .AN(n869), .B(n868), .Y(n3658) );
CLKBUFX2TS U3614 ( .A(n3658), .Y(n3634) );
AND3X1TS U3615 ( .A(n870), .B(n869), .C(n868), .Y(n3633) );
CLKBUFX2TS U3616 ( .A(n3633), .Y(n3657) );
AOI222XLTS U3617 ( .A0(n3659), .A1(n231), .B0(n3634), .B1(Data_B_i[4]), .C0(
n3657), .C1(n239), .Y(n871) );
ADDHXLTS U3618 ( .A(n874), .B(n873), .CO(n3088), .S(n909) );
NAND2X1TS U3619 ( .A(n876), .B(n875), .Y(n877) );
AOI222XLTS U3620 ( .A0(n3639), .A1(n235), .B0(n3634), .B1(Data_B_i[3]), .C0(
n3657), .C1(n243), .Y(n878) );
AOI21X1TS U3621 ( .A0(n882), .A1(n881), .B0(n880), .Y(n917) );
NAND2X1TS U3622 ( .A(n885), .B(n884), .Y(n886) );
AOI222XLTS U3623 ( .A0(n306), .A1(n222), .B0(n3717), .B1(n226), .C0(n3733),
.C1(n231), .Y(n888) );
ADDHXLTS U3624 ( .A(n270), .B(n890), .CO(n873), .S(n912) );
NAND2X1TS U3625 ( .A(n892), .B(n891), .Y(n895) );
NAND2X1TS U3626 ( .A(n351), .B(n893), .Y(n894) );
AOI222XLTS U3627 ( .A0(n3639), .A1(n239), .B0(n3634), .B1(n242), .C0(n3657),
.C1(n246), .Y(n896) );
XOR2X1TS U3628 ( .A(n897), .B(n276), .Y(n911) );
AOI222XLTS U3629 ( .A0(n3639), .A1(n243), .B0(n3634), .B1(Data_B_i[1]), .C0(
n3657), .C1(n3786), .Y(n898) );
CLKBUFX2TS U3630 ( .A(n3658), .Y(n3638) );
AOI22X1TS U3631 ( .A0(n3638), .A1(n3743), .B0(n3642), .B1(Data_B_i[1]), .Y(
n900) );
NAND2X1TS U3632 ( .A(n3642), .B(n3723), .Y(n902) );
OR2X2TS U3633 ( .A(n947), .B(n946), .Y(n3927) );
CMPR32X2TS U3634 ( .A(n906), .B(n905), .C(n904), .CO(n953), .S(n949) );
CMPR32X2TS U3635 ( .A(n909), .B(n908), .C(n907), .CO(n948), .S(n947) );
NAND2X1TS U3636 ( .A(n3927), .B(n3930), .Y(n952) );
CMPR32X2TS U3637 ( .A(n912), .B(n911), .C(n910), .CO(n946), .S(n944) );
NAND2X1TS U3638 ( .A(n915), .B(n914), .Y(n916) );
AOI222XLTS U3639 ( .A0(n306), .A1(n226), .B0(n3717), .B1(n230), .C0(n3699),
.C1(n234), .Y(n918) );
AOI222XLTS U3640 ( .A0(n3705), .A1(n242), .B0(n3717), .B1(n247), .C0(n3699),
.C1(n3786), .Y(n920) );
XOR2X1TS U3641 ( .A(n921), .B(n284), .Y(n2936) );
CLKBUFX2TS U3642 ( .A(n3704), .Y(n3734) );
AOI22X1TS U3643 ( .A0(n307), .A1(n246), .B0(n3734), .B1(n3786), .Y(n922) );
XNOR2X1TS U3644 ( .A(n923), .B(n283), .Y(n2940) );
NAND2X1TS U3645 ( .A(n924), .B(n283), .Y(n2939) );
NOR2XLTS U3646 ( .A(n2940), .B(n2939), .Y(n2937) );
NAND2X1TS U3647 ( .A(n2936), .B(n2937), .Y(n3941) );
AOI222XLTS U3648 ( .A0(n306), .A1(n239), .B0(n3717), .B1(Data_B_i[2]), .C0(
n3699), .C1(n247), .Y(n925) );
XOR2X1TS U3649 ( .A(n926), .B(n285), .Y(n929) );
ADDHXLTS U3650 ( .A(n275), .B(n927), .CO(n932), .S(n928) );
NAND2X1TS U3651 ( .A(n929), .B(n928), .Y(n3939) );
AOI222XLTS U3652 ( .A0(n307), .A1(n235), .B0(n3704), .B1(n238), .C0(n3699),
.C1(n242), .Y(n930) );
ADDHXLTS U3653 ( .A(n933), .B(n932), .CO(n939), .S(n934) );
OR2X1TS U3654 ( .A(n935), .B(n934), .Y(n2933) );
NAND2X1TS U3655 ( .A(n935), .B(n934), .Y(n2932) );
INVX2TS U3656 ( .A(n2932), .Y(n936) );
AOI21X1TS U3657 ( .A0(n2934), .A1(n2933), .B0(n936), .Y(n3936) );
AOI222XLTS U3658 ( .A0(n307), .A1(Data_B_i[5]), .B0(n3704), .B1(n234), .C0(
n3699), .C1(n239), .Y(n937) );
ADDHXLTS U3659 ( .A(n940), .B(n939), .CO(n910), .S(n941) );
NAND2X1TS U3660 ( .A(n942), .B(n941), .Y(n3934) );
NAND2X1TS U3661 ( .A(n944), .B(n943), .Y(n2928) );
INVX2TS U3662 ( .A(n2928), .Y(n945) );
AOI21X1TS U3663 ( .A0(n2929), .A1(n2930), .B0(n945), .Y(n2926) );
NAND2X1TS U3664 ( .A(n947), .B(n946), .Y(n2925) );
INVX2TS U3665 ( .A(n2925), .Y(n3926) );
NAND2X1TS U3666 ( .A(n949), .B(n948), .Y(n3929) );
INVX2TS U3667 ( .A(n3929), .Y(n950) );
AOI21X1TS U3668 ( .A0(n3930), .A1(n3926), .B0(n950), .Y(n951) );
NAND2X1TS U3669 ( .A(genblk1_right_mult_x_1_n888), .B(n953), .Y(n2922) );
INVX2TS U3670 ( .A(n2922), .Y(n954) );
NAND2X1TS U3671 ( .A(genblk1_right_mult_x_1_n883), .B(
genblk1_right_mult_x_1_n887), .Y(n2919) );
INVX2TS U3672 ( .A(n2919), .Y(n3919) );
NAND2X1TS U3673 ( .A(genblk1_right_mult_x_1_n878), .B(
genblk1_right_mult_x_1_n882), .Y(n3922) );
INVX2TS U3674 ( .A(n3922), .Y(n955) );
AOI21X1TS U3675 ( .A0(n3923), .A1(n3919), .B0(n955), .Y(n956) );
NAND2X1TS U3676 ( .A(genblk1_right_mult_x_1_n871), .B(
genblk1_right_mult_x_1_n877), .Y(n2915) );
INVX2TS U3677 ( .A(n2915), .Y(n958) );
AOI21X1TS U3678 ( .A0(n2918), .A1(n2916), .B0(n958), .Y(n2912) );
NAND2X1TS U3679 ( .A(n3908), .B(n3911), .Y(n961) );
NAND2X1TS U3680 ( .A(genblk1_right_mult_x_1_n864), .B(
genblk1_right_mult_x_1_n870), .Y(n2913) );
INVX2TS U3681 ( .A(n2913), .Y(n3907) );
NAND2X1TS U3682 ( .A(genblk1_right_mult_x_1_n857), .B(
genblk1_right_mult_x_1_n863), .Y(n3910) );
INVX2TS U3683 ( .A(n3910), .Y(n959) );
AOI21X1TS U3684 ( .A0(n3911), .A1(n3907), .B0(n959), .Y(n960) );
OAI21X1TS U3685 ( .A0(n2912), .A1(n961), .B0(n960), .Y(n2906) );
NAND2X1TS U3686 ( .A(genblk1_right_mult_x_1_n849), .B(
genblk1_right_mult_x_1_n856), .Y(n3915) );
NAND2X1TS U3687 ( .A(genblk1_right_mult_x_1_n841), .B(
genblk1_right_mult_x_1_n848), .Y(n2908) );
NAND2X1TS U3688 ( .A(genblk1_right_mult_x_1_n833), .B(
genblk1_right_mult_x_1_n840), .Y(n3903) );
OAI21X1TS U3689 ( .A0(n3906), .A1(n3902), .B0(n3903), .Y(n2900) );
NAND2X1TS U3690 ( .A(genblk1_right_mult_x_1_n823), .B(
genblk1_right_mult_x_1_n832), .Y(n3898) );
NAND2X1TS U3691 ( .A(genblk1_right_mult_x_1_n813), .B(
genblk1_right_mult_x_1_n822), .Y(n2902) );
NAND2X1TS U3692 ( .A(genblk1_right_mult_x_1_n803), .B(
genblk1_right_mult_x_1_n812), .Y(n3888) );
NAND2X1TS U3693 ( .A(genblk1_right_mult_x_1_n792), .B(
genblk1_right_mult_x_1_n802), .Y(n3893) );
OAI21X1TS U3694 ( .A0(n3892), .A1(n3888), .B0(n3893), .Y(n2891) );
NAND2X1TS U3695 ( .A(genblk1_right_mult_x_1_n781), .B(
genblk1_right_mult_x_1_n791), .Y(n3880) );
NAND2X1TS U3696 ( .A(genblk1_right_mult_x_1_n770), .B(
genblk1_right_mult_x_1_n780), .Y(n2894) );
AOI21X1TS U3697 ( .A0(n967), .A1(n2891), .B0(n966), .Y(n968) );
OAI21X2TS U3698 ( .A0(n969), .A1(n2890), .B0(n968), .Y(n2881) );
NAND2X1TS U3699 ( .A(n3876), .B(n360), .Y(n974) );
INVX2TS U3700 ( .A(n2886), .Y(n3885) );
NAND2X1TS U3701 ( .A(n3885), .B(n361), .Y(n2883) );
NAND2X1TS U3702 ( .A(genblk1_right_mult_x_1_n757), .B(
genblk1_right_mult_x_1_n769), .Y(n3884) );
NAND2X1TS U3703 ( .A(genblk1_right_mult_x_1_n744), .B(
genblk1_right_mult_x_1_n756), .Y(n2887) );
INVX2TS U3704 ( .A(n2887), .Y(n970) );
AOI21X1TS U3705 ( .A0(n361), .A1(n971), .B0(n970), .Y(n2882) );
NAND2X1TS U3706 ( .A(genblk1_right_mult_x_1_n731), .B(
genblk1_right_mult_x_1_n743), .Y(n2884) );
INVX2TS U3707 ( .A(n2884), .Y(n3873) );
NAND2X1TS U3708 ( .A(genblk1_right_mult_x_1_n719), .B(
genblk1_right_mult_x_1_n730), .Y(n3875) );
INVX2TS U3709 ( .A(n3875), .Y(n972) );
AOI21X1TS U3710 ( .A0(n3876), .A1(n3873), .B0(n972), .Y(n973) );
OAI21X1TS U3711 ( .A0(n974), .A1(n2882), .B0(n973), .Y(n975) );
AOI21X2TS U3712 ( .A0(n2881), .A1(n976), .B0(n975), .Y(n2871) );
NAND2X1TS U3713 ( .A(genblk1_right_mult_x_1_n707), .B(
genblk1_right_mult_x_1_n718), .Y(n3864) );
NAND2X1TS U3714 ( .A(genblk1_right_mult_x_1_n695), .B(
genblk1_right_mult_x_1_n706), .Y(n3869) );
NAND2X1TS U3715 ( .A(genblk1_right_mult_x_1_n683), .B(
genblk1_right_mult_x_1_n694), .Y(n3860) );
NAND2X1TS U3716 ( .A(genblk1_right_mult_x_1_n671), .B(
genblk1_right_mult_x_1_n682), .Y(n2875) );
NOR2X1TS U3717 ( .A(genblk1_right_mult_x_1_n647), .B(
genblk1_right_mult_x_1_n658), .Y(n2866) );
OR2X2TS U3718 ( .A(genblk1_right_mult_x_1_n624), .B(
genblk1_right_mult_x_1_n634), .Y(n3838) );
NAND2X1TS U3719 ( .A(n363), .B(n3838), .Y(n2863) );
OR2X2TS U3720 ( .A(genblk1_right_mult_x_1_n614), .B(
genblk1_right_mult_x_1_n623), .Y(n3830) );
NAND2X1TS U3721 ( .A(n3830), .B(n364), .Y(n984) );
NOR2X1TS U3722 ( .A(n2863), .B(n984), .Y(n986) );
NAND2X1TS U3723 ( .A(n2858), .B(n986), .Y(n2826) );
NOR2X1TS U3724 ( .A(genblk1_right_mult_x_1_n569), .B(
genblk1_right_mult_x_1_n576), .Y(n3812) );
NOR2X1TS U3725 ( .A(genblk1_right_mult_x_1_n562), .B(
genblk1_right_mult_x_1_n568), .Y(n2849) );
OR2X2TS U3726 ( .A(genblk1_right_mult_x_1_n577), .B(
genblk1_right_mult_x_1_n585), .Y(n2855) );
NAND2X1TS U3727 ( .A(n989), .B(n2855), .Y(n991) );
OR2X2TS U3728 ( .A(genblk1_right_mult_x_1_n586), .B(
genblk1_right_mult_x_1_n594), .Y(n3844) );
NAND2X1TS U3729 ( .A(n3848), .B(n3844), .Y(n2847) );
NOR2X1TS U3730 ( .A(genblk1_right_mult_x_1_n549), .B(
genblk1_right_mult_x_1_n554), .Y(n3820) );
NAND2X1TS U3731 ( .A(n2838), .B(n2843), .Y(n2832) );
NOR2X1TS U3732 ( .A(n2832), .B(n2833), .Y(n994) );
NAND2X1TS U3733 ( .A(n2827), .B(n994), .Y(n996) );
NOR2X1TS U3734 ( .A(n2826), .B(n996), .Y(n998) );
NAND2X1TS U3735 ( .A(genblk1_right_mult_x_1_n659), .B(
genblk1_right_mult_x_1_n670), .Y(n3855) );
NAND2X1TS U3736 ( .A(genblk1_right_mult_x_1_n647), .B(
genblk1_right_mult_x_1_n658), .Y(n2867) );
NAND2X1TS U3737 ( .A(genblk1_right_mult_x_1_n646), .B(
genblk1_right_mult_x_1_n635), .Y(n3851) );
INVX2TS U3738 ( .A(n3851), .Y(n3835) );
NAND2X1TS U3739 ( .A(genblk1_right_mult_x_1_n624), .B(
genblk1_right_mult_x_1_n634), .Y(n3837) );
INVX2TS U3740 ( .A(n3837), .Y(n981) );
AOI21X1TS U3741 ( .A0(n3835), .A1(n3838), .B0(n981), .Y(n2862) );
NAND2X1TS U3742 ( .A(genblk1_right_mult_x_1_n614), .B(
genblk1_right_mult_x_1_n623), .Y(n2864) );
INVX2TS U3743 ( .A(n2864), .Y(n3829) );
NAND2X1TS U3744 ( .A(genblk1_right_mult_x_1_n604), .B(
genblk1_right_mult_x_1_n613), .Y(n3832) );
INVX2TS U3745 ( .A(n3832), .Y(n982) );
AOI21X1TS U3746 ( .A0(n364), .A1(n3829), .B0(n982), .Y(n983) );
AOI21X1TS U3747 ( .A0(n2859), .A1(n986), .B0(n985), .Y(n2825) );
NAND2X1TS U3748 ( .A(genblk1_right_mult_x_1_n595), .B(
genblk1_right_mult_x_1_n603), .Y(n3847) );
INVX2TS U3749 ( .A(n3847), .Y(n3841) );
NAND2X1TS U3750 ( .A(genblk1_right_mult_x_1_n586), .B(
genblk1_right_mult_x_1_n594), .Y(n3843) );
INVX2TS U3751 ( .A(n3843), .Y(n987) );
NAND2X1TS U3752 ( .A(genblk1_right_mult_x_1_n577), .B(
genblk1_right_mult_x_1_n585), .Y(n2854) );
INVX2TS U3753 ( .A(n2854), .Y(n2848) );
NAND2X1TS U3754 ( .A(genblk1_right_mult_x_1_n569), .B(
genblk1_right_mult_x_1_n576), .Y(n3813) );
NAND2X1TS U3755 ( .A(genblk1_right_mult_x_1_n562), .B(
genblk1_right_mult_x_1_n568), .Y(n2850) );
AOI21X1TS U3756 ( .A0(n989), .A1(n2848), .B0(n988), .Y(n990) );
NAND2X1TS U3757 ( .A(genblk1_right_mult_x_1_n561), .B(
genblk1_right_mult_x_1_n555), .Y(n3825) );
NAND2X1TS U3758 ( .A(genblk1_right_mult_x_1_n549), .B(
genblk1_right_mult_x_1_n554), .Y(n3821) );
NAND2X1TS U3759 ( .A(genblk1_right_mult_x_1_n543), .B(
genblk1_right_mult_x_1_n548), .Y(n2842) );
INVX2TS U3760 ( .A(n2842), .Y(n992) );
AOI21X1TS U3761 ( .A0(n2839), .A1(n2843), .B0(n992), .Y(n2831) );
NAND2X1TS U3762 ( .A(genblk1_right_mult_x_1_n542), .B(
genblk1_right_mult_x_1_n537), .Y(n2834) );
AOI21X1TS U3763 ( .A0(n2828), .A1(n994), .B0(n993), .Y(n995) );
OAI21X1TS U3764 ( .A0(n2825), .A1(n996), .B0(n995), .Y(n997) );
NAND2X1TS U3765 ( .A(n1000), .B(n1103), .Y(n1001) );
CLKBUFX2TS U3766 ( .A(n2791), .Y(n2739) );
AOI222X1TS U3767 ( .A0(n293), .A1(n2670), .B0(n2738), .B1(n2739), .C0(n304),
.C1(n2419), .Y(n1003) );
XOR2X1TS U3768 ( .A(n1004), .B(n2743), .Y(n1017) );
NAND2X1TS U3769 ( .A(n1008), .B(n1007), .Y(n1009) );
XOR2X1TS U3770 ( .A(n1010), .B(n1009), .Y(n2764) );
CLKBUFX2TS U3771 ( .A(n1078), .Y(n2761) );
CLKBUFX2TS U3772 ( .A(n1023), .Y(n2228) );
OAI21XLTS U3773 ( .A0(n2648), .A1(n2764), .B0(n1011), .Y(n1012) );
ADDHXLTS U3774 ( .A(n1014), .B(n1013), .CO(n1338), .S(n1015) );
NAND2X1TS U3775 ( .A(n1020), .B(n1019), .Y(n1021) );
XNOR2X1TS U3776 ( .A(n1022), .B(n1021), .Y(n2361) );
CLKBUFX2TS U3777 ( .A(n1023), .Y(n2700) );
AOI222X1TS U3778 ( .A0(n2762), .A1(n2700), .B0(n311), .B1(n2227), .C0(n2759),
.C1(n2645), .Y(n1024) );
XOR2X1TS U3779 ( .A(n1052), .B(n1754), .Y(n1055) );
NOR2X1TS U3780 ( .A(n1055), .B(n1054), .Y(n1372) );
CLKBUFX2TS U3781 ( .A(n1372), .Y(n2703) );
XNOR2X1TS U3782 ( .A(n1052), .B(n1051), .Y(n1053) );
NOR2BX2TS U3783 ( .AN(n1054), .B(n1053), .Y(n2550) );
AND3X2TS U3784 ( .A(n1055), .B(n1054), .C(n1053), .Y(n2479) );
CLKBUFX2TS U3785 ( .A(n1949), .Y(n2711) );
XNOR2X1TS U3786 ( .A(n1059), .B(n1058), .Y(n1061) );
AOI222XLTS U3787 ( .A0(n2711), .A1(n2761), .B0(n2710), .B1(n2228), .C0(n2708), .C1(n2729), .Y(n1063) );
CLKBUFX2TS U3788 ( .A(n1067), .Y(n2416) );
AOI22X1TS U3789 ( .A0(n2738), .A1(n2691), .B0(n2416), .B1(n2645), .Y(n1065)
);
XOR2X1TS U3790 ( .A(n1066), .B(n2743), .Y(n1757) );
XOR2X1TS U3791 ( .A(n1068), .B(n2743), .Y(n1767) );
AOI21X1TS U3792 ( .A0(n1073), .A1(n346), .B0(n1072), .Y(n1077) );
NAND2X1TS U3793 ( .A(n1075), .B(n1074), .Y(n1076) );
CLKBUFX2TS U3794 ( .A(n2146), .Y(n2737) );
CLKBUFX2TS U3795 ( .A(n1078), .Y(n2803) );
AOI222X1TS U3796 ( .A0(n2348), .A1(n2739), .B0(n295), .B1(n2737), .C0(n308),
.C1(n2803), .Y(n1079) );
OAI21X1TS U3797 ( .A0(n345), .A1(n2664), .B0(n1079), .Y(n1080) );
AOI21X4TS U3798 ( .A0(n1085), .A1(n1110), .B0(n1084), .Y(n1086) );
OAI21X4TS U3799 ( .A0(n1088), .A1(n1087), .B0(n1086), .Y(n1572) );
CLKBUFX2TS U3800 ( .A(n1904), .Y(n2488) );
INVX2TS U3801 ( .A(n2161), .Y(n2166) );
NOR2X1TS U3802 ( .A(n1102), .B(n1101), .Y(n1106) );
NAND2X1TS U3803 ( .A(n1104), .B(n1103), .Y(n1105) );
INVX2TS U3804 ( .A(n1128), .Y(n1112) );
XOR2X1TS U3805 ( .A(n1119), .B(n1118), .Y(n1985) );
BUFX3TS U3806 ( .A(n2563), .Y(n2579) );
NOR2X1TS U3807 ( .A(n1985), .B(n2579), .Y(n2065) );
NOR2X1TS U3808 ( .A(n2579), .B(n2573), .Y(n1909) );
NOR2X1TS U3809 ( .A(n2065), .B(n1909), .Y(n1138) );
XOR2X1TS U3810 ( .A(n1136), .B(n1135), .Y(n2070) );
NOR2X1TS U3811 ( .A(n1971), .B(n1771), .Y(n1908) );
NAND2X1TS U3812 ( .A(n1138), .B(n1908), .Y(n1140) );
NAND2X1TS U3813 ( .A(n2070), .B(n1985), .Y(n1972) );
NAND2X1TS U3814 ( .A(n2070), .B(n1916), .Y(n1967) );
NAND2X1TS U3815 ( .A(n1972), .B(n1967), .Y(n1907) );
NAND2X1TS U3816 ( .A(n2579), .B(n2573), .Y(n1910) );
NAND2X1TS U3817 ( .A(n1985), .B(n2579), .Y(n2066) );
NAND2X1TS U3818 ( .A(n1910), .B(n2066), .Y(n1137) );
AOI21X1TS U3819 ( .A0(n1138), .A1(n1907), .B0(n1137), .Y(n1139) );
OAI21X2TS U3820 ( .A0(n1770), .A1(n1140), .B0(n1139), .Y(n1564) );
NOR2X1TS U3821 ( .A(n2573), .B(n1904), .Y(n2095) );
INVX2TS U3822 ( .A(n1148), .Y(n1141) );
NOR2X1TS U3823 ( .A(n2095), .B(n1899), .Y(n1889) );
INVX2TS U3824 ( .A(n1554), .Y(n1894) );
NAND2X1TS U3825 ( .A(n1889), .B(n1894), .Y(n1159) );
NAND2X1TS U3826 ( .A(n1904), .B(n1936), .Y(n1900) );
NAND2X1TS U3827 ( .A(n2573), .B(n1904), .Y(n2096) );
NAND2X1TS U3828 ( .A(n1900), .B(n2096), .Y(n1890) );
NAND2X1TS U3829 ( .A(n1936), .B(n2475), .Y(n1893) );
AOI21X1TS U3830 ( .A0(n1890), .A1(n1894), .B0(n1157), .Y(n1158) );
NOR2X1TS U3831 ( .A(n1956), .B(n2475), .Y(n1555) );
NAND2X1TS U3832 ( .A(n1956), .B(n2475), .Y(n1556) );
NAND2X1TS U3833 ( .A(n1166), .B(n1556), .Y(n1167) );
CLKBUFX2TS U3834 ( .A(n1956), .Y(n2493) );
CLKBUFX2TS U3835 ( .A(n1936), .Y(n2539) );
AOI222XLTS U3836 ( .A0(n2762), .A1(n2493), .B0(n2760), .B1(n2006), .C0(n2759), .C1(n2539), .Y(n1169) );
XOR2X1TS U3837 ( .A(n1170), .B(n2766), .Y(n1171) );
XNOR2X1TS U3838 ( .A(n1175), .B(n1174), .Y(genblk1_left_N50) );
INVX2TS U3839 ( .A(n2336), .Y(n1181) );
INVX2TS U3840 ( .A(result_A_adder_2_), .Y(n1182) );
NOR2X1TS U3841 ( .A(genblk1_middle_mult_x_1_n913), .B(
genblk1_middle_mult_x_1_n922), .Y(n2585) );
NOR2X1TS U3842 ( .A(n1716), .B(n2585), .Y(n1313) );
NOR2X2TS U3843 ( .A(genblk1_middle_mult_x_1_n931), .B(
genblk1_middle_mult_x_1_n938), .Y(n1722) );
NOR2X1TS U3844 ( .A(genblk1_middle_mult_x_1_n946), .B(
genblk1_middle_mult_x_1_n939), .Y(n2609) );
NOR2X1TS U3845 ( .A(n1722), .B(n2609), .Y(n1311) );
NOR2X1TS U3846 ( .A(genblk1_middle_mult_x_1_n954), .B(
genblk1_middle_mult_x_1_n960), .Y(n1183) );
INVX2TS U3847 ( .A(n1183), .Y(n2604) );
NAND2X1TS U3848 ( .A(n2604), .B(n357), .Y(n1309) );
NOR2X1TS U3849 ( .A(genblk1_middle_mult_x_1_n973), .B(
genblk1_middle_mult_x_1_n977), .Y(n2619) );
XNOR2X1TS U3850 ( .A(n2336), .B(n1206), .Y(n1237) );
BUFX3TS U3851 ( .A(n2025), .Y(n2328) );
NOR2X2TS U3852 ( .A(n1237), .B(n1238), .Y(n2439) );
XNOR2X1TS U3853 ( .A(n1207), .B(n1206), .Y(n1236) );
NOR2BX2TS U3854 ( .AN(n1237), .B(n1236), .Y(n2427) );
CLKBUFX2TS U3855 ( .A(n2427), .Y(n2555) );
AOI22X1TS U3856 ( .A0(n2439), .A1(n2808), .B0(n2555), .B1(n2691), .Y(n1208)
);
INVX2TS U3857 ( .A(n2654), .Y(n2724) );
OAI21X1TS U3858 ( .A0(n2328), .A1(n424), .B0(n368), .Y(n1210) );
XOR2X1TS U3859 ( .A(n1210), .B(n2724), .Y(n1246) );
INVX2TS U3860 ( .A(n1224), .Y(n1226) );
XOR2X1TS U3861 ( .A(n2336), .B(n1230), .Y(n1233) );
NOR2X1TS U3862 ( .A(n1233), .B(n1231), .Y(n1258) );
CLKBUFX2TS U3863 ( .A(n1258), .Y(n2569) );
XNOR2X1TS U3864 ( .A(n1230), .B(n1229), .Y(n1232) );
NOR2BX2TS U3865 ( .AN(n1231), .B(n1232), .Y(n2532) );
CLKBUFX2TS U3866 ( .A(n2532), .Y(n2769) );
CLKBUFX2TS U3867 ( .A(n2793), .Y(n2386) );
AOI222XLTS U3868 ( .A0(n2569), .A1(n2419), .B0(n2769), .B1(n2719), .C0(n2386), .C1(n2700), .Y(n1234) );
INVX2TS U3869 ( .A(n1181), .Y(n2080) );
CLKBUFX2TS U3870 ( .A(n2439), .Y(n2462) );
CLKBUFX2TS U3871 ( .A(n2227), .Y(n2359) );
CLKBUFX2TS U3872 ( .A(n2427), .Y(n2720) );
CLKBUFX2TS U3873 ( .A(n2727), .Y(n2709) );
CLKBUFX2TS U3874 ( .A(n2426), .Y(n2718) );
XOR2X1TS U3875 ( .A(n1240), .B(n2724), .Y(n1788) );
CLKBUFX2TS U3876 ( .A(n1916), .Y(n2776) );
CLKBUFX2TS U3877 ( .A(n2543), .Y(n2592) );
CLKBUFX2TS U3878 ( .A(n1286), .Y(n2582) );
NOR2BX1TS U3879 ( .AN(n566), .B(n1242), .Y(n2541) );
CLKBUFX2TS U3880 ( .A(n2541), .Y(n2591) );
CLKBUFX2TS U3881 ( .A(n301), .Y(n2590) );
AOI222XLTS U3882 ( .A0(n2776), .A1(n2352), .B0(n2582), .B1(n2591), .C0(n2590), .C1(n2669), .Y(n1244) );
INVX2TS U3883 ( .A(n1182), .Y(n2596) );
OR2X2TS U3884 ( .A(genblk1_middle_mult_x_1_n978), .B(n1303), .Y(n1737) );
ADDHXLTS U3885 ( .A(n2193), .B(n1246), .CO(n1284), .S(n1291) );
AOI222XLTS U3886 ( .A0(n1258), .A1(n2228), .B0(n2769), .B1(n2359), .C0(n2386), .C1(n2645), .Y(n1247) );
OAI21XLTS U3887 ( .A0(n2361), .A1(n2409), .B0(n1247), .Y(n1248) );
AOI222XLTS U3888 ( .A0(n2352), .A1(n2669), .B0(n2419), .B1(n2591), .C0(n2590), .C1(n2761), .Y(n1249) );
CLKBUFX2TS U3889 ( .A(n2541), .Y(n2351) );
AOI222XLTS U3890 ( .A0(n2352), .A1(n2419), .B0(n2351), .B1(n2719), .C0(n301),
.C1(n2700), .Y(n1251) );
INVX2TS U3891 ( .A(n1182), .Y(n2576) );
AOI222XLTS U3892 ( .A0(n2569), .A1(n2359), .B0(n2769), .B1(n2709), .C0(n2386), .C1(n2806), .Y(n1253) );
OAI21XLTS U3893 ( .A0(n2732), .A1(n2409), .B0(n1253), .Y(n1254) );
XOR2X1TS U3894 ( .A(n1254), .B(n2080), .Y(n1273) );
AOI222XLTS U3895 ( .A0(n2592), .A1(n2228), .B0(n2351), .B1(n2359), .C0(n300),
.C1(n2645), .Y(n1255) );
XOR2X1TS U3896 ( .A(n1256), .B(n2576), .Y(n1270) );
CLKBUFX2TS U3897 ( .A(n1258), .Y(n2407) );
AOI222XLTS U3898 ( .A0(n2592), .A1(n2359), .B0(n2351), .B1(n2709), .C0(n300),
.C1(n2806), .Y(n1260) );
OAI21XLTS U3899 ( .A0(n2732), .A1(n2546), .B0(n1260), .Y(n1261) );
XNOR2X1TS U3900 ( .A(n1261), .B(n2576), .Y(n2640) );
CLKAND2X2TS U3901 ( .A(n1263), .B(n4983), .Y(n1751) );
NAND2X1TS U3902 ( .A(n1750), .B(n1751), .Y(n2639) );
NOR2X1TS U3903 ( .A(n2640), .B(n2639), .Y(n1748) );
NAND2X1TS U3904 ( .A(n1265), .B(n1264), .Y(n1746) );
INVX2TS U3905 ( .A(n1746), .Y(n1266) );
AOI21X1TS U3906 ( .A0(n1747), .A1(n1748), .B0(n1266), .Y(n2637) );
AOI222XLTS U3907 ( .A0(n2352), .A1(n2719), .B0(n2351), .B1(n2228), .C0(n300),
.C1(n2729), .Y(n1267) );
NAND2X1TS U3908 ( .A(n1272), .B(n1271), .Y(n2635) );
OAI21X1TS U3909 ( .A0(n2637), .A1(n2634), .B0(n2635), .Y(n1744) );
ADDHXLTS U3910 ( .A(n1274), .B(n1273), .CO(n1280), .S(n1278) );
NAND2X1TS U3911 ( .A(n1278), .B(n1277), .Y(n1743) );
INVX2TS U3912 ( .A(n1743), .Y(n1279) );
AOI21X1TS U3913 ( .A0(n1744), .A1(n355), .B0(n1279), .Y(n2632) );
NAND2X1TS U3914 ( .A(n1281), .B(n1280), .Y(n2630) );
AOI222XLTS U3915 ( .A0(n2569), .A1(n2719), .B0(n2769), .B1(n2228), .C0(n2386), .C1(n2729), .Y(n1282) );
XOR2X1TS U3916 ( .A(n1283), .B(n2080), .Y(n1300) );
ADDHXLTS U3917 ( .A(n1285), .B(n1284), .CO(n1297), .S(n1299) );
CLKBUFX2TS U3918 ( .A(n1286), .Y(n2746) );
AOI222XLTS U3919 ( .A0(n2746), .A1(n2592), .B0(n2669), .B1(n2591), .C0(n2590), .C1(n2419), .Y(n1287) );
NAND2X1TS U3920 ( .A(n1293), .B(n1292), .Y(n1740) );
INVX2TS U3921 ( .A(n1740), .Y(n1294) );
AOI21X1TS U3922 ( .A0(n1741), .A1(n315), .B0(n1294), .Y(n2628) );
CMPR32X2TS U3923 ( .A(n1297), .B(n1296), .C(n1295), .CO(n1303), .S(n1302) );
CMPR32X2TS U3924 ( .A(n1300), .B(n1299), .C(n1298), .CO(n1301), .S(n1293) );
NOR2X1TS U3925 ( .A(n1302), .B(n1301), .Y(n2624) );
NAND2X1TS U3926 ( .A(n1302), .B(n1301), .Y(n2625) );
OAI21X1TS U3927 ( .A0(n2628), .A1(n2624), .B0(n2625), .Y(n1738) );
NAND2X1TS U3928 ( .A(genblk1_middle_mult_x_1_n978), .B(n1303), .Y(n1736) );
INVX2TS U3929 ( .A(n1736), .Y(n1304) );
NAND2X1TS U3930 ( .A(genblk1_middle_mult_x_1_n973), .B(
genblk1_middle_mult_x_1_n977), .Y(n2620) );
OAI21X2TS U3931 ( .A0(n2619), .A1(n2622), .B0(n2620), .Y(n1730) );
NOR2X1TS U3932 ( .A(genblk1_middle_mult_x_1_n961), .B(
genblk1_middle_mult_x_1_n967), .Y(n1731) );
NOR2X1TS U3933 ( .A(genblk1_middle_mult_x_1_n968), .B(
genblk1_middle_mult_x_1_n972), .Y(n2614) );
NOR2X1TS U3934 ( .A(n1731), .B(n2614), .Y(n1306) );
NAND2X1TS U3935 ( .A(genblk1_middle_mult_x_1_n961), .B(
genblk1_middle_mult_x_1_n967), .Y(n1732) );
OAI21X1TS U3936 ( .A0(n1731), .A1(n2615), .B0(n1732), .Y(n1305) );
NAND2X1TS U3937 ( .A(genblk1_middle_mult_x_1_n954), .B(
genblk1_middle_mult_x_1_n960), .Y(n1728) );
INVX2TS U3938 ( .A(n1728), .Y(n2603) );
NAND2X1TS U3939 ( .A(genblk1_middle_mult_x_1_n947), .B(
genblk1_middle_mult_x_1_n953), .Y(n2606) );
INVX2TS U3940 ( .A(n2606), .Y(n1307) );
NAND2X1TS U3941 ( .A(genblk1_middle_mult_x_1_n939), .B(
genblk1_middle_mult_x_1_n946), .Y(n2610) );
NAND2X1TS U3942 ( .A(genblk1_middle_mult_x_1_n931), .B(
genblk1_middle_mult_x_1_n938), .Y(n1723) );
OAI21X1TS U3943 ( .A0(n1722), .A1(n2610), .B0(n1723), .Y(n1310) );
NAND2X1TS U3944 ( .A(genblk1_middle_mult_x_1_n923), .B(
genblk1_middle_mult_x_1_n930), .Y(n2599) );
OAI21X2TS U3945 ( .A0(n2602), .A1(n2598), .B0(n2599), .Y(n1715) );
NAND2X1TS U3946 ( .A(genblk1_middle_mult_x_1_n903), .B(
genblk1_middle_mult_x_1_n912), .Y(n1717) );
OR2X2TS U3947 ( .A(genblk1_middle_mult_x_1_n882), .B(
genblk1_middle_mult_x_1_n892), .Y(n2470) );
NAND2X2TS U3948 ( .A(n356), .B(n2470), .Y(n1316) );
INVX2TS U3949 ( .A(n1713), .Y(n2467) );
NAND2X1TS U3950 ( .A(genblk1_middle_mult_x_1_n882), .B(
genblk1_middle_mult_x_1_n892), .Y(n2469) );
INVX2TS U3951 ( .A(n2469), .Y(n1314) );
OR2X4TS U3952 ( .A(genblk1_middle_mult_x_1_n834), .B(
genblk1_middle_mult_x_1_n846), .Y(n2368) );
OR2X2TS U3953 ( .A(genblk1_middle_mult_x_1_n847), .B(
genblk1_middle_mult_x_1_n859), .Y(n2365) );
NAND2X2TS U3954 ( .A(n2368), .B(n2365), .Y(n1321) );
NOR2X1TS U3955 ( .A(genblk1_middle_mult_x_1_n871), .B(
genblk1_middle_mult_x_1_n881), .Y(n1707) );
INVX2TS U3956 ( .A(n1707), .Y(n2380) );
NAND2X1TS U3957 ( .A(n1709), .B(n2380), .Y(n1704) );
NOR2X2TS U3958 ( .A(n1321), .B(n1704), .Y(n1323) );
NAND2X1TS U3959 ( .A(genblk1_middle_mult_x_1_n871), .B(
genblk1_middle_mult_x_1_n881), .Y(n2379) );
NAND2X1TS U3960 ( .A(genblk1_middle_mult_x_1_n860), .B(
genblk1_middle_mult_x_1_n870), .Y(n1708) );
INVX2TS U3961 ( .A(n1708), .Y(n1317) );
NAND2X1TS U3962 ( .A(genblk1_middle_mult_x_1_n847), .B(
genblk1_middle_mult_x_1_n859), .Y(n1705) );
INVX2TS U3963 ( .A(n1705), .Y(n2364) );
NAND2X1TS U3964 ( .A(genblk1_middle_mult_x_1_n834), .B(
genblk1_middle_mult_x_1_n846), .Y(n2367) );
INVX2TS U3965 ( .A(n2367), .Y(n1319) );
OAI21X2TS U3966 ( .A0(n1321), .A1(n1703), .B0(n1320), .Y(n1322) );
NOR2X2TS U3967 ( .A(genblk1_middle_mult_x_1_n797), .B(
genblk1_middle_mult_x_1_n808), .Y(n2293) );
NOR2X2TS U3968 ( .A(genblk1_middle_mult_x_1_n809), .B(
genblk1_middle_mult_x_1_n820), .Y(n2306) );
NOR2X1TS U3969 ( .A(genblk1_middle_mult_x_1_n821), .B(
genblk1_middle_mult_x_1_n833), .Y(n1700) );
NOR2X1TS U3970 ( .A(n2306), .B(n1700), .Y(n1694) );
NAND2X1TS U3971 ( .A(n1325), .B(n1694), .Y(n1327) );
NAND2X1TS U3972 ( .A(genblk1_middle_mult_x_1_n821), .B(
genblk1_middle_mult_x_1_n833), .Y(n2303) );
NAND2X1TS U3973 ( .A(genblk1_middle_mult_x_1_n809), .B(
genblk1_middle_mult_x_1_n820), .Y(n2307) );
OAI21X1TS U3974 ( .A0(n2306), .A1(n2303), .B0(n2307), .Y(n1693) );
NAND2X1TS U3975 ( .A(genblk1_middle_mult_x_1_n785), .B(
genblk1_middle_mult_x_1_n796), .Y(n1696) );
OAI21X2TS U3976 ( .A0(n1692), .A1(n1327), .B0(n1326), .Y(n1680) );
NOR2X2TS U3977 ( .A(genblk1_middle_mult_x_1_n737), .B(
genblk1_middle_mult_x_1_n748), .Y(n2279) );
NOR2X1TS U3978 ( .A(n1685), .B(n2279), .Y(n1329) );
NOR2X1TS U3979 ( .A(n2298), .B(n1687), .Y(n1681) );
NAND2X1TS U3980 ( .A(n1329), .B(n1681), .Y(n1379) );
NAND2X2TS U3981 ( .A(genblk1_middle_mult_x_1_n773), .B(
genblk1_middle_mult_x_1_n784), .Y(n2299) );
NAND2X1TS U3982 ( .A(genblk1_middle_mult_x_1_n761), .B(
genblk1_middle_mult_x_1_n772), .Y(n1688) );
NAND2X1TS U3983 ( .A(genblk1_middle_mult_x_1_n737), .B(
genblk1_middle_mult_x_1_n748), .Y(n2280) );
CLKINVX1TS U3984 ( .A(n1386), .Y(n1330) );
INVX2TS U3985 ( .A(n1621), .Y(n1679) );
NAND2X1TS U3986 ( .A(genblk1_middle_mult_x_1_n713), .B(
genblk1_middle_mult_x_1_n724), .Y(n1380) );
NAND2X1TS U3987 ( .A(n1333), .B(n1380), .Y(n1334) );
OAI2BB1X1TS U3988 ( .A0N(n1339), .A1N(n1338), .B0(n1337), .Y(
genblk1_middle_mult_x_1_n828) );
INVX2TS U3989 ( .A(n2567), .Y(n1340) );
CLKBUFX2TS U3990 ( .A(n2550), .Y(n2503) );
BUFX3TS U3991 ( .A(n1372), .Y(n2498) );
CLKBUFX2TS U3992 ( .A(n2439), .Y(n2721) );
INVX2TS U3993 ( .A(n1360), .Y(n1362) );
NOR2BX2TS U3994 ( .AN(n1367), .B(n1368), .Y(n2443) );
CLKBUFX2TS U3995 ( .A(n1372), .Y(n2695) );
XOR2X1TS U3996 ( .A(n1374), .B(n2706), .Y(n1778) );
NOR2X2TS U3997 ( .A(genblk1_middle_mult_x_1_n692), .B(
genblk1_middle_mult_x_1_n701), .Y(n1622) );
NOR2X1TS U3998 ( .A(genblk1_middle_mult_x_1_n702), .B(
genblk1_middle_mult_x_1_n712), .Y(n1616) );
NOR2X1TS U3999 ( .A(n1622), .B(n1616), .Y(n1383) );
NAND2X1TS U4000 ( .A(n1617), .B(n1383), .Y(n1385) );
NOR2X1TS U4001 ( .A(n1379), .B(n1385), .Y(n1389) );
NAND2X1TS U4002 ( .A(genblk1_middle_mult_x_1_n702), .B(
genblk1_middle_mult_x_1_n712), .Y(n1672) );
NAND2X1TS U4003 ( .A(genblk1_middle_mult_x_1_n692), .B(
genblk1_middle_mult_x_1_n701), .Y(n1623) );
AOI21X1TS U4004 ( .A0(n1383), .A1(n1618), .B0(n1382), .Y(n1384) );
OAI21X1TS U4005 ( .A0(n1386), .A1(n1385), .B0(n1384), .Y(n1387) );
INVX2TS U4006 ( .A(n1387), .Y(n1388) );
OAI2BB1X4TS U4007 ( .A0N(n1389), .A1N(n1680), .B0(n1388), .Y(n1390) );
NOR2X1TS U4008 ( .A(genblk1_middle_mult_x_1_n682), .B(
genblk1_middle_mult_x_1_n691), .Y(n1670) );
NOR2X1TS U4009 ( .A(n2265), .B(n1670), .Y(n1608) );
NAND2X2TS U4010 ( .A(n1608), .B(n1393), .Y(n1638) );
NAND2X1TS U4011 ( .A(n1391), .B(n1396), .Y(n1399) );
NAND2X1TS U4012 ( .A(genblk1_middle_mult_x_1_n682), .B(
genblk1_middle_mult_x_1_n691), .Y(n2262) );
NAND2X1TS U4013 ( .A(genblk1_middle_mult_x_1_n673), .B(
genblk1_middle_mult_x_1_n681), .Y(n2266) );
OAI21X1TS U4014 ( .A0(n2265), .A1(n2262), .B0(n2266), .Y(n1609) );
NAND2X1TS U4015 ( .A(genblk1_middle_mult_x_1_n664), .B(
genblk1_middle_mult_x_1_n672), .Y(n2150) );
NAND2X1TS U4016 ( .A(genblk1_middle_mult_x_1_n655), .B(
genblk1_middle_mult_x_1_n663), .Y(n1613) );
OAI21X1TS U4017 ( .A0(n1612), .A1(n2150), .B0(n1613), .Y(n1392) );
NAND2X1TS U4018 ( .A(genblk1_middle_mult_x_1_n647), .B(
genblk1_middle_mult_x_1_n654), .Y(n1666) );
INVX2TS U4019 ( .A(n1666), .Y(n1450) );
NAND2X1TS U4020 ( .A(genblk1_middle_mult_x_1_n640), .B(
genblk1_middle_mult_x_1_n646), .Y(n1451) );
AOI21X1TS U4021 ( .A0(n1397), .A1(n1396), .B0(n1395), .Y(n1398) );
OR2X2TS U4022 ( .A(genblk1_middle_mult_x_1_n633), .B(
genblk1_middle_mult_x_1_n639), .Y(n2112) );
NAND2X1TS U4023 ( .A(genblk1_middle_mult_x_1_n633), .B(
genblk1_middle_mult_x_1_n639), .Y(n2111) );
INVX2TS U4024 ( .A(n2111), .Y(n1464) );
OR2X2TS U4025 ( .A(genblk1_middle_mult_x_1_n627), .B(
genblk1_middle_mult_x_1_n632), .Y(n1465) );
NAND2X1TS U4026 ( .A(genblk1_middle_mult_x_1_n627), .B(
genblk1_middle_mult_x_1_n632), .Y(n1462) );
NAND2X1TS U4027 ( .A(n1465), .B(n1462), .Y(n1400) );
INVX2TS U4028 ( .A(n1444), .Y(n1442) );
NOR2XLTS U4029 ( .A(n209), .B(n205), .Y(n3244) );
NOR2X1TS U4030 ( .A(n3213), .B(n3219), .Y(n3203) );
NAND2X1TS U4031 ( .A(n3203), .B(n1406), .Y(n1408) );
NOR2X1TS U4032 ( .A(n3228), .B(n1408), .Y(n1410) );
NAND2X1TS U4033 ( .A(n214), .B(n219), .Y(n2991) );
NAND2X1TS U4034 ( .A(n2991), .B(n2988), .Y(n3240) );
NAND2X1TS U4035 ( .A(n211), .B(n207), .Y(n3245) );
NAND2X1TS U4036 ( .A(n215), .B(n210), .Y(n3237) );
NAND2X1TS U4037 ( .A(n3245), .B(n3237), .Y(n1403) );
AOI21X1TS U4038 ( .A0(n1404), .A1(n3240), .B0(n1403), .Y(n3227) );
NAND2X1TS U4039 ( .A(n131), .B(n136), .Y(n3220) );
NAND2X1TS U4040 ( .A(n132), .B(n206), .Y(n3229) );
NAND2X1TS U4041 ( .A(n3220), .B(n3229), .Y(n3202) );
NAND2X1TS U4042 ( .A(n144), .B(n139), .Y(n2966) );
NAND2X1TS U4043 ( .A(n135), .B(n140), .Y(n3207) );
NAND2X1TS U4044 ( .A(n2966), .B(n3207), .Y(n1405) );
AOI21X1TS U4045 ( .A0(n1406), .A1(n3202), .B0(n1405), .Y(n1407) );
NOR2X1TS U4046 ( .A(n3196), .B(n3189), .Y(n3179) );
NOR2XLTS U4047 ( .A(n249), .B(n154), .Y(n3172) );
NOR2X1TS U4048 ( .A(n3168), .B(n3172), .Y(n1414) );
NOR2XLTS U4049 ( .A(n154), .B(Data_B_i[20]), .Y(n3146) );
NOR2XLTS U4050 ( .A(n162), .B(Data_B_i[20]), .Y(n3152) );
NOR2X1TS U4051 ( .A(n3146), .B(n3152), .Y(n3136) );
NOR2XLTS U4052 ( .A(n166), .B(n170), .Y(n3128) );
NOR2XLTS U4053 ( .A(n3139), .B(n3128), .Y(n1416) );
NAND2X1TS U4054 ( .A(n3136), .B(n1416), .Y(n1418) );
NOR2XLTS U4055 ( .A(n1412), .B(n3094), .Y(n1421) );
NAND2X1TS U4056 ( .A(n3112), .B(n1421), .Y(n1423) );
NAND2X1TS U4057 ( .A(n148), .B(n151), .Y(n3190) );
NAND2X1TS U4058 ( .A(n143), .B(n146), .Y(n3197) );
NAND2X1TS U4059 ( .A(n3190), .B(n3197), .Y(n3180) );
NAND2X1TS U4060 ( .A(n250), .B(n155), .Y(n3173) );
NAND2X1TS U4061 ( .A(n251), .B(n152), .Y(n3183) );
NAND2X1TS U4062 ( .A(n3173), .B(n3183), .Y(n1413) );
AOI21X1TS U4063 ( .A0(n1414), .A1(n3180), .B0(n1413), .Y(n3159) );
NAND2X1TS U4064 ( .A(n164), .B(n160), .Y(n3153) );
NAND2X1TS U4065 ( .A(n156), .B(n158), .Y(n3161) );
NAND2X1TS U4066 ( .A(n3153), .B(n3161), .Y(n3135) );
NAND2X1TS U4067 ( .A(n167), .B(n172), .Y(n3129) );
NAND2X1TS U4068 ( .A(n163), .B(n168), .Y(n3140) );
NAND2X1TS U4069 ( .A(n3129), .B(n3140), .Y(n1415) );
AOI21X1TS U4070 ( .A0(n1416), .A1(n3135), .B0(n1415), .Y(n1417) );
NAND2X1TS U4071 ( .A(n127), .B(n174), .Y(n3106) );
NAND2X1TS U4072 ( .A(n126), .B(n170), .Y(n3116) );
NAND2X1TS U4073 ( .A(n3106), .B(n3116), .Y(n3090) );
NAND2X1TS U4074 ( .A(n174), .B(n42), .Y(n3095) );
OAI21XLTS U4075 ( .A0(n1419), .A1(n3094), .B0(n3095), .Y(n1420) );
AOI21X1TS U4076 ( .A0(n3113), .A1(n1421), .B0(n1420), .Y(n1422) );
XNOR2X1TS U4077 ( .A(n254), .B(Data_A_i[24]), .Y(n2970) );
CLKBUFX2TS U4078 ( .A(n2983), .Y(n3166) );
XNOR2X1TS U4079 ( .A(Data_A_i[24]), .B(Data_A_i[25]), .Y(n1425) );
NOR2BX1TS U4080 ( .AN(n2970), .B(n1425), .Y(n3256) );
CLKBUFX2TS U4081 ( .A(n3256), .Y(n3224) );
AOI21X1TS U4082 ( .A0(n298), .A1(n175), .B0(n1426), .Y(n1427) );
XNOR2X1TS U4083 ( .A(n1440), .B(n1429), .Y(genblk1_right_N51) );
CLKAND2X2TS U4084 ( .A(n289), .B(Data_B_i[25]), .Y(n1443) );
NAND2X1TS U4085 ( .A(n3112), .B(n1433), .Y(n1435) );
AOI21X1TS U4086 ( .A0(n3113), .A1(n1433), .B0(n1432), .Y(n1434) );
NAND2X1TS U4087 ( .A(n299), .B(Data_B_i[26]), .Y(n1436) );
ACHCINX2TS U4088 ( .CIN(n1440), .A(genblk1_right_mult_x_1_n520), .B(n1439),
.CO(n2818) );
CLKAND2X2TS U4089 ( .A(n288), .B(n43), .Y(n1445) );
XOR3X1TS U4090 ( .A(n286), .B(n1445), .C(n1444), .Y(n1446) );
NAND2X1TS U4091 ( .A(n1452), .B(n1451), .Y(n1453) );
ADDHX1TS U4092 ( .A(n1456), .B(n1455), .CO(genblk1_middle_mult_x_1_n830),
.S(n1336) );
INVX2TS U4093 ( .A(n1476), .Y(n2155) );
NAND2X1TS U4094 ( .A(n2112), .B(n1465), .Y(n1467) );
INVX2TS U4095 ( .A(n1477), .Y(n2137) );
NAND2X1TS U4096 ( .A(n1637), .B(n2137), .Y(n1471) );
NOR2X1TS U4097 ( .A(n1638), .B(n1471), .Y(n2254) );
OR2X2TS U4098 ( .A(genblk1_middle_mult_x_1_n620), .B(
genblk1_middle_mult_x_1_n615), .Y(n2259) );
NAND2X1TS U4099 ( .A(n2254), .B(n2259), .Y(n1473) );
AOI21X1TS U4100 ( .A0(n1465), .A1(n1464), .B0(n1463), .Y(n1466) );
NAND2X1TS U4101 ( .A(genblk1_middle_mult_x_1_n621), .B(
genblk1_middle_mult_x_1_n626), .Y(n2136) );
AOI21X1TS U4102 ( .A0(n1648), .A1(n2137), .B0(n1469), .Y(n1470) );
NAND2X1TS U4103 ( .A(genblk1_middle_mult_x_1_n620), .B(
genblk1_middle_mult_x_1_n615), .Y(n2258) );
INVX2TS U4104 ( .A(n2258), .Y(n1484) );
NAND2X1TS U4105 ( .A(genblk1_middle_mult_x_1_n610), .B(
genblk1_middle_mult_x_1_n614), .Y(n2154) );
NAND2X1TS U4106 ( .A(genblk1_middle_mult_x_1_n609), .B(
genblk1_middle_mult_x_1_n606), .Y(n1480) );
INVX2TS U4107 ( .A(n1491), .Y(n2143) );
INVX2TS U4108 ( .A(n1637), .Y(n1479) );
NAND2X1TS U4109 ( .A(n2259), .B(n1483), .Y(n1486) );
NAND2X1TS U4110 ( .A(n1493), .B(n1492), .Y(n1488) );
OAI21XLTS U4111 ( .A0(n2154), .A1(n1481), .B0(n1480), .Y(n1482) );
AOI21X1TS U4112 ( .A0(n1484), .A1(n1483), .B0(n1482), .Y(n1485) );
OAI21X1TS U4113 ( .A0(n1486), .A1(n2136), .B0(n1485), .Y(n1501) );
AOI21X1TS U4114 ( .A0(n1494), .A1(n1492), .B0(n1501), .Y(n1487) );
OAI21X1TS U4115 ( .A0(n2257), .A1(n1488), .B0(n1487), .Y(n2145) );
NAND2X1TS U4116 ( .A(genblk1_middle_mult_x_1_n602), .B(
genblk1_middle_mult_x_1_n605), .Y(n2142) );
NAND2X1TS U4117 ( .A(genblk1_middle_mult_x_1_n599), .B(
genblk1_middle_mult_x_1_n601), .Y(n1497) );
NOR2X1TS U4118 ( .A(n1491), .B(n1498), .Y(n1500) );
AOI21X1TS U4119 ( .A0(n1501), .A1(n1500), .B0(n1499), .Y(n1645) );
INVX2TS U4120 ( .A(n1657), .Y(n1641) );
XOR2X1TS U4121 ( .A(n1585), .B(n1540), .Y(n2030) );
BUFX3TS U4122 ( .A(n2243), .Y(n2345) );
NOR2X1TS U4123 ( .A(n2345), .B(n1956), .Y(n1809) );
NOR2X1TS U4124 ( .A(n1813), .B(n1809), .Y(n1870) );
NAND2X1TS U4125 ( .A(n1560), .B(n1870), .Y(n1562) );
NAND2X1TS U4126 ( .A(n1558), .B(n1889), .Y(n1882) );
NOR2X1TS U4127 ( .A(n1562), .B(n1882), .Y(n1565) );
NAND2X1TS U4128 ( .A(n1556), .B(n1893), .Y(n1557) );
AOI21X1TS U4129 ( .A0(n1558), .A1(n1890), .B0(n1557), .Y(n1881) );
NAND2X1TS U4130 ( .A(n2345), .B(n1953), .Y(n1814) );
NAND2X1TS U4131 ( .A(n2345), .B(n1956), .Y(n1883) );
NAND2X1TS U4132 ( .A(n1814), .B(n1883), .Y(n1869) );
NAND2X1TS U4133 ( .A(n2030), .B(n1931), .Y(n1862) );
NAND2X1TS U4134 ( .A(n1953), .B(n2030), .Y(n1875) );
NAND2X1TS U4135 ( .A(n1862), .B(n1875), .Y(n1559) );
AOI21X1TS U4136 ( .A0(n1560), .A1(n1869), .B0(n1559), .Y(n1561) );
OAI21X1TS U4137 ( .A0(n1562), .A1(n1881), .B0(n1561), .Y(n1563) );
AOI21X2TS U4138 ( .A0(n1565), .A1(n1564), .B0(n1563), .Y(n2123) );
XOR2X1TS U4139 ( .A(n1577), .B(n1574), .Y(n2396) );
NOR2X1TS U4140 ( .A(n2405), .B(n2326), .Y(n1589) );
INVX2TS U4141 ( .A(n1589), .Y(n1836) );
AFHCINX2TS U4142 ( .CIN(n1590), .B(n128), .A(n39), .S(n2355), .CO(n1591) );
INVX2TS U4143 ( .A(n1790), .Y(n2115) );
AHHCINX2TS U4144 ( .A(n1431), .CIN(n1592), .S(n2223), .CO(n2681) );
INVX2TS U4145 ( .A(n1597), .Y(n1826) );
NAND2X1TS U4146 ( .A(n1593), .B(n1826), .Y(n1599) );
NAND2X1TS U4147 ( .A(n2484), .B(n2405), .Y(n1803) );
NAND2X1TS U4148 ( .A(n1931), .B(n2484), .Y(n1850) );
NAND2X1TS U4149 ( .A(n1803), .B(n1850), .Y(n1837) );
NAND2X1TS U4150 ( .A(n2326), .B(n2454), .Y(n1841) );
NAND2X1TS U4151 ( .A(n2405), .B(n2326), .Y(n1834) );
NAND2X1TS U4152 ( .A(n1841), .B(n1834), .Y(n1594) );
NAND2X1TS U4153 ( .A(n2222), .B(n2795), .Y(n2125) );
NAND2X1TS U4154 ( .A(n2454), .B(n2222), .Y(n2117) );
NAND2X1TS U4155 ( .A(n2125), .B(n2117), .Y(n1628) );
INVX2TS U4156 ( .A(n1628), .Y(n1596) );
OAI21X1TS U4157 ( .A0(n2116), .A1(n1597), .B0(n1596), .Y(n1827) );
NAND2X1TS U4158 ( .A(n344), .B(n1827), .Y(n1598) );
OAI21X1TS U4159 ( .A0(n2123), .A1(n1599), .B0(n1598), .Y(n1600) );
BUFX3TS U4160 ( .A(n291), .Y(n2455) );
INVX2TS U4161 ( .A(n2102), .Y(n2315) );
AOI21X1TS U4162 ( .A0(n2455), .A1(n2771), .B0(n1601), .Y(n1602) );
INVX2TS U4163 ( .A(n1659), .Y(n2225) );
NAND2X1TS U4164 ( .A(genblk1_middle_mult_x_1_n598), .B(n1604), .Y(n1643) );
INVX2TS U4165 ( .A(n1607), .Y(n2151) );
OAI21X1TS U4166 ( .A0(n2257), .A1(n1611), .B0(n1610), .Y(n2153) );
NAND2X1TS U4167 ( .A(n1624), .B(n1623), .Y(n1625) );
INVX2TS U4168 ( .A(n2102), .Y(n2796) );
NAND2X1TS U4169 ( .A(n1627), .B(n1629), .Y(n1631) );
OR2X2TS U4170 ( .A(n1790), .B(n1631), .Y(n1633) );
NAND2X1TS U4171 ( .A(n1629), .B(n1628), .Y(n1630) );
NAND2X1TS U4172 ( .A(n2455), .B(n2681), .Y(n1634) );
NAND2X1TS U4173 ( .A(n1637), .B(n1647), .Y(n1650) );
NOR2X1TS U4174 ( .A(n1638), .B(n1650), .Y(n2271) );
CMPR32X2TS U4175 ( .A(n1641), .B(genblk1_middle_mult_x_1_n597), .C(n1639),
.CO(n1653), .S(n1604) );
CMPR32X2TS U4176 ( .A(n1642), .B(n1641), .C(n1640), .CO(n1664), .S(n1652) );
NAND2X1TS U4177 ( .A(n2271), .B(n366), .Y(n1656) );
AOI21X1TS U4178 ( .A0(n1648), .A1(n1647), .B0(n1646), .Y(n1649) );
NAND2X1TS U4179 ( .A(n1653), .B(n1652), .Y(n2272) );
AOI21X1TS U4180 ( .A0(n2270), .A1(n366), .B0(n1654), .Y(n1655) );
OAI21X2TS U4181 ( .A0(n2257), .A1(n1656), .B0(n1655), .Y(n1663) );
AFHCONX2TS U4182 ( .A(n1665), .B(n1664), .CI(n1663), .CON(n1662), .S(
genblk1_middle_N54) );
NAND2X1TS U4183 ( .A(n1667), .B(n1666), .Y(n1668) );
XNOR2X1TS U4184 ( .A(n1669), .B(n1668), .Y(genblk1_middle_N42) );
NAND2X1TS U4185 ( .A(n2264), .B(n2262), .Y(n1671) );
XNOR2X1TS U4186 ( .A(n1390), .B(n1671), .Y(genblk1_middle_N38) );
NAND2X1TS U4187 ( .A(n1673), .B(n1672), .Y(n1674) );
XNOR2X1TS U4188 ( .A(n1675), .B(n1674), .Y(genblk1_middle_N36) );
NAND2X1TS U4189 ( .A(n1677), .B(n1676), .Y(n1678) );
XNOR2X1TS U4190 ( .A(n1679), .B(n1678), .Y(genblk1_middle_N34) );
CLKINVX1TS U4191 ( .A(n1680), .Y(n2302) );
OAI21X1TS U4192 ( .A0(n2302), .A1(n1684), .B0(n1683), .Y(n2278) );
NAND2X1TS U4193 ( .A(n2277), .B(n2275), .Y(n1686) );
XNOR2X1TS U4194 ( .A(n2278), .B(n1686), .Y(genblk1_middle_N32) );
NAND2X1TS U4195 ( .A(n1689), .B(n1688), .Y(n1690) );
XNOR2X1TS U4196 ( .A(n1691), .B(n1690), .Y(genblk1_middle_N31) );
AOI21X1TS U4197 ( .A0(n16), .A1(n1694), .B0(n1693), .Y(n2297) );
NAND2X1TS U4198 ( .A(n1697), .B(n1696), .Y(n1698) );
XNOR2X1TS U4199 ( .A(n1699), .B(n1698), .Y(genblk1_middle_N29) );
NAND2X1TS U4200 ( .A(n2305), .B(n2303), .Y(n1701) );
XNOR2X1TS U4201 ( .A(n16), .B(n1701), .Y(genblk1_middle_N26) );
INVX2TS U4202 ( .A(n1702), .Y(n2382) );
NAND2X1TS U4203 ( .A(n2365), .B(n1705), .Y(n1706) );
XNOR2X1TS U4204 ( .A(n2366), .B(n1706), .Y(genblk1_middle_N24) );
NAND2X1TS U4205 ( .A(n1709), .B(n1708), .Y(n1710) );
XNOR2X1TS U4206 ( .A(n1711), .B(n1710), .Y(genblk1_middle_N23) );
NAND2X1TS U4207 ( .A(n356), .B(n1713), .Y(n1714) );
XNOR2X1TS U4208 ( .A(n2468), .B(n1714), .Y(genblk1_middle_N20) );
INVX2TS U4209 ( .A(n1715), .Y(n2589) );
NAND2X1TS U4210 ( .A(n1718), .B(n1717), .Y(n1719) );
XNOR2X1TS U4211 ( .A(n1720), .B(n1719), .Y(genblk1_middle_N19) );
INVX2TS U4212 ( .A(n1721), .Y(n2613) );
NAND2X1TS U4213 ( .A(n1724), .B(n1723), .Y(n1725) );
XNOR2X1TS U4214 ( .A(n1726), .B(n1725), .Y(genblk1_middle_N16) );
INVX2TS U4215 ( .A(n1727), .Y(n2605) );
NAND2X1TS U4216 ( .A(n2604), .B(n1728), .Y(n1729) );
XNOR2X1TS U4217 ( .A(n2605), .B(n1729), .Y(genblk1_middle_N13) );
INVX2TS U4218 ( .A(n1730), .Y(n2618) );
NAND2X1TS U4219 ( .A(n1733), .B(n1732), .Y(n1734) );
XNOR2X1TS U4220 ( .A(n1735), .B(n1734), .Y(genblk1_middle_N12) );
NAND2X1TS U4221 ( .A(n1737), .B(n1736), .Y(n1739) );
XNOR2X1TS U4222 ( .A(n1739), .B(n1738), .Y(genblk1_middle_N9) );
NAND2X1TS U4223 ( .A(n315), .B(n1740), .Y(n1742) );
XNOR2X1TS U4224 ( .A(n1742), .B(n1741), .Y(genblk1_middle_N7) );
NAND2X1TS U4225 ( .A(n355), .B(n1743), .Y(n1745) );
XNOR2X1TS U4226 ( .A(n1745), .B(n1744), .Y(genblk1_middle_N5) );
NAND2X1TS U4227 ( .A(n1747), .B(n1746), .Y(n1749) );
XNOR2X1TS U4228 ( .A(n1749), .B(n1748), .Y(genblk1_middle_N3) );
INVX2TS U4229 ( .A(n1750), .Y(n1752) );
XNOR2X1TS U4230 ( .A(n1752), .B(n1751), .Y(genblk1_middle_N1) );
AOI222XLTS U4231 ( .A0(n2703), .A1(n2747), .B0(n2550), .B1(n2746), .C0(n2549), .C1(n2791), .Y(n1753) );
ADDHX1TS U4232 ( .A(n1757), .B(n1756), .CO(n1763), .S(n1069) );
CLKBUFX2TS U4233 ( .A(n1949), .Y(n2749) );
XOR2X1TS U4234 ( .A(n1761), .B(n2743), .Y(n1765) );
CMPR32X2TS U4235 ( .A(n1764), .B(n1763), .C(n1762), .CO(
genblk1_middle_mult_x_1_n897), .S(genblk1_middle_mult_x_1_n898) );
ADDHXLTS U4236 ( .A(n1766), .B(n1765), .CO(genblk1_middle_mult_x_1_n899),
.S(n1762) );
ADDHXLTS U4237 ( .A(n2686), .B(n1767), .CO(n1756), .S(n1777) );
AOI222XLTS U4238 ( .A0(n2703), .A1(n2739), .B0(n2550), .B1(n2146), .C0(n2701), .C1(n2761), .Y(n1768) );
INVX2TS U4239 ( .A(n1770), .Y(n1970) );
INVX2TS U4240 ( .A(n1771), .Y(n1969) );
NAND2X1TS U4241 ( .A(n1969), .B(n1967), .Y(n1772) );
CLKBUFX2TS U4242 ( .A(n2070), .Y(n2556) );
CLKBUFX2TS U4243 ( .A(n2443), .Y(n2807) );
CLKBUFX2TS U4244 ( .A(n2442), .Y(n2562) );
AOI222XLTS U4245 ( .A0(n2564), .A1(n2556), .B0(n2807), .B1(n2776), .C0(n2562), .C1(n2746), .Y(n1773) );
CMPR32X2TS U4246 ( .A(n1777), .B(n1776), .C(n1775), .CO(
genblk1_middle_mult_x_1_n917), .S(genblk1_middle_mult_x_1_n918) );
ADDHXLTS U4247 ( .A(n1779), .B(n1778), .CO(genblk1_middle_mult_x_1_n950),
.S(n1375) );
CLKBUFX2TS U4248 ( .A(n1989), .Y(n2730) );
XOR2X1TS U4249 ( .A(n1782), .B(n2812), .Y(n1786) );
AOI222XLTS U4250 ( .A0(n2721), .A1(n2739), .B0(n2555), .B1(n2737), .C0(n2718), .C1(n2803), .Y(n1783) );
XOR2X1TS U4251 ( .A(n1784), .B(n2724), .Y(n1785) );
CMPR32X2TS U4252 ( .A(n1787), .B(n1786), .C(n1785), .CO(
genblk1_middle_mult_x_1_n962), .S(genblk1_middle_mult_x_1_n963) );
ADDHXLTS U4253 ( .A(n1789), .B(n1788), .CO(genblk1_middle_mult_x_1_n983),
.S(n1296) );
OAI21X1TS U4254 ( .A0(n2123), .A1(n1790), .B0(n2116), .Y(n1793) );
INVX2TS U4255 ( .A(n1791), .Y(n2119) );
NAND2X1TS U4256 ( .A(n2119), .B(n2117), .Y(n1792) );
XOR2X2TS U4257 ( .A(n1793), .B(n1792), .Y(n2357) );
CLKBUFX2TS U4258 ( .A(n2456), .Y(n2383) );
CLKBUFX2TS U4259 ( .A(n2355), .Y(n2371) );
AOI222XLTS U4260 ( .A0(n2458), .A1(n2383), .B0(n311), .B1(n2371), .C0(n2455),
.C1(n2326), .Y(n1794) );
OAI21X1TS U4261 ( .A0(n2123), .A1(n1797), .B0(n1796), .Y(n1799) );
NAND2X1TS U4262 ( .A(n1836), .B(n1834), .Y(n1798) );
CLKBUFX2TS U4263 ( .A(n2400), .Y(n2376) );
AOI222XLTS U4264 ( .A0(n2458), .A1(n2376), .B0(n310), .B1(n1950), .C0(n2778),
.C1(n2484), .Y(n1800) );
OAI21X1TS U4265 ( .A0(n2389), .A1(n2765), .B0(n1800), .Y(n1801) );
XOR2X1TS U4266 ( .A(n1801), .B(n2225), .Y(genblk1_middle_mult_x_1_n1310) );
NAND2X1TS U4267 ( .A(n1804), .B(n1803), .Y(n1805) );
CLKBUFX2TS U4268 ( .A(n1950), .Y(n2397) );
AOI222XLTS U4269 ( .A0(n2458), .A1(n2397), .B0(n310), .B1(n2396), .C0(n2455),
.C1(n2680), .Y(n1807) );
INVX2TS U4270 ( .A(n1882), .Y(n1868) );
INVX2TS U4271 ( .A(n1809), .Y(n1884) );
NAND2X1TS U4272 ( .A(n1868), .B(n1884), .Y(n1812) );
AOI21X1TS U4273 ( .A0(n1871), .A1(n1884), .B0(n1810), .Y(n1811) );
OAI21X1TS U4274 ( .A0(n2099), .A1(n1812), .B0(n1811), .Y(n1817) );
NAND2X1TS U4275 ( .A(n1815), .B(n1814), .Y(n1816) );
CLKBUFX2TS U4276 ( .A(n1953), .Y(n2521) );
CLKBUFX2TS U4277 ( .A(n2243), .Y(n2520) );
CLKBUFX2TS U4278 ( .A(n1956), .Y(n2544) );
AOI222XLTS U4279 ( .A0(n2762), .A1(n2521), .B0(n2760), .B1(n2520), .C0(n2759), .C1(n2544), .Y(n1818) );
XOR2X1TS U4280 ( .A(n1819), .B(n2785), .Y(genblk1_middle_mult_x_1_n1315) );
AOI222X1TS U4281 ( .A0(n2781), .A1(n2737), .B0(n310), .B1(n2803), .C0(n2759),
.C1(n2790), .Y(n1821) );
XOR2X1TS U4282 ( .A(n1822), .B(n2766), .Y(genblk1_middle_mult_x_1_n1328) );
NAND2X1TS U4283 ( .A(n309), .B(n2681), .Y(n1824) );
NAND2X1TS U4284 ( .A(n2115), .B(n1826), .Y(n1829) );
CLKBUFX2TS U4285 ( .A(n2660), .Y(n2646) );
AOI222XLTS U4286 ( .A0(n2330), .A1(n2796), .B0(n2646), .B1(n2457), .C0(n2391), .C1(n2222), .Y(n1831) );
OAI21XLTS U4287 ( .A0(n2285), .A1(n2648), .B0(n1831), .Y(n1832) );
INVX2TS U4288 ( .A(n408), .Y(n2214) );
XOR2X1TS U4289 ( .A(n1832), .B(n2214), .Y(genblk1_middle_mult_x_1_n1337) );
NAND2X1TS U4290 ( .A(n1833), .B(n1836), .Y(n1839) );
AOI21X1TS U4291 ( .A0(n1837), .A1(n1836), .B0(n1835), .Y(n1838) );
OAI21X1TS U4292 ( .A0(n2123), .A1(n1839), .B0(n1838), .Y(n1844) );
NAND2X1TS U4293 ( .A(n1842), .B(n1841), .Y(n1843) );
AOI222XLTS U4294 ( .A0(n2662), .A1(n2401), .B0(n2646), .B1(n2376), .C0(n2391), .C1(n2405), .Y(n1845) );
OAI21X1TS U4295 ( .A0(n2403), .A1(n2648), .B0(n1845), .Y(n1846) );
INVX2TS U4296 ( .A(n408), .Y(n2394) );
XOR2X1TS U4297 ( .A(n1846), .B(n2394), .Y(genblk1_middle_mult_x_1_n1340) );
AOI222XLTS U4298 ( .A0(n2662), .A1(n2376), .B0(n2646), .B1(n2397), .C0(n309),
.C1(n2484), .Y(n1847) );
XOR2X1TS U4299 ( .A(n1848), .B(n2394), .Y(genblk1_middle_mult_x_1_n1341) );
NAND2X1TS U4300 ( .A(n1851), .B(n1850), .Y(n1852) );
XNOR2X2TS U4301 ( .A(n2123), .B(n1852), .Y(n2486) );
CLKBUFX2TS U4302 ( .A(n2396), .Y(n2480) );
CLKBUFX2TS U4303 ( .A(n1931), .Y(n2497) );
CLKBUFX2TS U4304 ( .A(n2030), .Y(n2511) );
AOI222XLTS U4305 ( .A0(n2662), .A1(n2480), .B0(n2646), .B1(n2497), .C0(n2391), .C1(n2511), .Y(n1853) );
XOR2X1TS U4306 ( .A(n1854), .B(n2394), .Y(genblk1_middle_mult_x_1_n1343) );
NOR2X1TS U4307 ( .A(n1855), .B(n1874), .Y(n1858) );
NAND2X1TS U4308 ( .A(n1858), .B(n1868), .Y(n1860) );
AOI21X1TS U4309 ( .A0(n1858), .A1(n1871), .B0(n1857), .Y(n1859) );
OAI21X1TS U4310 ( .A0(n1860), .A1(n2099), .B0(n1859), .Y(n1865) );
NAND2X1TS U4311 ( .A(n1863), .B(n1862), .Y(n1864) );
CLKBUFX2TS U4312 ( .A(n2030), .Y(n2504) );
CLKBUFX2TS U4313 ( .A(n1953), .Y(n2641) );
AOI222XLTS U4314 ( .A0(n2662), .A1(n2497), .B0(n2660), .B1(n2504), .C0(n308),
.C1(n2641), .Y(n1866) );
XOR2X1TS U4315 ( .A(n1867), .B(n2394), .Y(genblk1_middle_mult_x_1_n1344) );
NAND2X1TS U4316 ( .A(n1868), .B(n1870), .Y(n1873) );
AOI21X1TS U4317 ( .A0(n1871), .A1(n1870), .B0(n1869), .Y(n1872) );
OAI21X1TS U4318 ( .A0(n2099), .A1(n1873), .B0(n1872), .Y(n1878) );
NAND2X1TS U4319 ( .A(n1876), .B(n1875), .Y(n1877) );
AOI222XLTS U4320 ( .A0(n2330), .A1(n2504), .B0(n2646), .B1(n2521), .C0(n308),
.C1(n2345), .Y(n1879) );
XOR2X1TS U4321 ( .A(n1880), .B(n2394), .Y(genblk1_middle_mult_x_1_n1345) );
NAND2X1TS U4322 ( .A(n1884), .B(n1883), .Y(n1885) );
CLKBUFX2TS U4323 ( .A(n2243), .Y(n2509) );
CLKBUFX2TS U4324 ( .A(n2006), .Y(n2542) );
AOI222XLTS U4325 ( .A0(n2330), .A1(n2509), .B0(n295), .B1(n2493), .C0(n308),
.C1(n2542), .Y(n1887) );
XOR2X1TS U4326 ( .A(n1888), .B(n2394), .Y(genblk1_middle_mult_x_1_n1347) );
OAI21X1TS U4327 ( .A0(n2099), .A1(n1892), .B0(n1891), .Y(n1896) );
NAND2X1TS U4328 ( .A(n1894), .B(n1893), .Y(n1895) );
XOR2X2TS U4329 ( .A(n1896), .B(n1895), .Y(n2437) );
CLKBUFX2TS U4330 ( .A(n2006), .Y(n2433) );
CLKBUFX2TS U4331 ( .A(n1936), .Y(n2489) );
CLKBUFX2TS U4332 ( .A(n1904), .Y(n2533) );
OAI21X1TS U4333 ( .A0(n2437), .A1(n2664), .B0(n1897), .Y(n1898) );
XOR2X1TS U4334 ( .A(n1898), .B(n399), .Y(genblk1_middle_mult_x_1_n1349) );
OAI21X1TS U4335 ( .A0(n2099), .A1(n2095), .B0(n2096), .Y(n1903) );
NAND2X1TS U4336 ( .A(n1901), .B(n1900), .Y(n1902) );
CLKBUFX2TS U4337 ( .A(n1904), .Y(n2661) );
CLKBUFX2TS U4338 ( .A(n2559), .Y(n2531) );
AOI222XLTS U4339 ( .A0(n2330), .A1(n2489), .B0(n2646), .B1(n2661), .C0(n309),
.C1(n2531), .Y(n1905) );
XOR2X1TS U4340 ( .A(n1906), .B(n2666), .Y(genblk1_middle_mult_x_1_n1350) );
AOI21X1TS U4341 ( .A0(n1970), .A1(n1908), .B0(n1907), .Y(n2069) );
NAND2X1TS U4342 ( .A(n1911), .B(n1910), .Y(n1912) );
CLKBUFX2TS U4343 ( .A(n2559), .Y(n2659) );
CLKBUFX2TS U4344 ( .A(n2563), .Y(n2780) );
CLKBUFX2TS U4345 ( .A(n1985), .Y(n2578) );
AOI222XLTS U4346 ( .A0(n2348), .A1(n2659), .B0(n295), .B1(n2780), .C0(n309),
.C1(n2578), .Y(n1914) );
CLKBUFX2TS U4347 ( .A(n1916), .Y(n2671) );
AOI222X1TS U4348 ( .A0(n2348), .A1(n2671), .B0(n2660), .B1(n2670), .C0(n308),
.C1(n2739), .Y(n1917) );
XOR2X1TS U4349 ( .A(n1924), .B(n399), .Y(genblk1_middle_mult_x_1_n1362) );
AOI21X1TS U4350 ( .A0(n305), .A1(n2771), .B0(n1926), .Y(n1927) );
CLKBUFX2TS U4351 ( .A(n2396), .Y(n2451) );
AOI222XLTS U4352 ( .A0(n2416), .A1(n2376), .B0(n2415), .B1(n2397), .C0(n2736), .C1(n2451), .Y(n1929) );
XOR2X1TS U4353 ( .A(n1930), .B(n2424), .Y(genblk1_middle_mult_x_1_n1372) );
CLKBUFX2TS U4354 ( .A(n1931), .Y(n2483) );
AOI222XLTS U4355 ( .A0(n2416), .A1(n2397), .B0(n2738), .B1(n2480), .C0(n305),
.C1(n2483), .Y(n1932) );
OAI21X1TS U4356 ( .A0(n2410), .A1(n2684), .B0(n1932), .Y(n1933) );
XOR2X1TS U4357 ( .A(n1933), .B(n2424), .Y(genblk1_middle_mult_x_1_n1373) );
AOI222XLTS U4358 ( .A0(n293), .A1(n2509), .B0(n2674), .B1(n2493), .C0(n2736),
.C1(n2475), .Y(n1934) );
XOR2X1TS U4359 ( .A(n1935), .B(n2424), .Y(genblk1_middle_mult_x_1_n1378) );
CLKBUFX2TS U4360 ( .A(n1936), .Y(n2432) );
AOI222XLTS U4361 ( .A0(n293), .A1(n2493), .B0(n2674), .B1(n2433), .C0(n2736),
.C1(n2432), .Y(n1937) );
XOR2X1TS U4362 ( .A(n1938), .B(n2743), .Y(genblk1_middle_mult_x_1_n1379) );
XOR2X1TS U4363 ( .A(n1942), .B(n2743), .Y(genblk1_middle_mult_x_1_n1391) );
CLKBUFX2TS U4364 ( .A(n1961), .Y(n2450) );
AOI21X1TS U4365 ( .A0(n2450), .A1(n2771), .B0(n1944), .Y(n1945) );
CLKBUFX2TS U4366 ( .A(n2456), .Y(n2792) );
AOI222XLTS U4367 ( .A0(n2711), .A1(n2796), .B0(n1964), .B1(n2457), .C0(n2450), .C1(n2792), .Y(n1947) );
OAI21X1TS U4368 ( .A0(n2285), .A1(n2713), .B0(n1947), .Y(n1948) );
XOR2X1TS U4369 ( .A(n1948), .B(n2753), .Y(genblk1_middle_mult_x_1_n1399) );
CLKBUFX2TS U4370 ( .A(n1949), .Y(n2692) );
CLKBUFX2TS U4371 ( .A(n1950), .Y(n2406) );
AOI222XLTS U4372 ( .A0(n2692), .A1(n2406), .B0(n2710), .B1(n2480), .C0(n2450), .C1(n2483), .Y(n1951) );
XOR2X1TS U4373 ( .A(n1952), .B(n2526), .Y(genblk1_middle_mult_x_1_n1404) );
CLKBUFX2TS U4374 ( .A(n1953), .Y(n2510) );
AOI222XLTS U4375 ( .A0(n2692), .A1(n2483), .B0(n2710), .B1(n2504), .C0(n2450), .C1(n2510), .Y(n1954) );
XOR2X1TS U4376 ( .A(n1955), .B(n2526), .Y(genblk1_middle_mult_x_1_n1406) );
CLKBUFX2TS U4377 ( .A(n1956), .Y(n2422) );
AOI222XLTS U4378 ( .A0(n2711), .A1(n2510), .B0(n2710), .B1(n2509), .C0(n2708), .C1(n2422), .Y(n1957) );
AOI222XLTS U4379 ( .A0(n2711), .A1(n2422), .B0(n2710), .B1(n2433), .C0(n2708), .C1(n2432), .Y(n1959) );
XOR2X1TS U4380 ( .A(n1960), .B(n2526), .Y(genblk1_middle_mult_x_1_n1410) );
AOI222XLTS U4381 ( .A0(n2711), .A1(n2539), .B0(n1964), .B1(n2661), .C0(n1961), .C1(n2573), .Y(n1962) );
CLKBUFX2TS U4382 ( .A(n1964), .Y(n2748) );
CLKBUFX2TS U4383 ( .A(n1985), .Y(n2779) );
AOI222XLTS U4384 ( .A0(n2749), .A1(n2531), .B0(n2748), .B1(n2780), .C0(n1961), .C1(n2779), .Y(n1965) );
AOI21X1TS U4385 ( .A0(n1970), .A1(n1969), .B0(n1968), .Y(n1975) );
NAND2X1TS U4386 ( .A(n1973), .B(n1972), .Y(n1974) );
AOI222XLTS U4387 ( .A0(n2749), .A1(n2578), .B0(n2748), .B1(n2556), .C0(n1961), .C1(n2776), .Y(n1976) );
XOR2X1TS U4388 ( .A(n1977), .B(n2753), .Y(genblk1_middle_mult_x_1_n1416) );
AOI222XLTS U4389 ( .A0(n2749), .A1(n2739), .B0(n2748), .B1(n2737), .C0(n2708), .C1(n2761), .Y(n1978) );
XOR2X1TS U4390 ( .A(n1979), .B(n2714), .Y(genblk1_middle_mult_x_1_n1420) );
AOI222XLTS U4391 ( .A0(n2695), .A1(n2521), .B0(n2702), .B1(n2520), .C0(n2701), .C1(n2422), .Y(n1981) );
INVX2TS U4392 ( .A(n2162), .Y(n2507) );
XOR2X1TS U4393 ( .A(n1982), .B(n2507), .Y(genblk1_middle_mult_x_1_n1439) );
AOI222XLTS U4394 ( .A0(n2695), .A1(n2493), .B0(n2702), .B1(n2006), .C0(n2701), .C1(n2539), .Y(n1983) );
XOR2X1TS U4395 ( .A(n1984), .B(n2706), .Y(genblk1_middle_mult_x_1_n1441) );
CLKBUFX2TS U4396 ( .A(n1985), .Y(n2528) );
CLKBUFX2TS U4397 ( .A(n2070), .Y(n2653) );
AOI222XLTS U4398 ( .A0(n2703), .A1(n2528), .B0(n2550), .B1(n2653), .C0(n2549), .C1(n2671), .Y(n1986) );
XOR2X1TS U4399 ( .A(n1987), .B(n2552), .Y(genblk1_middle_mult_x_1_n1447) );
CLKBUFX2TS U4400 ( .A(n2400), .Y(n2387) );
AOI222XLTS U4401 ( .A0(n1989), .A1(n2383), .B0(n2443), .B1(n2371), .C0(n2442), .C1(n2387), .Y(n1990) );
INVX2TS U4402 ( .A(n1340), .Y(n2446) );
XOR2X1TS U4403 ( .A(n1991), .B(n2446), .Y(genblk1_middle_mult_x_1_n1463) );
AOI222XLTS U4404 ( .A0(n1989), .A1(n2371), .B0(n2443), .B1(n2400), .C0(n2442), .C1(n2406), .Y(n1992) );
XOR2X1TS U4405 ( .A(n1993), .B(n2446), .Y(genblk1_middle_mult_x_1_n1464) );
AOI222XLTS U4406 ( .A0(n1989), .A1(n2376), .B0(n2443), .B1(n2405), .C0(n2726), .C1(n2451), .Y(n1994) );
OAI21X1TS U4407 ( .A0(n2389), .A1(n2811), .B0(n1994), .Y(n1995) );
XOR2X1TS U4408 ( .A(n1995), .B(n2446), .Y(genblk1_middle_mult_x_1_n1465) );
AOI222XLTS U4409 ( .A0(n1989), .A1(n2397), .B0(n2728), .B1(n2396), .C0(n2442), .C1(n2483), .Y(n1996) );
OAI21X1TS U4410 ( .A0(n2410), .A1(n2445), .B0(n1996), .Y(n1997) );
XOR2X1TS U4411 ( .A(n1997), .B(n2446), .Y(genblk1_middle_mult_x_1_n1466) );
AOI222XLTS U4412 ( .A0(n1989), .A1(n2497), .B0(n2728), .B1(n2511), .C0(n2562), .C1(n2510), .Y(n1998) );
AOI222XLTS U4413 ( .A0(n2730), .A1(n2504), .B0(n2443), .B1(n2641), .C0(n2726), .C1(n2520), .Y(n2000) );
OAI21X1TS U4414 ( .A0(n2525), .A1(n2445), .B0(n2000), .Y(n2001) );
AOI222XLTS U4415 ( .A0(n2730), .A1(n2521), .B0(n2728), .B1(n2520), .C0(n2726), .C1(n2422), .Y(n2002) );
XOR2X1TS U4416 ( .A(n2003), .B(n2446), .Y(genblk1_middle_mult_x_1_n1470) );
AOI222XLTS U4417 ( .A0(n2730), .A1(n2509), .B0(n2728), .B1(n2544), .C0(n2726), .C1(n2475), .Y(n2004) );
XOR2X1TS U4418 ( .A(n2005), .B(n2446), .Y(genblk1_middle_mult_x_1_n1471) );
AOI222XLTS U4419 ( .A0(n2730), .A1(n2493), .B0(n2728), .B1(n2006), .C0(n2726), .C1(n2432), .Y(n2007) );
XOR2X1TS U4420 ( .A(n2008), .B(n2446), .Y(genblk1_middle_mult_x_1_n1472) );
AOI222XLTS U4421 ( .A0(n2730), .A1(n2433), .B0(n2728), .B1(n2432), .C0(n2562), .C1(n2488), .Y(n2009) );
AOI222XLTS U4422 ( .A0(n2730), .A1(n2489), .B0(n2807), .B1(n2488), .C0(n2562), .C1(n2573), .Y(n2011) );
XOR2X1TS U4423 ( .A(n2012), .B(n2815), .Y(genblk1_middle_mult_x_1_n1474) );
AOI222XLTS U4424 ( .A0(n2564), .A1(n2528), .B0(n2807), .B1(n2653), .C0(n2562), .C1(n2776), .Y(n2013) );
XOR2X1TS U4425 ( .A(n2014), .B(n2815), .Y(genblk1_middle_mult_x_1_n1478) );
XOR2X1TS U4426 ( .A(n2016), .B(n2812), .Y(genblk1_middle_mult_x_1_n1480) );
XOR2X1TS U4427 ( .A(n2018), .B(n2812), .Y(genblk1_middle_mult_x_1_n1481) );
AOI222XLTS U4428 ( .A0(n2564), .A1(n2669), .B0(n2807), .B1(n2146), .C0(n2726), .C1(n2803), .Y(n2019) );
AOI222XLTS U4429 ( .A0(n2439), .A1(n2371), .B0(n2427), .B1(n2376), .C0(n2426), .C1(n2405), .Y(n2021) );
INVX2TS U4430 ( .A(n2654), .Y(n2465) );
XOR2X1TS U4431 ( .A(n2022), .B(n2465), .Y(genblk1_middle_mult_x_1_n1495) );
AOI222XLTS U4432 ( .A0(n2721), .A1(n2387), .B0(n2427), .B1(n2397), .C0(n2718), .C1(n2484), .Y(n2023) );
XOR2X1TS U4433 ( .A(n2024), .B(n2465), .Y(genblk1_middle_mult_x_1_n1496) );
AOI222XLTS U4434 ( .A0(n2439), .A1(n2406), .B0(n2720), .B1(n2480), .C0(n2426), .C1(n2680), .Y(n2026) );
OAI21X1TS U4435 ( .A0(n2410), .A1(n2464), .B0(n2026), .Y(n2027) );
XOR2X1TS U4436 ( .A(n2027), .B(n2465), .Y(genblk1_middle_mult_x_1_n1497) );
AOI222XLTS U4437 ( .A0(n2439), .A1(n2483), .B0(n2720), .B1(n2504), .C0(n2554), .C1(n2641), .Y(n2028) );
CLKBUFX2TS U4438 ( .A(n2030), .Y(n2522) );
AOI222XLTS U4439 ( .A0(n2462), .A1(n2522), .B0(n2427), .B1(n2521), .C0(n2718), .C1(n2345), .Y(n2031) );
XOR2X1TS U4440 ( .A(n2032), .B(n2465), .Y(genblk1_middle_mult_x_1_n1500) );
AOI222XLTS U4441 ( .A0(n2462), .A1(n2520), .B0(n2720), .B1(n2493), .C0(n2718), .C1(n2542), .Y(n2033) );
XOR2X1TS U4442 ( .A(n2034), .B(n2465), .Y(genblk1_middle_mult_x_1_n1502) );
AOI222XLTS U4443 ( .A0(n2462), .A1(n2422), .B0(n2720), .B1(n2433), .C0(n2718), .C1(n2539), .Y(n2035) );
XOR2X1TS U4444 ( .A(n2036), .B(n2724), .Y(genblk1_middle_mult_x_1_n1503) );
AOI222XLTS U4445 ( .A0(n2462), .A1(n2433), .B0(n2720), .B1(n2489), .C0(n2554), .C1(n2533), .Y(n2037) );
AOI222XLTS U4446 ( .A0(n2462), .A1(n2489), .B0(n2555), .B1(n2661), .C0(n2554), .C1(n2531), .Y(n2039) );
XOR2X1TS U4447 ( .A(n2040), .B(n2193), .Y(genblk1_middle_mult_x_1_n1505) );
AOI222XLTS U4448 ( .A0(n2721), .A1(n2659), .B0(n2555), .B1(n2780), .C0(n2554), .C1(n2578), .Y(n2041) );
AOI222XLTS U4449 ( .A0(n2721), .A1(n2528), .B0(n2555), .B1(n2556), .C0(n2554), .C1(n2671), .Y(n2043) );
AOI222XLTS U4450 ( .A0(n2462), .A1(n2719), .B0(n2720), .B1(n2228), .C0(n2718), .C1(n2758), .Y(n2045) );
XOR2X1TS U4451 ( .A(n2046), .B(n2724), .Y(genblk1_middle_mult_x_1_n1515) );
AOI222XLTS U4452 ( .A0(n2462), .A1(n2228), .B0(n2720), .B1(n2359), .C0(n2718), .C1(n2645), .Y(n2047) );
XOR2X1TS U4453 ( .A(n2048), .B(n2724), .Y(genblk1_middle_mult_x_1_n1516) );
AOI222XLTS U4454 ( .A0(n2407), .A1(n2371), .B0(n2387), .B1(n2532), .C0(n2793), .C1(n2406), .Y(n2049) );
INVX2TS U4455 ( .A(n1181), .Y(n2411) );
AOI222XLTS U4456 ( .A0(n2407), .A1(n2451), .B0(n2483), .B1(n2532), .C0(n2793), .C1(n2522), .Y(n2051) );
OAI21X1TS U4457 ( .A0(n2486), .A1(n2768), .B0(n2051), .Y(n2052) );
XOR2X1TS U4458 ( .A(n2052), .B(n2411), .Y(genblk1_middle_mult_x_1_n1529) );
AOI222XLTS U4459 ( .A0(n2407), .A1(n2483), .B0(n2522), .B1(n2532), .C0(n2793), .C1(n2510), .Y(n2053) );
XOR2X1TS U4460 ( .A(n2054), .B(n2411), .Y(genblk1_middle_mult_x_1_n1530) );
AOI222XLTS U4461 ( .A0(n1258), .A1(n2522), .B0(n2510), .B1(n2532), .C0(n2386), .C1(n2243), .Y(n2055) );
XOR2X1TS U4462 ( .A(n2056), .B(n2411), .Y(genblk1_middle_mult_x_1_n1531) );
CLKBUFX2TS U4463 ( .A(n2532), .Y(n2794) );
AOI222XLTS U4464 ( .A0(n1258), .A1(n2510), .B0(n2520), .B1(n2794), .C0(n2386), .C1(n2422), .Y(n2057) );
AOI222XLTS U4465 ( .A0(n1258), .A1(n2243), .B0(n2422), .B1(n2794), .C0(n2386), .C1(n2542), .Y(n2059) );
XOR2X1TS U4466 ( .A(n2060), .B(n2411), .Y(genblk1_middle_mult_x_1_n1533) );
AOI222XLTS U4467 ( .A0(n1258), .A1(n2422), .B0(n2542), .B1(n2794), .C0(n2386), .C1(n2539), .Y(n2061) );
CLKBUFX2TS U4468 ( .A(n2793), .Y(n2772) );
AOI222XLTS U4469 ( .A0(n1258), .A1(n2542), .B0(n2539), .B1(n2794), .C0(n2772), .C1(n2533), .Y(n2063) );
OAI21X1TS U4470 ( .A0(n2437), .A1(n2409), .B0(n2063), .Y(n2064) );
NAND2X1TS U4471 ( .A(n2067), .B(n2066), .Y(n2068) );
CLKBUFX2TS U4472 ( .A(n2563), .Y(n2657) );
CLKBUFX2TS U4473 ( .A(n2070), .Y(n2777) );
AOI222XLTS U4474 ( .A0(n2569), .A1(n2657), .B0(n2578), .B1(n2794), .C0(n2772), .C1(n2777), .Y(n2071) );
XOR2X1TS U4475 ( .A(n2072), .B(n2800), .Y(genblk1_middle_mult_x_1_n1539) );
AOI222XLTS U4476 ( .A0(n2569), .A1(n2777), .B0(n2769), .B1(n2747), .C0(n2772), .C1(n2582), .Y(n2073) );
AOI222XLTS U4477 ( .A0(n2569), .A1(n2671), .B0(n2769), .B1(n2670), .C0(n2772), .C1(n2669), .Y(n2075) );
XOR2X1TS U4478 ( .A(n2076), .B(n2080), .Y(genblk1_middle_mult_x_1_n1542) );
AOI222XLTS U4479 ( .A0(n2569), .A1(n2582), .B0(n2769), .B1(n2108), .C0(n2772), .C1(n2419), .Y(n2077) );
XOR2X1TS U4480 ( .A(n2078), .B(n2080), .Y(genblk1_middle_mult_x_1_n1543) );
AOI222XLTS U4481 ( .A0(n2569), .A1(n2739), .B0(n2769), .B1(n2737), .C0(n2386), .C1(n2761), .Y(n2079) );
XOR2X1TS U4482 ( .A(n2081), .B(n2080), .Y(genblk1_middle_mult_x_1_n1544) );
AOI222XLTS U4483 ( .A0(n2222), .A1(n2543), .B0(n2401), .B1(n2541), .C0(n2376), .C1(n2590), .Y(n2083) );
XOR2X1TS U4484 ( .A(n2084), .B(n2596), .Y(genblk1_middle_mult_x_1_n1556) );
AOI222XLTS U4485 ( .A0(n2326), .A1(n2543), .B0(n2406), .B1(n2541), .C0(n2480), .C1(n300), .Y(n2085) );
AOI222XLTS U4486 ( .A0(n2405), .A1(n2592), .B0(n2451), .B1(n2541), .C0(n2497), .C1(n301), .Y(n2087) );
OAI21X1TS U4487 ( .A0(n2410), .A1(n2515), .B0(n2087), .Y(n2088) );
XOR2X1TS U4488 ( .A(n2088), .B(result_A_adder_2_), .Y(
genblk1_middle_mult_x_1_n1559) );
AOI222XLTS U4489 ( .A0(n2345), .A1(n2543), .B0(n2422), .B1(n2541), .C0(n300),
.C1(n2542), .Y(n2089) );
XOR2X1TS U4490 ( .A(n2090), .B(n4983), .Y(genblk1_middle_mult_x_1_n1564) );
AOI222XLTS U4491 ( .A0(n2475), .A1(n2592), .B0(n2539), .B1(n2591), .C0(n301),
.C1(n2533), .Y(n2091) );
AOI222XLTS U4492 ( .A0(n2432), .A1(n2352), .B0(n2533), .B1(n2351), .C0(n300),
.C1(n2531), .Y(n2093) );
XOR2X1TS U4493 ( .A(n2094), .B(n2576), .Y(genblk1_middle_mult_x_1_n1567) );
NAND2X1TS U4494 ( .A(n2097), .B(n2096), .Y(n2098) );
XNOR2X2TS U4495 ( .A(n2099), .B(n2098), .Y(n2665) );
AOI222XLTS U4496 ( .A0(n2488), .A1(n2352), .B0(n2531), .B1(n2591), .C0(n2590), .C1(n2657), .Y(n2100) );
OAI21X1TS U4497 ( .A0(n2285), .A1(n2491), .B0(n2103), .Y(n2104) );
XOR2X1TS U4498 ( .A(n2104), .B(n2552), .Y(genblk1_middle_mult_x_1_n1430) );
AOI21X1TS U4499 ( .A0(n2795), .A1(n301), .B0(n2105), .Y(n2106) );
XOR2X1TS U4500 ( .A(n2107), .B(n2596), .Y(genblk1_middle_mult_x_1_n1553) );
AOI222X1TS U4501 ( .A0(n2781), .A1(n2670), .B0(n311), .B1(n2669), .C0(n2778),
.C1(n2642), .Y(n2109) );
XOR2X1TS U4502 ( .A(n2110), .B(n2766), .Y(genblk1_middle_mult_x_1_n1326) );
NAND2X1TS U4503 ( .A(n2112), .B(n2111), .Y(n2113) );
XNOR2X1TS U4504 ( .A(n2114), .B(n2113), .Y(genblk1_middle_N44) );
NAND2X1TS U4505 ( .A(n2115), .B(n2119), .Y(n2122) );
AOI21X1TS U4506 ( .A0(n2120), .A1(n2119), .B0(n2118), .Y(n2121) );
OAI21X1TS U4507 ( .A0(n2123), .A1(n2122), .B0(n2121), .Y(n2127) );
NAND2X1TS U4508 ( .A(n1627), .B(n2125), .Y(n2126) );
XOR2X2TS U4509 ( .A(n2127), .B(n2126), .Y(n2460) );
AOI222XLTS U4510 ( .A0(n2721), .A1(n2457), .B0(n2427), .B1(n2383), .C0(n2426), .C1(n2371), .Y(n2128) );
XOR2X1TS U4511 ( .A(n2129), .B(n2465), .Y(genblk1_middle_mult_x_1_n1493) );
XOR2X1TS U4512 ( .A(n2131), .B(n2800), .Y(genblk1_middle_mult_x_1_n1524) );
AOI222XLTS U4513 ( .A0(n1989), .A1(n2457), .B0(n2443), .B1(n2456), .C0(n2442), .C1(n2401), .Y(n2132) );
XOR2X1TS U4514 ( .A(n2133), .B(n2815), .Y(genblk1_middle_mult_x_1_n1462) );
NAND2X1TS U4515 ( .A(n2479), .B(n2315), .Y(n2134) );
XOR2X1TS U4516 ( .A(n2135), .B(n2552), .Y(genblk1_middle_mult_x_1_n1428) );
NAND2X1TS U4517 ( .A(n2137), .B(n2136), .Y(n2138) );
XNOR2X1TS U4518 ( .A(n2139), .B(n2138), .Y(genblk1_middle_N46) );
NAND2X1TS U4519 ( .A(n2426), .B(n2681), .Y(n2140) );
XOR2X1TS U4520 ( .A(n2141), .B(n2193), .Y(genblk1_middle_mult_x_1_n1490) );
NAND2X1TS U4521 ( .A(n2143), .B(n2142), .Y(n2144) );
XNOR2X1TS U4522 ( .A(n2145), .B(n2144), .Y(genblk1_middle_N50) );
AOI222X1TS U4523 ( .A0(n2781), .A1(n2669), .B0(n2760), .B1(n2146), .C0(n291),
.C1(n2803), .Y(n2147) );
NAND2X1TS U4524 ( .A(n2151), .B(n2150), .Y(n2152) );
XNOR2X1TS U4525 ( .A(n2153), .B(n2152), .Y(genblk1_middle_N40) );
NAND2X1TS U4526 ( .A(n2155), .B(n2154), .Y(n2156) );
XNOR2X1TS U4527 ( .A(n2157), .B(n2156), .Y(genblk1_middle_N48) );
AOI222XLTS U4528 ( .A0(n2795), .A1(n2543), .B0(n2792), .B1(n2351), .C0(n2371), .C1(n300), .Y(n2158) );
OAI21X1TS U4529 ( .A0(n2460), .A1(n2515), .B0(n2158), .Y(n2159) );
AND2X2TS U4530 ( .A(n2475), .B(n2802), .Y(n2160) );
CMPR32X2TS U4531 ( .A(n2162), .B(n2161), .C(n2160), .CO(
genblk1_middle_mult_x_1_n651), .S(genblk1_middle_mult_x_1_n652) );
AOI222XLTS U4532 ( .A0(n2762), .A1(n2509), .B0(n310), .B1(n2544), .C0(n2759),
.C1(n2542), .Y(n2163) );
OAI21X1TS U4533 ( .A0(n2477), .A1(n303), .B0(n2163), .Y(n2164) );
XOR2X1TS U4534 ( .A(n2164), .B(n2225), .Y(n2165) );
CMPR32X2TS U4535 ( .A(n2167), .B(n2166), .C(n2165), .CO(
genblk1_middle_mult_x_1_n659), .S(genblk1_middle_mult_x_1_n660) );
CMPR32X2TS U4536 ( .A(n2169), .B(n2170), .C(n2168), .CO(
genblk1_middle_mult_x_1_n611), .S(genblk1_middle_mult_x_1_n612) );
INVX2TS U4537 ( .A(n2170), .Y(n2689) );
AOI222XLTS U4538 ( .A0(n2662), .A1(n2383), .B0(n2646), .B1(n2355), .C0(n2391), .C1(n2326), .Y(n2171) );
CMPR32X2TS U4539 ( .A(n2689), .B(genblk1_middle_mult_x_1_n628), .C(n2173),
.CO(genblk1_middle_mult_x_1_n622), .S(genblk1_middle_mult_x_1_n623) );
AOI222XLTS U4540 ( .A0(n2730), .A1(n2761), .B0(n2728), .B1(n2790), .C0(n2726), .C1(n2758), .Y(n2174) );
XOR2X1TS U4541 ( .A(n2175), .B(n2812), .Y(n2182) );
AOI222XLTS U4542 ( .A0(n2721), .A1(n2670), .B0(n2555), .B1(n2108), .C0(n2554), .C1(n2642), .Y(n2176) );
OAI21XLTS U4543 ( .A0(n19), .A1(n2723), .B0(n2176), .Y(n2177) );
XOR2X1TS U4544 ( .A(n2177), .B(n2724), .Y(n2181) );
CMPR32X2TS U4545 ( .A(n2182), .B(n2181), .C(n2180), .CO(
genblk1_middle_mult_x_1_n955), .S(genblk1_middle_mult_x_1_n956) );
XOR2X1TS U4546 ( .A(n2184), .B(n2666), .Y(genblk1_middle_mult_x_1_n1355) );
AOI222X1TS U4547 ( .A0(n2781), .A1(n2556), .B0(n310), .B1(n2776), .C0(n2778),
.C1(n2582), .Y(n2185) );
XOR2X1TS U4548 ( .A(n2186), .B(n2225), .Y(genblk1_middle_mult_x_1_n1324) );
AOI222X1TS U4549 ( .A0(n2762), .A1(n2433), .B0(n310), .B1(n2432), .C0(n2455),
.C1(n2533), .Y(n2187) );
XOR2X1TS U4550 ( .A(n2190), .B(n2193), .Y(genblk1_middle_mult_x_1_n1492) );
AOI21X1TS U4551 ( .A0(n2426), .A1(n2771), .B0(n2191), .Y(n2192) );
XOR2X1TS U4552 ( .A(n2194), .B(n2193), .Y(genblk1_middle_mult_x_1_n1491) );
AOI21X1TS U4553 ( .A0(n2442), .A1(n2771), .B0(n2195), .Y(n2196) );
XOR2X1TS U4554 ( .A(n2197), .B(n2815), .Y(genblk1_middle_mult_x_1_n1460) );
AOI222XLTS U4555 ( .A0(n2730), .A1(n2796), .B0(n2443), .B1(n2223), .C0(n2442), .C1(n2792), .Y(n2198) );
OAI21X1TS U4556 ( .A0(n2285), .A1(n2811), .B0(n2198), .Y(n2199) );
NAND2X1TS U4557 ( .A(n2442), .B(n2681), .Y(n2200) );
XOR2X1TS U4558 ( .A(n2201), .B(n2815), .Y(genblk1_middle_mult_x_1_n1459) );
AOI222XLTS U4559 ( .A0(n2762), .A1(n2489), .B0(n310), .B1(n2488), .C0(n2778),
.C1(n2559), .Y(n2202) );
XOR2X1TS U4560 ( .A(n2203), .B(n2785), .Y(genblk1_middle_mult_x_1_n1319) );
AOI222XLTS U4561 ( .A0(n2348), .A1(n2780), .B0(n295), .B1(n2528), .C0(n309),
.C1(n2777), .Y(n2204) );
AOI21X1TS U4562 ( .A0(n2391), .A1(n2771), .B0(n2206), .Y(n2207) );
AOI222XLTS U4563 ( .A0(n2416), .A1(n2383), .B0(n2415), .B1(n2355), .C0(n304),
.C1(n2387), .Y(n2209) );
OAI21X1TS U4564 ( .A0(n2357), .A1(n2684), .B0(n2209), .Y(n2210) );
XOR2X1TS U4565 ( .A(n2210), .B(n2424), .Y(genblk1_middle_mult_x_1_n1370) );
AOI222XLTS U4566 ( .A0(n2740), .A1(n2796), .B0(n2415), .B1(n2457), .C0(n305),
.C1(n2792), .Y(n2211) );
AOI222XLTS U4567 ( .A0(n2662), .A1(n2457), .B0(n2646), .B1(n2383), .C0(n2391), .C1(n2401), .Y(n2213) );
XOR2X1TS U4568 ( .A(n2215), .B(n2214), .Y(genblk1_middle_mult_x_1_n1338) );
AOI222XLTS U4569 ( .A0(n2416), .A1(n2457), .B0(n2415), .B1(n2383), .C0(n305),
.C1(n2401), .Y(n2216) );
OAI21X1TS U4570 ( .A0(n2460), .A1(n2362), .B0(n2216), .Y(n2217) );
AOI222XLTS U4571 ( .A0(n2416), .A1(n2401), .B0(n2415), .B1(n2376), .C0(n304),
.C1(n2406), .Y(n2218) );
XOR2X1TS U4572 ( .A(n2219), .B(n2424), .Y(genblk1_middle_mult_x_1_n1371) );
XOR2X1TS U4573 ( .A(n2221), .B(n2686), .Y(genblk1_middle_mult_x_1_n1386) );
AOI222XLTS U4574 ( .A0(n2762), .A1(n2796), .B0(n311), .B1(n2223), .C0(n2455),
.C1(n2222), .Y(n2224) );
XOR2X1TS U4575 ( .A(n2230), .B(n2706), .Y(genblk1_middle_mult_x_1_n1454) );
XOR2X1TS U4576 ( .A(n2232), .B(n2526), .Y(genblk1_middle_mult_x_1_n1403) );
AOI222XLTS U4577 ( .A0(n2416), .A1(n2661), .B0(n2674), .B1(n2659), .C0(n304),
.C1(n2579), .Y(n2233) );
XOR2X1TS U4578 ( .A(n2234), .B(n2686), .Y(genblk1_middle_mult_x_1_n1382) );
XOR2X1TS U4579 ( .A(n2236), .B(n2686), .Y(genblk1_middle_mult_x_1_n1383) );
AOI222XLTS U4580 ( .A0(n2692), .A1(n2533), .B0(n2748), .B1(n2659), .C0(n1961), .C1(n2579), .Y(n2239) );
XOR2X1TS U4581 ( .A(n2240), .B(n2753), .Y(genblk1_middle_mult_x_1_n1413) );
AOI222XLTS U4582 ( .A0(n293), .A1(n2504), .B0(n2415), .B1(n2521), .C0(n2736),
.C1(n2243), .Y(n2244) );
AOI222XLTS U4583 ( .A0(n2564), .A1(n2780), .B0(n2807), .B1(n2779), .C0(n2562), .C1(n2653), .Y(n2246) );
XOR2X1TS U4584 ( .A(n2247), .B(n2815), .Y(genblk1_middle_mult_x_1_n1477) );
AOI222XLTS U4585 ( .A0(n2407), .A1(n2533), .B0(n2559), .B1(n2794), .C0(n2772), .C1(n2657), .Y(n2248) );
AOI222XLTS U4586 ( .A0(n2703), .A1(n2556), .B0(n2550), .B1(n2776), .C0(n2549), .C1(n2582), .Y(n2250) );
AOI222XLTS U4587 ( .A0(n2416), .A1(n2497), .B0(n2738), .B1(n2504), .C0(n305),
.C1(n2510), .Y(n2252) );
INVX2TS U4588 ( .A(n2254), .Y(n2256) );
NAND2X1TS U4589 ( .A(n2259), .B(n2258), .Y(n2260) );
AOI21X1TS U4590 ( .A0(n1390), .A1(n2264), .B0(n2263), .Y(n2269) );
NAND2X1TS U4591 ( .A(n2267), .B(n2266), .Y(n2268) );
AOI21X1TS U4592 ( .A0(n1390), .A1(n2271), .B0(n2270), .Y(n2274) );
NAND2X1TS U4593 ( .A(n366), .B(n2272), .Y(n2273) );
AOI21X1TS U4594 ( .A0(n2278), .A1(n2277), .B0(n2276), .Y(n2283) );
NAND2X1TS U4595 ( .A(n2281), .B(n2280), .Y(n2282) );
XOR2X1TS U4596 ( .A(n2286), .B(result_A_adder_2_), .Y(
genblk1_middle_mult_x_1_n1554) );
AOI222X1TS U4597 ( .A0(n2458), .A1(n2661), .B0(n311), .B1(n2531), .C0(n2778),
.C1(n2657), .Y(n2287) );
AOI222X1TS U4598 ( .A0(n2781), .A1(n2747), .B0(n311), .B1(n2746), .C0(n2778),
.C1(n2791), .Y(n2289) );
AOI222X1TS U4599 ( .A0(n2781), .A1(n2528), .B0(n311), .B1(n2653), .C0(n2778),
.C1(n2671), .Y(n2291) );
NAND2X1TS U4600 ( .A(n2295), .B(n2294), .Y(n2296) );
NAND2X1TS U4601 ( .A(n2300), .B(n2299), .Y(n2301) );
AOI21X1TS U4602 ( .A0(n16), .A1(n2305), .B0(n2304), .Y(n2310) );
NAND2X1TS U4603 ( .A(n2308), .B(n2307), .Y(n2309) );
AOI222XLTS U4604 ( .A0(n2330), .A1(n2493), .B0(n2660), .B1(n2433), .C0(n309),
.C1(n2539), .Y(n2311) );
XOR2X1TS U4605 ( .A(n2312), .B(n2394), .Y(genblk1_middle_mult_x_1_n1348) );
AOI222XLTS U4606 ( .A0(n2458), .A1(n2497), .B0(n2760), .B1(n2511), .C0(n2455), .C1(n2641), .Y(n2313) );
XOR2X1TS U4607 ( .A(n2314), .B(n2785), .Y(genblk1_middle_mult_x_1_n1313) );
AOI21X1TS U4608 ( .A0(n2479), .A1(n2771), .B0(n2316), .Y(n2317) );
XOR2X1TS U4609 ( .A(n2319), .B(n2552), .Y(genblk1_middle_mult_x_1_n1429) );
AOI222XLTS U4610 ( .A0(n2498), .A1(n2457), .B0(n2503), .B1(n2456), .C0(n2479), .C1(n2454), .Y(n2320) );
XOR2X1TS U4611 ( .A(n2321), .B(n2507), .Y(genblk1_middle_mult_x_1_n1431) );
INVX2TS U4612 ( .A(genblk1_middle_mult_x_1_n1017), .Y(
genblk1_middle_mult_x_1_n699) );
AOI222XLTS U4613 ( .A0(n2781), .A1(n2659), .B0(n311), .B1(n2563), .C0(n2778),
.C1(n2578), .Y(n2322) );
XOR2X1TS U4614 ( .A(n2323), .B(n2225), .Y(genblk1_middle_mult_x_1_n1321) );
NAND2X1TS U4615 ( .A(n2681), .B(n300), .Y(n2324) );
OAI21X1TS U4616 ( .A0(n2685), .A1(n2594), .B0(n2324), .Y(n2325) );
AOI222XLTS U4617 ( .A0(n2439), .A1(n2792), .B0(n2427), .B1(n2371), .C0(n2426), .C1(n2326), .Y(n2327) );
OAI21X1TS U4618 ( .A0(n2357), .A1(n2328), .B0(n2327), .Y(n2329) );
AOI222XLTS U4619 ( .A0(n2330), .A1(n2521), .B0(n2660), .B1(n2509), .C0(n309),
.C1(n2544), .Y(n2331) );
AOI222XLTS U4620 ( .A0(n2458), .A1(n2480), .B0(n310), .B1(n2680), .C0(n2455),
.C1(n2511), .Y(n2333) );
XOR2X1TS U4621 ( .A(n2334), .B(n2785), .Y(genblk1_middle_mult_x_1_n1312) );
NAND2X1TS U4622 ( .A(n2793), .B(n2681), .Y(n2335) );
OAI21X1TS U4623 ( .A0(n2685), .A1(n2409), .B0(n2335), .Y(n2337) );
AOI222XLTS U4624 ( .A0(n2498), .A1(n2383), .B0(n2503), .B1(n2371), .C0(n2479), .C1(n2387), .Y(n2338) );
XOR2X1TS U4625 ( .A(n2339), .B(n2507), .Y(genblk1_middle_mult_x_1_n1432) );
AOI222XLTS U4626 ( .A0(n2407), .A1(n2792), .B0(n2401), .B1(n2532), .C0(n2793), .C1(n2387), .Y(n2340) );
OAI21X1TS U4627 ( .A0(n2357), .A1(n2768), .B0(n2340), .Y(n2341) );
NAND2X1TS U4628 ( .A(n2450), .B(n2681), .Y(n2342) );
OAI21X1TS U4629 ( .A0(n2685), .A1(n2524), .B0(n2342), .Y(n2344) );
INVX2TS U4630 ( .A(genblk1_middle_mult_x_1_n1011), .Y(
genblk1_middle_mult_x_1_n644) );
AOI222XLTS U4631 ( .A0(n2762), .A1(n2504), .B0(n310), .B1(n2641), .C0(n2759),
.C1(n2345), .Y(n2346) );
XOR2X1TS U4632 ( .A(n2347), .B(n2785), .Y(genblk1_middle_mult_x_1_n1314) );
AOI222XLTS U4633 ( .A0(n2348), .A1(n2528), .B0(n2660), .B1(n2556), .C0(n309),
.C1(n2671), .Y(n2349) );
INVX2TS U4634 ( .A(genblk1_middle_mult_x_1_n1016), .Y(
genblk1_middle_mult_x_1_n689) );
AOI222XLTS U4635 ( .A0(n2454), .A1(n2352), .B0(n2387), .B1(n2351), .C0(n2397), .C1(n300), .Y(n2353) );
AOI222XLTS U4636 ( .A0(n2692), .A1(n2792), .B0(n1964), .B1(n2355), .C0(n2450), .C1(n2387), .Y(n2356) );
XOR2X1TS U4637 ( .A(n2358), .B(n2526), .Y(genblk1_middle_mult_x_1_n1401) );
AOI222X1TS U4638 ( .A0(n293), .A1(n2700), .B0(n2674), .B1(n2359), .C0(n2736),
.C1(n2709), .Y(n2360) );
AOI21X1TS U4639 ( .A0(n2366), .A1(n2365), .B0(n2364), .Y(n2370) );
NAND2X1TS U4640 ( .A(n2368), .B(n2367), .Y(n2369) );
AOI222XLTS U4641 ( .A0(n2692), .A1(n2371), .B0(n1964), .B1(n2376), .C0(n2450), .C1(n2406), .Y(n2372) );
XOR2X1TS U4642 ( .A(n2373), .B(n2526), .Y(genblk1_middle_mult_x_1_n1402) );
AOI222XLTS U4643 ( .A0(n2458), .A1(n2401), .B0(n311), .B1(n2400), .C0(n2455),
.C1(n2405), .Y(n2374) );
XOR2X1TS U4644 ( .A(n2375), .B(n2225), .Y(genblk1_middle_mult_x_1_n1309) );
XOR2X1TS U4645 ( .A(n2378), .B(n2507), .Y(genblk1_middle_mult_x_1_n1434) );
NAND2X1TS U4646 ( .A(n2380), .B(n2379), .Y(n2381) );
AOI222XLTS U4647 ( .A0(n2692), .A1(n2795), .B0(n1964), .B1(n2383), .C0(n2450), .C1(n2454), .Y(n2384) );
AOI222XLTS U4648 ( .A0(n2407), .A1(n2387), .B0(n2406), .B1(n2532), .C0(n2386), .C1(n2451), .Y(n2388) );
OAI21X1TS U4649 ( .A0(n2389), .A1(n2768), .B0(n2388), .Y(n2390) );
AOI222XLTS U4650 ( .A0(n2662), .A1(n2397), .B0(n295), .B1(n2480), .C0(n2391),
.C1(n2680), .Y(n2392) );
AOI222XLTS U4651 ( .A0(n2498), .A1(n2397), .B0(n2702), .B1(n2396), .C0(n2479), .C1(n2483), .Y(n2398) );
XOR2X1TS U4652 ( .A(n2399), .B(n2507), .Y(genblk1_middle_mult_x_1_n1435) );
AOI222XLTS U4653 ( .A0(n2498), .A1(n2401), .B0(n2503), .B1(n2400), .C0(n2479), .C1(n2406), .Y(n2402) );
INVX2TS U4654 ( .A(genblk1_middle_mult_x_1_n1005), .Y(
genblk1_middle_mult_x_1_n607) );
AOI222XLTS U4655 ( .A0(n2407), .A1(n2406), .B0(n2451), .B1(n2794), .C0(n2793), .C1(n2483), .Y(n2408) );
XOR2X1TS U4656 ( .A(n2412), .B(n2411), .Y(genblk1_middle_mult_x_1_n1528) );
AOI222XLTS U4657 ( .A0(n2498), .A1(n2661), .B0(n2550), .B1(n2531), .C0(n2549), .C1(n2657), .Y(n2413) );
XOR2X1TS U4658 ( .A(n2414), .B(n2552), .Y(genblk1_middle_mult_x_1_n1444) );
AOI222XLTS U4659 ( .A0(n2416), .A1(n2480), .B0(n2415), .B1(n2497), .C0(n304),
.C1(n2522), .Y(n2417) );
XOR2X1TS U4660 ( .A(n2418), .B(n2424), .Y(genblk1_middle_mult_x_1_n1374) );
AOI222XLTS U4661 ( .A0(n2749), .A1(n2582), .B0(n2748), .B1(n2108), .C0(n1961), .C1(n2419), .Y(n2420) );
XOR2X1TS U4662 ( .A(n2421), .B(n2714), .Y(genblk1_middle_mult_x_1_n1419) );
XOR2X1TS U4663 ( .A(n2425), .B(n2424), .Y(genblk1_middle_mult_x_1_n1377) );
AOI222XLTS U4664 ( .A0(n2439), .A1(n2451), .B0(n2427), .B1(n2497), .C0(n2426), .C1(n2511), .Y(n2428) );
OAI21X1TS U4665 ( .A0(n2486), .A1(n2464), .B0(n2428), .Y(n2429) );
AOI222XLTS U4666 ( .A0(n293), .A1(n2433), .B0(n2674), .B1(n2489), .C0(n304),
.C1(n2488), .Y(n2430) );
XOR2X1TS U4667 ( .A(n2431), .B(n2743), .Y(genblk1_middle_mult_x_1_n1380) );
AOI222XLTS U4668 ( .A0(n2695), .A1(n2433), .B0(n2702), .B1(n2432), .C0(n2549), .C1(n2533), .Y(n2434) );
AOI222XLTS U4669 ( .A0(n2711), .A1(n2542), .B0(n2710), .B1(n2489), .C0(n2450), .C1(n2488), .Y(n2436) );
XOR2X1TS U4670 ( .A(n2438), .B(n2714), .Y(genblk1_middle_mult_x_1_n1411) );
AOI222XLTS U4671 ( .A0(n2439), .A1(n2661), .B0(n2555), .B1(n2659), .C0(n2554), .C1(n2657), .Y(n2440) );
XOR2X1TS U4672 ( .A(n2441), .B(n2193), .Y(genblk1_middle_mult_x_1_n1506) );
AOI222XLTS U4673 ( .A0(n1989), .A1(n2480), .B0(n2443), .B1(n2680), .C0(n2442), .C1(n2522), .Y(n2444) );
AOI222XLTS U4674 ( .A0(n2695), .A1(n2509), .B0(n2702), .B1(n2544), .C0(n2701), .C1(n2542), .Y(n2448) );
XOR2X1TS U4675 ( .A(n2449), .B(n2507), .Y(genblk1_middle_mult_x_1_n1440) );
AOI222XLTS U4676 ( .A0(n2692), .A1(n2451), .B0(n1964), .B1(n2497), .C0(n2450), .C1(n2522), .Y(n2452) );
OAI21X1TS U4677 ( .A0(n2486), .A1(n2524), .B0(n2452), .Y(n2453) );
AOI222XLTS U4678 ( .A0(n2458), .A1(n2457), .B0(n310), .B1(n2456), .C0(n2455),
.C1(n2454), .Y(n2459) );
AOI222XLTS U4679 ( .A0(n2462), .A1(n2510), .B0(n2720), .B1(n2509), .C0(n2718), .C1(n2544), .Y(n2463) );
OAI21X1TS U4680 ( .A0(n2495), .A1(n2464), .B0(n2463), .Y(n2466) );
AOI21X1TS U4681 ( .A0(n2468), .A1(n356), .B0(n2467), .Y(n2472) );
NAND2X1TS U4682 ( .A(n2470), .B(n2469), .Y(n2471) );
AOI222XLTS U4683 ( .A0(n1989), .A1(n2661), .B0(n2807), .B1(n2531), .C0(n2562), .C1(n2579), .Y(n2473) );
XOR2X1TS U4684 ( .A(n2474), .B(n2815), .Y(genblk1_middle_mult_x_1_n1475) );
AOI222XLTS U4685 ( .A0(n2711), .A1(n2520), .B0(n2710), .B1(n2493), .C0(n2708), .C1(n2475), .Y(n2476) );
OAI21X1TS U4686 ( .A0(n2477), .A1(n2524), .B0(n2476), .Y(n2478) );
XOR2X1TS U4687 ( .A(n2478), .B(n2526), .Y(genblk1_middle_mult_x_1_n1409) );
AOI222XLTS U4688 ( .A0(n2498), .A1(n2480), .B0(n2503), .B1(n2680), .C0(n2479), .C1(n2522), .Y(n2481) );
AOI222XLTS U4689 ( .A0(n2695), .A1(n2489), .B0(n2503), .B1(n2488), .C0(n2549), .C1(n2531), .Y(n2490) );
OAI21X1TS U4690 ( .A0(n2495), .A1(n2546), .B0(n2494), .Y(n2496) );
AOI222XLTS U4691 ( .A0(n2498), .A1(n2497), .B0(n2702), .B1(n2511), .C0(n2549), .C1(n2510), .Y(n2499) );
AOI222XLTS U4692 ( .A0(n2695), .A1(n2504), .B0(n2503), .B1(n2641), .C0(n2701), .C1(n2520), .Y(n2505) );
XOR2X1TS U4693 ( .A(n2513), .B(n4983), .Y(genblk1_middle_mult_x_1_n1562) );
XOR2X1TS U4694 ( .A(n2517), .B(n4983), .Y(genblk1_middle_mult_x_1_n1561) );
AOI222XLTS U4695 ( .A0(n2749), .A1(n2657), .B0(n2748), .B1(n2528), .C0(n1961), .C1(n2653), .Y(n2518) );
AOI222XLTS U4696 ( .A0(n2711), .A1(n2522), .B0(n1964), .B1(n2521), .C0(n2708), .C1(n2520), .Y(n2523) );
OAI21X1TS U4697 ( .A0(n2525), .A1(n2524), .B0(n2523), .Y(n2527) );
XOR2X1TS U4698 ( .A(n2530), .B(n2193), .Y(genblk1_middle_mult_x_1_n1508) );
AOI222XLTS U4699 ( .A0(n1258), .A1(n2539), .B0(n2533), .B1(n2532), .C0(n2772), .C1(n2531), .Y(n2534) );
AOI222XLTS U4700 ( .A0(n2703), .A1(n2659), .B0(n2550), .B1(n2563), .C0(n2549), .C1(n2578), .Y(n2537) );
AOI222XLTS U4701 ( .A0(n2544), .A1(n2543), .B0(n2542), .B1(n2541), .C0(n301),
.C1(n2539), .Y(n2545) );
AOI222XLTS U4702 ( .A0(n2703), .A1(n2780), .B0(n2550), .B1(n2779), .C0(n2549), .C1(n2777), .Y(n2551) );
XOR2X1TS U4703 ( .A(n2553), .B(n2552), .Y(genblk1_middle_mult_x_1_n1446) );
AOI222XLTS U4704 ( .A0(n2721), .A1(n2556), .B0(n2555), .B1(n2747), .C0(n2554), .C1(n2582), .Y(n2557) );
AOI222XLTS U4705 ( .A0(n2569), .A1(n2559), .B0(n2657), .B1(n2794), .C0(n2772), .C1(n2578), .Y(n2560) );
AOI222XLTS U4706 ( .A0(n2564), .A1(n2659), .B0(n2807), .B1(n2563), .C0(n2562), .C1(n2779), .Y(n2565) );
AOI222XLTS U4707 ( .A0(n2573), .A1(n2352), .B0(n2657), .B1(n2591), .C0(n2590), .C1(n2578), .Y(n2574) );
AOI222XLTS U4708 ( .A0(n2579), .A1(n2352), .B0(n2578), .B1(n2591), .C0(n2590), .C1(n2777), .Y(n2580) );
AOI222XLTS U4709 ( .A0(n2653), .A1(n2592), .B0(n2671), .B1(n2591), .C0(n2590), .C1(n2582), .Y(n2583) );
NAND2X1TS U4710 ( .A(n2587), .B(n2586), .Y(n2588) );
AOI222XLTS U4711 ( .A0(n2779), .A1(n2592), .B0(n2777), .B1(n2591), .C0(n2590), .C1(n2671), .Y(n2593) );
NAND2X1TS U4712 ( .A(n2600), .B(n2599), .Y(n2601) );
AOI21X1TS U4713 ( .A0(n2605), .A1(n2604), .B0(n2603), .Y(n2608) );
NAND2X1TS U4714 ( .A(n357), .B(n2606), .Y(n2607) );
NAND2X1TS U4715 ( .A(n2611), .B(n2610), .Y(n2612) );
NAND2X1TS U4716 ( .A(n2616), .B(n2615), .Y(n2617) );
NAND2X1TS U4717 ( .A(n2621), .B(n2620), .Y(n2623) );
INVX2TS U4718 ( .A(n2624), .Y(n2626) );
NAND2X1TS U4719 ( .A(n2626), .B(n2625), .Y(n2627) );
NAND2X1TS U4720 ( .A(n2631), .B(n2630), .Y(n2633) );
INVX2TS U4721 ( .A(n2634), .Y(n2636) );
NAND2X1TS U4722 ( .A(n2636), .B(n2635), .Y(n2638) );
AND2X2TS U4723 ( .A(n2645), .B(n2802), .Y(genblk1_middle_mult_x_1_n1026) );
XOR2X1TS U4724 ( .A(n2644), .B(n2214), .Y(n2650) );
XOR2X1TS U4725 ( .A(n2649), .B(n2214), .Y(n2652) );
ADDHXLTS U4726 ( .A(n2666), .B(n2650), .CO(n2651), .S(
genblk1_middle_mult_x_1_n890) );
ADDHX1TS U4727 ( .A(n2652), .B(n2651), .CO(genblk1_middle_mult_x_1_n878),
.S(genblk1_middle_mult_x_1_n879) );
INVX2TS U4728 ( .A(n2656), .Y(n2788) );
AOI222X1TS U4729 ( .A0(n2662), .A1(n2661), .B0(n2660), .B1(n2659), .C0(n308),
.C1(n2657), .Y(n2663) );
XOR2X1TS U4730 ( .A(n2667), .B(n2666), .Y(n2668) );
CMPR32X2TS U4731 ( .A(n2788), .B(genblk1_middle_mult_x_1_n744), .C(n2668),
.CO(genblk1_middle_mult_x_1_n732), .S(genblk1_middle_mult_x_1_n733) );
XOR2X1TS U4732 ( .A(n2673), .B(n2714), .Y(n2678) );
XOR2X1TS U4733 ( .A(n2676), .B(n2743), .Y(n2677) );
NAND2X1TS U4734 ( .A(n305), .B(n2681), .Y(n2683) );
CMPR32X2TS U4735 ( .A(n2690), .B(n2689), .C(n2688), .CO(
genblk1_middle_mult_x_1_n616), .S(genblk1_middle_mult_x_1_n617) );
AOI22X1TS U4736 ( .A0(n2692), .A1(n2808), .B0(n2748), .B1(n2691), .Y(n2693)
);
XOR2X1TS U4737 ( .A(n2694), .B(n2714), .Y(n2699) );
AOI222X1TS U4738 ( .A0(n2695), .A1(n2719), .B0(n2702), .B1(n2790), .C0(n2701), .C1(n2729), .Y(n2696) );
XOR2X1TS U4739 ( .A(n2697), .B(n2706), .Y(n2698) );
ADDHX1TS U4740 ( .A(n2699), .B(n2698), .CO(genblk1_middle_mult_x_1_n935),
.S(genblk1_middle_mult_x_1_n936) );
XOR2X1TS U4741 ( .A(n2707), .B(n2706), .Y(n2717) );
XOR2X1TS U4742 ( .A(n2715), .B(n2714), .Y(n2716) );
XOR2X1TS U4743 ( .A(n2725), .B(n2724), .Y(n2735) );
XOR2X1TS U4744 ( .A(n2733), .B(n2812), .Y(n2734) );
AOI222X1TS U4745 ( .A0(n2740), .A1(n2739), .B0(n2674), .B1(n2737), .C0(n2736), .C1(n2761), .Y(n2741) );
OAI21XLTS U4746 ( .A0(n345), .A1(n2742), .B0(n2741), .Y(n2744) );
XOR2X1TS U4747 ( .A(n2744), .B(n2743), .Y(n2757) );
AOI222XLTS U4748 ( .A0(n2749), .A1(n2777), .B0(n2748), .B1(n2747), .C0(n1961), .C1(n2746), .Y(n2750) );
XOR2X1TS U4749 ( .A(n2754), .B(n2753), .Y(n2755) );
XOR2X1TS U4750 ( .A(n2767), .B(n2766), .Y(genblk1_middle_mult_x_1_n1329) );
INVX2TS U4751 ( .A(n2768), .Y(n2798) );
AO21X2TS U4752 ( .A0(n2774), .A1(n2798), .B0(n2773), .Y(n2775) );
XOR2X1TS U4753 ( .A(n2775), .B(n2800), .Y(genblk1_middle_mult_x_1_n1522) );
AOI222X1TS U4754 ( .A0(n2781), .A1(n2780), .B0(n311), .B1(n2779), .C0(n2778),
.C1(n2777), .Y(n2782) );
OAI21X1TS U4755 ( .A0(n2784), .A1(n303), .B0(n2782), .Y(n2786) );
XOR2X1TS U4756 ( .A(n2786), .B(n2785), .Y(n2787) );
AND2X2TS U4757 ( .A(n2790), .B(n2802), .Y(genblk1_middle_mult_x_1_n1024) );
OAI2BB1X1TS U4758 ( .A0N(n2799), .A1N(n2798), .B0(n2797), .Y(n2801) );
XOR2X1TS U4759 ( .A(n2801), .B(n2800), .Y(genblk1_middle_mult_x_1_n1523) );
AND2X2TS U4760 ( .A(n2803), .B(n2802), .Y(genblk1_middle_mult_x_1_n1023) );
XOR2X1TS U4761 ( .A(n2805), .B(n2812), .Y(n2814) );
AOI22X1TS U4762 ( .A0(n2564), .A1(n2808), .B0(n2807), .B1(n2806), .Y(n2809)
);
ADDHXLTS U4763 ( .A(n2815), .B(n2814), .CO(n2816), .S(
genblk1_middle_mult_x_1_n980) );
AFHCONX2TS U4764 ( .A(n2820), .B(n2819), .CI(n2818), .CON(n1449), .S(
genblk1_right_N52) );
AFHCONX2TS U4765 ( .A(genblk1_right_mult_x_1_n523), .B(
genblk1_right_mult_x_1_n521), .CI(n2821), .CON(n1440), .S(
genblk1_right_N50) );
AFHCONX2TS U4766 ( .A(genblk1_right_mult_x_1_n528), .B(
genblk1_right_mult_x_1_n531), .CI(n2822), .CON(n1402), .S(
genblk1_right_N48) );
AFHCINX2TS U4767 ( .CIN(n2823), .B(genblk1_right_mult_x_1_n532), .A(
genblk1_right_mult_x_1_n536), .S(genblk1_right_N47), .CO(n2822) );
INVX2TS U4768 ( .A(n2824), .Y(n3858) );
OAI21X1TS U4769 ( .A0(n3858), .A1(n2826), .B0(n2825), .Y(n3842) );
INVX2TS U4770 ( .A(n3842), .Y(n3850) );
INVX2TS U4771 ( .A(n3819), .Y(n3828) );
OAI21X1TS U4772 ( .A0(n3828), .A1(n2832), .B0(n2831), .Y(n2837) );
INVX2TS U4773 ( .A(n2833), .Y(n2835) );
NAND2X1TS U4774 ( .A(n2835), .B(n2834), .Y(n2836) );
XNOR2X1TS U4775 ( .A(n2837), .B(n2836), .Y(genblk1_right_N46) );
OAI21X1TS U4776 ( .A0(n3828), .A1(n2841), .B0(n2840), .Y(n2845) );
NAND2X1TS U4777 ( .A(n2843), .B(n2842), .Y(n2844) );
XNOR2X1TS U4778 ( .A(n2845), .B(n2844), .Y(genblk1_right_N45) );
OAI21X1TS U4779 ( .A0(n3850), .A1(n2847), .B0(n2846), .Y(n2857) );
AOI21X1TS U4780 ( .A0(n2857), .A1(n2855), .B0(n2848), .Y(n3816) );
NAND2X1TS U4781 ( .A(n2851), .B(n2850), .Y(n2852) );
XNOR2X1TS U4782 ( .A(n2853), .B(n2852), .Y(genblk1_right_N42) );
NAND2X1TS U4783 ( .A(n2855), .B(n2854), .Y(n2856) );
XNOR2X1TS U4784 ( .A(n2857), .B(n2856), .Y(genblk1_right_N40) );
INVX2TS U4785 ( .A(n3836), .Y(n3853) );
OAI21X1TS U4786 ( .A0(n3853), .A1(n2863), .B0(n2862), .Y(n3831) );
NAND2X1TS U4787 ( .A(n3830), .B(n2864), .Y(n2865) );
XNOR2X1TS U4788 ( .A(n3831), .B(n2865), .Y(genblk1_right_N36) );
NAND2X1TS U4789 ( .A(n2868), .B(n2867), .Y(n2869) );
XNOR2X1TS U4790 ( .A(n2870), .B(n2869), .Y(genblk1_right_N33) );
CLKINVX1TS U4791 ( .A(n2871), .Y(n3867) );
AOI21X1TS U4792 ( .A0(n3867), .A1(n2873), .B0(n2872), .Y(n3863) );
NAND2X1TS U4793 ( .A(n2876), .B(n2875), .Y(n2877) );
XNOR2X1TS U4794 ( .A(n2878), .B(n2877), .Y(genblk1_right_N31) );
INVX2TS U4795 ( .A(n2879), .Y(n3866) );
NAND2X1TS U4796 ( .A(n3866), .B(n3864), .Y(n2880) );
XNOR2X1TS U4797 ( .A(n3867), .B(n2880), .Y(genblk1_right_N28) );
INVX2TS U4798 ( .A(n2881), .Y(n3887) );
NAND2X1TS U4799 ( .A(n360), .B(n2884), .Y(n2885) );
XNOR2X1TS U4800 ( .A(n3874), .B(n2885), .Y(genblk1_right_N26) );
NAND2X1TS U4801 ( .A(n361), .B(n2887), .Y(n2888) );
XNOR2X1TS U4802 ( .A(n2889), .B(n2888), .Y(genblk1_right_N25) );
INVX2TS U4803 ( .A(n2890), .Y(n3891) );
AOI21X1TS U4804 ( .A0(n3891), .A1(n2892), .B0(n2891), .Y(n3883) );
NAND2X1TS U4805 ( .A(n2895), .B(n2894), .Y(n2896) );
XNOR2X1TS U4806 ( .A(n2897), .B(n2896), .Y(genblk1_right_N23) );
INVX2TS U4807 ( .A(n2898), .Y(n3890) );
NAND2X1TS U4808 ( .A(n3890), .B(n3888), .Y(n2899) );
XNOR2X1TS U4809 ( .A(n3891), .B(n2899), .Y(genblk1_right_N20) );
NAND2X1TS U4810 ( .A(n2903), .B(n2902), .Y(n2904) );
XNOR2X1TS U4811 ( .A(n2905), .B(n2904), .Y(genblk1_right_N19) );
INVX2TS U4812 ( .A(n2906), .Y(n3918) );
INVX2TS U4813 ( .A(n2907), .Y(n2909) );
NAND2X1TS U4814 ( .A(n2909), .B(n2908), .Y(n2910) );
XNOR2X1TS U4815 ( .A(n2911), .B(n2910), .Y(genblk1_right_N16) );
INVX2TS U4816 ( .A(n2912), .Y(n3909) );
NAND2X1TS U4817 ( .A(n3908), .B(n2913), .Y(n2914) );
XNOR2X1TS U4818 ( .A(n3909), .B(n2914), .Y(genblk1_right_N13) );
NAND2X1TS U4819 ( .A(n2916), .B(n2915), .Y(n2917) );
XNOR2X1TS U4820 ( .A(n2918), .B(n2917), .Y(genblk1_right_N12) );
NAND2X1TS U4821 ( .A(n3920), .B(n2919), .Y(n2921) );
INVX2TS U4822 ( .A(n2920), .Y(n3921) );
XNOR2X1TS U4823 ( .A(n2921), .B(n3921), .Y(genblk1_right_N10) );
NAND2X1TS U4824 ( .A(n353), .B(n2922), .Y(n2924) );
XNOR2X1TS U4825 ( .A(n2924), .B(n2923), .Y(genblk1_right_N9) );
NAND2X1TS U4826 ( .A(n3927), .B(n2925), .Y(n2927) );
INVX2TS U4827 ( .A(n2926), .Y(n3928) );
XNOR2X1TS U4828 ( .A(n2927), .B(n3928), .Y(genblk1_right_N7) );
NAND2X1TS U4829 ( .A(n2929), .B(n2928), .Y(n2931) );
XNOR2X1TS U4830 ( .A(n2931), .B(n2930), .Y(genblk1_right_N6) );
NAND2X1TS U4831 ( .A(n2933), .B(n2932), .Y(n2935) );
XNOR2X1TS U4832 ( .A(n2935), .B(n2934), .Y(genblk1_right_N4) );
XNOR2X1TS U4833 ( .A(n2938), .B(n2937), .Y(genblk1_right_N2) );
CMPR32X2TS U4834 ( .A(n277), .B(n2942), .C(n2941), .CO(
genblk1_right_mult_x_1_n533), .S(genblk1_right_mult_x_1_n534) );
INVX2TS U4835 ( .A(n2942), .Y(n2952) );
XNOR2X1TS U4836 ( .A(n258), .B(Data_A_i[18]), .Y(n3007) );
XNOR2X1TS U4837 ( .A(Data_A_i[18]), .B(Data_A_i[19]), .Y(n2947) );
AND3X1TS U4838 ( .A(n3008), .B(n3007), .C(n2947), .Y(n3343) );
NAND2X1TS U4839 ( .A(n3343), .B(n43), .Y(n2943) );
CMPR32X2TS U4840 ( .A(n2946), .B(n2952), .C(n2945), .CO(
genblk1_right_mult_x_1_n538), .S(genblk1_right_mult_x_1_n539) );
NOR2BX1TS U4841 ( .AN(n3007), .B(n2947), .Y(n3372) );
CLKBUFX2TS U4842 ( .A(n3372), .Y(n3744) );
AOI21X1TS U4843 ( .A0(n3343), .A1(n176), .B0(n2948), .Y(n2949) );
CMPR32X2TS U4844 ( .A(n2952), .B(genblk1_right_mult_x_1_n550), .C(n2951),
.CO(genblk1_right_mult_x_1_n544), .S(genblk1_right_mult_x_1_n545) );
CMPR32X2TS U4845 ( .A(n261), .B(n2954), .C(n2953), .CO(
genblk1_right_mult_x_1_n573), .S(genblk1_right_mult_x_1_n574) );
INVX2TS U4846 ( .A(n2954), .Y(n2975) );
XNOR2X1TS U4847 ( .A(n266), .B(Data_A_i[12]), .Y(n3437) );
XNOR2X1TS U4848 ( .A(Data_A_i[12]), .B(Data_A_i[13]), .Y(n3436) );
AND3X1TS U4849 ( .A(n3066), .B(n3437), .C(n3436), .Y(n3456) );
NAND2X1TS U4850 ( .A(n3456), .B(Data_B_i[26]), .Y(n2955) );
CMPR32X2TS U4851 ( .A(n2958), .B(n2975), .C(n2957), .CO(
genblk1_right_mult_x_1_n581), .S(genblk1_right_mult_x_1_n582) );
NOR2XLTS U4852 ( .A(n2959), .B(n3206), .Y(n2962) );
INVX2TS U4853 ( .A(n3228), .Y(n3214) );
NAND2X1TS U4854 ( .A(n2962), .B(n3214), .Y(n2964) );
OAI21XLTS U4855 ( .A0(n2960), .A1(n3206), .B0(n3207), .Y(n2961) );
AOI21X1TS U4856 ( .A0(n3216), .A1(n2962), .B0(n2961), .Y(n2963) );
NAND2X1TS U4857 ( .A(n2967), .B(n2966), .Y(n2968) );
NOR2X1TS U4858 ( .A(n2971), .B(n2970), .Y(n3259) );
CLKBUFX2TS U4859 ( .A(n3259), .Y(n3267) );
CLKBUFX2TS U4860 ( .A(n3256), .Y(n3266) );
AOI222XLTS U4861 ( .A0(n3267), .A1(Data_B_i[15]), .B0(n3266), .B1(n138),
.C0(n299), .C1(n134), .Y(n2972) );
OAI21X1TS U4862 ( .A0(n3701), .A1(n3269), .B0(n2972), .Y(n2973) );
XOR2X1TS U4863 ( .A(n2973), .B(n287), .Y(n2974) );
CMPR32X2TS U4864 ( .A(n2975), .B(genblk1_right_mult_x_1_n599), .C(n2974),
.CO(genblk1_right_mult_x_1_n590), .S(genblk1_right_mult_x_1_n591) );
CMPR32X2TS U4865 ( .A(n269), .B(n2977), .C(n2976), .CO(
genblk1_right_mult_x_1_n631), .S(genblk1_right_mult_x_1_n632) );
INVX2TS U4866 ( .A(n2977), .Y(n2998) );
OAI21X1TS U4867 ( .A0(n3243), .A1(n2979), .B0(n2978), .Y(n2982) );
NAND2X1TS U4868 ( .A(n3239), .B(n3237), .Y(n2981) );
CLKBUFX2TS U4869 ( .A(n298), .Y(n3253) );
AOI222XLTS U4870 ( .A0(n3259), .A1(n210), .B0(n3256), .B1(Data_B_i[9]), .C0(
n3253), .C1(n217), .Y(n2984) );
CMPR32X2TS U4871 ( .A(n2987), .B(n2998), .C(n2986), .CO(
genblk1_right_mult_x_1_n642), .S(genblk1_right_mult_x_1_n643) );
NAND2X1TS U4872 ( .A(n2992), .B(n2991), .Y(n2993) );
AOI222XLTS U4873 ( .A0(n3259), .A1(n215), .B0(n3256), .B1(n219), .C0(n3253),
.C1(n223), .Y(n2995) );
CMPR32X2TS U4874 ( .A(n2998), .B(genblk1_right_mult_x_1_n666), .C(n2997),
.CO(genblk1_right_mult_x_1_n654), .S(genblk1_right_mult_x_1_n655) );
AOI222XLTS U4875 ( .A0(n3267), .A1(n243), .B0(n3266), .B1(n247), .C0(n299),
.C1(n3786), .Y(n2999) );
CLKBUFX2TS U4876 ( .A(n3259), .Y(n3233) );
AOI22X1TS U4877 ( .A0(n3224), .A1(n3743), .B0(n3233), .B1(n247), .Y(n3001)
);
NAND2X1TS U4878 ( .A(n3233), .B(n3723), .Y(n3003) );
XOR2X1TS U4879 ( .A(n3004), .B(n289), .Y(n3031) );
ADDHX1TS U4880 ( .A(n3006), .B(n3005), .CO(genblk1_right_mult_x_1_n740), .S(
n3018) );
NOR2X1TS U4881 ( .A(n3008), .B(n3007), .Y(n3375) );
CLKBUFX2TS U4882 ( .A(n3343), .Y(n3369) );
AOI222XLTS U4883 ( .A0(n3375), .A1(n219), .B0(n3372), .B1(n222), .C0(n3369),
.C1(n226), .Y(n3009) );
XNOR2X1TS U4884 ( .A(n278), .B(Data_A_i[21]), .Y(n3012) );
XOR2X1TS U4885 ( .A(n254), .B(Data_A_i[22]), .Y(n3013) );
XNOR2X1TS U4886 ( .A(Data_A_i[21]), .B(Data_A_i[22]), .Y(n3011) );
NOR2BX1TS U4887 ( .AN(n3012), .B(n3011), .Y(n3326) );
CLKBUFX2TS U4888 ( .A(n3326), .Y(n3303) );
AND3X1TS U4889 ( .A(n3013), .B(n3012), .C(n3011), .Y(n3289) );
CLKBUFX2TS U4890 ( .A(n3289), .Y(n3325) );
AOI222XLTS U4891 ( .A0(n3327), .A1(n230), .B0(n3303), .B1(n235), .C0(n3325),
.C1(n239), .Y(n3014) );
CMPR32X2TS U4892 ( .A(n3018), .B(n3017), .C(n3016), .CO(
genblk1_right_mult_x_1_n738), .S(genblk1_right_mult_x_1_n739) );
ADDHXLTS U4893 ( .A(n3020), .B(n3019), .CO(n3005), .S(n3030) );
CLKBUFX2TS U4894 ( .A(n3327), .Y(n3308) );
AOI222XLTS U4895 ( .A0(n3308), .A1(n235), .B0(n3303), .B1(n239), .C0(n3325),
.C1(n242), .Y(n3021) );
XNOR2X1TS U4896 ( .A(n262), .B(Data_A_i[15]), .Y(n3024) );
NOR2X1TS U4897 ( .A(n3025), .B(n3024), .Y(n3805) );
XNOR2X1TS U4898 ( .A(Data_A_i[15]), .B(Data_A_i[16]), .Y(n3023) );
NOR2BX1TS U4899 ( .AN(n3024), .B(n3023), .Y(n3433) );
AND3X1TS U4900 ( .A(n3025), .B(n3024), .C(n3023), .Y(n3414) );
CLKBUFX2TS U4901 ( .A(n3414), .Y(n3430) );
AOI222XLTS U4902 ( .A0(n3805), .A1(n211), .B0(n3433), .B1(Data_B_i[9]), .C0(
n3430), .C1(n219), .Y(n3026) );
CMPR32X2TS U4903 ( .A(n3030), .B(n3029), .C(n3028), .CO(
genblk1_right_mult_x_1_n751), .S(genblk1_right_mult_x_1_n752) );
ADDHXLTS U4904 ( .A(n288), .B(n3031), .CO(n3019), .S(n3042) );
AOI222XLTS U4905 ( .A0(n3308), .A1(n237), .B0(n3303), .B1(n243), .C0(n3325),
.C1(n247), .Y(n3032) );
AOI222XLTS U4906 ( .A0(n3308), .A1(Data_B_i[2]), .B0(n3303), .B1(n246), .C0(
n3325), .C1(n3786), .Y(n3034) );
XOR2X1TS U4907 ( .A(n3035), .B(n254), .Y(n3044) );
CLKBUFX2TS U4908 ( .A(n3326), .Y(n3307) );
CLKBUFX2TS U4909 ( .A(n3327), .Y(n3311) );
AOI22X1TS U4910 ( .A0(n3307), .A1(n3743), .B0(n3311), .B1(n247), .Y(n3036)
);
NAND2X1TS U4911 ( .A(n3311), .B(n3723), .Y(n3038) );
CMPR32X2TS U4912 ( .A(n3042), .B(n3041), .C(n3040), .CO(
genblk1_right_mult_x_1_n764), .S(genblk1_right_mult_x_1_n765) );
ADDHXLTS U4913 ( .A(n3044), .B(n3043), .CO(n3040), .S(
genblk1_right_mult_x_1_n778) );
ADDHXLTS U4914 ( .A(n3046), .B(n3045), .CO(n3043), .S(
genblk1_right_mult_x_1_n789) );
NAND2X1TS U4915 ( .A(n3742), .B(n3723), .Y(n3048) );
CLKBUFX2TS U4916 ( .A(n3433), .Y(n3804) );
CLKBUFX2TS U4917 ( .A(n3414), .Y(n3803) );
AOI222XLTS U4918 ( .A0(n3749), .A1(n238), .B0(n3804), .B1(n243), .C0(n3803),
.C1(n246), .Y(n3050) );
AOI222XLTS U4919 ( .A0(n3749), .A1(Data_B_i[2]), .B0(n3804), .B1(Data_B_i[1]), .C0(n3803), .C1(n3786), .Y(n3052) );
CLKBUFX2TS U4920 ( .A(n3433), .Y(n3418) );
AOI22X1TS U4921 ( .A0(n3418), .A1(n3743), .B0(n3421), .B1(Data_B_i[1]), .Y(
n3054) );
NAND2X1TS U4922 ( .A(n3421), .B(n3723), .Y(n3056) );
CMPR32X2TS U4923 ( .A(n3061), .B(n3060), .C(n3059), .CO(
genblk1_right_mult_x_1_n827), .S(genblk1_right_mult_x_1_n828) );
ADDHXLTS U4924 ( .A(n3065), .B(n3064), .CO(n3062), .S(
genblk1_right_mult_x_1_n846) );
NOR2X1TS U4925 ( .A(n3066), .B(n3437), .Y(n3799) );
NAND2X1TS U4926 ( .A(n3725), .B(n3743), .Y(n3067) );
XNOR2X1TS U4927 ( .A(Data_A_i[8]), .B(Data_A_i[9]), .Y(n3070) );
NOR2X1TS U4928 ( .A(n3071), .B(n3070), .Y(n3779) );
CLKBUFX2TS U4929 ( .A(n3779), .Y(n3730) );
XNOR2X1TS U4930 ( .A(Data_A_i[9]), .B(Data_A_i[10]), .Y(n3069) );
NOR2BX1TS U4931 ( .AN(n3070), .B(n3069), .Y(n3542) );
CLKBUFX2TS U4932 ( .A(n3542), .Y(n3778) );
AND3X1TS U4933 ( .A(n3071), .B(n3070), .C(n3069), .Y(n3510) );
CLKBUFX2TS U4934 ( .A(n3510), .Y(n3777) );
AOI222XLTS U4935 ( .A0(n3730), .A1(Data_B_i[3]), .B0(n3778), .B1(Data_B_i[2]), .C0(n3777), .C1(n246), .Y(n3072) );
AOI222XLTS U4936 ( .A0(n3730), .A1(n242), .B0(n3778), .B1(Data_B_i[1]), .C0(
n3777), .C1(n3786), .Y(n3074) );
CLKBUFX2TS U4937 ( .A(n3542), .Y(n3525) );
CLKBUFX2TS U4938 ( .A(n3779), .Y(n3528) );
AOI22X1TS U4939 ( .A0(n3525), .A1(n3743), .B0(n3528), .B1(n246), .Y(n3076)
);
NAND2X1TS U4940 ( .A(n3528), .B(n3743), .Y(n3078) );
CMPR32X2TS U4941 ( .A(n3083), .B(n3082), .C(n3081), .CO(
genblk1_right_mult_x_1_n872), .S(genblk1_right_mult_x_1_n873) );
ADDHXLTS U4942 ( .A(n3085), .B(n3084), .CO(n3081), .S(
genblk1_right_mult_x_1_n880) );
ADDHXLTS U4943 ( .A(n3087), .B(n3086), .CO(n3084), .S(
genblk1_right_mult_x_1_n885) );
ADDHXLTS U4944 ( .A(n3089), .B(n3088), .CO(genblk1_right_mult_x_1_n893), .S(
n906) );
NAND2X1TS U4945 ( .A(n3112), .B(n3091), .Y(n3093) );
AOI21X1TS U4946 ( .A0(n3113), .A1(n3091), .B0(n3090), .Y(n3092) );
NAND2X1TS U4947 ( .A(n3096), .B(n3095), .Y(n3097) );
AOI222XLTS U4948 ( .A0(n3267), .A1(n42), .B0(n3224), .B1(n176), .C0(n299),
.C1(Data_B_i[24]), .Y(n3099) );
OAI21XLTS U4949 ( .A0(n362), .A1(n3166), .B0(n3099), .Y(n3100) );
NAND2X1TS U4950 ( .A(n3112), .B(n3117), .Y(n3104) );
AOI21X1TS U4951 ( .A0(n3113), .A1(n3117), .B0(n3102), .Y(n3103) );
NAND2X1TS U4952 ( .A(n3107), .B(n3106), .Y(n3108) );
AOI222XLTS U4953 ( .A0(n3233), .A1(Data_B_i[25]), .B0(n3224), .B1(n128),
.C0(n298), .C1(n171), .Y(n3110) );
OAI21XLTS U4954 ( .A0(n3673), .A1(n3166), .B0(n3110), .Y(n3111) );
NAND2X1TS U4955 ( .A(n3117), .B(n3116), .Y(n3118) );
AOI222XLTS U4956 ( .A0(n3233), .A1(Data_B_i[24]), .B0(n3224), .B1(
Data_B_i[23]), .C0(n299), .C1(n167), .Y(n3120) );
INVX2TS U4957 ( .A(n3160), .Y(n3147) );
NAND2X1TS U4958 ( .A(n3125), .B(n3147), .Y(n3127) );
INVX2TS U4959 ( .A(n3159), .Y(n3149) );
OAI21XLTS U4960 ( .A0(n3123), .A1(n3139), .B0(n3140), .Y(n3124) );
AOI21X1TS U4961 ( .A0(n3149), .A1(n3125), .B0(n3124), .Y(n3126) );
NAND2X1TS U4962 ( .A(n3130), .B(n3129), .Y(n3131) );
AOI222XLTS U4963 ( .A0(n3233), .A1(n171), .B0(n3224), .B1(n168), .C0(n298),
.C1(n163), .Y(n3133) );
OAI21XLTS U4964 ( .A0(n340), .A1(n3166), .B0(n3133), .Y(n3134) );
NAND2X1TS U4965 ( .A(n3147), .B(n3136), .Y(n3138) );
AOI21X1TS U4966 ( .A0(n3149), .A1(n3136), .B0(n3135), .Y(n3137) );
NAND2X1TS U4967 ( .A(n3141), .B(n3140), .Y(n3142) );
AOI222XLTS U4968 ( .A0(n3233), .A1(n167), .B0(n3224), .B1(n164), .C0(n299),
.C1(n160), .Y(n3144) );
OAI21XLTS U4969 ( .A0(n325), .A1(n3166), .B0(n3144), .Y(n3145) );
NAND2X1TS U4970 ( .A(n3147), .B(n3162), .Y(n3151) );
AOI21X1TS U4971 ( .A0(n3149), .A1(n3162), .B0(n3148), .Y(n3150) );
NAND2X1TS U4972 ( .A(n3154), .B(n3153), .Y(n3155) );
AOI222XLTS U4973 ( .A0(n3233), .A1(n163), .B0(n3266), .B1(n160), .C0(n298),
.C1(n156), .Y(n3157) );
OAI21XLTS U4974 ( .A0(n336), .A1(n3166), .B0(n3157), .Y(n3158) );
NAND2X1TS U4975 ( .A(n3162), .B(n3161), .Y(n3163) );
AOI222XLTS U4976 ( .A0(n3233), .A1(n159), .B0(n3224), .B1(n154), .C0(n3253),
.C1(n252), .Y(n3165) );
NAND2X1TS U4977 ( .A(n3179), .B(n3184), .Y(n3171) );
AOI21X1TS U4978 ( .A0(n3180), .A1(n3184), .B0(n3169), .Y(n3170) );
NAND2X1TS U4979 ( .A(n3174), .B(n3173), .Y(n3175) );
AOI222XLTS U4980 ( .A0(n3267), .A1(n156), .B0(n3224), .B1(n251), .C0(n3253),
.C1(n151), .Y(n3177) );
NAND2X1TS U4981 ( .A(n3184), .B(n3183), .Y(n3185) );
AOI222XLTS U4982 ( .A0(n3233), .A1(n252), .B0(n3266), .B1(n152), .C0(n299),
.C1(Data_B_i[16]), .Y(n3187) );
NAND2X1TS U4983 ( .A(n3191), .B(n3190), .Y(n3192) );
AOI222XLTS U4984 ( .A0(n3267), .A1(n151), .B0(n3266), .B1(Data_B_i[16]),
.C0(n298), .C1(n144), .Y(n3194) );
NAND2X1TS U4985 ( .A(n3198), .B(n3197), .Y(n3199) );
AOI222XLTS U4986 ( .A0(n3267), .A1(n148), .B0(n3266), .B1(n143), .C0(n299),
.C1(Data_B_i[14]), .Y(n3200) );
XOR2X1TS U4987 ( .A(n3201), .B(n36), .Y(genblk1_right_mult_x_1_n1236) );
NAND2X1TS U4988 ( .A(n3214), .B(n3203), .Y(n3205) );
AOI21X1TS U4989 ( .A0(n3216), .A1(n3203), .B0(n3202), .Y(n3204) );
NAND2X1TS U4990 ( .A(n3208), .B(n3207), .Y(n3209) );
AOI222XLTS U4991 ( .A0(n3267), .A1(n140), .B0(n3266), .B1(Data_B_i[13]),
.C0(n3253), .C1(n131), .Y(n3211) );
NAND2X1TS U4992 ( .A(n3214), .B(n3230), .Y(n3218) );
AOI21X1TS U4993 ( .A0(n3216), .A1(n3230), .B0(n3215), .Y(n3217) );
NAND2X1TS U4994 ( .A(n3221), .B(n3220), .Y(n3222) );
AOI222XLTS U4995 ( .A0(n3267), .A1(n136), .B0(n3224), .B1(n132), .C0(n3253),
.C1(n206), .Y(n3225) );
XOR2X1TS U4996 ( .A(n3226), .B(n289), .Y(genblk1_right_mult_x_1_n1239) );
NAND2X1TS U4997 ( .A(n3230), .B(n3229), .Y(n3231) );
AOI222XLTS U4998 ( .A0(n3233), .A1(n131), .B0(n3256), .B1(n206), .C0(n3253),
.C1(n211), .Y(n3234) );
NAND2X1TS U4999 ( .A(n3236), .B(n3239), .Y(n3242) );
AOI21X1TS U5000 ( .A0(n3240), .A1(n3239), .B0(n3238), .Y(n3241) );
NAND2X1TS U5001 ( .A(n3246), .B(n3245), .Y(n3247) );
AOI222XLTS U5002 ( .A0(n3259), .A1(n206), .B0(n3256), .B1(n210), .C0(n3253),
.C1(Data_B_i[9]), .Y(n3249) );
AOI222XLTS U5003 ( .A0(n3259), .A1(n218), .B0(n3256), .B1(n221), .C0(n3253),
.C1(Data_B_i[6]), .Y(n3251) );
XOR2X1TS U5004 ( .A(n3252), .B(n287), .Y(genblk1_right_mult_x_1_n1244) );
AOI222XLTS U5005 ( .A0(n3259), .A1(n222), .B0(n3256), .B1(n225), .C0(n3253),
.C1(n230), .Y(n3254) );
AOI222XLTS U5006 ( .A0(n3259), .A1(n227), .B0(n3256), .B1(Data_B_i[5]), .C0(
n299), .C1(Data_B_i[4]), .Y(n3257) );
XOR2X1TS U5007 ( .A(n3258), .B(n287), .Y(genblk1_right_mult_x_1_n1246) );
AOI222XLTS U5008 ( .A0(n3259), .A1(n230), .B0(n3266), .B1(n234), .C0(n298),
.C1(n239), .Y(n3260) );
AOI222XLTS U5009 ( .A0(n3267), .A1(n235), .B0(n3266), .B1(Data_B_i[3]), .C0(
n298), .C1(Data_B_i[2]), .Y(n3262) );
AOI222XLTS U5010 ( .A0(n3267), .A1(n238), .B0(n3266), .B1(n242), .C0(n298),
.C1(Data_B_i[1]), .Y(n3268) );
NAND2X1TS U5011 ( .A(n3289), .B(n43), .Y(n3272) );
AOI21X1TS U5012 ( .A0(n3289), .A1(n176), .B0(n3274), .Y(n3275) );
AOI222XLTS U5013 ( .A0(n3308), .A1(Data_B_i[26]), .B0(n3307), .B1(n175),
.C0(n3289), .C1(n128), .Y(n3277) );
AOI222XLTS U5014 ( .A0(n3311), .A1(Data_B_i[25]), .B0(n3307), .B1(n127),
.C0(n3289), .C1(Data_B_i[23]), .Y(n3279) );
AOI222XLTS U5015 ( .A0(n3311), .A1(n128), .B0(n3307), .B1(Data_B_i[23]),
.C0(n3289), .C1(n168), .Y(n3281) );
AOI222XLTS U5016 ( .A0(n3311), .A1(n171), .B0(n3307), .B1(Data_B_i[22]),
.C0(n3289), .C1(Data_B_i[21]), .Y(n3283) );
AOI222XLTS U5017 ( .A0(n3311), .A1(n168), .B0(n3307), .B1(Data_B_i[21]),
.C0(n3325), .C1(n158), .Y(n3285) );
CLKBUFX2TS U5018 ( .A(n3289), .Y(n3322) );
AOI222XLTS U5019 ( .A0(n3311), .A1(n163), .B0(n3303), .B1(n159), .C0(n3322),
.C1(n155), .Y(n3287) );
AOI222XLTS U5020 ( .A0(n3311), .A1(n158), .B0(n3307), .B1(n155), .C0(n3289),
.C1(n252), .Y(n3290) );
AOI222XLTS U5021 ( .A0(n3308), .A1(n156), .B0(n3307), .B1(n250), .C0(n3322),
.C1(n152), .Y(n3293) );
XOR2X1TS U5022 ( .A(n3294), .B(n255), .Y(genblk1_right_mult_x_1_n1263) );
AOI222XLTS U5023 ( .A0(n3311), .A1(n250), .B0(n3303), .B1(n150), .C0(n3325),
.C1(Data_B_i[16]), .Y(n3295) );
AOI222XLTS U5024 ( .A0(n3308), .A1(n152), .B0(n3303), .B1(n148), .C0(n3325),
.C1(Data_B_i[15]), .Y(n3297) );
XOR2X1TS U5025 ( .A(n3298), .B(n256), .Y(genblk1_right_mult_x_1_n1265) );
AOI222XLTS U5026 ( .A0(n3308), .A1(n148), .B0(n3303), .B1(n144), .C0(n3325),
.C1(Data_B_i[14]), .Y(n3299) );
XOR2X1TS U5027 ( .A(n3300), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1266) );
AOI222XLTS U5028 ( .A0(n3308), .A1(Data_B_i[15]), .B0(n3303), .B1(n140),
.C0(n3325), .C1(n136), .Y(n3301) );
AOI222XLTS U5029 ( .A0(n3308), .A1(n139), .B0(n3303), .B1(Data_B_i[13]),
.C0(n3322), .C1(Data_B_i[12]), .Y(n3304) );
OAI21X1TS U5030 ( .A0(n3708), .A1(n3305), .B0(n3304), .Y(n3306) );
AOI222XLTS U5031 ( .A0(n3308), .A1(n136), .B0(n3307), .B1(n131), .C0(n3322),
.C1(Data_B_i[11]), .Y(n3309) );
AOI222XLTS U5032 ( .A0(n3311), .A1(n131), .B0(n3326), .B1(n207), .C0(n3322),
.C1(n211), .Y(n3312) );
AOI222XLTS U5033 ( .A0(n3327), .A1(n207), .B0(n3326), .B1(n211), .C0(n3322),
.C1(n214), .Y(n3314) );
AOI222XLTS U5034 ( .A0(n3327), .A1(n210), .B0(n3326), .B1(n215), .C0(n3322),
.C1(Data_B_i[8]), .Y(n3316) );
AOI222XLTS U5035 ( .A0(n3327), .A1(n214), .B0(n3326), .B1(n219), .C0(n3322),
.C1(Data_B_i[7]), .Y(n3318) );
XOR2X1TS U5036 ( .A(n3319), .B(Data_A_i[23]), .Y(
genblk1_right_mult_x_1_n1273) );
AOI222XLTS U5037 ( .A0(n3327), .A1(n218), .B0(n3326), .B1(n222), .C0(n3322),
.C1(n227), .Y(n3320) );
AOI222XLTS U5038 ( .A0(n3327), .A1(n223), .B0(n3326), .B1(n227), .C0(n3322),
.C1(n229), .Y(n3323) );
AOI222XLTS U5039 ( .A0(n3327), .A1(n227), .B0(n3326), .B1(n231), .C0(n3325),
.C1(Data_B_i[4]), .Y(n3328) );
AOI222XLTS U5040 ( .A0(n3789), .A1(Data_B_i[26]), .B0(n3744), .B1(n175),
.C0(n3343), .C1(n127), .Y(n3331) );
OAI21XLTS U5041 ( .A0(n362), .A1(n3345), .B0(n3331), .Y(n3332) );
AOI222XLTS U5042 ( .A0(n3742), .A1(n176), .B0(n3744), .B1(Data_B_i[24]),
.C0(n3343), .C1(n172), .Y(n3333) );
AOI222XLTS U5043 ( .A0(n3742), .A1(n128), .B0(n3744), .B1(n171), .C0(n3343),
.C1(Data_B_i[22]), .Y(n3335) );
AOI222XLTS U5044 ( .A0(n3742), .A1(Data_B_i[23]), .B0(n3744), .B1(n167),
.C0(n3369), .C1(n163), .Y(n3337) );
OAI21X1TS U5045 ( .A0(n340), .A1(n3345), .B0(n3337), .Y(n3338) );
CLKBUFX2TS U5046 ( .A(n3343), .Y(n3787) );
AOI222XLTS U5047 ( .A0(n3742), .A1(n167), .B0(n3744), .B1(n163), .C0(n3787),
.C1(n159), .Y(n3339) );
XOR2X1TS U5048 ( .A(n3340), .B(n280), .Y(genblk1_right_mult_x_1_n1290) );
CLKBUFX2TS U5049 ( .A(n3372), .Y(n3788) );
AOI222XLTS U5050 ( .A0(n3742), .A1(n164), .B0(n3788), .B1(n160), .C0(n3343),
.C1(n155), .Y(n3341) );
XOR2X1TS U5051 ( .A(n3342), .B(n280), .Y(genblk1_right_mult_x_1_n1291) );
AOI222XLTS U5052 ( .A0(n3742), .A1(n160), .B0(n3744), .B1(n156), .C0(n3343),
.C1(n250), .Y(n3344) );
AOI222XLTS U5053 ( .A0(n3789), .A1(Data_B_i[19]), .B0(n3744), .B1(n250),
.C0(n3369), .C1(Data_B_i[17]), .Y(n3347) );
XOR2X1TS U5054 ( .A(n3348), .B(n280), .Y(genblk1_right_mult_x_1_n1293) );
AOI222XLTS U5055 ( .A0(n3742), .A1(n251), .B0(n3788), .B1(Data_B_i[17]),
.C0(n3787), .C1(n147), .Y(n3349) );
AOI222XLTS U5056 ( .A0(n3789), .A1(Data_B_i[17]), .B0(n3788), .B1(
Data_B_i[16]), .C0(n3787), .C1(n144), .Y(n3351) );
AOI222XLTS U5057 ( .A0(n3789), .A1(n147), .B0(n3788), .B1(n144), .C0(n3787),
.C1(n139), .Y(n3353) );
AOI222XLTS U5058 ( .A0(n3789), .A1(n143), .B0(n3788), .B1(n140), .C0(n3787),
.C1(n135), .Y(n3355) );
AOI222XLTS U5059 ( .A0(n3789), .A1(Data_B_i[14]), .B0(n3788), .B1(
Data_B_i[13]), .C0(n3369), .C1(n132), .Y(n3357) );
AOI222XLTS U5060 ( .A0(n3789), .A1(n135), .B0(n3744), .B1(Data_B_i[12]),
.C0(n3369), .C1(n207), .Y(n3359) );
XOR2X1TS U5061 ( .A(n3360), .B(n280), .Y(genblk1_right_mult_x_1_n1299) );
AOI222XLTS U5062 ( .A0(n3742), .A1(n131), .B0(n3372), .B1(n207), .C0(n3369),
.C1(n210), .Y(n3361) );
AOI222XLTS U5063 ( .A0(n3375), .A1(Data_B_i[11]), .B0(n3372), .B1(n211),
.C0(n3369), .C1(n214), .Y(n3363) );
AOI222XLTS U5064 ( .A0(n3375), .A1(n211), .B0(n3372), .B1(n215), .C0(n3369),
.C1(n218), .Y(n3365) );
AOI222XLTS U5065 ( .A0(n3375), .A1(n213), .B0(n3372), .B1(Data_B_i[8]), .C0(
n3369), .C1(Data_B_i[7]), .Y(n3367) );
AOI222XLTS U5066 ( .A0(n3375), .A1(n222), .B0(n3372), .B1(Data_B_i[6]), .C0(
n3369), .C1(n231), .Y(n3370) );
XOR2X1TS U5067 ( .A(n3371), .B(n279), .Y(genblk1_right_mult_x_1_n1305) );
AOI222XLTS U5068 ( .A0(n3375), .A1(n227), .B0(n3372), .B1(Data_B_i[5]), .C0(
n3787), .C1(n233), .Y(n3373) );
AOI222XLTS U5069 ( .A0(n3375), .A1(Data_B_i[5]), .B0(n3788), .B1(n234), .C0(
n3787), .C1(Data_B_i[3]), .Y(n3376) );
XOR2X1TS U5070 ( .A(n3377), .B(n281), .Y(genblk1_right_mult_x_1_n1307) );
AOI222XLTS U5071 ( .A0(n3789), .A1(n234), .B0(n3788), .B1(n238), .C0(n3787),
.C1(Data_B_i[2]), .Y(n3378) );
AOI222XLTS U5072 ( .A0(n3789), .A1(n238), .B0(n3788), .B1(n243), .C0(n3787),
.C1(Data_B_i[1]), .Y(n3381) );
NAND2X1TS U5073 ( .A(n3414), .B(n43), .Y(n3384) );
AOI21X1TS U5074 ( .A0(n3414), .A1(n175), .B0(n3386), .Y(n3387) );
XOR2X1TS U5075 ( .A(n3388), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1315) );
AOI222XLTS U5076 ( .A0(n3749), .A1(n43), .B0(n3418), .B1(n176), .C0(n3430),
.C1(Data_B_i[24]), .Y(n3389) );
AOI222XLTS U5077 ( .A0(n3421), .A1(n175), .B0(n3418), .B1(Data_B_i[24]),
.C0(n3414), .C1(n172), .Y(n3391) );
AOI222XLTS U5078 ( .A0(n3421), .A1(n127), .B0(n3418), .B1(Data_B_i[23]),
.C0(n3414), .C1(Data_B_i[22]), .Y(n3393) );
XOR2X1TS U5079 ( .A(n3394), .B(n259), .Y(genblk1_right_mult_x_1_n1318) );
AOI222XLTS U5080 ( .A0(n3421), .A1(n171), .B0(n3418), .B1(Data_B_i[22]),
.C0(n3430), .C1(Data_B_i[21]), .Y(n3395) );
XOR2X1TS U5081 ( .A(n3396), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1319) );
AOI222XLTS U5082 ( .A0(n3421), .A1(n168), .B0(n3418), .B1(Data_B_i[21]),
.C0(n3803), .C1(n158), .Y(n3397) );
XOR2X1TS U5083 ( .A(n3398), .B(n260), .Y(genblk1_right_mult_x_1_n1320) );
AOI222XLTS U5084 ( .A0(n3421), .A1(Data_B_i[21]), .B0(n3804), .B1(n159),
.C0(n3414), .C1(Data_B_i[19]), .Y(n3399) );
AOI222XLTS U5085 ( .A0(n3421), .A1(n160), .B0(n3418), .B1(n155), .C0(n3414),
.C1(n252), .Y(n3401) );
AOI222XLTS U5086 ( .A0(n3749), .A1(n155), .B0(n3418), .B1(n251), .C0(n3430),
.C1(n151), .Y(n3404) );
AOI222XLTS U5087 ( .A0(n3421), .A1(n250), .B0(n3804), .B1(Data_B_i[17]),
.C0(n3803), .C1(Data_B_i[16]), .Y(n3406) );
AOI222XLTS U5088 ( .A0(n3749), .A1(n152), .B0(n3804), .B1(n148), .C0(n3803),
.C1(n143), .Y(n3408) );
AOI222XLTS U5089 ( .A0(n3749), .A1(n147), .B0(n3804), .B1(n143), .C0(n3803),
.C1(n139), .Y(n3410) );
AOI222XLTS U5090 ( .A0(n3749), .A1(n144), .B0(n3804), .B1(n140), .C0(n3803),
.C1(Data_B_i[13]), .Y(n3412) );
AOI222XLTS U5091 ( .A0(n3749), .A1(n139), .B0(n3804), .B1(n135), .C0(n3414),
.C1(n132), .Y(n3415) );
AOI222XLTS U5092 ( .A0(n3749), .A1(n136), .B0(n3418), .B1(Data_B_i[12]),
.C0(n3430), .C1(Data_B_i[11]), .Y(n3419) );
AOI222XLTS U5093 ( .A0(n3421), .A1(n132), .B0(n3433), .B1(Data_B_i[11]),
.C0(n3430), .C1(Data_B_i[10]), .Y(n3422) );
AOI222XLTS U5094 ( .A0(n3805), .A1(Data_B_i[11]), .B0(n3433), .B1(n210),
.C0(n3430), .C1(Data_B_i[9]), .Y(n3424) );
AOI222XLTS U5095 ( .A0(n3805), .A1(Data_B_i[9]), .B0(n3433), .B1(Data_B_i[8]), .C0(n3430), .C1(n223), .Y(n3426) );
AOI222XLTS U5096 ( .A0(n3805), .A1(n218), .B0(n3433), .B1(Data_B_i[7]), .C0(
n3430), .C1(Data_B_i[6]), .Y(n3428) );
XOR2X1TS U5097 ( .A(n3429), .B(n259), .Y(genblk1_right_mult_x_1_n1334) );
AOI222XLTS U5098 ( .A0(n3805), .A1(Data_B_i[7]), .B0(n3433), .B1(n226), .C0(
n3430), .C1(n230), .Y(n3431) );
XOR2X1TS U5099 ( .A(n3432), .B(Data_A_i[17]), .Y(
genblk1_right_mult_x_1_n1335) );
AOI222XLTS U5100 ( .A0(n3805), .A1(Data_B_i[6]), .B0(n3433), .B1(n231), .C0(
n3803), .C1(Data_B_i[4]), .Y(n3434) );
NOR2BX1TS U5101 ( .AN(n3437), .B(n3436), .Y(n3798) );
CLKBUFX2TS U5102 ( .A(n3798), .Y(n3726) );
AOI21X1TS U5103 ( .A0(n3456), .A1(n176), .B0(n3438), .Y(n3439) );
XOR2X1TS U5104 ( .A(n3440), .B(n263), .Y(genblk1_right_mult_x_1_n1345) );
CLKBUFX2TS U5105 ( .A(n3456), .Y(n3797) );
AOI222XLTS U5106 ( .A0(n3763), .A1(n43), .B0(n3726), .B1(n176), .C0(n3797),
.C1(n127), .Y(n3441) );
XOR2X1TS U5107 ( .A(n3442), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1346) );
AOI222XLTS U5108 ( .A0(n3725), .A1(n176), .B0(n3726), .B1(n128), .C0(n3797),
.C1(n172), .Y(n3443) );
XOR2X1TS U5109 ( .A(n3444), .B(n264), .Y(genblk1_right_mult_x_1_n1347) );
AOI222XLTS U5110 ( .A0(n3725), .A1(Data_B_i[24]), .B0(n3726), .B1(n172),
.C0(n3456), .C1(n167), .Y(n3445) );
AOI222XLTS U5111 ( .A0(n3725), .A1(Data_B_i[23]), .B0(n3726), .B1(n168),
.C0(n3456), .C1(Data_B_i[21]), .Y(n3447) );
CLKBUFX2TS U5112 ( .A(n3456), .Y(n3761) );
AOI222XLTS U5113 ( .A0(n3725), .A1(n168), .B0(n3726), .B1(Data_B_i[21]),
.C0(n3761), .C1(n159), .Y(n3449) );
XOR2X1TS U5114 ( .A(n3450), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1350) );
CLKBUFX2TS U5115 ( .A(n3798), .Y(n3762) );
AOI222XLTS U5116 ( .A0(n3725), .A1(n163), .B0(n3762), .B1(n160), .C0(n3456),
.C1(Data_B_i[19]), .Y(n3451) );
AOI222XLTS U5117 ( .A0(n3725), .A1(n158), .B0(n3726), .B1(n156), .C0(n3456),
.C1(n251), .Y(n3453) );
AOI222XLTS U5118 ( .A0(n3763), .A1(Data_B_i[19]), .B0(n3726), .B1(n250),
.C0(n3456), .C1(Data_B_i[17]), .Y(n3457) );
AOI222XLTS U5119 ( .A0(n3725), .A1(n251), .B0(n3762), .B1(Data_B_i[17]),
.C0(n3761), .C1(n147), .Y(n3459) );
AOI222XLTS U5120 ( .A0(n3763), .A1(n151), .B0(n3762), .B1(Data_B_i[16]),
.C0(n3761), .C1(Data_B_i[15]), .Y(n3461) );
AOI222XLTS U5121 ( .A0(n3763), .A1(n148), .B0(n3762), .B1(Data_B_i[15]),
.C0(n3761), .C1(Data_B_i[14]), .Y(n3463) );
AOI222XLTS U5122 ( .A0(n3763), .A1(Data_B_i[15]), .B0(n3762), .B1(n139),
.C0(n3761), .C1(n135), .Y(n3465) );
AOI222XLTS U5123 ( .A0(n3763), .A1(n140), .B0(n3762), .B1(n136), .C0(n3797),
.C1(n132), .Y(n3467) );
AOI222XLTS U5124 ( .A0(n3763), .A1(n135), .B0(n3726), .B1(Data_B_i[12]),
.C0(n3797), .C1(Data_B_i[11]), .Y(n3470) );
XOR2X1TS U5125 ( .A(n3471), .B(Data_A_i[14]), .Y(
genblk1_right_mult_x_1_n1359) );
AOI222XLTS U5126 ( .A0(n3725), .A1(Data_B_i[12]), .B0(n3798), .B1(n207),
.C0(n3797), .C1(Data_B_i[10]), .Y(n3472) );
AOI222XLTS U5127 ( .A0(n3799), .A1(n207), .B0(n3798), .B1(Data_B_i[10]),
.C0(n3797), .C1(n214), .Y(n3474) );
XOR2X1TS U5128 ( .A(n3475), .B(n264), .Y(genblk1_right_mult_x_1_n1361) );
AOI222XLTS U5129 ( .A0(n3799), .A1(Data_B_i[10]), .B0(n3798), .B1(n215),
.C0(n3797), .C1(Data_B_i[8]), .Y(n3476) );
AOI222XLTS U5130 ( .A0(n3799), .A1(n214), .B0(n3798), .B1(Data_B_i[8]), .C0(
n3797), .C1(n223), .Y(n3478) );
AOI222XLTS U5131 ( .A0(n3799), .A1(n222), .B0(n3798), .B1(n226), .C0(n3797),
.C1(Data_B_i[5]), .Y(n3480) );
AOI222XLTS U5132 ( .A0(n3799), .A1(n226), .B0(n3798), .B1(n231), .C0(n3761),
.C1(n235), .Y(n3482) );
AOI222XLTS U5133 ( .A0(n3799), .A1(n231), .B0(n3762), .B1(Data_B_i[4]), .C0(
n3761), .C1(Data_B_i[3]), .Y(n3484) );
AOI222XLTS U5134 ( .A0(n3763), .A1(n235), .B0(n3762), .B1(n238), .C0(n3761),
.C1(n241), .Y(n3486) );
AOI222XLTS U5135 ( .A0(n3763), .A1(Data_B_i[3]), .B0(n3762), .B1(n242), .C0(
n3761), .C1(n247), .Y(n3488) );
NAND2X1TS U5136 ( .A(n3510), .B(n43), .Y(n3490) );
AOI21X1TS U5137 ( .A0(n3510), .A1(n176), .B0(n3492), .Y(n3493) );
XOR2X1TS U5138 ( .A(n3494), .B(n268), .Y(genblk1_right_mult_x_1_n1375) );
CLKBUFX2TS U5139 ( .A(n3510), .Y(n3539) );
AOI222XLTS U5140 ( .A0(n3730), .A1(n1431), .B0(n3525), .B1(Data_B_i[25]),
.C0(n3539), .C1(n127), .Y(n3495) );
OAI21X1TS U5141 ( .A0(n362), .A1(n3508), .B0(n3495), .Y(n3496) );
XOR2X1TS U5142 ( .A(n3496), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1376) );
AOI222XLTS U5143 ( .A0(n3528), .A1(Data_B_i[25]), .B0(n3525), .B1(n127),
.C0(n3539), .C1(n172), .Y(n3497) );
AOI222XLTS U5144 ( .A0(n3528), .A1(n128), .B0(n3525), .B1(n172), .C0(n3510),
.C1(n168), .Y(n3499) );
XOR2X1TS U5145 ( .A(n3500), .B(n267), .Y(genblk1_right_mult_x_1_n1378) );
AOI222XLTS U5146 ( .A0(n3528), .A1(Data_B_i[23]), .B0(n3525), .B1(
Data_B_i[22]), .C0(n3510), .C1(Data_B_i[21]), .Y(n3501) );
AOI222XLTS U5147 ( .A0(n3528), .A1(n168), .B0(n3525), .B1(n164), .C0(n3777),
.C1(n158), .Y(n3503) );
AOI222XLTS U5148 ( .A0(n3528), .A1(n163), .B0(n3778), .B1(n159), .C0(n3510),
.C1(n155), .Y(n3505) );
AOI222XLTS U5149 ( .A0(n3528), .A1(n158), .B0(n3525), .B1(Data_B_i[19]),
.C0(n3510), .C1(n250), .Y(n3507) );
AOI222XLTS U5150 ( .A0(n3730), .A1(n155), .B0(n3525), .B1(n252), .C0(n3510),
.C1(n152), .Y(n3511) );
AOI222XLTS U5151 ( .A0(n3528), .A1(n251), .B0(n3778), .B1(Data_B_i[17]),
.C0(n3777), .C1(n146), .Y(n3513) );
AOI222XLTS U5152 ( .A0(n3730), .A1(n151), .B0(n3778), .B1(n148), .C0(n3777),
.C1(n144), .Y(n3515) );
AOI222XLTS U5153 ( .A0(n3730), .A1(Data_B_i[16]), .B0(n3778), .B1(n144),
.C0(n3777), .C1(n139), .Y(n3517) );
AOI222XLTS U5154 ( .A0(n3730), .A1(n143), .B0(n3778), .B1(n139), .C0(n3777),
.C1(n135), .Y(n3519) );
AOI222XLTS U5155 ( .A0(n3730), .A1(n140), .B0(n3778), .B1(n136), .C0(n3539),
.C1(n132), .Y(n3521) );
AOI222XLTS U5156 ( .A0(n3730), .A1(n135), .B0(n3525), .B1(n131), .C0(n3539),
.C1(n206), .Y(n3526) );
AOI222XLTS U5157 ( .A0(n3528), .A1(n131), .B0(n3542), .B1(n206), .C0(n3539),
.C1(n210), .Y(n3529) );
XOR2X1TS U5158 ( .A(n3530), .B(Data_A_i[11]), .Y(
genblk1_right_mult_x_1_n1390) );
AOI222XLTS U5159 ( .A0(n3779), .A1(n206), .B0(n3542), .B1(Data_B_i[10]),
.C0(n3539), .C1(n215), .Y(n3531) );
AOI222XLTS U5160 ( .A0(n3779), .A1(n210), .B0(n3542), .B1(Data_B_i[9]), .C0(
n3539), .C1(n218), .Y(n3533) );
AOI222XLTS U5161 ( .A0(n3779), .A1(n215), .B0(n3542), .B1(n218), .C0(n3539),
.C1(Data_B_i[7]), .Y(n3535) );
AOI222XLTS U5162 ( .A0(n3779), .A1(Data_B_i[8]), .B0(n3542), .B1(n223), .C0(
n3539), .C1(Data_B_i[6]), .Y(n3537) );
AOI222XLTS U5163 ( .A0(n3779), .A1(Data_B_i[7]), .B0(n3542), .B1(Data_B_i[6]), .C0(n3539), .C1(n230), .Y(n3540) );
AOI222XLTS U5164 ( .A0(n3779), .A1(Data_B_i[6]), .B0(n3542), .B1(n230), .C0(
n3777), .C1(n234), .Y(n3543) );
NAND2X1TS U5165 ( .A(n3565), .B(n1431), .Y(n3545) );
OAI21X1TS U5166 ( .A0(n3665), .A1(n3563), .B0(n3545), .Y(n3546) );
XOR2X1TS U5167 ( .A(n3546), .B(n271), .Y(genblk1_right_mult_x_1_n1404) );
AOI21X1TS U5168 ( .A0(n3565), .A1(Data_B_i[25]), .B0(n3547), .Y(n3548) );
CLKBUFX2TS U5169 ( .A(n3565), .Y(n3771) );
AOI222XLTS U5170 ( .A0(n3754), .A1(n1431), .B0(n3753), .B1(n174), .C0(n3771),
.C1(n126), .Y(n3550) );
AOI222XLTS U5171 ( .A0(n3579), .A1(Data_B_i[25]), .B0(n3753), .B1(n128),
.C0(n3565), .C1(Data_B_i[23]), .Y(n3552) );
AOI222XLTS U5172 ( .A0(n3579), .A1(n127), .B0(n3753), .B1(n172), .C0(n3565),
.C1(n167), .Y(n3554) );
AOI222XLTS U5173 ( .A0(n3579), .A1(n172), .B0(n3753), .B1(n168), .C0(n3565),
.C1(Data_B_i[21]), .Y(n3556) );
AOI222XLTS U5174 ( .A0(n3579), .A1(Data_B_i[22]), .B0(n3753), .B1(n164),
.C0(n3596), .C1(n159), .Y(n3558) );
AOI222XLTS U5175 ( .A0(n3579), .A1(n164), .B0(n3597), .B1(n160), .C0(n3771),
.C1(n156), .Y(n3560) );
XOR2X1TS U5176 ( .A(n3561), .B(n272), .Y(genblk1_right_mult_x_1_n1411) );
AOI222XLTS U5177 ( .A0(n3579), .A1(n158), .B0(n3753), .B1(n156), .C0(n3565),
.C1(n252), .Y(n3562) );
AOI222XLTS U5178 ( .A0(n3754), .A1(n155), .B0(n3753), .B1(n252), .C0(n3565),
.C1(n151), .Y(n3566) );
AOI222XLTS U5179 ( .A0(n3579), .A1(n250), .B0(n3597), .B1(n152), .C0(n3596),
.C1(n147), .Y(n3568) );
AOI222XLTS U5180 ( .A0(n3754), .A1(Data_B_i[17]), .B0(n3597), .B1(
Data_B_i[16]), .C0(n3596), .C1(Data_B_i[15]), .Y(n3570) );
AOI222XLTS U5181 ( .A0(n3754), .A1(n147), .B0(n3597), .B1(n143), .C0(n3596),
.C1(Data_B_i[14]), .Y(n3572) );
XOR2X1TS U5182 ( .A(n3573), .B(n272), .Y(genblk1_right_mult_x_1_n1416) );
AOI222XLTS U5183 ( .A0(n3754), .A1(n144), .B0(n3597), .B1(Data_B_i[14]),
.C0(n3596), .C1(Data_B_i[13]), .Y(n3574) );
XOR2X1TS U5184 ( .A(n3575), .B(n270), .Y(genblk1_right_mult_x_1_n1417) );
AOI222XLTS U5185 ( .A0(n3754), .A1(Data_B_i[14]), .B0(n3597), .B1(
Data_B_i[13]), .C0(n3771), .C1(n131), .Y(n3576) );
AOI222XLTS U5186 ( .A0(n3579), .A1(Data_B_i[12]), .B0(n3772), .B1(
Data_B_i[11]), .C0(n3771), .C1(Data_B_i[10]), .Y(n3580) );
AOI222XLTS U5187 ( .A0(n3773), .A1(n205), .B0(n3772), .B1(n209), .C0(n3771),
.C1(n214), .Y(n3582) );
AOI222XLTS U5188 ( .A0(n3773), .A1(n211), .B0(n3772), .B1(n215), .C0(n3771),
.C1(Data_B_i[8]), .Y(n3584) );
AOI222XLTS U5189 ( .A0(n3773), .A1(n215), .B0(n3772), .B1(n219), .C0(n3771),
.C1(Data_B_i[7]), .Y(n3586) );
AOI222XLTS U5190 ( .A0(n3773), .A1(n223), .B0(n3772), .B1(n227), .C0(n3771),
.C1(Data_B_i[5]), .Y(n3588) );
AOI222XLTS U5191 ( .A0(n3773), .A1(n227), .B0(n3772), .B1(Data_B_i[5]), .C0(
n3596), .C1(Data_B_i[4]), .Y(n3590) );
AOI222XLTS U5192 ( .A0(n3773), .A1(n231), .B0(n3597), .B1(n234), .C0(n3596),
.C1(Data_B_i[3]), .Y(n3592) );
AOI222XLTS U5193 ( .A0(n3754), .A1(Data_B_i[4]), .B0(n3597), .B1(n239), .C0(
n3596), .C1(n242), .Y(n3594) );
AOI222XLTS U5194 ( .A0(n3754), .A1(n239), .B0(n3597), .B1(n243), .C0(n3596),
.C1(n247), .Y(n3598) );
NAND2X1TS U5195 ( .A(n3633), .B(Data_B_i[26]), .Y(n3603) );
AOI21X1TS U5196 ( .A0(n3633), .A1(Data_B_i[25]), .B0(n3605), .Y(n3606) );
AOI222XLTS U5197 ( .A0(n3639), .A1(n1431), .B0(n3638), .B1(n175), .C0(n3633),
.C1(n128), .Y(n3608) );
CLKBUFX2TS U5198 ( .A(n3633), .Y(n3653) );
AOI222XLTS U5199 ( .A0(n3642), .A1(n175), .B0(n3638), .B1(Data_B_i[24]),
.C0(n3653), .C1(Data_B_i[23]), .Y(n3610) );
OAI21X1TS U5200 ( .A0(n3673), .A1(n3621), .B0(n3610), .Y(n3611) );
AOI222XLTS U5201 ( .A0(n3642), .A1(Data_B_i[24]), .B0(n3638), .B1(n171),
.C0(n3653), .C1(Data_B_i[22]), .Y(n3612) );
OAI21X1TS U5202 ( .A0(n3676), .A1(n3621), .B0(n3612), .Y(n3613) );
XOR2X1TS U5203 ( .A(n3613), .B(n276), .Y(genblk1_right_mult_x_1_n1438) );
AOI222XLTS U5204 ( .A0(n3642), .A1(n171), .B0(n3638), .B1(Data_B_i[22]),
.C0(n3633), .C1(n163), .Y(n3614) );
AOI222XLTS U5205 ( .A0(n3642), .A1(n167), .B0(n3638), .B1(n163), .C0(n3657),
.C1(n158), .Y(n3616) );
XOR2X1TS U5206 ( .A(n3617), .B(n276), .Y(genblk1_right_mult_x_1_n1440) );
AOI222XLTS U5207 ( .A0(n3642), .A1(n164), .B0(n3634), .B1(n159), .C0(n3633),
.C1(Data_B_i[19]), .Y(n3618) );
OAI21XLTS U5208 ( .A0(n336), .A1(n3621), .B0(n3618), .Y(n3619) );
AOI222XLTS U5209 ( .A0(n3642), .A1(n159), .B0(n3638), .B1(Data_B_i[19]),
.C0(n3653), .C1(n252), .Y(n3620) );
OAI21X1TS U5210 ( .A0(n3686), .A1(n3621), .B0(n3620), .Y(n3622) );
AOI222XLTS U5211 ( .A0(n3639), .A1(n156), .B0(n3638), .B1(n252), .C0(n3633),
.C1(n152), .Y(n3623) );
AOI222XLTS U5212 ( .A0(n3642), .A1(n251), .B0(n3634), .B1(n151), .C0(n3657),
.C1(n148), .Y(n3625) );
XOR2X1TS U5213 ( .A(n3626), .B(Data_A_i[5]), .Y(genblk1_right_mult_x_1_n1444) );
AOI222XLTS U5214 ( .A0(n3639), .A1(n151), .B0(n3634), .B1(Data_B_i[16]),
.C0(n3657), .C1(n143), .Y(n3627) );
AOI222XLTS U5215 ( .A0(n3639), .A1(n148), .B0(n3634), .B1(n142), .C0(n3657),
.C1(Data_B_i[14]), .Y(n3629) );
AOI222XLTS U5216 ( .A0(n3639), .A1(n144), .B0(n3634), .B1(n140), .C0(n3657),
.C1(Data_B_i[13]), .Y(n3631) );
AOI222XLTS U5217 ( .A0(n3639), .A1(n140), .B0(n3634), .B1(Data_B_i[13]),
.C0(n3633), .C1(n130), .Y(n3635) );
AOI222XLTS U5218 ( .A0(n3639), .A1(Data_B_i[13]), .B0(n3638), .B1(
Data_B_i[12]), .C0(n3653), .C1(Data_B_i[11]), .Y(n3640) );
AOI222XLTS U5219 ( .A0(n3642), .A1(Data_B_i[12]), .B0(n3658), .B1(n207),
.C0(n3653), .C1(Data_B_i[10]), .Y(n3643) );
AOI222XLTS U5220 ( .A0(n3659), .A1(n206), .B0(n3658), .B1(n211), .C0(n3653),
.C1(Data_B_i[9]), .Y(n3645) );
AOI222XLTS U5221 ( .A0(n3659), .A1(Data_B_i[10]), .B0(n3658), .B1(
Data_B_i[9]), .C0(n3653), .C1(n219), .Y(n3647) );
AOI222XLTS U5222 ( .A0(n3659), .A1(n214), .B0(n3658), .B1(n218), .C0(n3653),
.C1(n223), .Y(n3649) );
AOI222XLTS U5223 ( .A0(n3659), .A1(n218), .B0(n3658), .B1(Data_B_i[7]), .C0(
n3653), .C1(Data_B_i[6]), .Y(n3651) );
AOI222XLTS U5224 ( .A0(n3659), .A1(n223), .B0(n3658), .B1(n226), .C0(n3653),
.C1(Data_B_i[5]), .Y(n3654) );
AOI222XLTS U5225 ( .A0(n3659), .A1(Data_B_i[6]), .B0(n3658), .B1(n230), .C0(
n3657), .C1(n235), .Y(n3660) );
NAND2X1TS U5226 ( .A(n3703), .B(n42), .Y(n3664) );
XOR2X1TS U5227 ( .A(n3666), .B(n284), .Y(genblk1_right_mult_x_1_n1464) );
AOI21X1TS U5228 ( .A0(n3703), .A1(n175), .B0(n3667), .Y(n3668) );
AOI222XLTS U5229 ( .A0(n3705), .A1(n42), .B0(n3734), .B1(n175), .C0(n3703),
.C1(n127), .Y(n3670) );
AOI222XLTS U5230 ( .A0(n307), .A1(Data_B_i[25]), .B0(n3734), .B1(n126), .C0(
n3733), .C1(n170), .Y(n3672) );
XOR2X1TS U5231 ( .A(n3674), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1467) );
AOI222XLTS U5232 ( .A0(n307), .A1(n128), .B0(n3734), .B1(n171), .C0(n3733),
.C1(n166), .Y(n3675) );
XOR2X1TS U5233 ( .A(n3677), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1468) );
AOI222XLTS U5234 ( .A0(n306), .A1(n171), .B0(n3734), .B1(n167), .C0(n3703),
.C1(n164), .Y(n3678) );
XOR2X1TS U5235 ( .A(n3679), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1469) );
AOI222XLTS U5236 ( .A0(n307), .A1(n167), .B0(n3734), .B1(n164), .C0(n3699),
.C1(n159), .Y(n3680) );
XOR2X1TS U5237 ( .A(n3681), .B(Data_A_i[2]), .Y(genblk1_right_mult_x_1_n1470) );
AOI222XLTS U5238 ( .A0(n307), .A1(n164), .B0(n3717), .B1(n160), .C0(n3703),
.C1(Data_B_i[19]), .Y(n3682) );
AOI222XLTS U5239 ( .A0(n306), .A1(n160), .B0(n3734), .B1(Data_B_i[19]), .C0(
n3703), .C1(n252), .Y(n3684) );
AOI222XLTS U5240 ( .A0(n3705), .A1(n156), .B0(n3734), .B1(n251), .C0(n3703),
.C1(n152), .Y(n3688) );
AOI222XLTS U5241 ( .A0(n307), .A1(n250), .B0(n3704), .B1(Data_B_i[17]), .C0(
n3699), .C1(n147), .Y(n3691) );
AOI222XLTS U5242 ( .A0(n3705), .A1(n151), .B0(n3704), .B1(n147), .C0(n3699),
.C1(n143), .Y(n3694) );
AOI222XLTS U5243 ( .A0(n3705), .A1(n147), .B0(n3704), .B1(Data_B_i[15]),
.C0(n3699), .C1(Data_B_i[14]), .Y(n3697) );
AOI222XLTS U5244 ( .A0(n3705), .A1(Data_B_i[15]), .B0(n3704), .B1(n139),
.C0(n3699), .C1(n135), .Y(n3700) );
AOI222XLTS U5245 ( .A0(n3705), .A1(n139), .B0(n3704), .B1(n136), .C0(n3703),
.C1(n132), .Y(n3706) );
AOI222XLTS U5246 ( .A0(n306), .A1(n132), .B0(n3717), .B1(n206), .C0(n3733),
.C1(n210), .Y(n3710) );
AOI222XLTS U5247 ( .A0(n306), .A1(n207), .B0(n3717), .B1(n211), .C0(n3733),
.C1(n214), .Y(n3712) );
AOI222XLTS U5248 ( .A0(n307), .A1(Data_B_i[10]), .B0(n3717), .B1(n215), .C0(
n3733), .C1(Data_B_i[8]), .Y(n3714) );
AOI222XLTS U5249 ( .A0(n306), .A1(Data_B_i[9]), .B0(n3717), .B1(n219), .C0(
n3733), .C1(Data_B_i[7]), .Y(n3718) );
ADDHXLTS U5250 ( .A(n259), .B(n3721), .CO(n3064), .S(
genblk1_right_mult_x_1_n854) );
ADDHXLTS U5251 ( .A(n268), .B(n3722), .CO(n3086), .S(
genblk1_right_mult_x_1_n890) );
CLKAND2X2TS U5252 ( .A(n289), .B(n245), .Y(genblk1_right_mult_x_1_n934) );
ADDHXLTS U5253 ( .A(n255), .B(n3724), .CO(n3045), .S(
genblk1_right_mult_x_1_n800) );
AOI22X1TS U5254 ( .A0(n3726), .A1(n3743), .B0(n3725), .B1(n247), .Y(n3727)
);
ADDHXLTS U5255 ( .A(n264), .B(n3729), .CO(n3767), .S(n3083) );
AOI222XLTS U5256 ( .A0(n3730), .A1(n234), .B0(n3778), .B1(n238), .C0(n3777),
.C1(n243), .Y(n3731) );
AOI222XLTS U5257 ( .A0(n307), .A1(n136), .B0(n3734), .B1(Data_B_i[12]), .C0(
n3733), .C1(n207), .Y(n3736) );
CMPR32X2TS U5258 ( .A(n3741), .B(n3740), .C(n3739), .CO(
genblk1_right_mult_x_1_n865), .S(genblk1_right_mult_x_1_n866) );
AOI22X1TS U5259 ( .A0(n3744), .A1(n3743), .B0(n3742), .B1(n246), .Y(n3745)
);
ADDHXLTS U5260 ( .A(n281), .B(n3748), .CO(n3793), .S(n3061) );
AOI222XLTS U5261 ( .A0(n3749), .A1(n234), .B0(n3804), .B1(Data_B_i[3]), .C0(
n3803), .C1(Data_B_i[2]), .Y(n3750) );
AOI222XLTS U5262 ( .A0(n3754), .A1(n135), .B0(n3753), .B1(n131), .C0(n3771),
.C1(Data_B_i[11]), .Y(n3755) );
CMPR32X2TS U5263 ( .A(n3760), .B(n3759), .C(n3758), .CO(
genblk1_right_mult_x_1_n817), .S(genblk1_right_mult_x_1_n818) );
AOI222XLTS U5264 ( .A0(n3763), .A1(Data_B_i[2]), .B0(n3762), .B1(n246), .C0(
n3761), .C1(n3786), .Y(n3764) );
ADDHXLTS U5265 ( .A(n3768), .B(n3767), .CO(n3769), .S(n3741) );
AOI222XLTS U5266 ( .A0(n3773), .A1(Data_B_i[8]), .B0(n3772), .B1(n223), .C0(
n3771), .C1(n227), .Y(n3774) );
AOI222XLTS U5267 ( .A0(n3779), .A1(Data_B_i[5]), .B0(n3778), .B1(Data_B_i[4]), .C0(n3777), .C1(n238), .Y(n3780) );
CMPR32X2TS U5268 ( .A(n3785), .B(n3784), .C(n3783), .CO(
genblk1_right_mult_x_1_n858), .S(genblk1_right_mult_x_1_n859) );
AOI222XLTS U5269 ( .A0(n3789), .A1(Data_B_i[2]), .B0(n3788), .B1(Data_B_i[1]), .C0(n3787), .C1(n3786), .Y(n3790) );
ADDHXLTS U5270 ( .A(n3794), .B(n3793), .CO(n3795), .S(n3760) );
ADDHXLTS U5271 ( .A(n3796), .B(n3795), .CO(genblk1_right_mult_x_1_n809), .S(
n3811) );
AOI222XLTS U5272 ( .A0(n3799), .A1(n218), .B0(n3798), .B1(n222), .C0(n3797),
.C1(n226), .Y(n3800) );
AOI222XLTS U5273 ( .A0(n3805), .A1(n231), .B0(n3804), .B1(Data_B_i[4]), .C0(
n3803), .C1(Data_B_i[3]), .Y(n3806) );
CMPR32X2TS U5274 ( .A(n3811), .B(n3810), .C(n3809), .CO(
genblk1_right_mult_x_1_n807), .S(genblk1_right_mult_x_1_n808) );
NAND2X1TS U5275 ( .A(n3814), .B(n3813), .Y(n3815) );
INVX2TS U5276 ( .A(n3817), .Y(n3826) );
AOI21X1TS U5277 ( .A0(n3819), .A1(n3826), .B0(n3818), .Y(n3824) );
NAND2X1TS U5278 ( .A(n3822), .B(n3821), .Y(n3823) );
NAND2X1TS U5279 ( .A(n3826), .B(n3825), .Y(n3827) );
AOI21X1TS U5280 ( .A0(n3831), .A1(n3830), .B0(n3829), .Y(n3834) );
NAND2X1TS U5281 ( .A(n364), .B(n3832), .Y(n3833) );
AOI21X1TS U5282 ( .A0(n3836), .A1(n363), .B0(n3835), .Y(n3840) );
NAND2X1TS U5283 ( .A(n3838), .B(n3837), .Y(n3839) );
AOI21X1TS U5284 ( .A0(n3842), .A1(n3848), .B0(n3841), .Y(n3846) );
NAND2X1TS U5285 ( .A(n3844), .B(n3843), .Y(n3845) );
NAND2X1TS U5286 ( .A(n3848), .B(n3847), .Y(n3849) );
NAND2X1TS U5287 ( .A(n363), .B(n3851), .Y(n3852) );
NAND2X1TS U5288 ( .A(n3856), .B(n3855), .Y(n3857) );
NAND2X1TS U5289 ( .A(n3861), .B(n3860), .Y(n3862) );
AOI21X1TS U5290 ( .A0(n3867), .A1(n3866), .B0(n3865), .Y(n3872) );
NAND2X1TS U5291 ( .A(n3870), .B(n3869), .Y(n3871) );
AOI21X1TS U5292 ( .A0(n3874), .A1(n360), .B0(n3873), .Y(n3878) );
NAND2X1TS U5293 ( .A(n3876), .B(n3875), .Y(n3877) );
NAND2X1TS U5294 ( .A(n3881), .B(n3880), .Y(n3882) );
NAND2X1TS U5295 ( .A(n3885), .B(n3884), .Y(n3886) );
INVX2TS U5296 ( .A(n3888), .Y(n3889) );
AOI21X1TS U5297 ( .A0(n3891), .A1(n3890), .B0(n3889), .Y(n3896) );
NAND2X1TS U5298 ( .A(n3894), .B(n3893), .Y(n3895) );
INVX2TS U5299 ( .A(genblk1_right_mult_x_1_n926), .Y(
genblk1_right_mult_x_1_n621) );
NAND2X1TS U5300 ( .A(n3899), .B(n3898), .Y(n3900) );
INVX2TS U5301 ( .A(genblk1_right_mult_x_1_n920), .Y(
genblk1_right_mult_x_1_n566) );
NAND2X1TS U5302 ( .A(n3904), .B(n3903), .Y(n3905) );
AOI21X1TS U5303 ( .A0(n3909), .A1(n3908), .B0(n3907), .Y(n3913) );
NAND2X1TS U5304 ( .A(n3911), .B(n3910), .Y(n3912) );
INVX2TS U5305 ( .A(n3914), .Y(n3916) );
NAND2X1TS U5306 ( .A(n3916), .B(n3915), .Y(n3917) );
AOI21X1TS U5307 ( .A0(n3921), .A1(n3920), .B0(n3919), .Y(n3925) );
NAND2X1TS U5308 ( .A(n3923), .B(n3922), .Y(n3924) );
AOI21X1TS U5309 ( .A0(n3928), .A1(n3927), .B0(n3926), .Y(n3932) );
NAND2X1TS U5310 ( .A(n3930), .B(n3929), .Y(n3931) );
INVX2TS U5311 ( .A(n3933), .Y(n3935) );
NAND2X1TS U5312 ( .A(n3935), .B(n3934), .Y(n3937) );
INVX2TS U5313 ( .A(genblk1_right_mult_x_1_n914), .Y(
genblk1_right_mult_x_1_n529) );
INVX2TS U5314 ( .A(n3938), .Y(n3940) );
NAND2X1TS U5315 ( .A(n3940), .B(n3939), .Y(n3942) );
NAND2X1TS U5316 ( .A(n3944), .B(n3943), .Y(n3945) );
AOI21X1TS U5317 ( .A0(n3948), .A1(n106), .B0(n3947), .Y(n3949) );
INVX2TS U5318 ( .A(n3952), .Y(n3954) );
NAND2X1TS U5319 ( .A(n3954), .B(n3953), .Y(n3955) );
INVX2TS U5320 ( .A(n3957), .Y(n3959) );
NAND2X1TS U5321 ( .A(n3959), .B(n3958), .Y(n3961) );
INVX2TS U5322 ( .A(n4403), .Y(n3962) );
NAND2X1TS U5323 ( .A(n3962), .B(n4401), .Y(n3964) );
INVX2TS U5324 ( .A(n3963), .Y(n4402) );
INVX2TS U5325 ( .A(n3965), .Y(n3967) );
NAND2X1TS U5326 ( .A(n3967), .B(n3966), .Y(n3969) );
INVX2TS U5327 ( .A(n3970), .Y(n3972) );
NAND2X1TS U5328 ( .A(n3972), .B(n3971), .Y(n3974) );
INVX2TS U5329 ( .A(n3975), .Y(n4391) );
INVX2TS U5330 ( .A(n4390), .Y(n3976) );
NAND2X1TS U5331 ( .A(n3976), .B(n4389), .Y(n3977) );
INVX2TS U5332 ( .A(n3978), .Y(n4388) );
AOI21X1TS U5333 ( .A0(n4388), .A1(n4386), .B0(n3979), .Y(n3983) );
NAND2X1TS U5334 ( .A(n3981), .B(n3980), .Y(n3982) );
INVX2TS U5335 ( .A(n3984), .Y(n4379) );
NAND2X1TS U5336 ( .A(n3985), .B(n4377), .Y(n3986) );
AOI21X1TS U5337 ( .A0(n4038), .A1(n4036), .B0(n3990), .Y(n3995) );
NAND2X1TS U5338 ( .A(n3993), .B(n3992), .Y(n3994) );
INVX2TS U5339 ( .A(n4101), .Y(n4481) );
AOI21X1TS U5340 ( .A0(n4481), .A1(n103), .B0(n3996), .Y(n3997) );
NAND2X1TS U5341 ( .A(n3999), .B(n4365), .Y(n4000) );
INVX2TS U5342 ( .A(n4001), .Y(n4376) );
AOI21X1TS U5343 ( .A0(n4376), .A1(n4374), .B0(n4002), .Y(n4006) );
NAND2X1TS U5344 ( .A(n4004), .B(n4003), .Y(n4005) );
INVX2TS U5345 ( .A(n4007), .Y(n4364) );
INVX2TS U5346 ( .A(n4008), .Y(n4362) );
INVX2TS U5347 ( .A(n4361), .Y(n4009) );
AOI21X1TS U5348 ( .A0(n4364), .A1(n4362), .B0(n4009), .Y(n4014) );
NAND2X1TS U5349 ( .A(n4012), .B(n4011), .Y(n4013) );
AOI21X1TS U5350 ( .A0(n4364), .A1(n4016), .B0(n4015), .Y(n4355) );
NAND2X1TS U5351 ( .A(n4017), .B(n4353), .Y(n4018) );
INVX2TS U5352 ( .A(n4019), .Y(n4347) );
NAND2X1TS U5353 ( .A(n4020), .B(n4345), .Y(n4021) );
AOI21X1TS U5354 ( .A0(n4207), .A1(n4205), .B0(n4027), .Y(n4032) );
NAND2X1TS U5355 ( .A(n4030), .B(n4029), .Y(n4031) );
CLKBUFX2TS U5356 ( .A(n4039), .Y(n4446) );
AOI21X1TS U5357 ( .A0(n4481), .A1(n98), .B0(n4033), .Y(n4034) );
NAND2X1TS U5358 ( .A(n4036), .B(n4035), .Y(n4037) );
AOI21X1TS U5359 ( .A0(n4481), .A1(n124), .B0(n4040), .Y(n4041) );
INVX2TS U5360 ( .A(genblk1_left_mult_x_1_n493), .Y(
genblk1_left_mult_x_1_n498) );
INVX2TS U5361 ( .A(n4049), .Y(n4108) );
INVX2TS U5362 ( .A(n4044), .Y(n4048) );
NAND2X1TS U5363 ( .A(n4048), .B(n4046), .Y(n4045) );
AOI21X1TS U5364 ( .A0(n4049), .A1(n4048), .B0(n4047), .Y(n4054) );
NAND2X1TS U5365 ( .A(n4052), .B(n4051), .Y(n4053) );
INVX2TS U5366 ( .A(n4059), .Y(n4342) );
AOI21X1TS U5367 ( .A0(n4344), .A1(n4342), .B0(n4060), .Y(n4065) );
NAND2X1TS U5368 ( .A(n4063), .B(n4062), .Y(n4064) );
INVX2TS U5369 ( .A(n4066), .Y(n4176) );
AOI21X1TS U5370 ( .A0(n4176), .A1(n4174), .B0(n4068), .Y(n4073) );
NAND2X1TS U5371 ( .A(n4071), .B(n4070), .Y(n4072) );
AOI21X1TS U5372 ( .A0(n4481), .A1(n90), .B0(n4074), .Y(n4075) );
INVX2TS U5373 ( .A(n4076), .Y(n4336) );
AOI21X1TS U5374 ( .A0(n4336), .A1(n4078), .B0(n4077), .Y(n4082) );
NAND2X1TS U5375 ( .A(n4080), .B(n4079), .Y(n4081) );
AOI21X1TS U5376 ( .A0(n4336), .A1(n4334), .B0(n4084), .Y(n4089) );
NAND2X1TS U5377 ( .A(n4087), .B(n4086), .Y(n4088) );
AOI21X1TS U5378 ( .A0(n4336), .A1(n4091), .B0(n4090), .Y(n4327) );
NAND2X1TS U5379 ( .A(n4092), .B(n4325), .Y(n4093) );
AOI21X1TS U5380 ( .A0(n4423), .A1(n4421), .B0(n4095), .Y(n4100) );
NAND2X1TS U5381 ( .A(n4098), .B(n4097), .Y(n4099) );
INVX2TS U5382 ( .A(n4101), .Y(n4458) );
AOI21X1TS U5383 ( .A0(n4458), .A1(n74), .B0(n4102), .Y(n4103) );
INVX2TS U5384 ( .A(n4109), .Y(n4338) );
AOI21X1TS U5385 ( .A0(n4340), .A1(n4338), .B0(n4110), .Y(n4115) );
NAND2X1TS U5386 ( .A(n4113), .B(n4112), .Y(n4114) );
INVX2TS U5387 ( .A(n4116), .Y(n4119) );
AOI21X1TS U5388 ( .A0(n4336), .A1(n4119), .B0(n4118), .Y(n4161) );
AOI21X1TS U5389 ( .A0(n4319), .A1(n4317), .B0(n4120), .Y(n4123) );
NAND2X1TS U5390 ( .A(n370), .B(n4121), .Y(n4122) );
OAI21X1TS U5391 ( .A0(n4156), .A1(n4125), .B0(n4124), .Y(n4130) );
NAND2X1TS U5392 ( .A(n4128), .B(n4127), .Y(n4129) );
AOI21X1TS U5393 ( .A0(n4458), .A1(n62), .B0(n4131), .Y(n4132) );
NAND2X1TS U5394 ( .A(n4134), .B(n4137), .Y(n4140) );
AOI21X1TS U5395 ( .A0(n4138), .A1(n4137), .B0(n4136), .Y(n4139) );
AOI21X1TS U5396 ( .A0(n4182), .A1(n4180), .B0(n4142), .Y(n4147) );
NAND2X1TS U5397 ( .A(n4145), .B(n4144), .Y(n4146) );
AOI21X1TS U5398 ( .A0(n4481), .A1(n83), .B0(n4148), .Y(n4149) );
AOI21X1TS U5399 ( .A0(n4458), .A1(n58), .B0(n4150), .Y(n4151) );
INVX2TS U5400 ( .A(genblk1_left_mult_x_1_n585), .Y(
genblk1_left_mult_x_1_n596) );
OAI21X1TS U5401 ( .A0(n4156), .A1(n4155), .B0(n4154), .Y(n4191) );
NAND2X1TS U5402 ( .A(n4190), .B(n4188), .Y(n4158) );
AOI21X1TS U5403 ( .A0(n4458), .A1(n4857), .B0(n4159), .Y(n4160) );
INVX2TS U5404 ( .A(n4161), .Y(n4324) );
AOI21X1TS U5405 ( .A0(n4324), .A1(n4163), .B0(n4162), .Y(n4307) );
INVX2TS U5406 ( .A(n4164), .Y(n4167) );
AOI21X1TS U5407 ( .A0(n4315), .A1(n4167), .B0(n4166), .Y(n4172) );
INVX2TS U5408 ( .A(n4168), .Y(n4170) );
NAND2X1TS U5409 ( .A(n4170), .B(n4169), .Y(n4171) );
NAND2X1TS U5410 ( .A(n4174), .B(n4173), .Y(n4175) );
AOI21X1TS U5411 ( .A0(n4481), .A1(n85), .B0(n4177), .Y(n4178) );
NAND2X1TS U5412 ( .A(n4180), .B(n4179), .Y(n4181) );
AOI21X1TS U5413 ( .A0(n4458), .A1(n78), .B0(n4183), .Y(n4184) );
INVX2TS U5414 ( .A(genblk1_left_mult_x_1_n530), .Y(
genblk1_left_mult_x_1_n538) );
AOI222XLTS U5415 ( .A0(n4221), .A1(n65), .B0(n4977), .B1(n4934), .C0(n4968),
.C1(n62), .Y(n4186) );
AOI21X1TS U5416 ( .A0(n4191), .A1(n4190), .B0(n4189), .Y(n4196) );
NAND2X1TS U5417 ( .A(n4194), .B(n4193), .Y(n4195) );
AOI222XLTS U5418 ( .A0(n4221), .A1(n74), .B0(n4977), .B1(Data_B_i[37]), .C0(
n4976), .C1(Data_B_i[36]), .Y(n4197) );
INVX2TS U5419 ( .A(n4224), .Y(n4965) );
AOI21X1TS U5420 ( .A0(n4965), .A1(n119), .B0(n4199), .Y(n4200) );
AOI222XLTS U5421 ( .A0(n4978), .A1(n111), .B0(n4961), .B1(n107), .C0(n4965),
.C1(Data_B_i[46]), .Y(n4202) );
NAND2X1TS U5422 ( .A(n4205), .B(n4204), .Y(n4206) );
AOI21X1TS U5423 ( .A0(n4481), .A1(n95), .B0(n4208), .Y(n4209) );
NOR2X1TS U5424 ( .A(n4211), .B(n4210), .Y(n4595) );
CLKBUFX2TS U5425 ( .A(n4595), .Y(n4585) );
AOI222XLTS U5426 ( .A0(n4585), .A1(n114), .B0(n4573), .B1(Data_B_i[48]),
.C0(n4576), .C1(n106), .Y(n4212) );
CMPR32X2TS U5427 ( .A(n193), .B(n4292), .C(n4214), .CO(
genblk1_left_mult_x_1_n502), .S(genblk1_left_mult_x_1_n503) );
AOI222XLTS U5428 ( .A0(n4973), .A1(n103), .B0(n4961), .B1(n122), .C0(n4965),
.C1(n98), .Y(n4215) );
AOI222XLTS U5429 ( .A0(n4973), .A1(n124), .B0(n4961), .B1(n99), .C0(n4965),
.C1(n95), .Y(n4217) );
AOI222XLTS U5430 ( .A0(n4973), .A1(n87), .B0(n4969), .B1(n83), .C0(n4976),
.C1(n79), .Y(n4219) );
AOI222XLTS U5431 ( .A0(n4221), .A1(n71), .B0(n4977), .B1(Data_B_i[36]), .C0(
n4976), .C1(n4185), .Y(n4222) );
AOI222XLTS U5432 ( .A0(n4973), .A1(Data_B_i[43]), .B0(n4969), .B1(
Data_B_i[42]), .C0(n4968), .C1(n85), .Y(n4226) );
AOI222XLTS U5433 ( .A0(n4978), .A1(Data_B_i[49]), .B0(n4961), .B1(n110),
.C0(n4965), .C1(Data_B_i[47]), .Y(n4228) );
XOR2X1TS U5434 ( .A(n4229), .B(n4959), .Y(genblk1_left_mult_x_1_n1318) );
XNOR2X1TS U5435 ( .A(n186), .B(Data_A_i[39]), .Y(n4266) );
NAND2BX1TS U5436 ( .AN(n4266), .B(n4267), .Y(n4706) );
XNOR2X1TS U5437 ( .A(Data_A_i[39]), .B(Data_A_i[40]), .Y(n4265) );
NOR2BX1TS U5438 ( .AN(n4266), .B(n4265), .Y(n4726) );
CLKBUFX2TS U5439 ( .A(n4726), .Y(n4750) );
NOR2X1TS U5440 ( .A(n4267), .B(n4266), .Y(n4753) );
AOI22X1TS U5441 ( .A0(n4750), .A1(n4549), .B0(n4740), .B1(n4761), .Y(n4230)
);
NAND2X1TS U5442 ( .A(n4740), .B(n4539), .Y(n4232) );
XNOR2X1TS U5443 ( .A(n182), .B(Data_A_i[36]), .Y(n4235) );
NAND2BX1TS U5444 ( .AN(n4235), .B(n4236), .Y(n4538) );
NOR2X1TS U5445 ( .A(n4236), .B(n4235), .Y(n4814) );
XNOR2X1TS U5446 ( .A(Data_A_i[36]), .B(Data_A_i[37]), .Y(n4234) );
NOR2BX1TS U5447 ( .AN(n4235), .B(n4234), .Y(n4784) );
CLKBUFX2TS U5448 ( .A(n4784), .Y(n4813) );
AND3X1TS U5449 ( .A(n4236), .B(n4235), .C(n4234), .Y(n4802) );
INVX2TS U5450 ( .A(n4802), .Y(n4439) );
INVX2TS U5451 ( .A(n4439), .Y(n4812) );
AOI222XLTS U5452 ( .A0(n4796), .A1(n4873), .B0(n4813), .B1(Data_B_i[30]),
.C0(n4812), .C1(Data_B_i[29]), .Y(n4237) );
AOI222XLTS U5453 ( .A0(n4947), .A1(Data_B_i[37]), .B0(n4940), .B1(
Data_B_i[36]), .C0(n4931), .C1(n4857), .Y(n4239) );
CMPR32X2TS U5454 ( .A(n4243), .B(n4242), .C(n4241), .CO(
genblk1_left_mult_x_1_n782), .S(genblk1_left_mult_x_1_n783) );
XNOR2X1TS U5455 ( .A(Data_A_i[44]), .B(Data_A_i[45]), .Y(n4259) );
XNOR2X1TS U5456 ( .A(Data_A_i[45]), .B(Data_A_i[46]), .Y(n4258) );
NOR2BX1TS U5457 ( .AN(n4259), .B(n4258), .Y(n4619) );
CLKBUFX2TS U5458 ( .A(n4619), .Y(n4639) );
NOR2X1TS U5459 ( .A(n4260), .B(n4259), .Y(n4642) );
CLKBUFX2TS U5460 ( .A(n4642), .Y(n4633) );
AOI22X1TS U5461 ( .A0(n4639), .A1(n4549), .B0(n4633), .B1(n4761), .Y(n4244)
);
NAND2X1TS U5462 ( .A(n4633), .B(n4539), .Y(n4246) );
XOR2X1TS U5463 ( .A(n4247), .B(n198), .Y(n4521) );
XNOR2X1TS U5464 ( .A(n190), .B(Data_A_i[42]), .Y(n4249) );
NAND2BX1TS U5465 ( .AN(n4249), .B(n4250), .Y(n4518) );
NOR2X1TS U5466 ( .A(n4250), .B(n4249), .Y(n4702) );
XNOR2X1TS U5467 ( .A(Data_A_i[42]), .B(Data_A_i[43]), .Y(n4248) );
NOR2BX1TS U5468 ( .AN(n4249), .B(n4248), .Y(n4672) );
CLKBUFX2TS U5469 ( .A(n4672), .Y(n4701) );
AND3X1TS U5470 ( .A(n4250), .B(n4249), .C(n4248), .Y(n4690) );
INVX2TS U5471 ( .A(n4690), .Y(n4293) );
INVX2TS U5472 ( .A(n4293), .Y(n4700) );
AOI222XLTS U5473 ( .A0(n4684), .A1(n4870), .B0(n4701), .B1(n51), .C0(n4700),
.C1(n47), .Y(n4251) );
CLKBUFX2TS U5474 ( .A(n4784), .Y(n4809) );
AOI222XLTS U5475 ( .A0(n4814), .A1(n70), .B0(n4809), .B1(n67), .C0(n4802),
.C1(n4857), .Y(n4253) );
CMPR32X2TS U5476 ( .A(n4257), .B(n4256), .C(n4255), .CO(
genblk1_left_mult_x_1_n734), .S(genblk1_left_mult_x_1_n735) );
CLKBUFX2TS U5477 ( .A(n4619), .Y(n4651) );
AND3X1TS U5478 ( .A(n4260), .B(n4259), .C(n4258), .Y(n4636) );
INVX2TS U5479 ( .A(n4636), .Y(n4601) );
INVX2TS U5480 ( .A(n4601), .Y(n4650) );
AOI222XLTS U5481 ( .A0(n4652), .A1(Data_B_i[29]), .B0(n4651), .B1(n4878),
.C0(n4650), .C1(n422), .Y(n4261) );
ADDHXLTS U5482 ( .A(n4264), .B(n4263), .CO(n4516), .S(n4257) );
CLKBUFX2TS U5483 ( .A(n4726), .Y(n4763) );
AND3X1TS U5484 ( .A(n4267), .B(n4266), .C(n4265), .Y(n4745) );
INVX2TS U5485 ( .A(n4745), .Y(n4708) );
INVX2TS U5486 ( .A(n4708), .Y(n4762) );
AOI222XLTS U5487 ( .A0(n4753), .A1(n516), .B0(n4763), .B1(n62), .C0(n4762),
.C1(Data_B_i[33]), .Y(n4268) );
AOI222XLTS U5488 ( .A0(n4684), .A1(n55), .B0(n4701), .B1(n4870), .C0(n4700),
.C1(n50), .Y(n4270) );
CMPR32X2TS U5489 ( .A(n4274), .B(n4273), .C(n4272), .CO(
genblk1_left_mult_x_1_n724), .S(genblk1_left_mult_x_1_n725) );
CLKBUFX2TS U5490 ( .A(n4518), .Y(n4668) );
INVX2TS U5491 ( .A(n4293), .Y(n4675) );
CLKBUFX2TS U5492 ( .A(n4672), .Y(n4697) );
AOI21X1TS U5493 ( .A0(n4675), .A1(n40), .B0(n4697), .Y(n4275) );
AOI222XLTS U5494 ( .A0(n4585), .A1(n107), .B0(n4573), .B1(n102), .C0(n4576),
.C1(n122), .Y(n4277) );
CMPR32X2TS U5495 ( .A(n4280), .B(genblk1_left_mult_x_1_n521), .C(n4279),
.CO(genblk1_left_mult_x_1_n514), .S(genblk1_left_mult_x_1_n515) );
AOI222XLTS U5496 ( .A0(n4764), .A1(n47), .B0(n4763), .B1(n4878), .C0(n4762),
.C1(n422), .Y(n4281) );
ADDHXLTS U5497 ( .A(n4284), .B(n4283), .CO(n4536), .S(n4243) );
AOI222XLTS U5498 ( .A0(n4867), .A1(n516), .B0(n4880), .B1(Data_B_i[34]),
.C0(n4858), .C1(n59), .Y(n4285) );
AOI222XLTS U5499 ( .A0(n4796), .A1(Data_B_i[32]), .B0(n4813), .B1(n4870),
.C0(n4812), .C1(Data_B_i[30]), .Y(n4287) );
CMPR32X2TS U5500 ( .A(n4291), .B(n4290), .C(n4289), .CO(
genblk1_left_mult_x_1_n775), .S(genblk1_left_mult_x_1_n776) );
CMPR32X2TS U5501 ( .A(n4297), .B(n4296), .C(n4295), .CO(
genblk1_left_mult_x_1_n507), .S(genblk1_left_mult_x_1_n508) );
NAND2X1TS U5502 ( .A(n4585), .B(n4539), .Y(n4298) );
XOR2X1TS U5503 ( .A(n4299), .B(n202), .Y(n4504) );
AFHCONX2TS U5504 ( .A(n4302), .B(n4301), .CI(n4300), .CON(n1175), .S(
genblk1_left_N49) );
AFHCONX2TS U5505 ( .A(n4304), .B(genblk1_left_mult_x_1_n488), .CI(n4303),
.CON(n826), .S(genblk1_left_N47) );
AFHCONX2TS U5506 ( .A(genblk1_left_mult_x_1_n492), .B(
genblk1_left_mult_x_1_n496), .CI(n4305), .CON(n1458), .S(
genblk1_left_N45) );
NAND2X1TS U5507 ( .A(n4309), .B(n4308), .Y(n4310) );
XNOR2X1TS U5508 ( .A(n4311), .B(n4310), .Y(genblk1_left_N42) );
NAND2X1TS U5509 ( .A(n4313), .B(n4312), .Y(n4314) );
XNOR2X1TS U5510 ( .A(n4315), .B(n4314), .Y(genblk1_left_N41) );
NAND2X1TS U5511 ( .A(n4317), .B(n4316), .Y(n4318) );
XNOR2X1TS U5512 ( .A(n4319), .B(n4318), .Y(genblk1_left_N39) );
NAND2X1TS U5513 ( .A(n4322), .B(n4321), .Y(n4323) );
XNOR2X1TS U5514 ( .A(n4324), .B(n4323), .Y(genblk1_left_N38) );
NAND2X1TS U5515 ( .A(n4330), .B(n4329), .Y(n4331) );
XNOR2X1TS U5516 ( .A(n4332), .B(n4331), .Y(genblk1_left_N37) );
NAND2X1TS U5517 ( .A(n4334), .B(n4333), .Y(n4335) );
XNOR2X1TS U5518 ( .A(n4336), .B(n4335), .Y(genblk1_left_N34) );
NAND2X1TS U5519 ( .A(n4338), .B(n4337), .Y(n4339) );
XNOR2X1TS U5520 ( .A(n4340), .B(n4339), .Y(genblk1_left_N32) );
NAND2X1TS U5521 ( .A(n4342), .B(n4341), .Y(n4343) );
XNOR2X1TS U5522 ( .A(n4344), .B(n4343), .Y(genblk1_left_N28) );
NAND2X1TS U5523 ( .A(n4350), .B(n4349), .Y(n4351) );
XNOR2X1TS U5524 ( .A(n4352), .B(n4351), .Y(genblk1_left_N27) );
NAND2X1TS U5525 ( .A(n4358), .B(n4357), .Y(n4359) );
XNOR2X1TS U5526 ( .A(n4360), .B(n4359), .Y(genblk1_left_N25) );
NAND2X1TS U5527 ( .A(n4362), .B(n4361), .Y(n4363) );
XNOR2X1TS U5528 ( .A(n4364), .B(n4363), .Y(genblk1_left_N22) );
NAND2X1TS U5529 ( .A(n4370), .B(n4369), .Y(n4371) );
XNOR2X1TS U5530 ( .A(n4372), .B(n4371), .Y(genblk1_left_N21) );
NAND2X1TS U5531 ( .A(n4374), .B(n4373), .Y(n4375) );
XNOR2X1TS U5532 ( .A(n4376), .B(n4375), .Y(genblk1_left_N18) );
NAND2X1TS U5533 ( .A(n4382), .B(n4381), .Y(n4383) );
XNOR2X1TS U5534 ( .A(n4384), .B(n4383), .Y(genblk1_left_N17) );
NAND2X1TS U5535 ( .A(n4386), .B(n4385), .Y(n4387) );
XNOR2X1TS U5536 ( .A(n4388), .B(n4387), .Y(genblk1_left_N14) );
INVX2TS U5537 ( .A(n4392), .Y(n4394) );
NAND2X1TS U5538 ( .A(n4394), .B(n4393), .Y(n4395) );
XNOR2X1TS U5539 ( .A(n4396), .B(n4395), .Y(genblk1_left_N13) );
NAND2X1TS U5540 ( .A(n4398), .B(n4397), .Y(n4400) );
XNOR2X1TS U5541 ( .A(n4400), .B(n4399), .Y(genblk1_left_N10) );
INVX2TS U5542 ( .A(n4404), .Y(n4406) );
NAND2X1TS U5543 ( .A(n4406), .B(n4405), .Y(n4407) );
XNOR2X1TS U5544 ( .A(n4408), .B(n4407), .Y(genblk1_left_N8) );
NAND2X1TS U5545 ( .A(n4410), .B(n4409), .Y(n4412) );
XNOR2X1TS U5546 ( .A(n4412), .B(n4411), .Y(genblk1_left_N5) );
NAND2X1TS U5547 ( .A(n4414), .B(n4413), .Y(n4416) );
XNOR2X1TS U5548 ( .A(n4416), .B(n4415), .Y(genblk1_left_N3) );
INVX2TS U5549 ( .A(n4417), .Y(n4419) );
XNOR2X1TS U5550 ( .A(n4419), .B(n4418), .Y(genblk1_left_N1) );
NAND2X1TS U5551 ( .A(n4421), .B(n4420), .Y(n4422) );
AOI21X1TS U5552 ( .A0(n4458), .A1(n71), .B0(n4424), .Y(n4425) );
OAI21X1TS U5553 ( .A0(n18), .A1(n4466), .B0(n4425), .Y(n4431) );
CLKBUFX2TS U5554 ( .A(n4573), .Y(n4579) );
INVX2TS U5555 ( .A(n4426), .Y(n4593) );
AOI222XLTS U5556 ( .A0(n4582), .A1(Data_B_i[43]), .B0(n4579), .B1(n91), .C0(
n4593), .C1(n86), .Y(n4427) );
OAI21X1TS U5557 ( .A0(n4917), .A1(n4452), .B0(n4427), .Y(n4428) );
CMPR32X2TS U5558 ( .A(n4430), .B(n4431), .C(n4429), .CO(
genblk1_left_mult_x_1_n545), .S(genblk1_left_mult_x_1_n546) );
INVX2TS U5559 ( .A(n4431), .Y(n4436) );
AOI222XLTS U5560 ( .A0(n4582), .A1(n87), .B0(n4579), .B1(n82), .C0(n4590),
.C1(n79), .Y(n4432) );
OAI21X1TS U5561 ( .A0(n4923), .A1(n4452), .B0(n4432), .Y(n4433) );
XOR2X1TS U5562 ( .A(n4433), .B(Data_A_i[50]), .Y(n4442) );
CLKBUFX2TS U5563 ( .A(n4538), .Y(n4780) );
CMPR32X2TS U5564 ( .A(n4436), .B(n4442), .C(n4435), .CO(
genblk1_left_mult_x_1_n553), .S(genblk1_left_mult_x_1_n554) );
AOI21X1TS U5565 ( .A0(n4458), .A1(n67), .B0(n4437), .Y(n4438) );
INVX2TS U5566 ( .A(n4439), .Y(n4787) );
AOI21X1TS U5567 ( .A0(n4787), .A1(n630), .B0(n4809), .Y(n4440) );
CMPR32X2TS U5568 ( .A(n4445), .B(n4444), .C(n4443), .CO(
genblk1_left_mult_x_1_n563), .S(genblk1_left_mult_x_1_n564) );
AOI21X1TS U5569 ( .A0(n4458), .A1(n55), .B0(n4447), .Y(n4448) );
CMPR32X2TS U5570 ( .A(n177), .B(n607), .C(n4449), .CO(
genblk1_left_mult_x_1_n606), .S(genblk1_left_mult_x_1_n607) );
AOI21X1TS U5571 ( .A0(n4458), .A1(n4944), .B0(n4450), .Y(n4451) );
AOI222XLTS U5572 ( .A0(n4595), .A1(n66), .B0(n4594), .B1(n4934), .C0(n4593),
.C1(n63), .Y(n4453) );
CMPR32X2TS U5573 ( .A(n4955), .B(n4456), .C(n4455), .CO(
genblk1_left_mult_x_1_n617), .S(genblk1_left_mult_x_1_n618) );
AOI21X1TS U5574 ( .A0(n4458), .A1(n50), .B0(n4457), .Y(n4459) );
AOI222XLTS U5575 ( .A0(n4595), .A1(n4934), .B0(n4579), .B1(n62), .C0(n4593),
.C1(n58), .Y(n4460) );
CMPR32X2TS U5576 ( .A(n4955), .B(n4463), .C(n4462), .CO(
genblk1_left_mult_x_1_n628), .S(genblk1_left_mult_x_1_n629) );
AOI21X1TS U5577 ( .A0(n4481), .A1(Data_B_i[29]), .B0(n4464), .Y(n4465) );
AOI222XLTS U5578 ( .A0(n4642), .A1(n70), .B0(n4639), .B1(n66), .C0(n4636),
.C1(n4857), .Y(n4467) );
XOR2X1TS U5579 ( .A(n4468), .B(Data_A_i[47]), .Y(n4469) );
CMPR32X2TS U5580 ( .A(n4955), .B(n4470), .C(n4469), .CO(
genblk1_left_mult_x_1_n639), .S(genblk1_left_mult_x_1_n640) );
AOI21X1TS U5581 ( .A0(n4481), .A1(n4548), .B0(n4471), .Y(n4472) );
AOI222XLTS U5582 ( .A0(n4595), .A1(n59), .B0(n4579), .B1(n54), .C0(n4593),
.C1(n4873), .Y(n4473) );
XOR2X1TS U5583 ( .A(n4474), .B(Data_A_i[50]), .Y(n4478) );
AOI222XLTS U5584 ( .A0(n4642), .A1(Data_B_i[36]), .B0(n4639), .B1(n4934),
.C0(n4650), .C1(n63), .Y(n4475) );
CMPR32X2TS U5585 ( .A(n4479), .B(n4478), .C(n4477), .CO(
genblk1_left_mult_x_1_n650), .S(genblk1_left_mult_x_1_n651) );
AOI21X1TS U5586 ( .A0(n4481), .A1(n4539), .B0(n4480), .Y(n4482) );
AOI222XLTS U5587 ( .A0(n4642), .A1(n516), .B0(n4651), .B1(Data_B_i[34]),
.C0(n4650), .C1(Data_B_i[33]), .Y(n4483) );
XOR2X1TS U5588 ( .A(n4484), .B(n199), .Y(n4488) );
AOI222XLTS U5589 ( .A0(n4582), .A1(n55), .B0(n4579), .B1(n4870), .C0(n4593),
.C1(n50), .Y(n4485) );
CMPR32X2TS U5590 ( .A(n4489), .B(n4488), .C(n4487), .CO(
genblk1_left_mult_x_1_n661), .S(genblk1_left_mult_x_1_n662) );
NAND2X1TS U5591 ( .A(n4490), .B(n4539), .Y(n4491) );
AOI222XLTS U5592 ( .A0(n4582), .A1(n4870), .B0(n4579), .B1(Data_B_i[30]),
.C0(n4593), .C1(n46), .Y(n4493) );
AOI222XLTS U5593 ( .A0(n4702), .A1(n71), .B0(n4697), .B1(n67), .C0(n4690),
.C1(n516), .Y(n4495) );
CMPR32X2TS U5594 ( .A(n4499), .B(n4498), .C(n4497), .CO(
genblk1_left_mult_x_1_n672), .S(genblk1_left_mult_x_1_n673) );
AOI222XLTS U5595 ( .A0(n4582), .A1(n46), .B0(n4579), .B1(n4878), .C0(n4593),
.C1(n422), .Y(n4500) );
XOR2X1TS U5596 ( .A(n4501), .B(n202), .Y(n4510) );
AOI22X1TS U5597 ( .A0(n4594), .A1(n4549), .B0(n4585), .B1(n4761), .Y(n4502)
);
ADDHXLTS U5598 ( .A(n202), .B(n4504), .CO(n4514), .S(
genblk1_left_mult_x_1_n717) );
NOR2XLTS U5599 ( .A(n4506), .B(n4505), .Y(n4513) );
AOI222XLTS U5600 ( .A0(n4582), .A1(n51), .B0(n4579), .B1(Data_B_i[29]), .C0(
n4593), .C1(n4761), .Y(n4507) );
CMPR32X2TS U5601 ( .A(n4513), .B(n4512), .C(n4511), .CO(
genblk1_left_mult_x_1_n683), .S(genblk1_left_mult_x_1_n684) );
ADDHXLTS U5602 ( .A(n4515), .B(n4514), .CO(n4509), .S(
genblk1_left_mult_x_1_n706) );
ADDHXLTS U5603 ( .A(n4517), .B(n4516), .CO(genblk1_left_mult_x_1_n726), .S(
n4274) );
CLKBUFX2TS U5604 ( .A(n4702), .Y(n4687) );
NAND2X1TS U5605 ( .A(n4687), .B(n4539), .Y(n4519) );
XOR2X1TS U5606 ( .A(n4520), .B(n194), .Y(n4528) );
ADDHXLTS U5607 ( .A(n197), .B(n4521), .CO(n4263), .S(n4531) );
AOI222XLTS U5608 ( .A0(n4684), .A1(n50), .B0(n4701), .B1(n47), .C0(n4700),
.C1(n4761), .Y(n4522) );
AOI222XLTS U5609 ( .A0(n4684), .A1(n47), .B0(n4701), .B1(n4878), .C0(n4700),
.C1(n422), .Y(n4524) );
AOI22X1TS U5610 ( .A0(n4697), .A1(n4549), .B0(n4687), .B1(n4761), .Y(n4526)
);
ADDHXLTS U5611 ( .A(n195), .B(n4528), .CO(n4534), .S(
genblk1_left_mult_x_1_n771) );
CMPR32X2TS U5612 ( .A(n4531), .B(n4530), .C(n4529), .CO(
genblk1_left_mult_x_1_n744), .S(genblk1_left_mult_x_1_n745) );
ADDHXLTS U5613 ( .A(n4533), .B(n4532), .CO(n4529), .S(
genblk1_left_mult_x_1_n755) );
ADDHXLTS U5614 ( .A(n4535), .B(n4534), .CO(n4532), .S(
genblk1_left_mult_x_1_n763) );
ADDHXLTS U5615 ( .A(n4537), .B(n4536), .CO(genblk1_left_mult_x_1_n777), .S(
n4291) );
CLKBUFX2TS U5616 ( .A(n4814), .Y(n4799) );
NAND2X1TS U5617 ( .A(n4799), .B(n4539), .Y(n4540) );
ADDHXLTS U5618 ( .A(n191), .B(n4543), .CO(n4283), .S(n4556) );
AOI222XLTS U5619 ( .A0(n4796), .A1(n51), .B0(n4813), .B1(n46), .C0(n4812),
.C1(n4878), .Y(n4544) );
AOI222XLTS U5620 ( .A0(n4796), .A1(Data_B_i[29]), .B0(n4813), .B1(n4878),
.C0(n4812), .C1(n422), .Y(n4546) );
AOI22X1TS U5621 ( .A0(n4809), .A1(n4549), .B0(n4799), .B1(n4548), .Y(n4550)
);
ADDHXLTS U5622 ( .A(n188), .B(n4553), .CO(n4559), .S(
genblk1_left_mult_x_1_n807) );
CMPR32X2TS U5623 ( .A(n4556), .B(n4555), .C(n4554), .CO(
genblk1_left_mult_x_1_n789), .S(genblk1_left_mult_x_1_n790) );
ADDHXLTS U5624 ( .A(n4558), .B(n4557), .CO(n4554), .S(
genblk1_left_mult_x_1_n797) );
ADDHXLTS U5625 ( .A(n4560), .B(n4559), .CO(n4557), .S(
genblk1_left_mult_x_1_n802) );
AOI21X1TS U5626 ( .A0(n4576), .A1(n119), .B0(n4561), .Y(n4562) );
AOI222XLTS U5627 ( .A0(n4585), .A1(Data_B_i[51]), .B0(n4594), .B1(n118),
.C0(n4576), .C1(Data_B_i[49]), .Y(n4564) );
AOI222XLTS U5628 ( .A0(n4585), .A1(Data_B_i[50]), .B0(n4573), .B1(
Data_B_i[49]), .C0(n4576), .C1(Data_B_i[48]), .Y(n4566) );
AOI222XLTS U5629 ( .A0(n4585), .A1(n111), .B0(n4573), .B1(n106), .C0(n4576),
.C1(n103), .Y(n4568) );
AOI222XLTS U5630 ( .A0(n4582), .A1(n102), .B0(n4573), .B1(n123), .C0(n4576),
.C1(Data_B_i[44]), .Y(n4571) );
AOI222XLTS U5631 ( .A0(n4582), .A1(n123), .B0(n4573), .B1(Data_B_i[44]),
.C0(n4576), .C1(n95), .Y(n4574) );
AOI222XLTS U5632 ( .A0(n4585), .A1(n99), .B0(n4579), .B1(Data_B_i[43]), .C0(
n4576), .C1(n89), .Y(n4577) );
AOI222XLTS U5633 ( .A0(n4582), .A1(n90), .B0(n4579), .B1(n86), .C0(n4593),
.C1(Data_B_i[40]), .Y(n4580) );
AOI222XLTS U5634 ( .A0(n4582), .A1(n83), .B0(n4594), .B1(Data_B_i[39]), .C0(
n4590), .C1(n75), .Y(n4583) );
XOR2X1TS U5635 ( .A(n4584), .B(n202), .Y(genblk1_left_mult_x_1_n1124) );
AOI222XLTS U5636 ( .A0(n4585), .A1(Data_B_i[39]), .B0(n4594), .B1(
Data_B_i[38]), .C0(n4590), .C1(n71), .Y(n4586) );
AOI222XLTS U5637 ( .A0(n4595), .A1(Data_B_i[38]), .B0(n4594), .B1(n70), .C0(
n4590), .C1(n66), .Y(n4588) );
AOI222XLTS U5638 ( .A0(n4595), .A1(Data_B_i[37]), .B0(n4594), .B1(
Data_B_i[36]), .C0(n4590), .C1(n516), .Y(n4591) );
XOR2X1TS U5639 ( .A(n4592), .B(n202), .Y(genblk1_left_mult_x_1_n1127) );
AOI222XLTS U5640 ( .A0(n4595), .A1(n62), .B0(n4594), .B1(Data_B_i[33]), .C0(
n4593), .C1(Data_B_i[32]), .Y(n4596) );
INVX2TS U5641 ( .A(n4601), .Y(n4622) );
AOI21X1TS U5642 ( .A0(n4622), .A1(n40), .B0(n4639), .Y(n4602) );
AOI21X1TS U5643 ( .A0(n4622), .A1(Data_B_i[50]), .B0(n4604), .Y(n4605) );
AOI222XLTS U5644 ( .A0(n4633), .A1(n40), .B0(n4639), .B1(Data_B_i[50]), .C0(
n4622), .C1(Data_B_i[49]), .Y(n4607) );
AOI222XLTS U5645 ( .A0(n4633), .A1(Data_B_i[50]), .B0(n4619), .B1(n115),
.C0(n4622), .C1(n110), .Y(n4609) );
AOI222XLTS U5646 ( .A0(n4633), .A1(n114), .B0(n4619), .B1(Data_B_i[48]),
.C0(n4622), .C1(Data_B_i[47]), .Y(n4611) );
AOI222XLTS U5647 ( .A0(n4633), .A1(n110), .B0(n4619), .B1(Data_B_i[47]),
.C0(n4622), .C1(Data_B_i[46]), .Y(n4613) );
AOI222XLTS U5648 ( .A0(n4633), .A1(n107), .B0(n4619), .B1(Data_B_i[46]),
.C0(n4622), .C1(n122), .Y(n4615) );
AOI222XLTS U5649 ( .A0(n4652), .A1(n102), .B0(n4619), .B1(n122), .C0(n4622),
.C1(Data_B_i[44]), .Y(n4617) );
AOI222XLTS U5650 ( .A0(n4652), .A1(n124), .B0(n4619), .B1(n99), .C0(n4622),
.C1(n95), .Y(n4620) );
AOI222XLTS U5651 ( .A0(n4633), .A1(n98), .B0(n4651), .B1(Data_B_i[43]), .C0(
n4622), .C1(n90), .Y(n4623) );
AOI222XLTS U5652 ( .A0(n4652), .A1(n95), .B0(n4651), .B1(n91), .C0(n4650),
.C1(n87), .Y(n4625) );
OAI21X1TS U5653 ( .A0(n4917), .A1(n4654), .B0(n4625), .Y(n4626) );
AOI222XLTS U5654 ( .A0(n4652), .A1(Data_B_i[42]), .B0(n4651), .B1(n87), .C0(
n4650), .C1(n82), .Y(n4627) );
AOI222XLTS U5655 ( .A0(n4652), .A1(n87), .B0(n4651), .B1(n82), .C0(n4636),
.C1(n79), .Y(n4629) );
AOI222XLTS U5656 ( .A0(n4652), .A1(Data_B_i[40]), .B0(n4639), .B1(
Data_B_i[39]), .C0(n4636), .C1(n75), .Y(n4631) );
AOI222XLTS U5657 ( .A0(n4633), .A1(n78), .B0(n4639), .B1(n74), .C0(n4636),
.C1(n70), .Y(n4634) );
AOI222XLTS U5658 ( .A0(n4642), .A1(Data_B_i[38]), .B0(n4639), .B1(
Data_B_i[37]), .C0(n4636), .C1(n66), .Y(n4637) );
AOI222XLTS U5659 ( .A0(n4642), .A1(n63), .B0(n4639), .B1(n58), .C0(n4650),
.C1(n54), .Y(n4640) );
AOI222XLTS U5660 ( .A0(n4642), .A1(Data_B_i[33]), .B0(n4651), .B1(
Data_B_i[32]), .C0(n4650), .C1(n4944), .Y(n4643) );
AOI222XLTS U5661 ( .A0(n4652), .A1(n54), .B0(n4651), .B1(n4870), .C0(n4650),
.C1(Data_B_i[30]), .Y(n4645) );
AOI222XLTS U5662 ( .A0(n4652), .A1(n4873), .B0(n4651), .B1(n51), .C0(n4650),
.C1(n47), .Y(n4647) );
AOI222XLTS U5663 ( .A0(n4652), .A1(Data_B_i[30]), .B0(n4651), .B1(n46), .C0(
n4650), .C1(n4761), .Y(n4653) );
AOI21X1TS U5664 ( .A0(n4675), .A1(n119), .B0(n4656), .Y(n4657) );
AOI222XLTS U5665 ( .A0(n4687), .A1(n630), .B0(n4697), .B1(Data_B_i[50]),
.C0(n4675), .C1(n114), .Y(n4659) );
AOI222XLTS U5666 ( .A0(n4687), .A1(n118), .B0(n4672), .B1(n115), .C0(n4675),
.C1(n111), .Y(n4661) );
AOI222XLTS U5667 ( .A0(n4687), .A1(n114), .B0(n4672), .B1(Data_B_i[48]),
.C0(n4675), .C1(n106), .Y(n4663) );
AOI222XLTS U5668 ( .A0(n4687), .A1(Data_B_i[48]), .B0(n4672), .B1(
Data_B_i[47]), .C0(n4675), .C1(Data_B_i[46]), .Y(n4665) );
AOI222XLTS U5669 ( .A0(n4687), .A1(Data_B_i[47]), .B0(n4672), .B1(n102),
.C0(n4675), .C1(n123), .Y(n4667) );
AOI222XLTS U5670 ( .A0(n4684), .A1(n103), .B0(n4672), .B1(n124), .C0(n4675),
.C1(n99), .Y(n4670) );
XOR2X1TS U5671 ( .A(n4671), .B(n195), .Y(genblk1_left_mult_x_1_n1176) );
AOI222XLTS U5672 ( .A0(n4684), .A1(n123), .B0(n4672), .B1(n99), .C0(n4675),
.C1(n95), .Y(n4673) );
AOI222XLTS U5673 ( .A0(n4687), .A1(Data_B_i[44]), .B0(n4701), .B1(n94), .C0(
n4675), .C1(Data_B_i[42]), .Y(n4676) );
AOI222XLTS U5674 ( .A0(n4684), .A1(n94), .B0(n4701), .B1(Data_B_i[42]), .C0(
n4700), .C1(n85), .Y(n4678) );
XOR2X1TS U5675 ( .A(n4679), .B(n195), .Y(genblk1_left_mult_x_1_n1179) );
AOI222XLTS U5676 ( .A0(n4684), .A1(n91), .B0(n4701), .B1(n87), .C0(n4700),
.C1(n83), .Y(n4680) );
AOI222XLTS U5677 ( .A0(n4684), .A1(n86), .B0(n4701), .B1(Data_B_i[40]), .C0(
n4690), .C1(Data_B_i[39]), .Y(n4682) );
XOR2X1TS U5678 ( .A(n4683), .B(n196), .Y(genblk1_left_mult_x_1_n1181) );
AOI222XLTS U5679 ( .A0(n4684), .A1(Data_B_i[40]), .B0(n4697), .B1(
Data_B_i[39]), .C0(n4690), .C1(n74), .Y(n4685) );
AOI222XLTS U5680 ( .A0(n4687), .A1(Data_B_i[39]), .B0(n4697), .B1(n74), .C0(
n4690), .C1(n70), .Y(n4688) );
XOR2X1TS U5681 ( .A(n4689), .B(n194), .Y(genblk1_left_mult_x_1_n1183) );
AOI222XLTS U5682 ( .A0(n4702), .A1(n75), .B0(n4697), .B1(Data_B_i[37]), .C0(
n4690), .C1(n67), .Y(n4691) );
AOI222XLTS U5683 ( .A0(n4702), .A1(n66), .B0(n4697), .B1(n4934), .C0(n4700),
.C1(n62), .Y(n4693) );
AOI222XLTS U5684 ( .A0(n4702), .A1(n4934), .B0(n4701), .B1(n63), .C0(n4700),
.C1(n58), .Y(n4695) );
AOI222XLTS U5685 ( .A0(n4702), .A1(n63), .B0(n4697), .B1(n59), .C0(n4700),
.C1(Data_B_i[32]), .Y(n4698) );
AOI222XLTS U5686 ( .A0(n4702), .A1(Data_B_i[33]), .B0(n4701), .B1(n54), .C0(
n4700), .C1(n4873), .Y(n4703) );
INVX2TS U5687 ( .A(n4708), .Y(n4729) );
AOI21X1TS U5688 ( .A0(n4729), .A1(n40), .B0(n4750), .Y(n4709) );
AOI21X1TS U5689 ( .A0(n4729), .A1(n118), .B0(n4711), .Y(n4712) );
AOI222XLTS U5690 ( .A0(n4740), .A1(Data_B_i[51]), .B0(n4750), .B1(n118),
.C0(n4729), .C1(n114), .Y(n4714) );
AOI222XLTS U5691 ( .A0(n4740), .A1(n118), .B0(n4726), .B1(n114), .C0(n4729),
.C1(n110), .Y(n4716) );
AOI222XLTS U5692 ( .A0(n4740), .A1(n115), .B0(n4726), .B1(n111), .C0(n4729),
.C1(Data_B_i[47]), .Y(n4718) );
AOI222XLTS U5693 ( .A0(n4740), .A1(n110), .B0(n4726), .B1(Data_B_i[47]),
.C0(n4729), .C1(Data_B_i[46]), .Y(n4720) );
XOR2X1TS U5694 ( .A(n4721), .B(n192), .Y(genblk1_left_mult_x_1_n1203) );
AOI222XLTS U5695 ( .A0(n4740), .A1(n106), .B0(n4726), .B1(n102), .C0(n4729),
.C1(n123), .Y(n4722) );
XOR2X1TS U5696 ( .A(n4723), .B(n192), .Y(genblk1_left_mult_x_1_n1204) );
AOI222XLTS U5697 ( .A0(n4764), .A1(Data_B_i[46]), .B0(n4726), .B1(n124),
.C0(n4729), .C1(n98), .Y(n4724) );
AOI222XLTS U5698 ( .A0(n4764), .A1(n123), .B0(n4726), .B1(Data_B_i[44]),
.C0(n4729), .C1(n95), .Y(n4727) );
AOI222XLTS U5699 ( .A0(n4740), .A1(n99), .B0(n4763), .B1(n94), .C0(n4729),
.C1(Data_B_i[42]), .Y(n4730) );
AOI222XLTS U5700 ( .A0(n4764), .A1(Data_B_i[43]), .B0(n4763), .B1(n90), .C0(
n4762), .C1(n86), .Y(n4732) );
XOR2X1TS U5701 ( .A(n4733), .B(n191), .Y(genblk1_left_mult_x_1_n1208) );
AOI222XLTS U5702 ( .A0(n4764), .A1(n91), .B0(n4763), .B1(n87), .C0(n4762),
.C1(n83), .Y(n4734) );
AOI222XLTS U5703 ( .A0(n4764), .A1(n85), .B0(n4763), .B1(n83), .C0(n4745),
.C1(n78), .Y(n4736) );
AOI222XLTS U5704 ( .A0(n4764), .A1(n82), .B0(n4750), .B1(n79), .C0(n4745),
.C1(n74), .Y(n4738) );
XOR2X1TS U5705 ( .A(n4739), .B(Data_A_i[41]), .Y(genblk1_left_mult_x_1_n1211) );
AOI222XLTS U5706 ( .A0(n4740), .A1(n79), .B0(n4750), .B1(n75), .C0(n4745),
.C1(Data_B_i[37]), .Y(n4741) );
AOI222XLTS U5707 ( .A0(n4753), .A1(Data_B_i[38]), .B0(n4750), .B1(n70), .C0(
n4745), .C1(n66), .Y(n4743) );
AOI222XLTS U5708 ( .A0(n4753), .A1(n70), .B0(n4750), .B1(n67), .C0(n4745),
.C1(n516), .Y(n4746) );
AOI222XLTS U5709 ( .A0(n4753), .A1(Data_B_i[36]), .B0(n4750), .B1(n4934),
.C0(n4762), .C1(n63), .Y(n4748) );
AOI222XLTS U5710 ( .A0(n4753), .A1(n63), .B0(n4750), .B1(n59), .C0(n4762),
.C1(n54), .Y(n4751) );
AOI222XLTS U5711 ( .A0(n4753), .A1(n58), .B0(n4763), .B1(Data_B_i[32]), .C0(
n4762), .C1(n4873), .Y(n4754) );
AOI222XLTS U5712 ( .A0(n4764), .A1(Data_B_i[32]), .B0(n4763), .B1(n4870),
.C0(n4762), .C1(n50), .Y(n4756) );
AOI222XLTS U5713 ( .A0(n4764), .A1(n4873), .B0(n4763), .B1(n51), .C0(n4762),
.C1(Data_B_i[29]), .Y(n4758) );
AOI222XLTS U5714 ( .A0(n4764), .A1(Data_B_i[30]), .B0(n4763), .B1(n46), .C0(
n4762), .C1(n4761), .Y(n4765) );
AOI21X1TS U5715 ( .A0(n4787), .A1(n118), .B0(n4768), .Y(n4769) );
AOI222XLTS U5716 ( .A0(n4799), .A1(n630), .B0(n4809), .B1(n119), .C0(n4787),
.C1(Data_B_i[49]), .Y(n4771) );
AOI222XLTS U5717 ( .A0(n4799), .A1(Data_B_i[50]), .B0(n4784), .B1(
Data_B_i[49]), .C0(n4787), .C1(n111), .Y(n4773) );
AOI222XLTS U5718 ( .A0(n4799), .A1(n115), .B0(n4784), .B1(n111), .C0(n4787),
.C1(Data_B_i[47]), .Y(n4775) );
AOI222XLTS U5719 ( .A0(n4799), .A1(n111), .B0(n4784), .B1(n107), .C0(n4787),
.C1(Data_B_i[46]), .Y(n4777) );
AOI222XLTS U5720 ( .A0(n4799), .A1(n107), .B0(n4784), .B1(n102), .C0(n4787),
.C1(n123), .Y(n4779) );
XOR2X1TS U5721 ( .A(n4781), .B(n188), .Y(genblk1_left_mult_x_1_n1233) );
AOI222XLTS U5722 ( .A0(n4796), .A1(n102), .B0(n4784), .B1(n122), .C0(n4787),
.C1(n98), .Y(n4782) );
AOI222XLTS U5723 ( .A0(n4796), .A1(n122), .B0(n4784), .B1(Data_B_i[44]),
.C0(n4787), .C1(n94), .Y(n4785) );
XOR2X1TS U5724 ( .A(n4786), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1235) );
AOI222XLTS U5725 ( .A0(n4799), .A1(n99), .B0(n4813), .B1(n94), .C0(n4787),
.C1(n91), .Y(n4788) );
AOI222XLTS U5726 ( .A0(n4796), .A1(n94), .B0(n4813), .B1(Data_B_i[42]), .C0(
n4812), .C1(n85), .Y(n4790) );
XOR2X1TS U5727 ( .A(n4791), .B(Data_A_i[38]), .Y(genblk1_left_mult_x_1_n1237) );
AOI222XLTS U5728 ( .A0(n4796), .A1(n90), .B0(n4813), .B1(n87), .C0(n4812),
.C1(n82), .Y(n4792) );
AOI222XLTS U5729 ( .A0(n4796), .A1(n86), .B0(n4813), .B1(Data_B_i[40]), .C0(
n4802), .C1(n79), .Y(n4794) );
AOI222XLTS U5730 ( .A0(n4796), .A1(n83), .B0(n4809), .B1(n78), .C0(n4802),
.C1(n73), .Y(n4797) );
AOI222XLTS U5731 ( .A0(n4799), .A1(n79), .B0(n4809), .B1(n75), .C0(n4802),
.C1(n69), .Y(n4800) );
AOI222XLTS U5732 ( .A0(n4814), .A1(n75), .B0(n4809), .B1(n70), .C0(n4802),
.C1(Data_B_i[36]), .Y(n4803) );
AOI222XLTS U5733 ( .A0(n4814), .A1(n67), .B0(n4809), .B1(n4934), .C0(n4812),
.C1(n62), .Y(n4805) );
AOI222XLTS U5734 ( .A0(n4814), .A1(n516), .B0(n4813), .B1(Data_B_i[34]),
.C0(n4812), .C1(n59), .Y(n4807) );
XOR2X1TS U5735 ( .A(n4808), .B(n188), .Y(genblk1_left_mult_x_1_n1245) );
AOI222XLTS U5736 ( .A0(n4814), .A1(n63), .B0(n4809), .B1(n58), .C0(n4812),
.C1(n53), .Y(n4810) );
AOI222XLTS U5737 ( .A0(n4814), .A1(n59), .B0(n4813), .B1(n55), .C0(n4812),
.C1(n4944), .Y(n4815) );
INVX2TS U5738 ( .A(n4820), .Y(n4841) );
AOI21X1TS U5739 ( .A0(n4841), .A1(Data_B_i[51]), .B0(n4864), .Y(n4821) );
AOI21X1TS U5740 ( .A0(n4841), .A1(n119), .B0(n4823), .Y(n4824) );
AOI222XLTS U5741 ( .A0(n4852), .A1(n630), .B0(n4864), .B1(n119), .C0(n4841),
.C1(Data_B_i[49]), .Y(n4826) );
AOI222XLTS U5742 ( .A0(n4852), .A1(Data_B_i[50]), .B0(n4838), .B1(n115),
.C0(n4841), .C1(Data_B_i[48]), .Y(n4828) );
AOI222XLTS U5743 ( .A0(n4852), .A1(Data_B_i[49]), .B0(n4838), .B1(n110),
.C0(n4841), .C1(n106), .Y(n4830) );
AOI222XLTS U5744 ( .A0(n4852), .A1(n110), .B0(n4838), .B1(n107), .C0(n4841),
.C1(n103), .Y(n4832) );
AOI222XLTS U5745 ( .A0(n4852), .A1(n106), .B0(n4838), .B1(n103), .C0(n4841),
.C1(n124), .Y(n4834) );
OAI21X1TS U5746 ( .A0(n4963), .A1(n4818), .B0(n4834), .Y(n4835) );
AOI222XLTS U5747 ( .A0(n4881), .A1(n102), .B0(n4838), .B1(n122), .C0(n4841),
.C1(n98), .Y(n4836) );
AOI222XLTS U5748 ( .A0(n4881), .A1(n124), .B0(n4838), .B1(n98), .C0(n4841),
.C1(Data_B_i[43]), .Y(n4839) );
AOI222XLTS U5749 ( .A0(n4852), .A1(Data_B_i[44]), .B0(n4880), .B1(
Data_B_i[43]), .C0(n4841), .C1(Data_B_i[42]), .Y(n4842) );
AOI222XLTS U5750 ( .A0(n4881), .A1(n94), .B0(n4880), .B1(n90), .C0(n4879),
.C1(n86), .Y(n4844) );
XOR2X1TS U5751 ( .A(n4845), .B(n184), .Y(genblk1_left_mult_x_1_n1266) );
AOI222XLTS U5752 ( .A0(n4881), .A1(n91), .B0(n4880), .B1(n86), .C0(n4879),
.C1(n83), .Y(n4846) );
AOI222XLTS U5753 ( .A0(n4881), .A1(n85), .B0(n4880), .B1(Data_B_i[40]), .C0(
n4858), .C1(n78), .Y(n4848) );
AOI222XLTS U5754 ( .A0(n4881), .A1(n82), .B0(n4864), .B1(Data_B_i[39]), .C0(
n4858), .C1(n74), .Y(n4850) );
AOI222XLTS U5755 ( .A0(n4852), .A1(n78), .B0(n4864), .B1(Data_B_i[38]), .C0(
n4858), .C1(Data_B_i[37]), .Y(n4853) );
XOR2X1TS U5756 ( .A(n4854), .B(Data_A_i[35]), .Y(genblk1_left_mult_x_1_n1270) );
AOI222XLTS U5757 ( .A0(n4867), .A1(n75), .B0(n4864), .B1(n71), .C0(n4879),
.C1(n66), .Y(n4855) );
AOI222XLTS U5758 ( .A0(n4867), .A1(n71), .B0(n4864), .B1(Data_B_i[36]), .C0(
n4858), .C1(n4857), .Y(n4859) );
AOI222XLTS U5759 ( .A0(n4867), .A1(n66), .B0(n4864), .B1(n4934), .C0(n4879),
.C1(Data_B_i[34]), .Y(n4862) );
AOI222XLTS U5760 ( .A0(n4881), .A1(Data_B_i[34]), .B0(n4864), .B1(
Data_B_i[33]), .C0(n4879), .C1(n54), .Y(n4865) );
AOI222XLTS U5761 ( .A0(n4867), .A1(Data_B_i[33]), .B0(n4880), .B1(n55), .C0(
n4879), .C1(n4944), .Y(n4868) );
XOR2X1TS U5762 ( .A(n4869), .B(n184), .Y(genblk1_left_mult_x_1_n1276) );
AOI222XLTS U5763 ( .A0(n4881), .A1(Data_B_i[32]), .B0(n4880), .B1(n4870),
.C0(n4879), .C1(n51), .Y(n4871) );
AOI222XLTS U5764 ( .A0(n4881), .A1(n4873), .B0(n4880), .B1(n50), .C0(n4879),
.C1(n47), .Y(n4874) );
AOI222XLTS U5765 ( .A0(n4881), .A1(Data_B_i[30]), .B0(n4880), .B1(n47), .C0(
n4879), .C1(n4878), .Y(n4882) );
INVX2TS U5766 ( .A(n4889), .Y(n4913) );
AOI21X1TS U5767 ( .A0(n4913), .A1(n40), .B0(n4940), .Y(n4890) );
AOI21X1TS U5768 ( .A0(n4913), .A1(n119), .B0(n4892), .Y(n4893) );
AOI222XLTS U5769 ( .A0(n4928), .A1(Data_B_i[51]), .B0(n4940), .B1(n118),
.C0(n4913), .C1(n114), .Y(n4895) );
AOI222XLTS U5770 ( .A0(n4928), .A1(n119), .B0(n4909), .B1(Data_B_i[49]),
.C0(n4913), .C1(Data_B_i[48]), .Y(n4897) );
OAI21X1TS U5771 ( .A0(n333), .A1(n4905), .B0(n4897), .Y(n4898) );
AOI222XLTS U5772 ( .A0(n4928), .A1(n115), .B0(n4909), .B1(n111), .C0(n4913),
.C1(n107), .Y(n4899) );
AOI222XLTS U5773 ( .A0(n4928), .A1(Data_B_i[48]), .B0(n4909), .B1(n107),
.C0(n4913), .C1(n102), .Y(n4902) );
AOI222XLTS U5774 ( .A0(n4928), .A1(n107), .B0(n4909), .B1(Data_B_i[46]),
.C0(n4913), .C1(n122), .Y(n4904) );
XOR2X1TS U5775 ( .A(n4906), .B(n179), .Y(genblk1_left_mult_x_1_n1291) );
AOI222XLTS U5776 ( .A0(n4925), .A1(n103), .B0(n4909), .B1(n124), .C0(n4913),
.C1(n99), .Y(n4907) );
AOI222XLTS U5777 ( .A0(n4925), .A1(n122), .B0(n4909), .B1(Data_B_i[44]),
.C0(n4913), .C1(Data_B_i[43]), .Y(n4910) );
XOR2X1TS U5778 ( .A(n4912), .B(n180), .Y(genblk1_left_mult_x_1_n1293) );
AOI222XLTS U5779 ( .A0(n4928), .A1(n97), .B0(n4946), .B1(n94), .C0(n4913),
.C1(n91), .Y(n4914) );
AOI222XLTS U5780 ( .A0(n4925), .A1(n95), .B0(n4946), .B1(n90), .C0(n4945),
.C1(n87), .Y(n4916) );
AOI222XLTS U5781 ( .A0(n4925), .A1(Data_B_i[42]), .B0(n4946), .B1(n86), .C0(
n4945), .C1(Data_B_i[40]), .Y(n4919) );
AOI222XLTS U5782 ( .A0(n4925), .A1(n85), .B0(n4946), .B1(n82), .C0(n4931),
.C1(n78), .Y(n4921) );
AOI222XLTS U5783 ( .A0(n4925), .A1(Data_B_i[40]), .B0(n4940), .B1(n77), .C0(
n4931), .C1(Data_B_i[38]), .Y(n4926) );
AOI222XLTS U5784 ( .A0(n4928), .A1(n79), .B0(n4940), .B1(n75), .C0(n4931),
.C1(Data_B_i[37]), .Y(n4929) );
AOI222XLTS U5785 ( .A0(n4947), .A1(Data_B_i[38]), .B0(n4940), .B1(n71), .C0(
n4931), .C1(n67), .Y(n4932) );
AOI222XLTS U5786 ( .A0(n4947), .A1(n66), .B0(n4940), .B1(n4934), .C0(n4945),
.C1(n62), .Y(n4935) );
AOI222XLTS U5787 ( .A0(n4947), .A1(n4185), .B0(n4946), .B1(Data_B_i[34]),
.C0(n4945), .C1(n58), .Y(n4938) );
AOI222XLTS U5788 ( .A0(n4947), .A1(Data_B_i[34]), .B0(n4940), .B1(n58), .C0(
n4945), .C1(n54), .Y(n4941) );
AOI222XLTS U5789 ( .A0(n4947), .A1(n57), .B0(n4946), .B1(Data_B_i[32]), .C0(
n4945), .C1(n4944), .Y(n4948) );
AOI21X1TS U5790 ( .A0(n4965), .A1(Data_B_i[51]), .B0(n4977), .Y(n4950) );
AOI222XLTS U5791 ( .A0(n4978), .A1(n40), .B0(n4977), .B1(Data_B_i[50]), .C0(
n4965), .C1(n115), .Y(n4953) );
AOI222XLTS U5792 ( .A0(n4978), .A1(n118), .B0(n4961), .B1(n114), .C0(n4965),
.C1(Data_B_i[48]), .Y(n4957) );
AOI222XLTS U5793 ( .A0(n4978), .A1(n106), .B0(n4961), .B1(n103), .C0(n4965),
.C1(n123), .Y(n4962) );
XOR2X1TS U5794 ( .A(n4964), .B(n4981), .Y(genblk1_left_mult_x_1_n1320) );
AOI222XLTS U5795 ( .A0(n4978), .A1(n99), .B0(n4969), .B1(n94), .C0(n4965),
.C1(n91), .Y(n4966) );
AOI222XLTS U5796 ( .A0(n4973), .A1(n91), .B0(n4969), .B1(n85), .C0(n4968),
.C1(Data_B_i[40]), .Y(n4970) );
AOI222XLTS U5797 ( .A0(n4973), .A1(n82), .B0(n4977), .B1(Data_B_i[39]), .C0(
n4976), .C1(n74), .Y(n4974) );
AOI222XLTS U5798 ( .A0(n4978), .A1(n79), .B0(n4977), .B1(Data_B_i[38]), .C0(
n4976), .C1(n71), .Y(n4979) );
XOR2X1TS U5799 ( .A(n4982), .B(n4981), .Y(genblk1_left_mult_x_1_n1328) );
CMPR42X1TS U5800 ( .A(genblk1_middle_mult_x_1_n1411), .B(
genblk1_middle_mult_x_1_n1439), .C(genblk1_middle_mult_x_1_n1383), .D(
genblk1_middle_mult_x_1_n1467), .ICI(genblk1_middle_mult_x_1_n786),
.S(genblk1_middle_mult_x_1_n779), .ICO(genblk1_middle_mult_x_1_n777),
.CO(genblk1_middle_mult_x_1_n778) );
CMPR42X1TS U5801 ( .A(genblk1_middle_mult_x_1_n1409), .B(
genblk1_middle_mult_x_1_n1381), .C(genblk1_middle_mult_x_1_n1437), .D(
genblk1_middle_mult_x_1_n1521), .ICI(genblk1_middle_mult_x_1_n762),
.S(genblk1_middle_mult_x_1_n755), .ICO(genblk1_middle_mult_x_1_n753),
.CO(genblk1_middle_mult_x_1_n754) );
CMPR42X1TS U5802 ( .A(genblk1_middle_mult_x_1_n1515), .B(
genblk1_middle_mult_x_1_n1543), .C(genblk1_middle_mult_x_1_n975), .D(
genblk1_middle_mult_x_1_n976), .ICI(genblk1_middle_mult_x_1_n1571),
.S(genblk1_middle_mult_x_1_n973), .ICO(genblk1_middle_mult_x_1_n971),
.CO(genblk1_middle_mult_x_1_n972) );
CMPR42X1TS U5803 ( .A(genblk1_right_mult_x_1_n913), .B(
genblk1_right_mult_x_1_n529), .C(genblk1_right_mult_x_1_n1254), .D(
genblk1_right_mult_x_1_n1227), .ICI(genblk1_right_mult_x_1_n526), .S(
genblk1_right_mult_x_1_n524), .ICO(genblk1_right_mult_x_1_n522), .CO(
genblk1_right_mult_x_1_n523) );
CMPR42X1TS U5804 ( .A(genblk1_right_mult_x_1_n621), .B(
genblk1_right_mult_x_1_n631), .C(genblk1_right_mult_x_1_n1267), .D(
genblk1_right_mult_x_1_n1240), .ICI(genblk1_right_mult_x_1_n1321), .S(
genblk1_right_mult_x_1_n620), .ICO(genblk1_right_mult_x_1_n618), .CO(
genblk1_right_mult_x_1_n619) );
CMPR42X1TS U5805 ( .A(genblk1_right_mult_x_1_n625), .B(
genblk1_right_mult_x_1_n629), .C(genblk1_right_mult_x_1_n626), .D(
genblk1_right_mult_x_1_n617), .ICI(genblk1_right_mult_x_1_n622), .S(
genblk1_right_mult_x_1_n614), .ICO(genblk1_right_mult_x_1_n612), .CO(
genblk1_right_mult_x_1_n613) );
CMPR42X1TS U5806 ( .A(genblk1_right_mult_x_1_n1258), .B(
genblk1_right_mult_x_1_n1231), .C(genblk1_right_mult_x_1_n545), .D(
genblk1_right_mult_x_1_n551), .ICI(genblk1_right_mult_x_1_n547), .S(
genblk1_right_mult_x_1_n543), .ICO(genblk1_right_mult_x_1_n541), .CO(
genblk1_right_mult_x_1_n542) );
CMPR42X1TS U5807 ( .A(n284), .B(genblk1_right_mult_x_1_n932), .C(
genblk1_right_mult_x_1_n1246), .D(genblk1_right_mult_x_1_n1273), .ICI(
genblk1_right_mult_x_1_n1327), .S(genblk1_right_mult_x_1_n692), .ICO(
genblk1_right_mult_x_1_n690), .CO(genblk1_right_mult_x_1_n691) );
CMPR42X1TS U5808 ( .A(n285), .B(genblk1_right_mult_x_1_n933), .C(
genblk1_right_mult_x_1_n1274), .D(genblk1_right_mult_x_1_n1247), .ICI(
genblk1_right_mult_x_1_n1328), .S(genblk1_right_mult_x_1_n704), .ICO(
genblk1_right_mult_x_1_n702), .CO(genblk1_right_mult_x_1_n703) );
CMPR42X1TS U5809 ( .A(genblk1_right_mult_x_1_n919), .B(
genblk1_right_mult_x_1_n566), .C(genblk1_right_mult_x_1_n1314), .D(
genblk1_right_mult_x_1_n1260), .ICI(genblk1_right_mult_x_1_n1287), .S(
genblk1_right_mult_x_1_n558), .ICO(genblk1_right_mult_x_1_n556), .CO(
genblk1_right_mult_x_1_n557) );
CMPR42X1TS U5810 ( .A(genblk1_right_mult_x_1_n1264), .B(
genblk1_right_mult_x_1_n596), .C(genblk1_right_mult_x_1_n597), .D(
genblk1_right_mult_x_1_n589), .ICI(genblk1_right_mult_x_1_n593), .S(
genblk1_right_mult_x_1_n586), .ICO(genblk1_right_mult_x_1_n584), .CO(
genblk1_right_mult_x_1_n585) );
CMPR42X1TS U5811 ( .A(genblk1_right_mult_x_1_n1349), .B(
genblk1_right_mult_x_1_n1322), .C(genblk1_right_mult_x_1_n642), .D(
genblk1_right_mult_x_1_n639), .ICI(genblk1_right_mult_x_1_n636), .S(
genblk1_right_mult_x_1_n627), .ICO(genblk1_right_mult_x_1_n625), .CO(
genblk1_right_mult_x_1_n626) );
CMPR42X1TS U5812 ( .A(genblk1_right_mult_x_1_n1380), .B(
genblk1_right_mult_x_1_n1353), .C(genblk1_right_mult_x_1_n687), .D(
genblk1_right_mult_x_1_n684), .ICI(genblk1_right_mult_x_1_n680), .S(
genblk1_right_mult_x_1_n674), .ICO(genblk1_right_mult_x_1_n672), .CO(
genblk1_right_mult_x_1_n673) );
CMPR42X1TS U5813 ( .A(genblk1_right_mult_x_1_n778), .B(
genblk1_right_mult_x_1_n1334), .C(genblk1_right_mult_x_1_n1307), .D(
genblk1_right_mult_x_1_n1388), .ICI(genblk1_right_mult_x_1_n782), .S(
genblk1_right_mult_x_1_n776), .ICO(genblk1_right_mult_x_1_n774), .CO(
genblk1_right_mult_x_1_n775) );
CMPR42X1TS U5814 ( .A(n285), .B(genblk1_right_mult_x_1_n931), .C(
genblk1_right_mult_x_1_n1299), .D(genblk1_right_mult_x_1_n1272), .ICI(
genblk1_right_mult_x_1_n1245), .S(genblk1_right_mult_x_1_n680), .ICO(
genblk1_right_mult_x_1_n678), .CO(genblk1_right_mult_x_1_n679) );
CMPR42X1TS U5815 ( .A(genblk1_left_mult_x_1_n596), .B(
genblk1_left_mult_x_1_n1102), .C(genblk1_left_mult_x_1_n1125), .D(
genblk1_left_mult_x_1_n1255), .ICI(genblk1_left_mult_x_1_n593), .S(
genblk1_left_mult_x_1_n584), .ICO(genblk1_left_mult_x_1_n582), .CO(
genblk1_left_mult_x_1_n583) );
CMPR42X1TS U5816 ( .A(genblk1_left_mult_x_1_n648), .B(
genblk1_left_mult_x_1_n638), .C(genblk1_left_mult_x_1_n645), .D(
genblk1_left_mult_x_1_n635), .ICI(genblk1_left_mult_x_1_n641), .S(
genblk1_left_mult_x_1_n632), .ICO(genblk1_left_mult_x_1_n630), .CO(
genblk1_left_mult_x_1_n631) );
CMPR42X1TS U5817 ( .A(genblk1_left_mult_x_1_n1148), .B(
genblk1_left_mult_x_1_n1200), .C(genblk1_left_mult_x_1_n1123), .D(
genblk1_left_mult_x_1_n1174), .ICI(genblk1_left_mult_x_1_n560), .S(
genblk1_left_mult_x_1_n552), .ICO(genblk1_left_mult_x_1_n550), .CO(
genblk1_left_mult_x_1_n551) );
CMPR42X1TS U5818 ( .A(genblk1_left_mult_x_1_n1210), .B(
genblk1_left_mult_x_1_n1314), .C(genblk1_left_mult_x_1_n1262), .D(
genblk1_left_mult_x_1_n672), .ICI(genblk1_left_mult_x_1_n666), .S(
genblk1_left_mult_x_1_n660), .ICO(genblk1_left_mult_x_1_n658), .CO(
genblk1_left_mult_x_1_n659) );
CMPR42X1TS U5819 ( .A(genblk1_left_mult_x_1_n741), .B(
genblk1_left_mult_x_1_n735), .C(genblk1_left_mult_x_1_n742), .D(
genblk1_left_mult_x_1_n738), .ICI(genblk1_left_mult_x_1_n733), .S(
genblk1_left_mult_x_1_n730), .ICO(genblk1_left_mult_x_1_n728), .CO(
genblk1_left_mult_x_1_n729) );
CMPR42X1TS U5820 ( .A(genblk1_left_mult_x_1_n1326), .B(
genblk1_left_mult_x_1_n782), .C(genblk1_left_mult_x_1_n1300), .D(
genblk1_left_mult_x_1_n776), .ICI(genblk1_left_mult_x_1_n779), .S(
genblk1_left_mult_x_1_n774), .ICO(genblk1_left_mult_x_1_n772), .CO(
genblk1_left_mult_x_1_n773) );
CMPR42X1TS U5821 ( .A(genblk1_left_mult_x_1_n538), .B(
genblk1_left_mult_x_1_n1198), .C(genblk1_left_mult_x_1_n1146), .D(
genblk1_left_mult_x_1_n545), .ICI(genblk1_left_mult_x_1_n1172), .S(
genblk1_left_mult_x_1_n537), .ICO(genblk1_left_mult_x_1_n535), .CO(
genblk1_left_mult_x_1_n536) );
CMPR42X1TS U5822 ( .A(n189), .B(genblk1_left_mult_x_1_n530), .C(
genblk1_left_mult_x_1_n1097), .D(genblk1_left_mult_x_1_n1144), .ICI(
genblk1_left_mult_x_1_n527), .S(genblk1_left_mult_x_1_n523), .ICO(
genblk1_left_mult_x_1_n521), .CO(genblk1_left_mult_x_1_n522) );
CMPR42X1TS U5823 ( .A(genblk1_left_mult_x_1_n1246), .B(
genblk1_left_mult_x_1_n767), .C(genblk1_left_mult_x_1_n764), .D(
genblk1_left_mult_x_1_n768), .ICI(genblk1_left_mult_x_1_n761), .S(
genblk1_left_mult_x_1_n758), .ICO(genblk1_left_mult_x_1_n756), .CO(
genblk1_left_mult_x_1_n757) );
CMPR42X1TS U5824 ( .A(genblk1_left_mult_x_1_n596), .B(
genblk1_left_mult_x_1_n1152), .C(genblk1_left_mult_x_1_n606), .D(
genblk1_left_mult_x_1_n1256), .ICI(genblk1_left_mult_x_1_n603), .S(
genblk1_left_mult_x_1_n595), .ICO(genblk1_left_mult_x_1_n593), .CO(
genblk1_left_mult_x_1_n594) );
CMPR42X1TS U5825 ( .A(genblk1_left_mult_x_1_n1181), .B(
genblk1_left_mult_x_1_n1285), .C(genblk1_left_mult_x_1_n1233), .D(
genblk1_left_mult_x_1_n629), .ICI(genblk1_left_mult_x_1_n636), .S(
genblk1_left_mult_x_1_n627), .ICO(genblk1_left_mult_x_1_n625), .CO(
genblk1_left_mult_x_1_n626) );
CMPR42X1TS U5826 ( .A(genblk1_left_mult_x_1_n1184), .B(
genblk1_left_mult_x_1_n1236), .C(genblk1_left_mult_x_1_n662), .D(
genblk1_left_mult_x_1_n669), .ICI(genblk1_left_mult_x_1_n1288), .S(
genblk1_left_mult_x_1_n657), .ICO(genblk1_left_mult_x_1_n655), .CO(
genblk1_left_mult_x_1_n656) );
CMPR42X1TS U5827 ( .A(genblk1_left_mult_x_1_n563), .B(
genblk1_left_mult_x_1_n554), .C(genblk1_left_mult_x_1_n561), .D(
genblk1_left_mult_x_1_n552), .ICI(genblk1_left_mult_x_1_n557), .S(
genblk1_left_mult_x_1_n549), .ICO(genblk1_left_mult_x_1_n547), .CO(
genblk1_left_mult_x_1_n548) );
CMPR42X1TS U5828 ( .A(genblk1_left_mult_x_1_n615), .B(
genblk1_left_mult_x_1_n605), .C(genblk1_left_mult_x_1_n612), .D(
genblk1_left_mult_x_1_n602), .ICI(genblk1_left_mult_x_1_n608), .S(
genblk1_left_mult_x_1_n599), .ICO(genblk1_left_mult_x_1_n597), .CO(
genblk1_left_mult_x_1_n598) );
CMPR42X1TS U5829 ( .A(genblk1_left_mult_x_1_n659), .B(
genblk1_left_mult_x_1_n649), .C(genblk1_left_mult_x_1_n656), .D(
genblk1_left_mult_x_1_n646), .ICI(genblk1_left_mult_x_1_n652), .S(
genblk1_left_mult_x_1_n643), .ICO(genblk1_left_mult_x_1_n641), .CO(
genblk1_left_mult_x_1_n642) );
CMPR42X1TS U5830 ( .A(genblk1_left_mult_x_1_n1290), .B(
genblk1_left_mult_x_1_n682), .C(genblk1_left_mult_x_1_n689), .D(
genblk1_left_mult_x_1_n679), .ICI(genblk1_left_mult_x_1_n685), .S(
genblk1_left_mult_x_1_n676), .ICO(genblk1_left_mult_x_1_n674), .CO(
genblk1_left_mult_x_1_n675) );
CMPR42X1TS U5831 ( .A(genblk1_left_mult_x_1_n1319), .B(
genblk1_left_mult_x_1_n715), .C(genblk1_left_mult_x_1_n722), .D(
genblk1_left_mult_x_1_n712), .ICI(genblk1_left_mult_x_1_n718), .S(
genblk1_left_mult_x_1_n709), .ICO(genblk1_left_mult_x_1_n707), .CO(
genblk1_left_mult_x_1_n708) );
CMPR42X1TS U5832 ( .A(genblk1_left_mult_x_1_n1317), .B(
genblk1_left_mult_x_1_n703), .C(genblk1_left_mult_x_1_n700), .D(
genblk1_left_mult_x_1_n690), .ICI(genblk1_left_mult_x_1_n696), .S(
genblk1_left_mult_x_1_n687), .ICO(genblk1_left_mult_x_1_n685), .CO(
genblk1_left_mult_x_1_n686) );
CMPR42X1TS U5833 ( .A(genblk1_left_mult_x_1_n1204), .B(
genblk1_left_mult_x_1_n1126), .C(genblk1_left_mult_x_1_n1178), .D(
genblk1_left_mult_x_1_n1230), .ICI(genblk1_left_mult_x_1_n600), .S(
genblk1_left_mult_x_1_n592), .ICO(genblk1_left_mult_x_1_n590), .CO(
genblk1_left_mult_x_1_n591) );
CMPR42X1TS U5834 ( .A(genblk1_left_mult_x_1_n639), .B(
genblk1_left_mult_x_1_n1155), .C(genblk1_left_mult_x_1_n1207), .D(
genblk1_left_mult_x_1_n1259), .ICI(genblk1_left_mult_x_1_n633), .S(
genblk1_left_mult_x_1_n624), .ICO(genblk1_left_mult_x_1_n622), .CO(
genblk1_left_mult_x_1_n623) );
CMPR42X1TS U5835 ( .A(n181), .B(genblk1_left_mult_x_1_n585), .C(
genblk1_left_mult_x_1_n1101), .D(genblk1_left_mult_x_1_n1150), .ICI(
genblk1_left_mult_x_1_n1202), .S(genblk1_left_mult_x_1_n575), .ICO(
genblk1_left_mult_x_1_n573), .CO(genblk1_left_mult_x_1_n574) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module shift_mux_array_SWR53_LEVEL0 ( Data_i, select_i, bit_shift_i, Data_o );
input [52:0] Data_i;
output [52:0] Data_o;
input select_i, bit_shift_i;
Multiplexer_AC genblk1_0__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[0]), .D1(Data_i[1]), .S(Data_o[0]) );
Multiplexer_AC genblk1_1__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[1]), .D1(Data_i[2]), .S(Data_o[1]) );
Multiplexer_AC genblk1_2__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[2]), .D1(Data_i[3]), .S(Data_o[2]) );
Multiplexer_AC genblk1_3__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[3]), .D1(Data_i[4]), .S(Data_o[3]) );
Multiplexer_AC genblk1_4__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[4]), .D1(Data_i[5]), .S(Data_o[4]) );
Multiplexer_AC genblk1_5__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[5]), .D1(Data_i[6]), .S(Data_o[5]) );
Multiplexer_AC genblk1_6__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[6]), .D1(Data_i[7]), .S(Data_o[6]) );
Multiplexer_AC genblk1_7__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[7]), .D1(Data_i[8]), .S(Data_o[7]) );
Multiplexer_AC genblk1_8__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[8]), .D1(Data_i[9]), .S(Data_o[8]) );
Multiplexer_AC genblk1_9__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[9]), .D1(Data_i[10]), .S(Data_o[9]) );
Multiplexer_AC genblk1_10__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[10]), .D1(Data_i[11]), .S(Data_o[10]) );
Multiplexer_AC genblk1_11__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[11]), .D1(Data_i[12]), .S(Data_o[11]) );
Multiplexer_AC genblk1_12__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[12]), .D1(Data_i[13]), .S(Data_o[12]) );
Multiplexer_AC genblk1_13__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[13]), .D1(Data_i[14]), .S(Data_o[13]) );
Multiplexer_AC genblk1_14__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[14]), .D1(Data_i[15]), .S(Data_o[14]) );
Multiplexer_AC genblk1_15__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[15]), .D1(Data_i[16]), .S(Data_o[15]) );
Multiplexer_AC genblk1_16__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[16]), .D1(Data_i[17]), .S(Data_o[16]) );
Multiplexer_AC genblk1_17__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[17]), .D1(Data_i[18]), .S(Data_o[17]) );
Multiplexer_AC genblk1_18__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[18]), .D1(Data_i[19]), .S(Data_o[18]) );
Multiplexer_AC genblk1_19__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[19]), .D1(Data_i[20]), .S(Data_o[19]) );
Multiplexer_AC genblk1_20__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[20]), .D1(Data_i[21]), .S(Data_o[20]) );
Multiplexer_AC genblk1_21__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[21]), .D1(Data_i[22]), .S(Data_o[21]) );
Multiplexer_AC genblk1_22__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[22]), .D1(Data_i[23]), .S(Data_o[22]) );
Multiplexer_AC genblk1_23__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[23]), .D1(Data_i[24]), .S(Data_o[23]) );
Multiplexer_AC genblk1_24__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[24]), .D1(Data_i[25]), .S(Data_o[24]) );
Multiplexer_AC genblk1_25__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[25]), .D1(Data_i[26]), .S(Data_o[25]) );
Multiplexer_AC genblk1_26__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[26]), .D1(Data_i[27]), .S(Data_o[26]) );
Multiplexer_AC genblk1_27__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[27]), .D1(Data_i[28]), .S(Data_o[27]) );
Multiplexer_AC genblk1_28__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[28]), .D1(Data_i[29]), .S(Data_o[28]) );
Multiplexer_AC genblk1_29__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[29]), .D1(Data_i[30]), .S(Data_o[29]) );
Multiplexer_AC genblk1_30__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[30]), .D1(Data_i[31]), .S(Data_o[30]) );
Multiplexer_AC genblk1_31__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[31]), .D1(Data_i[32]), .S(Data_o[31]) );
Multiplexer_AC genblk1_32__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[32]), .D1(Data_i[33]), .S(Data_o[32]) );
Multiplexer_AC genblk1_33__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[33]), .D1(Data_i[34]), .S(Data_o[33]) );
Multiplexer_AC genblk1_34__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[34]), .D1(Data_i[35]), .S(Data_o[34]) );
Multiplexer_AC genblk1_35__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[35]), .D1(Data_i[36]), .S(Data_o[35]) );
Multiplexer_AC genblk1_36__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[36]), .D1(Data_i[37]), .S(Data_o[36]) );
Multiplexer_AC genblk1_37__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[37]), .D1(Data_i[38]), .S(Data_o[37]) );
Multiplexer_AC genblk1_38__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[38]), .D1(Data_i[39]), .S(Data_o[38]) );
Multiplexer_AC genblk1_39__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[39]), .D1(Data_i[40]), .S(Data_o[39]) );
Multiplexer_AC genblk1_40__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[40]), .D1(Data_i[41]), .S(Data_o[40]) );
Multiplexer_AC genblk1_41__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[41]), .D1(Data_i[42]), .S(Data_o[41]) );
Multiplexer_AC genblk1_42__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[42]), .D1(Data_i[43]), .S(Data_o[42]) );
Multiplexer_AC genblk1_43__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[43]), .D1(Data_i[44]), .S(Data_o[43]) );
Multiplexer_AC genblk1_44__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[44]), .D1(Data_i[45]), .S(Data_o[44]) );
Multiplexer_AC genblk1_45__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[45]), .D1(Data_i[46]), .S(Data_o[45]) );
Multiplexer_AC genblk1_46__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[46]), .D1(Data_i[47]), .S(Data_o[46]) );
Multiplexer_AC genblk1_47__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[47]), .D1(Data_i[48]), .S(Data_o[47]) );
Multiplexer_AC genblk1_48__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[48]), .D1(Data_i[49]), .S(Data_o[48]) );
Multiplexer_AC genblk1_49__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[49]), .D1(Data_i[50]), .S(Data_o[49]) );
Multiplexer_AC genblk1_50__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[50]), .D1(Data_i[51]), .S(Data_o[50]) );
Multiplexer_AC genblk1_51__BLK2ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[51]), .D1(Data_i[52]), .S(Data_o[51]) );
Multiplexer_AC genblk1_52__BLK1ROT_rotate_mux ( .ctrl(select_i), .D0(
Data_i[52]), .D1(1'b1), .S(Data_o[52]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module Barrel_Shifter_M_SW53 ( clk, rst, load_i, Shift_Value_i, Shift_Data_i,
N_mant_o );
input [52:0] Shift_Data_i;
output [52:0] N_mant_o;
input clk, rst, load_i, Shift_Value_i;
wire n2, n3, n5, n7, n9, n11, n13, n15, n17, n19, n21, n23, n25, n27, n29,
n31, n33, n35, n37, n39, n41, n43, n45, n47, n49, n51, n53, n55, n57,
n59, n61, n63, n65, n67, n69, n71, n73, n75, n77, n79, n81, n83, n85,
n87, n89, n91, n93, n95, n97, n99, n101, n103, n105, n107, n1, n4, n6,
n8, n10, n12, n14, n16, n18, n20, n22, n24, n26, n28, n30, n32, n34;
wire [52:0] Data_Reg;
shift_mux_array_SWR53_LEVEL0 shift_mux_array ( .Data_i(Shift_Data_i),
.select_i(Shift_Value_i), .bit_shift_i(1'b1), .Data_o(Data_Reg) );
DFFRXLTS Output_Reg_Q_reg_52_ ( .D(n3), .CK(clk), .RN(n34), .Q(N_mant_o[52])
);
DFFRXLTS Output_Reg_Q_reg_0_ ( .D(n107), .CK(clk), .RN(n26), .Q(N_mant_o[0])
);
DFFRXLTS Output_Reg_Q_reg_1_ ( .D(n105), .CK(clk), .RN(n26), .Q(N_mant_o[1])
);
DFFRXLTS Output_Reg_Q_reg_6_ ( .D(n95), .CK(clk), .RN(n26), .Q(N_mant_o[6])
);
DFFRXLTS Output_Reg_Q_reg_8_ ( .D(n91), .CK(clk), .RN(n26), .Q(N_mant_o[8])
);
DFFRXLTS Output_Reg_Q_reg_10_ ( .D(n87), .CK(clk), .RN(n28), .Q(N_mant_o[10]) );
DFFRXLTS Output_Reg_Q_reg_12_ ( .D(n83), .CK(clk), .RN(n28), .Q(N_mant_o[12]) );
DFFRXLTS Output_Reg_Q_reg_14_ ( .D(n79), .CK(clk), .RN(n28), .Q(N_mant_o[14]) );
DFFRXLTS Output_Reg_Q_reg_16_ ( .D(n75), .CK(clk), .RN(n28), .Q(N_mant_o[16]) );
DFFRXLTS Output_Reg_Q_reg_18_ ( .D(n71), .CK(clk), .RN(n28), .Q(N_mant_o[18]) );
DFFRXLTS Output_Reg_Q_reg_20_ ( .D(n67), .CK(clk), .RN(n30), .Q(N_mant_o[20]) );
DFFRXLTS Output_Reg_Q_reg_22_ ( .D(n63), .CK(clk), .RN(n30), .Q(N_mant_o[22]) );
DFFRXLTS Output_Reg_Q_reg_24_ ( .D(n59), .CK(clk), .RN(n30), .Q(N_mant_o[24]) );
DFFRXLTS Output_Reg_Q_reg_26_ ( .D(n55), .CK(clk), .RN(n30), .Q(N_mant_o[26]) );
DFFRXLTS Output_Reg_Q_reg_28_ ( .D(n51), .CK(clk), .RN(n30), .Q(N_mant_o[28]) );
DFFRXLTS Output_Reg_Q_reg_30_ ( .D(n47), .CK(clk), .RN(n32), .Q(N_mant_o[30]) );
DFFRXLTS Output_Reg_Q_reg_32_ ( .D(n43), .CK(clk), .RN(n32), .Q(N_mant_o[32]) );
DFFRXLTS Output_Reg_Q_reg_34_ ( .D(n39), .CK(clk), .RN(n32), .Q(N_mant_o[34]) );
DFFRXLTS Output_Reg_Q_reg_36_ ( .D(n35), .CK(clk), .RN(n32), .Q(N_mant_o[36]) );
DFFRXLTS Output_Reg_Q_reg_38_ ( .D(n31), .CK(clk), .RN(n32), .Q(N_mant_o[38]) );
DFFRXLTS Output_Reg_Q_reg_40_ ( .D(n27), .CK(clk), .RN(n2), .Q(N_mant_o[40])
);
DFFRXLTS Output_Reg_Q_reg_42_ ( .D(n23), .CK(clk), .RN(n2), .Q(N_mant_o[42])
);
DFFRXLTS Output_Reg_Q_reg_44_ ( .D(n19), .CK(clk), .RN(n34), .Q(N_mant_o[44]) );
DFFRXLTS Output_Reg_Q_reg_46_ ( .D(n15), .CK(clk), .RN(n34), .Q(N_mant_o[46]) );
DFFRXLTS Output_Reg_Q_reg_48_ ( .D(n11), .CK(clk), .RN(n34), .Q(N_mant_o[48]) );
DFFRXLTS Output_Reg_Q_reg_50_ ( .D(n7), .CK(clk), .RN(n34), .Q(N_mant_o[50])
);
DFFRXLTS Output_Reg_Q_reg_4_ ( .D(n99), .CK(clk), .RN(n26), .Q(N_mant_o[4])
);
DFFRXLTS Output_Reg_Q_reg_7_ ( .D(n93), .CK(clk), .RN(n26), .Q(N_mant_o[7])
);
DFFRXLTS Output_Reg_Q_reg_9_ ( .D(n89), .CK(clk), .RN(n26), .Q(N_mant_o[9])
);
DFFRXLTS Output_Reg_Q_reg_11_ ( .D(n85), .CK(clk), .RN(n28), .Q(N_mant_o[11]) );
DFFRXLTS Output_Reg_Q_reg_13_ ( .D(n81), .CK(clk), .RN(n28), .Q(N_mant_o[13]) );
DFFRXLTS Output_Reg_Q_reg_15_ ( .D(n77), .CK(clk), .RN(n28), .Q(N_mant_o[15]) );
DFFRXLTS Output_Reg_Q_reg_17_ ( .D(n73), .CK(clk), .RN(n28), .Q(N_mant_o[17]) );
DFFRXLTS Output_Reg_Q_reg_19_ ( .D(n69), .CK(clk), .RN(n28), .Q(N_mant_o[19]) );
DFFRXLTS Output_Reg_Q_reg_21_ ( .D(n65), .CK(clk), .RN(n30), .Q(N_mant_o[21]) );
DFFRXLTS Output_Reg_Q_reg_23_ ( .D(n61), .CK(clk), .RN(n30), .Q(N_mant_o[23]) );
DFFRXLTS Output_Reg_Q_reg_25_ ( .D(n57), .CK(clk), .RN(n30), .Q(N_mant_o[25]) );
DFFRXLTS Output_Reg_Q_reg_27_ ( .D(n53), .CK(clk), .RN(n30), .Q(N_mant_o[27]) );
DFFRXLTS Output_Reg_Q_reg_29_ ( .D(n49), .CK(clk), .RN(n30), .Q(N_mant_o[29]) );
DFFRXLTS Output_Reg_Q_reg_31_ ( .D(n45), .CK(clk), .RN(n32), .Q(N_mant_o[31]) );
DFFRXLTS Output_Reg_Q_reg_33_ ( .D(n41), .CK(clk), .RN(n32), .Q(N_mant_o[33]) );
DFFRXLTS Output_Reg_Q_reg_35_ ( .D(n37), .CK(clk), .RN(n32), .Q(N_mant_o[35]) );
DFFRXLTS Output_Reg_Q_reg_37_ ( .D(n33), .CK(clk), .RN(n32), .Q(N_mant_o[37]) );
DFFRXLTS Output_Reg_Q_reg_39_ ( .D(n29), .CK(clk), .RN(n32), .Q(N_mant_o[39]) );
DFFRXLTS Output_Reg_Q_reg_41_ ( .D(n25), .CK(clk), .RN(n2), .Q(N_mant_o[41])
);
DFFRXLTS Output_Reg_Q_reg_43_ ( .D(n21), .CK(clk), .RN(n34), .Q(N_mant_o[43]) );
DFFRXLTS Output_Reg_Q_reg_45_ ( .D(n17), .CK(clk), .RN(n34), .Q(N_mant_o[45]) );
DFFRXLTS Output_Reg_Q_reg_47_ ( .D(n13), .CK(clk), .RN(n34), .Q(N_mant_o[47]) );
DFFRXLTS Output_Reg_Q_reg_49_ ( .D(n9), .CK(clk), .RN(n34), .Q(N_mant_o[49])
);
DFFRXLTS Output_Reg_Q_reg_51_ ( .D(n5), .CK(clk), .RN(n34), .Q(N_mant_o[51])
);
DFFRXLTS Output_Reg_Q_reg_5_ ( .D(n97), .CK(clk), .RN(n26), .Q(N_mant_o[5])
);
DFFRXLTS Output_Reg_Q_reg_3_ ( .D(n101), .CK(clk), .RN(n26), .Q(N_mant_o[3])
);
DFFRXLTS Output_Reg_Q_reg_2_ ( .D(n103), .CK(clk), .RN(n26), .Q(N_mant_o[2])
);
INVX2TS U2 ( .A(rst), .Y(n2) );
CLKBUFX2TS U3 ( .A(n2), .Y(n28) );
CLKBUFX2TS U4 ( .A(n2), .Y(n32) );
CLKBUFX2TS U5 ( .A(n2), .Y(n30) );
CLKBUFX2TS U6 ( .A(n2), .Y(n34) );
CLKBUFX2TS U7 ( .A(n2), .Y(n26) );
INVX2TS U8 ( .A(load_i), .Y(n4) );
CLKBUFX2TS U9 ( .A(n4), .Y(n22) );
CLKBUFX2TS U10 ( .A(n4), .Y(n20) );
AO22XLTS U11 ( .A0(n24), .A1(Data_Reg[0]), .B0(n20), .B1(N_mant_o[0]), .Y(
n107) );
AO22XLTS U12 ( .A0(n24), .A1(Data_Reg[1]), .B0(n20), .B1(N_mant_o[1]), .Y(
n105) );
AO22XLTS U13 ( .A0(n24), .A1(Data_Reg[2]), .B0(n20), .B1(N_mant_o[2]), .Y(
n103) );
AO22XLTS U14 ( .A0(n24), .A1(Data_Reg[3]), .B0(n20), .B1(N_mant_o[3]), .Y(
n101) );
AO22XLTS U15 ( .A0(n24), .A1(Data_Reg[4]), .B0(n20), .B1(N_mant_o[4]), .Y(
n99) );
AO22XLTS U16 ( .A0(n24), .A1(Data_Reg[5]), .B0(n20), .B1(N_mant_o[5]), .Y(
n97) );
AO22XLTS U17 ( .A0(n24), .A1(Data_Reg[6]), .B0(n20), .B1(N_mant_o[6]), .Y(
n95) );
AO22XLTS U18 ( .A0(load_i), .A1(Data_Reg[7]), .B0(n20), .B1(N_mant_o[7]),
.Y(n93) );
AO22XLTS U19 ( .A0(load_i), .A1(Data_Reg[8]), .B0(n20), .B1(N_mant_o[8]),
.Y(n91) );
CLKBUFX2TS U20 ( .A(n4), .Y(n14) );
AO22XLTS U21 ( .A0(load_i), .A1(Data_Reg[9]), .B0(n14), .B1(N_mant_o[9]),
.Y(n89) );
CLKBUFX2TS U22 ( .A(n4), .Y(n16) );
INVX2TS U23 ( .A(n16), .Y(n1) );
AO22XLTS U24 ( .A0(n1), .A1(Data_Reg[10]), .B0(n14), .B1(N_mant_o[10]), .Y(
n87) );
AO22XLTS U25 ( .A0(n1), .A1(Data_Reg[11]), .B0(n14), .B1(N_mant_o[11]), .Y(
n85) );
AO22XLTS U26 ( .A0(n1), .A1(Data_Reg[12]), .B0(n14), .B1(N_mant_o[12]), .Y(
n83) );
AO22XLTS U27 ( .A0(n1), .A1(Data_Reg[13]), .B0(n14), .B1(N_mant_o[13]), .Y(
n81) );
AO22XLTS U28 ( .A0(n1), .A1(Data_Reg[14]), .B0(n14), .B1(N_mant_o[14]), .Y(
n79) );
AO22XLTS U29 ( .A0(n1), .A1(Data_Reg[15]), .B0(n14), .B1(N_mant_o[15]), .Y(
n77) );
AO22XLTS U30 ( .A0(n1), .A1(Data_Reg[16]), .B0(n14), .B1(N_mant_o[16]), .Y(
n75) );
AO22XLTS U31 ( .A0(n1), .A1(Data_Reg[17]), .B0(n14), .B1(N_mant_o[17]), .Y(
n73) );
CLKBUFX2TS U32 ( .A(n4), .Y(n8) );
AO22XLTS U33 ( .A0(n1), .A1(Data_Reg[18]), .B0(n8), .B1(N_mant_o[18]), .Y(
n71) );
AO22XLTS U34 ( .A0(n1), .A1(Data_Reg[19]), .B0(n8), .B1(N_mant_o[19]), .Y(
n69) );
CLKBUFX2TS U35 ( .A(n4), .Y(n10) );
INVX2TS U36 ( .A(n10), .Y(n6) );
AO22XLTS U37 ( .A0(n6), .A1(Data_Reg[20]), .B0(n8), .B1(N_mant_o[20]), .Y(
n67) );
AO22XLTS U38 ( .A0(n6), .A1(Data_Reg[21]), .B0(n8), .B1(N_mant_o[21]), .Y(
n65) );
AO22XLTS U39 ( .A0(n6), .A1(Data_Reg[22]), .B0(n8), .B1(N_mant_o[22]), .Y(
n63) );
AO22XLTS U40 ( .A0(n6), .A1(Data_Reg[23]), .B0(n8), .B1(N_mant_o[23]), .Y(
n61) );
AO22XLTS U41 ( .A0(n6), .A1(Data_Reg[24]), .B0(n8), .B1(N_mant_o[24]), .Y(
n59) );
AO22XLTS U42 ( .A0(n6), .A1(Data_Reg[25]), .B0(n8), .B1(N_mant_o[25]), .Y(
n57) );
AO22XLTS U43 ( .A0(n6), .A1(Data_Reg[26]), .B0(n8), .B1(N_mant_o[26]), .Y(
n55) );
AO22XLTS U44 ( .A0(n6), .A1(Data_Reg[27]), .B0(n10), .B1(N_mant_o[27]), .Y(
n53) );
AO22XLTS U45 ( .A0(n6), .A1(Data_Reg[28]), .B0(n10), .B1(N_mant_o[28]), .Y(
n51) );
AO22XLTS U46 ( .A0(n6), .A1(Data_Reg[29]), .B0(n10), .B1(N_mant_o[29]), .Y(
n49) );
INVX2TS U47 ( .A(n8), .Y(n12) );
AO22XLTS U48 ( .A0(n12), .A1(Data_Reg[30]), .B0(n10), .B1(N_mant_o[30]), .Y(
n47) );
AO22XLTS U49 ( .A0(n12), .A1(Data_Reg[31]), .B0(n10), .B1(N_mant_o[31]), .Y(
n45) );
AO22XLTS U50 ( .A0(n12), .A1(Data_Reg[32]), .B0(n10), .B1(N_mant_o[32]), .Y(
n43) );
AO22XLTS U51 ( .A0(n12), .A1(Data_Reg[33]), .B0(n10), .B1(N_mant_o[33]), .Y(
n41) );
AO22XLTS U52 ( .A0(n12), .A1(Data_Reg[34]), .B0(n10), .B1(N_mant_o[34]), .Y(
n39) );
AO22XLTS U53 ( .A0(n12), .A1(Data_Reg[35]), .B0(n10), .B1(N_mant_o[35]), .Y(
n37) );
AO22XLTS U54 ( .A0(n12), .A1(Data_Reg[36]), .B0(n16), .B1(N_mant_o[36]), .Y(
n35) );
AO22XLTS U55 ( .A0(n12), .A1(Data_Reg[37]), .B0(n16), .B1(N_mant_o[37]), .Y(
n33) );
AO22XLTS U56 ( .A0(n12), .A1(Data_Reg[38]), .B0(n16), .B1(N_mant_o[38]), .Y(
n31) );
AO22XLTS U57 ( .A0(n12), .A1(Data_Reg[39]), .B0(n16), .B1(N_mant_o[39]), .Y(
n29) );
INVX2TS U58 ( .A(n14), .Y(n18) );
AO22XLTS U59 ( .A0(n18), .A1(Data_Reg[40]), .B0(n16), .B1(N_mant_o[40]), .Y(
n27) );
AO22XLTS U60 ( .A0(n18), .A1(Data_Reg[41]), .B0(n16), .B1(N_mant_o[41]), .Y(
n25) );
AO22XLTS U61 ( .A0(n18), .A1(Data_Reg[42]), .B0(n16), .B1(N_mant_o[42]), .Y(
n23) );
AO22XLTS U62 ( .A0(n18), .A1(Data_Reg[43]), .B0(n16), .B1(N_mant_o[43]), .Y(
n21) );
AO22XLTS U63 ( .A0(n18), .A1(Data_Reg[44]), .B0(n16), .B1(N_mant_o[44]), .Y(
n19) );
AO22XLTS U64 ( .A0(n18), .A1(Data_Reg[45]), .B0(n22), .B1(N_mant_o[45]), .Y(
n17) );
AO22XLTS U65 ( .A0(n18), .A1(Data_Reg[46]), .B0(n22), .B1(N_mant_o[46]), .Y(
n15) );
AO22XLTS U66 ( .A0(n18), .A1(Data_Reg[47]), .B0(n22), .B1(N_mant_o[47]), .Y(
n13) );
AO22XLTS U67 ( .A0(n18), .A1(Data_Reg[48]), .B0(n22), .B1(N_mant_o[48]), .Y(
n11) );
AO22XLTS U68 ( .A0(n18), .A1(Data_Reg[49]), .B0(n22), .B1(N_mant_o[49]), .Y(
n9) );
INVX2TS U69 ( .A(n20), .Y(n24) );
AO22XLTS U70 ( .A0(n24), .A1(Data_Reg[50]), .B0(n22), .B1(N_mant_o[50]), .Y(
n7) );
AO22XLTS U71 ( .A0(n24), .A1(Data_Reg[51]), .B0(n22), .B1(N_mant_o[51]), .Y(
n5) );
AO22XLTS U72 ( .A0(n24), .A1(Data_Reg[52]), .B0(n22), .B1(N_mant_o[52]), .Y(
n3) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module adder_W53 ( Data_A_i, Data_B_i, Data_S_o );
input [52:0] Data_A_i;
input [52:0] Data_B_i;
output [53:0] Data_S_o;
wire n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65, n66, n67,
n68, n69, n70, n71, n72, n73, n74, n75, n76, n77, n78, n79, n80, n81,
n82, n83, n84, n85, n86, n87, n88, n89, n90, n91, n92, n93, n94, n95,
n96, n97, n98, n99, n100, n101, n102, n103, n104, n105, n106, n107,
n108, n109, n110, n111, n112, n113, n114, n115, n116, n117, n118,
n119, n120, n121, n122, n123, n124, n125, n126;
assign Data_S_o[1] = Data_A_i[1];
assign Data_S_o[0] = Data_A_i[0];
AO21XLTS U1 ( .A0(Data_A_i[2]), .A1(Data_A_i[3]), .B0(Data_A_i[4]), .Y(n126)
);
NOR2XLTS U2 ( .A(Data_A_i[5]), .B(n126), .Y(n125) );
INVX2TS U3 ( .A(Data_A_i[6]), .Y(n123) );
NOR2XLTS U4 ( .A(n123), .B(n125), .Y(n122) );
INVX2TS U5 ( .A(Data_A_i[8]), .Y(n120) );
NOR2XLTS U6 ( .A(n120), .B(n121), .Y(n119) );
INVX2TS U7 ( .A(Data_A_i[10]), .Y(n117) );
NOR2XLTS U8 ( .A(n117), .B(n118), .Y(n116) );
INVX2TS U9 ( .A(Data_A_i[12]), .Y(n114) );
NOR2XLTS U10 ( .A(n114), .B(n115), .Y(n113) );
INVX2TS U11 ( .A(Data_A_i[14]), .Y(n111) );
INVX2TS U12 ( .A(Data_A_i[16]), .Y(n108) );
NOR2XLTS U13 ( .A(n108), .B(n109), .Y(n107) );
INVX2TS U14 ( .A(Data_A_i[18]), .Y(n105) );
NOR2XLTS U15 ( .A(n105), .B(n106), .Y(n104) );
INVX2TS U16 ( .A(Data_A_i[20]), .Y(n102) );
NOR2XLTS U17 ( .A(n102), .B(n103), .Y(n101) );
INVX2TS U18 ( .A(Data_A_i[22]), .Y(n99) );
NOR2XLTS U19 ( .A(n99), .B(n100), .Y(n98) );
INVX2TS U20 ( .A(Data_A_i[24]), .Y(n96) );
INVX2TS U21 ( .A(Data_A_i[26]), .Y(n93) );
NOR2XLTS U22 ( .A(n93), .B(n94), .Y(n92) );
INVX2TS U23 ( .A(Data_A_i[28]), .Y(n90) );
NOR2XLTS U24 ( .A(n90), .B(n91), .Y(n89) );
INVX2TS U25 ( .A(Data_A_i[30]), .Y(n87) );
NOR2XLTS U26 ( .A(n87), .B(n88), .Y(n86) );
INVX2TS U27 ( .A(Data_A_i[32]), .Y(n84) );
NOR2XLTS U28 ( .A(n84), .B(n85), .Y(n83) );
INVX2TS U29 ( .A(Data_A_i[34]), .Y(n81) );
INVX2TS U30 ( .A(Data_A_i[36]), .Y(n78) );
NOR2XLTS U31 ( .A(n78), .B(n79), .Y(n77) );
INVX2TS U32 ( .A(Data_A_i[38]), .Y(n75) );
NOR2XLTS U33 ( .A(n75), .B(n76), .Y(n74) );
INVX2TS U34 ( .A(Data_A_i[40]), .Y(n72) );
NOR2XLTS U35 ( .A(n72), .B(n73), .Y(n71) );
INVX2TS U36 ( .A(Data_A_i[42]), .Y(n69) );
NOR2XLTS U37 ( .A(n69), .B(n70), .Y(n68) );
INVX2TS U38 ( .A(Data_A_i[44]), .Y(n66) );
INVX2TS U39 ( .A(Data_A_i[46]), .Y(n63) );
NOR2XLTS U40 ( .A(n63), .B(n64), .Y(n62) );
INVX2TS U41 ( .A(Data_A_i[48]), .Y(n60) );
NOR2XLTS U42 ( .A(n60), .B(n61), .Y(n59) );
INVX2TS U43 ( .A(Data_A_i[50]), .Y(n57) );
NOR2XLTS U44 ( .A(n57), .B(n58), .Y(n56) );
INVX2TS U45 ( .A(Data_A_i[52]), .Y(n54) );
NOR2XLTS U46 ( .A(n111), .B(n112), .Y(n110) );
NOR2XLTS U47 ( .A(n96), .B(n97), .Y(n95) );
NOR2XLTS U48 ( .A(n81), .B(n82), .Y(n80) );
NOR2XLTS U49 ( .A(n66), .B(n67), .Y(n65) );
INVX2TS U50 ( .A(Data_A_i[2]), .Y(Data_S_o[2]) );
NOR2XLTS U51 ( .A(n54), .B(n55), .Y(Data_S_o[53]) );
NAND2X1TS U52 ( .A(n122), .B(Data_A_i[7]), .Y(n121) );
NAND2X1TS U53 ( .A(n119), .B(Data_A_i[9]), .Y(n118) );
NAND2X1TS U54 ( .A(n116), .B(Data_A_i[11]), .Y(n115) );
NAND2X1TS U55 ( .A(n113), .B(Data_A_i[13]), .Y(n112) );
NAND2X1TS U56 ( .A(n110), .B(Data_A_i[15]), .Y(n109) );
NAND2X1TS U57 ( .A(n107), .B(Data_A_i[17]), .Y(n106) );
NAND2X1TS U58 ( .A(n104), .B(Data_A_i[19]), .Y(n103) );
NAND2X1TS U59 ( .A(n101), .B(Data_A_i[21]), .Y(n100) );
NAND2X1TS U60 ( .A(n98), .B(Data_A_i[23]), .Y(n97) );
NAND2X1TS U61 ( .A(n95), .B(Data_A_i[25]), .Y(n94) );
NAND2X1TS U62 ( .A(n92), .B(Data_A_i[27]), .Y(n91) );
NAND2X1TS U63 ( .A(n89), .B(Data_A_i[29]), .Y(n88) );
NAND2X1TS U64 ( .A(n86), .B(Data_A_i[31]), .Y(n85) );
NAND2X1TS U65 ( .A(n83), .B(Data_A_i[33]), .Y(n82) );
NAND2X1TS U66 ( .A(n80), .B(Data_A_i[35]), .Y(n79) );
NAND2X1TS U67 ( .A(n77), .B(Data_A_i[37]), .Y(n76) );
NAND2X1TS U68 ( .A(n74), .B(Data_A_i[39]), .Y(n73) );
NAND2X1TS U69 ( .A(n71), .B(Data_A_i[41]), .Y(n70) );
NAND2X1TS U70 ( .A(n68), .B(Data_A_i[43]), .Y(n67) );
NAND2X1TS U71 ( .A(n65), .B(Data_A_i[45]), .Y(n64) );
NAND2X1TS U72 ( .A(n62), .B(Data_A_i[47]), .Y(n61) );
NAND2X1TS U73 ( .A(n59), .B(Data_A_i[49]), .Y(n58) );
NAND2X1TS U74 ( .A(n56), .B(Data_A_i[51]), .Y(n55) );
AOI21X1TS U75 ( .A0(n55), .A1(n54), .B0(Data_S_o[53]), .Y(Data_S_o[52]) );
OA21XLTS U76 ( .A0(n56), .A1(Data_A_i[51]), .B0(n55), .Y(Data_S_o[51]) );
AOI21X1TS U77 ( .A0(n58), .A1(n57), .B0(n56), .Y(Data_S_o[50]) );
OA21XLTS U78 ( .A0(n59), .A1(Data_A_i[49]), .B0(n58), .Y(Data_S_o[49]) );
AOI21X1TS U79 ( .A0(n61), .A1(n60), .B0(n59), .Y(Data_S_o[48]) );
OA21XLTS U80 ( .A0(n62), .A1(Data_A_i[47]), .B0(n61), .Y(Data_S_o[47]) );
AOI21X1TS U81 ( .A0(n64), .A1(n63), .B0(n62), .Y(Data_S_o[46]) );
OA21XLTS U82 ( .A0(n65), .A1(Data_A_i[45]), .B0(n64), .Y(Data_S_o[45]) );
AOI21X1TS U83 ( .A0(n67), .A1(n66), .B0(n65), .Y(Data_S_o[44]) );
OA21XLTS U84 ( .A0(n68), .A1(Data_A_i[43]), .B0(n67), .Y(Data_S_o[43]) );
AOI21X1TS U85 ( .A0(n70), .A1(n69), .B0(n68), .Y(Data_S_o[42]) );
OA21XLTS U86 ( .A0(n71), .A1(Data_A_i[41]), .B0(n70), .Y(Data_S_o[41]) );
AOI21X1TS U87 ( .A0(n73), .A1(n72), .B0(n71), .Y(Data_S_o[40]) );
OA21XLTS U88 ( .A0(n74), .A1(Data_A_i[39]), .B0(n73), .Y(Data_S_o[39]) );
AOI21X1TS U89 ( .A0(n76), .A1(n75), .B0(n74), .Y(Data_S_o[38]) );
OA21XLTS U90 ( .A0(n77), .A1(Data_A_i[37]), .B0(n76), .Y(Data_S_o[37]) );
AOI21X1TS U91 ( .A0(n79), .A1(n78), .B0(n77), .Y(Data_S_o[36]) );
OA21XLTS U92 ( .A0(n80), .A1(Data_A_i[35]), .B0(n79), .Y(Data_S_o[35]) );
AOI21X1TS U93 ( .A0(n82), .A1(n81), .B0(n80), .Y(Data_S_o[34]) );
OA21XLTS U94 ( .A0(n83), .A1(Data_A_i[33]), .B0(n82), .Y(Data_S_o[33]) );
AOI21X1TS U95 ( .A0(n85), .A1(n84), .B0(n83), .Y(Data_S_o[32]) );
OA21XLTS U96 ( .A0(n86), .A1(Data_A_i[31]), .B0(n85), .Y(Data_S_o[31]) );
AOI21X1TS U97 ( .A0(n88), .A1(n87), .B0(n86), .Y(Data_S_o[30]) );
OA21XLTS U98 ( .A0(n89), .A1(Data_A_i[29]), .B0(n88), .Y(Data_S_o[29]) );
AOI21X1TS U99 ( .A0(n91), .A1(n90), .B0(n89), .Y(Data_S_o[28]) );
OA21XLTS U100 ( .A0(n92), .A1(Data_A_i[27]), .B0(n91), .Y(Data_S_o[27]) );
AOI21X1TS U101 ( .A0(n94), .A1(n93), .B0(n92), .Y(Data_S_o[26]) );
OA21XLTS U102 ( .A0(n95), .A1(Data_A_i[25]), .B0(n94), .Y(Data_S_o[25]) );
AOI21X1TS U103 ( .A0(n97), .A1(n96), .B0(n95), .Y(Data_S_o[24]) );
OA21XLTS U104 ( .A0(n98), .A1(Data_A_i[23]), .B0(n97), .Y(Data_S_o[23]) );
AOI21X1TS U105 ( .A0(n100), .A1(n99), .B0(n98), .Y(Data_S_o[22]) );
OA21XLTS U106 ( .A0(n101), .A1(Data_A_i[21]), .B0(n100), .Y(Data_S_o[21]) );
AOI21X1TS U107 ( .A0(n103), .A1(n102), .B0(n101), .Y(Data_S_o[20]) );
OA21XLTS U108 ( .A0(n104), .A1(Data_A_i[19]), .B0(n103), .Y(Data_S_o[19]) );
AOI21X1TS U109 ( .A0(n106), .A1(n105), .B0(n104), .Y(Data_S_o[18]) );
OA21XLTS U110 ( .A0(n107), .A1(Data_A_i[17]), .B0(n106), .Y(Data_S_o[17]) );
AOI21X1TS U111 ( .A0(n109), .A1(n108), .B0(n107), .Y(Data_S_o[16]) );
OA21XLTS U112 ( .A0(n110), .A1(Data_A_i[15]), .B0(n109), .Y(Data_S_o[15]) );
AOI21X1TS U113 ( .A0(n112), .A1(n111), .B0(n110), .Y(Data_S_o[14]) );
OA21XLTS U114 ( .A0(n113), .A1(Data_A_i[13]), .B0(n112), .Y(Data_S_o[13]) );
AOI21X1TS U115 ( .A0(n115), .A1(n114), .B0(n113), .Y(Data_S_o[12]) );
OA21XLTS U116 ( .A0(n116), .A1(Data_A_i[11]), .B0(n115), .Y(Data_S_o[11]) );
AOI21X1TS U117 ( .A0(n118), .A1(n117), .B0(n116), .Y(Data_S_o[10]) );
OA21XLTS U118 ( .A0(n119), .A1(Data_A_i[9]), .B0(n118), .Y(Data_S_o[9]) );
AOI21X1TS U119 ( .A0(n121), .A1(n120), .B0(n119), .Y(Data_S_o[8]) );
OA21XLTS U120 ( .A0(n122), .A1(Data_A_i[7]), .B0(n121), .Y(Data_S_o[7]) );
AOI21X1TS U121 ( .A0(n125), .A1(n123), .B0(n122), .Y(Data_S_o[6]) );
NOR2BX1TS U122 ( .AN(Data_A_i[3]), .B(Data_S_o[2]), .Y(n124) );
AOI2BB1XLTS U123 ( .A0N(Data_A_i[2]), .A1N(Data_A_i[3]), .B0(n124), .Y(
Data_S_o[3]) );
OAI2BB1X1TS U124 ( .A0N(n124), .A1N(Data_A_i[4]), .B0(n126), .Y(Data_S_o[4])
);
AO21XLTS U125 ( .A0(Data_A_i[5]), .A1(n126), .B0(n125), .Y(Data_S_o[5]) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module Adder_Round_SW53 ( clk, rst, load_i, Data_A_i, Data_B_i, Data_Result_o,
FSM_C_o );
input [52:0] Data_A_i;
input [52:0] Data_B_i;
output [52:0] Data_Result_o;
input clk, rst, load_i;
output FSM_C_o;
wire [1:53] n;
wire [53:0] result_A_adder;
adder_W53 A_operation ( .Data_A_i(Data_A_i), .Data_B_i({1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1, 1'b1, 1'b0, 1'b1,
1'b0, 1'b0}), .Data_S_o(result_A_adder) );
RegisterAdd Add_Subt_Result ( .clk(clk), .rst(rst), .load(load_i), .D(
result_A_adder[52:0]), .Q(Data_Result_o) );
RegisterAdd Add_overflow_Result ( .clk(clk), .rst(rst), .load(load_i), .D(
result_A_adder[53]), .Q(FSM_C_o) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
module FPU_Multiplication_Function_W64_EW11_SW52 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [63:0] Data_MX;
input [63:0] Data_MY;
input [1:0] round_mode;
output [63:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire zero_flag, FSM_round_flag, FSM_add_overflow_flag,
FSM_first_phase_load, FSM_load_first_step,
FSM_exp_operation_load_result, FSM_load_second_step,
FSM_adder_round_norm_load, FSM_final_result_load,
FSM_barrel_shifter_load, selector_A, load_b, selector_C,
FSM_exp_operation_A_S, FSM_Shift_Value, rst_int, FSM_selector_A,
FSM_selector_C, sign_final_result, n1, n2, n3, n4, n5, n6, n7, n8, n9,
n10, n11, n12, n13, n14, n15, n16, n17, n18, n19, n20, n21, n22, n23,
n24, n25, n26, n27, n28, n29, n30, n31, n32, n33, n34, n35, n36, n37,
n38, n39, n40, n41, n42, n43, n44, n45, n46, n47, n48, n49, n50, n51,
n52, n53, n54, n55, n56, n57, n58, n59, n60, n61, n62, n63, n64, n65,
n66, n67, n68, n69, n70;
wire [105:0] P_Sgf;
wire [1:0] selector_B;
wire [1:0] FSM_selector_B;
wire [63:0] Op_MX;
wire [63:0] Op_MY;
wire [11:0] exp_oper_result;
wire [11:0] S_Oper_A_exp;
wire [10:0] S_Oper_B_exp;
wire [52:0] Add_result;
wire [52:0] S_Data_Shift;
wire [52:0] Sgf_normalized_result;
FSM_Mult_Function FS_Module ( .clk(clk), .rst(rst), .beg_FSM(beg_FSM),
.ack_FSM(ack_FSM), .zero_flag_i(zero_flag), .Mult_shift_i(P_Sgf[105]),
.round_flag_i(FSM_round_flag), .Add_Overflow_i(FSM_add_overflow_flag),
.load_0_o(FSM_first_phase_load), .load_1_o(FSM_load_first_step),
.load_2_o(FSM_exp_operation_load_result), .load_3_o(
FSM_load_second_step), .load_4_o(FSM_adder_round_norm_load),
.load_5_o(FSM_final_result_load), .load_6_o(FSM_barrel_shifter_load),
.ctrl_select_a_o(selector_A), .ctrl_select_b_o(load_b), .selector_b_o(
selector_B), .ctrl_select_c_o(selector_C), .exp_op_o(
FSM_exp_operation_A_S), .shift_value_o(FSM_Shift_Value), .rst_int(
rst_int), .ready(ready) );
RegisterAdd Sel_A ( .clk(clk), .rst(rst_int), .load(selector_A), .D(1'b1),
.Q(FSM_selector_A) );
RegisterAdd Sel_C ( .clk(clk), .rst(rst_int), .load(selector_C), .D(1'b1),
.Q(FSM_selector_C) );
RegisterAdd Sel_B ( .clk(clk), .rst(rst_int), .load(load_b), .D(selector_B),
.Q(FSM_selector_B) );
First_Phase_M_W64 Operands_load_reg ( .clk(clk), .rst(rst_int), .load(
FSM_first_phase_load), .Data_MX(Data_MX), .Data_MY(Data_MY), .Op_MX(
Op_MX), .Op_MY(Op_MY) );
Zero_InfMult_Unit Zero_Result_Detect ( .clk(clk), .rst(rst_int), .load(
FSM_load_first_step), .Data_A(Op_MX[62:0]), .Data_B(Op_MY[62:0]),
.zero_m_flag(zero_flag) );
Multiplexer_AC Exp_Oper_A_mux ( .ctrl(FSM_selector_A), .D0({1'b0,
Op_MX[62:52]}), .D1(exp_oper_result), .S(S_Oper_A_exp) );
Mux_3x1 Exp_Oper_B_mux ( .ctrl(FSM_selector_B), .D0(Op_MY[62:52]), .D1({1'b0,
1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1, 1'b1}), .D2({
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b1}),
.S(S_Oper_B_exp) );
Exp_Operation_m_EW11 Exp_module ( .clk(clk), .rst(rst_int), .load_a_i(
FSM_load_first_step), .load_b_i(FSM_load_second_step), .load_c_i(
FSM_exp_operation_load_result), .Data_A_i(S_Oper_A_exp), .Data_B_i({
1'b0, S_Oper_B_exp}), .Add_Subt_i(FSM_exp_operation_A_S),
.Data_Result_o(exp_oper_result), .Overflow_flag_o(overflow_flag),
.Underflow_flag_o(underflow_flag) );
XOR_M Sign_operation ( .Sgn_X(Op_MX[63]), .Sgn_Y(Op_MY[63]), .Sgn_Info(
sign_final_result) );
Sgf_Multiplication_SW53 Sgf_operation ( .clk(clk), .rst(rst), .load_b_i(
FSM_load_second_step), .Data_A_i({1'b1, Op_MX[51], n7, Op_MX[49:48],
n43, Op_MX[46:45], n42, Op_MX[43:42], n41, Op_MX[40:39], n6,
Op_MX[37:36], n40, Op_MX[34:33], n5, Op_MX[31:27], n16, Op_MX[25:24],
n69, Op_MX[22:18], n67, Op_MX[16:15], n15, Op_MX[13:12], n14,
Op_MX[10:9], n13, Op_MX[7:6], n66, Op_MX[4:3], n70, Op_MX[1:0]}),
.Data_B_i({1'b1, n17, n4, n37, n36, n34, n33, Op_MY[45], n32, n31, n3,
n29, n28, n27, n2, n26, n25, Op_MY[35], n24, n1, n22, Op_MY[31], n20,
n19, Op_MY[28:27], n35, n65, n38, n64, n63, n62, n61, n60, Op_MY[18],
n12, n59, n11, n57, n56, n10, n9, n55, n54, n53, n52, n50, n49, n48,
n8, n46, n44, Op_MY[0]}), .sgf_result_o(P_Sgf) );
Multiplexer_AC Barrel_Shifter_D_I_mux ( .ctrl(FSM_selector_C), .D0(
P_Sgf[104:52]), .D1(Add_result), .S(S_Data_Shift) );
Barrel_Shifter_M_SW53 Barrel_Shifter_module ( .clk(clk), .rst(rst_int),
.load_i(FSM_barrel_shifter_load), .Shift_Value_i(FSM_Shift_Value),
.Shift_Data_i(S_Data_Shift), .N_mant_o(Sgf_normalized_result) );
Round_decoder_M Round_Decoder ( .Round_Bits_i({1'b0, P_Sgf[51:0]}),
.Round_Mode_i(round_mode), .Sign_Result_i(sign_final_result),
.Round_Flag_o(FSM_round_flag) );
Adder_Round_SW53 Adder_M ( .clk(clk), .rst(rst_int), .load_i(
FSM_adder_round_norm_load), .Data_A_i(Sgf_normalized_result),
.Data_B_i({1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0,
1'b0, 1'b1, 1'b1, 1'b0, 1'b1, 1'b0, 1'b0}), .Data_Result_o(Add_result),
.FSM_C_o(FSM_add_overflow_flag) );
Tenth_Phase final_result_ieee_Module ( .clk(clk), .rst(rst_int), .load_i(
FSM_final_result_load), .sel_a_i(overflow_flag), .sel_b_i(
underflow_flag), .sign_i(sign_final_result), .exp_ieee_i(
exp_oper_result[10:0]), .sgf_ieee_i(Sgf_normalized_result[51:0]),
.final_result_ieee_o(final_result_ieee) );
CLKBUFX2TS U3 ( .A(Op_MX[44]), .Y(n42) );
CLKBUFX2TS U4 ( .A(Op_MX[8]), .Y(n13) );
CLKBUFX2TS U5 ( .A(Op_MY[8]), .Y(n53) );
BUFX3TS U6 ( .A(Op_MY[46]), .Y(n33) );
CLKBUFX2TS U7 ( .A(Op_MY[30]), .Y(n20) );
CLKBUFX2TS U8 ( .A(Op_MY[23]), .Y(n64) );
INVX3TS U9 ( .A(n39), .Y(n40) );
BUFX3TS U10 ( .A(Op_MY[40]), .Y(n28) );
BUFX3TS U11 ( .A(Op_MY[13]), .Y(n56) );
BUFX3TS U12 ( .A(Op_MY[1]), .Y(n44) );
CLKBUFX2TS U13 ( .A(Op_MY[41]), .Y(n29) );
BUFX4TS U14 ( .A(Op_MY[19]), .Y(n60) );
BUFX3TS U15 ( .A(Op_MY[37]), .Y(n26) );
BUFX3TS U16 ( .A(Op_MX[50]), .Y(n7) );
BUFX8TS U17 ( .A(Op_MY[33]), .Y(n1) );
INVX2TS U18 ( .A(n45), .Y(n46) );
INVX2TS U19 ( .A(n18), .Y(n19) );
BUFX3TS U20 ( .A(Op_MY[48]), .Y(n36) );
BUFX3TS U21 ( .A(Op_MY[14]), .Y(n57) );
CLKBUFX2TS U22 ( .A(Op_MY[25]), .Y(n65) );
CLKBUFX2TS U23 ( .A(Op_MY[20]), .Y(n61) );
INVX2TS U24 ( .A(Op_MY[29]), .Y(n18) );
BUFX3TS U25 ( .A(Op_MY[22]), .Y(n63) );
BUFX4TS U26 ( .A(Op_MX[38]), .Y(n6) );
INVX2TS U27 ( .A(Op_MY[2]), .Y(n45) );
INVX3TS U28 ( .A(n68), .Y(n69) );
INVX2TS U29 ( .A(n21), .Y(n22) );
BUFX3TS U30 ( .A(Op_MY[49]), .Y(n37) );
BUFX3TS U31 ( .A(Op_MY[11]), .Y(n9) );
BUFX3TS U32 ( .A(Op_MX[5]), .Y(n66) );
INVX2TS U33 ( .A(n58), .Y(n59) );
INVX2TS U34 ( .A(n30), .Y(n31) );
BUFX3TS U35 ( .A(Op_MX[32]), .Y(n5) );
BUFX3TS U36 ( .A(Op_MX[47]), .Y(n43) );
INVX2TS U37 ( .A(n23), .Y(n24) );
BUFX3TS U38 ( .A(Op_MX[11]), .Y(n14) );
BUFX3TS U39 ( .A(Op_MY[38]), .Y(n2) );
BUFX3TS U40 ( .A(Op_MY[42]), .Y(n3) );
CLKBUFX2TS U41 ( .A(Op_MY[50]), .Y(n4) );
BUFX3TS U42 ( .A(Op_MY[3]), .Y(n8) );
BUFX3TS U43 ( .A(Op_MY[5]), .Y(n49) );
BUFX3TS U44 ( .A(Op_MY[6]), .Y(n50) );
INVX2TS U45 ( .A(n51), .Y(n52) );
BUFX3TS U46 ( .A(Op_MY[12]), .Y(n10) );
BUFX3TS U47 ( .A(Op_MY[15]), .Y(n11) );
BUFX3TS U48 ( .A(Op_MY[17]), .Y(n12) );
BUFX3TS U49 ( .A(Op_MX[14]), .Y(n15) );
INVX2TS U50 ( .A(Op_MX[23]), .Y(n68) );
BUFX3TS U51 ( .A(Op_MX[26]), .Y(n16) );
CLKBUFX2TS U52 ( .A(Op_MY[51]), .Y(n17) );
INVX2TS U53 ( .A(Op_MY[32]), .Y(n21) );
INVX2TS U54 ( .A(Op_MY[34]), .Y(n23) );
BUFX3TS U55 ( .A(Op_MY[36]), .Y(n25) );
BUFX3TS U56 ( .A(Op_MY[39]), .Y(n27) );
INVX2TS U57 ( .A(Op_MY[43]), .Y(n30) );
BUFX3TS U58 ( .A(Op_MY[44]), .Y(n32) );
BUFX3TS U59 ( .A(Op_MY[47]), .Y(n34) );
CLKBUFX2TS U60 ( .A(Op_MY[26]), .Y(n35) );
CLKBUFX2TS U61 ( .A(Op_MY[24]), .Y(n38) );
INVX2TS U62 ( .A(Op_MX[35]), .Y(n39) );
BUFX3TS U63 ( .A(Op_MX[41]), .Y(n41) );
INVX2TS U64 ( .A(Op_MY[4]), .Y(n47) );
INVX2TS U65 ( .A(n47), .Y(n48) );
INVX2TS U66 ( .A(Op_MY[7]), .Y(n51) );
BUFX3TS U67 ( .A(Op_MY[9]), .Y(n54) );
BUFX3TS U68 ( .A(Op_MY[10]), .Y(n55) );
INVX2TS U69 ( .A(Op_MY[16]), .Y(n58) );
BUFX3TS U70 ( .A(Op_MY[21]), .Y(n62) );
BUFX3TS U71 ( .A(Op_MX[17]), .Y(n67) );
BUFX3TS U72 ( .A(Op_MX[2]), .Y(n70) );
initial $sdf_annotate("FPU_Multiplication_Function_syn.sdf");
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// Decompiler for Amber 25 Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Decompiler for debugging core - not synthesizable //
// Shows instruction in Execute Stage at last clock of //
// the instruction //
// //
// Author(s): //
// - Conor Santifort, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2011 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
`include "global_defines.v"
`include "a25_config_defines.v"
module a25_decompile
(
input i_clk,
input i_core_stall,
input [31:0] i_instruction,
input i_instruction_valid,
input i_instruction_undefined,
input i_instruction_execute,
input [2:0] i_interrupt, // non-zero value means interrupt triggered
input i_interrupt_state,
input [31:0] i_instruction_address,
input [2:0] i_pc_sel,
input i_pc_wen
);
`include "a25_localparams.v"
`ifdef A25_DECOMPILE
integer i;
wire [31:0] imm32;
wire [7:0] imm8;
wire [11:0] offset12;
wire [7:0] offset8;
wire [3:0] reg_n, reg_d, reg_m, reg_s;
wire [4:0] shift_imm;
wire [3:0] opcode;
wire [3:0] condition;
wire [3:0] type;
wire opcode_compare;
wire opcode_move;
wire no_shift;
wire shift_op_imm;
wire [1:0] mtrans_type;
wire s_bit;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE;
reg [(5*8)-1:0] xINSTRUCTION_EXECUTE_R = "--- ";
wire [(8*8)-1:0] TYPE_NAME;
reg [3:0] fchars;
reg [31:0] execute_address = 'd0;
reg [2:0] interrupt_d1;
reg [31:0] execute_instruction = 'd0;
reg execute_now = 'd0;
reg execute_valid = 'd0;
reg execute_undefined = 'd0;
// ========================================================
// Delay instruction to Execute stage
// ========================================================
always @( posedge i_clk )
if ( !i_core_stall && i_instruction_valid )
begin
execute_instruction <= i_instruction;
execute_address <= i_instruction_address;
execute_undefined <= i_instruction_undefined;
execute_now <= 1'd1;
end
else
execute_now <= 1'd0;
always @ ( posedge i_clk )
if ( !i_core_stall )
execute_valid <= i_instruction_valid;
// ========================================================
// Open File
// ========================================================
integer decompile_file;
initial
#1 decompile_file = $fopen(`A25_DECOMPILE_FILE, "w");
// ========================================================
// Fields within the instruction
// ========================================================
assign opcode = execute_instruction[24:21];
assign condition = execute_instruction[31:28];
assign s_bit = execute_instruction[20];
assign reg_n = execute_instruction[19:16];
assign reg_d = execute_instruction[15:12];
assign reg_m = execute_instruction[3:0];
assign reg_s = execute_instruction[11:8];
assign shift_imm = execute_instruction[11:7];
assign offset12 = execute_instruction[11:0];
assign offset8 = {execute_instruction[11:8], execute_instruction[3:0]};
assign imm8 = execute_instruction[7:0];
assign no_shift = execute_instruction[11:4] == 8'h0;
assign mtrans_type = execute_instruction[24:23];
assign opcode_compare =
opcode == CMP ||
opcode == CMN ||
opcode == TEQ ||
opcode == TST ;
assign opcode_move =
opcode == MOV ||
opcode == MVN ;
assign shift_op_imm = type == REGOP && execute_instruction[25] == 1'd1;
assign imm32 = execute_instruction[11:8] == 4'h0 ? { 24'h0, imm8[7:0] } :
execute_instruction[11:8] == 4'h1 ? { imm8[1:0], 24'h0, imm8[7:2] } :
execute_instruction[11:8] == 4'h2 ? { imm8[3:0], 24'h0, imm8[7:4] } :
execute_instruction[11:8] == 4'h3 ? { imm8[5:0], 24'h0, imm8[7:6] } :
execute_instruction[11:8] == 4'h4 ? { imm8[7:0], 24'h0 } :
execute_instruction[11:8] == 4'h5 ? { 2'h0, imm8[7:0], 22'h0 } :
execute_instruction[11:8] == 4'h6 ? { 4'h0, imm8[7:0], 20'h0 } :
execute_instruction[11:8] == 4'h7 ? { 6'h0, imm8[7:0], 18'h0 } :
execute_instruction[11:8] == 4'h8 ? { 8'h0, imm8[7:0], 16'h0 } :
execute_instruction[11:8] == 4'h9 ? { 10'h0, imm8[7:0], 14'h0 } :
execute_instruction[11:8] == 4'ha ? { 12'h0, imm8[7:0], 12'h0 } :
execute_instruction[11:8] == 4'hb ? { 14'h0, imm8[7:0], 10'h0 } :
execute_instruction[11:8] == 4'hc ? { 16'h0, imm8[7:0], 8'h0 } :
execute_instruction[11:8] == 4'hd ? { 18'h0, imm8[7:0], 6'h0 } :
execute_instruction[11:8] == 4'he ? { 20'h0, imm8[7:0], 4'h0 } :
{ 22'h0, imm8[7:0], 2'h0 } ;
// ========================================================
// Instruction decode
// ========================================================
// the order of these matters
assign type =
{execute_instruction[27:23], execute_instruction[21:20], execute_instruction[11:4] } == { 5'b00010, 2'b00, 8'b00001001 } ? SWAP : // Before REGOP
{execute_instruction[27:22], execute_instruction[7:4] } == { 6'b000000, 4'b1001 } ? MULT : // Before REGOP
{execute_instruction[27:26] } == { 2'b00 } ? REGOP :
{execute_instruction[27:26] } == { 2'b01 } ? TRANS :
{execute_instruction[27:25] } == { 3'b100 } ? MTRANS :
{execute_instruction[27:25] } == { 3'b101 } ? BRANCH :
{execute_instruction[27:25] } == { 3'b110 } ? CODTRANS :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b0 } ? COREGOP :
{execute_instruction[27:24], execute_instruction[4] } == { 4'b1110, 1'b1 } ? CORTRANS :
SWI ;
//
// Convert some important signals to ASCII
// so their values can easily be displayed on a waveform viewer
//
assign TYPE_NAME = type == REGOP ? "REGOP " :
type == MULT ? "MULT " :
type == SWAP ? "SWAP " :
type == TRANS ? "TRANS " :
type == MTRANS ? "MTRANS " :
type == BRANCH ? "BRANCH " :
type == CODTRANS ? "CODTRANS" :
type == COREGOP ? "COREGOP " :
type == CORTRANS ? "CORTRANS" :
type == SWI ? "SWI " :
"UNKNOWN " ;
always @*
begin
if ( !execute_now )
begin
xINSTRUCTION_EXECUTE = xINSTRUCTION_EXECUTE_R;
end // stalled
else if ( type == REGOP && opcode == ADC ) xINSTRUCTION_EXECUTE = "adc ";
else if ( type == REGOP && opcode == ADD ) xINSTRUCTION_EXECUTE = "add ";
else if ( type == REGOP && opcode == AND ) xINSTRUCTION_EXECUTE = "and ";
else if ( type == BRANCH && execute_instruction[24] == 1'b0 ) xINSTRUCTION_EXECUTE = "b ";
else if ( type == REGOP && opcode == BIC ) xINSTRUCTION_EXECUTE = "bic ";
else if ( type == BRANCH && execute_instruction[24] == 1'b1 ) xINSTRUCTION_EXECUTE = "bl ";
else if ( type == COREGOP ) xINSTRUCTION_EXECUTE = "cdp ";
else if ( type == REGOP && opcode == CMN ) xINSTRUCTION_EXECUTE = "cmn ";
else if ( type == REGOP && opcode == CMP ) xINSTRUCTION_EXECUTE = "cmp ";
else if ( type == REGOP && opcode == EOR ) xINSTRUCTION_EXECUTE = "eor ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "ldm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b1} ) xINSTRUCTION_EXECUTE = "ldr ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b1} ) xINSTRUCTION_EXECUTE = "ldrb ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "mcr ";
else if ( type == MULT && execute_instruction[21] == 1'b1 ) xINSTRUCTION_EXECUTE = "mla ";
else if ( type == REGOP && opcode == MOV ) xINSTRUCTION_EXECUTE = "mov ";
else if ( type == CORTRANS && execute_instruction[20] == 1'b1 ) xINSTRUCTION_EXECUTE = "mrc ";
else if ( type == MULT && execute_instruction[21] == 1'b0 ) xINSTRUCTION_EXECUTE = "mul ";
else if ( type == REGOP && opcode == MVN ) xINSTRUCTION_EXECUTE = "mvn ";
else if ( type == REGOP && opcode == ORR ) xINSTRUCTION_EXECUTE = "orr ";
else if ( type == REGOP && opcode == RSB ) xINSTRUCTION_EXECUTE = "rsb ";
else if ( type == REGOP && opcode == RSC ) xINSTRUCTION_EXECUTE = "rsc ";
else if ( type == REGOP && opcode == SBC ) xINSTRUCTION_EXECUTE = "sbc ";
else if ( type == CODTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stc ";
else if ( type == MTRANS && execute_instruction[20] == 1'b0 ) xINSTRUCTION_EXECUTE = "stm ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b0, 1'b0} ) xINSTRUCTION_EXECUTE = "str ";
else if ( type == TRANS && {execute_instruction[22],execute_instruction[20]} == {1'b1, 1'b0} ) xINSTRUCTION_EXECUTE = "strb ";
else if ( type == REGOP && opcode == SUB ) xINSTRUCTION_EXECUTE = "sub ";
else if ( type == SWI ) xINSTRUCTION_EXECUTE = "swi ";
else if ( type == SWAP && execute_instruction[22] == 1'b0 ) xINSTRUCTION_EXECUTE = "swp ";
else if ( type == SWAP && execute_instruction[22] == 1'b1 ) xINSTRUCTION_EXECUTE = "swpb ";
else if ( type == REGOP && opcode == TEQ ) xINSTRUCTION_EXECUTE = "teq ";
else if ( type == REGOP && opcode == TST ) xINSTRUCTION_EXECUTE = "tst ";
else xINSTRUCTION_EXECUTE = "unkow";
end
always @ ( posedge i_clk )
xINSTRUCTION_EXECUTE_R <= xINSTRUCTION_EXECUTE;
// =================================================================================
// Memory Reads and Writes
// =================================================================================
reg [31:0] tmp_address;
always @( posedge i_clk )
begin
// Data Write
if ( get_1bit_signal(0) && !get_1bit_signal(3) )
begin
$fwrite(decompile_file, "%09d write addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(2);
fwrite_hex_drop_zeros(decompile_file, {tmp_address [31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h, be %h",
get_32bit_signal(3), // u_cache.i_write_data
get_4bit_signal (0)); // u_cache.i_byte_enable
$fwrite(decompile_file, "\n");
end
// Data Read
if ( get_1bit_signal(4) && !get_1bit_signal(1) )
begin
$fwrite(decompile_file, "%09d read addr ", `U_TB.clk_count);
tmp_address = get_32bit_signal(5);
fwrite_hex_drop_zeros(decompile_file, {tmp_address[31:2], 2'd0} );
$fwrite(decompile_file, ", data %08h to ", get_32bit_signal(4));
warmreg(get_4bit_signal(1));
$fwrite(decompile_file, "\n");
end
// instruction
if ( execute_now )
begin
// Interrupts override instructions that are just starting
if ( interrupt_d1 == 3'd0 || interrupt_d1 == 3'd7 )
begin
$fwrite(decompile_file,"%09d ", `U_TB.clk_count);
// Right justify the address
if ( execute_address < 32'h10) $fwrite(decompile_file," %01x: ", {execute_address[ 3:1], 1'd0});
else if ( execute_address < 32'h100) $fwrite(decompile_file," %02x: ", {execute_address[ 7:1], 1'd0});
else if ( execute_address < 32'h1000) $fwrite(decompile_file," %03x: ", {execute_address[11:1], 1'd0});
else if ( execute_address < 32'h10000) $fwrite(decompile_file," %04x: ", {execute_address[15:1], 1'd0});
else if ( execute_address < 32'h100000) $fwrite(decompile_file," %05x: ", {execute_address[19:1], 1'd0});
else if ( execute_address < 32'h1000000) $fwrite(decompile_file," %06x: ", {execute_address[23:1], 1'd0});
else if ( execute_address < 32'h10000000) $fwrite(decompile_file," %07x: ", {execute_address[27:1], 1'd0});
else $fwrite(decompile_file,"%8x: ", {execute_address[31:1], 1'd0});
// Mark that the instruction is not being executed
// condition field in execute stage allows instruction to execute ?
if (!i_instruction_execute)
begin
$fwrite(decompile_file,"-");
if ( type == SWI )
$display ("Cycle %09d SWI not taken *************", `U_TB.clk_count);
end
else
$fwrite(decompile_file," ");
// ========================================
// print the instruction name
// ========================================
case (numchars( xINSTRUCTION_EXECUTE ))
4'd1: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:32] );
4'd2: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:24] );
4'd3: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39:16] );
4'd4: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 8] );
default: $fwrite(decompile_file,"%s", xINSTRUCTION_EXECUTE[39: 0] );
endcase
fchars = 8 - numchars(xINSTRUCTION_EXECUTE);
// Print the Multiple transfer type
if (type == MTRANS )
begin
w_mtrans_type;
fchars = fchars - 2;
end
// Print the s bit
if ( ((type == REGOP && !opcode_compare) || type == MULT ) && s_bit == 1'b1 )
begin
$fwrite(decompile_file,"s");
fchars = fchars - 1;
end
// Print the p bit
if ( type == REGOP && opcode_compare && s_bit == 1'b1 && reg_d == 4'd15 )
begin
$fwrite(decompile_file,"p");
fchars = fchars - 1;
end
// Print the condition code
if ( condition != AL )
begin
wcond;
fchars = fchars - 2;
end
// Align spaces after instruction
case ( fchars )
4'd0: $fwrite(decompile_file,"");
4'd1: $fwrite(decompile_file," ");
4'd2: $fwrite(decompile_file," ");
4'd3: $fwrite(decompile_file," ");
4'd4: $fwrite(decompile_file," ");
4'd5: $fwrite(decompile_file," ");
4'd6: $fwrite(decompile_file," ");
4'd7: $fwrite(decompile_file," ");
4'd8: $fwrite(decompile_file," ");
default: $fwrite(decompile_file," ");
endcase
// ========================================
// print the arguments for the instruction
// ========================================
case ( type )
REGOP: regop_args;
TRANS: trans_args;
MTRANS: mtrans_args;
BRANCH: branch_args;
MULT: mult_args;
SWAP: swap_args;
CODTRANS: codtrans_args;
COREGOP: begin
// `TB_ERROR_MESSAGE
$write("Coregop not implemented in decompiler yet\n");
end
CORTRANS: cortrans_args;
SWI: $fwrite(decompile_file,"#0x%06h", execute_instruction[23:0]);
default: begin
`TB_ERROR_MESSAGE
$write("Unknown Instruction Type ERROR\n");
end
endcase
$fwrite( decompile_file,"\n" );
end
// Undefined Instruction Interrupts
if ( i_instruction_execute && execute_undefined )
begin
$fwrite( decompile_file,"%09d interrupt undefined instruction", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
// Software Interrupt
if ( i_instruction_execute && type == SWI )
begin
$fwrite( decompile_file,"%09d interrupt swi", `U_TB.clk_count );
$fwrite( decompile_file,", return addr " );
$fwrite( decompile_file,"%08x\n", pcf(get_reg_val(5'd21)-4'd4) );
end
end
end
always @( posedge i_clk )
if ( !i_core_stall )
begin
interrupt_d1 <= i_interrupt;
// Asynchronous Interrupts
if ( interrupt_d1 != 3'd0 && i_interrupt_state )
begin
$fwrite( decompile_file,"%09d interrupt ", `U_TB.clk_count );
case ( interrupt_d1 )
3'd1: $fwrite( decompile_file,"data abort" );
3'd2: $fwrite( decompile_file,"firq" );
3'd3: $fwrite( decompile_file,"irq" );
3'd4: $fwrite( decompile_file,"address exception" );
3'd5: $fwrite( decompile_file,"instruction abort" );
default: $fwrite( decompile_file,"unknown type" );
endcase
$fwrite( decompile_file,", return addr " );
case ( interrupt_d1 )
3'd1: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd16)));
3'd2: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd17)));
3'd3: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd18)));
3'd4: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd5: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd19)));
3'd7: $fwrite(decompile_file,"%08h\n", pcf(get_reg_val(5'd20)));
default: ;
endcase
end
end
// jump
// Dont print a jump message for interrupts
always @( posedge i_clk )
if (
i_pc_sel != 3'd0 &&
i_pc_wen &&
!i_core_stall &&
i_instruction_execute &&
i_interrupt == 3'd0 &&
!execute_undefined &&
type != SWI &&
execute_address != get_32bit_signal(0) // Don't print jump to same address
)
begin
$fwrite(decompile_file,"%09d jump from ", `U_TB.clk_count);
fwrite_hex_drop_zeros(decompile_file, pcf(execute_address));
$fwrite(decompile_file," to ");
fwrite_hex_drop_zeros(decompile_file, pcf(get_32bit_signal(0)) ); // u_execute.pc_nxt
$fwrite(decompile_file,", r0 %08h, ", get_reg_val ( 5'd0 ));
$fwrite(decompile_file,"r1 %08h\n", get_reg_val ( 5'd1 ));
end
// =================================================================================
// Tasks
// =================================================================================
// Write Condition field
task wcond;
begin
case( condition)
4'h0: $fwrite(decompile_file,"eq");
4'h1: $fwrite(decompile_file,"ne");
4'h2: $fwrite(decompile_file,"cs");
4'h3: $fwrite(decompile_file,"cc");
4'h4: $fwrite(decompile_file,"mi");
4'h5: $fwrite(decompile_file,"pl");
4'h6: $fwrite(decompile_file,"vs");
4'h7: $fwrite(decompile_file,"vc");
4'h8: $fwrite(decompile_file,"hi");
4'h9: $fwrite(decompile_file,"ls");
4'ha: $fwrite(decompile_file,"ge");
4'hb: $fwrite(decompile_file,"lt");
4'hc: $fwrite(decompile_file,"gt");
4'hd: $fwrite(decompile_file,"le");
4'he: $fwrite(decompile_file," "); // Always
default: $fwrite(decompile_file,"nv"); // Never
endcase
end
endtask
// ldm and stm types
task w_mtrans_type;
begin
case( mtrans_type )
4'h0: $fwrite(decompile_file,"da");
4'h1: $fwrite(decompile_file,"ia");
4'h2: $fwrite(decompile_file,"db");
4'h3: $fwrite(decompile_file,"ib");
default: $fwrite(decompile_file,"xx");
endcase
end
endtask
// e.g. mrc 15, 0, r9, cr0, cr0, {0}
task cortrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// opcode1
$fwrite(decompile_file,"%1d, ", execute_instruction[23:21]);
// Rd [15:12]
warmreg(reg_d);
// CRn [19:16]
$fwrite(decompile_file,", cr%1d", execute_instruction[19:16]);
// CRm [3:0]
$fwrite(decompile_file,", cr%1d", execute_instruction[3:0]);
// Opcode2 [7:5]
$fwrite(decompile_file,", {%1d}", execute_instruction[7:5]);
end
endtask
// ldc 15, 0, r9, cr0, cr0, {0}
task codtrans_args;
begin
// Co-Processor Number
$fwrite(decompile_file,"%1d, ", execute_instruction[11:8]);
// CRd [15:12]
$fwrite(decompile_file,"cr%1d, ", execute_instruction[15:12]);
// Rd [19:16]
warmreg(reg_n);
end
endtask
task branch_args;
reg [31:0] shift_amount;
begin
if (execute_instruction[23]) // negative
shift_amount = {~execute_instruction[23:0] + 24'd1, 2'd0};
else
shift_amount = {execute_instruction[23:0], 2'd0};
if (execute_instruction[23]) // negative
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) - shift_amount );
else
fwrite_hex_drop_zeros ( decompile_file, get_reg_val( 5'd21 ) + shift_amount );
end
endtask
task mult_args;
begin
warmreg(reg_n); // Rd is in the Rn position for MULT instructions
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", ");
warmreg(reg_s);
if (execute_instruction[21]) // MLA
begin
$fwrite(decompile_file,", ");
warmreg(reg_d);
end
end
endtask
task swap_args;
begin
warmreg(reg_d);
$fwrite(decompile_file,", ");
warmreg(reg_m);
$fwrite(decompile_file,", [");
warmreg(reg_n);
$fwrite(decompile_file,"]");
end
endtask
task regop_args;
begin
if (!opcode_compare)
warmreg(reg_d);
if (!opcode_move )
begin
if (!opcode_compare)
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
warmreg(reg_n);
$fwrite(decompile_file,", ");
if (reg_n < 4'd10 || reg_n > 4'd12)
$fwrite(decompile_file," ");
end
else
begin
$fwrite(decompile_file,", ");
if (reg_d < 4'd10 || reg_d > 4'd12)
$fwrite(decompile_file," ");
end
if (shift_op_imm)
begin
if (|imm32[31:15])
$fwrite(decompile_file,"#0x%08h", imm32);
else
$fwrite(decompile_file,"#%1d", imm32);
end
else // Rm
begin
warmreg(reg_m);
if (execute_instruction[4])
// Register Shifts
wshiftreg;
else
// Immediate shifts
wshift;
end
end
endtask
task trans_args;
begin
warmreg(reg_d); // Destination register
casez ({execute_instruction[25:23], execute_instruction[21], no_shift, offset12==12'd0})
6'b0100?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]" , offset12); end
6'b0110?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]" , offset12); end
6'b0100?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0110?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0101?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #-%1d]!", offset12); end
6'b0111?? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", #%1d]!" , offset12); end
6'b0000?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0010?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0001?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #-%1d", offset12); end
6'b0011?0 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], #%1d" , offset12); end
6'b0000?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0010?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0001?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b0011?1 : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"]"); end
6'b11001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]"); end
6'b11011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b11111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); $fwrite(decompile_file,"]!"); end
6'b10001? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10101? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b10011? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); end
6'b10111? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); end
6'b11000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]"); end
6'b11010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", -"); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b11110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,", "); warmreg(reg_m); wshift; $fwrite(decompile_file,"]!");end
6'b10000? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10100? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
6'b10010? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], -"); warmreg(reg_m); wshift; end
6'b10110? : begin $fwrite(decompile_file,", ["); warmreg(reg_n); $fwrite(decompile_file,"], "); warmreg(reg_m); wshift; end
endcase
end
endtask
task mtrans_args;
begin
warmreg(reg_n);
if (execute_instruction[21]) $fwrite(decompile_file,"!");
$fwrite(decompile_file,", {");
for (i=0;i<16;i=i+1)
if (execute_instruction[i])
begin
warmreg(i);
if (more_to_come(execute_instruction[15:0], i))
$fwrite(decompile_file,", ");
end
$fwrite(decompile_file,"}");
// SDM: store the user mode registers, when in priviledged mode
if (execute_instruction[22:20] == 3'b100)
$fwrite(decompile_file,"^");
end
endtask
task wshift;
begin
// Check that its a valid shift operation. LSL by #0 is the null operator
if (execute_instruction[6:5] != LSL || shift_imm != 5'd0)
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl");
2'd1: $fwrite(decompile_file,", lsr");
2'd2: $fwrite(decompile_file,", asr");
2'd3: if (shift_imm == 5'd0) $fwrite(decompile_file,", rrx"); else $fwrite(decompile_file,", ror");
endcase
if (execute_instruction[6:5] != 2'd3 || shift_imm != 5'd0)
$fwrite(decompile_file," #%1d", shift_imm);
end
end
endtask
task wshiftreg;
begin
case(execute_instruction[6:5])
2'd0: $fwrite(decompile_file,", lsl ");
2'd1: $fwrite(decompile_file,", lsr ");
2'd2: $fwrite(decompile_file,", asr ");
2'd3: $fwrite(decompile_file,", ror ");
endcase
warmreg(reg_s);
end
endtask
task warmreg;
input [3:0] regnum;
begin
if (regnum < 4'd12)
$fwrite(decompile_file,"r%1d", regnum);
else
case (regnum)
4'd12 : $fwrite(decompile_file,"ip");
4'd13 : $fwrite(decompile_file,"sp");
4'd14 : $fwrite(decompile_file,"lr");
4'd15 : $fwrite(decompile_file,"pc");
endcase
end
endtask
task fwrite_hex_drop_zeros;
input [31:0] file;
input [31:0] num;
begin
if (num[31:28] != 4'd0)
$fwrite(file, "%x", num);
else if (num[27:24] != 4'd0)
$fwrite(file, "%x", num[27:0]);
else if (num[23:20] != 4'd0)
$fwrite(file, "%x", num[23:0]);
else if (num[19:16] != 4'd0)
$fwrite(file, "%x", num[19:0]);
else if (num[15:12] != 4'd0)
$fwrite(file, "%x", num[15:0]);
else if (num[11:8] != 4'd0)
$fwrite(file, "%x", num[11:0]);
else if (num[7:4] != 4'd0)
$fwrite(file, "%x", num[7:0]);
else
$fwrite(file, "%x", num[3:0]);
end
endtask
// =================================================================================
// Functions
// =================================================================================
// Get current value of register
function [31:0] get_reg_val;
input [4:0] regnum;
begin
case (regnum)
5'd0 : get_reg_val = `U_REGISTER_BANK.r0_out;
5'd1 : get_reg_val = `U_REGISTER_BANK.r1_out;
5'd2 : get_reg_val = `U_REGISTER_BANK.r2_out;
5'd3 : get_reg_val = `U_REGISTER_BANK.r3_out;
5'd4 : get_reg_val = `U_REGISTER_BANK.r4_out;
5'd5 : get_reg_val = `U_REGISTER_BANK.r5_out;
5'd6 : get_reg_val = `U_REGISTER_BANK.r6_out;
5'd7 : get_reg_val = `U_REGISTER_BANK.r7_out;
5'd8 : get_reg_val = `U_REGISTER_BANK.r8_out;
5'd9 : get_reg_val = `U_REGISTER_BANK.r9_out;
5'd10 : get_reg_val = `U_REGISTER_BANK.r10_out;
5'd11 : get_reg_val = `U_REGISTER_BANK.r11_out;
5'd12 : get_reg_val = `U_REGISTER_BANK.r12_out;
5'd13 : get_reg_val = `U_REGISTER_BANK.r13_out;
5'd14 : get_reg_val = `U_REGISTER_BANK.r14_out;
5'd15 : get_reg_val = `U_REGISTER_BANK.r15_out_rm; // the version of pc with status bits
5'd16 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd17 : get_reg_val = `U_REGISTER_BANK.r14_firq;
5'd18 : get_reg_val = `U_REGISTER_BANK.r14_irq;
5'd19 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd20 : get_reg_val = `U_REGISTER_BANK.r14_svc;
5'd21 : get_reg_val = `U_REGISTER_BANK.r15_out_rn; // the version of pc without status bits
endcase
end
endfunction
function [31:0] get_32bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_32bit_signal = `U_EXECUTE.pc_nxt;
3'd1: get_32bit_signal = `U_EXECUTE.o_iaddress;
3'd2: get_32bit_signal = `U_EXECUTE.o_daddress;
3'd3: get_32bit_signal = `U_EXECUTE.o_write_data;
// 3'd4: get_32bit_signal = `U_EXECUTE.read_data_filtered;
3'd4: get_32bit_signal = `U_EXECUTE.i_wb_read_data;
3'd5: get_32bit_signal = `U_WB.daddress_r;
endcase
end
endfunction
function get_1bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_1bit_signal = `U_EXECUTE.o_write_enable;
3'd1: get_1bit_signal = `U_AMBER.mem_stall;
3'd2: get_1bit_signal = `U_EXECUTE.o_daddress_valid;
3'd3: get_1bit_signal = `U_AMBER.core_stall;
3'd4: get_1bit_signal = `U_WB.mem_read_data_valid_r;
endcase
end
endfunction
function [3:0] get_4bit_signal;
input [2:0] num;
begin
case (num)
3'd0: get_4bit_signal = `U_EXECUTE.o_byte_enable;
3'd1: get_4bit_signal = `U_WB.mem_load_rd_r;
endcase
end
endfunction
function [3:0] numchars;
input [(5*8)-1:0] xINSTRUCTION_EXECUTE;
begin
if (xINSTRUCTION_EXECUTE[31:0] == " ")
numchars = 4'd1;
else if (xINSTRUCTION_EXECUTE[23:0] == " ")
numchars = 4'd2;
else if (xINSTRUCTION_EXECUTE[15:0] == " ")
numchars = 4'd3;
else if (xINSTRUCTION_EXECUTE[7:0] == " ")
numchars = 4'd4;
else
numchars = 4'd5;
end
endfunction
function more_to_come;
input [15:0] regs;
input [31:0] i;
begin
case (i)
15 : more_to_come = 1'd0;
14 : more_to_come = regs[15] ? 1'd1 : 1'd0;
13 : more_to_come = |regs[15:14] ? 1'd1 : 1'd0;
12 : more_to_come = |regs[15:13] ? 1'd1 : 1'd0;
11 : more_to_come = |regs[15:12] ? 1'd1 : 1'd0;
10 : more_to_come = |regs[15:11] ? 1'd1 : 1'd0;
9 : more_to_come = |regs[15:10] ? 1'd1 : 1'd0;
8 : more_to_come = |regs[15: 9] ? 1'd1 : 1'd0;
7 : more_to_come = |regs[15: 8] ? 1'd1 : 1'd0;
6 : more_to_come = |regs[15: 7] ? 1'd1 : 1'd0;
5 : more_to_come = |regs[15: 6] ? 1'd1 : 1'd0;
4 : more_to_come = |regs[15: 5] ? 1'd1 : 1'd0;
3 : more_to_come = |regs[15: 4] ? 1'd1 : 1'd0;
2 : more_to_come = |regs[15: 3] ? 1'd1 : 1'd0;
1 : more_to_come = |regs[15: 2] ? 1'd1 : 1'd0;
0 : more_to_come = |regs[15: 1] ? 1'd1 : 1'd0;
endcase
end
endfunction
`endif
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: phy_dm_iob.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:33 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_dm_iob.v,v 1.13 2010/02/26 08:58:33 pboya Exp $
**$Date: 2010/02/26 08:58:33 $
**$Author: pboya $
**$Revision: 1.13 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_dm_iob.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_dm_iob #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCWL = 5, // CAS Write Latency
parameter DRAM_TYPE = "DDR3", // Memory I/F type: "DDR3", "DDR2"
parameter WRLVL = "ON", // "OFF" for "DDR3" component interface
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter IODELAY_HP_MODE = "ON", // IODELAY High Performance Mode
parameter IODELAY_GRP = "IODELAY_MIG" // May be assigned unique name
// when mult IP cores in design
)
(
input clk_mem,
input clk,
input clk_rsync,
input rst,
// IODELAY I/F
input [4:0] dlyval,
input dm_ce,
input inv_dqs,
input [1:0] wr_calib_dly,
input mask_data_rise0,
input mask_data_fall0,
input mask_data_rise1,
input mask_data_fall1,
output ddr_dm
);
// Set performance mode for IODELAY (power vs. performance tradeoff)
localparam HIGH_PERFORMANCE_MODE
= (IODELAY_HP_MODE == "OFF") ? "FALSE" :
((IODELAY_HP_MODE == "ON") ? "TRUE" : "ILLEGAL");
wire dm_odelay;
wire dm_oq;
reg mask_data_fall0_r1;
reg mask_data_fall0_r2;
reg mask_data_fall0_r3;
reg mask_data_fall0_r4;
reg mask_data_fall1_r1;
reg mask_data_fall1_r2;
reg mask_data_fall1_r3;
reg mask_data_fall1_r4;
reg mask_data_rise0_r1;
reg mask_data_rise0_r2;
reg mask_data_rise0_r3;
reg mask_data_rise0_r4;
reg mask_data_rise1_r1;
reg mask_data_rise1_r2;
reg mask_data_rise1_r3;
reg mask_data_rise1_r4;
reg out_d1;
reg out_d2;
reg out_d3;
reg out_d4;
//***************************************************************************
// Data Mask Bitslip
//***************************************************************************
// dfi_wrdata_en0 - even clk cycles channel 0
// dfi_wrdata_en1 - odd clk cycles channel 1
// tphy_wrlat set to 0 clk cycle for CWL = 5,6,7,8
// Valid dfi_wrdata* sent 1 clk cycle after dfi_wrdata_en* is asserted
// mask_data_rise0 - first rising edge data mask (rise0)
// mask_data_fall0 - first falling edge data mask (fall0)
// mask_data_rise1 - second rising edge data mask (rise1)
// mask_data_fall1 - second falling edge data mask (fall1)
always @(posedge clk) begin
if (DRAM_TYPE == "DDR3")begin
mask_data_rise0_r1 <= #TCQ dm_ce & mask_data_rise0;
mask_data_fall0_r1 <= #TCQ dm_ce & mask_data_fall0;
mask_data_rise1_r1 <= #TCQ dm_ce & mask_data_rise1;
mask_data_fall1_r1 <= #TCQ dm_ce & mask_data_fall1;
end else begin
mask_data_rise0_r1 <= #TCQ mask_data_rise0;
mask_data_fall0_r1 <= #TCQ mask_data_fall0;
mask_data_rise1_r1 <= #TCQ mask_data_rise1;
mask_data_fall1_r1 <= #TCQ mask_data_fall1;
end
mask_data_rise0_r2 <= #TCQ mask_data_rise0_r1;
mask_data_fall0_r2 <= #TCQ mask_data_fall0_r1;
mask_data_rise1_r2 <= #TCQ mask_data_rise1_r1;
mask_data_fall1_r2 <= #TCQ mask_data_fall1_r1;
mask_data_rise0_r3 <= #TCQ mask_data_rise0_r2;
mask_data_fall0_r3 <= #TCQ mask_data_fall0_r2;
mask_data_rise1_r3 <= #TCQ mask_data_rise1_r2;
mask_data_fall1_r3 <= #TCQ mask_data_fall1_r2;
mask_data_rise0_r4 <= #TCQ mask_data_rise0_r3;
mask_data_fall0_r4 <= #TCQ mask_data_fall0_r3;
mask_data_rise1_r4 <= #TCQ mask_data_rise1_r3;
mask_data_fall1_r4 <= #TCQ mask_data_fall1_r3;
end
// Different nCWL values: 5, 6, 7, 8, 9
generate
if (DRAM_TYPE == "DDR3")begin: gen_dm_ddr3_write_lat
if ((nCWL == 5) | (nCWL == 7) | (nCWL == 9)) begin: gen_dm_ncwl5_odd
always @(posedge clk) begin
if (WRLVL == "OFF") begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end else begin
// write command sent by MC on channel1
// D3,D4 inputs of the OCB used to send write command to DDR3
// Shift bitslip logic by 1 or 2 clk_mem cycles
// Write calibration currently supports only upto 2 clk_mem cycles
case ({wr_calib_dly[1:0], inv_dqs})
// 0 clk_mem delay required as per write calibration
3'b000: begin
out_d1 <= #TCQ mask_data_fall0_r1;
out_d2 <= #TCQ mask_data_rise1_r1;
out_d3 <= #TCQ mask_data_fall1_r1;
out_d4 <= #TCQ mask_data_rise0;
end
// DQS inverted during write leveling
3'b001: begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end
// 1 clk_mem delay required as per write cal
3'b010: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
// DQS inverted during write leveling
// 1 clk_mem delay required per write cal
3'b011: begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end
// 2 clk_mem delay required as per write cal
3'b100: begin
out_d1 <= #TCQ mask_data_fall0_r2;
out_d2 <= #TCQ mask_data_rise1_r2;
out_d3 <= #TCQ mask_data_fall1_r2;
out_d4 <= #TCQ mask_data_rise0_r1;
end
// DQS inverted during write leveling
// 2 clk_mem delay required as per write cal
3'b101: begin
out_d1 <= #TCQ mask_data_rise0_r2;
out_d2 <= #TCQ mask_data_fall0_r2;
out_d3 <= #TCQ mask_data_rise1_r2;
out_d4 <= #TCQ mask_data_fall1_r2;
end
// 3 clk_mem delay required as per write cal
3'b110: begin
out_d1 <= #TCQ mask_data_fall1_r3;
out_d2 <= #TCQ mask_data_rise0_r2;
out_d3 <= #TCQ mask_data_fall0_r2;
out_d4 <= #TCQ mask_data_rise1_r2;
end
// DQS inverted during write leveling
// 3 clk_mem delay required as per write cal
3'b111: begin
out_d1 <= #TCQ mask_data_rise1_r3;
out_d2 <= #TCQ mask_data_fall1_r3;
out_d3 <= #TCQ mask_data_rise0_r2;
out_d4 <= #TCQ mask_data_fall0_r2;
end
// defaults to 0 clk_mem delay
default: begin
out_d1 <= #TCQ mask_data_fall0_r1;
out_d2 <= #TCQ mask_data_rise1_r1;
out_d3 <= #TCQ mask_data_fall1_r1;
out_d4 <= #TCQ mask_data_rise0;
end
endcase
end
end
end else if ((nCWL == 6) | (nCWL == 8)) begin: gen_dm_ncwl_even
always @(posedge clk) begin
if (WRLVL == "OFF") begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end else begin
// write command sent by MC on channel1
// D3,D4 inputs of the OCB used to send write command to DDR3
// Shift bitslip logic by 1 or 2 clk_mem cycles
// Write calibration currently supports only upto 2 clk_mem cycles
case ({wr_calib_dly[1:0], inv_dqs})
// 0 clk_mem delay required as per write calibration
// could not test 0011 case
3'b000: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
// DQS inverted during write leveling
3'b001: begin
out_d1 <= #TCQ mask_data_rise1_r2;
out_d2 <= #TCQ mask_data_fall1_r2;
out_d3 <= #TCQ mask_data_rise0_r1;
out_d4 <= #TCQ mask_data_fall0_r1;
end
// 1 clk_mem delay required as per write cal
3'b010: begin
out_d1 <= #TCQ mask_data_fall0_r2;
out_d2 <= #TCQ mask_data_rise1_r2;
out_d3 <= #TCQ mask_data_fall1_r2;
out_d4 <= #TCQ mask_data_rise0_r1;
end
// DQS inverted during write leveling
// 1 clk_mem delay required as per write cal
3'b011: begin
out_d1 <= #TCQ mask_data_rise0_r2;
out_d2 <= #TCQ mask_data_fall0_r2;
out_d3 <= #TCQ mask_data_rise1_r2;
out_d4 <= #TCQ mask_data_fall1_r2;
end
// 2 clk_mem delay required as per write cal
3'b100: begin
out_d1 <= #TCQ mask_data_fall1_r3;
out_d2 <= #TCQ mask_data_rise0_r2;
out_d3 <= #TCQ mask_data_fall0_r2;
out_d4 <= #TCQ mask_data_rise1_r2;
end
// DQS inverted during write leveling
// 2 clk_mem delay required as per write cal
3'b101: begin
out_d1 <= #TCQ mask_data_rise1_r3;
out_d2 <= #TCQ mask_data_fall1_r3;
out_d3 <= #TCQ mask_data_rise0_r2;
out_d4 <= #TCQ mask_data_fall0_r2;
end
// 3 clk_mem delay required as per write cal
3'b110: begin
out_d1 <= #TCQ mask_data_fall0_r3;
out_d2 <= #TCQ mask_data_rise1_r3;
out_d3 <= #TCQ mask_data_fall1_r3;
out_d4 <= #TCQ mask_data_rise0_r2;
end
// DQS inverted during write leveling
// 3 clk_mem delay required as per write cal
3'b111: begin
out_d1 <= #TCQ mask_data_rise0_r3;
out_d2 <= #TCQ mask_data_fall0_r3;
out_d3 <= #TCQ mask_data_rise1_r3;
out_d4 <= #TCQ mask_data_fall1_r3;
end
// defaults to 0 clk_mem delay
default: begin
out_d1 <= #TCQ mask_data_fall1_r2;
out_d2 <= #TCQ mask_data_rise0_r1;
out_d3 <= #TCQ mask_data_fall0_r1;
out_d4 <= #TCQ mask_data_rise1_r1;
end
endcase
end
end
end
end else if (DRAM_TYPE == "DDR2") begin: gen_dm_lat_ddr2
if (nCWL == 2) begin: gen_ddr2_ncwl2
always @(mask_data_rise1_r1 or mask_data_fall1_r1 or
mask_data_rise0 or mask_data_fall0) begin
out_d1 = mask_data_rise1_r1;
out_d2 = mask_data_fall1_r1;
out_d3 = mask_data_rise0;
out_d4 = mask_data_fall0;
end
end else if (nCWL == 3) begin: gen_ddr2_ncwl3
always @(posedge clk) begin
out_d1 <= #TCQ mask_data_rise0;
out_d2 <= #TCQ mask_data_fall0;
out_d3 <= #TCQ mask_data_rise1;
out_d4 <= #TCQ mask_data_fall1;
end
end else if (nCWL == 4) begin: gen_ddr2_ncwl4
always @(posedge clk) begin
out_d1 = mask_data_rise1_r1;
out_d2 = mask_data_fall1_r1;
out_d3 = mask_data_rise0;
out_d4 = mask_data_fall0;
end
end else if (nCWL == 5) begin: gen_ddr2_ncwl5
always @(posedge clk) begin
out_d1 <= #TCQ mask_data_rise0_r1;
out_d2 <= #TCQ mask_data_fall0_r1;
out_d3 <= #TCQ mask_data_rise1_r1;
out_d4 <= #TCQ mask_data_fall1_r1;
end
end else if (nCWL == 6) begin: gen_ddr2_ncwl6
always @(posedge clk) begin
out_d1 = mask_data_rise1_r2;
out_d2 = mask_data_fall1_r2;
out_d3 = mask_data_rise0_r1;
out_d4 = mask_data_fall0_r1;
end
end
end
endgenerate
//***************************************************************************
OSERDESE1 #
(
.DATA_RATE_OQ ("DDR"),
.DATA_RATE_TQ ("DDR"),
.DATA_WIDTH (4),
.DDR3_DATA (0),
.INIT_OQ (1'b0),
.INIT_TQ (1'b0),
.INTERFACE_TYPE ("DEFAULT"),
.ODELAY_USED (0),
.SERDES_MODE ("MASTER"),
.SRVAL_OQ (1'b0),
.SRVAL_TQ (1'b0),
.TRISTATE_WIDTH (4)
)
u_oserdes_dm
(
.OCBEXTEND (),
.OFB (),
.OQ (dm_oq),
.SHIFTOUT1 (),
.SHIFTOUT2 (),
.TQ (),
.CLK (clk_mem),
.CLKDIV (clk),
.CLKPERF (),
.CLKPERFDELAY (),
.D1 (out_d1),
.D2 (out_d2),
.D3 (out_d3),
.D4 (out_d4),
.D5 (),
.D6 (),
.OCE (1'b1),
.ODV (1'b0),
.SHIFTIN1 (),
.SHIFTIN2 (),
.RST (rst),
.T1 (1'b0),
.T2 (1'b0),
.T3 (1'b0),
.T4 (1'b0),
.TFB (),
.TCE (1'b1),
.WC (1'b0)
);
// Output of OSERDES drives IODELAY (ODELAY)
(* IODELAY_GROUP = IODELAY_GRP *) IODELAYE1 #
(
.CINVCTRL_SEL ("FALSE"),
.DELAY_SRC ("O"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE ("FIXED"),
.IDELAY_VALUE (0),
.ODELAY_TYPE ("VAR_LOADABLE"),
.ODELAY_VALUE (0),
.REFCLK_FREQUENCY (REFCLK_FREQ),
.SIGNAL_PATTERN ("DATA")
)
u_odelay_dm
(
.DATAOUT (dm_odelay),
.C (clk_rsync),
.CE (1'b0),
.DATAIN (),
.IDATAIN (),
.INC (1'b0),
.ODATAIN (dm_oq),
.RST (1'b1),
.T (),
.CNTVALUEIN (dlyval),
.CNTVALUEOUT (),
.CLKIN (),
.CINVCTRL (1'b0)
);
// Output of ODELAY drives OBUF
OBUF u_obuf_dm
(
.I (dm_odelay),
.O (ddr_dm)
);
endmodule
|
`define ADDR_DEC_W 8 // Number of bits used to decode.
`define ADDR_DEVICE0 `ADDR_DEC_W'h10 // Device 0 located at address 20xx_xxxxh
`define ADDR_DEVICE1 `ADDR_DEC_W'h1F // Device 1 located at address 20xx_xxxxh
module top ( ) ;
// Instantiation of the module
//
child_module #(`ADDR_DEC_W, `ADDR_DEVICE0, `ADDR_DEVICE1) my_module ( );
initial begin
#1 ;
end
endmodule
module child_module ( );
// Parameters:
parameter dec_addr_w = 4 ;
parameter t0_addr = 4'd0 ;
parameter t1_addr = 4'd0 ;
// Instantiation of the grandchild module
//
grandchild_module #(dec_addr_w, t0_addr, t1_addr) my_grandchild_module ( );
initial begin
$display ("CHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
end
endmodule
module grandchild_module ( );
// Parameters:
parameter dec_addr_w = 4 ;
parameter t0_addr = 4'd0 ;
parameter t1_addr = 4'd0 ;
initial begin
$display ("GRANDCHILD parameters are: %h %h %h", dec_addr_w, t0_addr, t1_addr) ;
end
endmodule
|
// bsg_delay_line
//
// new settings are delivered via bsg_tag_i
//
// the clock is designed to be atomically updated
// between any of its values without glitching.
//
// the order of components is:
//
// ADT, CDT, FDT --> feedback (and buffer to outside world)
//
// All three stages invert their outputs.
//
// All of the modules have delay circuits that clock their config
// flops right after the signal has passed through. All of them are
// configured to grab the new value after a negedge enters the beginning of
// of the ADT, but of course since the signal is inverted at each stage
// ADT and FDT do it on posege and CDT does it on negedge.
//
// We employ a MUXI4 that is part of the standard cell library
// that we verify to be glitch-free using spice simulation (presumably because it is based on a
// t-gate design). If the MUXI4 were made out of AND-OR circuits, care
// would have to be taken to make sure that the transitions occur when
// either all inputs are 0 or 1 to the MUXI4, depending on the implementation.
// For example, if the mux is AOI, triggered on negedge edge of input clock would
// be okay. Fortunately, we don't have to worry about this (and confirmed by spice.)
//
// We have verified this in TSMC 40 by running with sdf annotations.
//
// Gen 2 specific info (starting with 40nm) MBT 5-26-2018
//
// This Gen 2 clock generator has been slight redesigned in order to address the races
// in the gen 1 design that prevented automation.
//
// We use the bsg_tag_client_unsync implementation in order to reduce the load on
// the internally generated clock. Additionally, we separate out the we_r trigger
// signal so that it is explicitly set. This means that to set the frequency
// on average, three packets will need to be sent. First, a packet will be sent
// to set clock configuration bits. Then a packet will be sent to enable the we_r
// signal. Finally a packet will be sent to clear the we_r signal.
// This applies only for the oscillator programming.
//
// The trigger is synchronized inside the ADT; and then the synchronized signal
// is buffered and passed on to the CDT and then to the FDT, mirroring the
// flow of the clock signal through the units.
//
// The goal of this approach is to ensure that a new value is latched into the
// oscillator's configuration registers atomically, and during the first negative
// clock phase after a positive edge.
//
//
// The downsampler uses the normal interface.
//
//
// Gen 1 specific info (for reference)
//
// There is an implicit race between the bsg_tag's output fb_we_r (clocked on
// positive edge of FDT output) and these config flops that cannot be addressed
// in ICC because we cannot explicitly control timing between ICC-managed
// clocks and our internal oscillator clocks.
//
// A final check must be made on the 5 flops inside the adt / cdt / fdt
// to see that async reset drops and data inputs do not come too close
// to the appropriate clock edge. This could be verified via a script that
// processes the SDF file, but for now we pull the test trace up in DVE and
// manually check these points. Typically, the ADT is the closest
// call, where in MAX timing mode, the data changes about 481 ps before the
// positive edge of the flop's clock. With a setup time on the order of
// 261 ps, there is a slack of 220 ps. This path was originally a problem
// and it fixed by sending the clock out to the BTC at the beginning of
// the FDT as opposed to at the end. This gives more time for propagate
// through the ICC-generate clock tree for the BTC.
//
//
//
//
`timescale 1ps/1ps
`include "bsg_clk_gen.vh"
module bsg_dly_line
import bsg_tag_pkg::bsg_tag_s;
#(parameter num_adgs_p=1)
(
input bsg_tag_s bsg_tag_i
,input bsg_tag_s bsg_tag_trigger_i
,input async_reset_i
,input clk_i
,output clk_o
);
wire fb_clk;
wire async_reset_neg = ~async_reset_i;
`declare_bsg_clk_gen_osc_tag_payload_s(num_adgs_p)
bsg_clk_gen_osc_tag_payload_s tag_r_async;
wire tag_trigger_r_async;
wire adt_to_cdt_trigger_lo, cdt_to_fdt_trigger_lo;
// this is a raw interface; and wires will toggle
// as the bits shift in. the wires are also
// unsynchronized with respect to the target domain.
bsg_tag_client_unsync
#(.width_p($bits(bsg_clk_gen_osc_tag_payload_s))
,.harden_p(1)
) btc
(.bsg_tag_i(bsg_tag_i)
,.data_async_r_o(tag_r_async)
);
bsg_tag_client_unsync
#(.width_p(1)
,.harden_p(1)
) btc_trigger
(.bsg_tag_i(bsg_tag_trigger_i)
,.data_async_r_o(tag_trigger_r_async)
);
wire adt_lo, cdt_lo;
wire fb_clk_del;
// this adds some delay in the loop for RTL simulation
// should be ignored in synthesis
assign #4000 fb_clk_del = fb_clk;
wire clk_inv;
assign clk_inv = ~clk_i;
bsg_rp_clk_gen_atomic_delay_tuner adt
(.i(clk_inv)
,.we_async_i (tag_trigger_r_async )
,.we_inited_i(bsg_tag_trigger_i.en )
,.async_reset_neg_i(async_reset_neg )
,.sel_i(tag_r_async.adg[0] )
,.we_o(adt_to_cdt_trigger_lo )
,.o(adt_lo )
);
// instantatiate CDT (coarse delay tuner)
// this one inverts the output
// captures config state on negative edge of input clock
bsg_rp_clk_gen_coarse_delay_tuner cdt
(.i (adt_lo)
,.we_i (adt_to_cdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg )
,.sel_i (tag_r_async.cdt )
,.we_o (cdt_to_fdt_trigger_lo)
,.o (cdt_lo)
);
// instantiate FDT (fine delay tuner)
// captures config state on positive edge of (inverted) input clk
// non-inverting
bsg_rp_clk_gen_fine_delay_tuner fdt
(.i (cdt_lo)
,.we_i (cdt_to_fdt_trigger_lo)
,.async_reset_neg_i(async_reset_neg)
,.sel_i (tag_r_async.fdt)
,.o (fb_clk) // in the actual critical loop
,.buf_o (clk_o) // outside this module
);
//always @(*)
// $display("%m async_reset_neg=%b fb_clk=%b adg_int=%b fb_tag_r=%b fb_we_r=%b",
// async_reset_neg,fb_clk,adg_int,fb_tag_r,fb_we_r);
endmodule // bsg_clk_gen_osc
`BSG_ABSTRACT_MODULE(bsg_dly_line)
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*
Copyright (C) 2014 Adapteva, Inc.
Contributed by Fred Huettig <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.This program is distributed in the hope
that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details. You should have received a copy
of the GNU General Public License along with this program (see the file
COPYING). If not, see <http://www.gnu.org/licenses/>.
*/
`timescale 1ns/10ps
module tb_elink2 ();
//Parallella Master parameters (connect to test slave)
parameter MIDW = 6; //ID Width
parameter MAW = 32; //Address Bus Width
parameter MDW = 64; //Data Bus Width
parameter MSTW = 8; //Number of strobes
//Parallella Slave parameters (connect to test master)
parameter SIDW = 12; //ID Width
parameter SAW = 32; //Address Bus Width
parameter SDW = 32; //Data Bus Width
parameter SSTW = 8; //Number of strobes
parameter CLOCKPERIOD = 10;
reg clock;
reg resetn;
wire reset = ~resetn;
initial begin
clock <= 1'b0;
resetn <= 1'b0;
#50 resetn <= 1'b1;
end
always
#(CLOCKPERIOD/2.0) clock <= ~clock;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [3:0] DONE; // From maxi_gold of maxi_test.v, ...
wire [3:0] ERROR; // From maxi_gold of maxi_test.v, ...
wire d2g_cclk_n; // From golden of parallella.v
wire d2g_cclk_p; // From golden of parallella.v
wire [7:0] d2g_data_n; // From dut of parallella.v
wire [7:0] d2g_data_p; // From dut of parallella.v
wire d2g_frame_n; // From dut of parallella.v
wire d2g_frame_p; // From dut of parallella.v
wire d2g_lclk_n; // From dut of parallella.v
wire d2g_lclk_p; // From dut of parallella.v
wire d2g_rd_wait_n; // From golden of parallella.v
wire d2g_rd_wait_p; // From golden of parallella.v
wire d2g_wr_wait_n; // From golden of parallella.v
wire d2g_wr_wait_p; // From golden of parallella.v
wire [MAW-1:0] dut_emaxi_araddr; // From dut of parallella.v
wire [1:0] dut_emaxi_arburst; // From dut of parallella.v
wire [3:0] dut_emaxi_arcache; // From dut of parallella.v
wire [MIDW-1:0] dut_emaxi_arid; // From dut of parallella.v
wire [3:0] dut_emaxi_arlen; // From dut of parallella.v
wire [1:0] dut_emaxi_arlock; // From dut of parallella.v
wire [2:0] dut_emaxi_arprot; // From dut of parallella.v
wire [3:0] dut_emaxi_arqos; // From dut of parallella.v
wire dut_emaxi_arready; // From saxi_dut of saxi_test.v
wire [2:0] dut_emaxi_arsize; // From dut of parallella.v
wire dut_emaxi_arvalid; // From dut of parallella.v
wire [MAW-1:0] dut_emaxi_awaddr; // From dut of parallella.v
wire [1:0] dut_emaxi_awburst; // From dut of parallella.v
wire [3:0] dut_emaxi_awcache; // From dut of parallella.v
wire [MIDW-1:0] dut_emaxi_awid; // From dut of parallella.v
wire [3:0] dut_emaxi_awlen; // From dut of parallella.v
wire [1:0] dut_emaxi_awlock; // From dut of parallella.v
wire [2:0] dut_emaxi_awprot; // From dut of parallella.v
wire [3:0] dut_emaxi_awqos; // From dut of parallella.v
wire dut_emaxi_awready; // From saxi_dut of saxi_test.v
wire [2:0] dut_emaxi_awsize; // From dut of parallella.v
wire dut_emaxi_awvalid; // From dut of parallella.v
wire [MIDW-1:0] dut_emaxi_bid; // From saxi_dut of saxi_test.v
wire dut_emaxi_bready; // From dut of parallella.v
wire [1:0] dut_emaxi_bresp; // From saxi_dut of saxi_test.v
wire dut_emaxi_bvalid; // From saxi_dut of saxi_test.v
wire [MDW-1:0] dut_emaxi_rdata; // From saxi_dut of saxi_test.v
wire [MIDW-1:0] dut_emaxi_rid; // From saxi_dut of saxi_test.v
wire dut_emaxi_rlast; // From saxi_dut of saxi_test.v
wire dut_emaxi_rready; // From dut of parallella.v
wire [1:0] dut_emaxi_rresp; // From saxi_dut of saxi_test.v
wire dut_emaxi_rvalid; // From saxi_dut of saxi_test.v
wire [MDW-1:0] dut_emaxi_wdata; // From dut of parallella.v
wire [MIDW-1:0] dut_emaxi_wid; // From dut of parallella.v
wire dut_emaxi_wlast; // From dut of parallella.v
wire dut_emaxi_wready; // From saxi_dut of saxi_test.v
wire [MSTW-1:0] dut_emaxi_wstrb; // From dut of parallella.v
wire dut_emaxi_wvalid; // From dut of parallella.v
wire [SAW-1:0] dut_esaxi_araddr; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_arburst; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_arcache; // From maxi_dut of maxi_test.v
wire [SIDW-1:0] dut_esaxi_arid; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_arlen; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_arlock; // From maxi_dut of maxi_test.v
wire [2:0] dut_esaxi_arprot; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_arqos; // From maxi_dut of maxi_test.v
wire dut_esaxi_arready; // From dut of parallella.v
wire [2:0] dut_esaxi_arsize; // From maxi_dut of maxi_test.v
wire dut_esaxi_arvalid; // From maxi_dut of maxi_test.v
wire [SAW-1:0] dut_esaxi_awaddr; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_awburst; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_awcache; // From maxi_dut of maxi_test.v
wire [SIDW-1:0] dut_esaxi_awid; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_awlen; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_awlock; // From maxi_dut of maxi_test.v
wire [2:0] dut_esaxi_awprot; // From maxi_dut of maxi_test.v
wire [3:0] dut_esaxi_awqos; // From maxi_dut of maxi_test.v
wire dut_esaxi_awready; // From dut of parallella.v
wire [2:0] dut_esaxi_awsize; // From maxi_dut of maxi_test.v
wire dut_esaxi_awvalid; // From maxi_dut of maxi_test.v
wire [SIDW-1:0] dut_esaxi_bid; // From dut of parallella.v
wire dut_esaxi_bready; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_bresp; // From dut of parallella.v
wire dut_esaxi_bvalid; // From dut of parallella.v
wire [SDW-1:0] dut_esaxi_rdata; // From dut of parallella.v
wire [SIDW-1:0] dut_esaxi_rid; // From dut of parallella.v
wire dut_esaxi_rlast; // From dut of parallella.v
wire dut_esaxi_rready; // From maxi_dut of maxi_test.v
wire [1:0] dut_esaxi_rresp; // From dut of parallella.v
wire dut_esaxi_rvalid; // From dut of parallella.v
wire [SDW-1:0] dut_esaxi_wdata; // From maxi_dut of maxi_test.v
wire [SIDW-1:0] dut_esaxi_wid; // From maxi_dut of maxi_test.v
wire dut_esaxi_wlast; // From maxi_dut of maxi_test.v
wire dut_esaxi_wready; // From dut of parallella.v
wire [SSTW-1:0] dut_esaxi_wstrb; // From maxi_dut of maxi_test.v
wire dut_esaxi_wvalid; // From maxi_dut of maxi_test.v
wire g2d_cclk_n; // From dut of parallella.v
wire g2d_cclk_p; // From dut of parallella.v
wire [7:0] g2d_data_n; // From golden of parallella.v
wire [7:0] g2d_data_p; // From golden of parallella.v
wire g2d_frame_n; // From golden of parallella.v
wire g2d_frame_p; // From golden of parallella.v
wire g2d_lclk_n; // From golden of parallella.v
wire g2d_lclk_p; // From golden of parallella.v
wire g2d_rd_wait_n; // From dut of parallella.v
wire g2d_rd_wait_p; // From dut of parallella.v
wire g2d_wr_wait_n; // From dut of parallella.v
wire g2d_wr_wait_p; // From dut of parallella.v
wire [MAW-1:0] gold_emaxi_araddr; // From golden of parallella.v
wire [1:0] gold_emaxi_arburst; // From golden of parallella.v
wire [3:0] gold_emaxi_arcache; // From golden of parallella.v
wire [MIDW-1:0] gold_emaxi_arid; // From golden of parallella.v
wire [3:0] gold_emaxi_arlen; // From golden of parallella.v
wire [1:0] gold_emaxi_arlock; // From golden of parallella.v
wire [2:0] gold_emaxi_arprot; // From golden of parallella.v
wire [3:0] gold_emaxi_arqos; // From golden of parallella.v
wire gold_emaxi_arready; // From saxi_gold of saxi_test.v
wire [2:0] gold_emaxi_arsize; // From golden of parallella.v
wire gold_emaxi_arvalid; // From golden of parallella.v
wire [MAW-1:0] gold_emaxi_awaddr; // From golden of parallella.v
wire [1:0] gold_emaxi_awburst; // From golden of parallella.v
wire [3:0] gold_emaxi_awcache; // From golden of parallella.v
wire [MIDW-1:0] gold_emaxi_awid; // From golden of parallella.v
wire [3:0] gold_emaxi_awlen; // From golden of parallella.v
wire [1:0] gold_emaxi_awlock; // From golden of parallella.v
wire [2:0] gold_emaxi_awprot; // From golden of parallella.v
wire [3:0] gold_emaxi_awqos; // From golden of parallella.v
wire gold_emaxi_awready; // From saxi_gold of saxi_test.v
wire [2:0] gold_emaxi_awsize; // From golden of parallella.v
wire gold_emaxi_awvalid; // From golden of parallella.v
wire [MIDW-1:0] gold_emaxi_bid; // From saxi_gold of saxi_test.v
wire gold_emaxi_bready; // From golden of parallella.v
wire [1:0] gold_emaxi_bresp; // From saxi_gold of saxi_test.v
wire gold_emaxi_bvalid; // From saxi_gold of saxi_test.v
wire [MDW-1:0] gold_emaxi_rdata; // From saxi_gold of saxi_test.v
wire [MIDW-1:0] gold_emaxi_rid; // From saxi_gold of saxi_test.v
wire gold_emaxi_rlast; // From saxi_gold of saxi_test.v
wire gold_emaxi_rready; // From golden of parallella.v
wire [1:0] gold_emaxi_rresp; // From saxi_gold of saxi_test.v
wire gold_emaxi_rvalid; // From saxi_gold of saxi_test.v
wire [MDW-1:0] gold_emaxi_wdata; // From golden of parallella.v
wire [MIDW-1:0] gold_emaxi_wid; // From golden of parallella.v
wire gold_emaxi_wlast; // From golden of parallella.v
wire gold_emaxi_wready; // From saxi_gold of saxi_test.v
wire [MSTW-1:0] gold_emaxi_wstrb; // From golden of parallella.v
wire gold_emaxi_wvalid; // From golden of parallella.v
wire [SAW-1:0] gold_esaxi_araddr; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_arburst; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_arcache; // From maxi_gold of maxi_test.v
wire [SIDW-1:0] gold_esaxi_arid; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_arlen; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_arlock; // From maxi_gold of maxi_test.v
wire [2:0] gold_esaxi_arprot; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_arqos; // From maxi_gold of maxi_test.v
wire gold_esaxi_arready; // From golden of parallella.v
wire [2:0] gold_esaxi_arsize; // From maxi_gold of maxi_test.v
wire gold_esaxi_arvalid; // From maxi_gold of maxi_test.v
wire [SAW-1:0] gold_esaxi_awaddr; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_awburst; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_awcache; // From maxi_gold of maxi_test.v
wire [SIDW-1:0] gold_esaxi_awid; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_awlen; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_awlock; // From maxi_gold of maxi_test.v
wire [2:0] gold_esaxi_awprot; // From maxi_gold of maxi_test.v
wire [3:0] gold_esaxi_awqos; // From maxi_gold of maxi_test.v
wire gold_esaxi_awready; // From golden of parallella.v
wire [2:0] gold_esaxi_awsize; // From maxi_gold of maxi_test.v
wire gold_esaxi_awvalid; // From maxi_gold of maxi_test.v
wire [SIDW-1:0] gold_esaxi_bid; // From golden of parallella.v
wire gold_esaxi_bready; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_bresp; // From golden of parallella.v
wire gold_esaxi_bvalid; // From golden of parallella.v
wire [SDW-1:0] gold_esaxi_rdata; // From golden of parallella.v
wire [SIDW-1:0] gold_esaxi_rid; // From golden of parallella.v
wire gold_esaxi_rlast; // From golden of parallella.v
wire gold_esaxi_rready; // From maxi_gold of maxi_test.v
wire [1:0] gold_esaxi_rresp; // From golden of parallella.v
wire gold_esaxi_rvalid; // From golden of parallella.v
wire [SDW-1:0] gold_esaxi_wdata; // From maxi_gold of maxi_test.v
wire [SIDW-1:0] gold_esaxi_wid; // From maxi_gold of maxi_test.v
wire gold_esaxi_wlast; // From maxi_gold of maxi_test.v
wire gold_esaxi_wready; // From golden of parallella.v
wire [SSTW-1:0] gold_esaxi_wstrb; // From maxi_gold of maxi_test.v
wire gold_esaxi_wvalid; // From maxi_gold of maxi_test.v
// End of automatics
/* maxi_test AUTO_TEMPLATE(
.ERROR (ERROR[0]),
.DONE (DONE[0]),
..*_aclk (clock),
..*_aresetn (resetn),
.m_axi\(.*\) (gold_esaxi\1[]),
); */
maxi_test
#(/*AUTOINSTPARAM*/
// Parameters
.SIDW (SIDW),
.SAW (SAW),
.SDW (SDW),
.SSTW (SSTW))
maxi_gold
(/*AUTOINST*/
// Outputs
.ERROR (ERROR[0]), // Templated
.DONE (DONE[0]), // Templated
.m_axi_awid (gold_esaxi_awid[SIDW-1:0]), // Templated
.m_axi_awaddr (gold_esaxi_awaddr[SAW-1:0]), // Templated
.m_axi_awlen (gold_esaxi_awlen[3:0]), // Templated
.m_axi_awsize (gold_esaxi_awsize[2:0]), // Templated
.m_axi_awburst (gold_esaxi_awburst[1:0]), // Templated
.m_axi_awlock (gold_esaxi_awlock[1:0]), // Templated
.m_axi_awcache (gold_esaxi_awcache[3:0]), // Templated
.m_axi_awprot (gold_esaxi_awprot[2:0]), // Templated
.m_axi_awvalid (gold_esaxi_awvalid), // Templated
.m_axi_awqos (gold_esaxi_awqos[3:0]), // Templated
.m_axi_wid (gold_esaxi_wid[SIDW-1:0]), // Templated
.m_axi_wdata (gold_esaxi_wdata[SDW-1:0]), // Templated
.m_axi_wstrb (gold_esaxi_wstrb[SSTW-1:0]), // Templated
.m_axi_wlast (gold_esaxi_wlast), // Templated
.m_axi_wvalid (gold_esaxi_wvalid), // Templated
.m_axi_bready (gold_esaxi_bready), // Templated
.m_axi_arid (gold_esaxi_arid[SIDW-1:0]), // Templated
.m_axi_araddr (gold_esaxi_araddr[SAW-1:0]), // Templated
.m_axi_arlen (gold_esaxi_arlen[3:0]), // Templated
.m_axi_arsize (gold_esaxi_arsize[2:0]), // Templated
.m_axi_arburst (gold_esaxi_arburst[1:0]), // Templated
.m_axi_arlock (gold_esaxi_arlock[1:0]), // Templated
.m_axi_arcache (gold_esaxi_arcache[3:0]), // Templated
.m_axi_arprot (gold_esaxi_arprot[2:0]), // Templated
.m_axi_arvalid (gold_esaxi_arvalid), // Templated
.m_axi_arqos (gold_esaxi_arqos[3:0]), // Templated
.m_axi_rready (gold_esaxi_rready), // Templated
// Inputs
.m_axi_aclk (clock), // Templated
.m_axi_aresetn (resetn), // Templated
.m_axi_awready (gold_esaxi_awready), // Templated
.m_axi_wready (gold_esaxi_wready), // Templated
.m_axi_bid (gold_esaxi_bid[SIDW-1:0]), // Templated
.m_axi_bresp (gold_esaxi_bresp[1:0]), // Templated
.m_axi_bvalid (gold_esaxi_bvalid), // Templated
.m_axi_arready (gold_esaxi_arready), // Templated
.m_axi_rid (gold_esaxi_rid[SIDW-1:0]), // Templated
.m_axi_rdata (gold_esaxi_rdata[SDW-1:0]), // Templated
.m_axi_rresp (gold_esaxi_rresp[1:0]), // Templated
.m_axi_rlast (gold_esaxi_rlast), // Templated
.m_axi_rvalid (gold_esaxi_rvalid)); // Templated
/* saxi_test AUTO_TEMPLATE(
.ERROR (ERROR[1]),
.DONE (DONE[1]),
..*_aclk (clock),
..*_aresetn (resetn),
.s_axi\(.*\) (gold_emaxi\1[]),
); */
saxi_test
#(/*AUTOINSTPARAM*/
// Parameters
.MIDW (MIDW),
.MAW (MAW),
.MDW (MDW),
.MSTW (MSTW))
saxi_gold
(/*AUTOINST*/
// Outputs
.ERROR (ERROR[1]), // Templated
.DONE (DONE[1]), // Templated
.s_axi_awready (gold_emaxi_awready), // Templated
.s_axi_wready (gold_emaxi_wready), // Templated
.s_axi_bid (gold_emaxi_bid[MIDW-1:0]), // Templated
.s_axi_bresp (gold_emaxi_bresp[1:0]), // Templated
.s_axi_bvalid (gold_emaxi_bvalid), // Templated
.s_axi_arready (gold_emaxi_arready), // Templated
.s_axi_rid (gold_emaxi_rid[MIDW-1:0]), // Templated
.s_axi_rdata (gold_emaxi_rdata[MDW-1:0]), // Templated
.s_axi_rresp (gold_emaxi_rresp[1:0]), // Templated
.s_axi_rlast (gold_emaxi_rlast), // Templated
.s_axi_rvalid (gold_emaxi_rvalid), // Templated
// Inputs
.s_axi_aclk (clock), // Templated
.s_axi_aresetn (resetn), // Templated
.s_axi_awid (gold_emaxi_awid[MIDW-1:0]), // Templated
.s_axi_awaddr (gold_emaxi_awaddr[MAW-1:0]), // Templated
.s_axi_awlen (gold_emaxi_awlen[3:0]), // Templated
.s_axi_awsize (gold_emaxi_awsize[2:0]), // Templated
.s_axi_awburst (gold_emaxi_awburst[1:0]), // Templated
.s_axi_awlock (gold_emaxi_awlock[1:0]), // Templated
.s_axi_awcache (gold_emaxi_awcache[3:0]), // Templated
.s_axi_awprot (gold_emaxi_awprot[2:0]), // Templated
.s_axi_awvalid (gold_emaxi_awvalid), // Templated
.s_axi_awqos (gold_emaxi_awqos[3:0]), // Templated
.s_axi_wid (gold_emaxi_wid[MIDW-1:0]), // Templated
.s_axi_wdata (gold_emaxi_wdata[MDW-1:0]), // Templated
.s_axi_wstrb (gold_emaxi_wstrb[MSTW-1:0]), // Templated
.s_axi_wlast (gold_emaxi_wlast), // Templated
.s_axi_wvalid (gold_emaxi_wvalid), // Templated
.s_axi_bready (gold_emaxi_bready), // Templated
.s_axi_arid (gold_emaxi_arid[MIDW-1:0]), // Templated
.s_axi_araddr (gold_emaxi_araddr[MAW-1:0]), // Templated
.s_axi_arlen (gold_emaxi_arlen[3:0]), // Templated
.s_axi_arsize (gold_emaxi_arsize[2:0]), // Templated
.s_axi_arburst (gold_emaxi_arburst[1:0]), // Templated
.s_axi_arlock (gold_emaxi_arlock[1:0]), // Templated
.s_axi_arcache (gold_emaxi_arcache[3:0]), // Templated
.s_axi_arprot (gold_emaxi_arprot[2:0]), // Templated
.s_axi_arvalid (gold_emaxi_arvalid), // Templated
.s_axi_arqos (gold_emaxi_arqos[3:0]), // Templated
.s_axi_rready (gold_emaxi_rready)); // Templated
/* parallella AUTO_TEMPLATE(
..*_aclk (clock),
..*_aresetn (resetn),
.tx[io]\(.*\) (g2d\1[]),
.rx[io]\(.*\) (d2g\1[]),
.emaxi\(.*\) (gold_emaxi\1[]),
.esaxi\(.*\) (gold_esaxi\1[]),
); */
// Reference module
parallella golden
(
.csysack (),
.csysreq (1'b0),
.cactive (),
.reset_chip (),
.reset_fpga (),
.clkin_100 (clock),
/*AUTOINST*/
// Outputs
.txo_data_p (g2d_data_p[7:0]), // Templated
.txo_data_n (g2d_data_n[7:0]), // Templated
.txo_frame_p (g2d_frame_p), // Templated
.txo_frame_n (g2d_frame_n), // Templated
.txo_lclk_p (g2d_lclk_p), // Templated
.txo_lclk_n (g2d_lclk_n), // Templated
.rxo_wr_wait_p (d2g_wr_wait_p), // Templated
.rxo_wr_wait_n (d2g_wr_wait_n), // Templated
.rxo_rd_wait_p (d2g_rd_wait_p), // Templated
.rxo_rd_wait_n (d2g_rd_wait_n), // Templated
.rxi_cclk_p (d2g_cclk_p), // Templated
.rxi_cclk_n (d2g_cclk_n), // Templated
.emaxi_awid (gold_emaxi_awid[MIDW-1:0]), // Templated
.emaxi_awaddr (gold_emaxi_awaddr[MAW-1:0]), // Templated
.emaxi_awlen (gold_emaxi_awlen[3:0]), // Templated
.emaxi_awsize (gold_emaxi_awsize[2:0]), // Templated
.emaxi_awburst (gold_emaxi_awburst[1:0]), // Templated
.emaxi_awlock (gold_emaxi_awlock[1:0]), // Templated
.emaxi_awcache (gold_emaxi_awcache[3:0]), // Templated
.emaxi_awprot (gold_emaxi_awprot[2:0]), // Templated
.emaxi_awvalid (gold_emaxi_awvalid), // Templated
.esaxi_awready (gold_esaxi_awready), // Templated
.emaxi_wid (gold_emaxi_wid[MIDW-1:0]), // Templated
.emaxi_wdata (gold_emaxi_wdata[MDW-1:0]), // Templated
.emaxi_wstrb (gold_emaxi_wstrb[MSTW-1:0]), // Templated
.emaxi_wlast (gold_emaxi_wlast), // Templated
.emaxi_wvalid (gold_emaxi_wvalid), // Templated
.esaxi_wready (gold_esaxi_wready), // Templated
.emaxi_bready (gold_emaxi_bready), // Templated
.esaxi_bid (gold_esaxi_bid[SIDW-1:0]), // Templated
.esaxi_bresp (gold_esaxi_bresp[1:0]), // Templated
.esaxi_bvalid (gold_esaxi_bvalid), // Templated
.emaxi_arid (gold_emaxi_arid[MIDW-1:0]), // Templated
.emaxi_araddr (gold_emaxi_araddr[MAW-1:0]), // Templated
.emaxi_arlen (gold_emaxi_arlen[3:0]), // Templated
.emaxi_arsize (gold_emaxi_arsize[2:0]), // Templated
.emaxi_arburst (gold_emaxi_arburst[1:0]), // Templated
.emaxi_arlock (gold_emaxi_arlock[1:0]), // Templated
.emaxi_arcache (gold_emaxi_arcache[3:0]), // Templated
.emaxi_arprot (gold_emaxi_arprot[2:0]), // Templated
.emaxi_arvalid (gold_emaxi_arvalid), // Templated
.esaxi_arready (gold_esaxi_arready), // Templated
.emaxi_rready (gold_emaxi_rready), // Templated
.esaxi_rid (gold_esaxi_rid[SIDW-1:0]), // Templated
.esaxi_rdata (gold_esaxi_rdata[SDW-1:0]), // Templated
.esaxi_rresp (gold_esaxi_rresp[1:0]), // Templated
.esaxi_rlast (gold_esaxi_rlast), // Templated
.esaxi_rvalid (gold_esaxi_rvalid), // Templated
.emaxi_awqos (gold_emaxi_awqos[3:0]), // Templated
.emaxi_arqos (gold_emaxi_arqos[3:0]), // Templated
// Inputs
.esaxi_aclk (clock), // Templated
.emaxi_aclk (clock), // Templated
.reset (reset),
.esaxi_aresetn (resetn), // Templated
.emaxi_aresetn (resetn), // Templated
.rxi_data_p (d2g_data_p[7:0]), // Templated
.rxi_data_n (d2g_data_n[7:0]), // Templated
.rxi_frame_p (d2g_frame_p), // Templated
.rxi_frame_n (d2g_frame_n), // Templated
.rxi_lclk_p (d2g_lclk_p), // Templated
.rxi_lclk_n (d2g_lclk_n), // Templated
.txi_wr_wait_p (g2d_wr_wait_p), // Templated
.txi_wr_wait_n (g2d_wr_wait_n), // Templated
.txi_rd_wait_p (g2d_rd_wait_p), // Templated
.txi_rd_wait_n (g2d_rd_wait_n), // Templated
.emaxi_awready (gold_emaxi_awready), // Templated
.esaxi_awid (gold_esaxi_awid[SIDW-1:0]), // Templated
.esaxi_awaddr (gold_esaxi_awaddr[MAW-1:0]), // Templated
.esaxi_awlen (gold_esaxi_awlen[3:0]), // Templated
.esaxi_awsize (gold_esaxi_awsize[2:0]), // Templated
.esaxi_awburst (gold_esaxi_awburst[1:0]), // Templated
.esaxi_awlock (gold_esaxi_awlock[1:0]), // Templated
.esaxi_awcache (gold_esaxi_awcache[3:0]), // Templated
.esaxi_awprot (gold_esaxi_awprot[2:0]), // Templated
.esaxi_awvalid (gold_esaxi_awvalid), // Templated
.emaxi_wready (gold_emaxi_wready), // Templated
.esaxi_wid (gold_esaxi_wid[SIDW-1:0]), // Templated
.esaxi_wdata (gold_esaxi_wdata[SDW-1:0]), // Templated
.esaxi_wstrb (gold_esaxi_wstrb[SSTW-1:0]), // Templated
.esaxi_wlast (gold_esaxi_wlast), // Templated
.esaxi_wvalid (gold_esaxi_wvalid), // Templated
.emaxi_bid (gold_emaxi_bid[MIDW-1:0]), // Templated
.emaxi_bresp (gold_emaxi_bresp[1:0]), // Templated
.emaxi_bvalid (gold_emaxi_bvalid), // Templated
.esaxi_bready (gold_esaxi_bready), // Templated
.emaxi_arready (gold_emaxi_arready), // Templated
.esaxi_arid (gold_esaxi_arid[SIDW-1:0]), // Templated
.esaxi_araddr (gold_esaxi_araddr[MAW-1:0]), // Templated
.esaxi_arlen (gold_esaxi_arlen[3:0]), // Templated
.esaxi_arsize (gold_esaxi_arsize[2:0]), // Templated
.esaxi_arburst (gold_esaxi_arburst[1:0]), // Templated
.esaxi_arlock (gold_esaxi_arlock[1:0]), // Templated
.esaxi_arcache (gold_esaxi_arcache[3:0]), // Templated
.esaxi_arprot (gold_esaxi_arprot[2:0]), // Templated
.esaxi_arvalid (gold_esaxi_arvalid), // Templated
.emaxi_rid (gold_emaxi_rid[MIDW-1:0]), // Templated
.emaxi_rdata (gold_emaxi_rdata[MDW-1:0]), // Templated
.emaxi_rresp (gold_emaxi_rresp[1:0]), // Templated
.emaxi_rlast (gold_emaxi_rlast), // Templated
.emaxi_rvalid (gold_emaxi_rvalid), // Templated
.esaxi_rready (gold_esaxi_rready), // Templated
.esaxi_awqos (gold_esaxi_awqos[3:0]), // Templated
.esaxi_arqos (gold_esaxi_arqos[3:0])); // Templated
/* parallella AUTO_TEMPLATE(
..*_aclk (clock),
..*_aresetn (resetn),
.tx[io]\(.*\) (d2g\1[]),
.rx[io]\(.*\) (g2d\1[]),
.emaxi\(.*\) (dut_emaxi\1[]),
.esaxi\(.*\) (dut_esaxi\1[]),
); */
parallella dut
(
.csysack (),
.csysreq (1'b0),
.cactive (),
.reset_chip (),
.reset_fpga (),
.clkin_100 (clock),
/*AUTOINST*/
// Outputs
.txo_data_p (d2g_data_p[7:0]), // Templated
.txo_data_n (d2g_data_n[7:0]), // Templated
.txo_frame_p (d2g_frame_p), // Templated
.txo_frame_n (d2g_frame_n), // Templated
.txo_lclk_p (d2g_lclk_p), // Templated
.txo_lclk_n (d2g_lclk_n), // Templated
.rxo_wr_wait_p (g2d_wr_wait_p), // Templated
.rxo_wr_wait_n (g2d_wr_wait_n), // Templated
.rxo_rd_wait_p (g2d_rd_wait_p), // Templated
.rxo_rd_wait_n (g2d_rd_wait_n), // Templated
.rxi_cclk_p (g2d_cclk_p), // Templated
.rxi_cclk_n (g2d_cclk_n), // Templated
.emaxi_awid (dut_emaxi_awid[MIDW-1:0]), // Templated
.emaxi_awaddr (dut_emaxi_awaddr[MAW-1:0]), // Templated
.emaxi_awlen (dut_emaxi_awlen[3:0]), // Templated
.emaxi_awsize (dut_emaxi_awsize[2:0]), // Templated
.emaxi_awburst (dut_emaxi_awburst[1:0]), // Templated
.emaxi_awlock (dut_emaxi_awlock[1:0]), // Templated
.emaxi_awcache (dut_emaxi_awcache[3:0]), // Templated
.emaxi_awprot (dut_emaxi_awprot[2:0]), // Templated
.emaxi_awvalid (dut_emaxi_awvalid), // Templated
.esaxi_awready (dut_esaxi_awready), // Templated
.emaxi_wid (dut_emaxi_wid[MIDW-1:0]), // Templated
.emaxi_wdata (dut_emaxi_wdata[MDW-1:0]), // Templated
.emaxi_wstrb (dut_emaxi_wstrb[MSTW-1:0]), // Templated
.emaxi_wlast (dut_emaxi_wlast), // Templated
.emaxi_wvalid (dut_emaxi_wvalid), // Templated
.esaxi_wready (dut_esaxi_wready), // Templated
.emaxi_bready (dut_emaxi_bready), // Templated
.esaxi_bid (dut_esaxi_bid[SIDW-1:0]), // Templated
.esaxi_bresp (dut_esaxi_bresp[1:0]), // Templated
.esaxi_bvalid (dut_esaxi_bvalid), // Templated
.emaxi_arid (dut_emaxi_arid[MIDW-1:0]), // Templated
.emaxi_araddr (dut_emaxi_araddr[MAW-1:0]), // Templated
.emaxi_arlen (dut_emaxi_arlen[3:0]), // Templated
.emaxi_arsize (dut_emaxi_arsize[2:0]), // Templated
.emaxi_arburst (dut_emaxi_arburst[1:0]), // Templated
.emaxi_arlock (dut_emaxi_arlock[1:0]), // Templated
.emaxi_arcache (dut_emaxi_arcache[3:0]), // Templated
.emaxi_arprot (dut_emaxi_arprot[2:0]), // Templated
.emaxi_arvalid (dut_emaxi_arvalid), // Templated
.esaxi_arready (dut_esaxi_arready), // Templated
.emaxi_rready (dut_emaxi_rready), // Templated
.esaxi_rid (dut_esaxi_rid[SIDW-1:0]), // Templated
.esaxi_rdata (dut_esaxi_rdata[SDW-1:0]), // Templated
.esaxi_rresp (dut_esaxi_rresp[1:0]), // Templated
.esaxi_rlast (dut_esaxi_rlast), // Templated
.esaxi_rvalid (dut_esaxi_rvalid), // Templated
.emaxi_awqos (dut_emaxi_awqos[3:0]), // Templated
.emaxi_arqos (dut_emaxi_arqos[3:0]), // Templated
// Inputs
.esaxi_aclk (clock), // Templated
.emaxi_aclk (clock), // Templated
.reset (reset),
.esaxi_aresetn (resetn), // Templated
.emaxi_aresetn (resetn), // Templated
.rxi_data_p (g2d_data_p[7:0]), // Templated
.rxi_data_n (g2d_data_n[7:0]), // Templated
.rxi_frame_p (g2d_frame_p), // Templated
.rxi_frame_n (g2d_frame_n), // Templated
.rxi_lclk_p (g2d_lclk_p), // Templated
.rxi_lclk_n (g2d_lclk_n), // Templated
.txi_wr_wait_p (d2g_wr_wait_p), // Templated
.txi_wr_wait_n (d2g_wr_wait_n), // Templated
.txi_rd_wait_p (d2g_rd_wait_p), // Templated
.txi_rd_wait_n (d2g_rd_wait_n), // Templated
.emaxi_awready (dut_emaxi_awready), // Templated
.esaxi_awid (dut_esaxi_awid[SIDW-1:0]), // Templated
.esaxi_awaddr (dut_esaxi_awaddr[MAW-1:0]), // Templated
.esaxi_awlen (dut_esaxi_awlen[3:0]), // Templated
.esaxi_awsize (dut_esaxi_awsize[2:0]), // Templated
.esaxi_awburst (dut_esaxi_awburst[1:0]), // Templated
.esaxi_awlock (dut_esaxi_awlock[1:0]), // Templated
.esaxi_awcache (dut_esaxi_awcache[3:0]), // Templated
.esaxi_awprot (dut_esaxi_awprot[2:0]), // Templated
.esaxi_awvalid (dut_esaxi_awvalid), // Templated
.emaxi_wready (dut_emaxi_wready), // Templated
.esaxi_wid (dut_esaxi_wid[SIDW-1:0]), // Templated
.esaxi_wdata (dut_esaxi_wdata[SDW-1:0]), // Templated
.esaxi_wstrb (dut_esaxi_wstrb[SSTW-1:0]), // Templated
.esaxi_wlast (dut_esaxi_wlast), // Templated
.esaxi_wvalid (dut_esaxi_wvalid), // Templated
.emaxi_bid (dut_emaxi_bid[MIDW-1:0]), // Templated
.emaxi_bresp (dut_emaxi_bresp[1:0]), // Templated
.emaxi_bvalid (dut_emaxi_bvalid), // Templated
.esaxi_bready (dut_esaxi_bready), // Templated
.emaxi_arready (dut_emaxi_arready), // Templated
.esaxi_arid (dut_esaxi_arid[SIDW-1:0]), // Templated
.esaxi_araddr (dut_esaxi_araddr[MAW-1:0]), // Templated
.esaxi_arlen (dut_esaxi_arlen[3:0]), // Templated
.esaxi_arsize (dut_esaxi_arsize[2:0]), // Templated
.esaxi_arburst (dut_esaxi_arburst[1:0]), // Templated
.esaxi_arlock (dut_esaxi_arlock[1:0]), // Templated
.esaxi_arcache (dut_esaxi_arcache[3:0]), // Templated
.esaxi_arprot (dut_esaxi_arprot[2:0]), // Templated
.esaxi_arvalid (dut_esaxi_arvalid), // Templated
.emaxi_rid (dut_emaxi_rid[MIDW-1:0]), // Templated
.emaxi_rdata (dut_emaxi_rdata[MDW-1:0]), // Templated
.emaxi_rresp (dut_emaxi_rresp[1:0]), // Templated
.emaxi_rlast (dut_emaxi_rlast), // Templated
.emaxi_rvalid (dut_emaxi_rvalid), // Templated
.esaxi_rready (dut_esaxi_rready), // Templated
.esaxi_awqos (dut_esaxi_awqos[3:0]), // Templated
.esaxi_arqos (dut_esaxi_arqos[3:0])); // Templated
/* maxi_test AUTO_TEMPLATE(
.ERROR (ERROR[2]),
.DONE (DONE[2]),
..*_aclk (clock),
..*_aresetn (resetn),
.m_axi\(.*\) (dut_esaxi\1[]),
); */
maxi_test
#(/*AUTOINSTPARAM*/
// Parameters
.SIDW (SIDW),
.SAW (SAW),
.SDW (SDW),
.SSTW (SSTW))
maxi_dut
(/*AUTOINST*/
// Outputs
.ERROR (ERROR[2]), // Templated
.DONE (DONE[2]), // Templated
.m_axi_awid (dut_esaxi_awid[SIDW-1:0]), // Templated
.m_axi_awaddr (dut_esaxi_awaddr[SAW-1:0]), // Templated
.m_axi_awlen (dut_esaxi_awlen[3:0]), // Templated
.m_axi_awsize (dut_esaxi_awsize[2:0]), // Templated
.m_axi_awburst (dut_esaxi_awburst[1:0]), // Templated
.m_axi_awlock (dut_esaxi_awlock[1:0]), // Templated
.m_axi_awcache (dut_esaxi_awcache[3:0]), // Templated
.m_axi_awprot (dut_esaxi_awprot[2:0]), // Templated
.m_axi_awvalid (dut_esaxi_awvalid), // Templated
.m_axi_awqos (dut_esaxi_awqos[3:0]), // Templated
.m_axi_wid (dut_esaxi_wid[SIDW-1:0]), // Templated
.m_axi_wdata (dut_esaxi_wdata[SDW-1:0]), // Templated
.m_axi_wstrb (dut_esaxi_wstrb[SSTW-1:0]), // Templated
.m_axi_wlast (dut_esaxi_wlast), // Templated
.m_axi_wvalid (dut_esaxi_wvalid), // Templated
.m_axi_bready (dut_esaxi_bready), // Templated
.m_axi_arid (dut_esaxi_arid[SIDW-1:0]), // Templated
.m_axi_araddr (dut_esaxi_araddr[SAW-1:0]), // Templated
.m_axi_arlen (dut_esaxi_arlen[3:0]), // Templated
.m_axi_arsize (dut_esaxi_arsize[2:0]), // Templated
.m_axi_arburst (dut_esaxi_arburst[1:0]), // Templated
.m_axi_arlock (dut_esaxi_arlock[1:0]), // Templated
.m_axi_arcache (dut_esaxi_arcache[3:0]), // Templated
.m_axi_arprot (dut_esaxi_arprot[2:0]), // Templated
.m_axi_arvalid (dut_esaxi_arvalid), // Templated
.m_axi_arqos (dut_esaxi_arqos[3:0]), // Templated
.m_axi_rready (dut_esaxi_rready), // Templated
// Inputs
.m_axi_aclk (clock), // Templated
.m_axi_aresetn (resetn), // Templated
.m_axi_awready (dut_esaxi_awready), // Templated
.m_axi_wready (dut_esaxi_wready), // Templated
.m_axi_bid (dut_esaxi_bid[SIDW-1:0]), // Templated
.m_axi_bresp (dut_esaxi_bresp[1:0]), // Templated
.m_axi_bvalid (dut_esaxi_bvalid), // Templated
.m_axi_arready (dut_esaxi_arready), // Templated
.m_axi_rid (dut_esaxi_rid[SIDW-1:0]), // Templated
.m_axi_rdata (dut_esaxi_rdata[SDW-1:0]), // Templated
.m_axi_rresp (dut_esaxi_rresp[1:0]), // Templated
.m_axi_rlast (dut_esaxi_rlast), // Templated
.m_axi_rvalid (dut_esaxi_rvalid)); // Templated
/* saxi_test AUTO_TEMPLATE(
.ERROR (ERROR[3]),
.DONE (DONE[3]),
..*_aclk (clock),
..*_aresetn (resetn),
.s_axi\(.*\) (dut_emaxi\1[]),
); */
saxi_test
#(/*AUTOINSTPARAM*/
// Parameters
.MIDW (MIDW),
.MAW (MAW),
.MDW (MDW),
.MSTW (MSTW))
saxi_dut
(/*AUTOINST*/
// Outputs
.ERROR (ERROR[3]), // Templated
.DONE (DONE[3]), // Templated
.s_axi_awready (dut_emaxi_awready), // Templated
.s_axi_wready (dut_emaxi_wready), // Templated
.s_axi_bid (dut_emaxi_bid[MIDW-1:0]), // Templated
.s_axi_bresp (dut_emaxi_bresp[1:0]), // Templated
.s_axi_bvalid (dut_emaxi_bvalid), // Templated
.s_axi_arready (dut_emaxi_arready), // Templated
.s_axi_rid (dut_emaxi_rid[MIDW-1:0]), // Templated
.s_axi_rdata (dut_emaxi_rdata[MDW-1:0]), // Templated
.s_axi_rresp (dut_emaxi_rresp[1:0]), // Templated
.s_axi_rlast (dut_emaxi_rlast), // Templated
.s_axi_rvalid (dut_emaxi_rvalid), // Templated
// Inputs
.s_axi_aclk (clock), // Templated
.s_axi_aresetn (resetn), // Templated
.s_axi_awid (dut_emaxi_awid[MIDW-1:0]), // Templated
.s_axi_awaddr (dut_emaxi_awaddr[MAW-1:0]), // Templated
.s_axi_awlen (dut_emaxi_awlen[3:0]), // Templated
.s_axi_awsize (dut_emaxi_awsize[2:0]), // Templated
.s_axi_awburst (dut_emaxi_awburst[1:0]), // Templated
.s_axi_awlock (dut_emaxi_awlock[1:0]), // Templated
.s_axi_awcache (dut_emaxi_awcache[3:0]), // Templated
.s_axi_awprot (dut_emaxi_awprot[2:0]), // Templated
.s_axi_awvalid (dut_emaxi_awvalid), // Templated
.s_axi_awqos (dut_emaxi_awqos[3:0]), // Templated
.s_axi_wid (dut_emaxi_wid[MIDW-1:0]), // Templated
.s_axi_wdata (dut_emaxi_wdata[MDW-1:0]), // Templated
.s_axi_wstrb (dut_emaxi_wstrb[MSTW-1:0]), // Templated
.s_axi_wlast (dut_emaxi_wlast), // Templated
.s_axi_wvalid (dut_emaxi_wvalid), // Templated
.s_axi_bready (dut_emaxi_bready), // Templated
.s_axi_arid (dut_emaxi_arid[MIDW-1:0]), // Templated
.s_axi_araddr (dut_emaxi_araddr[MAW-1:0]), // Templated
.s_axi_arlen (dut_emaxi_arlen[3:0]), // Templated
.s_axi_arsize (dut_emaxi_arsize[2:0]), // Templated
.s_axi_arburst (dut_emaxi_arburst[1:0]), // Templated
.s_axi_arlock (dut_emaxi_arlock[1:0]), // Templated
.s_axi_arcache (dut_emaxi_arcache[3:0]), // Templated
.s_axi_arprot (dut_emaxi_arprot[2:0]), // Templated
.s_axi_arvalid (dut_emaxi_arvalid), // Templated
.s_axi_arqos (dut_emaxi_arqos[3:0]), // Templated
.s_axi_rready (dut_emaxi_rready)); // Templated
endmodule // tb_elink2
// Local Variables:
// verilog-library-directories:("." "../hdl/parallella-I" "../hdl/elink")
// End:
|
module receive_data_gen (
//input
input clk_50M ,
input clk_100M,
input reset_n ,
//output
output [11:0] Data_A ,
output [11:0] Data_B ,
output [11:0] Data_C ,
output [11:0] Data_D ,
output [11:0] Data_E ,
output [11:0] Data_F ,
output [11:0] Data_G ,
output [11:0] Data_H ,
output [7:0] Line_Num,
output [1:0] Focus_Num,
output Pr_Gate ,
output RX_Gate ,
output Sample_Gate,
output End_Gate
);
//wire
//reg
data_gen_submodule data_gen_submodule (
//input
.clk (clk_50M),
.reset_n (reset_n),
//output
.Data_A (Data_A),
.Data_B (Data_B),
.Data_C (Data_C),
.Data_D (Data_D),
.Data_E (Data_E),
.Data_F (Data_F),
.Data_G (Data_G),
.Data_H (Data_H)
);
cmd_gen_submodule cmd_gen_submodule (
//input
.clk (clk_100M),
.reset_n (reset_n),
//output
.Line_Num (Line_Num),
.Focus_Num (Focus_Num),
.Pr_Gate (Pr_Gate),
.RX_Gate (RX_Gate),
.Sample_Gate (Sample_Gate),
.End_Gate (End_Gate)
);
endmodule
|
module AUDIO_DAC(
// host
clk,
reset,
write,
writedata,
full,
clear,
// dac
bclk,
daclrc,
dacdat
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter DATA_WIDTH = 32;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
input clk;
input reset;
input write;
input [(DATA_WIDTH-1):0] writedata;
output full;
input clear;
input bclk;
input daclrc;
output dacdat;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
/*****************************************************************************
* Internal wires and registers Declarations *
*****************************************************************************/
// Note. Left Justified Mode
reg request_bit;
reg bit_to_dac;
reg [4:0] bit_index; //0~31
reg dac_is_left;
reg [(DATA_WIDTH-1):0] data_to_dac;
reg [(DATA_WIDTH-1):0] shift_data_to_dac;
//
wire dacfifo_empty;
wire dacfifo_read;
wire [(DATA_WIDTH-1):0] dacfifo_readdata;
wire is_left_ch;
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential logic *
*****************************************************************************/
//////////// read data from fifo
assign dacfifo_read = (dacfifo_empty)?1'b0:1'b1;
always @ (negedge is_left_ch)
begin
if (dacfifo_empty)
data_to_dac = 0;
else
data_to_dac = dacfifo_readdata;
end
//////////// streaming data(32-bits) to dac chip(I2S 1-bits port)
assign is_left_ch = ~daclrc;
always @ (negedge bclk)
begin
if (reset || clear)
begin
request_bit = 0;
bit_index = 0;
dac_is_left = is_left_ch;
bit_to_dac = 1'b0;
end
else
begin
if (dac_is_left ^ is_left_ch)
begin // channel change
dac_is_left = is_left_ch;
request_bit = 1;
if (dac_is_left)
begin
shift_data_to_dac = data_to_dac;
bit_index = DATA_WIDTH;
end
end
// serial data to dac
if (request_bit)
begin
bit_index = bit_index - 1'b1;
bit_to_dac = shift_data_to_dac[bit_index]; // MSB as first bit
if ((bit_index == 0) || (bit_index == (DATA_WIDTH/2)))
request_bit = 0;
end
else
bit_to_dac = 1'b0;
end
end
/*****************************************************************************
* Combinational logic *
*****************************************************************************/
assign dacdat = bit_to_dac;
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
audio_fifo dac_fifo(
// write
.wrclk(clk),
.wrreq(write),
.data(writedata),
.wrfull(full),
.aclr(clear), // sync with wrclk
// read
//.rdclk(bclk),
.rdclk(is_left_ch),
.rdreq(dacfifo_read),
.q(dacfifo_readdata),
.rdempty(dacfifo_empty)
);
endmodule
|
//////////////////////////////////////////////////////////////////////
//// ////
//// eth_txcounters.v ////
//// ////
//// This file is part of the Ethernet IP core project ////
//// http://www.opencores.org/project,ethmac ////
//// ////
//// Author(s): ////
//// - Igor Mohor ([email protected]) ////
//// - Novan Hartadi ([email protected]) ////
//// - Mahmud Galela ([email protected]) ////
//// ////
//// All additional information is avaliable in the Readme.txt ////
//// file. ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Authors ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// CVS Revision History
//
// $Log: not supported by cvs2svn $
// Revision 1.5 2002/04/22 14:54:14 mohor
// FCS should not be included in NibbleMinFl.
//
// Revision 1.4 2002/01/23 10:28:16 mohor
// Link in the header changed.
//
// Revision 1.3 2001/10/19 08:43:51 mohor
// eth_timescale.v changed to timescale.v This is done because of the
// simulation of the few cores in a one joined project.
//
// Revision 1.2 2001/09/11 14:17:00 mohor
// Few little NCSIM warnings fixed.
//
// Revision 1.1 2001/08/06 14:44:29 mohor
// A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
// Include files fixed to contain no path.
// File names and module names changed ta have a eth_ prologue in the name.
// File eth_timescale.v is used to define timescale
// All pin names on the top module are changed to contain _I, _O or _OE at the end.
// Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
// and Mdo_OE. The bidirectional signal must be created on the top level. This
// is done due to the ASIC tools.
//
// Revision 1.1 2001/07/30 21:23:42 mohor
// Directory structure changed. Files checked and joind together.
//
// Revision 1.4 2001/06/27 21:27:45 mohor
// Few typos fixed.
//
// Revision 1.2 2001/06/19 10:38:07 mohor
// Minor changes in header.
//
// Revision 1.1 2001/06/19 10:27:57 mohor
// TxEthMAC initial release.
//
//
//
`include "timescale.v"
module eth_txcounters (StatePreamble, StateIPG, StateData, StatePAD, StateFCS, StateJam,
StateBackOff, StateDefer, StateIdle, StartDefer, StartIPG, StartFCS,
StartJam, StartBackoff, TxStartFrm, MTxClk, Reset, MinFL, MaxFL, HugEn,
ExDfrEn, PacketFinished_q, DlyCrcEn, StateSFD, ByteCnt, NibCnt,
ExcessiveDefer, NibCntEq7, NibCntEq15, MaxFrame, NibbleMinFl, DlyCrcCnt
);
input MTxClk; // Tx clock
input Reset; // Reset
input StatePreamble; // Preamble state
input StateIPG; // IPG state
input [1:0] StateData; // Data state
input StatePAD; // PAD state
input StateFCS; // FCS state
input StateJam; // Jam state
input StateBackOff; // Backoff state
input StateDefer; // Defer state
input StateIdle; // Idle state
input StateSFD; // SFD state
input StartDefer; // Defer state will be activated in next clock
input StartIPG; // IPG state will be activated in next clock
input StartFCS; // FCS state will be activated in next clock
input StartJam; // Jam state will be activated in next clock
input StartBackoff; // Backoff state will be activated in next clock
input TxStartFrm; // Tx start frame
input [15:0] MinFL; // Minimum frame length (in bytes)
input [15:0] MaxFL; // Miximum frame length (in bytes)
input HugEn; // Pakets bigger then MaxFL enabled
input ExDfrEn; // Excessive deferral enabled
input PacketFinished_q;
input DlyCrcEn; // Delayed CRC enabled
output [15:0] ByteCnt; // Byte counter
output [15:0] NibCnt; // Nibble counter
output ExcessiveDefer; // Excessive Deferral occuring
output NibCntEq7; // Nibble counter is equal to 7
output NibCntEq15; // Nibble counter is equal to 15
output MaxFrame; // Maximum frame occured
output NibbleMinFl; // Nibble counter is greater than the minimum frame length
output [2:0] DlyCrcCnt; // Delayed CRC Count
wire ExcessiveDeferCnt;
wire ResetNibCnt;
wire IncrementNibCnt;
wire ResetByteCnt;
wire IncrementByteCnt;
wire ByteCntMax;
reg [15:0] NibCnt;
reg [15:0] ByteCnt;
reg [2:0] DlyCrcCnt;
assign IncrementNibCnt = StateIPG | StatePreamble | (|StateData) | StatePAD
| StateFCS | StateJam | StateBackOff | StateDefer & ~ExcessiveDefer & TxStartFrm;
assign ResetNibCnt = StateDefer & ExcessiveDefer & ~TxStartFrm | StatePreamble & NibCntEq15
| StateJam & NibCntEq7 | StateIdle | StartDefer | StartIPG | StartFCS | StartJam;
// Nibble Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
NibCnt <= 16'h0;
else
begin
if(ResetNibCnt)
NibCnt <= 16'h0;
else
if(IncrementNibCnt)
NibCnt <= NibCnt + 16'd1;
end
end
assign NibCntEq7 = &NibCnt[2:0];
assign NibCntEq15 = &NibCnt[3:0];
assign NibbleMinFl = NibCnt >= (((MinFL-16'd4)<<1) -1); // FCS should not be included in NibbleMinFl
assign ExcessiveDeferCnt = NibCnt[13:0] == 14'h17b7;
assign ExcessiveDefer = NibCnt[13:0] == 14'h17b7 & ~ExDfrEn; // 6071 nibbles
assign IncrementByteCnt = StateData[1] & ~ByteCntMax
| StateBackOff & (&NibCnt[6:0])
| (StatePAD | StateFCS) & NibCnt[0] & ~ByteCntMax;
assign ResetByteCnt = StartBackoff | StateIdle & TxStartFrm | PacketFinished_q;
// Transmit Byte Counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
ByteCnt[15:0] <= 16'h0;
else
begin
if(ResetByteCnt)
ByteCnt[15:0] <= 16'h0;
else
if(IncrementByteCnt)
ByteCnt[15:0] <= ByteCnt[15:0] + 16'd1;
end
end
assign MaxFrame = ByteCnt[15:0] == MaxFL[15:0] & ~HugEn;
assign ByteCntMax = &ByteCnt[15:0];
// Delayed CRC counter
always @ (posedge MTxClk or posedge Reset)
begin
if(Reset)
DlyCrcCnt <= 3'h0;
else
begin
if(StateData[1] & DlyCrcCnt == 3'h4 | StartJam | PacketFinished_q)
DlyCrcCnt <= 3'h0;
else
if(DlyCrcEn & (StateSFD | StateData[1] & (|DlyCrcCnt[2:0])))
DlyCrcCnt <= DlyCrcCnt + 3'd1;
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
//////////////////////////////////////////////////////////////////////////////
//name : server
//input : input_eth_rx:16
//input : input_socket:16
//output : output_socket:16
//output : output_eth_tx:16
//source_file : ../source/server.c
///======
///
///Created by C2CHIP
//////////////////////////////////////////////////////////////////////////////
// Register Allocation
// ===================
// Register Name Size
// 0 put_eth return address 2
// 1 variable i 2
// 2 put_socket return address 2
// 3 variable i 2
// 4 get_eth return address 2
// 5 variable get_eth return value 2
// 6 rdy_eth return address 2
// 7 variable rdy_eth return value 2
// 8 get_socket return address 2
// 9 variable get_socket return value 2
// 10 array 2
// 11 variable checksum 4
// 12 reset_checksum return address 2
// 13 add_checksum return address 2
// 14 variable data 2
// 15 check_checksum return address 2
// 16 variable check_checksum return value 2
// 17 calc_ack return address 2
// 18 variable calc_ack return value 2
// 19 array 2
// 20 array 2
// 21 variable length 2
// 22 variable new_ack_0 2
// 23 variable new_ack_1 2
// 24 variable return_value 2
// 25 put_ethernet_packet return address 2
// 26 array 2
// 27 variable number_of_bytes 2
// 28 variable destination_mac_address_hi 2
// 29 variable destination_mac_address_med 2
// 30 variable destination_mac_address_lo 2
// 31 variable protocol 2
// 32 variable byte 2
// 33 variable index 2
// 34 get_ethernet_packet return address 2
// 35 variable get_ethernet_packet return value 2
// 36 array 2
// 37 variable number_of_bytes 2
// 38 variable index 2
// 39 variable byte 2
// 40 array 2
// 41 array 2
// 42 array 2
// 43 array 2
// 44 array 2
// 45 variable arp_pounsigneder 2
// 46 get_arp_cache return address 2
// 47 variable get_arp_cache return value 2
// 48 variable ip_hi 2
// 49 variable ip_lo 2
// 50 variable number_of_bytes 2
// 51 variable byte 2
// 52 array 2
// 53 variable i 2
// 54 put_ip_packet return address 2
// 55 array 2
// 56 variable total_length 2
// 57 variable protocol 2
// 58 variable ip_hi 2
// 59 variable ip_lo 2
// 60 variable number_of_bytes 2
// 61 variable i 2
// 62 variable arp_cache 2
// 63 get_ip_packet return address 2
// 64 variable get_ip_packet return value 2
// 65 array 2
// 66 variable total_length 2
// 67 variable header_length 2
// 68 variable payload_start 2
// 69 variable payload_length 2
// 70 variable i 2
// 71 variable from 2
// 72 variable to 2
// 73 variable payload_end 2
// 74 variable number_of_bytes 2
// 75 variable remote_ip_hi 2
// 76 variable remote_ip_lo 2
// 77 variable tx_source 2
// 78 variable tx_dest 2
// 79 array 2
// 80 array 2
// 81 array 2
// 82 variable tx_window 2
// 83 variable tx_fin_flag 2
// 84 variable tx_syn_flag 2
// 85 variable tx_rst_flag 2
// 86 variable tx_psh_flag 2
// 87 variable tx_ack_flag 2
// 88 variable tx_urg_flag 2
// 89 variable rx_source 2
// 90 variable rx_dest 2
// 91 array 2
// 92 array 2
// 93 variable rx_fin_flag 2
// 94 variable rx_syn_flag 2
// 95 variable rx_rst_flag 2
// 96 variable rx_ack_flag 2
// 97 put_tcp_packet return address 2
// 98 array 2
// 99 variable tx_length 2
// 100 variable payload_start 2
// 101 variable packet_length 2
// 102 variable index 2
// 103 variable i 2
// 104 variable rx_length 2
// 105 variable rx_start 2
// 106 get_tcp_packet return address 2
// 107 variable get_tcp_packet return value 2
// 108 array 2
// 109 variable number_of_bytes 2
// 110 variable header_length 2
// 111 variable payload_start 2
// 112 variable total_length 2
// 113 variable payload_length 2
// 114 variable tcp_header_length 2
// 115 application_put_data return address 2
// 116 array 2
// 117 variable start 2
// 118 variable length 2
// 119 variable i 2
// 120 variable index 2
// 121 application_get_data return address 2
// 122 variable application_get_data return value 2
// 123 array 2
// 124 variable start 2
// 125 variable i 2
// 126 variable index 2
// 127 variable length 2
// 128 server return address 2
// 129 array 2
// 130 array 2
// 131 variable tx_start 2
// 132 variable tx_length 2
// 133 variable timeout 2
// 134 variable resend_wait 2
// 135 variable bytes 2
// 136 variable index 2
// 137 variable last_state 2
// 138 variable new_rx_data 2
// 139 variable state 2
// 140 temporary_register 2
// 141 temporary_register 2
// 142 temporary_register 2
// 143 temporary_register 4
// 144 temporary_register 4
// 145 temporary_register 4
// 146 temporary_register 2
// 147 temporary_register 2
// 148 temporary_register 1024
// 149 temporary_register 2
// 150 temporary_register 2
// 151 temporary_register 2048
module server(input_eth_rx,input_socket,input_eth_rx_stb,input_socket_stb,output_socket_ack,output_eth_tx_ack,clk,rst,output_socket,output_eth_tx,output_socket_stb,output_eth_tx_stb,input_eth_rx_ack,input_socket_ack);
integer file_count;
real fp_value;
input [15:0] input_eth_rx;
input [15:0] input_socket;
input input_eth_rx_stb;
input input_socket_stb;
input output_socket_ack;
input output_eth_tx_ack;
input clk;
input rst;
output [15:0] output_socket;
output [15:0] output_eth_tx;
output output_socket_stb;
output output_eth_tx_stb;
output input_eth_rx_ack;
output input_socket_ack;
reg [15:0] timer;
reg timer_enable;
reg stage_0_enable;
reg stage_1_enable;
reg stage_2_enable;
reg [11:0] program_counter;
reg [11:0] program_counter_0;
reg [53:0] instruction_0;
reg [5:0] opcode_0;
reg [7:0] dest_0;
reg [7:0] src_0;
reg [7:0] srcb_0;
reg [31:0] literal_0;
reg [11:0] program_counter_1;
reg [5:0] opcode_1;
reg [7:0] dest_1;
reg [31:0] register_1;
reg [31:0] registerb_1;
reg [31:0] literal_1;
reg [7:0] dest_2;
reg [31:0] result_2;
reg write_enable_2;
reg [15:0] address_2;
reg [15:0] data_out_2;
reg [15:0] data_in_2;
reg memory_enable_2;
reg [15:0] address_4;
reg [31:0] data_out_4;
reg [31:0] data_in_4;
reg memory_enable_4;
reg [15:0] s_output_socket_stb;
reg [15:0] s_output_eth_tx_stb;
reg [15:0] s_output_socket;
reg [15:0] s_output_eth_tx;
reg [15:0] s_input_eth_rx_ack;
reg [15:0] s_input_socket_ack;
reg [15:0] memory_2 [2685:0];
reg [53:0] instructions [3551:0];
reg [31:0] registers [151:0];
//////////////////////////////////////////////////////////////////////////////
// INSTRUCTION INITIALIZATION
//
// Initialise the contents of the instruction memory
//
// Intruction Set
// ==============
// 0 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'literal'}
// 1 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_and_link'}
// 2 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'stop'}
// 3 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'move'}
// 4 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'nop'}
// 5 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'eth_tx', 'op': 'write'}
// 6 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'jmp_to_reg'}
// 7 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'output': 'socket', 'op': 'write'}
// 8 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'read'}
// 9 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'eth_rx', 'op': 'ready'}
// 10 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'read'}
// 11 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '+'}
// 12 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '&'}
// 13 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_false'}
// 14 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '+'}
// 15 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'goto'}
// 16 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '~'}
// 17 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_request'}
// 18 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read_wait'}
// 19 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_read'}
// 20 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<'}
// 21 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '!='}
// 22 {'float': False, 'literal': True, 'right': False, 'unsigned': False, 'op': 'jmp_if_true'}
// 23 {'right': False, 'element_size': 2, 'float': False, 'unsigned': False, 'literal': False, 'op': 'memory_write'}
// 24 {'right': False, 'float': False, 'unsigned': True, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'op': 'report'}
// 25 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '=='}
// 26 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '!='}
// 27 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': '+'}
// 28 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<'}
// 29 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '=='}
// 30 {'float': False, 'literal': True, 'right': False, 'unsigned': True, 'op': '|'}
// 31 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<='}
// 32 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '>>'}
// 33 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '<<'}
// 34 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '-'}
// 35 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '-'}
// 36 {'float': False, 'literal': False, 'right': False, 'unsigned': True, 'op': '<='}
// 37 {'float': False, 'literal': True, 'right': True, 'unsigned': True, 'op': '|'}
// 38 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'input': 'socket', 'op': 'ready'}
// 39 {'float': False, 'literal': True, 'right': True, 'unsigned': False, 'op': '=='}
// 40 {'right': False, 'float': False, 'unsigned': False, 'literal': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'op': 'report'}
// 41 {'float': False, 'literal': False, 'right': False, 'unsigned': False, 'op': 'wait_clocks'}
// Intructions
// ===========
initial
begin
instructions[0] = {6'd0, 8'd10, 8'd0, 32'd0};//{'dest': 10, 'literal': 0, 'op': 'literal'}
instructions[1] = {6'd0, 8'd11, 8'd0, 32'd0};//{'dest': 11, 'literal': 0, 'size': 4, 'signed': 4, 'op': 'literal'}
instructions[2] = {6'd0, 8'd40, 8'd0, 32'd520};//{'dest': 40, 'literal': 520, 'op': 'literal'}
instructions[3] = {6'd0, 8'd41, 8'd0, 32'd536};//{'dest': 41, 'literal': 536, 'op': 'literal'}
instructions[4] = {6'd0, 8'd42, 8'd0, 32'd552};//{'dest': 42, 'literal': 552, 'op': 'literal'}
instructions[5] = {6'd0, 8'd43, 8'd0, 32'd568};//{'dest': 43, 'literal': 568, 'op': 'literal'}
instructions[6] = {6'd0, 8'd44, 8'd0, 32'd584};//{'dest': 44, 'literal': 584, 'op': 'literal'}
instructions[7] = {6'd0, 8'd45, 8'd0, 32'd0};//{'dest': 45, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[8] = {6'd0, 8'd75, 8'd0, 32'd0};//{'dest': 75, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[9] = {6'd0, 8'd76, 8'd0, 32'd0};//{'dest': 76, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[10] = {6'd0, 8'd77, 8'd0, 32'd0};//{'dest': 77, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[11] = {6'd0, 8'd78, 8'd0, 32'd0};//{'dest': 78, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[12] = {6'd0, 8'd79, 8'd0, 32'd620};//{'dest': 79, 'literal': 620, 'op': 'literal'}
instructions[13] = {6'd0, 8'd80, 8'd0, 32'd622};//{'dest': 80, 'literal': 622, 'op': 'literal'}
instructions[14] = {6'd0, 8'd81, 8'd0, 32'd624};//{'dest': 81, 'literal': 624, 'op': 'literal'}
instructions[15] = {6'd0, 8'd82, 8'd0, 32'd1460};//{'dest': 82, 'literal': 1460, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[16] = {6'd0, 8'd83, 8'd0, 32'd0};//{'dest': 83, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[17] = {6'd0, 8'd84, 8'd0, 32'd0};//{'dest': 84, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[18] = {6'd0, 8'd85, 8'd0, 32'd0};//{'dest': 85, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[19] = {6'd0, 8'd86, 8'd0, 32'd0};//{'dest': 86, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[20] = {6'd0, 8'd87, 8'd0, 32'd0};//{'dest': 87, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[21] = {6'd0, 8'd88, 8'd0, 32'd0};//{'dest': 88, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[22] = {6'd0, 8'd89, 8'd0, 32'd0};//{'dest': 89, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[23] = {6'd0, 8'd90, 8'd0, 32'd0};//{'dest': 90, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[24] = {6'd0, 8'd91, 8'd0, 32'd626};//{'dest': 91, 'literal': 626, 'op': 'literal'}
instructions[25] = {6'd0, 8'd92, 8'd0, 32'd628};//{'dest': 92, 'literal': 628, 'op': 'literal'}
instructions[26] = {6'd0, 8'd93, 8'd0, 32'd0};//{'dest': 93, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[27] = {6'd0, 8'd94, 8'd0, 32'd0};//{'dest': 94, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[28] = {6'd0, 8'd95, 8'd0, 32'd0};//{'dest': 95, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[29] = {6'd0, 8'd96, 8'd0, 32'd0};//{'dest': 96, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[30] = {6'd0, 8'd104, 8'd0, 32'd0};//{'dest': 104, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[31] = {6'd0, 8'd105, 8'd0, 32'd0};//{'dest': 105, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[32] = {6'd1, 8'd128, 8'd0, 32'd2627};//{'dest': 128, 'label': 2627, 'op': 'jmp_and_link'}
instructions[33] = {6'd2, 8'd0, 8'd0, 32'd0};//{'op': 'stop'}
instructions[34] = {6'd3, 8'd140, 8'd1, 32'd0};//{'dest': 140, 'src': 1, 'op': 'move'}
instructions[35] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[36] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[37] = {6'd5, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'eth_tx', 'op': 'write'}
instructions[38] = {6'd6, 8'd0, 8'd0, 32'd0};//{'src': 0, 'op': 'jmp_to_reg'}
instructions[39] = {6'd3, 8'd140, 8'd3, 32'd0};//{'dest': 140, 'src': 3, 'op': 'move'}
instructions[40] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[41] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[42] = {6'd7, 8'd0, 8'd140, 32'd0};//{'src': 140, 'output': 'socket', 'op': 'write'}
instructions[43] = {6'd6, 8'd0, 8'd2, 32'd0};//{'src': 2, 'op': 'jmp_to_reg'}
instructions[44] = {6'd8, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'read'}
instructions[45] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[46] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[47] = {6'd3, 8'd5, 8'd140, 32'd0};//{'dest': 5, 'src': 140, 'op': 'move'}
instructions[48] = {6'd6, 8'd0, 8'd4, 32'd0};//{'src': 4, 'op': 'jmp_to_reg'}
instructions[49] = {6'd9, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'eth_rx', 'op': 'ready'}
instructions[50] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[51] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[52] = {6'd3, 8'd7, 8'd140, 32'd0};//{'dest': 7, 'src': 140, 'op': 'move'}
instructions[53] = {6'd6, 8'd0, 8'd6, 32'd0};//{'src': 6, 'op': 'jmp_to_reg'}
instructions[54] = {6'd10, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'read'}
instructions[55] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[56] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[57] = {6'd3, 8'd9, 8'd140, 32'd0};//{'dest': 9, 'src': 140, 'op': 'move'}
instructions[58] = {6'd6, 8'd0, 8'd8, 32'd0};//{'src': 8, 'op': 'jmp_to_reg'}
instructions[59] = {6'd0, 8'd143, 8'd0, 32'd0};//{'dest': 143, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[60] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[61] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[62] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[63] = {6'd6, 8'd0, 8'd12, 32'd0};//{'src': 12, 'op': 'jmp_to_reg'}
instructions[64] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[65] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[66] = {6'd3, 8'd145, 8'd14, 32'd0};//{'dest': 145, 'src': 14, 'op': 'move'}
instructions[67] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[68] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[69] = {6'd11, 8'd143, 8'd144, 32'd145};//{'srcb': 145, 'src': 144, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[70] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[71] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[72] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[73] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[74] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[75] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[76] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[77] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[78] = {6'd12, 8'd143, 8'd144, 32'd65536};//{'src': 144, 'right': 65536, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[79] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[80] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[81] = {6'd13, 8'd0, 8'd143, 32'd99};//{'src': 143, 'label': 99, 'op': 'jmp_if_false'}
instructions[82] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[83] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[84] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[85] = {6'd12, 8'd143, 8'd144, 32'd65535};//{'src': 144, 'right': 65535, 'dest': 143, 'signed': False, 'op': '&', 'type': 'int', 'size': 4}
instructions[86] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[87] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[88] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[89] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[90] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[91] = {6'd3, 8'd144, 8'd11, 32'd0};//{'dest': 144, 'src': 11, 'op': 'move'}
instructions[92] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[93] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[94] = {6'd14, 8'd143, 8'd144, 32'd1};//{'src': 144, 'right': 1, 'dest': 143, 'signed': False, 'op': '+', 'type': 'int', 'size': 4}
instructions[95] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[96] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[97] = {6'd3, 8'd11, 8'd143, 32'd0};//{'dest': 11, 'src': 143, 'op': 'move'}
instructions[98] = {6'd15, 8'd0, 8'd0, 32'd99};//{'label': 99, 'op': 'goto'}
instructions[99] = {6'd6, 8'd0, 8'd13, 32'd0};//{'src': 13, 'op': 'jmp_to_reg'}
instructions[100] = {6'd3, 8'd143, 8'd11, 32'd0};//{'dest': 143, 'src': 11, 'op': 'move'}
instructions[101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[103] = {6'd16, 8'd140, 8'd143, 32'd0};//{'dest': 140, 'src': 143, 'op': '~'}
instructions[104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[106] = {6'd3, 8'd16, 8'd140, 32'd0};//{'dest': 16, 'src': 140, 'op': 'move'}
instructions[107] = {6'd6, 8'd0, 8'd15, 32'd0};//{'src': 15, 'op': 'jmp_to_reg'}
instructions[108] = {6'd0, 8'd22, 8'd0, 32'd0};//{'dest': 22, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[109] = {6'd0, 8'd23, 8'd0, 32'd0};//{'dest': 23, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[110] = {6'd0, 8'd24, 8'd0, 32'd0};//{'dest': 24, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[111] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[112] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[114] = {6'd11, 8'd146, 8'd142, 32'd20};//{'dest': 146, 'src': 142, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[117] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887811007192, 'op': 'memory_read_request'}
instructions[118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[119] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887811007192, 'op': 'memory_read_wait'}
instructions[120] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887811007192, 'element_size': 2, 'op': 'memory_read'}
instructions[121] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[123] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[124] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[126] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[127] = {6'd3, 8'd22, 8'd140, 32'd0};//{'dest': 22, 'src': 140, 'op': 'move'}
instructions[128] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[130] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[131] = {6'd11, 8'd142, 8'd141, 32'd20};//{'dest': 142, 'src': 141, 'srcb': 20, 'signed': False, 'op': '+'}
instructions[132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[134] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887811007696, 'op': 'memory_read_request'}
instructions[135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[136] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887811007696, 'op': 'memory_read_wait'}
instructions[137] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887811007696, 'element_size': 2, 'op': 'memory_read'}
instructions[138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[140] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[141] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[142] = {6'd3, 8'd142, 8'd21, 32'd0};//{'dest': 142, 'src': 21, 'op': 'move'}
instructions[143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[145] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[148] = {6'd13, 8'd0, 8'd140, 32'd157};//{'src': 140, 'label': 157, 'op': 'jmp_if_false'}
instructions[149] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[152] = {6'd14, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[155] = {6'd3, 8'd23, 8'd140, 32'd0};//{'dest': 23, 'src': 140, 'op': 'move'}
instructions[156] = {6'd15, 8'd0, 8'd0, 32'd157};//{'label': 157, 'op': 'goto'}
instructions[157] = {6'd3, 8'd141, 8'd22, 32'd0};//{'dest': 141, 'src': 22, 'op': 'move'}
instructions[158] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[161] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[164] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029472, 'op': 'memory_read_request'}
instructions[165] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[166] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029472, 'op': 'memory_read_wait'}
instructions[167] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811029472, 'element_size': 2, 'op': 'memory_read'}
instructions[168] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[170] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[173] = {6'd22, 8'd0, 8'd140, 32'd188};//{'src': 140, 'label': 188, 'op': 'jmp_if_true'}
instructions[174] = {6'd3, 8'd141, 8'd23, 32'd0};//{'dest': 141, 'src': 23, 'op': 'move'}
instructions[175] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[176] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[178] = {6'd11, 8'd147, 8'd146, 32'd19};//{'dest': 147, 'src': 146, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[180] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[181] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029760, 'op': 'memory_read_request'}
instructions[182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[183] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811029760, 'op': 'memory_read_wait'}
instructions[184] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811029760, 'element_size': 2, 'op': 'memory_read'}
instructions[185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[187] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[190] = {6'd13, 8'd0, 8'd140, 32'd212};//{'src': 140, 'label': 212, 'op': 'jmp_if_false'}
instructions[191] = {6'd3, 8'd140, 8'd22, 32'd0};//{'dest': 140, 'src': 22, 'op': 'move'}
instructions[192] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[195] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[199] = {6'd3, 8'd140, 8'd23, 32'd0};//{'dest': 140, 'src': 23, 'op': 'move'}
instructions[200] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[203] = {6'd11, 8'd142, 8'd141, 32'd19};//{'dest': 142, 'src': 141, 'srcb': 19, 'signed': False, 'op': '+'}
instructions[204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[207] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[208] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[210] = {6'd3, 8'd24, 8'd140, 32'd0};//{'dest': 24, 'src': 140, 'op': 'move'}
instructions[211] = {6'd15, 8'd0, 8'd0, 32'd212};//{'label': 212, 'op': 'goto'}
instructions[212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[213] = {6'd3, 8'd140, 8'd24, 32'd0};//{'dest': 140, 'src': 24, 'op': 'move'}
instructions[214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[216] = {6'd3, 8'd18, 8'd140, 32'd0};//{'dest': 18, 'src': 140, 'op': 'move'}
instructions[217] = {6'd6, 8'd0, 8'd17, 32'd0};//{'src': 17, 'op': 'jmp_to_reg'}
instructions[218] = {6'd0, 8'd32, 8'd0, 32'd0};//{'dest': 32, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[219] = {6'd0, 8'd33, 8'd0, 32'd0};//{'dest': 33, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[220] = {6'd3, 8'd140, 8'd27, 32'd0};//{'dest': 140, 'src': 27, 'op': 'move'}
instructions[221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[223] = {6'd24, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': False, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 107, 'type': 'int', 'op': 'report'}
instructions[224] = {6'd3, 8'd140, 8'd28, 32'd0};//{'dest': 140, 'src': 28, 'op': 'move'}
instructions[225] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[227] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[228] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[230] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[231] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[232] = {6'd3, 8'd140, 8'd29, 32'd0};//{'dest': 140, 'src': 29, 'op': 'move'}
instructions[233] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[236] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[239] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[240] = {6'd3, 8'd140, 8'd30, 32'd0};//{'dest': 140, 'src': 30, 'op': 'move'}
instructions[241] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[244] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[247] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[248] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[249] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[252] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[255] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[256] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[257] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[260] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[263] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[264] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[265] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[268] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[271] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[272] = {6'd3, 8'd140, 8'd31, 32'd0};//{'dest': 140, 'src': 31, 'op': 'move'}
instructions[273] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[275] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[276] = {6'd11, 8'd142, 8'd141, 32'd26};//{'dest': 142, 'src': 141, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[279] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[280] = {6'd3, 8'd141, 8'd27, 32'd0};//{'dest': 141, 'src': 27, 'op': 'move'}
instructions[281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[282] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[283] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[284] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[285] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[288] = {6'd3, 8'd33, 8'd140, 32'd0};//{'dest': 33, 'src': 140, 'op': 'move'}
instructions[289] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[292] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[295] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[296] = {6'd3, 8'd142, 8'd27, 32'd0};//{'dest': 142, 'src': 27, 'op': 'move'}
instructions[297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[299] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[302] = {6'd13, 8'd0, 8'd140, 32'd327};//{'src': 140, 'label': 327, 'op': 'jmp_if_false'}
instructions[303] = {6'd3, 8'd142, 8'd33, 32'd0};//{'dest': 142, 'src': 33, 'op': 'move'}
instructions[304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[306] = {6'd11, 8'd146, 8'd142, 32'd26};//{'dest': 146, 'src': 142, 'srcb': 26, 'signed': False, 'op': '+'}
instructions[307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[309] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810549952, 'op': 'memory_read_request'}
instructions[310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[311] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810549952, 'op': 'memory_read_wait'}
instructions[312] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810549952, 'element_size': 2, 'op': 'memory_read'}
instructions[313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[315] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[316] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[317] = {6'd3, 8'd140, 8'd33, 32'd0};//{'dest': 140, 'src': 33, 'op': 'move'}
instructions[318] = {6'd14, 8'd33, 8'd33, 32'd1};//{'src': 33, 'right': 1, 'dest': 33, 'signed': False, 'op': '+', 'size': 2}
instructions[319] = {6'd3, 8'd141, 8'd32, 32'd0};//{'dest': 141, 'src': 32, 'op': 'move'}
instructions[320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[322] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[325] = {6'd3, 8'd32, 8'd140, 32'd0};//{'dest': 32, 'src': 140, 'op': 'move'}
instructions[326] = {6'd15, 8'd0, 8'd0, 32'd293};//{'label': 293, 'op': 'goto'}
instructions[327] = {6'd6, 8'd0, 8'd25, 32'd0};//{'src': 25, 'op': 'jmp_to_reg'}
instructions[328] = {6'd0, 8'd37, 8'd0, 32'd0};//{'dest': 37, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[329] = {6'd0, 8'd38, 8'd0, 32'd0};//{'dest': 38, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[330] = {6'd0, 8'd39, 8'd0, 32'd0};//{'dest': 39, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[331] = {6'd1, 8'd6, 8'd0, 32'd49};//{'dest': 6, 'label': 49, 'op': 'jmp_and_link'}
instructions[332] = {6'd3, 8'd141, 8'd7, 32'd0};//{'dest': 141, 'src': 7, 'op': 'move'}
instructions[333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[335] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[338] = {6'd13, 8'd0, 8'd140, 32'd345};//{'src': 140, 'label': 345, 'op': 'jmp_if_false'}
instructions[339] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[340] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[342] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[343] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[344] = {6'd15, 8'd0, 8'd0, 32'd345};//{'label': 345, 'op': 'goto'}
instructions[345] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[346] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[348] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[349] = {6'd3, 8'd37, 8'd140, 32'd0};//{'dest': 37, 'src': 140, 'op': 'move'}
instructions[350] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[353] = {6'd3, 8'd38, 8'd140, 32'd0};//{'dest': 38, 'src': 140, 'op': 'move'}
instructions[354] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[357] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[360] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[361] = {6'd3, 8'd142, 8'd37, 32'd0};//{'dest': 142, 'src': 37, 'op': 'move'}
instructions[362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[364] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[367] = {6'd13, 8'd0, 8'd140, 32'd387};//{'src': 140, 'label': 387, 'op': 'jmp_if_false'}
instructions[368] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[369] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[370] = {6'd3, 8'd141, 8'd38, 32'd0};//{'dest': 141, 'src': 38, 'op': 'move'}
instructions[371] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[373] = {6'd11, 8'd142, 8'd141, 32'd36};//{'dest': 142, 'src': 141, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[376] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[377] = {6'd3, 8'd140, 8'd38, 32'd0};//{'dest': 140, 'src': 38, 'op': 'move'}
instructions[378] = {6'd14, 8'd38, 8'd38, 32'd1};//{'src': 38, 'right': 1, 'dest': 38, 'signed': False, 'op': '+', 'size': 2}
instructions[379] = {6'd3, 8'd141, 8'd39, 32'd0};//{'dest': 141, 'src': 39, 'op': 'move'}
instructions[380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[382] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[384] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[385] = {6'd3, 8'd39, 8'd140, 32'd0};//{'dest': 39, 'src': 140, 'op': 'move'}
instructions[386] = {6'd15, 8'd0, 8'd0, 32'd358};//{'label': 358, 'op': 'goto'}
instructions[387] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[390] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[393] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810550960, 'op': 'memory_read_request'}
instructions[394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[395] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810550960, 'op': 'memory_read_wait'}
instructions[396] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810550960, 'element_size': 2, 'op': 'memory_read'}
instructions[397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[399] = {6'd26, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[402] = {6'd13, 8'd0, 8'd140, 32'd416};//{'src': 140, 'label': 416, 'op': 'jmp_if_false'}
instructions[403] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[406] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[409] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810551248, 'op': 'memory_read_request'}
instructions[410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[411] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810551248, 'op': 'memory_read_wait'}
instructions[412] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810551248, 'element_size': 2, 'op': 'memory_read'}
instructions[413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[415] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[418] = {6'd13, 8'd0, 8'd140, 32'd425};//{'src': 140, 'label': 425, 'op': 'jmp_if_false'}
instructions[419] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[422] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[423] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[424] = {6'd15, 8'd0, 8'd0, 32'd425};//{'label': 425, 'op': 'goto'}
instructions[425] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[428] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[431] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572368, 'op': 'memory_read_request'}
instructions[432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[433] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572368, 'op': 'memory_read_wait'}
instructions[434] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810572368, 'element_size': 2, 'op': 'memory_read'}
instructions[435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[437] = {6'd26, 8'd140, 8'd141, 32'd515};//{'src': 141, 'right': 515, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[440] = {6'd13, 8'd0, 8'd140, 32'd454};//{'src': 140, 'label': 454, 'op': 'jmp_if_false'}
instructions[441] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[444] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[447] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572656, 'op': 'memory_read_request'}
instructions[448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[449] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810572656, 'op': 'memory_read_wait'}
instructions[450] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810572656, 'element_size': 2, 'op': 'memory_read'}
instructions[451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[453] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[456] = {6'd13, 8'd0, 8'd140, 32'd463};//{'src': 140, 'label': 463, 'op': 'jmp_if_false'}
instructions[457] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[458] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[460] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[461] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[462] = {6'd15, 8'd0, 8'd0, 32'd463};//{'label': 463, 'op': 'goto'}
instructions[463] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[466] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[469] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573232, 'op': 'memory_read_request'}
instructions[470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[471] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573232, 'op': 'memory_read_wait'}
instructions[472] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810573232, 'element_size': 2, 'op': 'memory_read'}
instructions[473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[475] = {6'd26, 8'd140, 8'd141, 32'd1029};//{'src': 141, 'right': 1029, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[477] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[478] = {6'd13, 8'd0, 8'd140, 32'd492};//{'src': 140, 'label': 492, 'op': 'jmp_if_false'}
instructions[479] = {6'd0, 8'd142, 8'd0, 32'd2};//{'dest': 142, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[482] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[485] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573520, 'op': 'memory_read_request'}
instructions[486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[487] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810573520, 'op': 'memory_read_wait'}
instructions[488] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810573520, 'element_size': 2, 'op': 'memory_read'}
instructions[489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[491] = {6'd26, 8'd140, 8'd141, 32'd65535};//{'src': 141, 'right': 65535, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[494] = {6'd13, 8'd0, 8'd140, 32'd501};//{'src': 140, 'label': 501, 'op': 'jmp_if_false'}
instructions[495] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[496] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[498] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[499] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[500] = {6'd15, 8'd0, 8'd0, 32'd501};//{'label': 501, 'op': 'goto'}
instructions[501] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[504] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[507] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574096, 'op': 'memory_read_request'}
instructions[508] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[509] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574096, 'op': 'memory_read_wait'}
instructions[510] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810574096, 'element_size': 2, 'op': 'memory_read'}
instructions[511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[512] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[513] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[515] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[516] = {6'd13, 8'd0, 8'd140, 32'd749};//{'src': 140, 'label': 749, 'op': 'jmp_if_false'}
instructions[517] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[520] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[523] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574600, 'op': 'memory_read_request'}
instructions[524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[525] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810574600, 'op': 'memory_read_wait'}
instructions[526] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810574600, 'element_size': 2, 'op': 'memory_read'}
instructions[527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[528] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[529] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[532] = {6'd13, 8'd0, 8'd140, 32'd743};//{'src': 140, 'label': 743, 'op': 'jmp_if_false'}
instructions[533] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[534] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[537] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[540] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[541] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[542] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[545] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[547] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[548] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[549] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[550] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[553] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[556] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[557] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[558] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[561] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[562] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[564] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[565] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[566] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[569] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[572] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[573] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[574] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[577] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[578] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[579] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[580] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[581] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[582] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[585] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[588] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[589] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[590] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[593] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[596] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[597] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[598] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[599] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[601] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[603] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[604] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[605] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[608] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[611] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810594864, 'op': 'memory_read_request'}
instructions[612] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[613] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810594864, 'op': 'memory_read_wait'}
instructions[614] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810594864, 'element_size': 2, 'op': 'memory_read'}
instructions[615] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[618] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[620] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[621] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[622] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[625] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[628] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595296, 'op': 'memory_read_request'}
instructions[629] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[630] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595296, 'op': 'memory_read_wait'}
instructions[631] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810595296, 'element_size': 2, 'op': 'memory_read'}
instructions[632] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[633] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[635] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[636] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[637] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[638] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[639] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[642] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[645] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595728, 'op': 'memory_read_request'}
instructions[646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[647] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810595728, 'op': 'memory_read_wait'}
instructions[648] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810595728, 'element_size': 2, 'op': 'memory_read'}
instructions[649] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[650] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[652] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[653] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[654] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[655] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[656] = {6'd0, 8'd146, 8'd0, 32'd14};//{'dest': 146, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[657] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[659] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[660] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[662] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596160, 'op': 'memory_read_request'}
instructions[663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[664] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596160, 'op': 'memory_read_wait'}
instructions[665] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810596160, 'element_size': 2, 'op': 'memory_read'}
instructions[666] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[668] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[669] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[672] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[673] = {6'd0, 8'd146, 8'd0, 32'd15};//{'dest': 146, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[676] = {6'd11, 8'd147, 8'd146, 32'd36};//{'dest': 147, 'src': 146, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[679] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596592, 'op': 'memory_read_request'}
instructions[680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[681] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810596592, 'op': 'memory_read_wait'}
instructions[682] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810596592, 'element_size': 2, 'op': 'memory_read'}
instructions[683] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[684] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[686] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[689] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[690] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[693] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[694] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[697] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[698] = {6'd0, 8'd142, 8'd0, 32'd11};//{'dest': 142, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[699] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[701] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[704] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810617928, 'op': 'memory_read_request'}
instructions[705] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[706] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810617928, 'op': 'memory_read_wait'}
instructions[707] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810617928, 'element_size': 2, 'op': 'memory_read'}
instructions[708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[710] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[711] = {6'd0, 8'd142, 8'd0, 32'd12};//{'dest': 142, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[713] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[714] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[717] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618072, 'op': 'memory_read_request'}
instructions[718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[719] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618072, 'op': 'memory_read_wait'}
instructions[720] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618072, 'element_size': 2, 'op': 'memory_read'}
instructions[721] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[723] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[724] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[727] = {6'd11, 8'd146, 8'd142, 32'd36};//{'dest': 146, 'src': 142, 'srcb': 36, 'signed': False, 'op': '+'}
instructions[728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[730] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618216, 'op': 'memory_read_request'}
instructions[731] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[732] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618216, 'op': 'memory_read_wait'}
instructions[733] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618216, 'element_size': 2, 'op': 'memory_read'}
instructions[734] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[736] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[737] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[739] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[740] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[741] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[742] = {6'd15, 8'd0, 8'd0, 32'd743};//{'label': 743, 'op': 'goto'}
instructions[743] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[746] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[747] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[748] = {6'd15, 8'd0, 8'd0, 32'd749};//{'label': 749, 'op': 'goto'}
instructions[749] = {6'd3, 8'd140, 8'd37, 32'd0};//{'dest': 140, 'src': 37, 'op': 'move'}
instructions[750] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[752] = {6'd3, 8'd35, 8'd140, 32'd0};//{'dest': 35, 'src': 140, 'op': 'move'}
instructions[753] = {6'd6, 8'd0, 8'd34, 32'd0};//{'src': 34, 'op': 'jmp_to_reg'}
instructions[754] = {6'd0, 8'd50, 8'd0, 32'd0};//{'dest': 50, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[755] = {6'd0, 8'd51, 8'd0, 32'd0};//{'dest': 51, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[756] = {6'd0, 8'd52, 8'd0, 32'd600};//{'dest': 52, 'literal': 600, 'op': 'literal'}
instructions[757] = {6'd0, 8'd53, 8'd0, 32'd0};//{'dest': 53, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[758] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[761] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[764] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[767] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[770] = {6'd13, 8'd0, 8'd140, 32'd814};//{'src': 140, 'label': 814, 'op': 'jmp_if_false'}
instructions[771] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[774] = {6'd11, 8'd146, 8'd142, 32'd40};//{'dest': 146, 'src': 142, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[777] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618576, 'op': 'memory_read_request'}
instructions[778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[779] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618576, 'op': 'memory_read_wait'}
instructions[780] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618576, 'element_size': 2, 'op': 'memory_read'}
instructions[781] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[784] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[787] = {6'd13, 8'd0, 8'd140, 32'd802};//{'src': 140, 'label': 802, 'op': 'jmp_if_false'}
instructions[788] = {6'd3, 8'd142, 8'd53, 32'd0};//{'dest': 142, 'src': 53, 'op': 'move'}
instructions[789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[790] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[791] = {6'd11, 8'd146, 8'd142, 32'd41};//{'dest': 146, 'src': 142, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[794] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618864, 'op': 'memory_read_request'}
instructions[795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[796] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810618864, 'op': 'memory_read_wait'}
instructions[797] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810618864, 'element_size': 2, 'op': 'memory_read'}
instructions[798] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[801] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[804] = {6'd13, 8'd0, 8'd140, 32'd811};//{'src': 140, 'label': 811, 'op': 'jmp_if_false'}
instructions[805] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[808] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[809] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[810] = {6'd15, 8'd0, 8'd0, 32'd811};//{'label': 811, 'op': 'goto'}
instructions[811] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[812] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[813] = {6'd15, 8'd0, 8'd0, 32'd762};//{'label': 762, 'op': 'goto'}
instructions[814] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[815] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[818] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[822] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[823] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[826] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[829] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[830] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[831] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[833] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[834] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[837] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[838] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[839] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[842] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[843] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[845] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[846] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[847] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[850] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[851] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[853] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[854] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[855] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[858] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[859] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[861] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[862] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[863] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[865] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[866] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[869] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[870] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[871] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[874] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[875] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[877] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[878] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[879] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[881] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[882] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[885] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[886] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[887] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[890] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[893] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[894] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[895] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[898] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[901] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[902] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[905] = {6'd3, 8'd26, 8'd148, 32'd0};//{'dest': 26, 'src': 148, 'op': 'move'}
instructions[906] = {6'd0, 8'd141, 8'd0, 32'd64};//{'dest': 141, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[909] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[910] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[913] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[914] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[917] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[918] = {6'd0, 8'd141, 8'd0, 32'd65535};//{'dest': 141, 'literal': 65535, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[921] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[922] = {6'd0, 8'd141, 8'd0, 32'd2054};//{'dest': 141, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[925] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[926] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[927] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[928] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[931] = {6'd3, 8'd50, 8'd140, 32'd0};//{'dest': 50, 'src': 140, 'op': 'move'}
instructions[932] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[935] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[936] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[939] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[942] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[943] = {6'd3, 8'd142, 8'd50, 32'd0};//{'dest': 142, 'src': 50, 'op': 'move'}
instructions[944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[946] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[947] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[949] = {6'd13, 8'd0, 8'd140, 32'd979};//{'src': 140, 'label': 979, 'op': 'jmp_if_false'}
instructions[950] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[951] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[953] = {6'd28, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[955] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[956] = {6'd13, 8'd0, 8'd140, 32'd967};//{'src': 140, 'label': 967, 'op': 'jmp_if_false'}
instructions[957] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[958] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[959] = {6'd3, 8'd141, 8'd53, 32'd0};//{'dest': 141, 'src': 53, 'op': 'move'}
instructions[960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[962] = {6'd11, 8'd142, 8'd141, 32'd52};//{'dest': 142, 'src': 141, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[963] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[965] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[966] = {6'd15, 8'd0, 8'd0, 32'd969};//{'label': 969, 'op': 'goto'}
instructions[967] = {6'd1, 8'd4, 8'd0, 32'd44};//{'dest': 4, 'label': 44, 'op': 'jmp_and_link'}
instructions[968] = {6'd3, 8'd140, 8'd5, 32'd0};//{'dest': 140, 'src': 5, 'op': 'move'}
instructions[969] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[970] = {6'd14, 8'd53, 8'd53, 32'd1};//{'src': 53, 'right': 1, 'dest': 53, 'signed': False, 'op': '+', 'size': 2}
instructions[971] = {6'd3, 8'd141, 8'd51, 32'd0};//{'dest': 141, 'src': 51, 'op': 'move'}
instructions[972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[974] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[977] = {6'd3, 8'd51, 8'd140, 32'd0};//{'dest': 51, 'src': 140, 'op': 'move'}
instructions[978] = {6'd15, 8'd0, 8'd0, 32'd940};//{'label': 940, 'op': 'goto'}
instructions[979] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[982] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[985] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673120, 'op': 'memory_read_request'}
instructions[986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[987] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673120, 'op': 'memory_read_wait'}
instructions[988] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673120, 'element_size': 2, 'op': 'memory_read'}
instructions[989] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[991] = {6'd25, 8'd140, 8'd141, 32'd2054};//{'src': 141, 'right': 2054, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[994] = {6'd13, 8'd0, 8'd140, 32'd1008};//{'src': 140, 'label': 1008, 'op': 'jmp_if_false'}
instructions[995] = {6'd0, 8'd142, 8'd0, 32'd10};//{'dest': 142, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[998] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1001] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673408, 'op': 'memory_read_request'}
instructions[1002] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1003] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673408, 'op': 'memory_read_wait'}
instructions[1004] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673408, 'element_size': 2, 'op': 'memory_read'}
instructions[1005] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1007] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1009] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1010] = {6'd13, 8'd0, 8'd140, 32'd1139};//{'src': 140, 'label': 1139, 'op': 'jmp_if_false'}
instructions[1011] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1013] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1014] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1017] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673984, 'op': 'memory_read_request'}
instructions[1018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1019] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810673984, 'op': 'memory_read_wait'}
instructions[1020] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810673984, 'element_size': 2, 'op': 'memory_read'}
instructions[1021] = {6'd3, 8'd142, 8'd48, 32'd0};//{'dest': 142, 'src': 48, 'op': 'move'}
instructions[1022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1023] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1024] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1027] = {6'd13, 8'd0, 8'd140, 32'd1042};//{'src': 140, 'label': 1042, 'op': 'jmp_if_false'}
instructions[1028] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1031] = {6'd11, 8'd146, 8'd142, 32'd52};//{'dest': 146, 'src': 142, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1033] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1034] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810674272, 'op': 'memory_read_request'}
instructions[1035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1036] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810674272, 'op': 'memory_read_wait'}
instructions[1037] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810674272, 'element_size': 2, 'op': 'memory_read'}
instructions[1038] = {6'd3, 8'd142, 8'd49, 32'd0};//{'dest': 142, 'src': 49, 'op': 'move'}
instructions[1039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1041] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1042] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1044] = {6'd13, 8'd0, 8'd140, 32'd1138};//{'src': 140, 'label': 1138, 'op': 'jmp_if_false'}
instructions[1045] = {6'd3, 8'd140, 8'd48, 32'd0};//{'dest': 140, 'src': 48, 'op': 'move'}
instructions[1046] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1047] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1049] = {6'd11, 8'd142, 8'd141, 32'd40};//{'dest': 142, 'src': 141, 'srcb': 40, 'signed': False, 'op': '+'}
instructions[1050] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1052] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1053] = {6'd3, 8'd140, 8'd49, 32'd0};//{'dest': 140, 'src': 49, 'op': 'move'}
instructions[1054] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1055] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1056] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1057] = {6'd11, 8'd142, 8'd141, 32'd41};//{'dest': 142, 'src': 141, 'srcb': 41, 'signed': False, 'op': '+'}
instructions[1058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1060] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1061] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1064] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1067] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810687992, 'op': 'memory_read_request'}
instructions[1068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1069] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810687992, 'op': 'memory_read_wait'}
instructions[1070] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810687992, 'element_size': 2, 'op': 'memory_read'}
instructions[1071] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1073] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1074] = {6'd11, 8'd142, 8'd141, 32'd42};//{'dest': 142, 'src': 141, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1077] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1078] = {6'd0, 8'd146, 8'd0, 32'd12};//{'dest': 146, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1081] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1084] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688424, 'op': 'memory_read_request'}
instructions[1085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1086] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688424, 'op': 'memory_read_wait'}
instructions[1087] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810688424, 'element_size': 2, 'op': 'memory_read'}
instructions[1088] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1091] = {6'd11, 8'd142, 8'd141, 32'd43};//{'dest': 142, 'src': 141, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1092] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1094] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1095] = {6'd0, 8'd146, 8'd0, 32'd13};//{'dest': 146, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1098] = {6'd11, 8'd147, 8'd146, 32'd52};//{'dest': 147, 'src': 146, 'srcb': 52, 'signed': False, 'op': '+'}
instructions[1099] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1101] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688856, 'op': 'memory_read_request'}
instructions[1102] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1103] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810688856, 'op': 'memory_read_wait'}
instructions[1104] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810688856, 'element_size': 2, 'op': 'memory_read'}
instructions[1105] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1106] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1108] = {6'd11, 8'd142, 8'd141, 32'd44};//{'dest': 142, 'src': 141, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1111] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1112] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1115] = {6'd3, 8'd53, 8'd140, 32'd0};//{'dest': 53, 'src': 140, 'op': 'move'}
instructions[1116] = {6'd3, 8'd140, 8'd45, 32'd0};//{'dest': 140, 'src': 45, 'op': 'move'}
instructions[1117] = {6'd14, 8'd45, 8'd45, 32'd1};//{'src': 45, 'right': 1, 'dest': 45, 'signed': False, 'op': '+', 'size': 2}
instructions[1118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1120] = {6'd3, 8'd141, 8'd45, 32'd0};//{'dest': 141, 'src': 45, 'op': 'move'}
instructions[1121] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1122] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1123] = {6'd25, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1126] = {6'd13, 8'd0, 8'd140, 32'd1132};//{'src': 140, 'label': 1132, 'op': 'jmp_if_false'}
instructions[1127] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1130] = {6'd3, 8'd45, 8'd140, 32'd0};//{'dest': 45, 'src': 140, 'op': 'move'}
instructions[1131] = {6'd15, 8'd0, 8'd0, 32'd1132};//{'label': 1132, 'op': 'goto'}
instructions[1132] = {6'd3, 8'd140, 8'd53, 32'd0};//{'dest': 140, 'src': 53, 'op': 'move'}
instructions[1133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1135] = {6'd3, 8'd47, 8'd140, 32'd0};//{'dest': 47, 'src': 140, 'op': 'move'}
instructions[1136] = {6'd6, 8'd0, 8'd46, 32'd0};//{'src': 46, 'op': 'jmp_to_reg'}
instructions[1137] = {6'd15, 8'd0, 8'd0, 32'd1138};//{'label': 1138, 'op': 'goto'}
instructions[1138] = {6'd15, 8'd0, 8'd0, 32'd1139};//{'label': 1139, 'op': 'goto'}
instructions[1139] = {6'd15, 8'd0, 8'd0, 32'd927};//{'label': 927, 'op': 'goto'}
instructions[1140] = {6'd0, 8'd60, 8'd0, 32'd0};//{'dest': 60, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1141] = {6'd0, 8'd61, 8'd0, 32'd0};//{'dest': 61, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1142] = {6'd0, 8'd62, 8'd0, 32'd0};//{'dest': 62, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1143] = {6'd3, 8'd141, 8'd58, 32'd0};//{'dest': 141, 'src': 58, 'op': 'move'}
instructions[1144] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1146] = {6'd3, 8'd48, 8'd141, 32'd0};//{'dest': 48, 'src': 141, 'op': 'move'}
instructions[1147] = {6'd3, 8'd141, 8'd59, 32'd0};//{'dest': 141, 'src': 59, 'op': 'move'}
instructions[1148] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1150] = {6'd3, 8'd49, 8'd141, 32'd0};//{'dest': 49, 'src': 141, 'op': 'move'}
instructions[1151] = {6'd1, 8'd46, 8'd0, 32'd754};//{'dest': 46, 'label': 754, 'op': 'jmp_and_link'}
instructions[1152] = {6'd3, 8'd140, 8'd47, 32'd0};//{'dest': 140, 'src': 47, 'op': 'move'}
instructions[1153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1155] = {6'd3, 8'd62, 8'd140, 32'd0};//{'dest': 62, 'src': 140, 'op': 'move'}
instructions[1156] = {6'd0, 8'd140, 8'd0, 32'd17664};//{'dest': 140, 'literal': 17664, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1157] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1160] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1161] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1163] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1164] = {6'd3, 8'd140, 8'd56, 32'd0};//{'dest': 140, 'src': 56, 'op': 'move'}
instructions[1165] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1168] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1171] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1172] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1173] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1176] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1179] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1180] = {6'd0, 8'd140, 8'd0, 32'd16384};//{'dest': 140, 'literal': 16384, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1181] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1183] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1184] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1186] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1187] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1188] = {6'd3, 8'd146, 8'd57, 32'd0};//{'dest': 146, 'src': 57, 'op': 'move'}
instructions[1189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1191] = {6'd30, 8'd140, 8'd146, 32'd65280};//{'src': 146, 'dest': 140, 'signed': False, 'op': '|', 'size': 2, 'type': 'int', 'left': 65280}
instructions[1192] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1195] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1198] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1199] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1200] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1201] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1203] = {6'd27, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': True, 'op': '+'}
instructions[1204] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1206] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1207] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1208] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1211] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1214] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1215] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1216] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1219] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1222] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1223] = {6'd3, 8'd140, 8'd58, 32'd0};//{'dest': 140, 'src': 58, 'op': 'move'}
instructions[1224] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1227] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1230] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1231] = {6'd3, 8'd140, 8'd59, 32'd0};//{'dest': 140, 'src': 59, 'op': 'move'}
instructions[1232] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1234] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1235] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1238] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1239] = {6'd3, 8'd141, 8'd56, 32'd0};//{'dest': 141, 'src': 56, 'op': 'move'}
instructions[1240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1242] = {6'd14, 8'd140, 8'd141, 32'd14};//{'src': 141, 'right': 14, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1243] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1245] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1246] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1247] = {6'd0, 8'd140, 8'd0, 32'd7};//{'dest': 140, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1250] = {6'd3, 8'd61, 8'd140, 32'd0};//{'dest': 61, 'src': 140, 'op': 'move'}
instructions[1251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1252] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1253] = {6'd3, 8'd141, 8'd61, 32'd0};//{'dest': 141, 'src': 61, 'op': 'move'}
instructions[1254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1255] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1256] = {6'd31, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1258] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1259] = {6'd13, 8'd0, 8'd140, 32'd1277};//{'src': 140, 'label': 1277, 'op': 'jmp_if_false'}
instructions[1260] = {6'd3, 8'd142, 8'd61, 32'd0};//{'dest': 142, 'src': 61, 'op': 'move'}
instructions[1261] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1263] = {6'd11, 8'd146, 8'd142, 32'd55};//{'dest': 146, 'src': 142, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1265] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1266] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810743112, 'op': 'memory_read_request'}
instructions[1267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1268] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810743112, 'op': 'memory_read_wait'}
instructions[1269] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810743112, 'element_size': 2, 'op': 'memory_read'}
instructions[1270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1272] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1273] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1274] = {6'd3, 8'd140, 8'd61, 32'd0};//{'dest': 140, 'src': 61, 'op': 'move'}
instructions[1275] = {6'd14, 8'd61, 8'd61, 32'd1};//{'src': 61, 'right': 1, 'dest': 61, 'signed': False, 'op': '+', 'size': 2}
instructions[1276] = {6'd15, 8'd0, 8'd0, 32'd1251};//{'label': 1251, 'op': 'goto'}
instructions[1277] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1278] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1279] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1282] = {6'd11, 8'd142, 8'd141, 32'd55};//{'dest': 142, 'src': 141, 'srcb': 55, 'signed': False, 'op': '+'}
instructions[1283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1285] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1286] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1287] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1288] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1289] = {6'd28, 8'd140, 8'd141, 32'd64};//{'src': 141, 'right': 64, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[1290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1292] = {6'd13, 8'd0, 8'd140, 32'd1298};//{'src': 140, 'label': 1298, 'op': 'jmp_if_false'}
instructions[1293] = {6'd0, 8'd140, 8'd0, 32'd64};//{'dest': 140, 'literal': 64, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1295] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1296] = {6'd3, 8'd60, 8'd140, 32'd0};//{'dest': 60, 'src': 140, 'op': 'move'}
instructions[1297] = {6'd15, 8'd0, 8'd0, 32'd1298};//{'label': 1298, 'op': 'goto'}
instructions[1298] = {6'd3, 8'd143, 8'd55, 32'd0};//{'dest': 143, 'src': 55, 'op': 'move'}
instructions[1299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1301] = {6'd3, 8'd26, 8'd143, 32'd0};//{'dest': 26, 'src': 143, 'op': 'move'}
instructions[1302] = {6'd3, 8'd141, 8'd60, 32'd0};//{'dest': 141, 'src': 60, 'op': 'move'}
instructions[1303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1304] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1305] = {6'd3, 8'd27, 8'd141, 32'd0};//{'dest': 27, 'src': 141, 'op': 'move'}
instructions[1306] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1309] = {6'd11, 8'd146, 8'd142, 32'd42};//{'dest': 146, 'src': 142, 'srcb': 42, 'signed': False, 'op': '+'}
instructions[1310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1312] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810748928, 'op': 'memory_read_request'}
instructions[1313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1314] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810748928, 'op': 'memory_read_wait'}
instructions[1315] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810748928, 'element_size': 2, 'op': 'memory_read'}
instructions[1316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1318] = {6'd3, 8'd28, 8'd141, 32'd0};//{'dest': 28, 'src': 141, 'op': 'move'}
instructions[1319] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1321] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1322] = {6'd11, 8'd146, 8'd142, 32'd43};//{'dest': 146, 'src': 142, 'srcb': 43, 'signed': False, 'op': '+'}
instructions[1323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1325] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749072, 'op': 'memory_read_request'}
instructions[1326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1327] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749072, 'op': 'memory_read_wait'}
instructions[1328] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749072, 'element_size': 2, 'op': 'memory_read'}
instructions[1329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1331] = {6'd3, 8'd29, 8'd141, 32'd0};//{'dest': 29, 'src': 141, 'op': 'move'}
instructions[1332] = {6'd3, 8'd142, 8'd62, 32'd0};//{'dest': 142, 'src': 62, 'op': 'move'}
instructions[1333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1334] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1335] = {6'd11, 8'd146, 8'd142, 32'd44};//{'dest': 146, 'src': 142, 'srcb': 44, 'signed': False, 'op': '+'}
instructions[1336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1338] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749216, 'op': 'memory_read_request'}
instructions[1339] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1340] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749216, 'op': 'memory_read_wait'}
instructions[1341] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749216, 'element_size': 2, 'op': 'memory_read'}
instructions[1342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1344] = {6'd3, 8'd30, 8'd141, 32'd0};//{'dest': 30, 'src': 141, 'op': 'move'}
instructions[1345] = {6'd0, 8'd141, 8'd0, 32'd2048};//{'dest': 141, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1347] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1348] = {6'd3, 8'd31, 8'd141, 32'd0};//{'dest': 31, 'src': 141, 'op': 'move'}
instructions[1349] = {6'd1, 8'd25, 8'd0, 32'd218};//{'dest': 25, 'label': 218, 'op': 'jmp_and_link'}
instructions[1350] = {6'd6, 8'd0, 8'd54, 32'd0};//{'src': 54, 'op': 'jmp_to_reg'}
instructions[1351] = {6'd0, 8'd66, 8'd0, 32'd0};//{'dest': 66, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1352] = {6'd0, 8'd67, 8'd0, 32'd0};//{'dest': 67, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1353] = {6'd0, 8'd68, 8'd0, 32'd0};//{'dest': 68, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1354] = {6'd0, 8'd69, 8'd0, 32'd0};//{'dest': 69, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1355] = {6'd0, 8'd70, 8'd0, 32'd0};//{'dest': 70, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1356] = {6'd0, 8'd71, 8'd0, 32'd0};//{'dest': 71, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1357] = {6'd0, 8'd72, 8'd0, 32'd0};//{'dest': 72, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1358] = {6'd0, 8'd73, 8'd0, 32'd0};//{'dest': 73, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1359] = {6'd0, 8'd74, 8'd0, 32'd0};//{'dest': 74, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1360] = {6'd3, 8'd143, 8'd65, 32'd0};//{'dest': 143, 'src': 65, 'op': 'move'}
instructions[1361] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1363] = {6'd3, 8'd36, 8'd143, 32'd0};//{'dest': 36, 'src': 143, 'op': 'move'}
instructions[1364] = {6'd1, 8'd34, 8'd0, 32'd328};//{'dest': 34, 'label': 328, 'op': 'jmp_and_link'}
instructions[1365] = {6'd3, 8'd140, 8'd35, 32'd0};//{'dest': 140, 'src': 35, 'op': 'move'}
instructions[1366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1368] = {6'd3, 8'd74, 8'd140, 32'd0};//{'dest': 74, 'src': 140, 'op': 'move'}
instructions[1369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1371] = {6'd3, 8'd141, 8'd74, 32'd0};//{'dest': 141, 'src': 74, 'op': 'move'}
instructions[1372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1374] = {6'd25, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1377] = {6'd13, 8'd0, 8'd140, 32'd1384};//{'src': 140, 'label': 1384, 'op': 'jmp_if_false'}
instructions[1378] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1379] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1380] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1381] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1382] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1383] = {6'd15, 8'd0, 8'd0, 32'd1384};//{'label': 1384, 'op': 'goto'}
instructions[1384] = {6'd0, 8'd142, 8'd0, 32'd6};//{'dest': 142, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1387] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1388] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1390] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749936, 'op': 'memory_read_request'}
instructions[1391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1392] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810749936, 'op': 'memory_read_wait'}
instructions[1393] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810749936, 'element_size': 2, 'op': 'memory_read'}
instructions[1394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1396] = {6'd26, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1397] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1399] = {6'd13, 8'd0, 8'd140, 32'd1406};//{'src': 140, 'label': 1406, 'op': 'jmp_if_false'}
instructions[1400] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1401] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1403] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1404] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1405] = {6'd15, 8'd0, 8'd0, 32'd1406};//{'label': 1406, 'op': 'goto'}
instructions[1406] = {6'd0, 8'd142, 8'd0, 32'd15};//{'dest': 142, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1409] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1410] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1412] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750440, 'op': 'memory_read_request'}
instructions[1413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1414] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750440, 'op': 'memory_read_wait'}
instructions[1415] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810750440, 'element_size': 2, 'op': 'memory_read'}
instructions[1416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1418] = {6'd26, 8'd140, 8'd141, 32'd49320};//{'src': 141, 'right': 49320, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1420] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1421] = {6'd13, 8'd0, 8'd140, 32'd1428};//{'src': 140, 'label': 1428, 'op': 'jmp_if_false'}
instructions[1422] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1425] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1426] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1427] = {6'd15, 8'd0, 8'd0, 32'd1428};//{'label': 1428, 'op': 'goto'}
instructions[1428] = {6'd0, 8'd142, 8'd0, 32'd16};//{'dest': 142, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1431] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750944, 'op': 'memory_read_request'}
instructions[1435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810750944, 'op': 'memory_read_wait'}
instructions[1437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810750944, 'element_size': 2, 'op': 'memory_read'}
instructions[1438] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1440] = {6'd26, 8'd140, 8'd141, 32'd119};//{'src': 141, 'right': 119, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1443] = {6'd13, 8'd0, 8'd140, 32'd1450};//{'src': 140, 'label': 1450, 'op': 'jmp_if_false'}
instructions[1444] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1447] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1448] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1449] = {6'd15, 8'd0, 8'd0, 32'd1450};//{'label': 1450, 'op': 'goto'}
instructions[1450] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1453] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1454] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1456] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811492968, 'op': 'memory_read_request'}
instructions[1457] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1458] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811492968, 'op': 'memory_read_wait'}
instructions[1459] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887811492968, 'element_size': 2, 'op': 'memory_read'}
instructions[1460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1462] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1464] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1465] = {6'd25, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1467] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1468] = {6'd13, 8'd0, 8'd140, 32'd1675};//{'src': 140, 'label': 1675, 'op': 'jmp_if_false'}
instructions[1469] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1470] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1472] = {6'd11, 8'd149, 8'd147, 32'd65};//{'dest': 149, 'src': 147, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1473] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1474] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1475] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810781056, 'op': 'memory_read_request'}
instructions[1476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1477] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810781056, 'op': 'memory_read_wait'}
instructions[1478] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810781056, 'element_size': 2, 'op': 'memory_read'}
instructions[1479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1481] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1483] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1484] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1486] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1487] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[1488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1490] = {6'd3, 8'd67, 8'd140, 32'd0};//{'dest': 67, 'src': 140, 'op': 'move'}
instructions[1491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1493] = {6'd3, 8'd141, 8'd67, 32'd0};//{'dest': 141, 'src': 67, 'op': 'move'}
instructions[1494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1496] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1499] = {6'd3, 8'd68, 8'd140, 32'd0};//{'dest': 68, 'src': 140, 'op': 'move'}
instructions[1500] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1503] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1504] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1506] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810751160, 'op': 'memory_read_request'}
instructions[1507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1508] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810751160, 'op': 'memory_read_wait'}
instructions[1509] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810751160, 'element_size': 2, 'op': 'memory_read'}
instructions[1510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1512] = {6'd3, 8'd66, 8'd140, 32'd0};//{'dest': 66, 'src': 140, 'op': 'move'}
instructions[1513] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1514] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1515] = {6'd3, 8'd146, 8'd66, 32'd0};//{'dest': 146, 'src': 66, 'op': 'move'}
instructions[1516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1518] = {6'd14, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1521] = {6'd32, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[1522] = {6'd3, 8'd142, 8'd67, 32'd0};//{'dest': 142, 'src': 67, 'op': 'move'}
instructions[1523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1525] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1528] = {6'd3, 8'd69, 8'd140, 32'd0};//{'dest': 69, 'src': 140, 'op': 'move'}
instructions[1529] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1531] = {6'd3, 8'd146, 8'd69, 32'd0};//{'dest': 146, 'src': 69, 'op': 'move'}
instructions[1532] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1534] = {6'd11, 8'd141, 8'd142, 32'd146};//{'srcb': 146, 'src': 142, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1535] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1537] = {6'd35, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[1538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1539] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1540] = {6'd3, 8'd73, 8'd140, 32'd0};//{'dest': 73, 'src': 140, 'op': 'move'}
instructions[1541] = {6'd3, 8'd142, 8'd68, 32'd0};//{'dest': 142, 'src': 68, 'op': 'move'}
instructions[1542] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1544] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1547] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810744192, 'op': 'memory_read_request'}
instructions[1548] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1549] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810744192, 'op': 'memory_read_wait'}
instructions[1550] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810744192, 'element_size': 2, 'op': 'memory_read'}
instructions[1551] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1552] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1553] = {6'd25, 8'd140, 8'd141, 32'd2048};//{'src': 141, 'right': 2048, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[1554] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1555] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1556] = {6'd13, 8'd0, 8'd140, 32'd1669};//{'src': 140, 'label': 1669, 'op': 'jmp_if_false'}
instructions[1557] = {6'd0, 8'd140, 8'd0, 32'd19};//{'dest': 140, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1558] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1560] = {6'd3, 8'd72, 8'd140, 32'd0};//{'dest': 72, 'src': 140, 'op': 'move'}
instructions[1561] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[1562] = {6'd3, 8'd141, 8'd68, 32'd0};//{'dest': 141, 'src': 68, 'op': 'move'}
instructions[1563] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1564] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1565] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1566] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1567] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1568] = {6'd3, 8'd71, 8'd140, 32'd0};//{'dest': 71, 'src': 140, 'op': 'move'}
instructions[1569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1570] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1571] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1572] = {6'd3, 8'd142, 8'd73, 32'd0};//{'dest': 142, 'src': 73, 'op': 'move'}
instructions[1573] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1574] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1575] = {6'd36, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<=', 'type': 'int', 'size': 2}
instructions[1576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1577] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1578] = {6'd13, 8'd0, 8'd140, 32'd1612};//{'src': 140, 'label': 1612, 'op': 'jmp_if_false'}
instructions[1579] = {6'd3, 8'd141, 8'd71, 32'd0};//{'dest': 141, 'src': 71, 'op': 'move'}
instructions[1580] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1582] = {6'd11, 8'd142, 8'd141, 32'd65};//{'dest': 142, 'src': 141, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1583] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1584] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1585] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810779904, 'op': 'memory_read_request'}
instructions[1586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1587] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810779904, 'op': 'memory_read_wait'}
instructions[1588] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810779904, 'element_size': 2, 'op': 'memory_read'}
instructions[1589] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1591] = {6'd3, 8'd70, 8'd140, 32'd0};//{'dest': 70, 'src': 140, 'op': 'move'}
instructions[1592] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1594] = {6'd3, 8'd141, 8'd70, 32'd0};//{'dest': 141, 'src': 70, 'op': 'move'}
instructions[1595] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1596] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1597] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[1598] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[1599] = {6'd3, 8'd140, 8'd70, 32'd0};//{'dest': 140, 'src': 70, 'op': 'move'}
instructions[1600] = {6'd3, 8'd141, 8'd72, 32'd0};//{'dest': 141, 'src': 72, 'op': 'move'}
instructions[1601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1602] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1603] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1604] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1605] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1606] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1607] = {6'd3, 8'd140, 8'd72, 32'd0};//{'dest': 140, 'src': 72, 'op': 'move'}
instructions[1608] = {6'd14, 8'd72, 8'd72, 32'd1};//{'src': 72, 'right': 1, 'dest': 72, 'signed': False, 'op': '+', 'size': 2}
instructions[1609] = {6'd3, 8'd140, 8'd71, 32'd0};//{'dest': 140, 'src': 71, 'op': 'move'}
instructions[1610] = {6'd14, 8'd71, 8'd71, 32'd1};//{'src': 71, 'right': 1, 'dest': 71, 'signed': False, 'op': '+', 'size': 2}
instructions[1611] = {6'd15, 8'd0, 8'd0, 32'd1569};//{'label': 1569, 'op': 'goto'}
instructions[1612] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1613] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1614] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1616] = {6'd27, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': True, 'op': '+'}
instructions[1617] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1619] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1620] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[1621] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[1622] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1625] = {6'd11, 8'd142, 8'd141, 32'd10};//{'dest': 142, 'src': 141, 'srcb': 10, 'signed': False, 'op': '+'}
instructions[1626] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1627] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1628] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1629] = {6'd3, 8'd148, 8'd10, 32'd0};//{'dest': 148, 'src': 10, 'op': 'move'}
instructions[1630] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1631] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1632] = {6'd3, 8'd55, 8'd148, 32'd0};//{'dest': 55, 'src': 148, 'op': 'move'}
instructions[1633] = {6'd3, 8'd141, 8'd66, 32'd0};//{'dest': 141, 'src': 66, 'op': 'move'}
instructions[1634] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1635] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1636] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[1637] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1638] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1639] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1640] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[1641] = {6'd0, 8'd142, 8'd0, 32'd13};//{'dest': 142, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1642] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1644] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1645] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1646] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1647] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264096, 'op': 'memory_read_request'}
instructions[1648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1649] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264096, 'op': 'memory_read_wait'}
instructions[1650] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810264096, 'element_size': 2, 'op': 'memory_read'}
instructions[1651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1653] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[1654] = {6'd0, 8'd142, 8'd0, 32'd14};//{'dest': 142, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1657] = {6'd11, 8'd146, 8'd142, 32'd65};//{'dest': 146, 'src': 142, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1658] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1659] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1660] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264240, 'op': 'memory_read_request'}
instructions[1661] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1662] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810264240, 'op': 'memory_read_wait'}
instructions[1663] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810264240, 'element_size': 2, 'op': 'memory_read'}
instructions[1664] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1665] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1666] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[1667] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[1668] = {6'd15, 8'd0, 8'd0, 32'd1669};//{'label': 1669, 'op': 'goto'}
instructions[1669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1672] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1673] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1674] = {6'd15, 8'd0, 8'd0, 32'd1675};//{'label': 1675, 'op': 'goto'}
instructions[1675] = {6'd0, 8'd146, 8'd0, 32'd11};//{'dest': 146, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1676] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1677] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1678] = {6'd11, 8'd147, 8'd146, 32'd65};//{'dest': 147, 'src': 146, 'srcb': 65, 'signed': False, 'op': '+'}
instructions[1679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1680] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1681] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810264672, 'op': 'memory_read_request'}
instructions[1682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1683] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810264672, 'op': 'memory_read_wait'}
instructions[1684] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810264672, 'element_size': 2, 'op': 'memory_read'}
instructions[1685] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1687] = {6'd12, 8'd141, 8'd142, 32'd255};//{'src': 142, 'right': 255, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[1688] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1689] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1690] = {6'd26, 8'd140, 8'd141, 32'd6};//{'src': 141, 'right': 6, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[1691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1692] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1693] = {6'd13, 8'd0, 8'd140, 32'd1700};//{'src': 140, 'label': 1700, 'op': 'jmp_if_false'}
instructions[1694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1697] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1698] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1699] = {6'd15, 8'd0, 8'd0, 32'd1700};//{'label': 1700, 'op': 'goto'}
instructions[1700] = {6'd3, 8'd140, 8'd74, 32'd0};//{'dest': 140, 'src': 74, 'op': 'move'}
instructions[1701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1702] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1703] = {6'd3, 8'd64, 8'd140, 32'd0};//{'dest': 64, 'src': 140, 'op': 'move'}
instructions[1704] = {6'd6, 8'd0, 8'd63, 32'd0};//{'src': 63, 'op': 'jmp_to_reg'}
instructions[1705] = {6'd0, 8'd100, 8'd0, 32'd17};//{'dest': 100, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1706] = {6'd0, 8'd101, 8'd0, 32'd0};//{'dest': 101, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1707] = {6'd0, 8'd102, 8'd0, 32'd0};//{'dest': 102, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1708] = {6'd0, 8'd103, 8'd0, 32'd0};//{'dest': 103, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1709] = {6'd3, 8'd140, 8'd77, 32'd0};//{'dest': 140, 'src': 77, 'op': 'move'}
instructions[1710] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1713] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1714] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1715] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1716] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1718] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1719] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1720] = {6'd3, 8'd140, 8'd78, 32'd0};//{'dest': 140, 'src': 78, 'op': 'move'}
instructions[1721] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1722] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1723] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1724] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1726] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1727] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1729] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1730] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1731] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1734] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1737] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810299664, 'op': 'memory_read_request'}
instructions[1738] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1739] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810299664, 'op': 'memory_read_wait'}
instructions[1740] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810299664, 'element_size': 2, 'op': 'memory_read'}
instructions[1741] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1742] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1744] = {6'd14, 8'd141, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1745] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1746] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1747] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1750] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1751] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1753] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1754] = {6'd11, 8'd147, 8'd146, 32'd79};//{'dest': 147, 'src': 146, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[1755] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1757] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300240, 'op': 'memory_read_request'}
instructions[1758] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1759] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300240, 'op': 'memory_read_wait'}
instructions[1760] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810300240, 'element_size': 2, 'op': 'memory_read'}
instructions[1761] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1762] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1763] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1764] = {6'd14, 8'd141, 8'd146, 32'd3};//{'src': 146, 'right': 3, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1766] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1767] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1769] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1770] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1771] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1774] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1777] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300816, 'op': 'memory_read_request'}
instructions[1778] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1779] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810300816, 'op': 'memory_read_wait'}
instructions[1780] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810300816, 'element_size': 2, 'op': 'memory_read'}
instructions[1781] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1782] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1784] = {6'd14, 8'd141, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1785] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1786] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1787] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1790] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1791] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1793] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1794] = {6'd11, 8'd147, 8'd146, 32'd81};//{'dest': 147, 'src': 146, 'srcb': 81, 'signed': False, 'op': '+'}
instructions[1795] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1797] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810301392, 'op': 'memory_read_request'}
instructions[1798] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1799] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810301392, 'op': 'memory_read_wait'}
instructions[1800] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810301392, 'element_size': 2, 'op': 'memory_read'}
instructions[1801] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1802] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1803] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1804] = {6'd14, 8'd141, 8'd146, 32'd5};//{'src': 146, 'right': 5, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1806] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1807] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1809] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1810] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1811] = {6'd0, 8'd140, 8'd0, 32'd20480};//{'dest': 140, 'literal': 20480, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1812] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1814] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1815] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1817] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1818] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1819] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1821] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1822] = {6'd3, 8'd140, 8'd82, 32'd0};//{'dest': 140, 'src': 82, 'op': 'move'}
instructions[1823] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1825] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1826] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1827] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1829] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1830] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1832] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1833] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1834] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1835] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1837] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1838] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1840] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1841] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1842] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1843] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1844] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[1845] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1846] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1848] = {6'd14, 8'd141, 8'd146, 32'd9};//{'src': 146, 'right': 9, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1849] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1850] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1851] = {6'd27, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': True, 'op': '+'}
instructions[1852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1854] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1855] = {6'd3, 8'd140, 8'd83, 32'd0};//{'dest': 140, 'src': 83, 'op': 'move'}
instructions[1856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1857] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1858] = {6'd13, 8'd0, 8'd140, 32'd1886};//{'src': 140, 'label': 1886, 'op': 'jmp_if_false'}
instructions[1859] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1862] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1865] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1866] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1867] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1868] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533136, 'op': 'memory_read_request'}
instructions[1869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1870] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533136, 'op': 'memory_read_wait'}
instructions[1871] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811533136, 'element_size': 2, 'op': 'memory_read'}
instructions[1872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1873] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1874] = {6'd37, 8'd140, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1875] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1878] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1881] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1882] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1884] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1885] = {6'd15, 8'd0, 8'd0, 32'd1886};//{'label': 1886, 'op': 'goto'}
instructions[1886] = {6'd3, 8'd140, 8'd84, 32'd0};//{'dest': 140, 'src': 84, 'op': 'move'}
instructions[1887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1888] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1889] = {6'd13, 8'd0, 8'd140, 32'd1917};//{'src': 140, 'label': 1917, 'op': 'jmp_if_false'}
instructions[1890] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1891] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1893] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1894] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1895] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1896] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1898] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1899] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533856, 'op': 'memory_read_request'}
instructions[1900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1901] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811533856, 'op': 'memory_read_wait'}
instructions[1902] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811533856, 'element_size': 2, 'op': 'memory_read'}
instructions[1903] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1904] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1905] = {6'd37, 8'd140, 8'd146, 32'd2};//{'src': 146, 'right': 2, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1906] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1907] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1908] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1909] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1910] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1911] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1912] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1914] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1915] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1916] = {6'd15, 8'd0, 8'd0, 32'd1917};//{'label': 1917, 'op': 'goto'}
instructions[1917] = {6'd3, 8'd140, 8'd85, 32'd0};//{'dest': 140, 'src': 85, 'op': 'move'}
instructions[1918] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1919] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1920] = {6'd13, 8'd0, 8'd140, 32'd1948};//{'src': 140, 'label': 1948, 'op': 'jmp_if_false'}
instructions[1921] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1922] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1923] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1924] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1926] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1927] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1928] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1930] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811534576, 'op': 'memory_read_request'}
instructions[1931] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1932] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887811534576, 'op': 'memory_read_wait'}
instructions[1933] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887811534576, 'element_size': 2, 'op': 'memory_read'}
instructions[1934] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1935] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1936] = {6'd37, 8'd140, 8'd146, 32'd4};//{'src': 146, 'right': 4, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1937] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1938] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1939] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1940] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1942] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1943] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1946] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1947] = {6'd15, 8'd0, 8'd0, 32'd1948};//{'label': 1948, 'op': 'goto'}
instructions[1948] = {6'd3, 8'd140, 8'd86, 32'd0};//{'dest': 140, 'src': 86, 'op': 'move'}
instructions[1949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1950] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1951] = {6'd13, 8'd0, 8'd140, 32'd1979};//{'src': 140, 'label': 1979, 'op': 'jmp_if_false'}
instructions[1952] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1954] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1955] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1958] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1959] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1961] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327040, 'op': 'memory_read_request'}
instructions[1962] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1963] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327040, 'op': 'memory_read_wait'}
instructions[1964] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810327040, 'element_size': 2, 'op': 'memory_read'}
instructions[1965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1966] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1967] = {6'd37, 8'd140, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1968] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[1969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1971] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1974] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1976] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1977] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[1978] = {6'd15, 8'd0, 8'd0, 32'd1979};//{'label': 1979, 'op': 'goto'}
instructions[1979] = {6'd3, 8'd140, 8'd87, 32'd0};//{'dest': 140, 'src': 87, 'op': 'move'}
instructions[1980] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1981] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1982] = {6'd13, 8'd0, 8'd140, 32'd2010};//{'src': 140, 'label': 2010, 'op': 'jmp_if_false'}
instructions[1983] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[1984] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1986] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[1987] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1989] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[1990] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1992] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327760, 'op': 'memory_read_request'}
instructions[1993] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1994] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810327760, 'op': 'memory_read_wait'}
instructions[1995] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810327760, 'element_size': 2, 'op': 'memory_read'}
instructions[1996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1997] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[1998] = {6'd37, 8'd140, 8'd146, 32'd16};//{'src': 146, 'right': 16, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[1999] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2001] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2002] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2005] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2006] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2008] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2009] = {6'd15, 8'd0, 8'd0, 32'd2010};//{'label': 2010, 'op': 'goto'}
instructions[2010] = {6'd3, 8'd140, 8'd88, 32'd0};//{'dest': 140, 'src': 88, 'op': 'move'}
instructions[2011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2013] = {6'd13, 8'd0, 8'd140, 32'd2041};//{'src': 140, 'label': 2041, 'op': 'jmp_if_false'}
instructions[2014] = {6'd3, 8'd150, 8'd100, 32'd0};//{'dest': 150, 'src': 100, 'op': 'move'}
instructions[2015] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2016] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2017] = {6'd14, 8'd147, 8'd150, 32'd6};//{'src': 150, 'right': 6, 'dest': 147, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2019] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2020] = {6'd11, 8'd149, 8'd147, 32'd98};//{'dest': 149, 'src': 147, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2023] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810328480, 'op': 'memory_read_request'}
instructions[2024] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2025] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810328480, 'op': 'memory_read_wait'}
instructions[2026] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810328480, 'element_size': 2, 'op': 'memory_read'}
instructions[2027] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2028] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2029] = {6'd37, 8'd140, 8'd146, 32'd32};//{'src': 146, 'right': 32, 'dest': 140, 'signed': False, 'op': '|', 'type': 'int', 'size': 2}
instructions[2030] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2031] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2032] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2033] = {6'd14, 8'd141, 8'd146, 32'd6};//{'src': 146, 'right': 6, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2034] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2036] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2037] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2038] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2039] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2040] = {6'd15, 8'd0, 8'd0, 32'd2041};//{'label': 2041, 'op': 'goto'}
instructions[2041] = {6'd1, 8'd12, 8'd0, 32'd59};//{'dest': 12, 'label': 59, 'op': 'jmp_and_link'}
instructions[2042] = {6'd0, 8'd141, 8'd0, 32'd49320};//{'dest': 141, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2043] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2045] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2046] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2047] = {6'd0, 8'd141, 8'd0, 32'd119};//{'dest': 141, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2050] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2051] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2052] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2053] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2055] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2056] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2057] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2060] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2061] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2062] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2063] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2064] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2065] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2066] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2067] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2070] = {6'd14, 8'd141, 8'd142, 32'd20};//{'src': 142, 'right': 20, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2072] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2073] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2074] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2075] = {6'd3, 8'd146, 8'd99, 32'd0};//{'dest': 146, 'src': 99, 'op': 'move'}
instructions[2076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2077] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2078] = {6'd14, 8'd142, 8'd146, 32'd20};//{'src': 146, 'right': 20, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2080] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2081] = {6'd14, 8'd141, 8'd142, 32'd1};//{'src': 142, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2084] = {6'd32, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2085] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2087] = {6'd3, 8'd101, 8'd140, 32'd0};//{'dest': 101, 'src': 140, 'op': 'move'}
instructions[2088] = {6'd3, 8'd140, 8'd100, 32'd0};//{'dest': 140, 'src': 100, 'op': 'move'}
instructions[2089] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2091] = {6'd3, 8'd102, 8'd140, 32'd0};//{'dest': 102, 'src': 140, 'op': 'move'}
instructions[2092] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2093] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2094] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2095] = {6'd3, 8'd103, 8'd140, 32'd0};//{'dest': 103, 'src': 140, 'op': 'move'}
instructions[2096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2098] = {6'd3, 8'd141, 8'd103, 32'd0};//{'dest': 141, 'src': 103, 'op': 'move'}
instructions[2099] = {6'd3, 8'd142, 8'd101, 32'd0};//{'dest': 142, 'src': 101, 'op': 'move'}
instructions[2100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2102] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2103] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2105] = {6'd13, 8'd0, 8'd140, 32'd2125};//{'src': 140, 'label': 2125, 'op': 'jmp_if_false'}
instructions[2106] = {6'd3, 8'd142, 8'd102, 32'd0};//{'dest': 142, 'src': 102, 'op': 'move'}
instructions[2107] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2109] = {6'd11, 8'd146, 8'd142, 32'd98};//{'dest': 146, 'src': 142, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2110] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2111] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2112] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810349176, 'op': 'memory_read_request'}
instructions[2113] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2114] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810349176, 'op': 'memory_read_wait'}
instructions[2115] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810349176, 'element_size': 2, 'op': 'memory_read'}
instructions[2116] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2117] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2118] = {6'd3, 8'd14, 8'd141, 32'd0};//{'dest': 14, 'src': 141, 'op': 'move'}
instructions[2119] = {6'd1, 8'd13, 8'd0, 32'd64};//{'dest': 13, 'label': 64, 'op': 'jmp_and_link'}
instructions[2120] = {6'd3, 8'd140, 8'd102, 32'd0};//{'dest': 140, 'src': 102, 'op': 'move'}
instructions[2121] = {6'd14, 8'd102, 8'd102, 32'd1};//{'src': 102, 'right': 1, 'dest': 102, 'signed': False, 'op': '+', 'size': 2}
instructions[2122] = {6'd3, 8'd140, 8'd103, 32'd0};//{'dest': 140, 'src': 103, 'op': 'move'}
instructions[2123] = {6'd14, 8'd103, 8'd103, 32'd1};//{'src': 103, 'right': 1, 'dest': 103, 'signed': False, 'op': '+', 'size': 2}
instructions[2124] = {6'd15, 8'd0, 8'd0, 32'd2096};//{'label': 2096, 'op': 'goto'}
instructions[2125] = {6'd1, 8'd15, 8'd0, 32'd100};//{'dest': 15, 'label': 100, 'op': 'jmp_and_link'}
instructions[2126] = {6'd3, 8'd140, 8'd16, 32'd0};//{'dest': 140, 'src': 16, 'op': 'move'}
instructions[2127] = {6'd3, 8'd146, 8'd100, 32'd0};//{'dest': 146, 'src': 100, 'op': 'move'}
instructions[2128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2130] = {6'd14, 8'd141, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2131] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2133] = {6'd11, 8'd142, 8'd141, 32'd98};//{'dest': 142, 'src': 141, 'srcb': 98, 'signed': False, 'op': '+'}
instructions[2134] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2135] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2136] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2137] = {6'd3, 8'd143, 8'd98, 32'd0};//{'dest': 143, 'src': 98, 'op': 'move'}
instructions[2138] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2139] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2140] = {6'd3, 8'd55, 8'd143, 32'd0};//{'dest': 55, 'src': 143, 'op': 'move'}
instructions[2141] = {6'd3, 8'd142, 8'd99, 32'd0};//{'dest': 142, 'src': 99, 'op': 'move'}
instructions[2142] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2143] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2144] = {6'd14, 8'd141, 8'd142, 32'd40};//{'src': 142, 'right': 40, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2145] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2147] = {6'd3, 8'd56, 8'd141, 32'd0};//{'dest': 56, 'src': 141, 'op': 'move'}
instructions[2148] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2149] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2151] = {6'd3, 8'd57, 8'd141, 32'd0};//{'dest': 57, 'src': 141, 'op': 'move'}
instructions[2152] = {6'd3, 8'd141, 8'd75, 32'd0};//{'dest': 141, 'src': 75, 'op': 'move'}
instructions[2153] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2154] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2155] = {6'd3, 8'd58, 8'd141, 32'd0};//{'dest': 58, 'src': 141, 'op': 'move'}
instructions[2156] = {6'd3, 8'd141, 8'd76, 32'd0};//{'dest': 141, 'src': 76, 'op': 'move'}
instructions[2157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2158] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2159] = {6'd3, 8'd59, 8'd141, 32'd0};//{'dest': 59, 'src': 141, 'op': 'move'}
instructions[2160] = {6'd1, 8'd54, 8'd0, 32'd1140};//{'dest': 54, 'label': 1140, 'op': 'jmp_and_link'}
instructions[2161] = {6'd6, 8'd0, 8'd97, 32'd0};//{'src': 97, 'op': 'jmp_to_reg'}
instructions[2162] = {6'd0, 8'd109, 8'd0, 32'd0};//{'dest': 109, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2163] = {6'd0, 8'd110, 8'd0, 32'd0};//{'dest': 110, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2164] = {6'd0, 8'd111, 8'd0, 32'd0};//{'dest': 111, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2165] = {6'd0, 8'd112, 8'd0, 32'd0};//{'dest': 112, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2166] = {6'd0, 8'd113, 8'd0, 32'd0};//{'dest': 113, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2167] = {6'd0, 8'd114, 8'd0, 32'd0};//{'dest': 114, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2168] = {6'd3, 8'd143, 8'd108, 32'd0};//{'dest': 143, 'src': 108, 'op': 'move'}
instructions[2169] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2170] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2171] = {6'd3, 8'd65, 8'd143, 32'd0};//{'dest': 65, 'src': 143, 'op': 'move'}
instructions[2172] = {6'd1, 8'd63, 8'd0, 32'd1351};//{'dest': 63, 'label': 1351, 'op': 'jmp_and_link'}
instructions[2173] = {6'd3, 8'd140, 8'd64, 32'd0};//{'dest': 140, 'src': 64, 'op': 'move'}
instructions[2174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2176] = {6'd3, 8'd109, 8'd140, 32'd0};//{'dest': 109, 'src': 140, 'op': 'move'}
instructions[2177] = {6'd0, 8'd147, 8'd0, 32'd7};//{'dest': 147, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2179] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2180] = {6'd11, 8'd149, 8'd147, 32'd108};//{'dest': 149, 'src': 147, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2183] = {6'd17, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810371096, 'op': 'memory_read_request'}
instructions[2184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2185] = {6'd18, 8'd0, 8'd149, 32'd0};//{'element_size': 2, 'src': 149, 'sequence': 139887810371096, 'op': 'memory_read_wait'}
instructions[2186] = {6'd19, 8'd146, 8'd149, 32'd0};//{'dest': 146, 'src': 149, 'sequence': 139887810371096, 'element_size': 2, 'op': 'memory_read'}
instructions[2187] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2189] = {6'd32, 8'd142, 8'd146, 32'd8};//{'src': 146, 'right': 8, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2190] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2192] = {6'd12, 8'd141, 8'd142, 32'd15};//{'src': 142, 'right': 15, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2193] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2194] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2195] = {6'd33, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2198] = {6'd3, 8'd110, 8'd140, 32'd0};//{'dest': 110, 'src': 140, 'op': 'move'}
instructions[2199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2201] = {6'd3, 8'd141, 8'd110, 32'd0};//{'dest': 141, 'src': 110, 'op': 'move'}
instructions[2202] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2203] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2204] = {6'd14, 8'd140, 8'd141, 32'd7};//{'src': 141, 'right': 7, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2207] = {6'd3, 8'd111, 8'd140, 32'd0};//{'dest': 111, 'src': 140, 'op': 'move'}
instructions[2208] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2211] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2212] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2214] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810777744, 'op': 'memory_read_request'}
instructions[2215] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2216] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810777744, 'op': 'memory_read_wait'}
instructions[2217] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810777744, 'element_size': 2, 'op': 'memory_read'}
instructions[2218] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2219] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2220] = {6'd3, 8'd112, 8'd140, 32'd0};//{'dest': 112, 'src': 140, 'op': 'move'}
instructions[2221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2222] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2223] = {6'd3, 8'd141, 8'd112, 32'd0};//{'dest': 141, 'src': 112, 'op': 'move'}
instructions[2224] = {6'd3, 8'd146, 8'd110, 32'd0};//{'dest': 146, 'src': 110, 'op': 'move'}
instructions[2225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2226] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2227] = {6'd33, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '<<', 'type': 'int', 'size': 2}
instructions[2228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2230] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2231] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2233] = {6'd3, 8'd113, 8'd140, 32'd0};//{'dest': 113, 'src': 140, 'op': 'move'}
instructions[2234] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2235] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2237] = {6'd14, 8'd146, 8'd149, 32'd6};//{'src': 149, 'right': 6, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2238] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2239] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2240] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2242] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2243] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381872, 'op': 'memory_read_request'}
instructions[2244] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2245] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381872, 'op': 'memory_read_wait'}
instructions[2246] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810381872, 'element_size': 2, 'op': 'memory_read'}
instructions[2247] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2248] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2249] = {6'd12, 8'd141, 8'd142, 32'd61440};//{'src': 142, 'right': 61440, 'dest': 141, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2251] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2252] = {6'd32, 8'd140, 8'd141, 32'd10};//{'src': 141, 'right': 10, 'dest': 140, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2255] = {6'd3, 8'd114, 8'd140, 32'd0};//{'dest': 114, 'src': 140, 'op': 'move'}
instructions[2256] = {6'd3, 8'd141, 8'd113, 32'd0};//{'dest': 141, 'src': 113, 'op': 'move'}
instructions[2257] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2258] = {6'd3, 8'd142, 8'd114, 32'd0};//{'dest': 142, 'src': 114, 'op': 'move'}
instructions[2259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2261] = {6'd34, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '-', 'type': 'int', 'size': 2}
instructions[2262] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2264] = {6'd3, 8'd104, 8'd140, 32'd0};//{'dest': 104, 'src': 140, 'op': 'move'}
instructions[2265] = {6'd3, 8'd141, 8'd111, 32'd0};//{'dest': 141, 'src': 111, 'op': 'move'}
instructions[2266] = {6'd3, 8'd146, 8'd114, 32'd0};//{'dest': 146, 'src': 114, 'op': 'move'}
instructions[2267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2268] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2269] = {6'd32, 8'd142, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 142, 'signed': False, 'op': '>>', 'type': 'int', 'size': 2}
instructions[2270] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2271] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2272] = {6'd11, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2275] = {6'd3, 8'd105, 8'd140, 32'd0};//{'dest': 105, 'src': 140, 'op': 'move'}
instructions[2276] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2278] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2279] = {6'd14, 8'd141, 8'd146, 32'd0};//{'src': 146, 'right': 0, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2282] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2285] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810351048, 'op': 'memory_read_request'}
instructions[2286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2287] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810351048, 'op': 'memory_read_wait'}
instructions[2288] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810351048, 'element_size': 2, 'op': 'memory_read'}
instructions[2289] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2291] = {6'd3, 8'd89, 8'd140, 32'd0};//{'dest': 89, 'src': 140, 'op': 'move'}
instructions[2292] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2295] = {6'd14, 8'd141, 8'd146, 32'd1};//{'src': 146, 'right': 1, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2296] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2298] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2299] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2301] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810367712, 'op': 'memory_read_request'}
instructions[2302] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2303] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810367712, 'op': 'memory_read_wait'}
instructions[2304] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810367712, 'element_size': 2, 'op': 'memory_read'}
instructions[2305] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2306] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2307] = {6'd3, 8'd90, 8'd140, 32'd0};//{'dest': 90, 'src': 140, 'op': 'move'}
instructions[2308] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2309] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2311] = {6'd14, 8'd146, 8'd149, 32'd2};//{'src': 149, 'right': 2, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2312] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2313] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2314] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2316] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2317] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380504, 'op': 'memory_read_request'}
instructions[2318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2319] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380504, 'op': 'memory_read_wait'}
instructions[2320] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810380504, 'element_size': 2, 'op': 'memory_read'}
instructions[2321] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2322] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2323] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2324] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2326] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2327] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2328] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2329] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2330] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2331] = {6'd14, 8'd146, 8'd149, 32'd3};//{'src': 149, 'right': 3, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2333] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2334] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2335] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2336] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2337] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380648, 'op': 'memory_read_request'}
instructions[2338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2339] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810380648, 'op': 'memory_read_wait'}
instructions[2340] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810380648, 'element_size': 2, 'op': 'memory_read'}
instructions[2341] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2343] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2344] = {6'd11, 8'd142, 8'd141, 32'd91};//{'dest': 142, 'src': 141, 'srcb': 91, 'signed': False, 'op': '+'}
instructions[2345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2347] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2348] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2349] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2351] = {6'd14, 8'd146, 8'd149, 32'd4};//{'src': 149, 'right': 4, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2352] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2353] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2354] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2356] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2357] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381368, 'op': 'memory_read_request'}
instructions[2358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2359] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810381368, 'op': 'memory_read_wait'}
instructions[2360] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810381368, 'element_size': 2, 'op': 'memory_read'}
instructions[2361] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2362] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2364] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2365] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2366] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2367] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2368] = {6'd3, 8'd149, 8'd111, 32'd0};//{'dest': 149, 'src': 111, 'op': 'move'}
instructions[2369] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2370] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2371] = {6'd14, 8'd146, 8'd149, 32'd5};//{'src': 149, 'right': 5, 'dest': 146, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2372] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2374] = {6'd11, 8'd147, 8'd146, 32'd108};//{'dest': 147, 'src': 146, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2375] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2376] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2377] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810382160, 'op': 'memory_read_request'}
instructions[2378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2379] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810382160, 'op': 'memory_read_wait'}
instructions[2380] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810382160, 'element_size': 2, 'op': 'memory_read'}
instructions[2381] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2383] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2384] = {6'd11, 8'd142, 8'd141, 32'd92};//{'dest': 142, 'src': 141, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[2385] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2387] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2388] = {6'd3, 8'd146, 8'd111, 32'd0};//{'dest': 146, 'src': 111, 'op': 'move'}
instructions[2389] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2391] = {6'd14, 8'd141, 8'd146, 32'd7};//{'src': 146, 'right': 7, 'dest': 141, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2392] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2393] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2394] = {6'd11, 8'd142, 8'd141, 32'd108};//{'dest': 142, 'src': 141, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2396] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2397] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810382664, 'op': 'memory_read_request'}
instructions[2398] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2399] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810382664, 'op': 'memory_read_wait'}
instructions[2400] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810382664, 'element_size': 2, 'op': 'memory_read'}
instructions[2401] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2402] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2404] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2405] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2407] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2408] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2410] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383168, 'op': 'memory_read_request'}
instructions[2411] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2412] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383168, 'op': 'memory_read_wait'}
instructions[2413] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810383168, 'element_size': 2, 'op': 'memory_read'}
instructions[2414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2415] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2416] = {6'd12, 8'd140, 8'd141, 32'd1};//{'src': 141, 'right': 1, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2418] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2419] = {6'd3, 8'd93, 8'd140, 32'd0};//{'dest': 93, 'src': 140, 'op': 'move'}
instructions[2420] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2421] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2423] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2424] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2426] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2427] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2428] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2429] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383816, 'op': 'memory_read_request'}
instructions[2430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2431] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810383816, 'op': 'memory_read_wait'}
instructions[2432] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810383816, 'element_size': 2, 'op': 'memory_read'}
instructions[2433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2434] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2435] = {6'd12, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2436] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2437] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2438] = {6'd3, 8'd94, 8'd140, 32'd0};//{'dest': 94, 'src': 140, 'op': 'move'}
instructions[2439] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2441] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2442] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2444] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2445] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2446] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2447] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2448] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810396816, 'op': 'memory_read_request'}
instructions[2449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2450] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810396816, 'op': 'memory_read_wait'}
instructions[2451] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810396816, 'element_size': 2, 'op': 'memory_read'}
instructions[2452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2453] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2454] = {6'd12, 8'd140, 8'd141, 32'd4};//{'src': 141, 'right': 4, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2457] = {6'd3, 8'd95, 8'd140, 32'd0};//{'dest': 95, 'src': 140, 'op': 'move'}
instructions[2458] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2459] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2460] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2461] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2463] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2464] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2467] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810397464, 'op': 'memory_read_request'}
instructions[2468] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2469] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810397464, 'op': 'memory_read_wait'}
instructions[2470] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810397464, 'element_size': 2, 'op': 'memory_read'}
instructions[2471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2473] = {6'd12, 8'd140, 8'd141, 32'd8};//{'src': 141, 'right': 8, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2474] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2477] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2478] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2479] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2480] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2482] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2483] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398112, 'op': 'memory_read_request'}
instructions[2484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2485] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398112, 'op': 'memory_read_wait'}
instructions[2486] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810398112, 'element_size': 2, 'op': 'memory_read'}
instructions[2487] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2489] = {6'd12, 8'd140, 8'd141, 32'd16};//{'src': 141, 'right': 16, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2490] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2491] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2492] = {6'd3, 8'd96, 8'd140, 32'd0};//{'dest': 96, 'src': 140, 'op': 'move'}
instructions[2493] = {6'd3, 8'd147, 8'd111, 32'd0};//{'dest': 147, 'src': 111, 'op': 'move'}
instructions[2494] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2495] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2496] = {6'd14, 8'd142, 8'd147, 32'd6};//{'src': 147, 'right': 6, 'dest': 142, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2497] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2499] = {6'd11, 8'd146, 8'd142, 32'd108};//{'dest': 146, 'src': 142, 'srcb': 108, 'signed': False, 'op': '+'}
instructions[2500] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2502] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398760, 'op': 'memory_read_request'}
instructions[2503] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2504] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810398760, 'op': 'memory_read_wait'}
instructions[2505] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810398760, 'element_size': 2, 'op': 'memory_read'}
instructions[2506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2507] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2508] = {6'd12, 8'd140, 8'd141, 32'd32};//{'src': 141, 'right': 32, 'dest': 140, 'signed': False, 'op': '&', 'type': 'int', 'size': 2}
instructions[2509] = {6'd3, 8'd140, 8'd109, 32'd0};//{'dest': 140, 'src': 109, 'op': 'move'}
instructions[2510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2511] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2512] = {6'd3, 8'd107, 8'd140, 32'd0};//{'dest': 107, 'src': 140, 'op': 'move'}
instructions[2513] = {6'd6, 8'd0, 8'd106, 32'd0};//{'src': 106, 'op': 'jmp_to_reg'}
instructions[2514] = {6'd0, 8'd119, 8'd0, 32'd0};//{'dest': 119, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2515] = {6'd0, 8'd120, 8'd0, 32'd0};//{'dest': 120, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2516] = {6'd3, 8'd140, 8'd117, 32'd0};//{'dest': 140, 'src': 117, 'op': 'move'}
instructions[2517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2518] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2519] = {6'd3, 8'd120, 8'd140, 32'd0};//{'dest': 120, 'src': 140, 'op': 'move'}
instructions[2520] = {6'd3, 8'd141, 8'd118, 32'd0};//{'dest': 141, 'src': 118, 'op': 'move'}
instructions[2521] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2522] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2523] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2524] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2525] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2526] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2527] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2528] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2529] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2531] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2532] = {6'd3, 8'd142, 8'd118, 32'd0};//{'dest': 142, 'src': 118, 'op': 'move'}
instructions[2533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2535] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2536] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2538] = {6'd13, 8'd0, 8'd140, 32'd2563};//{'src': 140, 'label': 2563, 'op': 'jmp_if_false'}
instructions[2539] = {6'd3, 8'd142, 8'd120, 32'd0};//{'dest': 142, 'src': 120, 'op': 'move'}
instructions[2540] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2541] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2542] = {6'd11, 8'd146, 8'd142, 32'd116};//{'dest': 146, 'src': 142, 'srcb': 116, 'signed': False, 'op': '+'}
instructions[2543] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2545] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810422904, 'op': 'memory_read_request'}
instructions[2546] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2547] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810422904, 'op': 'memory_read_wait'}
instructions[2548] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810422904, 'element_size': 2, 'op': 'memory_read'}
instructions[2549] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2550] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2551] = {6'd3, 8'd3, 8'd141, 32'd0};//{'dest': 3, 'src': 141, 'op': 'move'}
instructions[2552] = {6'd1, 8'd2, 8'd0, 32'd39};//{'dest': 2, 'label': 39, 'op': 'jmp_and_link'}
instructions[2553] = {6'd3, 8'd140, 8'd120, 32'd0};//{'dest': 140, 'src': 120, 'op': 'move'}
instructions[2554] = {6'd14, 8'd120, 8'd120, 32'd1};//{'src': 120, 'right': 1, 'dest': 120, 'signed': False, 'op': '+', 'size': 2}
instructions[2555] = {6'd3, 8'd141, 8'd119, 32'd0};//{'dest': 141, 'src': 119, 'op': 'move'}
instructions[2556] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2557] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2558] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2559] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2560] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2561] = {6'd3, 8'd119, 8'd140, 32'd0};//{'dest': 119, 'src': 140, 'op': 'move'}
instructions[2562] = {6'd15, 8'd0, 8'd0, 32'd2529};//{'label': 2529, 'op': 'goto'}
instructions[2563] = {6'd6, 8'd0, 8'd115, 32'd0};//{'src': 115, 'op': 'jmp_to_reg'}
instructions[2564] = {6'd0, 8'd125, 8'd0, 32'd0};//{'dest': 125, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2565] = {6'd0, 8'd126, 8'd0, 32'd0};//{'dest': 126, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2566] = {6'd0, 8'd127, 8'd0, 32'd0};//{'dest': 127, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2567] = {6'd38, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'input': 'socket', 'op': 'ready'}
instructions[2568] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2569] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2570] = {6'd39, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': True, 'op': '==', 'type': 'int', 'size': 2}
instructions[2571] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2572] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2573] = {6'd13, 8'd0, 8'd140, 32'd2580};//{'src': 140, 'label': 2580, 'op': 'jmp_if_false'}
instructions[2574] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2575] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2576] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2577] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2578] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2579] = {6'd15, 8'd0, 8'd0, 32'd2580};//{'label': 2580, 'op': 'goto'}
instructions[2580] = {6'd3, 8'd140, 8'd124, 32'd0};//{'dest': 140, 'src': 124, 'op': 'move'}
instructions[2581] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2582] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2583] = {6'd3, 8'd126, 8'd140, 32'd0};//{'dest': 126, 'src': 140, 'op': 'move'}
instructions[2584] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2585] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2586] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2587] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2588] = {6'd3, 8'd127, 8'd140, 32'd0};//{'dest': 127, 'src': 140, 'op': 'move'}
instructions[2589] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2590] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2591] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2592] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2593] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2594] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2595] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2596] = {6'd3, 8'd142, 8'd127, 32'd0};//{'dest': 142, 'src': 127, 'op': 'move'}
instructions[2597] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2598] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2599] = {6'd20, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2600] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2601] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2602] = {6'd13, 8'd0, 8'd140, 32'd2622};//{'src': 140, 'label': 2622, 'op': 'jmp_if_false'}
instructions[2603] = {6'd1, 8'd8, 8'd0, 32'd54};//{'dest': 8, 'label': 54, 'op': 'jmp_and_link'}
instructions[2604] = {6'd3, 8'd140, 8'd9, 32'd0};//{'dest': 140, 'src': 9, 'op': 'move'}
instructions[2605] = {6'd3, 8'd141, 8'd126, 32'd0};//{'dest': 141, 'src': 126, 'op': 'move'}
instructions[2606] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2607] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2608] = {6'd11, 8'd142, 8'd141, 32'd123};//{'dest': 142, 'src': 141, 'srcb': 123, 'signed': False, 'op': '+'}
instructions[2609] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2610] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2611] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2612] = {6'd3, 8'd140, 8'd126, 32'd0};//{'dest': 140, 'src': 126, 'op': 'move'}
instructions[2613] = {6'd14, 8'd126, 8'd126, 32'd1};//{'src': 126, 'right': 1, 'dest': 126, 'signed': False, 'op': '+', 'size': 2}
instructions[2614] = {6'd3, 8'd141, 8'd125, 32'd0};//{'dest': 141, 'src': 125, 'op': 'move'}
instructions[2615] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2616] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2617] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2618] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2619] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2620] = {6'd3, 8'd125, 8'd140, 32'd0};//{'dest': 125, 'src': 140, 'op': 'move'}
instructions[2621] = {6'd15, 8'd0, 8'd0, 32'd2593};//{'label': 2593, 'op': 'goto'}
instructions[2622] = {6'd3, 8'd140, 8'd127, 32'd0};//{'dest': 140, 'src': 127, 'op': 'move'}
instructions[2623] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2624] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2625] = {6'd3, 8'd122, 8'd140, 32'd0};//{'dest': 122, 'src': 140, 'op': 'move'}
instructions[2626] = {6'd6, 8'd0, 8'd121, 32'd0};//{'src': 121, 'op': 'jmp_to_reg'}
instructions[2627] = {6'd0, 8'd129, 8'd0, 32'd638};//{'dest': 129, 'literal': 638, 'op': 'literal'}
instructions[2628] = {6'd0, 8'd130, 8'd0, 32'd1662};//{'dest': 130, 'literal': 1662, 'op': 'literal'}
instructions[2629] = {6'd0, 8'd131, 8'd0, 32'd27};//{'dest': 131, 'literal': 27, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2630] = {6'd0, 8'd132, 8'd0, 32'd0};//{'dest': 132, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2631] = {6'd0, 8'd133, 8'd0, 32'd0};//{'dest': 133, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2632] = {6'd0, 8'd134, 8'd0, 32'd0};//{'dest': 134, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2633] = {6'd0, 8'd135, 8'd0, 32'd0};//{'dest': 135, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2634] = {6'd0, 8'd136, 8'd0, 32'd0};//{'dest': 136, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2635] = {6'd0, 8'd137, 8'd0, 32'd0};//{'dest': 137, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2636] = {6'd0, 8'd138, 8'd0, 32'd0};//{'dest': 138, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2637] = {6'd0, 8'd139, 8'd0, 32'd0};//{'dest': 139, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2638] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2639] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2640] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2641] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2642] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2643] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2644] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2645] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2646] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2647] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2648] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2649] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2650] = {6'd27, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': True, 'op': '+'}
instructions[2651] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2652] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2653] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2654] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2655] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2656] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2657] = {6'd13, 8'd0, 8'd140, 32'd2661};//{'src': 140, 'label': 2661, 'op': 'jmp_if_false'}
instructions[2658] = {6'd3, 8'd140, 8'd133, 32'd0};//{'dest': 140, 'src': 133, 'op': 'move'}
instructions[2659] = {6'd35, 8'd133, 8'd133, 32'd1};//{'src': 133, 'right': 1, 'dest': 133, 'signed': False, 'op': '-', 'size': 2}
instructions[2660] = {6'd15, 8'd0, 8'd0, 32'd2928};//{'label': 2928, 'op': 'goto'}
instructions[2661] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2662] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2663] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2664] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[2665] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2666] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2667] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2668] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[2669] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2670] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2671] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2672] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2673] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2674] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2675] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2676] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2677] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2678] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2679] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2680] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2681] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2682] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2683] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2684] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2685] = {6'd0, 8'd140, 8'd0, 32'd46};//{'dest': 140, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2686] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2687] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2688] = {6'd40, 8'd0, 8'd140, 32'd0};//{'src': 140, 'signed': True, 'file': '/home/amer/Nexys3/TCP3/source/server.h', 'line': 542, 'type': 'int', 'op': 'report'}
instructions[2689] = {6'd0, 8'd141, 8'd0, 32'd46};//{'dest': 141, 'literal': 46, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2690] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2691] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2692] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2693] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2694] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2695] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2696] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2697] = {6'd3, 8'd136, 8'd140, 32'd0};//{'dest': 136, 'src': 140, 'op': 'move'}
instructions[2698] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2699] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2700] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2701] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2702] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2703] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2704] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2705] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2706] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2707] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2708] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2709] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2710] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2711] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2712] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2713] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2714] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2715] = {6'd0, 8'd141, 8'd0, 32'd2};//{'dest': 141, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2716] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2717] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2718] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2719] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2720] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2721] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2722] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2723] = {6'd0, 8'd141, 8'd0, 32'd3};//{'dest': 141, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2724] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2725] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2726] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2727] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2728] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2729] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2730] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2731] = {6'd0, 8'd141, 8'd0, 32'd4};//{'dest': 141, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2732] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2733] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2734] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2735] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2736] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2737] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2738] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2739] = {6'd0, 8'd141, 8'd0, 32'd5};//{'dest': 141, 'literal': 5, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2740] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2741] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2742] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2743] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2744] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2745] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2746] = {6'd0, 8'd140, 8'd0, 32'd2054};//{'dest': 140, 'literal': 2054, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2747] = {6'd0, 8'd141, 8'd0, 32'd6};//{'dest': 141, 'literal': 6, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2748] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2749] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2750] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2751] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2752] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2753] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2754] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2755] = {6'd0, 8'd141, 8'd0, 32'd7};//{'dest': 141, 'literal': 7, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2756] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2757] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2758] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2759] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2760] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2761] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2762] = {6'd0, 8'd140, 8'd0, 32'd2048};//{'dest': 140, 'literal': 2048, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2763] = {6'd0, 8'd141, 8'd0, 32'd8};//{'dest': 141, 'literal': 8, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2764] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2765] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2766] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2767] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2768] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2769] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2770] = {6'd0, 8'd140, 8'd0, 32'd1540};//{'dest': 140, 'literal': 1540, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2771] = {6'd0, 8'd141, 8'd0, 32'd9};//{'dest': 141, 'literal': 9, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2772] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2773] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2774] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2775] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2776] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2777] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2778] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2779] = {6'd0, 8'd141, 8'd0, 32'd10};//{'dest': 141, 'literal': 10, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2780] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2781] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2782] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2783] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2784] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2785] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2786] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2787] = {6'd0, 8'd141, 8'd0, 32'd11};//{'dest': 141, 'literal': 11, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2788] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2789] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2790] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2791] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2792] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2793] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2794] = {6'd0, 8'd140, 8'd0, 32'd515};//{'dest': 140, 'literal': 515, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2795] = {6'd0, 8'd141, 8'd0, 32'd12};//{'dest': 141, 'literal': 12, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2796] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2797] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2798] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2799] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2800] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2801] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2802] = {6'd0, 8'd140, 8'd0, 32'd1029};//{'dest': 140, 'literal': 1029, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2803] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2804] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2805] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2806] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2807] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2808] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2809] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2810] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2811] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2812] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2813] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2814] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2815] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2816] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2817] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2818] = {6'd0, 8'd140, 8'd0, 32'd119};//{'dest': 140, 'literal': 119, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2819] = {6'd0, 8'd141, 8'd0, 32'd15};//{'dest': 141, 'literal': 15, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2820] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2821] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2822] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2823] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2824] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2825] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2826] = {6'd0, 8'd140, 8'd0, 32'd24};//{'dest': 140, 'literal': 24, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2827] = {6'd0, 8'd141, 8'd0, 32'd16};//{'dest': 141, 'literal': 16, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2828] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2829] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2830] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2831] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2832] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2833] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2834] = {6'd0, 8'd140, 8'd0, 32'd62290};//{'dest': 140, 'literal': 62290, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2835] = {6'd0, 8'd141, 8'd0, 32'd17};//{'dest': 141, 'literal': 17, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2836] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2837] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2838] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2839] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2840] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2841] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2842] = {6'd0, 8'd140, 8'd0, 32'd64494};//{'dest': 140, 'literal': 64494, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2843] = {6'd0, 8'd141, 8'd0, 32'd18};//{'dest': 141, 'literal': 18, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2844] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2845] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2846] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2847] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2848] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2849] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2850] = {6'd0, 8'd140, 8'd0, 32'd49320};//{'dest': 140, 'literal': 49320, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2851] = {6'd0, 8'd141, 8'd0, 32'd19};//{'dest': 141, 'literal': 19, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2852] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2853] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2854] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2855] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2856] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2857] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2858] = {6'd0, 8'd140, 8'd0, 32'd105};//{'dest': 140, 'literal': 105, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2859] = {6'd0, 8'd141, 8'd0, 32'd20};//{'dest': 141, 'literal': 20, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2860] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2861] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2862] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2863] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2864] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2865] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2866] = {6'd0, 8'd140, 8'd0, 32'd58291};//{'dest': 140, 'literal': 58291, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2867] = {6'd0, 8'd141, 8'd0, 32'd21};//{'dest': 141, 'literal': 21, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2868] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2869] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2870] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2871] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2872] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2873] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2874] = {6'd0, 8'd140, 8'd0, 32'd12976};//{'dest': 140, 'literal': 12976, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2875] = {6'd0, 8'd141, 8'd0, 32'd22};//{'dest': 141, 'literal': 22, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2876] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2877] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2878] = {6'd11, 8'd142, 8'd141, 32'd130};//{'dest': 142, 'src': 141, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2879] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2880] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2881] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[2882] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2883] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2884] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2885] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2886] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2887] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2888] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2889] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2890] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2891] = {6'd28, 8'd140, 8'd141, 32'd46};//{'src': 141, 'right': 46, 'dest': 140, 'signed': False, 'op': '<', 'type': 'int', 'size': 2}
instructions[2892] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2893] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2894] = {6'd13, 8'd0, 8'd140, 32'd2919};//{'src': 140, 'label': 2919, 'op': 'jmp_if_false'}
instructions[2895] = {6'd3, 8'd142, 8'd136, 32'd0};//{'dest': 142, 'src': 136, 'op': 'move'}
instructions[2896] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2897] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2898] = {6'd11, 8'd146, 8'd142, 32'd130};//{'dest': 146, 'src': 142, 'srcb': 130, 'signed': False, 'op': '+'}
instructions[2899] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2900] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2901] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810502240, 'op': 'memory_read_request'}
instructions[2902] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2903] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810502240, 'op': 'memory_read_wait'}
instructions[2904] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810502240, 'element_size': 2, 'op': 'memory_read'}
instructions[2905] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2906] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2907] = {6'd3, 8'd1, 8'd141, 32'd0};//{'dest': 1, 'src': 141, 'op': 'move'}
instructions[2908] = {6'd1, 8'd0, 8'd0, 32'd34};//{'dest': 0, 'label': 34, 'op': 'jmp_and_link'}
instructions[2909] = {6'd3, 8'd140, 8'd136, 32'd0};//{'dest': 140, 'src': 136, 'op': 'move'}
instructions[2910] = {6'd14, 8'd136, 8'd136, 32'd1};//{'src': 136, 'right': 1, 'dest': 136, 'signed': False, 'op': '+', 'size': 2}
instructions[2911] = {6'd3, 8'd141, 8'd135, 32'd0};//{'dest': 141, 'src': 135, 'op': 'move'}
instructions[2912] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2913] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2914] = {6'd14, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '+', 'type': 'int', 'size': 2}
instructions[2915] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2916] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2917] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[2918] = {6'd15, 8'd0, 8'd0, 32'd2886};//{'label': 2886, 'op': 'goto'}
instructions[2919] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[2920] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2921] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2922] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[2923] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2924] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2925] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2926] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[2927] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[2928] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[2929] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2930] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2931] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2932] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2933] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2934] = {6'd22, 8'd0, 8'd141, 32'd2951};//{'src': 141, 'label': 2951, 'op': 'jmp_if_true'}
instructions[2935] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2936] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2937] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2938] = {6'd22, 8'd0, 8'd141, 32'd2968};//{'src': 141, 'label': 2968, 'op': 'jmp_if_true'}
instructions[2939] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2940] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2941] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2942] = {6'd22, 8'd0, 8'd141, 32'd3034};//{'src': 141, 'label': 3034, 'op': 'jmp_if_true'}
instructions[2943] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2944] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2945] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2946] = {6'd22, 8'd0, 8'd141, 32'd3113};//{'src': 141, 'label': 3113, 'op': 'jmp_if_true'}
instructions[2947] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[2948] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2949] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2950] = {6'd22, 8'd0, 8'd141, 32'd3123};//{'src': 141, 'label': 3123, 'op': 'jmp_if_true'}
instructions[2951] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2952] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2953] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2954] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[2955] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2956] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2957] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2958] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[2959] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2960] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2961] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2962] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[2963] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2964] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2965] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2966] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[2967] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[2968] = {6'd0, 8'd141, 8'd0, 32'd13};//{'dest': 141, 'literal': 13, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2969] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2970] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2971] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2972] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2973] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2974] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810452368, 'op': 'memory_read_request'}
instructions[2975] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2976] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810452368, 'op': 'memory_read_wait'}
instructions[2977] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810452368, 'element_size': 2, 'op': 'memory_read'}
instructions[2978] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2979] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2980] = {6'd3, 8'd75, 8'd140, 32'd0};//{'dest': 75, 'src': 140, 'op': 'move'}
instructions[2981] = {6'd0, 8'd141, 8'd0, 32'd14};//{'dest': 141, 'literal': 14, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2982] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2983] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2984] = {6'd11, 8'd142, 8'd141, 32'd129};//{'dest': 142, 'src': 141, 'srcb': 129, 'signed': False, 'op': '+'}
instructions[2985] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2986] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2987] = {6'd17, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810501808, 'op': 'memory_read_request'}
instructions[2988] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2989] = {6'd18, 8'd0, 8'd142, 32'd0};//{'element_size': 2, 'src': 142, 'sequence': 139887810501808, 'op': 'memory_read_wait'}
instructions[2990] = {6'd19, 8'd140, 8'd142, 32'd0};//{'dest': 140, 'src': 142, 'sequence': 139887810501808, 'element_size': 2, 'op': 'memory_read'}
instructions[2991] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2992] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2993] = {6'd3, 8'd76, 8'd140, 32'd0};//{'dest': 76, 'src': 140, 'op': 'move'}
instructions[2994] = {6'd3, 8'd140, 8'd89, 32'd0};//{'dest': 140, 'src': 89, 'op': 'move'}
instructions[2995] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2996] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[2997] = {6'd3, 8'd78, 8'd140, 32'd0};//{'dest': 78, 'src': 140, 'op': 'move'}
instructions[2998] = {6'd0, 8'd140, 8'd0, 32'd80};//{'dest': 140, 'literal': 80, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[2999] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3000] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3001] = {6'd3, 8'd77, 8'd140, 32'd0};//{'dest': 77, 'src': 140, 'op': 'move'}
instructions[3002] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3003] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3004] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3005] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3006] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3007] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3008] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3009] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3010] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3011] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3012] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3013] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3014] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3015] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3016] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3017] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3018] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3019] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3020] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3021] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3022] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3023] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3024] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3025] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3026] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3027] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3028] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3029] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3030] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3031] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3032] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3033] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3034] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3035] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3036] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3037] = {6'd3, 8'd123, 8'd151, 32'd0};//{'dest': 123, 'src': 151, 'op': 'move'}
instructions[3038] = {6'd3, 8'd141, 8'd131, 32'd0};//{'dest': 141, 'src': 131, 'op': 'move'}
instructions[3039] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3040] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3041] = {6'd3, 8'd124, 8'd141, 32'd0};//{'dest': 124, 'src': 141, 'op': 'move'}
instructions[3042] = {6'd1, 8'd121, 8'd0, 32'd2564};//{'dest': 121, 'label': 2564, 'op': 'jmp_and_link'}
instructions[3043] = {6'd3, 8'd140, 8'd122, 32'd0};//{'dest': 140, 'src': 122, 'op': 'move'}
instructions[3044] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3045] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3046] = {6'd3, 8'd132, 8'd140, 32'd0};//{'dest': 132, 'src': 140, 'op': 'move'}
instructions[3047] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3048] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3049] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3050] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3051] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3052] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3053] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810512656, 'op': 'memory_read_request'}
instructions[3054] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3055] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810512656, 'op': 'memory_read_wait'}
instructions[3056] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810512656, 'element_size': 2, 'op': 'memory_read'}
instructions[3057] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3058] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3059] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3060] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3061] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3062] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3063] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3064] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3065] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3066] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3067] = {6'd11, 8'd147, 8'd146, 32'd80};//{'dest': 147, 'src': 146, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3068] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3069] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3070] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810513088, 'op': 'memory_read_request'}
instructions[3071] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3072] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810513088, 'op': 'memory_read_wait'}
instructions[3073] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810513088, 'element_size': 2, 'op': 'memory_read'}
instructions[3074] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3075] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3076] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3077] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3078] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3079] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3080] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3081] = {6'd3, 8'd143, 8'd80, 32'd0};//{'dest': 143, 'src': 80, 'op': 'move'}
instructions[3082] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3083] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3084] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3085] = {6'd3, 8'd143, 8'd79, 32'd0};//{'dest': 143, 'src': 79, 'op': 'move'}
instructions[3086] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3087] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3088] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3089] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3090] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3091] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3092] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3093] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3094] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3095] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3096] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3097] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3098] = {6'd3, 8'd84, 8'd140, 32'd0};//{'dest': 84, 'src': 140, 'op': 'move'}
instructions[3099] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3100] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3101] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3102] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3103] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3104] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3105] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3106] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3107] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3108] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3109] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3110] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3111] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3112] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3113] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3114] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3115] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3116] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3117] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3118] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3119] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3120] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3121] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3122] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3123] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3124] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3125] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3126] = {6'd3, 8'd83, 8'd140, 32'd0};//{'dest': 83, 'src': 140, 'op': 'move'}
instructions[3127] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3128] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3129] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3130] = {6'd3, 8'd87, 8'd140, 32'd0};//{'dest': 87, 'src': 140, 'op': 'move'}
instructions[3131] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3132] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3133] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3134] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3135] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3136] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3137] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3138] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3139] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3140] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3141] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3142] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3143] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3144] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3145] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3146] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3147] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3148] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3149] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3150] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3151] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3152] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3153] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3154] = {6'd15, 8'd0, 8'd0, 32'd3155};//{'label': 3155, 'op': 'goto'}
instructions[3155] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3156] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3157] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3158] = {6'd3, 8'd134, 8'd140, 32'd0};//{'dest': 134, 'src': 140, 'op': 'move'}
instructions[3159] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3160] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3161] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3162] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3163] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3164] = {6'd13, 8'd0, 8'd140, 32'd3550};//{'src': 140, 'label': 3550, 'op': 'jmp_if_false'}
instructions[3165] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3166] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3167] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3168] = {6'd3, 8'd108, 8'd151, 32'd0};//{'dest': 108, 'src': 151, 'op': 'move'}
instructions[3169] = {6'd1, 8'd106, 8'd0, 32'd2162};//{'dest': 106, 'label': 2162, 'op': 'jmp_and_link'}
instructions[3170] = {6'd3, 8'd140, 8'd107, 32'd0};//{'dest': 140, 'src': 107, 'op': 'move'}
instructions[3171] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3172] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3173] = {6'd3, 8'd135, 8'd140, 32'd0};//{'dest': 135, 'src': 140, 'op': 'move'}
instructions[3174] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3175] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3176] = {6'd3, 8'd140, 8'd135, 32'd0};//{'dest': 140, 'src': 135, 'op': 'move'}
instructions[3177] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3178] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3179] = {6'd13, 8'd0, 8'd140, 32'd3184};//{'src': 140, 'label': 3184, 'op': 'jmp_if_false'}
instructions[3180] = {6'd3, 8'd141, 8'd90, 32'd0};//{'dest': 141, 'src': 90, 'op': 'move'}
instructions[3181] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3182] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3183] = {6'd25, 8'd140, 8'd141, 32'd80};//{'src': 141, 'right': 80, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3184] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3185] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3186] = {6'd13, 8'd0, 8'd140, 32'd3543};//{'src': 140, 'label': 3543, 'op': 'jmp_if_false'}
instructions[3187] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3188] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3189] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3190] = {6'd26, 8'd140, 8'd141, 32'd0};//{'src': 141, 'right': 0, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3191] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3192] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3193] = {6'd13, 8'd0, 8'd140, 32'd3199};//{'src': 140, 'label': 3199, 'op': 'jmp_if_false'}
instructions[3194] = {6'd3, 8'd141, 8'd89, 32'd0};//{'dest': 141, 'src': 89, 'op': 'move'}
instructions[3195] = {6'd3, 8'd142, 8'd78, 32'd0};//{'dest': 142, 'src': 78, 'op': 'move'}
instructions[3196] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3197] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3198] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3199] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3200] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3201] = {6'd13, 8'd0, 8'd140, 32'd3204};//{'src': 140, 'label': 3204, 'op': 'jmp_if_false'}
instructions[3202] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3203] = {6'd15, 8'd0, 8'd0, 32'd3204};//{'label': 3204, 'op': 'goto'}
instructions[3204] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3205] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3206] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3207] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3208] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3209] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3210] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3211] = {6'd3, 8'd137, 8'd140, 32'd0};//{'dest': 137, 'src': 140, 'op': 'move'}
instructions[3212] = {6'd3, 8'd140, 8'd139, 32'd0};//{'dest': 140, 'src': 139, 'op': 'move'}
instructions[3213] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3214] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3215] = {6'd39, 8'd141, 8'd140, 32'd0};//{'src': 140, 'right': 0, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3216] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3217] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3218] = {6'd22, 8'd0, 8'd141, 32'd3235};//{'src': 141, 'label': 3235, 'op': 'jmp_if_true'}
instructions[3219] = {6'd39, 8'd141, 8'd140, 32'd1};//{'src': 140, 'right': 1, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3220] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3221] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3222] = {6'd22, 8'd0, 8'd141, 32'd3258};//{'src': 141, 'label': 3258, 'op': 'jmp_if_true'}
instructions[3223] = {6'd39, 8'd141, 8'd140, 32'd2};//{'src': 140, 'right': 2, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3224] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3225] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3226] = {6'd22, 8'd0, 8'd141, 32'd3336};//{'src': 141, 'label': 3336, 'op': 'jmp_if_true'}
instructions[3227] = {6'd39, 8'd141, 8'd140, 32'd3};//{'src': 140, 'right': 3, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3228] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3229] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3230] = {6'd22, 8'd0, 8'd141, 32'd3372};//{'src': 141, 'label': 3372, 'op': 'jmp_if_true'}
instructions[3231] = {6'd39, 8'd141, 8'd140, 32'd4};//{'src': 140, 'right': 4, 'dest': 141, 'signed': True, 'op': '==', 'size': 2}
instructions[3232] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3233] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3234] = {6'd22, 8'd0, 8'd141, 32'd3460};//{'src': 141, 'label': 3460, 'op': 'jmp_if_true'}
instructions[3235] = {6'd3, 8'd140, 8'd94, 32'd0};//{'dest': 140, 'src': 94, 'op': 'move'}
instructions[3236] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3237] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3238] = {6'd13, 8'd0, 8'd140, 32'd3244};//{'src': 140, 'label': 3244, 'op': 'jmp_if_false'}
instructions[3239] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3240] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3241] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3242] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3243] = {6'd15, 8'd0, 8'd0, 32'd3257};//{'label': 3257, 'op': 'goto'}
instructions[3244] = {6'd0, 8'd140, 8'd0, 32'd1};//{'dest': 140, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3245] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3246] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3247] = {6'd3, 8'd85, 8'd140, 32'd0};//{'dest': 85, 'src': 140, 'op': 'move'}
instructions[3248] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3249] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3250] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3251] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3252] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3253] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3254] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3255] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3256] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3257] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3258] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3259] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3260] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3261] = {6'd13, 8'd0, 8'd140, 32'd3335};//{'src': 140, 'label': 3335, 'op': 'jmp_if_false'}
instructions[3262] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3263] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3264] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3265] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3266] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3267] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3268] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014384, 'op': 'memory_read_request'}
instructions[3269] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3270] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014384, 'op': 'memory_read_wait'}
instructions[3271] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810014384, 'element_size': 2, 'op': 'memory_read'}
instructions[3272] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3273] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3274] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3275] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3276] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3277] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3278] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3279] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3280] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3281] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3282] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3283] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3284] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3285] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014816, 'op': 'memory_read_request'}
instructions[3286] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3287] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810014816, 'op': 'memory_read_wait'}
instructions[3288] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887810014816, 'element_size': 2, 'op': 'memory_read'}
instructions[3289] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3290] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3291] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3292] = {6'd11, 8'd142, 8'd141, 32'd79};//{'dest': 142, 'src': 141, 'srcb': 79, 'signed': False, 'op': '+'}
instructions[3293] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3294] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3295] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3296] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3297] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3298] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3299] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3300] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3301] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3302] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133520, 'op': 'memory_read_request'}
instructions[3303] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3304] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133520, 'op': 'memory_read_wait'}
instructions[3305] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887811133520, 'element_size': 2, 'op': 'memory_read'}
instructions[3306] = {6'd0, 8'd141, 8'd0, 32'd1};//{'dest': 141, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3307] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3308] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3309] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3310] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3311] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3312] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3313] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3314] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3315] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3316] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3317] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3318] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3319] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133952, 'op': 'memory_read_request'}
instructions[3320] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3321] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887811133952, 'op': 'memory_read_wait'}
instructions[3322] = {6'd19, 8'd140, 8'd147, 32'd0};//{'dest': 140, 'src': 147, 'sequence': 139887811133952, 'element_size': 2, 'op': 'memory_read'}
instructions[3323] = {6'd0, 8'd141, 8'd0, 32'd0};//{'dest': 141, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3324] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3325] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3326] = {6'd11, 8'd142, 8'd141, 32'd80};//{'dest': 142, 'src': 141, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3327] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3328] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3329] = {6'd23, 8'd0, 8'd142, 32'd140};//{'srcb': 140, 'src': 142, 'element_size': 2, 'op': 'memory_write'}
instructions[3330] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3331] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3332] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3333] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3334] = {6'd15, 8'd0, 8'd0, 32'd3335};//{'label': 3335, 'op': 'goto'}
instructions[3335] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3336] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3337] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3338] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3339] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3340] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3341] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3342] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3343] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3344] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3345] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3346] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3347] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3348] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3349] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3350] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3351] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3352] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3353] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3354] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3355] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3356] = {6'd13, 8'd0, 8'd140, 32'd3362};//{'src': 140, 'label': 3362, 'op': 'jmp_if_false'}
instructions[3357] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3358] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3359] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3360] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3361] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3362] = {6'd3, 8'd140, 8'd132, 32'd0};//{'dest': 140, 'src': 132, 'op': 'move'}
instructions[3363] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3364] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3365] = {6'd13, 8'd0, 8'd140, 32'd3371};//{'src': 140, 'label': 3371, 'op': 'jmp_if_false'}
instructions[3366] = {6'd0, 8'd140, 8'd0, 32'd3};//{'dest': 140, 'literal': 3, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3367] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3368] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3369] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3370] = {6'd15, 8'd0, 8'd0, 32'd3371};//{'label': 3371, 'op': 'goto'}
instructions[3371] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3372] = {6'd3, 8'd143, 8'd81, 32'd0};//{'dest': 143, 'src': 81, 'op': 'move'}
instructions[3373] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3374] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3375] = {6'd3, 8'd19, 8'd143, 32'd0};//{'dest': 19, 'src': 143, 'op': 'move'}
instructions[3376] = {6'd3, 8'd143, 8'd91, 32'd0};//{'dest': 143, 'src': 91, 'op': 'move'}
instructions[3377] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3378] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3379] = {6'd3, 8'd20, 8'd143, 32'd0};//{'dest': 20, 'src': 143, 'op': 'move'}
instructions[3380] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3381] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3382] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3383] = {6'd3, 8'd21, 8'd141, 32'd0};//{'dest': 21, 'src': 141, 'op': 'move'}
instructions[3384] = {6'd1, 8'd17, 8'd0, 32'd108};//{'dest': 17, 'label': 108, 'op': 'jmp_and_link'}
instructions[3385] = {6'd3, 8'd140, 8'd18, 32'd0};//{'dest': 140, 'src': 18, 'op': 'move'}
instructions[3386] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3387] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3388] = {6'd3, 8'd138, 8'd140, 32'd0};//{'dest': 138, 'src': 140, 'op': 'move'}
instructions[3389] = {6'd3, 8'd140, 8'd93, 32'd0};//{'dest': 140, 'src': 93, 'op': 'move'}
instructions[3390] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3391] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3392] = {6'd13, 8'd0, 8'd140, 32'd3398};//{'src': 140, 'label': 3398, 'op': 'jmp_if_false'}
instructions[3393] = {6'd0, 8'd140, 8'd0, 32'd4};//{'dest': 140, 'literal': 4, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3394] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3395] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3396] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3397] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3398] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3399] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3400] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3401] = {6'd13, 8'd0, 8'd140, 32'd3425};//{'src': 140, 'label': 3425, 'op': 'jmp_if_false'}
instructions[3402] = {6'd0, 8'd142, 8'd0, 32'd1};//{'dest': 142, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3403] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3404] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3405] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3406] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3407] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3408] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044416, 'op': 'memory_read_request'}
instructions[3409] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3410] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044416, 'op': 'memory_read_wait'}
instructions[3411] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810044416, 'element_size': 2, 'op': 'memory_read'}
instructions[3412] = {6'd0, 8'd146, 8'd0, 32'd1};//{'dest': 146, 'literal': 1, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3413] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3414] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3415] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3416] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3417] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3418] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044560, 'op': 'memory_read_request'}
instructions[3419] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3420] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044560, 'op': 'memory_read_wait'}
instructions[3421] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810044560, 'element_size': 2, 'op': 'memory_read'}
instructions[3422] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3423] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3424] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3425] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3426] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3427] = {6'd13, 8'd0, 8'd140, 32'd3451};//{'src': 140, 'label': 3451, 'op': 'jmp_if_false'}
instructions[3428] = {6'd0, 8'd142, 8'd0, 32'd0};//{'dest': 142, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3429] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3430] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3431] = {6'd11, 8'd146, 8'd142, 32'd80};//{'dest': 146, 'src': 142, 'srcb': 80, 'signed': False, 'op': '+'}
instructions[3432] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3433] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3434] = {6'd17, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044848, 'op': 'memory_read_request'}
instructions[3435] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3436] = {6'd18, 8'd0, 8'd146, 32'd0};//{'element_size': 2, 'src': 146, 'sequence': 139887810044848, 'op': 'memory_read_wait'}
instructions[3437] = {6'd19, 8'd141, 8'd146, 32'd0};//{'dest': 141, 'src': 146, 'sequence': 139887810044848, 'element_size': 2, 'op': 'memory_read'}
instructions[3438] = {6'd0, 8'd146, 8'd0, 32'd0};//{'dest': 146, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3439] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3440] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3441] = {6'd11, 8'd147, 8'd146, 32'd92};//{'dest': 147, 'src': 146, 'srcb': 92, 'signed': False, 'op': '+'}
instructions[3442] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3443] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3444] = {6'd17, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044992, 'op': 'memory_read_request'}
instructions[3445] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3446] = {6'd18, 8'd0, 8'd147, 32'd0};//{'element_size': 2, 'src': 147, 'sequence': 139887810044992, 'op': 'memory_read_wait'}
instructions[3447] = {6'd19, 8'd142, 8'd147, 32'd0};//{'dest': 142, 'src': 147, 'sequence': 139887810044992, 'element_size': 2, 'op': 'memory_read'}
instructions[3448] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3449] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3450] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3451] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3452] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3453] = {6'd13, 8'd0, 8'd140, 32'd3459};//{'src': 140, 'label': 3459, 'op': 'jmp_if_false'}
instructions[3454] = {6'd0, 8'd140, 8'd0, 32'd2};//{'dest': 140, 'literal': 2, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3455] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3456] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3457] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3458] = {6'd15, 8'd0, 8'd0, 32'd3459};//{'label': 3459, 'op': 'goto'}
instructions[3459] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3460] = {6'd3, 8'd140, 8'd96, 32'd0};//{'dest': 140, 'src': 96, 'op': 'move'}
instructions[3461] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3462] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3463] = {6'd13, 8'd0, 8'd140, 32'd3469};//{'src': 140, 'label': 3469, 'op': 'jmp_if_false'}
instructions[3464] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3465] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3466] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3467] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3468] = {6'd15, 8'd0, 8'd0, 32'd3469};//{'label': 3469, 'op': 'goto'}
instructions[3469] = {6'd15, 8'd0, 8'd0, 32'd3470};//{'label': 3470, 'op': 'goto'}
instructions[3470] = {6'd3, 8'd140, 8'd95, 32'd0};//{'dest': 140, 'src': 95, 'op': 'move'}
instructions[3471] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3472] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3473] = {6'd13, 8'd0, 8'd140, 32'd3479};//{'src': 140, 'label': 3479, 'op': 'jmp_if_false'}
instructions[3474] = {6'd0, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'literal': 0, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3475] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3476] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3477] = {6'd3, 8'd139, 8'd140, 32'd0};//{'dest': 139, 'src': 140, 'op': 'move'}
instructions[3478] = {6'd15, 8'd0, 8'd0, 32'd3479};//{'label': 3479, 'op': 'goto'}
instructions[3479] = {6'd3, 8'd140, 8'd138, 32'd0};//{'dest': 140, 'src': 138, 'op': 'move'}
instructions[3480] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3481] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3482] = {6'd13, 8'd0, 8'd140, 32'd3515};//{'src': 140, 'label': 3515, 'op': 'jmp_if_false'}
instructions[3483] = {6'd3, 8'd151, 8'd129, 32'd0};//{'dest': 151, 'src': 129, 'op': 'move'}
instructions[3484] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3485] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3486] = {6'd3, 8'd116, 8'd151, 32'd0};//{'dest': 116, 'src': 151, 'op': 'move'}
instructions[3487] = {6'd3, 8'd141, 8'd105, 32'd0};//{'dest': 141, 'src': 105, 'op': 'move'}
instructions[3488] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3489] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3490] = {6'd3, 8'd117, 8'd141, 32'd0};//{'dest': 117, 'src': 141, 'op': 'move'}
instructions[3491] = {6'd3, 8'd141, 8'd104, 32'd0};//{'dest': 141, 'src': 104, 'op': 'move'}
instructions[3492] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3493] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3494] = {6'd3, 8'd118, 8'd141, 32'd0};//{'dest': 118, 'src': 141, 'op': 'move'}
instructions[3495] = {6'd1, 8'd115, 8'd0, 32'd2514};//{'dest': 115, 'label': 2514, 'op': 'jmp_and_link'}
instructions[3496] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3497] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3498] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3499] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3500] = {6'd29, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3501] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3502] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3503] = {6'd13, 8'd0, 8'd140, 32'd3514};//{'src': 140, 'label': 3514, 'op': 'jmp_if_false'}
instructions[3504] = {6'd3, 8'd151, 8'd130, 32'd0};//{'dest': 151, 'src': 130, 'op': 'move'}
instructions[3505] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3506] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3507] = {6'd3, 8'd98, 8'd151, 32'd0};//{'dest': 98, 'src': 151, 'op': 'move'}
instructions[3508] = {6'd3, 8'd141, 8'd132, 32'd0};//{'dest': 141, 'src': 132, 'op': 'move'}
instructions[3509] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3510] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3511] = {6'd3, 8'd99, 8'd141, 32'd0};//{'dest': 99, 'src': 141, 'op': 'move'}
instructions[3512] = {6'd1, 8'd97, 8'd0, 32'd1705};//{'dest': 97, 'label': 1705, 'op': 'jmp_and_link'}
instructions[3513] = {6'd15, 8'd0, 8'd0, 32'd3514};//{'label': 3514, 'op': 'goto'}
instructions[3514] = {6'd15, 8'd0, 8'd0, 32'd3515};//{'label': 3515, 'op': 'goto'}
instructions[3515] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3516] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3517] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3518] = {6'd25, 8'd140, 8'd141, 32'd2};//{'src': 141, 'right': 2, 'dest': 140, 'signed': False, 'op': '==', 'type': 'int', 'size': 2}
instructions[3519] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3520] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3521] = {6'd13, 8'd0, 8'd140, 32'd3523};//{'src': 140, 'label': 3523, 'op': 'jmp_if_false'}
instructions[3522] = {6'd38, 8'd140, 8'd0, 32'd0};//{'dest': 140, 'input': 'socket', 'op': 'ready'}
instructions[3523] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3524] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3525] = {6'd13, 8'd0, 8'd140, 32'd3528};//{'src': 140, 'label': 3528, 'op': 'jmp_if_false'}
instructions[3526] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3527] = {6'd15, 8'd0, 8'd0, 32'd3528};//{'label': 3528, 'op': 'goto'}
instructions[3528] = {6'd3, 8'd141, 8'd139, 32'd0};//{'dest': 141, 'src': 139, 'op': 'move'}
instructions[3529] = {6'd3, 8'd142, 8'd137, 32'd0};//{'dest': 142, 'src': 137, 'op': 'move'}
instructions[3530] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3531] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3532] = {6'd21, 8'd140, 8'd141, 32'd142};//{'srcb': 142, 'src': 141, 'dest': 140, 'signed': False, 'op': '!=', 'type': 'int', 'size': 2}
instructions[3533] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3534] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3535] = {6'd13, 8'd0, 8'd140, 32'd3542};//{'src': 140, 'label': 3542, 'op': 'jmp_if_false'}
instructions[3536] = {6'd0, 8'd140, 8'd0, 32'd120};//{'dest': 140, 'literal': 120, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3537] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3538] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3539] = {6'd3, 8'd133, 8'd140, 32'd0};//{'dest': 133, 'src': 140, 'op': 'move'}
instructions[3540] = {6'd15, 8'd0, 8'd0, 32'd3550};//{'label': 3550, 'op': 'goto'}
instructions[3541] = {6'd15, 8'd0, 8'd0, 32'd3542};//{'label': 3542, 'op': 'goto'}
instructions[3542] = {6'd15, 8'd0, 8'd0, 32'd3547};//{'label': 3547, 'op': 'goto'}
instructions[3543] = {6'd0, 8'd140, 8'd0, 32'd10000};//{'dest': 140, 'literal': 10000, 'size': 2, 'signed': 2, 'op': 'literal'}
instructions[3544] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3545] = {6'd4, 8'd0, 8'd0, 32'd0};//{'op': 'nop'}
instructions[3546] = {6'd41, 8'd0, 8'd140, 32'd0};//{'src': 140, 'op': 'wait_clocks'}
instructions[3547] = {6'd3, 8'd140, 8'd134, 32'd0};//{'dest': 140, 'src': 134, 'op': 'move'}
instructions[3548] = {6'd35, 8'd134, 8'd134, 32'd1};//{'src': 134, 'right': 1, 'dest': 134, 'signed': False, 'op': '-', 'size': 2}
instructions[3549] = {6'd15, 8'd0, 8'd0, 32'd3159};//{'label': 3159, 'op': 'goto'}
instructions[3550] = {6'd15, 8'd0, 8'd0, 32'd2654};//{'label': 2654, 'op': 'goto'}
instructions[3551] = {6'd6, 8'd0, 8'd128, 32'd0};//{'src': 128, 'op': 'jmp_to_reg'}
end
//////////////////////////////////////////////////////////////////////////////
// CPU IMPLEMENTAION OF C PROCESS
//
// This section of the file contains a CPU implementing the C process.
always @(posedge clk)
begin
//implement memory for 2 byte x n arrays
if (memory_enable_2 == 1'b1) begin
memory_2[address_2] <= data_in_2;
end
data_out_2 <= memory_2[address_2];
memory_enable_2 <= 1'b0;
write_enable_2 <= 0;
//stage 0 instruction fetch
if (stage_0_enable) begin
stage_1_enable <= 1;
instruction_0 <= instructions[program_counter];
opcode_0 = instruction_0[53:48];
dest_0 = instruction_0[47:40];
src_0 = instruction_0[39:32];
srcb_0 = instruction_0[7:0];
literal_0 = instruction_0[31:0];
if(write_enable_2) begin
registers[dest_2] <= result_2;
end
program_counter_0 <= program_counter;
program_counter <= program_counter + 1;
end
//stage 1 opcode fetch
if (stage_1_enable) begin
stage_2_enable <= 1;
register_1 <= registers[src_0];
registerb_1 <= registers[srcb_0];
dest_1 <= dest_0;
literal_1 <= literal_0;
opcode_1 <= opcode_0;
program_counter_1 <= program_counter_0;
end
//stage 2 opcode fetch
if (stage_2_enable) begin
dest_2 <= dest_1;
case(opcode_1)
16'd0:
begin
result_2 <= literal_1;
write_enable_2 <= 1;
end
16'd1:
begin
program_counter <= literal_1;
result_2 <= program_counter_1 + 1;
write_enable_2 <= 1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd2:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd3:
begin
result_2 <= register_1;
write_enable_2 <= 1;
end
16'd5:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_eth_tx_stb <= 1'b1;
s_output_eth_tx <= register_1;
end
16'd6:
begin
program_counter <= register_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd7:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_output_socket_stb <= 1'b1;
s_output_socket <= register_1;
end
16'd8:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_eth_rx_ack <= 1'b1;
end
16'd9:
begin
result_2 <= 0;
result_2[0] <= input_eth_rx_stb;
write_enable_2 <= 1;
end
16'd10:
begin
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
s_input_socket_ack <= 1'b1;
end
16'd11:
begin
result_2 <= $unsigned(register_1) + $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd12:
begin
result_2 <= $unsigned(register_1) & $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd13:
begin
if (register_1 == 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd14:
begin
result_2 <= $unsigned(register_1) + $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd15:
begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
16'd16:
begin
result_2 <= ~register_1;
write_enable_2 <= 1;
end
16'd17:
begin
address_2 <= register_1;
end
16'd19:
begin
result_2 <= data_out_2;
write_enable_2 <= 1;
end
16'd20:
begin
result_2 <= $unsigned(register_1) < $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd21:
begin
result_2 <= $unsigned(register_1) != $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd22:
begin
if (register_1 != 0) begin
program_counter <= literal_1;
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
end
16'd23:
begin
address_2 <= register_1;
data_in_2 <= registerb_1;
memory_enable_2 <= 1'b1;
end
16'd24:
begin
$display ("%d (report at line: 107 in file: /home/amer/Nexys3/TCP3/source/server.h)", $unsigned(register_1));
end
16'd25:
begin
result_2 <= $unsigned(register_1) == $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd26:
begin
result_2 <= $unsigned(register_1) != $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd27:
begin
result_2 <= $signed(register_1) + $signed(registerb_1);
write_enable_2 <= 1;
end
16'd28:
begin
result_2 <= $unsigned(register_1) < $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd29:
begin
result_2 <= $unsigned(register_1) == $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd30:
begin
result_2 <= $unsigned(literal_1) | $unsigned(register_1);
write_enable_2 <= 1;
end
16'd31:
begin
result_2 <= $unsigned(register_1) <= $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd32:
begin
result_2 <= $unsigned(register_1) >> $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd33:
begin
result_2 <= $unsigned(register_1) << $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd34:
begin
result_2 <= $unsigned(register_1) - $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd35:
begin
result_2 <= $unsigned(register_1) - $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd36:
begin
result_2 <= $unsigned(register_1) <= $unsigned(registerb_1);
write_enable_2 <= 1;
end
16'd37:
begin
result_2 <= $unsigned(register_1) | $unsigned(literal_1);
write_enable_2 <= 1;
end
16'd38:
begin
result_2 <= 0;
result_2[0] <= input_socket_stb;
write_enable_2 <= 1;
end
16'd39:
begin
result_2 <= $signed(register_1) == $signed(literal_1);
write_enable_2 <= 1;
end
16'd40:
begin
$display ("%d (report at line: 542 in file: /home/amer/Nexys3/TCP3/source/server.h)", $signed(register_1));
end
16'd41:
begin
timer <= register_1;
timer_enable <= 1;
stage_0_enable <= 0;
stage_1_enable <= 0;
stage_2_enable <= 0;
end
endcase
end
if (s_output_eth_tx_stb == 1'b1 && output_eth_tx_ack == 1'b1) begin
s_output_eth_tx_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_output_socket_stb == 1'b1 && output_socket_ack == 1'b1) begin
s_output_socket_stb <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_eth_rx_ack == 1'b1 && input_eth_rx_stb == 1'b1) begin
result_2 <= input_eth_rx;
write_enable_2 <= 1;
s_input_eth_rx_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (s_input_socket_ack == 1'b1 && input_socket_stb == 1'b1) begin
result_2 <= input_socket;
write_enable_2 <= 1;
s_input_socket_ack <= 1'b0;
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
end
if (timer == 0) begin
if (timer_enable) begin
stage_0_enable <= 1;
stage_1_enable <= 1;
stage_2_enable <= 1;
timer_enable <= 0;
end
end else begin
timer <= timer - 1;
end
if (rst == 1'b1) begin
stage_0_enable <= 1;
stage_1_enable <= 0;
stage_2_enable <= 0;
timer <= 0;
timer_enable <= 0;
program_counter <= 0;
s_input_eth_rx_ack <= 0;
s_input_socket_ack <= 0;
s_output_socket_stb <= 0;
s_output_eth_tx_stb <= 0;
end
end
assign input_eth_rx_ack = s_input_eth_rx_ack;
assign input_socket_ack = s_input_socket_ack;
assign output_socket_stb = s_output_socket_stb;
assign output_socket = s_output_socket;
assign output_eth_tx_stb = s_output_eth_tx_stb;
assign output_eth_tx = s_output_eth_tx;
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V
`define SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__NOR4_BEHAVIORAL_PP_V |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__OR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LP__OR3B_FUNCTIONAL_PP_V
/**
* or3b: 3-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__or3b (
X ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , C_N );
or or0 (or0_out_X , B, A, not0_out );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__OR3B_FUNCTIONAL_PP_V |
// $Id: c_wf_alloc_rot.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// wavefront allocator variant which rotates inputs and outputs based on
// priority
module c_wf_alloc_rot
(clk, reset, update, req, gnt);
`include "c_functions.v"
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// try to recover from errors
parameter error_recovery = 0; // FIXME: actually implement this
parameter reset_type = `RESET_TYPE_ASYNC;
localparam prio_width = clogb(num_ports);
input clk;
input reset;
// update arbitration priorities
input update;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] y;
wire [0:prio_width-1] prio_next, prio_q;
c_incr
#(.width(prio_width),
.min_value(0),
.max_value(num_ports-1))
prio_incr
(.data_in(prio_q),
.data_out(prio_next));
wire [0:prio_width-1] prio_s;
assign prio_s = update ? prio_next : prio_q;
c_dff
#(.width(prio_width),
.reset_type(reset_type))
prioq
(.clk(clk),
.reset(reset),
.d(prio_s),
.q(prio_q));
generate
genvar row;
for(row = 0; row < num_ports; row = row + 1)
begin:rows
wire [0:num_ports-1] req_row;
assign req_row = req[row*num_ports:(row+1)*num_ports-1];
wire [0:prio_width-1] current_row;
assign current_row = row;
wire [0:num_ports-1] req_tmp;
c_rotator
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_RIGHT))
req_tmp_rot
(.amount(current_row),
.data_in(req_row),
.data_out(req_tmp));
wire [0:num_ports-1] req_in;
c_rotator
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_LEFT))
req_in_rot
(.amount(prio_q),
.data_in(req_tmp),
.data_out(req_in));
wire [0:num_ports-1] x_in, y_in;
wire [0:num_ports] x_out, y_out;
assign x_in = x_out[0:num_ports-1];
assign y_in = y[((row+num_ports)%num_ports)*num_ports:
((row+num_ports)%num_ports+1)*num_ports-1];
assign x_out = {1'b1, (~y_in | ~req_in) & x_in};
assign y_out = {1'b1, (~x_in | ~req_in) & y_in};
wire [0:num_ports-1] gnt_out;
assign gnt_out = req_in & x_in & y_in;
assign y[((row+num_ports+1)%num_ports)*num_ports:
((row+num_ports+1)%num_ports+1)*num_ports-1]
= y_out[0:num_ports-1];
wire [0:num_ports-1] gnt_tmp;
c_rotator
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_RIGHT))
gnt_tmp_rot
(.amount(prio_q),
.data_in(gnt_out),
.data_out(gnt_tmp));
wire [0:num_ports-1] gnt_row;
c_rotator
#(.width(num_ports),
.rotate_dir(`ROTATE_DIR_LEFT))
gnt_row_rot
(.amount(current_row),
.data_in(gnt_tmp),
.data_out(gnt_row));
assign gnt[row*num_ports:(row+1)*num_ports-1] = gnt_row;
end
endgenerate
endmodule
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.