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module main();
// Parameters
parameter PER=10;
// FIFO parameters
parameter DATA_WIDTH = 8;
parameter DEPTH = 32;
parameter CNTR_WIDTH = 6; // floor(log(32)) + 1
parameter RD_WINDOW = 1;
parameter RD_ADVANCE = 1;
parameter RD_ADDR_WIDTH = 1;
parameter WR_WINDOW = 1;
parameter WR_ADVANCE = 1;
parameter WR_ADDR_WIDTH = 1;
// Clock & reset
reg clk;
reg rst;
// Module inputs
reg [DATA_WIDTH-1:0] write_data;
// FIFO interface abstraction:
// Connect deq to read_advance and read_ready
// Connect enq to write_advance and write_valid
// Set read_addr and write_addr to 0
reg deq;
reg enq;
// Module outputs
wire [DATA_WIDTH-1:0] read_data;
wire read_valid;
wire write_ready;
wire [CNTR_WIDTH-1:0] status_counter;
// Module instantiation
tvm_buffer #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(DEPTH),
.CNTR_WIDTH(CNTR_WIDTH),
.RD_WINDOW(RD_WINDOW),
.RD_ADVANCE(RD_ADVANCE),
.RD_ADDR_WIDTH(RD_ADDR_WIDTH),
.WR_WINDOW(WR_WINDOW),
.WR_ADVANCE(WR_ADVANCE),
.WR_ADDR_WIDTH(WR_ADDR_WIDTH)
) uut (
.clk(clk),
.rst(rst),
.read_advance(deq),
.read_addr({RD_ADDR_WIDTH{1'b0}}),
.read_ready(deq),
.read_valid(read_valid),
.read_data(read_data),
.write_advance(enq),
.write_addr({WR_ADDR_WIDTH{1'b0}}),
.write_ready(write_ready),
.write_valid(enq),
.write_data(write_data),
.status_counter(status_counter)
);
// clock generation
always begin
#(PER/2) clk =~ clk;
end
// fifo read logic
always @(posedge clk) begin
if (rst)
deq <= 0;
else
deq <= read_valid;
end
// read_data_valid logic
reg read_data_valid;
always @(posedge clk) begin
if (rst)
read_data_valid <= 0;
else
read_data_valid <= deq;
end
initial begin
// This will allow tvm session to be called every cycle.
$tvm_session(clk);
end
endmodule
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// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun Jun 04 15:55:33 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_clk_wiz_1_0 -prefix
// system_clk_wiz_1_0_ system_clk_wiz_1_0_stub.v
// Design : system_clk_wiz_1_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
module system_clk_wiz_1_0(clk_out1, clk_in1)
/* synthesis syn_black_box black_box_pad_pin="clk_out1,clk_in1" */;
output clk_out1;
input clk_in1;
endmodule
|
// Copyright 2007, Martin Whitaker
// This file may be freely copied for any purpose.
module macro_with_args();
`define forward_and_reverse(str1,str2,str3) /* comment */ \
$write("%0s", str1); /* comment */ \
$write(".."); /* comment */ \
$write("%0s", str3); /* comment */ \
$write("%0s", str2); /* comment */ \
$write("%0s", str3); /* comment */ \
$write(".."); /* comment */ \
$write("%0s", str1); /* comment */ \
$write("\n")
`define sqr( x ) (x * x) // comment
`define sum( a /* comment */ , b /* comment */ ) /* comment */ \
(a + b)
`define sumsqr(
a // comment
,
b // comment
) \
`sum ( \
`sqr(a) \
, \
`sqr(b) \
)
`define no_args (a,b,c)
`define null1 // null
`define null2
integer value;
reg [79:0] astr, bstr, cstr;
initial begin
`forward_and_reverse("first"," first,last ","last");
$sformat(astr, "(a%s)", ``null1);
$sformat(bstr, " %s ", ``no_args);
$sformat(cstr, "(c%s)", ``null2);
`forward_and_reverse // comment
( // comment
astr // comment
, // comment
bstr // comment
, // comment
cstr // comment
); // comment
value = `sumsqr(3,4);
$display("sumsqr(3,4) = %1d", value);
if (value != `sqr(5)) $display("sumsqr expansion failed");
value = `sumsqr
(
(2 + 3) /* 5 */
,
(4 + 8) /* 12 */
);
$display("sumsqr(5,12) = %1d", value);
if (value != `sqr(13)) $display("sumsqr expansion failed");
end
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:axi_crossbar:2.1
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_xbar_1 (
aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_rvalid,
m_axi_rready
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLKIF CLK" *)
input wire aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RSTIF RST" *)
input wire aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI AWADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI AWBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI AWPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI AWQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI AWREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI AWREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI WDATA [63:0] [127:64]" *)
input wire [127 : 0] s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WSTRB [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI WSTRB [7:0] [15:8]" *)
input wire [15 : 0] s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WLAST [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI WREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI WREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI BRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI BREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI BREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARADDR [31:0] [31:0], xilinx.com:interface:aximm:1.0 S01_AXI ARADDR [31:0] [63:32]" *)
input wire [63 : 0] s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLEN [7:0] [7:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLEN [7:0] [15:8]" *)
input wire [15 : 0] s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARSIZE [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARSIZE [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARBURST [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI ARBURST [1:0] [3:2]" *)
input wire [3 : 0] s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARLOCK [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARLOCK [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARCACHE [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARCACHE [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARPROT [2:0] [2:0], xilinx.com:interface:aximm:1.0 S01_AXI ARPROT [2:0] [5:3]" *)
input wire [5 : 0] s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARQOS [3:0] [3:0], xilinx.com:interface:aximm:1.0 S01_AXI ARQOS [3:0] [7:4]" *)
input wire [7 : 0] s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARVALID [0:0] [1:1]" *)
input wire [1 : 0] s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI ARREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI ARREADY [0:0] [1:1]" *)
output wire [1 : 0] s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RDATA [63:0] [63:0], xilinx.com:interface:aximm:1.0 S01_AXI RDATA [63:0] [127:64]" *)
output wire [127 : 0] s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RRESP [1:0] [1:0], xilinx.com:interface:aximm:1.0 S01_AXI RRESP [1:0] [3:2]" *)
output wire [3 : 0] s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RLAST [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RLAST [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RVALID [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RVALID [0:0] [1:1]" *)
output wire [1 : 0] s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S00_AXI RREADY [0:0] [0:0], xilinx.com:interface:aximm:1.0 S01_AXI RREADY [0:0] [1:1]" *)
input wire [1 : 0] s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWID" *)
output wire [0 : 0] m_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWADDR" *)
output wire [31 : 0] m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLEN" *)
output wire [7 : 0] m_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWSIZE" *)
output wire [2 : 0] m_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWBURST" *)
output wire [1 : 0] m_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWLOCK" *)
output wire [0 : 0] m_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWCACHE" *)
output wire [3 : 0] m_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWPROT" *)
output wire [2 : 0] m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREGION" *)
output wire [3 : 0] m_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWQOS" *)
output wire [3 : 0] m_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWVALID" *)
output wire [0 : 0] m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI AWREADY" *)
input wire [0 : 0] m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WDATA" *)
output wire [63 : 0] m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WSTRB" *)
output wire [7 : 0] m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WLAST" *)
output wire [0 : 0] m_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WVALID" *)
output wire [0 : 0] m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI WREADY" *)
input wire [0 : 0] m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BID" *)
input wire [0 : 0] m_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BRESP" *)
input wire [1 : 0] m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BVALID" *)
input wire [0 : 0] m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI BREADY" *)
output wire [0 : 0] m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARID" *)
output wire [0 : 0] m_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARADDR" *)
output wire [31 : 0] m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLEN" *)
output wire [7 : 0] m_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARSIZE" *)
output wire [2 : 0] m_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARBURST" *)
output wire [1 : 0] m_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARLOCK" *)
output wire [0 : 0] m_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARCACHE" *)
output wire [3 : 0] m_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARPROT" *)
output wire [2 : 0] m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREGION" *)
output wire [3 : 0] m_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARQOS" *)
output wire [3 : 0] m_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARVALID" *)
output wire [0 : 0] m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI ARREADY" *)
input wire [0 : 0] m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RID" *)
input wire [0 : 0] m_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RDATA" *)
input wire [63 : 0] m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RRESP" *)
input wire [1 : 0] m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RLAST" *)
input wire [0 : 0] m_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RVALID" *)
input wire [0 : 0] m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M00_AXI RREADY" *)
output wire [0 : 0] m_axi_rready;
axi_crossbar_v2_1_axi_crossbar #(
.C_FAMILY("zynq"),
.C_NUM_SLAVE_SLOTS(2),
.C_NUM_MASTER_SLOTS(1),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(64),
.C_AXI_PROTOCOL(0),
.C_NUM_ADDR_RANGES(1),
.C_M_AXI_BASE_ADDR(64'H0000000000000000),
.C_M_AXI_ADDR_WIDTH(32'H0000001e),
.C_S_AXI_BASE_ID(64'H0000000100000000),
.C_S_AXI_THREAD_ID_WIDTH(64'H0000000000000000),
.C_AXI_SUPPORTS_USER_SIGNALS(0),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_M_AXI_WRITE_CONNECTIVITY(32'H00000003),
.C_M_AXI_READ_CONNECTIVITY(32'H00000003),
.C_R_REGISTER(0),
.C_S_AXI_SINGLE_THREAD(64'H0000000000000000),
.C_S_AXI_WRITE_ACCEPTANCE(64'H0000000400000004),
.C_S_AXI_READ_ACCEPTANCE(64'H0000000400000004),
.C_M_AXI_WRITE_ISSUING(32'H00000008),
.C_M_AXI_READ_ISSUING(32'H00000008),
.C_S_AXI_ARB_PRIORITY(64'H0000000000000000),
.C_M_AXI_SECURE(32'H00000000),
.C_CONNECTIVITY_MODE(1)
) inst (
.aclk(aclk),
.aresetn(aresetn),
.s_axi_awid(s_axi_awid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awlen(s_axi_awlen),
.s_axi_awsize(s_axi_awsize),
.s_axi_awburst(s_axi_awburst),
.s_axi_awlock(s_axi_awlock),
.s_axi_awcache(s_axi_awcache),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awuser(2'H0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_awready(s_axi_awready),
.s_axi_wid(2'H0),
.s_axi_wdata(s_axi_wdata),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wlast(s_axi_wlast),
.s_axi_wuser(2'H0),
.s_axi_wvalid(s_axi_wvalid),
.s_axi_wready(s_axi_wready),
.s_axi_bid(s_axi_bid),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_bready(s_axi_bready),
.s_axi_arid(s_axi_arid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arlen(s_axi_arlen),
.s_axi_arsize(s_axi_arsize),
.s_axi_arburst(s_axi_arburst),
.s_axi_arlock(s_axi_arlock),
.s_axi_arcache(s_axi_arcache),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_aruser(2'H0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arready(s_axi_arready),
.s_axi_rid(s_axi_rid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rresp(s_axi_rresp),
.s_axi_rlast(s_axi_rlast),
.s_axi_ruser(),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rready(s_axi_rready),
.m_axi_awid(m_axi_awid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awlen(m_axi_awlen),
.m_axi_awsize(m_axi_awsize),
.m_axi_awburst(m_axi_awburst),
.m_axi_awlock(m_axi_awlock),
.m_axi_awcache(m_axi_awcache),
.m_axi_awprot(m_axi_awprot),
.m_axi_awregion(m_axi_awregion),
.m_axi_awqos(m_axi_awqos),
.m_axi_awuser(),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_awready(m_axi_awready),
.m_axi_wid(),
.m_axi_wdata(m_axi_wdata),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wlast(m_axi_wlast),
.m_axi_wuser(),
.m_axi_wvalid(m_axi_wvalid),
.m_axi_wready(m_axi_wready),
.m_axi_bid(m_axi_bid),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'H0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.m_axi_arid(m_axi_arid),
.m_axi_araddr(m_axi_araddr),
.m_axi_arlen(m_axi_arlen),
.m_axi_arsize(m_axi_arsize),
.m_axi_arburst(m_axi_arburst),
.m_axi_arlock(m_axi_arlock),
.m_axi_arcache(m_axi_arcache),
.m_axi_arprot(m_axi_arprot),
.m_axi_arregion(m_axi_arregion),
.m_axi_arqos(m_axi_arqos),
.m_axi_aruser(),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_arready(m_axi_arready),
.m_axi_rid(m_axi_rid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rresp(m_axi_rresp),
.m_axi_rlast(m_axi_rlast),
.m_axi_ruser(1'H0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_rready(m_axi_rready)
);
endmodule
|
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_7_b2s_ar_channel #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of ID signals.
// Range: >= 1.
parameter integer C_ID_WIDTH = 4,
// Width of AxADDR
// Range: 32.
parameter integer C_AXI_ADDR_WIDTH = 32
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI Slave Interface
// Slave Interface System Signals
input wire clk ,
input wire reset ,
// Slave Interface Read Address Ports
input wire [C_ID_WIDTH-1:0] s_arid ,
input wire [C_AXI_ADDR_WIDTH-1:0] s_araddr ,
input wire [7:0] s_arlen ,
input wire [2:0] s_arsize ,
input wire [1:0] s_arburst ,
input wire s_arvalid ,
output wire s_arready ,
output wire m_arvalid ,
output wire [C_AXI_ADDR_WIDTH-1:0] m_araddr ,
input wire m_arready ,
// Connections to/from axi_protocol_converter_v2_1_7_b2s_r_channel module
output wire [C_ID_WIDTH-1:0] r_arid ,
output wire r_push ,
output wire r_rlast ,
input wire r_full
);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
wire next ;
wire next_pending ;
wire a_push;
wire incr_burst;
reg [C_ID_WIDTH-1:0] s_arid_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// Translate the AXI transaction to the MC transaction(s)
axi_protocol_converter_v2_1_7_b2s_cmd_translator #
(
.C_AXI_ADDR_WIDTH ( C_AXI_ADDR_WIDTH )
)
cmd_translator_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_axaddr ( s_araddr ) ,
.s_axlen ( s_arlen ) ,
.s_axsize ( s_arsize ) ,
.s_axburst ( s_arburst ) ,
.s_axhandshake ( s_arvalid & a_push ) ,
.incr_burst ( incr_burst ) ,
.m_axaddr ( m_araddr ) ,
.next ( next ) ,
.next_pending ( next_pending )
);
axi_protocol_converter_v2_1_7_b2s_rd_cmd_fsm ar_cmd_fsm_0
(
.clk ( clk ) ,
.reset ( reset ) ,
.s_arready ( s_arready ) ,
.s_arvalid ( s_arvalid ) ,
.s_arlen ( s_arlen ) ,
.m_arvalid ( m_arvalid ) ,
.m_arready ( m_arready ) ,
.next ( next ) ,
.next_pending ( next_pending ) ,
.data_ready ( ~r_full ) ,
.a_push ( a_push ) ,
.r_push ( r_push )
);
// these signals can be moved out of this block to the top level.
assign r_arid = s_arid_r;
assign r_rlast = ~next_pending;
always @(posedge clk) begin
s_arid_r <= s_arid ;
end
endmodule
`default_nettype wire
|
// (C) 1992-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_ic_to_avm #(
parameter integer DATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1
)
(
// AVM interface
output logic avm_enable,
output logic avm_read,
output logic avm_write,
output logic [DATA_W-1:0] avm_writedata,
output logic [BURSTCOUNT_W-1:0] avm_burstcount,
output logic [ADDRESS_W-1:0] avm_address,
output logic [BYTEENA_W-1:0] avm_byteenable,
input logic avm_waitrequest,
input logic avm_readdatavalid,
input logic [DATA_W-1:0] avm_readdata,
input logic avm_writeack, // not a true Avalon signal, so ignore this
// IC interface
input logic ic_arb_request,
input logic ic_arb_enable,
input logic ic_arb_read,
input logic ic_arb_write,
input logic [DATA_W-1:0] ic_arb_writedata,
input logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
input logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
input logic [BYTEENA_W-1:0] ic_arb_byteenable,
input logic [ID_W-1:0] ic_arb_id,
output logic ic_arb_stall,
output logic ic_wrp_ack,
output logic ic_rrp_datavalid,
output logic [DATA_W-1:0] ic_rrp_data
);
assign avm_read = ic_arb_read;
assign avm_write = ic_arb_write;
assign avm_writedata = ic_arb_writedata;
assign avm_burstcount = ic_arb_burstcount;
assign avm_address = {ic_arb_address, {$clog2(DATA_W / 8){1'b0}}};
assign avm_byteenable = ic_arb_byteenable;
assign ic_arb_stall = avm_waitrequest;
assign ic_rrp_datavalid = avm_readdatavalid;
assign ic_rrp_data = avm_readdata;
//assign ic_wrp_ack = avm_writeack;
assign ic_wrp_ack = avm_write & ~avm_waitrequest;
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:xlslice:1.0
// IP Revision: 0
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module design_1_xlslice_4_0 (
Din,
Dout
);
input wire [31 : 0] Din;
output wire [23 : 0] Dout;
xlslice #(
.DIN_WIDTH(32),
.DIN_FROM(29),
.DIN_TO(6)
) inst (
.Din(Din),
.Dout(Dout)
);
endmodule
|
(** * MoreCoq: More About Coq's Tactics *)
Require Export Poly.
(** This chapter introduces several more proof strategies and
tactics that, together, allow us to prove theorems about the
functional programs we have been writing. In particular, we'll
reason about functions that work with natural numbers and lists.
In particular, we will see:
- how to use auxiliary lemmas, in both forwards and backwards reasoning;
- how to reason about data constructors, which are injective and disjoint;
- how to create a strong induction hypotheses (and when
strengthening is required); and
- how to reason by case analysis.
*)
(* ###################################################### *)
(** * The [apply] Tactic *)
(** We often encounter situations where the goal to be proved is
exactly the same as some hypothesis in the context or some
previously proved lemma. *)
Theorem silly1 : forall (n m o p : nat),
n = m ->
[n;o] = [n;p] ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
rewrite <- eq1.
(* At this point, we could finish with
"[rewrite -> eq2. reflexivity.]" as we have
done several times above. But we can achieve the
same effect in a single step by using the
[apply] tactic instead: *)
apply eq2. Qed.
(** The [apply] tactic also works with _conditional_ hypotheses
and lemmas: if the statement being applied is an implication, then
the premises of this implication will be added to the list of
subgoals needing to be proved. *)
Theorem silly2 : forall (n m o p : nat),
n = m ->
(forall (q r : nat), q = r -> [q;o] = [r;p]) ->
[n;o] = [m;p].
Proof.
intros n m o p eq1 eq2.
apply eq2. apply eq1. Qed.
(** You may find it instructive to experiment with this proof
and see if there is a way to complete it using just [rewrite]
instead of [apply]. *)
(** Typically, when we use [apply H], the statement [H] will
begin with a [forall] binding some _universal variables_. When
Coq matches the current goal against the conclusion of [H], it
will try to find appropriate values for these variables. For
example, when we do [apply eq2] in the following proof, the
universal variable [q] in [eq2] gets instantiated with [n] and [r]
gets instantiated with [m]. *)
Theorem silly2a : forall (n m : nat),
(n,n) = (m,m) ->
(forall (q r : nat), (q,q) = (r,r) -> [q] = [r]) ->
[n] = [m].
Proof.
intros n m eq1 eq2.
apply eq2. apply eq1. Qed.
(** **** Exercise: 2 stars, optional (silly_ex) *)
(** Complete the following proof without using [simpl]. *)
Theorem silly_ex :
(forall n, evenb n = true -> oddb (S n) = true) ->
evenb 3 = true ->
oddb 4 = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** To use the [apply] tactic, the (conclusion of the) fact
being applied must match the goal _exactly_ -- for example, [apply]
will not work if the left and right sides of the equality are
swapped. *)
Theorem silly3_firsttry : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
simpl.
(* Here we cannot use [apply] directly *)
Abort.
(** In this case we can use the [symmetry] tactic, which switches the
left and right sides of an equality in the goal. *)
Theorem silly3 : forall (n : nat),
true = beq_nat n 5 ->
beq_nat (S (S n)) 7 = true.
Proof.
intros n H.
symmetry.
simpl. (* Actually, this [simpl] is unnecessary, since
[apply] will perform simplification first. *)
apply H. Qed.
(** **** Exercise: 3 stars (apply_exercise1) *)
(** Hint: you can use [apply] with previously defined lemmas, not
just hypotheses in the context. Remember that [SearchAbout] is
your friend. *)
Theorem rev_exercise1 : forall (l l' : list nat),
l = rev l' ->
l' = rev l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (apply_rewrite) *)
(** Briefly explain the difference between the tactics [apply] and
[rewrite]. Are there situations where both can usefully be
applied?
(* FILL IN HERE *)
*)
(** [] *)
(* ###################################################### *)
(** * The [apply ... with ...] Tactic *)
(** The following silly example uses two rewrites in a row to
get from [[a,b]] to [[e,f]]. *)
Example trans_eq_example : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
rewrite -> eq1. rewrite -> eq2. reflexivity. Qed.
(** Since this is a common pattern, we might
abstract it out as a lemma recording once and for all
the fact that equality is transitive. *)
Theorem trans_eq : forall (X:Type) (n m o : X),
n = m -> m = o -> n = o.
Proof.
intros X n m o eq1 eq2. rewrite -> eq1. rewrite -> eq2.
reflexivity. Qed.
(** Now, we should be able to use [trans_eq] to
prove the above example. However, to do this we need
a slight refinement of the [apply] tactic. *)
Example trans_eq_example' : forall (a b c d e f : nat),
[a;b] = [c;d] ->
[c;d] = [e;f] ->
[a;b] = [e;f].
Proof.
intros a b c d e f eq1 eq2.
(* If we simply tell Coq [apply trans_eq] at this point,
it can tell (by matching the goal against the
conclusion of the lemma) that it should instantiate [X]
with [[nat]], [n] with [[a,b]], and [o] with [[e,f]].
However, the matching process doesn't determine an
instantiation for [m]: we have to supply one explicitly
by adding [with (m:=[c,d])] to the invocation of
[apply]. *)
apply trans_eq with (m:=[c;d]). apply eq1. apply eq2. Qed.
(** Actually, we usually don't have to include the name [m]
in the [with] clause; Coq is often smart enough to
figure out which instantiation we're giving. We could
instead write: [apply trans_eq with [c,d]]. *)
(** **** Exercise: 3 stars, optional (apply_with_exercise) *)
Example trans_eq_exercise : forall (n m o p : nat),
m = (minustwo o) ->
(n + p) = m ->
(n + p) = (minustwo o).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * The [inversion] tactic *)
(** Recall the definition of natural numbers:
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
It is clear from this definition that every number has one of two
forms: either it is the constructor [O] or it is built by applying
the constructor [S] to another number. But there is more here than
meets the eye: implicit in the definition (and in our informal
understanding of how datatype declarations work in other
programming languages) are two other facts:
- The constructor [S] is _injective_. That is, the only way we can
have [S n = S m] is if [n = m].
- The constructors [O] and [S] are _disjoint_. That is, [O] is not
equal to [S n] for any [n]. *)
(** Similar principles apply to all inductively defined types: all
constructors are injective, and the values built from distinct
constructors are never equal. For lists, the [cons] constructor is
injective and [nil] is different from every non-empty list. For
booleans, [true] and [false] are unequal. (Since neither [true]
nor [false] take any arguments, their injectivity is not an issue.) *)
(** Coq provides a tactic called [inversion] that allows us to exploit
these principles in proofs.
The [inversion] tactic is used like this. Suppose [H] is a
hypothesis in the context (or a previously proven lemma) of the
form
c a1 a2 ... an = d b1 b2 ... bm
for some constructors [c] and [d] and arguments [a1 ... an] and
[b1 ... bm]. Then [inversion H] instructs Coq to "invert" this
equality to extract the information it contains about these terms:
- If [c] and [d] are the same constructor, then we know, by the
injectivity of this constructor, that [a1 = b1], [a2 = b2],
etc.; [inversion H] adds these facts to the context, and tries
to use them to rewrite the goal.
- If [c] and [d] are different constructors, then the hypothesis
[H] is contradictory. That is, a false assumption has crept
into the context, and this means that any goal whatsoever is
provable! In this case, [inversion H] marks the current goal as
completed and pops it off the goal stack. *)
(** The [inversion] tactic is probably easier to understand by
seeing it in action than from general descriptions like the above.
Below you will find example theorems that demonstrate the use of
[inversion] and exercises to test your understanding. *)
Theorem eq_add_S : forall (n m : nat),
S n = S m ->
n = m.
Proof.
intros n m eq. inversion eq. reflexivity. Qed.
Theorem silly4 : forall (n m : nat),
[n] = [m] ->
n = m.
Proof.
intros n o eq. inversion eq. reflexivity. Qed.
(** As a convenience, the [inversion] tactic can also
destruct equalities between complex values, binding
multiple variables as it goes. *)
Theorem silly5 : forall (n m o : nat),
[n;m] = [o;o] ->
[n] = [m].
Proof.
intros n m o eq. inversion eq. reflexivity. Qed.
(** **** Exercise: 1 star (sillyex1) *)
Example sillyex1 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = z :: j ->
y :: l = x :: j ->
x = y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Theorem silly6 : forall (n : nat),
S n = O ->
2 + 2 = 5.
Proof.
intros n contra. inversion contra. Qed.
Theorem silly7 : forall (n m : nat),
false = true ->
[n] = [m].
Proof.
intros n m contra. inversion contra. Qed.
(** **** Exercise: 1 star (sillyex2) *)
Example sillyex2 : forall (X : Type) (x y z : X) (l j : list X),
x :: y :: l = [] ->
y :: l = z :: j ->
x = z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** While the injectivity of constructors allows us to reason
[forall (n m : nat), S n = S m -> n = m], the reverse direction of
the implication is an instance of a more general fact about
constructors and functions, which we will often find useful: *)
Theorem f_equal : forall (A B : Type) (f: A -> B) (x y: A),
x = y -> f x = f y.
Proof. intros A B f x y eq. rewrite eq. reflexivity. Qed.
(** **** Exercise: 2 stars, optional (practice) *)
(** A couple more nontrivial but not-too-complicated proofs to work
together in class, or for you to work as exercises. *)
Theorem beq_nat_0_l : forall n,
beq_nat 0 n = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
Theorem beq_nat_0_r : forall n,
beq_nat n 0 = true -> n = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using Tactics on Hypotheses *)
(** By default, most tactics work on the goal formula and leave
the context unchanged. However, most tactics also have a variant
that performs a similar operation on a statement in the context.
For example, the tactic [simpl in H] performs simplification in
the hypothesis named [H] in the context. *)
Theorem S_inj : forall (n m : nat) (b : bool),
beq_nat (S n) (S m) = b ->
beq_nat n m = b.
Proof.
intros n m b H. simpl in H. apply H. Qed.
(** Similarly, the tactic [apply L in H] matches some
conditional statement [L] (of the form [L1 -> L2], say) against a
hypothesis [H] in the context. However, unlike ordinary
[apply] (which rewrites a goal matching [L2] into a subgoal [L1]),
[apply L in H] matches [H] against [L1] and, if successful,
replaces it with [L2].
In other words, [apply L in H] gives us a form of "forward
reasoning" -- from [L1 -> L2] and a hypothesis matching [L1], it
gives us a hypothesis matching [L2]. By contrast, [apply L] is
"backward reasoning" -- it says that if we know [L1->L2] and we
are trying to prove [L2], it suffices to prove [L1].
Here is a variant of a proof from above, using forward reasoning
throughout instead of backward reasoning. *)
Theorem silly3' : forall (n : nat),
(beq_nat n 5 = true -> beq_nat (S (S n)) 7 = true) ->
true = beq_nat n 5 ->
true = beq_nat (S (S n)) 7.
Proof.
intros n eq H.
symmetry in H. apply eq in H. symmetry in H.
apply H. Qed.
(** Forward reasoning starts from what is _given_ (premises,
previously proven theorems) and iteratively draws conclusions from
them until the goal is reached. Backward reasoning starts from
the _goal_, and iteratively reasons about what would imply the
goal, until premises or previously proven theorems are reached.
If you've seen informal proofs before (for example, in a math or
computer science class), they probably used forward reasoning. In
general, Coq tends to favor backward reasoning, but in some
situations the forward style can be easier to use or to think
about. *)
(** **** Exercise: 3 stars (plus_n_n_injective) *)
(** Practice using "in" variants in this exercise. *)
Theorem plus_n_n_injective : forall n m,
n + n = m + m ->
n = m.
Proof.
intros n. induction n as [| n'].
(* Hint: use the plus_n_Sm lemma *)
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Varying the Induction Hypothesis *)
(** Sometimes it is important to control the exact form of the
induction hypothesis when carrying out inductive proofs in Coq.
In particular, we need to be careful about which of the
assumptions we move (using [intros]) from the goal to the context
before invoking the [induction] tactic. For example, suppose
we want to show that the [double] function is injective -- i.e.,
that it always maps different arguments to different results:
Theorem double_injective: forall n m, double n = double m -> n = m.
The way we _start_ this proof is a little bit delicate: if we
begin it with
intros n. induction n.
]]
all is well. But if we begin it with
intros n m. induction n.
we get stuck in the middle of the inductive case... *)
Theorem double_injective_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction n as [| n'].
Case "n = O". simpl. intros eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'". intros eq. destruct m as [| m'].
SCase "m = O". inversion eq.
SCase "m = S m'". apply f_equal.
(* Here we are stuck. The induction hypothesis, [IHn'], does
not give us [n' = m'] -- there is an extra [S] in the
way -- so the goal is not provable. *)
Abort.
(** What went wrong? *)
(** The problem is that, at the point we invoke the induction
hypothesis, we have already introduced [m] into the context --
intuitively, we have told Coq, "Let's consider some particular
[n] and [m]..." and we now have to prove that, if [double n =
double m] for _this particular_ [n] and [m], then [n = m].
The next tactic, [induction n] says to Coq: We are going to show
the goal by induction on [n]. That is, we are going to prove that
the proposition
- [P n] = "if [double n = double m], then [n = m]"
holds for all [n] by showing
- [P O]
(i.e., "if [double O = double m] then [O = m]")
- [P n -> P (S n)]
(i.e., "if [double n = double m] then [n = m]" implies "if
[double (S n) = double m] then [S n = m]").
If we look closely at the second statement, it is saying something
rather strange: it says that, for a _particular_ [m], if we know
- "if [double n = double m] then [n = m]"
then we can prove
- "if [double (S n) = double m] then [S n = m]".
To see why this is strange, let's think of a particular [m] --
say, [5]. The statement is then saying that, if we know
- [Q] = "if [double n = 10] then [n = 5]"
then we can prove
- [R] = "if [double (S n) = 10] then [S n = 5]".
But knowing [Q] doesn't give us any help with proving [R]! (If we
tried to prove [R] from [Q], we would say something like "Suppose
[double (S n) = 10]..." but then we'd be stuck: knowing that
[double (S n)] is [10] tells us nothing about whether [double n]
is [10], so [Q] is useless at this point.) *)
(** To summarize: Trying to carry out this proof by induction on [n]
when [m] is already in the context doesn't work because we are
trying to prove a relation involving _every_ [n] but just a
_single_ [m]. *)
(** The good proof of [double_injective] leaves [m] in the goal
statement at the point where the [induction] tactic is invoked on
[n]: *)
Theorem double_injective : forall n m,
double n = double m ->
n = m.
Proof.
intros n. induction n as [| n'].
Case "n = O". simpl. intros m eq. destruct m as [| m'].
SCase "m = O". reflexivity.
SCase "m = S m'". inversion eq.
Case "n = S n'".
(* Notice that both the goal and the induction
hypothesis have changed: the goal asks us to prove
something more general (i.e., to prove the
statement for _every_ [m]), but the IH is
correspondingly more flexible, allowing us to
choose any [m] we like when we apply the IH. *)
intros m eq.
(* Now we choose a particular [m] and introduce the
assumption that [double n = double m]. Since we
are doing a case analysis on [n], we need a case
analysis on [m] to keep the two "in sync." *)
destruct m as [| m'].
SCase "m = O".
(* The 0 case is trivial *)
inversion eq.
SCase "m = S m'".
apply f_equal.
(* At this point, since we are in the second
branch of the [destruct m], the [m'] mentioned
in the context at this point is actually the
predecessor of the one we started out talking
about. Since we are also in the [S] branch of
the induction, this is perfect: if we
instantiate the generic [m] in the IH with the
[m'] that we are talking about right now (this
instantiation is performed automatically by
[apply]), then [IHn'] gives us exactly what we
need to finish the proof. *)
apply IHn'. inversion eq. reflexivity. Qed.
(** What this teaches us is that we need to be careful about using
induction to try to prove something too specific: If we're proving
a property of [n] and [m] by induction on [n], we may need to
leave [m] generic. *)
(** The proof of this theorem (left as an exercise) has to be treated similarly: *)
(** **** Exercise: 2 stars (beq_nat_true) *)
Theorem beq_nat_true : forall n m,
beq_nat n m = true -> n = m.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, advanced (beq_nat_true_informal) *)
(** Give a careful informal proof of [beq_nat_true], being as explicit
as possible about quantifiers. *)
(* FILL IN HERE *)
(** [] *)
(** The strategy of doing fewer [intros] before an [induction] doesn't
always work directly; sometimes a little _rearrangement_ of
quantified variables is needed. Suppose, for example, that we
wanted to prove [double_injective] by induction on [m] instead of
[n]. *)
Theorem double_injective_take2_FAILED : forall n m,
double n = double m ->
n = m.
Proof.
intros n m. induction m as [| m'].
Case "m = O". simpl. intros eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
(* Stuck again here, just like before. *)
Abort.
(** The problem is that, to do induction on [m], we must first
introduce [n]. (If we simply say [induction m] without
introducing anything first, Coq will automatically introduce
[n] for us!) *)
(** What can we do about this? One possibility is to rewrite the
statement of the lemma so that [m] is quantified before [n]. This
will work, but it's not nice: We don't want to have to mangle the
statements of lemmas to fit the needs of a particular strategy for
proving them -- we want to state them in the most clear and
natural way. *)
(** What we can do instead is to first introduce all the
quantified variables and then _re-generalize_ one or more of
them, taking them out of the context and putting them back at
the beginning of the goal. The [generalize dependent] tactic
does this. *)
Theorem double_injective_take2 : forall n m,
double n = double m ->
n = m.
Proof.
intros n m.
(* [n] and [m] are both in the context *)
generalize dependent n.
(* Now [n] is back in the goal and we can do induction on
[m] and get a sufficiently general IH. *)
induction m as [| m'].
Case "m = O". simpl. intros n eq. destruct n as [| n'].
SCase "n = O". reflexivity.
SCase "n = S n'". inversion eq.
Case "m = S m'". intros n eq. destruct n as [| n'].
SCase "n = O". inversion eq.
SCase "n = S n'". apply f_equal.
apply IHm'. inversion eq. reflexivity. Qed.
(** Let's look at an informal proof of this theorem. Note that
the proposition we prove by induction leaves [n] quantified,
corresponding to the use of generalize dependent in our formal
proof.
_Theorem_: For any nats [n] and [m], if [double n = double m], then
[n = m].
_Proof_: Let [m] be a [nat]. We prove by induction on [m] that, for
any [n], if [double n = double m] then [n = m].
- First, suppose [m = 0], and suppose [n] is a number such
that [double n = double m]. We must show that [n = 0].
Since [m = 0], by the definition of [double] we have [double n =
0]. There are two cases to consider for [n]. If [n = 0] we are
done, since this is what we wanted to show. Otherwise, if [n = S
n'] for some [n'], we derive a contradiction: by the definition of
[double] we would have [double n = S (S (double n'))], but this
contradicts the assumption that [double n = 0].
- Otherwise, suppose [m = S m'] and that [n] is again a number such
that [double n = double m]. We must show that [n = S m'], with
the induction hypothesis that for every number [s], if [double s =
double m'] then [s = m'].
By the fact that [m = S m'] and the definition of [double], we
have [double n = S (S (double m'))]. There are two cases to
consider for [n].
If [n = 0], then by definition [double n = 0], a contradiction.
Thus, we may assume that [n = S n'] for some [n'], and again by
the definition of [double] we have [S (S (double n')) = S (S
(double m'))], which implies by inversion that [double n' = double
m'].
Instantiating the induction hypothesis with [n'] thus allows us to
conclude that [n' = m'], and it follows immediately that [S n' = S
m']. Since [S n' = n] and [S m' = m], this is just what we wanted
to show. [] *)
(** Here's another illustration of [inversion] and using an
appropriately general induction hypothesis. This is a slightly
roundabout way of stating a fact that we have already proved
above. The extra equalities force us to do a little more
equational reasoning and exercise some of the tactics we've seen
recently. *)
Theorem length_snoc' : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l. induction l as [| v' l'].
Case "l = []".
intros n eq. rewrite <- eq. reflexivity.
Case "l = v' :: l'".
intros n eq. simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. apply IHl'. inversion eq. reflexivity. Qed.
(** It might be tempting to start proving the above theorem
by introducing [n] and [eq] at the outset. However, this leads
to an induction hypothesis that is not strong enough. Compare
the above to the following (aborted) attempt: *)
Theorem length_snoc_bad : forall (X : Type) (v : X)
(l : list X) (n : nat),
length l = n ->
length (snoc l v) = S n.
Proof.
intros X v l n eq. induction l as [| v' l'].
Case "l = []".
rewrite <- eq. reflexivity.
Case "l = v' :: l'".
simpl. destruct n as [| n'].
SCase "n = 0". inversion eq.
SCase "n = S n'".
apply f_equal. Abort. (* apply IHl'. *) (* The IH doesn't apply! *)
(** As in the double examples, the problem is that by
introducing [n] before doing induction on [l], the induction
hypothesis is specialized to one particular natural number, namely
[n]. In the induction case, however, we need to be able to use
the induction hypothesis on some other natural number [n'].
Retaining the more general form of the induction hypothesis thus
gives us more flexibility.
In general, a good rule of thumb is to make the induction hypothesis
as general as possible. *)
(** **** Exercise: 3 stars (gen_dep_practice) *)
(** Prove this by induction on [l]. *)
Theorem index_after_last: forall (n : nat) (X : Type) (l : list X),
length l = n ->
index n l = None.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (index_after_last_informal) *)
(** Write an informal proof corresponding to your Coq proof
of [index_after_last]:
_Theorem_: For all sets [X], lists [l : list X], and numbers
[n], if [length l = n] then [index n l = None].
_Proof_:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (gen_dep_practice_more) *)
(** Prove this by induction on [l]. *)
Theorem length_snoc''' : forall (n : nat) (X : Type)
(v : X) (l : list X),
length l = n ->
length (snoc l v) = S n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (app_length_cons) *)
(** Prove this by induction on [l1], without using [app_length]
from [Lists]. *)
Theorem app_length_cons : forall (X : Type) (l1 l2 : list X)
(x : X) (n : nat),
length (l1 ++ (x :: l2)) = n ->
S (length (l1 ++ l2)) = n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, optional (app_length_twice) *)
(** Prove this by induction on [l], without using app_length. *)
Theorem app_length_twice : forall (X:Type) (n:nat) (l:list X),
length l = n ->
length (l ++ l) = n + n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (double_induction) *)
(** Prove the following principle of induction over two naturals. *)
Theorem double_induction: forall (P : nat -> nat -> Prop),
P 0 0 ->
(forall m, P m 0 -> P (S m) 0) ->
(forall n, P 0 n -> P 0 (S n)) ->
(forall m n, P m n -> P (S m) (S n)) ->
forall m n, P m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ###################################################### *)
(** * Using [destruct] on Compound Expressions *)
(** We have seen many examples where the [destruct] tactic is
used to perform case analysis of the value of some variable. But
sometimes we need to reason by cases on the result of some
_expression_. We can also do this with [destruct].
Here are some examples: *)
Definition sillyfun (n : nat) : bool :=
if beq_nat n 3 then false
else if beq_nat n 5 then false
else false.
Theorem sillyfun_false : forall (n : nat),
sillyfun n = false.
Proof.
intros n. unfold sillyfun.
destruct (beq_nat n 3).
Case "beq_nat n 3 = true". reflexivity.
Case "beq_nat n 3 = false". destruct (beq_nat n 5).
SCase "beq_nat n 5 = true". reflexivity.
SCase "beq_nat n 5 = false". reflexivity. Qed.
(** After unfolding [sillyfun] in the above proof, we find that
we are stuck on [if (beq_nat n 3) then ... else ...]. Well,
either [n] is equal to [3] or it isn't, so we use [destruct
(beq_nat n 3)] to let us reason about the two cases.
In general, the [destruct] tactic can be used to perform case
analysis of the results of arbitrary computations. If [e] is an
expression whose type is some inductively defined type [T], then,
for each constructor [c] of [T], [destruct e] generates a subgoal
in which all occurrences of [e] (in the goal and in the context)
are replaced by [c].
*)
(** **** Exercise: 1 star (override_shadow) *)
Theorem override_shadow : forall (X:Type) x1 x2 k1 k2 (f : nat->X),
(override (override f k1 x2) k1 x1) k2 = (override f k1 x1) k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (combine_split) *)
(** Complete the proof below *)
Theorem combine_split : forall X Y (l : list (X * Y)) l1 l2,
split l = (l1, l2) ->
combine l1 l2 = l.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Sometimes, doing a [destruct] on a compound expression (a
non-variable) will erase information we need to complete a proof. *)
(** For example, suppose
we define a function [sillyfun1] like this: *)
Definition sillyfun1 (n : nat) : bool :=
if beq_nat n 3 then true
else if beq_nat n 5 then true
else false.
(** And suppose that we want to convince Coq of the rather
obvious observation that [sillyfun1 n] yields [true] only when [n]
is odd. By analogy with the proofs we did with [sillyfun] above,
it is natural to start the proof like this: *)
Theorem sillyfun1_odd_FAILED : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3).
(* stuck... *)
Abort.
(** We get stuck at this point because the context does not
contain enough information to prove the goal! The problem is that
the substitution peformed by [destruct] is too brutal -- it threw
away every occurrence of [beq_nat n 3], but we need to keep some
memory of this expression and how it was destructed, because we
need to be able to reason that since, in this branch of the case
analysis, [beq_nat n 3 = true], it must be that [n = 3], from
which it follows that [n] is odd.
What we would really like is to substitute away all existing
occurences of [beq_nat n 3], but at the same time add an equation
to the context that records which case we are in. The [eqn:]
qualifier allows us to introduce such an equation (with whatever
name we choose). *)
Theorem sillyfun1_odd : forall (n : nat),
sillyfun1 n = true ->
oddb n = true.
Proof.
intros n eq. unfold sillyfun1 in eq.
destruct (beq_nat n 3) eqn:Heqe3.
(* Now we have the same state as at the point where we got stuck
above, except that the context contains an extra equality
assumption, which is exactly what we need to make progress. *)
Case "e3 = true". apply beq_nat_true in Heqe3.
rewrite -> Heqe3. reflexivity.
Case "e3 = false".
(* When we come to the second equality test in the body of the
function we are reasoning about, we can use [eqn:] again in the
same way, allow us to finish the proof. *)
destruct (beq_nat n 5) eqn:Heqe5.
SCase "e5 = true".
apply beq_nat_true in Heqe5.
rewrite -> Heqe5. reflexivity.
SCase "e5 = false". inversion eq. Qed.
(** **** Exercise: 2 stars (destruct_eqn_practice) *)
Theorem bool_fn_applied_thrice :
forall (f : bool -> bool) (b : bool),
f (f (f b)) = f b.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (override_same) *)
Theorem override_same : forall (X:Type) x1 k1 k2 (f : nat->X),
f k1 = x1 ->
(override f k1 x1) k2 = f k2.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ################################################################## *)
(** * Review *)
(** We've now seen a bunch of Coq's fundamental tactics. We'll
introduce a few more as we go along through the coming lectures,
and later in the course we'll introduce some more powerful
_automation_ tactics that make Coq do more of the low-level work
in many cases. But basically we've got what we need to get work
done.
Here are the ones we've seen:
- [intros]:
move hypotheses/variables from goal to context
- [reflexivity]:
finish the proof (when the goal looks like [e = e])
- [apply]:
prove goal using a hypothesis, lemma, or constructor
- [apply... in H]:
apply a hypothesis, lemma, or constructor to a hypothesis in
the context (forward reasoning)
- [apply... with...]:
explicitly specify values for variables that cannot be
determined by pattern matching
- [simpl]:
simplify computations in the goal
- [simpl in H]:
... or a hypothesis
- [rewrite]:
use an equality hypothesis (or lemma) to rewrite the goal
- [rewrite ... in H]:
... or a hypothesis
- [symmetry]:
changes a goal of the form [t=u] into [u=t]
- [symmetry in H]:
changes a hypothesis of the form [t=u] into [u=t]
- [unfold]:
replace a defined constant by its right-hand side in the goal
- [unfold... in H]:
... or a hypothesis
- [destruct... as...]:
case analysis on values of inductively defined types
- [destruct... eqn:...]:
specify the name of an equation to be added to the context,
recording the result of the case analysis
- [induction... as...]:
induction on values of inductively defined types
- [inversion]:
reason by injectivity and distinctness of constructors
- [assert (e) as H]:
introduce a "local lemma" [e] and call it [H]
- [generalize dependent x]:
move the variable [x] (and anything else that depends on it)
from the context back to an explicit hypothesis in the goal
formula
*)
(* ###################################################### *)
(** * Additional Exercises *)
(** **** Exercise: 3 stars (beq_nat_sym) *)
Theorem beq_nat_sym : forall (n m : nat),
beq_nat n m = beq_nat m n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced, optional (beq_nat_sym_informal) *)
(** Give an informal proof of this lemma that corresponds to your
formal proof above:
Theorem: For any [nat]s [n] [m], [beq_nat n m = beq_nat m n].
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 3 stars, optional (beq_nat_trans) *)
Theorem beq_nat_trans : forall n m p,
beq_nat n m = true ->
beq_nat m p = true ->
beq_nat n p = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (split_combine) *)
(** We have just proven that for all lists of pairs, [combine] is the
inverse of [split]. How would you formalize the statement that
[split] is the inverse of [combine]? When is this property true?
Complete the definition of [split_combine_statement] below with a
property that states that [split] is the inverse of
[combine]. Then, prove that the property holds. (Be sure to leave
your induction hypothesis general by not doing [intros] on more
things than necessary. Hint: what property do you need of [l1]
and [l2] for [split] [combine l1 l2 = (l1,l2)] to be true?) *)
Definition split_combine_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem split_combine : split_combine_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars (override_permute) *)
Theorem override_permute : forall (X:Type) x1 x2 k1 k2 k3 (f : nat->X),
beq_nat k2 k1 = false ->
(override (override f k2 x2) k1 x1) k3 = (override (override f k1 x1) k2 x2) k3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (filter_exercise) *)
(** This one is a bit challenging. Pay attention to the form of your IH. *)
Theorem filter_exercise : forall (X : Type) (test : X -> bool)
(x : X) (l lf : list X),
filter test l = x :: lf ->
test x = true.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars, advanced (forall_exists_challenge) *)
(** Define two recursive [Fixpoints], [forallb] and [existsb]. The
first checks whether every element in a list satisfies a given
predicate:
forallb oddb [1;3;5;7;9] = true
forallb negb [false;false] = true
forallb evenb [0;2;4;5] = false
forallb (beq_nat 5) [] = true
The second checks whether there exists an element in the list that
satisfies a given predicate:
existsb (beq_nat 5) [0;2;3;6] = false
existsb (andb true) [true;true;false] = true
existsb oddb [1;0;0;0;0;3] = true
existsb evenb [] = false
Next, define a _nonrecursive_ version of [existsb] -- call it
[existsb'] -- using [forallb] and [negb].
Prove theorem [existsb_existsb'] that [existsb'] and [existsb] have
the same behavior.
*)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 16:01:37 -0500 (Wed, 31 Dec 2014) $ *)
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_altdqdqs (
core_clock_in,
reset_n_core_clock_in,
fr_clock_in,
hr_clock_in,
write_strobe_clock_in,
write_strobe,
strobe_ena_hr_clock_in,
capture_strobe_tracking,
read_write_data_io,
write_oe_in,
strobe_io,
output_strobe_ena,
strobe_n_io,
oct_ena_in,
read_data_out,
capture_strobe_out,
write_data_in,
extra_write_data_in,
extra_write_data_out,
parallelterminationcontrol_in,
seriesterminationcontrol_in,
config_data_in,
config_update,
config_dqs_ena,
config_io_ena,
config_extra_io_ena,
config_dqs_io_ena,
config_clock_in,
lfifo_rdata_en,
lfifo_rdata_en_full,
lfifo_rd_latency,
lfifo_reset_n,
lfifo_rdata_valid,
vfifo_qvld,
vfifo_inc_wr_ptr,
vfifo_reset_n,
rfifo_reset_n,
dll_delayctrl_in
);
input [7-1:0] dll_delayctrl_in;
input core_clock_in;
input reset_n_core_clock_in;
input fr_clock_in;
input hr_clock_in;
input write_strobe_clock_in;
input [3:0] write_strobe;
input strobe_ena_hr_clock_in;
output capture_strobe_tracking;
inout [8-1:0] read_write_data_io;
input [2*8-1:0] write_oe_in;
inout strobe_io;
input [2-1:0] output_strobe_ena;
inout strobe_n_io;
input [2-1:0] oct_ena_in;
output [2 * 2 * 8-1:0] read_data_out;
output capture_strobe_out;
input [2 * 2 * 8-1:0] write_data_in;
input [2 * 2 * 1-1:0] extra_write_data_in;
output [1-1:0] extra_write_data_out;
input [16-1:0] parallelterminationcontrol_in;
input [16-1:0] seriesterminationcontrol_in;
input config_data_in;
input config_update;
input config_dqs_ena;
input [8-1:0] config_io_ena;
input [1-1:0] config_extra_io_ena;
input config_dqs_io_ena;
input config_clock_in;
input [2-1:0] lfifo_rdata_en;
input [2-1:0] lfifo_rdata_en_full;
input [4:0] lfifo_rd_latency;
input lfifo_reset_n;
output lfifo_rdata_valid;
input [2-1:0] vfifo_qvld;
input [2-1:0] vfifo_inc_wr_ptr;
input vfifo_reset_n;
input rfifo_reset_n;
parameter ALTERA_ALTDQ_DQS2_FAST_SIM_MODEL = "";
altdq_dqs2_acv_connect_to_hard_phy_cyclonev altdq_dqs2_inst (
.core_clock_in( core_clock_in),
.reset_n_core_clock_in (reset_n_core_clock_in),
.fr_clock_in( fr_clock_in),
.hr_clock_in( hr_clock_in),
.write_strobe_clock_in (write_strobe_clock_in),
.write_strobe(write_strobe),
.strobe_ena_hr_clock_in( strobe_ena_hr_clock_in),
.capture_strobe_tracking (capture_strobe_tracking),
.read_write_data_io( read_write_data_io),
.write_oe_in( write_oe_in),
.strobe_io( strobe_io),
.output_strobe_ena( output_strobe_ena),
.strobe_n_io( strobe_n_io),
.oct_ena_in( oct_ena_in),
.read_data_out( read_data_out),
.capture_strobe_out( capture_strobe_out),
.write_data_in( write_data_in),
.extra_write_data_in( extra_write_data_in),
.extra_write_data_out( extra_write_data_out),
.parallelterminationcontrol_in( parallelterminationcontrol_in),
.seriesterminationcontrol_in( seriesterminationcontrol_in),
.config_data_in( config_data_in),
.config_update( config_update),
.config_dqs_ena( config_dqs_ena),
.config_io_ena( config_io_ena),
.config_extra_io_ena( config_extra_io_ena),
.config_dqs_io_ena( config_dqs_io_ena),
.config_clock_in( config_clock_in),
.lfifo_rdata_en(lfifo_rdata_en),
.lfifo_rdata_en_full(lfifo_rdata_en_full),
.lfifo_rd_latency(lfifo_rd_latency),
.lfifo_reset_n(lfifo_reset_n),
.lfifo_rdata_valid(lfifo_rdata_valid),
.vfifo_qvld(vfifo_qvld),
.vfifo_inc_wr_ptr(vfifo_inc_wr_ptr),
.vfifo_reset_n(vfifo_reset_n),
.rfifo_reset_n(rfifo_reset_n),
.dll_delayctrl_in(dll_delayctrl_in)
);
defparam altdq_dqs2_inst.PIN_WIDTH = 8;
defparam altdq_dqs2_inst.PIN_TYPE = "bidir";
defparam altdq_dqs2_inst.USE_INPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_OUTPUT_PHASE_ALIGNMENT = "false";
defparam altdq_dqs2_inst.USE_LDC_AS_LOW_SKEW_CLOCK = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_INPUT = "false";
defparam altdq_dqs2_inst.USE_HALF_RATE_OUTPUT = "true";
defparam altdq_dqs2_inst.DIFFERENTIAL_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SEPARATE_CAPTURE_STROBE = "false";
defparam altdq_dqs2_inst.INPUT_FREQ = 400.0;
defparam altdq_dqs2_inst.INPUT_FREQ_PS = "2500 ps";
defparam altdq_dqs2_inst.DELAY_CHAIN_BUFFER_MODE = "high";
defparam altdq_dqs2_inst.DQS_PHASE_SETTING = 0;
defparam altdq_dqs2_inst.DQS_PHASE_SHIFT = 0;
defparam altdq_dqs2_inst.DQS_ENABLE_PHASE_SETTING = 3;
defparam altdq_dqs2_inst.USE_DYNAMIC_CONFIG = "true";
defparam altdq_dqs2_inst.INVERT_CAPTURE_STROBE = "true";
defparam altdq_dqs2_inst.SWAP_CAPTURE_STROBE_POLARITY = "false";
defparam altdq_dqs2_inst.USE_TERMINATION_CONTROL = "true";
defparam altdq_dqs2_inst.USE_DQS_ENABLE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_OUTPUT_STROBE_RESET = "false";
defparam altdq_dqs2_inst.DIFFERENTIAL_OUTPUT_STROBE = "true";
defparam altdq_dqs2_inst.USE_BIDIR_STROBE = "true";
defparam altdq_dqs2_inst.REVERSE_READ_WORDS = "false";
defparam altdq_dqs2_inst.EXTRA_OUTPUT_WIDTH = 1;
defparam altdq_dqs2_inst.DYNAMIC_MODE = "dynamic";
defparam altdq_dqs2_inst.OCT_SERIES_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.OCT_PARALLEL_TERM_CONTROL_WIDTH = 16;
defparam altdq_dqs2_inst.DLL_WIDTH = 7;
defparam altdq_dqs2_inst.USE_DATA_OE_FOR_OCT = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_WIDTH = 1;
defparam altdq_dqs2_inst.USE_OCT_ENA_IN_FOR_OCT = "true";
defparam altdq_dqs2_inst.PREAMBLE_TYPE = "high";
defparam altdq_dqs2_inst.EMIF_UNALIGNED_PREAMBLE_SUPPORT = "false";
defparam altdq_dqs2_inst.EMIF_BYPASS_OCT_DDIO = "false";
defparam altdq_dqs2_inst.USE_OFFSET_CTRL = "false";
defparam altdq_dqs2_inst.HR_DDIO_OUT_HAS_THREE_REGS = "false";
defparam altdq_dqs2_inst.DQS_ENABLE_PHASECTRL = "true";
defparam altdq_dqs2_inst.USE_2X_FF = "false";
defparam altdq_dqs2_inst.DLL_USE_2X_CLK = "false";
defparam altdq_dqs2_inst.USE_DQS_TRACKING = "true";
defparam altdq_dqs2_inst.USE_HARD_FIFOS = "true";
defparam altdq_dqs2_inst.USE_DQSIN_FOR_VFIFO_READ = "false";
defparam altdq_dqs2_inst.CALIBRATION_SUPPORT = "false";
defparam altdq_dqs2_inst.NATURAL_ALIGNMENT = "true";
defparam altdq_dqs2_inst.SEPERATE_LDC_FOR_WRITE_STROBE = "false";
defparam altdq_dqs2_inst.HHP_HPS = "true";
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_saturation_endEe_DSP48_0(
input [20 - 1:0] in0,
input [16 - 1:0] in1,
input [27 - 1:0] in2,
output [36 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in0);
assign b = $signed(in1);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_saturation_endEe(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_saturation_endEe_DSP48_0 hls_saturation_endEe_DSP48_0_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__SDFRBP_PP_SYMBOL_V
`define SKY130_FD_SC_HS__SDFRBP_PP_SYMBOL_V
/**
* sdfrbp: Scan delay flop, inverted reset, non-inverted clock,
* complementary outputs.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__sdfrbp (
//# {{data|Data Signals}}
input D ,
output Q ,
output Q_N ,
//# {{control|Control Signals}}
input RESET_B,
//# {{scanchain|Scan Chain}}
input SCD ,
input SCE ,
//# {{clocks|Clocking}}
input CLK ,
//# {{power|Power}}
input VPWR ,
input VGND
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__SDFRBP_PP_SYMBOL_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_buf.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ecc_buf
#(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 4,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DATA_WIDTH = 64,
parameter nCK_PER_CLK = 4
)
(
/*AUTOARG*/
// Outputs
rd_merge_data,
// Inputs
clk, rst, rd_data_addr, rd_data_offset, wr_data_addr,
wr_data_offset, rd_data, wr_ecc_buf
);
input clk;
input rst;
// RMW architecture supports only 16 data buffer entries.
// Allow DATA_BUF_ADDR_WIDTH to be greater than 4, but
// assume the upper bits are used for tagging.
input [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
wire [4:0] buf_wr_addr;
input [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
input [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
reg [4:0] buf_rd_addr_r;
generate
if (DATA_BUF_ADDR_WIDTH >= 4) begin : ge_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{wr_data_addr[3:0], wr_data_offset};
assign buf_wr_addr = {rd_data_addr[3:0], rd_data_offset};
end
else begin : lt_4_addr_bits
always @(posedge clk)
buf_rd_addr_r <= #TCQ{{4-DATA_BUF_ADDR_WIDTH{1'b0}},
wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
wr_data_offset};
assign buf_wr_addr = {{4-DATA_BUF_ADDR_WIDTH{1'b0}},
rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0],
rd_data_offset};
end
endgenerate
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data;
reg [2*nCK_PER_CLK*DATA_WIDTH-1:0] payload;
integer h;
always @(/*AS*/rd_data)
for (h=0; h<2*nCK_PER_CLK; h=h+1)
payload[h*DATA_WIDTH+:DATA_WIDTH] =
rd_data[h*PAYLOAD_WIDTH+:DATA_WIDTH];
input wr_ecc_buf;
localparam BUF_WIDTH = 2*nCK_PER_CLK*DATA_WIDTH;
localparam FULL_RAM_CNT = (BUF_WIDTH/6);
localparam REMAINDER = BUF_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
wire [RAM_WIDTH-1:0] buf_out_data;
generate
begin : ram_buf
wire [RAM_WIDTH-1:0] buf_in_data;
if (REMAINDER == 0)
assign buf_in_data = payload;
else
assign buf_in_data = {{6-REMAINDER{1'b0}}, payload};
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : rd_buffer_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(buf_out_data[((i*6)+4)+:2]),
.DOB(buf_out_data[((i*6)+2)+:2]),
.DOC(buf_out_data[((i*6)+0)+:2]),
.DOD(),
.DIA(buf_in_data[((i*6)+4)+:2]),
.DIB(buf_in_data[((i*6)+2)+:2]),
.DIC(buf_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(buf_rd_addr_r),
.ADDRB(buf_rd_addr_r),
.ADDRC(buf_rd_addr_r),
.ADDRD(buf_wr_addr),
.WE(wr_ecc_buf),
.WCLK(clk)
);
end // block: rd_buffer_ram
end
endgenerate
output wire [2*nCK_PER_CLK*DATA_WIDTH-1:0] rd_merge_data;
assign rd_merge_data = buf_out_data[2*nCK_PER_CLK*DATA_WIDTH-1:0];
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module nvme_irq # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [15:0] cfg_command,
output cfg_interrupt,
input cfg_interrupt_rdy,
output cfg_interrupt_assert,
output [7:0] cfg_interrupt_di,
input [7:0] cfg_interrupt_do,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input cfg_interrupt_msixfm,
output cfg_interrupt_stat,
output [4:0] cfg_pciecap_interrupt_msgnum,
input nvme_intms_ivms,
input nvme_intmc_ivmc,
output cq_irq_status,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
input [7:0] admin_cq_tail_ptr,
input [7:0] io_cq1_tail_ptr,
input [7:0] io_cq2_tail_ptr,
input [7:0] io_cq3_tail_ptr,
input [7:0] io_cq4_tail_ptr,
input [7:0] io_cq5_tail_ptr,
input [7:0] io_cq6_tail_ptr,
input [7:0] io_cq7_tail_ptr,
input [7:0] io_cq8_tail_ptr,
input [7:0] admin_cq_head_ptr,
input [7:0] io_cq1_head_ptr,
input [7:0] io_cq2_head_ptr,
input [7:0] io_cq3_head_ptr,
input [7:0] io_cq4_head_ptr,
input [7:0] io_cq5_head_ptr,
input [7:0] io_cq6_head_ptr,
input [7:0] io_cq7_head_ptr,
input [7:0] io_cq8_head_ptr,
input [8:0] cq_head_update
);
wire w_pcie_legacy_irq_set;
wire w_pcie_msi_irq_set;
wire [2:0] w_pcie_irq_vector;
wire w_pcie_legacy_irq_clear;
wire w_pcie_irq_done;
pcie_irq_gen
pcie_irq_gen_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt (cfg_interrupt),
.cfg_interrupt_rdy (cfg_interrupt_rdy),
.cfg_interrupt_assert (cfg_interrupt_assert),
.cfg_interrupt_di (cfg_interrupt_di),
.cfg_interrupt_do (cfg_interrupt_do),
.cfg_interrupt_mmenable (cfg_interrupt_mmenable),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.cfg_interrupt_msixenable (cfg_interrupt_msixenable),
.cfg_interrupt_msixfm (cfg_interrupt_msixfm),
.cfg_interrupt_stat (cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum (cfg_pciecap_interrupt_msgnum),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
nvme_irq_handler
nvme_irq_handler_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.cfg_command (cfg_command),
.cfg_interrupt_msienable (cfg_interrupt_msienable),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.cq_rst_n (cq_rst_n),
.cq_valid (cq_valid),
.io_cq_irq_en (io_cq_irq_en),
.io_cq1_iv (io_cq1_iv),
.io_cq2_iv (io_cq2_iv),
.io_cq3_iv (io_cq3_iv),
.io_cq4_iv (io_cq4_iv),
.io_cq5_iv (io_cq5_iv),
.io_cq6_iv (io_cq6_iv),
.io_cq7_iv (io_cq7_iv),
.io_cq8_iv (io_cq8_iv),
.admin_cq_tail_ptr (admin_cq_tail_ptr),
.io_cq1_tail_ptr (io_cq1_tail_ptr),
.io_cq2_tail_ptr (io_cq2_tail_ptr),
.io_cq3_tail_ptr (io_cq3_tail_ptr),
.io_cq4_tail_ptr (io_cq4_tail_ptr),
.io_cq5_tail_ptr (io_cq5_tail_ptr),
.io_cq6_tail_ptr (io_cq6_tail_ptr),
.io_cq7_tail_ptr (io_cq7_tail_ptr),
.io_cq8_tail_ptr (io_cq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update),
.pcie_legacy_irq_set (w_pcie_legacy_irq_set),
.pcie_msi_irq_set (w_pcie_msi_irq_set),
.pcie_irq_vector (w_pcie_irq_vector),
.pcie_legacy_irq_clear (w_pcie_legacy_irq_clear),
.pcie_irq_done (w_pcie_irq_done)
);
endmodule
|
/***********************************************
Module Name: name of the module (i.e., frac_FreqDiv)
Feature: feature description(i.e., Integer frequency division)
Coder: name of the writer (i.e., Garfield)
Organization: department of the writer(i.e., XXXX Group, Department of Architecture)
------------------------------------------------------
Input ports: input-port(s) list
(i.e., CLK_in, 1bit clock
RST, 1 bit, reset)
Output Ports: output-port(s) list
(i.e., CLK_out, Divided Clock)
------------------------------------------------------
History: story on creation, verification and modification oprations
(i.e., 02-05-2016: First Version by Garfield
02-05-2016: First verified by int_FreqDiv_test ISE/Modelsim)
***********************************************/
module frac_FreqDiv #(parameter DIV_IN = 3, DIV_OUT = 2)
//module declaration (with parameter(s))
//parameter(s)description, (i.e., DIV: factor for frequency division)
(
input CLK_in, RST,
output CLK_out
);
//port(s) list
//Declaration of local parameter(s) with descriptions
localparam N = DIV_IN / DIV_OUT;
localparam DIV_X = DIV_IN - DIV_OUT * N;
localparam DIV_Y = DIV_OUT;
localparam M1 = DIV_Y - DIV_X;
localparam M2 = DIV_X;
//Parameters in the paper
localparam CLK_M1 = M1 * N;
localparam CLK_M2 = M2 * (N + 1);
//Clock numbers for two periods
localparam CLK_NUMBER = CLK_M1 + CLK_M2;
//Total clock number
localparam WIDTH = int_log2(CLK_NUMBER);
//Counter width
//function(s) and task(s) definition
function integer int_log2(input integer num);
//feature description, i.e., Return the up-integer for log2(num)
begin
int_log2 = 1;
//operation description, i.e., Initial
while ( (2 ** int_log2) < num)
//Not reaching the number
begin
int_log2 = int_log2 + 1;
end
end
endfunction
//Definition for Variables in the module with description
reg[WIDTH - 1:0] counter;
//Counter inset
wire c1, c2;
//Clock output for the two int_FreqDiv modules
reg sync1, sync2;
//Synchronization control
reg clk_selection;
//Clock slection between the two integer frequncy division modules
//Load other module(s)
int_FreqDiv #(.DIV(N)) I1(.CLK_in(CLK_in), .RST(RST),.SYNC(sync1), .CLK_out(c1));
int_FreqDiv #(.DIV(N+1)) I2(.CLK_in(CLK_in), .RST(RST), .SYNC(sync2), .CLK_out(c2));
//Logic
//assign block(s) with description
assign CLK_out =(clk_selection) ? (c1) : (c2);
//Clock switching
//always blocks
//for combined logic with description
always @(*)
begin
sync1 <= (counter < CLK_M1 );
end
always @(*)
begin
assign sync2 <= ~sync1;
end
//for timing logic with description
always @(posedge CLK_in or negedge RST)
//Counter operation
begin
if (!RST)
//Reset
begin
counter <= 1'h0;
end
else if (counter == CLK_NUMBER - 1)
//Reached the division value
begin
counter <= 1'h0;
end
else
//Not yet
begin
counter <= counter + 1'h1;
end
end
always @(posedge CLK_in or negedge RST)
//Counter operation
begin
if (!RST)
//Reset
begin
clk_selection <=1'b0;
end
else
//1 clock delay for sync1
//Inter_FreqDiv has 1 clock delay between SYNC and CLK_out'e positive edge
begin
clk_selection <= sync1;
end
end
endmodule |
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:27:32 06/14/2012
// Design Name:
// Module Name: reorder_queue
// Project Name:
// Target Devices:
// Tool versions:
// Description:
// Reorders downstream TLPs to output in increasing tag sequence. Input packets
// are stored in RAM and then read out when all previous sequence numbers have
// arrived and been read out. This module also provides the next available tag
// for the TX engine to use when sending memory request TLPs.
//
// Dependencies:
// reorder_queue_input.v
// reorder_queue_output.v
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`include "trellis.vh"
`timescale 1ns / 1ps
module reorder_queue
#(
parameter C_PCI_DATA_WIDTH = 9'd128,
parameter C_NUM_CHNL = 4'd12,
parameter C_MAX_READ_REQ_BYTES = 512, // Max size of read requests (in bytes)
parameter C_TAG_WIDTH = 5, // Number of outstanding requests
// Local parameters
parameter C_PCI_DATA_WORD = C_PCI_DATA_WIDTH/32,
parameter C_PCI_DATA_COUNT_WIDTH = clog2(C_PCI_DATA_WORD+1),
parameter C_NUM_TAGS = 2**C_TAG_WIDTH,
parameter C_DW_PER_TAG = C_MAX_READ_REQ_BYTES/4,
parameter C_TAG_DW_COUNT_WIDTH = clog2s(C_DW_PER_TAG+1),
parameter C_DATA_ADDR_STRIDE_WIDTH = clog2s(C_DW_PER_TAG/C_PCI_DATA_WORD), // div by C_PCI_DATA_WORD b/c there are C_PCI_DATA_WORD RAMs
parameter C_DATA_ADDR_WIDTH = C_TAG_WIDTH + C_DATA_ADDR_STRIDE_WIDTH
)
(
input CLK, // Clock
input RST, // Synchronous reset
input VALID, // Valid input packet
input [C_PCI_DATA_WIDTH-1:0] DATA, // Input packet payload
input [(C_PCI_DATA_WIDTH/32)-1:0] DATA_EN, // Input packet payload data enable
input DATA_START_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_START_OFFSET, // Input packet payload data enable count
input DATA_END_FLAG, // Input packet payload
input [clog2s(C_PCI_DATA_WIDTH/32)-1:0] DATA_END_OFFSET, // Input packet payload data enable count
input DONE, // Input packet done
input ERR, // Input packet has error
input [C_TAG_WIDTH-1:0] TAG, // Input packet tag (external tag)
input [5:0] INT_TAG, // Internal tag to exchange with external
input INT_TAG_VALID, // High to signal tag exchange
output [C_TAG_WIDTH-1:0] EXT_TAG, // External tag to provide in exchange for internal tag
output EXT_TAG_VALID, // High to signal external tag is valid
output [C_PCI_DATA_WIDTH-1:0] ENG_DATA, // Engine data
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] MAIN_DATA_EN, // Main data enable
output [C_NUM_CHNL-1:0] MAIN_DONE, // Main data complete
output [C_NUM_CHNL-1:0] MAIN_ERR, // Main data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_RX_DATA_EN, // Scatter gather for RX data enable
output [C_NUM_CHNL-1:0] SG_RX_DONE, // Scatter gather for RX data complete
output [C_NUM_CHNL-1:0] SG_RX_ERR, // Scatter gather for RX data completed with error
output [(C_NUM_CHNL*C_PCI_DATA_COUNT_WIDTH)-1:0] SG_TX_DATA_EN, // Scatter gather for TX data enable
output [C_NUM_CHNL-1:0] SG_TX_DONE, // Scatter gather for TX data complete
output [C_NUM_CHNL-1:0] SG_TX_ERR // Scatter gather for TX data completed with error
);
wire [(C_DATA_ADDR_WIDTH*C_PCI_DATA_WORD)-1:0] wWrDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wWrData;
wire [C_PCI_DATA_WORD-1:0] wWrDataEn;
wire [C_TAG_WIDTH-1:0] wWrPktTag;
wire [C_TAG_DW_COUNT_WIDTH-1:0] wWrPktWords;
wire wWrPktWordsLTE1;
wire wWrPktWordsLTE2;
wire wWrPktValid;
wire wWrPktDone;
wire wWrPktErr;
wire [C_DATA_ADDR_WIDTH-1:0] wRdDataAddr;
wire [C_PCI_DATA_WIDTH-1:0] wRdData;
wire [C_TAG_WIDTH-1:0] wRdPktTag;
wire [(1+1+1+1+C_TAG_DW_COUNT_WIDTH)-1:0] wRdPktInfo;
wire [5:0] wRdTagMap;
wire [C_NUM_TAGS-1:0] wFinish;
wire [C_NUM_TAGS-1:0] wClear;
reg [C_TAG_WIDTH-1:0] rPos=0;
reg rValid=0;
reg [C_NUM_TAGS-1:0] rFinished=0;
reg [C_NUM_TAGS-1:0] rUse=0;
reg [C_NUM_TAGS-1:0] rUsing=0;
assign EXT_TAG = rPos;
assign EXT_TAG_VALID = rValid;
// Move through tag/slot/bucket space.
always @ (posedge CLK) begin
if (RST) begin
rPos <= #1 0;
rUse <= #1 0;
rValid <= #1 0;
end
else begin
if (INT_TAG_VALID & EXT_TAG_VALID) begin
rPos <= #1 rPos + 1'd1;
rUse <= #1 1<<rPos;
rValid <= #1 !rUsing[rPos + 1'd1];
end
else begin
rUse <= #1 0;
rValid <= #1 !rUsing[rPos];
end
end
end
// Update tag/slot/bucket status.
always @ (posedge CLK) begin
if (RST) begin
rUsing <= #1 0;
rFinished <= #1 0;
end
else begin
rUsing <= #1 (rUsing | rUse) & ~wClear;
rFinished <= #1 (rFinished | wFinish) & ~wClear;
end
end
genvar r;
generate
for (r = 0; r < C_PCI_DATA_WORD; r = r + 1) begin : rams
// RAMs for packet reordering.
(* RAM_STYLE="BLOCK" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(32),
.C_RAM_DEPTH(C_NUM_TAGS*C_DW_PER_TAG/C_PCI_DATA_WORD)
)
ram
(
.CLK(CLK),
.ADDRA(wWrDataAddr[C_DATA_ADDR_WIDTH*r +:C_DATA_ADDR_WIDTH]),
.WEA(wWrDataEn[r]),
.DINA(wWrData[32*r +:32]),
.ADDRB(wRdDataAddr),
.DOUTB(wRdData[32*r +:32])
);
end
endgenerate
// RAM for bucket done, err, final DW count
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(1 + 1 + 1 + 1 + C_TAG_DW_COUNT_WIDTH),
.C_RAM_DEPTH(C_NUM_TAGS))
pktRam
(
.CLK(CLK),
.ADDRA(wWrPktTag),
.WEA((wWrPktDone | wWrPktErr) & wWrPktValid),
.DINA({wWrPktDone, wWrPktErr, wWrPktWordsLTE2, wWrPktWordsLTE1, wWrPktWords}),
.ADDRB(wRdPktTag),
.DOUTB(wRdPktInfo)
);
// RAM for tag map
(* RAM_STYLE="DISTRIBUTED" *)
ram_1clk_1w_1r
#(.C_RAM_WIDTH(6),
.C_RAM_DEPTH(C_NUM_TAGS))
mapRam
(
.CLK(CLK),
.ADDRA(rPos),
.WEA(INT_TAG_VALID & EXT_TAG_VALID),
.DINA(INT_TAG),
.ADDRB(wRdPktTag),
.DOUTB(wRdTagMap)
);
// Demux input data into the correct slot/bucket.
reorder_queue_input
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_input
(
.CLK(CLK),
.RST(RST),
.VALID(VALID),
.DATA_START_FLAG (DATA_START_FLAG),
.DATA_START_OFFSET (DATA_START_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA_END_FLAG (DATA_END_FLAG),
.DATA_END_OFFSET (DATA_END_OFFSET[clog2s(C_PCI_DATA_WIDTH/32)-1:0]),
.DATA (DATA),
.DATA_EN (DATA_EN),
.DONE(DONE),
.ERR(ERR),
.TAG(TAG),
.TAG_FINISH(wFinish),
.TAG_CLEAR(wClear),
.STORED_DATA_ADDR(wWrDataAddr),
.STORED_DATA(wWrData),
.STORED_DATA_EN(wWrDataEn),
.PKT_VALID(wWrPktValid),
.PKT_TAG(wWrPktTag),
.PKT_WORDS(wWrPktWords),
.PKT_WORDS_LTE1(wWrPktWordsLTE1),
.PKT_WORDS_LTE2(wWrPktWordsLTE2),
.PKT_DONE(wWrPktDone),
.PKT_ERR(wWrPktErr)
);
// Output packets in increasing tag order.
reorder_queue_output
#(
.C_PCI_DATA_WIDTH(C_PCI_DATA_WIDTH),
.C_NUM_CHNL(C_NUM_CHNL),
.C_TAG_WIDTH(C_TAG_WIDTH),
.C_TAG_DW_COUNT_WIDTH(C_TAG_DW_COUNT_WIDTH),
.C_DATA_ADDR_STRIDE_WIDTH(C_DATA_ADDR_STRIDE_WIDTH),
.C_DATA_ADDR_WIDTH(C_DATA_ADDR_WIDTH)
)
data_output
(
.CLK(CLK),
.RST(RST),
.DATA_ADDR(wRdDataAddr),
.DATA(wRdData),
.TAG_FINISHED(rFinished),
.TAG_CLEAR(wClear),
.TAG(wRdPktTag),
.TAG_MAPPED(wRdTagMap),
.PKT_WORDS(wRdPktInfo[0 +:C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE1(wRdPktInfo[C_TAG_DW_COUNT_WIDTH]),
.PKT_WORDS_LTE2(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+1]),
.PKT_ERR(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+2]),
.PKT_DONE(wRdPktInfo[C_TAG_DW_COUNT_WIDTH+3]),
.ENG_DATA(ENG_DATA),
.MAIN_DATA_EN(MAIN_DATA_EN),
.MAIN_DONE(MAIN_DONE),
.MAIN_ERR(MAIN_ERR),
.SG_RX_DATA_EN(SG_RX_DATA_EN),
.SG_RX_DONE(SG_RX_DONE),
.SG_RX_ERR(SG_RX_ERR),
.SG_TX_DATA_EN(SG_TX_DATA_EN),
.SG_TX_DONE(SG_TX_DONE),
.SG_TX_ERR(SG_TX_ERR)
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V
/**
* xnor3: 3-input exclusive NOR.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__xnor3 (
X ,
A ,
B ,
C ,
VPWR,
VGND
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input VPWR;
input VGND;
// Local signals
wire xnor0_out_X ;
wire u_vpwr_vgnd0_out_X;
// Name Output Other arguments
xnor xnor0 (xnor0_out_X , A, B, C );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_X, xnor0_out_X, VPWR, VGND);
buf buf0 (X , u_vpwr_vgnd0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__XNOR3_FUNCTIONAL_PP_V |
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ebc_e
//
// Generated
// by: wig
// on: Mon Mar 22 13:27:59 2004
// cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ebc_e.v,v 1.1 2004/04/06 10:50:49 wig Exp $
// $Date: 2004/04/06 10:50:49 $
// $Log: inst_ebc_e.v,v $
// Revision 1.1 2004/04/06 10:50:49 wig
// Adding result/mde_tests
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
//
// Generator: mix_0.pl Revision: 1.26 , [email protected]
// (C) 2003 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns / 1ps
//
//
// Start of Generated Module rtl of inst_ebc_e
//
// No `defines in this module
module inst_ebc_e
//
// Generated module inst_ebc
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ebc_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/* Read memory, dump to UART on trigger */
`timescale 1 ns / 1 ps
`default_nettype none
`define WIDTH 16
module top(input clk,
output TXD, // UART TX
input RXD, // UART RX
input resetq
);
localparam MHZ = 12;
// ###### UART ##########################################
//
wire uart0_valid, uart0_busy;
wire [7:0] uart0_data_in;
wire [7:0] uart0_data_out;
wire uart0_wr;
wire uart0_rd;
reg uart0_reset = 1'b0;
buart _uart0 (
.clk(clk),
.resetq(uart0_reset),
.rx(RXD),
.tx(TXD),
.rd(uart0_rd),
.wr(uart0_wr),
.valid(uart0_valid),
.busy(uart0_busy),
.tx_data(uart0_data_out),
.rx_data(uart0_data_in));
// ###### ROM ##########################################
//
wire [15:0] rom_rd;
wire [7:0] rom_rdb;
wire [8:0] rom_raddr; // 512x8
SB_RAM40_4KNRNW #(
.WRITE_MODE(1), // 8 bit
.READ_MODE(1), // 8 bit
.INIT_0(256'h0000000000400105005501400044504015400014008828bb28a028b028362895),
.INIT_1(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_2(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_3(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_4(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_5(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_6(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_7(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_8(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_9(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_A(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_B(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_C(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_D(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_E(256'h0000000000000000000000000000000000000000000000000000000000000000),
.INIT_F(256'h0000000000000000000000000000000000000000000000000000000000000000)
) _rom (
.RDATA(rom_rd),
.RADDR({2'b00, rom_raddr}),
.RCLKN(clk), .RCLKE(1'b1), .RE(1'b1),
.WCLKN(1'b0), .WCLKE(1'b0), .WE(1'b0),
.WADDR(11'h0),
.MASK(16'h0000), .WDATA(16'h0));
assign rom_rdb = {rom_rd[14],rom_rd[12],rom_rd[10],rom_rd[8],rom_rd[6],rom_rd[4],rom_rd[2],rom_rd[0]}; // read byte
// ###### CPU ##########################################
//
// States
localparam S_IDLE =3'b000,
S_OP =3'b001,
S_IMM8 =3'b010,
S_UART_WAIT=3'b011,
S_UART_END =3'b100,
S_MEM_LOAD =3'b101;
reg [8:0] ptr;
wire [8:0] ptr_plus_one = ptr + 9'h1;
assign rom_raddr = ptr;
reg [8:0] ptr_saved;
reg [7:0] outb;
reg outf;
reg [2:0] state;
reg [7:0] opcode;
reg [7:0] cpuregs [3:0];
always @(posedge clk) begin
case (state)
S_IDLE: begin
// "a" to start
if (uart0_valid && uart0_data_in == "a") begin
ptr <= 9'h0;
state <= S_OP;
end
end
S_OP: begin
opcode <= rom_rdb;
ptr <= ptr_plus_one;
casez (rom_rdb)
8'b00000001, // 0x01 JUMP
8'b000001zz, // 0x04-0x07 MOV IMM r0-r3
8'b000100zz: begin // 0x10-0x13 JNZ
state <= S_IMM8;
end
8'b000010zz: begin // 0x08-0x0B SEND r0-r3
state <= S_UART_WAIT;
outb <= cpuregs[rom_rdb[1:0]];
end
// ALU (single reg)
8'b000011zz: begin // 0x0C-0x0F DEC r0-r3
cpuregs[rom_rdb[1:0]] <= cpuregs[rom_rdb[1:0]] - 8'h1;
end
8'b000110zz: begin // 0x18-0x1B INC r0-r3
cpuregs[rom_rdb[1:0]] <= cpuregs[rom_rdb[1:0]] + 8'h1;
end
// ALU (dual reg)
8'b1000zzzz: begin // 0x80-0x8F ADD rx, ry
cpuregs[rom_rdb[3:2]] <= cpuregs[rom_rdb[3:2]] + cpuregs[rom_rdb[1:0]];
end
// Load from memory (page 2)
8'b1100zzzz: begin // 0xC0-0xCF LD rx,[{ry+1,ry}]
state <= S_MEM_LOAD;
ptr_saved <= ptr_plus_one;
ptr <= {1'b1, cpuregs[{rom_rdb[1],1'b0}]}; // wrong
//ptr <= {1'b1, cpuregs[rom_rdb[1]<<1]}; // wrong
//ptr <= {1'b1, cpuregs[rom_rdb&2'h2]}; // wrong
//ptr <= {1'b1, cpuregs[rom_rdb[1:0]]}; // ok
end
default: begin // Invalid instruction, back to IDLE state
state <= S_IDLE;
end
endcase
end
S_IMM8: begin
ptr <= ptr_plus_one;
state <= S_OP;
casez (opcode)
8'b00000001: begin // JUMP
ptr <= rom_rdb;
end
8'b000100zz: begin // 0x10-0x13 JNZ
if (|cpuregs[opcode[1:0]]) begin
ptr <= rom_rdb;
end
end
8'b000001zz: begin // MOV IMM
cpuregs[opcode[1:0]] <= rom_rdb;
end
endcase
end
S_UART_WAIT: begin
if (!uart0_busy) begin // Send byte when UART ready
state <= S_UART_END;
outf <= 1;
end
end
S_UART_END: begin // Clear outf flag after sending to UART
outf <= 0;
state <= S_OP;
end
S_MEM_LOAD: begin // Load from memory
cpuregs[opcode[3:2]] <= rom_rdb;
ptr <= ptr_saved;
state <= S_OP;
end
endcase
// Reset logic
if (!uart0_reset) begin // Reset UART only for one clock
uart0_reset <= 1;
state <= S_IDLE;
end
end
assign uart0_wr = outf;
assign uart0_rd = (state == S_IDLE);
assign uart0_data_out = outb;
endmodule // top
|
`include "defines.v"
module brouter_3x3(
input `control_w b0000_ci,
input `control_w b0001_ci,
input `control_w b0010_ci,
input `control_w b0100_ci,
input `control_w b0101_ci,
input `control_w b0110_ci,
input `control_w b1000_ci,
input `control_w b1001_ci,
input `control_w b1010_ci,
input `data_w b0000_di,
input `data_w b0001_di,
input `data_w b0010_di,
input `data_w b0100_di,
input `data_w b0101_di,
input `data_w b0110_di,
input `data_w b1000_di,
input `data_w b1001_di,
input `data_w b1010_di,
input clk,
input rst,
output `control_w b0000_co,
output `control_w b0001_co,
output `control_w b0010_co,
output `control_w b0100_co,
output `control_w b0101_co,
output `control_w b0110_co,
output `control_w b1000_co,
output `control_w b1001_co,
output `control_w b1010_co,
output `data_w b0000_do,
output `data_w b0001_do,
output `data_w b0010_do,
output `data_w b0100_do,
output `data_w b0101_do,
output `data_w b0110_do,
output `data_w b1000_do,
output `data_w b1001_do,
output `data_w b1010_do,
output b0000_r,
output b0001_r,
output b0010_r,
output b0100_r,
output b0101_r,
output b0110_r,
output b1000_r,
output b1001_r,
output b1010_r);
wire `control_w c01, c10, c12, c21, c02, c20, // Cols
c45, c54, c56, c65, c46, c64,
c89, c98, ca9, c9a, c8a, ca8,
c04, c40, c48, c84, c08, c80, // Rows
c15, c51, c59, c95, c19, c91,
c26, c62, c6a, ca6, c2a, ca2;
wire `data_w d01, d10, d12, d21, d02, d20, // Cols
d45, d54, d56, d65, d46, d64,
d89, d98, da9, d9a, d8a, da8,
d04, d40, d48, d84, d08, d80, // Rows
d15, d51, d59, d95, d19, d91,
d26, d62, d6a, da6, d2a, da2;
brouter #(4'b0000) br0000
(.port0_ci(c20),
.port0_di(d20),
.port0_co(c02),
.port0_do(d02),
.port1_ci(c10),
.port1_di(d10),
.port1_co(c01),
.port1_do(d01),
.port2_ci(c40),
.port2_di(d40),
.port2_co(c04),
.port2_do(d04),
.port3_ci(c80),
.port3_di(d80),
.port3_co(c08),
.port3_do(d08),
.port4_ci(b0000_ci),
.port4_di(b0000_di),
.port4_co(b0000_co),
.port4_do(b0000_do),
.port4_ready(b0000_r),
.clk(clk),
.rst(rst));
brouter #(4'b0001) br0001
(.port0_ci(c01),
.port0_di(d01),
.port0_co(c10),
.port0_do(d10),
.port1_ci(c21),
.port1_di(d21),
.port1_co(c12),
.port1_do(d12),
.port2_ci(c51),
.port2_di(d51),
.port2_co(c15),
.port2_do(d15),
.port3_ci(c91),
.port3_di(d91),
.port3_co(c19),
.port3_do(d19),
.port4_ci(b0001_ci),
.port4_di(b0001_di),
.port4_co(b0001_co),
.port4_do(b0001_do),
.port4_ready(b0001_r),
.clk(clk),
.rst(rst));
brouter #(4'b0010) br0010
(.port0_ci(c12),
.port0_di(d12),
.port0_co(c21),
.port0_do(d21),
.port1_ci(c02),
.port1_di(d02),
.port1_co(c20),
.port1_do(d20),
.port2_ci(c62),
.port2_di(d62),
.port2_co(c26),
.port2_do(d26),
.port3_ci(ca2),
.port3_di(da2),
.port3_co(c2a),
.port3_do(d2a),
.port4_ci(b0010_ci),
.port4_di(b0010_di),
.port4_co(b0010_co),
.port4_do(b0010_do),
.port4_ready(b0010_r),
.clk(clk),
.rst(rst));
brouter #(4'b0100) br0100
(.port0_ci(c64),
.port0_di(d64),
.port0_co(c46),
.port0_do(d46),
.port1_ci(c54),
.port1_di(d54),
.port1_co(c45),
.port1_do(d45),
.port2_ci(c84),
.port2_di(d84),
.port2_co(c48),
.port2_do(d48),
.port3_ci(c04),
.port3_di(d04),
.port3_co(c40),
.port3_do(d40),
.port4_ci(b0100_ci),
.port4_di(b0100_di),
.port4_co(b0100_co),
.port4_do(b0100_do),
.port4_ready(b0100_r),
.clk(clk),
.rst(rst));
brouter #(4'b0101) br0101
(.port0_ci(c45),
.port0_di(d45),
.port0_co(c54),
.port0_do(d54),
.port1_ci(c65),
.port1_di(d65),
.port1_co(c56),
.port1_do(d56),
.port2_ci(c95),
.port2_di(d95),
.port2_co(c59),
.port2_do(d59),
.port3_ci(c15),
.port3_di(d15),
.port3_co(c51),
.port3_do(d51),
.port4_ci(b0101_ci),
.port4_di(b0101_di),
.port4_co(b0101_co),
.port4_do(b0101_do),
.port4_ready(b0101_r),
.clk(clk),
.rst(rst));
brouter #(4'b0110) br0110
(.port0_ci(c56),
.port0_di(d56),
.port0_co(c65),
.port0_do(d65),
.port1_ci(c46),
.port1_di(d46),
.port1_co(c64),
.port1_do(d64),
.port2_ci(ca6),
.port2_di(da6),
.port2_co(c6a),
.port2_do(d6a),
.port3_ci(c26),
.port3_di(d26),
.port3_co(c62),
.port3_do(d62),
.port4_ci(b0110_ci),
.port4_di(b0110_di),
.port4_co(b0110_co),
.port4_do(b0110_do),
.port4_ready(b0110_r),
.clk(clk),
.rst(rst));
brouter #(4'b1000) br1000
(.port0_ci(ca8),
.port0_di(da8),
.port0_co(c8a),
.port0_do(d8a),
.port1_ci(c98),
.port1_di(d98),
.port1_co(c89),
.port1_do(d89),
.port2_ci(c08),
.port2_di(d08),
.port2_co(c80),
.port2_do(d80),
.port3_ci(c48),
.port3_di(d48),
.port3_co(c84),
.port3_do(d84),
.port4_ci(b1000_ci),
.port4_di(b1000_di),
.port4_co(b1000_co),
.port4_do(b1000_do),
.port4_ready(b1000_r),
.clk(clk),
.rst(rst));
brouter #(4'b1001) br1001
(.port0_ci(c89),
.port0_di(d89),
.port0_co(c98),
.port0_do(d98),
.port1_ci(ca9),
.port1_di(da9),
.port1_co(c9a),
.port1_do(d9a),
.port2_ci(c19),
.port2_di(d19),
.port2_co(c91),
.port2_do(d91),
.port3_ci(c59),
.port3_di(d59),
.port3_co(c95),
.port3_do(d95),
.port4_ci(b1001_ci),
.port4_di(b1001_di),
.port4_co(b1001_co),
.port4_do(b1001_do),
.port4_ready(b1001_r),
.clk(clk),
.rst(rst));
brouter #(4'b1010) br1010
(.port0_ci(c9a),
.port0_di(d9a),
.port0_co(ca9),
.port0_do(da9),
.port1_ci(c8a),
.port1_di(d8a),
.port1_co(ca8),
.port1_do(da8),
.port2_ci(c2a),
.port2_di(d2a),
.port2_co(ca2),
.port2_do(da2),
.port3_ci(c6a),
.port3_di(d6a),
.port3_co(ca6),
.port3_do(da6),
.port4_ci(b1010_ci),
.port4_di(b1010_di),
.port4_co(b1010_co),
.port4_do(b1010_do),
.port4_ready(b1010_r),
.clk(clk),
.rst(rst));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// t_sqrt_pipelined.v
// Created: 4.2.2012
// Modified: 4.5.2012
//
// Testbench for generic sqrt operation
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_sqrt_pipelined();
parameter
INPUT_BITS = 4;
localparam
OUTPUT_BITS = INPUT_BITS / 2 + INPUT_BITS % 2;
reg [INPUT_BITS-1:0] radicand;
reg clk, start, reset_n;
wire [OUTPUT_BITS-1:0] root;
wire data_valid;
// wire [7:0] root_good;
sqrt_pipelined
#(
.INPUT_BITS(INPUT_BITS)
)
sqrt_pipelined
(
.clk(clk),
.reset_n(reset_n),
.start(start),
.radicand(radicand),
.data_valid(data_valid),
.root(root)
);
initial begin
radicand = 16'bx; clk = 1'bx; start = 1'bx; reset_n = 1'bx;;
#10 reset_n = 0; clk = 0;
#50 reset_n = 1; radicand = 0;
// #40 radicand = 81; start = 1;
// #10 radicand = 16'bx; start = 0;
#10000 $finish;
end
always
#5 clk = ~clk;
always begin
#10 radicand = radicand + 1; start = 1;
#10 start = 0;
end
// always begin
// #80 start = 1;
// #10 start = 0;
// end
endmodule
|
/* Copyright (c) 2006 Rice University */
/* All Rights Reserved */
/* This code is covered by the Rice-WARP license */
/* See http://warp.rice.edu/license/ for details */
module user_logic
(
spi_clk,
data_out,
Radio1_cs,
Radio2_cs,
Radio3_cs,
Radio4_cs,
Dac1_cs,
Dac2_cs,
Dac3_cs,
Dac4_cs,
Radio1_SHDN,
Radio1_TxEn,
Radio1_RxEn,
Radio1_RxHP,
Radio1_LD,
Radio1_24PA,
Radio1_5PA,
Radio1_ANTSW,
Radio1_LED,
Radio1_ADC_RX_DCS,
Radio1_ADC_RX_DFS,
Radio1_ADC_RX_OTRA,
Radio1_ADC_RX_OTRB,
Radio1_ADC_RX_PWDNA,
Radio1_ADC_RX_PWDNB,
Radio1_DIPSW,
Radio1_RSSI_ADC_CLAMP,
Radio1_RSSI_ADC_HIZ,
Radio1_RSSI_ADC_OTR,
Radio1_RSSI_ADC_SLEEP,
Radio1_RSSI_ADC_D,
Radio1_TX_DAC_PLL_LOCK,
Radio1_TX_DAC_RESET,
Radio1_RxHP_external,
Radio1_TxGain,
Radio1_TxStart,
Radio2_SHDN,
Radio2_TxEn,
Radio2_RxEn,
Radio2_RxHP,
Radio2_LD,
Radio2_24PA,
Radio2_5PA,
Radio2_ANTSW,
Radio2_LED,
Radio2_ADC_RX_DCS,
Radio2_ADC_RX_DFS,
Radio2_ADC_RX_OTRA,
Radio2_ADC_RX_OTRB,
Radio2_ADC_RX_PWDNA,
Radio2_ADC_RX_PWDNB,
Radio2_DIPSW,
Radio2_RSSI_ADC_CLAMP,
Radio2_RSSI_ADC_HIZ,
Radio2_RSSI_ADC_OTR,
Radio2_RSSI_ADC_SLEEP,
Radio2_RSSI_ADC_D,
Radio2_TX_DAC_PLL_LOCK,
Radio2_TX_DAC_RESET,
Radio2_RxHP_external,
Radio2_TxGain,
Radio2_TxStart,
Radio3_SHDN,
Radio3_TxEn,
Radio3_RxEn,
Radio3_RxHP,
Radio3_LD,
Radio3_24PA,
Radio3_5PA,
Radio3_ANTSW,
Radio3_LED,
Radio3_ADC_RX_DCS,
Radio3_ADC_RX_DFS,
Radio3_ADC_RX_OTRA,
Radio3_ADC_RX_OTRB,
Radio3_ADC_RX_PWDNA,
Radio3_ADC_RX_PWDNB,
Radio3_DIPSW,
Radio3_RSSI_ADC_CLAMP,
Radio3_RSSI_ADC_HIZ,
Radio3_RSSI_ADC_OTR,
Radio3_RSSI_ADC_SLEEP,
Radio3_RSSI_ADC_D,
Radio3_TX_DAC_PLL_LOCK,
Radio3_TX_DAC_RESET,
Radio3_RxHP_external,
Radio3_TxGain,
Radio3_TxStart,
Radio4_SHDN,
Radio4_TxEn,
Radio4_RxEn,
Radio4_RxHP,
Radio4_LD,
Radio4_24PA,
Radio4_5PA,
Radio4_ANTSW,
Radio4_LED,
Radio4_ADC_RX_DCS,
Radio4_ADC_RX_DFS,
Radio4_ADC_RX_OTRA,
Radio4_ADC_RX_OTRB,
Radio4_ADC_RX_PWDNA,
Radio4_ADC_RX_PWDNB,
Radio4_DIPSW,
Radio4_RSSI_ADC_CLAMP,
Radio4_RSSI_ADC_HIZ,
Radio4_RSSI_ADC_OTR,
Radio4_RSSI_ADC_SLEEP,
Radio4_RSSI_ADC_D,
Radio4_TX_DAC_PLL_LOCK,
Radio4_TX_DAC_RESET,
Radio4_RxHP_external,
Radio4_TxGain,
Radio4_TxStart,
// -- DO NOT EDIT BELOW THIS LINE ------------------
// -- Bus protocol ports, do not add to or delete
Bus2IP_Clk, // Bus to IP clock
Bus2IP_Reset, // Bus to IP reset
Bus2IP_Data, // Bus to IP data bus for user logic
Bus2IP_BE, // Bus to IP byte enables for user logic
Bus2IP_RdCE, // Bus to IP read chip enable for user logic
Bus2IP_WrCE, // Bus to IP write chip enable for user logic
IP2Bus_Data, // IP to Bus data bus for user logic
IP2Bus_Ack, // IP to Bus acknowledgement
IP2Bus_Retry, // IP to Bus retry response
IP2Bus_Error, // IP to Bus error response
IP2Bus_ToutSup // IP to Bus timeout suppress
// -- DO NOT EDIT ABOVE THIS LINE ------------------
);
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol parameters, do not add to or delete
parameter C_DWIDTH = 32;
// parameter C_NUM_CE = 8;
parameter C_NUM_CE = 16;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
output spi_clk;
output data_out;
output Radio1_cs;
output Radio2_cs;
output Radio3_cs;
output Radio4_cs;
output Dac1_cs;
output Dac2_cs;
output Dac3_cs;
output Dac4_cs;
output Radio1_SHDN;
output Radio1_TxEn;
output Radio1_RxEn;
output Radio1_RxHP;
input Radio1_LD;
output Radio1_24PA;
output Radio1_5PA;
output [0 : 1] Radio1_ANTSW;
output [0 : 2] Radio1_LED;
output Radio1_ADC_RX_DCS;
output Radio1_ADC_RX_DFS;
input Radio1_ADC_RX_OTRA;
input Radio1_ADC_RX_OTRB;
output Radio1_ADC_RX_PWDNA;
output Radio1_ADC_RX_PWDNB;
input [0 : 3] Radio1_DIPSW;
output Radio1_RSSI_ADC_CLAMP;
output Radio1_RSSI_ADC_HIZ;
input Radio1_RSSI_ADC_OTR;
output Radio1_RSSI_ADC_SLEEP;
input [0 : 9] Radio1_RSSI_ADC_D;
input Radio1_TX_DAC_PLL_LOCK;
output Radio1_TX_DAC_RESET;
input Radio1_RxHP_external;
output [0:5] Radio1_TxGain;
output Radio1_TxStart;
output Radio2_SHDN;
output Radio2_TxEn;
output Radio2_RxEn;
output Radio2_RxHP;
input Radio2_LD;
output Radio2_24PA;
output Radio2_5PA;
output [0 : 1] Radio2_ANTSW;
output [0 : 2] Radio2_LED;
output Radio2_ADC_RX_DCS;
output Radio2_ADC_RX_DFS;
input Radio2_ADC_RX_OTRA;
input Radio2_ADC_RX_OTRB;
output Radio2_ADC_RX_PWDNA;
output Radio2_ADC_RX_PWDNB;
input [0 : 3] Radio2_DIPSW;
output Radio2_RSSI_ADC_CLAMP;
output Radio2_RSSI_ADC_HIZ;
input Radio2_RSSI_ADC_OTR;
output Radio2_RSSI_ADC_SLEEP;
input [0 : 9] Radio2_RSSI_ADC_D;
input Radio2_TX_DAC_PLL_LOCK;
output Radio2_TX_DAC_RESET;
input Radio2_RxHP_external;
output [0:5] Radio2_TxGain;
output Radio2_TxStart;
output Radio3_SHDN;
output Radio3_TxEn;
output Radio3_RxEn;
output Radio3_RxHP;
input Radio3_LD;
output Radio3_24PA;
output Radio3_5PA;
output [0 : 1] Radio3_ANTSW;
output [0 : 2] Radio3_LED;
output Radio3_ADC_RX_DCS;
output Radio3_ADC_RX_DFS;
input Radio3_ADC_RX_OTRA;
input Radio3_ADC_RX_OTRB;
output Radio3_ADC_RX_PWDNA;
output Radio3_ADC_RX_PWDNB;
input [0 : 3] Radio3_DIPSW;
output Radio3_RSSI_ADC_CLAMP;
output Radio3_RSSI_ADC_HIZ;
input Radio3_RSSI_ADC_OTR;
output Radio3_RSSI_ADC_SLEEP;
input [0 : 9] Radio3_RSSI_ADC_D;
input Radio3_TX_DAC_PLL_LOCK;
output Radio3_TX_DAC_RESET;
input Radio3_RxHP_external;
output [0:5] Radio3_TxGain;
output Radio3_TxStart;
output Radio4_SHDN;
output Radio4_TxEn;
output Radio4_RxEn;
output Radio4_RxHP;
input Radio4_LD;
output Radio4_24PA;
output Radio4_5PA;
output [0 : 1] Radio4_ANTSW;
output [0 : 2] Radio4_LED;
output Radio4_ADC_RX_DCS;
output Radio4_ADC_RX_DFS;
input Radio4_ADC_RX_OTRA;
input Radio4_ADC_RX_OTRB;
output Radio4_ADC_RX_PWDNA;
output Radio4_ADC_RX_PWDNB;
input [0 : 3] Radio4_DIPSW;
output Radio4_RSSI_ADC_CLAMP;
output Radio4_RSSI_ADC_HIZ;
input Radio4_RSSI_ADC_OTR;
output Radio4_RSSI_ADC_SLEEP;
input [0 : 9] Radio4_RSSI_ADC_D;
input Radio4_TX_DAC_PLL_LOCK;
output Radio4_TX_DAC_RESET;
input Radio4_RxHP_external;
output [0:5] Radio4_TxGain;
output Radio4_TxStart;
// -- DO NOT EDIT BELOW THIS LINE --------------------
// -- Bus protocol ports, do not add to or delete
input Bus2IP_Clk;
input Bus2IP_Reset;
input [0 : C_DWIDTH-1] Bus2IP_Data;
input [0 : C_DWIDTH/8-1] Bus2IP_BE;
input [0 : C_NUM_CE-1] Bus2IP_RdCE;
input [0 : C_NUM_CE-1] Bus2IP_WrCE;
output [0 : C_DWIDTH-1] IP2Bus_Data;
output IP2Bus_Ack;
output IP2Bus_Retry;
output IP2Bus_Error;
output IP2Bus_ToutSup;
// -- DO NOT EDIT ABOVE THIS LINE --------------------
//----------------------------------------------------------------------------
// Implementation
//----------------------------------------------------------------------------
reg [0 : C_DWIDTH-1] slv_reg0;
reg [0 : C_DWIDTH-1] slv_reg1;
reg [0 : C_DWIDTH-1] slv_reg2;
reg [0 : C_DWIDTH-1] slv_reg3;
reg [0 : C_DWIDTH-1] slv_reg4;
reg [0 : C_DWIDTH-1] slv_reg5;
reg [0 : C_DWIDTH-1] slv_reg6;
reg [0 : C_DWIDTH-1] slv_reg7;
reg [0 : C_DWIDTH-1] slv_reg8;
reg [0 : C_DWIDTH-1] slv_reg9;
reg [0 : C_DWIDTH-1] slv_reg10;
reg [0 : C_DWIDTH-1] slv_reg11;
reg [0 : C_DWIDTH-1] slv_reg12;
reg [0 : C_DWIDTH-1] slv_reg13;
reg [0 : C_DWIDTH-1] slv_reg14;
reg [0 : C_DWIDTH-1] slv_reg15;
wire [0 : 15] slv_reg_write_select;
wire [0 : 15] slv_reg_read_select;
reg [0 : C_DWIDTH-1] slv_ip2bus_data;
wire slv_read_ack;
wire slv_write_ack;
integer byte_index, bit_index;
wire [7:0] ss_pad_o;
wire mytip;
wire [13:0] reg_ctrl;
wire [7:0] reg_ss;
wire reg_divider;
wire [17:0] reg_tx;
wire Radio1_PowerAmpEnable, Radio1_swTxEn, Radio1_sw24PAEn, Radio1_sw5PAEn;
wire Radio2_PowerAmpEnable, Radio2_swTxEn, Radio2_sw24PAEn, Radio2_sw5PAEn;
wire Radio3_PowerAmpEnable, Radio3_swTxEn, Radio3_sw24PAEn, Radio3_sw5PAEn;
wire Radio4_PowerAmpEnable, Radio4_swTxEn, Radio4_sw24PAEn, Radio4_sw5PAEn;
//Internal signals for calculating Tx gains
wire [0:5] Radio1_TargetTxGain, Radio2_TargetTxGain, Radio3_TargetTxGain, Radio4_TargetTxGain;
wire [0:3] Radio1_TxGainStep, Radio2_TxGainStep, Radio3_TxGainStep, Radio4_TxGainStep;
wire [0:3] Radio1_TxGainTimeStep, Radio2_TxGainTimeStep, Radio3_TxGainTimeStep, Radio4_TxGainTimeStep;
//Internal signals setting delays used to control Tx timing
wire [0:7] Radio1_GainRampThresh, Radio1_PAThresh, Radio1_TxEnThresh, Radio1_TxStartThresh;
wire [0:7] Radio2_GainRampThresh, Radio2_PAThresh, Radio2_TxEnThresh, Radio2_TxStartThresh;
wire [0:7] Radio3_GainRampThresh, Radio3_PAThresh, Radio3_TxEnThresh, Radio3_TxStartThresh;
wire [0:7] Radio4_GainRampThresh, Radio4_PAThresh, Radio4_TxEnThresh, Radio4_TxStartThresh;
assign Radio1_SHDN = ~slv_reg0[31];
assign Radio1_RxEn = slv_reg0[29];
assign Radio1_swTxEn = slv_reg0[30];
assign Radio1_RxHP = (slv_reg0[27])?slv_reg0[28]:Radio1_RxHP_external;
assign Radio1_sw24PAEn = slv_reg0[26];
assign Radio1_sw5PAEn = slv_reg0[25];
assign Radio1_24PA = ~(Radio1_sw24PAEn & Radio1_PowerAmpEnable); //active low output
assign Radio1_5PA = ~(Radio1_sw5PAEn & Radio1_PowerAmpEnable); //active low output
assign Radio1_ANTSW[0] = slv_reg0[23];
assign Radio1_ANTSW[1] = slv_reg0[24];
assign Radio1_ADC_RX_DCS = slv_reg0[22];
assign Radio1_LED[0] = Radio1_RxEn;
assign Radio1_LED[1] = Radio1_TxEn;
assign Radio1_LED[2] = ~Radio1_LD;
assign Radio1_ADC_RX_PWDNA = slv_reg0[18];
assign Radio1_ADC_RX_PWDNB = slv_reg0[17];
assign Radio1_RSSI_ADC_SLEEP = slv_reg0[16];
assign Radio1_TX_DAC_RESET = slv_reg0[10];
assign Radio1_ADC_RX_DFS = 1'b1; //slv_reg0[18];
assign Radio1_RSSI_ADC_CLAMP = 1'b0; //slv_reg0[9];
assign Radio1_RSSI_ADC_HIZ = 1'b0; //slv_reg0[8];
assign Radio2_SHDN = ~slv_reg1[31];
assign Radio2_swTxEn = slv_reg1[30];
assign Radio2_RxEn = slv_reg1[29];
assign Radio2_RxHP = (slv_reg1[27])?slv_reg1[28]:Radio2_RxHP_external;
assign Radio2_sw24PAEn = slv_reg1[26];
assign Radio2_sw5PAEn = slv_reg1[25];
assign Radio2_24PA = ~(Radio2_sw24PAEn & Radio2_PowerAmpEnable); //active low output
assign Radio2_5PA = ~(Radio2_sw5PAEn & Radio2_PowerAmpEnable); //active low output
assign Radio2_ANTSW[0] = slv_reg1[23];
assign Radio2_ANTSW[1] = slv_reg1[24];
assign Radio2_ADC_RX_DCS = slv_reg1[22];
assign Radio2_LED[0] = Radio2_RxEn;
assign Radio2_LED[1] = Radio2_TxEn;
assign Radio2_LED[2] = ~Radio2_LD;
assign Radio2_ADC_RX_PWDNA = slv_reg1[18];
assign Radio2_ADC_RX_PWDNB = slv_reg1[17];
assign Radio2_RSSI_ADC_SLEEP = slv_reg1[16];
assign Radio2_TX_DAC_RESET = slv_reg1[10];
assign Radio2_ADC_RX_DFS = 1'b1; //slv_reg1[18];
assign Radio2_RSSI_ADC_CLAMP = 1'b0; //slv_reg1[9];
assign Radio2_RSSI_ADC_HIZ = 1'b0; //slv_reg1[8];
assign Radio3_SHDN = ~slv_reg2[31];
assign Radio3_swTxEn = slv_reg2[30];
assign Radio3_RxEn = slv_reg2[29];
assign Radio3_RxHP = (slv_reg2[27])?slv_reg2[28]:Radio3_RxHP_external;
assign Radio3_sw24PAEn = slv_reg2[26];
assign Radio3_sw5PAEn = slv_reg2[25];
assign Radio3_24PA = ~(Radio3_sw24PAEn & Radio3_PowerAmpEnable); //active low output
assign Radio3_5PA = ~(Radio3_sw5PAEn & Radio3_PowerAmpEnable); //active low output
assign Radio3_ANTSW[0] = slv_reg2[23];
assign Radio3_ANTSW[1] = slv_reg2[24];
assign Radio3_ADC_RX_DCS = slv_reg2[22];
assign Radio3_LED[0] = Radio3_RxEn;
assign Radio3_LED[1] = Radio3_TxEn;
assign Radio3_LED[2] = ~Radio3_LD;
assign Radio3_ADC_RX_PWDNA = slv_reg2[18];
assign Radio3_ADC_RX_PWDNB = slv_reg2[17];
assign Radio3_RSSI_ADC_SLEEP = slv_reg2[16];
assign Radio3_TX_DAC_RESET = slv_reg2[10];
assign Radio3_ADC_RX_DFS = 1'b1; //slv_reg2[18];
assign Radio3_RSSI_ADC_CLAMP = 1'b0; //slv_reg2[9];
assign Radio3_RSSI_ADC_HIZ = 1'b0; //slv_reg2[8];
assign Radio4_SHDN = ~slv_reg3[31];
assign Radio4_swTxEn = slv_reg3[30];
assign Radio4_RxEn = slv_reg3[29];
assign Radio4_RxHP = (slv_reg3[27])?slv_reg3[28]:Radio4_RxHP_external;
assign Radio4_sw24PAEn = slv_reg3[26];
assign Radio4_sw5PAEn = slv_reg3[25];
assign Radio4_24PA = ~(Radio4_sw24PAEn & Radio4_PowerAmpEnable); //active low output
assign Radio4_5PA = ~(Radio4_sw5PAEn & Radio4_PowerAmpEnable); //active low output
assign Radio4_ANTSW[0] = slv_reg3[23];
assign Radio4_ANTSW[1] = slv_reg3[24];
assign Radio4_ADC_RX_DCS = slv_reg3[22];
assign Radio4_LED[0] = Radio4_RxEn;
assign Radio4_LED[1] = Radio4_TxEn;
assign Radio4_LED[2] = ~Radio4_LD;
assign Radio4_ADC_RX_PWDNA = slv_reg3[18];
assign Radio4_ADC_RX_PWDNB = slv_reg3[17];
assign Radio4_RSSI_ADC_SLEEP = slv_reg3[16];
assign Radio4_TX_DAC_RESET = slv_reg3[10];
assign Radio4_ADC_RX_DFS = 1'b1; //slv_reg3[18];
assign Radio4_RSSI_ADC_CLAMP = 1'b0; //slv_reg3[9];
assign Radio4_RSSI_ADC_HIZ = 1'b0; //slv_reg3[8];
assign Radio1_cs = ss_pad_o[0];
assign Radio2_cs = ss_pad_o[1];
assign Radio3_cs = ss_pad_o[2];
assign Radio4_cs = ss_pad_o[3];
assign Dac1_cs = ss_pad_o[4];
assign Dac2_cs = ss_pad_o[5];
assign Dac3_cs = ss_pad_o[6];
assign Dac4_cs = ss_pad_o[7];
assign reg_ctrl = slv_reg4[18:31];
assign reg_divider = slv_reg5[31];
assign reg_ss = slv_reg6[24:31];
assign reg_tx = slv_reg7[14:31];
assign
slv_reg_write_select = Bus2IP_WrCE[0:15],
slv_reg_read_select = Bus2IP_RdCE[0:15],
slv_write_ack = Bus2IP_WrCE[0] || Bus2IP_WrCE[1] || Bus2IP_WrCE[2] || Bus2IP_WrCE[3] || Bus2IP_WrCE[4] || Bus2IP_WrCE[5] || Bus2IP_WrCE[6] || Bus2IP_WrCE[7] || Bus2IP_WrCE[8] || Bus2IP_WrCE[9] || Bus2IP_WrCE[10] || Bus2IP_WrCE[11] || Bus2IP_WrCE[12] || Bus2IP_WrCE[13] || Bus2IP_WrCE[14] || Bus2IP_WrCE[15],
slv_read_ack = Bus2IP_RdCE[0] || Bus2IP_RdCE[1] || Bus2IP_RdCE[2] || Bus2IP_RdCE[3] || Bus2IP_RdCE[4] || Bus2IP_RdCE[5] || Bus2IP_RdCE[6] || Bus2IP_RdCE[7] || Bus2IP_RdCE[8] || Bus2IP_RdCE[9] || Bus2IP_RdCE[10] || Bus2IP_RdCE[11] || Bus2IP_RdCE[12] || Bus2IP_RdCE[13] || Bus2IP_RdCE[14] || Bus2IP_RdCE[15];
assign IP2Bus_Data = slv_ip2bus_data;
assign IP2Bus_Ack = slv_write_ack || slv_read_ack;
assign IP2Bus_Error = 0;
assign IP2Bus_Retry = 0;
assign IP2Bus_ToutSup = 0;
// implement slave model register(s)
always @( posedge Bus2IP_Clk )
begin: SLAVE_REG_WRITE_PROC
if ( Bus2IP_Reset == 1 )
begin
slv_reg0 <= 0;
slv_reg1 <= 0;
slv_reg2 <= 0;
slv_reg3 <= 0;
slv_reg4 <= 0;
slv_reg5 <= 0;
slv_reg6 <= 0;
slv_reg7 <= 0;
slv_reg8 <= {14'h3fff, 22'h0}; //Gain increment, targets & delays all default to max values
slv_reg9 <= {14'h3fff, 22'h0};
slv_reg10 <= {14'h3fff, 22'h0};
slv_reg11 <= {14'h3fff, 22'h0};
slv_reg12 <= 0;
slv_reg13 <= 0;
slv_reg14 <= 0;
slv_reg15 <= 0;
end
else
case ( slv_reg_write_select )
16'b1000000000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg0[bit_index] <= Bus2IP_Data[bit_index];
16'b0100000000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg1[bit_index] <= Bus2IP_Data[bit_index];
16'b0010000000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg2[bit_index] <= Bus2IP_Data[bit_index];
16'b0001000000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg3[bit_index] <= Bus2IP_Data[bit_index];
16'b0000100000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg4[bit_index] <= Bus2IP_Data[bit_index];
16'b0000010000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg5[bit_index] <= Bus2IP_Data[bit_index];
16'b0000001000000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg6[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000100000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg7[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000010000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg8[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000001000000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg9[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000100000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg10[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000010000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg11[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000001000 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg12[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000100 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg13[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000010 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg14[bit_index] <= Bus2IP_Data[bit_index];
16'b0000000000000001 :
for ( byte_index = 0; byte_index <= (C_DWIDTH/8)-1; byte_index = byte_index+1 )
if ( Bus2IP_BE[byte_index] == 1 )
for ( bit_index = byte_index*8; bit_index <= byte_index*8+7; bit_index = bit_index+1 )
slv_reg15[bit_index] <= Bus2IP_Data[bit_index];
default : ;
endcase
end // SLAVE_REG_WRITE_PROC
// implement slave model register read mux
always @( slv_reg_read_select or slv_reg0 or slv_reg1 or slv_reg2 or slv_reg3 or slv_reg4 or slv_reg5 or slv_reg6 or slv_reg7 or slv_reg8 or slv_reg9 or slv_reg10 or slv_reg11 or slv_reg12 or slv_reg13 or slv_reg14 or slv_reg15
or Radio1_RSSI_ADC_D or Radio1_TX_DAC_PLL_LOCK or Radio1_RSSI_ADC_OTR or Radio1_DIPSW or Radio1_ADC_RX_OTRB or Radio1_ADC_RX_OTRA or Radio1_ADC_RX_DFS or Radio1_LD
or Radio2_RSSI_ADC_D or Radio2_TX_DAC_PLL_LOCK or Radio2_RSSI_ADC_OTR or Radio2_DIPSW or Radio2_ADC_RX_OTRB or Radio2_ADC_RX_OTRA or Radio2_ADC_RX_DFS or Radio2_LD
or Radio3_RSSI_ADC_D or Radio3_TX_DAC_PLL_LOCK or Radio3_RSSI_ADC_OTR or Radio3_DIPSW or Radio3_ADC_RX_OTRB or Radio3_ADC_RX_OTRA or Radio3_ADC_RX_DFS or Radio3_LD
or Radio4_RSSI_ADC_D or Radio4_TX_DAC_PLL_LOCK or Radio4_RSSI_ADC_OTR or Radio4_DIPSW or Radio4_ADC_RX_OTRB or Radio4_ADC_RX_OTRA or Radio4_ADC_RX_DFS or Radio4_LD
or mytip )
begin: SLAVE_REG_READ_PROC
case ( slv_reg_read_select )
16'b1000000000000000 : slv_ip2bus_data <= {Radio1_RSSI_ADC_D[0:9],
slv_reg0[10],
Radio1_TX_DAC_PLL_LOCK,
Radio1_RSSI_ADC_OTR,
Radio1_DIPSW[3],
Radio1_DIPSW[2],
Radio1_DIPSW[1],
Radio1_DIPSW[0],
slv_reg0[17:18],
Radio1_ADC_RX_OTRB,
Radio1_ADC_RX_OTRA,
Radio1_ADC_RX_DFS,
slv_reg0[22:26],
Radio1_LD,
slv_reg0[28:31]};
16'b0100000000000000 : slv_ip2bus_data <= {Radio2_RSSI_ADC_D[0:9],
slv_reg1[10],
Radio2_TX_DAC_PLL_LOCK,
Radio2_RSSI_ADC_OTR,
Radio2_DIPSW[3],
Radio2_DIPSW[2],
Radio2_DIPSW[1],
Radio2_DIPSW[0],
slv_reg1[17:18],
Radio2_ADC_RX_OTRB,
Radio2_ADC_RX_OTRA,
Radio2_ADC_RX_DFS,
slv_reg1[22:26],
Radio2_LD,
slv_reg1[28:31]};
16'b0010000000000000 : slv_ip2bus_data <= {Radio3_RSSI_ADC_D[0:9],
slv_reg2[10],
Radio3_TX_DAC_PLL_LOCK,
Radio3_RSSI_ADC_OTR,
Radio3_DIPSW[3],
Radio3_DIPSW[2],
Radio3_DIPSW[1],
Radio3_DIPSW[0],
slv_reg2[17:18],
Radio3_ADC_RX_OTRB,
Radio3_ADC_RX_OTRA,
Radio3_ADC_RX_DFS,
slv_reg2[22:26],
Radio3_LD,
slv_reg2[28:31]};
16'b0001000000000000 : slv_ip2bus_data <= {Radio4_RSSI_ADC_D[0:9],
slv_reg3[10],
Radio4_TX_DAC_PLL_LOCK,
Radio4_RSSI_ADC_OTR,
Radio4_DIPSW[3],
Radio4_DIPSW[2],
Radio4_DIPSW[1],
Radio4_DIPSW[0],
slv_reg3[17:18],
Radio4_ADC_RX_OTRB,
Radio4_ADC_RX_OTRA,
Radio4_ADC_RX_DFS,
slv_reg3[22:26],
Radio4_LD,
slv_reg3[28:31]};
16'b0000100000000000 : slv_ip2bus_data <= {slv_reg4[0:22], mytip, slv_reg4[24:31]};
16'b0000010000000000 : slv_ip2bus_data <= slv_reg5;
16'b0000001000000000 : slv_ip2bus_data <= slv_reg6;
16'b0000000100000000 : slv_ip2bus_data <= slv_reg7;
16'b0000000010000000 : slv_ip2bus_data <= slv_reg8;
16'b0000000001000000 : slv_ip2bus_data <= slv_reg9;
16'b0000000000100000 : slv_ip2bus_data <= slv_reg10;
16'b0000000000010000 : slv_ip2bus_data <= slv_reg11;
16'b0000000000001000 : slv_ip2bus_data <= slv_reg12;
16'b0000000000000100 : slv_ip2bus_data <= slv_reg13;
16'b0000000000000010 : slv_ip2bus_data <= slv_reg14;
16'b0000000000000001 : slv_ip2bus_data <= slv_reg15;
default : slv_ip2bus_data <= 0;
endcase
end // SLAVE_REG_READ_PROC
//Instantiate the SPI controller top-level
spi_top spi_top(
.opb_clk_i(Bus2IP_Clk),
.opb_rst_i(Bus2IP_Reset),
.reg_ctrl(reg_ctrl),
.reg_ss(reg_ss),
.reg_divider(reg_divider),
.reg_tx(reg_tx),
.ctrlwrite(Bus2IP_WrCE[4]),
.busval(Bus2IP_Data[23]),
.go(mytip),
.ss_pad_o(ss_pad_o),
.sclk_pad_o(spi_clk),
.mosi_pad_o(data_out)
);
//Instantiate four copies of the mode which controls the timing
// of various signals during each Tx cycle
radio_controller_TxTiming Radio1_TxTiming (
.clk(Bus2IP_Clk),
.reset(Bus2IP_Reset),
.Tx_swEnable(Radio1_swTxEn),
.TxGain_target(Radio1_TargetTxGain),
.TxGain_rampGainStep(Radio1_TxGainStep),
.TxGain_rampTimeStep(Radio1_TxGainTimeStep),
.dly_hwTxEn(Radio1_TxEnThresh),
.dly_TxStart(Radio1_TxStartThresh),
.dly_PowerAmpEn(Radio1_PAThresh),
.dly_RampGain(Radio1_GainRampThresh),
.hw_TxEn(Radio1_TxEn),
.hw_TxGain(Radio1_TxGain),
.hw_PAEn(Radio1_PowerAmpEnable),
.hw_TxStart(Radio1_TxStart)
);
radio_controller_TxTiming Radio2_TxTiming (
.clk(Bus2IP_Clk),
.reset(Bus2IP_Reset),
.Tx_swEnable(Radio2_swTxEn),
.TxGain_target(Radio2_TargetTxGain),
.TxGain_rampGainStep(Radio2_TxGainStep),
.TxGain_rampTimeStep(Radio2_TxGainTimeStep),
.dly_hwTxEn(Radio2_TxEnThresh),
.dly_TxStart(Radio2_TxStartThresh),
.dly_PowerAmpEn(Radio2_PAThresh),
.dly_RampGain(Radio2_GainRampThresh),
.hw_TxEn(Radio2_TxEn),
.hw_TxGain(Radio2_TxGain),
.hw_PAEn(Radio2_PowerAmpEnable),
.hw_TxStart(Radio2_TxStart)
);
radio_controller_TxTiming Radio3_TxTiming (
.clk(Bus2IP_Clk),
.reset(Bus2IP_Reset),
.Tx_swEnable(Radio3_swTxEn),
.TxGain_target(Radio3_TargetTxGain),
.TxGain_rampGainStep(Radio3_TxGainStep),
.TxGain_rampTimeStep(Radio3_TxGainTimeStep),
.dly_hwTxEn(Radio3_TxEnThresh),
.dly_TxStart(Radio3_TxStartThresh),
.dly_PowerAmpEn(Radio3_PAThresh),
.dly_RampGain(Radio3_GainRampThresh),
.hw_TxEn(Radio3_TxEn),
.hw_TxGain(Radio3_TxGain),
.hw_PAEn(Radio3_PowerAmpEnable),
.hw_TxStart(Radio3_TxStart)
);
radio_controller_TxTiming Radio4_TxTiming (
.clk(Bus2IP_Clk),
.reset(Bus2IP_Reset),
.Tx_swEnable(Radio4_swTxEn),
.TxGain_target(Radio4_TargetTxGain),
.TxGain_rampGainStep(Radio4_TxGainStep),
.TxGain_rampTimeStep(Radio4_TxGainTimeStep),
.dly_hwTxEn(Radio4_TxEnThresh),
.dly_TxStart(Radio4_TxStartThresh),
.dly_PowerAmpEn(Radio4_PAThresh),
.dly_RampGain(Radio4_GainRampThresh),
.hw_TxEn(Radio4_TxEn),
.hw_TxGain(Radio4_TxGain),
.hw_PAEn(Radio4_PowerAmpEnable),
.hw_TxStart(Radio4_TxStart)
);
//Read the user register for each radio's programmed target Tx gain
assign Radio1_TargetTxGain = slv_reg8[0:5];
assign Radio2_TargetTxGain = slv_reg9[0:5];
assign Radio3_TargetTxGain = slv_reg10[0:5];
assign Radio4_TargetTxGain = slv_reg11[0:5];
//Read the user regsiter for each radio's programmed Tx gain ramp increment
assign Radio1_TxGainStep = slv_reg8[6:9];
assign Radio2_TxGainStep = slv_reg9[6:9];
assign Radio3_TxGainStep = slv_reg10[6:9];
assign Radio4_TxGainStep = slv_reg11[6:9];
//Read the user register for each radio's programmed delay between gain steps
assign Radio1_TxGainTimeStep = slv_reg8[10:13];
assign Radio2_TxGainTimeStep = slv_reg9[10:13];
assign Radio3_TxGainTimeStep = slv_reg10[10:13];
assign Radio4_TxGainTimeStep = slv_reg11[10:13];
//slv_reg{8,9,10,11}[14:31] available for future use
//Read the user registers for the the delays before each Tx event
assign Radio1_GainRampThresh = slv_reg12[0:7];
assign Radio2_GainRampThresh = slv_reg13[0:7];
assign Radio3_GainRampThresh = slv_reg14[0:7];
assign Radio4_GainRampThresh = slv_reg15[0:7];
assign Radio1_PAThresh = slv_reg12[8:15];
assign Radio2_PAThresh = slv_reg13[8:15];
assign Radio3_PAThresh = slv_reg14[8:15];
assign Radio4_PAThresh = slv_reg15[8:15];
assign Radio1_TxEnThresh = slv_reg12[16:23];
assign Radio2_TxEnThresh = slv_reg13[16:23];
assign Radio3_TxEnThresh = slv_reg14[16:23];
assign Radio4_TxEnThresh = slv_reg15[16:23];
assign Radio1_TxStartThresh = slv_reg12[24:31];
assign Radio2_TxStartThresh = slv_reg13[24:31];
assign Radio3_TxStartThresh = slv_reg14[24:31];
assign Radio4_TxStartThresh = slv_reg15[24:31];
endmodule
|
/*
Copyright 2018 Nuclei System Technology, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
//=====================================================================
//
// Designer : Bob Hu
//
// Description:
// The top level module of otp
//
// ====================================================================
module sirv_otp_top(
input clk,
input rst_n,
input i_icb_cmd_valid,
output i_icb_cmd_ready,
input [32-1:0] i_icb_cmd_addr,
input i_icb_cmd_read,
input [32-1:0] i_icb_cmd_wdata,
output i_icb_rsp_valid,
input i_icb_rsp_ready,
output [32-1:0] i_icb_rsp_rdata,
input f_icb_cmd_valid,
output f_icb_cmd_ready,
input [32-1:0] f_icb_cmd_addr,
input f_icb_cmd_read,
input [32-1:0] f_icb_cmd_wdata,
output f_icb_rsp_valid,
input f_icb_rsp_ready,
output [32-1:0] f_icb_rsp_rdata
);
assign i_icb_cmd_ready = 1'b0;
assign i_icb_rsp_valid = 1'b0;
assign i_icb_rsp_rdata = 32'b0;
assign f_icb_cmd_ready = 1'b0;
assign f_icb_rsp_valid = 1'b0;
assign f_icb_rsp_rdata = 32'b0;
// In FPGA platform this module is just an empty wrapper
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Engineer: Ryan
//
// Create Date: 06/07/2017
// Module Name: ClkDiv_20Hz
// Project Name: Joystick_Controller
// Target Devices: ICEStick
// Tool versions: iCEcube2
// Description: Converts input 12 MHz clock signal to a 20Hz "update system" clock signal
//////////////////////////////////////////////////////////////////////////////////
// ==============================================================================
// Define Module
// ==============================================================================
module ClkDiv_20Hz(
CLK, // 12MHz onbaord clock
RST, // Reset
CLKOUT, // New clock output
CLKOUTn
);
// ===========================================================================
// Port Declarations
// ===========================================================================
input CLK;
input RST;
output CLKOUT;
output CLKOUTn;
// ===========================================================================
// Parameters, Regsiters, and Wires
// ===========================================================================
// Output register
reg CLKOUT = 1'b1;
// Value to toggle output clock at
parameter cntEndVal = 19'h493E0;
// Current count
reg [18:0] clkCount = 19'h00000;
// ===========================================================================
// Implementation
// ===========================================================================
assign CLKOUTn = ~CLKOUT;
//-------------------------------------------------
// 20Hz Clock Divider Generates timing to initiate Send/Receive
//-------------------------------------------------
always @(posedge CLK) begin
// Reset clock
if(RST == 1'b1) begin
CLKOUT <= 1'b0;
clkCount <= 0;
end
// Count/toggle normally
else begin
if(clkCount == cntEndVal) begin
CLKOUT <= ~CLKOUT;
clkCount <= 0;
end
else begin
clkCount <= clkCount + 1'b1;
end
end
end
endmodule
|
/***************************************************************************************************
** fpga_nes/hw/src/cmn/block_ram/block_ram.v
*
* Copyright (c) 2012, Brian Bennett
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification, are permitted
* provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice, this list of conditions
* and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice, this list of
* conditions and the following disclaimer in the documentation and/or other materials provided
* with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
* FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY
* WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* Various generic, inferred block ram descriptors.
***************************************************************************************************/
// Dual port RAM with synchronous read. Modified version of listing 12.4 in "FPGA Prototyping by
// Verilog Examples," itself a modified version of XST 8.11 v_rams_11.
module dual_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [ADDR_WIDTH-1:0] addr_b,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a,
output wire [DATA_WIDTH-1:0] dout_b
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr_a;
reg [ADDR_WIDTH-1:0] q_addr_b;
always @(posedge clk)
begin
if (we)
ram[addr_a] <= din_a;
q_addr_a <= addr_a;
q_addr_b <= addr_b;
end
assign dout_a = ram[q_addr_a];
assign dout_b = ram[q_addr_b];
endmodule
// Single port RAM with synchronous read.
module single_port_ram_sync
#(
parameter ADDR_WIDTH = 6,
parameter DATA_WIDTH = 8
)
(
input wire clk,
input wire we,
input wire [ADDR_WIDTH-1:0] addr_a,
input wire [DATA_WIDTH-1:0] din_a,
output wire [DATA_WIDTH-1:0] dout_a
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] q_addr_a;
always @(posedge clk)
begin
if (we)
ram[addr_a] <= din_a;
q_addr_a <= addr_a;
end
assign dout_a = ram[q_addr_a];
endmodule
|
`include "hglobal.v"
`default_nettype none
module debouncer
(
`NS_DECLARE_GLB_CHNL(gch),
input bouncing,
output steady
);
parameter TOT_CKS = 1; //old val 250000
reg [0:0] rg_dbn_rdy = 0;
reg [$clog2(TOT_CKS):0] cnt_cks = 0;
reg rg_stdy = 1'b0;
always @(posedge gch_clk)
begin
if(gch_reset) begin
rg_dbn_rdy <= 0;
end
if(! gch_reset && ! rg_dbn_rdy) begin
rg_dbn_rdy <= ! rg_dbn_rdy;
cnt_cks <= 0;
rg_stdy <= 1'b0;
end
if(! gch_reset && rg_dbn_rdy) begin
// Switch input is different than internal switch value, so an input is
// changing. Increase the counter until it is stable for enough time.
if (bouncing !== rg_stdy && cnt_cks < TOT_CKS) begin
cnt_cks <= cnt_cks + 1;
end
// End of counter reached, switch is stable, register it, restart counter
else if (cnt_cks == TOT_CKS)
begin
rg_stdy <= bouncing;
cnt_cks <= 0;
end
// Switches are the same state, restart the counter
else
begin
cnt_cks <= 0;
end
end
end
assign gch_ready = rg_dbn_rdy;
// Assign internal register to output (debounced!)
assign steady = rg_stdy;
endmodule
|
module last_row_routing(
// input clk,
input [fpga_width*wire_width*12-1:0] brbselect,
inout [wire_width-1:0] left, right,
inout [wire_width*fpga_width-1:0] top, bottom
);
parameter wire_width = 3;
parameter fpga_width = 5;
wire [wire_width-1:0] brb[fpga_width-1:0];
genvar x;
generate
for (x = 0; x < fpga_width-1; x = x + 1) begin
localparam brb_base = x*wire_width*12;
localparam tb_base = x*wire_width;
if (x == 0) begin
bidir_routing_block #(wire_width) brb(
.select(brbselect[brb_base+wire_width*12-1:brb_base]),
.left(left),
.right(brb[x]),
.top(top[tb_base+wire_width-1:tb_base]),
.bottom(bottom[tb_base+wire_width-1:tb_base])
);
end
else if (x == fpga_width-2) begin
bidir_routing_block #(wire_width) brb(
.select(brbselect[brb_base+wire_width*12-1:brb_base]),
.left(brb[x]),
.right(right),
.top(top[tb_base+wire_width-1:tb_base]),
.bottom(bottom[tb_base+wire_width-1:tb_base])
);
end
else begin
bidir_routing_block #(wire_width) brb(
.select(brbselect[brb_base+wire_width*12-1:brb_base]),
.left(brb[x-1]),
.right(brb[x]),
.top(top[tb_base+wire_width-1:tb_base]),
.bottom(bottom[tb_base+wire_width-1:tb_base])
);
end
end
endgenerate
/*bidir_routing_block brb1(brbselect[35:0], left, brb1_2, top[2:0], bottom[2:0]);
bidir_routing_block brb2(brbselect[71:36], brb1_2, brb2_3, top[5:3], bottom[5:3]);
bidir_routing_block brb3(brbselect[107:72], brb2_3, brb3_4, top[8:6], bottom[8:6]);
bidir_routing_block brb4(brbselect[143:108], brb3_4, brb4_5, top[11:9], bottom[11:9]);
bidir_routing_block brb5(brbselect[179:144], brb4_5, right, top[14:12], bottom[14:12]);*/
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Posted Packet Builder module. This module takes the
// length info from the Posted Packet Slicer, and requests a tag from
// the Tag Generator and uses that info to build a posted memory write header
// which it writes into a FIFO
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module posted_pkt_builder(
input clk,
input rst,
input [15:0] req_id, //from pcie block
//to/from posted_pkt_slicer
input posted_fifo_full,
input go,
output reg ack,
input [63:0] dmawad,
input [9:0] length,
//to posted_pkt_header_fifo
output reg [63:0] header_data_out,
output reg header_data_wren
);
//State machine states
localparam IDLE = 4'h0;
localparam HEAD1 = 4'h1;
localparam HEAD2 = 4'h2;
localparam WAIT_FOR_GO_DEASSERT = 4'h3;
//parameters used to define fixed header fields
localparam rsvd = 1'b0; //reserved and unused header fields to zero
localparam MWr = 5'b00000; //format for memory write header
localparam TC = 3'b000; //traffic class 0
localparam TD = 1'b0; //digest bit always 0
localparam EP = 1'b0; //poisoned bit always 0
localparam ATTR = 2'b00; //no snoop or relaxed-ordering
localparam LastBE = 4'b1111; //LastBE is always asserted since all transfers
//are on 128B boundaries and are always at least
//128B long
localparam FirstBE = 4'b1111;//FirstBE is always asserted since all transfers
//are on 128B boundaries
wire [1:0] fmt;
reg [3:0] state;
reg [63:0] dmawad_reg;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
//if the upper DWord of the destination address is zero
//than make the format of the packet header 3DW; otherwise 4DW
assign fmt[1:0] = (dmawad_reg[63:32] == 0) ? 2'b10 : 2'b11;
//if the posted_pkt_slicer asserts "go" then register the dma write params
always@(posedge clk)begin
if(rst_reg)begin
dmawad_reg[63:0] <= 0;
end else if(go)begin
dmawad_reg <= dmawad;
end
end
// State machine
// Builds headers for posted memory writes
// Writes them into a FIFO
always @ (posedge clk) begin
if (rst_reg) begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end else begin
case (state)
IDLE : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
if(go & ~posted_fifo_full) // Jiansong: prevent p_hdr_fifo overflow
state<= HEAD1;
else
state<= IDLE;
end
HEAD1 : begin
//write the first 64-bits of a posted header into the
//posted fifo
header_data_out <= {rsvd,fmt[1:0],MWr,rsvd,TC,rsvd,rsvd,rsvd,rsvd,
TD,EP,ATTR,rsvd,rsvd,length[9:0],req_id[15:0],
8'b00000000 ,LastBE,FirstBE};
ack <= 0;
header_data_wren <= 1'b1;
state <= HEAD2;
end
HEAD2 : begin
//write the next 32 or 64 bits of a posted header to the
//posted header fifo (32 if 3DW - 64 if 4DW header)
header_data_out <= (fmt[0]==1'b1)
? {dmawad_reg[63:2],2'b00}
: {dmawad_reg[31:2], 2'b00, dmawad_reg[63:32]};
header_data_wren <= 1'b1;
ack <= 1'b1; //acknowledge to the posted_packet_slicer that
//the packet has been queued up for transmission
state <= WAIT_FOR_GO_DEASSERT;
end
WAIT_FOR_GO_DEASSERT: begin
//ack causes "go" to deassert but we need to give the
//posted_pkt_slicer a chance to deassert "go" before returning
//to IDLE
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
default : begin
header_data_out <= 0;
header_data_wren <= 1'b0;
ack <= 1'b0;
state <= IDLE;
end
endcase
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V
`define SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N;
// Local signals
wire not0_out ;
wire or0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X, not0_out, C, B, A);
buf buf0 (X , or0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_FUNCTIONAL_V |
/*
* Copyright (c) 2015, Arch Laboratory
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
module to_sdram
(
input wire clk_sys,
input wire rst,
input wire ao486_rst,
// input pc_bus_sdram
input wire [31:0] pc_bus_sdram_address,
input wire [3:0] pc_bus_sdram_byteenable,
input wire pc_bus_sdram_read,
output wire [31:0] pc_bus_sdram_readdata,
input wire pc_bus_sdram_write,
input wire [31:0] pc_bus_sdram_writedata,
output wire pc_bus_sdram_waitrequest,
output wire pc_bus_sdram_readdatavalid,
input wire [2:0] pc_bus_sdram_burstcount,
// input driver_sd_avm
input wire [31:0] driver_sd_avm_address,
input wire driver_sd_avm_read,
output wire [31:0] driver_sd_avm_readdata,
input wire driver_sd_avm_write,
input wire [31:0] driver_sd_avm_writedata,
output wire driver_sd_avm_waitrequest,
output wire driver_sd_avm_readdatavalid,
// output sdram_mem
output wire [24:0] sdram_address,
output wire [3:0] sdram_byteenable,
output wire sdram_read,
input wire [31:0] sdram_readdata,
output wire sdram_write,
output wire [31:0] sdram_writedata,
input wire sdram_waitrequest,
input wire sdram_readdatavalid,
input wire sdram_chipselect
);
wire [31:0] burst_converted_address;
wire burst_converted_write;
wire [31:0] burst_converted_writedata;
wire burst_converted_read;
wire [31:0] burst_converted_readdata;
wire burst_converted_readdatavalid;
wire [3:0] burst_converted_byteenable;
wire burst_converted_waitrequest;
burst_converter #(.IADDR(32), .OADDR(27))
burst_converter (
.clk_sys (clk_sys),
.rst (rst),
.addr_in (pc_bus_sdram_address),
.write_in (pc_bus_sdram_write),
.writedata_in (pc_bus_sdram_writedata),
.read_in (pc_bus_sdram_read),
.readdata_out (pc_bus_sdram_readdata),
.readdatavalid_out (pc_bus_sdram_readdatavalid),
.byteenable_in (pc_bus_sdram_byteenable),
.burstcount_in (pc_bus_sdram_burstcount),
.waitrequest_out (pc_bus_sdram_waitrequest),
.addr_out (burst_converted_address),
.write_out (burst_converted_write),
.writedata_out (burst_converted_writedata),
.read_out (burst_converted_read),
.readdata_in (burst_converted_readdata),
.readdatavalid_in (burst_converted_readdatavalid),
.byteenable_out (burst_converted_byteenable),
.waitrequest_in (burst_converted_waitrequest)
);
assign sdram_address = (~ao486_rst) ? burst_converted_address[26:2] : driver_sd_avm_address[26:2];
assign sdram_byteenable = (~ao486_rst) ? burst_converted_byteenable : 4'b1111;
assign sdram_read = (~ao486_rst) ? burst_converted_read : (driver_sd_avm_read && driver_sd_avm_address[27]);
assign sdram_write = (~ao486_rst) ? burst_converted_write : (driver_sd_avm_write && driver_sd_avm_address[27]);
assign sdram_writedata = (~ao486_rst) ? burst_converted_writedata : driver_sd_avm_writedata;
assign burst_converted_readdata = (~ao486_rst) ? sdram_readdata : 0;
assign burst_converted_readdatavalid = (~ao486_rst) ? sdram_readdatavalid : 0;
assign burst_converted_waitrequest = (~ao486_rst) ? sdram_waitrequest : 0;
assign driver_sd_avm_readdata = (ao486_rst) ? sdram_readdata : 0;
assign driver_sd_avm_readdatavalid = (ao486_rst) ? sdram_readdatavalid : 0;
assign driver_sd_avm_waitrequest = (ao486_rst) ? sdram_waitrequest : 0;
endmodule
|
// (C) 2001-2015 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// ***************************************************************************
// File name: write_datapath.v
// ***************************************************************************
`timescale 1 ps / 1 ps
(* altera_attribute = "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF" *)
module nios_mem_if_ddr2_emif_0_p0_write_datapath(
pll_afi_clk,
reset_n,
force_oct_off,
afi_dqs_en,
phy_ddio_oct_ena,
afi_wdata,
afi_wdata_valid,
afi_dm,
phy_ddio_dq,
phy_ddio_dqs_en,
phy_ddio_wrdata_en,
phy_ddio_wrdata_mask,
seq_num_write_fr_cycle_shifts
);
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter AFI_ADDRESS_WIDTH = "";
parameter AFI_DATA_MASK_WIDTH = "";
parameter AFI_CONTROL_WIDTH = "";
parameter AFI_DATA_WIDTH = "";
parameter AFI_DQS_WIDTH = "";
parameter NUM_WRITE_PATH_FLOP_STAGES = "";
parameter NUM_WRITE_FR_CYCLE_SHIFTS = "";
localparam RATE_MULT = 2;
localparam DQ_GROUP_WIDTH = MEM_DQ_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam DM_GROUP_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
input pll_afi_clk;
input reset_n;
input [AFI_DQS_WIDTH-1:0] force_oct_off;
input [AFI_DQS_WIDTH-1:0] afi_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena;
input [AFI_DATA_WIDTH-1:0] afi_wdata;
input [AFI_DQS_WIDTH-1:0] afi_wdata_valid;
input [AFI_DATA_MASK_WIDTH-1:0] afi_dm;
output [AFI_DATA_WIDTH-1:0] phy_ddio_dq;
output [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en;
output [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en;
output [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask;
input [MEM_WRITE_DQS_WIDTH * 2 - 1:0] seq_num_write_fr_cycle_shifts;
wire [AFI_DQS_WIDTH-1:0] oct_ena_source = afi_dqs_en;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_oct_ena_pre_shift;
wire [AFI_DATA_WIDTH-1:0] phy_ddio_dq_pre_shift;
wire [AFI_DQS_WIDTH-1:0] phy_ddio_wrdata_en_pre_shift;
wire [AFI_DATA_MASK_WIDTH-1:0] phy_ddio_wrdata_mask_pre_shift;
generate
genvar stage;
if (NUM_WRITE_PATH_FLOP_STAGES == 0)
begin
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_extender oct_ena_source_extender(
.clk (pll_afi_clk),
.extend_by (2'b10),
.reset_n (1'b1),
.datain (oct_ena_source),
.dataout (oct_ena_source_extended)
);
defparam oct_ena_source_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
assign phy_ddio_oct_ena_pre_shift = ~oct_ena_source_extended & ~force_oct_off;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter afi_dqs_en_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_dqs_en),
.dataout (phy_ddio_dqs_en_pre_shift)
);
defparam afi_dqs_en_shifter.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter afi_wdata_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_wdata),
.dataout (phy_ddio_dq_pre_shift)
);
defparam afi_wdata_shifter.DATA_WIDTH = (MEM_DQ_WIDTH * 2);
nios_mem_if_ddr2_emif_0_p0_fr_cycle_extender afi_wdata_valid_extender(
.clk (pll_afi_clk),
.extend_by (2'b10),
.reset_n (1'b1),
.datain (afi_wdata_valid),
.dataout (phy_ddio_wrdata_en_pre_shift)
);
defparam afi_wdata_valid_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter afi_dm_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (afi_dm),
.dataout (phy_ddio_wrdata_mask_pre_shift)
);
defparam afi_dm_shifter.DATA_WIDTH = (MEM_DM_WIDTH * 2);
end
else
begin
reg [AFI_DATA_WIDTH-1:0] afi_wdata_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
reg [AFI_DQS_WIDTH-1:0] afi_wdata_valid_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] oct_ena_source_r [NUM_WRITE_PATH_FLOP_STAGES-1:0] /* synthesis dont_merge */;
reg [AFI_DQS_WIDTH-1:0] afi_dqs_en_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
// phy_ddio_wrdata_mask is tied low during calibration
// the purpose of the assignment is to avoid Quartus from connecting the signal to the sclr pin of the flop
// sclr pin is very slow and causes timing failures
(* altera_attribute = {"-name ALLOW_SYNCH_CTRL_USAGE OFF"}*) reg [AFI_DATA_MASK_WIDTH-1:0] afi_dm_r [NUM_WRITE_PATH_FLOP_STAGES-1:0];
for (stage = 0; stage < NUM_WRITE_PATH_FLOP_STAGES; stage = stage + 1)
begin : stage_gen
always @(posedge pll_afi_clk)
begin
oct_ena_source_r[stage] <= (stage == 0) ? oct_ena_source : oct_ena_source_r[stage-1];
afi_wdata_r[stage] <= (stage == 0) ? afi_wdata : afi_wdata_r[stage-1];
afi_wdata_valid_r[stage] <= (stage == 0) ? afi_wdata_valid : afi_wdata_valid_r[stage-1];
afi_dm_r[stage] <= (stage == 0) ? afi_dm : afi_dm_r[stage-1];
afi_dqs_en_r[stage] <= (stage == 0) ? afi_dqs_en : afi_dqs_en_r[stage-1];
end
end
assign phy_ddio_dq_pre_shift = afi_wdata_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_en_pre_shift = afi_wdata_valid_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_wrdata_mask_pre_shift = afi_dm_r[NUM_WRITE_PATH_FLOP_STAGES-1];
assign phy_ddio_dqs_en_pre_shift = afi_dqs_en_r[NUM_WRITE_PATH_FLOP_STAGES-1];
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_extender oct_ena_source_extender(
.clk (pll_afi_clk),
.reset_n (1'b1),
.extend_by (2'b10),
.datain ((NUM_WRITE_PATH_FLOP_STAGES == 1) ? oct_ena_source : oct_ena_source_r[NUM_WRITE_PATH_FLOP_STAGES - 2]),
.dataout (oct_ena_source_extended)
);
defparam oct_ena_source_extender.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
wire [AFI_DQS_WIDTH-1:0] oct_ena_source_extended_shifted;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter oct_ena_source_extended_shifter(
.clk (pll_afi_clk),
.shift_by (2'b01),
.reset_n (1'b1),
.datain (oct_ena_source_extended),
.dataout (oct_ena_source_extended_shifted)
);
defparam oct_ena_source_extended_shifter.DATA_WIDTH = MEM_WRITE_DQS_WIDTH;
assign phy_ddio_oct_ena_pre_shift = ~oct_ena_source_extended_shifted & ~force_oct_off;
end
endgenerate
generate
genvar i, t;
for (i=0; i<MEM_WRITE_DQS_WIDTH; i=i+1)
begin: bs_wr_grp
wire [1:0] seq_num_write_fr_cycle_shifts_per_group = seq_num_write_fr_cycle_shifts[2 * (i + 1) - 1 : i * 2];
wire [1:0] shift_fr_cycle =
(NUM_WRITE_FR_CYCLE_SHIFTS == 0) ? 2'b00 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 1) ? 2'b01 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 2) ? 2'b10 : (
(NUM_WRITE_FR_CYCLE_SHIFTS == 3) ? 2'b11 : (
seq_num_write_fr_cycle_shifts_per_group))));
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_oct_ena;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dqs_en;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq_pre_shift;
wire [AFI_DATA_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_dq;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en_pre_shift;
wire [AFI_DQS_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_en;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask_pre_shift;
wire [AFI_DATA_MASK_WIDTH / MEM_WRITE_DQS_WIDTH - 1:0] grp_wrdata_mask;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter dq_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dq_pre_shift),
.dataout (grp_dq)
);
defparam dq_shifter.DATA_WIDTH = (DQ_GROUP_WIDTH * 2);
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter wrdata_mask_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_mask_pre_shift),
.dataout (grp_wrdata_mask)
);
defparam wrdata_mask_shifter.DATA_WIDTH = (DM_GROUP_WIDTH * 2);
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter wrdata_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_wrdata_en_pre_shift),
.dataout (grp_wrdata_en)
);
defparam wrdata_en_shifter.DATA_WIDTH = 1;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter dqs_en_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_dqs_en_pre_shift),
.dataout (grp_dqs_en)
);
defparam dqs_en_shifter.DATA_WIDTH = 1;
nios_mem_if_ddr2_emif_0_p0_fr_cycle_shifter oct_ena_shifter(
.clk (pll_afi_clk),
.shift_by (shift_fr_cycle),
.reset_n (1'b1),
.datain (grp_oct_ena_pre_shift),
.dataout (grp_oct_ena)
);
defparam oct_ena_shifter.DATA_WIDTH = 1;
for (t=0; t<RATE_MULT*2; t=t+1)
begin: extract_ddr_grp
wire [DQ_GROUP_WIDTH-1:0] dq_t_pre_shift = phy_ddio_dq_pre_shift[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t];
assign grp_dq_pre_shift[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH] = dq_t_pre_shift;
wire [DQ_GROUP_WIDTH-1:0] dq_t = grp_dq[(t+1) * DQ_GROUP_WIDTH - 1 : t * DQ_GROUP_WIDTH];
assign phy_ddio_dq[DQ_GROUP_WIDTH * (i+1) + MEM_DQ_WIDTH * t - 1 : DQ_GROUP_WIDTH * i + MEM_DQ_WIDTH * t] = dq_t;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t_pre_shift = phy_ddio_wrdata_mask_pre_shift[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t];
assign grp_wrdata_mask_pre_shift[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH] = wrdata_mask_t_pre_shift;
wire [DM_GROUP_WIDTH-1:0] wrdata_mask_t = grp_wrdata_mask[(t+1) * DM_GROUP_WIDTH - 1 : t * DM_GROUP_WIDTH];
assign phy_ddio_wrdata_mask[DM_GROUP_WIDTH * (i+1) + MEM_DM_WIDTH * t - 1 : DM_GROUP_WIDTH * i + MEM_DM_WIDTH * t] = wrdata_mask_t;
end
for (t=0; t<RATE_MULT; t=t+1)
begin: extract_sdr_grp
assign grp_oct_ena_pre_shift[t] = phy_ddio_oct_ena_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_oct_ena[i + MEM_WRITE_DQS_WIDTH * t] = grp_oct_ena[t];
assign grp_dqs_en_pre_shift[t] = phy_ddio_dqs_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_dqs_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_dqs_en[t];
assign grp_wrdata_en_pre_shift[t] = phy_ddio_wrdata_en_pre_shift[i + MEM_WRITE_DQS_WIDTH * t];
assign phy_ddio_wrdata_en[i + MEM_WRITE_DQS_WIDTH * t] = grp_wrdata_en[t];
end
end
endgenerate
endmodule
|
module snoop_adapter (
clk,
reset,
kernel_clk,
kernel_reset,
address,
read,
readdata,
readdatavalid,
write,
writedata,
burstcount,
byteenable,
waitrequest,
burstbegin,
snoop_data,
snoop_valid,
snoop_ready,
export_address,
export_read,
export_readdata,
export_readdatavalid,
export_write,
export_writedata,
export_burstcount,
export_burstbegin,
export_byteenable,
export_waitrequest
);
parameter NUM_BYTES = 4;
parameter BYTE_ADDRESS_WIDTH = 32;
parameter WORD_ADDRESS_WIDTH = 32;
parameter BURSTCOUNT_WIDTH = 1;
localparam DATA_WIDTH = NUM_BYTES * 8;
localparam ADDRESS_SHIFT = BYTE_ADDRESS_WIDTH - WORD_ADDRESS_WIDTH;
localparam DEVICE_BLOCKRAM_MIN_DEPTH = 256; //Stratix IV M9Ks
localparam FIFO_SIZE = DEVICE_BLOCKRAM_MIN_DEPTH;
localparam LOG2_FIFO_SIZE =$clog2(FIFO_SIZE);
input clk;
input reset;
input kernel_clk;
input kernel_reset;
input [WORD_ADDRESS_WIDTH-1:0] address;
input read;
output [DATA_WIDTH-1:0] readdata;
output readdatavalid;
input write;
input [DATA_WIDTH-1:0] writedata;
input [BURSTCOUNT_WIDTH-1:0] burstcount;
input burstbegin;
input [NUM_BYTES-1:0] byteenable;
output waitrequest;
output [1+WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data;
output snoop_valid;
input snoop_ready;
output [BYTE_ADDRESS_WIDTH-1:0] export_address;
output export_read;
input [DATA_WIDTH-1:0] export_readdata;
input export_readdatavalid;
output export_write;
output [DATA_WIDTH-1:0] export_writedata;
output [BURSTCOUNT_WIDTH-1:0] export_burstcount;
output export_burstbegin;
output [NUM_BYTES-1:0] export_byteenable;
input export_waitrequest;
reg snoop_overflow;
// Register snoop data first
reg [WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0] snoop_data_r; //word-address
reg snoop_valid_r;
wire snoop_fifo_empty;
wire overflow;
wire [ LOG2_FIFO_SIZE-1 : 0 ] rdusedw;
always@(posedge clk)
begin
snoop_data_r<={address,export_burstcount};
snoop_valid_r<=export_write && !export_waitrequest;
end
// 1) Fifo to store snooped accesses from host
dcfifo dcfifo_component (
.wrclk (clk),
.data (snoop_data_r),
.wrreq (snoop_valid_r),
.rdclk (kernel_clk),
.rdreq (snoop_valid & snoop_ready),
.q (snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH-1:0]),
.rdempty (snoop_fifo_empty),
.rdfull (overflow),
.aclr (1'b0),
.rdusedw (rdusedw),
.wrempty (),
.wrfull (),
.wrusedw ());
defparam
dcfifo_component.intended_device_family = "Stratix IV",
dcfifo_component.lpm_numwords = FIFO_SIZE,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH,
dcfifo_component.lpm_widthu = LOG2_FIFO_SIZE,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 4,
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.wrsync_delaypipe = 4;
assign snoop_valid=~snoop_fifo_empty;
always@(posedge kernel_clk)
snoop_overflow = ( rdusedw >= ( FIFO_SIZE - 12 ) );
// Overflow piggy backed onto MSB of stream. Since overflow guarantees
// there is something to be read out, we can be sure that this will reach
// the cache.
assign snoop_data[WORD_ADDRESS_WIDTH+BURSTCOUNT_WIDTH] = snoop_overflow;
assign export_address = address << ADDRESS_SHIFT;
assign export_read = read;
assign readdata = export_readdata;
assign readdatavalid = export_readdatavalid;
assign export_write = write;
assign export_writedata = writedata;
assign export_burstcount = burstcount;
assign export_burstbegin = burstbegin;
assign export_byteenable = byteenable;
assign waitrequest = export_waitrequest;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 17:01:20 11/17/2015
// Design Name:
// Module Name: MPU_controller
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MPU_controller(
input clk,
input clk_frame,
input rst,
input en,
output reg busy,
output reg [15:0] AcX,
output reg [15:0] AcY,
output reg [15:0] AcZ,
output reg [15:0] GyX,
output reg [15:0] GyY,
output reg [15:0] GyZ,
output reg error_i2c,
output SCL,
input SDA_in,
output SDA_out,
output SDA_oen
);
////////////////////// MPU-6050 Registers ////////////////////////////////////////
localparam MPU_SPRT = 8'h19, // Sample Rate //
MPU_CONF = 8'h1A, // General Configuration //
MPU_CONF_GYRO = 8'h1B, // Gyroscope Configuration //
MPU_CONF_ACC = 8'h1C, // Accelerometer Configuration //
MPU_ACC_X_H = 8'h3B, // Accelerometer Reading //
MPU_ACC_X_L = 8'h3C, // Accelerometer Reading //
MPU_ACC_Y_H = 8'h3D, // Accelerometer Reading //
MPU_ACC_Y_L = 8'h3E, // Accelerometer Reading //
MPU_ACC_Z_H = 8'h3F, // Accelerometer Reading //
MPU_ACC_Z_L = 8'h40, // Accelerometer Reading //
MPU_TMP_h = 8'h41, // Temperature Reading //
MPU_TMP_L = 8'h42, // Temperature Reading //
MPU_GYR_X_H = 8'h43, // Gyroscope Reading //
MPU_GYR_X_L = 8'h44, // Gyroscope Reading //
MPU_GYR_Y_H = 8'h45, // Gyroscope Reading //
MPU_GYR_Y_L = 8'h46, // Gyroscope Reading //
MPU_GYR_Z_H = 8'h47, // Gyroscope Reading //
MPU_GYR_Z_L = 8'h48, // Gyroscope Reading //
MPU_PWR_MGM = 8'h6B, // Powr Management Register //
MPU_WAI = 8'h75; // Who Am I? //
//////////////////////////////////////////////////////////////////////////////////
///////////////// MPU-6050 Registers Configuration ///////////////////////////////
localparam MPU_SPRT_VAL = 8'h00, // SR = GOR/(1+MPU_SPRT_VAL) //
MPU_FSYNC_DIS = 8'h00, // Disable Frame Synchronization //
MPU_LPF_CONF_260 = 8'h00, // Low Pass Filter: 260Hz -> GOR = 8000 //
MPU_LPF_CONF_184 = 8'h01, // Low Pass Filter: 184Hz -> GOR = 1000 //
MPU_LPF_CONF_94 = 8'h02, // Low Pass Filter: 094Hz -> GOR = 1000 //
MPU_LPF_CONF_44 = 8'h03, // Low Pass Filter: 044Hz -> GOR = 1000 //
MPU_LPF_CONF_21 = 8'h04, // Low Pass Filter: 021Hz -> GOR = 1000 //
MPU_LPF_CONF_10 = 8'h05, // Low Pass Filter: 010Hz -> GOR = 1000 //
MPU_LPF_CONF_5 = 8'h06, // Low Pass Filter: 005Hz -> GOR = 1000 //
MPU_GYRO_250 = 8'h00, // 250°/S //
MPU_GYRO_500 = 8'h08, // 500°/S //
MPU_GYRO_1000 = 8'h10, // 1000°/S //
MPU_GYRO_2000 = 8'h18, // 2000°/S //
MPU_ACCL_2 = 8'h00, // 2g //
MPU_ACCL_4 = 8'h08, // 4g //
MPU_ACCL_8 = 8'h10, // 8g //
MPU_ACCL_16 = 8'h18, // 16g //
MPU_RST = 8'h80, // Resets device //
MPU_WUP = 8'h00, // Wakes up Device //
ADDR_W = 8'b01101000, // Slave Addres, Write mode //
ADDR_R = 8'b01101001; // Generate START condition //
//////////////////////////////////////////////////////////////////////////////////
//////////////////////// Internal Registers ///////////////////////
reg [7:0] regDir,data,regDir_d,data_d; //
reg [3:0] i; //
reg stop_d,ack_o_d;
///////////////////////////////////////////////////////////////////
///////////////////// I2C Instantiation /////////////////////////////////
reg en_i2c,start,stop,ack_o,rw; //
reg[7:0] out_byte; //
wire err,busy_i2c; //
wire[7:0] in_byte; //
I2C_Top I2C ( //
.clk(clk), //
.clk_frame(clk_frame), //
.rst(rst), //
.en(en_i2c), //
.start(start), //
.stop(stop), //
.ack_o(ack_o), //
.rw(rw), //
.out_byte(out_byte), //
.busy(busy_i2c), //
.err(err_i2c), //
.in_byte(in_byte), //
.SCL(SCL), //
.SDA_in(SDA_in), //
.SDA_out(SDA_out), //
.SDA_oen(SDA_oen) //
); //
/////////////////////////////////////////////////////////////////////////
///////////////////////// Math Instances ////////////////////////////////
reg [15:0] mul1_A; //
reg [15:0] mul1_B; //
reg mul1_en; //
reg mul1_rst; //
reg mul1_busy; //
wire [31:0] mul1_R; //
booth_mult multi_1 ( //
.clk(clk), //
.rst(mul1_rst), //
.en(mul1_en), //
.A(mul1_A), //
.B(mul1_B), //
.busy(mul1_busy), //
.R(mul1_R) //
); //
reg [15:0] mul2_A; //
reg [15:0] mul2_B; //
reg mul2_en; //
reg mul2_rst; //
reg mul2_busy; //
wire [31:0] mul2_R; //
booth_mult multi_2 ( //
.clk(clk), //
.rst(mul2_rst), //
.en(mul2_en), //
.A(mul2_A), //
.B(mul2_B), //
.busy(mul2_busy), //
.R(mul2_R) //
); //
/////////////////////////////////////////////////////////////////////////
///////////////////////////// States ////////////////////////////////////
reg [4:0] state, pointer, pointer2, pointer3,temp; //
initial begin
state = 5'h00;
pointer = 5'h00;
pointer2 = 5'h00;
pointer3 = 5'h00;
end
localparam reset = 00, //
set_FSNC = 01, //
set_LPF = 02, //
set_res_gyr = 03, //
set_res_acc = 04, //
wake_up = 05, //
idle = 06, //
write_accX = 07, //
read = 08, //
read_w = 09, //
check1 = 10, //
check2 = 11, //
check3 = 12, //
error = 13, //
start_cond = 14, //
send_addresR = 15, //
send_addresW = 16, //
send_regAddr = 17, //
send_byte = 18, //
read_8_ACK = 19, //
read_8_NACK = 20, //
stop_cond = 21, //
wait_i2c = 22, //
wait_i2c_A = 23, //
wait_i2c_B = 24; //
/////////////////////////////////////////////////////////////////////////
always@(posedge clk) begin
if(rst) begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= set_FSNC;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
state <= reset;
end
else begin
case(state)
reset: begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= set_FSNC;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
end
set_FSNC: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_LPF;
end
set_LPF: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_res_gyr;
end
set_res_gyr: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= set_res_acc;
end
set_res_acc: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= wake_up;
end
wake_up: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
state <= send_addresW;
pointer <= send_regAddr;
pointer2 <= send_byte;
pointer3 <= idle;
end
idle: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= idle;
pointer2 <= idle;
pointer3 <= idle;
if(en) state <= write_accX;
else state <= idle;
end
write_accX: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= send_regAddr;
pointer2 <= send_addresR;
pointer3 <= read;
state <= send_addresW;
end
read: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= read_w;
else state <= read;
end
read_w: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= read_w;
else state <= check1;
end
check1: begin
i <= i;
case(i)
4'h0: begin
AcX[15:8] <= in_byte;
AcX[7:0] <= 8'h00;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h1: begin
AcX[15:8] <= AcX[15:8];
AcX[7:0] <= in_byte;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h2: begin
AcX <= AcX;
AcY[15:8] <= in_byte;
AcY[7:0] <= 8'h00;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h3: begin
AcX <= AcX;
AcY[15:8] <= AcY[15:8];
AcY[7:0] <= in_byte;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h4: begin
AcX <= AcX;
AcY <= AcY;
AcZ[15:8] <= in_byte;
AcZ[7:0] <= 8'h00;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h5: begin
AcX <= AcX;
AcY <= AcY;
AcZ[15:8] <= AcZ[15:8];
AcZ[7:0] <= in_byte;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h6: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h7: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
end
4'h8: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX[15:8] <= in_byte;
GyX[7:0] <= 8'h00;
GyY <= GyY;
GyZ <= GyZ;
end
4'h9: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX[15:8] <= GyX[15:8];
GyX[7:0] <= in_byte;
GyY <= GyY;
GyZ <= GyZ;
end
4'hA: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY[15:8] <= in_byte;
GyY[7:0] <= 8'h00;
GyZ <= GyZ;
end
4'hB: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY[15:8] <= GyY[15:8];
GyY[7:0] <= in_byte;
GyZ <= GyZ;
end
4'hC: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ[15:8] <= in_byte;
GyZ[7:0] <= 8'h00;
end
4'hD: begin
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ[15:8] <= GyZ[15:8];
GyZ[7:0] <= in_byte;
end
default: begin
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ[15:8] <= 16'h0000;
GyZ[7:0] <= 16'h0000;
end
endcase
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
state <= check2;
end
check2: begin
i <= i+1;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
state <= check3;
end
check3: begin
i <= i;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(i == 4'hE) state <= idle;
else state <= read;
end
error: begin
i <= 4'h00;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= error;
pointer2 <= error;
pointer3 <= error;
state <= error;
end
send_addresR: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_addresR;
end
send_addresW: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_addresW;
end
send_regAddr: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_regAddr;
end
send_byte: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_A;
else state <= send_byte;
end
wait_i2c_A: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer2;
pointer2 <= pointer3;
pointer3 <= pointer;
state <= wait_i2c_B;
end
wait_i2c_B: begin
i <= 4'h0;
AcX <= AcX;
AcY <= AcY;
AcZ <= AcZ;
GyX <= GyX;
GyY <= GyY;
GyZ <= GyZ;
pointer <= pointer;
pointer2 <= pointer2;
pointer3 <= pointer3;
if(busy_i2c) state <= wait_i2c_B;
else state <= pointer3;
end
default: begin
i <= 4'h0;
AcX <= 16'h0000;
AcY <= 16'h0000;
AcZ <= 16'h0000;
GyX <= 16'h0000;
GyY <= 16'h0000;
GyZ <= 16'h0000;
state <= error;
pointer <= reset;
pointer2 <= reset;
pointer3 <= reset;
end
endcase
end
end
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
always@(*) begin
case(state)
reset: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_FSNC: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF;
data <= MPU_FSYNC_DIS;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_LPF: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF;
data <= MPU_LPF_CONF_184;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_res_gyr: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF_GYRO;
data <= MPU_GYRO_250;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
set_res_acc: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_CONF_ACC;
data <= MPU_ACCL_2;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
wake_up: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_PWR_MGM;
data <= MPU_WUP;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
idle: begin
busy <= 1'b0;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
write_accX: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= MPU_ACC_X_H;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b00;
stop <= 1'b00;
ack_o <= 1'b00;
rw <= 1'b00;
out_byte <= 8'h00;
end
read: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b1;
start <= 1'b0;
if(i == 4'hD) begin
stop <= 1'b1;
ack_o <= 1'b1;
end
else begin
stop <= 1'b0;
ack_o <= 1'b0;
end
rw <= 1'b0;
out_byte <= 8'h00;
end
read_w: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check1: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check2: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
check3: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
error: begin
busy <= 1'b0;
error_i2c<= 1'b1;
regDir <= 8'h00;
data <= 8'h00;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b0;
out_byte <= 8'h00;
end
send_addresR: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b1;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= ADDR_R;
end
send_addresW: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b1;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= ADDR_W;
end
send_regAddr: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b0;
stop <= 1'b0;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= regDir;
end
send_byte: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b1;
start <= 1'b0;
stop <= 1'b1;
ack_o <= 1'b0;
rw <= 1'b1;
out_byte <= data;
end
wait_i2c_A: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
wait_i2c_B: begin
busy <= 1'b1;
error_i2c<= 1'b0;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
default: begin
busy <= 1'b0;
error_i2c<= 1'b1;
regDir <= regDir_d;
data <= data_d;
en_i2c <= 1'b0;
start <= 1'b0;
stop <= stop_d;
ack_o <= ack_o_d;
rw <= 1'b0;
out_byte <= 8'h00;
end
endcase
end
always@(negedge clk) begin
regDir_d <= regDir;
data_d <= data;
stop_d <= stop;
ack_o_d <= ack_o;
end
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 23:00:42 01/05/2013
// Design Name:
// Module Name: Control_Character
// Project Name: P.O.V
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Control_Character(
input Clock,
input Reset,
input ClockKeyboard,
input DataKeyboard,
output New,
output [6:0]Char
);
wire NewScanCode;
wire ScanCodeType;
wire LoadDato;
wire LoadChar;
wire NewAscii;
wire [7:0]Anterior;
wire [7:0]Actual;
wire [7:0]ScanCode;
wire [6:0]Ascii;
MaquinaDeControl Maquina_Control(.Clock(Clock), .Reset(Reset), .NewScanCode(NewScanCode), .NewAscii(NewAscii), .LoadDato(LoadDato), .LoadChar(LoadChar), .ScanCodeType(ScanCodeType));
Anterior_Actual Anterior_Actual_Module(.Clock(Clock), .Reset(Reset), .LoadDato(LoadDato), .Dato(ScanCode), .Anterior(Anterior), .Actual(Actual));
Converter Convertir(.Clock(Clock), .Reset(Reset), .ScanCodeType(ScanCodeType), .Actual(Actual), .Ascii(Ascii), .NewAscii(NewAscii), .Anterior(Anterior));
Char_Ascii Converter_Ascii(.Clock(Clock), .Reset(Reset), .LoadChar(LoadChar), .Ascii(Ascii), .New(New), .Char(Char));
ScanCodeModule ScanCode_Module(.Clk(Clock), .Reset(Reset), .ClkKB(ClockKeyboard), .DataKB(DataKeyboard), .NewScanCode(NewScanCode), .ScanCode(ScanCode));
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 4;
localparam MEM_EXTRA = 4;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("i64.add.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 0;
wire [63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR)
)
dut
(
.clk(clk),
.reset(reset),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("i64.add_tb.vcd");
$dumpvars(0, cpu_tb);
if(USE_64B) begin
#24
`assert(result, 3);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#12
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__DECAP_TB_V
`define SKY130_FD_SC_LS__DECAP_TB_V
/**
* decap: Decoupling capacitance filler.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__decap.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__decap dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__DECAP_TB_V
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: altpcie_pll_phy1_62p5.v
// Megafunction Name(s):
// altpll
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Build 235 06/17/2009 SP 2 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2009 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_pll_phy1_62p5 (
areset,
inclk0,
c0,
c1,
c2,
locked);
input areset;
input inclk0;
output c0;
output c1;
output c2;
output locked;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 areset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [5:0] sub_wire0;
wire sub_wire4;
wire [0:0] sub_wire7 = 1'h0;
wire [2:2] sub_wire3 = sub_wire0[2:2];
wire [1:1] sub_wire2 = sub_wire0[1:1];
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire c1 = sub_wire2;
wire c2 = sub_wire3;
wire locked = sub_wire4;
wire sub_wire5 = inclk0;
wire [1:0] sub_wire6 = {sub_wire7, sub_wire5};
altpll altpll_component (
.inclk (sub_wire6),
.areset (areset),
.clk (sub_wire0),
.locked (sub_wire4),
.activeclock (),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.clk0_divide_by = 1,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = 1,
altpll_component.clk0_phase_shift = "0",
altpll_component.clk1_divide_by = 1,
altpll_component.clk1_duty_cycle = 50,
altpll_component.clk1_multiply_by = 1,
altpll_component.clk1_phase_shift = "-3200",
altpll_component.clk2_divide_by = 2,
altpll_component.clk2_duty_cycle = 50,
altpll_component.clk2_multiply_by = 1,
altpll_component.clk2_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.gate_lock_signal = "NO",
altpll_component.inclk0_input_frequency = 8000,
altpll_component.intended_device_family = "Cyclone II",
altpll_component.invalid_lock_multiplier = 5,
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_USED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_USED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_USED",
altpll_component.port_clk2 = "PORT_USED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.valid_lock_multiplier = 1;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH STRING "2.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
// Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "125.000000"
// Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "62.500000"
// Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "10000"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "125.000"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "375.000"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "ps"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT2 STRING "ps"
// Retrieval info: PRIVATE: MIG_DEVICE_SPEED_GRADE STRING "Any"
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK1 STRING "0"
// Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "1"
// Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "1"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "125.00000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "62.50000000"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
// Retrieval info: PRIVATE: PHASE_RECONFIG_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: PHASE_RECONFIG_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT1 STRING "-3.20000000"
// Retrieval info: PRIVATE: PHASE_SHIFT2 STRING "0.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT_STEP_ENABLED_CHECK STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT1 STRING "ns"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT2 STRING "ns"
// Retrieval info: PRIVATE: PLL_ADVANCED_PARAM_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "1"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_FBMIMIC_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_TARGET_HARCOPY_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: RECONFIG_FILE STRING "altpcie_pll_phy1_62p5.mif"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SELF_RESET_LOCK_LOSS STRING "0"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK1 STRING "1"
// Retrieval info: PRIVATE: STICKY_CLK2 STRING "1"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "1"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: USE_CLK1 STRING "1"
// Retrieval info: PRIVATE: USE_CLK2 STRING "1"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA1 STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA2 STRING "0"
// Retrieval info: PRIVATE: USE_MIL_SPEED_GRADE NUMERIC "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: CLK1_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "-3200"
// Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "2"
// Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1"
// Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: GATE_LOCK_SIGNAL STRING "NO"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "8000"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
// Retrieval info: CONSTANT: INVALID_LOCK_MULTIPLIER NUMERIC "5"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: PORT_ACTIVECLOCK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_ARESET STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_CLKBAD0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKBAD1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKLOSS STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CLKSWITCH STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_CONFIGUPDATE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_FBIN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_INCLK0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_INCLK1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_LOCKED STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_PFDENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASECOUNTERSELECT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASESTEP STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PHASEUPDOWN STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_PLLENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANACLR STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLK STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANCLKENA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATA STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDATAOUT STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANDONE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANREAD STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_SCANWRITE STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk0 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk1 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk2 STRING "PORT_USED"
// Retrieval info: CONSTANT: PORT_clk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clk5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena4 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_clkena5 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk0 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk1 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk2 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: PORT_extclk3 STRING "PORT_UNUSED"
// Retrieval info: CONSTANT: VALID_LOCK_MULTIPLIER NUMERIC "1"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT_CLK_EXT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT_CLK_EXT VCC "@extclk[3..0]"
// Retrieval info: USED_PORT: areset 0 0 0 0 INPUT GND "areset"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT_CLK_EXT VCC "c0"
// Retrieval info: USED_PORT: c1 0 0 0 0 OUTPUT_CLK_EXT VCC "c1"
// Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
// Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
// Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
// Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: CONNECT: @areset 0 0 0 0 areset 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_bb.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_waveforms.html FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5_wave*.jpg FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_pll_phy1_62p5.ppf TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//*****************************************************************************
// (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mig_7series_v1_8_ddr_phy_tempmon.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Jul 25 2012
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Monitors chip temperature via the XADC and adjusts the
// stage 2 tap values as appropriate.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v1_8_ddr_phy_tempmon #
(
parameter TCQ = 100, // Register delay (simulation only)
// Temperature bands must be in order. To disable bands, set to extreme.
parameter BAND1_TEMP_MIN = 0, // Degrees C. Min=-273. Max=231
parameter BAND2_TEMP_MIN = 12, // Degrees C. Min=-273. Max=231
parameter BAND3_TEMP_MIN = 46, // Degrees C. Min=-273. Max=231
parameter BAND4_TEMP_MIN = 82, // Degrees C. Min=-273. Max=231
parameter TEMP_HYST = 5
)
(
input clk, // Fabric clock
input rst, // System reset
input calib_complete, // Calibration complete
input tempmon_sample_en, // Signal to enable sampling
input [11:0] device_temp, // Current device temperature
output tempmon_pi_f_inc, // Increment PHASER_IN taps
output tempmon_pi_f_dec, // Decrement PHASER_IN taps
output tempmon_sel_pi_incdec // Assume control of PHASER_IN taps
);
// translate hysteresis into XADC units
localparam HYST_OFFSET = (TEMP_HYST * 4096) / 504;
// translate band boundaries into XADC units
localparam BAND1_OFFSET = ((BAND1_TEMP_MIN + 273) * 4096) / 504;
localparam BAND2_OFFSET = ((BAND2_TEMP_MIN + 273) * 4096) / 504;
localparam BAND3_OFFSET = ((BAND3_TEMP_MIN + 273) * 4096) / 504;
localparam BAND4_OFFSET = ((BAND4_TEMP_MIN + 273) * 4096) / 504;
// incorporate hysteresis into band boundaries
localparam BAND0_DEC_OFFSET =
BAND1_OFFSET - HYST_OFFSET > 0 ? BAND1_OFFSET - HYST_OFFSET : 0 ;
localparam BAND1_INC_OFFSET =
BAND1_OFFSET + HYST_OFFSET < 4096 ? BAND1_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND1_DEC_OFFSET =
BAND2_OFFSET - HYST_OFFSET > 0 ? BAND2_OFFSET - HYST_OFFSET : 0 ;
localparam BAND2_INC_OFFSET =
BAND2_OFFSET + HYST_OFFSET < 4096 ? BAND2_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND2_DEC_OFFSET =
BAND3_OFFSET - HYST_OFFSET > 0 ? BAND3_OFFSET - HYST_OFFSET : 0 ;
localparam BAND3_INC_OFFSET =
BAND3_OFFSET + HYST_OFFSET < 4096 ? BAND3_OFFSET + HYST_OFFSET : 4096 ;
localparam BAND3_DEC_OFFSET =
BAND4_OFFSET - HYST_OFFSET > 0 ? BAND4_OFFSET - HYST_OFFSET : 0 ;
localparam BAND4_INC_OFFSET =
BAND4_OFFSET + HYST_OFFSET < 4096 ? BAND4_OFFSET + HYST_OFFSET : 4096 ;
// Temperature sampler FSM encoding
localparam INIT = 2'b00;
localparam IDLE = 2'b01;
localparam UPDATE = 2'b10;
localparam WAIT = 2'b11;
// Temperature sampler state
reg [2:0] tempmon_state = INIT;
reg [2:0] tempmon_next_state = INIT;
// Temperature storage
reg [11:0] previous_temp = 12'b0;
// Temperature bands
reg [2:0] target_band = 3'b000;
reg [2:0] current_band = 3'b000;
// Tap count and control
reg pi_f_inc = 1'b0;
reg pi_f_dec = 1'b0;
reg sel_pi_incdec = 1'b0;
// Temperature and band comparisons
reg device_temp_lt_previous_temp = 1'b0;
reg device_temp_gt_previous_temp = 1'b0;
reg device_temp_lt_band1 = 1'b0;
reg device_temp_lt_band2 = 1'b0;
reg device_temp_lt_band3 = 1'b0;
reg device_temp_lt_band4 = 1'b0;
reg device_temp_lt_band0_dec = 1'b0;
reg device_temp_lt_band1_dec = 1'b0;
reg device_temp_lt_band2_dec = 1'b0;
reg device_temp_lt_band3_dec = 1'b0;
reg device_temp_gt_band1_inc = 1'b0;
reg device_temp_gt_band2_inc = 1'b0;
reg device_temp_gt_band3_inc = 1'b0;
reg device_temp_gt_band4_inc = 1'b0;
reg current_band_lt_target_band = 1'b0;
reg current_band_gt_target_band = 1'b0;
reg target_band_gt_1 = 1'b0;
reg target_band_gt_2 = 1'b0;
reg target_band_gt_3 = 1'b0;
reg target_band_lt_1 = 1'b0;
reg target_band_lt_2 = 1'b0;
reg target_band_lt_3 = 1'b0;
// Pass tap control signals back up to PHY
assign tempmon_pi_f_inc = pi_f_inc;
assign tempmon_pi_f_dec = pi_f_dec;
assign tempmon_sel_pi_incdec = sel_pi_incdec;
// XADC sampler state transition
always @(posedge clk)
if(rst)
tempmon_state <= #TCQ INIT;
else
tempmon_state <= #TCQ tempmon_next_state;
// XADC sampler next state transition
always @(tempmon_state or calib_complete or tempmon_sample_en) begin
tempmon_next_state = tempmon_state;
case(tempmon_state)
INIT:
if(calib_complete)
tempmon_next_state = IDLE;
IDLE:
if(tempmon_sample_en)
tempmon_next_state = UPDATE;
UPDATE:
tempmon_next_state = WAIT;
WAIT:
if(~tempmon_sample_en)
tempmon_next_state = IDLE;
default:
tempmon_next_state = INIT;
endcase
end
// Record previous temperature during update cycle
always @(posedge clk)
if((tempmon_state == INIT) || (tempmon_state == UPDATE))
previous_temp <= #TCQ device_temp;
// Update target band
always @(posedge clk) begin
// register temperature comparisons
device_temp_lt_previous_temp <= #TCQ (device_temp < previous_temp) ? 1'b1 : 1'b0;
device_temp_gt_previous_temp <= #TCQ (device_temp > previous_temp) ? 1'b1 : 1'b0;
device_temp_lt_band1 <= #TCQ (device_temp < BAND1_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band2 <= #TCQ (device_temp < BAND2_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band3 <= #TCQ (device_temp < BAND3_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band4 <= #TCQ (device_temp < BAND4_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band0_dec <= #TCQ (device_temp < BAND0_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band1_dec <= #TCQ (device_temp < BAND1_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band2_dec <= #TCQ (device_temp < BAND2_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_lt_band3_dec <= #TCQ (device_temp < BAND3_DEC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band1_inc <= #TCQ (device_temp > BAND1_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band2_inc <= #TCQ (device_temp > BAND2_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band3_inc <= #TCQ (device_temp > BAND3_INC_OFFSET) ? 1'b1 : 1'b0;
device_temp_gt_band4_inc <= #TCQ (device_temp > BAND4_INC_OFFSET) ? 1'b1 : 1'b0;
target_band_gt_1 <= #TCQ (target_band > 3'b001) ? 1'b1 : 1'b0;
target_band_gt_2 <= #TCQ (target_band > 3'b010) ? 1'b1 : 1'b0;
target_band_gt_3 <= #TCQ (target_band > 3'b011) ? 1'b1 : 1'b0;
target_band_lt_1 <= #TCQ (target_band < 3'b001) ? 1'b1 : 1'b0;
target_band_lt_2 <= #TCQ (target_band < 3'b010) ? 1'b1 : 1'b0;
target_band_lt_3 <= #TCQ (target_band < 3'b011) ? 1'b1 : 1'b0;
// Initialize band
if(tempmon_state == INIT) begin
if(device_temp_lt_band1)
target_band <= #TCQ 3'b000;
else if(device_temp_lt_band2)
target_band <= #TCQ 3'b001;
else if(device_temp_lt_band3)
target_band <= #TCQ 3'b010;
else if(device_temp_lt_band4)
target_band <= #TCQ 3'b011;
else
target_band <= #TCQ 3'b100;
end
// Ready to update
else if(tempmon_state == IDLE) begin
// Temperature has increased, see if it is in a new band
if(device_temp_gt_previous_temp) begin
if(device_temp_gt_band4_inc)
target_band <= #TCQ 3'b100;
else if(device_temp_gt_band3_inc && target_band_lt_3)
target_band <= #TCQ 3'b011;
else if(device_temp_gt_band2_inc && target_band_lt_2)
target_band <= #TCQ 3'b010;
else if(device_temp_gt_band1_inc && target_band_lt_1)
target_band <= #TCQ 3'b001;
end
// Temperature has decreased, see if it is in new band
else if(device_temp_lt_previous_temp) begin
if(device_temp_lt_band0_dec)
target_band <= #TCQ 3'b000;
else if(device_temp_lt_band1_dec && target_band_gt_1)
target_band <= #TCQ 3'b001;
else if(device_temp_lt_band2_dec && target_band_gt_2)
target_band <= #TCQ 3'b010;
else if(device_temp_lt_band3_dec && target_band_gt_3)
target_band <= #TCQ 3'b011;
end
end
end
// Current band
always @(posedge clk) begin
current_band_lt_target_band = (current_band < target_band) ? 1'b1 : 1'b0;
current_band_gt_target_band = (current_band > target_band) ? 1'b1 : 1'b0;
if(tempmon_state == INIT) begin
if(device_temp_lt_band1)
current_band <= #TCQ 3'b000;
else if(device_temp_lt_band2)
current_band <= #TCQ 3'b001;
else if(device_temp_lt_band3)
current_band <= #TCQ 3'b010;
else if(device_temp_lt_band4)
current_band <= #TCQ 3'b011;
else
current_band <= #TCQ 3'b100;
end
else if(tempmon_state == UPDATE) begin
if(current_band_lt_target_band)
current_band <= #TCQ current_band + 1;
else if(current_band_gt_target_band)
current_band <= #TCQ current_band - 1;
end
end
// Tap control
always @(posedge clk) begin
if(rst) begin
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
sel_pi_incdec <= #TCQ 1'b0;
end
else if(tempmon_state == UPDATE) begin
if(current_band_lt_target_band) begin
sel_pi_incdec <= #TCQ 1'b1;
pi_f_dec <= #TCQ 1'b1;
end
else if(current_band_gt_target_band) begin
sel_pi_incdec <= #TCQ 1'b1;
pi_f_inc <= #TCQ 1'b1;
end
end
else begin
pi_f_inc <= #TCQ 1'b0;
pi_f_dec <= #TCQ 1'b0;
sel_pi_incdec <= #TCQ 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
/**
* sedfxbp: Scan delay flop, data enable, non-inverted clock,
* complementary outputs.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__sedfxbp (
Q ,
Q_N,
CLK,
D ,
DE ,
SCD,
SCE
);
output Q ;
output Q_N;
input CLK;
input D ;
input DE ;
input SCD;
input SCE;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__SEDFXBP_BLACKBOX_V
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_cntl_slave # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output rx_np_ok,
output rx_np_req,
input mreq_fifo_wr_en,
input [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output tx_cpld_req,
output [7:0] tx_cpld_tag,
output [15:0] tx_cpld_req_id,
output [11:2] tx_cpld_len,
output [11:0] tx_cpld_bc,
output [6:0] tx_cpld_laddr,
output [63:0] tx_cpld_data,
input tx_cpld_req_ack,
output nvme_cc_en,
output [1:0] nvme_cc_shn,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
output nvme_intms_ivms,
output nvme_intmc_ivmc,
input cq_irq_status,
input [8:0] sq_rst_n,
input [8:0] cq_rst_n,
output [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
output [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
output [7:0] admin_sq_size,
output [7:0] admin_cq_size,
output [7:0] admin_sq_tail_ptr,
output [7:0] io_sq1_tail_ptr,
output [7:0] io_sq2_tail_ptr,
output [7:0] io_sq3_tail_ptr,
output [7:0] io_sq4_tail_ptr,
output [7:0] io_sq5_tail_ptr,
output [7:0] io_sq6_tail_ptr,
output [7:0] io_sq7_tail_ptr,
output [7:0] io_sq8_tail_ptr,
output [7:0] admin_cq_head_ptr,
output [7:0] io_cq1_head_ptr,
output [7:0] io_cq2_head_ptr,
output [7:0] io_cq3_head_ptr,
output [7:0] io_cq4_head_ptr,
output [7:0] io_cq5_head_ptr,
output [7:0] io_cq6_head_ptr,
output [7:0] io_cq7_head_ptr,
output [7:0] io_cq8_head_ptr,
output [8:0] cq_head_update
);
wire w_mreq_fifo_rd_en;
wire [C_PCIE_DATA_WIDTH-1:0] w_mreq_fifo_rd_data;
wire w_mreq_fifo_empty_n;
pcie_cntl_reg # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_cntl_reg_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.rx_np_ok (),
.rx_np_req (rx_np_req),
.mreq_fifo_rd_en (w_mreq_fifo_rd_en),
.mreq_fifo_rd_data (w_mreq_fifo_rd_data),
.mreq_fifo_empty_n (w_mreq_fifo_empty_n),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.nvme_cc_en (nvme_cc_en),
.nvme_cc_shn (nvme_cc_shn),
.nvme_csts_shst (nvme_csts_shst),
.nvme_csts_rdy (nvme_csts_rdy),
.nvme_intms_ivms (nvme_intms_ivms),
.nvme_intmc_ivmc (nvme_intmc_ivmc),
.cq_irq_status (cq_irq_status),
.sq_rst_n (sq_rst_n),
.cq_rst_n (cq_rst_n),
.admin_sq_bs_addr (admin_sq_bs_addr),
.admin_cq_bs_addr (admin_cq_bs_addr),
.admin_sq_size (admin_sq_size),
.admin_cq_size (admin_cq_size),
.admin_sq_tail_ptr (admin_sq_tail_ptr),
.io_sq1_tail_ptr (io_sq1_tail_ptr),
.io_sq2_tail_ptr (io_sq2_tail_ptr),
.io_sq3_tail_ptr (io_sq3_tail_ptr),
.io_sq4_tail_ptr (io_sq4_tail_ptr),
.io_sq5_tail_ptr (io_sq5_tail_ptr),
.io_sq6_tail_ptr (io_sq6_tail_ptr),
.io_sq7_tail_ptr (io_sq7_tail_ptr),
.io_sq8_tail_ptr (io_sq8_tail_ptr),
.admin_cq_head_ptr (admin_cq_head_ptr),
.io_cq1_head_ptr (io_cq1_head_ptr),
.io_cq2_head_ptr (io_cq2_head_ptr),
.io_cq3_head_ptr (io_cq3_head_ptr),
.io_cq4_head_ptr (io_cq4_head_ptr),
.io_cq5_head_ptr (io_cq5_head_ptr),
.io_cq6_head_ptr (io_cq6_head_ptr),
.io_cq7_head_ptr (io_cq7_head_ptr),
.io_cq8_head_ptr (io_cq8_head_ptr),
.cq_head_update (cq_head_update)
);
pcie_cntl_rx_fifo
pcie_cntl_rx_fifo_inst0(
.clk (pcie_user_clk),
.rst_n (pcie_user_rst_n),
////////////////////////////////////////////////////////////////
//bram fifo write signals
.wr_en (mreq_fifo_wr_en),
.wr_data (mreq_fifo_wr_data),
.full_n (),
.almost_full_n (rx_np_ok),
////////////////////////////////////////////////////////////////
//bram fifo read signals
.rd_en (w_mreq_fifo_rd_en),
.rd_data (w_mreq_fifo_rd_data),
.empty_n (w_mreq_fifo_empty_n)
);
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003 by Wilson Snyder.
`define INT_RANGE 31:0
`define INT_RANGE 31:0 // Duplicate identical defs are OK
`define INT_RANGE_MAX 31
`define VECTOR_RANGE 511:0
module t (clk);
// verilator lint_off WIDTH
parameter WIDTH = 16; // Must be a power of 2
parameter WIDTH_LOG2 = 4; // set to log2(WIDTH)
parameter USE_BS = 1; // set to 1 for enable
input clk;
function [`VECTOR_RANGE] func_tree_left;
input [`VECTOR_RANGE] x; // x[width-1:0] is the input vector
reg [`VECTOR_RANGE] flip;
begin
flip = 'd0;
func_tree_left = flip;
end
endfunction
reg [WIDTH-1:0] a; // value to be shifted
reg [WIDTH-1:0] tree_left;
always @(a) begin : barrel_shift
tree_left = func_tree_left (a);
end // barrel_shift
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a = 5;
end
if (cyc==2) begin
$display ("%x\n",tree_left);
//if (tree_left != 'd15) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
Require Import Classical.
Require Import List.
Require Import Omega.
Require Import Arith.
Require Import Wf.
Require Import ranked_properties.
Require sf_spec.
Section sf_spec_properties.
Variable candidate:Set.
Let rankSelection := list candidate.
Let ballot := list rankSelection.
Let election := list ballot.
Lemma next_ranking_elim_unchanged :
forall (elim elim':candidate -> Prop) b c r,
(forall x, elim x -> elim' x) ->
~elim' c ->
sf_spec.next_ranking candidate elim b r ->
In c r ->
sf_spec.next_ranking candidate elim' b r.
Proof.
intros.
induction H1.
* apply sf_spec.next_ranking_eliminated; auto.
rewrite Forall_forall in *; firstorder.
* apply sf_spec.next_ranking_valid with c; auto.
Qed.
Lemma selected_candidate_elim_unchanged :
forall (elim elim':candidate -> Prop) b c,
sf_spec.selected_candidate candidate elim b c ->
(forall x, elim x -> elim' x) ->
~elim' c ->
sf_spec.selected_candidate candidate elim' b c.
Proof.
intros.
destruct H.
destruct H2 as [r [Hr Hc]].
split.
* intro. apply H.
destruct H2.
elim H2.
exists r. eapply next_ranking_elim_unchanged; eauto.
destruct H2 as [r' [??]].
assert (r = r').
{ cut (sf_spec.next_ranking candidate elim' b r'); [ apply sf_spec.next_ranking_unique; auto | auto ].
eapply next_ranking_elim_unchanged; eauto.
}
subst r'.
right; exists r; split; auto.
* exists r; split; auto.
eapply next_ranking_elim_unchanged; eauto.
Qed.
(** As we eliminate candidates, the first-choice counts of the remaining
candidates increases monotonically.
*)
Lemma first_choices_monotone :
forall elim elim' e c m n,
~elim' c ->
sf_spec.first_choices candidate elim c e m ->
sf_spec.first_choices candidate elim' c e n ->
(forall x, elim x -> elim' x) ->
m <= n.
Proof.
intros.
revert n H1.
induction H0; intros.
* auto with arith.
* inversion H3; subst; clear H3.
- cut (n' <= n'0). auto with arith.
apply IHfirst_choices; auto.
- elim H6.
eapply selected_candidate_elim_unchanged; eauto.
* inversion H3; subst; clear H3.
transitivity n'; auto with arith.
apply IHfirst_choices; eauto.
Qed.
Let sf_may_win_election c e :=
sf_spec.winner candidate e (fun _ => False) c.
Definition all_candidates : election -> list candidate :=
fold_right (fun a b => b ++ fold_right (@app _) nil a) nil.
Lemma all_candidates_participates : forall c e,
In c (all_candidates e) <-> sf_spec.participates _ c e.
Proof.
intros c e. induction e; simpl; intuition.
destruct H as [? [??]]. elim H.
apply in_app_or in H1. destruct H1.
apply H in H1.
destruct H1 as [? [??]].
exists x. split; simpl; auto.
exists a. split; simpl; auto.
induction a; simpl in *.
elim H1.
apply in_app_or in H1.
destruct H1.
exists a. split; auto.
apply IHa in H1.
destruct H1 as [r [??]].
eauto.
apply in_or_app.
destruct H1 as [b [??]].
simpl in H1.
destruct H1.
subst a.
right.
induction b.
destruct H2 as [r [??]].
elim H1.
simpl.
apply in_or_app.
destruct H2 as [r [??]].
simpl in H1. destruct H1.
subst a.
auto.
right. eauto.
left. apply H0.
red; eauto.
Qed.
Lemma list_remove_prop_weak : forall A (l:list A) (P:A -> Prop),
exists l',
length l' <= length l /\
(forall a, In a l -> In a l' \/ P a) /\
(forall a, In a l' -> In a l /\ ~P a).
Proof.
intro A. induction l; simpl; intuition.
* exists nil; simpl; intuition.
* destruct (IHl P) as [l' [?[??]]].
destruct (classic (P a)).
+ exists l'. simpl; intuition.
subst; auto.
apply H1 in H3. intuition.
apply H1 in H3; intuition.
+ exists (a::l'). simpl; intuition.
destruct (H0 a0); intuition.
subst a0. auto.
destruct (H1 a0); auto.
destruct (H1 a0); auto.
Qed.
Lemma list_remove_prop : forall A (l:list A) (P:A -> Prop) x,
P x -> In x l ->
exists l',
length l' < length l /\
(forall a, In a l -> In a l' \/ P a) /\
(forall a, In a l' -> In a l /\ ~P a).
Proof.
intro A. induction l; simpl; intuition.
* subst a.
destruct (list_remove_prop_weak A l P) as [l' [?[??]]].
exists l'. simpl; intuition; subst; auto.
apply H2 in H3. intuition.
apply H2 in H3. intuition.
* destruct (IHl P x) as [l' [?[??]]]; auto.
destruct (classic (P a)).
+ exists l'; intuition.
subst; auto.
apply H3 in H5. intuition.
apply H3 in H5. intuition.
+ exists (a::l'); simpl; intuition.
destruct (H2 a0); intuition; subst; auto.
subst; auto.
apply H3 in H6. intuition.
apply H3 in H6. intuition.
Qed.
Lemma majority_satisfies_ballot_exists P e :
majority_satisfies candidate P e ->
exists b, P b /\ In b e.
Proof.
intros [n [t [?[??]]]].
revert t H0 H1.
induction H; intros.
exists b; intuition.
red in H1.
inversion H1; subst; clear H1.
destruct (IHcount_votes n0) as [b' [??]]; auto.
omega.
exists b'. split; simpl; auto.
destruct (IHcount_votes t) as [b' [??]]; auto.
exists b'. split; simpl; auto.
omega.
Qed.
Lemma continuing_ballot_selects (b:ballot) (eliminated:candidate -> Prop) :
sf_spec.continuing_ballot _ eliminated b <->
exists c, sf_spec.selected_candidate _ eliminated b c.
Proof.
split; intros.
destruct (classic (exists c, sf_spec.selected_candidate _ eliminated b c )); auto.
elim H. clear H.
rewrite sf_spec.exhausted_ballot_next_ranking_iff.
intros.
destruct (sf_spec.next_ranking_spec candidate eliminated b r); auto.
destruct H1 as [c[?[??]]].
elim H0. exists c.
split; eauto.
intro. destruct H4.
elim H4. eauto.
destruct H4 as [r' [??]].
assert (r = r'). { eapply sf_spec.next_ranking_unique; eauto. }
subst r'.
destruct H5 as [r1 [r2 [?[??]]]].
rewrite Forall_forall in H1.
apply H7. transitivity c; firstorder.
destruct H as [c ?].
intros [?|?].
destruct H as [? [r [??]]].
elim H0; eauto.
destruct H0 as [r [??]].
destruct H.
apply H.
right. exists r. split; auto.
Qed.
Lemma sf_forced_majority (e:election) (eliminated:candidate -> Prop) :
forall c n,
n > 0 ->
sf_spec.first_choices _ eliminated c e n ->
(forall c', sf_spec.participates _ c' e -> ~eliminated c' -> c' = c) ->
sf_spec.majority _ eliminated e c.
Proof.
induction e; simpl; intros.
red; simpl; intros.
inversion H3; subst; clear H3.
inversion H2; subst; clear H2.
inversion H0. subst n. omega.
red; intros.
assert ( winner_votes = n ) by
(eapply sf_spec.sf_first_choices_unique; eauto).
subst n. clear H0.
inversion H2; clear H2; subst.
inversion H3; clear H3; subst.
*
destruct n'.
simpl.
assert( n = 0 ).
{ cut (forall c', sf_spec.participates _ c' e -> ~eliminated c' -> c' = c).
clear -H7 H8.
revert n H7; induction e; intros.
+ inversion H7; subst; auto.
+ inversion H8; subst; clear H8; subst; auto.
inversion H7; subst; clear H7; subst; auto.
apply continuing_ballot_selects in H3.
destruct H3 as [c' ?].
elim H2.
replace c with c'; auto.
apply H; auto.
exists a. split; simpl; auto.
destruct H0 as [?[?[??]]].
exists x; split; auto.
eapply sf_spec.next_ranking_in_ballot; eauto.
eapply sf_spec.selected_candidate_not_eliminated; eauto.
apply IHe; eauto.
intros. apply H; auto.
destruct H0 as [b [??]].
exists b; intuition.
+ intros. apply H1; auto.
destruct H0 as [b [??]].
exists b; intuition.
}
subst n. omega.
cut (S n' * 2 > n). omega.
eapply (IHe c (S n')); auto.
omega.
intros. apply H1; auto.
destruct H0 as [b [??]].
exists b; intuition.
* apply continuing_ballot_selects in H5.
destruct H5 as [c' ?].
elim H4.
replace c with c'; auto.
apply H1; auto.
destruct H0.
destruct H2 as [r [??]].
exists a. split; simpl; auto.
exists r; split; simpl; auto.
eapply sf_spec.next_ranking_in_ballot; eauto.
assert (sf_spec.continuing_ballot _ eliminated a).
apply continuing_ballot_selects.
eauto.
eapply sf_spec.selected_candidate_not_eliminated; eauto.
* inversion H3; clear H3; subst.
destruct H4. elim H0. auto.
apply (IHe c winner_votes); auto.
intros. apply H1; auto.
destruct H0 as [b [??]].
exists b; intuition.
Qed.
Lemma nonzero_first_choices_selected :
forall (eliminated:candidate -> Prop) c e n,
sf_spec.first_choices _ eliminated c e n ->
n > 0 ->
exists b, In b e /\ sf_spec.selected_candidate _ eliminated b c.
Proof.
intros. induction H.
* omega.
* simpl; eauto.
* destruct IHfirst_choices as [b [??]]; simpl; eauto.
Qed.
Section sf_spec_existential_induction.
Variable e : election.
Variable P : (candidate -> Prop) -> Prop.
Variable Q : (candidate -> Prop) -> candidate -> Prop.
Variable Hbase : forall eliminated c,
P eliminated ->
sf_spec.majority _ eliminated e c ->
Q eliminated c.
Variable Hind : forall eliminated,
P eliminated ->
(exists c0 n, n > 0 /\ sf_spec.first_choices _ eliminated c0 e n) ->
sf_spec.no_majority _ eliminated e ->
exists loser,
sf_spec.is_loser _ eliminated e loser /\
let eliminated' := sf_spec.update_eliminated _ eliminated loser in
P eliminated' /\
(forall c, Q eliminated' c -> Q eliminated c).
Lemma sf_spec_existential_induction_aux : forall
(n:nat)
(viable:list candidate)
(eliminated:candidate -> Prop),
(forall c, In c viable -> sf_spec.participates _ c e) ->
(exists c, In c viable /\ exists n, n > 0 /\ sf_spec.first_choices _ eliminated c e n) ->
(forall c, eliminated c <-> sf_spec.participates _ c e /\ ~In c viable) ->
1 <= length viable <= n ->
P eliminated ->
exists c, Q eliminated c.
Proof.
induction n; [ simpl; intros; omega | ].
intros viable eliminated Hviable ????.
destruct (classic (exists c, sf_spec.majority _ eliminated e c)).
* destruct H3 as [c ?].
exists c. apply Hbase; auto.
* destruct (Hind eliminated) as [loser [?[??]]]; auto.
+ destruct H as [c [??]]; eauto.
+ destruct (list_remove_prop candidate viable (eq loser) loser)
as [viable' [?[??]]]; auto.
destruct (classic (In loser viable)); auto.
destruct H4 as [[??]?].
elim H4. apply H0. split; auto.
set ( eliminated' := sf_spec.update_eliminated _ eliminated loser).
assert (Hviable' : exists c', In c' viable').
{ destruct viable'; simpl; auto.
destruct H as [c [? [nc [??]]]].
exists c.
apply H8 in H. destruct H. elim H. subst c.
elim H3. exists loser.
apply sf_forced_majority with nc; auto.
intros.
destruct (H8 c'); auto.
destruct (classic (In c' viable)); auto.
elim H12.
apply H0. split; auto.
elim H13.
eauto.
}
destruct (IHn viable' eliminated') as [c ?]; auto.
- intros. apply H9 in H10. intuition.
- destruct H as [c [? [cn [??]]]].
destruct (classic (c = loser)).
subst c.
destruct Hviable' as [c' ?].
exists c'. split; auto.
destruct (sf_spec.sf_first_choices_total candidate eliminated' e c') as [n' ?].
destruct (sf_spec.sf_first_choices_total candidate eliminated e c') as [n'' ?].
exists n'; split; auto.
cut (n'' <= n'). intro Hn''.
cut (cn <= n''). omega.
{ destruct H4.
apply (H15 c'); auto.
split.
intro. apply H0 in H16. intuition.
apply H19.
apply H9 in H12; intuition.
apply Hviable.
apply H9 in H12. intuition.
}
{ apply first_choices_monotone with eliminated eliminated' e c'; auto.
intro. hnf in H15. apply H9 in H12.
destruct H15.
apply H0 in H15.
intuition.
intuition.
intros. hnf. auto.
}
exists c; intuition.
apply H8 in H. intuition.
elim H12; auto.
destruct (sf_spec.sf_first_choices_total candidate eliminated' e c) as [cn' ?].
exists cn'; split; auto.
cut (cn <= cn'). omega.
apply first_choices_monotone with eliminated eliminated' e c; auto.
intro. hnf in H15.
destruct H15.
apply H0 in H15.
intuition.
elim H12; auto.
intros. hnf. auto.
- unfold eliminated'.
unfold sf_spec.update_eliminated.
intuition.
apply H0 in H12; intuition.
apply H0 in H12; intuition.
apply H14. apply H9. auto.
subst c.
destruct H4 as [[??]?]; auto.
subst c; auto.
apply H9 in H1.
intuition.
destruct (classic (c = loser)).
subst c. auto.
left.
apply H0.
split; auto.
intros. apply H13.
apply H8 in H14.
intuition.
subst. intuition.
- split; auto.
destruct viable'; simpl; auto.
destruct Hviable' as [?[]].
omega.
omega.
- exists c.
apply H6. auto.
Qed.
Lemma sf_spec_existential_induction : forall (eliminated:candidate -> Prop),
(forall c0, eliminated c0 -> sf_spec.participates _ c0 e) ->
(exists c0 n, n > 0 /\ sf_spec.first_choices _ eliminated c0 e n) ->
P eliminated -> exists c, Q eliminated c.
Proof.
intros.
destruct (list_remove_prop_weak _ (all_candidates e) eliminated)
as [viable [?[??]]].
apply (sf_spec_existential_induction_aux (length viable) viable); auto.
* intros. apply H4 in H5. destruct H5.
apply (all_candidates_participates c e); auto.
* destruct H0 as [c [n[??]]].
exists c; split; eauto.
destruct (nonzero_first_choices_selected eliminated c e n) as [b [??]]; auto.
generalize (sf_spec.selected_candidate_not_eliminated _ _ b c H7); intro.
assert ( sf_spec.participates candidate c e ).
destruct H7.
red; exists b. split; auto.
destruct H9 as [r [??]].
exists r; split; auto.
eapply sf_spec.next_ranking_in_ballot; eauto.
generalize (all_candidates_participates c e); intros [??].
apply H11 in H9.
apply H3 in H9.
intuition.
* intuition.
apply H4 in H6. intuition.
generalize (all_candidates_participates c e); intros [??].
apply H8 in H6.
apply H3 in H6.
intuition.
* intuition.
destruct H0 as [c [n [??]]].
destruct (nonzero_first_choices_selected eliminated c e n) as [b [??]]; auto.
generalize (sf_spec.selected_candidate_not_eliminated _ _ b c H7); intro.
assert ( sf_spec.participates candidate c e ).
destruct H7.
red; exists b. split; auto.
destruct H9 as [r [??]].
exists r; split; auto.
eapply sf_spec.next_ranking_in_ballot; eauto.
generalize (all_candidates_participates c e); intros [??].
apply H11 in H9.
apply H3 in H9.
destruct H9.
- destruct viable. elim H9.
simpl. omega.
- contradiction.
Qed.
End sf_spec_existential_induction.
Section sf_loser_exists.
Variable (e:election).
Variable (eliminated:candidate -> Prop).
Lemma sf_loser_exists_aux :
forall (n:nat) c,
~eliminated c ->
sf_spec.participates _ c e ->
sf_spec.first_choices _ eliminated c e n ->
exists c', sf_spec.is_loser _ eliminated e c'.
Proof.
induction n using (well_founded_induction lt_wf).
intros.
destruct (classic (exists c', ~eliminated c' /\
sf_spec.participates _ c' e /\
exists n', n' < n /\
sf_spec.first_choices _ eliminated c' e n')).
* destruct H3 as [c' [?[?[n' [??]]]]].
apply (H n') with c'; auto.
* exists c. split; auto. split; auto.
intros.
destruct (classic (n0 <= m)); auto.
destruct H4.
elim H3. exists c'. split; auto. split; auto.
assert( n = n0 ).
eapply sf_spec.sf_first_choices_unique; eauto.
subst n0.
exists m. split; auto. omega.
Qed.
Lemma sf_loser_exists :
(exists c, ~eliminated c /\ sf_spec.participates _ c e) ->
exists c, sf_spec.is_loser _ eliminated e c.
Proof.
intros.
destruct H as [c [??]].
destruct (sf_spec.sf_first_choices_total _ eliminated e c) as [n ?].
apply sf_loser_exists_aux with n c; auto.
Qed.
End sf_loser_exists.
Theorem sf_spec_total e (eliminated:candidate -> Prop) :
(forall c0, eliminated c0 -> sf_spec.participates _ c0 e) ->
(exists c n, n > 0 /\ sf_spec.first_choices _ eliminated c e n) ->
exists c, sf_spec.winner _ e eliminated c.
Proof.
intros.
apply sf_spec_existential_induction with e (fun _ => True); intuition.
* apply sf_spec.winner_now; auto.
* destruct (sf_loser_exists e eliminated0) as [loser ?]; auto.
+ destruct H2 as [c [n [??]]].
destruct (nonzero_first_choices_selected eliminated0 c e n) as [b [??]]; auto.
exists c.
generalize (sf_spec.selected_candidate_not_eliminated _ _ b c H6); intro.
split; auto.
destruct H6.
red; exists b. split; auto.
destruct H8 as [r [??]].
exists r; split; auto.
eapply sf_spec.next_ranking_in_ballot; eauto.
+ exists loser; intuition.
apply sf_spec.winner_elimination with loser; auto.
Qed.
Definition mutual_majority_invariant (e:election) (group:list candidate) (eliminated:candidate -> Prop) :=
exists c, In c group /\ ~eliminated c.
Lemma majority_satisfies_monotone (P Q:ballot -> Prop) :
forall e,
(forall b, P b -> Q b) ->
majority_satisfies _ P e ->
majority_satisfies _ Q e.
Proof.
intros e HPQ [nmaj [ntotal [?[??]]]].
destruct (count_monotone _ P Q e HPQ nmaj H) as [nmaj' [??]].
exists nmaj'. exists ntotal. intuition.
Qed.
Lemma selected_candidate_tail (eliminated : candidate -> Prop) :
forall a h c,
sf_spec.does_not_select _ eliminated a ->
sf_spec.selected_candidate _ eliminated h c ->
sf_spec.selected_candidate _ eliminated (a :: h) c.
Proof.
intros. destruct H0. split.
intro. apply H0.
destruct H2.
left.
intros [q ?].
apply H2. exists q.
apply sf_spec.next_ranking_eliminated; auto.
rewrite Forall_forall.
intros.
destruct H. subst a. elim H4.
destruct H as [c' [?[??]]].
rewrite Forall_forall in H.
replace x with c'; auto.
intros [?[?[?[??]]]].
destruct H. subst a. elim H4.
apply H6.
destruct H as [c' [?[??]]].
rewrite Forall_forall in H.
transitivity c'; auto. symmetry; auto.
right.
destruct H2 as [q [??]].
exists q; split; auto.
inversion H2; clear H2; subst; auto.
elimtype False.
destruct H.
subst q. elim H6.
destruct H as [c' [?[??]]].
rewrite Forall_forall in H.
destruct H8.
destruct H5 as [?[?[?[??]]]].
apply H8.
transitivity c'; auto. symmetry; auto.
apply H5.
replace c0 with c'; auto.
destruct H1 as [r [??]].
exists r; split; auto.
apply sf_spec.next_ranking_eliminated; auto.
rewrite Forall_forall. intros.
destruct H. subst a. elim H3.
destruct H as [c' [?[??]]].
rewrite Forall_forall in H.
replace x with c'; auto.
intros [?[?[?[??]]]].
apply H5.
destruct H. subst. elim H3.
destruct H as [c' [?[??]]].
rewrite Forall_forall in H.
transitivity c'; auto. symmetry; auto.
Qed.
Lemma sf_total_le_total (eliminated : candidate -> Prop) :
forall e n n',
sf_spec.total_selected _ eliminated e n ->
total_votes _ e n' ->
n <= n'.
Proof.
induction e; intros.
inversion H. inversion H0. auto.
inversion H; subst; clear H;
inversion H0; subst; clear H0; auto.
cut (n0 <= n). omega.
apply IHe; auto.
elim H2.
rewrite (continuing_ballot_selects a eliminated) in H3.
destruct H3 as [c ?].
clear -H.
destruct H. destruct H0 as [r [??]].
induction H0.
rewrite Forall_forall in H0.
destruct r'.
destruct IHnext_ranking as [c' ?]; auto.
{ intro. elim H.
destruct H4.
left. intros [q ?].
apply H4. exists q.
inversion H5; clear H5; subst; auto.
elim H8.
destruct H4 as [q [??]].
right. exists q; split; auto.
apply sf_spec.next_ranking_eliminated; auto.
}
exists c'.
apply first_skip. auto.
exists c0. apply first_top.
split; simpl; auto.
intros.
destruct (classic (c0 = c')); auto.
elim H2.
exists c0, c'. simpl; intuition.
exists c.
apply first_top.
split; auto.
intros.
destruct (classic (c = c')); auto.
elim H.
right.
exists r.
split.
apply sf_spec.next_ranking_valid with c0; auto.
exists c. exists c'; intuition.
Qed.
Theorem sf_mutual_majority :
mutual_majority_criterion candidate sf_may_win_election.
Proof.
red; intros. red.
cut (forall (eliminated:candidate -> Prop) c,
mutual_majority_invariant e group eliminated ->
sf_spec.winner _ e eliminated c ->
In c group).
{ intuition.
destruct (sf_spec_total e (fun _ => False)).
intuition.
destruct (majority_satisfies_ballot_exists _ _ H0) as [b [??]].
red in H2.
destruct H as [[cin ?] [cout ?]].
generalize (H2 cin cout H H4); intros.
clear -H2 H3 H5.
{ induction e; intros.
* elim H3.
* simpl in H3. destruct H3.
+ clear IHe. subst b.
clear H2.
induction H5.
- destruct (sf_spec.sf_first_choices_total _ (fun _ => False) ((r::b) :: e) cin) as [n ?].
exists cin. exists n. split; auto.
inversion H0; subst; clear H0.
omega.
elim H3; clear H3. split.
intro. destruct H0.
apply H0.
exists r.
apply sf_spec.next_ranking_valid with cin; auto.
destruct H. auto.
destruct H0 as [r' [??]].
assert (r = r').
eapply sf_spec.next_ranking_unique; eauto.
apply sf_spec.next_ranking_valid with cin.
destruct H; auto.
right; auto.
subst r'.
destruct H.
destruct H1 as [c1 [c2 [?[??]]]].
elim H4.
transitivity cin; firstorder.
exists r. split; auto.
apply sf_spec.next_ranking_valid with cin.
destruct H; auto.
right; auto.
destruct H; auto.
- destruct IHprefers as [c [n [??]]].
exists c. exists n. split; auto.
inversion H0; subst; clear H0.
apply sf_spec.first_choices_selected.
destruct H3. split.
intro. apply H0.
destruct H2.
left. intro.
apply H2.
destruct H3 as [r ?].
exists r. apply sf_spec.next_ranking_eliminated.
rewrite Forall_forall. simpl; auto.
intros [?[?[??]]]. elim H4.
auto.
right.
destruct H2 as [r [??]].
exists r; split; auto.
inversion H2; subst; clear H2.
auto.
destruct H3 as [?[?[??]]]. elim H2.
destruct H1 as [r [??]].
exists r; split; auto.
apply sf_spec.next_ranking_eliminated.
rewrite Forall_forall. simpl; auto.
intros [?[?[??]]]. elim H3.
auto.
auto.
apply sf_spec.first_choices_not_selected; auto.
intro. apply H3.
destruct H0. split.
intro. apply H0.
destruct H2. left.
intro. apply H2.
destruct H4 as [r ?].
exists r.
inversion H4; subst; clear H4.
auto.
elim H9.
right.
destruct H2 as [r [??]].
exists r; split; auto.
apply sf_spec.next_ranking_eliminated.
rewrite Forall_forall; auto.
intros [?[?[??]]]. elim H7.
auto.
destruct H1 as [r [??]].
exists r. split; auto.
inversion H1; subst; clear H1.
auto.
elim H2.
- destruct IHprefers as [c [n [??]]].
destruct (sf_spec.sf_first_choices_total _ (fun _ => False) ((r::b)::e) c').
exists c'. exists x. split; auto.
inversion H4; subst; clear H4.
omega.
elim H8.
split.
intro. destruct H4.
apply H4.
exists r.
apply sf_spec.next_ranking_valid with c'.
destruct H1. auto.
auto.
destruct H4 as [r' [??]].
inversion H4; subst; clear H4.
destruct H1.
rewrite Forall_forall in H11.
apply H11 in H1. auto.
destruct H6 as [?[?[?[??]]]].
destruct H1.
elim H7.
transitivity c'; auto.
symmetry; auto.
exists r; split; auto.
2: destruct H1; auto.
apply sf_spec.next_ranking_valid with c'.
destruct H1; auto.
auto.
+ destruct IHe as [c [n [??]]]; auto.
destruct (classic (sf_spec.selected_candidate _ (fun _ => False) a c)).
exists c. exists (S n).
split. omega.
apply sf_spec.first_choices_selected; auto.
exists c. exists n.
split; auto.
apply sf_spec.first_choices_not_selected; auto.
}
exists x; split; auto.
apply (H1 (fun _ => False)); auto.
red.
destruct H.
destruct H as [c ?]. eauto.
apply (H1 (fun _ => False)); auto.
red; simpl; auto.
destruct H.
destruct H as [c' ?]. eauto.
}
intros.
induction H2.
(* a winning candidate is always selected from the group *)
* red in H0.
red in H2.
destruct H0 as [n [t [?[??]]]].
destruct (sf_spec.sf_first_choices_total _ eliminated election0 winning_candidate) as [nwin ?].
destruct (sf_spec.total_selected_total _ eliminated election0) as [ntotal ?].
assert (nwin * 2 > ntotal) by (apply H2; auto). clear H2.
destruct (classic (In winning_candidate group)); auto.
elimtype False.
destruct H1 as [cg [??]].
assert( ntotal <= t ).
{ eapply sf_total_le_total; eauto. }
assert( ntotal < n + nwin ) by omega.
assert( n + nwin <= ntotal ).
{ revert cg H1 H8 H0 H2 H5 H6. clear. revert n nwin ntotal.
induction election0; simpl; intros.
* inversion H0; subst; clear H0.
inversion H5; subst; clear H5.
simpl. omega.
* inversion H6; clear H6; subst.
inversion H0; clear H0; subst;
inversion H5; clear H5; subst.
{ elimtype False.
hnf in H6.
generalize (H6 cg winning_candidate H1 H2); intro.
clear IHelection0 H9 H10 H11.
assert (Hnelim : ~eliminated winning_candidate) by
(eapply sf_spec.selected_candidate_not_eliminated; eauto).
clear H6.
induction H.
- inversion H3; clear H3; subst.
destruct H5 as [r' [??]].
destruct H.
inversion H3; clear H3; subst.
rewrite Forall_forall in H10.
elim H8. apply H10. auto.
elim H2.
replace winning_candidate with cg; auto.
- apply IHprefers; auto.
intro. apply H4.
destruct H0.
left. intros [q ?]. apply H0. exists q.
inversion H5; clear H5; subst. auto.
elim H9.
right.
destruct H0 as [q [??]].
exists q. split; auto.
constructor.
rewrite Forall_forall. simpl. intuition.
intro. destruct H6 as [?[?[??]]]. elim H6.
auto.
destruct H3. split; auto.
intro. apply H0.
clear -H5.
destruct H5.
left.
intros [r ?].
apply H. exists r. inversion H0; subst; auto.
elim H3.
right.
destruct H as [r [??]].
exists r; split; auto.
constructor; auto.
intros [?[?[??]]]. elim H1.
destruct H3 as [r [??]].
exists r; split; auto.
inversion H3; clear H3; subst; auto.
elim H9.
- destruct H3.
destruct H7 as [q [??]].
inversion H7; clear H7; subst.
assert (sf_spec.continuing_ballot candidate eliminated b).
{ intro. destruct H7.
apply H7; eauto.
destruct H7 as [q' [??]].
apply H3.
right.
exists q'. split; auto.
apply sf_spec.next_ranking_eliminated; auto.
}
apply IHprefers; auto.
split; auto.
exists q; split; auto.
destruct H5.
apply H0.
apply H7. auto.
}
- cut (n1 + nwin <= n0). omega.
eapply IHelection0; eauto.
- cut (n + n' <= n0). omega.
eapply IHelection0; eauto.
- cut (n + nwin <= n0). omega.
eapply IHelection0; eauto.
- inversion H5; clear H5; subst; auto.
elimtype False.
destruct H6.
apply H; auto.
inversion H0; clear H0; subst; auto.
hnf in H5.
elimtype False.
generalize (H5 cg winning_candidate H1 H2).
clear H11 H5 n0 H10 H6 H9.
intro.
induction H.
destruct H4.
elim H0. exists r.
apply sf_spec.next_ranking_valid with cg.
destruct H; auto.
right; auto.
destruct H0 as [q [??]].
inversion H0; clear H0; subst.
rewrite Forall_forall in H6.
apply H8. apply H6.
destruct H; auto.
destruct H3 as [?[?[?[??]]]].
destruct H.
apply H4.
transitivity cg; auto.
symmetry; auto.
apply IHprefers.
destruct H4.
left; intro.
apply H0.
destruct H3 as [q ?].
exists q.
apply sf_spec.next_ranking_eliminated.
rewrite Forall_forall. simpl. intuition.
intros [?[?[?[??]]]]. elim H4.
auto.
right.
destruct H0 as [q [??]].
exists q. split; auto.
inversion H0; clear H0; subst.
auto.
elim H6.
destruct (classic (eliminated c')).
apply IHprefers.
destruct H4.
left.
intros [q ?].
apply H4.
exists q.
apply sf_spec.next_ranking_eliminated.
rewrite Forall_forall.
intros.
destruct H3.
replace x with c'; auto.
intros [?[?[?[??]]]].
apply H11; auto.
destruct H3.
transitivity c'; auto. symmetry; auto.
auto.
destruct H4 as [q [??]].
right.
exists q.
split; auto.
inversion H4; clear H4; subst; auto.
destruct H13.
destruct H4 as [?[?[?[??]]]].
elim H10.
destruct H3.
transitivity c'; auto. symmetry; auto.
elim H4.
replace c with c'; auto.
destruct H3; auto.
destruct H4.
apply H4.
exists r.
apply sf_spec.next_ranking_valid with c'; auto.
destruct H3; auto.
destruct H4 as [q [??]].
inversion H4; clear H4; subst; auto.
rewrite Forall_forall in H11.
apply H6. apply H11. destruct H3; auto.
destruct H7 as [?[?[?[??]]]].
apply H9.
destruct H3.
transitivity c'; auto. symmetry; auto.
eapply IHelection0; eauto.
}
omega.
(* After every elimination, some member from the group remains in the running, because otherwise the last
remaining member of the group must have had a majority. *)
* apply IHwinner; auto. clear IHwinner. hnf.
destruct (classic (exists c, In c group /\ ~eliminated' c)); auto.
assert (forall c, In c group -> eliminated' c).
intros.
destruct (classic (eliminated' c)); auto.
elim H5; eauto.
elimtype False. clear H5.
unfold eliminated' in H6.
unfold sf_spec.update_eliminated in H6.
elim H2.
destruct H1 as [winner [??]].
exists winner.
hnf; intros.
destruct H0 as [n [t [?[??]]]].
assert (n <= winner_votes).
{
assert (winner = loser).
{
destruct (H6 _ H1); auto.
elim H5; auto.
}
clear -H H0 H1 H5 H6 H8 H11.
subst loser.
revert n H0. induction H8; intros.
* inversion H0; clear H0; subst; auto.
* inversion H2; clear H2; subst; auto.
cut (n0 <= n'). omega.
apply IHfirst_choices; auto.
* inversion H2; clear H2; subst; auto.
elim H0.
clear t n n1 IHfirst_choices H0 H8 H10.
destruct H as [_ [cOther ?]].
specialize (H7 winner).
induction h.
- generalize (H7 cOther H1 H).
intros. inversion H0.
- destruct (sf_spec.ranking_cases _ eliminated a) as [?|[?|?]].
+ generalize (H7 cOther H1 H); intros.
inversion H2; clear H2; subst.
destruct H0 as [?[?[?[??]]]].
elim H3. destruct H4.
transitivity winner; auto. symmetry; auto.
destruct H0 as [?[?[?[??]]]]. elim H0.
destruct H0 as [?[?[?[??]]]].
destruct H10.
elim H3.
transitivity c'; auto. symmetry; auto.
+ destruct H0 as [c [?[??]]].
assert (c = winner).
{ destruct (classic (In c group)).
apply H6 in H4. intuition.
generalize (H7 c H1 H4). intros.
inversion H8; clear H8; subst.
destruct H10.
symmetry; auto.
inversion H2.
elim H12.
destruct H13. auto.
}
subst c.
split.
intros [?|?].
elim H4.
exists a. apply sf_spec.next_ranking_valid with winner; auto.
destruct H4 as [q [??]].
inversion H4; clear H4; subst.
rewrite Forall_forall in H11.
elim H5. apply H11. auto.
rewrite Forall_forall in H0.
destruct H8 as [?[?[?[??]]]].
elim H9.
transitivity winner; auto. symmetry; auto.
exists a; split; auto.
apply sf_spec.next_ranking_valid with winner; auto.
+
apply selected_candidate_tail; auto.
apply IHh.
intros.
generalize (H7 cout H2 H3).
intros.
inversion H4; clear H4; subst; auto.
destruct H0.
subst a. destruct H9. elim H0.
destruct H0 as [c' [?[??]]].
rewrite Forall_forall in H0.
destruct H9.
assert (c' = winner) by auto.
subst c'.
elim H5; auto.
}
assert (total_votes <= t).
{ eapply sf_total_le_total; eauto. }
omega.
Qed.
End sf_spec_properties.
Check sf_mutual_majority.
Print Assumptions sf_mutual_majority.
Check sf_spec_total.
Print Assumptions sf_spec_total.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_V
`define SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_V
/**
* o2bb2a: 2-input NAND and 2-input OR into 2-input AND.
*
* X = (!(A1 & A2) & (B1 | B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_hdll__o2bb2a (
X ,
A1_N,
A2_N,
B1 ,
B2
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
// Module supplies
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire nand0_out ;
wire or0_out ;
wire and0_out_X;
// Name Output Other arguments
nand nand0 (nand0_out , A2_N, A1_N );
or or0 (or0_out , B2, B1 );
and and0 (and0_out_X, nand0_out, or0_out);
buf buf0 (X , and0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__O2BB2A_BEHAVIORAL_V |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2014 Xilinx, Inc.
// All Right Reserved.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2014.2
// \ \ Description : Xilinx Timing Simulation Library Component
// / / 48-bit Multi-Functional Arithmetic Block
// /___/ /\ Filename : DSP_MULTIPLIER.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
// 07/15/12 - Migrate from E1.
// 12/10/12 - Add dynamic registers
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module DSP_MULTIPLIER #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter AMULTSEL = "A",
parameter BMULTSEL = "B",
parameter USE_MULT = "MULTIPLY"
)(
output AMULT26,
output BMULT17,
output [44:0] U,
output [44:0] V,
input [26:0] A2A1,
input [26:0] AD_DATA,
input [17:0] B2B1
);
// define constants
localparam MODULE_NAME = "DSP_MULTIPLIER";
localparam in_delay = 0;
localparam out_delay = 0;
localparam inclk_delay = 0;
localparam outclk_delay = 0;
// Parameter encodings and registers
localparam AMULTSEL_A = 0;
localparam AMULTSEL_AD = 1;
localparam BMULTSEL_AD = 1;
localparam BMULTSEL_B = 0;
localparam USE_MULT_DYNAMIC = 1;
localparam USE_MULT_MULTIPLY = 0;
localparam USE_MULT_NONE = 2;
// include dynamic registers - XILINX test only
reg trig_attr = 1'b0;
`ifdef XIL_DR
`include "DSP_MULTIPLIER_dr.v"
`else
localparam [16:1] AMULTSEL_REG = AMULTSEL;
localparam [16:1] BMULTSEL_REG = BMULTSEL;
localparam [64:1] USE_MULT_REG = USE_MULT;
`endif
wire AMULTSEL_BIN;
wire BMULTSEL_BIN;
wire [1:0] USE_MULT_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
wire AMULT26_out;
wire BMULT17_out;
wire [44:0] U_out;
wire [44:0] V_out;
`ifdef XIL_TIMING
wire AMULT26_delay;
wire BMULT17_delay;
wire [44:0] U_delay;
wire [44:0] V_delay;
`endif
wire [17:0] B2B1_in;
wire [26:0] A2A1_in;
wire [26:0] AD_DATA_in;
`ifdef XIL_TIMING
wire [17:0] B2B1_delay;
wire [26:0] A2A1_delay;
wire [26:0] AD_DATA_delay;
`endif
// wire [17:0] b_mult_mux;
// wire [26:0] a_mult_mux;
reg [17:0] b_mult_mux;
reg [26:0] a_mult_mux;
reg [44:0] mult;
reg [43:0] ps_u_mask = 44'h55555555555;
reg [43:0] ps_v_mask = 44'haaaaaaaaaaa;
assign AMULT26 = AMULT26_out;
assign BMULT17 = BMULT17_out;
assign U = U_out;
assign V = V_out;
// inputs with no timing checks
assign #(in_delay) A2A1_delay = A2A1;
assign #(in_delay) AD_DATA_delay = AD_DATA;
assign #(in_delay) B2B1_delay = B2B1;
assign A2A1_in = A2A1_delay;
assign AD_DATA_in = AD_DATA_delay;
assign B2B1_in = B2B1_delay;
assign A2A1_in = A2A1;
assign AD_DATA_in = AD_DATA;
assign B2B1_in = B2B1;
assign AMULTSEL_BIN =
(AMULTSEL_REG == "A") ? AMULTSEL_A :
(AMULTSEL_REG == "AD") ? AMULTSEL_AD :
AMULTSEL_A;
assign BMULTSEL_BIN =
(BMULTSEL_REG == "B") ? BMULTSEL_B :
(BMULTSEL_REG == "AD") ? BMULTSEL_AD :
BMULTSEL_B;
assign USE_MULT_BIN =
(USE_MULT_REG == "MULTIPLY") ? USE_MULT_MULTIPLY :
(USE_MULT_REG == "DYNAMIC") ? USE_MULT_DYNAMIC :
(USE_MULT_REG == "NONE") ? USE_MULT_NONE :
USE_MULT_MULTIPLY;
`ifndef XIL_TIMING
initial begin
$display("Error: [Unisim %s-140] SIMPRIM primitive is not intended for direct instantiation in RTL or functional netlists. This primitive is only available in the SIMPRIM library for implemented netlists, please ensure you are pointing to the correct library. Instance %m", MODULE_NAME);
#100;
$finish;
end
`endif
initial begin
#1;
trig_attr = ~trig_attr;
end
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((AMULTSEL_REG != "A") &&
(AMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-104] AMULTSEL attribute is set to %s. Legal values for this attribute are A or AD. Instance: %m", MODULE_NAME, AMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((BMULTSEL_REG != "B") &&
(BMULTSEL_REG != "AD"))) begin
$display("Error: [Unisim %s-110] BMULTSEL attribute is set to %s. Legal values for this attribute are B or AD. Instance: %m", MODULE_NAME, BMULTSEL_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((USE_MULT_REG != "MULTIPLY") &&
(USE_MULT_REG != "DYNAMIC") &&
(USE_MULT_REG != "NONE"))) begin
$display("Error: [Unisim %s-142] USE_MULT attribute is set to %s. Legal values for this attribute are MULTIPLY, DYNAMIC or NONE. Instance: %m", MODULE_NAME, USE_MULT_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) $finish;
end
//assign a_mult_mux = (AMULTSEL_BIN == AMULTSEL_A) ? A2A1_in : AD_DATA_in;
//assign b_mult_mux = (BMULTSEL_BIN == BMULTSEL_B) ? B2B1_in : AD_DATA_in;
always @ (*) begin
if (AMULTSEL_BIN == AMULTSEL_A) a_mult_mux = A2A1_in;
else a_mult_mux = AD_DATA_in;
end
always @ (*) begin
if (BMULTSEL_BIN == BMULTSEL_B) b_mult_mux = B2B1_in;
else b_mult_mux = AD_DATA_in;
end
assign AMULT26_out = a_mult_mux[26];
assign BMULT17_out = b_mult_mux[17];
// U[44],V[44] 11 when mult[44]=0, 10 when mult[44]=1
assign U_out = {1'b1, mult[43:0] & ps_u_mask};
assign V_out = {~mult[44], mult[43:0] & ps_v_mask};
always @(*) begin
if (USE_MULT_BIN == USE_MULT_NONE) mult = 45'b0;
else mult = ({{18{a_mult_mux[26]}},a_mult_mux} * {{27{b_mult_mux[17]}},b_mult_mux});
end
specify
(A2A1[0] => U[10]) = (0:0:0, 0:0:0);
(A2A1[0] => U[11]) = (0:0:0, 0:0:0);
(A2A1[0] => U[12]) = (0:0:0, 0:0:0);
(A2A1[0] => U[13]) = (0:0:0, 0:0:0);
(A2A1[0] => U[14]) = (0:0:0, 0:0:0);
(A2A1[0] => U[15]) = (0:0:0, 0:0:0);
(A2A1[0] => U[16]) = (0:0:0, 0:0:0);
(A2A1[0] => U[17]) = (0:0:0, 0:0:0);
(A2A1[0] => U[18]) = (0:0:0, 0:0:0);
(A2A1[0] => U[19]) = (0:0:0, 0:0:0);
(A2A1[0] => U[1]) = (0:0:0, 0:0:0);
(A2A1[0] => U[20]) = (0:0:0, 0:0:0);
(A2A1[0] => U[21]) = (0:0:0, 0:0:0);
(A2A1[0] => U[2]) = (0:0:0, 0:0:0);
(A2A1[0] => U[3]) = (0:0:0, 0:0:0);
(A2A1[0] => U[4]) = (0:0:0, 0:0:0);
(A2A1[0] => U[5]) = (0:0:0, 0:0:0);
(A2A1[0] => U[6]) = (0:0:0, 0:0:0);
(A2A1[0] => U[7]) = (0:0:0, 0:0:0);
(A2A1[0] => U[8]) = (0:0:0, 0:0:0);
(A2A1[0] => U[9]) = (0:0:0, 0:0:0);
(A2A1[0] => V[0]) = (0:0:0, 0:0:0);
(A2A1[0] => V[10]) = (0:0:0, 0:0:0);
(A2A1[0] => V[11]) = (0:0:0, 0:0:0);
(A2A1[0] => V[12]) = (0:0:0, 0:0:0);
(A2A1[0] => V[13]) = (0:0:0, 0:0:0);
(A2A1[0] => V[14]) = (0:0:0, 0:0:0);
(A2A1[0] => V[15]) = (0:0:0, 0:0:0);
(A2A1[0] => V[16]) = (0:0:0, 0:0:0);
(A2A1[0] => V[17]) = (0:0:0, 0:0:0);
(A2A1[0] => V[18]) = (0:0:0, 0:0:0);
(A2A1[0] => V[19]) = (0:0:0, 0:0:0);
(A2A1[0] => V[20]) = (0:0:0, 0:0:0);
(A2A1[0] => V[4]) = (0:0:0, 0:0:0);
(A2A1[0] => V[5]) = (0:0:0, 0:0:0);
(A2A1[0] => V[6]) = (0:0:0, 0:0:0);
(A2A1[0] => V[7]) = (0:0:0, 0:0:0);
(A2A1[0] => V[8]) = (0:0:0, 0:0:0);
(A2A1[0] => V[9]) = (0:0:0, 0:0:0);
(A2A1[10] => U[11]) = (0:0:0, 0:0:0);
(A2A1[10] => U[12]) = (0:0:0, 0:0:0);
(A2A1[10] => U[13]) = (0:0:0, 0:0:0);
(A2A1[10] => U[14]) = (0:0:0, 0:0:0);
(A2A1[10] => U[15]) = (0:0:0, 0:0:0);
(A2A1[10] => U[16]) = (0:0:0, 0:0:0);
(A2A1[10] => U[17]) = (0:0:0, 0:0:0);
(A2A1[10] => U[18]) = (0:0:0, 0:0:0);
(A2A1[10] => U[19]) = (0:0:0, 0:0:0);
(A2A1[10] => U[20]) = (0:0:0, 0:0:0);
(A2A1[10] => U[21]) = (0:0:0, 0:0:0);
(A2A1[10] => U[22]) = (0:0:0, 0:0:0);
(A2A1[10] => U[23]) = (0:0:0, 0:0:0);
(A2A1[10] => U[24]) = (0:0:0, 0:0:0);
(A2A1[10] => U[25]) = (0:0:0, 0:0:0);
(A2A1[10] => U[26]) = (0:0:0, 0:0:0);
(A2A1[10] => U[27]) = (0:0:0, 0:0:0);
(A2A1[10] => U[28]) = (0:0:0, 0:0:0);
(A2A1[10] => U[29]) = (0:0:0, 0:0:0);
(A2A1[10] => U[30]) = (0:0:0, 0:0:0);
(A2A1[10] => U[31]) = (0:0:0, 0:0:0);
(A2A1[10] => V[10]) = (0:0:0, 0:0:0);
(A2A1[10] => V[11]) = (0:0:0, 0:0:0);
(A2A1[10] => V[12]) = (0:0:0, 0:0:0);
(A2A1[10] => V[13]) = (0:0:0, 0:0:0);
(A2A1[10] => V[14]) = (0:0:0, 0:0:0);
(A2A1[10] => V[15]) = (0:0:0, 0:0:0);
(A2A1[10] => V[16]) = (0:0:0, 0:0:0);
(A2A1[10] => V[17]) = (0:0:0, 0:0:0);
(A2A1[10] => V[18]) = (0:0:0, 0:0:0);
(A2A1[10] => V[19]) = (0:0:0, 0:0:0);
(A2A1[10] => V[20]) = (0:0:0, 0:0:0);
(A2A1[10] => V[21]) = (0:0:0, 0:0:0);
(A2A1[10] => V[22]) = (0:0:0, 0:0:0);
(A2A1[10] => V[23]) = (0:0:0, 0:0:0);
(A2A1[10] => V[24]) = (0:0:0, 0:0:0);
(A2A1[10] => V[25]) = (0:0:0, 0:0:0);
(A2A1[10] => V[26]) = (0:0:0, 0:0:0);
(A2A1[10] => V[27]) = (0:0:0, 0:0:0);
(A2A1[10] => V[28]) = (0:0:0, 0:0:0);
(A2A1[10] => V[29]) = (0:0:0, 0:0:0);
(A2A1[10] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[12]) = (0:0:0, 0:0:0);
(A2A1[11] => U[13]) = (0:0:0, 0:0:0);
(A2A1[11] => U[14]) = (0:0:0, 0:0:0);
(A2A1[11] => U[15]) = (0:0:0, 0:0:0);
(A2A1[11] => U[16]) = (0:0:0, 0:0:0);
(A2A1[11] => U[17]) = (0:0:0, 0:0:0);
(A2A1[11] => U[18]) = (0:0:0, 0:0:0);
(A2A1[11] => U[19]) = (0:0:0, 0:0:0);
(A2A1[11] => U[20]) = (0:0:0, 0:0:0);
(A2A1[11] => U[21]) = (0:0:0, 0:0:0);
(A2A1[11] => U[22]) = (0:0:0, 0:0:0);
(A2A1[11] => U[23]) = (0:0:0, 0:0:0);
(A2A1[11] => U[24]) = (0:0:0, 0:0:0);
(A2A1[11] => U[25]) = (0:0:0, 0:0:0);
(A2A1[11] => U[26]) = (0:0:0, 0:0:0);
(A2A1[11] => U[27]) = (0:0:0, 0:0:0);
(A2A1[11] => U[28]) = (0:0:0, 0:0:0);
(A2A1[11] => U[29]) = (0:0:0, 0:0:0);
(A2A1[11] => U[30]) = (0:0:0, 0:0:0);
(A2A1[11] => U[31]) = (0:0:0, 0:0:0);
(A2A1[11] => U[32]) = (0:0:0, 0:0:0);
(A2A1[11] => V[11]) = (0:0:0, 0:0:0);
(A2A1[11] => V[12]) = (0:0:0, 0:0:0);
(A2A1[11] => V[13]) = (0:0:0, 0:0:0);
(A2A1[11] => V[14]) = (0:0:0, 0:0:0);
(A2A1[11] => V[15]) = (0:0:0, 0:0:0);
(A2A1[11] => V[16]) = (0:0:0, 0:0:0);
(A2A1[11] => V[17]) = (0:0:0, 0:0:0);
(A2A1[11] => V[18]) = (0:0:0, 0:0:0);
(A2A1[11] => V[19]) = (0:0:0, 0:0:0);
(A2A1[11] => V[20]) = (0:0:0, 0:0:0);
(A2A1[11] => V[21]) = (0:0:0, 0:0:0);
(A2A1[11] => V[22]) = (0:0:0, 0:0:0);
(A2A1[11] => V[23]) = (0:0:0, 0:0:0);
(A2A1[11] => V[24]) = (0:0:0, 0:0:0);
(A2A1[11] => V[25]) = (0:0:0, 0:0:0);
(A2A1[11] => V[26]) = (0:0:0, 0:0:0);
(A2A1[11] => V[27]) = (0:0:0, 0:0:0);
(A2A1[11] => V[28]) = (0:0:0, 0:0:0);
(A2A1[11] => V[29]) = (0:0:0, 0:0:0);
(A2A1[11] => V[30]) = (0:0:0, 0:0:0);
(A2A1[11] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[13]) = (0:0:0, 0:0:0);
(A2A1[12] => U[14]) = (0:0:0, 0:0:0);
(A2A1[12] => U[15]) = (0:0:0, 0:0:0);
(A2A1[12] => U[16]) = (0:0:0, 0:0:0);
(A2A1[12] => U[17]) = (0:0:0, 0:0:0);
(A2A1[12] => U[18]) = (0:0:0, 0:0:0);
(A2A1[12] => U[19]) = (0:0:0, 0:0:0);
(A2A1[12] => U[20]) = (0:0:0, 0:0:0);
(A2A1[12] => U[21]) = (0:0:0, 0:0:0);
(A2A1[12] => U[22]) = (0:0:0, 0:0:0);
(A2A1[12] => U[23]) = (0:0:0, 0:0:0);
(A2A1[12] => U[24]) = (0:0:0, 0:0:0);
(A2A1[12] => U[25]) = (0:0:0, 0:0:0);
(A2A1[12] => U[26]) = (0:0:0, 0:0:0);
(A2A1[12] => U[27]) = (0:0:0, 0:0:0);
(A2A1[12] => U[28]) = (0:0:0, 0:0:0);
(A2A1[12] => U[29]) = (0:0:0, 0:0:0);
(A2A1[12] => U[30]) = (0:0:0, 0:0:0);
(A2A1[12] => U[31]) = (0:0:0, 0:0:0);
(A2A1[12] => U[32]) = (0:0:0, 0:0:0);
(A2A1[12] => U[33]) = (0:0:0, 0:0:0);
(A2A1[12] => V[12]) = (0:0:0, 0:0:0);
(A2A1[12] => V[13]) = (0:0:0, 0:0:0);
(A2A1[12] => V[14]) = (0:0:0, 0:0:0);
(A2A1[12] => V[15]) = (0:0:0, 0:0:0);
(A2A1[12] => V[16]) = (0:0:0, 0:0:0);
(A2A1[12] => V[17]) = (0:0:0, 0:0:0);
(A2A1[12] => V[18]) = (0:0:0, 0:0:0);
(A2A1[12] => V[19]) = (0:0:0, 0:0:0);
(A2A1[12] => V[20]) = (0:0:0, 0:0:0);
(A2A1[12] => V[21]) = (0:0:0, 0:0:0);
(A2A1[12] => V[22]) = (0:0:0, 0:0:0);
(A2A1[12] => V[23]) = (0:0:0, 0:0:0);
(A2A1[12] => V[24]) = (0:0:0, 0:0:0);
(A2A1[12] => V[25]) = (0:0:0, 0:0:0);
(A2A1[12] => V[26]) = (0:0:0, 0:0:0);
(A2A1[12] => V[27]) = (0:0:0, 0:0:0);
(A2A1[12] => V[28]) = (0:0:0, 0:0:0);
(A2A1[12] => V[29]) = (0:0:0, 0:0:0);
(A2A1[12] => V[30]) = (0:0:0, 0:0:0);
(A2A1[12] => V[31]) = (0:0:0, 0:0:0);
(A2A1[12] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[14]) = (0:0:0, 0:0:0);
(A2A1[13] => U[15]) = (0:0:0, 0:0:0);
(A2A1[13] => U[16]) = (0:0:0, 0:0:0);
(A2A1[13] => U[17]) = (0:0:0, 0:0:0);
(A2A1[13] => U[18]) = (0:0:0, 0:0:0);
(A2A1[13] => U[19]) = (0:0:0, 0:0:0);
(A2A1[13] => U[20]) = (0:0:0, 0:0:0);
(A2A1[13] => U[21]) = (0:0:0, 0:0:0);
(A2A1[13] => U[22]) = (0:0:0, 0:0:0);
(A2A1[13] => U[23]) = (0:0:0, 0:0:0);
(A2A1[13] => U[24]) = (0:0:0, 0:0:0);
(A2A1[13] => U[25]) = (0:0:0, 0:0:0);
(A2A1[13] => U[26]) = (0:0:0, 0:0:0);
(A2A1[13] => U[27]) = (0:0:0, 0:0:0);
(A2A1[13] => U[28]) = (0:0:0, 0:0:0);
(A2A1[13] => U[29]) = (0:0:0, 0:0:0);
(A2A1[13] => U[30]) = (0:0:0, 0:0:0);
(A2A1[13] => U[31]) = (0:0:0, 0:0:0);
(A2A1[13] => U[32]) = (0:0:0, 0:0:0);
(A2A1[13] => U[33]) = (0:0:0, 0:0:0);
(A2A1[13] => U[34]) = (0:0:0, 0:0:0);
(A2A1[13] => V[13]) = (0:0:0, 0:0:0);
(A2A1[13] => V[14]) = (0:0:0, 0:0:0);
(A2A1[13] => V[15]) = (0:0:0, 0:0:0);
(A2A1[13] => V[16]) = (0:0:0, 0:0:0);
(A2A1[13] => V[17]) = (0:0:0, 0:0:0);
(A2A1[13] => V[18]) = (0:0:0, 0:0:0);
(A2A1[13] => V[19]) = (0:0:0, 0:0:0);
(A2A1[13] => V[20]) = (0:0:0, 0:0:0);
(A2A1[13] => V[21]) = (0:0:0, 0:0:0);
(A2A1[13] => V[22]) = (0:0:0, 0:0:0);
(A2A1[13] => V[23]) = (0:0:0, 0:0:0);
(A2A1[13] => V[24]) = (0:0:0, 0:0:0);
(A2A1[13] => V[25]) = (0:0:0, 0:0:0);
(A2A1[13] => V[26]) = (0:0:0, 0:0:0);
(A2A1[13] => V[27]) = (0:0:0, 0:0:0);
(A2A1[13] => V[28]) = (0:0:0, 0:0:0);
(A2A1[13] => V[29]) = (0:0:0, 0:0:0);
(A2A1[13] => V[30]) = (0:0:0, 0:0:0);
(A2A1[13] => V[31]) = (0:0:0, 0:0:0);
(A2A1[13] => V[32]) = (0:0:0, 0:0:0);
(A2A1[13] => V[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[15]) = (0:0:0, 0:0:0);
(A2A1[14] => U[16]) = (0:0:0, 0:0:0);
(A2A1[14] => U[17]) = (0:0:0, 0:0:0);
(A2A1[14] => U[18]) = (0:0:0, 0:0:0);
(A2A1[14] => U[19]) = (0:0:0, 0:0:0);
(A2A1[14] => U[20]) = (0:0:0, 0:0:0);
(A2A1[14] => U[21]) = (0:0:0, 0:0:0);
(A2A1[14] => U[22]) = (0:0:0, 0:0:0);
(A2A1[14] => U[23]) = (0:0:0, 0:0:0);
(A2A1[14] => U[24]) = (0:0:0, 0:0:0);
(A2A1[14] => U[25]) = (0:0:0, 0:0:0);
(A2A1[14] => U[26]) = (0:0:0, 0:0:0);
(A2A1[14] => U[27]) = (0:0:0, 0:0:0);
(A2A1[14] => U[28]) = (0:0:0, 0:0:0);
(A2A1[14] => U[29]) = (0:0:0, 0:0:0);
(A2A1[14] => U[30]) = (0:0:0, 0:0:0);
(A2A1[14] => U[31]) = (0:0:0, 0:0:0);
(A2A1[14] => U[32]) = (0:0:0, 0:0:0);
(A2A1[14] => U[33]) = (0:0:0, 0:0:0);
(A2A1[14] => U[34]) = (0:0:0, 0:0:0);
(A2A1[14] => V[14]) = (0:0:0, 0:0:0);
(A2A1[14] => V[15]) = (0:0:0, 0:0:0);
(A2A1[14] => V[16]) = (0:0:0, 0:0:0);
(A2A1[14] => V[17]) = (0:0:0, 0:0:0);
(A2A1[14] => V[18]) = (0:0:0, 0:0:0);
(A2A1[14] => V[19]) = (0:0:0, 0:0:0);
(A2A1[14] => V[20]) = (0:0:0, 0:0:0);
(A2A1[14] => V[21]) = (0:0:0, 0:0:0);
(A2A1[14] => V[22]) = (0:0:0, 0:0:0);
(A2A1[14] => V[23]) = (0:0:0, 0:0:0);
(A2A1[14] => V[24]) = (0:0:0, 0:0:0);
(A2A1[14] => V[25]) = (0:0:0, 0:0:0);
(A2A1[14] => V[26]) = (0:0:0, 0:0:0);
(A2A1[14] => V[27]) = (0:0:0, 0:0:0);
(A2A1[14] => V[28]) = (0:0:0, 0:0:0);
(A2A1[14] => V[29]) = (0:0:0, 0:0:0);
(A2A1[14] => V[30]) = (0:0:0, 0:0:0);
(A2A1[14] => V[31]) = (0:0:0, 0:0:0);
(A2A1[14] => V[32]) = (0:0:0, 0:0:0);
(A2A1[14] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[16]) = (0:0:0, 0:0:0);
(A2A1[15] => U[17]) = (0:0:0, 0:0:0);
(A2A1[15] => U[18]) = (0:0:0, 0:0:0);
(A2A1[15] => U[19]) = (0:0:0, 0:0:0);
(A2A1[15] => U[20]) = (0:0:0, 0:0:0);
(A2A1[15] => U[21]) = (0:0:0, 0:0:0);
(A2A1[15] => U[22]) = (0:0:0, 0:0:0);
(A2A1[15] => U[23]) = (0:0:0, 0:0:0);
(A2A1[15] => U[24]) = (0:0:0, 0:0:0);
(A2A1[15] => U[25]) = (0:0:0, 0:0:0);
(A2A1[15] => U[26]) = (0:0:0, 0:0:0);
(A2A1[15] => U[27]) = (0:0:0, 0:0:0);
(A2A1[15] => U[28]) = (0:0:0, 0:0:0);
(A2A1[15] => U[29]) = (0:0:0, 0:0:0);
(A2A1[15] => U[30]) = (0:0:0, 0:0:0);
(A2A1[15] => U[31]) = (0:0:0, 0:0:0);
(A2A1[15] => U[32]) = (0:0:0, 0:0:0);
(A2A1[15] => U[33]) = (0:0:0, 0:0:0);
(A2A1[15] => U[34]) = (0:0:0, 0:0:0);
(A2A1[15] => U[35]) = (0:0:0, 0:0:0);
(A2A1[15] => U[36]) = (0:0:0, 0:0:0);
(A2A1[15] => V[15]) = (0:0:0, 0:0:0);
(A2A1[15] => V[16]) = (0:0:0, 0:0:0);
(A2A1[15] => V[17]) = (0:0:0, 0:0:0);
(A2A1[15] => V[18]) = (0:0:0, 0:0:0);
(A2A1[15] => V[19]) = (0:0:0, 0:0:0);
(A2A1[15] => V[20]) = (0:0:0, 0:0:0);
(A2A1[15] => V[21]) = (0:0:0, 0:0:0);
(A2A1[15] => V[22]) = (0:0:0, 0:0:0);
(A2A1[15] => V[23]) = (0:0:0, 0:0:0);
(A2A1[15] => V[24]) = (0:0:0, 0:0:0);
(A2A1[15] => V[25]) = (0:0:0, 0:0:0);
(A2A1[15] => V[26]) = (0:0:0, 0:0:0);
(A2A1[15] => V[27]) = (0:0:0, 0:0:0);
(A2A1[15] => V[28]) = (0:0:0, 0:0:0);
(A2A1[15] => V[29]) = (0:0:0, 0:0:0);
(A2A1[15] => V[30]) = (0:0:0, 0:0:0);
(A2A1[15] => V[31]) = (0:0:0, 0:0:0);
(A2A1[15] => V[32]) = (0:0:0, 0:0:0);
(A2A1[15] => V[33]) = (0:0:0, 0:0:0);
(A2A1[15] => V[34]) = (0:0:0, 0:0:0);
(A2A1[15] => V[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[17]) = (0:0:0, 0:0:0);
(A2A1[16] => U[18]) = (0:0:0, 0:0:0);
(A2A1[16] => U[19]) = (0:0:0, 0:0:0);
(A2A1[16] => U[20]) = (0:0:0, 0:0:0);
(A2A1[16] => U[21]) = (0:0:0, 0:0:0);
(A2A1[16] => U[22]) = (0:0:0, 0:0:0);
(A2A1[16] => U[23]) = (0:0:0, 0:0:0);
(A2A1[16] => U[24]) = (0:0:0, 0:0:0);
(A2A1[16] => U[25]) = (0:0:0, 0:0:0);
(A2A1[16] => U[26]) = (0:0:0, 0:0:0);
(A2A1[16] => U[27]) = (0:0:0, 0:0:0);
(A2A1[16] => U[28]) = (0:0:0, 0:0:0);
(A2A1[16] => U[29]) = (0:0:0, 0:0:0);
(A2A1[16] => U[30]) = (0:0:0, 0:0:0);
(A2A1[16] => U[31]) = (0:0:0, 0:0:0);
(A2A1[16] => U[32]) = (0:0:0, 0:0:0);
(A2A1[16] => U[33]) = (0:0:0, 0:0:0);
(A2A1[16] => U[34]) = (0:0:0, 0:0:0);
(A2A1[16] => U[35]) = (0:0:0, 0:0:0);
(A2A1[16] => U[36]) = (0:0:0, 0:0:0);
(A2A1[16] => V[16]) = (0:0:0, 0:0:0);
(A2A1[16] => V[17]) = (0:0:0, 0:0:0);
(A2A1[16] => V[18]) = (0:0:0, 0:0:0);
(A2A1[16] => V[19]) = (0:0:0, 0:0:0);
(A2A1[16] => V[20]) = (0:0:0, 0:0:0);
(A2A1[16] => V[21]) = (0:0:0, 0:0:0);
(A2A1[16] => V[22]) = (0:0:0, 0:0:0);
(A2A1[16] => V[23]) = (0:0:0, 0:0:0);
(A2A1[16] => V[24]) = (0:0:0, 0:0:0);
(A2A1[16] => V[25]) = (0:0:0, 0:0:0);
(A2A1[16] => V[26]) = (0:0:0, 0:0:0);
(A2A1[16] => V[27]) = (0:0:0, 0:0:0);
(A2A1[16] => V[28]) = (0:0:0, 0:0:0);
(A2A1[16] => V[29]) = (0:0:0, 0:0:0);
(A2A1[16] => V[30]) = (0:0:0, 0:0:0);
(A2A1[16] => V[31]) = (0:0:0, 0:0:0);
(A2A1[16] => V[32]) = (0:0:0, 0:0:0);
(A2A1[16] => V[33]) = (0:0:0, 0:0:0);
(A2A1[16] => V[34]) = (0:0:0, 0:0:0);
(A2A1[16] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[18]) = (0:0:0, 0:0:0);
(A2A1[17] => U[19]) = (0:0:0, 0:0:0);
(A2A1[17] => U[20]) = (0:0:0, 0:0:0);
(A2A1[17] => U[21]) = (0:0:0, 0:0:0);
(A2A1[17] => U[22]) = (0:0:0, 0:0:0);
(A2A1[17] => U[23]) = (0:0:0, 0:0:0);
(A2A1[17] => U[24]) = (0:0:0, 0:0:0);
(A2A1[17] => U[25]) = (0:0:0, 0:0:0);
(A2A1[17] => U[26]) = (0:0:0, 0:0:0);
(A2A1[17] => U[27]) = (0:0:0, 0:0:0);
(A2A1[17] => U[28]) = (0:0:0, 0:0:0);
(A2A1[17] => U[29]) = (0:0:0, 0:0:0);
(A2A1[17] => U[30]) = (0:0:0, 0:0:0);
(A2A1[17] => U[31]) = (0:0:0, 0:0:0);
(A2A1[17] => U[32]) = (0:0:0, 0:0:0);
(A2A1[17] => U[33]) = (0:0:0, 0:0:0);
(A2A1[17] => U[34]) = (0:0:0, 0:0:0);
(A2A1[17] => U[35]) = (0:0:0, 0:0:0);
(A2A1[17] => U[36]) = (0:0:0, 0:0:0);
(A2A1[17] => U[37]) = (0:0:0, 0:0:0);
(A2A1[17] => V[17]) = (0:0:0, 0:0:0);
(A2A1[17] => V[18]) = (0:0:0, 0:0:0);
(A2A1[17] => V[19]) = (0:0:0, 0:0:0);
(A2A1[17] => V[20]) = (0:0:0, 0:0:0);
(A2A1[17] => V[21]) = (0:0:0, 0:0:0);
(A2A1[17] => V[22]) = (0:0:0, 0:0:0);
(A2A1[17] => V[23]) = (0:0:0, 0:0:0);
(A2A1[17] => V[24]) = (0:0:0, 0:0:0);
(A2A1[17] => V[25]) = (0:0:0, 0:0:0);
(A2A1[17] => V[26]) = (0:0:0, 0:0:0);
(A2A1[17] => V[27]) = (0:0:0, 0:0:0);
(A2A1[17] => V[28]) = (0:0:0, 0:0:0);
(A2A1[17] => V[29]) = (0:0:0, 0:0:0);
(A2A1[17] => V[30]) = (0:0:0, 0:0:0);
(A2A1[17] => V[31]) = (0:0:0, 0:0:0);
(A2A1[17] => V[32]) = (0:0:0, 0:0:0);
(A2A1[17] => V[33]) = (0:0:0, 0:0:0);
(A2A1[17] => V[34]) = (0:0:0, 0:0:0);
(A2A1[17] => V[35]) = (0:0:0, 0:0:0);
(A2A1[17] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[19]) = (0:0:0, 0:0:0);
(A2A1[18] => U[20]) = (0:0:0, 0:0:0);
(A2A1[18] => U[21]) = (0:0:0, 0:0:0);
(A2A1[18] => U[22]) = (0:0:0, 0:0:0);
(A2A1[18] => U[23]) = (0:0:0, 0:0:0);
(A2A1[18] => U[24]) = (0:0:0, 0:0:0);
(A2A1[18] => U[25]) = (0:0:0, 0:0:0);
(A2A1[18] => U[26]) = (0:0:0, 0:0:0);
(A2A1[18] => U[27]) = (0:0:0, 0:0:0);
(A2A1[18] => U[28]) = (0:0:0, 0:0:0);
(A2A1[18] => U[29]) = (0:0:0, 0:0:0);
(A2A1[18] => U[30]) = (0:0:0, 0:0:0);
(A2A1[18] => U[31]) = (0:0:0, 0:0:0);
(A2A1[18] => U[32]) = (0:0:0, 0:0:0);
(A2A1[18] => U[33]) = (0:0:0, 0:0:0);
(A2A1[18] => U[34]) = (0:0:0, 0:0:0);
(A2A1[18] => U[35]) = (0:0:0, 0:0:0);
(A2A1[18] => U[36]) = (0:0:0, 0:0:0);
(A2A1[18] => U[37]) = (0:0:0, 0:0:0);
(A2A1[18] => U[38]) = (0:0:0, 0:0:0);
(A2A1[18] => V[18]) = (0:0:0, 0:0:0);
(A2A1[18] => V[19]) = (0:0:0, 0:0:0);
(A2A1[18] => V[20]) = (0:0:0, 0:0:0);
(A2A1[18] => V[21]) = (0:0:0, 0:0:0);
(A2A1[18] => V[22]) = (0:0:0, 0:0:0);
(A2A1[18] => V[23]) = (0:0:0, 0:0:0);
(A2A1[18] => V[24]) = (0:0:0, 0:0:0);
(A2A1[18] => V[25]) = (0:0:0, 0:0:0);
(A2A1[18] => V[26]) = (0:0:0, 0:0:0);
(A2A1[18] => V[27]) = (0:0:0, 0:0:0);
(A2A1[18] => V[28]) = (0:0:0, 0:0:0);
(A2A1[18] => V[29]) = (0:0:0, 0:0:0);
(A2A1[18] => V[30]) = (0:0:0, 0:0:0);
(A2A1[18] => V[31]) = (0:0:0, 0:0:0);
(A2A1[18] => V[32]) = (0:0:0, 0:0:0);
(A2A1[18] => V[33]) = (0:0:0, 0:0:0);
(A2A1[18] => V[34]) = (0:0:0, 0:0:0);
(A2A1[18] => V[35]) = (0:0:0, 0:0:0);
(A2A1[18] => V[36]) = (0:0:0, 0:0:0);
(A2A1[18] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[20]) = (0:0:0, 0:0:0);
(A2A1[19] => U[21]) = (0:0:0, 0:0:0);
(A2A1[19] => U[22]) = (0:0:0, 0:0:0);
(A2A1[19] => U[23]) = (0:0:0, 0:0:0);
(A2A1[19] => U[24]) = (0:0:0, 0:0:0);
(A2A1[19] => U[25]) = (0:0:0, 0:0:0);
(A2A1[19] => U[26]) = (0:0:0, 0:0:0);
(A2A1[19] => U[27]) = (0:0:0, 0:0:0);
(A2A1[19] => U[28]) = (0:0:0, 0:0:0);
(A2A1[19] => U[29]) = (0:0:0, 0:0:0);
(A2A1[19] => U[30]) = (0:0:0, 0:0:0);
(A2A1[19] => U[31]) = (0:0:0, 0:0:0);
(A2A1[19] => U[32]) = (0:0:0, 0:0:0);
(A2A1[19] => U[33]) = (0:0:0, 0:0:0);
(A2A1[19] => U[34]) = (0:0:0, 0:0:0);
(A2A1[19] => U[35]) = (0:0:0, 0:0:0);
(A2A1[19] => U[36]) = (0:0:0, 0:0:0);
(A2A1[19] => U[37]) = (0:0:0, 0:0:0);
(A2A1[19] => U[38]) = (0:0:0, 0:0:0);
(A2A1[19] => U[39]) = (0:0:0, 0:0:0);
(A2A1[19] => V[19]) = (0:0:0, 0:0:0);
(A2A1[19] => V[20]) = (0:0:0, 0:0:0);
(A2A1[19] => V[21]) = (0:0:0, 0:0:0);
(A2A1[19] => V[22]) = (0:0:0, 0:0:0);
(A2A1[19] => V[23]) = (0:0:0, 0:0:0);
(A2A1[19] => V[24]) = (0:0:0, 0:0:0);
(A2A1[19] => V[25]) = (0:0:0, 0:0:0);
(A2A1[19] => V[26]) = (0:0:0, 0:0:0);
(A2A1[19] => V[27]) = (0:0:0, 0:0:0);
(A2A1[19] => V[28]) = (0:0:0, 0:0:0);
(A2A1[19] => V[29]) = (0:0:0, 0:0:0);
(A2A1[19] => V[30]) = (0:0:0, 0:0:0);
(A2A1[19] => V[31]) = (0:0:0, 0:0:0);
(A2A1[19] => V[32]) = (0:0:0, 0:0:0);
(A2A1[19] => V[33]) = (0:0:0, 0:0:0);
(A2A1[19] => V[34]) = (0:0:0, 0:0:0);
(A2A1[19] => V[35]) = (0:0:0, 0:0:0);
(A2A1[19] => V[36]) = (0:0:0, 0:0:0);
(A2A1[19] => V[37]) = (0:0:0, 0:0:0);
(A2A1[19] => V[38]) = (0:0:0, 0:0:0);
(A2A1[1] => U[10]) = (0:0:0, 0:0:0);
(A2A1[1] => U[11]) = (0:0:0, 0:0:0);
(A2A1[1] => U[12]) = (0:0:0, 0:0:0);
(A2A1[1] => U[13]) = (0:0:0, 0:0:0);
(A2A1[1] => U[14]) = (0:0:0, 0:0:0);
(A2A1[1] => U[15]) = (0:0:0, 0:0:0);
(A2A1[1] => U[16]) = (0:0:0, 0:0:0);
(A2A1[1] => U[17]) = (0:0:0, 0:0:0);
(A2A1[1] => U[18]) = (0:0:0, 0:0:0);
(A2A1[1] => U[19]) = (0:0:0, 0:0:0);
(A2A1[1] => U[1]) = (0:0:0, 0:0:0);
(A2A1[1] => U[20]) = (0:0:0, 0:0:0);
(A2A1[1] => U[21]) = (0:0:0, 0:0:0);
(A2A1[1] => U[22]) = (0:0:0, 0:0:0);
(A2A1[1] => U[2]) = (0:0:0, 0:0:0);
(A2A1[1] => U[3]) = (0:0:0, 0:0:0);
(A2A1[1] => U[4]) = (0:0:0, 0:0:0);
(A2A1[1] => U[5]) = (0:0:0, 0:0:0);
(A2A1[1] => U[6]) = (0:0:0, 0:0:0);
(A2A1[1] => U[7]) = (0:0:0, 0:0:0);
(A2A1[1] => U[8]) = (0:0:0, 0:0:0);
(A2A1[1] => U[9]) = (0:0:0, 0:0:0);
(A2A1[1] => V[10]) = (0:0:0, 0:0:0);
(A2A1[1] => V[11]) = (0:0:0, 0:0:0);
(A2A1[1] => V[12]) = (0:0:0, 0:0:0);
(A2A1[1] => V[13]) = (0:0:0, 0:0:0);
(A2A1[1] => V[14]) = (0:0:0, 0:0:0);
(A2A1[1] => V[15]) = (0:0:0, 0:0:0);
(A2A1[1] => V[16]) = (0:0:0, 0:0:0);
(A2A1[1] => V[17]) = (0:0:0, 0:0:0);
(A2A1[1] => V[18]) = (0:0:0, 0:0:0);
(A2A1[1] => V[19]) = (0:0:0, 0:0:0);
(A2A1[1] => V[20]) = (0:0:0, 0:0:0);
(A2A1[1] => V[21]) = (0:0:0, 0:0:0);
(A2A1[1] => V[4]) = (0:0:0, 0:0:0);
(A2A1[1] => V[5]) = (0:0:0, 0:0:0);
(A2A1[1] => V[6]) = (0:0:0, 0:0:0);
(A2A1[1] => V[7]) = (0:0:0, 0:0:0);
(A2A1[1] => V[8]) = (0:0:0, 0:0:0);
(A2A1[1] => V[9]) = (0:0:0, 0:0:0);
(A2A1[20] => U[21]) = (0:0:0, 0:0:0);
(A2A1[20] => U[22]) = (0:0:0, 0:0:0);
(A2A1[20] => U[23]) = (0:0:0, 0:0:0);
(A2A1[20] => U[24]) = (0:0:0, 0:0:0);
(A2A1[20] => U[25]) = (0:0:0, 0:0:0);
(A2A1[20] => U[26]) = (0:0:0, 0:0:0);
(A2A1[20] => U[27]) = (0:0:0, 0:0:0);
(A2A1[20] => U[28]) = (0:0:0, 0:0:0);
(A2A1[20] => U[29]) = (0:0:0, 0:0:0);
(A2A1[20] => U[30]) = (0:0:0, 0:0:0);
(A2A1[20] => U[31]) = (0:0:0, 0:0:0);
(A2A1[20] => U[32]) = (0:0:0, 0:0:0);
(A2A1[20] => U[33]) = (0:0:0, 0:0:0);
(A2A1[20] => U[34]) = (0:0:0, 0:0:0);
(A2A1[20] => U[35]) = (0:0:0, 0:0:0);
(A2A1[20] => U[36]) = (0:0:0, 0:0:0);
(A2A1[20] => U[37]) = (0:0:0, 0:0:0);
(A2A1[20] => U[38]) = (0:0:0, 0:0:0);
(A2A1[20] => U[39]) = (0:0:0, 0:0:0);
(A2A1[20] => V[20]) = (0:0:0, 0:0:0);
(A2A1[20] => V[21]) = (0:0:0, 0:0:0);
(A2A1[20] => V[22]) = (0:0:0, 0:0:0);
(A2A1[20] => V[23]) = (0:0:0, 0:0:0);
(A2A1[20] => V[24]) = (0:0:0, 0:0:0);
(A2A1[20] => V[25]) = (0:0:0, 0:0:0);
(A2A1[20] => V[26]) = (0:0:0, 0:0:0);
(A2A1[20] => V[27]) = (0:0:0, 0:0:0);
(A2A1[20] => V[28]) = (0:0:0, 0:0:0);
(A2A1[20] => V[29]) = (0:0:0, 0:0:0);
(A2A1[20] => V[30]) = (0:0:0, 0:0:0);
(A2A1[20] => V[31]) = (0:0:0, 0:0:0);
(A2A1[20] => V[32]) = (0:0:0, 0:0:0);
(A2A1[20] => V[33]) = (0:0:0, 0:0:0);
(A2A1[20] => V[34]) = (0:0:0, 0:0:0);
(A2A1[20] => V[35]) = (0:0:0, 0:0:0);
(A2A1[20] => V[36]) = (0:0:0, 0:0:0);
(A2A1[20] => V[37]) = (0:0:0, 0:0:0);
(A2A1[20] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[22]) = (0:0:0, 0:0:0);
(A2A1[21] => U[23]) = (0:0:0, 0:0:0);
(A2A1[21] => U[24]) = (0:0:0, 0:0:0);
(A2A1[21] => U[25]) = (0:0:0, 0:0:0);
(A2A1[21] => U[26]) = (0:0:0, 0:0:0);
(A2A1[21] => U[27]) = (0:0:0, 0:0:0);
(A2A1[21] => U[28]) = (0:0:0, 0:0:0);
(A2A1[21] => U[29]) = (0:0:0, 0:0:0);
(A2A1[21] => U[30]) = (0:0:0, 0:0:0);
(A2A1[21] => U[31]) = (0:0:0, 0:0:0);
(A2A1[21] => U[32]) = (0:0:0, 0:0:0);
(A2A1[21] => U[33]) = (0:0:0, 0:0:0);
(A2A1[21] => U[34]) = (0:0:0, 0:0:0);
(A2A1[21] => U[35]) = (0:0:0, 0:0:0);
(A2A1[21] => U[36]) = (0:0:0, 0:0:0);
(A2A1[21] => U[37]) = (0:0:0, 0:0:0);
(A2A1[21] => U[38]) = (0:0:0, 0:0:0);
(A2A1[21] => U[39]) = (0:0:0, 0:0:0);
(A2A1[21] => U[40]) = (0:0:0, 0:0:0);
(A2A1[21] => V[21]) = (0:0:0, 0:0:0);
(A2A1[21] => V[22]) = (0:0:0, 0:0:0);
(A2A1[21] => V[23]) = (0:0:0, 0:0:0);
(A2A1[21] => V[24]) = (0:0:0, 0:0:0);
(A2A1[21] => V[25]) = (0:0:0, 0:0:0);
(A2A1[21] => V[26]) = (0:0:0, 0:0:0);
(A2A1[21] => V[27]) = (0:0:0, 0:0:0);
(A2A1[21] => V[28]) = (0:0:0, 0:0:0);
(A2A1[21] => V[29]) = (0:0:0, 0:0:0);
(A2A1[21] => V[30]) = (0:0:0, 0:0:0);
(A2A1[21] => V[31]) = (0:0:0, 0:0:0);
(A2A1[21] => V[32]) = (0:0:0, 0:0:0);
(A2A1[21] => V[33]) = (0:0:0, 0:0:0);
(A2A1[21] => V[34]) = (0:0:0, 0:0:0);
(A2A1[21] => V[35]) = (0:0:0, 0:0:0);
(A2A1[21] => V[36]) = (0:0:0, 0:0:0);
(A2A1[21] => V[37]) = (0:0:0, 0:0:0);
(A2A1[21] => V[38]) = (0:0:0, 0:0:0);
(A2A1[21] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[23]) = (0:0:0, 0:0:0);
(A2A1[22] => U[24]) = (0:0:0, 0:0:0);
(A2A1[22] => U[25]) = (0:0:0, 0:0:0);
(A2A1[22] => U[26]) = (0:0:0, 0:0:0);
(A2A1[22] => U[27]) = (0:0:0, 0:0:0);
(A2A1[22] => U[28]) = (0:0:0, 0:0:0);
(A2A1[22] => U[29]) = (0:0:0, 0:0:0);
(A2A1[22] => U[30]) = (0:0:0, 0:0:0);
(A2A1[22] => U[31]) = (0:0:0, 0:0:0);
(A2A1[22] => U[32]) = (0:0:0, 0:0:0);
(A2A1[22] => U[33]) = (0:0:0, 0:0:0);
(A2A1[22] => U[34]) = (0:0:0, 0:0:0);
(A2A1[22] => U[35]) = (0:0:0, 0:0:0);
(A2A1[22] => U[36]) = (0:0:0, 0:0:0);
(A2A1[22] => U[37]) = (0:0:0, 0:0:0);
(A2A1[22] => U[38]) = (0:0:0, 0:0:0);
(A2A1[22] => U[39]) = (0:0:0, 0:0:0);
(A2A1[22] => U[40]) = (0:0:0, 0:0:0);
(A2A1[22] => U[41]) = (0:0:0, 0:0:0);
(A2A1[22] => V[22]) = (0:0:0, 0:0:0);
(A2A1[22] => V[23]) = (0:0:0, 0:0:0);
(A2A1[22] => V[24]) = (0:0:0, 0:0:0);
(A2A1[22] => V[25]) = (0:0:0, 0:0:0);
(A2A1[22] => V[26]) = (0:0:0, 0:0:0);
(A2A1[22] => V[27]) = (0:0:0, 0:0:0);
(A2A1[22] => V[28]) = (0:0:0, 0:0:0);
(A2A1[22] => V[29]) = (0:0:0, 0:0:0);
(A2A1[22] => V[30]) = (0:0:0, 0:0:0);
(A2A1[22] => V[31]) = (0:0:0, 0:0:0);
(A2A1[22] => V[32]) = (0:0:0, 0:0:0);
(A2A1[22] => V[33]) = (0:0:0, 0:0:0);
(A2A1[22] => V[34]) = (0:0:0, 0:0:0);
(A2A1[22] => V[35]) = (0:0:0, 0:0:0);
(A2A1[22] => V[36]) = (0:0:0, 0:0:0);
(A2A1[22] => V[37]) = (0:0:0, 0:0:0);
(A2A1[22] => V[38]) = (0:0:0, 0:0:0);
(A2A1[22] => V[39]) = (0:0:0, 0:0:0);
(A2A1[22] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[24]) = (0:0:0, 0:0:0);
(A2A1[23] => U[25]) = (0:0:0, 0:0:0);
(A2A1[23] => U[26]) = (0:0:0, 0:0:0);
(A2A1[23] => U[27]) = (0:0:0, 0:0:0);
(A2A1[23] => U[28]) = (0:0:0, 0:0:0);
(A2A1[23] => U[29]) = (0:0:0, 0:0:0);
(A2A1[23] => U[30]) = (0:0:0, 0:0:0);
(A2A1[23] => U[31]) = (0:0:0, 0:0:0);
(A2A1[23] => U[32]) = (0:0:0, 0:0:0);
(A2A1[23] => U[33]) = (0:0:0, 0:0:0);
(A2A1[23] => U[34]) = (0:0:0, 0:0:0);
(A2A1[23] => U[35]) = (0:0:0, 0:0:0);
(A2A1[23] => U[36]) = (0:0:0, 0:0:0);
(A2A1[23] => U[37]) = (0:0:0, 0:0:0);
(A2A1[23] => U[38]) = (0:0:0, 0:0:0);
(A2A1[23] => U[39]) = (0:0:0, 0:0:0);
(A2A1[23] => U[40]) = (0:0:0, 0:0:0);
(A2A1[23] => U[41]) = (0:0:0, 0:0:0);
(A2A1[23] => U[42]) = (0:0:0, 0:0:0);
(A2A1[23] => V[23]) = (0:0:0, 0:0:0);
(A2A1[23] => V[24]) = (0:0:0, 0:0:0);
(A2A1[23] => V[25]) = (0:0:0, 0:0:0);
(A2A1[23] => V[26]) = (0:0:0, 0:0:0);
(A2A1[23] => V[27]) = (0:0:0, 0:0:0);
(A2A1[23] => V[28]) = (0:0:0, 0:0:0);
(A2A1[23] => V[29]) = (0:0:0, 0:0:0);
(A2A1[23] => V[30]) = (0:0:0, 0:0:0);
(A2A1[23] => V[31]) = (0:0:0, 0:0:0);
(A2A1[23] => V[32]) = (0:0:0, 0:0:0);
(A2A1[23] => V[33]) = (0:0:0, 0:0:0);
(A2A1[23] => V[34]) = (0:0:0, 0:0:0);
(A2A1[23] => V[35]) = (0:0:0, 0:0:0);
(A2A1[23] => V[36]) = (0:0:0, 0:0:0);
(A2A1[23] => V[37]) = (0:0:0, 0:0:0);
(A2A1[23] => V[38]) = (0:0:0, 0:0:0);
(A2A1[23] => V[39]) = (0:0:0, 0:0:0);
(A2A1[23] => V[40]) = (0:0:0, 0:0:0);
(A2A1[23] => V[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[25]) = (0:0:0, 0:0:0);
(A2A1[24] => U[26]) = (0:0:0, 0:0:0);
(A2A1[24] => U[27]) = (0:0:0, 0:0:0);
(A2A1[24] => U[28]) = (0:0:0, 0:0:0);
(A2A1[24] => U[29]) = (0:0:0, 0:0:0);
(A2A1[24] => U[30]) = (0:0:0, 0:0:0);
(A2A1[24] => U[31]) = (0:0:0, 0:0:0);
(A2A1[24] => U[32]) = (0:0:0, 0:0:0);
(A2A1[24] => U[33]) = (0:0:0, 0:0:0);
(A2A1[24] => U[34]) = (0:0:0, 0:0:0);
(A2A1[24] => U[35]) = (0:0:0, 0:0:0);
(A2A1[24] => U[36]) = (0:0:0, 0:0:0);
(A2A1[24] => U[37]) = (0:0:0, 0:0:0);
(A2A1[24] => U[38]) = (0:0:0, 0:0:0);
(A2A1[24] => U[39]) = (0:0:0, 0:0:0);
(A2A1[24] => U[40]) = (0:0:0, 0:0:0);
(A2A1[24] => U[41]) = (0:0:0, 0:0:0);
(A2A1[24] => U[42]) = (0:0:0, 0:0:0);
(A2A1[24] => V[24]) = (0:0:0, 0:0:0);
(A2A1[24] => V[25]) = (0:0:0, 0:0:0);
(A2A1[24] => V[26]) = (0:0:0, 0:0:0);
(A2A1[24] => V[27]) = (0:0:0, 0:0:0);
(A2A1[24] => V[28]) = (0:0:0, 0:0:0);
(A2A1[24] => V[29]) = (0:0:0, 0:0:0);
(A2A1[24] => V[30]) = (0:0:0, 0:0:0);
(A2A1[24] => V[31]) = (0:0:0, 0:0:0);
(A2A1[24] => V[32]) = (0:0:0, 0:0:0);
(A2A1[24] => V[33]) = (0:0:0, 0:0:0);
(A2A1[24] => V[34]) = (0:0:0, 0:0:0);
(A2A1[24] => V[35]) = (0:0:0, 0:0:0);
(A2A1[24] => V[36]) = (0:0:0, 0:0:0);
(A2A1[24] => V[37]) = (0:0:0, 0:0:0);
(A2A1[24] => V[38]) = (0:0:0, 0:0:0);
(A2A1[24] => V[39]) = (0:0:0, 0:0:0);
(A2A1[24] => V[40]) = (0:0:0, 0:0:0);
(A2A1[24] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[26]) = (0:0:0, 0:0:0);
(A2A1[25] => U[27]) = (0:0:0, 0:0:0);
(A2A1[25] => U[28]) = (0:0:0, 0:0:0);
(A2A1[25] => U[29]) = (0:0:0, 0:0:0);
(A2A1[25] => U[30]) = (0:0:0, 0:0:0);
(A2A1[25] => U[31]) = (0:0:0, 0:0:0);
(A2A1[25] => U[32]) = (0:0:0, 0:0:0);
(A2A1[25] => U[33]) = (0:0:0, 0:0:0);
(A2A1[25] => U[34]) = (0:0:0, 0:0:0);
(A2A1[25] => U[35]) = (0:0:0, 0:0:0);
(A2A1[25] => U[36]) = (0:0:0, 0:0:0);
(A2A1[25] => U[37]) = (0:0:0, 0:0:0);
(A2A1[25] => U[38]) = (0:0:0, 0:0:0);
(A2A1[25] => U[39]) = (0:0:0, 0:0:0);
(A2A1[25] => U[40]) = (0:0:0, 0:0:0);
(A2A1[25] => U[41]) = (0:0:0, 0:0:0);
(A2A1[25] => U[42]) = (0:0:0, 0:0:0);
(A2A1[25] => U[43]) = (0:0:0, 0:0:0);
(A2A1[25] => V[25]) = (0:0:0, 0:0:0);
(A2A1[25] => V[26]) = (0:0:0, 0:0:0);
(A2A1[25] => V[27]) = (0:0:0, 0:0:0);
(A2A1[25] => V[28]) = (0:0:0, 0:0:0);
(A2A1[25] => V[29]) = (0:0:0, 0:0:0);
(A2A1[25] => V[30]) = (0:0:0, 0:0:0);
(A2A1[25] => V[31]) = (0:0:0, 0:0:0);
(A2A1[25] => V[32]) = (0:0:0, 0:0:0);
(A2A1[25] => V[33]) = (0:0:0, 0:0:0);
(A2A1[25] => V[34]) = (0:0:0, 0:0:0);
(A2A1[25] => V[35]) = (0:0:0, 0:0:0);
(A2A1[25] => V[36]) = (0:0:0, 0:0:0);
(A2A1[25] => V[37]) = (0:0:0, 0:0:0);
(A2A1[25] => V[38]) = (0:0:0, 0:0:0);
(A2A1[25] => V[39]) = (0:0:0, 0:0:0);
(A2A1[25] => V[40]) = (0:0:0, 0:0:0);
(A2A1[25] => V[41]) = (0:0:0, 0:0:0);
(A2A1[25] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => AMULT26) = (0:0:0, 0:0:0);
(A2A1[26] => U[27]) = (0:0:0, 0:0:0);
(A2A1[26] => U[28]) = (0:0:0, 0:0:0);
(A2A1[26] => U[29]) = (0:0:0, 0:0:0);
(A2A1[26] => U[30]) = (0:0:0, 0:0:0);
(A2A1[26] => U[31]) = (0:0:0, 0:0:0);
(A2A1[26] => U[32]) = (0:0:0, 0:0:0);
(A2A1[26] => U[33]) = (0:0:0, 0:0:0);
(A2A1[26] => U[34]) = (0:0:0, 0:0:0);
(A2A1[26] => U[35]) = (0:0:0, 0:0:0);
(A2A1[26] => U[36]) = (0:0:0, 0:0:0);
(A2A1[26] => U[37]) = (0:0:0, 0:0:0);
(A2A1[26] => U[38]) = (0:0:0, 0:0:0);
(A2A1[26] => U[39]) = (0:0:0, 0:0:0);
(A2A1[26] => U[40]) = (0:0:0, 0:0:0);
(A2A1[26] => U[41]) = (0:0:0, 0:0:0);
(A2A1[26] => U[42]) = (0:0:0, 0:0:0);
(A2A1[26] => U[43]) = (0:0:0, 0:0:0);
(A2A1[26] => V[26]) = (0:0:0, 0:0:0);
(A2A1[26] => V[27]) = (0:0:0, 0:0:0);
(A2A1[26] => V[28]) = (0:0:0, 0:0:0);
(A2A1[26] => V[29]) = (0:0:0, 0:0:0);
(A2A1[26] => V[30]) = (0:0:0, 0:0:0);
(A2A1[26] => V[31]) = (0:0:0, 0:0:0);
(A2A1[26] => V[32]) = (0:0:0, 0:0:0);
(A2A1[26] => V[33]) = (0:0:0, 0:0:0);
(A2A1[26] => V[34]) = (0:0:0, 0:0:0);
(A2A1[26] => V[35]) = (0:0:0, 0:0:0);
(A2A1[26] => V[36]) = (0:0:0, 0:0:0);
(A2A1[26] => V[37]) = (0:0:0, 0:0:0);
(A2A1[26] => V[38]) = (0:0:0, 0:0:0);
(A2A1[26] => V[39]) = (0:0:0, 0:0:0);
(A2A1[26] => V[40]) = (0:0:0, 0:0:0);
(A2A1[26] => V[41]) = (0:0:0, 0:0:0);
(A2A1[26] => V[42]) = (0:0:0, 0:0:0);
(A2A1[26] => V[43]) = (0:0:0, 0:0:0);
(A2A1[2] => U[10]) = (0:0:0, 0:0:0);
(A2A1[2] => U[11]) = (0:0:0, 0:0:0);
(A2A1[2] => U[12]) = (0:0:0, 0:0:0);
(A2A1[2] => U[13]) = (0:0:0, 0:0:0);
(A2A1[2] => U[14]) = (0:0:0, 0:0:0);
(A2A1[2] => U[15]) = (0:0:0, 0:0:0);
(A2A1[2] => U[16]) = (0:0:0, 0:0:0);
(A2A1[2] => U[17]) = (0:0:0, 0:0:0);
(A2A1[2] => U[18]) = (0:0:0, 0:0:0);
(A2A1[2] => U[19]) = (0:0:0, 0:0:0);
(A2A1[2] => U[20]) = (0:0:0, 0:0:0);
(A2A1[2] => U[21]) = (0:0:0, 0:0:0);
(A2A1[2] => U[22]) = (0:0:0, 0:0:0);
(A2A1[2] => U[23]) = (0:0:0, 0:0:0);
(A2A1[2] => U[2]) = (0:0:0, 0:0:0);
(A2A1[2] => U[3]) = (0:0:0, 0:0:0);
(A2A1[2] => U[4]) = (0:0:0, 0:0:0);
(A2A1[2] => U[5]) = (0:0:0, 0:0:0);
(A2A1[2] => U[6]) = (0:0:0, 0:0:0);
(A2A1[2] => U[7]) = (0:0:0, 0:0:0);
(A2A1[2] => U[8]) = (0:0:0, 0:0:0);
(A2A1[2] => U[9]) = (0:0:0, 0:0:0);
(A2A1[2] => V[10]) = (0:0:0, 0:0:0);
(A2A1[2] => V[11]) = (0:0:0, 0:0:0);
(A2A1[2] => V[12]) = (0:0:0, 0:0:0);
(A2A1[2] => V[13]) = (0:0:0, 0:0:0);
(A2A1[2] => V[14]) = (0:0:0, 0:0:0);
(A2A1[2] => V[15]) = (0:0:0, 0:0:0);
(A2A1[2] => V[16]) = (0:0:0, 0:0:0);
(A2A1[2] => V[17]) = (0:0:0, 0:0:0);
(A2A1[2] => V[18]) = (0:0:0, 0:0:0);
(A2A1[2] => V[19]) = (0:0:0, 0:0:0);
(A2A1[2] => V[20]) = (0:0:0, 0:0:0);
(A2A1[2] => V[21]) = (0:0:0, 0:0:0);
(A2A1[2] => V[22]) = (0:0:0, 0:0:0);
(A2A1[2] => V[4]) = (0:0:0, 0:0:0);
(A2A1[2] => V[5]) = (0:0:0, 0:0:0);
(A2A1[2] => V[6]) = (0:0:0, 0:0:0);
(A2A1[2] => V[7]) = (0:0:0, 0:0:0);
(A2A1[2] => V[8]) = (0:0:0, 0:0:0);
(A2A1[2] => V[9]) = (0:0:0, 0:0:0);
(A2A1[3] => U[10]) = (0:0:0, 0:0:0);
(A2A1[3] => U[11]) = (0:0:0, 0:0:0);
(A2A1[3] => U[12]) = (0:0:0, 0:0:0);
(A2A1[3] => U[13]) = (0:0:0, 0:0:0);
(A2A1[3] => U[14]) = (0:0:0, 0:0:0);
(A2A1[3] => U[15]) = (0:0:0, 0:0:0);
(A2A1[3] => U[16]) = (0:0:0, 0:0:0);
(A2A1[3] => U[17]) = (0:0:0, 0:0:0);
(A2A1[3] => U[18]) = (0:0:0, 0:0:0);
(A2A1[3] => U[19]) = (0:0:0, 0:0:0);
(A2A1[3] => U[20]) = (0:0:0, 0:0:0);
(A2A1[3] => U[21]) = (0:0:0, 0:0:0);
(A2A1[3] => U[22]) = (0:0:0, 0:0:0);
(A2A1[3] => U[23]) = (0:0:0, 0:0:0);
(A2A1[3] => U[24]) = (0:0:0, 0:0:0);
(A2A1[3] => U[3]) = (0:0:0, 0:0:0);
(A2A1[3] => U[4]) = (0:0:0, 0:0:0);
(A2A1[3] => U[5]) = (0:0:0, 0:0:0);
(A2A1[3] => U[6]) = (0:0:0, 0:0:0);
(A2A1[3] => U[7]) = (0:0:0, 0:0:0);
(A2A1[3] => U[8]) = (0:0:0, 0:0:0);
(A2A1[3] => U[9]) = (0:0:0, 0:0:0);
(A2A1[3] => V[10]) = (0:0:0, 0:0:0);
(A2A1[3] => V[11]) = (0:0:0, 0:0:0);
(A2A1[3] => V[12]) = (0:0:0, 0:0:0);
(A2A1[3] => V[13]) = (0:0:0, 0:0:0);
(A2A1[3] => V[14]) = (0:0:0, 0:0:0);
(A2A1[3] => V[15]) = (0:0:0, 0:0:0);
(A2A1[3] => V[16]) = (0:0:0, 0:0:0);
(A2A1[3] => V[17]) = (0:0:0, 0:0:0);
(A2A1[3] => V[18]) = (0:0:0, 0:0:0);
(A2A1[3] => V[19]) = (0:0:0, 0:0:0);
(A2A1[3] => V[20]) = (0:0:0, 0:0:0);
(A2A1[3] => V[21]) = (0:0:0, 0:0:0);
(A2A1[3] => V[22]) = (0:0:0, 0:0:0);
(A2A1[3] => V[23]) = (0:0:0, 0:0:0);
(A2A1[3] => V[4]) = (0:0:0, 0:0:0);
(A2A1[3] => V[5]) = (0:0:0, 0:0:0);
(A2A1[3] => V[6]) = (0:0:0, 0:0:0);
(A2A1[3] => V[7]) = (0:0:0, 0:0:0);
(A2A1[3] => V[8]) = (0:0:0, 0:0:0);
(A2A1[3] => V[9]) = (0:0:0, 0:0:0);
(A2A1[4] => U[10]) = (0:0:0, 0:0:0);
(A2A1[4] => U[11]) = (0:0:0, 0:0:0);
(A2A1[4] => U[12]) = (0:0:0, 0:0:0);
(A2A1[4] => U[13]) = (0:0:0, 0:0:0);
(A2A1[4] => U[14]) = (0:0:0, 0:0:0);
(A2A1[4] => U[15]) = (0:0:0, 0:0:0);
(A2A1[4] => U[16]) = (0:0:0, 0:0:0);
(A2A1[4] => U[17]) = (0:0:0, 0:0:0);
(A2A1[4] => U[18]) = (0:0:0, 0:0:0);
(A2A1[4] => U[19]) = (0:0:0, 0:0:0);
(A2A1[4] => U[20]) = (0:0:0, 0:0:0);
(A2A1[4] => U[21]) = (0:0:0, 0:0:0);
(A2A1[4] => U[22]) = (0:0:0, 0:0:0);
(A2A1[4] => U[23]) = (0:0:0, 0:0:0);
(A2A1[4] => U[24]) = (0:0:0, 0:0:0);
(A2A1[4] => U[25]) = (0:0:0, 0:0:0);
(A2A1[4] => U[5]) = (0:0:0, 0:0:0);
(A2A1[4] => U[6]) = (0:0:0, 0:0:0);
(A2A1[4] => U[7]) = (0:0:0, 0:0:0);
(A2A1[4] => U[8]) = (0:0:0, 0:0:0);
(A2A1[4] => U[9]) = (0:0:0, 0:0:0);
(A2A1[4] => V[10]) = (0:0:0, 0:0:0);
(A2A1[4] => V[11]) = (0:0:0, 0:0:0);
(A2A1[4] => V[12]) = (0:0:0, 0:0:0);
(A2A1[4] => V[13]) = (0:0:0, 0:0:0);
(A2A1[4] => V[14]) = (0:0:0, 0:0:0);
(A2A1[4] => V[15]) = (0:0:0, 0:0:0);
(A2A1[4] => V[16]) = (0:0:0, 0:0:0);
(A2A1[4] => V[17]) = (0:0:0, 0:0:0);
(A2A1[4] => V[18]) = (0:0:0, 0:0:0);
(A2A1[4] => V[19]) = (0:0:0, 0:0:0);
(A2A1[4] => V[20]) = (0:0:0, 0:0:0);
(A2A1[4] => V[21]) = (0:0:0, 0:0:0);
(A2A1[4] => V[22]) = (0:0:0, 0:0:0);
(A2A1[4] => V[23]) = (0:0:0, 0:0:0);
(A2A1[4] => V[24]) = (0:0:0, 0:0:0);
(A2A1[4] => V[4]) = (0:0:0, 0:0:0);
(A2A1[4] => V[5]) = (0:0:0, 0:0:0);
(A2A1[4] => V[6]) = (0:0:0, 0:0:0);
(A2A1[4] => V[7]) = (0:0:0, 0:0:0);
(A2A1[4] => V[8]) = (0:0:0, 0:0:0);
(A2A1[4] => V[9]) = (0:0:0, 0:0:0);
(A2A1[5] => U[10]) = (0:0:0, 0:0:0);
(A2A1[5] => U[11]) = (0:0:0, 0:0:0);
(A2A1[5] => U[12]) = (0:0:0, 0:0:0);
(A2A1[5] => U[13]) = (0:0:0, 0:0:0);
(A2A1[5] => U[14]) = (0:0:0, 0:0:0);
(A2A1[5] => U[15]) = (0:0:0, 0:0:0);
(A2A1[5] => U[16]) = (0:0:0, 0:0:0);
(A2A1[5] => U[17]) = (0:0:0, 0:0:0);
(A2A1[5] => U[18]) = (0:0:0, 0:0:0);
(A2A1[5] => U[19]) = (0:0:0, 0:0:0);
(A2A1[5] => U[20]) = (0:0:0, 0:0:0);
(A2A1[5] => U[21]) = (0:0:0, 0:0:0);
(A2A1[5] => U[22]) = (0:0:0, 0:0:0);
(A2A1[5] => U[23]) = (0:0:0, 0:0:0);
(A2A1[5] => U[24]) = (0:0:0, 0:0:0);
(A2A1[5] => U[25]) = (0:0:0, 0:0:0);
(A2A1[5] => U[26]) = (0:0:0, 0:0:0);
(A2A1[5] => U[6]) = (0:0:0, 0:0:0);
(A2A1[5] => U[7]) = (0:0:0, 0:0:0);
(A2A1[5] => U[8]) = (0:0:0, 0:0:0);
(A2A1[5] => U[9]) = (0:0:0, 0:0:0);
(A2A1[5] => V[10]) = (0:0:0, 0:0:0);
(A2A1[5] => V[11]) = (0:0:0, 0:0:0);
(A2A1[5] => V[12]) = (0:0:0, 0:0:0);
(A2A1[5] => V[13]) = (0:0:0, 0:0:0);
(A2A1[5] => V[14]) = (0:0:0, 0:0:0);
(A2A1[5] => V[15]) = (0:0:0, 0:0:0);
(A2A1[5] => V[16]) = (0:0:0, 0:0:0);
(A2A1[5] => V[17]) = (0:0:0, 0:0:0);
(A2A1[5] => V[18]) = (0:0:0, 0:0:0);
(A2A1[5] => V[19]) = (0:0:0, 0:0:0);
(A2A1[5] => V[20]) = (0:0:0, 0:0:0);
(A2A1[5] => V[21]) = (0:0:0, 0:0:0);
(A2A1[5] => V[22]) = (0:0:0, 0:0:0);
(A2A1[5] => V[23]) = (0:0:0, 0:0:0);
(A2A1[5] => V[24]) = (0:0:0, 0:0:0);
(A2A1[5] => V[25]) = (0:0:0, 0:0:0);
(A2A1[5] => V[5]) = (0:0:0, 0:0:0);
(A2A1[5] => V[6]) = (0:0:0, 0:0:0);
(A2A1[5] => V[7]) = (0:0:0, 0:0:0);
(A2A1[5] => V[8]) = (0:0:0, 0:0:0);
(A2A1[5] => V[9]) = (0:0:0, 0:0:0);
(A2A1[6] => U[10]) = (0:0:0, 0:0:0);
(A2A1[6] => U[11]) = (0:0:0, 0:0:0);
(A2A1[6] => U[12]) = (0:0:0, 0:0:0);
(A2A1[6] => U[13]) = (0:0:0, 0:0:0);
(A2A1[6] => U[14]) = (0:0:0, 0:0:0);
(A2A1[6] => U[15]) = (0:0:0, 0:0:0);
(A2A1[6] => U[16]) = (0:0:0, 0:0:0);
(A2A1[6] => U[17]) = (0:0:0, 0:0:0);
(A2A1[6] => U[18]) = (0:0:0, 0:0:0);
(A2A1[6] => U[19]) = (0:0:0, 0:0:0);
(A2A1[6] => U[20]) = (0:0:0, 0:0:0);
(A2A1[6] => U[21]) = (0:0:0, 0:0:0);
(A2A1[6] => U[22]) = (0:0:0, 0:0:0);
(A2A1[6] => U[23]) = (0:0:0, 0:0:0);
(A2A1[6] => U[24]) = (0:0:0, 0:0:0);
(A2A1[6] => U[25]) = (0:0:0, 0:0:0);
(A2A1[6] => U[26]) = (0:0:0, 0:0:0);
(A2A1[6] => U[27]) = (0:0:0, 0:0:0);
(A2A1[6] => U[7]) = (0:0:0, 0:0:0);
(A2A1[6] => U[8]) = (0:0:0, 0:0:0);
(A2A1[6] => U[9]) = (0:0:0, 0:0:0);
(A2A1[6] => V[10]) = (0:0:0, 0:0:0);
(A2A1[6] => V[11]) = (0:0:0, 0:0:0);
(A2A1[6] => V[12]) = (0:0:0, 0:0:0);
(A2A1[6] => V[13]) = (0:0:0, 0:0:0);
(A2A1[6] => V[14]) = (0:0:0, 0:0:0);
(A2A1[6] => V[15]) = (0:0:0, 0:0:0);
(A2A1[6] => V[16]) = (0:0:0, 0:0:0);
(A2A1[6] => V[17]) = (0:0:0, 0:0:0);
(A2A1[6] => V[18]) = (0:0:0, 0:0:0);
(A2A1[6] => V[19]) = (0:0:0, 0:0:0);
(A2A1[6] => V[20]) = (0:0:0, 0:0:0);
(A2A1[6] => V[21]) = (0:0:0, 0:0:0);
(A2A1[6] => V[22]) = (0:0:0, 0:0:0);
(A2A1[6] => V[23]) = (0:0:0, 0:0:0);
(A2A1[6] => V[24]) = (0:0:0, 0:0:0);
(A2A1[6] => V[25]) = (0:0:0, 0:0:0);
(A2A1[6] => V[26]) = (0:0:0, 0:0:0);
(A2A1[6] => V[6]) = (0:0:0, 0:0:0);
(A2A1[6] => V[7]) = (0:0:0, 0:0:0);
(A2A1[6] => V[8]) = (0:0:0, 0:0:0);
(A2A1[6] => V[9]) = (0:0:0, 0:0:0);
(A2A1[7] => U[10]) = (0:0:0, 0:0:0);
(A2A1[7] => U[11]) = (0:0:0, 0:0:0);
(A2A1[7] => U[12]) = (0:0:0, 0:0:0);
(A2A1[7] => U[13]) = (0:0:0, 0:0:0);
(A2A1[7] => U[14]) = (0:0:0, 0:0:0);
(A2A1[7] => U[15]) = (0:0:0, 0:0:0);
(A2A1[7] => U[16]) = (0:0:0, 0:0:0);
(A2A1[7] => U[17]) = (0:0:0, 0:0:0);
(A2A1[7] => U[18]) = (0:0:0, 0:0:0);
(A2A1[7] => U[19]) = (0:0:0, 0:0:0);
(A2A1[7] => U[20]) = (0:0:0, 0:0:0);
(A2A1[7] => U[21]) = (0:0:0, 0:0:0);
(A2A1[7] => U[22]) = (0:0:0, 0:0:0);
(A2A1[7] => U[23]) = (0:0:0, 0:0:0);
(A2A1[7] => U[24]) = (0:0:0, 0:0:0);
(A2A1[7] => U[25]) = (0:0:0, 0:0:0);
(A2A1[7] => U[26]) = (0:0:0, 0:0:0);
(A2A1[7] => U[27]) = (0:0:0, 0:0:0);
(A2A1[7] => U[28]) = (0:0:0, 0:0:0);
(A2A1[7] => U[8]) = (0:0:0, 0:0:0);
(A2A1[7] => U[9]) = (0:0:0, 0:0:0);
(A2A1[7] => V[10]) = (0:0:0, 0:0:0);
(A2A1[7] => V[11]) = (0:0:0, 0:0:0);
(A2A1[7] => V[12]) = (0:0:0, 0:0:0);
(A2A1[7] => V[13]) = (0:0:0, 0:0:0);
(A2A1[7] => V[14]) = (0:0:0, 0:0:0);
(A2A1[7] => V[15]) = (0:0:0, 0:0:0);
(A2A1[7] => V[16]) = (0:0:0, 0:0:0);
(A2A1[7] => V[17]) = (0:0:0, 0:0:0);
(A2A1[7] => V[18]) = (0:0:0, 0:0:0);
(A2A1[7] => V[19]) = (0:0:0, 0:0:0);
(A2A1[7] => V[20]) = (0:0:0, 0:0:0);
(A2A1[7] => V[21]) = (0:0:0, 0:0:0);
(A2A1[7] => V[22]) = (0:0:0, 0:0:0);
(A2A1[7] => V[23]) = (0:0:0, 0:0:0);
(A2A1[7] => V[24]) = (0:0:0, 0:0:0);
(A2A1[7] => V[25]) = (0:0:0, 0:0:0);
(A2A1[7] => V[26]) = (0:0:0, 0:0:0);
(A2A1[7] => V[27]) = (0:0:0, 0:0:0);
(A2A1[7] => V[7]) = (0:0:0, 0:0:0);
(A2A1[7] => V[8]) = (0:0:0, 0:0:0);
(A2A1[7] => V[9]) = (0:0:0, 0:0:0);
(A2A1[8] => U[10]) = (0:0:0, 0:0:0);
(A2A1[8] => U[11]) = (0:0:0, 0:0:0);
(A2A1[8] => U[12]) = (0:0:0, 0:0:0);
(A2A1[8] => U[13]) = (0:0:0, 0:0:0);
(A2A1[8] => U[14]) = (0:0:0, 0:0:0);
(A2A1[8] => U[15]) = (0:0:0, 0:0:0);
(A2A1[8] => U[16]) = (0:0:0, 0:0:0);
(A2A1[8] => U[17]) = (0:0:0, 0:0:0);
(A2A1[8] => U[18]) = (0:0:0, 0:0:0);
(A2A1[8] => U[19]) = (0:0:0, 0:0:0);
(A2A1[8] => U[20]) = (0:0:0, 0:0:0);
(A2A1[8] => U[21]) = (0:0:0, 0:0:0);
(A2A1[8] => U[22]) = (0:0:0, 0:0:0);
(A2A1[8] => U[23]) = (0:0:0, 0:0:0);
(A2A1[8] => U[24]) = (0:0:0, 0:0:0);
(A2A1[8] => U[25]) = (0:0:0, 0:0:0);
(A2A1[8] => U[26]) = (0:0:0, 0:0:0);
(A2A1[8] => U[27]) = (0:0:0, 0:0:0);
(A2A1[8] => U[28]) = (0:0:0, 0:0:0);
(A2A1[8] => U[29]) = (0:0:0, 0:0:0);
(A2A1[8] => U[9]) = (0:0:0, 0:0:0);
(A2A1[8] => V[10]) = (0:0:0, 0:0:0);
(A2A1[8] => V[11]) = (0:0:0, 0:0:0);
(A2A1[8] => V[12]) = (0:0:0, 0:0:0);
(A2A1[8] => V[13]) = (0:0:0, 0:0:0);
(A2A1[8] => V[14]) = (0:0:0, 0:0:0);
(A2A1[8] => V[15]) = (0:0:0, 0:0:0);
(A2A1[8] => V[16]) = (0:0:0, 0:0:0);
(A2A1[8] => V[17]) = (0:0:0, 0:0:0);
(A2A1[8] => V[18]) = (0:0:0, 0:0:0);
(A2A1[8] => V[19]) = (0:0:0, 0:0:0);
(A2A1[8] => V[20]) = (0:0:0, 0:0:0);
(A2A1[8] => V[21]) = (0:0:0, 0:0:0);
(A2A1[8] => V[22]) = (0:0:0, 0:0:0);
(A2A1[8] => V[23]) = (0:0:0, 0:0:0);
(A2A1[8] => V[24]) = (0:0:0, 0:0:0);
(A2A1[8] => V[25]) = (0:0:0, 0:0:0);
(A2A1[8] => V[26]) = (0:0:0, 0:0:0);
(A2A1[8] => V[27]) = (0:0:0, 0:0:0);
(A2A1[8] => V[28]) = (0:0:0, 0:0:0);
(A2A1[8] => V[8]) = (0:0:0, 0:0:0);
(A2A1[8] => V[9]) = (0:0:0, 0:0:0);
(A2A1[9] => U[10]) = (0:0:0, 0:0:0);
(A2A1[9] => U[11]) = (0:0:0, 0:0:0);
(A2A1[9] => U[12]) = (0:0:0, 0:0:0);
(A2A1[9] => U[13]) = (0:0:0, 0:0:0);
(A2A1[9] => U[14]) = (0:0:0, 0:0:0);
(A2A1[9] => U[15]) = (0:0:0, 0:0:0);
(A2A1[9] => U[16]) = (0:0:0, 0:0:0);
(A2A1[9] => U[17]) = (0:0:0, 0:0:0);
(A2A1[9] => U[18]) = (0:0:0, 0:0:0);
(A2A1[9] => U[19]) = (0:0:0, 0:0:0);
(A2A1[9] => U[20]) = (0:0:0, 0:0:0);
(A2A1[9] => U[21]) = (0:0:0, 0:0:0);
(A2A1[9] => U[22]) = (0:0:0, 0:0:0);
(A2A1[9] => U[23]) = (0:0:0, 0:0:0);
(A2A1[9] => U[24]) = (0:0:0, 0:0:0);
(A2A1[9] => U[25]) = (0:0:0, 0:0:0);
(A2A1[9] => U[26]) = (0:0:0, 0:0:0);
(A2A1[9] => U[27]) = (0:0:0, 0:0:0);
(A2A1[9] => U[28]) = (0:0:0, 0:0:0);
(A2A1[9] => U[29]) = (0:0:0, 0:0:0);
(A2A1[9] => U[30]) = (0:0:0, 0:0:0);
(A2A1[9] => V[10]) = (0:0:0, 0:0:0);
(A2A1[9] => V[11]) = (0:0:0, 0:0:0);
(A2A1[9] => V[12]) = (0:0:0, 0:0:0);
(A2A1[9] => V[13]) = (0:0:0, 0:0:0);
(A2A1[9] => V[14]) = (0:0:0, 0:0:0);
(A2A1[9] => V[15]) = (0:0:0, 0:0:0);
(A2A1[9] => V[16]) = (0:0:0, 0:0:0);
(A2A1[9] => V[17]) = (0:0:0, 0:0:0);
(A2A1[9] => V[18]) = (0:0:0, 0:0:0);
(A2A1[9] => V[19]) = (0:0:0, 0:0:0);
(A2A1[9] => V[20]) = (0:0:0, 0:0:0);
(A2A1[9] => V[21]) = (0:0:0, 0:0:0);
(A2A1[9] => V[22]) = (0:0:0, 0:0:0);
(A2A1[9] => V[23]) = (0:0:0, 0:0:0);
(A2A1[9] => V[24]) = (0:0:0, 0:0:0);
(A2A1[9] => V[25]) = (0:0:0, 0:0:0);
(A2A1[9] => V[26]) = (0:0:0, 0:0:0);
(A2A1[9] => V[27]) = (0:0:0, 0:0:0);
(A2A1[9] => V[28]) = (0:0:0, 0:0:0);
(A2A1[9] => V[29]) = (0:0:0, 0:0:0);
(A2A1[9] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[0] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[10] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[10] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[11] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[11] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[12] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[12] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[13] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[13] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[14] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[14] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[15] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[16] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => BMULT17) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[17] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[18] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[18] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[19] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[19] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[1]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[0]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[1] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[20] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[20] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[21] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[21] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[22] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[22] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[23] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[23] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[24] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[24] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[25] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[25] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => AMULT26) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => U[43]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[40]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[41]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[42]) = (0:0:0, 0:0:0);
(AD_DATA[26] => V[43]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[2] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[2]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[3]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[3] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[4] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[4]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[5]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[5] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[6] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[6]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[7]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[7] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[8] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[8] => V[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[40]) = (0:0:0, 0:0:0);
(AD_DATA[9] => U[9]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[10]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[11]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[12]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[13]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[14]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[15]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[16]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[17]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[18]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[19]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[20]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[21]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[22]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[23]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[24]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[25]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[26]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[27]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[28]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[29]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[30]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[31]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[32]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[33]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[34]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[35]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[36]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[37]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[38]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[39]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[8]) = (0:0:0, 0:0:0);
(AD_DATA[9] => V[9]) = (0:0:0, 0:0:0);
(B2B1[0] => U[10]) = (0:0:0, 0:0:0);
(B2B1[0] => U[11]) = (0:0:0, 0:0:0);
(B2B1[0] => U[12]) = (0:0:0, 0:0:0);
(B2B1[0] => U[13]) = (0:0:0, 0:0:0);
(B2B1[0] => U[14]) = (0:0:0, 0:0:0);
(B2B1[0] => U[15]) = (0:0:0, 0:0:0);
(B2B1[0] => U[16]) = (0:0:0, 0:0:0);
(B2B1[0] => U[17]) = (0:0:0, 0:0:0);
(B2B1[0] => U[18]) = (0:0:0, 0:0:0);
(B2B1[0] => U[19]) = (0:0:0, 0:0:0);
(B2B1[0] => U[1]) = (0:0:0, 0:0:0);
(B2B1[0] => U[20]) = (0:0:0, 0:0:0);
(B2B1[0] => U[21]) = (0:0:0, 0:0:0);
(B2B1[0] => U[22]) = (0:0:0, 0:0:0);
(B2B1[0] => U[23]) = (0:0:0, 0:0:0);
(B2B1[0] => U[24]) = (0:0:0, 0:0:0);
(B2B1[0] => U[25]) = (0:0:0, 0:0:0);
(B2B1[0] => U[26]) = (0:0:0, 0:0:0);
(B2B1[0] => U[27]) = (0:0:0, 0:0:0);
(B2B1[0] => U[28]) = (0:0:0, 0:0:0);
(B2B1[0] => U[29]) = (0:0:0, 0:0:0);
(B2B1[0] => U[2]) = (0:0:0, 0:0:0);
(B2B1[0] => U[30]) = (0:0:0, 0:0:0);
(B2B1[0] => U[31]) = (0:0:0, 0:0:0);
(B2B1[0] => U[3]) = (0:0:0, 0:0:0);
(B2B1[0] => U[4]) = (0:0:0, 0:0:0);
(B2B1[0] => U[5]) = (0:0:0, 0:0:0);
(B2B1[0] => U[6]) = (0:0:0, 0:0:0);
(B2B1[0] => U[7]) = (0:0:0, 0:0:0);
(B2B1[0] => U[8]) = (0:0:0, 0:0:0);
(B2B1[0] => U[9]) = (0:0:0, 0:0:0);
(B2B1[0] => V[0]) = (0:0:0, 0:0:0);
(B2B1[0] => V[10]) = (0:0:0, 0:0:0);
(B2B1[0] => V[11]) = (0:0:0, 0:0:0);
(B2B1[0] => V[12]) = (0:0:0, 0:0:0);
(B2B1[0] => V[13]) = (0:0:0, 0:0:0);
(B2B1[0] => V[14]) = (0:0:0, 0:0:0);
(B2B1[0] => V[15]) = (0:0:0, 0:0:0);
(B2B1[0] => V[16]) = (0:0:0, 0:0:0);
(B2B1[0] => V[17]) = (0:0:0, 0:0:0);
(B2B1[0] => V[18]) = (0:0:0, 0:0:0);
(B2B1[0] => V[19]) = (0:0:0, 0:0:0);
(B2B1[0] => V[20]) = (0:0:0, 0:0:0);
(B2B1[0] => V[21]) = (0:0:0, 0:0:0);
(B2B1[0] => V[22]) = (0:0:0, 0:0:0);
(B2B1[0] => V[23]) = (0:0:0, 0:0:0);
(B2B1[0] => V[24]) = (0:0:0, 0:0:0);
(B2B1[0] => V[25]) = (0:0:0, 0:0:0);
(B2B1[0] => V[26]) = (0:0:0, 0:0:0);
(B2B1[0] => V[27]) = (0:0:0, 0:0:0);
(B2B1[0] => V[28]) = (0:0:0, 0:0:0);
(B2B1[0] => V[29]) = (0:0:0, 0:0:0);
(B2B1[0] => V[30]) = (0:0:0, 0:0:0);
(B2B1[0] => V[4]) = (0:0:0, 0:0:0);
(B2B1[0] => V[5]) = (0:0:0, 0:0:0);
(B2B1[0] => V[6]) = (0:0:0, 0:0:0);
(B2B1[0] => V[7]) = (0:0:0, 0:0:0);
(B2B1[0] => V[8]) = (0:0:0, 0:0:0);
(B2B1[0] => V[9]) = (0:0:0, 0:0:0);
(B2B1[10] => U[11]) = (0:0:0, 0:0:0);
(B2B1[10] => U[12]) = (0:0:0, 0:0:0);
(B2B1[10] => U[13]) = (0:0:0, 0:0:0);
(B2B1[10] => U[14]) = (0:0:0, 0:0:0);
(B2B1[10] => U[15]) = (0:0:0, 0:0:0);
(B2B1[10] => U[16]) = (0:0:0, 0:0:0);
(B2B1[10] => U[17]) = (0:0:0, 0:0:0);
(B2B1[10] => U[18]) = (0:0:0, 0:0:0);
(B2B1[10] => U[19]) = (0:0:0, 0:0:0);
(B2B1[10] => U[20]) = (0:0:0, 0:0:0);
(B2B1[10] => U[21]) = (0:0:0, 0:0:0);
(B2B1[10] => U[22]) = (0:0:0, 0:0:0);
(B2B1[10] => U[23]) = (0:0:0, 0:0:0);
(B2B1[10] => U[24]) = (0:0:0, 0:0:0);
(B2B1[10] => U[25]) = (0:0:0, 0:0:0);
(B2B1[10] => U[26]) = (0:0:0, 0:0:0);
(B2B1[10] => U[27]) = (0:0:0, 0:0:0);
(B2B1[10] => U[28]) = (0:0:0, 0:0:0);
(B2B1[10] => U[29]) = (0:0:0, 0:0:0);
(B2B1[10] => U[30]) = (0:0:0, 0:0:0);
(B2B1[10] => U[31]) = (0:0:0, 0:0:0);
(B2B1[10] => U[32]) = (0:0:0, 0:0:0);
(B2B1[10] => U[33]) = (0:0:0, 0:0:0);
(B2B1[10] => U[34]) = (0:0:0, 0:0:0);
(B2B1[10] => U[35]) = (0:0:0, 0:0:0);
(B2B1[10] => U[36]) = (0:0:0, 0:0:0);
(B2B1[10] => U[37]) = (0:0:0, 0:0:0);
(B2B1[10] => U[38]) = (0:0:0, 0:0:0);
(B2B1[10] => U[39]) = (0:0:0, 0:0:0);
(B2B1[10] => U[40]) = (0:0:0, 0:0:0);
(B2B1[10] => V[10]) = (0:0:0, 0:0:0);
(B2B1[10] => V[11]) = (0:0:0, 0:0:0);
(B2B1[10] => V[12]) = (0:0:0, 0:0:0);
(B2B1[10] => V[13]) = (0:0:0, 0:0:0);
(B2B1[10] => V[14]) = (0:0:0, 0:0:0);
(B2B1[10] => V[15]) = (0:0:0, 0:0:0);
(B2B1[10] => V[16]) = (0:0:0, 0:0:0);
(B2B1[10] => V[17]) = (0:0:0, 0:0:0);
(B2B1[10] => V[18]) = (0:0:0, 0:0:0);
(B2B1[10] => V[19]) = (0:0:0, 0:0:0);
(B2B1[10] => V[20]) = (0:0:0, 0:0:0);
(B2B1[10] => V[21]) = (0:0:0, 0:0:0);
(B2B1[10] => V[22]) = (0:0:0, 0:0:0);
(B2B1[10] => V[23]) = (0:0:0, 0:0:0);
(B2B1[10] => V[24]) = (0:0:0, 0:0:0);
(B2B1[10] => V[25]) = (0:0:0, 0:0:0);
(B2B1[10] => V[26]) = (0:0:0, 0:0:0);
(B2B1[10] => V[27]) = (0:0:0, 0:0:0);
(B2B1[10] => V[28]) = (0:0:0, 0:0:0);
(B2B1[10] => V[29]) = (0:0:0, 0:0:0);
(B2B1[10] => V[30]) = (0:0:0, 0:0:0);
(B2B1[10] => V[31]) = (0:0:0, 0:0:0);
(B2B1[10] => V[32]) = (0:0:0, 0:0:0);
(B2B1[10] => V[33]) = (0:0:0, 0:0:0);
(B2B1[10] => V[34]) = (0:0:0, 0:0:0);
(B2B1[10] => V[35]) = (0:0:0, 0:0:0);
(B2B1[10] => V[36]) = (0:0:0, 0:0:0);
(B2B1[10] => V[37]) = (0:0:0, 0:0:0);
(B2B1[10] => V[38]) = (0:0:0, 0:0:0);
(B2B1[10] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[11]) = (0:0:0, 0:0:0);
(B2B1[11] => U[12]) = (0:0:0, 0:0:0);
(B2B1[11] => U[13]) = (0:0:0, 0:0:0);
(B2B1[11] => U[14]) = (0:0:0, 0:0:0);
(B2B1[11] => U[15]) = (0:0:0, 0:0:0);
(B2B1[11] => U[16]) = (0:0:0, 0:0:0);
(B2B1[11] => U[17]) = (0:0:0, 0:0:0);
(B2B1[11] => U[18]) = (0:0:0, 0:0:0);
(B2B1[11] => U[19]) = (0:0:0, 0:0:0);
(B2B1[11] => U[20]) = (0:0:0, 0:0:0);
(B2B1[11] => U[21]) = (0:0:0, 0:0:0);
(B2B1[11] => U[22]) = (0:0:0, 0:0:0);
(B2B1[11] => U[23]) = (0:0:0, 0:0:0);
(B2B1[11] => U[24]) = (0:0:0, 0:0:0);
(B2B1[11] => U[25]) = (0:0:0, 0:0:0);
(B2B1[11] => U[26]) = (0:0:0, 0:0:0);
(B2B1[11] => U[27]) = (0:0:0, 0:0:0);
(B2B1[11] => U[28]) = (0:0:0, 0:0:0);
(B2B1[11] => U[29]) = (0:0:0, 0:0:0);
(B2B1[11] => U[30]) = (0:0:0, 0:0:0);
(B2B1[11] => U[31]) = (0:0:0, 0:0:0);
(B2B1[11] => U[32]) = (0:0:0, 0:0:0);
(B2B1[11] => U[33]) = (0:0:0, 0:0:0);
(B2B1[11] => U[34]) = (0:0:0, 0:0:0);
(B2B1[11] => U[35]) = (0:0:0, 0:0:0);
(B2B1[11] => U[36]) = (0:0:0, 0:0:0);
(B2B1[11] => U[37]) = (0:0:0, 0:0:0);
(B2B1[11] => U[38]) = (0:0:0, 0:0:0);
(B2B1[11] => U[39]) = (0:0:0, 0:0:0);
(B2B1[11] => U[40]) = (0:0:0, 0:0:0);
(B2B1[11] => U[41]) = (0:0:0, 0:0:0);
(B2B1[11] => V[10]) = (0:0:0, 0:0:0);
(B2B1[11] => V[11]) = (0:0:0, 0:0:0);
(B2B1[11] => V[12]) = (0:0:0, 0:0:0);
(B2B1[11] => V[13]) = (0:0:0, 0:0:0);
(B2B1[11] => V[14]) = (0:0:0, 0:0:0);
(B2B1[11] => V[15]) = (0:0:0, 0:0:0);
(B2B1[11] => V[16]) = (0:0:0, 0:0:0);
(B2B1[11] => V[17]) = (0:0:0, 0:0:0);
(B2B1[11] => V[18]) = (0:0:0, 0:0:0);
(B2B1[11] => V[19]) = (0:0:0, 0:0:0);
(B2B1[11] => V[20]) = (0:0:0, 0:0:0);
(B2B1[11] => V[21]) = (0:0:0, 0:0:0);
(B2B1[11] => V[22]) = (0:0:0, 0:0:0);
(B2B1[11] => V[23]) = (0:0:0, 0:0:0);
(B2B1[11] => V[24]) = (0:0:0, 0:0:0);
(B2B1[11] => V[25]) = (0:0:0, 0:0:0);
(B2B1[11] => V[26]) = (0:0:0, 0:0:0);
(B2B1[11] => V[27]) = (0:0:0, 0:0:0);
(B2B1[11] => V[28]) = (0:0:0, 0:0:0);
(B2B1[11] => V[29]) = (0:0:0, 0:0:0);
(B2B1[11] => V[30]) = (0:0:0, 0:0:0);
(B2B1[11] => V[31]) = (0:0:0, 0:0:0);
(B2B1[11] => V[32]) = (0:0:0, 0:0:0);
(B2B1[11] => V[33]) = (0:0:0, 0:0:0);
(B2B1[11] => V[34]) = (0:0:0, 0:0:0);
(B2B1[11] => V[35]) = (0:0:0, 0:0:0);
(B2B1[11] => V[36]) = (0:0:0, 0:0:0);
(B2B1[11] => V[37]) = (0:0:0, 0:0:0);
(B2B1[11] => V[38]) = (0:0:0, 0:0:0);
(B2B1[11] => V[39]) = (0:0:0, 0:0:0);
(B2B1[11] => V[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[13]) = (0:0:0, 0:0:0);
(B2B1[12] => U[14]) = (0:0:0, 0:0:0);
(B2B1[12] => U[15]) = (0:0:0, 0:0:0);
(B2B1[12] => U[16]) = (0:0:0, 0:0:0);
(B2B1[12] => U[17]) = (0:0:0, 0:0:0);
(B2B1[12] => U[18]) = (0:0:0, 0:0:0);
(B2B1[12] => U[19]) = (0:0:0, 0:0:0);
(B2B1[12] => U[20]) = (0:0:0, 0:0:0);
(B2B1[12] => U[21]) = (0:0:0, 0:0:0);
(B2B1[12] => U[22]) = (0:0:0, 0:0:0);
(B2B1[12] => U[23]) = (0:0:0, 0:0:0);
(B2B1[12] => U[24]) = (0:0:0, 0:0:0);
(B2B1[12] => U[25]) = (0:0:0, 0:0:0);
(B2B1[12] => U[26]) = (0:0:0, 0:0:0);
(B2B1[12] => U[27]) = (0:0:0, 0:0:0);
(B2B1[12] => U[28]) = (0:0:0, 0:0:0);
(B2B1[12] => U[29]) = (0:0:0, 0:0:0);
(B2B1[12] => U[30]) = (0:0:0, 0:0:0);
(B2B1[12] => U[31]) = (0:0:0, 0:0:0);
(B2B1[12] => U[32]) = (0:0:0, 0:0:0);
(B2B1[12] => U[33]) = (0:0:0, 0:0:0);
(B2B1[12] => U[34]) = (0:0:0, 0:0:0);
(B2B1[12] => U[35]) = (0:0:0, 0:0:0);
(B2B1[12] => U[36]) = (0:0:0, 0:0:0);
(B2B1[12] => U[37]) = (0:0:0, 0:0:0);
(B2B1[12] => U[38]) = (0:0:0, 0:0:0);
(B2B1[12] => U[39]) = (0:0:0, 0:0:0);
(B2B1[12] => U[40]) = (0:0:0, 0:0:0);
(B2B1[12] => U[41]) = (0:0:0, 0:0:0);
(B2B1[12] => V[12]) = (0:0:0, 0:0:0);
(B2B1[12] => V[13]) = (0:0:0, 0:0:0);
(B2B1[12] => V[14]) = (0:0:0, 0:0:0);
(B2B1[12] => V[15]) = (0:0:0, 0:0:0);
(B2B1[12] => V[16]) = (0:0:0, 0:0:0);
(B2B1[12] => V[17]) = (0:0:0, 0:0:0);
(B2B1[12] => V[18]) = (0:0:0, 0:0:0);
(B2B1[12] => V[19]) = (0:0:0, 0:0:0);
(B2B1[12] => V[20]) = (0:0:0, 0:0:0);
(B2B1[12] => V[21]) = (0:0:0, 0:0:0);
(B2B1[12] => V[22]) = (0:0:0, 0:0:0);
(B2B1[12] => V[23]) = (0:0:0, 0:0:0);
(B2B1[12] => V[24]) = (0:0:0, 0:0:0);
(B2B1[12] => V[25]) = (0:0:0, 0:0:0);
(B2B1[12] => V[26]) = (0:0:0, 0:0:0);
(B2B1[12] => V[27]) = (0:0:0, 0:0:0);
(B2B1[12] => V[28]) = (0:0:0, 0:0:0);
(B2B1[12] => V[29]) = (0:0:0, 0:0:0);
(B2B1[12] => V[30]) = (0:0:0, 0:0:0);
(B2B1[12] => V[31]) = (0:0:0, 0:0:0);
(B2B1[12] => V[32]) = (0:0:0, 0:0:0);
(B2B1[12] => V[33]) = (0:0:0, 0:0:0);
(B2B1[12] => V[34]) = (0:0:0, 0:0:0);
(B2B1[12] => V[35]) = (0:0:0, 0:0:0);
(B2B1[12] => V[36]) = (0:0:0, 0:0:0);
(B2B1[12] => V[37]) = (0:0:0, 0:0:0);
(B2B1[12] => V[38]) = (0:0:0, 0:0:0);
(B2B1[12] => V[39]) = (0:0:0, 0:0:0);
(B2B1[12] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[13]) = (0:0:0, 0:0:0);
(B2B1[13] => U[14]) = (0:0:0, 0:0:0);
(B2B1[13] => U[15]) = (0:0:0, 0:0:0);
(B2B1[13] => U[16]) = (0:0:0, 0:0:0);
(B2B1[13] => U[17]) = (0:0:0, 0:0:0);
(B2B1[13] => U[18]) = (0:0:0, 0:0:0);
(B2B1[13] => U[19]) = (0:0:0, 0:0:0);
(B2B1[13] => U[20]) = (0:0:0, 0:0:0);
(B2B1[13] => U[21]) = (0:0:0, 0:0:0);
(B2B1[13] => U[22]) = (0:0:0, 0:0:0);
(B2B1[13] => U[23]) = (0:0:0, 0:0:0);
(B2B1[13] => U[24]) = (0:0:0, 0:0:0);
(B2B1[13] => U[25]) = (0:0:0, 0:0:0);
(B2B1[13] => U[26]) = (0:0:0, 0:0:0);
(B2B1[13] => U[27]) = (0:0:0, 0:0:0);
(B2B1[13] => U[28]) = (0:0:0, 0:0:0);
(B2B1[13] => U[29]) = (0:0:0, 0:0:0);
(B2B1[13] => U[30]) = (0:0:0, 0:0:0);
(B2B1[13] => U[31]) = (0:0:0, 0:0:0);
(B2B1[13] => U[32]) = (0:0:0, 0:0:0);
(B2B1[13] => U[33]) = (0:0:0, 0:0:0);
(B2B1[13] => U[34]) = (0:0:0, 0:0:0);
(B2B1[13] => U[35]) = (0:0:0, 0:0:0);
(B2B1[13] => U[36]) = (0:0:0, 0:0:0);
(B2B1[13] => U[37]) = (0:0:0, 0:0:0);
(B2B1[13] => U[38]) = (0:0:0, 0:0:0);
(B2B1[13] => U[39]) = (0:0:0, 0:0:0);
(B2B1[13] => U[40]) = (0:0:0, 0:0:0);
(B2B1[13] => U[41]) = (0:0:0, 0:0:0);
(B2B1[13] => U[42]) = (0:0:0, 0:0:0);
(B2B1[13] => V[12]) = (0:0:0, 0:0:0);
(B2B1[13] => V[13]) = (0:0:0, 0:0:0);
(B2B1[13] => V[14]) = (0:0:0, 0:0:0);
(B2B1[13] => V[15]) = (0:0:0, 0:0:0);
(B2B1[13] => V[16]) = (0:0:0, 0:0:0);
(B2B1[13] => V[17]) = (0:0:0, 0:0:0);
(B2B1[13] => V[18]) = (0:0:0, 0:0:0);
(B2B1[13] => V[19]) = (0:0:0, 0:0:0);
(B2B1[13] => V[20]) = (0:0:0, 0:0:0);
(B2B1[13] => V[21]) = (0:0:0, 0:0:0);
(B2B1[13] => V[22]) = (0:0:0, 0:0:0);
(B2B1[13] => V[23]) = (0:0:0, 0:0:0);
(B2B1[13] => V[24]) = (0:0:0, 0:0:0);
(B2B1[13] => V[25]) = (0:0:0, 0:0:0);
(B2B1[13] => V[26]) = (0:0:0, 0:0:0);
(B2B1[13] => V[27]) = (0:0:0, 0:0:0);
(B2B1[13] => V[28]) = (0:0:0, 0:0:0);
(B2B1[13] => V[29]) = (0:0:0, 0:0:0);
(B2B1[13] => V[30]) = (0:0:0, 0:0:0);
(B2B1[13] => V[31]) = (0:0:0, 0:0:0);
(B2B1[13] => V[32]) = (0:0:0, 0:0:0);
(B2B1[13] => V[33]) = (0:0:0, 0:0:0);
(B2B1[13] => V[34]) = (0:0:0, 0:0:0);
(B2B1[13] => V[35]) = (0:0:0, 0:0:0);
(B2B1[13] => V[36]) = (0:0:0, 0:0:0);
(B2B1[13] => V[37]) = (0:0:0, 0:0:0);
(B2B1[13] => V[38]) = (0:0:0, 0:0:0);
(B2B1[13] => V[39]) = (0:0:0, 0:0:0);
(B2B1[13] => V[40]) = (0:0:0, 0:0:0);
(B2B1[13] => V[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[15]) = (0:0:0, 0:0:0);
(B2B1[14] => U[16]) = (0:0:0, 0:0:0);
(B2B1[14] => U[17]) = (0:0:0, 0:0:0);
(B2B1[14] => U[18]) = (0:0:0, 0:0:0);
(B2B1[14] => U[19]) = (0:0:0, 0:0:0);
(B2B1[14] => U[20]) = (0:0:0, 0:0:0);
(B2B1[14] => U[21]) = (0:0:0, 0:0:0);
(B2B1[14] => U[22]) = (0:0:0, 0:0:0);
(B2B1[14] => U[23]) = (0:0:0, 0:0:0);
(B2B1[14] => U[24]) = (0:0:0, 0:0:0);
(B2B1[14] => U[25]) = (0:0:0, 0:0:0);
(B2B1[14] => U[26]) = (0:0:0, 0:0:0);
(B2B1[14] => U[27]) = (0:0:0, 0:0:0);
(B2B1[14] => U[28]) = (0:0:0, 0:0:0);
(B2B1[14] => U[29]) = (0:0:0, 0:0:0);
(B2B1[14] => U[30]) = (0:0:0, 0:0:0);
(B2B1[14] => U[31]) = (0:0:0, 0:0:0);
(B2B1[14] => U[32]) = (0:0:0, 0:0:0);
(B2B1[14] => U[33]) = (0:0:0, 0:0:0);
(B2B1[14] => U[34]) = (0:0:0, 0:0:0);
(B2B1[14] => U[35]) = (0:0:0, 0:0:0);
(B2B1[14] => U[36]) = (0:0:0, 0:0:0);
(B2B1[14] => U[37]) = (0:0:0, 0:0:0);
(B2B1[14] => U[38]) = (0:0:0, 0:0:0);
(B2B1[14] => U[39]) = (0:0:0, 0:0:0);
(B2B1[14] => U[40]) = (0:0:0, 0:0:0);
(B2B1[14] => U[41]) = (0:0:0, 0:0:0);
(B2B1[14] => U[42]) = (0:0:0, 0:0:0);
(B2B1[14] => V[14]) = (0:0:0, 0:0:0);
(B2B1[14] => V[15]) = (0:0:0, 0:0:0);
(B2B1[14] => V[16]) = (0:0:0, 0:0:0);
(B2B1[14] => V[17]) = (0:0:0, 0:0:0);
(B2B1[14] => V[18]) = (0:0:0, 0:0:0);
(B2B1[14] => V[19]) = (0:0:0, 0:0:0);
(B2B1[14] => V[20]) = (0:0:0, 0:0:0);
(B2B1[14] => V[21]) = (0:0:0, 0:0:0);
(B2B1[14] => V[22]) = (0:0:0, 0:0:0);
(B2B1[14] => V[23]) = (0:0:0, 0:0:0);
(B2B1[14] => V[24]) = (0:0:0, 0:0:0);
(B2B1[14] => V[25]) = (0:0:0, 0:0:0);
(B2B1[14] => V[26]) = (0:0:0, 0:0:0);
(B2B1[14] => V[27]) = (0:0:0, 0:0:0);
(B2B1[14] => V[28]) = (0:0:0, 0:0:0);
(B2B1[14] => V[29]) = (0:0:0, 0:0:0);
(B2B1[14] => V[30]) = (0:0:0, 0:0:0);
(B2B1[14] => V[31]) = (0:0:0, 0:0:0);
(B2B1[14] => V[32]) = (0:0:0, 0:0:0);
(B2B1[14] => V[33]) = (0:0:0, 0:0:0);
(B2B1[14] => V[34]) = (0:0:0, 0:0:0);
(B2B1[14] => V[35]) = (0:0:0, 0:0:0);
(B2B1[14] => V[36]) = (0:0:0, 0:0:0);
(B2B1[14] => V[37]) = (0:0:0, 0:0:0);
(B2B1[14] => V[38]) = (0:0:0, 0:0:0);
(B2B1[14] => V[39]) = (0:0:0, 0:0:0);
(B2B1[14] => V[40]) = (0:0:0, 0:0:0);
(B2B1[14] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[15]) = (0:0:0, 0:0:0);
(B2B1[15] => U[16]) = (0:0:0, 0:0:0);
(B2B1[15] => U[17]) = (0:0:0, 0:0:0);
(B2B1[15] => U[18]) = (0:0:0, 0:0:0);
(B2B1[15] => U[19]) = (0:0:0, 0:0:0);
(B2B1[15] => U[20]) = (0:0:0, 0:0:0);
(B2B1[15] => U[21]) = (0:0:0, 0:0:0);
(B2B1[15] => U[22]) = (0:0:0, 0:0:0);
(B2B1[15] => U[23]) = (0:0:0, 0:0:0);
(B2B1[15] => U[24]) = (0:0:0, 0:0:0);
(B2B1[15] => U[25]) = (0:0:0, 0:0:0);
(B2B1[15] => U[26]) = (0:0:0, 0:0:0);
(B2B1[15] => U[27]) = (0:0:0, 0:0:0);
(B2B1[15] => U[28]) = (0:0:0, 0:0:0);
(B2B1[15] => U[29]) = (0:0:0, 0:0:0);
(B2B1[15] => U[30]) = (0:0:0, 0:0:0);
(B2B1[15] => U[31]) = (0:0:0, 0:0:0);
(B2B1[15] => U[32]) = (0:0:0, 0:0:0);
(B2B1[15] => U[33]) = (0:0:0, 0:0:0);
(B2B1[15] => U[34]) = (0:0:0, 0:0:0);
(B2B1[15] => U[35]) = (0:0:0, 0:0:0);
(B2B1[15] => U[36]) = (0:0:0, 0:0:0);
(B2B1[15] => U[37]) = (0:0:0, 0:0:0);
(B2B1[15] => U[38]) = (0:0:0, 0:0:0);
(B2B1[15] => U[39]) = (0:0:0, 0:0:0);
(B2B1[15] => U[40]) = (0:0:0, 0:0:0);
(B2B1[15] => U[41]) = (0:0:0, 0:0:0);
(B2B1[15] => U[42]) = (0:0:0, 0:0:0);
(B2B1[15] => U[43]) = (0:0:0, 0:0:0);
(B2B1[15] => V[14]) = (0:0:0, 0:0:0);
(B2B1[15] => V[15]) = (0:0:0, 0:0:0);
(B2B1[15] => V[16]) = (0:0:0, 0:0:0);
(B2B1[15] => V[17]) = (0:0:0, 0:0:0);
(B2B1[15] => V[18]) = (0:0:0, 0:0:0);
(B2B1[15] => V[19]) = (0:0:0, 0:0:0);
(B2B1[15] => V[20]) = (0:0:0, 0:0:0);
(B2B1[15] => V[21]) = (0:0:0, 0:0:0);
(B2B1[15] => V[22]) = (0:0:0, 0:0:0);
(B2B1[15] => V[23]) = (0:0:0, 0:0:0);
(B2B1[15] => V[24]) = (0:0:0, 0:0:0);
(B2B1[15] => V[25]) = (0:0:0, 0:0:0);
(B2B1[15] => V[26]) = (0:0:0, 0:0:0);
(B2B1[15] => V[27]) = (0:0:0, 0:0:0);
(B2B1[15] => V[28]) = (0:0:0, 0:0:0);
(B2B1[15] => V[29]) = (0:0:0, 0:0:0);
(B2B1[15] => V[30]) = (0:0:0, 0:0:0);
(B2B1[15] => V[31]) = (0:0:0, 0:0:0);
(B2B1[15] => V[32]) = (0:0:0, 0:0:0);
(B2B1[15] => V[33]) = (0:0:0, 0:0:0);
(B2B1[15] => V[34]) = (0:0:0, 0:0:0);
(B2B1[15] => V[35]) = (0:0:0, 0:0:0);
(B2B1[15] => V[36]) = (0:0:0, 0:0:0);
(B2B1[15] => V[37]) = (0:0:0, 0:0:0);
(B2B1[15] => V[38]) = (0:0:0, 0:0:0);
(B2B1[15] => V[39]) = (0:0:0, 0:0:0);
(B2B1[15] => V[40]) = (0:0:0, 0:0:0);
(B2B1[15] => V[41]) = (0:0:0, 0:0:0);
(B2B1[15] => V[42]) = (0:0:0, 0:0:0);
(B2B1[15] => V[43]) = (0:0:0, 0:0:0);
(B2B1[16] => U[17]) = (0:0:0, 0:0:0);
(B2B1[16] => U[18]) = (0:0:0, 0:0:0);
(B2B1[16] => U[19]) = (0:0:0, 0:0:0);
(B2B1[16] => U[20]) = (0:0:0, 0:0:0);
(B2B1[16] => U[21]) = (0:0:0, 0:0:0);
(B2B1[16] => U[22]) = (0:0:0, 0:0:0);
(B2B1[16] => U[23]) = (0:0:0, 0:0:0);
(B2B1[16] => U[24]) = (0:0:0, 0:0:0);
(B2B1[16] => U[25]) = (0:0:0, 0:0:0);
(B2B1[16] => U[26]) = (0:0:0, 0:0:0);
(B2B1[16] => U[27]) = (0:0:0, 0:0:0);
(B2B1[16] => U[28]) = (0:0:0, 0:0:0);
(B2B1[16] => U[29]) = (0:0:0, 0:0:0);
(B2B1[16] => U[30]) = (0:0:0, 0:0:0);
(B2B1[16] => U[31]) = (0:0:0, 0:0:0);
(B2B1[16] => U[32]) = (0:0:0, 0:0:0);
(B2B1[16] => U[33]) = (0:0:0, 0:0:0);
(B2B1[16] => U[34]) = (0:0:0, 0:0:0);
(B2B1[16] => U[35]) = (0:0:0, 0:0:0);
(B2B1[16] => U[36]) = (0:0:0, 0:0:0);
(B2B1[16] => U[37]) = (0:0:0, 0:0:0);
(B2B1[16] => U[38]) = (0:0:0, 0:0:0);
(B2B1[16] => U[39]) = (0:0:0, 0:0:0);
(B2B1[16] => U[40]) = (0:0:0, 0:0:0);
(B2B1[16] => U[41]) = (0:0:0, 0:0:0);
(B2B1[16] => U[42]) = (0:0:0, 0:0:0);
(B2B1[16] => U[43]) = (0:0:0, 0:0:0);
(B2B1[16] => V[16]) = (0:0:0, 0:0:0);
(B2B1[16] => V[17]) = (0:0:0, 0:0:0);
(B2B1[16] => V[18]) = (0:0:0, 0:0:0);
(B2B1[16] => V[19]) = (0:0:0, 0:0:0);
(B2B1[16] => V[20]) = (0:0:0, 0:0:0);
(B2B1[16] => V[21]) = (0:0:0, 0:0:0);
(B2B1[16] => V[22]) = (0:0:0, 0:0:0);
(B2B1[16] => V[23]) = (0:0:0, 0:0:0);
(B2B1[16] => V[24]) = (0:0:0, 0:0:0);
(B2B1[16] => V[25]) = (0:0:0, 0:0:0);
(B2B1[16] => V[26]) = (0:0:0, 0:0:0);
(B2B1[16] => V[27]) = (0:0:0, 0:0:0);
(B2B1[16] => V[28]) = (0:0:0, 0:0:0);
(B2B1[16] => V[29]) = (0:0:0, 0:0:0);
(B2B1[16] => V[30]) = (0:0:0, 0:0:0);
(B2B1[16] => V[31]) = (0:0:0, 0:0:0);
(B2B1[16] => V[32]) = (0:0:0, 0:0:0);
(B2B1[16] => V[33]) = (0:0:0, 0:0:0);
(B2B1[16] => V[34]) = (0:0:0, 0:0:0);
(B2B1[16] => V[35]) = (0:0:0, 0:0:0);
(B2B1[16] => V[36]) = (0:0:0, 0:0:0);
(B2B1[16] => V[37]) = (0:0:0, 0:0:0);
(B2B1[16] => V[38]) = (0:0:0, 0:0:0);
(B2B1[16] => V[39]) = (0:0:0, 0:0:0);
(B2B1[16] => V[40]) = (0:0:0, 0:0:0);
(B2B1[16] => V[41]) = (0:0:0, 0:0:0);
(B2B1[16] => V[42]) = (0:0:0, 0:0:0);
(B2B1[16] => V[43]) = (0:0:0, 0:0:0);
(B2B1[17] => BMULT17) = (0:0:0, 0:0:0);
(B2B1[17] => U[17]) = (0:0:0, 0:0:0);
(B2B1[17] => U[18]) = (0:0:0, 0:0:0);
(B2B1[17] => U[19]) = (0:0:0, 0:0:0);
(B2B1[17] => U[20]) = (0:0:0, 0:0:0);
(B2B1[17] => U[21]) = (0:0:0, 0:0:0);
(B2B1[17] => U[22]) = (0:0:0, 0:0:0);
(B2B1[17] => U[23]) = (0:0:0, 0:0:0);
(B2B1[17] => U[24]) = (0:0:0, 0:0:0);
(B2B1[17] => U[25]) = (0:0:0, 0:0:0);
(B2B1[17] => U[26]) = (0:0:0, 0:0:0);
(B2B1[17] => U[27]) = (0:0:0, 0:0:0);
(B2B1[17] => U[28]) = (0:0:0, 0:0:0);
(B2B1[17] => U[29]) = (0:0:0, 0:0:0);
(B2B1[17] => U[30]) = (0:0:0, 0:0:0);
(B2B1[17] => U[31]) = (0:0:0, 0:0:0);
(B2B1[17] => U[32]) = (0:0:0, 0:0:0);
(B2B1[17] => U[33]) = (0:0:0, 0:0:0);
(B2B1[17] => U[34]) = (0:0:0, 0:0:0);
(B2B1[17] => U[35]) = (0:0:0, 0:0:0);
(B2B1[17] => U[36]) = (0:0:0, 0:0:0);
(B2B1[17] => U[37]) = (0:0:0, 0:0:0);
(B2B1[17] => U[38]) = (0:0:0, 0:0:0);
(B2B1[17] => U[39]) = (0:0:0, 0:0:0);
(B2B1[17] => U[40]) = (0:0:0, 0:0:0);
(B2B1[17] => U[41]) = (0:0:0, 0:0:0);
(B2B1[17] => U[42]) = (0:0:0, 0:0:0);
(B2B1[17] => U[43]) = (0:0:0, 0:0:0);
(B2B1[17] => V[16]) = (0:0:0, 0:0:0);
(B2B1[17] => V[17]) = (0:0:0, 0:0:0);
(B2B1[17] => V[18]) = (0:0:0, 0:0:0);
(B2B1[17] => V[19]) = (0:0:0, 0:0:0);
(B2B1[17] => V[20]) = (0:0:0, 0:0:0);
(B2B1[17] => V[21]) = (0:0:0, 0:0:0);
(B2B1[17] => V[22]) = (0:0:0, 0:0:0);
(B2B1[17] => V[23]) = (0:0:0, 0:0:0);
(B2B1[17] => V[24]) = (0:0:0, 0:0:0);
(B2B1[17] => V[25]) = (0:0:0, 0:0:0);
(B2B1[17] => V[26]) = (0:0:0, 0:0:0);
(B2B1[17] => V[27]) = (0:0:0, 0:0:0);
(B2B1[17] => V[28]) = (0:0:0, 0:0:0);
(B2B1[17] => V[29]) = (0:0:0, 0:0:0);
(B2B1[17] => V[30]) = (0:0:0, 0:0:0);
(B2B1[17] => V[31]) = (0:0:0, 0:0:0);
(B2B1[17] => V[32]) = (0:0:0, 0:0:0);
(B2B1[17] => V[33]) = (0:0:0, 0:0:0);
(B2B1[17] => V[34]) = (0:0:0, 0:0:0);
(B2B1[17] => V[35]) = (0:0:0, 0:0:0);
(B2B1[17] => V[36]) = (0:0:0, 0:0:0);
(B2B1[17] => V[37]) = (0:0:0, 0:0:0);
(B2B1[17] => V[38]) = (0:0:0, 0:0:0);
(B2B1[17] => V[39]) = (0:0:0, 0:0:0);
(B2B1[17] => V[40]) = (0:0:0, 0:0:0);
(B2B1[17] => V[41]) = (0:0:0, 0:0:0);
(B2B1[17] => V[42]) = (0:0:0, 0:0:0);
(B2B1[17] => V[43]) = (0:0:0, 0:0:0);
(B2B1[1] => U[0]) = (0:0:0, 0:0:0);
(B2B1[1] => U[10]) = (0:0:0, 0:0:0);
(B2B1[1] => U[11]) = (0:0:0, 0:0:0);
(B2B1[1] => U[12]) = (0:0:0, 0:0:0);
(B2B1[1] => U[13]) = (0:0:0, 0:0:0);
(B2B1[1] => U[14]) = (0:0:0, 0:0:0);
(B2B1[1] => U[15]) = (0:0:0, 0:0:0);
(B2B1[1] => U[16]) = (0:0:0, 0:0:0);
(B2B1[1] => U[17]) = (0:0:0, 0:0:0);
(B2B1[1] => U[18]) = (0:0:0, 0:0:0);
(B2B1[1] => U[19]) = (0:0:0, 0:0:0);
(B2B1[1] => U[1]) = (0:0:0, 0:0:0);
(B2B1[1] => U[20]) = (0:0:0, 0:0:0);
(B2B1[1] => U[21]) = (0:0:0, 0:0:0);
(B2B1[1] => U[22]) = (0:0:0, 0:0:0);
(B2B1[1] => U[23]) = (0:0:0, 0:0:0);
(B2B1[1] => U[24]) = (0:0:0, 0:0:0);
(B2B1[1] => U[25]) = (0:0:0, 0:0:0);
(B2B1[1] => U[26]) = (0:0:0, 0:0:0);
(B2B1[1] => U[27]) = (0:0:0, 0:0:0);
(B2B1[1] => U[28]) = (0:0:0, 0:0:0);
(B2B1[1] => U[29]) = (0:0:0, 0:0:0);
(B2B1[1] => U[2]) = (0:0:0, 0:0:0);
(B2B1[1] => U[30]) = (0:0:0, 0:0:0);
(B2B1[1] => U[31]) = (0:0:0, 0:0:0);
(B2B1[1] => U[32]) = (0:0:0, 0:0:0);
(B2B1[1] => U[33]) = (0:0:0, 0:0:0);
(B2B1[1] => U[3]) = (0:0:0, 0:0:0);
(B2B1[1] => U[4]) = (0:0:0, 0:0:0);
(B2B1[1] => U[5]) = (0:0:0, 0:0:0);
(B2B1[1] => U[6]) = (0:0:0, 0:0:0);
(B2B1[1] => U[7]) = (0:0:0, 0:0:0);
(B2B1[1] => U[8]) = (0:0:0, 0:0:0);
(B2B1[1] => U[9]) = (0:0:0, 0:0:0);
(B2B1[1] => V[0]) = (0:0:0, 0:0:0);
(B2B1[1] => V[10]) = (0:0:0, 0:0:0);
(B2B1[1] => V[11]) = (0:0:0, 0:0:0);
(B2B1[1] => V[12]) = (0:0:0, 0:0:0);
(B2B1[1] => V[13]) = (0:0:0, 0:0:0);
(B2B1[1] => V[14]) = (0:0:0, 0:0:0);
(B2B1[1] => V[15]) = (0:0:0, 0:0:0);
(B2B1[1] => V[16]) = (0:0:0, 0:0:0);
(B2B1[1] => V[17]) = (0:0:0, 0:0:0);
(B2B1[1] => V[18]) = (0:0:0, 0:0:0);
(B2B1[1] => V[19]) = (0:0:0, 0:0:0);
(B2B1[1] => V[20]) = (0:0:0, 0:0:0);
(B2B1[1] => V[21]) = (0:0:0, 0:0:0);
(B2B1[1] => V[22]) = (0:0:0, 0:0:0);
(B2B1[1] => V[23]) = (0:0:0, 0:0:0);
(B2B1[1] => V[24]) = (0:0:0, 0:0:0);
(B2B1[1] => V[25]) = (0:0:0, 0:0:0);
(B2B1[1] => V[26]) = (0:0:0, 0:0:0);
(B2B1[1] => V[27]) = (0:0:0, 0:0:0);
(B2B1[1] => V[28]) = (0:0:0, 0:0:0);
(B2B1[1] => V[29]) = (0:0:0, 0:0:0);
(B2B1[1] => V[30]) = (0:0:0, 0:0:0);
(B2B1[1] => V[31]) = (0:0:0, 0:0:0);
(B2B1[1] => V[32]) = (0:0:0, 0:0:0);
(B2B1[1] => V[4]) = (0:0:0, 0:0:0);
(B2B1[1] => V[5]) = (0:0:0, 0:0:0);
(B2B1[1] => V[6]) = (0:0:0, 0:0:0);
(B2B1[1] => V[7]) = (0:0:0, 0:0:0);
(B2B1[1] => V[8]) = (0:0:0, 0:0:0);
(B2B1[1] => V[9]) = (0:0:0, 0:0:0);
(B2B1[2] => U[10]) = (0:0:0, 0:0:0);
(B2B1[2] => U[11]) = (0:0:0, 0:0:0);
(B2B1[2] => U[12]) = (0:0:0, 0:0:0);
(B2B1[2] => U[13]) = (0:0:0, 0:0:0);
(B2B1[2] => U[14]) = (0:0:0, 0:0:0);
(B2B1[2] => U[15]) = (0:0:0, 0:0:0);
(B2B1[2] => U[16]) = (0:0:0, 0:0:0);
(B2B1[2] => U[17]) = (0:0:0, 0:0:0);
(B2B1[2] => U[18]) = (0:0:0, 0:0:0);
(B2B1[2] => U[19]) = (0:0:0, 0:0:0);
(B2B1[2] => U[20]) = (0:0:0, 0:0:0);
(B2B1[2] => U[21]) = (0:0:0, 0:0:0);
(B2B1[2] => U[22]) = (0:0:0, 0:0:0);
(B2B1[2] => U[23]) = (0:0:0, 0:0:0);
(B2B1[2] => U[24]) = (0:0:0, 0:0:0);
(B2B1[2] => U[25]) = (0:0:0, 0:0:0);
(B2B1[2] => U[26]) = (0:0:0, 0:0:0);
(B2B1[2] => U[27]) = (0:0:0, 0:0:0);
(B2B1[2] => U[28]) = (0:0:0, 0:0:0);
(B2B1[2] => U[29]) = (0:0:0, 0:0:0);
(B2B1[2] => U[2]) = (0:0:0, 0:0:0);
(B2B1[2] => U[30]) = (0:0:0, 0:0:0);
(B2B1[2] => U[31]) = (0:0:0, 0:0:0);
(B2B1[2] => U[32]) = (0:0:0, 0:0:0);
(B2B1[2] => U[33]) = (0:0:0, 0:0:0);
(B2B1[2] => U[3]) = (0:0:0, 0:0:0);
(B2B1[2] => U[4]) = (0:0:0, 0:0:0);
(B2B1[2] => U[5]) = (0:0:0, 0:0:0);
(B2B1[2] => U[6]) = (0:0:0, 0:0:0);
(B2B1[2] => U[7]) = (0:0:0, 0:0:0);
(B2B1[2] => U[8]) = (0:0:0, 0:0:0);
(B2B1[2] => U[9]) = (0:0:0, 0:0:0);
(B2B1[2] => V[10]) = (0:0:0, 0:0:0);
(B2B1[2] => V[11]) = (0:0:0, 0:0:0);
(B2B1[2] => V[12]) = (0:0:0, 0:0:0);
(B2B1[2] => V[13]) = (0:0:0, 0:0:0);
(B2B1[2] => V[14]) = (0:0:0, 0:0:0);
(B2B1[2] => V[15]) = (0:0:0, 0:0:0);
(B2B1[2] => V[16]) = (0:0:0, 0:0:0);
(B2B1[2] => V[17]) = (0:0:0, 0:0:0);
(B2B1[2] => V[18]) = (0:0:0, 0:0:0);
(B2B1[2] => V[19]) = (0:0:0, 0:0:0);
(B2B1[2] => V[20]) = (0:0:0, 0:0:0);
(B2B1[2] => V[21]) = (0:0:0, 0:0:0);
(B2B1[2] => V[22]) = (0:0:0, 0:0:0);
(B2B1[2] => V[23]) = (0:0:0, 0:0:0);
(B2B1[2] => V[24]) = (0:0:0, 0:0:0);
(B2B1[2] => V[25]) = (0:0:0, 0:0:0);
(B2B1[2] => V[26]) = (0:0:0, 0:0:0);
(B2B1[2] => V[27]) = (0:0:0, 0:0:0);
(B2B1[2] => V[28]) = (0:0:0, 0:0:0);
(B2B1[2] => V[29]) = (0:0:0, 0:0:0);
(B2B1[2] => V[30]) = (0:0:0, 0:0:0);
(B2B1[2] => V[31]) = (0:0:0, 0:0:0);
(B2B1[2] => V[32]) = (0:0:0, 0:0:0);
(B2B1[2] => V[4]) = (0:0:0, 0:0:0);
(B2B1[2] => V[5]) = (0:0:0, 0:0:0);
(B2B1[2] => V[6]) = (0:0:0, 0:0:0);
(B2B1[2] => V[7]) = (0:0:0, 0:0:0);
(B2B1[2] => V[8]) = (0:0:0, 0:0:0);
(B2B1[2] => V[9]) = (0:0:0, 0:0:0);
(B2B1[3] => U[10]) = (0:0:0, 0:0:0);
(B2B1[3] => U[11]) = (0:0:0, 0:0:0);
(B2B1[3] => U[12]) = (0:0:0, 0:0:0);
(B2B1[3] => U[13]) = (0:0:0, 0:0:0);
(B2B1[3] => U[14]) = (0:0:0, 0:0:0);
(B2B1[3] => U[15]) = (0:0:0, 0:0:0);
(B2B1[3] => U[16]) = (0:0:0, 0:0:0);
(B2B1[3] => U[17]) = (0:0:0, 0:0:0);
(B2B1[3] => U[18]) = (0:0:0, 0:0:0);
(B2B1[3] => U[19]) = (0:0:0, 0:0:0);
(B2B1[3] => U[20]) = (0:0:0, 0:0:0);
(B2B1[3] => U[21]) = (0:0:0, 0:0:0);
(B2B1[3] => U[22]) = (0:0:0, 0:0:0);
(B2B1[3] => U[23]) = (0:0:0, 0:0:0);
(B2B1[3] => U[24]) = (0:0:0, 0:0:0);
(B2B1[3] => U[25]) = (0:0:0, 0:0:0);
(B2B1[3] => U[26]) = (0:0:0, 0:0:0);
(B2B1[3] => U[27]) = (0:0:0, 0:0:0);
(B2B1[3] => U[28]) = (0:0:0, 0:0:0);
(B2B1[3] => U[29]) = (0:0:0, 0:0:0);
(B2B1[3] => U[2]) = (0:0:0, 0:0:0);
(B2B1[3] => U[30]) = (0:0:0, 0:0:0);
(B2B1[3] => U[31]) = (0:0:0, 0:0:0);
(B2B1[3] => U[32]) = (0:0:0, 0:0:0);
(B2B1[3] => U[33]) = (0:0:0, 0:0:0);
(B2B1[3] => U[34]) = (0:0:0, 0:0:0);
(B2B1[3] => U[35]) = (0:0:0, 0:0:0);
(B2B1[3] => U[3]) = (0:0:0, 0:0:0);
(B2B1[3] => U[4]) = (0:0:0, 0:0:0);
(B2B1[3] => U[5]) = (0:0:0, 0:0:0);
(B2B1[3] => U[6]) = (0:0:0, 0:0:0);
(B2B1[3] => U[7]) = (0:0:0, 0:0:0);
(B2B1[3] => U[8]) = (0:0:0, 0:0:0);
(B2B1[3] => U[9]) = (0:0:0, 0:0:0);
(B2B1[3] => V[10]) = (0:0:0, 0:0:0);
(B2B1[3] => V[11]) = (0:0:0, 0:0:0);
(B2B1[3] => V[12]) = (0:0:0, 0:0:0);
(B2B1[3] => V[13]) = (0:0:0, 0:0:0);
(B2B1[3] => V[14]) = (0:0:0, 0:0:0);
(B2B1[3] => V[15]) = (0:0:0, 0:0:0);
(B2B1[3] => V[16]) = (0:0:0, 0:0:0);
(B2B1[3] => V[17]) = (0:0:0, 0:0:0);
(B2B1[3] => V[18]) = (0:0:0, 0:0:0);
(B2B1[3] => V[19]) = (0:0:0, 0:0:0);
(B2B1[3] => V[20]) = (0:0:0, 0:0:0);
(B2B1[3] => V[21]) = (0:0:0, 0:0:0);
(B2B1[3] => V[22]) = (0:0:0, 0:0:0);
(B2B1[3] => V[23]) = (0:0:0, 0:0:0);
(B2B1[3] => V[24]) = (0:0:0, 0:0:0);
(B2B1[3] => V[25]) = (0:0:0, 0:0:0);
(B2B1[3] => V[26]) = (0:0:0, 0:0:0);
(B2B1[3] => V[27]) = (0:0:0, 0:0:0);
(B2B1[3] => V[28]) = (0:0:0, 0:0:0);
(B2B1[3] => V[29]) = (0:0:0, 0:0:0);
(B2B1[3] => V[30]) = (0:0:0, 0:0:0);
(B2B1[3] => V[31]) = (0:0:0, 0:0:0);
(B2B1[3] => V[32]) = (0:0:0, 0:0:0);
(B2B1[3] => V[33]) = (0:0:0, 0:0:0);
(B2B1[3] => V[34]) = (0:0:0, 0:0:0);
(B2B1[3] => V[4]) = (0:0:0, 0:0:0);
(B2B1[3] => V[5]) = (0:0:0, 0:0:0);
(B2B1[3] => V[6]) = (0:0:0, 0:0:0);
(B2B1[3] => V[7]) = (0:0:0, 0:0:0);
(B2B1[3] => V[8]) = (0:0:0, 0:0:0);
(B2B1[3] => V[9]) = (0:0:0, 0:0:0);
(B2B1[4] => U[10]) = (0:0:0, 0:0:0);
(B2B1[4] => U[11]) = (0:0:0, 0:0:0);
(B2B1[4] => U[12]) = (0:0:0, 0:0:0);
(B2B1[4] => U[13]) = (0:0:0, 0:0:0);
(B2B1[4] => U[14]) = (0:0:0, 0:0:0);
(B2B1[4] => U[15]) = (0:0:0, 0:0:0);
(B2B1[4] => U[16]) = (0:0:0, 0:0:0);
(B2B1[4] => U[17]) = (0:0:0, 0:0:0);
(B2B1[4] => U[18]) = (0:0:0, 0:0:0);
(B2B1[4] => U[19]) = (0:0:0, 0:0:0);
(B2B1[4] => U[20]) = (0:0:0, 0:0:0);
(B2B1[4] => U[21]) = (0:0:0, 0:0:0);
(B2B1[4] => U[22]) = (0:0:0, 0:0:0);
(B2B1[4] => U[23]) = (0:0:0, 0:0:0);
(B2B1[4] => U[24]) = (0:0:0, 0:0:0);
(B2B1[4] => U[25]) = (0:0:0, 0:0:0);
(B2B1[4] => U[26]) = (0:0:0, 0:0:0);
(B2B1[4] => U[27]) = (0:0:0, 0:0:0);
(B2B1[4] => U[28]) = (0:0:0, 0:0:0);
(B2B1[4] => U[29]) = (0:0:0, 0:0:0);
(B2B1[4] => U[30]) = (0:0:0, 0:0:0);
(B2B1[4] => U[31]) = (0:0:0, 0:0:0);
(B2B1[4] => U[32]) = (0:0:0, 0:0:0);
(B2B1[4] => U[33]) = (0:0:0, 0:0:0);
(B2B1[4] => U[34]) = (0:0:0, 0:0:0);
(B2B1[4] => U[35]) = (0:0:0, 0:0:0);
(B2B1[4] => U[5]) = (0:0:0, 0:0:0);
(B2B1[4] => U[6]) = (0:0:0, 0:0:0);
(B2B1[4] => U[7]) = (0:0:0, 0:0:0);
(B2B1[4] => U[8]) = (0:0:0, 0:0:0);
(B2B1[4] => U[9]) = (0:0:0, 0:0:0);
(B2B1[4] => V[10]) = (0:0:0, 0:0:0);
(B2B1[4] => V[11]) = (0:0:0, 0:0:0);
(B2B1[4] => V[12]) = (0:0:0, 0:0:0);
(B2B1[4] => V[13]) = (0:0:0, 0:0:0);
(B2B1[4] => V[14]) = (0:0:0, 0:0:0);
(B2B1[4] => V[15]) = (0:0:0, 0:0:0);
(B2B1[4] => V[16]) = (0:0:0, 0:0:0);
(B2B1[4] => V[17]) = (0:0:0, 0:0:0);
(B2B1[4] => V[18]) = (0:0:0, 0:0:0);
(B2B1[4] => V[19]) = (0:0:0, 0:0:0);
(B2B1[4] => V[20]) = (0:0:0, 0:0:0);
(B2B1[4] => V[21]) = (0:0:0, 0:0:0);
(B2B1[4] => V[22]) = (0:0:0, 0:0:0);
(B2B1[4] => V[23]) = (0:0:0, 0:0:0);
(B2B1[4] => V[24]) = (0:0:0, 0:0:0);
(B2B1[4] => V[25]) = (0:0:0, 0:0:0);
(B2B1[4] => V[26]) = (0:0:0, 0:0:0);
(B2B1[4] => V[27]) = (0:0:0, 0:0:0);
(B2B1[4] => V[28]) = (0:0:0, 0:0:0);
(B2B1[4] => V[29]) = (0:0:0, 0:0:0);
(B2B1[4] => V[30]) = (0:0:0, 0:0:0);
(B2B1[4] => V[31]) = (0:0:0, 0:0:0);
(B2B1[4] => V[32]) = (0:0:0, 0:0:0);
(B2B1[4] => V[33]) = (0:0:0, 0:0:0);
(B2B1[4] => V[34]) = (0:0:0, 0:0:0);
(B2B1[4] => V[4]) = (0:0:0, 0:0:0);
(B2B1[4] => V[5]) = (0:0:0, 0:0:0);
(B2B1[4] => V[6]) = (0:0:0, 0:0:0);
(B2B1[4] => V[7]) = (0:0:0, 0:0:0);
(B2B1[4] => V[8]) = (0:0:0, 0:0:0);
(B2B1[4] => V[9]) = (0:0:0, 0:0:0);
(B2B1[5] => U[10]) = (0:0:0, 0:0:0);
(B2B1[5] => U[11]) = (0:0:0, 0:0:0);
(B2B1[5] => U[12]) = (0:0:0, 0:0:0);
(B2B1[5] => U[13]) = (0:0:0, 0:0:0);
(B2B1[5] => U[14]) = (0:0:0, 0:0:0);
(B2B1[5] => U[15]) = (0:0:0, 0:0:0);
(B2B1[5] => U[16]) = (0:0:0, 0:0:0);
(B2B1[5] => U[17]) = (0:0:0, 0:0:0);
(B2B1[5] => U[18]) = (0:0:0, 0:0:0);
(B2B1[5] => U[19]) = (0:0:0, 0:0:0);
(B2B1[5] => U[20]) = (0:0:0, 0:0:0);
(B2B1[5] => U[21]) = (0:0:0, 0:0:0);
(B2B1[5] => U[22]) = (0:0:0, 0:0:0);
(B2B1[5] => U[23]) = (0:0:0, 0:0:0);
(B2B1[5] => U[24]) = (0:0:0, 0:0:0);
(B2B1[5] => U[25]) = (0:0:0, 0:0:0);
(B2B1[5] => U[26]) = (0:0:0, 0:0:0);
(B2B1[5] => U[27]) = (0:0:0, 0:0:0);
(B2B1[5] => U[28]) = (0:0:0, 0:0:0);
(B2B1[5] => U[29]) = (0:0:0, 0:0:0);
(B2B1[5] => U[30]) = (0:0:0, 0:0:0);
(B2B1[5] => U[31]) = (0:0:0, 0:0:0);
(B2B1[5] => U[32]) = (0:0:0, 0:0:0);
(B2B1[5] => U[33]) = (0:0:0, 0:0:0);
(B2B1[5] => U[34]) = (0:0:0, 0:0:0);
(B2B1[5] => U[35]) = (0:0:0, 0:0:0);
(B2B1[5] => U[36]) = (0:0:0, 0:0:0);
(B2B1[5] => U[5]) = (0:0:0, 0:0:0);
(B2B1[5] => U[6]) = (0:0:0, 0:0:0);
(B2B1[5] => U[7]) = (0:0:0, 0:0:0);
(B2B1[5] => U[8]) = (0:0:0, 0:0:0);
(B2B1[5] => U[9]) = (0:0:0, 0:0:0);
(B2B1[5] => V[10]) = (0:0:0, 0:0:0);
(B2B1[5] => V[11]) = (0:0:0, 0:0:0);
(B2B1[5] => V[12]) = (0:0:0, 0:0:0);
(B2B1[5] => V[13]) = (0:0:0, 0:0:0);
(B2B1[5] => V[14]) = (0:0:0, 0:0:0);
(B2B1[5] => V[15]) = (0:0:0, 0:0:0);
(B2B1[5] => V[16]) = (0:0:0, 0:0:0);
(B2B1[5] => V[17]) = (0:0:0, 0:0:0);
(B2B1[5] => V[18]) = (0:0:0, 0:0:0);
(B2B1[5] => V[19]) = (0:0:0, 0:0:0);
(B2B1[5] => V[20]) = (0:0:0, 0:0:0);
(B2B1[5] => V[21]) = (0:0:0, 0:0:0);
(B2B1[5] => V[22]) = (0:0:0, 0:0:0);
(B2B1[5] => V[23]) = (0:0:0, 0:0:0);
(B2B1[5] => V[24]) = (0:0:0, 0:0:0);
(B2B1[5] => V[25]) = (0:0:0, 0:0:0);
(B2B1[5] => V[26]) = (0:0:0, 0:0:0);
(B2B1[5] => V[27]) = (0:0:0, 0:0:0);
(B2B1[5] => V[28]) = (0:0:0, 0:0:0);
(B2B1[5] => V[29]) = (0:0:0, 0:0:0);
(B2B1[5] => V[30]) = (0:0:0, 0:0:0);
(B2B1[5] => V[31]) = (0:0:0, 0:0:0);
(B2B1[5] => V[32]) = (0:0:0, 0:0:0);
(B2B1[5] => V[33]) = (0:0:0, 0:0:0);
(B2B1[5] => V[34]) = (0:0:0, 0:0:0);
(B2B1[5] => V[35]) = (0:0:0, 0:0:0);
(B2B1[5] => V[4]) = (0:0:0, 0:0:0);
(B2B1[5] => V[5]) = (0:0:0, 0:0:0);
(B2B1[5] => V[6]) = (0:0:0, 0:0:0);
(B2B1[5] => V[7]) = (0:0:0, 0:0:0);
(B2B1[5] => V[8]) = (0:0:0, 0:0:0);
(B2B1[5] => V[9]) = (0:0:0, 0:0:0);
(B2B1[6] => U[10]) = (0:0:0, 0:0:0);
(B2B1[6] => U[11]) = (0:0:0, 0:0:0);
(B2B1[6] => U[12]) = (0:0:0, 0:0:0);
(B2B1[6] => U[13]) = (0:0:0, 0:0:0);
(B2B1[6] => U[14]) = (0:0:0, 0:0:0);
(B2B1[6] => U[15]) = (0:0:0, 0:0:0);
(B2B1[6] => U[16]) = (0:0:0, 0:0:0);
(B2B1[6] => U[17]) = (0:0:0, 0:0:0);
(B2B1[6] => U[18]) = (0:0:0, 0:0:0);
(B2B1[6] => U[19]) = (0:0:0, 0:0:0);
(B2B1[6] => U[20]) = (0:0:0, 0:0:0);
(B2B1[6] => U[21]) = (0:0:0, 0:0:0);
(B2B1[6] => U[22]) = (0:0:0, 0:0:0);
(B2B1[6] => U[23]) = (0:0:0, 0:0:0);
(B2B1[6] => U[24]) = (0:0:0, 0:0:0);
(B2B1[6] => U[25]) = (0:0:0, 0:0:0);
(B2B1[6] => U[26]) = (0:0:0, 0:0:0);
(B2B1[6] => U[27]) = (0:0:0, 0:0:0);
(B2B1[6] => U[28]) = (0:0:0, 0:0:0);
(B2B1[6] => U[29]) = (0:0:0, 0:0:0);
(B2B1[6] => U[30]) = (0:0:0, 0:0:0);
(B2B1[6] => U[31]) = (0:0:0, 0:0:0);
(B2B1[6] => U[32]) = (0:0:0, 0:0:0);
(B2B1[6] => U[33]) = (0:0:0, 0:0:0);
(B2B1[6] => U[34]) = (0:0:0, 0:0:0);
(B2B1[6] => U[35]) = (0:0:0, 0:0:0);
(B2B1[6] => U[36]) = (0:0:0, 0:0:0);
(B2B1[6] => U[7]) = (0:0:0, 0:0:0);
(B2B1[6] => U[8]) = (0:0:0, 0:0:0);
(B2B1[6] => U[9]) = (0:0:0, 0:0:0);
(B2B1[6] => V[10]) = (0:0:0, 0:0:0);
(B2B1[6] => V[11]) = (0:0:0, 0:0:0);
(B2B1[6] => V[12]) = (0:0:0, 0:0:0);
(B2B1[6] => V[13]) = (0:0:0, 0:0:0);
(B2B1[6] => V[14]) = (0:0:0, 0:0:0);
(B2B1[6] => V[15]) = (0:0:0, 0:0:0);
(B2B1[6] => V[16]) = (0:0:0, 0:0:0);
(B2B1[6] => V[17]) = (0:0:0, 0:0:0);
(B2B1[6] => V[18]) = (0:0:0, 0:0:0);
(B2B1[6] => V[19]) = (0:0:0, 0:0:0);
(B2B1[6] => V[20]) = (0:0:0, 0:0:0);
(B2B1[6] => V[21]) = (0:0:0, 0:0:0);
(B2B1[6] => V[22]) = (0:0:0, 0:0:0);
(B2B1[6] => V[23]) = (0:0:0, 0:0:0);
(B2B1[6] => V[24]) = (0:0:0, 0:0:0);
(B2B1[6] => V[25]) = (0:0:0, 0:0:0);
(B2B1[6] => V[26]) = (0:0:0, 0:0:0);
(B2B1[6] => V[27]) = (0:0:0, 0:0:0);
(B2B1[6] => V[28]) = (0:0:0, 0:0:0);
(B2B1[6] => V[29]) = (0:0:0, 0:0:0);
(B2B1[6] => V[30]) = (0:0:0, 0:0:0);
(B2B1[6] => V[31]) = (0:0:0, 0:0:0);
(B2B1[6] => V[32]) = (0:0:0, 0:0:0);
(B2B1[6] => V[33]) = (0:0:0, 0:0:0);
(B2B1[6] => V[34]) = (0:0:0, 0:0:0);
(B2B1[6] => V[35]) = (0:0:0, 0:0:0);
(B2B1[6] => V[6]) = (0:0:0, 0:0:0);
(B2B1[6] => V[7]) = (0:0:0, 0:0:0);
(B2B1[6] => V[8]) = (0:0:0, 0:0:0);
(B2B1[6] => V[9]) = (0:0:0, 0:0:0);
(B2B1[7] => U[10]) = (0:0:0, 0:0:0);
(B2B1[7] => U[11]) = (0:0:0, 0:0:0);
(B2B1[7] => U[12]) = (0:0:0, 0:0:0);
(B2B1[7] => U[13]) = (0:0:0, 0:0:0);
(B2B1[7] => U[14]) = (0:0:0, 0:0:0);
(B2B1[7] => U[15]) = (0:0:0, 0:0:0);
(B2B1[7] => U[16]) = (0:0:0, 0:0:0);
(B2B1[7] => U[17]) = (0:0:0, 0:0:0);
(B2B1[7] => U[18]) = (0:0:0, 0:0:0);
(B2B1[7] => U[19]) = (0:0:0, 0:0:0);
(B2B1[7] => U[20]) = (0:0:0, 0:0:0);
(B2B1[7] => U[21]) = (0:0:0, 0:0:0);
(B2B1[7] => U[22]) = (0:0:0, 0:0:0);
(B2B1[7] => U[23]) = (0:0:0, 0:0:0);
(B2B1[7] => U[24]) = (0:0:0, 0:0:0);
(B2B1[7] => U[25]) = (0:0:0, 0:0:0);
(B2B1[7] => U[26]) = (0:0:0, 0:0:0);
(B2B1[7] => U[27]) = (0:0:0, 0:0:0);
(B2B1[7] => U[28]) = (0:0:0, 0:0:0);
(B2B1[7] => U[29]) = (0:0:0, 0:0:0);
(B2B1[7] => U[30]) = (0:0:0, 0:0:0);
(B2B1[7] => U[31]) = (0:0:0, 0:0:0);
(B2B1[7] => U[32]) = (0:0:0, 0:0:0);
(B2B1[7] => U[33]) = (0:0:0, 0:0:0);
(B2B1[7] => U[34]) = (0:0:0, 0:0:0);
(B2B1[7] => U[35]) = (0:0:0, 0:0:0);
(B2B1[7] => U[36]) = (0:0:0, 0:0:0);
(B2B1[7] => U[37]) = (0:0:0, 0:0:0);
(B2B1[7] => U[38]) = (0:0:0, 0:0:0);
(B2B1[7] => U[7]) = (0:0:0, 0:0:0);
(B2B1[7] => U[8]) = (0:0:0, 0:0:0);
(B2B1[7] => U[9]) = (0:0:0, 0:0:0);
(B2B1[7] => V[10]) = (0:0:0, 0:0:0);
(B2B1[7] => V[11]) = (0:0:0, 0:0:0);
(B2B1[7] => V[12]) = (0:0:0, 0:0:0);
(B2B1[7] => V[13]) = (0:0:0, 0:0:0);
(B2B1[7] => V[14]) = (0:0:0, 0:0:0);
(B2B1[7] => V[15]) = (0:0:0, 0:0:0);
(B2B1[7] => V[16]) = (0:0:0, 0:0:0);
(B2B1[7] => V[17]) = (0:0:0, 0:0:0);
(B2B1[7] => V[18]) = (0:0:0, 0:0:0);
(B2B1[7] => V[19]) = (0:0:0, 0:0:0);
(B2B1[7] => V[20]) = (0:0:0, 0:0:0);
(B2B1[7] => V[21]) = (0:0:0, 0:0:0);
(B2B1[7] => V[22]) = (0:0:0, 0:0:0);
(B2B1[7] => V[23]) = (0:0:0, 0:0:0);
(B2B1[7] => V[24]) = (0:0:0, 0:0:0);
(B2B1[7] => V[25]) = (0:0:0, 0:0:0);
(B2B1[7] => V[26]) = (0:0:0, 0:0:0);
(B2B1[7] => V[27]) = (0:0:0, 0:0:0);
(B2B1[7] => V[28]) = (0:0:0, 0:0:0);
(B2B1[7] => V[29]) = (0:0:0, 0:0:0);
(B2B1[7] => V[30]) = (0:0:0, 0:0:0);
(B2B1[7] => V[31]) = (0:0:0, 0:0:0);
(B2B1[7] => V[32]) = (0:0:0, 0:0:0);
(B2B1[7] => V[33]) = (0:0:0, 0:0:0);
(B2B1[7] => V[34]) = (0:0:0, 0:0:0);
(B2B1[7] => V[35]) = (0:0:0, 0:0:0);
(B2B1[7] => V[36]) = (0:0:0, 0:0:0);
(B2B1[7] => V[37]) = (0:0:0, 0:0:0);
(B2B1[7] => V[6]) = (0:0:0, 0:0:0);
(B2B1[7] => V[7]) = (0:0:0, 0:0:0);
(B2B1[7] => V[8]) = (0:0:0, 0:0:0);
(B2B1[7] => V[9]) = (0:0:0, 0:0:0);
(B2B1[8] => U[10]) = (0:0:0, 0:0:0);
(B2B1[8] => U[11]) = (0:0:0, 0:0:0);
(B2B1[8] => U[12]) = (0:0:0, 0:0:0);
(B2B1[8] => U[13]) = (0:0:0, 0:0:0);
(B2B1[8] => U[14]) = (0:0:0, 0:0:0);
(B2B1[8] => U[15]) = (0:0:0, 0:0:0);
(B2B1[8] => U[16]) = (0:0:0, 0:0:0);
(B2B1[8] => U[17]) = (0:0:0, 0:0:0);
(B2B1[8] => U[18]) = (0:0:0, 0:0:0);
(B2B1[8] => U[19]) = (0:0:0, 0:0:0);
(B2B1[8] => U[20]) = (0:0:0, 0:0:0);
(B2B1[8] => U[21]) = (0:0:0, 0:0:0);
(B2B1[8] => U[22]) = (0:0:0, 0:0:0);
(B2B1[8] => U[23]) = (0:0:0, 0:0:0);
(B2B1[8] => U[24]) = (0:0:0, 0:0:0);
(B2B1[8] => U[25]) = (0:0:0, 0:0:0);
(B2B1[8] => U[26]) = (0:0:0, 0:0:0);
(B2B1[8] => U[27]) = (0:0:0, 0:0:0);
(B2B1[8] => U[28]) = (0:0:0, 0:0:0);
(B2B1[8] => U[29]) = (0:0:0, 0:0:0);
(B2B1[8] => U[30]) = (0:0:0, 0:0:0);
(B2B1[8] => U[31]) = (0:0:0, 0:0:0);
(B2B1[8] => U[32]) = (0:0:0, 0:0:0);
(B2B1[8] => U[33]) = (0:0:0, 0:0:0);
(B2B1[8] => U[34]) = (0:0:0, 0:0:0);
(B2B1[8] => U[35]) = (0:0:0, 0:0:0);
(B2B1[8] => U[36]) = (0:0:0, 0:0:0);
(B2B1[8] => U[37]) = (0:0:0, 0:0:0);
(B2B1[8] => U[38]) = (0:0:0, 0:0:0);
(B2B1[8] => U[9]) = (0:0:0, 0:0:0);
(B2B1[8] => V[10]) = (0:0:0, 0:0:0);
(B2B1[8] => V[11]) = (0:0:0, 0:0:0);
(B2B1[8] => V[12]) = (0:0:0, 0:0:0);
(B2B1[8] => V[13]) = (0:0:0, 0:0:0);
(B2B1[8] => V[14]) = (0:0:0, 0:0:0);
(B2B1[8] => V[15]) = (0:0:0, 0:0:0);
(B2B1[8] => V[16]) = (0:0:0, 0:0:0);
(B2B1[8] => V[17]) = (0:0:0, 0:0:0);
(B2B1[8] => V[18]) = (0:0:0, 0:0:0);
(B2B1[8] => V[19]) = (0:0:0, 0:0:0);
(B2B1[8] => V[20]) = (0:0:0, 0:0:0);
(B2B1[8] => V[21]) = (0:0:0, 0:0:0);
(B2B1[8] => V[22]) = (0:0:0, 0:0:0);
(B2B1[8] => V[23]) = (0:0:0, 0:0:0);
(B2B1[8] => V[24]) = (0:0:0, 0:0:0);
(B2B1[8] => V[25]) = (0:0:0, 0:0:0);
(B2B1[8] => V[26]) = (0:0:0, 0:0:0);
(B2B1[8] => V[27]) = (0:0:0, 0:0:0);
(B2B1[8] => V[28]) = (0:0:0, 0:0:0);
(B2B1[8] => V[29]) = (0:0:0, 0:0:0);
(B2B1[8] => V[30]) = (0:0:0, 0:0:0);
(B2B1[8] => V[31]) = (0:0:0, 0:0:0);
(B2B1[8] => V[32]) = (0:0:0, 0:0:0);
(B2B1[8] => V[33]) = (0:0:0, 0:0:0);
(B2B1[8] => V[34]) = (0:0:0, 0:0:0);
(B2B1[8] => V[35]) = (0:0:0, 0:0:0);
(B2B1[8] => V[36]) = (0:0:0, 0:0:0);
(B2B1[8] => V[37]) = (0:0:0, 0:0:0);
(B2B1[8] => V[8]) = (0:0:0, 0:0:0);
(B2B1[8] => V[9]) = (0:0:0, 0:0:0);
(B2B1[9] => U[10]) = (0:0:0, 0:0:0);
(B2B1[9] => U[11]) = (0:0:0, 0:0:0);
(B2B1[9] => U[12]) = (0:0:0, 0:0:0);
(B2B1[9] => U[13]) = (0:0:0, 0:0:0);
(B2B1[9] => U[14]) = (0:0:0, 0:0:0);
(B2B1[9] => U[15]) = (0:0:0, 0:0:0);
(B2B1[9] => U[16]) = (0:0:0, 0:0:0);
(B2B1[9] => U[17]) = (0:0:0, 0:0:0);
(B2B1[9] => U[18]) = (0:0:0, 0:0:0);
(B2B1[9] => U[19]) = (0:0:0, 0:0:0);
(B2B1[9] => U[20]) = (0:0:0, 0:0:0);
(B2B1[9] => U[21]) = (0:0:0, 0:0:0);
(B2B1[9] => U[22]) = (0:0:0, 0:0:0);
(B2B1[9] => U[23]) = (0:0:0, 0:0:0);
(B2B1[9] => U[24]) = (0:0:0, 0:0:0);
(B2B1[9] => U[25]) = (0:0:0, 0:0:0);
(B2B1[9] => U[26]) = (0:0:0, 0:0:0);
(B2B1[9] => U[27]) = (0:0:0, 0:0:0);
(B2B1[9] => U[28]) = (0:0:0, 0:0:0);
(B2B1[9] => U[29]) = (0:0:0, 0:0:0);
(B2B1[9] => U[30]) = (0:0:0, 0:0:0);
(B2B1[9] => U[31]) = (0:0:0, 0:0:0);
(B2B1[9] => U[32]) = (0:0:0, 0:0:0);
(B2B1[9] => U[33]) = (0:0:0, 0:0:0);
(B2B1[9] => U[34]) = (0:0:0, 0:0:0);
(B2B1[9] => U[35]) = (0:0:0, 0:0:0);
(B2B1[9] => U[36]) = (0:0:0, 0:0:0);
(B2B1[9] => U[37]) = (0:0:0, 0:0:0);
(B2B1[9] => U[38]) = (0:0:0, 0:0:0);
(B2B1[9] => U[39]) = (0:0:0, 0:0:0);
(B2B1[9] => U[40]) = (0:0:0, 0:0:0);
(B2B1[9] => U[9]) = (0:0:0, 0:0:0);
(B2B1[9] => V[10]) = (0:0:0, 0:0:0);
(B2B1[9] => V[11]) = (0:0:0, 0:0:0);
(B2B1[9] => V[12]) = (0:0:0, 0:0:0);
(B2B1[9] => V[13]) = (0:0:0, 0:0:0);
(B2B1[9] => V[14]) = (0:0:0, 0:0:0);
(B2B1[9] => V[15]) = (0:0:0, 0:0:0);
(B2B1[9] => V[16]) = (0:0:0, 0:0:0);
(B2B1[9] => V[17]) = (0:0:0, 0:0:0);
(B2B1[9] => V[18]) = (0:0:0, 0:0:0);
(B2B1[9] => V[19]) = (0:0:0, 0:0:0);
(B2B1[9] => V[20]) = (0:0:0, 0:0:0);
(B2B1[9] => V[21]) = (0:0:0, 0:0:0);
(B2B1[9] => V[22]) = (0:0:0, 0:0:0);
(B2B1[9] => V[23]) = (0:0:0, 0:0:0);
(B2B1[9] => V[24]) = (0:0:0, 0:0:0);
(B2B1[9] => V[25]) = (0:0:0, 0:0:0);
(B2B1[9] => V[26]) = (0:0:0, 0:0:0);
(B2B1[9] => V[27]) = (0:0:0, 0:0:0);
(B2B1[9] => V[28]) = (0:0:0, 0:0:0);
(B2B1[9] => V[29]) = (0:0:0, 0:0:0);
(B2B1[9] => V[30]) = (0:0:0, 0:0:0);
(B2B1[9] => V[31]) = (0:0:0, 0:0:0);
(B2B1[9] => V[32]) = (0:0:0, 0:0:0);
(B2B1[9] => V[33]) = (0:0:0, 0:0:0);
(B2B1[9] => V[34]) = (0:0:0, 0:0:0);
(B2B1[9] => V[35]) = (0:0:0, 0:0:0);
(B2B1[9] => V[36]) = (0:0:0, 0:0:0);
(B2B1[9] => V[37]) = (0:0:0, 0:0:0);
(B2B1[9] => V[38]) = (0:0:0, 0:0:0);
(B2B1[9] => V[39]) = (0:0:0, 0:0:0);
(B2B1[9] => V[8]) = (0:0:0, 0:0:0);
(B2B1[9] => V[9]) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef int unit_type_t;
function [3:0] unit_plusone(input [3:0] i);
unit_plusone = i+1;
endfunction
package p;
typedef int package_type_t;
integer pi = 123;
function [3:0] plusone(input [3:0] i);
plusone = i+1;
endfunction
endpackage
package p2;
typedef int package2_type_t;
function [3:0] plustwo(input [3:0] i);
plustwo = i+2;
endfunction
endpackage
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
unit_type_t vu;
$unit::unit_type_t vdu;
p::package_type_t vp;
t2 t2 ();
initial begin
if (unit_plusone(1) !== 2) $stop;
if ($unit::unit_plusone(1) !== 2) $stop;
if (p::plusone(1) !== 2) $stop;
p::pi = 124;
if (p::pi !== 124) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
always @ (posedge clk) begin
p::pi += 1;
if (p::pi < 124) $stop;
end
endmodule
module t2;
import p::*;
import p2::plustwo;
import p2::package2_type_t;
package_type_t vp;
package2_type_t vp2;
initial begin
if (plusone(1) !== 2) $stop;
if (plustwo(1) !== 3) $stop;
if (p::pi !== 123 && p::pi !== 124) $stop; // may race with other initial, so either value
end
endmodule
|
// megafunction wizard: %ROM: 1-PORT%VBB%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: sword.v
// Megafunction Name(s):
// altsyncram
//
// Simulation Library Files(s):
// altera_mf
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 13.1.1 Build 166 11/26/2013 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
module sword (
address,
clock,
q);
input [14:0] address;
input clock;
output [15:0] q;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0"
// Retrieval info: PRIVATE: AclrAddr NUMERIC "0"
// Retrieval info: PRIVATE: AclrByte NUMERIC "0"
// Retrieval info: PRIVATE: AclrOutput NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_ENABLE NUMERIC "0"
// Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8"
// Retrieval info: PRIVATE: BlankMemory NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0"
// Retrieval info: PRIVATE: Clken NUMERIC "0"
// Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
// Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
// Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
// Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
// Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0"
// Retrieval info: PRIVATE: MIFfilename STRING "../audio_mifs/sword.mif"
// Retrieval info: PRIVATE: NUMWORDS_A NUMERIC "32768"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: RegAddr NUMERIC "1"
// Retrieval info: PRIVATE: RegOutput NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: SingleClock NUMERIC "1"
// Retrieval info: PRIVATE: UseDQRAM NUMERIC "0"
// Retrieval info: PRIVATE: WidthAddr NUMERIC "15"
// Retrieval info: PRIVATE: WidthData NUMERIC "16"
// Retrieval info: PRIVATE: rden NUMERIC "0"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: ADDRESS_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
// Retrieval info: CONSTANT: INIT_FILE STRING "../audio_mifs/sword.mif"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone V"
// Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
// Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "32768"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "ROM"
// Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
// Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
// Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "15"
// Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
// Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "1"
// Retrieval info: USED_PORT: address 0 0 15 0 INPUT NODEFVAL "address[14..0]"
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC "clock"
// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL "q[15..0]"
// Retrieval info: CONNECT: @address_a 0 0 15 0 address 0 0 15 0
// Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
// Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
// Retrieval info: GEN_FILE: TYPE_NORMAL sword.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL sword.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sword.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sword.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sword_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL sword_bb.v TRUE
// Retrieval info: LIB_FILE: altera_mf
|
//-----------------------------------------------------
// This is FSM demo program using always block
// Design Name : fsm_using_always
// File Name : fsm_using_always.v
//-----------------------------------------------------
module fsm_using_always (
clock , // clock
reset , // Active high, syn reset
req_0 , // Request 0
req_1 , // Request 1
gnt_0 , // Grant 0
gnt_1
);
//-------------Input Ports-----------------------------
input clock,reset,req_0,req_1;
//-------------Output Ports----------------------------
output gnt_0,gnt_1;
//-------------Input ports Data Type-------------------
wire clock,reset,req_0,req_1;
//-------------Output Ports Data Type------------------
reg gnt_0,gnt_1;
//-------------Internal Constants--------------------------
parameter SIZE = 3 ;
parameter IDLE = 3'b001,GNT0 = 3'b010,GNT1 = 3'b100 ;
//-------------Internal Variables---------------------------
reg [SIZE-1:0] state ;// Seq part of the FSM
reg [SIZE-1:0] next_state ;// combo part of FSM
//----------Code startes Here------------------------
always @ (state or req_0 or req_1)
begin : FSM_COMBO
next_state = 3'b000;
case(state)
IDLE : if (req_0 == 1'b1) begin
next_state = GNT0;
end else if (req_1 == 1'b1) begin
next_state= GNT1;
end else begin
next_state = IDLE;
end
GNT0 : if (req_0 == 1'b1) begin
next_state = GNT0;
end else begin
next_state = IDLE;
end
GNT1 : if (req_1 == 1'b1) begin
next_state = GNT1;
end else begin
next_state = IDLE;
end
default : next_state = IDLE;
endcase
end
//----------Seq Logic-----------------------------
always @ (posedge clock)
begin : FSM_SEQ
if (reset == 1'b1) begin
state <= #1 IDLE;
end else begin
state <= #1 next_state;
end
end
//----------Output Logic-----------------------------
always @ (posedge clock)
begin : OUTPUT_LOGIC
if (reset == 1'b1) begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
else begin
case(state)
IDLE : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
GNT0 : begin
gnt_0 <= #1 1'b1;
gnt_1 <= #1 1'b0;
end
GNT1 : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b1;
end
default : begin
gnt_0 <= #1 1'b0;
gnt_1 <= #1 1'b0;
end
endcase
end
end // End Of Block OUTPUT_LOGIC
endmodule // End of Module arbiter
|
module dualport_RAM(clk, d_in_1, d_out_1, addr_1, rd_1, wr_1, d_in_2, d_out_2, addr_2, rd_2, wr_2);
input clk;
input [15:0]d_in_1;
output reg [15:0]d_out_1=0;
input [7:0]addr_1; // 8 LSB from address
input rd_1;
input wr_1;
input [15:0]d_in_2;
output reg [15:0]d_out_2=0;
input [7:0]addr_2; // 8 LSB from address
input rd_2;
input wr_2;
// Declare the RAM variable
reg [7:0] ram [0:31]; // 32-bit x 8-bit RAM
always @(negedge clk)
begin
//------------------ port 1 : core J1---------------------
if (rd_1) begin
d_out_1[7:0] <= ram[addr_1];
d_out_1[15:8] <= ram[addr_1+1];
end
else if(wr_1) begin
ram[addr_1] <= d_in_1[7:0];
ram[addr_1+1] <= d_in_1[15:8];
end
//------------------ port 1 : core J1---------------------
//------------------ port 2 : core peripheric-------------
else if (rd_2) begin
d_out_2[7:0] <= ram[addr_2];
d_out_2[15:8] <= ram[addr_2+1];
end
else if(wr_2) begin
ram[addr_2] <= d_in_2[7:0];
ram[addr_2+1] <= d_in_2[15:8];
end
// else
// ram[addr_2] <= ram[addr_2];
//------------------ port 2 : core peripheric-------------
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V
`define SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V
/**
* lsbufiso1p: ????.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_lp__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_lp__lsbufiso1p (
X ,
A ,
SLEEP
);
// Module ports
output X ;
input A ;
input SLEEP;
// Module supplies
supply1 DESTPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 DESTVPB;
supply1 VPB ;
supply0 VNB ;
// Local signals
wire or0_out_X;
// Name Output Other arguments
or or0 (or0_out_X, A, SLEEP );
sky130_fd_sc_lp__udp_pwrgood_pp$PG pwrgood_pp0 (X , or0_out_X, DESTPWR, VGND);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__LSBUFISO1P_BEHAVIORAL_V |
// cpu_cache.v
// 2013, [email protected]
// this is a simple 2-way set-asociative cache
// write-through, look-through
// 2kB data cache size, 1kB per way
// with write buffer
// uses five M4K blocks in Cyclone II
// ! requires Altera Quartus prepared memories because of the byte-selects !
module cpu_cache (
// system
input wire clk, // clock (CPU)
input wire rst, // reset (CPU)
input wire cache_ena, // cache control
// cpu
input wire [ 6-1:0] cpu_state, // CPU state
input wire [ 25-1:1] cpu_adr, // CPU address
input wire [ 2-1:0] cpu_bs, // CPU byte selects
input wire [ 16-1:0] cpu_dat_w, // CPU write data
output reg [ 16-1:0] cpu_dat_r, // CPU read data
output reg cpu_ack, // CPU cpuena
// sdram controller
input wire [ 4-1:0] sdr_state, // SDRAM state
input wire [ 25-1:0] sdr_adr, // SDRAM address
input wire sdr_cpucycle, // SDRAM CPU got the cycle
input wire sdr_cas, // SDRAM cas
input wire [ 16-1:0] sdr_dat_r, // SDRAM read data
output wire [ 16-1:0] sdr_dat_w, // SDRAM write data
output wire sdr_cpu_act // SDRAM CPU requires access
);
//// params ////
// cache states
localparam [2:0]
ST_INIT = 3'd0,
ST_IDLE = 3'd1,
ST_PREP = 3'd2,
ST_CPU_WRITE = 3'd3,
ST_CPU_READ = 3'd4,
ST_FILL = 3'd5;
// SDRAM states
localparam [3:0]
ph0 = 4'd0,
ph1 = 4'd1,
ph2 = 4'd2,
ph3 = 4'd3,
ph4 = 4'd4,
ph5 = 4'd5,
ph6 = 4'd6,
ph7 = 4'd7,
ph8 = 4'd8,
ph9 = 4'd9,
ph10 = 4'd10,
ph11 = 4'd11,
ph12 = 4'd12,
ph13 = 4'd13,
ph14 = 4'd14,
ph15 = 4'd15;
//// internal signals ////
reg [ 6-1:0] cpu_state_r = 0;
reg [25-1:1] cpu_adr_r = 0;
reg [ 2-1:0] cpu_bs_r = 0;
reg [16-1:0] cpu_dat_w_r = 0;
reg [16-1:0] sdr_dat_r_r = 0;
wire cpu_cs;
wire cpu_rw;
wire cpu_wr;
wire cpu_rd;
wire [ 2-1:0] adr_blk;
wire [ 7-1:0] adr_idx;
wire [15-1:0] adr_tag;
reg [ 3-1:0] state = 0;
reg [ 9-1:0] st_adr = 0;
reg st_lru = 0;
reg st_tag_we = 0;
reg [32-1:0] st_tag_dat_w = 0;
reg st_mem_we_0 = 0;
reg st_mem_we_1 = 0;
reg [ 2-1:0] st_mem_bs = 0;
reg [16-1:0] st_mem_dat_w = 0;
wire [ 7-1:0] tag_wadr;
wire [ 7-1:0] tag_radr;
wire tag_we;
wire [32-1:0] tag_dat_w;
wire [32-1:0] tag_dat_r;
reg [32-1:0] tag_dat_r_reg;
wire tag_lru;
wire tag_w0_match;
wire tag_w1_match;
wire tag_hit;
wire [ 9-1:0] mem_wadr;
wire [ 9-1:0] mem_radr;
wire mem_we_0;
wire mem_we_1;
wire [ 2-1:0] mem_bs;
wire [16-1:0] mem_dat_w;
wire [16-1:0] mem_dat_r_0;
wire [16-1:0] mem_dat_r_1;
reg [16-1:0] mem_dat_r_0_reg;
reg [16-1:0] mem_dat_r_1_reg;
//// CPU logic ////
// register CPU bus
always @ (posedge clk) begin
if (rst) begin
cpu_state_r <= #1 6'b111111;
end else if (state == ST_IDLE) begin
cpu_state_r <= #1 cpu_state;
end
end
always @ (posedge clk) begin
if (state == ST_IDLE) begin
cpu_adr_r <= #1 cpu_adr;
cpu_bs_r <= #1 cpu_bs;
cpu_dat_w_r <= #1 cpu_dat_w;
end
end
always @ (posedge clk) begin
sdr_dat_r_r <= #1 sdr_dat_r;
end
// decode cpu control signals
// 00-> fetch code 10->read data 11->write data 01->no memaccess
//assign cpu_cs = !cpu_state[2] && !cpu_state[5] && (cpu_state[1:0] != 2'b01);
assign cpu_cs = !cpu_state[2];
assign cpu_rw = !cpu_state[1] | !cpu_state[0];
assign cpu_wr = &cpu_state[1:0];
//assign cpu_rd = !cpu_state[0];
assign cpu_rd = cpu_state[1:0] == 2'b00; // instruction
//assign cpu_rd = cpu_state[1:0] == 2'b10; // data
//assign cpu_rd = 0;
// slice up cpu address
assign adr_blk = cpu_adr[2:1];
assign adr_idx = cpu_adr[9:3];
assign adr_tag = cpu_adr[24:10];
// CPU read register
always @ (posedge clk) begin
if (cache_ena && cpu_cs && tag_w0_match && (state == ST_CPU_READ))
cpu_dat_r <= #1 mem_dat_r_0;
else if (cache_ena && cpu_cs && tag_w1_match && (state == ST_CPU_READ))
cpu_dat_r <= #1 mem_dat_r_1;
else if (sdr_cpucycle && (sdr_state == ph9))
cpu_dat_r <= #1 sdr_dat_r;
end
// CPU write buffer
reg cpu_wb_act = 0;
reg [16-1:0] cpu_wb = 0;
always @ (posedge clk) begin
if (rst)
cpu_wb_act <= #1 1'b0;
else if (sdr_cpucycle && (sdr_state == ph11) && !sdr_cas && (sdr_adr[24:1] == cpu_adr))
cpu_wb_act <= #1 1'b0;
else if (cpu_cs && cpu_wr)
cpu_wb_act <= #1 1'b1;
end
always @ (posedge clk) begin
if (cpu_cs && cpu_wr && !cpu_wb_act)
cpu_wb <= #1 cpu_dat_w;
end
// CPU acknowledge
reg ack;
always @ (posedge clk) begin
if (rst)
ack <= #1 1'b0;
else begin
if (cpu_state[5])
ack <= #1 1'b0;
else if (cache_ena && cpu_cs && (state == ST_CPU_READ) && (tag_w0_match || tag_w1_match))
ack <= #1 1'b1;
end
end
always @ (posedge clk) begin
if (rst)
cpu_ack <= #1 1'b0;
else begin
if (cpu_state[5])
cpu_ack <= #1 1'b0;
else if (cache_ena && cpu_cs && tag_w0_match && (state == ST_CPU_READ))
cpu_ack <= #1 1'b1;
else if (cache_ena && cpu_cs && tag_w1_match && (state == ST_CPU_READ))
cpu_ack <= #1 1'b1;
// else if (cpu_cs && cpu_wr && !cpu_wb_act)
// cpu_ack <= #1 1'b1;
// else if (ack)
// cpu_ack <= #1 1'b1;
else if (sdr_cpucycle && (sdr_state == ph11) && !sdr_cas && (sdr_adr[24:1] == cpu_adr))
cpu_ack <= #1 1'b1;
end
end
//// cache control state machine ////
always @ (posedge clk) begin
if (rst) begin
state <= #1 ST_INIT;
st_adr <= #1 9'd0;
st_lru <= #1 1'b0;
st_tag_we <= #1 1'b1;
st_tag_dat_w <= #1 32'd0;
st_mem_we_0 <= #1 1'b1;
st_mem_we_1 <= #1 1'b1;
st_mem_bs <= #1 2'b11;
st_mem_dat_w <= #1 16'd0;
end else begin
state <= #1 ST_IDLE;
st_adr <= #1 {adr_idx, adr_blk};
st_tag_we <= #1 1'b0;
st_tag_dat_w <= #1 32'd0;
st_mem_we_0 <= #1 1'b0;
st_mem_we_1 <= #1 1'b0;
st_mem_bs <= #1 2'b11;
st_mem_dat_w <= #1 16'd0;
case (state)
ST_INIT : begin
// clear cache, should be done on every CPU reset
st_adr <= #1 st_adr + 9'd1;
st_tag_we <= #1 1'b1;
//st_mem_we_0 <= #1 1'b1;
//st_mem_we_1 <= #1 1'b1;
if (&st_adr) state <= #1 ST_IDLE;
else state <= #1 ST_INIT;
end
ST_IDLE : begin
if (cpu_cs && !cpu_ack)
state <= #1 ST_PREP;
else
state <= #1 ST_IDLE;
end
ST_PREP : begin
if (cpu_cs) begin
// state <= #1 cpu_rw ? ST_CPU_READ : ST_CPU_WRITE;
if (cpu_wr) state <= #1 ST_CPU_WRITE;
else if (cpu_rd) state <= #1 ST_CPU_READ;
end
end
ST_CPU_WRITE : begin
// on hit, update cache, on miss, no update neccessary
st_mem_bs <= #1 ~cpu_bs;
st_mem_dat_w <= #1 cpu_dat_w;
st_mem_we_0 <= #1 tag_w0_match;
st_mem_we_1 <= #1 tag_w1_match;
state <= #1 cpu_ack ? ST_IDLE : ST_CPU_WRITE;
//if (cpu_cs) begin
// if (tag_w0_match || tag_w1_match) begin
// st_tag_we <= #1 1'b1;
// st_tag_dat_w <= #1 32'd0;
// end
// state <= #1 cpu_ack ? ST_IDLE : ST_CPU_WRITE;
//end
end
ST_CPU_READ : begin
//if (cpu_cs) begin
// on hit, update LRU flag in tag memory
if (tag_w0_match) begin
st_tag_we <= #1 1'b1;
st_tag_dat_w <= #1 {1'b0, tag_dat_r[30:0]};
state <= #1 cpu_ack ? ST_IDLE : ST_CPU_READ;
end else if (tag_w1_match) begin
st_tag_we <= #1 1'b1;
st_tag_dat_w <= #1 {1'b1, tag_dat_r[30:0]};
state <= #1 cpu_ack ? ST_IDLE : ST_CPU_READ;
end else begin
// on miss, fetch data from SDRAM & update tag
st_lru <= #1 tag_lru;
state <= #1 ST_FILL;
end
//end
end
ST_FILL : begin
if (sdr_cpucycle) begin
st_mem_bs <= #1 2'b11;
st_mem_dat_w <= #1 sdr_dat_r;
case (sdr_state)
ph9,
ph10,
ph11,
ph12 : begin
st_mem_we_0 <= #1 st_lru;
st_mem_we_1 <= #1 !st_lru;
end
endcase
case (sdr_state)
ph10,
ph11,
ph12 : begin
st_adr <= #1 {st_adr[8:2], {st_adr[1:0] + 2'b01}};
end
endcase
if (sdr_state == ph12) begin
st_tag_we <= #1 1'b1;
st_tag_dat_w <= #1 {!st_lru, st_lru ? {tag_dat_r[30:16], 1'b0, adr_tag} : {adr_tag, tag_dat_r[15:0]}};
end
end
state <= #1 cpu_ack ? ST_IDLE : ST_FILL;
end
endcase
end
end
//// tag RAM ////
assign tag_radr = adr_idx;
assign tag_wadr = st_adr[8:2];
assign tag_dat_w = st_tag_dat_w;
assign tag_we = st_tag_we;
assign tag_w0_match = (adr_tag == tag_dat_r[14: 0]);
assign tag_w1_match = (adr_tag == tag_dat_r[30:16]);
assign tag_hit = tag_w0_match || tag_w1_match;
assign tag_lru = tag_dat_r[31];
`ifdef SOC_SIM
tpram_inf_128x32
`else
tpram_128x32
`endif
tag_ram (
.clock (clk ),
.wraddress (tag_wadr ),
.wren (tag_we ),
.data (tag_dat_w ),
.rdaddress (tag_radr ),
.q (tag_dat_r )
);
always @ (posedge clk) tag_dat_r_reg <= #1 tag_dat_r;
//// data RAM ////
assign mem_radr = {adr_idx, adr_blk};
assign mem_wadr = st_adr;
assign mem_dat_w = st_mem_dat_w;
assign mem_we_0 = st_mem_we_0;
assign mem_we_1 = st_mem_we_1;
assign mem_bs = st_mem_bs;
`ifdef SOC_SIM
tpram_inf_be_512x16
`else
tpram_be_512x16
`endif
mem_ram_0 (
.clock (clk ),
.wraddress (mem_wadr ),
.wren (mem_we_0 ),
.byteena_a (mem_bs ),
.data (mem_dat_w ),
.rdaddress (mem_radr ),
.q (mem_dat_r_0)
);
always @ (posedge clk) mem_dat_r_0_reg <= #1 mem_dat_r_0;
`ifdef SOC_SIM
tpram_inf_be_512x16
`else
tpram_be_512x16
`endif
mem_ram_1 (
.clock (clk ),
.wraddress (mem_wadr ),
.wren (mem_we_1 ),
.byteena_a (mem_bs ),
.data (mem_dat_w ),
.rdaddress (mem_radr ),
.q (mem_dat_r_1)
);
always @ (posedge clk) mem_dat_r_1_reg <= #1 mem_dat_r_1;
endmodule
|
`default_nettype none
`timescale 1ns / 1ps
`include "../src/message_formatter.v"
// ============================================================================
module tb;
// ============================================================================
reg CLK;
initial CLK <= 1'b0;
always #0.5 CLK <= !CLK;
reg [3:0] rst_sr;
initial rst_sr <= 4'hF;
always @(posedge CLK) rst_sr <= rst_sr >> 1;
wire RST;
assign RST = rst_sr[0];
// ============================================================================
initial begin
$dumpfile("waveforms.vcd");
$dumpvars;
end
integer cycle_cnt;
initial cycle_cnt <= 0;
always @(posedge CLK)
if (!RST) cycle_cnt <= cycle_cnt + 1;
always @(posedge CLK)
if (!RST && cycle_cnt >= 150)
$finish;
// ============================================================================
wire i_stb = (cycle_cnt == 10);
wire [32*2-1:0] i_dat = 64'h01234567_ABCD4321;
wire o_stb;
wire [7:0] o_dat;
message_formatter #
(
.WIDTH (32),
.COUNT (2),
.TX_INTERVAL (4)
)
dut
(
.CLK (CLK),
.RST (RST),
.I_STB (i_stb),
.I_DAT (i_dat),
.O_STB (o_stb),
.O_DAT (o_dat)
);
always @(posedge CLK)
if (o_stb)
$display("%c", o_dat);
endmodule
|
// (C) 2001-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1ps/1ps
module altera_pll_reconfig_top
#(
parameter reconf_width = 64,
parameter device_family = "Stratix V",
parameter RECONFIG_ADDR_WIDTH = 6,
parameter RECONFIG_DATA_WIDTH = 32,
parameter ROM_ADDR_WIDTH = 9,
parameter ROM_DATA_WIDTH = 32,
parameter ROM_NUM_WORDS = 512,
parameter ENABLE_MIF = 0,
parameter MIF_FILE_NAME = ""
) (
//input
input wire mgmt_clk,
input wire mgmt_reset,
//conduits
output wire [reconf_width-1:0] reconfig_to_pll,
input wire [reconf_width-1:0] reconfig_from_pll,
// user data (avalon-MM slave interface)
output wire [31:0] mgmt_readdata,
output wire mgmt_waitrequest,
input wire [5:0] mgmt_address,
input wire mgmt_read,
input wire mgmt_write,
input wire [31:0] mgmt_writedata
);
localparam MIF_ADDR_REG = 6'b011111;
localparam START_REG = 6'b000010;
generate
if (ENABLE_MIF == 1)
begin:mif_reconfig // Generate Reconfig with MIF
// MIF-related regs/wires
reg [RECONFIG_ADDR_WIDTH-1:0] reconfig_mgmt_addr;
reg reconfig_mgmt_read;
reg reconfig_mgmt_write;
reg [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_writedata;
wire reconfig_mgmt_waitrequest;
wire [RECONFIG_DATA_WIDTH-1:0] reconfig_mgmt_readdata;
wire [RECONFIG_ADDR_WIDTH-1:0] mif2reconfig_addr;
wire mif2reconfig_busy;
wire mif2reconfig_read;
wire mif2reconfig_write;
wire [RECONFIG_DATA_WIDTH-1:0] mif2reconfig_writedata;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
reg mif_select;
reg user_start;
wire reconfig2mif_start_out;
assign mgmt_waitrequest = reconfig_mgmt_waitrequest | mif2reconfig_busy | user_start;
// Don't output readdata if MIF streaming is taking place
assign mgmt_readdata = (mif_select) ? 32'b0 : reconfig_mgmt_readdata;
always @(posedge mgmt_clk)
begin
if (mgmt_reset)
begin
reconfig_mgmt_addr <= 0;
reconfig_mgmt_read <= 0;
reconfig_mgmt_write <= 0;
reconfig_mgmt_writedata <= 0;
user_start <= 0;
end
else
begin
reconfig_mgmt_addr <= (mif_select) ? mif2reconfig_addr : mgmt_address;
reconfig_mgmt_read <= (mif_select) ? mif2reconfig_read : mgmt_read;
reconfig_mgmt_write <= (mif_select) ? mif2reconfig_write : mgmt_write;
reconfig_mgmt_writedata <= (mif_select) ? mif2reconfig_writedata : mgmt_writedata;
user_start <= (mgmt_address == START_REG && mgmt_write == 1'b1) ? 1'b1 : 1'b0;
end
end
always @(*)
begin
if (mgmt_reset)
begin
mif_select <= 0;
end
else
begin
mif_select <= (reconfig2mif_start_out || mif2reconfig_busy) ? 1'b1 : 1'b0;
end
end
altera_pll_reconfig_mif_reader
#(
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS),
.DEVICE_FAMILY(device_family),
.ENABLE_MIF(ENABLE_MIF),
.MIF_FILE_NAME(MIF_FILE_NAME)
) altera_pll_reconfig_mif_reader_inst0 (
.mif_clk(mgmt_clk),
.mif_rst(mgmt_reset),
//Altera_PLL Reconfig interface
//inputs
.reconfig_busy(reconfig_mgmt_waitrequest),
.reconfig_read_data(reconfig_mgmt_readdata),
//outputs
.reconfig_write_data(mif2reconfig_writedata),
.reconfig_addr(mif2reconfig_addr),
.reconfig_write(mif2reconfig_write),
.reconfig_read(mif2reconfig_read),
//MIF Ctrl Interface
//inputs
.mif_base_addr(mif_base_addr),
.mif_start(reconfig2mif_start_out),
//outputs
.mif_busy(mif2reconfig_busy)
);
// ------ END MIF-RELATED MANAGEMENT ------
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(reconfig_mgmt_readdata),
.mgmt_waitrequest(reconfig_mgmt_waitrequest),
//User data inputs
.mgmt_address(reconfig_mgmt_addr),
.mgmt_read(reconfig_mgmt_read),
.mgmt_write(reconfig_mgmt_write),
.mgmt_writedata(reconfig_mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig with MIF
else
begin:reconfig_core // Generate Reconfig core only
wire reconfig2mif_start_out;
wire [ROM_ADDR_WIDTH-1:0] mif_base_addr;
altera_pll_reconfig_core
#(
.reconf_width(reconf_width),
.device_family(device_family),
.RECONFIG_ADDR_WIDTH(RECONFIG_ADDR_WIDTH),
.RECONFIG_DATA_WIDTH(RECONFIG_DATA_WIDTH),
.ROM_ADDR_WIDTH(ROM_ADDR_WIDTH),
.ROM_DATA_WIDTH(ROM_DATA_WIDTH),
.ROM_NUM_WORDS(ROM_NUM_WORDS)
) altera_pll_reconfig_core_inst0 (
//inputs
.mgmt_clk(mgmt_clk),
.mgmt_reset(mgmt_reset),
//PLL interface conduits
.reconfig_to_pll(reconfig_to_pll),
.reconfig_from_pll(reconfig_from_pll),
//User data outputs
.mgmt_readdata(mgmt_readdata),
.mgmt_waitrequest(mgmt_waitrequest),
//User data inputs
.mgmt_address(mgmt_address),
.mgmt_read(mgmt_read),
.mgmt_write(mgmt_write),
.mgmt_writedata(mgmt_writedata),
// other
.mif_start_out(reconfig2mif_start_out),
.mif_base_addr(mif_base_addr)
);
end // End generate reconfig core only
endgenerate
endmodule
|
module fifo(/*AUTOARG*/
// Outputs
fifo_full_w, data_valid_r, rdata_r,
// Inputs
clk, rst_n, enqueue_w, data_in_w, dequeue_w, full_threshold
);
input clk;
input rst_n;
output fifo_full_w;
input enqueue_w;
input [(DATA_WIDTH-1):0] data_in_w;
output data_valid_r;
input dequeue_w;
input [1:0] full_threshold;
output [(DATA_WIDTH-1):0] rdata_r;
endmodule
module req (p_clk, carb_rst_rnp, req_rp, len_rxp, deq_req, deq_len, deq_val);
input p_clk;
input carb_rst_rnp;
input [4:0] len_rxp;
input req_rp;
input deq_req;
output [4:0] deq_len;
output deq_val;
reg [5:0] fifo_entry1_rp;
reg [5:0] fifo_entry2_rp;
reg [4:0] deq_len;
reg deq_val;
endmodule
module pull( /*AUTOARG*/
// Outputs
d_len, d_val,
// Inputs
clk, rst_rnpha, lenar_rxp, rem_rpd, d_rews
);
input clk;
input rst_rnpha;
input [4:0] lenar_rxp;
input rem_rpd;
input d_rews;
output [4:0] d_len;
output d_val;
/* req AUTO_TEMPLATE "\(g[a-z0-9]+\|g.*[0-9]\)" (
.p_clk (my_clk_@),
.len_rxp (carb_rst_rnp_@),
.carb_rst_rnp (pull_req1));
*/
req test432_gbe5(/*AUTOINST*/
// Outputs
.deq_len (deq_len[4:0]),
.deq_val (deq_val),
// Inputs
.p_clk (my_clk_gbe5), // Templated
.carb_rst_rnp (pull_req1), // Templated
.len_rxp (carb_rst_rnp_gbe5), // Templated
.req_rp (req_rp),
.deq_req (deq_req));
req gbe9_vreos(/*AUTOINST*/
// Outputs
.deq_len (deq_len[4:0]),
.deq_val (deq_val),
// Inputs
.p_clk (my_clk_gbe9), // Templated
.carb_rst_rnp (pull_req1), // Templated
.len_rxp (carb_rst_rnp_gbe9), // Templated
.req_rp (req_rp),
.deq_req (deq_req));
/* fifo AUTO_TEMPLATE "gbe[0-9]+_\([^\_]+\)" (
.clk (@_clk),
.\(.*data.*\) (@_\1),
.\(.*\)\(full\)\(.*\) (\1@\3),
.\(en\|de\)\(.\).+ (@_\1\2));
*/
fifo #(5) gbe2_pull_req (/*AUTOINST*/
// Outputs
.fifo_full_w (fifo_pull_w), // Templated
.data_valid_r (pull_data_valid_r), // Templated
.rdata_r (pull_rdata_r), // Templated
// Inputs
.clk (pull_clk), // Templated
.rst_n (rst_n),
.enqueue_w (pull_enq), // Templated
.data_in_w (pull_data_in_w), // Templated
.dequeue_w (pull_deq), // Templated
.full_threshold (pull_threshold)); // Templated
fifo #(5)
gbe1_pull_req_fifo( /*AUTOINST*/
// Outputs
.fifo_full_w (fifo_pull_w), // Templated
.data_valid_r (pull_data_valid_r), // Templated
.rdata_r (pull_rdata_r), // Templated
// Inputs
.clk (pull_clk), // Templated
.rst_n (rst_n),
.enqueue_w (pull_enq), // Templated
.data_in_w (pull_data_in_w), // Templated
.dequeue_w (pull_deq), // Templated
.full_threshold (pull_threshold)); // Templated
endmodule // pull_arb
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW: readmemh function - comments in data file
//
//
module main ();
reg [7:0] array [0:7];
reg error ;
reg [3:0] count;
initial
begin
error = 0;
$readmemh("ivltests/readmemh4.dat",array);
for(count = 0; count <= 7; count = count + 1)
begin
if(array[count[2:0]] !== count)
begin
error = 1;
$display("FAILED - array[count] == %h, s/b %h",
array[count],count);
end
end
if(error == 0)
$display("PASSED\n");
$finish ;
end
endmodule
|
//
// Designed by Qiang Wu
// 16K bytes, 32bit interface
`timescale 1ns/1ps
module bbram(clk, addr, data_in, data_out, we, en, reset);
input clk;
input [13:2] addr;
input [31:0] data_in;
output [31:0] data_out;
input [3:0] we;
input en;
input reset;
RAMB16_S4 localram0(
.DO (data_out[3:0]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[3:0]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram0.INIT_00 = 256'hEECCCBABCBAA98061EDEFEDDDCBDFFDDDCBCDCBBA94307555385689665A70303;
defparam localram0.INIT_01 = 256'h05B3709AD059097099D960BC70BAD06BA70BADCB65BAF147587D0DCDEDCCCBAC;
defparam localram0.INIT_02 = 256'h01808B850770550A3077B3607C0677ABD00808B850770550A3077B3070577AAD;
defparam localram0.INIT_03 = 256'hA70983040A609B50A70983040A609B50A70954040A7DD8DCAAD706CE0AAA7ABD;
defparam localram0.INIT_04 = 256'h50A70983040A609B50A70983040A609B50A70954040AB50AA50976040A60AB50;
defparam localram0.INIT_05 = 256'hBB40780576C4078057670C7D76DD056B7ECAE0506BCAAD706BCA7098040A609B;
defparam localram0.INIT_06 = 256'hDD4D60C70ABDA0AB70080950FA4078056670BBDC4C0780586BA70BBDC60ACC30;
defparam localram0.INIT_07 = 256'h457754688450B650B80CBD70C90B3BDACC4D74688450C650C80DCE70D90C3CEB;
defparam localram0.INIT_08 = 256'h86A5018440ABB50A60563AA436ACB664A40561568640AB05AB09A0BC4580CD9C;
defparam localram0.INIT_09 = 256'h00000000000000000021232123212308D7470564BB9709DD960AB70AADA07805;
defparam localram0.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram0.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram1(
.DO (data_out[7:4]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[7:4]),
.EN (en),
.SSR (reset),
.WE (we[0])
);
defparam localram1.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram1.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram2(
.DO (data_out[11:8]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[11:8]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram2.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram2.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram3(
.DO (data_out[15:12]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[15:12]),
.EN (en),
.SSR (reset),
.WE (we[1])
);
defparam localram3.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram3.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram4(
.DO (data_out[19:16]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[19:16]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram4.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram4.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram5(
.DO (data_out[23:20]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[23:20]),
.EN (en),
.SSR (reset),
.WE (we[2])
);
defparam localram5.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram5.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram6(
.DO (data_out[27:24]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[27:24]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram6.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram6.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
RAMB16_S4 localram7(
.DO (data_out[31:28]),
.ADDR (addr[13:2]),
.CLK (clk),
.DI (data_in[31:28]),
.EN (en),
.SSR (reset),
.WE (we[3])
);
defparam localram7.INIT_00 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_01 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_02 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_03 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_04 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_05 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_06 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_07 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_08 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_09 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_0F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_10 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_11 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_12 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_13 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_14 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_15 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_16 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_17 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_18 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_19 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_1F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_20 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_21 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_22 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_23 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_24 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_25 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_26 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_27 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_28 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_29 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_2F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_30 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_31 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_32 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_33 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_34 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_35 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_36 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_37 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_38 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_39 = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3A = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3B = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3C = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3D = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3E = 256'h0000000000000000000000000000000000000000000000000000000000000000;
defparam localram7.INIT_3F = 256'h0000000000000000000000000000000000000000000000000000000000000000;
endmodule |
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_SCC_N_poe for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Kibin Park <[email protected]>
// Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Kibin Park <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_SCC_N_poe
// Module Name: NPCG_Toggle_SCC_N_poe
// File Name: NPCG_Toggle_SCC_N_poe.v
//
// Version: v1.0.0
//
// Description: NFC power on reset
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_SCC_N_poe
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iCMDValid ,
oCMDReady ,
oStart ,
oLastStep ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_NumOfData
);
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input iCMDValid ;
output oCMDReady ;
output oStart ;
output oLastStep ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [15:0] oPM_NumOfData ;
wire wModuleTriggered ;
localparam State_Idle = 3'b000;
localparam State_POECmdIssue = 3'b001;
localparam State_POEWait = 3'b011;
reg [2:0] rCurState ;
reg [2:0] rNextState ;
wire wTimerTrig;
always @ (posedge iSystemClock)
if (iReset)
rCurState <= State_Idle;
else
rCurState <= rNextState;
always @ (*)
case (rCurState)
State_Idle:
rNextState <= (wModuleTriggered)?State_POECmdIssue:State_Idle;
State_POECmdIssue:
rNextState <= (iPM_Ready)?State_POEWait:State_POECmdIssue;
State_POEWait:
rNextState <= (oLastStep)?State_Idle:State_POEWait;
default:
rNextState <= State_Idle;
endcase
assign wModuleTriggered = (iCMDValid && iTargetID[4:0] == 5'b00101 && iOpcode[5:0] == 6'b111110);
assign oCMDReady = (rCurState == State_Idle);
assign wTimerTrig = (rCurState == State_POECmdIssue);
assign oStart = wModuleTriggered;
assign oLastStep = (rCurState == State_POEWait) & iPM_LastStep[0];
assign oPM_PCommand[7:0] = {1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, 1'b0, wTimerTrig};
assign oPM_PCommandOption[2:0] = 3'b000;
assign oPM_NumOfData[15:0] = 16'd11000;
endmodule
|
//Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
//--------------------------------------------------------------------------------
//Tool Version: Vivado v.2017.2 (lin64) Build 1909853 Thu Jun 15 18:39:10 MDT 2017
//Date : Wed Jul 5 01:27:13 2017
//Host : saturn running 64-bit Ubuntu 16.10
//Command : generate_target fmrv32im_artya7_wrapper.bd
//Design : fmrv32im_artya7_wrapper
//Purpose : IP block netlist
//--------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module fmrv32im_artya7_wrapper
(CLK100MHZ,
GPIO_ot,
UART_rx,
UART_tx,
gpio_i,
gpio_o);
input CLK100MHZ;
output [31:0]GPIO_ot;
input UART_rx;
output UART_tx;
input [31:0]gpio_i;
output [31:0]gpio_o;
wire CLK100MHZ;
wire [31:0]GPIO_ot;
wire UART_rx;
wire UART_tx;
wire [31:0]gpio_i;
wire [31:0]gpio_o;
fmrv32im_artya7 fmrv32im_artya7_i
(.CLK100MHZ(CLK100MHZ),
.GPIO_i(gpio_i),
.GPIO_o(gpio_o),
.GPIO_ot(GPIO_ot),
.UART_rx(UART_rx),
.UART_tx(UART_tx));
endmodule
|
/*
* Copyright (c) 1998-2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* SDW: This test is a first expression test inside a parameter declaration.
*/
module test;
parameter A0 = 2'b10 & 2'b11 ;
initial
begin
if(A0 !== 2'b10)
$display("FAILED - A0 expression AND doesn't work.");
else
$display("PASSED");
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_bypass_reg2(clock, resetn, i_settings,
i_register_settings,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataouta, o_dataouta_valid, i_dataouta_stall,
o_dataoutb, o_dataoutb_valid, i_dataoutb_stall);
parameter DATA_WIDTH = 32;
input clock;
input resetn;
input [1:0] i_settings;
input [DATA_WIDTH-1:0] i_register_settings;
input [DATA_WIDTH-1:0] i_dataa, i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataouta, o_dataoutb;
output o_dataouta_valid, o_dataoutb_valid;
input i_dataouta_stall, i_dataoutb_stall;
assign o_dataouta = i_settings[0] ? i_register_settings : i_dataa;
assign o_dataoutb = i_settings[1] ? i_register_settings : i_datab;
assign o_dataouta_valid = i_dataa_valid;
assign o_dataoutb_valid = i_datab_valid;
assign o_dataa_stall = i_dataouta_stall;
assign o_datab_stall = i_dataoutb_stall;
endmodule
|
`timescale 1ns/100ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 2, Question 2
*/
// Testbench for behavioral model for the decoder
// Import the modules that will be tested for in this testbench
`include "ham_15_11_decoder.syn.v"
`include "ham_decoder.syn.v"
`include "/auto/home-scf-06/ee577/design_pdk/osu_stdcells/lib/tsmc018/lib/osu018_stdcells.v"
// IMPORTANT: To run this, try: ncverilog -f ee577bHw2q2.f +gui
module tb_decoder();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the arbiter
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
wire [10:0] qout;
// Declare "reg" signals: inputs to the DUT
reg [14:0] cin;
/**
* Instantiate an instance of arbiter_LRU4 so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "arb"
*/
ham_15_11_decoder dec (
// instance_name(signal name),
// Signal name can be the same as the instance name
cin,qout);
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display(" << Starting the simulation >>");
cin = 15'b110101100000011;
$display(cin[1]," << b1 b2 >>",cin[2]);
$display(cin[3]," << b1 b2 >>",cin[4]);
// @ t=0,
#1;
cin = 15'b111000111000011;
#1;
cin = 15'b110011101010011;
#1;
cin = 15'b111101110010011;
#1;
cin = 15'b111110000100011;
#20;
$display(" << Finishing the simulation >>");
$finish;
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
(** Extraction to Ocaml : use of basic Ocaml types *)
Extract Inductive bool => bool [ true false ].
Extract Inductive option => option [ Some None ].
Extract Inductive unit => unit [ "()" ].
Extract Inductive list => list [ "[]" "( :: )" ].
Extract Inductive prod => "( * )" [ "" ].
(** NB: The "" above is a hack, but produce nicer code than "(,)" *)
(** Mapping sumbool to bool and sumor to option is not always nicer,
but it helps when realizing stuff like [lt_eq_lt_dec] *)
Extract Inductive sumbool => bool [ true false ].
Extract Inductive sumor => option [ Some None ].
(** Restore lazyness of andb, orb.
NB: without these Extract Constant, andb/orb would be inlined
by extraction in order to have lazyness, producing inelegant
(if ... then ... else false) and (if ... then true else ...).
*)
Extract Inlined Constant andb => "(&&)".
Extract Inlined Constant orb => "(||)".
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 18:23:12 08/15/2011
// Design Name:
// Module Name: RCB_FRL_RX_Data_FIFO_8bit
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module RCB_FRL_RX_Data_FIFO_8bit(
input RDCLK,
input RDEN,
input WRCLK,
input WREN,
input RST,
input [7:0] DI,
output ALMOSTEMPTY,
output ALMOSTFULL,
output EMPTY,
output FULL,
output [7:0] DO
);
wire [7:0] temp1;
FIFO18 FIFO18_inst (
.ALMOSTEMPTY(ALMOSTEMPTY), // 1-bit almost empty output flag
.ALMOSTFULL(ALMOSTFULL), // 1-bit almost full output flag
.DO({temp1, DO[7:0]}), // 16-bit data output
.DOP(), // 2-bit parity data output
.EMPTY(EMPTY), // 1-bit empty output flag
.FULL(FULL), // 1-bit full output flag
.RDCOUNT(), // 12-bit read count output
.RDERR(), // 1-bit read error output
.WRCOUNT(), // 12-bit write count output
.WRERR(), // 1-bit write error
.DI({8'h0,DI[7:0]}), // 16-bit data input
.DIP(), // 2-bit parity input
.RDCLK(RDCLK), // 1-bit read clock input
.RDEN(RDEN), // 1-bit read enable input
.RST(RST), // 1-bit reset input
.WRCLK(WRCLK), // 1-bit write clock input
.WREN(WREN) // 1-bit write enable input
);
defparam FIFO18_inst.DATA_WIDTH = 9;
defparam FIFO18_inst.ALMOST_EMPTY_OFFSET = 6;
endmodule
|
module dut (output reg[31:0] size,
output reg signed [31:0] ival,
output reg [31:0] hval);
parameter string foo = "1234";
string tmp;
real rval;
initial begin
size = foo.len();
ival = foo.atoi();
hval = foo.atohex();
rval = foo.atoreal();
tmp = foo;
$display("foo=%0s, tmp=%0s", foo, tmp);
if (tmp != foo) begin
$display("FAILED");
$finish;
end
$display("rval=%f", rval);
if (rval != ival) begin
$display("FAILED -- rval=%f, ival=%0d", rval, ival);
$finish;
end
end
endmodule // dut
module main;
wire [31:0] dut0_size, dut1_size, dut2_size;
wire signed [31:0] dut0_ival, dut1_ival, dut2_ival;
wire unsigned [31:0] dut0_hval, dut1_hval, dut2_hval;
// Instantate module with string parameter, use default value.
dut dut0 (dut0_size, dut0_ival, dut0_hval);
// Instantate module with string parameter, use override value.
dut #(.foo("12345")) dut1 (dut1_size, dut1_ival, dut1_hval);
// Instantate module with string parameter, use defparam value.
defparam dut2.foo = "123456";
dut dut2 (dut2_size, dut2_ival, dut2_hval);
initial begin
#100 ;
$display("dut0_size=%0d", dut0_size);
if (dut0_size !== 4) begin
$display("FAILED");
$finish;
end
$display("dut1_size=%0d", dut1_size);
if (dut1_size !== 5) begin
$display("FAILED");
$finish;
end
$display("dut2_size=%0d", dut2_size);
if (dut2_size !== 6) begin
$display("FAILED");
$finish;
end
$display("dut0_ival=%0d", dut0_ival);
if (dut0_ival !== 1234) begin
$display("FAILED");
$finish;
end
$display("dut1_ival=%0d", dut1_ival);
if (dut1_ival !== 12345) begin
$display("FAILED");
$finish;
end
$display("dut2_ival=%0d", dut2_ival);
if (dut2_ival !== 123456) begin
$display("FAILED");
$finish;
end
$display("dut0_hval=%0h", dut0_hval);
if (dut0_hval !== 32'h1234) begin
$display("FAILED");
$finish;
end
$display("dut1_hval=%0h", dut1_hval);
if (dut1_hval !== 32'h12345) begin
$display("FAILED");
$finish;
end
$display("dut2_hval=%0h", dut2_hval);
if (dut2_hval !== 32'h123456) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
endmodule // main
|
`default_nettype none
`timescale 1ns / 1ps
// The transmit queue gives the client a (typically, 16) deep FIFO in which
// a processor can store data for eventual transmission.
module sia_txq(
input clk_i,
input reset_i,
input [SRW:0] dat_i,
input we_i,
input [BW:0] bits_i,
input [BRW:0] baud_i,
input [2:0] txcmod_i,
output txd_o,
output txc_o,
output not_full_o,
output empty_o,
output idle_o
);
parameter SHIFT_REG_WIDTH = 16;
parameter BITS_WIDTH = 5;
parameter BAUD_RATE_WIDTH = 32;
parameter DEPTH_BITS = 4;
parameter DATA_BITS = SHIFT_REG_WIDTH;
parameter BW = BITS_WIDTH - 1;
parameter BRW = BAUD_RATE_WIDTH - 1;
parameter SRW = SHIFT_REG_WIDTH - 1;
wire txc;
assign txc_o = (txc & txcmod_i[2]) ^ txcmod_i[0];
wire [SRW:0] txq_dat;
wire txq_en, txq_pop, txq_oe, txq_full, txq_empty;
wire txq_idle;
assign txq_en = txq_idle & ~txq_empty;
assign txq_oe = txq_en;
assign txq_pop = txq_en;
assign empty_o = txq_empty;
assign not_full_o = ~txq_full;
assign idle_o = txq_idle;
queue #(
.DEPTH_BITS(DEPTH_BITS),
.DATA_BITS(DATA_BITS)
) q (
.clk_i(clk_i),
.reset_i(reset_i),
.dat_i(dat_i),
.push_i(we_i),
.pop_i(txq_pop),
.oe_i(txq_oe),
.dat_o(txq_dat),
.full_o(txq_full),
.empty_o(txq_empty)
);
sia_transmitter #(
.SHIFT_REG_WIDTH(SHIFT_REG_WIDTH),
.BAUD_RATE_WIDTH(BAUD_RATE_WIDTH),
.BITS_WIDTH(BITS_WIDTH)
) t (
.clk_i(clk_i),
.reset_i(reset_i),
.rxd_i(1'b1),
.dat_i(txq_dat),
.txreg_we_i(txq_en),
.txreg_oe_i(1'b0),
.txbaud_i(baud_i),
.bits_i(bits_i),
.txd_o(txd_o),
.txc_o(txc),
.idle_o(txq_idle),
.brg_o(),
.bits_o(),
.dat_o()
);
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// NOTE This only works for N=4, max decim rate of 128
// NOTE signal "rate" is ONE LESS THAN the actual rate
module cic_dec_shifter(rate,signal_in,signal_out);
parameter bw = 16;
parameter maxbitgain = 28;
input [7:0] rate;
input wire [bw+maxbitgain-1:0] signal_in;
output reg [bw-1:0] signal_out;
function [4:0] bitgain;
input [7:0] rate;
case(rate)
// Exact Cases -- N*log2(rate)
8'd4 : bitgain = 8;
8'd8 : bitgain = 12;
8'd16 : bitgain = 16;
8'd32 : bitgain = 20;
8'd64 : bitgain = 24;
8'd128 : bitgain = 28;
// Nearest without overflow -- ceil(N*log2(rate))
8'd5 : bitgain = 10;
8'd6 : bitgain = 11;
8'd7 : bitgain = 12;
8'd9 : bitgain = 13;
8'd10,8'd11 : bitgain = 14;
8'd12,8'd13 : bitgain = 15;
8'd14,8'd15 : bitgain = 16;
8'd17,8'd18,8'd19 : bitgain = 17;
8'd20,8'd21,8'd22 : bitgain = 18;
8'd23,8'd24,8'd25,8'd26 : bitgain = 19;
8'd27,8'd28,8'd29,8'd30,8'd31 : bitgain = 20;
8'd33,8'd34,8'd35,8'd36,8'd37,8'd38 : bitgain = 21;
8'd39,8'd40,8'd41,8'd42,8'd43,8'd44,8'd45 : bitgain = 22;
8'd46,8'd47,8'd48,8'd49,8'd50,8'd51,8'd52,8'd53 : bitgain = 23;
8'd54,8'd55,8'd56,8'd57,8'd58,8'd59,8'd60,8'd61,8'd62,8'd63 : bitgain = 24;
8'd65,8'd66,8'd67,8'd68,8'd69,8'd70,8'd71,8'd72,8'd73,8'd74,8'd75,8'd76 : bitgain = 25;
8'd77,8'd78,8'd79,8'd80,8'd81,8'd82,8'd83,8'd84,8'd85,8'd86,8'd87,8'd88,8'd89,8'd90 : bitgain = 26;
8'd91,8'd92,8'd93,8'd94,8'd95,8'd96,8'd97,8'd98,8'd99,8'd100,8'd101,8'd102,8'd103,8'd104,8'd105,8'd106,8'd107 : bitgain = 27;
default : bitgain = 28;
endcase // case(rate)
endfunction // bitgain
wire [4:0] shift = bitgain(rate+1);
// We should be able to do this, but can't ....
// assign signal_out = signal_in[shift+bw-1:shift];
always @*
case(shift)
5'd8 : signal_out = signal_in[8+bw-1:8];
5'd10 : signal_out = signal_in[10+bw-1:10];
5'd11 : signal_out = signal_in[11+bw-1:11];
5'd12 : signal_out = signal_in[12+bw-1:12];
5'd13 : signal_out = signal_in[13+bw-1:13];
5'd14 : signal_out = signal_in[14+bw-1:14];
5'd15 : signal_out = signal_in[15+bw-1:15];
5'd16 : signal_out = signal_in[16+bw-1:16];
5'd17 : signal_out = signal_in[17+bw-1:17];
5'd18 : signal_out = signal_in[18+bw-1:18];
5'd19 : signal_out = signal_in[19+bw-1:19];
5'd20 : signal_out = signal_in[20+bw-1:20];
5'd21 : signal_out = signal_in[21+bw-1:21];
5'd22 : signal_out = signal_in[22+bw-1:22];
5'd23 : signal_out = signal_in[23+bw-1:23];
5'd24 : signal_out = signal_in[24+bw-1:24];
5'd25 : signal_out = signal_in[25+bw-1:25];
5'd26 : signal_out = signal_in[26+bw-1:26];
5'd27 : signal_out = signal_in[27+bw-1:27];
5'd28 : signal_out = signal_in[28+bw-1:28];
default : signal_out = signal_in[28+bw-1:28];
endcase // case(shift)
endmodule // cic_dec_shifter
|
module Pipeline(
input clk,
output [31:0] PC_IF_ID,
output [5:0] Op_IF_ID,
output [4:0] Rs_IF_ID,
output [4:0] Rt_IF_ID,
output [4:0] Rd_IF_ID,
output [4:0] Shamt_IF_ID,
output [5:0] Func_IF_ID,
output [31:0] PC_ID_EX,
output [5:0] Op_ID_EX,
output [2:0] Condition_ID_EX,
output Branch_ID_EX,
output MemWrite_ID_EX,
output Reg_Write_ID_EX,
output MemRead_ID_EX,
output Jump_ID_EX,
output [1:0] ExResultSrc_ID_EX,
output ALUSrcA_ID_EX,
output ALUSrcB_ID_EX,
output [3:0] ALUOp_ID_EX,
output [1:0] RegDst_ID_EX,
output ShiftAmountSrc_ID_EX,
output [1:0] ShiftOp_ID_EX,
output [31:0] A_in_ID_EX,B_in_ID_EX,
output [31:0] A, B,
output [4:0] Rs_ID_EX,Rt_ID_EX,Rd_ID_EX,
output [31:0] Imm32_ID_EX,
output [4:0] Shamt_ID_EX,
output [31:0] Branch_addr_EX_MEM,
output [5:0] Op_EX_MEM,
output [2:0] Codition_EX_MEM,
output Branch_EX_MEM,
output MemWrite_EX_MEM,
output Reg_Write_EX_MEM,
output MemRead_EX_MEM,
output [31:0] MemData_EX_MEM,
output [31:0] WBData_EX_MEM,
output Less_EX_MEM,Zero_EX_MEM,Overflow_EX_MEM,
output [4:0] Rd_EX_MEM,
output [31:0] MemData_MEM_WR,
output [3:0] Rd_write_byte_en_MEM_WR,
output [31:0] WBData_MEM_WR,
output MemRead_MEM_WR,
output Reg_Write_MEM_WR,
output [4:0] Rd_MEM_WR,
output [3:0] Mem_write_byte_en,
output IF_ID_Flush, ID_EX_Flush, IF_ID_Stall, ID_EX_Stall,
output [31:0]Rs_out_EX, Rt_out_EX,
output [7:0] A_in_sel, B_in_sel,
output [3:0] RsOut_sel, RtOut_sel
);
wire [31:0] PC3;
wire [1:0] PCSrc;
wire [31:0] PC_IF;
wire [31:0] IR_out;
//wire IF_ID_Stall,IF_ID_Flush;
wire [31:0] Data;
//wire [3:0] RsOut_sel,RtOut_sel;
wire [31:0] A_in_ID;
wire [31:0] B_in_ID;
wire [31:0] Immediate32_ID;
wire [2:0] Condition_ID;
wire Branch_ID;
wire MemWrite_ID;
wire RegWrite_ID;
wire MemRead_ID;
wire Jump_ID;
wire [1:0] ExResultSrc_ID;
wire ALUSrcA_ID;
wire ALUSrcB_ID;
wire [3:0] ALUOp_ID;
wire [1:0] RegDst_ID;
wire ShiftAmountSrc_ID;
wire [1:0] ShiftOp_ID;
wire IF_ID_RtRead_ID;
wire loadusein, loaduseout;
//wire ID_EX_Stall,ID_EX_Flush;
//wire [7:0] A_in_sel,B_in_sel;
wire [31:0] Branch_Addr;
wire [31:0] WBData_EX;
wire [31:0] MemData;
wire Less,Zero,Overflow;
wire [4:0] Rd_Dst;
wire EX_MEM_Stall,EX_MEM_Flush;
wire [31:0] MemData_MEM;
wire [3:0] Rd_write_byte_en_MEM;
wire RegWriteValid,BranchValid;
wire MEM_WR_Stall,MEM_WR_Flush;
wire [3:0] Rd_write_byte_en_new;
//取指令
IF IF(clk,PCSrc,PC_IF_ID,{PC_ID_EX[31:28],Rs_ID_EX,Rt_ID_EX,Imm32_ID_EX[15:0],2'b00},Branch_addr_EX_MEM,PC3,PC_IF,IR_out);
IF_ID IF_ID(clk,IF_ID_Stall,IF_ID_Flush,PC_IF,IR_out[31:26],
IR_out[25:21],IR_out[20:16],IR_out[15:11],IR_out[10:6],
IR_out[5:0],PC_IF_ID,Op_IF_ID,Rs_IF_ID,Rt_IF_ID,Rd_IF_ID,
Shamt_IF_ID,Func_IF_ID);
//译码取数
ID ID(clk,Op_IF_ID,Rs_IF_ID,Rt_IF_ID,Rd_IF_ID,Shamt_IF_ID,
Func_IF_ID,Rd_write_byte_en_new,RsOut_sel,RtOut_sel,
Data,A_in_ID,B_in_ID,Immediate32_ID,Condition_ID,Branch_ID,
MemWrite_ID,RegWrite_ID,MemRead_ID,Jump_ID,ExResultSrc_ID,
ALUSrcA_ID,ALUSrcB_ID,ALUOp_ID,RegDst_ID,ShiftAmountSrc_ID,
ShiftOp_ID,IF_ID_RtRead_ID, Rs_out_EX, Rt_out_EX);
ID_EX ID_EX(clk,ID_EX_Stall,ID_EX_Flush,PC_IF_ID,Op_IF_ID,Condition_ID,
Branch_ID,MemWrite_ID,RegWrite_ID,MemRead_ID,Jump_ID,ExResultSrc_ID,
ALUSrcA_ID,ALUSrcB_ID,ALUOp_ID,RegDst_ID,ShiftAmountSrc_ID,
ShiftOp_ID,A_in_ID,B_in_ID,Rs_IF_ID,Rt_IF_ID,Rd_IF_ID,Immediate32_ID,
Shamt_IF_ID,loadusein, PC_ID_EX,Op_ID_EX,Condition_ID_EX,Branch_ID_EX,MemWrite_ID_EX,
Reg_Write_ID_EX,MemRead_ID_EX,Jump_ID_EX,ExResultSrc_ID_EX,ALUSrcA_ID_EX,
ALUSrcB_ID_EX,ALUOp_ID_EX,RegDst_ID_EX,ShiftAmountSrc_ID_EX,ShiftOp_ID_EX,
A_in_ID_EX,B_in_ID_EX,Rs_ID_EX,Rt_ID_EX,Rd_ID_EX,Imm32_ID_EX,Shamt_ID_EX,loaduseout
);
//执行
EX EX(PC_ID_EX,PC_IF_ID,ExResultSrc_ID_EX,ALUSrcA_ID_EX,ALUSrcB_ID_EX,ALUOp_ID_EX,
RegDst_ID_EX,ShiftAmountSrc_ID_EX,ShiftOp_ID_EX,A_in_ID_EX,B_in_ID_EX,Rs_ID_EX,
Rt_ID_EX,Rd_ID_EX,Imm32_ID_EX,Shamt_ID_EX,A_in_sel,B_in_sel,WBData_EX_MEM,Data,
Branch_Addr,WBData_EX,MemData,PC3,Less,Zero,Overflow,Rd_Dst, A, B
);
EX_MEM EX_MEM(clk,EX_MEM_Stall,EX_MEM_Flush,Branch_Addr,Op_ID_EX,Condition_ID_EX,
Branch_ID_EX,MemWrite_ID_EX,Reg_Write_ID_EX,MemRead_ID_EX,MemData,WBData_EX,
Less,Zero,Overflow,Rd_Dst,Branch_addr_EX_MEM,Op_EX_MEM,Codition_EX_MEM,Branch_EX_MEM,
MemWrite_EX_MEM,Reg_Write_EX_MEM,MemRead_EX_MEM,MemData_EX_MEM,WBData_EX_MEM,
Less_EX_MEM,Zero_EX_MEM,Overflow_EX_MEM,Rd_EX_MEM
);
//读写存储器
MEM MEM(clk,Op_EX_MEM,Codition_EX_MEM,Branch_EX_MEM,MemWrite_EX_MEM,Reg_Write_EX_MEM,
MemData_EX_MEM,Less_EX_MEM,Zero_EX_MEM,Overflow_EX_MEM,WBData_EX_MEM,MemData_MEM,
Rd_write_byte_en_MEM,RegWriteValid,BranchValid, Mem_write_byte_en
);
MEM_WR MEM_WR(clk,MEM_WR_Stall,MEM_WR_Flush,MemData_MEM,Rd_write_byte_en_MEM,WBData_EX_MEM,
MemRead_EX_MEM,RegWriteValid,Rd_EX_MEM,MemData_MEM_WR,Rd_write_byte_en_MEM_WR,
WBData_MEM_WR,MemRead_MEM_WR,Reg_Write_MEM_WR,Rd_MEM_WR
);
//写回寄存器
WR WR(Rd_write_byte_en_MEM_WR,Reg_Write_MEM_WR,MemData_MEM_WR,WBData_MEM_WR,MemRead_MEM_WR,Data,
Rd_write_byte_en_new
);
//冒险检测
HAZARD HAZARD(Rt_IF_ID,Rs_IF_ID,Rt_ID_EX,IF_ID_RtRead_ID,Jump_ID_EX,MemRead_ID_EX,BranchValid,
PCSrc,IF_ID_Stall,IF_ID_Flush,ID_EX_Stall,ID_EX_Flush, EX_MEM_Stall,EX_MEM_Flush,MEM_WR_Stall,
MEM_WR_Flush, loadusein
);
//转发控制单元
FORWARD FORWARD(Rs_ID_EX,Rt_ID_EX,Rd_EX_MEM,Rs_IF_ID,Rt_IF_ID,Rd_MEM_WR,RegWriteValid,Reg_Write_MEM_WR,
Rd_write_byte_en_new,loaduseout, RsOut_sel,RtOut_sel,A_in_sel,B_in_sel
);
endmodule
|
`define bsg_inv_macro(bits) \
if (harden_p && (width_p==bits) && vertical_p) \
begin: macro \
bsg_rp_tsmc_250_INVX8_b``bits inv_gate (.i0(i),.o); \
end \
else \
if (harden_p && (width_p==bits) && ~vertical_p) \
begin: macro \
bsg_rp_tsmc_250_INVX8_horiz_b``bits inv_gate (.i0(i),.o); \
end
module bsg_inv #(parameter `BSG_INV_PARAM(width_p)
, parameter harden_p=1
, parameter vertical_p=1
)
(input [width_p-1:0] i
, output [width_p-1:0] o
);
`bsg_inv_macro(85) else
`bsg_inv_macro(84) else
`bsg_inv_macro(83) else
`bsg_inv_macro(82) else
`bsg_inv_macro(81) else
`bsg_inv_macro(80) else
`bsg_inv_macro(79) else
`bsg_inv_macro(78) else
`bsg_inv_macro(77) else
`bsg_inv_macro(76) else
`bsg_inv_macro(75) else
`bsg_inv_macro(74) else
`bsg_inv_macro(73) else
`bsg_inv_macro(72) else
`bsg_inv_macro(71) else
`bsg_inv_macro(70) else
`bsg_inv_macro(69) else
`bsg_inv_macro(68) else
`bsg_inv_macro(67) else
`bsg_inv_macro(66) else
`bsg_inv_macro(65) else
`bsg_inv_macro(64) else
`bsg_inv_macro(63) else
`bsg_inv_macro(62) else
`bsg_inv_macro(61) else
`bsg_inv_macro(60) else
`bsg_inv_macro(59) else
`bsg_inv_macro(58) else
`bsg_inv_macro(57) else
`bsg_inv_macro(56) else
`bsg_inv_macro(55) else
`bsg_inv_macro(54) else
`bsg_inv_macro(53) else
`bsg_inv_macro(52) else
`bsg_inv_macro(51) else
`bsg_inv_macro(50) else
`bsg_inv_macro(49) else
`bsg_inv_macro(48) else
`bsg_inv_macro(47) else
`bsg_inv_macro(46) else
`bsg_inv_macro(45) else
`bsg_inv_macro(44) else
`bsg_inv_macro(43) else
`bsg_inv_macro(42) else
`bsg_inv_macro(41) else
`bsg_inv_macro(40) else
`bsg_inv_macro(39) else
`bsg_inv_macro(38) else
`bsg_inv_macro(37) else
`bsg_inv_macro(36) else
`bsg_inv_macro(35) else
`bsg_inv_macro(34) else
`bsg_inv_macro(33) else
`bsg_inv_macro(32) else
`bsg_inv_macro(31) else
`bsg_inv_macro(30) else
`bsg_inv_macro(29) else
`bsg_inv_macro(28) else
`bsg_inv_macro(27) else
`bsg_inv_macro(26) else
`bsg_inv_macro(25) else
`bsg_inv_macro(24) else
`bsg_inv_macro(23) else
`bsg_inv_macro(22) else
`bsg_inv_macro(21) else
`bsg_inv_macro(20) else
`bsg_inv_macro(19) else
`bsg_inv_macro(18) else
`bsg_inv_macro(17) else
`bsg_inv_macro(16) else
`bsg_inv_macro(15) else
`bsg_inv_macro(14) else
`bsg_inv_macro(13) else
`bsg_inv_macro(12) else
`bsg_inv_macro(11) else
`bsg_inv_macro(10) else
`bsg_inv_macro(9) else
`bsg_inv_macro(8) else
`bsg_inv_macro(7) else
`bsg_inv_macro(6) else
`bsg_inv_macro(5) else
`bsg_inv_macro(4) else
`bsg_inv_macro(3) else
`bsg_inv_macro(2) else
`bsg_inv_macro(1) else
begin :notmacro
initial assert(harden_p==0) else $error("## %m wanted to harden but no macro");
assign o = i;
end
endmodule
`BSG_ABSTRACT_MODULE(bsg_inv)
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Module Name: arduino_switch
// Project Name: XPP
//
//////////////////////////////////////////////////////////////////////////////////
module arduino_switch(
// configuration
input [31:0] analog_uart_gpio_sel, // bit 31- UART or digital IO on D0 and D1, bit 1:0- analog or IO on A5-A0 channels
input [15:0] digital_gpio_sel1, // configures Digital I/O bits 2 through 5
input [15:0] digital_gpio_sel2, // configures Digital I/O bits 6 through 9
input [15:0] digital_gpio_sel3, // configures Digital I/O bits 10 through 13
// Shield side
// analog channels
input [5:0] shield2sw_data_in_a5_a0,
output [5:0] sw2shield_data_out_a5_a0,
output [5:0] sw2shield_tri_out_a5_a0,
// input [5:0] analog_p_in,
// input [5:0] analog_n_in,
// digital channels
input [1:0] shield2sw_data_in_d1_d0,
output [1:0] sw2shield_data_out_d1_d0,
output [1:0] sw2shield_tri_out_d1_d0,
input [11:0] shield2sw_data_in_d13_d2,
output [11:0] sw2shield_data_out_d13_d2,
output [11:0] sw2shield_tri_out_d13_d2,
// dedicated i2c channel on J3 header
input shield2sw_sda_i_in,
output sw2shield_sda_o_out,
output sw2shield_sda_t_out,
input shield2sw_scl_i_in,
output sw2shield_scl_o_out,
output sw2shield_scl_t_out,
// dedicated SPI on J6
input shield2sw_spick_i,
output sw2shield_spick_o,
output sw2shield_spick_t,
input shield2sw_miso_i,
output sw2shield_miso_o,
output sw2shield_miso_t,
input shield2sw_mosi_i,
output sw2shield_mosi_o,
output sw2shield_mosi_t,
input shield2sw_ss_i,
output sw2shield_ss_o,
output sw2shield_ss_t,
// PL Side
// analog channels related
output [5:0] sw2pl_data_in_a5_a0,
input [5:0] pl2sw_data_o_a5_a0,
input [5:0] pl2sw_tri_o_a5_a0,
// output [5:0] analog_p_out, // analog output to XADC
// output [5:0] analog_n_out, // analog output to XADC
output sda_i_in_a4,
input sda_o_in_a4,
input sda_t_in_a4,
output scl_i_in_a5,
input scl_o_in_a5,
input scl_t_in_a5,
// digital 0 and 1 channels related (UART)
output [1:0] sw2pl_data_in_d1_d0, // data from switch to PL
input [1:0] pl2sw_data_o_d1_d0, // data from PL to switch
input [1:0] pl2sw_tri_o_d1_d0, // tri state control from PL to switch
output rx_i_in_d0, // rx data from switch to UART
input tx_o_in_d1, // tx data from UART to switch
input tx_t_in_d1, // tx tri state control from UART to switch
// digital 2 to 13 channels related
output [11:0] sw2pl_data_in_d13_d2,
input [11:0] pl2sw_data_o_d13_d2,
input [11:0] pl2sw_tri_o_d13_d2,
// SPI
output spick_i_in_d13,
input spick_o_in_d13,
input spick_t_in_d13,
output miso_i_in_d12,
input miso_o_in_d12,
input miso_t_in_d12,
output mosi_i_in_d11,
input mosi_o_in_d11,
input mosi_t_in_d11,
output ss_i_in_d10,
input ss_o_in_d10,
input ss_t_in_d10,
// Interrupts
output [11:0] interrupt_i_in_d13_d2,
output [1:0] interrupt_i_in_d1_d0,
output [5:0] interrupt_i_in_a5_a0,
// dedicated i2c
output pl2iic_sda_i_in,
input iic2pl_sda_o_out,
input iic2pl_sda_t_out,
output pl2iic_scl_i_in,
input iic2pl_scl_o_out,
input iic2pl_scl_t_out,
// dedicated SPI
output pl2qspi_spick_i,
input qspi2pl_spick_o,
input qspi2pl_spick_t,
output pl2qspi_mosi_i,
input qspi2pl_mosi_o,
input qspi2pl_mosi_t,
output pl2qspi_miso_i,
input qspi2pl_miso_o,
input qspi2pl_miso_t,
output pl2qspi_ss_i,
input qspi2pl_ss_o,
input qspi2pl_ss_t,
// PWM
input [5:0] pwm_o_in,
input [5:0] pwm_t_in,
// Timer
output [7:0] timer_i_in, // Input capture
input [7:0] timer_o_in, // output compare
input [7:0] timer_t_in
);
assign pl2iic_sda_i_in=shield2sw_sda_i_in;
assign sw2shield_sda_o_out=iic2pl_sda_o_out;
assign sw2shield_sda_t_out=iic2pl_sda_t_out;
assign pl2iic_scl_i_in=shield2sw_scl_i_in;
assign sw2shield_scl_o_out=iic2pl_scl_o_out;
assign sw2shield_scl_t_out=iic2pl_scl_t_out;
assign pl2qspi_spick_i=shield2sw_spick_i; //
assign sw2shield_spick_o=qspi2pl_spick_o;
assign sw2shield_spick_t=qspi2pl_spick_t;
assign pl2qspi_mosi_i=shield2sw_mosi_i;
assign sw2shield_mosi_o=qspi2pl_mosi_o;
assign sw2shield_mosi_t=qspi2pl_mosi_t;
assign pl2qspi_miso_i=shield2sw_miso_i;
assign sw2shield_miso_o=qspi2pl_miso_o;
assign sw2shield_miso_t=qspi2pl_miso_t;
assign pl2qspi_ss_i=shield2sw_ss_i;
assign sw2shield_ss_o=qspi2pl_ss_o;
assign sw2shield_ss_t=qspi2pl_ss_t;
arduino_switch_analog_top analog(
// configuration
.pl2sw_gpio_sel(analog_uart_gpio_sel[11:0]),
// Shield connector side
.shield2sw_data_in(shield2sw_data_in_a5_a0), .sw2shield_data_out(sw2shield_data_out_a5_a0), .sw2shield_tri_out(sw2shield_tri_out_a5_a0), // input, output, output
// .analog_p_in(analog_p_in), .analog_n_in(analog_n_in), // input
// PL Side
.sw2pl_data_in(sw2pl_data_in_a5_a0), .pl2sw_data_o(pl2sw_data_o_a5_a0), .pl2sw_tri_o(pl2sw_tri_o_a5_a0), // output, input, input
// .analog_p_out(analog_p_out), .analog_n_out(analog_n_out), // output
.interrupt_i_in(interrupt_i_in_a5_a0),
.sda_i_in(sda_i_in_a4), .sda_o_in(sda_o_in_a4), .sda_t_in(sda_t_in_a4), // output, input, input
.scl_i_in(scl_i_in_a5), .scl_o_in(scl_o_in_a5), .scl_t_in(scl_t_in_a5) // output, input, input
);
arduino_switch_digital_1_0_top d0_d1_uart(
// configuration
.pl2sw_gpio_sel(analog_uart_gpio_sel[31]), // 0=digital I/O, 1= uart
// Shield connector side
.shield2sw_data_in(shield2sw_data_in_d1_d0), .sw2shield_data_out(sw2shield_data_out_d1_d0), .sw2shield_tri_out(sw2shield_tri_out_d1_d0),
// PL side
.sw2pl_data_in(sw2pl_data_in_d1_d0), .pl2sw_data_o(pl2sw_data_o_d1_d0), .pl2sw_tri_o(pl2sw_tri_o_d1_d0), // output, input, input
.interrupt_i_in(interrupt_i_in_d1_d0),
.rx_i_in(rx_i_in_d0), .tx_o_in(tx_o_in_d1), .tx_t_in(tx_t_in_d1) // output, input, input
);
arduino_switch_digital_13_2_top d2_d13(
// configuration
.gpio_sel1(digital_gpio_sel1), .gpio_sel2(digital_gpio_sel2), .gpio_sel3(digital_gpio_sel3),
// Shield connector side
.shield2sw_data_in(shield2sw_data_in_d13_d2), .sw2shield_data_out(sw2shield_data_out_d13_d2), .sw2shield_tri_out(sw2shield_tri_out_d13_d2), // input, output, output
// PL side
.sw2pl_data_in(sw2pl_data_in_d13_d2), .pl2sw_data_o(pl2sw_data_o_d13_d2), .pl2sw_tri_o(pl2sw_tri_o_d13_d2),
.spick_i_in(spick_i_in_d13), .spick_o_in(spick_o_in_d13), .spick_t_in(spick_t_in_d13),
.miso_i_in(miso_i_in_d12), .miso_o_in(miso_o_in_d12), .miso_t_in(miso_t_in_d12),
.mosi_i_in(mosi_i_in_d11), .mosi_o_in(mosi_o_in_d11), .mosi_t_in(mosi_t_in_d11),
.ss_i_in(ss_i_in_d10), .ss_o_in(ss_o_in_d10), .ss_t_in(ss_t_in_d10),
.interrupt_i_in(interrupt_i_in_d13_d2),
.pwm_o_in(pwm_o_in), .pwm_t_in(pwm_t_in),
.timer_i_in(timer_i_in), .timer_o_in(timer_o_in), .timer_t_in(timer_t_in)
);
endmodule
|
module msg_rx(
input clk_sys,
input [0:7] data_in,
input data_in_ready,
output reg ready,
output reg r,
output reg w,
output reg in,
output reg pa,
output reg ok,
output reg pe,
output reg en,
output reg cpd,
output reg cpr,
output reg cpf,
output reg cps,
output reg [0:7] a1,
output reg [0:15] a2,
output reg [0:15] a3
);
reg [0:7] tcmd;
reg [0:7] ta1;
reg [0:15] ta2;
reg [0:15] ta3;
wire [1:3] arg = tcmd[5:7];
// --- Decoder -----------------------------------------------------------
wire xr, xw, xin, xpa, xok, xpe, xen, xcpd, xcpr, xcpf, xcps;
msg_cmd_dec MSG_CMD_DEC(
.cmd(tcmd),
.r(xr),
.w(xw),
.in(xin),
.pa(xpa),
.ok(xok),
.pe(xpe),
.en(xen),
.cpd(xcpd),
.cpr(xcpr),
.cpf(xcpf),
.cps(xcps)
);
// --- Receiver ----------------------------------------------------------
localparam IDLE = 4'd0;
localparam ARG = 4'd1;
localparam A1 = 4'd2;
localparam A2H = 4'd3;
localparam A2L = 4'd4;
localparam A3H = 4'd5;
localparam A3L = 4'd6;
localparam DONE = 4'd7;
reg [0:2] state = IDLE;
always @ (posedge clk_sys) begin
ready <= 0;
case (state)
IDLE: begin
if (data_in_ready) begin
tcmd <= data_in;
state <= ARG;
end
end
ARG: begin
if (arg[1]) state <= A1;
else if (arg[2]) state <= A2H;
else if (arg[3]) state <= A3H;
else state <= DONE;
end
A1: begin
if (data_in_ready) begin
ta1 <= data_in;
if (arg[2]) state <= A2H;
else if (arg[3]) state <= A3H;
else state <= DONE;
end
end
A2H: begin
if (data_in_ready) begin
ta2[0:7] <= data_in;
state <= A2L;
end
end
A2L: begin
if (data_in_ready) begin
ta2[8:15] <= data_in;
if (arg[3]) state <= A3H;
else state <= DONE;
end
end
A3H: begin
if (data_in_ready) begin
ta3[0:7] <= data_in;
state <= A3L;
end
end
A3L: begin
if (data_in_ready) begin
ta3[8:15] <= data_in;
state <= DONE;
end
end
DONE: begin
{ r, w, in, pa, ok, pe, en } <= { xr, xw, xin, xpa, xok, xpe, xen };
{ cpd, cpr, cpf, cps } <= { xcpd, xcpr, xcpf, xcps };
a1 <= ta1;
a2 <= ta2;
a3 <= ta3;
ready <= 1;
state <= IDLE;
end
endcase
end
endmodule
// vim: tabstop=2 shiftwidth=2 autoindent noexpandtab
|
/////////////////////////////////////////////////////////////
// Created by: Synopsys DC Ultra(TM) in wire load mode
// Version : L-2016.03-SP3
// Date : Thu Nov 10 01:18:35 2016
/////////////////////////////////////////////////////////////
module FPU_Multiplication_Function_W32_EW8_SW23 ( clk, rst, beg_FSM, ack_FSM,
Data_MX, Data_MY, round_mode, overflow_flag, underflow_flag, ready,
final_result_ieee );
input [31:0] Data_MX;
input [31:0] Data_MY;
input [1:0] round_mode;
output [31:0] final_result_ieee;
input clk, rst, beg_FSM, ack_FSM;
output overflow_flag, underflow_flag, ready;
wire FSM_add_overflow_flag, FSM_selector_A, FSM_selector_C,
Exp_module_Overflow_flag_A, n167, n168, n170, n171, n172, n173, n174,
n175, n176, n177, n178, n179, n180, n181, n182, n183, n184, n185,
n186, n187, n188, n189, n190, n191, n192, n193, n194, n195, n196,
n197, n198, n199, n200, n201, n202, n203, n204, n205, n206, n207,
n208, n209, n210, n211, n212, n213, n214, n215, n216, n217, n218,
n219, n220, n221, n222, n223, n224, n225, n226, n227, n228, n229,
n230, n231, n232, n233, n234, n235, n236, n237, n238, n239, n240,
n241, n242, n243, n244, n245, n246, n247, n248, n249, n250, n251,
n252, n253, n254, n255, n256, n257, n258, n259, n260, n261, n262,
n263, n264, n265, n266, n267, n268, n269, n270, n271, n272, n273,
n274, n275, n276, n277, n278, n279, n280, n281, n282, n283, n284,
n285, n286, n287, n288, n289, n290, n291, n292, n293, n294, n295,
n296, n297, n298, n299, n300, n301, n302, n303, n304, n305, n306,
n307, n308, n309, n310, n311, n312, n313, n314, n315, n316, n317,
n318, n319, n320, n321, n322, n323, n324, n325, n326, n327, n328,
n329, n330, n331, n332, n333, n334, n335, n336, n337, n338, n339,
n340, n341, n342, n343, n344, n345, n346, n347, n348, n349, n350,
n351, n352, n353, n354, n355, n356, n357, n358, n359, n360, n361,
n362, n363, n364, n365, n366, n367, n368, n369, n370, n371, n372,
n373, n374, n375, n376, n377, n378, n379, n380, n381, mult_x_19_n779,
mult_x_19_n771, mult_x_19_n770, mult_x_19_n769, mult_x_19_n768,
mult_x_19_n767, mult_x_19_n766, mult_x_19_n765, mult_x_19_n764,
mult_x_19_n763, mult_x_19_n762, mult_x_19_n761, mult_x_19_n760,
mult_x_19_n759, mult_x_19_n758, mult_x_19_n757, mult_x_19_n756,
mult_x_19_n755, mult_x_19_n753, mult_x_19_n752, mult_x_19_n747,
mult_x_19_n746, mult_x_19_n745, mult_x_19_n744, mult_x_19_n743,
mult_x_19_n742, mult_x_19_n741, mult_x_19_n740, mult_x_19_n739,
mult_x_19_n738, mult_x_19_n737, mult_x_19_n736, mult_x_19_n735,
mult_x_19_n734, mult_x_19_n733, mult_x_19_n732, mult_x_19_n731,
mult_x_19_n730, mult_x_19_n729, mult_x_19_n728, mult_x_19_n726,
mult_x_19_n725, mult_x_19_n717, mult_x_19_n716, mult_x_19_n715,
mult_x_19_n714, mult_x_19_n713, mult_x_19_n712, mult_x_19_n711,
mult_x_19_n710, mult_x_19_n709, mult_x_19_n708, mult_x_19_n707,
mult_x_19_n706, mult_x_19_n705, mult_x_19_n704, mult_x_19_n703,
mult_x_19_n702, mult_x_19_n701, mult_x_19_n699, mult_x_19_n698,
mult_x_19_n693, mult_x_19_n692, mult_x_19_n691, mult_x_19_n690,
mult_x_19_n689, mult_x_19_n688, mult_x_19_n687, mult_x_19_n686,
mult_x_19_n685, mult_x_19_n684, mult_x_19_n683, mult_x_19_n682,
mult_x_19_n681, mult_x_19_n680, mult_x_19_n679, mult_x_19_n678,
mult_x_19_n677, mult_x_19_n676, mult_x_19_n675, mult_x_19_n674,
mult_x_19_n672, mult_x_19_n671, mult_x_19_n663, mult_x_19_n662,
mult_x_19_n661, mult_x_19_n660, mult_x_19_n659, mult_x_19_n658,
mult_x_19_n657, mult_x_19_n656, mult_x_19_n655, mult_x_19_n654,
mult_x_19_n653, mult_x_19_n652, mult_x_19_n651, mult_x_19_n650,
mult_x_19_n649, mult_x_19_n648, mult_x_19_n647, mult_x_19_n645,
mult_x_19_n644, mult_x_19_n639, mult_x_19_n638, mult_x_19_n637,
mult_x_19_n636, mult_x_19_n635, mult_x_19_n634, mult_x_19_n633,
mult_x_19_n632, mult_x_19_n631, mult_x_19_n630, mult_x_19_n629,
mult_x_19_n628, mult_x_19_n627, mult_x_19_n626, mult_x_19_n625,
mult_x_19_n624, mult_x_19_n623, mult_x_19_n622, mult_x_19_n621,
mult_x_19_n620, mult_x_19_n618, mult_x_19_n617, mult_x_19_n608,
mult_x_19_n607, mult_x_19_n606, mult_x_19_n605, mult_x_19_n602,
mult_x_19_n601, mult_x_19_n600, mult_x_19_n599, mult_x_19_n597,
mult_x_19_n596, mult_x_19_n595, mult_x_19_n594, mult_x_19_n593,
mult_x_19_n474, mult_x_19_n472, mult_x_19_n471, mult_x_19_n469,
mult_x_19_n468, mult_x_19_n467, mult_x_19_n466, mult_x_19_n464,
mult_x_19_n463, mult_x_19_n462, mult_x_19_n461, mult_x_19_n459,
mult_x_19_n458, mult_x_19_n457, mult_x_19_n454, mult_x_19_n452,
mult_x_19_n451, mult_x_19_n450, mult_x_19_n447, mult_x_19_n445,
mult_x_19_n444, mult_x_19_n443, mult_x_19_n441, mult_x_19_n440,
mult_x_19_n439, mult_x_19_n438, mult_x_19_n437, mult_x_19_n436,
mult_x_19_n435, mult_x_19_n433, mult_x_19_n432, mult_x_19_n431,
mult_x_19_n430, mult_x_19_n429, mult_x_19_n428, mult_x_19_n427,
mult_x_19_n425, mult_x_19_n424, mult_x_19_n423, mult_x_19_n422,
mult_x_19_n421, mult_x_19_n420, mult_x_19_n419, mult_x_19_n417,
mult_x_19_n416, mult_x_19_n415, mult_x_19_n414, mult_x_19_n413,
mult_x_19_n412, mult_x_19_n409, mult_x_19_n407, mult_x_19_n406,
mult_x_19_n405, mult_x_19_n404, mult_x_19_n403, mult_x_19_n402,
mult_x_19_n399, mult_x_19_n397, mult_x_19_n396, mult_x_19_n395,
mult_x_19_n394, mult_x_19_n393, mult_x_19_n392, mult_x_19_n390,
mult_x_19_n389, mult_x_19_n388, mult_x_19_n387, mult_x_19_n386,
mult_x_19_n385, mult_x_19_n384, mult_x_19_n383, mult_x_19_n382,
mult_x_19_n381, mult_x_19_n379, mult_x_19_n378, mult_x_19_n377,
mult_x_19_n376, mult_x_19_n375, mult_x_19_n374, mult_x_19_n373,
mult_x_19_n372, mult_x_19_n371, mult_x_19_n370, mult_x_19_n368,
mult_x_19_n367, mult_x_19_n366, mult_x_19_n365, mult_x_19_n364,
mult_x_19_n363, mult_x_19_n362, mult_x_19_n361, mult_x_19_n360,
mult_x_19_n359, mult_x_19_n357, mult_x_19_n356, mult_x_19_n355,
mult_x_19_n354, mult_x_19_n353, mult_x_19_n352, mult_x_19_n351,
mult_x_19_n350, mult_x_19_n349, mult_x_19_n348, mult_x_19_n346,
mult_x_19_n345, mult_x_19_n344, mult_x_19_n343, mult_x_19_n342,
mult_x_19_n341, mult_x_19_n340, mult_x_19_n339, mult_x_19_n338,
mult_x_19_n337, mult_x_19_n336, mult_x_19_n335, mult_x_19_n334,
mult_x_19_n333, mult_x_19_n332, mult_x_19_n331, mult_x_19_n330,
mult_x_19_n329, mult_x_19_n328, mult_x_19_n327, mult_x_19_n326,
mult_x_19_n325, mult_x_19_n324, mult_x_19_n323, mult_x_19_n322,
mult_x_19_n321, mult_x_19_n320, mult_x_19_n319, mult_x_19_n318,
mult_x_19_n317, mult_x_19_n316, mult_x_19_n315, mult_x_19_n314,
mult_x_19_n313, mult_x_19_n312, mult_x_19_n311, mult_x_19_n310,
mult_x_19_n309, mult_x_19_n308, mult_x_19_n307, mult_x_19_n306,
mult_x_19_n305, mult_x_19_n304, mult_x_19_n303, mult_x_19_n302,
mult_x_19_n301, mult_x_19_n300, mult_x_19_n299, mult_x_19_n298,
mult_x_19_n297, mult_x_19_n296, mult_x_19_n295, mult_x_19_n294,
mult_x_19_n293, mult_x_19_n292, mult_x_19_n291, mult_x_19_n290,
mult_x_19_n289, mult_x_19_n288, mult_x_19_n287, mult_x_19_n286,
mult_x_19_n285, mult_x_19_n284, mult_x_19_n283, mult_x_19_n281,
mult_x_19_n280, mult_x_19_n279, mult_x_19_n278, mult_x_19_n277,
mult_x_19_n276, mult_x_19_n275, mult_x_19_n274, mult_x_19_n273,
mult_x_19_n271, mult_x_19_n270, mult_x_19_n269, mult_x_19_n268,
mult_x_19_n267, mult_x_19_n266, mult_x_19_n265, mult_x_19_n264,
mult_x_19_n263, mult_x_19_n262, mult_x_19_n261, mult_x_19_n260,
mult_x_19_n259, mult_x_19_n258, mult_x_19_n257, mult_x_19_n256,
mult_x_19_n255, mult_x_19_n254, mult_x_19_n252, mult_x_19_n251,
mult_x_19_n250, mult_x_19_n249, mult_x_19_n248, mult_x_19_n247,
mult_x_19_n246, mult_x_19_n245, mult_x_19_n243, mult_x_19_n242,
mult_x_19_n241, mult_x_19_n240, mult_x_19_n239, mult_x_19_n238,
mult_x_19_n237, mult_x_19_n236, mult_x_19_n235, mult_x_19_n234,
mult_x_19_n233, mult_x_19_n232, mult_x_19_n231, mult_x_19_n230,
mult_x_19_n229, mult_x_19_n228, mult_x_19_n226, mult_x_19_n225,
mult_x_19_n224, mult_x_19_n223, mult_x_19_n222, mult_x_19_n221,
mult_x_19_n219, mult_x_19_n218, mult_x_19_n217, mult_x_19_n216,
mult_x_19_n215, mult_x_19_n214, mult_x_19_n213, mult_x_19_n212,
mult_x_19_n211, mult_x_19_n210, mult_x_19_n209, mult_x_19_n208,
mult_x_19_n206, mult_x_19_n204, mult_x_19_n203, mult_x_19_n202,
mult_x_19_n200, mult_x_19_n199, mult_x_19_n198, mult_x_19_n197,
mult_x_19_n196, mult_x_19_n195, mult_x_19_n194, mult_x_19_n193,
mult_x_19_n192, mult_x_19_n191, mult_x_19_n189, mult_x_19_n188,
mult_x_19_n187, mult_x_19_n185, mult_x_19_n184, mult_x_19_n183,
mult_x_19_n182, mult_x_19_n181, mult_x_19_n180,
DP_OP_32J138_122_6543_n33, DP_OP_32J138_122_6543_n22,
DP_OP_32J138_122_6543_n21, DP_OP_32J138_122_6543_n20,
DP_OP_32J138_122_6543_n19, DP_OP_32J138_122_6543_n18,
DP_OP_32J138_122_6543_n17, DP_OP_32J138_122_6543_n16,
DP_OP_32J138_122_6543_n15, DP_OP_32J138_122_6543_n9,
DP_OP_32J138_122_6543_n8, DP_OP_32J138_122_6543_n7,
DP_OP_32J138_122_6543_n6, DP_OP_32J138_122_6543_n5,
DP_OP_32J138_122_6543_n4, DP_OP_32J138_122_6543_n3,
DP_OP_32J138_122_6543_n2, DP_OP_32J138_122_6543_n1, n391, n392, n393,
n394, n395, n396, n397, n398, n399, n400, n401, n402, n403, n404,
n405, n406, n407, n408, n409, n410, n411, n412, n413, n414, n415,
n416, n417, n418, n419, n420, n421, n422, n423, n424, n425, n426,
n427, n428, n429, n430, n431, n432, n433, n434, n435, n436, n437,
n438, n439, n440, n441, n442, n443, n444, n445, n446, n447, n448,
n449, n450, n451, n452, n453, n454, n455, n456, n457, n458, n459,
n460, n461, n462, n463, n464, n465, n466, n467, n468, n469, n470,
n471, n472, n473, n474, n475, n476, n477, n478, n479, n480, n481,
n482, n483, n484, n485, n486, n487, n488, n489, n490, n491, n492,
n493, n494, n495, n496, n497, n498, n499, n500, n501, n502, n503,
n504, n505, n506, n507, n508, n509, n510, n511, n512, n513, n514,
n515, n516, n517, n518, n519, n520, n521, n522, n523, n524, n525,
n526, n527, n528, n529, n530, n531, n532, n533, n534, n535, n536,
n537, n538, n539, n540, n541, n542, n543, n544, n545, n546, n547,
n548, n549, n550, n551, n552, n553, n554, n555, n556, n557, n558,
n559, n560, n561, n562, n563, n564, n565, n566, n567, n568, n569,
n570, n571, n572, n573, n574, n575, n576, n577, n578, n579, n580,
n581, n582, n583, n584, n585, n586, n587, n588, n589, n590, n591,
n592, n593, n594, n595, n596, n597, n598, n599, n600, n601, n602,
n603, n604, n605, n606, n607, n608, n609, n610, n611, n612, n613,
n614, n615, n616, n617, n618, n619, n620, n621, n622, n623, n624,
n625, n626, n627, n628, n629, n630, n631, n632, n633, n634, n635,
n636, n637, n638, n639, n640, n641, n642, n643, n644, n645, n646,
n647, n648, n649, n650, n651, n652, n653, n654, n655, n656, n657,
n658, n659, n660, n661, n662, n663, n664, n665, n666, n667, n668,
n669, n670, n671, n672, n673, n674, n675, n676, n677, n678, n679,
n680, n681, n682, n683, n684, n685, n686, n687, n688, n689, n690,
n691, n692, n693, n694, n695, n696, n697, n698, n699, n700, n701,
n702, n703, n704, n705, n706, n707, n708, n709, n710, n711, n712,
n713, n714, n715, n716, n717, n718, n719, n720, n721, n722, n723,
n724, n725, n726, n727, n728, n729, n730, n731, n732, n733, n734,
n735, n736, n737, n738, n739, n740, n741, n742, n743, n744, n745,
n746, n747, n748, n749, n750, n751, n752, n753, n754, n755, n756,
n757, n758, n759, n760, n761, n762, n763, n764, n765, n766, n767,
n768, n769, n770, n771, n772, n773, n774, n775, n776, n777, n778,
n779, n780, n781, n782, n783, n784, n785, n786, n787, n788, n789,
n790, n791, n792, n793, n794, n795, n796, n797, n798, n799, n800,
n801, n802, n803, n804, n805, n806, n807, n808, n809, n810, n811,
n812, n813, n814, n815, n816, n817, n818, n819, n820, n821, n822,
n823, n824, n825, n826, n827, n828, n829, n830, n831, n832, n833,
n834, n835, n836, n837, n838, n839, n840, n841, n842, n843, n844,
n845, n846, n847, n848, n849, n850, n851, n852, n853, n854, n855,
n856, n857, n858, n859, n860, n861, n862, n863, n864, n865, n866,
n867, n868, n869, n870, n871, n872, n873, n874, n875, n876, n877,
n878, n879, n880, n881, n882, n883, n884, n885, n886, n887, n888,
n889, n890, n891, n892, n893, n894, n895, n896, n897, n898, n899,
n900, n901, n902, n903, n904, n905, n906, n907, n908, n909, n910,
n911, n912, n913, n914, n915, n916, n917, n918, n919, n920, n921,
n922, n923, n924, n925, n926, n927, n928, n929, n930, n931, n932,
n933, n934, n935, n936, n937, n938, n939, n940, n941, n942, n943,
n944, n945, n946, n947, n948, n949, n950, n951, n952, n953, n954,
n955, n956, n957, n958, n959, n960, n961, n962, n963, n964, n965,
n966, n967, n968, n969, n970, n971, n972, n973, n974, n975, n976,
n977, n978, n979, n980, n981, n982, n983, n984, n985, n986, n987,
n988, n989, n990, n991, n992, n993, n994, n995, n996, n997, n998,
n999, n1000, n1001, n1002, n1003, n1004, n1005, n1006, n1007, n1008,
n1009, n1010, n1011, n1012, n1013, n1014, n1015, n1016, n1017, n1018,
n1019, n1020, n1021, n1022, n1023, n1024, n1025, n1026, n1027, n1028,
n1029, n1030, n1031, n1032, n1033, n1034, n1035, n1036, n1037, n1038,
n1039, n1040, n1041, n1042, n1043, n1044, n1045, n1046, n1047, n1048,
n1049, n1050, n1051, n1052, n1053, n1054, n1055, n1056, n1057, n1058,
n1059, n1060, n1061, n1062, n1063, n1064, n1065, n1066, n1067, n1068,
n1069, n1070, n1071, n1072, n1073, n1074, n1075, n1076, n1077, n1078,
n1079, n1080, n1081, n1082, n1083, n1084, n1085, n1086, n1087, n1088,
n1089, n1090, n1091, n1092, n1093, n1094, n1095, n1096, n1097, n1098,
n1099, n1100, n1101, n1102, n1103, n1104, n1105, n1106, n1107, n1108,
n1109, n1110, n1111, n1112, n1113, n1114, n1115, n1116, n1117, n1118,
n1119, n1120, n1121, n1122, n1123, n1124, n1125, n1126, n1127, n1128,
n1129, n1130, n1131, n1132, n1133, n1134, n1135, n1136, n1137, n1138,
n1139, n1140, n1141, n1142, n1143, n1144, n1145, n1146, n1147, n1148,
n1149, n1150, n1151, n1152, n1153, n1154, n1155, n1156, n1157, n1158,
n1159, n1160, n1161, n1162, n1163, n1164, n1165, n1166, n1167, n1168,
n1169, n1170, n1171, n1172, n1173, n1174, n1175, n1176, n1177, n1178,
n1179, n1180, n1181, n1182, n1183, n1184, n1185, n1186, n1187, n1188,
n1189, n1190, n1191, n1192, n1193, n1194, n1195, n1196, n1197, n1198,
n1199, n1200, n1201, n1202, n1203, n1204, n1205, n1206, n1207, n1208,
n1209, n1210, n1211, n1212, n1213, n1214, n1215, n1216, n1217, n1218,
n1219, n1220, n1221, n1222, n1223, n1224, n1225, n1226, n1227, n1228,
n1229, n1230, n1231, n1232, n1233, n1234, n1235, n1236, n1237, n1238,
n1239, n1240, n1241, n1242, n1243, n1244, n1245, n1246, n1247, n1248,
n1249, n1250, n1251, n1252, n1253, n1254, n1255, n1256, n1257, n1258,
n1259, n1260, n1261, n1262, n1263, n1264, n1265, n1266, n1267, n1268,
n1269, n1270, n1271, n1272, n1273, n1274, n1275, n1276, n1277, n1278,
n1279, n1280, n1281, n1282, n1283, n1284, n1285, n1286, n1287, n1288,
n1289, n1290, n1291, n1292, n1293, n1294, n1295, n1296, n1297, n1298,
n1299, n1300, n1301, n1302, n1303, n1304, n1305, n1306, n1307, n1308,
n1309, n1310, n1311, n1312, n1313, n1314, n1315, n1316, n1317, n1318,
n1319, n1320, n1321, n1322, n1323, n1324, n1325, n1326, n1327, n1328,
n1329, n1330, n1331, n1332, n1333, n1334, n1335, n1336, n1337, n1338,
n1339, n1340, n1341, n1342, n1343, n1344, n1345, n1346, n1347, n1348,
n1349, n1350, n1351, n1352, n1353, n1354, n1355, n1356, n1357, n1358,
n1359, n1360, n1361, n1362, n1363, n1364, n1365, n1366, n1367, n1368,
n1369, n1370, n1371, n1372, n1373, n1374, n1375, n1376, n1377, n1378,
n1379, n1380, n1381, n1382, n1383, n1384, n1385, n1386, n1387, n1388,
n1389, n1390, n1391, n1392, n1393, n1394, n1395, n1396, n1397, n1398,
n1399, n1400, n1401, n1402, n1403, n1404, n1405, n1406, n1407, n1408,
n1409, n1410, n1411, n1412, n1413, n1414, n1415, n1416, n1417, n1418,
n1419, n1420, n1421, n1422, n1423, n1424, n1425, n1426, n1427, n1428,
n1429, n1430, n1431, n1432, n1433, n1434, n1435, n1436, n1437, n1438,
n1439, n1440, n1441, n1442, n1443, n1444, n1445, n1446, n1447, n1448,
n1449, n1450, n1451, n1452, n1453, n1454, n1455, n1456, n1457, n1458,
n1459, n1460, n1461, n1462, n1463, n1464, n1465, n1466, n1467, n1468,
n1469, n1470, n1471, n1472, n1473, n1474, n1475, n1476, n1477, n1478,
n1479, n1480, n1481, n1482, n1483, n1484, n1485, n1486, n1487, n1488,
n1489, n1490, n1491, n1492, n1493, n1494, n1495, n1496, n1497, n1498,
n1499, n1500, n1501, n1502, n1503, n1504, n1505, n1506, n1507, n1508,
n1509, n1510, n1511, n1512, n1513, n1514, n1515, n1516, n1517, n1518,
n1519, n1520, n1521, n1522, n1523, n1524, n1525, n1526, n1527, n1528,
n1529, n1530, n1531, n1532, n1533, n1534, n1535, n1536, n1537, n1538,
n1539, n1540, n1541, n1542, n1543, n1544, n1545, n1546, n1547, n1548,
n1549, n1550, n1551, n1552, n1553, n1554, n1555, n1556, n1557, n1558,
n1559, n1560, n1561, n1562, n1563, n1564, n1565, n1566, n1567, n1568,
n1569, n1570, n1571, n1572, n1573, n1574, n1575, n1576, n1577, n1578,
n1579, n1580, n1581, n1582, n1583, n1584, n1585, n1586, n1587, n1588,
n1589, n1590, n1591, n1592, n1593, n1594, n1595, n1596, n1597, n1598,
n1599, n1600, n1601, n1602, n1603, n1604, n1605, n1606, n1607, n1608,
n1609, n1610, n1611, n1612, n1613, n1614, n1615, n1616, n1617, n1618,
n1619, n1620, n1621, n1622, n1623, n1624, n1625, n1626, n1627, n1628,
n1629, n1630, n1631, n1632, n1633, n1634, n1635, n1636, n1637, n1638,
n1639, n1640, n1641, n1642, n1643, n1644, n1645, n1646, n1647, n1648,
n1649, n1650, n1651, n1652, n1653, n1654, n1655, n1656, n1657, n1658,
n1659, n1660, n1661, n1662, n1663, n1664, n1665, n1666, n1667, n1668,
n1669, n1670, n1671, n1672, n1673, n1674, n1675, n1676, n1677, n1678,
n1679, n1680, n1681, n1682, n1683, n1684, n1685, n1686, n1687, n1688,
n1689, n1690, n1691, n1692, n1693, n1694, n1695, n1696, n1697, n1698,
n1699, n1700, n1701, n1702, n1703, n1704, n1705, n1706, n1707, n1708,
n1709, n1710, n1711, n1712, n1713, n1714, n1715, n1716, n1717, n1718,
n1719, n1720, n1721, n1722, n1723, n1724, n1725, n1726, n1727, n1728,
n1729, n1730, n1731, n1732, n1733, n1734, n1735, n1736, n1737, n1738,
n1739, n1740, n1741, n1742, n1743, n1744, n1745, n1746, n1747, n1748,
n1749, n1750, n1751, n1752, n1753, n1754, n1755, n1756, n1757, n1758,
n1759, n1760, n1761, n1762, n1763, n1764, n1765, n1766, n1767, n1768,
n1769, n1770, n1771, n1772, n1773, n1774, n1775, n1776, n1777, n1778,
n1779, n1780, n1781, n1782, n1783, n1784, n1785, n1786, n1787, n1788,
n1789, n1790, n1791, n1792, n1793, n1794, n1795, n1796, n1797, n1798,
n1799, n1800, n1801, n1802, n1803, n1804, n1805, n1806, n1807, n1808,
n1809, n1810, n1811, n1812, n1813, n1814, n1815, n1816, n1817, n1818,
n1819, n1820, n1821, n1822, n1823, n1824, n1825, n1826, n1827, n1828,
n1829, n1830, n1831, n1832, n1833, n1834, n1835, n1836, n1837, n1838,
n1839, n1840, n1841, n1842, n1843, n1844, n1845, n1846, n1847, n1848,
n1849, n1850, n1851, n1852, n1853, n1854, n1855, n1856, n1857, n1858,
n1859, n1860, n1861, n1862, n1863, n1864, n1865, n1866, n1867, n1868,
n1869, n1870, n1871, n1872, n1873, n1874, n1875, n1876, n1877, n1878,
n1879, n1880, n1881, n1882, n1883, n1884, n1885, n1886, n1887, n1888,
n1889, n1890, n1891, n1893, n1894, n1895, n1896, n1897, n1898, n1899,
n1900, n1901, n1902, n1903, n1904, n1905, n1906, n1907;
wire [47:0] P_Sgf;
wire [1:0] FSM_selector_B;
wire [31:0] Op_MX;
wire [31:0] Op_MY;
wire [8:0] exp_oper_result;
wire [8:0] S_Oper_A_exp;
wire [23:0] Add_result;
wire [23:0] Sgf_normalized_result;
wire [3:0] FS_Module_state_reg;
wire [8:0] Exp_module_Data_S;
CMPR42X1TS mult_x_19_U292 ( .A(mult_x_19_n471), .B(mult_x_19_n747), .C(
mult_x_19_n474), .D(mult_x_19_n771), .ICI(mult_x_19_n472), .S(
mult_x_19_n469), .ICO(mult_x_19_n467), .CO(mult_x_19_n468) );
CMPR42X1TS mult_x_19_U290 ( .A(mult_x_19_n746), .B(mult_x_19_n466), .C(
mult_x_19_n467), .D(mult_x_19_n770), .ICI(mult_x_19_n468), .S(
mult_x_19_n464), .ICO(mult_x_19_n462), .CO(mult_x_19_n463) );
CMPR42X1TS mult_x_19_U288 ( .A(mult_x_19_n745), .B(mult_x_19_n461), .C(
mult_x_19_n462), .D(mult_x_19_n769), .ICI(mult_x_19_n463), .S(
mult_x_19_n459), .ICO(mult_x_19_n457), .CO(mult_x_19_n458) );
CMPR42X1TS mult_x_19_U285 ( .A(mult_x_19_n744), .B(mult_x_19_n454), .C(
mult_x_19_n457), .D(mult_x_19_n768), .ICI(mult_x_19_n458), .S(
mult_x_19_n452), .ICO(mult_x_19_n450), .CO(mult_x_19_n451) );
CMPR42X1TS mult_x_19_U282 ( .A(mult_x_19_n743), .B(mult_x_19_n447), .C(
mult_x_19_n450), .D(mult_x_19_n767), .ICI(mult_x_19_n451), .S(
mult_x_19_n445), .ICO(mult_x_19_n443), .CO(mult_x_19_n444) );
CMPR42X1TS mult_x_19_U279 ( .A(mult_x_19_n742), .B(mult_x_19_n440), .C(
mult_x_19_n443), .D(mult_x_19_n766), .ICI(mult_x_19_n444), .S(
mult_x_19_n438), .ICO(mult_x_19_n436), .CO(mult_x_19_n437) );
CMPR42X1TS mult_x_19_U277 ( .A(mult_x_19_n435), .B(mult_x_19_n693), .C(
mult_x_19_n441), .D(mult_x_19_n717), .ICI(mult_x_19_n439), .S(
mult_x_19_n433), .ICO(mult_x_19_n431), .CO(mult_x_19_n432) );
CMPR42X1TS mult_x_19_U276 ( .A(mult_x_19_n741), .B(mult_x_19_n433), .C(
mult_x_19_n436), .D(mult_x_19_n765), .ICI(mult_x_19_n437), .S(
mult_x_19_n430), .ICO(mult_x_19_n428), .CO(mult_x_19_n429) );
CMPR42X1TS mult_x_19_U274 ( .A(mult_x_19_n692), .B(mult_x_19_n427), .C(
mult_x_19_n431), .D(mult_x_19_n716), .ICI(mult_x_19_n432), .S(
mult_x_19_n425), .ICO(mult_x_19_n423), .CO(mult_x_19_n424) );
CMPR42X1TS mult_x_19_U273 ( .A(mult_x_19_n740), .B(mult_x_19_n425), .C(
mult_x_19_n428), .D(mult_x_19_n764), .ICI(mult_x_19_n429), .S(
mult_x_19_n422), .ICO(mult_x_19_n420), .CO(mult_x_19_n421) );
CMPR42X1TS mult_x_19_U271 ( .A(mult_x_19_n691), .B(mult_x_19_n419), .C(
mult_x_19_n423), .D(mult_x_19_n715), .ICI(mult_x_19_n424), .S(
mult_x_19_n417), .ICO(mult_x_19_n415), .CO(mult_x_19_n416) );
CMPR42X1TS mult_x_19_U270 ( .A(mult_x_19_n739), .B(mult_x_19_n417), .C(
mult_x_19_n420), .D(mult_x_19_n763), .ICI(mult_x_19_n421), .S(
mult_x_19_n414), .ICO(mult_x_19_n412), .CO(mult_x_19_n413) );
CMPR42X1TS mult_x_19_U267 ( .A(mult_x_19_n690), .B(mult_x_19_n409), .C(
mult_x_19_n415), .D(mult_x_19_n714), .ICI(mult_x_19_n416), .S(
mult_x_19_n407), .ICO(mult_x_19_n405), .CO(mult_x_19_n406) );
CMPR42X1TS mult_x_19_U266 ( .A(mult_x_19_n738), .B(mult_x_19_n407), .C(
mult_x_19_n412), .D(mult_x_19_n762), .ICI(mult_x_19_n413), .S(
mult_x_19_n404), .ICO(mult_x_19_n402), .CO(mult_x_19_n403) );
CMPR42X1TS mult_x_19_U263 ( .A(mult_x_19_n689), .B(mult_x_19_n399), .C(
mult_x_19_n405), .D(mult_x_19_n713), .ICI(mult_x_19_n406), .S(
mult_x_19_n397), .ICO(mult_x_19_n395), .CO(mult_x_19_n396) );
CMPR42X1TS mult_x_19_U262 ( .A(mult_x_19_n397), .B(mult_x_19_n737), .C(
mult_x_19_n402), .D(mult_x_19_n761), .ICI(mult_x_19_n403), .S(
mult_x_19_n394), .ICO(mult_x_19_n392), .CO(mult_x_19_n393) );
CMPR42X1TS mult_x_19_U259 ( .A(mult_x_19_n688), .B(mult_x_19_n389), .C(
mult_x_19_n395), .D(mult_x_19_n712), .ICI(mult_x_19_n396), .S(
mult_x_19_n387), .ICO(mult_x_19_n385), .CO(mult_x_19_n386) );
CMPR42X1TS mult_x_19_U258 ( .A(mult_x_19_n387), .B(mult_x_19_n736), .C(
mult_x_19_n392), .D(mult_x_19_n760), .ICI(mult_x_19_n393), .S(
mult_x_19_n384), .ICO(mult_x_19_n382), .CO(mult_x_19_n383) );
CMPR42X1TS mult_x_19_U256 ( .A(mult_x_19_n381), .B(mult_x_19_n639), .C(
mult_x_19_n390), .D(mult_x_19_n663), .ICI(mult_x_19_n388), .S(
mult_x_19_n379), .ICO(mult_x_19_n377), .CO(mult_x_19_n378) );
CMPR42X1TS mult_x_19_U255 ( .A(mult_x_19_n687), .B(mult_x_19_n379), .C(
mult_x_19_n385), .D(mult_x_19_n711), .ICI(mult_x_19_n386), .S(
mult_x_19_n376), .ICO(mult_x_19_n374), .CO(mult_x_19_n375) );
CMPR42X1TS mult_x_19_U254 ( .A(mult_x_19_n376), .B(mult_x_19_n735), .C(
mult_x_19_n382), .D(mult_x_19_n759), .ICI(mult_x_19_n383), .S(
mult_x_19_n373), .ICO(mult_x_19_n371), .CO(mult_x_19_n372) );
CMPR42X1TS mult_x_19_U252 ( .A(mult_x_19_n370), .B(mult_x_19_n638), .C(
mult_x_19_n377), .D(mult_x_19_n662), .ICI(mult_x_19_n378), .S(
mult_x_19_n368), .ICO(mult_x_19_n366), .CO(mult_x_19_n367) );
CMPR42X1TS mult_x_19_U251 ( .A(mult_x_19_n686), .B(mult_x_19_n368), .C(
mult_x_19_n374), .D(mult_x_19_n710), .ICI(mult_x_19_n375), .S(
mult_x_19_n365), .ICO(mult_x_19_n363), .CO(mult_x_19_n364) );
CMPR42X1TS mult_x_19_U250 ( .A(mult_x_19_n365), .B(mult_x_19_n734), .C(
mult_x_19_n371), .D(mult_x_19_n758), .ICI(mult_x_19_n372), .S(
mult_x_19_n362), .ICO(mult_x_19_n360), .CO(mult_x_19_n361) );
CMPR42X1TS mult_x_19_U248 ( .A(mult_x_19_n359), .B(mult_x_19_n637), .C(
mult_x_19_n366), .D(mult_x_19_n661), .ICI(mult_x_19_n367), .S(
mult_x_19_n357), .ICO(mult_x_19_n355), .CO(mult_x_19_n356) );
CMPR42X1TS mult_x_19_U247 ( .A(mult_x_19_n685), .B(mult_x_19_n357), .C(
mult_x_19_n363), .D(mult_x_19_n709), .ICI(mult_x_19_n364), .S(
mult_x_19_n354), .ICO(mult_x_19_n352), .CO(mult_x_19_n353) );
CMPR42X1TS mult_x_19_U246 ( .A(mult_x_19_n354), .B(mult_x_19_n733), .C(
mult_x_19_n360), .D(mult_x_19_n757), .ICI(mult_x_19_n361), .S(
mult_x_19_n351), .ICO(mult_x_19_n349), .CO(mult_x_19_n350) );
CMPR42X1TS mult_x_19_U244 ( .A(mult_x_19_n348), .B(mult_x_19_n636), .C(
mult_x_19_n355), .D(mult_x_19_n660), .ICI(mult_x_19_n356), .S(
mult_x_19_n346), .ICO(mult_x_19_n344), .CO(mult_x_19_n345) );
CMPR42X1TS mult_x_19_U243 ( .A(mult_x_19_n684), .B(mult_x_19_n346), .C(
mult_x_19_n352), .D(mult_x_19_n708), .ICI(mult_x_19_n353), .S(
mult_x_19_n343), .ICO(mult_x_19_n341), .CO(mult_x_19_n342) );
CMPR42X1TS mult_x_19_U242 ( .A(mult_x_19_n343), .B(mult_x_19_n732), .C(
mult_x_19_n349), .D(mult_x_19_n756), .ICI(mult_x_19_n350), .S(
mult_x_19_n340), .ICO(mult_x_19_n338), .CO(mult_x_19_n339) );
CMPR42X1TS mult_x_19_U240 ( .A(mult_x_19_n337), .B(mult_x_19_n635), .C(
mult_x_19_n344), .D(mult_x_19_n659), .ICI(mult_x_19_n345), .S(
mult_x_19_n335), .ICO(mult_x_19_n333), .CO(mult_x_19_n334) );
CMPR42X1TS mult_x_19_U239 ( .A(mult_x_19_n335), .B(mult_x_19_n683), .C(
mult_x_19_n341), .D(mult_x_19_n707), .ICI(mult_x_19_n342), .S(
mult_x_19_n332), .ICO(mult_x_19_n330), .CO(mult_x_19_n331) );
CMPR42X1TS mult_x_19_U238 ( .A(mult_x_19_n332), .B(mult_x_19_n731), .C(
mult_x_19_n338), .D(mult_x_19_n755), .ICI(mult_x_19_n779), .S(
mult_x_19_n329), .ICO(mult_x_19_n327), .CO(mult_x_19_n328) );
CMPR42X1TS mult_x_19_U236 ( .A(mult_x_19_n326), .B(mult_x_19_n336), .C(
mult_x_19_n634), .D(mult_x_19_n333), .ICI(mult_x_19_n658), .S(
mult_x_19_n324), .ICO(mult_x_19_n322), .CO(mult_x_19_n323) );
CMPR42X1TS mult_x_19_U235 ( .A(mult_x_19_n324), .B(mult_x_19_n334), .C(
mult_x_19_n682), .D(mult_x_19_n330), .ICI(mult_x_19_n706), .S(
mult_x_19_n321), .ICO(mult_x_19_n319), .CO(mult_x_19_n320) );
CMPR42X1TS mult_x_19_U234 ( .A(mult_x_19_n331), .B(mult_x_19_n321), .C(
mult_x_19_n730), .D(mult_x_19_n327), .ICI(mult_x_19_n328), .S(
mult_x_19_n318), .ICO(mult_x_19_n316), .CO(mult_x_19_n317) );
CMPR42X1TS mult_x_19_U232 ( .A(mult_x_19_n325), .B(mult_x_19_n315), .C(
mult_x_19_n322), .D(mult_x_19_n633), .ICI(mult_x_19_n323), .S(
mult_x_19_n313), .ICO(mult_x_19_n311), .CO(mult_x_19_n312) );
CMPR42X1TS mult_x_19_U231 ( .A(mult_x_19_n657), .B(mult_x_19_n313), .C(
mult_x_19_n319), .D(mult_x_19_n681), .ICI(mult_x_19_n320), .S(
mult_x_19_n310), .ICO(mult_x_19_n308), .CO(mult_x_19_n309) );
CMPR42X1TS mult_x_19_U230 ( .A(mult_x_19_n705), .B(mult_x_19_n310), .C(
mult_x_19_n316), .D(mult_x_19_n729), .ICI(mult_x_19_n753), .S(
mult_x_19_n307), .ICO(mult_x_19_n305), .CO(mult_x_19_n306) );
CMPR42X1TS mult_x_19_U228 ( .A(mult_x_19_n314), .B(mult_x_19_n304), .C(
mult_x_19_n311), .D(mult_x_19_n632), .ICI(mult_x_19_n312), .S(
mult_x_19_n302), .ICO(mult_x_19_n300), .CO(mult_x_19_n301) );
CMPR42X1TS mult_x_19_U227 ( .A(mult_x_19_n656), .B(mult_x_19_n302), .C(
mult_x_19_n308), .D(mult_x_19_n680), .ICI(mult_x_19_n309), .S(
mult_x_19_n299), .ICO(mult_x_19_n297), .CO(mult_x_19_n298) );
CMPR42X1TS mult_x_19_U226 ( .A(mult_x_19_n704), .B(mult_x_19_n299), .C(
mult_x_19_n305), .D(mult_x_19_n728), .ICI(mult_x_19_n752), .S(
mult_x_19_n296), .ICO(mult_x_19_n294), .CO(mult_x_19_n295) );
CMPR42X1TS mult_x_19_U224 ( .A(mult_x_19_n293), .B(mult_x_19_n608), .C(
mult_x_19_n303), .D(mult_x_19_n300), .ICI(mult_x_19_n631), .S(
mult_x_19_n291), .ICO(mult_x_19_n289), .CO(mult_x_19_n290) );
CMPR42X1TS mult_x_19_U223 ( .A(mult_x_19_n291), .B(mult_x_19_n301), .C(
mult_x_19_n655), .D(mult_x_19_n297), .ICI(mult_x_19_n679), .S(
mult_x_19_n288), .ICO(mult_x_19_n286), .CO(mult_x_19_n287) );
CMPR42X1TS mult_x_19_U222 ( .A(mult_x_19_n288), .B(mult_x_19_n298), .C(
mult_x_19_n703), .D(mult_x_19_n294), .ICI(mult_x_19_n295), .S(
mult_x_19_n285), .ICO(mult_x_19_n283), .CO(mult_x_19_n284) );
CMPR42X1TS mult_x_19_U220 ( .A(n517), .B(mult_x_19_n292), .C(mult_x_19_n289),
.D(mult_x_19_n607), .ICI(mult_x_19_n630), .S(mult_x_19_n281), .ICO(
mult_x_19_n279), .CO(mult_x_19_n280) );
CMPR42X1TS mult_x_19_U219 ( .A(mult_x_19_n290), .B(mult_x_19_n281), .C(
mult_x_19_n286), .D(mult_x_19_n654), .ICI(mult_x_19_n678), .S(
mult_x_19_n278), .ICO(mult_x_19_n276), .CO(mult_x_19_n277) );
CMPR42X1TS mult_x_19_U218 ( .A(mult_x_19_n287), .B(mult_x_19_n278), .C(
mult_x_19_n283), .D(mult_x_19_n702), .ICI(mult_x_19_n726), .S(
mult_x_19_n275), .ICO(mult_x_19_n273), .CO(mult_x_19_n274) );
CMPR42X1TS mult_x_19_U216 ( .A(Op_MY[6]), .B(n1850), .C(mult_x_19_n279), .D(
mult_x_19_n606), .ICI(mult_x_19_n280), .S(mult_x_19_n271), .ICO(
mult_x_19_n269), .CO(mult_x_19_n270) );
CMPR42X1TS mult_x_19_U215 ( .A(mult_x_19_n629), .B(mult_x_19_n271), .C(
mult_x_19_n276), .D(mult_x_19_n653), .ICI(mult_x_19_n277), .S(
mult_x_19_n268), .ICO(mult_x_19_n266), .CO(mult_x_19_n267) );
CMPR42X1TS mult_x_19_U214 ( .A(mult_x_19_n677), .B(mult_x_19_n268), .C(
mult_x_19_n273), .D(mult_x_19_n701), .ICI(mult_x_19_n725), .S(
mult_x_19_n265), .ICO(mult_x_19_n263), .CO(mult_x_19_n264) );
CMPR42X1TS mult_x_19_U213 ( .A(n1882), .B(Op_MY[8]), .C(Op_MY[7]), .D(
mult_x_19_n269), .ICI(mult_x_19_n605), .S(mult_x_19_n262), .ICO(
mult_x_19_n260), .CO(mult_x_19_n261) );
CMPR42X1TS mult_x_19_U212 ( .A(mult_x_19_n262), .B(mult_x_19_n270), .C(
mult_x_19_n628), .D(mult_x_19_n266), .ICI(mult_x_19_n652), .S(
mult_x_19_n259), .ICO(mult_x_19_n257), .CO(mult_x_19_n258) );
CMPR42X1TS mult_x_19_U211 ( .A(mult_x_19_n259), .B(mult_x_19_n267), .C(
mult_x_19_n676), .D(mult_x_19_n263), .ICI(mult_x_19_n264), .S(
mult_x_19_n256), .ICO(mult_x_19_n254), .CO(mult_x_19_n255) );
CMPR42X1TS mult_x_19_U208 ( .A(mult_x_19_n261), .B(mult_x_19_n252), .C(
mult_x_19_n257), .D(mult_x_19_n627), .ICI(mult_x_19_n651), .S(
mult_x_19_n250), .ICO(mult_x_19_n248), .CO(mult_x_19_n249) );
CMPR42X1TS mult_x_19_U207 ( .A(mult_x_19_n258), .B(mult_x_19_n250), .C(
mult_x_19_n254), .D(mult_x_19_n675), .ICI(mult_x_19_n699), .S(
mult_x_19_n247), .ICO(mult_x_19_n245), .CO(mult_x_19_n246) );
CMPR42X1TS mult_x_19_U204 ( .A(mult_x_19_n251), .B(mult_x_19_n243), .C(
mult_x_19_n248), .D(mult_x_19_n626), .ICI(mult_x_19_n249), .S(
mult_x_19_n241), .ICO(mult_x_19_n239), .CO(mult_x_19_n240) );
CMPR42X1TS mult_x_19_U203 ( .A(mult_x_19_n650), .B(mult_x_19_n241), .C(
mult_x_19_n245), .D(mult_x_19_n674), .ICI(mult_x_19_n698), .S(
mult_x_19_n238), .ICO(mult_x_19_n236), .CO(mult_x_19_n237) );
CMPR42X1TS mult_x_19_U201 ( .A(mult_x_19_n235), .B(mult_x_19_n242), .C(
mult_x_19_n602), .D(mult_x_19_n239), .ICI(mult_x_19_n625), .S(
mult_x_19_n233), .ICO(mult_x_19_n231), .CO(mult_x_19_n232) );
CMPR42X1TS mult_x_19_U200 ( .A(mult_x_19_n233), .B(mult_x_19_n240), .C(
mult_x_19_n649), .D(mult_x_19_n236), .ICI(mult_x_19_n237), .S(
mult_x_19_n230), .ICO(mult_x_19_n228), .CO(mult_x_19_n229) );
CMPR42X1TS mult_x_19_U198 ( .A(n514), .B(mult_x_19_n234), .C(mult_x_19_n231),
.D(mult_x_19_n601), .ICI(mult_x_19_n624), .S(mult_x_19_n226), .ICO(
mult_x_19_n224), .CO(mult_x_19_n225) );
CMPR42X1TS mult_x_19_U197 ( .A(mult_x_19_n232), .B(mult_x_19_n226), .C(
mult_x_19_n228), .D(mult_x_19_n648), .ICI(mult_x_19_n672), .S(
mult_x_19_n223), .ICO(mult_x_19_n221), .CO(mult_x_19_n222) );
CMPR42X1TS mult_x_19_U195 ( .A(Op_MY[12]), .B(n1853), .C(mult_x_19_n224),
.D(mult_x_19_n600), .ICI(mult_x_19_n225), .S(mult_x_19_n219), .ICO(
mult_x_19_n217), .CO(mult_x_19_n218) );
CMPR42X1TS mult_x_19_U194 ( .A(mult_x_19_n623), .B(mult_x_19_n219), .C(
mult_x_19_n221), .D(mult_x_19_n647), .ICI(mult_x_19_n671), .S(
mult_x_19_n216), .ICO(mult_x_19_n214), .CO(mult_x_19_n215) );
CMPR42X1TS mult_x_19_U193 ( .A(n1881), .B(Op_MY[13]), .C(Op_MY[14]), .D(
mult_x_19_n217), .ICI(mult_x_19_n599), .S(mult_x_19_n213), .ICO(
mult_x_19_n211), .CO(mult_x_19_n212) );
CMPR42X1TS mult_x_19_U192 ( .A(mult_x_19_n213), .B(mult_x_19_n218), .C(
mult_x_19_n622), .D(mult_x_19_n214), .ICI(mult_x_19_n215), .S(
mult_x_19_n210), .ICO(mult_x_19_n208), .CO(mult_x_19_n209) );
CMPR42X1TS mult_x_19_U189 ( .A(mult_x_19_n212), .B(mult_x_19_n206), .C(
mult_x_19_n208), .D(mult_x_19_n621), .ICI(mult_x_19_n645), .S(
mult_x_19_n204), .ICO(mult_x_19_n202), .CO(mult_x_19_n203) );
CMPR42X1TS mult_x_19_U186 ( .A(mult_x_19_n597), .B(mult_x_19_n200), .C(
mult_x_19_n202), .D(mult_x_19_n620), .ICI(mult_x_19_n644), .S(
mult_x_19_n198), .ICO(mult_x_19_n196), .CO(mult_x_19_n197) );
CMPR42X1TS mult_x_19_U184 ( .A(mult_x_19_n195), .B(mult_x_19_n199), .C(
mult_x_19_n596), .D(mult_x_19_n196), .ICI(mult_x_19_n197), .S(
mult_x_19_n193), .ICO(mult_x_19_n191), .CO(mult_x_19_n192) );
CMPR42X1TS mult_x_19_U182 ( .A(n480), .B(mult_x_19_n194), .C(mult_x_19_n191),
.D(mult_x_19_n595), .ICI(mult_x_19_n618), .S(mult_x_19_n189), .ICO(
mult_x_19_n187), .CO(mult_x_19_n188) );
CMPR42X1TS mult_x_19_U180 ( .A(Op_MY[19]), .B(n480), .C(mult_x_19_n187), .D(
mult_x_19_n594), .ICI(mult_x_19_n617), .S(mult_x_19_n185), .ICO(
mult_x_19_n183), .CO(mult_x_19_n184) );
CMPR42X1TS mult_x_19_U179 ( .A(n1880), .B(Op_MY[18]), .C(Op_MY[20]), .D(
mult_x_19_n183), .ICI(mult_x_19_n593), .S(mult_x_19_n182), .ICO(
mult_x_19_n180), .CO(mult_x_19_n181) );
DFFRX2TS FS_Module_state_reg_reg_0_ ( .D(n379), .CK(n1902), .RN(n1887), .Q(
FS_Module_state_reg[0]), .QN(n1862) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_31_ ( .D(n168),
.CK(n481), .RN(n1863), .Q(final_result_ieee[31]), .QN(n1861) );
DFFRX2TS FS_Module_state_reg_reg_3_ ( .D(n380), .CK(n1905), .RN(n167), .Q(
FS_Module_state_reg[3]), .QN(n1860) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_2_ ( .D(n307), .CK(n406), .RN(n1873),
.Q(Add_result[2]), .QN(n1859) );
DFFRXLTS Barrel_Shifter_module_Output_Reg_Q_reg_23_ ( .D(n310), .CK(n1891),
.RN(n1868), .Q(Sgf_normalized_result[23]), .QN(n1858) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_8_ ( .D(n352), .CK(n1901), .RN(
n1876), .Q(Op_MX[8]), .QN(n1849) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_14_ ( .D(n358), .CK(n1903), .RN(
n1877), .Q(Op_MX[14]), .QN(n1848) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_20_ ( .D(n364), .CK(n406), .RN(
n1877), .Q(Op_MX[20]), .QN(n1847) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_2_ ( .D(n240), .CK(n1901), .RN(n1886),
.QN(n1843) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_24_ ( .D(n262), .CK(n1899), .RN(n1884),
.Q(P_Sgf[24]), .QN(n1842) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_25_ ( .D(n263), .CK(n1889), .RN(n1884),
.Q(P_Sgf[25]), .QN(n1841) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_26_ ( .D(n264), .CK(n1898), .RN(n1884),
.Q(P_Sgf[26]), .QN(n1840) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_27_ ( .D(n265), .CK(n1896), .RN(n1884),
.Q(P_Sgf[27]), .QN(n1839) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_28_ ( .D(n266), .CK(n1889), .RN(n1884),
.Q(P_Sgf[28]), .QN(n1838) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_30_ ( .D(n268), .CK(n1893), .RN(n1883),
.Q(P_Sgf[30]), .QN(n1836) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_31_ ( .D(n269), .CK(n406), .RN(n1883),
.Q(P_Sgf[31]), .QN(n1835) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_32_ ( .D(n270), .CK(n1895), .RN(n1883),
.Q(P_Sgf[32]), .QN(n1834) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_33_ ( .D(n271), .CK(n1894), .RN(n1883),
.Q(P_Sgf[33]), .QN(n1833) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_34_ ( .D(n272), .CK(n1898), .RN(n1883),
.Q(P_Sgf[34]), .QN(n1832) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_35_ ( .D(n273), .CK(n1889), .RN(n1883),
.Q(P_Sgf[35]), .QN(n1831) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_36_ ( .D(n274), .CK(n407), .RN(n1883),
.Q(P_Sgf[36]), .QN(n1830) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_37_ ( .D(n275), .CK(n1899), .RN(n1883),
.Q(P_Sgf[37]), .QN(n1829) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_38_ ( .D(n276), .CK(n1898), .RN(n1883),
.Q(P_Sgf[38]), .QN(n1828) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_39_ ( .D(n277), .CK(n1899), .RN(n1883),
.Q(P_Sgf[39]), .QN(n1827) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_40_ ( .D(n278), .CK(n1897), .RN(n1887),
.Q(P_Sgf[40]), .QN(n1826) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_41_ ( .D(n279), .CK(n1895), .RN(n1887),
.Q(P_Sgf[41]), .QN(n1825) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_42_ ( .D(n280), .CK(n407), .RN(n1887),
.Q(P_Sgf[42]), .QN(n1824) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_43_ ( .D(n281), .CK(n408), .RN(n167),
.Q(P_Sgf[43]), .QN(n1823) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_45_ ( .D(n283), .CK(n1889), .RN(n1887),
.Q(P_Sgf[45]), .QN(n1821) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_4_ ( .D(n206), .CK(n1905),
.RN(n1866), .Q(Sgf_normalized_result[4]), .QN(n1820) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_22_ ( .D(n224), .CK(n1901),
.RN(n1868), .Q(Sgf_normalized_result[22]), .QN(n1819) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_20_ ( .D(n222), .CK(n1903),
.RN(n1868), .Q(Sgf_normalized_result[20]), .QN(n1818) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_18_ ( .D(n220), .CK(n1888),
.RN(n1868), .Q(Sgf_normalized_result[18]), .QN(n1817) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_16_ ( .D(n218), .CK(n1905),
.RN(n1868), .Q(Sgf_normalized_result[16]), .QN(n1816) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_14_ ( .D(n216), .CK(n1904),
.RN(n1867), .Q(Sgf_normalized_result[14]), .QN(n1815) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_12_ ( .D(n214), .CK(n1888),
.RN(n1867), .Q(Sgf_normalized_result[12]), .QN(n1814) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_10_ ( .D(n212), .CK(n1905),
.RN(n1867), .Q(Sgf_normalized_result[10]), .QN(n1813) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_8_ ( .D(n210), .CK(n1904),
.RN(n1867), .Q(Sgf_normalized_result[8]), .QN(n1812) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_6_ ( .D(n208), .CK(n1888),
.RN(n1867), .Q(Sgf_normalized_result[6]), .QN(n1811) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_21_ ( .D(n365), .CK(n481), .RN(
n1878), .Q(Op_MX[21]), .QN(n1810) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_7_ ( .D(n351), .CK(n1890), .RN(
n1876), .Q(Op_MX[7]), .QN(n1809) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_15_ ( .D(n359), .CK(n1890), .RN(
n1877), .Q(Op_MX[15]), .QN(n1808) );
DFFRX1TS Zero_Result_Detect_Zero_Info_Mult_Q_reg_0_ ( .D(n311), .CK(n1888),
.RN(n1863), .QN(n1807) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_12_ ( .D(n356), .CK(n1901), .RN(
n1877), .Q(Op_MX[12]), .QN(n1806) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_18_ ( .D(n362), .CK(n1893), .RN(
n1877), .Q(Op_MX[18]), .QN(n1805) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_9_ ( .D(n353), .CK(n1903), .RN(
n1876), .Q(Op_MX[9]), .QN(n1804) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_3_ ( .D(n347), .CK(n1901), .RN(
n1876), .Q(Op_MX[3]), .QN(n1803) );
DFFRX2TS Sel_C_Q_reg_0_ ( .D(n375), .CK(n1890), .RN(n1868), .Q(
FSM_selector_C), .QN(n1802) );
DFFRX2TS Sel_B_Q_reg_1_ ( .D(n235), .CK(n1902), .RN(n1869), .Q(
FSM_selector_B[1]), .QN(n1801) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_6_ ( .D(n350), .CK(n1903), .RN(
n1876), .Q(Op_MX[6]), .QN(n1796) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_19_ ( .D(n363), .CK(n1899), .RN(
n1877), .Q(Op_MX[19]), .QN(n1795) );
DFFRX2TS FS_Module_state_reg_reg_1_ ( .D(n378), .CK(n1904), .RN(n1887), .Q(
FS_Module_state_reg[1]), .QN(n1794) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_10_ ( .D(n354), .CK(n1890), .RN(
n1876), .Q(Op_MX[10]), .QN(n1793) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_4_ ( .D(n348), .CK(n1890), .RN(
n1876), .Q(Op_MX[4]), .QN(n1792) );
DFFRX2TS FS_Module_state_reg_reg_2_ ( .D(n377), .CK(n1902), .RN(n1887), .Q(
FS_Module_state_reg[2]), .QN(n1790) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_13_ ( .D(n357), .CK(n1901), .RN(
n1877), .Q(Op_MX[13]), .QN(n1785) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_16_ ( .D(n360), .CK(n1903), .RN(
n1877), .Q(Op_MX[16]), .QN(n1784) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_0_ ( .D(n344), .CK(n1901), .RN(
n1875), .Q(Op_MX[0]), .QN(n1783) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_1_ ( .D(n345), .CK(n1903), .RN(
n1876), .Q(Op_MX[1]), .QN(n1777) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_4_ ( .D(n196),
.CK(n1907), .RN(n1865), .Q(final_result_ieee[4]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_6_ ( .D(n194),
.CK(n407), .RN(n1865), .Q(final_result_ieee[6]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_8_ ( .D(n192),
.CK(clk), .RN(n1865), .Q(final_result_ieee[8]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_10_ ( .D(n190),
.CK(n1907), .RN(n1865), .Q(final_result_ieee[10]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_12_ ( .D(n188),
.CK(clk), .RN(n1865), .Q(final_result_ieee[12]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_14_ ( .D(n186),
.CK(clk), .RN(n1864), .Q(final_result_ieee[14]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_16_ ( .D(n184),
.CK(n1907), .RN(n1864), .Q(final_result_ieee[16]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_18_ ( .D(n182),
.CK(clk), .RN(n1864), .Q(final_result_ieee[18]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_20_ ( .D(n180),
.CK(n1907), .RN(n1864), .Q(final_result_ieee[20]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_22_ ( .D(n178),
.CK(n481), .RN(n1864), .Q(final_result_ieee[22]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_0_ ( .D(n200),
.CK(n406), .RN(n1866), .Q(final_result_ieee[0]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_1_ ( .D(n199),
.CK(n407), .RN(n1866), .Q(final_result_ieee[1]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_2_ ( .D(n198),
.CK(n407), .RN(n1866), .Q(final_result_ieee[2]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_3_ ( .D(n197),
.CK(n481), .RN(n1865), .Q(final_result_ieee[3]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_5_ ( .D(n195),
.CK(n1906), .RN(n1865), .Q(final_result_ieee[5]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_7_ ( .D(n193),
.CK(n481), .RN(n1865), .Q(final_result_ieee[7]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_9_ ( .D(n191),
.CK(n1906), .RN(n1865), .Q(final_result_ieee[9]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_11_ ( .D(n189),
.CK(clk), .RN(n1865), .Q(final_result_ieee[11]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_13_ ( .D(n187),
.CK(n1907), .RN(n1864), .Q(final_result_ieee[13]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_15_ ( .D(n185),
.CK(n1906), .RN(n1864), .Q(final_result_ieee[15]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_17_ ( .D(n183),
.CK(n1906), .RN(n1864), .Q(final_result_ieee[17]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_19_ ( .D(n181),
.CK(n481), .RN(n1864), .Q(final_result_ieee[19]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_21_ ( .D(n179),
.CK(n481), .RN(n1864), .Q(final_result_ieee[21]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_29_ ( .D(n171),
.CK(n481), .RN(n1863), .Q(final_result_ieee[29]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_30_ ( .D(n170),
.CK(n406), .RN(n1863), .Q(final_result_ieee[30]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_23_ ( .D(n177),
.CK(n407), .RN(n1863), .Q(final_result_ieee[23]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_24_ ( .D(n176),
.CK(clk), .RN(n1863), .Q(final_result_ieee[24]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_25_ ( .D(n175),
.CK(clk), .RN(n1863), .Q(final_result_ieee[25]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_26_ ( .D(n174),
.CK(clk), .RN(n1863), .Q(final_result_ieee[26]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_27_ ( .D(n173),
.CK(n1898), .RN(n1863), .Q(final_result_ieee[27]) );
DFFRXLTS final_result_ieee_Module_Final_Result_IEEE_Q_reg_28_ ( .D(n172),
.CK(n1906), .RN(n1863), .Q(final_result_ieee[28]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_3_ ( .D(n241), .CK(n1903), .RN(n1886),
.Q(P_Sgf[3]) );
DFFRXLTS Exp_module_Oflow_A_m_Q_reg_0_ ( .D(n225), .CK(n1902), .RN(n1870),
.Q(Exp_module_Overflow_flag_A) );
DFFRXLTS Operands_load_reg_YMRegister_Q_reg_31_ ( .D(n381), .CK(n1902), .RN(
n1871), .Q(Op_MY[31]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_20_ ( .D(n258), .CK(n1900), .RN(n1884),
.Q(P_Sgf[20]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_16_ ( .D(n254), .CK(n1900), .RN(n1885),
.Q(P_Sgf[16]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_12_ ( .D(n250), .CK(n1900), .RN(n1885),
.Q(P_Sgf[12]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_6_ ( .D(n244), .CK(n1890), .RN(n1886),
.Q(P_Sgf[6]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_19_ ( .D(n257), .CK(n1900), .RN(n1885),
.Q(P_Sgf[19]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_11_ ( .D(n249), .CK(n1891), .RN(n1885),
.Q(P_Sgf[11]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_1_ ( .D(n239), .CK(n1902), .RN(n1886),
.Q(P_Sgf[1]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_7_ ( .D(n245), .CK(n1891), .RN(n1886),
.Q(P_Sgf[7]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_4_ ( .D(n242), .CK(n1891), .RN(n1886),
.Q(P_Sgf[4]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_21_ ( .D(n259), .CK(n1900), .RN(n1884),
.Q(P_Sgf[21]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_17_ ( .D(n255), .CK(n1900), .RN(n1885),
.Q(P_Sgf[17]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_13_ ( .D(n251), .CK(n1900), .RN(n1885),
.Q(P_Sgf[13]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_9_ ( .D(n247), .CK(n1891), .RN(n1886),
.Q(P_Sgf[9]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_0_ ( .D(n238), .CK(n1902), .RN(n1886),
.Q(P_Sgf[0]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_10_ ( .D(n248), .CK(n1891), .RN(n1885),
.Q(P_Sgf[10]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_8_ ( .D(n246), .CK(n1891), .RN(n1886),
.Q(P_Sgf[8]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_5_ ( .D(n243), .CK(n1891), .RN(n1886),
.Q(P_Sgf[5]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_23_ ( .D(n286), .CK(n1897), .RN(n1873), .Q(Add_result[23]) );
DFFRXLTS Adder_M_Add_Subt_Result_Q_reg_0_ ( .D(n309), .CK(n1895), .RN(n1873),
.Q(Add_result[0]) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_23_ ( .D(n261), .CK(n1895), .RN(n1884),
.Q(P_Sgf[23]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_28_ ( .D(n340), .CK(n1899), .RN(
n1873), .Q(Op_MY[28]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_24_ ( .D(n336), .CK(n1889), .RN(
n1872), .Q(Op_MY[24]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_25_ ( .D(n337), .CK(n1894), .RN(
n1872), .Q(Op_MY[25]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_29_ ( .D(n341), .CK(n1893), .RN(
n1873), .Q(Op_MY[29]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_27_ ( .D(n339), .CK(n408), .RN(
n1872), .Q(Op_MY[27]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_26_ ( .D(n338), .CK(n1895), .RN(
n1872), .Q(Op_MY[26]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_23_ ( .D(n335), .CK(n1896), .RN(
n1872), .Q(Op_MY[23]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_47_ ( .D(n237), .CK(n1905), .RN(n1887),
.Q(P_Sgf[47]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_30_ ( .D(n342), .CK(n1897), .RN(
n1873), .Q(Op_MY[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_30_ ( .D(n374), .CK(n1888), .RN(
n1878), .Q(Op_MX[30]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_25_ ( .D(n369), .CK(n1896), .RN(
n1878), .Q(Op_MX[25]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_24_ ( .D(n368), .CK(n1893), .RN(
n1878), .Q(Op_MX[24]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_27_ ( .D(n371), .CK(n1895), .RN(
n1878), .Q(Op_MX[27]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_29_ ( .D(n373), .CK(n1905), .RN(
n1878), .Q(Op_MX[29]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_26_ ( .D(n370), .CK(n1898), .RN(
n1878), .Q(Op_MX[26]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_23_ ( .D(n367), .CK(n1894), .RN(
n1878), .Q(Op_MX[23]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_8_ ( .D(n226), .CK(n1890), .RN(n1868),
.Q(exp_oper_result[8]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_28_ ( .D(n372), .CK(n1904), .RN(
n1878), .Q(Op_MX[28]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_0_ ( .D(n234), .CK(n1904), .RN(n1869),
.Q(exp_oper_result[0]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_1_ ( .D(n233), .CK(n1888), .RN(n1869),
.Q(exp_oper_result[1]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_2_ ( .D(n232), .CK(n1905), .RN(n1869),
.Q(exp_oper_result[2]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_3_ ( .D(n231), .CK(n1904), .RN(n1869),
.Q(exp_oper_result[3]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_4_ ( .D(n230), .CK(n1901), .RN(n1869),
.Q(exp_oper_result[4]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_5_ ( .D(n229), .CK(n1903), .RN(n1869),
.Q(exp_oper_result[5]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_6_ ( .D(n228), .CK(n1890), .RN(n1869),
.Q(exp_oper_result[6]) );
DFFRX1TS Exp_module_exp_result_m_Q_reg_7_ ( .D(n227), .CK(n1901), .RN(n1869),
.Q(exp_oper_result[7]) );
DFFRX1TS Adder_M_Add_overflow_Result_Q_reg_0_ ( .D(n285), .CK(n1897), .RN(
n1873), .Q(FSM_add_overflow_flag) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_5_ ( .D(n304), .CK(n1897), .RN(n1874),
.Q(Add_result[5]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_3_ ( .D(n306), .CK(n1895), .RN(n1873),
.Q(Add_result[3]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_4_ ( .D(n305), .CK(n1894), .RN(n1873),
.Q(Add_result[4]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_21_ ( .D(n288), .CK(n1893), .RN(n1875), .Q(Add_result[21]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_19_ ( .D(n290), .CK(n1893), .RN(n1875), .Q(Add_result[19]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_17_ ( .D(n292), .CK(n1894), .RN(n1875), .Q(Add_result[17]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_15_ ( .D(n294), .CK(n1895), .RN(n1875), .Q(Add_result[15]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_13_ ( .D(n296), .CK(n1895), .RN(n1874), .Q(Add_result[13]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_11_ ( .D(n298), .CK(n1896), .RN(n1874), .Q(Add_result[11]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_9_ ( .D(n300), .CK(n1894), .RN(n1874),
.Q(Add_result[9]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_7_ ( .D(n302), .CK(n1899), .RN(n1874),
.Q(Add_result[7]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_1_ ( .D(n308), .CK(n1896), .RN(n1873),
.Q(Add_result[1]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_22_ ( .D(n287), .CK(n1901), .RN(n1875), .Q(Add_result[22]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_20_ ( .D(n289), .CK(n1896), .RN(n1875), .Q(Add_result[20]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_18_ ( .D(n291), .CK(n1893), .RN(n1875), .Q(Add_result[18]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_16_ ( .D(n293), .CK(n1889), .RN(n1875), .Q(Add_result[16]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_14_ ( .D(n295), .CK(n481), .RN(n1874),
.Q(Add_result[14]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_12_ ( .D(n297), .CK(n1899), .RN(n1874), .Q(Add_result[12]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_10_ ( .D(n299), .CK(n1889), .RN(n1874), .Q(Add_result[10]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_8_ ( .D(n301), .CK(n1897), .RN(n1874),
.Q(Add_result[8]) );
DFFRX1TS Adder_M_Add_Subt_Result_Q_reg_6_ ( .D(n303), .CK(n407), .RN(n1874),
.Q(Add_result[6]) );
DFFRX1TS Sel_B_Q_reg_0_ ( .D(n236), .CK(n1888), .RN(n1869), .Q(
FSM_selector_B[0]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_2_ ( .D(n204), .CK(n1905),
.RN(n1866), .Q(Sgf_normalized_result[2]) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_22_ ( .D(n366), .CK(n408), .RN(
n1878), .Q(Op_MX[22]), .QN(n548) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_21_ ( .D(n223), .CK(n1903),
.RN(n1868), .Q(Sgf_normalized_result[21]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_19_ ( .D(n221), .CK(n1904),
.RN(n1868), .Q(Sgf_normalized_result[19]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_17_ ( .D(n219), .CK(n1888),
.RN(n1868), .Q(Sgf_normalized_result[17]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_15_ ( .D(n217), .CK(n1905),
.RN(n1867), .Q(Sgf_normalized_result[15]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_13_ ( .D(n215), .CK(n1904),
.RN(n1867), .Q(Sgf_normalized_result[13]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_11_ ( .D(n213), .CK(n1888),
.RN(n1867), .Q(Sgf_normalized_result[11]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_9_ ( .D(n211), .CK(n1904),
.RN(n1867), .Q(Sgf_normalized_result[9]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_7_ ( .D(n209), .CK(n1888),
.RN(n1867), .Q(Sgf_normalized_result[7]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_5_ ( .D(n207), .CK(n1905),
.RN(n1866), .Q(Sgf_normalized_result[5]) );
DFFRX1TS Barrel_Shifter_module_Output_Reg_Q_reg_3_ ( .D(n205), .CK(n1904),
.RN(n1866), .Q(Sgf_normalized_result[3]) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_1_ ( .D(n203), .CK(n1902),
.RN(n1866), .Q(Sgf_normalized_result[1]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_11_ ( .D(n323), .CK(n408), .RN(
n1871), .Q(Op_MY[11]), .QN(n1778) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_5_ ( .D(n317), .CK(n481), .RN(
n1870), .Q(Op_MY[5]), .QN(n1797) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_20_ ( .D(n332), .CK(n1899), .RN(
n1872), .Q(Op_MY[20]), .QN(n1798) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_19_ ( .D(n331), .CK(n1898), .RN(
n1872), .Q(Op_MY[19]), .QN(n1779) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_18_ ( .D(n330), .CK(n1896), .RN(
n1872), .Q(Op_MY[18]), .QN(n1857) );
DFFRX2TS Barrel_Shifter_module_Output_Reg_Q_reg_0_ ( .D(n202), .CK(n1902),
.RN(n1866), .Q(Sgf_normalized_result[0]) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_10_ ( .D(n322), .CK(n1898), .RN(
n1871), .Q(Op_MY[10]), .QN(n1852) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_4_ ( .D(n316), .CK(n1893), .RN(
n1870), .Q(Op_MY[4]), .QN(n1781) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_3_ ( .D(n315), .CK(n1895), .RN(
n1870), .Q(Op_MY[3]), .QN(n1788) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_14_ ( .D(n326), .CK(n1897), .RN(
n1871), .Q(Op_MY[14]), .QN(n1776) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_12_ ( .D(n324), .CK(n1894), .RN(
n1871), .Q(Op_MY[12]), .QN(n1787) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_6_ ( .D(n318), .CK(n1897), .RN(
n1870), .Q(Op_MY[6]), .QN(n1786) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_8_ ( .D(n320), .CK(n1889), .RN(
n1870), .Q(Op_MY[8]), .QN(n1775) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_1_ ( .D(n313), .CK(n1899), .RN(
n1870), .Q(Op_MY[1]), .QN(n1780) );
DFFRX2TS Sel_A_Q_reg_0_ ( .D(n376), .CK(n1902), .RN(n1879), .Q(
FSM_selector_A), .QN(n549) );
CMPR32X2TS DP_OP_32J138_122_6543_U10 ( .A(S_Oper_A_exp[0]), .B(
DP_OP_32J138_122_6543_n33), .C(DP_OP_32J138_122_6543_n22), .CO(
DP_OP_32J138_122_6543_n9), .S(Exp_module_Data_S[0]) );
CMPR32X2TS DP_OP_32J138_122_6543_U9 ( .A(DP_OP_32J138_122_6543_n21), .B(
S_Oper_A_exp[1]), .C(DP_OP_32J138_122_6543_n9), .CO(
DP_OP_32J138_122_6543_n8), .S(Exp_module_Data_S[1]) );
CMPR32X2TS DP_OP_32J138_122_6543_U8 ( .A(DP_OP_32J138_122_6543_n20), .B(
S_Oper_A_exp[2]), .C(DP_OP_32J138_122_6543_n8), .CO(
DP_OP_32J138_122_6543_n7), .S(Exp_module_Data_S[2]) );
CMPR32X2TS DP_OP_32J138_122_6543_U7 ( .A(DP_OP_32J138_122_6543_n19), .B(
S_Oper_A_exp[3]), .C(DP_OP_32J138_122_6543_n7), .CO(
DP_OP_32J138_122_6543_n6), .S(Exp_module_Data_S[3]) );
CMPR32X2TS DP_OP_32J138_122_6543_U6 ( .A(DP_OP_32J138_122_6543_n18), .B(
S_Oper_A_exp[4]), .C(DP_OP_32J138_122_6543_n6), .CO(
DP_OP_32J138_122_6543_n5), .S(Exp_module_Data_S[4]) );
CMPR32X2TS DP_OP_32J138_122_6543_U5 ( .A(DP_OP_32J138_122_6543_n17), .B(
S_Oper_A_exp[5]), .C(DP_OP_32J138_122_6543_n5), .CO(
DP_OP_32J138_122_6543_n4), .S(Exp_module_Data_S[5]) );
CMPR32X2TS DP_OP_32J138_122_6543_U4 ( .A(DP_OP_32J138_122_6543_n16), .B(
S_Oper_A_exp[6]), .C(DP_OP_32J138_122_6543_n4), .CO(
DP_OP_32J138_122_6543_n3), .S(Exp_module_Data_S[6]) );
CMPR32X2TS DP_OP_32J138_122_6543_U3 ( .A(DP_OP_32J138_122_6543_n15), .B(
S_Oper_A_exp[7]), .C(DP_OP_32J138_122_6543_n3), .CO(
DP_OP_32J138_122_6543_n2), .S(Exp_module_Data_S[7]) );
CMPR32X2TS DP_OP_32J138_122_6543_U2 ( .A(DP_OP_32J138_122_6543_n33), .B(
S_Oper_A_exp[8]), .C(DP_OP_32J138_122_6543_n2), .CO(
DP_OP_32J138_122_6543_n1), .S(Exp_module_Data_S[8]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_22_ ( .D(n334), .CK(n1893), .RN(
n1872), .Q(Op_MY[22]), .QN(n1782) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_11_ ( .D(n355), .CK(n1891), .RN(
n1877), .Q(Op_MX[11]), .QN(n1791) );
DFFRX4TS Operands_load_reg_XMRegister_Q_reg_2_ ( .D(n346), .CK(n1891), .RN(
n1876), .Q(Op_MX[2]), .QN(n1844) );
DFFRX1TS Operands_load_reg_XMRegister_Q_reg_31_ ( .D(n343), .CK(n1903), .RN(
n1875), .Q(Op_MX[31]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_7_ ( .D(n319), .CK(n1899), .RN(
n1870), .Q(Op_MY[7]), .QN(n1850) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_15_ ( .D(n253), .CK(n1900), .RN(n1885),
.Q(P_Sgf[15]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_18_ ( .D(n256), .CK(n1900), .RN(n1885),
.Q(P_Sgf[18]) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_14_ ( .D(n252), .CK(n1900), .RN(n1885),
.Q(P_Sgf[14]) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_16_ ( .D(n328), .CK(n1896), .RN(
n1871), .Q(Op_MY[16]), .QN(n1855) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_13_ ( .D(n325), .CK(n1894), .RN(
n1871), .Q(Op_MY[13]), .QN(n1853) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_9_ ( .D(n321), .CK(n1896), .RN(
n1871), .Q(Op_MY[9]), .QN(n1851) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_15_ ( .D(n327), .CK(n1889), .RN(
n1871), .Q(Op_MY[15]), .QN(n1854) );
DFFRX4TS Operands_load_reg_YMRegister_Q_reg_17_ ( .D(n329), .CK(n1893), .RN(
n1871), .Q(Op_MY[17]), .QN(n1856) );
DFFRX1TS Sgf_operation_finalreg_Q_reg_22_ ( .D(n260), .CK(n1898), .RN(n1884),
.Q(P_Sgf[22]) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_2_ ( .D(n314), .CK(n1894), .RN(
n1870), .Q(Op_MY[2]), .QN(n1799) );
DFFRX1TS Operands_load_reg_YMRegister_Q_reg_21_ ( .D(n333), .CK(n1889), .RN(
n1872), .Q(Op_MY[21]), .QN(n1789) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_17_ ( .D(n361), .CK(n1890), .RN(
n1877), .Q(Op_MX[17]), .QN(n1846) );
DFFRX2TS Operands_load_reg_XMRegister_Q_reg_5_ ( .D(n349), .CK(n1890), .RN(
n1876), .Q(Op_MX[5]), .QN(n1845) );
DFFRX2TS Operands_load_reg_YMRegister_Q_reg_0_ ( .D(n312), .CK(n407), .RN(
n1870), .Q(Op_MY[0]), .QN(n1800) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_46_ ( .D(n284), .CK(n1897), .RN(n167),
.Q(P_Sgf[46]) );
DFFRX1TS Exp_module_Underflow_m_Q_reg_0_ ( .D(n201), .CK(n1898), .RN(n1866),
.Q(underflow_flag) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_29_ ( .D(n267), .CK(n1896), .RN(n1884),
.Q(P_Sgf[29]), .QN(n1837) );
DFFRXLTS Sgf_operation_finalreg_Q_reg_44_ ( .D(n282), .CK(n408), .RN(n167),
.Q(P_Sgf[44]), .QN(n1822) );
INVX2TS U406 ( .A(n405), .Y(n406) );
CLKINVX6TS U407 ( .A(n405), .Y(n408) );
ADDFX1TS U408 ( .A(Op_MY[20]), .B(n417), .CI(n871), .CO(n888), .S(n1557) );
CLKBUFX2TS U409 ( .A(n1545), .Y(n477) );
AND2X2TS U410 ( .A(n605), .B(n604), .Y(n1190) );
OA21X2TS U411 ( .A0(n751), .A1(n1530), .B0(FS_Module_state_reg[1]), .Y(n734)
);
ADDFX1TS U412 ( .A(Op_MX[11]), .B(n1851), .CI(n509), .CO(n1018), .S(n1170)
);
ADDFX1TS U413 ( .A(Op_MX[5]), .B(n1797), .CI(n409), .CO(n1017), .S(n1201) );
ADDFX1TS U414 ( .A(Op_MX[17]), .B(n1854), .CI(n1856), .CO(n1066), .S(n1109)
);
CLKBUFX3TS U415 ( .A(n1857), .Y(n480) );
OAI22X1TS U416 ( .A0(n1803), .A1(Op_MX[4]), .B0(n1792), .B1(Op_MX[3]), .Y(
n396) );
CLKINVX3TS U417 ( .A(n1586), .Y(n391) );
INVX4TS U418 ( .A(n405), .Y(n407) );
AOI222X1TS U419 ( .A0(Op_MY[1]), .A1(n451), .B0(n547), .B1(n421), .C0(n671),
.C1(n420), .Y(n617) );
OAI211X1TS U420 ( .A0(n966), .A1(n1780), .B0(n597), .C0(n596), .Y(n601) );
AO21XLTS U421 ( .A0(n417), .A1(n888), .B0(Op_MY[22]), .Y(n397) );
INVX2TS U422 ( .A(n588), .Y(n584) );
INVX2TS U423 ( .A(n581), .Y(n577) );
CLKAND2X2TS U424 ( .A(n661), .B(n669), .Y(n393) );
OAI22X1TS U425 ( .A0(n1844), .A1(n1777), .B0(Op_MX[1]), .B1(n1356), .Y(n935)
);
CLKAND2X2TS U426 ( .A(n595), .B(n594), .Y(n392) );
OAI31X1TS U427 ( .A0(n1380), .A1(n1356), .A2(n1379), .B0(n1378), .Y(n1424)
);
OAI31X1TS U428 ( .A0(n1238), .A1(n411), .A2(n1237), .B0(n1236), .Y(n1239) );
OAI31X1TS U429 ( .A0(n1267), .A1(Op_MX[2]), .A2(n1266), .B0(n1265), .Y(n1407) );
OAI31X1TS U430 ( .A0(n1263), .A1(Op_MX[2]), .A2(n1262), .B0(n1261), .Y(n1394) );
OAI31X1TS U431 ( .A0(n1283), .A1(Op_MX[2]), .A2(n1282), .B0(n1281), .Y(n1390) );
OAI31X1TS U432 ( .A0(n1376), .A1(n1433), .A2(n1375), .B0(n1374), .Y(n1382)
);
OAI31X1TS U433 ( .A0(n1252), .A1(Op_MX[2]), .A2(n1251), .B0(n1250), .Y(n1364) );
OAI222X1TS U434 ( .A0(n1800), .A1(n469), .B0(n506), .B1(n530), .C0(n461),
.C1(n939), .Y(n1358) );
OAI31X1TS U435 ( .A0(n1294), .A1(Op_MX[2]), .A2(n1293), .B0(n1292), .Y(n1300) );
INVX2TS U436 ( .A(n1774), .Y(n1331) );
OAI31X1TS U437 ( .A0(n1436), .A1(n409), .A2(n1435), .B0(n1434), .Y(n1760) );
AOI211X1TS U438 ( .A0(n412), .A1(Op_MX[0]), .B0(n1844), .C0(n1358), .Y(n941)
);
CLKBUFX3TS U439 ( .A(n1692), .Y(n1691) );
NOR3X6TS U440 ( .A(n947), .B(n1794), .C(n1862), .Y(n1774) );
AO22XLTS U441 ( .A0(n398), .A1(Data_MX[31]), .B0(n425), .B1(Op_MX[31]), .Y(
n343) );
OAI33X1TS U442 ( .A0(n418), .A1(Op_MY[22]), .A2(n1478), .B0(n424), .B1(n484),
.B2(n1477), .Y(n1483) );
OAI32X1TS U443 ( .A0(n1773), .A1(n949), .A2(overflow_flag), .B0(n1774), .B1(
n1861), .Y(n168) );
INVX2TS U444 ( .A(n938), .Y(n1431) );
INVX2TS U445 ( .A(n1444), .Y(n489) );
INVX2TS U446 ( .A(n1437), .Y(n1209) );
INVX2TS U447 ( .A(n1436), .Y(n1377) );
INVX2TS U448 ( .A(n1449), .Y(n1214) );
NAND2X2TS U449 ( .A(n579), .B(n581), .Y(n1184) );
AND2X2TS U450 ( .A(n622), .B(n396), .Y(n394) );
NOR2X4TS U451 ( .A(FSM_selector_C), .B(n731), .Y(n930) );
INVX2TS U452 ( .A(n1454), .Y(n1207) );
INVX2TS U453 ( .A(n1456), .Y(n1204) );
NAND2BX2TS U454 ( .AN(n1488), .B(n1802), .Y(n933) );
OR2X1TS U455 ( .A(n1802), .B(n731), .Y(n395) );
AND2X2TS U456 ( .A(n1532), .B(n1325), .Y(n398) );
OR2X1TS U457 ( .A(Op_MX[22]), .B(n615), .Y(n399) );
NOR3X2TS U458 ( .A(underflow_flag), .B(overflow_flag), .C(n1773), .Y(n1772)
);
AOI211X1TS U459 ( .A0(n1623), .A1(n418), .B0(n452), .C0(n554), .Y(
mult_x_19_n593) );
INVX2TS U460 ( .A(Op_MX[17]), .Y(n400) );
INVX2TS U461 ( .A(n400), .Y(n401) );
INVX2TS U462 ( .A(Op_MX[5]), .Y(n402) );
INVX2TS U463 ( .A(n402), .Y(n403) );
INVX2TS U464 ( .A(n1799), .Y(n404) );
INVX2TS U465 ( .A(clk), .Y(n405) );
INVX2TS U466 ( .A(n410), .Y(n1356) );
INVX2TS U467 ( .A(n410), .Y(n1433) );
INVX2TS U468 ( .A(n1844), .Y(n409) );
INVX2TS U469 ( .A(Op_MX[2]), .Y(n410) );
INVX2TS U470 ( .A(n410), .Y(n411) );
INVX2TS U471 ( .A(n1800), .Y(n412) );
INVX2TS U472 ( .A(n412), .Y(n413) );
INVX2TS U473 ( .A(n1772), .Y(n414) );
INVX2TS U474 ( .A(n414), .Y(n415) );
INVX2TS U475 ( .A(n414), .Y(n416) );
INVX2TS U476 ( .A(n1789), .Y(n417) );
INVX2TS U477 ( .A(n1789), .Y(n418) );
INVX2TS U478 ( .A(n399), .Y(n419) );
INVX2TS U479 ( .A(n399), .Y(n420) );
INVX2TS U480 ( .A(n391), .Y(n421) );
INVX2TS U481 ( .A(n1772), .Y(n422) );
INVX2TS U482 ( .A(Op_MY[21]), .Y(n423) );
CLKINVX3TS U483 ( .A(Op_MY[21]), .Y(n424) );
INVX2TS U484 ( .A(n398), .Y(n425) );
INVX2TS U485 ( .A(n398), .Y(n426) );
INVX2TS U486 ( .A(n1799), .Y(n427) );
CLKINVX3TS U487 ( .A(n427), .Y(n428) );
CLKINVX3TS U488 ( .A(n427), .Y(n429) );
INVX2TS U489 ( .A(n1184), .Y(n430) );
INVX2TS U490 ( .A(n430), .Y(n431) );
INVX2TS U491 ( .A(n430), .Y(n432) );
INVX2TS U492 ( .A(n482), .Y(n433) );
INVX2TS U493 ( .A(n482), .Y(n434) );
INVX2TS U494 ( .A(n489), .Y(n435) );
INVX2TS U495 ( .A(n435), .Y(n436) );
INVX2TS U496 ( .A(n435), .Y(n437) );
INVX2TS U497 ( .A(n394), .Y(n438) );
INVX2TS U498 ( .A(n394), .Y(n439) );
INVX2TS U499 ( .A(n394), .Y(n440) );
INVX2TS U500 ( .A(n393), .Y(n441) );
INVX2TS U501 ( .A(n393), .Y(n442) );
INVX2TS U502 ( .A(n393), .Y(n443) );
INVX2TS U503 ( .A(n392), .Y(n444) );
INVX2TS U504 ( .A(n392), .Y(n445) );
INVX2TS U505 ( .A(n392), .Y(n446) );
INVX2TS U506 ( .A(n1190), .Y(n447) );
INVX2TS U507 ( .A(n1190), .Y(n448) );
INVX2TS U508 ( .A(n1190), .Y(n449) );
OR2X1TS U509 ( .A(n548), .B(n615), .Y(n1587) );
INVX2TS U510 ( .A(n1587), .Y(n450) );
INVX2TS U511 ( .A(n1587), .Y(n451) );
INVX2TS U512 ( .A(n1587), .Y(n452) );
INVX2TS U513 ( .A(n395), .Y(n453) );
INVX2TS U514 ( .A(n395), .Y(n454) );
INVX2TS U515 ( .A(n395), .Y(n455) );
INVX2TS U516 ( .A(n930), .Y(n456) );
INVX2TS U517 ( .A(n456), .Y(n457) );
INVX2TS U518 ( .A(n456), .Y(n458) );
INVX2TS U519 ( .A(n1431), .Y(n459) );
INVX2TS U520 ( .A(n459), .Y(n460) );
INVX2TS U521 ( .A(n459), .Y(n461) );
INVX2TS U522 ( .A(n1204), .Y(n462) );
INVX2TS U523 ( .A(n462), .Y(n463) );
INVX2TS U524 ( .A(n462), .Y(n464) );
INVX2TS U525 ( .A(n1214), .Y(n465) );
INVX2TS U526 ( .A(n465), .Y(n466) );
INVX2TS U527 ( .A(n465), .Y(n467) );
BUFX4TS U528 ( .A(n1907), .Y(n1898) );
INVX2TS U529 ( .A(n1377), .Y(n468) );
INVX2TS U530 ( .A(n468), .Y(n469) );
INVX2TS U531 ( .A(n468), .Y(n470) );
BUFX3TS U532 ( .A(n408), .Y(n523) );
INVX2TS U533 ( .A(n1207), .Y(n471) );
INVX2TS U534 ( .A(n471), .Y(n472) );
INVX2TS U535 ( .A(n471), .Y(n473) );
INVX2TS U536 ( .A(n1209), .Y(n474) );
INVX2TS U537 ( .A(n474), .Y(n475) );
INVX2TS U538 ( .A(n474), .Y(n476) );
AOI21X2TS U539 ( .A0(n1028), .A1(n419), .B0(n1027), .Y(n1543) );
OAI21X1TS U540 ( .A0(n429), .A1(n391), .B0(n1026), .Y(n1027) );
BUFX3TS U541 ( .A(n1791), .Y(n867) );
AOI211X1TS U542 ( .A0(Op_MY[22]), .A1(n1445), .B0(n1444), .C0(n1443), .Y(
n1446) );
AOI222X1TS U543 ( .A0(Op_MY[1]), .A1(n1444), .B0(Op_MY[0]), .B1(n1445), .C0(
n671), .C1(n910), .Y(n665) );
NOR2X2TS U544 ( .A(n575), .B(n571), .Y(n1444) );
OAI211XLTS U545 ( .A0(Sgf_normalized_result[9]), .A1(n1339), .B0(n1664),
.C0(n1342), .Y(n567) );
NOR2X2TS U546 ( .A(n1812), .B(n1340), .Y(n1339) );
OAI211XLTS U547 ( .A0(Sgf_normalized_result[13]), .A1(n1652), .B0(n1664),
.C0(n1651), .Y(n1653) );
NOR2X2TS U548 ( .A(n1814), .B(n1648), .Y(n1652) );
OAI211XLTS U549 ( .A0(Sgf_normalized_result[17]), .A1(n1658), .B0(n1664),
.C0(n1657), .Y(n1659) );
NOR2X2TS U550 ( .A(n1816), .B(n1654), .Y(n1658) );
OAI211XLTS U551 ( .A0(Sgf_normalized_result[21]), .A1(n1665), .B0(n1664),
.C0(n1663), .Y(n1666) );
NOR2X2TS U552 ( .A(n1818), .B(n1660), .Y(n1665) );
CLKBUFX3TS U553 ( .A(n1852), .Y(n1607) );
CLKINVX3TS U554 ( .A(n1692), .Y(n1763) );
INVX2TS U555 ( .A(n1692), .Y(n1416) );
INVX2TS U556 ( .A(n1692), .Y(n1738) );
NAND2X4TS U557 ( .A(n1639), .B(n1765), .Y(n1496) );
CLKBUFX3TS U558 ( .A(n1692), .Y(n1765) );
CLKINVX3TS U559 ( .A(n734), .Y(n1486) );
INVX2TS U560 ( .A(n704), .Y(n835) );
NOR2X2TS U561 ( .A(n413), .B(n593), .Y(mult_x_19_n471) );
INVX2TS U562 ( .A(n397), .Y(n478) );
INVX2TS U563 ( .A(n397), .Y(n479) );
CLKXOR2X4TS U564 ( .A(n810), .B(n1520), .Y(n1568) );
CLKXOR2X4TS U565 ( .A(n888), .B(n1470), .Y(n1553) );
OAI31X1TS U566 ( .A0(n1515), .A1(n655), .A2(n1624), .B0(n654), .Y(n1084) );
NAND2X2TS U567 ( .A(n547), .B(n581), .Y(n1515) );
OAI31X1TS U568 ( .A0(n1880), .A1(n639), .A2(n1507), .B0(n638), .Y(n1049) );
NAND2X2TS U569 ( .A(Op_MY[0]), .B(n588), .Y(n1507) );
AOI22X2TS U570 ( .A0(Op_MX[8]), .A1(Op_MX[7]), .B0(n1809), .B1(n1128), .Y(
n571) );
CLKBUFX3TS U571 ( .A(n1849), .Y(n1128) );
CLKBUFX3TS U572 ( .A(n1692), .Y(n1771) );
OAI31X4TS U573 ( .A0(n1256), .A1(n409), .A2(n1255), .B0(n1254), .Y(n1413) );
OAI31X4TS U574 ( .A0(n1229), .A1(n1433), .A2(n1228), .B0(n1227), .Y(n1368)
);
OAI31X4TS U575 ( .A0(n1234), .A1(n1225), .A2(n1224), .B0(n1223), .Y(n1366)
);
NAND2X2TS U576 ( .A(n547), .B(n669), .Y(n1234) );
NOR3X2TS U577 ( .A(FS_Module_state_reg[0]), .B(FS_Module_state_reg[3]), .C(
n1790), .Y(n934) );
CLKBUFX3TS U578 ( .A(n1855), .Y(n1600) );
OAI22X2TS U579 ( .A0(n1000), .A1(n1795), .B0(Op_MX[19]), .B1(Op_MX[20]), .Y(
n586) );
CLKBUFX3TS U580 ( .A(n1847), .Y(n1000) );
CLKBUFX3TS U581 ( .A(n1848), .Y(n1624) );
OAI22X2TS U582 ( .A0(n814), .A1(n1793), .B0(Op_MX[10]), .B1(Op_MX[11]), .Y(
n594) );
OAI22X4TS U583 ( .A0(n1625), .A1(Op_MX[18]), .B0(n1805), .B1(Op_MX[17]), .Y(
n588) );
OAI22X2TS U584 ( .A0(n1193), .A1(n1784), .B0(Op_MX[16]), .B1(Op_MX[17]), .Y(
n606) );
AOI22X2TS U585 ( .A0(Op_MX[5]), .A1(n1796), .B0(Op_MX[6]), .B1(n1626), .Y(
n575) );
BUFX4TS U586 ( .A(n1906), .Y(n1897) );
BUFX4TS U587 ( .A(n408), .Y(n1894) );
BUFX6TS U588 ( .A(n523), .Y(n1902) );
BUFX6TS U589 ( .A(n523), .Y(n1888) );
BUFX6TS U590 ( .A(n523), .Y(n1905) );
BUFX6TS U591 ( .A(n523), .Y(n1904) );
BUFX6TS U592 ( .A(n1907), .Y(n1900) );
CLKINVX6TS U593 ( .A(n405), .Y(n481) );
BUFX6TS U594 ( .A(n523), .Y(n1899) );
BUFX6TS U595 ( .A(n523), .Y(n1891) );
BUFX6TS U596 ( .A(n523), .Y(n1901) );
BUFX6TS U597 ( .A(n523), .Y(n1903) );
BUFX6TS U598 ( .A(n523), .Y(n1890) );
BUFX6TS U599 ( .A(clk), .Y(n1895) );
BUFX6TS U600 ( .A(n1907), .Y(n1896) );
BUFX6TS U601 ( .A(n408), .Y(n1889) );
BUFX6TS U602 ( .A(n523), .Y(n1893) );
INVX2TS U603 ( .A(n1151), .Y(n482) );
NAND2X1TS U604 ( .A(n586), .B(n588), .Y(n1151) );
INVX2TS U605 ( .A(n1782), .Y(n483) );
INVX2TS U606 ( .A(n483), .Y(n484) );
INVX2TS U607 ( .A(n483), .Y(n485) );
INVX2TS U608 ( .A(n933), .Y(n486) );
INVX2TS U609 ( .A(n486), .Y(n487) );
INVX2TS U610 ( .A(n486), .Y(n488) );
OAI22X2TS U611 ( .A0(n1844), .A1(n1803), .B0(Op_MX[3]), .B1(n1356), .Y(n622)
);
OAI22X2TS U612 ( .A0(n423), .A1(n1782), .B0(Op_MY[22]), .B1(n417), .Y(n1470)
);
INVX2TS U613 ( .A(n1776), .Y(n490) );
INVX2TS U614 ( .A(n490), .Y(n491) );
INVX2TS U615 ( .A(n490), .Y(n492) );
INVX2TS U616 ( .A(n1775), .Y(n493) );
INVX2TS U617 ( .A(n493), .Y(n494) );
INVX2TS U618 ( .A(n493), .Y(n495) );
INVX2TS U619 ( .A(n1781), .Y(n496) );
INVX2TS U620 ( .A(n496), .Y(n497) );
INVX2TS U621 ( .A(n496), .Y(n498) );
INVX2TS U622 ( .A(n1788), .Y(n499) );
INVX2TS U623 ( .A(n499), .Y(n500) );
INVX2TS U624 ( .A(n499), .Y(n501) );
INVX2TS U625 ( .A(Op_MY[20]), .Y(n502) );
INVX2TS U626 ( .A(Op_MY[20]), .Y(n503) );
INVX2TS U627 ( .A(n1780), .Y(n504) );
INVX2TS U628 ( .A(n504), .Y(n505) );
INVX2TS U629 ( .A(n504), .Y(n506) );
INVX2TS U630 ( .A(Op_MY[19]), .Y(n507) );
INVX2TS U631 ( .A(Op_MY[19]), .Y(n508) );
INVX2TS U632 ( .A(Op_MY[11]), .Y(n509) );
INVX2TS U633 ( .A(Op_MY[11]), .Y(n510) );
INVX2TS U634 ( .A(Op_MY[5]), .Y(n511) );
INVX2TS U635 ( .A(Op_MY[5]), .Y(n512) );
INVX2TS U636 ( .A(n1787), .Y(n513) );
INVX2TS U637 ( .A(n513), .Y(n514) );
INVX2TS U638 ( .A(n513), .Y(n515) );
INVX2TS U639 ( .A(n1786), .Y(n516) );
INVX2TS U640 ( .A(n516), .Y(n517) );
INVX2TS U641 ( .A(n516), .Y(n518) );
CLKBUFX2TS U642 ( .A(n1465), .Y(n1202) );
INVX2TS U643 ( .A(n1202), .Y(n519) );
INVX2TS U644 ( .A(n1202), .Y(n520) );
INVX2TS U645 ( .A(n1202), .Y(n521) );
NOR2X2TS U646 ( .A(n1819), .B(n1663), .Y(n1668) );
OAI211XLTS U647 ( .A0(Sgf_normalized_result[19]), .A1(n1661), .B0(n1664),
.C0(n1660), .Y(n1662) );
NOR2X2TS U648 ( .A(n1817), .B(n1657), .Y(n1661) );
OAI211XLTS U649 ( .A0(Sgf_normalized_result[15]), .A1(n1655), .B0(n1664),
.C0(n1654), .Y(n1656) );
NOR2X2TS U650 ( .A(n1815), .B(n1651), .Y(n1655) );
OAI211XLTS U651 ( .A0(Sgf_normalized_result[11]), .A1(n1649), .B0(n1664),
.C0(n1648), .Y(n1650) );
NOR2X2TS U652 ( .A(n1813), .B(n1342), .Y(n1649) );
OAI211XLTS U653 ( .A0(Sgf_normalized_result[7]), .A1(n1336), .B0(n1664),
.C0(n1340), .Y(n566) );
NOR2X2TS U654 ( .A(n1811), .B(n1645), .Y(n1336) );
NOR4X1TS U655 ( .A(Op_MX[15]), .B(Op_MX[16]), .C(Op_MX[18]), .D(Op_MX[19]),
.Y(n1629) );
OAI22X2TS U656 ( .A0(beg_FSM), .A1(n1879), .B0(ack_FSM), .B1(n945), .Y(n1327) );
NOR2X2TS U657 ( .A(n413), .B(n604), .Y(mult_x_19_n435) );
AOI222X1TS U658 ( .A0(n1417), .A1(n1418), .B0(n1417), .B1(n1419), .C0(n1418),
.C1(n1419), .Y(n1245) );
XNOR2X2TS U659 ( .A(n1222), .B(n1221), .Y(n1417) );
OAI32X1TS U660 ( .A0(n1691), .A1(n944), .A2(n943), .B0(n1843), .B1(n1767),
.Y(n240) );
OAI22X2TS U661 ( .A0(n1792), .A1(n1224), .B0(Op_MX[5]), .B1(Op_MX[4]), .Y(
n661) );
XOR2XLTS U662 ( .A(n1418), .B(n1417), .Y(n1420) );
AOI222X4TS U663 ( .A0(n1366), .A1(n1368), .B0(n1366), .B1(n1766), .C0(n1368),
.C1(n1766), .Y(n1418) );
OAI22X2TS U664 ( .A0(n1804), .A1(Op_MX[8]), .B0(n1882), .B1(Op_MX[9]), .Y(
n595) );
OAI22X2TS U665 ( .A0(n1624), .A1(n1785), .B0(Op_MX[13]), .B1(Op_MX[14]), .Y(
n579) );
INVX2TS U666 ( .A(n1329), .Y(n522) );
NAND2X2TS U667 ( .A(n934), .B(n1794), .Y(n1329) );
AOI22X2TS U668 ( .A0(Op_MX[20]), .A1(n1810), .B0(Op_MX[21]), .B1(n1000), .Y(
n615) );
BUFX4TS U669 ( .A(n408), .Y(n1907) );
INVX2TS U670 ( .A(n1199), .Y(n524) );
OAI22X4TS U671 ( .A0(n867), .A1(Op_MX[12]), .B0(n1806), .B1(Op_MX[11]), .Y(
n581) );
CLKBUFX3TS U672 ( .A(n1791), .Y(n1199) );
CLKBUFX2TS U673 ( .A(n1427), .Y(n1432) );
INVX2TS U674 ( .A(n1432), .Y(n525) );
INVX2TS U675 ( .A(n1432), .Y(n526) );
INVX2TS U676 ( .A(n1432), .Y(n527) );
CLKAND2X2TS U677 ( .A(Op_MX[0]), .B(n935), .Y(n1428) );
INVX2TS U678 ( .A(n1428), .Y(n528) );
INVX2TS U679 ( .A(n1428), .Y(n529) );
INVX2TS U680 ( .A(n1428), .Y(n530) );
CLKAND2X2TS U681 ( .A(n607), .B(n606), .Y(n1457) );
INVX2TS U682 ( .A(n1457), .Y(n531) );
INVX2TS U683 ( .A(n1457), .Y(n532) );
INVX2TS U684 ( .A(n1457), .Y(n533) );
OAI22X2TS U685 ( .A0(n1808), .A1(Op_MX[14]), .B0(n1881), .B1(Op_MX[15]), .Y(
n607) );
CLKBUFX3TS U686 ( .A(n1136), .Y(n534) );
CLKBUFX3TS U687 ( .A(n1136), .Y(n535) );
NAND2BX1TS U688 ( .AN(n570), .B(n575), .Y(n1136) );
CLKAND2X2TS U689 ( .A(n577), .B(n580), .Y(n1451) );
INVX2TS U690 ( .A(n1451), .Y(n536) );
INVX2TS U691 ( .A(n1451), .Y(n537) );
INVX2TS U692 ( .A(n1451), .Y(n538) );
CLKAND2X2TS U693 ( .A(n584), .B(n587), .Y(n1461) );
INVX2TS U694 ( .A(n1461), .Y(n539) );
INVX2TS U695 ( .A(n1461), .Y(n540) );
INVX2TS U696 ( .A(n1461), .Y(n541) );
OR2X1TS U697 ( .A(n1488), .B(n1802), .Y(n929) );
INVX2TS U698 ( .A(n929), .Y(n542) );
INVX2TS U699 ( .A(n929), .Y(n543) );
INVX2TS U700 ( .A(n929), .Y(n544) );
INVX2TS U701 ( .A(n670), .Y(n545) );
INVX2TS U702 ( .A(n670), .Y(n546) );
INVX2TS U703 ( .A(n670), .Y(n1439) );
NOR2X2TS U704 ( .A(n622), .B(n661), .Y(n670) );
CLKBUFX3TS U705 ( .A(Op_MY[0]), .Y(n547) );
AOI222X4TS U706 ( .A0(Op_MY[1]), .A1(n430), .B0(n547), .B1(n1451), .C0(n671),
.C1(n724), .Y(n655) );
AOI222X4TS U707 ( .A0(Op_MY[1]), .A1(n482), .B0(n547), .B1(n1461), .C0(n671),
.C1(n711), .Y(n639) );
OAI22X2TS U708 ( .A0(n505), .A1(n413), .B0(n412), .B1(Op_MY[1]), .Y(n939) );
OAI21XLTS U709 ( .A0(n506), .A1(n540), .B0(n589), .Y(n590) );
OAI21XLTS U710 ( .A0(n1511), .A1(n1584), .B0(n1510), .Y(n1512) );
OAI21XLTS U711 ( .A0(n848), .A1(n847), .B0(n1846), .Y(n846) );
OAI21XLTS U712 ( .A0(n1584), .A1(n1583), .B0(n1582), .Y(n1585) );
OAI21XLTS U713 ( .A0(n902), .A1(n901), .B0(n1114), .Y(n900) );
OAI21XLTS U714 ( .A0(n1162), .A1(n1161), .B0(n603), .Y(n1160) );
OAI21XLTS U715 ( .A0(n1126), .A1(n1125), .B0(n1848), .Y(n1124) );
OAI21XLTS U716 ( .A0(n838), .A1(n837), .B0(n1196), .Y(n836) );
OAI21XLTS U717 ( .A0(n817), .A1(n816), .B0(n814), .Y(n815) );
INVX2TS U718 ( .A(mult_x_19_n211), .Y(n1519) );
OAI21XLTS U719 ( .A0(n730), .A1(n729), .B0(n1000), .Y(n728) );
OAI21XLTS U720 ( .A0(n717), .A1(n716), .B0(n1625), .Y(n715) );
OAI21XLTS U721 ( .A0(n925), .A1(n924), .B0(n1625), .Y(n923) );
OAI21XLTS U722 ( .A0(n1120), .A1(n1119), .B0(n1598), .Y(n1118) );
OAI21XLTS U723 ( .A0(n1093), .A1(n1092), .B0(n1598), .Y(n1091) );
OAI21XLTS U724 ( .A0(n842), .A1(n841), .B0(n402), .Y(n840) );
OAI21XLTS U725 ( .A0(n770), .A1(n769), .B0(n402), .Y(n768) );
OAI21XLTS U726 ( .A0(n1123), .A1(n1122), .B0(n591), .Y(n1121) );
OAI21XLTS U727 ( .A0(n959), .A1(n958), .B0(n1114), .Y(n957) );
OAI21XLTS U728 ( .A0(n965), .A1(n964), .B0(n400), .Y(n963) );
OAI21XLTS U729 ( .A0(n1215), .A1(n479), .B0(n466), .Y(n1216) );
OAI21XLTS U730 ( .A0(n956), .A1(n955), .B0(n1595), .Y(n954) );
OAI21XLTS U731 ( .A0(n1212), .A1(n479), .B0(n1441), .Y(n1213) );
OAI21XLTS U732 ( .A0(n1445), .A1(n690), .B0(n1598), .Y(n689) );
OAI21XLTS U733 ( .A0(n546), .A1(n479), .B0(n475), .Y(n1210) );
OAI21XLTS U734 ( .A0(n913), .A1(n912), .B0(n591), .Y(n911) );
OAI21XLTS U735 ( .A0(n1004), .A1(n1003), .B0(n591), .Y(n1002) );
OAI21XLTS U736 ( .A0(n1238), .A1(n1237), .B0(n1356), .Y(n1236) );
OAI21XLTS U737 ( .A0(n1234), .A1(n1626), .B0(n1225), .Y(n1223) );
OAI21XLTS U738 ( .A0(FSM_selector_B[0]), .A1(n1497), .B0(n1504), .Y(n1498)
);
OAI21XLTS U739 ( .A0(n1287), .A1(n1286), .B0(n1433), .Y(n1285) );
OAI21XLTS U740 ( .A0(n1283), .A1(n1282), .B0(n1433), .Y(n1281) );
OAI21XLTS U741 ( .A0(n1229), .A1(n1228), .B0(n411), .Y(n1227) );
OAI21XLTS U742 ( .A0(n1319), .A1(n1318), .B0(n1433), .Y(n1317) );
OAI211XLTS U743 ( .A0(n1463), .A1(n1459), .B0(n1458), .C0(n531), .Y(n1460)
);
NOR2XLTS U744 ( .A(Sgf_normalized_result[1]), .B(Sgf_normalized_result[0]),
.Y(n1350) );
OAI21XLTS U745 ( .A0(n1668), .A1(Sgf_normalized_result[23]), .B0(n1667), .Y(
n1669) );
OAI211XLTS U746 ( .A0(n1769), .A1(n1768), .B0(n1767), .C0(n1766), .Y(n1770)
);
OAI21XLTS U747 ( .A0(Sgf_normalized_result[1]), .A1(Sgf_normalized_result[0]), .B0(Sgf_normalized_result[2]), .Y(n1422) );
OAI211XLTS U748 ( .A0(n933), .A1(n1842), .B0(n819), .C0(n818), .Y(n202) );
OAI211XLTS U749 ( .A0(n933), .A1(n1835), .B0(n864), .C0(n863), .Y(n209) );
OAI211XLTS U750 ( .A0(n933), .A1(n1828), .B0(n742), .C0(n741), .Y(n216) );
NOR2X1TS U751 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]), .Y(
n1325) );
NAND3X2TS U752 ( .A(n1862), .B(n1325), .C(n1794), .Y(n550) );
BUFX3TS U753 ( .A(n550), .Y(n1864) );
INVX2TS U754 ( .A(rst), .Y(n167) );
BUFX3TS U755 ( .A(n167), .Y(n1884) );
BUFX3TS U756 ( .A(n167), .Y(n1886) );
BUFX3TS U757 ( .A(n167), .Y(n1885) );
CLKBUFX2TS U758 ( .A(n550), .Y(n568) );
BUFX3TS U759 ( .A(n568), .Y(n1873) );
BUFX3TS U760 ( .A(n568), .Y(n1874) );
BUFX3TS U761 ( .A(n568), .Y(n1875) );
BUFX3TS U762 ( .A(n550), .Y(n1878) );
BUFX3TS U763 ( .A(n550), .Y(n1863) );
BUFX3TS U764 ( .A(n568), .Y(n1869) );
BUFX3TS U765 ( .A(n550), .Y(n1866) );
BUFX3TS U766 ( .A(n550), .Y(n1877) );
BUFX3TS U767 ( .A(n167), .Y(n1883) );
BUFX3TS U768 ( .A(n568), .Y(n1870) );
BUFX3TS U769 ( .A(n568), .Y(n1871) );
BUFX3TS U770 ( .A(n550), .Y(n1876) );
NOR3X1TS U771 ( .A(Op_MX[20]), .B(Op_MX[22]), .C(Op_MX[21]), .Y(n1022) );
CLKBUFX2TS U772 ( .A(n1022), .Y(n551) );
CLKBUFX3TS U773 ( .A(n551), .Y(n1623) );
CLKBUFX3TS U774 ( .A(n1854), .Y(n1602) );
CLKBUFX3TS U775 ( .A(n1851), .Y(n1608) );
AOI21X1TS U776 ( .A0(n429), .A1(n1800), .B0(n1780), .Y(n634) );
INVX2TS U777 ( .A(n552), .Y(n771) );
AOI222X1TS U778 ( .A0(n1607), .A1(n1608), .B0(n1607), .B1(n771), .C0(n1608),
.C1(n771), .Y(n697) );
INVX2TS U779 ( .A(n553), .Y(n810) );
AOI222X1TS U780 ( .A0(n1600), .A1(n1602), .B0(n1600), .B1(n810), .C0(n1602),
.C1(n810), .Y(n691) );
OAI32X4TS U781 ( .A0(n478), .A1(n418), .A2(n888), .B0(Op_MY[22]), .B1(n478),
.Y(n1463) );
INVX2TS U782 ( .A(n419), .Y(n1584) );
CLKBUFX2TS U783 ( .A(n1847), .Y(n1114) );
CLKBUFX3TS U784 ( .A(n1114), .Y(n1593) );
OAI33X4TS U785 ( .A0(Op_MX[20]), .A1(Op_MX[21]), .A2(n548), .B0(n1593), .B1(
n1810), .B2(Op_MX[22]), .Y(n1586) );
OAI22X1TS U786 ( .A0(n1463), .A1(n1584), .B0(n1782), .B1(n391), .Y(n554) );
NAND2X1TS U787 ( .A(FS_Module_state_reg[3]), .B(n1790), .Y(n947) );
NOR2X2TS U788 ( .A(FS_Module_state_reg[0]), .B(n947), .Y(n1530) );
INVX2TS U789 ( .A(n1530), .Y(n565) );
NOR4X1TS U790 ( .A(P_Sgf[5]), .B(P_Sgf[4]), .C(P_Sgf[1]), .D(P_Sgf[0]), .Y(
n555) );
NAND3BXLTS U791 ( .AN(P_Sgf[3]), .B(n555), .C(n1843), .Y(n564) );
NOR4X1TS U792 ( .A(P_Sgf[14]), .B(P_Sgf[15]), .C(P_Sgf[16]), .D(P_Sgf[17]),
.Y(n559) );
NOR4X1TS U793 ( .A(P_Sgf[18]), .B(P_Sgf[19]), .C(P_Sgf[20]), .D(P_Sgf[21]),
.Y(n558) );
NOR4X1TS U794 ( .A(P_Sgf[10]), .B(P_Sgf[11]), .C(P_Sgf[12]), .D(P_Sgf[13]),
.Y(n557) );
NOR4X1TS U795 ( .A(P_Sgf[8]), .B(P_Sgf[7]), .C(P_Sgf[6]), .D(P_Sgf[9]), .Y(
n556) );
NAND4XLTS U796 ( .A(n559), .B(n558), .C(n557), .D(n556), .Y(n563) );
CLKXOR2X2TS U797 ( .A(Op_MX[31]), .B(Op_MY[31]), .Y(n948) );
INVX2TS U798 ( .A(round_mode[1]), .Y(n561) );
NAND3XLTS U799 ( .A(round_mode[0]), .B(n948), .C(n561), .Y(n560) );
OAI31X1TS U800 ( .A0(round_mode[0]), .A1(n948), .A2(n561), .B0(n560), .Y(
n562) );
OAI31X1TS U801 ( .A0(P_Sgf[22]), .A1(n564), .A2(n563), .B0(n562), .Y(n1529)
);
OAI31X1TS U802 ( .A0(FS_Module_state_reg[1]), .A1(n565), .A2(n1529), .B0(
n1802), .Y(n375) );
OR2X1TS U803 ( .A(exp_oper_result[8]), .B(Exp_module_Overflow_flag_A), .Y(
overflow_flag) );
NOR2X2TS U804 ( .A(FS_Module_state_reg[1]), .B(n1862), .Y(n1532) );
NAND3X1TS U805 ( .A(FS_Module_state_reg[3]), .B(n1532), .C(n1790), .Y(n1337)
);
CLKBUFX2TS U806 ( .A(n1337), .Y(n1491) );
OR3X1TS U807 ( .A(Sgf_normalized_result[2]), .B(Sgf_normalized_result[1]),
.C(Sgf_normalized_result[0]), .Y(n1643) );
NAND2X1TS U808 ( .A(Sgf_normalized_result[3]), .B(n1643), .Y(n1642) );
NAND2X1TS U809 ( .A(n1820), .B(n1642), .Y(n1646) );
NAND2X1TS U810 ( .A(Sgf_normalized_result[5]), .B(n1646), .Y(n1645) );
INVX2TS U811 ( .A(n1491), .Y(n1664) );
NAND2X1TS U812 ( .A(Sgf_normalized_result[7]), .B(n1336), .Y(n1340) );
OAI2BB1X1TS U813 ( .A0N(Add_result[7]), .A1N(n1337), .B0(n566), .Y(n302) );
NAND2X1TS U814 ( .A(Sgf_normalized_result[9]), .B(n1339), .Y(n1342) );
OAI2BB1X1TS U815 ( .A0N(Add_result[9]), .A1N(n1337), .B0(n567), .Y(n300) );
CLKBUFX2TS U816 ( .A(n568), .Y(n1879) );
INVX2TS U817 ( .A(n1329), .Y(DP_OP_32J138_122_6543_n33) );
BUFX3TS U818 ( .A(n408), .Y(n1906) );
OAI22X1TS U819 ( .A0(n1796), .A1(n1809), .B0(Op_MX[7]), .B1(Op_MX[6]), .Y(
n570) );
CLKBUFX3TS U820 ( .A(n402), .Y(n1626) );
OAI21XLTS U821 ( .A0(n412), .A1(n506), .B0(n404), .Y(n569) );
OAI31X4TS U822 ( .A0(n547), .A1(n404), .A2(n506), .B0(n569), .Y(n1023) );
NAND2BX2TS U823 ( .AN(n575), .B(n571), .Y(n1212) );
INVX2TS U824 ( .A(n1212), .Y(n910) );
OAI2BB2X1TS U825 ( .B0(n506), .B1(n535), .A0N(n1023), .A1N(n910), .Y(n574)
);
NAND3XLTS U826 ( .A(n571), .B(n575), .C(n570), .Y(n688) );
CLKBUFX2TS U827 ( .A(n688), .Y(n1441) );
OAI22X1TS U828 ( .A0(n428), .A1(n437), .B0(n1800), .B1(n1441), .Y(n573) );
OAI21XLTS U829 ( .A0(n574), .A1(n573), .B0(Op_MX[8]), .Y(n572) );
OAI31X1TS U830 ( .A0(n574), .A1(Op_MX[8]), .A2(n573), .B0(n572), .Y(n682) );
NOR2X2TS U831 ( .A(n413), .B(n575), .Y(n1220) );
CLKBUFX2TS U832 ( .A(n1849), .Y(n1598) );
INVX2TS U833 ( .A(n534), .Y(n1445) );
INVX2TS U834 ( .A(n939), .Y(n671) );
NAND2X1TS U835 ( .A(Op_MX[8]), .B(n665), .Y(n576) );
OR3X1TS U836 ( .A(n1220), .B(n1598), .C(n576), .Y(n681) );
NOR2X1TS U837 ( .A(n682), .B(n681), .Y(mult_x_19_n474) );
OAI22X1TS U838 ( .A0(n1806), .A1(Op_MX[13]), .B0(n1785), .B1(Op_MX[12]), .Y(
n580) );
INVX2TS U839 ( .A(n579), .Y(n578) );
NAND2X2TS U840 ( .A(n581), .B(n578), .Y(n1163) );
INVX2TS U841 ( .A(n1163), .Y(n724) );
NAND3XLTS U842 ( .A(Op_MX[14]), .B(n655), .C(n1515), .Y(n656) );
NOR3X2TS U843 ( .A(n581), .B(n580), .C(n579), .Y(n1454) );
AOI22X1TS U844 ( .A0(n427), .A1(n430), .B0(n1023), .B1(n724), .Y(n582) );
OAI21XLTS U845 ( .A0(n1780), .A1(n537), .B0(n582), .Y(n583) );
AOI21X1TS U846 ( .A0(n412), .A1(n1454), .B0(n583), .Y(n658) );
NAND2X1TS U847 ( .A(Op_MX[14]), .B(n658), .Y(n657) );
NOR2X1TS U848 ( .A(n656), .B(n657), .Y(mult_x_19_n441) );
CLKBUFX3TS U849 ( .A(n400), .Y(n1625) );
OAI22X1TS U850 ( .A0(n1805), .A1(Op_MX[19]), .B0(n1795), .B1(Op_MX[18]), .Y(
n587) );
INVX2TS U851 ( .A(n586), .Y(n585) );
NAND2X2TS U852 ( .A(n588), .B(n585), .Y(n982) );
INVX2TS U853 ( .A(n982), .Y(n711) );
NAND3XLTS U854 ( .A(Op_MX[20]), .B(n639), .C(n1507), .Y(n640) );
NOR3X2TS U855 ( .A(n588), .B(n587), .C(n586), .Y(n1465) );
AOI22X1TS U856 ( .A0(n427), .A1(n482), .B0(n1023), .B1(n711), .Y(n589) );
AOI21X1TS U857 ( .A0(n412), .A1(n1465), .B0(n590), .Y(n642) );
NAND2X1TS U858 ( .A(Op_MX[20]), .B(n642), .Y(n641) );
NOR2X1TS U859 ( .A(n640), .B(n641), .Y(mult_x_19_n390) );
CLKBUFX2TS U860 ( .A(n1849), .Y(n591) );
CLKBUFX3TS U861 ( .A(n591), .Y(n1882) );
INVX2TS U862 ( .A(n595), .Y(n593) );
CLKBUFX3TS U863 ( .A(n867), .Y(n814) );
OAI22X1TS U864 ( .A0(n1804), .A1(Op_MX[10]), .B0(n1793), .B1(Op_MX[9]), .Y(
n592) );
CLKAND2X2TS U865 ( .A(n592), .B(n593), .Y(n704) );
NOR3X2TS U866 ( .A(n594), .B(n592), .C(n595), .Y(n1449) );
NOR2X1TS U867 ( .A(n593), .B(n594), .Y(n598) );
AOI22X1TS U868 ( .A0(n412), .A1(n1449), .B0(n1023), .B1(n598), .Y(n597) );
NAND2X1TS U869 ( .A(n404), .B(n392), .Y(n596) );
NOR2X1TS U870 ( .A(n814), .B(n601), .Y(n599) );
INVX2TS U871 ( .A(n598), .Y(n1215) );
INVX2TS U872 ( .A(n704), .Y(n1447) );
OAI222X1TS U873 ( .A0(n1215), .A1(n939), .B0(n445), .B1(n506), .C0(n413),
.C1(n835), .Y(n1550) );
NOR3X1TS U874 ( .A(mult_x_19_n471), .B(n814), .C(n1550), .Y(n600) );
NAND2X1TS U875 ( .A(n599), .B(n600), .Y(n1517) );
AOI211X1TS U876 ( .A0(n1199), .A1(n601), .B0(n600), .C0(n599), .Y(n602) );
NOR2BX1TS U877 ( .AN(n1517), .B(n602), .Y(mult_x_19_n461) );
CLKBUFX2TS U878 ( .A(n1848), .Y(n603) );
CLKBUFX3TS U879 ( .A(n603), .Y(n1881) );
INVX2TS U880 ( .A(n607), .Y(n604) );
CLKBUFX3TS U881 ( .A(n400), .Y(n1193) );
OAI22X1TS U882 ( .A0(n1808), .A1(Op_MX[16]), .B0(n1784), .B1(Op_MX[15]), .Y(
n605) );
NOR3X2TS U883 ( .A(n606), .B(n605), .C(n607), .Y(n1456) );
NOR2X1TS U884 ( .A(n604), .B(n606), .Y(n610) );
AOI22X1TS U885 ( .A0(Op_MY[0]), .A1(n1456), .B0(n1023), .B1(n610), .Y(n609)
);
AOI2BB2XLTS U886 ( .B0(Op_MY[1]), .B1(n1190), .A0N(n429), .A1N(n532), .Y(
n608) );
NAND2X1TS U887 ( .A(n609), .B(n608), .Y(n613) );
NOR2X1TS U888 ( .A(n1625), .B(n613), .Y(n611) );
INVX2TS U889 ( .A(n610), .Y(n1459) );
CLKBUFX2TS U890 ( .A(n1459), .Y(n1205) );
OAI222X1TS U891 ( .A0(n1205), .A1(n939), .B0(n532), .B1(n1780), .C0(n413),
.C1(n449), .Y(n1548) );
NOR3X1TS U892 ( .A(mult_x_19_n435), .B(n1625), .C(n1548), .Y(n612) );
NAND2X1TS U893 ( .A(n611), .B(n612), .Y(n1509) );
CLKBUFX3TS U894 ( .A(n400), .Y(n1176) );
AOI211X1TS U895 ( .A0(n1176), .A1(n613), .B0(n612), .C0(n611), .Y(n614) );
NOR2BX1TS U896 ( .AN(n1509), .B(n614), .Y(mult_x_19_n419) );
CLKBUFX3TS U897 ( .A(n1847), .Y(n1880) );
NOR2X1TS U898 ( .A(n1800), .B(n615), .Y(mult_x_19_n381) );
INVX2TS U899 ( .A(mult_x_19_n381), .Y(n616) );
NAND2X1TS U900 ( .A(n616), .B(n617), .Y(n1547) );
OA21XLTS U901 ( .A0(n617), .A1(n616), .B0(n1547), .Y(mult_x_19_n370) );
BUFX3TS U902 ( .A(n1879), .Y(n1865) );
BUFX3TS U903 ( .A(n1879), .Y(n1867) );
CLKBUFX3TS U904 ( .A(n167), .Y(n1887) );
BUFX3TS U905 ( .A(n1879), .Y(n1872) );
BUFX3TS U906 ( .A(n1879), .Y(n1868) );
INVX2TS U907 ( .A(n478), .Y(n1469) );
INVX2TS U908 ( .A(n711), .Y(n1462) );
OAI22X1TS U909 ( .A0(n485), .A1(n519), .B0(n1469), .B1(n1462), .Y(n619) );
OAI21XLTS U910 ( .A0(n1461), .A1(n619), .B0(n1593), .Y(n618) );
OAI31X1TS U911 ( .A0(n1461), .A1(n1000), .A2(n619), .B0(n618), .Y(
mult_x_19_n618) );
CLKBUFX2TS U912 ( .A(n1205), .Y(n845) );
OAI22X1TS U913 ( .A0(n484), .A1(n464), .B0(n1469), .B1(n845), .Y(n621) );
OAI21XLTS U914 ( .A0(n1190), .A1(n621), .B0(n400), .Y(n620) );
OAI31X1TS U915 ( .A0(n1190), .A1(n1176), .A2(n621), .B0(n620), .Y(
mult_x_19_n645) );
CLKBUFX3TS U916 ( .A(n402), .Y(n891) );
CLKBUFX3TS U917 ( .A(n402), .Y(n1224) );
INVX2TS U918 ( .A(n622), .Y(n669) );
NOR3X2TS U919 ( .A(n669), .B(n396), .C(n661), .Y(n1437) );
OAI22X1TS U920 ( .A0(n545), .A1(n1469), .B0(n1209), .B1(n484), .Y(n624) );
OAI21XLTS U921 ( .A0(n394), .A1(n624), .B0(n1845), .Y(n623) );
OAI31X1TS U922 ( .A0(n394), .A1(n891), .A2(n624), .B0(n623), .Y(
mult_x_19_n753) );
CMPR32X2TS U923 ( .A(Op_MY[4]), .B(Op_MY[5]), .C(n625), .CO(n752), .S(n626)
);
INVX2TS U924 ( .A(n626), .Y(n1522) );
OAI22X1TS U925 ( .A0(n1788), .A1(n1204), .B0(n1522), .B1(n845), .Y(n629) );
OAI22X1TS U926 ( .A0(n498), .A1(n447), .B0(n1797), .B1(n533), .Y(n628) );
OAI21XLTS U927 ( .A0(n629), .A1(n628), .B0(n401), .Y(n627) );
OAI31X1TS U928 ( .A0(n629), .A1(n401), .A2(n628), .B0(n627), .Y(n1064) );
CMPR32X2TS U929 ( .A(Op_MY[3]), .B(Op_MY[4]), .C(n630), .CO(n625), .S(n1029)
);
INVX2TS U930 ( .A(n1029), .Y(n1226) );
OAI22X1TS U931 ( .A0(n428), .A1(n463), .B0(n1226), .B1(n845), .Y(n633) );
OAI22X1TS U932 ( .A0(n1788), .A1(n447), .B0(n1781), .B1(n531), .Y(n632) );
OAI21XLTS U933 ( .A0(n633), .A1(n632), .B0(n401), .Y(n631) );
OAI31X1TS U934 ( .A0(n633), .A1(Op_MX[17]), .A2(n632), .B0(n631), .Y(n1051)
);
CMPR32X2TS U935 ( .A(Op_MY[2]), .B(Op_MY[3]), .C(n634), .CO(n630), .S(n1028)
);
INVX2TS U936 ( .A(n1028), .Y(n1230) );
OAI22X1TS U937 ( .A0(n505), .A1(n464), .B0(n1230), .B1(n845), .Y(n637) );
OAI22X1TS U938 ( .A0(n1788), .A1(n532), .B0(n428), .B1(n449), .Y(n636) );
OAI21XLTS U939 ( .A0(n637), .A1(n636), .B0(n401), .Y(n635) );
OAI31X1TS U940 ( .A0(n637), .A1(n401), .A2(n636), .B0(n635), .Y(n1506) );
AO21XLTS U941 ( .A0(n1509), .A1(n1507), .B0(n1506), .Y(n1050) );
OAI21XLTS U942 ( .A0(n1000), .A1(n1507), .B0(n639), .Y(n638) );
OAI211XLTS U943 ( .A0(Op_MX[20]), .A1(n642), .B0(n641), .C0(n640), .Y(n643)
);
NAND2BXLTS U944 ( .AN(mult_x_19_n390), .B(n643), .Y(n1062) );
INVX2TS U945 ( .A(n644), .Y(mult_x_19_n388) );
CLKBUFX2TS U946 ( .A(n1215), .Y(n806) );
OAI22X1TS U947 ( .A0(n1788), .A1(n467), .B0(n1522), .B1(n806), .Y(n647) );
OAI22X1TS U948 ( .A0(n497), .A1(n1447), .B0(n1797), .B1(n446), .Y(n646) );
OAI21XLTS U949 ( .A0(n647), .A1(n646), .B0(n524), .Y(n645) );
OAI31X1TS U950 ( .A0(n647), .A1(Op_MX[11]), .A2(n646), .B0(n645), .Y(n1038)
);
OAI22X1TS U951 ( .A0(n428), .A1(n1214), .B0(n1226), .B1(n806), .Y(n650) );
OAI22X1TS U952 ( .A0(n500), .A1(n1447), .B0(n1781), .B1(n445), .Y(n649) );
OAI21XLTS U953 ( .A0(n650), .A1(n649), .B0(n524), .Y(n648) );
OAI31X1TS U954 ( .A0(n650), .A1(Op_MX[11]), .A2(n649), .B0(n648), .Y(n1086)
);
OAI22X1TS U955 ( .A0(n505), .A1(n466), .B0(n1230), .B1(n1215), .Y(n653) );
INVX2TS U956 ( .A(n704), .Y(n966) );
OAI22X1TS U957 ( .A0(n501), .A1(n445), .B0(n428), .B1(n835), .Y(n652) );
OAI21XLTS U958 ( .A0(n653), .A1(n652), .B0(n524), .Y(n651) );
OAI31X1TS U959 ( .A0(n653), .A1(Op_MX[11]), .A2(n652), .B0(n651), .Y(n1514)
);
AO21XLTS U960 ( .A0(n1517), .A1(n1515), .B0(n1514), .Y(n1085) );
OAI21XLTS U961 ( .A0(n1515), .A1(n1624), .B0(n655), .Y(n654) );
OAI211XLTS U962 ( .A0(Op_MX[14]), .A1(n658), .B0(n657), .C0(n656), .Y(n659)
);
NAND2BXLTS U963 ( .AN(mult_x_19_n441), .B(n659), .Y(n1036) );
INVX2TS U964 ( .A(n660), .Y(mult_x_19_n439) );
OAI22X1TS U965 ( .A0(n500), .A1(n475), .B0(n1439), .B1(n1522), .Y(n664) );
OAI22X1TS U966 ( .A0(n441), .A1(n512), .B0(n438), .B1(n498), .Y(n663) );
OAI21XLTS U967 ( .A0(n664), .A1(n663), .B0(n403), .Y(n662) );
OAI31X1TS U968 ( .A0(n664), .A1(n403), .A2(n663), .B0(n662), .Y(n1259) );
NAND2X1TS U969 ( .A(Op_MX[8]), .B(n1220), .Y(n666) );
XNOR2X1TS U970 ( .A(n666), .B(n665), .Y(n1249) );
AOI22X1TS U971 ( .A0(Op_MY[0]), .A1(n1437), .B0(n1023), .B1(n670), .Y(n667)
);
OAI21XLTS U972 ( .A0(n506), .A1(n439), .B0(n667), .Y(n668) );
AOI21X1TS U973 ( .A0(n404), .A1(n393), .B0(n668), .Y(n1221) );
NAND2X1TS U974 ( .A(n403), .B(n1221), .Y(n673) );
AOI222X4TS U975 ( .A0(Op_MY[1]), .A1(n393), .B0(Op_MY[0]), .B1(n394), .C0(
n671), .C1(n670), .Y(n1225) );
NAND2X1TS U976 ( .A(n1234), .B(n1225), .Y(n672) );
NOR2X1TS U977 ( .A(n673), .B(n672), .Y(n1218) );
OAI22X1TS U978 ( .A0(n506), .A1(n476), .B0(n1230), .B1(n545), .Y(n676) );
OAI22X1TS U979 ( .A0(n501), .A1(n441), .B0(n428), .B1(n440), .Y(n675) );
OAI21XLTS U980 ( .A0(n676), .A1(n675), .B0(n403), .Y(n674) );
OAI31X1TS U981 ( .A0(n676), .A1(Op_MX[5]), .A2(n675), .B0(n674), .Y(n677) );
INVX2TS U982 ( .A(n677), .Y(n1217) );
OAI21XLTS U983 ( .A0(n1218), .A1(n1220), .B0(n1217), .Y(n1248) );
OAI22X1TS U984 ( .A0(n428), .A1(n475), .B0(n1439), .B1(n1226), .Y(n680) );
OAI22X1TS U985 ( .A0(n500), .A1(n440), .B0(n441), .B1(n497), .Y(n679) );
OAI21XLTS U986 ( .A0(n680), .A1(n679), .B0(n403), .Y(n678) );
OAI31X1TS U987 ( .A0(n680), .A1(n403), .A2(n679), .B0(n678), .Y(n1247) );
AO21XLTS U988 ( .A0(n682), .A1(n681), .B0(mult_x_19_n474), .Y(n1257) );
INVX2TS U989 ( .A(n683), .Y(mult_x_19_n472) );
CMPR32X2TS U990 ( .A(Op_MY[12]), .B(Op_MY[11]), .C(n684), .CO(n787), .S(
n1073) );
INVX2TS U991 ( .A(n1073), .Y(n1272) );
OAI22X1TS U992 ( .A0(n541), .A1(n509), .B0(n982), .B1(n1272), .Y(n687) );
CLKBUFX3TS U993 ( .A(n1000), .Y(n1154) );
OAI22X1TS U994 ( .A0(n434), .A1(n514), .B0(n519), .B1(n1607), .Y(n686) );
OAI21XLTS U995 ( .A0(n687), .A1(n686), .B0(n1847), .Y(n685) );
OAI31X1TS U996 ( .A0(n687), .A1(n1154), .A2(n686), .B0(n685), .Y(
mult_x_19_n630) );
CLKBUFX3TS U997 ( .A(n688), .Y(n1127) );
INVX2TS U998 ( .A(n910), .Y(n1442) );
OAI22X1TS U999 ( .A0(n485), .A1(n1127), .B0(n1469), .B1(n1135), .Y(n690) );
OAI31X1TS U1000 ( .A0(n1445), .A1(n1128), .A2(n690), .B0(n689), .Y(
mult_x_19_n726) );
CLKBUFX3TS U1001 ( .A(n1854), .Y(n1291) );
CMPR32X2TS U1002 ( .A(Op_MY[16]), .B(Op_MY[17]), .C(n691), .CO(n705), .S(
n692) );
INVX2TS U1003 ( .A(n692), .Y(n1565) );
OAI22X1TS U1004 ( .A0(n466), .A1(n1291), .B0(n1215), .B1(n1565), .Y(n695) );
CLKBUFX3TS U1005 ( .A(n1855), .Y(n1307) );
CLKBUFX3TS U1006 ( .A(n1856), .Y(n1614) );
OAI22X1TS U1007 ( .A0(n1447), .A1(n1307), .B0(n444), .B1(n1614), .Y(n694) );
OAI21XLTS U1008 ( .A0(n695), .A1(n694), .B0(n1791), .Y(n693) );
OAI31X1TS U1009 ( .A0(n695), .A1(n1199), .A2(n694), .B0(n693), .Y(
mult_x_19_n706) );
CLKBUFX2TS U1010 ( .A(n1459), .Y(n696) );
CMPR32X2TS U1011 ( .A(Op_MY[10]), .B(Op_MY[11]), .C(n697), .CO(n684), .S(
n698) );
INVX2TS U1012 ( .A(n698), .Y(n1577) );
OAI22X1TS U1013 ( .A0(n463), .A1(n1851), .B0(n696), .B1(n1577), .Y(n701) );
OAI22X1TS U1014 ( .A0(n448), .A1(n1607), .B0(n531), .B1(n1778), .Y(n700) );
OAI21XLTS U1015 ( .A0(n701), .A1(n700), .B0(n1846), .Y(n699) );
OAI31X1TS U1016 ( .A0(n701), .A1(n1176), .A2(n700), .B0(n699), .Y(
mult_x_19_n658) );
OAI22X1TS U1017 ( .A0(n484), .A1(n467), .B0(n1469), .B1(n806), .Y(n703) );
OAI21XLTS U1018 ( .A0(n704), .A1(n703), .B0(n814), .Y(n702) );
OAI31X1TS U1019 ( .A0(n704), .A1(n1199), .A2(n703), .B0(n702), .Y(
mult_x_19_n699) );
CMPR32X2TS U1020 ( .A(Op_MY[18]), .B(Op_MY[17]), .C(n705), .CO(n839), .S(
n1077) );
INVX2TS U1021 ( .A(n1077), .Y(n1306) );
OAI22X1TS U1022 ( .A0(n538), .A1(n1856), .B0(n1163), .B1(n1306), .Y(n708) );
CLKBUFX3TS U1023 ( .A(n1624), .Y(n1187) );
OAI22X1TS U1024 ( .A0(n431), .A1(n1857), .B0(n1207), .B1(n1307), .Y(n707) );
CLKBUFX3TS U1025 ( .A(n603), .Y(n1595) );
OAI21XLTS U1026 ( .A0(n708), .A1(n707), .B0(n1595), .Y(n706) );
OAI31X1TS U1027 ( .A0(n708), .A1(n1187), .A2(n707), .B0(n706), .Y(
mult_x_19_n678) );
INVX2TS U1028 ( .A(n724), .Y(n1452) );
OAI22X1TS U1029 ( .A0(n485), .A1(n473), .B0(n1469), .B1(n1452), .Y(n710) );
OAI21XLTS U1030 ( .A0(n1451), .A1(n710), .B0(n1848), .Y(n709) );
OAI31X1TS U1031 ( .A0(n1451), .A1(n1881), .A2(n710), .B0(n709), .Y(
mult_x_19_n672) );
INVX2TS U1032 ( .A(n711), .Y(n1113) );
OAI22X1TS U1033 ( .A0(n539), .A1(n1607), .B0(n1462), .B1(n1577), .Y(n714) );
OAI22X1TS U1034 ( .A0(n433), .A1(n509), .B0(n520), .B1(n1608), .Y(n713) );
OAI21XLTS U1035 ( .A0(n714), .A1(n713), .B0(n1114), .Y(n712) );
OAI31X1TS U1036 ( .A0(n714), .A1(n1880), .A2(n713), .B0(n712), .Y(
mult_x_19_n631) );
OAI22X1TS U1037 ( .A0(n464), .A1(n1855), .B0(n696), .B1(n1306), .Y(n717) );
CLKBUFX3TS U1038 ( .A(n480), .Y(n1312) );
OAI22X1TS U1039 ( .A0(n449), .A1(n1856), .B0(n532), .B1(n1312), .Y(n716) );
OAI31X1TS U1040 ( .A0(n717), .A1(n1193), .A2(n716), .B0(n715), .Y(
mult_x_19_n651) );
OAI22X1TS U1041 ( .A0(n540), .A1(n1614), .B0(n982), .B1(n1306), .Y(n720) );
OAI22X1TS U1042 ( .A0(n433), .A1(n480), .B0(n521), .B1(n1600), .Y(n719) );
OAI21XLTS U1043 ( .A0(n720), .A1(n719), .B0(n1593), .Y(n718) );
OAI31X1TS U1044 ( .A0(n720), .A1(n1154), .A2(n719), .B0(n718), .Y(
mult_x_19_n624) );
OAI22X1TS U1045 ( .A0(n463), .A1(n1854), .B0(n696), .B1(n1565), .Y(n723) );
OAI22X1TS U1046 ( .A0(n448), .A1(n1855), .B0(n533), .B1(n1614), .Y(n722) );
OAI21XLTS U1047 ( .A0(n723), .A1(n722), .B0(n1625), .Y(n721) );
OAI31X1TS U1048 ( .A0(n723), .A1(n1193), .A2(n722), .B0(n721), .Y(
mult_x_19_n652) );
INVX2TS U1049 ( .A(n724), .Y(n1159) );
OAI22X1TS U1050 ( .A0(n536), .A1(n1855), .B0(n1452), .B1(n1565), .Y(n727) );
CLKBUFX2TS U1051 ( .A(n1856), .Y(n1599) );
OAI22X1TS U1052 ( .A0(n431), .A1(n1599), .B0(n1207), .B1(n1291), .Y(n726) );
OAI21XLTS U1053 ( .A0(n727), .A1(n726), .B0(n1595), .Y(n725) );
OAI31X1TS U1054 ( .A0(n727), .A1(n1187), .A2(n726), .B0(n725), .Y(
mult_x_19_n679) );
OAI22X1TS U1055 ( .A0(n541), .A1(n1855), .B0(n1113), .B1(n1565), .Y(n730) );
OAI22X1TS U1056 ( .A0(n434), .A1(n1599), .B0(n519), .B1(n1602), .Y(n729) );
OAI31X1TS U1057 ( .A0(n730), .A1(n1154), .A2(n729), .B0(n728), .Y(
mult_x_19_n625) );
AOI32X2TS U1058 ( .A0(FSM_add_overflow_flag), .A1(FS_Module_state_reg[1]),
.A2(n1530), .B0(n934), .B1(FS_Module_state_reg[1]), .Y(n1488) );
NOR2X1TS U1059 ( .A(FS_Module_state_reg[3]), .B(n1790), .Y(n751) );
INVX2TS U1060 ( .A(n734), .Y(n897) );
AOI22X1TS U1061 ( .A0(Sgf_normalized_result[20]), .A1(n885), .B0(
Add_result[21]), .B1(n544), .Y(n733) );
NAND2X1TS U1062 ( .A(n734), .B(n1488), .Y(n731) );
AOI22X1TS U1063 ( .A0(Add_result[20]), .A1(n453), .B0(n457), .B1(P_Sgf[43]),
.Y(n732) );
OAI211XLTS U1064 ( .A0(n1822), .A1(n488), .B0(n733), .C0(n732), .Y(n222) );
AOI22X1TS U1065 ( .A0(FSM_selector_C), .A1(Add_result[23]), .B0(P_Sgf[46]),
.B1(n1802), .Y(n1487) );
AOI22X1TS U1066 ( .A0(Sgf_normalized_result[22]), .A1(n1486), .B0(
Add_result[22]), .B1(n454), .Y(n736) );
NAND2X1TS U1067 ( .A(n930), .B(P_Sgf[45]), .Y(n735) );
OAI211XLTS U1068 ( .A0(n1488), .A1(n1487), .B0(n736), .C0(n735), .Y(n224) );
INVX2TS U1069 ( .A(n734), .Y(n885) );
AOI22X1TS U1070 ( .A0(Sgf_normalized_result[12]), .A1(n885), .B0(
Add_result[13]), .B1(n542), .Y(n738) );
AOI22X1TS U1071 ( .A0(Add_result[12]), .A1(n453), .B0(n458), .B1(P_Sgf[35]),
.Y(n737) );
OAI211XLTS U1072 ( .A0(n933), .A1(n1830), .B0(n738), .C0(n737), .Y(n214) );
AOI22X1TS U1073 ( .A0(Sgf_normalized_result[18]), .A1(n897), .B0(
Add_result[19]), .B1(n543), .Y(n740) );
AOI22X1TS U1074 ( .A0(Add_result[18]), .A1(n453), .B0(n930), .B1(P_Sgf[41]),
.Y(n739) );
OAI211XLTS U1075 ( .A0(n933), .A1(n1824), .B0(n740), .C0(n739), .Y(n220) );
AOI22X1TS U1076 ( .A0(Sgf_normalized_result[14]), .A1(n897), .B0(
Add_result[15]), .B1(n544), .Y(n742) );
AOI22X1TS U1077 ( .A0(Add_result[14]), .A1(n453), .B0(n458), .B1(P_Sgf[37]),
.Y(n741) );
AOI22X1TS U1078 ( .A0(Sgf_normalized_result[10]), .A1(n885), .B0(
Add_result[11]), .B1(n542), .Y(n744) );
AOI22X1TS U1079 ( .A0(Add_result[10]), .A1(n453), .B0(n930), .B1(P_Sgf[33]),
.Y(n743) );
OAI211XLTS U1080 ( .A0(n933), .A1(n1832), .B0(n744), .C0(n743), .Y(n212) );
AOI22X1TS U1081 ( .A0(Sgf_normalized_result[16]), .A1(n897), .B0(
Add_result[17]), .B1(n543), .Y(n746) );
AOI22X1TS U1082 ( .A0(Add_result[16]), .A1(n453), .B0(n458), .B1(P_Sgf[39]),
.Y(n745) );
OAI211XLTS U1083 ( .A0(n488), .A1(n1826), .B0(n746), .C0(n745), .Y(n218) );
AOI22X1TS U1084 ( .A0(Sgf_normalized_result[8]), .A1(n885), .B0(
Add_result[9]), .B1(n544), .Y(n748) );
AOI22X1TS U1085 ( .A0(Add_result[8]), .A1(n453), .B0(n930), .B1(P_Sgf[31]),
.Y(n747) );
OAI211XLTS U1086 ( .A0(n487), .A1(n1834), .B0(n748), .C0(n747), .Y(n210) );
AOI22X1TS U1087 ( .A0(Sgf_normalized_result[6]), .A1(n1486), .B0(
Add_result[7]), .B1(n542), .Y(n750) );
AOI22X1TS U1088 ( .A0(Add_result[6]), .A1(n455), .B0(n458), .B1(P_Sgf[29]),
.Y(n749) );
OAI211XLTS U1089 ( .A0(n488), .A1(n1836), .B0(n750), .C0(n749), .Y(n208) );
INVX2TS U1090 ( .A(n1491), .Y(n1495) );
NOR2X1TS U1091 ( .A(FS_Module_state_reg[2]), .B(n1794), .Y(n1534) );
NAND3X2TS U1092 ( .A(n1534), .B(n1860), .C(FS_Module_state_reg[0]), .Y(n1639) );
INVX2TS U1093 ( .A(n1639), .Y(n1641) );
NAND2X1TS U1094 ( .A(n1532), .B(n751), .Y(n1328) );
NAND2BXLTS U1095 ( .AN(n1328), .B(P_Sgf[47]), .Y(n908) );
OAI31X1TS U1096 ( .A0(n1495), .A1(n1641), .A2(n1801), .B0(n908), .Y(n235) );
CMPR32X2TS U1097 ( .A(Op_MY[6]), .B(Op_MY[5]), .C(n752), .CO(n757), .S(n753)
);
INVX2TS U1098 ( .A(n753), .Y(n1526) );
OAI22X1TS U1099 ( .A0(n546), .A1(n1526), .B0(n1781), .B1(n476), .Y(n756) );
OAI22X1TS U1100 ( .A0(n441), .A1(n518), .B0(n438), .B1(n511), .Y(n755) );
OAI21XLTS U1101 ( .A0(n756), .A1(n755), .B0(n1845), .Y(n754) );
OAI31X1TS U1102 ( .A0(n756), .A1(n891), .A2(n755), .B0(n754), .Y(
mult_x_19_n771) );
CMPR32X2TS U1103 ( .A(Op_MY[6]), .B(Op_MY[7]), .C(n757), .CO(n762), .S(n758)
);
INVX2TS U1104 ( .A(n758), .Y(n1511) );
OAI22X1TS U1105 ( .A0(n545), .A1(n1511), .B0(n1209), .B1(n512), .Y(n761) );
CLKBUFX2TS U1106 ( .A(n1850), .Y(n1609) );
OAI22X1TS U1107 ( .A0(n441), .A1(n1609), .B0(n438), .B1(n517), .Y(n760) );
OAI21XLTS U1108 ( .A0(n761), .A1(n760), .B0(n1845), .Y(n759) );
OAI31X1TS U1109 ( .A0(n761), .A1(n891), .A2(n760), .B0(n759), .Y(
mult_x_19_n770) );
CMPR32X2TS U1110 ( .A(Op_MY[7]), .B(Op_MY[8]), .C(n762), .CO(n766), .S(n1592) );
INVX2TS U1111 ( .A(n1592), .Y(n1253) );
OAI22X1TS U1112 ( .A0(n546), .A1(n1253), .B0(n1209), .B1(n518), .Y(n765) );
OAI22X1TS U1113 ( .A0(n441), .A1(n494), .B0(n438), .B1(n1609), .Y(n764) );
OAI21XLTS U1114 ( .A0(n765), .A1(n764), .B0(n1845), .Y(n763) );
OAI31X1TS U1115 ( .A0(n765), .A1(n891), .A2(n764), .B0(n763), .Y(
mult_x_19_n769) );
CMPR32X2TS U1116 ( .A(Op_MY[8]), .B(Op_MY[9]), .C(n766), .CO(n552), .S(n767)
);
INVX2TS U1117 ( .A(n767), .Y(n1583) );
OAI22X1TS U1118 ( .A0(n545), .A1(n1583), .B0(n1209), .B1(n1609), .Y(n770) );
OAI22X1TS U1119 ( .A0(n442), .A1(n1851), .B0(n438), .B1(n494), .Y(n769) );
OAI31X1TS U1120 ( .A0(n770), .A1(n891), .A2(n769), .B0(n768), .Y(
mult_x_19_n768) );
NOR2X1TS U1121 ( .A(Op_MY[10]), .B(n1608), .Y(n1540) );
AOI21X1TS U1122 ( .A0(Op_MY[10]), .A1(n1608), .B0(n1540), .Y(n1542) );
XNOR2X4TS U1123 ( .A(n1542), .B(n771), .Y(n1580) );
OAI22X1TS U1124 ( .A0(n1580), .A1(n1439), .B0(n1209), .B1(n495), .Y(n774) );
CLKBUFX3TS U1125 ( .A(n1851), .Y(n1264) );
OAI22X1TS U1126 ( .A0(n443), .A1(n1852), .B0(n438), .B1(n1264), .Y(n773) );
OAI21XLTS U1127 ( .A0(n774), .A1(n773), .B0(n1626), .Y(n772) );
OAI31X1TS U1128 ( .A0(n774), .A1(n891), .A2(n773), .B0(n772), .Y(
mult_x_19_n767) );
OAI22X1TS U1129 ( .A0(n546), .A1(n1577), .B0(n1209), .B1(n1608), .Y(n777) );
CLKBUFX3TS U1130 ( .A(n1852), .Y(n1268) );
OAI22X1TS U1131 ( .A0(n442), .A1(n509), .B0(n439), .B1(n1268), .Y(n776) );
OAI21XLTS U1132 ( .A0(n777), .A1(n776), .B0(n1626), .Y(n775) );
OAI31X1TS U1133 ( .A0(n777), .A1(n1224), .A2(n776), .B0(n775), .Y(
mult_x_19_n766) );
CLKBUFX3TS U1134 ( .A(n806), .Y(n1195) );
OAI22X1TS U1135 ( .A0(n498), .A1(n466), .B0(n1195), .B1(n1526), .Y(n780) );
OAI22X1TS U1136 ( .A0(n511), .A1(n1447), .B0(n517), .B1(n446), .Y(n779) );
OAI21XLTS U1137 ( .A0(n780), .A1(n779), .B0(n814), .Y(n778) );
OAI31X1TS U1138 ( .A0(n780), .A1(n1199), .A2(n779), .B0(n778), .Y(
mult_x_19_n717) );
OAI22X1TS U1139 ( .A0(n545), .A1(n1272), .B0(n476), .B1(n1268), .Y(n783) );
OAI22X1TS U1140 ( .A0(n443), .A1(n514), .B0(n440), .B1(n510), .Y(n782) );
OAI21XLTS U1141 ( .A0(n783), .A1(n782), .B0(n1626), .Y(n781) );
OAI31X1TS U1142 ( .A0(n783), .A1(n1224), .A2(n782), .B0(n781), .Y(
mult_x_19_n765) );
OAI22X1TS U1143 ( .A0(n512), .A1(n467), .B0(n1511), .B1(n806), .Y(n786) );
OAI22X1TS U1144 ( .A0(n1850), .A1(n446), .B0(n517), .B1(n966), .Y(n785) );
OAI21XLTS U1145 ( .A0(n786), .A1(n785), .B0(n814), .Y(n784) );
OAI31X1TS U1146 ( .A0(n786), .A1(n1199), .A2(n785), .B0(n784), .Y(
mult_x_19_n716) );
CMPR32X2TS U1147 ( .A(Op_MY[12]), .B(Op_MY[13]), .C(n787), .CO(n794), .S(
n1537) );
INVX2TS U1148 ( .A(n1537), .Y(n1280) );
OAI22X1TS U1149 ( .A0(n546), .A1(n1280), .B0(n475), .B1(n1778), .Y(n790) );
OAI22X1TS U1150 ( .A0(n442), .A1(n1853), .B0(n439), .B1(n1787), .Y(n789) );
OAI21XLTS U1151 ( .A0(n790), .A1(n789), .B0(n1626), .Y(n788) );
OAI31X1TS U1152 ( .A0(n790), .A1(n1224), .A2(n789), .B0(n788), .Y(
mult_x_19_n764) );
OAI22X1TS U1153 ( .A0(n1786), .A1(n466), .B0(n1253), .B1(n806), .Y(n793) );
CLKBUFX3TS U1154 ( .A(n1850), .Y(n1590) );
OAI22X1TS U1155 ( .A0(n1590), .A1(n1447), .B0(n495), .B1(n445), .Y(n792) );
OAI21XLTS U1156 ( .A0(n793), .A1(n792), .B0(n814), .Y(n791) );
OAI31X1TS U1157 ( .A0(n793), .A1(n867), .A2(n792), .B0(n791), .Y(
mult_x_19_n715) );
CMPR32X2TS U1158 ( .A(Op_MY[13]), .B(Op_MY[14]), .C(n794), .CO(n801), .S(
n1575) );
INVX2TS U1159 ( .A(n1575), .Y(n1284) );
OAI22X1TS U1160 ( .A0(n545), .A1(n1284), .B0(n476), .B1(n515), .Y(n797) );
CLKBUFX3TS U1161 ( .A(n1853), .Y(n1189) );
OAI22X1TS U1162 ( .A0(n443), .A1(n492), .B0(n440), .B1(n1189), .Y(n796) );
OAI21XLTS U1163 ( .A0(n797), .A1(n796), .B0(n1626), .Y(n795) );
OAI31X1TS U1164 ( .A0(n797), .A1(n1224), .A2(n796), .B0(n795), .Y(
mult_x_19_n763) );
OAI22X1TS U1165 ( .A0(n1590), .A1(n467), .B0(n1195), .B1(n1583), .Y(n800) );
OAI22X1TS U1166 ( .A0(n494), .A1(n1447), .B0(n444), .B1(n1264), .Y(n799) );
OAI21XLTS U1167 ( .A0(n800), .A1(n799), .B0(n814), .Y(n798) );
OAI31X1TS U1168 ( .A0(n800), .A1(n867), .A2(n799), .B0(n798), .Y(
mult_x_19_n714) );
CMPR32X2TS U1169 ( .A(Op_MY[14]), .B(Op_MY[15]), .C(n801), .CO(n553), .S(
n802) );
INVX2TS U1170 ( .A(n802), .Y(n1571) );
OAI22X1TS U1171 ( .A0(n546), .A1(n1571), .B0(n475), .B1(n1189), .Y(n805) );
OAI22X1TS U1172 ( .A0(n442), .A1(n1602), .B0(n439), .B1(n492), .Y(n804) );
OAI21XLTS U1173 ( .A0(n805), .A1(n804), .B0(n1845), .Y(n803) );
OAI31X1TS U1174 ( .A0(n805), .A1(n1224), .A2(n804), .B0(n803), .Y(
mult_x_19_n762) );
OAI22X1TS U1175 ( .A0(n1580), .A1(n806), .B0(n1775), .B1(n467), .Y(n809) );
OAI22X1TS U1176 ( .A0(n835), .A1(n1851), .B0(n444), .B1(n1268), .Y(n808) );
OAI21XLTS U1177 ( .A0(n809), .A1(n808), .B0(n814), .Y(n807) );
OAI31X1TS U1178 ( .A0(n809), .A1(n867), .A2(n808), .B0(n807), .Y(
mult_x_19_n713) );
AOI22X1TS U1179 ( .A0(Op_MY[16]), .A1(Op_MY[15]), .B0(n1291), .B1(n1600),
.Y(n1520) );
OAI22X1TS U1180 ( .A0(n1568), .A1(n1439), .B0(n476), .B1(n491), .Y(n813) );
OAI22X1TS U1181 ( .A0(n443), .A1(n1855), .B0(n440), .B1(n1291), .Y(n812) );
OAI21XLTS U1182 ( .A0(n813), .A1(n812), .B0(n1626), .Y(n811) );
OAI31X1TS U1183 ( .A0(n813), .A1(n1224), .A2(n812), .B0(n811), .Y(
mult_x_19_n761) );
OAI22X1TS U1184 ( .A0(n467), .A1(n1851), .B0(n1195), .B1(n1577), .Y(n817) );
OAI22X1TS U1185 ( .A0(n966), .A1(n1268), .B0(n444), .B1(n510), .Y(n816) );
OAI31X1TS U1186 ( .A0(n817), .A1(n867), .A2(n816), .B0(n815), .Y(
mult_x_19_n712) );
AOI22X1TS U1187 ( .A0(Sgf_normalized_result[0]), .A1(n897), .B0(n542), .B1(
Add_result[1]), .Y(n819) );
AOI22X1TS U1188 ( .A0(n457), .A1(P_Sgf[23]), .B0(n454), .B1(Add_result[0]),
.Y(n818) );
OAI22X1TS U1189 ( .A0(n545), .A1(n1565), .B0(n475), .B1(n1291), .Y(n822) );
OAI22X1TS U1190 ( .A0(n442), .A1(n1856), .B0(n439), .B1(n1307), .Y(n821) );
OAI21XLTS U1191 ( .A0(n822), .A1(n821), .B0(n1845), .Y(n820) );
OAI31X1TS U1192 ( .A0(n822), .A1(n1224), .A2(n821), .B0(n820), .Y(
mult_x_19_n760) );
OAI22X1TS U1193 ( .A0(n497), .A1(n463), .B0(n696), .B1(n1526), .Y(n825) );
OAI22X1TS U1194 ( .A0(n511), .A1(n447), .B0(n517), .B1(n532), .Y(n824) );
OAI21XLTS U1195 ( .A0(n825), .A1(n824), .B0(n1846), .Y(n823) );
OAI31X1TS U1196 ( .A0(n825), .A1(n1176), .A2(n824), .B0(n823), .Y(
mult_x_19_n663) );
OAI22X1TS U1197 ( .A0(n466), .A1(n1852), .B0(n1195), .B1(n1272), .Y(n828) );
OAI22X1TS U1198 ( .A0(n835), .A1(n509), .B0(n444), .B1(n1787), .Y(n827) );
OAI21XLTS U1199 ( .A0(n828), .A1(n827), .B0(n1791), .Y(n826) );
OAI31X1TS U1200 ( .A0(n828), .A1(n867), .A2(n827), .B0(n826), .Y(
mult_x_19_n711) );
OAI22X1TS U1201 ( .A0(n546), .A1(n1306), .B0(n476), .B1(n1307), .Y(n831) );
OAI22X1TS U1202 ( .A0(n443), .A1(n480), .B0(n440), .B1(n1599), .Y(n830) );
OAI21XLTS U1203 ( .A0(n831), .A1(n830), .B0(n402), .Y(n829) );
OAI31X1TS U1204 ( .A0(n831), .A1(n891), .A2(n830), .B0(n829), .Y(
mult_x_19_n759) );
OAI22X1TS U1205 ( .A0(n512), .A1(n464), .B0(n1511), .B1(n845), .Y(n834) );
OAI22X1TS U1206 ( .A0(n1590), .A1(n533), .B0(n517), .B1(n448), .Y(n833) );
OAI21XLTS U1207 ( .A0(n834), .A1(n833), .B0(n1846), .Y(n832) );
OAI31X1TS U1208 ( .A0(n834), .A1(n1176), .A2(n833), .B0(n832), .Y(
mult_x_19_n662) );
OAI22X1TS U1209 ( .A0(n467), .A1(n509), .B0(n1195), .B1(n1280), .Y(n838) );
OAI22X1TS U1210 ( .A0(n966), .A1(n514), .B0(n444), .B1(n1189), .Y(n837) );
CLKBUFX2TS U1211 ( .A(n1791), .Y(n1196) );
OAI31X1TS U1212 ( .A0(n838), .A1(n867), .A2(n837), .B0(n836), .Y(
mult_x_19_n710) );
OAI22X1TS U1213 ( .A0(n442), .A1(n507), .B0(n475), .B1(n1614), .Y(n842) );
CMPR32X2TS U1214 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(n839), .CO(n854), .S(
n1563) );
INVX2TS U1215 ( .A(n1563), .Y(n1311) );
OAI22X1TS U1216 ( .A0(n439), .A1(n480), .B0(n1439), .B1(n1311), .Y(n841) );
OAI31X1TS U1217 ( .A0(n842), .A1(n1224), .A2(n841), .B0(n840), .Y(
mult_x_19_n758) );
AOI22X1TS U1218 ( .A0(Sgf_normalized_result[1]), .A1(n1486), .B0(n543), .B1(
Add_result[2]), .Y(n844) );
AOI22X1TS U1219 ( .A0(n457), .A1(P_Sgf[24]), .B0(n455), .B1(Add_result[1]),
.Y(n843) );
OAI211XLTS U1220 ( .A0(n487), .A1(n1841), .B0(n844), .C0(n843), .Y(n203) );
OAI22X1TS U1221 ( .A0(n518), .A1(n463), .B0(n1253), .B1(n845), .Y(n848) );
OAI22X1TS U1222 ( .A0(n1590), .A1(n447), .B0(n1775), .B1(n533), .Y(n847) );
OAI31X1TS U1223 ( .A0(n848), .A1(n1176), .A2(n847), .B0(n846), .Y(
mult_x_19_n661) );
OAI22X1TS U1224 ( .A0(n466), .A1(n514), .B0(n1195), .B1(n1284), .Y(n851) );
CLKBUFX2TS U1225 ( .A(n1853), .Y(n1605) );
OAI22X1TS U1226 ( .A0(n1447), .A1(n1605), .B0(n445), .B1(n492), .Y(n850) );
OAI21XLTS U1227 ( .A0(n851), .A1(n850), .B0(n1791), .Y(n849) );
OAI31X1TS U1228 ( .A0(n851), .A1(n867), .A2(n850), .B0(n849), .Y(
mult_x_19_n709) );
AOI22X1TS U1229 ( .A0(Sgf_normalized_result[3]), .A1(n1486), .B0(n544), .B1(
Add_result[4]), .Y(n853) );
AOI22X1TS U1230 ( .A0(n457), .A1(P_Sgf[26]), .B0(n454), .B1(Add_result[3]),
.Y(n852) );
OAI211XLTS U1231 ( .A0(n488), .A1(n1839), .B0(n853), .C0(n852), .Y(n205) );
OAI22X1TS U1232 ( .A0(n443), .A1(n502), .B0(n476), .B1(n1312), .Y(n857) );
CMPR32X2TS U1233 ( .A(Op_MY[19]), .B(Op_MY[20]), .C(n854), .CO(n871), .S(
n1560) );
INVX2TS U1234 ( .A(n1560), .Y(n1316) );
OAI22X1TS U1235 ( .A0(n440), .A1(n507), .B0(n1439), .B1(n1316), .Y(n856) );
OAI21XLTS U1236 ( .A0(n857), .A1(n856), .B0(n1845), .Y(n855) );
OAI31X1TS U1237 ( .A0(n857), .A1(n891), .A2(n856), .B0(n855), .Y(
mult_x_19_n757) );
AOI22X1TS U1238 ( .A0(Sgf_normalized_result[5]), .A1(n1486), .B0(
Add_result[6]), .B1(n543), .Y(n859) );
AOI22X1TS U1239 ( .A0(n457), .A1(P_Sgf[28]), .B0(n455), .B1(Add_result[5]),
.Y(n858) );
OAI211XLTS U1240 ( .A0(n487), .A1(n1837), .B0(n859), .C0(n858), .Y(n207) );
OAI22X1TS U1241 ( .A0(n1590), .A1(n464), .B0(n1459), .B1(n1583), .Y(n862) );
OAI22X1TS U1242 ( .A0(n495), .A1(n447), .B0(n531), .B1(n1264), .Y(n861) );
OAI21XLTS U1243 ( .A0(n862), .A1(n861), .B0(n400), .Y(n860) );
OAI31X1TS U1244 ( .A0(n862), .A1(n1176), .A2(n861), .B0(n860), .Y(
mult_x_19_n660) );
AOI22X1TS U1245 ( .A0(Sgf_normalized_result[7]), .A1(n1486), .B0(
Add_result[8]), .B1(n544), .Y(n864) );
AOI22X1TS U1246 ( .A0(Add_result[7]), .A1(n454), .B0(n930), .B1(P_Sgf[30]),
.Y(n863) );
OAI22X1TS U1247 ( .A0(n467), .A1(n1605), .B0(n1195), .B1(n1571), .Y(n868) );
OAI22X1TS U1248 ( .A0(n835), .A1(n1776), .B0(n446), .B1(n1291), .Y(n866) );
OAI21XLTS U1249 ( .A0(n868), .A1(n866), .B0(n1196), .Y(n865) );
OAI31X1TS U1250 ( .A0(n868), .A1(n867), .A2(n866), .B0(n865), .Y(
mult_x_19_n708) );
AOI22X1TS U1251 ( .A0(Sgf_normalized_result[9]), .A1(n885), .B0(
Add_result[10]), .B1(n542), .Y(n870) );
AOI22X1TS U1252 ( .A0(Add_result[9]), .A1(n455), .B0(n458), .B1(P_Sgf[32]),
.Y(n869) );
OAI211XLTS U1253 ( .A0(n488), .A1(n1833), .B0(n870), .C0(n869), .Y(n211) );
OAI22X1TS U1254 ( .A0(n442), .A1(n423), .B0(n475), .B1(n508), .Y(n874) );
INVX2TS U1255 ( .A(n1557), .Y(n1373) );
OAI22X1TS U1256 ( .A0(n439), .A1(n502), .B0(n1439), .B1(n1373), .Y(n873) );
OAI21XLTS U1257 ( .A0(n874), .A1(n873), .B0(n1845), .Y(n872) );
OAI31X1TS U1258 ( .A0(n874), .A1(n891), .A2(n873), .B0(n872), .Y(
mult_x_19_n756) );
AOI22X1TS U1259 ( .A0(Sgf_normalized_result[11]), .A1(n897), .B0(
Add_result[12]), .B1(n543), .Y(n876) );
AOI22X1TS U1260 ( .A0(Add_result[11]), .A1(n454), .B0(n930), .B1(P_Sgf[34]),
.Y(n875) );
OAI211XLTS U1261 ( .A0(n487), .A1(n1831), .B0(n876), .C0(n875), .Y(n213) );
OAI22X1TS U1262 ( .A0(n1580), .A1(n1205), .B0(n1775), .B1(n464), .Y(n879) );
OAI22X1TS U1263 ( .A0(n449), .A1(n1851), .B0(n532), .B1(n1268), .Y(n878) );
OAI21XLTS U1264 ( .A0(n879), .A1(n878), .B0(n1846), .Y(n877) );
OAI31X1TS U1265 ( .A0(n879), .A1(n1176), .A2(n878), .B0(n877), .Y(
mult_x_19_n659) );
AOI22X1TS U1266 ( .A0(Sgf_normalized_result[13]), .A1(n885), .B0(
Add_result[14]), .B1(n544), .Y(n881) );
AOI22X1TS U1267 ( .A0(Add_result[13]), .A1(n455), .B0(n458), .B1(P_Sgf[36]),
.Y(n880) );
OAI211XLTS U1268 ( .A0(n488), .A1(n1829), .B0(n881), .C0(n880), .Y(n215) );
OAI22X1TS U1269 ( .A0(n1568), .A1(n1215), .B0(n1214), .B1(n491), .Y(n884) );
OAI22X1TS U1270 ( .A0(n966), .A1(n1854), .B0(n445), .B1(n1307), .Y(n883) );
OAI21XLTS U1271 ( .A0(n884), .A1(n883), .B0(n1196), .Y(n882) );
OAI31X1TS U1272 ( .A0(n884), .A1(n1791), .A2(n883), .B0(n882), .Y(
mult_x_19_n707) );
AOI22X1TS U1273 ( .A0(Sgf_normalized_result[15]), .A1(n897), .B0(
Add_result[16]), .B1(n542), .Y(n887) );
AOI22X1TS U1274 ( .A0(Add_result[15]), .A1(n454), .B0(n930), .B1(P_Sgf[38]),
.Y(n886) );
OAI211XLTS U1275 ( .A0(n487), .A1(n1827), .B0(n887), .C0(n886), .Y(n217) );
OAI22X1TS U1276 ( .A0(n443), .A1(n484), .B0(n476), .B1(n1798), .Y(n892) );
OAI22X1TS U1277 ( .A0(n1553), .A1(n546), .B0(n439), .B1(n424), .Y(n890) );
OAI21XLTS U1278 ( .A0(n892), .A1(n890), .B0(n402), .Y(n889) );
OAI31X1TS U1279 ( .A0(n892), .A1(n891), .A2(n890), .B0(n889), .Y(
mult_x_19_n755) );
AOI22X1TS U1280 ( .A0(Sgf_normalized_result[17]), .A1(n885), .B0(
Add_result[18]), .B1(n543), .Y(n894) );
AOI22X1TS U1281 ( .A0(Add_result[17]), .A1(n455), .B0(n458), .B1(P_Sgf[40]),
.Y(n893) );
OAI211XLTS U1282 ( .A0(n488), .A1(n1825), .B0(n894), .C0(n893), .Y(n219) );
AOI22X1TS U1283 ( .A0(Sgf_normalized_result[19]), .A1(n897), .B0(
Add_result[20]), .B1(n544), .Y(n896) );
AOI22X1TS U1284 ( .A0(Add_result[19]), .A1(n454), .B0(n457), .B1(P_Sgf[42]),
.Y(n895) );
OAI211XLTS U1285 ( .A0(n487), .A1(n1823), .B0(n896), .C0(n895), .Y(n221) );
AOI22X1TS U1286 ( .A0(Sgf_normalized_result[21]), .A1(n885), .B0(
Add_result[22]), .B1(n542), .Y(n899) );
AOI22X1TS U1287 ( .A0(Add_result[21]), .A1(n455), .B0(n458), .B1(P_Sgf[44]),
.Y(n898) );
OAI211XLTS U1288 ( .A0(n1821), .A1(n487), .B0(n899), .C0(n898), .Y(n223) );
OAI22X1TS U1289 ( .A0(n494), .A1(n539), .B0(n982), .B1(n1583), .Y(n902) );
OAI22X1TS U1290 ( .A0(n1590), .A1(n520), .B0(n433), .B1(n1264), .Y(n901) );
OAI31X1TS U1291 ( .A0(n902), .A1(n1880), .A2(n901), .B0(n900), .Y(
mult_x_19_n633) );
AOI22X1TS U1292 ( .A0(Sgf_normalized_result[2]), .A1(n1486), .B0(n542), .B1(
Add_result[3]), .Y(n904) );
AOI22X1TS U1293 ( .A0(n457), .A1(P_Sgf[25]), .B0(n454), .B1(Add_result[2]),
.Y(n903) );
OAI211XLTS U1294 ( .A0(n488), .A1(n1840), .B0(n904), .C0(n903), .Y(n204) );
OAI22X1TS U1295 ( .A0(n537), .A1(n1776), .B0(n1163), .B1(n1571), .Y(n907) );
OAI22X1TS U1296 ( .A0(n432), .A1(n1854), .B0(n1207), .B1(n1189), .Y(n906) );
OAI21XLTS U1297 ( .A0(n907), .A1(n906), .B0(n1595), .Y(n905) );
OAI31X1TS U1298 ( .A0(n907), .A1(n1187), .A2(n906), .B0(n905), .Y(
mult_x_19_n681) );
AOI211X1TS U1299 ( .A0(n908), .A1(FSM_selector_B[0]), .B0(n1641), .C0(n1495),
.Y(n909) );
INVX2TS U1300 ( .A(n909), .Y(n236) );
OAI22X1TS U1301 ( .A0(n423), .A1(n436), .B0(n534), .B1(n503), .Y(n913) );
CLKBUFX3TS U1302 ( .A(n1441), .Y(n1137) );
INVX2TS U1303 ( .A(n910), .Y(n1135) );
OAI22X1TS U1304 ( .A0(n1137), .A1(n507), .B0(n1135), .B1(n1373), .Y(n912) );
OAI31X1TS U1305 ( .A0(n913), .A1(n1128), .A2(n912), .B0(n911), .Y(
mult_x_19_n729) );
OAI22X1TS U1306 ( .A0(n1580), .A1(n982), .B0(n540), .B1(n1608), .Y(n916) );
OAI22X1TS U1307 ( .A0(n495), .A1(n521), .B0(n433), .B1(n1607), .Y(n915) );
OAI21XLTS U1308 ( .A0(n916), .A1(n915), .B0(n1847), .Y(n914) );
OAI31X1TS U1309 ( .A0(n916), .A1(n1880), .A2(n915), .B0(n914), .Y(
mult_x_19_n632) );
OAI22X1TS U1310 ( .A0(n1568), .A1(n1452), .B0(n537), .B1(n1291), .Y(n919) );
OAI22X1TS U1311 ( .A0(n1184), .A1(n1855), .B0(n1207), .B1(n492), .Y(n918) );
OAI21XLTS U1312 ( .A0(n919), .A1(n918), .B0(n1595), .Y(n917) );
OAI31X1TS U1313 ( .A0(n919), .A1(n1187), .A2(n918), .B0(n917), .Y(
mult_x_19_n680) );
OAI22X1TS U1314 ( .A0(n423), .A1(n534), .B0(n1782), .B1(n437), .Y(n922) );
CLKBUFX3TS U1315 ( .A(n1128), .Y(n1140) );
OAI22X1TS U1316 ( .A0(n1553), .A1(n1135), .B0(n1127), .B1(n1798), .Y(n921)
);
OAI21XLTS U1317 ( .A0(n922), .A1(n921), .B0(n1598), .Y(n920) );
OAI31X1TS U1318 ( .A0(n922), .A1(n1140), .A2(n921), .B0(n920), .Y(
mult_x_19_n728) );
OAI22X1TS U1319 ( .A0(n464), .A1(n1189), .B0(n1459), .B1(n1571), .Y(n925) );
OAI22X1TS U1320 ( .A0(n448), .A1(n1776), .B0(n533), .B1(n1602), .Y(n924) );
OAI31X1TS U1321 ( .A0(n925), .A1(n1193), .A2(n924), .B0(n923), .Y(
mult_x_19_n654) );
OAI22X1TS U1322 ( .A0(n423), .A1(n445), .B0(n1214), .B1(n1779), .Y(n928) );
OAI22X1TS U1323 ( .A0(n835), .A1(n502), .B0(n1195), .B1(n1373), .Y(n927) );
OAI21XLTS U1324 ( .A0(n928), .A1(n927), .B0(n1196), .Y(n926) );
OAI31X1TS U1325 ( .A0(n928), .A1(n1199), .A2(n927), .B0(n926), .Y(
mult_x_19_n702) );
AOI22X1TS U1326 ( .A0(Sgf_normalized_result[4]), .A1(n1486), .B0(n543), .B1(
Add_result[5]), .Y(n932) );
AOI22X1TS U1327 ( .A0(n457), .A1(P_Sgf[27]), .B0(n455), .B1(Add_result[4]),
.Y(n931) );
OAI211XLTS U1328 ( .A0(n487), .A1(n1838), .B0(n932), .C0(n931), .Y(n206) );
AOI31X4TS U1329 ( .A0(n1530), .A1(FS_Module_state_reg[1]), .A2(
FSM_add_overflow_flag), .B0(n934), .Y(n1692) );
NOR3X2TS U1330 ( .A(n410), .B(Op_MX[0]), .C(Op_MX[1]), .Y(n1427) );
NOR2X1TS U1331 ( .A(n1783), .B(n935), .Y(n938) );
AOI22X1TS U1332 ( .A0(n1427), .A1(n412), .B0(n938), .B1(n1023), .Y(n937) );
NOR2X2TS U1333 ( .A(n1777), .B(Op_MX[0]), .Y(n1436) );
OA22X1TS U1334 ( .A0(n470), .A1(n505), .B0(n529), .B1(n429), .Y(n936) );
NAND2X1TS U1335 ( .A(n937), .B(n936), .Y(n942) );
NOR2X1TS U1336 ( .A(n1844), .B(n942), .Y(n940) );
NAND2X1TS U1337 ( .A(n940), .B(n941), .Y(n1235) );
INVX2TS U1338 ( .A(n1235), .Y(n944) );
AOI211X1TS U1339 ( .A0(n410), .A1(n942), .B0(n941), .C0(n940), .Y(n943) );
INVX2TS U1340 ( .A(n1691), .Y(n1767) );
NAND2X1TS U1341 ( .A(FS_Module_state_reg[2]), .B(FS_Module_state_reg[3]),
.Y(n1531) );
NOR3X1TS U1342 ( .A(FS_Module_state_reg[1]), .B(FS_Module_state_reg[0]), .C(
n1531), .Y(ready) );
INVX2TS U1343 ( .A(ready), .Y(n945) );
OAI21XLTS U1344 ( .A0(n1790), .A1(n1327), .B0(FS_Module_state_reg[3]), .Y(
n946) );
OAI211XLTS U1345 ( .A0(n1807), .A1(n1329), .B0(n1486), .C0(n946), .Y(n380)
);
CLKBUFX3TS U1346 ( .A(n1331), .Y(n1773) );
NOR2XLTS U1347 ( .A(n948), .B(underflow_flag), .Y(n949) );
AOI22X1TS U1348 ( .A0(DP_OP_32J138_122_6543_n33), .A1(n1807), .B0(n1790),
.B1(n1862), .Y(n950) );
OAI22X1TS U1349 ( .A0(n950), .A1(n1327), .B0(P_Sgf[47]), .B1(n1328), .Y(n379) );
OAI22X1TS U1350 ( .A0(n424), .A1(n540), .B0(n1782), .B1(n434), .Y(n953) );
OAI22X1TS U1351 ( .A0(n1553), .A1(n1462), .B0(n520), .B1(n503), .Y(n952) );
OAI21XLTS U1352 ( .A0(n953), .A1(n952), .B0(n1593), .Y(n951) );
OAI31X1TS U1353 ( .A0(n953), .A1(n1154), .A2(n952), .B0(n951), .Y(
mult_x_19_n620) );
OAI22X1TS U1354 ( .A0(n424), .A1(n431), .B0(n538), .B1(n1798), .Y(n956) );
OAI22X1TS U1355 ( .A0(n1159), .A1(n1373), .B0(n1207), .B1(n508), .Y(n955) );
OAI31X1TS U1356 ( .A0(n956), .A1(n1881), .A2(n955), .B0(n954), .Y(
mult_x_19_n675) );
OAI22X1TS U1357 ( .A0(n424), .A1(n433), .B0(n541), .B1(n503), .Y(n959) );
OAI22X1TS U1358 ( .A0(n1113), .A1(n1373), .B0(n521), .B1(n1779), .Y(n958) );
OAI31X1TS U1359 ( .A0(n959), .A1(n1000), .A2(n958), .B0(n957), .Y(
mult_x_19_n621) );
OAI22X1TS U1360 ( .A0(n1568), .A1(n1205), .B0(n1204), .B1(n491), .Y(n962) );
OAI22X1TS U1361 ( .A0(n449), .A1(n1854), .B0(n531), .B1(n1600), .Y(n961) );
OAI21XLTS U1362 ( .A0(n962), .A1(n961), .B0(n1625), .Y(n960) );
OAI31X1TS U1363 ( .A0(n962), .A1(n1193), .A2(n961), .B0(n960), .Y(
mult_x_19_n653) );
OAI22X1TS U1364 ( .A0(n484), .A1(n531), .B0(n1204), .B1(n1798), .Y(n965) );
OAI22X1TS U1365 ( .A0(n1553), .A1(n1205), .B0(n423), .B1(n448), .Y(n964) );
OAI31X1TS U1366 ( .A0(n965), .A1(n1176), .A2(n964), .B0(n963), .Y(
mult_x_19_n647) );
OAI22X1TS U1367 ( .A0(n485), .A1(n446), .B0(n1214), .B1(n503), .Y(n969) );
OAI22X1TS U1368 ( .A0(n1553), .A1(n1215), .B0(n423), .B1(n835), .Y(n968) );
OAI21XLTS U1369 ( .A0(n969), .A1(n968), .B0(n1791), .Y(n967) );
OAI31X1TS U1370 ( .A0(n969), .A1(n1791), .A2(n968), .B0(n967), .Y(
mult_x_19_n701) );
OAI22X1TS U1371 ( .A0(n424), .A1(n532), .B0(n1204), .B1(n508), .Y(n972) );
OAI22X1TS U1372 ( .A0(n448), .A1(n502), .B0(n696), .B1(n1373), .Y(n971) );
OAI21XLTS U1373 ( .A0(n972), .A1(n971), .B0(n400), .Y(n970) );
OAI31X1TS U1374 ( .A0(n972), .A1(n1193), .A2(n971), .B0(n970), .Y(
mult_x_19_n648) );
OAI22X1TS U1375 ( .A0(n424), .A1(n536), .B0(n1782), .B1(n432), .Y(n975) );
OAI22X1TS U1376 ( .A0(n1553), .A1(n1159), .B0(n1207), .B1(n1798), .Y(n974)
);
OAI21XLTS U1377 ( .A0(n975), .A1(n974), .B0(n1595), .Y(n973) );
OAI31X1TS U1378 ( .A0(n975), .A1(n1881), .A2(n974), .B0(n973), .Y(
mult_x_19_n674) );
OAI22X1TS U1379 ( .A0(n1568), .A1(n1113), .B0(n539), .B1(n1602), .Y(n978) );
OAI22X1TS U1380 ( .A0(n433), .A1(n1855), .B0(n519), .B1(n492), .Y(n977) );
OAI21XLTS U1381 ( .A0(n978), .A1(n977), .B0(n1847), .Y(n976) );
OAI31X1TS U1382 ( .A0(n978), .A1(n1154), .A2(n977), .B0(n976), .Y(
mult_x_19_n626) );
OAI22X1TS U1383 ( .A0(n539), .A1(n1776), .B0(n982), .B1(n1571), .Y(n981) );
OAI22X1TS U1384 ( .A0(n434), .A1(n1854), .B0(n520), .B1(n1605), .Y(n980) );
OAI21XLTS U1385 ( .A0(n981), .A1(n980), .B0(n1847), .Y(n979) );
OAI31X1TS U1386 ( .A0(n981), .A1(n1154), .A2(n980), .B0(n979), .Y(
mult_x_19_n627) );
OAI22X1TS U1387 ( .A0(n540), .A1(n1189), .B0(n982), .B1(n1284), .Y(n985) );
OAI22X1TS U1388 ( .A0(n1151), .A1(n1776), .B0(n521), .B1(n515), .Y(n984) );
OAI21XLTS U1389 ( .A0(n985), .A1(n984), .B0(n1847), .Y(n983) );
OAI31X1TS U1390 ( .A0(n985), .A1(n1154), .A2(n984), .B0(n983), .Y(
mult_x_19_n628) );
OAI22X1TS U1391 ( .A0(n463), .A1(n514), .B0(n1205), .B1(n1284), .Y(n988) );
OAI22X1TS U1392 ( .A0(n449), .A1(n1189), .B0(n532), .B1(n491), .Y(n987) );
OAI21XLTS U1393 ( .A0(n988), .A1(n987), .B0(n1846), .Y(n986) );
OAI31X1TS U1394 ( .A0(n988), .A1(n1193), .A2(n987), .B0(n986), .Y(
mult_x_19_n655) );
OAI22X1TS U1395 ( .A0(n432), .A1(n502), .B0(n536), .B1(n1779), .Y(n991) );
OAI22X1TS U1396 ( .A0(n1452), .A1(n1316), .B0(n473), .B1(n1312), .Y(n990) );
OAI21XLTS U1397 ( .A0(n991), .A1(n990), .B0(n1595), .Y(n989) );
OAI31X1TS U1398 ( .A0(n991), .A1(n1881), .A2(n990), .B0(n989), .Y(
mult_x_19_n676) );
OAI22X1TS U1399 ( .A0(n1590), .A1(n541), .B0(n1253), .B1(n1113), .Y(n994) );
OAI22X1TS U1400 ( .A0(n1786), .A1(n519), .B0(n1775), .B1(n434), .Y(n993) );
OAI21XLTS U1401 ( .A0(n994), .A1(n993), .B0(n1847), .Y(n992) );
OAI31X1TS U1402 ( .A0(n994), .A1(n1154), .A2(n993), .B0(n992), .Y(
mult_x_19_n634) );
OAI22X1TS U1403 ( .A0(n538), .A1(n1853), .B0(n1163), .B1(n1284), .Y(n997) );
OAI22X1TS U1404 ( .A0(n1184), .A1(n1776), .B0(n472), .B1(n1787), .Y(n996) );
OAI21XLTS U1405 ( .A0(n997), .A1(n996), .B0(n603), .Y(n995) );
OAI31X1TS U1406 ( .A0(n997), .A1(n1187), .A2(n996), .B0(n995), .Y(
mult_x_19_n682) );
OAI22X1TS U1407 ( .A0(n434), .A1(n502), .B0(n540), .B1(n508), .Y(n1001) );
OAI22X1TS U1408 ( .A0(n1462), .A1(n1316), .B0(n519), .B1(n1857), .Y(n999) );
OAI21XLTS U1409 ( .A0(n1001), .A1(n999), .B0(n1114), .Y(n998) );
OAI31X1TS U1410 ( .A0(n1001), .A1(n1000), .A2(n999), .B0(n998), .Y(
mult_x_19_n622) );
OAI22X1TS U1411 ( .A0(n436), .A1(n502), .B0(n534), .B1(n507), .Y(n1004) );
OAI22X1TS U1412 ( .A0(n1137), .A1(n1312), .B0(n1442), .B1(n1316), .Y(n1003)
);
OAI31X1TS U1413 ( .A0(n1004), .A1(n1128), .A2(n1003), .B0(n1002), .Y(
mult_x_19_n730) );
OAI22X1TS U1414 ( .A0(n445), .A1(n503), .B0(n1214), .B1(n1312), .Y(n1007) );
OAI22X1TS U1415 ( .A0(n966), .A1(n507), .B0(n1195), .B1(n1316), .Y(n1006) );
OAI21XLTS U1416 ( .A0(n1007), .A1(n1006), .B0(n1196), .Y(n1005) );
OAI31X1TS U1417 ( .A0(n1007), .A1(n1199), .A2(n1006), .B0(n1005), .Y(
mult_x_19_n703) );
OAI22X1TS U1418 ( .A0(n533), .A1(n1798), .B0(n1204), .B1(n1857), .Y(n1010)
);
OAI22X1TS U1419 ( .A0(n448), .A1(n507), .B0(n1459), .B1(n1316), .Y(n1009) );
OAI21XLTS U1420 ( .A0(n1010), .A1(n1009), .B0(n1846), .Y(n1008) );
OAI31X1TS U1421 ( .A0(n1010), .A1(n1193), .A2(n1009), .B0(n1008), .Y(
mult_x_19_n649) );
OAI22X1TS U1422 ( .A0(n535), .A1(n1856), .B0(n1135), .B1(n1306), .Y(n1013)
);
OAI22X1TS U1423 ( .A0(n1137), .A1(n1307), .B0(n436), .B1(n1312), .Y(n1012)
);
OAI21XLTS U1424 ( .A0(n1013), .A1(n1012), .B0(n1849), .Y(n1011) );
OAI31X1TS U1425 ( .A0(n1013), .A1(n1140), .A2(n1012), .B0(n1011), .Y(
mult_x_19_n732) );
OAI22X1TS U1426 ( .A0(n518), .A1(n539), .B0(n1511), .B1(n1113), .Y(n1016) );
OAI22X1TS U1427 ( .A0(n511), .A1(n520), .B0(n1850), .B1(n433), .Y(n1015) );
OAI21XLTS U1428 ( .A0(n1016), .A1(n1015), .B0(n1847), .Y(n1014) );
OAI31X1TS U1429 ( .A0(n1016), .A1(n1880), .A2(n1015), .B0(n1014), .Y(
mult_x_19_n635) );
INVX2TS U1430 ( .A(n1017), .Y(mult_x_19_n292) );
INVX2TS U1431 ( .A(n1018), .Y(mult_x_19_n234) );
OAI22X1TS U1432 ( .A0(n501), .A1(n540), .B0(n1226), .B1(n1462), .Y(n1021) );
OAI22X1TS U1433 ( .A0(n428), .A1(n521), .B0(n1781), .B1(n434), .Y(n1020) );
OAI21XLTS U1434 ( .A0(n1021), .A1(n1020), .B0(n1593), .Y(n1019) );
OAI31X1TS U1435 ( .A0(n1021), .A1(n1880), .A2(n1020), .B0(n1019), .Y(
mult_x_19_n638) );
AOI22X1TS U1436 ( .A0(n404), .A1(n450), .B0(Op_MY[0]), .B1(n551), .Y(n1025)
);
NAND2X1TS U1437 ( .A(n1023), .B(n420), .Y(n1024) );
OAI211X1TS U1438 ( .A0(n391), .A1(n1780), .B0(n1025), .C0(n1024), .Y(n1546)
);
NOR2X1TS U1439 ( .A(n1547), .B(n1546), .Y(n1545) );
AOI22X1TS U1440 ( .A0(Op_MY[3]), .A1(n450), .B0(Op_MY[1]), .B1(n551), .Y(
n1026) );
OAI21XLTS U1441 ( .A0(n547), .A1(n477), .B0(n1543), .Y(n1168) );
CLKBUFX3TS U1442 ( .A(n1022), .Y(n1588) );
AOI22X1TS U1443 ( .A0(n404), .A1(n1588), .B0(Op_MY[4]), .B1(n451), .Y(n1031)
);
AOI22X1TS U1444 ( .A0(Op_MY[3]), .A1(n1586), .B0(n1029), .B1(n420), .Y(n1030) );
NAND2X1TS U1445 ( .A(n1031), .B(n1030), .Y(n1167) );
INVX2TS U1446 ( .A(n1032), .Y(mult_x_19_n336) );
OAI22X1TS U1447 ( .A0(n498), .A1(n541), .B0(n1522), .B1(n1462), .Y(n1035) );
OAI22X1TS U1448 ( .A0(n500), .A1(n519), .B0(n1797), .B1(n433), .Y(n1034) );
OAI21XLTS U1449 ( .A0(n1035), .A1(n1034), .B0(n1593), .Y(n1033) );
OAI31X1TS U1450 ( .A0(n1035), .A1(n1880), .A2(n1034), .B0(n1033), .Y(
mult_x_19_n637) );
CMPR32X2TS U1451 ( .A(n1038), .B(n1037), .C(n1036), .CO(n660), .S(n1039) );
INVX2TS U1452 ( .A(n1039), .Y(mult_x_19_n440) );
OAI22X1TS U1453 ( .A0(n437), .A1(n507), .B0(n534), .B1(n1312), .Y(n1042) );
OAI22X1TS U1454 ( .A0(n1137), .A1(n1856), .B0(n1442), .B1(n1311), .Y(n1041)
);
OAI21XLTS U1455 ( .A0(n1042), .A1(n1041), .B0(n591), .Y(n1040) );
OAI31X1TS U1456 ( .A0(n1042), .A1(n1140), .A2(n1041), .B0(n1040), .Y(
mult_x_19_n731) );
OAI22X1TS U1457 ( .A0(n1568), .A1(n1212), .B0(n534), .B1(n1291), .Y(n1045)
);
OAI22X1TS U1458 ( .A0(n1137), .A1(n491), .B0(n489), .B1(n1307), .Y(n1044) );
OAI21XLTS U1459 ( .A0(n1045), .A1(n1044), .B0(n1128), .Y(n1043) );
OAI31X1TS U1460 ( .A0(n1045), .A1(n1140), .A2(n1044), .B0(n1043), .Y(
mult_x_19_n734) );
OAI22X1TS U1461 ( .A0(n535), .A1(n1855), .B0(n1135), .B1(n1565), .Y(n1048)
);
OAI22X1TS U1462 ( .A0(n1137), .A1(n1854), .B0(n489), .B1(n1614), .Y(n1047)
);
OAI21XLTS U1463 ( .A0(n1048), .A1(n1047), .B0(n1128), .Y(n1046) );
OAI31X1TS U1464 ( .A0(n1048), .A1(n1140), .A2(n1047), .B0(n1046), .Y(
mult_x_19_n733) );
CMPR32X2TS U1465 ( .A(n1051), .B(n1050), .C(n1049), .CO(n1063), .S(n1052) );
INVX2TS U1466 ( .A(n1052), .Y(mult_x_19_n399) );
OAI22X1TS U1467 ( .A0(n536), .A1(n514), .B0(n1159), .B1(n1280), .Y(n1055) );
OAI22X1TS U1468 ( .A0(n432), .A1(n1853), .B0(n473), .B1(n1778), .Y(n1054) );
OAI21XLTS U1469 ( .A0(n1055), .A1(n1054), .B0(n603), .Y(n1053) );
OAI31X1TS U1470 ( .A0(n1055), .A1(n1187), .A2(n1054), .B0(n1053), .Y(
mult_x_19_n683) );
OAI22X1TS U1471 ( .A0(n428), .A1(n537), .B0(n1230), .B1(n1159), .Y(n1058) );
OAI22X1TS U1472 ( .A0(n501), .A1(n431), .B0(n505), .B1(n473), .Y(n1057) );
OAI21XLTS U1473 ( .A0(n1058), .A1(n1057), .B0(n1848), .Y(n1056) );
OAI31X1TS U1474 ( .A0(n1058), .A1(n1881), .A2(n1057), .B0(n1056), .Y(
mult_x_19_n693) );
OAI22X1TS U1475 ( .A0(n534), .A1(n492), .B0(n1442), .B1(n1571), .Y(n1061) );
OAI22X1TS U1476 ( .A0(n1137), .A1(n1853), .B0(n489), .B1(n1291), .Y(n1060)
);
OAI21XLTS U1477 ( .A0(n1061), .A1(n1060), .B0(n1849), .Y(n1059) );
OAI31X1TS U1478 ( .A0(n1061), .A1(n1140), .A2(n1060), .B0(n1059), .Y(
mult_x_19_n735) );
CMPR32X2TS U1479 ( .A(n1064), .B(n1063), .C(n1062), .CO(n644), .S(n1065) );
INVX2TS U1480 ( .A(n1065), .Y(mult_x_19_n389) );
INVX2TS U1481 ( .A(n1066), .Y(mult_x_19_n194) );
OAI22X1TS U1482 ( .A0(n535), .A1(n1853), .B0(n1212), .B1(n1284), .Y(n1069)
);
OAI22X1TS U1483 ( .A0(n1137), .A1(n515), .B0(n489), .B1(n492), .Y(n1068) );
OAI21XLTS U1484 ( .A0(n1069), .A1(n1068), .B0(n1849), .Y(n1067) );
OAI31X1TS U1485 ( .A0(n1069), .A1(n1140), .A2(n1068), .B0(n1067), .Y(
mult_x_19_n736) );
OAI22X1TS U1486 ( .A0(n428), .A1(n539), .B0(n1230), .B1(n1113), .Y(n1072) );
OAI22X1TS U1487 ( .A0(n500), .A1(n433), .B0(n505), .B1(n521), .Y(n1071) );
OAI21XLTS U1488 ( .A0(n1072), .A1(n1071), .B0(n1593), .Y(n1070) );
OAI31X1TS U1489 ( .A0(n1072), .A1(n1880), .A2(n1071), .B0(n1070), .Y(
mult_x_19_n639) );
INVX2TS U1490 ( .A(mult_x_19_n260), .Y(n1179) );
AOI22X1TS U1491 ( .A0(n1623), .A1(Op_MY[10]), .B0(n450), .B1(Op_MY[12]), .Y(
n1075) );
AOI22X1TS U1492 ( .A0(n419), .A1(n1073), .B0(n1586), .B1(Op_MY[11]), .Y(
n1074) );
NAND2X1TS U1493 ( .A(n1075), .B(n1074), .Y(n1178) );
INVX2TS U1494 ( .A(n1076), .Y(mult_x_19_n252) );
AOI22X1TS U1495 ( .A0(n1623), .A1(Op_MY[16]), .B0(n450), .B1(Op_MY[18]), .Y(
n1079) );
AOI22X1TS U1496 ( .A0(n419), .A1(n1077), .B0(n1586), .B1(Op_MY[17]), .Y(
n1078) );
NAND2X1TS U1497 ( .A(n1079), .B(n1078), .Y(n1518) );
INVX2TS U1498 ( .A(n1080), .Y(mult_x_19_n206) );
OAI22X1TS U1499 ( .A0(n535), .A1(n1787), .B0(n1212), .B1(n1280), .Y(n1083)
);
OAI22X1TS U1500 ( .A0(n1137), .A1(n509), .B0(n489), .B1(n1189), .Y(n1082) );
OAI21XLTS U1501 ( .A0(n1083), .A1(n1082), .B0(n1849), .Y(n1081) );
OAI31X1TS U1502 ( .A0(n1083), .A1(n1140), .A2(n1082), .B0(n1081), .Y(
mult_x_19_n737) );
CMPR32X2TS U1503 ( .A(n1086), .B(n1085), .C(n1084), .CO(n1037), .S(n1087) );
INVX2TS U1504 ( .A(n1087), .Y(mult_x_19_n447) );
OAI22X1TS U1505 ( .A0(n512), .A1(n540), .B0(n1462), .B1(n1526), .Y(n1090) );
OAI22X1TS U1506 ( .A0(n497), .A1(n520), .B0(n517), .B1(n434), .Y(n1089) );
OAI21XLTS U1507 ( .A0(n1090), .A1(n1089), .B0(n1114), .Y(n1088) );
OAI31X1TS U1508 ( .A0(n1090), .A1(n1880), .A2(n1089), .B0(n1088), .Y(
mult_x_19_n636) );
OAI22X1TS U1509 ( .A0(n429), .A1(n535), .B0(n1230), .B1(n1442), .Y(n1093) );
OAI22X1TS U1510 ( .A0(n501), .A1(n436), .B0(n505), .B1(n1441), .Y(n1092) );
OAI31X1TS U1511 ( .A0(n1093), .A1(n1882), .A2(n1092), .B0(n1091), .Y(
mult_x_19_n747) );
OAI22X1TS U1512 ( .A0(n494), .A1(n1136), .B0(n1135), .B1(n1583), .Y(n1096)
);
OAI22X1TS U1513 ( .A0(n1850), .A1(n1127), .B0(n437), .B1(n1264), .Y(n1095)
);
OAI21XLTS U1514 ( .A0(n1096), .A1(n1095), .B0(n591), .Y(n1094) );
OAI31X1TS U1515 ( .A0(n1096), .A1(n1882), .A2(n1095), .B0(n1094), .Y(
mult_x_19_n741) );
OAI22X1TS U1516 ( .A0(n1850), .A1(n535), .B0(n1253), .B1(n1135), .Y(n1099)
);
OAI22X1TS U1517 ( .A0(n1786), .A1(n1127), .B0(n1775), .B1(n436), .Y(n1098)
);
OAI21XLTS U1518 ( .A0(n1099), .A1(n1098), .B0(n1598), .Y(n1097) );
OAI31X1TS U1519 ( .A0(n1099), .A1(n1882), .A2(n1098), .B0(n1097), .Y(
mult_x_19_n742) );
OAI22X1TS U1520 ( .A0(n511), .A1(n1136), .B0(n1442), .B1(n1526), .Y(n1102)
);
OAI22X1TS U1521 ( .A0(n498), .A1(n1127), .B0(n517), .B1(n437), .Y(n1101) );
OAI21XLTS U1522 ( .A0(n1102), .A1(n1101), .B0(n1849), .Y(n1100) );
OAI31X1TS U1523 ( .A0(n1102), .A1(n1882), .A2(n1101), .B0(n1100), .Y(
mult_x_19_n744) );
OAI22X1TS U1524 ( .A0(n497), .A1(n535), .B0(n1522), .B1(n1442), .Y(n1105) );
OAI22X1TS U1525 ( .A0(n500), .A1(n1127), .B0(n1797), .B1(n436), .Y(n1104) );
OAI21XLTS U1526 ( .A0(n1105), .A1(n1104), .B0(n591), .Y(n1103) );
OAI31X1TS U1527 ( .A0(n1105), .A1(n1882), .A2(n1104), .B0(n1103), .Y(
mult_x_19_n745) );
OAI22X1TS U1528 ( .A0(n518), .A1(n534), .B0(n1511), .B1(n1212), .Y(n1108) );
OAI22X1TS U1529 ( .A0(n512), .A1(n1127), .B0(n1609), .B1(n437), .Y(n1107) );
OAI21XLTS U1530 ( .A0(n1108), .A1(n1107), .B0(n1849), .Y(n1106) );
OAI31X1TS U1531 ( .A0(n1108), .A1(n1140), .A2(n1107), .B0(n1106), .Y(
mult_x_19_n743) );
INVX2TS U1532 ( .A(n1109), .Y(mult_x_19_n195) );
OAI22X1TS U1533 ( .A0(n501), .A1(n538), .B0(n1226), .B1(n1452), .Y(n1112) );
OAI22X1TS U1534 ( .A0(n429), .A1(n472), .B0(n1781), .B1(n431), .Y(n1111) );
OAI21XLTS U1535 ( .A0(n1112), .A1(n1111), .B0(n603), .Y(n1110) );
OAI31X1TS U1536 ( .A0(n1112), .A1(n1881), .A2(n1111), .B0(n1110), .Y(
mult_x_19_n692) );
OAI22X1TS U1537 ( .A0(n541), .A1(n515), .B0(n1113), .B1(n1280), .Y(n1117) );
OAI22X1TS U1538 ( .A0(n434), .A1(n1189), .B0(n520), .B1(n510), .Y(n1116) );
OAI21XLTS U1539 ( .A0(n1117), .A1(n1116), .B0(n1114), .Y(n1115) );
OAI31X1TS U1540 ( .A0(n1117), .A1(n1154), .A2(n1116), .B0(n1115), .Y(
mult_x_19_n629) );
OAI22X1TS U1541 ( .A0(n500), .A1(n535), .B0(n1226), .B1(n1135), .Y(n1120) );
OAI22X1TS U1542 ( .A0(n429), .A1(n1127), .B0(n1781), .B1(n436), .Y(n1119) );
OAI31X1TS U1543 ( .A0(n1120), .A1(n1882), .A2(n1119), .B0(n1118), .Y(
mult_x_19_n746) );
OAI22X1TS U1544 ( .A0(n1580), .A1(n1212), .B0(n534), .B1(n1264), .Y(n1123)
);
OAI22X1TS U1545 ( .A0(n495), .A1(n1127), .B0(n436), .B1(n1268), .Y(n1122) );
OAI31X1TS U1546 ( .A0(n1123), .A1(n1882), .A2(n1122), .B0(n1121), .Y(
mult_x_19_n740) );
OAI22X1TS U1547 ( .A0(n498), .A1(n536), .B0(n1522), .B1(n1159), .Y(n1126) );
OAI22X1TS U1548 ( .A0(n501), .A1(n473), .B0(n1797), .B1(n432), .Y(n1125) );
OAI31X1TS U1549 ( .A0(n1126), .A1(n1187), .A2(n1125), .B0(n1124), .Y(
mult_x_19_n691) );
OAI22X1TS U1550 ( .A0(n535), .A1(n1852), .B0(n1135), .B1(n1577), .Y(n1131)
);
OAI22X1TS U1551 ( .A0(n1127), .A1(n1851), .B0(n437), .B1(n1778), .Y(n1130)
);
OAI21XLTS U1552 ( .A0(n1131), .A1(n1130), .B0(n1128), .Y(n1129) );
OAI31X1TS U1553 ( .A0(n1131), .A1(n1882), .A2(n1130), .B0(n1129), .Y(
mult_x_19_n739) );
OAI22X1TS U1554 ( .A0(n511), .A1(n537), .B0(n1452), .B1(n1526), .Y(n1134) );
OAI22X1TS U1555 ( .A0(n497), .A1(n472), .B0(n1786), .B1(n1184), .Y(n1133) );
OAI21XLTS U1556 ( .A0(n1134), .A1(n1133), .B0(n1848), .Y(n1132) );
OAI31X1TS U1557 ( .A0(n1134), .A1(n1881), .A2(n1133), .B0(n1132), .Y(
mult_x_19_n690) );
OAI22X1TS U1558 ( .A0(n534), .A1(n510), .B0(n1442), .B1(n1272), .Y(n1141) );
OAI22X1TS U1559 ( .A0(n1137), .A1(n1268), .B0(n489), .B1(n515), .Y(n1139) );
OAI21XLTS U1560 ( .A0(n1141), .A1(n1139), .B0(n1849), .Y(n1138) );
OAI31X1TS U1561 ( .A0(n1141), .A1(n1140), .A2(n1139), .B0(n1138), .Y(
mult_x_19_n738) );
OAI22X1TS U1562 ( .A0(n1786), .A1(n538), .B0(n1511), .B1(n1159), .Y(n1144)
);
OAI22X1TS U1563 ( .A0(n512), .A1(n473), .B0(n1850), .B1(n432), .Y(n1143) );
OAI21XLTS U1564 ( .A0(n1144), .A1(n1143), .B0(n1848), .Y(n1142) );
OAI31X1TS U1565 ( .A0(n1144), .A1(n1187), .A2(n1143), .B0(n1142), .Y(
mult_x_19_n689) );
OAI22X1TS U1566 ( .A0(n1590), .A1(n536), .B0(n1253), .B1(n1452), .Y(n1147)
);
OAI22X1TS U1567 ( .A0(n518), .A1(n472), .B0(n1775), .B1(n1184), .Y(n1146) );
OAI21XLTS U1568 ( .A0(n1147), .A1(n1146), .B0(n1848), .Y(n1145) );
OAI31X1TS U1569 ( .A0(n1147), .A1(n1187), .A2(n1146), .B0(n1145), .Y(
mult_x_19_n688) );
OAI22X1TS U1570 ( .A0(n494), .A1(n537), .B0(n1163), .B1(n1583), .Y(n1150) );
OAI22X1TS U1571 ( .A0(n1590), .A1(n473), .B0(n431), .B1(n1264), .Y(n1149) );
OAI21XLTS U1572 ( .A0(n1150), .A1(n1149), .B0(n603), .Y(n1148) );
OAI31X1TS U1573 ( .A0(n1150), .A1(n1881), .A2(n1149), .B0(n1148), .Y(
mult_x_19_n687) );
OAI22X1TS U1574 ( .A0(n1151), .A1(n507), .B0(n541), .B1(n1857), .Y(n1155) );
OAI22X1TS U1575 ( .A0(n1113), .A1(n1311), .B0(n521), .B1(n1599), .Y(n1153)
);
OAI21XLTS U1576 ( .A0(n1155), .A1(n1153), .B0(n1593), .Y(n1152) );
OAI31X1TS U1577 ( .A0(n1155), .A1(n1154), .A2(n1153), .B0(n1152), .Y(
mult_x_19_n623) );
OAI22X1TS U1578 ( .A0(n1580), .A1(n1163), .B0(n537), .B1(n1264), .Y(n1158)
);
OAI22X1TS U1579 ( .A0(n495), .A1(n472), .B0(n431), .B1(n1268), .Y(n1157) );
OAI21XLTS U1580 ( .A0(n1158), .A1(n1157), .B0(n1848), .Y(n1156) );
OAI31X1TS U1581 ( .A0(n1158), .A1(n1624), .A2(n1157), .B0(n1156), .Y(
mult_x_19_n686) );
OAI22X1TS U1582 ( .A0(n537), .A1(n1852), .B0(n1159), .B1(n1577), .Y(n1162)
);
OAI22X1TS U1583 ( .A0(n1184), .A1(n1778), .B0(n472), .B1(n1264), .Y(n1161)
);
OAI31X1TS U1584 ( .A0(n1162), .A1(n1624), .A2(n1161), .B0(n1160), .Y(
mult_x_19_n685) );
OAI22X1TS U1585 ( .A0(n538), .A1(n510), .B0(n1163), .B1(n1272), .Y(n1166) );
OAI22X1TS U1586 ( .A0(n432), .A1(n1787), .B0(n473), .B1(n1268), .Y(n1165) );
OAI21XLTS U1587 ( .A0(n1166), .A1(n1165), .B0(n1848), .Y(n1164) );
OAI31X1TS U1588 ( .A0(n1166), .A1(n1624), .A2(n1165), .B0(n1164), .Y(
mult_x_19_n684) );
CMPR32X2TS U1589 ( .A(n505), .B(n1168), .C(n1167), .CO(n1032), .S(n1169) );
INVX2TS U1590 ( .A(n1169), .Y(mult_x_19_n337) );
INVX2TS U1591 ( .A(n1170), .Y(mult_x_19_n235) );
OAI22X1TS U1592 ( .A0(n531), .A1(n1779), .B0(n1204), .B1(n1614), .Y(n1173)
);
OAI22X1TS U1593 ( .A0(n449), .A1(n480), .B0(n696), .B1(n1311), .Y(n1172) );
OAI21XLTS U1594 ( .A0(n1173), .A1(n1172), .B0(n1846), .Y(n1171) );
OAI31X1TS U1595 ( .A0(n1173), .A1(n1193), .A2(n1172), .B0(n1171), .Y(
mult_x_19_n650) );
OAI22X1TS U1596 ( .A0(n464), .A1(n1852), .B0(n1459), .B1(n1272), .Y(n1177)
);
OAI22X1TS U1597 ( .A0(n448), .A1(n1778), .B0(n533), .B1(n1787), .Y(n1175) );
OAI21XLTS U1598 ( .A0(n1177), .A1(n1175), .B0(n400), .Y(n1174) );
OAI31X1TS U1599 ( .A0(n1177), .A1(n1176), .A2(n1175), .B0(n1174), .Y(
mult_x_19_n657) );
CMPR32X2TS U1600 ( .A(n1179), .B(Op_MY[9]), .C(n1178), .CO(n1180), .S(n1076)
);
INVX2TS U1601 ( .A(n1180), .Y(mult_x_19_n251) );
OAI22X1TS U1602 ( .A0(n466), .A1(n1307), .B0(n1215), .B1(n1306), .Y(n1183)
);
OAI22X1TS U1603 ( .A0(n835), .A1(n1856), .B0(n446), .B1(n1312), .Y(n1182) );
OAI21XLTS U1604 ( .A0(n1183), .A1(n1182), .B0(n1196), .Y(n1181) );
OAI31X1TS U1605 ( .A0(n1183), .A1(n1199), .A2(n1182), .B0(n1181), .Y(
mult_x_19_n705) );
OAI22X1TS U1606 ( .A0(n1184), .A1(n508), .B0(n538), .B1(n1312), .Y(n1188) );
OAI22X1TS U1607 ( .A0(n1159), .A1(n1311), .B0(n472), .B1(n1614), .Y(n1186)
);
OAI21XLTS U1608 ( .A0(n1188), .A1(n1186), .B0(n1595), .Y(n1185) );
OAI31X1TS U1609 ( .A0(n1188), .A1(n1187), .A2(n1186), .B0(n1185), .Y(
mult_x_19_n677) );
OAI22X1TS U1610 ( .A0(n463), .A1(n510), .B0(n1459), .B1(n1280), .Y(n1194) );
OAI22X1TS U1611 ( .A0(n447), .A1(n515), .B0(n531), .B1(n1189), .Y(n1192) );
OAI21XLTS U1612 ( .A0(n1194), .A1(n1192), .B0(n1625), .Y(n1191) );
OAI31X1TS U1613 ( .A0(n1194), .A1(n1193), .A2(n1192), .B0(n1191), .Y(
mult_x_19_n656) );
OAI22X1TS U1614 ( .A0(n446), .A1(n1779), .B0(n1214), .B1(n1614), .Y(n1200)
);
OAI22X1TS U1615 ( .A0(n966), .A1(n480), .B0(n1195), .B1(n1311), .Y(n1198) );
OAI21XLTS U1616 ( .A0(n1200), .A1(n1198), .B0(n1196), .Y(n1197) );
OAI31X1TS U1617 ( .A0(n1200), .A1(n1199), .A2(n1198), .B0(n1197), .Y(
mult_x_19_n704) );
INVX2TS U1618 ( .A(n1201), .Y(mult_x_19_n293) );
OAI21XLTS U1619 ( .A0(n1462), .A1(n479), .B0(n519), .Y(n1203) );
XOR2XLTS U1620 ( .A(Op_MX[20]), .B(n1203), .Y(mult_x_19_n617) );
OAI21XLTS U1621 ( .A0(n1205), .A1(n479), .B0(n463), .Y(n1206) );
XOR2XLTS U1622 ( .A(n401), .B(n1206), .Y(mult_x_19_n644) );
OAI21XLTS U1623 ( .A0(n1452), .A1(n479), .B0(n472), .Y(n1208) );
XOR2XLTS U1624 ( .A(Op_MX[14]), .B(n1208), .Y(mult_x_19_n671) );
XOR2XLTS U1625 ( .A(n403), .B(n1210), .Y(mult_x_19_n752) );
AOI21X1TS U1626 ( .A0(Op_MX[0]), .A1(n478), .B0(Op_MX[1]), .Y(n1211) );
OAI32X1TS U1627 ( .A0(n1783), .A1(n1777), .A2(n478), .B0(n1211), .B1(n1844),
.Y(mult_x_19_n779) );
XOR2XLTS U1628 ( .A(Op_MX[8]), .B(n1213), .Y(mult_x_19_n725) );
XOR2XLTS U1629 ( .A(Op_MX[11]), .B(n1216), .Y(mult_x_19_n698) );
XNOR2X1TS U1630 ( .A(n1218), .B(n1217), .Y(n1219) );
XOR2X1TS U1631 ( .A(n1220), .B(n1219), .Y(n1246) );
AOI21X1TS U1632 ( .A0(n1225), .A1(n1234), .B0(n402), .Y(n1222) );
OAI22X1TS U1633 ( .A0(n429), .A1(n525), .B0(n460), .B1(n1226), .Y(n1229) );
OAI22X1TS U1634 ( .A0(n528), .A1(n498), .B0(n1788), .B1(n470), .Y(n1228) );
OAI22X1TS U1635 ( .A0(n1780), .A1(n526), .B0(n460), .B1(n1230), .Y(n1233) );
OAI22X1TS U1636 ( .A0(n529), .A1(n1788), .B0(n1377), .B1(n429), .Y(n1232) );
OAI21XLTS U1637 ( .A0(n1233), .A1(n1232), .B0(n410), .Y(n1231) );
OAI31X1TS U1638 ( .A0(n1233), .A1(n410), .A2(n1232), .B0(n1231), .Y(n1769)
);
NAND2X1TS U1639 ( .A(n1235), .B(n1234), .Y(n1768) );
NAND2X1TS U1640 ( .A(n1769), .B(n1768), .Y(n1766) );
OAI22X1TS U1641 ( .A0(n500), .A1(n527), .B0(n460), .B1(n1522), .Y(n1238) );
OAI22X1TS U1642 ( .A0(n530), .A1(n511), .B0(n1377), .B1(n498), .Y(n1237) );
INVX2TS U1643 ( .A(n1239), .Y(n1419) );
OAI22X1TS U1644 ( .A0(n525), .A1(n497), .B0(n460), .B1(n1526), .Y(n1242) );
OAI22X1TS U1645 ( .A0(n528), .A1(n1786), .B0(n1377), .B1(n511), .Y(n1241) );
OAI21XLTS U1646 ( .A0(n1242), .A1(n1241), .B0(n409), .Y(n1240) );
OAI31X1TS U1647 ( .A0(n1242), .A1(n409), .A2(n1241), .B0(n1240), .Y(n1244)
);
AOI2BB2XLTS U1648 ( .B0(n1243), .B1(n1767), .A0N(n1416), .A1N(P_Sgf[6]), .Y(
n244) );
INVX2TS U1649 ( .A(mult_x_19_n452), .Y(n1279) );
INVX2TS U1650 ( .A(mult_x_19_n459), .Y(n1354) );
INVX2TS U1651 ( .A(mult_x_19_n464), .Y(n1409) );
INVX2TS U1652 ( .A(mult_x_19_n469), .Y(n1396) );
CMPR32X2TS U1653 ( .A(n1246), .B(n1245), .C(n1244), .CO(n1361), .S(n1243) );
CMPR32X2TS U1654 ( .A(n1249), .B(n1248), .C(n1247), .CO(n1258), .S(n1362) );
OAI22X1TS U1655 ( .A0(n526), .A1(n512), .B0(n460), .B1(n1511), .Y(n1252) );
OAI22X1TS U1656 ( .A0(n529), .A1(n1850), .B0(n1377), .B1(n1786), .Y(n1251)
);
OAI21XLTS U1657 ( .A0(n1252), .A1(n1251), .B0(n1433), .Y(n1250) );
OR2X1TS U1658 ( .A(n1361), .B(n1362), .Y(n1360) );
AOI22X1TS U1659 ( .A0(n1361), .A1(n1362), .B0(n1364), .B1(n1360), .Y(n1411)
);
OAI22X1TS U1660 ( .A0(n527), .A1(n518), .B0(n460), .B1(n1253), .Y(n1256) );
OAI22X1TS U1661 ( .A0(n530), .A1(n495), .B0(n1377), .B1(n1609), .Y(n1255) );
OAI21XLTS U1662 ( .A0(n1256), .A1(n1255), .B0(n411), .Y(n1254) );
CMPR32X2TS U1663 ( .A(n1259), .B(n1258), .C(n1257), .CO(n683), .S(n1412) );
NOR2XLTS U1664 ( .A(n1413), .B(n1412), .Y(n1260) );
OAI2BB2XLTS U1665 ( .B0(n1411), .B1(n1260), .A0N(n1413), .A1N(n1412), .Y(
n1395) );
OAI22X1TS U1666 ( .A0(n525), .A1(n1850), .B0(n460), .B1(n1583), .Y(n1263) );
OAI22X1TS U1667 ( .A0(n528), .A1(n1608), .B0(n1377), .B1(n494), .Y(n1262) );
OAI21XLTS U1668 ( .A0(n1263), .A1(n1262), .B0(n1356), .Y(n1261) );
OAI22X1TS U1669 ( .A0(n1580), .A1(n1431), .B0(n525), .B1(n495), .Y(n1267) );
OAI22X1TS U1670 ( .A0(n529), .A1(n1852), .B0(n469), .B1(n1264), .Y(n1266) );
OAI21XLTS U1671 ( .A0(n1267), .A1(n1266), .B0(n411), .Y(n1265) );
OAI22X1TS U1672 ( .A0(n526), .A1(n1851), .B0(n461), .B1(n1577), .Y(n1271) );
OAI22X1TS U1673 ( .A0(n530), .A1(n1778), .B0(n470), .B1(n1268), .Y(n1270) );
OAI21XLTS U1674 ( .A0(n1271), .A1(n1270), .B0(n411), .Y(n1269) );
OAI31X1TS U1675 ( .A0(n1271), .A1(n1356), .A2(n1270), .B0(n1269), .Y(n1352)
);
OAI22X1TS U1676 ( .A0(n527), .A1(n1852), .B0(n1431), .B1(n1272), .Y(n1275)
);
OAI22X1TS U1677 ( .A0(n528), .A1(n1787), .B0(n469), .B1(n510), .Y(n1274) );
OAI21XLTS U1678 ( .A0(n1275), .A1(n1274), .B0(n411), .Y(n1273) );
OAI31X1TS U1679 ( .A0(n1275), .A1(n1356), .A2(n1274), .B0(n1273), .Y(n1277)
);
AOI2BB2XLTS U1680 ( .B0(n1276), .B1(n1767), .A0N(n1738), .A1N(P_Sgf[12]),
.Y(n250) );
INVX2TS U1681 ( .A(mult_x_19_n422), .Y(n1302) );
INVX2TS U1682 ( .A(mult_x_19_n430), .Y(n1298) );
INVX2TS U1683 ( .A(mult_x_19_n438), .Y(n1405) );
INVX2TS U1684 ( .A(mult_x_19_n445), .Y(n1392) );
CMPR32X2TS U1685 ( .A(n1279), .B(n1278), .C(n1277), .CO(n1391), .S(n1276) );
OAI22X1TS U1686 ( .A0(n525), .A1(n510), .B0(n461), .B1(n1280), .Y(n1283) );
OAI22X1TS U1687 ( .A0(n529), .A1(n1853), .B0(n470), .B1(n515), .Y(n1282) );
OAI22X1TS U1688 ( .A0(n526), .A1(n515), .B0(n1431), .B1(n1284), .Y(n1287) );
OAI22X1TS U1689 ( .A0(n530), .A1(n491), .B0(n469), .B1(n1605), .Y(n1286) );
OAI31X1TS U1690 ( .A0(n1287), .A1(n1356), .A2(n1286), .B0(n1285), .Y(n1403)
);
OAI22X1TS U1691 ( .A0(n527), .A1(n1853), .B0(n461), .B1(n1571), .Y(n1290) );
OAI22X1TS U1692 ( .A0(n528), .A1(n1602), .B0(n470), .B1(n491), .Y(n1289) );
OAI21XLTS U1693 ( .A0(n1290), .A1(n1289), .B0(n1433), .Y(n1288) );
OAI31X1TS U1694 ( .A0(n1290), .A1(n1433), .A2(n1289), .B0(n1288), .Y(n1296)
);
OAI22X1TS U1695 ( .A0(n1568), .A1(n461), .B0(n526), .B1(n492), .Y(n1294) );
OAI22X1TS U1696 ( .A0(n529), .A1(n1600), .B0(n469), .B1(n1291), .Y(n1293) );
OAI21XLTS U1697 ( .A0(n1294), .A1(n1293), .B0(n411), .Y(n1292) );
INVX2TS U1698 ( .A(n1771), .Y(n1475) );
INVX2TS U1699 ( .A(n1771), .Y(n1716) );
AOI2BB2XLTS U1700 ( .B0(n1295), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[16]),
.Y(n254) );
CMPR32X2TS U1701 ( .A(n1298), .B(n1297), .C(n1296), .CO(n1301), .S(n1299) );
AOI2BB2XLTS U1702 ( .B0(n1299), .B1(n1475), .A0N(n1416), .A1N(P_Sgf[15]),
.Y(n253) );
INVX2TS U1703 ( .A(mult_x_19_n384), .Y(n1372) );
INVX2TS U1704 ( .A(mult_x_19_n394), .Y(n1323) );
INVX2TS U1705 ( .A(mult_x_19_n404), .Y(n1401) );
INVX2TS U1706 ( .A(mult_x_19_n414), .Y(n1388) );
CMPR32X2TS U1707 ( .A(n1302), .B(n1301), .C(n1300), .CO(n1387), .S(n1295) );
OAI22X1TS U1708 ( .A0(n525), .A1(n1854), .B0(n1431), .B1(n1565), .Y(n1305)
);
OAI22X1TS U1709 ( .A0(n530), .A1(n1856), .B0(n470), .B1(n1307), .Y(n1304) );
OAI21XLTS U1710 ( .A0(n1305), .A1(n1304), .B0(n411), .Y(n1303) );
OAI31X1TS U1711 ( .A0(n1305), .A1(Op_MX[2]), .A2(n1304), .B0(n1303), .Y(
n1386) );
OAI22X1TS U1712 ( .A0(n526), .A1(n1307), .B0(n461), .B1(n1306), .Y(n1310) );
OAI22X1TS U1713 ( .A0(n528), .A1(n480), .B0(n469), .B1(n1599), .Y(n1309) );
OAI21XLTS U1714 ( .A0(n1310), .A1(n1309), .B0(n411), .Y(n1308) );
OAI31X1TS U1715 ( .A0(n1310), .A1(Op_MX[2]), .A2(n1309), .B0(n1308), .Y(
n1399) );
OAI22X1TS U1716 ( .A0(n527), .A1(n1614), .B0(n1431), .B1(n1311), .Y(n1315)
);
OAI22X1TS U1717 ( .A0(n529), .A1(n508), .B0(n470), .B1(n1312), .Y(n1314) );
OAI21XLTS U1718 ( .A0(n1315), .A1(n1314), .B0(n411), .Y(n1313) );
OAI31X1TS U1719 ( .A0(n1315), .A1(Op_MX[2]), .A2(n1314), .B0(n1313), .Y(
n1321) );
OAI22X1TS U1720 ( .A0(n525), .A1(n1857), .B0(n461), .B1(n1316), .Y(n1319) );
OAI22X1TS U1721 ( .A0(n530), .A1(n503), .B0(n469), .B1(n508), .Y(n1318) );
OAI31X1TS U1722 ( .A0(n1319), .A1(Op_MX[2]), .A2(n1318), .B0(n1317), .Y(
n1370) );
AOI2BB2XLTS U1723 ( .B0(n1320), .B1(n1475), .A0N(n1738), .A1N(P_Sgf[20]),
.Y(n258) );
CMPR32X2TS U1724 ( .A(n1323), .B(n1322), .C(n1321), .CO(n1371), .S(n1324) );
AOI2BB2XLTS U1725 ( .B0(n1324), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[19]),
.Y(n257) );
INVX2TS U1726 ( .A(n425), .Y(n1594) );
CLKBUFX2TS U1727 ( .A(n1594), .Y(n1596) );
CLKBUFX2TS U1728 ( .A(n1596), .Y(n1604) );
AO22XLTS U1729 ( .A0(n398), .A1(Data_MY[31]), .B0(n425), .B1(Op_MY[31]), .Y(
n381) );
XNOR2X1TS U1730 ( .A(DP_OP_32J138_122_6543_n1), .B(n1329), .Y(n1326) );
AO22XLTS U1731 ( .A0(n1326), .A1(n1767), .B0(n1691), .B1(
Exp_module_Overflow_flag_A), .Y(n225) );
AOI32X1TS U1732 ( .A0(FS_Module_state_reg[1]), .A1(n1790), .A2(
FS_Module_state_reg[0]), .B0(FS_Module_state_reg[2]), .B1(n1327), .Y(
n1330) );
NAND3XLTS U1733 ( .A(n1330), .B(n1329), .C(n1328), .Y(n377) );
CLKBUFX2TS U1734 ( .A(n1331), .Y(n1332) );
AO22XLTS U1735 ( .A0(Sgf_normalized_result[0]), .A1(n415), .B0(
final_result_ieee[0]), .B1(n1332), .Y(n200) );
AO22XLTS U1736 ( .A0(Sgf_normalized_result[1]), .A1(n415), .B0(
final_result_ieee[1]), .B1(n1332), .Y(n199) );
AO22XLTS U1737 ( .A0(Sgf_normalized_result[2]), .A1(n415), .B0(
final_result_ieee[2]), .B1(n1332), .Y(n198) );
AO22XLTS U1738 ( .A0(Sgf_normalized_result[21]), .A1(n415), .B0(
final_result_ieee[21]), .B1(n1332), .Y(n179) );
AO22XLTS U1739 ( .A0(Sgf_normalized_result[3]), .A1(n415), .B0(
final_result_ieee[3]), .B1(n1331), .Y(n197) );
AO22XLTS U1740 ( .A0(Sgf_normalized_result[19]), .A1(n415), .B0(
final_result_ieee[19]), .B1(n1332), .Y(n181) );
AO22XLTS U1741 ( .A0(Sgf_normalized_result[5]), .A1(n416), .B0(
final_result_ieee[5]), .B1(n1332), .Y(n195) );
AO22XLTS U1742 ( .A0(Sgf_normalized_result[17]), .A1(n416), .B0(
final_result_ieee[17]), .B1(n1331), .Y(n183) );
AO22XLTS U1743 ( .A0(Sgf_normalized_result[7]), .A1(n416), .B0(
final_result_ieee[7]), .B1(n1332), .Y(n193) );
AO22XLTS U1744 ( .A0(Sgf_normalized_result[15]), .A1(n416), .B0(
final_result_ieee[15]), .B1(n1331), .Y(n185) );
AO22XLTS U1745 ( .A0(Sgf_normalized_result[9]), .A1(n416), .B0(
final_result_ieee[9]), .B1(n1331), .Y(n191) );
AO22XLTS U1746 ( .A0(Sgf_normalized_result[11]), .A1(n416), .B0(
final_result_ieee[11]), .B1(n1331), .Y(n189) );
AO22XLTS U1747 ( .A0(Sgf_normalized_result[13]), .A1(n416), .B0(
final_result_ieee[13]), .B1(n1331), .Y(n187) );
NAND2X1TS U1748 ( .A(n1639), .B(n549), .Y(n376) );
NOR3XLTS U1749 ( .A(Exp_module_Data_S[7]), .B(Exp_module_Data_S[8]), .C(
n1639), .Y(n1335) );
AND4X1TS U1750 ( .A(Exp_module_Data_S[6]), .B(Exp_module_Data_S[3]), .C(
Exp_module_Data_S[2]), .D(Exp_module_Data_S[1]), .Y(n1333) );
NAND4XLTS U1751 ( .A(Exp_module_Data_S[0]), .B(Exp_module_Data_S[5]), .C(
Exp_module_Data_S[4]), .D(n1333), .Y(n1334) );
AO22XLTS U1752 ( .A0(n1335), .A1(n1334), .B0(underflow_flag), .B1(n1639),
.Y(n201) );
AOI21X1TS U1753 ( .A0(n1811), .A1(n1645), .B0(n1336), .Y(n1338) );
CLKBUFX3TS U1754 ( .A(n1337), .Y(n1494) );
AO22XLTS U1755 ( .A0(n1495), .A1(n1338), .B0(n1494), .B1(Add_result[6]), .Y(
n303) );
AOI21X1TS U1756 ( .A0(n1812), .A1(n1340), .B0(n1339), .Y(n1341) );
AO22XLTS U1757 ( .A0(n1495), .A1(n1341), .B0(n1494), .B1(Add_result[8]), .Y(
n301) );
INVX2TS U1758 ( .A(n1491), .Y(n1493) );
AOI21X1TS U1759 ( .A0(n1813), .A1(n1342), .B0(n1649), .Y(n1343) );
AO22XLTS U1760 ( .A0(n1493), .A1(n1343), .B0(n1494), .B1(Add_result[10]),
.Y(n299) );
NAND2X1TS U1761 ( .A(Sgf_normalized_result[11]), .B(n1649), .Y(n1648) );
AOI21X1TS U1762 ( .A0(n1814), .A1(n1648), .B0(n1652), .Y(n1344) );
AO22XLTS U1763 ( .A0(n1493), .A1(n1344), .B0(n1494), .B1(Add_result[12]),
.Y(n297) );
NAND2X1TS U1764 ( .A(Sgf_normalized_result[13]), .B(n1652), .Y(n1651) );
AOI21X1TS U1765 ( .A0(n1815), .A1(n1651), .B0(n1655), .Y(n1345) );
AO22XLTS U1766 ( .A0(n1493), .A1(n1345), .B0(n1494), .B1(Add_result[14]),
.Y(n295) );
NAND2X1TS U1767 ( .A(Sgf_normalized_result[15]), .B(n1655), .Y(n1654) );
AOI21X1TS U1768 ( .A0(n1816), .A1(n1654), .B0(n1658), .Y(n1346) );
CLKBUFX3TS U1769 ( .A(n1491), .Y(n1670) );
AO22XLTS U1770 ( .A0(n1495), .A1(n1346), .B0(n1670), .B1(Add_result[16]),
.Y(n293) );
NAND2X1TS U1771 ( .A(Sgf_normalized_result[17]), .B(n1658), .Y(n1657) );
AOI21X1TS U1772 ( .A0(n1817), .A1(n1657), .B0(n1661), .Y(n1347) );
AO22XLTS U1773 ( .A0(n1495), .A1(n1347), .B0(n1494), .B1(Add_result[18]),
.Y(n291) );
NAND2X1TS U1774 ( .A(Sgf_normalized_result[19]), .B(n1661), .Y(n1660) );
AOI21X1TS U1775 ( .A0(n1818), .A1(n1660), .B0(n1665), .Y(n1348) );
AO22XLTS U1776 ( .A0(n1493), .A1(n1348), .B0(n1494), .B1(Add_result[20]),
.Y(n289) );
NAND2X1TS U1777 ( .A(Sgf_normalized_result[21]), .B(n1665), .Y(n1663) );
AOI211XLTS U1778 ( .A0(n1819), .A1(n1663), .B0(n1668), .C0(n1494), .Y(n1349)
);
AO21XLTS U1779 ( .A0(Add_result[22]), .A1(n1670), .B0(n1349), .Y(n287) );
AOI21X1TS U1780 ( .A0(Sgf_normalized_result[0]), .A1(
Sgf_normalized_result[1]), .B0(n1350), .Y(n1351) );
AOI2BB2XLTS U1781 ( .B0(n1495), .B1(n1351), .A0N(Add_result[1]), .A1N(n1493),
.Y(n308) );
CMPR32X2TS U1782 ( .A(n1354), .B(n1353), .C(n1352), .CO(n1278), .S(n1355) );
AOI2BB2XLTS U1783 ( .B0(n1355), .B1(n1767), .A0N(n1416), .A1N(P_Sgf[11]),
.Y(n249) );
INVX2TS U1784 ( .A(n1771), .Y(n1485) );
NAND3XLTS U1785 ( .A(n1433), .B(Op_MX[0]), .C(n547), .Y(n1357) );
XNOR2X1TS U1786 ( .A(n1358), .B(n1357), .Y(n1359) );
AO22XLTS U1787 ( .A0(n1771), .A1(P_Sgf[1]), .B0(n1485), .B1(n1359), .Y(n239)
);
OAI2BB1X1TS U1788 ( .A0N(n1362), .A1N(n1361), .B0(n1360), .Y(n1363) );
XOR2XLTS U1789 ( .A(n1364), .B(n1363), .Y(n1365) );
AO22XLTS U1790 ( .A0(n1771), .A1(P_Sgf[7]), .B0(n1485), .B1(n1365), .Y(n245)
);
XOR2XLTS U1791 ( .A(n1366), .B(n1766), .Y(n1367) );
XNOR2X1TS U1792 ( .A(n1368), .B(n1367), .Y(n1369) );
AO22XLTS U1793 ( .A0(n1691), .A1(P_Sgf[4]), .B0(n1485), .B1(n1369), .Y(n242)
);
INVX2TS U1794 ( .A(mult_x_19_n362), .Y(n1426) );
INVX2TS U1795 ( .A(mult_x_19_n373), .Y(n1384) );
CMPR32X2TS U1796 ( .A(n1372), .B(n1371), .C(n1370), .CO(n1383), .S(n1320) );
OAI22X1TS U1797 ( .A0(n526), .A1(n1779), .B0(n1431), .B1(n1373), .Y(n1376)
);
OAI22X1TS U1798 ( .A0(n528), .A1(n423), .B0(n470), .B1(n503), .Y(n1375) );
OAI21XLTS U1799 ( .A0(n1376), .A1(n1375), .B0(n409), .Y(n1374) );
OAI22X1TS U1800 ( .A0(n1553), .A1(n460), .B0(n527), .B1(n502), .Y(n1380) );
OAI22X1TS U1801 ( .A0(n529), .A1(n485), .B0(n469), .B1(n424), .Y(n1379) );
OAI21XLTS U1802 ( .A0(n1380), .A1(n1379), .B0(n409), .Y(n1378) );
AOI2BB2XLTS U1803 ( .B0(n1381), .B1(n1475), .A0N(n1738), .A1N(P_Sgf[22]),
.Y(n260) );
CMPR32X2TS U1804 ( .A(n1384), .B(n1383), .C(n1382), .CO(n1425), .S(n1385) );
AOI2BB2XLTS U1805 ( .B0(n1385), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[21]),
.Y(n259) );
CMPR32X2TS U1806 ( .A(n1388), .B(n1387), .C(n1386), .CO(n1400), .S(n1389) );
AOI2BB2XLTS U1807 ( .B0(n1389), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[17]),
.Y(n255) );
CMPR32X2TS U1808 ( .A(n1392), .B(n1391), .C(n1390), .CO(n1404), .S(n1393) );
AOI2BB2XLTS U1809 ( .B0(n1393), .B1(n1767), .A0N(n1716), .A1N(P_Sgf[13]),
.Y(n251) );
CMPR32X2TS U1810 ( .A(n1396), .B(n1395), .C(n1394), .CO(n1408), .S(n1397) );
AOI2BB2XLTS U1811 ( .B0(n1397), .B1(n1767), .A0N(n1416), .A1N(P_Sgf[9]), .Y(
n247) );
NOR2XLTS U1812 ( .A(n1783), .B(n413), .Y(n1398) );
AO22XLTS U1813 ( .A0(n1765), .A1(P_Sgf[0]), .B0(n1485), .B1(n1398), .Y(n238)
);
CMPR32X2TS U1814 ( .A(n1401), .B(n1400), .C(n1399), .CO(n1322), .S(n1402) );
AOI2BB2XLTS U1815 ( .B0(n1402), .B1(n1475), .A0N(n1738), .A1N(P_Sgf[18]),
.Y(n256) );
CMPR32X2TS U1816 ( .A(n1405), .B(n1404), .C(n1403), .CO(n1297), .S(n1406) );
AOI2BB2XLTS U1817 ( .B0(n1406), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[14]),
.Y(n252) );
CMPR32X2TS U1818 ( .A(n1409), .B(n1408), .C(n1407), .CO(n1353), .S(n1410) );
AOI2BB2XLTS U1819 ( .B0(n1410), .B1(n1767), .A0N(n1416), .A1N(P_Sgf[10]),
.Y(n248) );
XNOR2X1TS U1820 ( .A(n1412), .B(n1411), .Y(n1414) );
XNOR2X1TS U1821 ( .A(n1414), .B(n1413), .Y(n1415) );
AO22XLTS U1822 ( .A0(n1692), .A1(P_Sgf[8]), .B0(n1738), .B1(n1415), .Y(n246)
);
XOR2XLTS U1823 ( .A(n1420), .B(n1419), .Y(n1421) );
AO22XLTS U1824 ( .A0(n1771), .A1(P_Sgf[5]), .B0(n1485), .B1(n1421), .Y(n243)
);
AOI32X1TS U1825 ( .A0(n1643), .A1(n1495), .A2(n1422), .B0(n1859), .B1(n1494),
.Y(n307) );
INVX2TS U1826 ( .A(mult_x_19_n180), .Y(n1468) );
AOI22X1TS U1827 ( .A0(Op_MY[22]), .A1(n1588), .B0(n478), .B1(n420), .Y(n1423) );
NAND2X1TS U1828 ( .A(n1423), .B(n391), .Y(n1467) );
INVX2TS U1829 ( .A(mult_x_19_n181), .Y(n1673) );
INVX2TS U1830 ( .A(mult_x_19_n184), .Y(n1677) );
INVX2TS U1831 ( .A(mult_x_19_n182), .Y(n1676) );
INVX2TS U1832 ( .A(mult_x_19_n185), .Y(n1681) );
INVX2TS U1833 ( .A(mult_x_19_n188), .Y(n1680) );
INVX2TS U1834 ( .A(mult_x_19_n189), .Y(n1685) );
INVX2TS U1835 ( .A(mult_x_19_n192), .Y(n1684) );
INVX2TS U1836 ( .A(mult_x_19_n193), .Y(n1689) );
INVX2TS U1837 ( .A(mult_x_19_n198), .Y(n1695) );
INVX2TS U1838 ( .A(mult_x_19_n203), .Y(n1694) );
INVX2TS U1839 ( .A(mult_x_19_n204), .Y(n1699) );
INVX2TS U1840 ( .A(mult_x_19_n209), .Y(n1698) );
INVX2TS U1841 ( .A(mult_x_19_n210), .Y(n1703) );
INVX2TS U1842 ( .A(mult_x_19_n216), .Y(n1707) );
INVX2TS U1843 ( .A(mult_x_19_n222), .Y(n1706) );
INVX2TS U1844 ( .A(mult_x_19_n223), .Y(n1711) );
INVX2TS U1845 ( .A(mult_x_19_n229), .Y(n1710) );
INVX2TS U1846 ( .A(mult_x_19_n230), .Y(n1715) );
INVX2TS U1847 ( .A(mult_x_19_n238), .Y(n1720) );
INVX2TS U1848 ( .A(mult_x_19_n246), .Y(n1719) );
INVX2TS U1849 ( .A(mult_x_19_n247), .Y(n1724) );
INVX2TS U1850 ( .A(mult_x_19_n255), .Y(n1723) );
INVX2TS U1851 ( .A(mult_x_19_n256), .Y(n1728) );
INVX2TS U1852 ( .A(mult_x_19_n265), .Y(n1732) );
INVX2TS U1853 ( .A(mult_x_19_n274), .Y(n1731) );
INVX2TS U1854 ( .A(mult_x_19_n275), .Y(n1737) );
INVX2TS U1855 ( .A(mult_x_19_n284), .Y(n1736) );
INVX2TS U1856 ( .A(mult_x_19_n285), .Y(n1742) );
INVX2TS U1857 ( .A(mult_x_19_n296), .Y(n1746) );
INVX2TS U1858 ( .A(mult_x_19_n306), .Y(n1745) );
INVX2TS U1859 ( .A(mult_x_19_n307), .Y(n1750) );
INVX2TS U1860 ( .A(mult_x_19_n317), .Y(n1749) );
INVX2TS U1861 ( .A(mult_x_19_n318), .Y(n1754) );
INVX2TS U1862 ( .A(mult_x_19_n339), .Y(n1758) );
INVX2TS U1863 ( .A(mult_x_19_n329), .Y(n1757) );
INVX2TS U1864 ( .A(mult_x_19_n340), .Y(n1762) );
INVX2TS U1865 ( .A(mult_x_19_n351), .Y(n1474) );
CMPR32X2TS U1866 ( .A(n1426), .B(n1425), .C(n1424), .CO(n1473), .S(n1381) );
AOI22X1TS U1867 ( .A0(n1436), .A1(Op_MY[22]), .B0(n1427), .B1(n418), .Y(
n1429) );
OAI211XLTS U1868 ( .A0(n1463), .A1(n1431), .B0(n1429), .C0(n528), .Y(n1430)
);
XOR2X1TS U1869 ( .A(n1844), .B(n1430), .Y(n1472) );
OAI22X1TS U1870 ( .A0(n527), .A1(n484), .B0(n461), .B1(n1469), .Y(n1435) );
OAI21XLTS U1871 ( .A0(n1436), .A1(n1435), .B0(n1433), .Y(n1434) );
AOI22X1TS U1872 ( .A0(n394), .A1(Op_MY[22]), .B0(n1437), .B1(n418), .Y(n1438) );
OAI211XLTS U1873 ( .A0(n1463), .A1(n545), .B0(n1438), .C0(n442), .Y(n1440)
);
XOR2X1TS U1874 ( .A(n1626), .B(n1440), .Y(n1752) );
OAI22X1TS U1875 ( .A0(n1463), .A1(n1442), .B0(n423), .B1(n1441), .Y(n1443)
);
XOR2X1TS U1876 ( .A(n1446), .B(Op_MX[8]), .Y(n1740) );
OAI22X1TS U1877 ( .A0(n1463), .A1(n1215), .B0(n1782), .B1(n966), .Y(n1448)
);
AOI211X1TS U1878 ( .A0(n417), .A1(n1449), .B0(n392), .C0(n1448), .Y(n1450)
);
XOR2X1TS U1879 ( .A(n1450), .B(Op_MX[11]), .Y(n1726) );
OAI22X1TS U1880 ( .A0(n1463), .A1(n1452), .B0(n484), .B1(n536), .Y(n1453) );
AOI211X1TS U1881 ( .A0(n417), .A1(n1454), .B0(n430), .C0(n1453), .Y(n1455)
);
XOR2X1TS U1882 ( .A(n1455), .B(Op_MX[14]), .Y(n1713) );
AOI22X1TS U1883 ( .A0(n418), .A1(n1456), .B0(Op_MY[22]), .B1(n1190), .Y(
n1458) );
XOR2X1TS U1884 ( .A(n1625), .B(n1460), .Y(n1701) );
OAI22X1TS U1885 ( .A0(n1463), .A1(n1462), .B0(n485), .B1(n539), .Y(n1464) );
AOI211X1TS U1886 ( .A0(n417), .A1(n1465), .B0(n482), .C0(n1464), .Y(n1466)
);
XOR2X1TS U1887 ( .A(n1466), .B(Op_MX[20]), .Y(n1687) );
CMPR32X2TS U1888 ( .A(n417), .B(n1468), .C(n1467), .CO(n1481), .S(n1671) );
AOI21X1TS U1889 ( .A0(n419), .A1(n1469), .B0(n551), .Y(n1478) );
INVX2TS U1890 ( .A(n1478), .Y(n1477) );
AOI2BB2XLTS U1891 ( .B0(n1470), .B1(n1477), .A0N(n1477), .A1N(n1470), .Y(
n1479) );
AOI2BB2XLTS U1892 ( .B0(n1471), .B1(n1767), .A0N(n1716), .A1N(P_Sgf[46]),
.Y(n284) );
AOI2BB2XLTS U1893 ( .B0(n1495), .B1(Sgf_normalized_result[0]), .A0N(
Add_result[0]), .A1N(n1493), .Y(n309) );
CMPR32X2TS U1894 ( .A(n1474), .B(n1473), .C(n1472), .CO(n1761), .S(n1476) );
AOI2BB2XLTS U1895 ( .B0(n1476), .B1(n1475), .A0N(n1716), .A1N(P_Sgf[23]),
.Y(n261) );
CLKBUFX3TS U1896 ( .A(n1604), .Y(n1489) );
AO22XLTS U1897 ( .A0(n1489), .A1(Data_MY[28]), .B0(n425), .B1(Op_MY[28]),
.Y(n340) );
AO22XLTS U1898 ( .A0(n1489), .A1(Data_MY[24]), .B0(n425), .B1(Op_MY[24]),
.Y(n336) );
AO22XLTS U1899 ( .A0(n1489), .A1(Data_MY[25]), .B0(n425), .B1(Op_MY[25]),
.Y(n337) );
AO22XLTS U1900 ( .A0(n1489), .A1(Data_MY[29]), .B0(Op_MY[29]), .B1(n426),
.Y(n341) );
AO22XLTS U1901 ( .A0(n1489), .A1(Data_MY[27]), .B0(n425), .B1(Op_MY[27]),
.Y(n339) );
AO22XLTS U1902 ( .A0(n1489), .A1(Data_MY[26]), .B0(n425), .B1(Op_MY[26]),
.Y(n338) );
AO22XLTS U1903 ( .A0(n1489), .A1(Data_MY[23]), .B0(n425), .B1(Op_MY[23]),
.Y(n335) );
CMPR32X2TS U1904 ( .A(n1481), .B(n1480), .C(n1479), .CO(n1482), .S(n1471) );
XNOR2X1TS U1905 ( .A(n1483), .B(n1482), .Y(n1484) );
AO22XLTS U1906 ( .A0(n1771), .A1(P_Sgf[47]), .B0(n1485), .B1(n1484), .Y(n237) );
AO22XLTS U1907 ( .A0(n1489), .A1(Data_MY[30]), .B0(n426), .B1(Op_MY[30]),
.Y(n342) );
AO22XLTS U1908 ( .A0(n1489), .A1(Data_MX[30]), .B0(n426), .B1(Op_MX[30]),
.Y(n374) );
CLKBUFX3TS U1909 ( .A(n1604), .Y(n1611) );
AO22XLTS U1910 ( .A0(n1611), .A1(Data_MX[25]), .B0(n426), .B1(Op_MX[25]),
.Y(n369) );
AO22XLTS U1911 ( .A0(n1611), .A1(Data_MX[24]), .B0(n426), .B1(Op_MX[24]),
.Y(n368) );
AOI32X1TS U1912 ( .A0(n1488), .A1(n734), .A2(n1487), .B0(n1858), .B1(n1486),
.Y(n310) );
AO22XLTS U1913 ( .A0(n1611), .A1(Data_MX[27]), .B0(n426), .B1(Op_MX[27]),
.Y(n371) );
AO22XLTS U1914 ( .A0(n1489), .A1(Data_MX[29]), .B0(n426), .B1(Op_MX[29]),
.Y(n373) );
AO22XLTS U1915 ( .A0(n1611), .A1(Data_MX[26]), .B0(n426), .B1(Op_MX[26]),
.Y(n370) );
AO22XLTS U1916 ( .A0(n1611), .A1(Data_MX[23]), .B0(n426), .B1(Op_MX[23]),
.Y(n367) );
MX2X1TS U1917 ( .A(exp_oper_result[8]), .B(Exp_module_Data_S[8]), .S0(n1496),
.Y(n226) );
CLKAND2X2TS U1918 ( .A(FSM_selector_A), .B(exp_oper_result[8]), .Y(
S_Oper_A_exp[8]) );
MX2X1TS U1919 ( .A(exp_oper_result[7]), .B(Exp_module_Data_S[7]), .S0(n1496),
.Y(n227) );
MX2X1TS U1920 ( .A(Op_MX[30]), .B(exp_oper_result[7]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[7]) );
NOR3BX1TS U1921 ( .AN(Op_MY[30]), .B(FSM_selector_B[1]), .C(
FSM_selector_B[0]), .Y(n1490) );
XOR2X1TS U1922 ( .A(DP_OP_32J138_122_6543_n33), .B(n1490), .Y(
DP_OP_32J138_122_6543_n15) );
AO22XLTS U1923 ( .A0(n1611), .A1(Data_MX[28]), .B0(n426), .B1(Op_MX[28]),
.Y(n372) );
MX2X1TS U1924 ( .A(exp_oper_result[2]), .B(Exp_module_Data_S[2]), .S0(n1496),
.Y(n232) );
MX2X1TS U1925 ( .A(exp_oper_result[5]), .B(Exp_module_Data_S[5]), .S0(n1496),
.Y(n229) );
MX2X1TS U1926 ( .A(exp_oper_result[0]), .B(Exp_module_Data_S[0]), .S0(n1496),
.Y(n234) );
MX2X1TS U1927 ( .A(exp_oper_result[1]), .B(Exp_module_Data_S[1]), .S0(n1496),
.Y(n233) );
MX2X1TS U1928 ( .A(exp_oper_result[4]), .B(Exp_module_Data_S[4]), .S0(n1496),
.Y(n230) );
MX2X1TS U1929 ( .A(exp_oper_result[3]), .B(Exp_module_Data_S[3]), .S0(n1496),
.Y(n231) );
OAI21XLTS U1930 ( .A0(n1642), .A1(n1820), .B0(n1646), .Y(n1492) );
AO22XLTS U1931 ( .A0(n1493), .A1(n1492), .B0(n1491), .B1(Add_result[4]), .Y(
n305) );
AOI21X1TS U1932 ( .A0(n1668), .A1(Sgf_normalized_result[23]), .B0(n1494),
.Y(n1667) );
AOI2BB1XLTS U1933 ( .A0N(n1495), .A1N(FSM_add_overflow_flag), .B0(n1667),
.Y(n285) );
MX2X1TS U1934 ( .A(exp_oper_result[6]), .B(Exp_module_Data_S[6]), .S0(n1496),
.Y(n228) );
NOR2XLTS U1935 ( .A(FSM_selector_B[1]), .B(Op_MY[23]), .Y(n1497) );
NAND2X2TS U1936 ( .A(FSM_selector_B[0]), .B(n1801), .Y(n1504) );
XOR2X1TS U1937 ( .A(DP_OP_32J138_122_6543_n33), .B(n1498), .Y(
DP_OP_32J138_122_6543_n22) );
MX2X1TS U1938 ( .A(Op_MX[23]), .B(exp_oper_result[0]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[0]) );
MX2X1TS U1939 ( .A(Op_MX[24]), .B(exp_oper_result[1]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[1]) );
OAI2BB1X1TS U1940 ( .A0N(Op_MY[24]), .A1N(n1801), .B0(n1504), .Y(n1499) );
XOR2X1TS U1941 ( .A(DP_OP_32J138_122_6543_n33), .B(n1499), .Y(
DP_OP_32J138_122_6543_n21) );
MX2X1TS U1942 ( .A(Op_MX[25]), .B(exp_oper_result[2]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[2]) );
OAI2BB1X1TS U1943 ( .A0N(Op_MY[25]), .A1N(n1801), .B0(n1504), .Y(n1500) );
XOR2X1TS U1944 ( .A(DP_OP_32J138_122_6543_n33), .B(n1500), .Y(
DP_OP_32J138_122_6543_n20) );
MX2X1TS U1945 ( .A(Op_MX[26]), .B(exp_oper_result[3]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[3]) );
OAI2BB1X1TS U1946 ( .A0N(Op_MY[26]), .A1N(n1801), .B0(n1504), .Y(n1501) );
XOR2X1TS U1947 ( .A(DP_OP_32J138_122_6543_n33), .B(n1501), .Y(
DP_OP_32J138_122_6543_n19) );
MX2X1TS U1948 ( .A(Op_MX[27]), .B(exp_oper_result[4]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[4]) );
OAI2BB1X1TS U1949 ( .A0N(Op_MY[27]), .A1N(n1801), .B0(n1504), .Y(n1502) );
XOR2X1TS U1950 ( .A(n522), .B(n1502), .Y(DP_OP_32J138_122_6543_n18) );
MX2X1TS U1951 ( .A(Op_MX[28]), .B(exp_oper_result[5]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[5]) );
OAI2BB1X1TS U1952 ( .A0N(Op_MY[28]), .A1N(n1801), .B0(n1504), .Y(n1503) );
XOR2X1TS U1953 ( .A(n522), .B(n1503), .Y(DP_OP_32J138_122_6543_n17) );
MX2X1TS U1954 ( .A(Op_MX[29]), .B(exp_oper_result[6]), .S0(FSM_selector_A),
.Y(S_Oper_A_exp[6]) );
OAI2BB1X1TS U1955 ( .A0N(Op_MY[29]), .A1N(n1801), .B0(n1504), .Y(n1505) );
XOR2X1TS U1956 ( .A(n522), .B(n1505), .Y(DP_OP_32J138_122_6543_n16) );
XNOR2X1TS U1957 ( .A(n1507), .B(n1506), .Y(n1508) );
XOR2X1TS U1958 ( .A(n1509), .B(n1508), .Y(mult_x_19_n409) );
AOI22X1TS U1959 ( .A0(Op_MY[5]), .A1(n1588), .B0(Op_MY[7]), .B1(n452), .Y(
n1510) );
AOI21X1TS U1960 ( .A0(Op_MY[6]), .A1(n421), .B0(n1512), .Y(n1513) );
CMPR32X2TS U1961 ( .A(Op_MY[4]), .B(n409), .C(n1513), .CO(mult_x_19_n303),
.S(mult_x_19_n304) );
XNOR2X1TS U1962 ( .A(n1515), .B(n1514), .Y(n1516) );
XOR2X1TS U1963 ( .A(n1517), .B(n1516), .Y(mult_x_19_n454) );
CMPR32X2TS U1964 ( .A(n1519), .B(Op_MY[15]), .C(n1518), .CO(n1535), .S(n1080) );
XOR2X1TS U1965 ( .A(n1535), .B(n1520), .Y(mult_x_19_n200) );
AOI22X1TS U1966 ( .A0(Op_MY[3]), .A1(n1588), .B0(Op_MY[5]), .B1(n451), .Y(
n1521) );
OAI21XLTS U1967 ( .A0(n1522), .A1(n1584), .B0(n1521), .Y(n1523) );
AOI21X1TS U1968 ( .A0(Op_MY[4]), .A1(n421), .B0(n1523), .Y(n1524) );
CMPR32X2TS U1969 ( .A(n427), .B(n409), .C(n1524), .CO(mult_x_19_n325), .S(
mult_x_19_n326) );
AOI22X1TS U1970 ( .A0(Op_MY[4]), .A1(n1588), .B0(Op_MY[6]), .B1(n452), .Y(
n1525) );
OAI21XLTS U1971 ( .A0(n1584), .A1(n1526), .B0(n1525), .Y(n1527) );
AOI21X1TS U1972 ( .A0(Op_MY[5]), .A1(n421), .B0(n1527), .Y(n1528) );
CMPR32X2TS U1973 ( .A(Op_MY[3]), .B(n1356), .C(n1528), .CO(mult_x_19_n314),
.S(mult_x_19_n315) );
AOI22X1TS U1974 ( .A0(n1532), .A1(n1531), .B0(n1530), .B1(n1529), .Y(n1533)
);
OAI2BB1X1TS U1975 ( .A0N(n1534), .A1N(n1862), .B0(n1533), .Y(n378) );
NOR2XLTS U1976 ( .A(Op_MY[16]), .B(n1602), .Y(n1536) );
OAI22X1TS U1977 ( .A0(Op_MY[15]), .A1(n1600), .B0(n1536), .B1(n1535), .Y(
mult_x_19_n199) );
AOI22X1TS U1978 ( .A0(n1623), .A1(Op_MY[11]), .B0(n450), .B1(Op_MY[13]), .Y(
n1539) );
AOI22X1TS U1979 ( .A0(n419), .A1(n1537), .B0(n421), .B1(Op_MY[12]), .Y(n1538) );
NAND2X1TS U1980 ( .A(n1539), .B(n1538), .Y(n1541) );
OAI22X1TS U1981 ( .A0(Op_MY[9]), .A1(n1607), .B0(n1540), .B1(n1541), .Y(
mult_x_19_n242) );
XNOR2X1TS U1982 ( .A(n1542), .B(n1541), .Y(mult_x_19_n243) );
AOI2BB2XLTS U1983 ( .B0(n1543), .B1(n1800), .A0N(n1800), .A1N(n1543), .Y(
n1544) );
XNOR2X1TS U1984 ( .A(n1545), .B(n1544), .Y(mult_x_19_n348) );
AOI21X1TS U1985 ( .A0(n1547), .A1(n1546), .B0(n477), .Y(mult_x_19_n359) );
NAND2X1TS U1986 ( .A(mult_x_19_n435), .B(n401), .Y(n1549) );
XNOR2X1TS U1987 ( .A(n1549), .B(n1548), .Y(mult_x_19_n427) );
NAND2X1TS U1988 ( .A(mult_x_19_n471), .B(Op_MX[11]), .Y(n1551) );
XNOR2X1TS U1989 ( .A(n1551), .B(n1550), .Y(mult_x_19_n466) );
AOI22X1TS U1990 ( .A0(n418), .A1(n1586), .B0(Op_MY[22]), .B1(n451), .Y(n1552) );
OAI21XLTS U1991 ( .A0(n1553), .A1(n399), .B0(n1552), .Y(n1554) );
AOI21X1TS U1992 ( .A0(n551), .A1(Op_MY[20]), .B0(n1554), .Y(mult_x_19_n594)
);
AOI22X1TS U1993 ( .A0(n418), .A1(n450), .B0(n1588), .B1(Op_MY[19]), .Y(n1555) );
OAI21XLTS U1994 ( .A0(n391), .A1(n1798), .B0(n1555), .Y(n1556) );
AOI21X1TS U1995 ( .A0(n419), .A1(n1557), .B0(n1556), .Y(mult_x_19_n595) );
AOI22X1TS U1996 ( .A0(n1588), .A1(Op_MY[18]), .B0(n450), .B1(Op_MY[20]), .Y(
n1558) );
OAI21XLTS U1997 ( .A0(n391), .A1(n508), .B0(n1558), .Y(n1559) );
AOI21X1TS U1998 ( .A0(n420), .A1(n1560), .B0(n1559), .Y(mult_x_19_n596) );
AOI22X1TS U1999 ( .A0(n1623), .A1(Op_MY[17]), .B0(n451), .B1(Op_MY[19]), .Y(
n1561) );
OAI21XLTS U2000 ( .A0(n391), .A1(n480), .B0(n1561), .Y(n1562) );
AOI21X1TS U2001 ( .A0(n420), .A1(n1563), .B0(n1562), .Y(mult_x_19_n597) );
AOI22X1TS U2002 ( .A0(n1623), .A1(Op_MY[15]), .B0(n452), .B1(Op_MY[17]), .Y(
n1564) );
OAI21XLTS U2003 ( .A0(n1584), .A1(n1565), .B0(n1564), .Y(n1566) );
AOI21X1TS U2004 ( .A0(n421), .A1(Op_MY[16]), .B0(n1566), .Y(mult_x_19_n599)
);
AOI22X1TS U2005 ( .A0(n1586), .A1(Op_MY[15]), .B0(n451), .B1(Op_MY[16]), .Y(
n1567) );
OAI21XLTS U2006 ( .A0(n1568), .A1(n399), .B0(n1567), .Y(n1569) );
AOI21X1TS U2007 ( .A0(n1588), .A1(Op_MY[14]), .B0(n1569), .Y(mult_x_19_n600)
);
AOI22X1TS U2008 ( .A0(n1623), .A1(Op_MY[13]), .B0(n452), .B1(Op_MY[15]), .Y(
n1570) );
OAI21XLTS U2009 ( .A0(n1584), .A1(n1571), .B0(n1570), .Y(n1572) );
AOI21X1TS U2010 ( .A0(n421), .A1(Op_MY[14]), .B0(n1572), .Y(mult_x_19_n601)
);
AOI22X1TS U2011 ( .A0(n1623), .A1(Op_MY[12]), .B0(n451), .B1(Op_MY[14]), .Y(
n1573) );
OAI21XLTS U2012 ( .A0(n391), .A1(n1605), .B0(n1573), .Y(n1574) );
AOI21X1TS U2013 ( .A0(n420), .A1(n1575), .B0(n1574), .Y(mult_x_19_n602) );
AOI22X1TS U2014 ( .A0(n1623), .A1(Op_MY[9]), .B0(n452), .B1(Op_MY[11]), .Y(
n1576) );
OAI21XLTS U2015 ( .A0(n1584), .A1(n1577), .B0(n1576), .Y(n1578) );
AOI21X1TS U2016 ( .A0(n421), .A1(Op_MY[10]), .B0(n1578), .Y(mult_x_19_n605)
);
AOI22X1TS U2017 ( .A0(n1586), .A1(Op_MY[9]), .B0(n451), .B1(Op_MY[10]), .Y(
n1579) );
OAI21XLTS U2018 ( .A0(n1580), .A1(n1584), .B0(n1579), .Y(n1581) );
AOI21X1TS U2019 ( .A0(Op_MY[8]), .A1(n551), .B0(n1581), .Y(mult_x_19_n606)
);
AOI22X1TS U2020 ( .A0(Op_MY[7]), .A1(n1588), .B0(n452), .B1(Op_MY[9]), .Y(
n1582) );
AOI21X1TS U2021 ( .A0(Op_MY[8]), .A1(n421), .B0(n1585), .Y(mult_x_19_n607)
);
AOI22X1TS U2022 ( .A0(Op_MY[6]), .A1(n1588), .B0(Op_MY[8]), .B1(n452), .Y(
n1589) );
OAI21XLTS U2023 ( .A0(n1590), .A1(n391), .B0(n1589), .Y(n1591) );
AOI21X1TS U2024 ( .A0(n1592), .A1(n420), .B0(n1591), .Y(mult_x_19_n608) );
CLKBUFX3TS U2025 ( .A(n1594), .Y(n1612) );
OAI2BB2XLTS U2026 ( .B0(n398), .B1(n548), .A0N(n1612), .A1N(Data_MX[22]),
.Y(n366) );
OAI2BB2XLTS U2027 ( .B0(n398), .B1(n1810), .A0N(n1612), .A1N(Data_MX[21]),
.Y(n365) );
CLKBUFX3TS U2028 ( .A(n1594), .Y(n1597) );
OAI2BB2XLTS U2029 ( .B0(n1597), .B1(n1593), .A0N(n1612), .A1N(Data_MX[20]),
.Y(n364) );
CLKBUFX3TS U2030 ( .A(n1594), .Y(n1610) );
OAI2BB2XLTS U2031 ( .B0(n1597), .B1(n1795), .A0N(n1610), .A1N(Data_MX[19]),
.Y(n363) );
OAI2BB2XLTS U2032 ( .B0(n1597), .B1(n1805), .A0N(n1610), .A1N(Data_MX[18]),
.Y(n362) );
OAI2BB2XLTS U2033 ( .B0(n1597), .B1(n1846), .A0N(n1610), .A1N(Data_MX[17]),
.Y(n361) );
CLKBUFX3TS U2034 ( .A(n1596), .Y(n1613) );
CLKBUFX3TS U2035 ( .A(n1596), .Y(n1606) );
OAI2BB2XLTS U2036 ( .B0(n1613), .B1(n1784), .A0N(n1606), .A1N(Data_MX[16]),
.Y(n360) );
OAI2BB2XLTS U2037 ( .B0(n1597), .B1(n1808), .A0N(n1606), .A1N(Data_MX[15]),
.Y(n359) );
OAI2BB2XLTS U2038 ( .B0(n1613), .B1(n1595), .A0N(n1606), .A1N(Data_MX[14]),
.Y(n358) );
OAI2BB2XLTS U2039 ( .B0(n1597), .B1(n1785), .A0N(n1606), .A1N(Data_MX[13]),
.Y(n357) );
CLKBUFX3TS U2040 ( .A(n1596), .Y(n1601) );
OAI2BB2XLTS U2041 ( .B0(n1597), .B1(n1806), .A0N(n1601), .A1N(Data_MX[12]),
.Y(n356) );
OAI2BB2XLTS U2042 ( .B0(n1597), .B1(n1791), .A0N(n1604), .A1N(Data_MX[11]),
.Y(n355) );
OAI2BB2XLTS U2043 ( .B0(n1597), .B1(n1793), .A0N(n398), .A1N(Data_MX[10]),
.Y(n354) );
OAI2BB2XLTS U2044 ( .B0(n1597), .B1(n1804), .A0N(n398), .A1N(Data_MX[9]),
.Y(n353) );
OAI2BB2XLTS U2045 ( .B0(n1613), .B1(n1598), .A0N(n1594), .A1N(Data_MX[8]),
.Y(n352) );
OAI2BB2XLTS U2046 ( .B0(n1613), .B1(n1809), .A0N(n1601), .A1N(Data_MX[7]),
.Y(n351) );
OAI2BB2XLTS U2047 ( .B0(n1613), .B1(n1796), .A0N(n1610), .A1N(Data_MX[6]),
.Y(n350) );
OAI2BB2XLTS U2048 ( .B0(n1613), .B1(n1845), .A0N(n1601), .A1N(Data_MX[5]),
.Y(n349) );
OAI2BB2XLTS U2049 ( .B0(n1613), .B1(n1792), .A0N(n1612), .A1N(Data_MX[4]),
.Y(n348) );
OAI2BB2XLTS U2050 ( .B0(n1613), .B1(n1803), .A0N(n1601), .A1N(Data_MX[3]),
.Y(n347) );
OAI2BB2XLTS U2051 ( .B0(n1613), .B1(n1844), .A0N(n1601), .A1N(Data_MX[2]),
.Y(n346) );
CLKBUFX3TS U2052 ( .A(n1604), .Y(n1603) );
OAI2BB2XLTS U2053 ( .B0(n1603), .B1(n1777), .A0N(n1606), .A1N(Data_MX[1]),
.Y(n345) );
OAI2BB2XLTS U2054 ( .B0(n1603), .B1(n1783), .A0N(n1612), .A1N(Data_MX[0]),
.Y(n344) );
OAI2BB2XLTS U2055 ( .B0(n1603), .B1(n485), .A0N(n1601), .A1N(Data_MY[22]),
.Y(n334) );
OAI2BB2XLTS U2056 ( .B0(n1603), .B1(n424), .A0N(n398), .A1N(Data_MY[21]),
.Y(n333) );
OAI2BB2XLTS U2057 ( .B0(n1603), .B1(n503), .A0N(n1594), .A1N(Data_MY[20]),
.Y(n332) );
OAI2BB2XLTS U2058 ( .B0(n1603), .B1(n1779), .A0N(n1601), .A1N(Data_MY[19]),
.Y(n331) );
OAI2BB2XLTS U2059 ( .B0(n1603), .B1(n1857), .A0N(n1601), .A1N(Data_MY[18]),
.Y(n330) );
OAI2BB2XLTS U2060 ( .B0(n1603), .B1(n1599), .A0N(n1606), .A1N(Data_MY[17]),
.Y(n329) );
OAI2BB2XLTS U2061 ( .B0(n1603), .B1(n1600), .A0N(n1601), .A1N(Data_MY[16]),
.Y(n328) );
OAI2BB2XLTS U2062 ( .B0(n1603), .B1(n1602), .A0N(n1601), .A1N(Data_MY[15]),
.Y(n327) );
OAI2BB2XLTS U2063 ( .B0(n1594), .B1(n491), .A0N(n1606), .A1N(Data_MY[14]),
.Y(n326) );
OAI2BB2XLTS U2064 ( .B0(n1596), .B1(n1605), .A0N(n1606), .A1N(Data_MY[13]),
.Y(n325) );
OAI2BB2XLTS U2065 ( .B0(n1604), .B1(n514), .A0N(n1610), .A1N(Data_MY[12]),
.Y(n324) );
OAI2BB2XLTS U2066 ( .B0(n1594), .B1(n509), .A0N(n1606), .A1N(Data_MY[11]),
.Y(n323) );
OAI2BB2XLTS U2067 ( .B0(n1596), .B1(n1607), .A0N(n1606), .A1N(Data_MY[10]),
.Y(n322) );
OAI2BB2XLTS U2068 ( .B0(n1604), .B1(n1608), .A0N(n1610), .A1N(Data_MY[9]),
.Y(n321) );
OAI2BB2XLTS U2069 ( .B0(n1594), .B1(n494), .A0N(n1610), .A1N(Data_MY[8]),
.Y(n320) );
OAI2BB2XLTS U2070 ( .B0(n1596), .B1(n1609), .A0N(n1610), .A1N(Data_MY[7]),
.Y(n319) );
OAI2BB2XLTS U2071 ( .B0(n1604), .B1(n518), .A0N(n1610), .A1N(Data_MY[6]),
.Y(n318) );
OAI2BB2XLTS U2072 ( .B0(n1594), .B1(n512), .A0N(n1610), .A1N(Data_MY[5]),
.Y(n317) );
OAI2BB2XLTS U2073 ( .B0(n1611), .B1(n497), .A0N(n1612), .A1N(Data_MY[4]),
.Y(n316) );
OAI2BB2XLTS U2074 ( .B0(n1611), .B1(n501), .A0N(n1612), .A1N(Data_MY[3]),
.Y(n315) );
OAI2BB2XLTS U2075 ( .B0(n1611), .B1(n429), .A0N(n1612), .A1N(Data_MY[2]),
.Y(n314) );
OAI2BB2XLTS U2076 ( .B0(n1611), .B1(n1780), .A0N(n1612), .A1N(Data_MY[1]),
.Y(n313) );
OAI2BB2XLTS U2077 ( .B0(n1613), .B1(n1800), .A0N(n1612), .A1N(Data_MY[0]),
.Y(n312) );
NOR4X1TS U2078 ( .A(Op_MY[4]), .B(Op_MY[5]), .C(Op_MY[7]), .D(Op_MY[6]), .Y(
n1638) );
NOR4X1TS U2079 ( .A(Op_MY[8]), .B(Op_MY[29]), .C(Op_MY[28]), .D(Op_MY[27]),
.Y(n1637) );
NOR2XLTS U2080 ( .A(Op_MY[1]), .B(Op_MY[0]), .Y(n1615) );
NAND4XLTS U2081 ( .A(n1615), .B(n485), .C(n424), .D(n1614), .Y(n1621) );
NOR4X1TS U2082 ( .A(Op_MY[30]), .B(Op_MY[12]), .C(Op_MY[13]), .D(Op_MY[14]),
.Y(n1619) );
NOR4X1TS U2083 ( .A(Op_MY[26]), .B(Op_MY[25]), .C(Op_MY[24]), .D(Op_MY[23]),
.Y(n1618) );
NOR4X1TS U2084 ( .A(Op_MY[9]), .B(Op_MY[11]), .C(Op_MY[16]), .D(Op_MY[15]),
.Y(n1617) );
NOR4X1TS U2085 ( .A(Op_MY[18]), .B(Op_MY[19]), .C(Op_MY[20]), .D(Op_MY[10]),
.Y(n1616) );
NAND4XLTS U2086 ( .A(n1619), .B(n1618), .C(n1617), .D(n1616), .Y(n1620) );
NOR4X1TS U2087 ( .A(Op_MY[3]), .B(Op_MY[2]), .C(n1621), .D(n1620), .Y(n1636)
);
NOR2XLTS U2088 ( .A(Op_MX[6]), .B(Op_MX[7]), .Y(n1622) );
NAND4XLTS U2089 ( .A(n1623), .B(n1622), .C(n1793), .D(n1804), .Y(n1634) );
NAND4XLTS U2090 ( .A(n1792), .B(n1626), .C(n1625), .D(n1624), .Y(n1633) );
NAND4XLTS U2091 ( .A(n410), .B(n1783), .C(n1777), .D(n1803), .Y(n1632) );
NOR4X1TS U2092 ( .A(Op_MX[11]), .B(Op_MX[8]), .C(Op_MX[30]), .D(Op_MX[29]),
.Y(n1630) );
NOR4X1TS U2093 ( .A(Op_MX[12]), .B(Op_MX[13]), .C(Op_MX[25]), .D(Op_MX[23]),
.Y(n1628) );
NOR4X1TS U2094 ( .A(Op_MX[28]), .B(Op_MX[27]), .C(Op_MX[24]), .D(Op_MX[26]),
.Y(n1627) );
NAND4XLTS U2095 ( .A(n1630), .B(n1629), .C(n1628), .D(n1627), .Y(n1631) );
NOR4X1TS U2096 ( .A(n1634), .B(n1633), .C(n1632), .D(n1631), .Y(n1635) );
AOI31XLTS U2097 ( .A0(n1638), .A1(n1637), .A2(n1636), .B0(n1635), .Y(n1640)
);
AOI22X1TS U2098 ( .A0(n1641), .A1(n1640), .B0(n1807), .B1(n1639), .Y(n311)
);
OAI211XLTS U2099 ( .A0(Sgf_normalized_result[3]), .A1(n1643), .B0(n1664),
.C0(n1642), .Y(n1644) );
OAI2BB1X1TS U2100 ( .A0N(Add_result[3]), .A1N(n1670), .B0(n1644), .Y(n306)
);
OAI211XLTS U2101 ( .A0(Sgf_normalized_result[5]), .A1(n1646), .B0(n1664),
.C0(n1645), .Y(n1647) );
OAI2BB1X1TS U2102 ( .A0N(Add_result[5]), .A1N(n1491), .B0(n1647), .Y(n304)
);
OAI2BB1X1TS U2103 ( .A0N(Add_result[11]), .A1N(n1670), .B0(n1650), .Y(n298)
);
OAI2BB1X1TS U2104 ( .A0N(Add_result[13]), .A1N(n1670), .B0(n1653), .Y(n296)
);
OAI2BB1X1TS U2105 ( .A0N(Add_result[15]), .A1N(n1670), .B0(n1656), .Y(n294)
);
OAI2BB1X1TS U2106 ( .A0N(Add_result[17]), .A1N(n1670), .B0(n1659), .Y(n292)
);
OAI2BB1X1TS U2107 ( .A0N(Add_result[19]), .A1N(n1670), .B0(n1662), .Y(n290)
);
OAI2BB1X1TS U2108 ( .A0N(Add_result[21]), .A1N(n1670), .B0(n1666), .Y(n288)
);
OAI2BB1X1TS U2109 ( .A0N(Add_result[23]), .A1N(n1670), .B0(n1669), .Y(n286)
);
CMPR32X2TS U2110 ( .A(n1673), .B(n1672), .C(n1671), .CO(n1480), .S(n1674) );
AOI22X1TS U2111 ( .A0(n1765), .A1(n1821), .B0(n1674), .B1(n1416), .Y(n283)
);
CMPR32X2TS U2112 ( .A(n1677), .B(n1676), .C(n1675), .CO(n1672), .S(n1678) );
AOI22X1TS U2113 ( .A0(n1691), .A1(n1822), .B0(n1678), .B1(n1738), .Y(n282)
);
CMPR32X2TS U2114 ( .A(n1681), .B(n1680), .C(n1679), .CO(n1675), .S(n1682) );
AOI22X1TS U2115 ( .A0(n1691), .A1(n1823), .B0(n1682), .B1(n1416), .Y(n281)
);
CMPR32X2TS U2116 ( .A(n1685), .B(n1684), .C(n1683), .CO(n1679), .S(n1686) );
AOI22X1TS U2117 ( .A0(n1691), .A1(n1824), .B0(n1686), .B1(n1763), .Y(n280)
);
CMPR32X2TS U2118 ( .A(n1689), .B(n1688), .C(n1687), .CO(n1683), .S(n1690) );
AOI22X1TS U2119 ( .A0(n1691), .A1(n1825), .B0(n1690), .B1(n1738), .Y(n279)
);
CLKBUFX3TS U2120 ( .A(n1692), .Y(n1734) );
CMPR32X2TS U2121 ( .A(n1695), .B(n1694), .C(n1693), .CO(n1688), .S(n1696) );
AOI22X1TS U2122 ( .A0(n1734), .A1(n1826), .B0(n1696), .B1(n1416), .Y(n278)
);
CMPR32X2TS U2123 ( .A(n1699), .B(n1698), .C(n1697), .CO(n1693), .S(n1700) );
AOI22X1TS U2124 ( .A0(n1734), .A1(n1827), .B0(n1700), .B1(n1738), .Y(n277)
);
CMPR32X2TS U2125 ( .A(n1703), .B(n1702), .C(n1701), .CO(n1697), .S(n1704) );
AOI22X1TS U2126 ( .A0(n1734), .A1(n1828), .B0(n1704), .B1(n1763), .Y(n276)
);
CMPR32X2TS U2127 ( .A(n1707), .B(n1706), .C(n1705), .CO(n1702), .S(n1708) );
AOI22X1TS U2128 ( .A0(n1734), .A1(n1829), .B0(n1708), .B1(n1416), .Y(n275)
);
CMPR32X2TS U2129 ( .A(n1711), .B(n1710), .C(n1709), .CO(n1705), .S(n1712) );
AOI22X1TS U2130 ( .A0(n1734), .A1(n1830), .B0(n1712), .B1(n1716), .Y(n274)
);
CMPR32X2TS U2131 ( .A(n1715), .B(n1714), .C(n1713), .CO(n1709), .S(n1717) );
AOI22X1TS U2132 ( .A0(n1734), .A1(n1831), .B0(n1717), .B1(n1716), .Y(n273)
);
CMPR32X2TS U2133 ( .A(n1720), .B(n1719), .C(n1718), .CO(n1714), .S(n1721) );
AOI22X1TS U2134 ( .A0(n1734), .A1(n1832), .B0(n1721), .B1(n1738), .Y(n272)
);
CMPR32X2TS U2135 ( .A(n1724), .B(n1723), .C(n1722), .CO(n1718), .S(n1725) );
AOI22X1TS U2136 ( .A0(n1734), .A1(n1833), .B0(n1725), .B1(n1416), .Y(n271)
);
CMPR32X2TS U2137 ( .A(n1728), .B(n1727), .C(n1726), .CO(n1722), .S(n1729) );
AOI22X1TS U2138 ( .A0(n1734), .A1(n1834), .B0(n1729), .B1(n1763), .Y(n270)
);
CMPR32X2TS U2139 ( .A(n1732), .B(n1731), .C(n1730), .CO(n1727), .S(n1733) );
AOI22X1TS U2140 ( .A0(n1734), .A1(n1835), .B0(n1733), .B1(n1763), .Y(n269)
);
CMPR32X2TS U2141 ( .A(n1737), .B(n1736), .C(n1735), .CO(n1730), .S(n1739) );
AOI22X1TS U2142 ( .A0(n1765), .A1(n1836), .B0(n1739), .B1(n1738), .Y(n268)
);
CMPR32X2TS U2143 ( .A(n1742), .B(n1741), .C(n1740), .CO(n1735), .S(n1743) );
AOI22X1TS U2144 ( .A0(n1765), .A1(n1837), .B0(n1743), .B1(n1763), .Y(n267)
);
CMPR32X2TS U2145 ( .A(n1746), .B(n1745), .C(n1744), .CO(n1741), .S(n1747) );
AOI22X1TS U2146 ( .A0(n1765), .A1(n1838), .B0(n1747), .B1(n1763), .Y(n266)
);
CMPR32X2TS U2147 ( .A(n1750), .B(n1749), .C(n1748), .CO(n1744), .S(n1751) );
AOI22X1TS U2148 ( .A0(n1765), .A1(n1839), .B0(n1751), .B1(n1763), .Y(n265)
);
CMPR32X2TS U2149 ( .A(n1754), .B(n1753), .C(n1752), .CO(n1748), .S(n1755) );
AOI22X1TS U2150 ( .A0(n1765), .A1(n1840), .B0(n1755), .B1(n1763), .Y(n264)
);
CMPR32X2TS U2151 ( .A(n1758), .B(n1757), .C(n1756), .CO(n1753), .S(n1759) );
AOI22X1TS U2152 ( .A0(n1765), .A1(n1841), .B0(n1759), .B1(n1763), .Y(n263)
);
CMPR32X2TS U2153 ( .A(n1762), .B(n1761), .C(n1760), .CO(n1756), .S(n1764) );
AOI22X1TS U2154 ( .A0(n1765), .A1(n1842), .B0(n1764), .B1(n1763), .Y(n262)
);
OAI2BB1X1TS U2155 ( .A0N(n1771), .A1N(P_Sgf[3]), .B0(n1770), .Y(n241) );
OAI2BB2XLTS U2156 ( .B0(n1820), .B1(n422), .A0N(final_result_ieee[4]), .A1N(
n1331), .Y(n196) );
OAI2BB2XLTS U2157 ( .B0(n1811), .B1(n422), .A0N(final_result_ieee[6]), .A1N(
n1331), .Y(n194) );
OAI2BB2XLTS U2158 ( .B0(n1812), .B1(n422), .A0N(final_result_ieee[8]), .A1N(
n1773), .Y(n192) );
OAI2BB2XLTS U2159 ( .B0(n1813), .B1(n422), .A0N(final_result_ieee[10]),
.A1N(n1773), .Y(n190) );
OAI2BB2XLTS U2160 ( .B0(n1814), .B1(n422), .A0N(final_result_ieee[12]),
.A1N(n1773), .Y(n188) );
OAI2BB2XLTS U2161 ( .B0(n1815), .B1(n422), .A0N(final_result_ieee[14]),
.A1N(n1773), .Y(n186) );
OAI2BB2XLTS U2162 ( .B0(n1816), .B1(n422), .A0N(final_result_ieee[16]),
.A1N(n1773), .Y(n184) );
OAI2BB2XLTS U2163 ( .B0(n1817), .B1(n422), .A0N(final_result_ieee[18]),
.A1N(n1773), .Y(n182) );
OAI2BB2XLTS U2164 ( .B0(n1818), .B1(n422), .A0N(final_result_ieee[20]),
.A1N(n1773), .Y(n180) );
OAI2BB2XLTS U2165 ( .B0(n1819), .B1(n414), .A0N(final_result_ieee[22]),
.A1N(n1773), .Y(n178) );
OA22X1TS U2166 ( .A0(n1774), .A1(final_result_ieee[23]), .B0(
exp_oper_result[0]), .B1(n422), .Y(n177) );
OA22X1TS U2167 ( .A0(n1774), .A1(final_result_ieee[24]), .B0(
exp_oper_result[1]), .B1(n414), .Y(n176) );
OA22X1TS U2168 ( .A0(n1774), .A1(final_result_ieee[25]), .B0(
exp_oper_result[2]), .B1(n414), .Y(n175) );
OA22X1TS U2169 ( .A0(n1774), .A1(final_result_ieee[26]), .B0(
exp_oper_result[3]), .B1(n414), .Y(n174) );
OA22X1TS U2170 ( .A0(n1774), .A1(final_result_ieee[27]), .B0(
exp_oper_result[4]), .B1(n414), .Y(n173) );
OA22X1TS U2171 ( .A0(n1774), .A1(final_result_ieee[28]), .B0(
exp_oper_result[5]), .B1(n414), .Y(n172) );
OA22X1TS U2172 ( .A0(n1774), .A1(final_result_ieee[29]), .B0(
exp_oper_result[6]), .B1(n414), .Y(n171) );
OA22X1TS U2173 ( .A0(n1774), .A1(final_result_ieee[30]), .B0(
exp_oper_result[7]), .B1(n414), .Y(n170) );
initial $sdf_annotate("FPU_Multiplication_Function_ASIC_fpu_syn_constraints_noclk.tcl_DW_1STAGE_syn.sdf");
endmodule
|
// megafunction wizard: %ALTERA_FP_FUNCTIONS v15.1%
// GENERATION: XML
// xlr8_float_mult2.v
// Generated using ACDS version 15.1 185
`timescale 1 ps / 1 ps
module xlr8_float_mult2 (
input wire clk, // clk.clk
input wire areset, // areset.reset
input wire [0:0] en, // en.en
input wire [31:0] a, // a.a
input wire [31:0] b, // b.b
output wire [31:0] q // q.q
);
xlr8_float_mult2_0002 xlr8_float_mult2_inst (
.clk (clk), // clk.clk
.areset (areset), // areset.reset
.en (en), // en.en
.a (a), // a.a
.b (b), // b.b
.q (q) // q.q
);
endmodule
// Retrieval info: <?xml version="1.0"?>
//<!--
// Generated by Altera MegaWizard Launcher Utility version 1.0
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// ************************************************************
// Copyright (C) 1991-2016 Altera Corporation
// Any megafunction design, and related net list (encrypted or decrypted),
// support information, device programming or simulation file, and any other
// associated documentation or information provided by Altera or a partner
// under Altera's Megafunction Partnership Program may be used only to
// program PLD devices (but not masked PLD devices) from Altera. Any other
// use of such megafunction design, net list, support information, device
// programming or simulation file, or any other related documentation or
// information is prohibited for any other purpose, including, but not
// limited to modification, reverse engineering, de-compiling, or use with
// any other silicon devices, unless such use is explicitly licensed under
// a separate agreement with Altera or a megafunction partner. Title to
// the intellectual property, including patents, copyrights, trademarks,
// trade secrets, or maskworks, embodied in any such megafunction design,
// net list, support information, device programming or simulation file, or
// any other related documentation or information provided by Altera or a
// megafunction partner, remains with Altera, the megafunction partner, or
// their respective licensors. No other licenses, including any licenses
// needed under any third party's intellectual property, are provided herein.
//-->
// Retrieval info: <instance entity-name="altera_fp_functions" version="15.1" >
// Retrieval info: <generic name="FUNCTION_FAMILY" value="ARITH" />
// Retrieval info: <generic name="ARITH_function" value="MUL" />
// Retrieval info: <generic name="CONVERT_function" value="FXP_FP" />
// Retrieval info: <generic name="ALL_function" value="ADD" />
// Retrieval info: <generic name="EXP_LOG_function" value="EXPE" />
// Retrieval info: <generic name="TRIG_function" value="SIN" />
// Retrieval info: <generic name="COMPARE_function" value="MIN" />
// Retrieval info: <generic name="ROOTS_function" value="SQRT" />
// Retrieval info: <generic name="fp_format" value="single" />
// Retrieval info: <generic name="fp_exp" value="8" />
// Retrieval info: <generic name="fp_man" value="23" />
// Retrieval info: <generic name="exponent_width" value="23" />
// Retrieval info: <generic name="frequency_target" value="200" />
// Retrieval info: <generic name="latency_target" value="2" />
// Retrieval info: <generic name="performance_goal" value="latency" />
// Retrieval info: <generic name="rounding_mode" value="nearest with tie breaking away from zero" />
// Retrieval info: <generic name="faithful_rounding" value="false" />
// Retrieval info: <generic name="gen_enable" value="true" />
// Retrieval info: <generic name="divide_type" value="0" />
// Retrieval info: <generic name="select_signal_enable" value="false" />
// Retrieval info: <generic name="scale_by_pi" value="false" />
// Retrieval info: <generic name="number_of_inputs" value="2" />
// Retrieval info: <generic name="trig_no_range_reduction" value="false" />
// Retrieval info: <generic name="report_resources_to_xml" value="false" />
// Retrieval info: <generic name="fxpt_width" value="32" />
// Retrieval info: <generic name="fxpt_fraction" value="0" />
// Retrieval info: <generic name="fxpt_sign" value="1" />
// Retrieval info: <generic name="fp_out_format" value="single" />
// Retrieval info: <generic name="fp_out_exp" value="8" />
// Retrieval info: <generic name="fp_out_man" value="23" />
// Retrieval info: <generic name="fp_in_format" value="single" />
// Retrieval info: <generic name="fp_in_exp" value="8" />
// Retrieval info: <generic name="fp_in_man" value="23" />
// Retrieval info: <generic name="enable_hard_fp" value="true" />
// Retrieval info: <generic name="manual_dsp_planning" value="true" />
// Retrieval info: <generic name="forceRegisters" value="1111" />
// Retrieval info: <generic name="selected_device_family" value="MAX 10" />
// Retrieval info: <generic name="selected_device_speedgrade" value="6" />
// Retrieval info: </instance>
// IPFS_FILES : xlr8_float_mult2.vo
// RELATED_FILES: xlr8_float_mult2.v, dspba_library_package.vhd, dspba_library.vhd, xlr8_float_mult2_0002.vhd
|
module MSS_XTLOSC(
XTL,
CLKOUT );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="XTL" */
output CLKOUT;
input XTL;
endmodule
module MSS_LPXTLOSC(
LPXIN,
CLKOUT );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="LPXIN" */
output CLKOUT;
input LPXIN;
endmodule
module INBUF_MSS(
PAD,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
input PAD;
output Y;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module OUTBUF_MSS(
D,
PAD );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
input D;
output PAD;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module TRIBUFF_MSS(
D,
E,
PAD );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
input D;
input E;
output PAD;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module BIBUF_MSS(
PAD,
D,
E,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
inout PAD;
input D;
input E;
output Y;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module BIBUF_OPEND_MSS(
PAD,
E,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
inout PAD;
input E;
output Y;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module INBUF_MCCC(
PAD,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PAD" */
input PAD;
output Y;
parameter ACT_PIN = "";
parameter ACT_CONFIG = 1'b0;
endmodule
module INBUF_LVPECL_MCCC(
PADP,
PADN,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PADP, PADN" */
input PADP;
input PADN;
output Y;
parameter ACT_PIN = "";
endmodule
module INBUF_LVDS_MCCC(
PADP,
PADN,
Y );
/* synthesis syn_black_box */
/* synthesis black_box_pad_pin ="PADP, PADN" */
input PADP;
input PADN;
output Y;
parameter ACT_PIN = "";
endmodule
module MSSINT(Y,A);
/* synthesis syn_black_box */
input A;
output Y;
endmodule
module MSS_CCC(
CLKA,
EXTFB,
GLA,
GLAMSS,
LOCK,
LOCKMSS,
CLKB,
GLB,
YB,
CLKC,
GLC,
YC,
MACCLK,
OADIV,
OADIVHALF,
OAMUX,
BYPASSA,
DLYGLA,
DLYGLAMSS,
DLYGLAFAB,
OBDIV,
OBDIVHALF,
OBMUX,
BYPASSB,
DLYGLB,
OCDIV,
OCDIVHALF,
OCMUX,
BYPASSC,
DLYGLC,
FINDIV,
FBDIV,
FBDLY,
FBSEL,
XDLYSEL,
GLMUXSEL,
GLMUXCFG
);
/* synthesis syn_black_box */
input CLKA;
input EXTFB;
output GLA;
output GLAMSS;
output LOCK;
output LOCKMSS;
input CLKB;
output GLB;
output YB;
input CLKC;
output GLC;
output YC;
output MACCLK;
input [4:0] OADIV;
input OADIVHALF;
input [2:0] OAMUX;
input BYPASSA;
input [4:0] DLYGLA;
input [4:0] DLYGLAMSS;
input [4:0] DLYGLAFAB;
input [4:0] OBDIV;
input OBDIVHALF;
input [2:0] OBMUX;
input BYPASSB;
input [4:0] DLYGLB;
input [4:0] OCDIV;
input OCDIVHALF;
input [2:0] OCMUX;
input BYPASSC;
input [4:0] DLYGLC;
input [6:0] FINDIV;
input [6:0] FBDIV;
input [4:0] FBDLY;
input [1:0] FBSEL;
input XDLYSEL;
input [1:0] GLMUXSEL;
input [1:0] GLMUXCFG;
parameter VCOFREQUENCY = 0.0;
endmodule
module MSS_ALL(
HMADDR,
HMWDATA,
HMTRANS,
HMSIZE,
HMMASTLOCK,
HMAHBWRITE,
HMRDATA,
HMAHBREADY,
HMRESP,
FMADDR,
FMWDATA,
FMTRANS,
FMSIZE,
FMMASTLOCK,
FMAHBWRITE,
FMAHBSEL,
FMAHBREADY,
FMRDATA,
FMREADYOUT,
FMRESP,
HMPSEL,
HMPENABLE,
HMPWRITE,
FMPSLVERR,
HMPREADY,
HMPSLVERR,
FMPSEL,
FMPENABLE,
FMPWRITE,
FMPREADY,
SYNCCLKFDBK,
CALIBOUT,
CALIBIN,
FABINT,
MSSINT,
WDINT,
F2MRESETn,
DMAREADY,
RXEV,
VRON,
M2FRESETn,
DEEPSLEEP,
SLEEP,
TXEV,
UART0CTSn,
UART0DSRn,
UART0RIn,
UART0DCDn,
UART0RTSn,
UART0DTRn,
UART1CTSn,
UART1DSRn,
UART1RIn,
UART1DCDn,
UART1RTSn,
UART1DTRn,
I2C0SMBUSNI,
I2C0SMBALERTNI,
I2C0BCLK,
I2C0SMBUSNO,
I2C0SMBALERTNO,
I2C1SMBUSNI,
I2C1SMBALERTNI,
I2C1BCLK,
I2C1SMBUSNO,
I2C1SMBALERTNO,
MACM2FTXD,
MACF2MRXD,
MACM2FTXEN,
MACF2MCRSDV,
MACF2MRXER,
MACF2MMDI,
MACM2FMDO,
MACM2FMDEN,
MACM2FMDC,
FABSDD0D,
FABSDD1D,
FABSDD2D,
FABSDD0CLK,
FABSDD1CLK,
FABSDD2CLK,
FABACETRIG,
ACEFLAGS,
CMP0,
CMP1,
CMP2,
CMP3,
CMP4,
CMP5,
CMP6,
CMP7,
CMP8,
CMP9,
CMP10,
CMP11,
LVTTL0EN,
LVTTL1EN,
LVTTL2EN,
LVTTL3EN,
LVTTL4EN,
LVTTL5EN,
LVTTL6EN,
LVTTL7EN,
LVTTL8EN,
LVTTL9EN,
LVTTL10EN,
LVTTL11EN,
LVTTL0,
LVTTL1,
LVTTL2,
LVTTL3,
LVTTL4,
LVTTL5,
LVTTL6,
LVTTL7,
LVTTL8,
LVTTL9,
LVTTL10,
LVTTL11,
PUFABn,
VCC15GOOD,
VCC33GOOD,
FCLK,
MACCLKCCC,
RCOSC,
MACCLK,
PLLLOCK,
MSSRESETn,
GPI,
GPO,
GPOE,
SPI0DO,
SPI0DOE,
SPI0DI,
SPI0CLKI,
SPI0CLKO,
SPI0MODE,
SPI0SSI,
SPI0SSO,
UART0TXD,
UART0RXD,
I2C0SDAI,
I2C0SDAO,
I2C0SCLI,
I2C0SCLO,
SPI1DO,
SPI1DOE,
SPI1DI,
SPI1CLKI,
SPI1CLKO,
SPI1MODE,
SPI1SSI,
SPI1SSO,
UART1TXD,
UART1RXD,
I2C1SDAI,
I2C1SDAO,
I2C1SCLI,
I2C1SCLO,
MACTXD,
MACRXD,
MACTXEN,
MACCRSDV,
MACRXER,
MACMDI,
MACMDO,
MACMDEN,
MACMDC,
EMCCLK,
EMCCLKRTN,
EMCRDB,
EMCAB,
EMCWDB,
EMCRWn,
EMCCS0n,
EMCCS1n,
EMCOEN0n,
EMCOEN1n,
EMCBYTEN,
EMCDBOE,
ADC0,
ADC1,
ADC2,
ADC3,
ADC4,
ADC5,
ADC6,
ADC7,
ADC8,
ADC9,
ADC10,
ADC11,
SDD0,
SDD1,
SDD2,
ABPS0,
ABPS1,
ABPS2,
ABPS3,
ABPS4,
ABPS5,
ABPS6,
ABPS7,
ABPS8,
ABPS9,
ABPS10,
ABPS11,
TM0,
TM1,
TM2,
TM3,
TM4,
TM5,
CM0,
CM1,
CM2,
CM3,
CM4,
CM5,
GNDTM0,
GNDTM1,
GNDTM2,
VAREF0,
VAREF1,
VAREF2,
VAREFOUT,
GNDVAREF,
PUn
);
/* synthesis syn_black_box */
output [19:0] HMADDR;
output [31:0] HMWDATA;
output HMTRANS;
output [1:0] HMSIZE;
output HMMASTLOCK;
output HMAHBWRITE;
input [31:0] HMRDATA;
input HMAHBREADY;
input HMRESP;
input [31:0] FMADDR;
input [31:0] FMWDATA;
input FMTRANS;
input [1:0] FMSIZE;
input FMMASTLOCK;
input FMAHBWRITE;
input FMAHBSEL;
input FMAHBREADY;
output [31:0] FMRDATA;
output FMREADYOUT;
output FMRESP;
output HMPSEL;
output HMPENABLE;
output HMPWRITE;
output FMPSLVERR;
input HMPREADY;
input HMPSLVERR;
input FMPSEL;
input FMPENABLE;
input FMPWRITE;
output FMPREADY;
input SYNCCLKFDBK;
output CALIBOUT;
input CALIBIN;
input FABINT;
output [7:0] MSSINT;
output WDINT;
input F2MRESETn;
input [1:0] DMAREADY;
input RXEV;
input VRON;
output M2FRESETn;
output DEEPSLEEP;
output SLEEP;
output TXEV;
input UART0CTSn;
input UART0DSRn;
input UART0RIn;
input UART0DCDn;
output UART0RTSn;
output UART0DTRn;
input UART1CTSn;
input UART1DSRn;
input UART1RIn;
input UART1DCDn;
output UART1RTSn;
output UART1DTRn;
input I2C0SMBUSNI;
input I2C0SMBALERTNI;
input I2C0BCLK;
output I2C0SMBUSNO;
output I2C0SMBALERTNO;
input I2C1SMBUSNI;
input I2C1SMBALERTNI;
input I2C1BCLK;
output I2C1SMBUSNO;
output I2C1SMBALERTNO;
output [1:0] MACM2FTXD;
input [1:0] MACF2MRXD;
output MACM2FTXEN;
input MACF2MCRSDV;
input MACF2MRXER;
input MACF2MMDI;
output MACM2FMDO;
output MACM2FMDEN;
output MACM2FMDC;
input FABSDD0D;
input FABSDD1D;
input FABSDD2D;
input FABSDD0CLK;
input FABSDD1CLK;
input FABSDD2CLK;
input FABACETRIG;
output [31:0] ACEFLAGS;
output CMP0;
output CMP1;
output CMP2;
output CMP3;
output CMP4;
output CMP5;
output CMP6;
output CMP7;
output CMP8;
output CMP9;
output CMP10;
output CMP11;
input LVTTL0EN;
input LVTTL1EN;
input LVTTL2EN;
input LVTTL3EN;
input LVTTL4EN;
input LVTTL5EN;
input LVTTL6EN;
input LVTTL7EN;
input LVTTL8EN;
input LVTTL9EN;
input LVTTL10EN;
input LVTTL11EN;
output LVTTL0;
output LVTTL1;
output LVTTL2;
output LVTTL3;
output LVTTL4;
output LVTTL5;
output LVTTL6;
output LVTTL7;
output LVTTL8;
output LVTTL9;
output LVTTL10;
output LVTTL11;
output PUFABn;
output VCC15GOOD;
output VCC33GOOD;
input FCLK;
input MACCLKCCC;
input RCOSC;
input MACCLK;
input PLLLOCK;
input MSSRESETn;
input [31:0] GPI;
output [31:0] GPO;
output [31:0] GPOE;
output SPI0DO;
output SPI0DOE;
input SPI0DI;
input SPI0CLKI;
output SPI0CLKO;
output SPI0MODE;
input SPI0SSI;
output [7:0] SPI0SSO;
output UART0TXD;
input UART0RXD;
input I2C0SDAI;
output I2C0SDAO;
input I2C0SCLI;
output I2C0SCLO;
output SPI1DO;
output SPI1DOE;
input SPI1DI;
input SPI1CLKI;
output SPI1CLKO;
output SPI1MODE;
input SPI1SSI;
output [7:0] SPI1SSO;
output UART1TXD;
input UART1RXD;
input I2C1SDAI;
output I2C1SDAO;
input I2C1SCLI;
output I2C1SCLO;
output [1:0] MACTXD;
input [1:0] MACRXD;
output MACTXEN;
input MACCRSDV;
input MACRXER;
input MACMDI;
output MACMDO;
output MACMDEN;
output MACMDC;
output EMCCLK;
input EMCCLKRTN;
input [15:0] EMCRDB;
output [25:0] EMCAB;
output [15:0] EMCWDB;
output EMCRWn;
output EMCCS0n;
output EMCCS1n;
output EMCOEN0n;
output EMCOEN1n;
output [1:0] EMCBYTEN;
output EMCDBOE;
input ADC0;
input ADC1;
input ADC2;
input ADC3;
input ADC4;
input ADC5;
input ADC6;
input ADC7;
input ADC8;
input ADC9;
input ADC10;
input ADC11;
output SDD0;
output SDD1;
output SDD2;
input ABPS0;
input ABPS1;
input ABPS2;
input ABPS3;
input ABPS4;
input ABPS5;
input ABPS6;
input ABPS7;
input ABPS8;
input ABPS9;
input ABPS10;
input ABPS11;
input TM0;
input TM1;
input TM2;
input TM3;
input TM4;
input TM5;
input CM0;
input CM1;
input CM2;
input CM3;
input CM4;
input CM5;
input GNDTM0;
input GNDTM1;
input GNDTM2;
input VAREF0;
input VAREF1;
input VAREF2;
output VAREFOUT;
input GNDVAREF;
input PUn;
parameter ACT_CONFIG = 1'b0;
parameter ACT_FCLK = 0;
parameter ACT_DIE = "";
parameter ACT_PKG = "";
endmodule
|
//Legal Notice: (C)2013 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_input_efifo_module (
// inputs:
clk,
rd,
reset_n,
wr,
wr_data,
// outputs:
almost_empty,
almost_full,
empty,
full,
rd_data
)
;
output almost_empty;
output almost_full;
output empty;
output full;
output [ 40: 0] rd_data;
input clk;
input rd;
input reset_n;
input wr;
input [ 40: 0] wr_data;
wire almost_empty;
wire almost_full;
wire empty;
reg [ 1: 0] entries;
reg [ 40: 0] entry_0;
reg [ 40: 0] entry_1;
wire full;
reg rd_address;
reg [ 40: 0] rd_data;
wire [ 1: 0] rdwr;
reg wr_address;
assign rdwr = {rd, wr};
assign full = entries == 2;
assign almost_full = entries >= 1;
assign empty = entries == 0;
assign almost_empty = entries <= 1;
always @(entry_0 or entry_1 or rd_address)
begin
case (rd_address) // synthesis parallel_case full_case
1'd0: begin
rd_data = entry_0;
end // 1'd0
1'd1: begin
rd_data = entry_1;
end // 1'd1
default: begin
end // default
endcase // rd_address
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
wr_address <= 0;
rd_address <= 0;
entries <= 0;
end
else
case (rdwr) // synthesis parallel_case full_case
2'd1: begin
// Write data
if (!full)
begin
entries <= entries + 1;
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
end
end // 2'd1
2'd2: begin
// Read data
if (!empty)
begin
entries <= entries - 1;
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end
end // 2'd2
2'd3: begin
wr_address <= (wr_address == 1) ? 0 : (wr_address + 1);
rd_address <= (rd_address == 1) ? 0 : (rd_address + 1);
end // 2'd3
default: begin
end // default
endcase // rdwr
end
always @(posedge clk)
begin
//Write data
if (wr & !full)
case (wr_address) // synthesis parallel_case full_case
1'd0: begin
entry_0 <= wr_data;
end // 1'd0
1'd1: begin
entry_1 <= wr_data;
end // 1'd1
default: begin
end // default
endcase // wr_address
end
endmodule
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0 (
// inputs:
az_addr,
az_be_n,
az_cs,
az_data,
az_rd_n,
az_wr_n,
clk,
reset_n,
// outputs:
za_data,
za_valid,
za_waitrequest,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dq,
zs_dqm,
zs_ras_n,
zs_we_n
)
;
output [ 15: 0] za_data;
output za_valid;
output za_waitrequest;
output [ 11: 0] zs_addr;
output [ 1: 0] zs_ba;
output zs_cas_n;
output zs_cke;
output zs_cs_n;
inout [ 15: 0] zs_dq;
output [ 1: 0] zs_dqm;
output zs_ras_n;
output zs_we_n;
input [ 21: 0] az_addr;
input [ 1: 0] az_be_n;
input az_cs;
input [ 15: 0] az_data;
input az_rd_n;
input az_wr_n;
input clk;
input reset_n;
wire [ 23: 0] CODE;
reg ack_refresh_request;
reg [ 21: 0] active_addr;
wire [ 1: 0] active_bank;
reg active_cs_n;
reg [ 15: 0] active_data;
reg [ 1: 0] active_dqm;
reg active_rnw;
wire almost_empty;
wire almost_full;
wire bank_match;
wire [ 7: 0] cas_addr;
wire clk_en;
wire [ 3: 0] cmd_all;
wire [ 2: 0] cmd_code;
wire cs_n;
wire csn_decode;
wire csn_match;
wire [ 21: 0] f_addr;
wire [ 1: 0] f_bank;
wire f_cs_n;
wire [ 15: 0] f_data;
wire [ 1: 0] f_dqm;
wire f_empty;
reg f_pop;
wire f_rnw;
wire f_select;
wire [ 40: 0] fifo_read_data;
reg [ 11: 0] i_addr;
reg [ 3: 0] i_cmd;
reg [ 2: 0] i_count;
reg [ 2: 0] i_next;
reg [ 2: 0] i_refs;
reg [ 2: 0] i_state;
reg init_done;
reg [ 11: 0] m_addr /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 1: 0] m_bank /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 3: 0] m_cmd /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 2: 0] m_count;
reg [ 15: 0] m_data /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON ; FAST_OUTPUT_ENABLE_REGISTER=ON" */;
reg [ 1: 0] m_dqm /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON" */;
reg [ 8: 0] m_next;
reg [ 8: 0] m_state;
reg oe /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON" */;
wire pending;
wire rd_strobe;
reg [ 2: 0] rd_valid;
reg [ 12: 0] refresh_counter;
reg refresh_request;
wire rnw_match;
wire row_match;
wire [ 23: 0] txt_code;
reg za_cannotrefresh;
reg [ 15: 0] za_data /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON" */;
reg za_valid;
wire za_waitrequest;
wire [ 11: 0] zs_addr;
wire [ 1: 0] zs_ba;
wire zs_cas_n;
wire zs_cke;
wire zs_cs_n;
wire [ 15: 0] zs_dq;
wire [ 1: 0] zs_dqm;
wire zs_ras_n;
wire zs_we_n;
assign clk_en = 1;
//s1, which is an e_avalon_slave
assign {zs_cs_n, zs_ras_n, zs_cas_n, zs_we_n} = m_cmd;
assign zs_addr = m_addr;
assign zs_cke = clk_en;
assign zs_dq = oe?m_data:{16{1'bz}};
assign zs_dqm = m_dqm;
assign zs_ba = m_bank;
assign f_select = f_pop & pending;
assign f_cs_n = 1'b0;
assign cs_n = f_select ? f_cs_n : active_cs_n;
assign csn_decode = cs_n;
assign {f_rnw, f_addr, f_dqm, f_data} = fifo_read_data;
sdram_0_input_efifo_module the_sdram_0_input_efifo_module
(
.almost_empty (almost_empty),
.almost_full (almost_full),
.clk (clk),
.empty (f_empty),
.full (za_waitrequest),
.rd (f_select),
.rd_data (fifo_read_data),
.reset_n (reset_n),
.wr ((~az_wr_n | ~az_rd_n) & !za_waitrequest),
.wr_data ({az_wr_n, az_addr, az_wr_n ? 2'b0 : az_be_n, az_data})
);
assign f_bank = {f_addr[21],f_addr[8]};
// Refresh/init counter.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_counter <= 5000;
else if (refresh_counter == 0)
refresh_counter <= 781;
else
refresh_counter <= refresh_counter - 1'b1;
end
// Refresh request signal.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
refresh_request <= 0;
else if (1)
refresh_request <= ((refresh_counter == 0) | refresh_request) & ~ack_refresh_request & init_done;
end
// Generate an Interrupt if two ref_reqs occur before one ack_refresh_request
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_cannotrefresh <= 0;
else if (1)
za_cannotrefresh <= (refresh_counter == 0) & refresh_request;
end
// Initialization-done flag.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
init_done <= 0;
else if (1)
init_done <= init_done | (i_state == 3'b101);
end
// **** Init FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
i_state <= 3'b000;
i_next <= 3'b000;
i_cmd <= 4'b1111;
i_addr <= {12{1'b1}};
i_count <= {3{1'b0}};
end
else
begin
i_addr <= {12{1'b1}};
case (i_state) // synthesis parallel_case full_case
3'b000: begin
i_cmd <= 4'b1111;
i_refs <= 3'b0;
//Wait for refresh count-down after reset
if (refresh_counter == 0)
i_state <= 3'b001;
end // 3'b000
3'b001: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h2};
i_count <= 0;
i_next <= 3'b010;
end // 3'b001
3'b010: begin
i_cmd <= {{1{1'b0}},3'h1};
i_refs <= i_refs + 1'b1;
i_state <= 3'b011;
i_count <= 3;
// Count up init_refresh_commands
if (i_refs == 3'h1)
i_next <= 3'b111;
else
i_next <= 3'b010;
end // 3'b010
3'b011: begin
i_cmd <= {{1{1'b0}},3'h7};
//WAIT til safe to Proceed...
if (i_count > 1)
i_count <= i_count - 1'b1;
else
i_state <= i_next;
end // 3'b011
3'b101: begin
i_state <= 3'b101;
end // 3'b101
3'b111: begin
i_state <= 3'b011;
i_cmd <= {{1{1'b0}},3'h0};
i_addr <= {{2{1'b0}},1'b0,2'b00,3'h3,4'h0};
i_count <= 4;
i_next <= 3'b101;
end // 3'b111
default: begin
i_state <= 3'b000;
end // default
endcase // i_state
end
end
assign active_bank = {active_addr[21],active_addr[8]};
assign csn_match = active_cs_n == f_cs_n;
assign rnw_match = active_rnw == f_rnw;
assign bank_match = active_bank == f_bank;
assign row_match = {active_addr[20 : 9]} == {f_addr[20 : 9]};
assign pending = csn_match && rnw_match && bank_match && row_match && !f_empty;
assign cas_addr = f_select ? { {4{1'b0}},f_addr[7 : 0] } : { {4{1'b0}},active_addr[7 : 0] };
// **** Main FSM ****
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
begin
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= 4'b1111;
m_bank <= 2'b00;
m_addr <= 12'b000000000000;
m_data <= 16'b0000000000000000;
m_dqm <= 2'b00;
m_count <= 3'b000;
ack_refresh_request <= 1'b0;
f_pop <= 1'b0;
oe <= 1'b0;
end
else
begin
f_pop <= 1'b0;
oe <= 1'b0;
case (m_state) // synthesis parallel_case full_case
9'b000000001: begin
//Wait for init-fsm to be done...
if (init_done)
begin
//Hold bus if another cycle ended to arf.
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= 4'b1111;
ack_refresh_request <= 1'b0;
//Wait for a read/write request.
if (refresh_request)
begin
m_state <= 9'b001000000;
m_next <= 9'b010000000;
m_count <= 0;
active_cs_n <= 1'b1;
end
else if (!f_empty)
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
m_state <= 9'b000000010;
end
end
else
begin
m_addr <= i_addr;
m_state <= 9'b000000001;
m_next <= 9'b000000001;
m_cmd <= i_cmd;
end
end // 9'b000000001
9'b000000010: begin
m_state <= 9'b000000100;
m_cmd <= {csn_decode,3'h3};
m_bank <= active_bank;
m_addr <= active_addr[20 : 9];
m_data <= active_data;
m_dqm <= active_dqm;
m_count <= 1;
m_next <= active_rnw ? 9'b000001000 : 9'b000010000;
end // 9'b000000010
9'b000000100: begin
// precharge all if arf, else precharge csn_decode
if (m_next == 9'b010000000)
m_cmd <= {{1{1'b0}},3'h7};
else
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
m_state <= m_next;
end // 9'b000000100
9'b000001000: begin
m_cmd <= {csn_decode,3'h5};
m_bank <= f_select ? f_bank : active_bank;
m_dqm <= f_select ? f_dqm : active_dqm;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 2;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end RD spin cycle if fifo mt
if (~pending & f_pop)
m_cmd <= {csn_decode,3'h7};
m_state <= 9'b100000000;
end
end // 9'b000001000
9'b000010000: begin
m_cmd <= {csn_decode,3'h4};
oe <= 1'b1;
m_data <= f_select ? f_data : active_data;
m_dqm <= f_select ? f_dqm : active_dqm;
m_bank <= f_select ? f_bank : active_bank;
m_addr <= cas_addr;
//Do we have a transaction pending?
if (pending)
begin
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else
begin
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
end
else
begin
//correctly end WR spin cycle if fifo empty
if (~pending & f_pop)
begin
m_cmd <= {csn_decode,3'h7};
oe <= 1'b0;
end
m_state <= 9'b100000000;
end
end // 9'b000010000
9'b000100000: begin
m_cmd <= {csn_decode,3'h7};
//Count down til safe to Proceed...
if (m_count > 1)
m_count <= m_count - 1'b1;
else
begin
m_state <= 9'b001000000;
m_count <= 0;
end
end // 9'b000100000
9'b001000000: begin
m_state <= 9'b000000100;
m_addr <= {12{1'b1}};
// precharge all if arf, else precharge csn_decode
if (refresh_request)
m_cmd <= {{1{1'b0}},3'h2};
else
m_cmd <= {csn_decode,3'h2};
end // 9'b001000000
9'b010000000: begin
ack_refresh_request <= 1'b1;
m_state <= 9'b000000100;
m_cmd <= {{1{1'b0}},3'h1};
m_count <= 3;
m_next <= 9'b000000001;
end // 9'b010000000
9'b100000000: begin
m_cmd <= {csn_decode,3'h7};
//if we need to ARF, bail, else spin
if (refresh_request)
begin
m_state <= 9'b000000100;
m_next <= 9'b000000001;
m_count <= 1;
end
else //wait for fifo to have contents
if (!f_empty)
//Are we 'pending' yet?
if (csn_match && rnw_match && bank_match && row_match)
begin
m_state <= f_rnw ? 9'b000001000 : 9'b000010000;
f_pop <= 1'b1;
active_cs_n <= f_cs_n;
active_rnw <= f_rnw;
active_addr <= f_addr;
active_data <= f_data;
active_dqm <= f_dqm;
end
else
begin
m_state <= 9'b000100000;
m_next <= 9'b000000001;
m_count <= 1;
end
end // 9'b100000000
// synthesis translate_off
default: begin
m_state <= m_state;
m_cmd <= 4'b1111;
f_pop <= 1'b0;
oe <= 1'b0;
end // default
// synthesis translate_on
endcase // m_state
end
end
assign rd_strobe = m_cmd[2 : 0] == 3'h5;
//Track RD Req's based on cas_latency w/shift reg
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
rd_valid <= {3{1'b0}};
else
rd_valid <= (rd_valid << 1) | { {2{1'b0}}, rd_strobe };
end
// Register dq data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_data <= 0;
else
za_data <= zs_dq;
end
// Delay za_valid to match registered data.
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
za_valid <= 0;
else if (1)
za_valid <= rd_valid[2];
end
assign cmd_code = m_cmd[2 : 0];
assign cmd_all = m_cmd;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
initial
begin
$write("\n");
$write("This reference design requires a vendor simulation model.\n");
$write("To simulate accesses to SDRAM, you must:\n");
$write(" - Download the vendor model\n");
$write(" - Install the model in the system_sim directory\n");
$write(" - `include the vendor model in the the top-level system file,\n");
$write(" - Instantiate sdram simulation models and wire them to testbench signals\n");
$write(" - Be aware that you may have to disable some timing checks in the vendor model\n");
$write(" (because this simulation is zero-delay based)\n");
$write("\n");
end
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
assign CODE = &(cmd_all|4'h7) ? 24'h494e48 : txt_code;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
//
// Generated by Bluespec Compiler, version 2018.10.beta1 (build e1df8052c, 2018-10-17)
//
//
//
//
// Ports:
// Name I/O size props
// CLK I 1 clock
// RST_N I 1 reset
//
// No combinational paths from inputs to outputs
//
//
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
`ifdef BSV_POSITIVE_RESET
`define BSV_RESET_VALUE 1'b1
`define BSV_RESET_EDGE posedge
`else
`define BSV_RESET_VALUE 1'b0
`define BSV_RESET_EDGE negedge
`endif
module mkTop_HW_Side(CLK,
RST_N);
input CLK;
input RST_N;
// register rg_banner_printed
reg rg_banner_printed;
wire rg_banner_printed$D_IN, rg_banner_printed$EN;
// ports of submodule mem_model
wire [352 : 0] mem_model$mem_server_request_put;
wire [255 : 0] mem_model$mem_server_response_get;
wire mem_model$EN_mem_server_request_put,
mem_model$EN_mem_server_response_get,
mem_model$RDY_mem_server_request_put,
mem_model$RDY_mem_server_response_get;
// ports of submodule soc_top
wire [352 : 0] soc_top$to_raw_mem_request_get;
wire [255 : 0] soc_top$to_raw_mem_response_put;
wire [63 : 0] soc_top$set_verbosity_logdelay,
soc_top$set_watch_tohost_tohost_addr;
wire [7 : 0] soc_top$get_to_console_get,
soc_top$put_from_console_put,
soc_top$status;
wire [3 : 0] soc_top$set_verbosity_verbosity;
wire soc_top$EN_get_to_console_get,
soc_top$EN_put_from_console_put,
soc_top$EN_set_verbosity,
soc_top$EN_set_watch_tohost,
soc_top$EN_to_raw_mem_request_get,
soc_top$EN_to_raw_mem_response_put,
soc_top$RDY_get_to_console_get,
soc_top$RDY_to_raw_mem_request_get,
soc_top$RDY_to_raw_mem_response_put,
soc_top$set_watch_tohost_watch_tohost;
// rule scheduling signals
wire CAN_FIRE_RL_memCnx_ClientServerRequest,
CAN_FIRE_RL_memCnx_ClientServerResponse,
CAN_FIRE_RL_rl_relay_console_out,
CAN_FIRE_RL_rl_step0,
CAN_FIRE_RL_rl_terminate,
WILL_FIRE_RL_memCnx_ClientServerRequest,
WILL_FIRE_RL_memCnx_ClientServerResponse,
WILL_FIRE_RL_rl_relay_console_out,
WILL_FIRE_RL_rl_step0,
WILL_FIRE_RL_rl_terminate;
// declarations used by system tasks
// synopsys translate_off
reg TASK_testplusargs___d12;
reg TASK_testplusargs___d11;
reg [31 : 0] v__h536;
reg [31 : 0] v__h530;
// synopsys translate_on
// submodule mem_model
mkMem_Model mem_model(.CLK(CLK),
.RST_N(RST_N),
.mem_server_request_put(mem_model$mem_server_request_put),
.EN_mem_server_request_put(mem_model$EN_mem_server_request_put),
.EN_mem_server_response_get(mem_model$EN_mem_server_response_get),
.RDY_mem_server_request_put(mem_model$RDY_mem_server_request_put),
.mem_server_response_get(mem_model$mem_server_response_get),
.RDY_mem_server_response_get(mem_model$RDY_mem_server_response_get));
// submodule soc_top
mkSoC_Top soc_top(.CLK(CLK),
.RST_N(RST_N),
.put_from_console_put(soc_top$put_from_console_put),
.set_verbosity_logdelay(soc_top$set_verbosity_logdelay),
.set_verbosity_verbosity(soc_top$set_verbosity_verbosity),
.set_watch_tohost_tohost_addr(soc_top$set_watch_tohost_tohost_addr),
.set_watch_tohost_watch_tohost(soc_top$set_watch_tohost_watch_tohost),
.to_raw_mem_response_put(soc_top$to_raw_mem_response_put),
.EN_set_verbosity(soc_top$EN_set_verbosity),
.EN_to_raw_mem_request_get(soc_top$EN_to_raw_mem_request_get),
.EN_to_raw_mem_response_put(soc_top$EN_to_raw_mem_response_put),
.EN_get_to_console_get(soc_top$EN_get_to_console_get),
.EN_put_from_console_put(soc_top$EN_put_from_console_put),
.EN_set_watch_tohost(soc_top$EN_set_watch_tohost),
.RDY_set_verbosity(),
.to_raw_mem_request_get(soc_top$to_raw_mem_request_get),
.RDY_to_raw_mem_request_get(soc_top$RDY_to_raw_mem_request_get),
.RDY_to_raw_mem_response_put(soc_top$RDY_to_raw_mem_response_put),
.get_to_console_get(soc_top$get_to_console_get),
.RDY_get_to_console_get(soc_top$RDY_get_to_console_get),
.RDY_put_from_console_put(),
.status(soc_top$status),
.RDY_set_watch_tohost());
// rule RL_rl_step0
assign CAN_FIRE_RL_rl_step0 = !rg_banner_printed ;
assign WILL_FIRE_RL_rl_step0 = CAN_FIRE_RL_rl_step0 ;
// rule RL_rl_terminate
assign CAN_FIRE_RL_rl_terminate = soc_top$status != 8'd0 ;
assign WILL_FIRE_RL_rl_terminate = CAN_FIRE_RL_rl_terminate ;
// rule RL_rl_relay_console_out
assign CAN_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
assign WILL_FIRE_RL_rl_relay_console_out = soc_top$RDY_get_to_console_get ;
// rule RL_memCnx_ClientServerRequest
assign CAN_FIRE_RL_memCnx_ClientServerRequest =
soc_top$RDY_to_raw_mem_request_get &&
mem_model$RDY_mem_server_request_put ;
assign WILL_FIRE_RL_memCnx_ClientServerRequest =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
// rule RL_memCnx_ClientServerResponse
assign CAN_FIRE_RL_memCnx_ClientServerResponse =
soc_top$RDY_to_raw_mem_response_put &&
mem_model$RDY_mem_server_response_get ;
assign WILL_FIRE_RL_memCnx_ClientServerResponse =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// register rg_banner_printed
assign rg_banner_printed$D_IN = 1'd1 ;
assign rg_banner_printed$EN = CAN_FIRE_RL_rl_step0 ;
// submodule mem_model
assign mem_model$mem_server_request_put = soc_top$to_raw_mem_request_get ;
assign mem_model$EN_mem_server_request_put =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign mem_model$EN_mem_server_response_get =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
// submodule soc_top
assign soc_top$put_from_console_put = 8'h0 ;
assign soc_top$set_verbosity_logdelay = 64'd0 ;
assign soc_top$set_verbosity_verbosity =
TASK_testplusargs___d11 ?
4'd2 :
(TASK_testplusargs___d12 ? 4'd1 : 4'd0) ;
assign soc_top$set_watch_tohost_tohost_addr = 64'h0 ;
assign soc_top$set_watch_tohost_watch_tohost = 1'b0 ;
assign soc_top$to_raw_mem_response_put = mem_model$mem_server_response_get ;
assign soc_top$EN_set_verbosity = CAN_FIRE_RL_rl_step0 ;
assign soc_top$EN_to_raw_mem_request_get =
CAN_FIRE_RL_memCnx_ClientServerRequest ;
assign soc_top$EN_to_raw_mem_response_put =
CAN_FIRE_RL_memCnx_ClientServerResponse ;
assign soc_top$EN_get_to_console_get = soc_top$RDY_get_to_console_get ;
assign soc_top$EN_put_from_console_put = 1'b0 ;
assign soc_top$EN_set_watch_tohost = 1'b0 ;
// handling of inlined registers
always@(posedge CLK)
begin
if (RST_N == `BSV_RESET_VALUE)
begin
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY 1'd0;
end
else
begin
if (rg_banner_printed$EN)
rg_banner_printed <= `BSV_ASSIGNMENT_DELAY rg_banner_printed$D_IN;
end
end
// synopsys translate_off
`ifdef BSV_NO_INITIAL_BLOCKS
`else // not BSV_NO_INITIAL_BLOCKS
initial
begin
rg_banner_printed = 1'h0;
end
`endif // BSV_NO_INITIAL_BLOCKS
// synopsys translate_on
// handling of system tasks
// synopsys translate_off
always@(negedge CLK)
begin
#0;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Bluespec RISC-V standalone system simulation v1.2");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("Copyright (c) 2017-2019 Bluespec, Inc. All Rights Reserved.");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
$display("================================================================");
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d12 = $test$plusargs("v1");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_step0)
begin
TASK_testplusargs___d11 = $test$plusargs("v2");
#0;
end
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
begin
v__h536 = $stime;
#0;
end
v__h530 = v__h536 / 32'd10;
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate)
$display("%0d: %m:.rl_terminate: soc_top status is 0x%0h (= 0d%0d)",
v__h530,
soc_top$status,
soc_top$status);
if (RST_N != `BSV_RESET_VALUE)
if (WILL_FIRE_RL_rl_terminate) $finish(32'd0);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get)
$write("%c", soc_top$get_to_console_get);
if (RST_N != `BSV_RESET_VALUE)
if (soc_top$RDY_get_to_console_get) $fflush(32'h80000001);
end
// synopsys translate_on
endmodule // mkTop_HW_Side
|
//#############################################################################
//# Function: Low power clock gate circuit #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_clockgate (
input clk, // clock input
input te, // test enable enable
input en, // enable (from positive edge FF)
output eclk // enabled clock output
);
localparam ASIC = `CFG_ASIC; // use ASIC lib
generate
if(ASIC)
begin : asic
asic_icg icg (.en(en),
.te(te),
.clk(clk),
.eclk(eclk));
end
else
begin : generic
wire en_sh;
wire en_sl;
//Stable low/valid rising edge enable
assign en_sl = en | te;
//Stable high enable signal
oh_lat0 lat0 (.out (en_sh),
.in (en_sl),
.clk (clk));
assign eclk = clk & en_sh;
end
endgenerate
endmodule // oh_clockgate
|
`define ADDER_WIDTH 015
`define DUMMY_WIDTH 128
`define 3_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.3
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1ns/1ps
module convolve_kernel_fbkb
#(parameter
ID = 1,
NUM_STAGE = 9,
din0_WIDTH = 32,
din1_WIDTH = 32,
dout_WIDTH = 32
)(
input wire clk,
input wire reset,
input wire ce,
input wire [din0_WIDTH-1:0] din0,
input wire [din1_WIDTH-1:0] din1,
output wire [dout_WIDTH-1:0] dout
);
//------------------------Local signal-------------------
wire aclk;
wire aclken;
wire a_tvalid;
wire [31:0] a_tdata;
wire b_tvalid;
wire [31:0] b_tdata;
wire r_tvalid;
wire [31:0] r_tdata;
reg [din0_WIDTH-1:0] din0_buf1;
reg [din1_WIDTH-1:0] din1_buf1;
reg ce_r;
wire [dout_WIDTH-1:0] dout_i;
reg [dout_WIDTH-1:0] dout_r;
//------------------------Instantiation------------------
convolve_kernel_ap_fadd_7_full_dsp_32 convolve_kernel_ap_fadd_7_full_dsp_32_u (
.aclk ( aclk ),
.aclken ( aclken ),
.s_axis_a_tvalid ( a_tvalid ),
.s_axis_a_tdata ( a_tdata ),
.s_axis_b_tvalid ( b_tvalid ),
.s_axis_b_tdata ( b_tdata ),
.m_axis_result_tvalid ( r_tvalid ),
.m_axis_result_tdata ( r_tdata )
);
//------------------------Body---------------------------
assign aclk = clk;
assign aclken = ce_r;
assign a_tvalid = 1'b1;
assign a_tdata = din0_buf1;
assign b_tvalid = 1'b1;
assign b_tdata = din1_buf1;
assign dout_i = r_tdata;
always @(posedge clk) begin
if (ce) begin
din0_buf1 <= din0;
din1_buf1 <= din1;
end
end
always @ (posedge clk) begin
ce_r <= ce;
end
always @ (posedge clk) begin
if (ce_r) begin
dout_r <= dout_i;
end
end
assign dout = ce_r?dout_i:dout_r;
endmodule
|
module wrapper
(
input USER_RESET,
output SPI_SCK,
output [0:0] SPI_CS_n,
inout SPI_IO1,
inout SPI_IO2,
inout SPI_IO3,
inout SPI_IO4,
input USER_CLOCK,
input GPIO_DIP1,
input GPIO_DIP2,
input GPIO_DIP3,
input GPIO_DIP4,
output [3:0] GPIO_LED,
input USB_RS232_RXD,
output USB_RS232_TXD,
inout SCL,
input SDA,
output [12:0] LPDDR_A,
output [1:0] LPDDR_BA,
inout [15:0] LPDDR_DQ,
output LPDDR_LDM,
output LPDDR_UDM,
inout LPDDR_LDQS,
inout LPDDR_UDQS,
output LPDDR_CK_N,
output LPDDR_CK_P,
output LPDDR_CKE,
output LPDDR_CAS_n,
output LPDDR_RAS_n,
output LPDDR_WE_n,
output LPDDR_RZQ,
input ETH_COL,
input ETH_CRS,
input ETH_MDC,
input ETH_MDIO,
output ETH_RESET_n,
input ETH_RX_CLK,
input [3:0] ETH_RX_D,
input ETH_RX_DV,
input ETH_RX_ER,
input ETH_TX_CLK,
output [3:0] ETH_TX_D,
output ETH_TX_EN
);
wire [7:0] led;
assign GPIO_LED = led[3:0];
system #(
.CLKSPEED(40000000),
.BAUD(115200),
.SEVEN_SEG_DUTY_CYCLE(7)
) system (
.clk(USER_CLOCK),
.sw({4'b0, GPIO_DIP4, GPIO_DIP3, GPIO_DIP2, GPIO_DIP1}),
.led(led),
.rxd(USB_RS232_RXD),
.txd(USB_RS232_TXD),
.seg(),
.an(),
.select(!USER_RESET)
);
// Sensible defaults for AVNet On-board peripherals
assign SPI_SCK = 1'b1;
assign SPI_CS_n = 1'b1;
assign SPI_IO1 = 1'bz;
assign SPI_IO2 = 1'bz;
assign SPI_IO3 = 1'bz;
assign SPI_IO4 = 1'bz;
assign SCL = 1'bz;
assign LPDDR_A = 13'b0;
assign LPDDR_BA = 1'b0;
assign LPDDR_DQ = 16'bz;
assign LPDDR_LDM = 1'b0;
assign LPDDR_UDM = 1'b0;
assign LPDDR_LDQS = 1'bz;
assign LPDDR_UDQS = 1'bz;
assign LPDDR_CKE = 1'b0;
assign LPDDR_CAS_n = 1'b1;
assign LPDDR_RAS_n = 1'b1;
assign LPDDR_WE_n = 1'b1;
assign LPDDR_RZQ = 1'bz;
assign ETH_RESET_n = 1'b1;
assign ETH_TX_D = 4'bz;
assign ETH_TX_EN = 1'b0;
OBUFDS LPDDR_CK_inst (
.O(LPDDR_CK_P), // Diff_p output (connect directly to top-level port)
.OB(LPDDR_CK_N), // Diff_n output (connect directly to top-level port)
.I(1'b0)
);
endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: afifo.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:37:18 $
// \ \ / \ Date Created: Oct 21 2008
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: A generic synchronous fifo.
//Reference:
//Revision History: 1.2 11/8/2010 Removed unused signals.
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v1_9_afifo #
(
parameter TCQ = 100,
parameter DSIZE = 32,
parameter FIFO_DEPTH = 16,
parameter ASIZE = 4,
parameter SYNC = 1 // only has always '1' logic.
)
(
input wr_clk,
input rst,
input wr_en,
input [DSIZE-1:0] wr_data,
input rd_en,
input rd_clk,
output [DSIZE-1:0] rd_data,
output reg full,
output reg empty,
output reg almost_full
);
// memory array
reg [DSIZE-1:0] mem [0:FIFO_DEPTH-1];
//Read Capture Logic
// if Sync = 1, then no need to remove metastability logic because wrclk = rdclk
reg [ASIZE:0] rd_capture_ptr;
reg [ASIZE:0] pre_rd_capture_gray_ptr;
reg [ASIZE:0] rd_capture_gray_ptr;
reg [ASIZE:0] wr_capture_ptr;
reg [ASIZE:0] pre_wr_capture_gray_ptr;
reg [ASIZE:0] wr_capture_gray_ptr;
wire [ASIZE:0] buf_avail;
wire [ASIZE:0] buf_filled;
wire [ASIZE-1:0] wr_addr, rd_addr;
wire COutb,COutd;
reg COuta,COutc;
reg [ASIZE:0] wr_ptr, rd_ptr,rd_ptr_cp;
integer i,j,k;
always @ (rd_ptr)
rd_capture_ptr = rd_ptr;
//capture the wr_gray_pointers to rd_clk domains and convert the gray pointers to binary pointers
// before do comparison.
always @ (wr_ptr)
wr_capture_ptr = wr_ptr;
// dualport ram
// Memory (RAM) that holds the contents of the FIFO
assign wr_addr = wr_ptr[ASIZE-1:0];
assign rd_data = mem[rd_addr];
always @(posedge wr_clk)
begin
if (wr_en && !full)
mem[wr_addr] <= #TCQ wr_data;
end
// Read Side Logic
assign rd_addr = rd_ptr_cp[ASIZE-1:0];
assign rd_strobe = rd_en && !empty;
integer n;
// change the binary pointer to gray pointer
always @(posedge rd_clk)
begin
if (rst)
begin
rd_ptr <= #TCQ 'b0;
rd_ptr_cp <= #TCQ 'b0;
end
else begin
if (rd_strobe) begin
{COuta,rd_ptr} <= #TCQ rd_ptr + 1'b1;
rd_ptr_cp <= #TCQ rd_ptr_cp + 1'b1;
end
// change the binary pointer to gray pointer
end
end
//generate empty signal
assign {COutb,buf_filled} = wr_capture_ptr - rd_ptr;
always @ (posedge rd_clk )
begin
if (rst)
empty <= #TCQ 1'b1;
else if ((buf_filled == 0) || (buf_filled == 1 && rd_strobe))
empty <= #TCQ 1'b1;
else
empty <= #TCQ 1'b0;
end
// write side logic;
reg [ASIZE:0] wbin;
wire [ASIZE:0] wgraynext, wbinnext;
always @(posedge rd_clk)
begin
if (rst)
begin
wr_ptr <= #TCQ 'b0;
end
else begin
if (wr_en)
{COutc, wr_ptr} <= #TCQ wr_ptr + 1'b1;
// change the binary pointer to gray pointer
end
end
// calculate how many buf still available
//assign {COutd,buf_avail }= (rd_capture_ptr + 5'd16) - wr_ptr;
assign {COutd,buf_avail }= rd_capture_ptr - wr_ptr + + 5'd16;
always @ (posedge wr_clk )
begin
if (rst)
full <= #TCQ 1'b0;
else if ((buf_avail == 0) || (buf_avail == 1 && wr_en))
full <= #TCQ 1'b1;
else
full <= #TCQ 1'b0;
end
always @ (posedge wr_clk )
begin
if (rst)
almost_full <= #TCQ 1'b0;
else if ((buf_avail == FIFO_DEPTH - 2 ) || ((buf_avail == FIFO_DEPTH -3) && wr_en))
almost_full <= #TCQ 1'b1;
else
almost_full <= #TCQ 1'b0;
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_tans_if # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
//PCIe user clock
input pcie_user_clk,
input pcie_user_rst_n,
//PCIe rx interface
output mreq_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] mreq_fifo_wr_data,
output [7:0] cpld0_fifo_tag,
output cpld0_fifo_tag_last,
output cpld0_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld0_fifo_wr_data,
output [7:0] cpld1_fifo_tag,
output cpld1_fifo_tag_last,
output cpld1_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld1_fifo_wr_data,
output [7:0] cpld2_fifo_tag,
output cpld2_fifo_tag_last,
output cpld2_fifo_wr_en,
output [C_PCIE_DATA_WIDTH-1:0] cpld2_fifo_wr_data,
//PCIe tx interface
input tx_cpld_req,
input [7:0] tx_cpld_tag,
input [15:0] tx_cpld_req_id,
input [11:2] tx_cpld_len,
input [11:0] tx_cpld_bc,
input [6:0] tx_cpld_laddr,
input [63:0] tx_cpld_data,
output tx_cpld_req_ack,
input tx_mrd0_req,
input [7:0] tx_mrd0_tag,
input [11:2] tx_mrd0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd0_addr,
output tx_mrd0_req_ack,
input tx_mrd1_req,
input [7:0] tx_mrd1_tag,
input [11:2] tx_mrd1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd1_addr,
output tx_mrd1_req_ack,
input tx_mrd2_req,
input [7:0] tx_mrd2_tag,
input [11:2] tx_mrd2_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mrd2_addr,
output tx_mrd2_req_ack,
input tx_mwr0_req,
input [7:0] tx_mwr0_tag,
input [11:2] tx_mwr0_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr0_addr,
output tx_mwr0_req_ack,
output tx_mwr0_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr0_rd_data,
output tx_mwr0_data_last,
input tx_mwr1_req,
input [7:0] tx_mwr1_tag,
input [11:2] tx_mwr1_len,
input [C_PCIE_ADDR_WIDTH-1:2] tx_mwr1_addr,
output tx_mwr1_req_ack,
output tx_mwr1_rd_en,
input [C_PCIE_DATA_WIDTH-1:0] tx_mwr1_rd_data,
output tx_mwr1_data_last,
output pcie_mreq_err,
output pcie_cpld_err,
output pcie_cpld_len_err,
//PCIe Integrated Block Interface
input [5:0] tx_buf_av,
input tx_err_drop,
input tx_cfg_req,
input s_axis_tx_tready,
output [C_PCIE_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [(C_PCIE_DATA_WIDTH/8)-1:0] s_axis_tx_tkeep,
output [3:0] s_axis_tx_tuser,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_cfg_gnt,
input [C_PCIE_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [(C_PCIE_DATA_WIDTH/8)-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input [11:0] fc_cpld,
input [7:0] fc_cplh,
input [11:0] fc_npd,
input [7:0] fc_nph,
input [11:0] fc_pd,
input [7:0] fc_ph,
output [2:0] fc_sel,
input [7:0] cfg_bus_number,
input [4:0] cfg_device_number,
input [2:0] cfg_function_number
);
wire w_tx_cpld_gnt;
wire w_tx_mrd_gnt;
wire w_tx_mwr_gnt;
reg [15:0] r_pcie_dev_id;
always @(posedge pcie_user_clk) begin
r_pcie_dev_id <= {cfg_bus_number, cfg_device_number, cfg_function_number};
end
pcie_fc_cntl
pcie_fc_cntl_inst0
(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.fc_cpld (fc_cpld),
.fc_cplh (fc_cplh),
.fc_npd (fc_npd),
.fc_nph (fc_nph),
.fc_pd (fc_pd),
.fc_ph (fc_ph),
.fc_sel (fc_sel),
.tx_buf_av (tx_buf_av),
.tx_cfg_req (tx_cfg_req),
.tx_cfg_gnt (tx_cfg_gnt),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt)
);
pcie_rx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_rx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
//pcie rx signal
.s_axis_rx_tdata (m_axis_rx_tdata),
.s_axis_rx_tkeep (m_axis_rx_tkeep),
.s_axis_rx_tlast (m_axis_rx_tlast),
.s_axis_rx_tvalid (m_axis_rx_tvalid),
.s_axis_rx_tready (m_axis_rx_tready),
.s_axis_rx_tuser (m_axis_rx_tuser),
.pcie_mreq_err (pcie_mreq_err),
.pcie_cpld_err (pcie_cpld_err),
.pcie_cpld_len_err (pcie_cpld_len_err),
.mreq_fifo_wr_en (mreq_fifo_wr_en),
.mreq_fifo_wr_data (mreq_fifo_wr_data),
.cpld0_fifo_tag (cpld0_fifo_tag),
.cpld0_fifo_tag_last (cpld0_fifo_tag_last),
.cpld0_fifo_wr_en (cpld0_fifo_wr_en),
.cpld0_fifo_wr_data (cpld0_fifo_wr_data),
.cpld1_fifo_tag (cpld1_fifo_tag),
.cpld1_fifo_tag_last (cpld1_fifo_tag_last),
.cpld1_fifo_wr_en (cpld1_fifo_wr_en),
.cpld1_fifo_wr_data (cpld1_fifo_wr_data),
.cpld2_fifo_tag (cpld2_fifo_tag),
.cpld2_fifo_tag_last (cpld2_fifo_tag_last),
.cpld2_fifo_wr_en (cpld2_fifo_wr_en),
.cpld2_fifo_wr_data (cpld2_fifo_wr_data)
);
pcie_tx # (
.C_PCIE_DATA_WIDTH (C_PCIE_DATA_WIDTH)
)
pcie_tx_inst0(
.pcie_user_clk (pcie_user_clk),
.pcie_user_rst_n (pcie_user_rst_n),
.pcie_dev_id (r_pcie_dev_id),
.tx_err_drop (tx_err_drop),
.tx_cpld_gnt (w_tx_cpld_gnt),
.tx_mrd_gnt (w_tx_mrd_gnt),
.tx_mwr_gnt (w_tx_mwr_gnt),
//pcie tx signal
.m_axis_tx_tready (s_axis_tx_tready),
.m_axis_tx_tdata (s_axis_tx_tdata),
.m_axis_tx_tkeep (s_axis_tx_tkeep),
.m_axis_tx_tuser (s_axis_tx_tuser),
.m_axis_tx_tlast (s_axis_tx_tlast),
.m_axis_tx_tvalid (s_axis_tx_tvalid),
.tx_cpld_req (tx_cpld_req),
.tx_cpld_tag (tx_cpld_tag),
.tx_cpld_req_id (tx_cpld_req_id),
.tx_cpld_len (tx_cpld_len),
.tx_cpld_bc (tx_cpld_bc),
.tx_cpld_laddr (tx_cpld_laddr),
.tx_cpld_data (tx_cpld_data),
.tx_cpld_req_ack (tx_cpld_req_ack),
.tx_mrd0_req (tx_mrd0_req),
.tx_mrd0_tag (tx_mrd0_tag),
.tx_mrd0_len (tx_mrd0_len),
.tx_mrd0_addr (tx_mrd0_addr),
.tx_mrd0_req_ack (tx_mrd0_req_ack),
.tx_mrd1_req (tx_mrd1_req),
.tx_mrd1_tag (tx_mrd1_tag),
.tx_mrd1_len (tx_mrd1_len),
.tx_mrd1_addr (tx_mrd1_addr),
.tx_mrd1_req_ack (tx_mrd1_req_ack),
.tx_mrd2_req (tx_mrd2_req),
.tx_mrd2_tag (tx_mrd2_tag),
.tx_mrd2_len (tx_mrd2_len),
.tx_mrd2_addr (tx_mrd2_addr),
.tx_mrd2_req_ack (tx_mrd2_req_ack),
.tx_mwr0_req (tx_mwr0_req),
.tx_mwr0_tag (tx_mwr0_tag),
.tx_mwr0_len (tx_mwr0_len),
.tx_mwr0_addr (tx_mwr0_addr),
.tx_mwr0_req_ack (tx_mwr0_req_ack),
.tx_mwr0_rd_en (tx_mwr0_rd_en),
.tx_mwr0_rd_data (tx_mwr0_rd_data),
.tx_mwr0_data_last (tx_mwr0_data_last),
.tx_mwr1_req (tx_mwr1_req),
.tx_mwr1_tag (tx_mwr1_tag),
.tx_mwr1_len (tx_mwr1_len),
.tx_mwr1_addr (tx_mwr1_addr),
.tx_mwr1_req_ack (tx_mwr1_req_ack),
.tx_mwr1_rd_en (tx_mwr1_rd_en),
.tx_mwr1_rd_data (tx_mwr1_rd_data),
.tx_mwr1_data_last (tx_mwr1_data_last)
);
endmodule
|
`timescale 1ns / 1ps
`include "Defintions.v"
module MiniAlu
(
input wire Clock,
input wire Reset,
output wire [7:0] oLed
);
wire [15:0] wIP,wIP_temp;
reg rWriteEnable,rBranchTaken;
wire [27:0] wInstruction;
wire [3:0] wOperation;
reg [15:0] rResult;
wire [7:0] wSourceAddr0,wSourceAddr1,wDestination;
wire [15:0] wSourceData0,wSourceData1,wIPInitialValue,wImmediateValue;
//////////////////////////
// Señales del pipeline //
wire [7:0] wDestinationPrev;
wire [15:0] wSourceData0_RAM,wSourceData1_RAM,wResultPrev;
wire wHazard0, wHazard1, wWriteEnablePrev, wIsImmediate;
///////////////////////////////
// Señales de multiplicacion //
wire signed [15:0] wSignedData1, wSignedData0;
reg signed [31:0] rResultMult;
wire [31:0] wMultResult0;
assign wSignedData0 = wSourceData0;
assign wSignedData1 = wSourceData1;
///////////////////////////////
ROM InstructionRom
(
.iAddress( wIP ),
.oInstruction( wInstruction )
);
RAM_DUAL_READ_PORT DataRam
(
.Clock( Clock ),
.iWriteEnable( rWriteEnable ),
.iReadAddress0( wInstruction[7:0] ),
.iReadAddress1( wInstruction[15:8] ),
.iWriteAddress( wDestination ),
.iDataIn( rResult ),
.oDataOut0( wSourceData0 ),
.oDataOut1( wSourceData1 )
);
assign wIPInitialValue = (Reset) ? 8'b0 : wDestination;
UPCOUNTER_POSEDGE IP
(
.Clock( Clock ),
.Reset( Reset | rBranchTaken ),
.Initial( wIPInitialValue + 16'd1 ),
.Enable( 1'b1 ),
.Q( wIP_temp )
);
assign wIP = (rBranchTaken) ? wIPInitialValue : wIP_temp;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 4 ) FFD1
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[27:24]),
.Q(wOperation)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD2
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[7:0]),
.Q(wSourceAddr0)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD3
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[15:8]),
.Q(wSourceAddr1)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD4
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wInstruction[23:16]),
.Q(wDestination)
);
reg rFFLedEN;
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FF_LEDS
(
.Clock(Clock),
.Reset(Reset),
.Enable( rFFLedEN ),
.D( wSourceData1[7:0] ),
.Q( oLed )
);
assign wImmediateValue = {wSourceAddr1,wSourceAddr0};
/////////////////////////////////
// Data Hazards en el pipeline //
FFD_POSEDGE_SYNCRONOUS_RESET # ( 8 ) FFD41
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D(wDestination),
.Q(wDestinationPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 16 ) FFDRES
(
.Clock(Clock),
.Reset(Reset),
.Enable(rWriteEnable),
.D(rResult),
.Q(wResultPrev)
);
FFD_POSEDGE_SYNCRONOUS_RESET # ( 1 ) FFDWRITE
(
.Clock(Clock),
.Reset(Reset),
.Enable(1'b1),
.D( {rWriteEnable} ),
.Q( {wWriteEnablePrev} )
);
assign wIsImmediate = wOperation[3] && wOperation[2];
assign wHazard0 = ((wDestinationPrev == wSourceAddr0) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wHazard1 = ((wDestinationPrev == wSourceAddr1) && wWriteEnablePrev && ~wIsImmediate ) ? 1'b1 : 1'b0;
assign wSourceData0 = (wHazard0) ? wResultPrev : wSourceData0_RAM;
assign wSourceData1 = (wHazard1) ? wResultPrev : wSourceData1_RAM;
// //
/////////////////////////////////
//////////////////////////////////
// MUL //
Mult16x16 MUL_LUT
(
.A(wSourceData0),
.B(wSourceData1),
.Result(wMultResult0)
);
// //
//////////////////////////////////
always @ ( * )
begin
case (wOperation)
//-------------------------------------
`NOP:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
end
//-------------------------------------
`ADD:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 + wSourceData0;
end
//-------------------------------------
`SUB:
begin
rFFLedEN <= 1'b0;
rBranchTaken <= 1'b0;
rWriteEnable <= 1'b1;
rResult <= wSourceData1 - wSourceData0;
end
//-------------------------------------
`STO:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b1;
rBranchTaken <= 1'b0;
rResult <= wImmediateValue;
end
//-------------------------------------
`BLE:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
if (wSourceData1 <= wSourceData0 )
rBranchTaken <= 1'b1;
else
rBranchTaken <= 1'b0;
end
//-------------------------------------
`JMP:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b1;
end
//-------------------------------------
`LED:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
`SMUL:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rResultMult <= wSignedData1*wSignedData0;
end
//-------------------------------------
`IMUL2:
begin
rFFLedEN <= 1'b0;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
rResultMult <= wMultResult0;
end
//-------------------------------------
default:
begin
rFFLedEN <= 1'b1;
rWriteEnable <= 1'b0;
rResult <= 0;
rBranchTaken <= 1'b0;
end
//-------------------------------------
endcase
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(** * An light axiomatization of integers (used in MSetAVL). *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when mesuring the height of an AVL tree).
*)
Require Import BinInt.
Delimit Scope Int_scope with I.
Local Open Scope Int_scope.
(** * A specification of integers *)
Module Type Int.
Parameter t : Set.
Bind Scope Int_scope with t.
Parameter i2z : t -> Z.
Parameter _0 : t.
Parameter _1 : t.
Parameter _2 : t.
Parameter _3 : t.
Parameter add : t -> t -> t.
Parameter opp : t -> t.
Parameter sub : t -> t -> t.
Parameter mul : t -> t -> t.
Parameter max : t -> t -> t.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := add : Int_scope.
Infix "-" := sub : Int_scope.
Infix "*" := mul : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (i2z x <= i2z y)%Z : Int_scope.
Notation "x < y" := (i2z x < i2z y)%Z : Int_scope.
Notation "x >= y" := (i2z x >= i2z y)%Z : Int_scope.
Notation "x > y" := (i2z x > i2z y)%Z : Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Informative comparisons. *)
Axiom eqb : t -> t -> bool.
Axiom ltb : t -> t -> bool.
Axiom leb : t -> t -> bool.
Infix "=?" := eqb.
Infix "<?" := ltb.
Infix "<=?" := leb.
(** For compatibility, some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y : t, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : t, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : t, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic
is easier. *)
Axiom i2z_eq : forall n p : t, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Axiom i2z_0 : i2z _0 = 0%Z.
Axiom i2z_1 : i2z _1 = 1%Z.
Axiom i2z_2 : i2z _2 = 2%Z.
Axiom i2z_3 : i2z _3 = 3%Z.
Axiom i2z_add : forall n p, i2z (n + p) = (i2z n + i2z p)%Z.
Axiom i2z_opp : forall n, i2z (-n) = (-i2z n)%Z.
Axiom i2z_sub : forall n p, i2z (n - p) = (i2z n - i2z p)%Z.
Axiom i2z_mul : forall n p, i2z (n * p) = (i2z n * i2z p)%Z.
Axiom i2z_max : forall n p, i2z (max n p) = Z.max (i2z n) (i2z p).
Axiom i2z_eqb : forall n p, eqb n p = Z.eqb (i2z n) (i2z p).
Axiom i2z_ltb : forall n p, ltb n p = Z.ltb (i2z n) (i2z p).
Axiom i2z_leb : forall n p, leb n p = Z.leb (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (Import I:Int).
Local Notation int := I.t.
Lemma eqb_eq n p : (n =? p) = true <-> n == p.
Proof.
now rewrite i2z_eqb, Z.eqb_eq.
Qed.
Lemma eqb_neq n p : (n =? p) = false <-> ~(n == p).
Proof.
rewrite <- eqb_eq. destruct (n =? p); intuition.
Qed.
Lemma ltb_lt n p : (n <? p) = true <-> n < p.
Proof.
now rewrite i2z_ltb, Z.ltb_lt.
Qed.
Lemma ltb_nlt n p : (n <? p) = false <-> ~(n < p).
Proof.
rewrite <- ltb_lt. destruct (n <? p); intuition.
Qed.
Lemma leb_le n p : (n <=? p) = true <-> n <= p.
Proof.
now rewrite i2z_leb, Z.leb_le.
Qed.
Lemma leb_nle n p : (n <=? p) = false <-> ~(n <= p).
Proof.
rewrite <- leb_le. destruct (n <=? p); intuition.
Qed.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_add i2z_opp i2z_sub i2z_mul i2z_max
i2z_eqb i2z_ltb i2z_leb : i2z.
Ltac i2z := match goal with
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- ?a = ?b =>
apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- ?a = ?b => apply (i2z_eq a b); i2z_gen
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : eq (A:=Z) ?a ?b |- _ => revert H; i2z_gen
| H : Z.lt ?a ?b |- _ => revert H; i2z_gen
| H : Z.le ?a ?b |- _ => revert H; i2z_gen
| H : Z.gt ?a ?b |- _ => revert H; i2z_gen
| H : Z.ge ?a ?b |- _ => revert H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => revert H; i2z_gen
end
| H : _ <-> _ |- _ => revert H; i2z_gen
| H : _ /\ _ |- _ => revert H; i2z_gen
| H : _ \/ _ |- _ => revert H; i2z_gen
| H : ~ _ |- _ => revert H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIadd : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIsub : ExprI -> ExprI -> ExprI
| EImul : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZadd : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZsub : ExprZ -> ExprZ -> ExprZ
| EZmul : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:trm with
| 0 => constr:EI0
| 1 => constr:EI1
| 2 => constr:EI2
| 3 => constr:EI3
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIadd ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIsub ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImul ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:trm with
| (?x + ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZadd ex ey)
| (?x - ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZsub ex ey)
| (?x * ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmul ex ey)
| (Z.max ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (- ?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:trm with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x < ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x <= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x > ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x >= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIadd e1 e2 => (ei2i e1)+(ei2i e2)
| EIsub e1 e2 => (ei2i e1)-(ei2i e2)
| EImul e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZadd e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZsub e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmul e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Z.max (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIadd e1 e2 => EZadd (norm_ei e1) (norm_ei e2)
| EIsub e1 e2 => EZsub (norm_ei e1) (norm_ei e2)
| EImul e1 e2 => EZmul (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZadd e1 e2 => EZadd (norm_ez e1) (norm_ez e2)
| EZsub e1 e2 => EZsub (norm_ez e1) (norm_ez e2)
| EZmul e1 e2 => EZmul (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct (e:ExprI) : ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct (e:ExprZ) : ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct (e:ExprP) : ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; rewrite ?norm_ez_correct; intuition.
Qed.
Lemma norm_ep_correct2 (e:ExprP) : ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Local Open Scope Z_scope.
Definition t := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition add := Z.add.
Definition opp := Z.opp.
Definition sub := Z.sub.
Definition mul := Z.mul.
Definition max := Z.max.
Definition eqb := Z.eqb.
Definition ltb := Z.ltb.
Definition leb := Z.leb.
Definition eq_dec := Z.eq_dec.
Definition gt_le_dec i j : {i > j} + { i <= j }.
Proof.
generalize (Z.ltb_spec j i).
destruct (j <? i); [left|right]; inversion H; trivial.
now apply Z.lt_gt.
Defined.
Definition ge_lt_dec i j : {i >= j} + { i < j }.
Proof.
generalize (Z.ltb_spec i j).
destruct (i <? j); [right|left]; inversion H; trivial.
now apply Z.le_ge.
Defined.
Definition i2z : t -> Z := fun n => n.
Lemma i2z_eq n p : i2z n = i2z p -> n = p. Proof. trivial. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. reflexivity. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. reflexivity. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. reflexivity. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. reflexivity. Qed.
Lemma i2z_add n p : i2z (n + p) = i2z n + i2z p.
Proof. reflexivity. Qed.
Lemma i2z_opp n : i2z (- n) = - i2z n.
Proof. reflexivity. Qed.
Lemma i2z_sub n p : i2z (n - p) = i2z n - i2z p.
Proof. reflexivity. Qed.
Lemma i2z_mul n p : i2z (n * p) = i2z n * i2z p.
Proof. reflexivity. Qed.
Lemma i2z_max n p : i2z (max n p) = Z.max (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_eqb n p : eqb n p = Z.eqb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_leb n p : leb n p = Z.leb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_ltb n p : ltb n p = Z.ltb (i2z n) (i2z p).
Proof. reflexivity. Qed.
End Z_as_Int.
|
// megafunction wizard: %ALTFP_CONVERT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: ALTFP_CONVERT
// ============================================================
// File Name: acl_fp_uitofp.v
// Megafunction Name(s):
// ALTFP_CONVERT
//
// Simulation Library Files(s):
// lpm
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.0 Build 262 08/18/2010 SP 1 SJ Full Version
// ************************************************************
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altfp_convert CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" OPERATION="INT2FLOAT" ROUNDING="TO_NEAREST" WIDTH_DATA=33 WIDTH_EXP_INPUT=8 WIDTH_EXP_OUTPUT=8 WIDTH_INT=33 WIDTH_MAN_INPUT=23 WIDTH_MAN_OUTPUT=23 WIDTH_RESULT=32 clk_en clock dataa result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_altfp_convert 2010:08:18:21:07:09:SJ cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_altsyncram 2010:08:18:21:07:10:SJ cbx_cycloneii 2010:08:18:21:07:12:SJ cbx_lpm_abs 2010:08:18:21:07:12:SJ cbx_lpm_add_sub 2010:08:18:21:07:12:SJ cbx_lpm_compare 2010:08:18:21:07:12:SJ cbx_lpm_decode 2010:08:18:21:07:12:SJ cbx_lpm_divide 2010:08:18:21:07:12:SJ cbx_lpm_mux 2010:08:18:21:07:12:SJ cbx_mgl 2010:08:18:21:11:11:SJ cbx_stratix 2010:08:18:21:07:13:SJ cbx_stratixii 2010:08:18:21:07:13:SJ cbx_stratixiii 2010:08:18:21:07:13:SJ cbx_stratixv 2010:08:18:21:07:13:SJ cbx_util_mgl 2010:08:18:21:07:13:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//altbarrel_shift CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Stratix IV" PIPELINE=2 SHIFTDIR="LEFT" SHIFTTYPE="LOGICAL" WIDTH=33 WIDTHDIST=6 aclr clk_en clock data distance result
//VERSION_BEGIN 10.0SP1 cbx_altbarrel_shift 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources = reg 71
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altbarrel_shift_ssf
(
aclr,
clk_en,
clock,
data,
distance,
result) ;
input aclr;
input clk_en;
input clock;
input [32:0] data;
input [5:0] distance;
output [32:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
tri1 clk_en;
tri0 clock;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
reg [1:0] dir_pipe;
reg [32:0] sbit_piper1d;
reg [32:0] sbit_piper2d;
reg sel_pipec3r1d;
reg sel_pipec4r1d;
reg sel_pipec5r1d;
wire [6:0] dir_w;
wire direction_w;
wire [31:0] pad_w;
wire [230:0] sbit_w;
wire [5:0] sel_w;
wire [197:0] smux_w;
// synopsys translate_off
initial
dir_pipe = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) dir_pipe <= 2'b0;
else if (clk_en == 1'b1) dir_pipe <= {dir_w[5], dir_w[2]};
// synopsys translate_off
initial
sbit_piper1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper1d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper1d <= smux_w[98:66];
// synopsys translate_off
initial
sbit_piper2d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sbit_piper2d <= 33'b0;
else if (clk_en == 1'b1) sbit_piper2d <= smux_w[197:165];
// synopsys translate_off
initial
sel_pipec3r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec3r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec3r1d <= distance[3];
// synopsys translate_off
initial
sel_pipec4r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec4r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec4r1d <= distance[4];
// synopsys translate_off
initial
sel_pipec5r1d = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sel_pipec5r1d <= 1'b0;
else if (clk_en == 1'b1) sel_pipec5r1d <= distance[5];
assign
dir_w = {dir_pipe[1], dir_w[4:3], dir_pipe[0], dir_w[1:0], direction_w},
direction_w = 1'b0,
pad_w = {32{1'b0}},
result = sbit_w[230:198],
sbit_w = {sbit_piper2d, smux_w[164:99], sbit_piper1d, smux_w[65:0], data},
sel_w = {sel_pipec5r1d, sel_pipec4r1d, sel_pipec3r1d, distance[2:0]},
smux_w = {((({33{(sel_w[5] & (~ dir_w[5]))}} & {sbit_w[165], pad_w[31:0]}) | ({33{(sel_w[5] & dir_w[5])}} & {pad_w[31:0], sbit_w[197]})) | ({33{(~ sel_w[5])}} & sbit_w[197:165])), ((({33{(sel_w[4] & (~ dir_w[4]))}} & {sbit_w[148:132], pad_w[15:0]}) | ({33{(sel_w[4] & dir_w[4])}} & {pad_w[15:0], sbit_w[164:148]})) | ({33{(~ sel_w[4])}} & sbit_w[164:132])), ((({33{(sel_w[3] & (~ dir_w[3]))}} & {sbit_w[123:99], pad_w[7:0]}) | ({33{(sel_w[3] & dir_w[3])}} & {pad_w[7:0], sbit_w[131:107]})) | ({33{(~ sel_w[3])}} & sbit_w[131:99])), ((({33{(sel_w[2] & (~ dir_w[2]))}} & {sbit_w[94:66], pad_w[3:0]}) | ({33{(sel_w[2] & dir_w[2])}} & {pad_w[3:0], sbit_w[98:70]})) | ({33{(~ sel_w[2])}} & sbit_w[98:66])), ((({33{(sel_w[1] & (~ dir_w[1]))}} & {sbit_w[63:33], pad_w[1:0]}) | ({33{(sel_w[1] & dir_w[1])}} & {pad_w[1:0], sbit_w[65:35]})) | ({33{(~ sel_w[1])}} & sbit_w[65:33])), ((({33{(sel_w[0] & (~ dir_w[0]))}} & {sbit_w[31:0], pad_w[0]}) | ({33{(sel_w[0] & dir_w[0])}} & {pad_w[0], sbit_w[32:1]})) | ({33{(~ sel_w[0])}} & sbit_w[32:0]))};
endmodule //acl_fp_uitofp_altbarrel_shift_ssf
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" WIDTH=64 WIDTHAD=6 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q zero
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_3e8
(
data,
q,
zero) ;
input [1:0] data;
output [0:0] q;
output zero;
assign
q = {data[1]},
zero = (~ (data[0] | data[1]));
endmodule //acl_fp_uitofp_altpriority_encoder_3e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_6e8
(
data,
q,
zero) ;
input [3:0] data;
output [1:0] q;
output zero;
wire [0:0] wire_altpriority_encoder17_q;
wire wire_altpriority_encoder17_zero;
wire [0:0] wire_altpriority_encoder18_q;
wire wire_altpriority_encoder18_zero;
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder17
(
.data(data[1:0]),
.q(wire_altpriority_encoder17_q),
.zero(wire_altpriority_encoder17_zero));
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder18
(
.data(data[3:2]),
.q(wire_altpriority_encoder18_q),
.zero(wire_altpriority_encoder18_zero));
assign
q = {(~ wire_altpriority_encoder18_zero), ((wire_altpriority_encoder18_zero & wire_altpriority_encoder17_q) | ((~ wire_altpriority_encoder18_zero) & wire_altpriority_encoder18_q))},
zero = (wire_altpriority_encoder17_zero & wire_altpriority_encoder18_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_6e8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_be8
(
data,
q,
zero) ;
input [7:0] data;
output [2:0] q;
output zero;
wire [1:0] wire_altpriority_encoder15_q;
wire wire_altpriority_encoder15_zero;
wire [1:0] wire_altpriority_encoder16_q;
wire wire_altpriority_encoder16_zero;
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder15
(
.data(data[3:0]),
.q(wire_altpriority_encoder15_q),
.zero(wire_altpriority_encoder15_zero));
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder16
(
.data(data[7:4]),
.q(wire_altpriority_encoder16_q),
.zero(wire_altpriority_encoder16_zero));
assign
q = {(~ wire_altpriority_encoder16_zero), (({2{wire_altpriority_encoder16_zero}} & wire_altpriority_encoder15_q) | ({2{(~ wire_altpriority_encoder16_zero)}} & wire_altpriority_encoder16_q))},
zero = (wire_altpriority_encoder15_zero & wire_altpriority_encoder16_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_be8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_rf8
(
data,
q,
zero) ;
input [15:0] data;
output [3:0] q;
output zero;
wire [2:0] wire_altpriority_encoder13_q;
wire wire_altpriority_encoder13_zero;
wire [2:0] wire_altpriority_encoder14_q;
wire wire_altpriority_encoder14_zero;
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder13
(
.data(data[7:0]),
.q(wire_altpriority_encoder13_q),
.zero(wire_altpriority_encoder13_zero));
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder14
(
.data(data[15:8]),
.q(wire_altpriority_encoder14_q),
.zero(wire_altpriority_encoder14_zero));
assign
q = {(~ wire_altpriority_encoder14_zero), (({3{wire_altpriority_encoder14_zero}} & wire_altpriority_encoder13_q) | ({3{(~ wire_altpriority_encoder14_zero)}} & wire_altpriority_encoder14_q))},
zero = (wire_altpriority_encoder13_zero & wire_altpriority_encoder14_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_rf8
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_qf8
(
data,
q,
zero) ;
input [31:0] data;
output [4:0] q;
output zero;
wire [3:0] wire_altpriority_encoder11_q;
wire wire_altpriority_encoder11_zero;
wire [3:0] wire_altpriority_encoder12_q;
wire wire_altpriority_encoder12_zero;
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder11
(
.data(data[15:0]),
.q(wire_altpriority_encoder11_q),
.zero(wire_altpriority_encoder11_zero));
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder12
(
.data(data[31:16]),
.q(wire_altpriority_encoder12_q),
.zero(wire_altpriority_encoder12_zero));
assign
q = {(~ wire_altpriority_encoder12_zero), (({4{wire_altpriority_encoder12_zero}} & wire_altpriority_encoder11_q) | ({4{(~ wire_altpriority_encoder12_zero)}} & wire_altpriority_encoder12_q))},
zero = (wire_altpriority_encoder11_zero & wire_altpriority_encoder12_zero);
endmodule //acl_fp_uitofp_altpriority_encoder_qf8
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=32 WIDTHAD=5 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=16 WIDTHAD=4 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=8 WIDTHAD=3 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=4 WIDTHAD=2 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//altpriority_encoder CBX_AUTO_BLACKBOX="ALL" LSB_PRIORITY="NO" WIDTH=2 WIDTHAD=1 data q
//VERSION_BEGIN 10.0SP1 cbx_altpriority_encoder 2010:08:18:21:07:09:SJ cbx_mgl 2010:08:18:21:11:11:SJ VERSION_END
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_3v7
(
data,
q) ;
input [1:0] data;
output [0:0] q;
assign
q = {data[1]};
endmodule //acl_fp_uitofp_altpriority_encoder_3v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_6v7
(
data,
q) ;
input [3:0] data;
output [1:0] q;
wire [0:0] wire_altpriority_encoder25_q;
wire [0:0] wire_altpriority_encoder26_q;
wire wire_altpriority_encoder26_zero;
acl_fp_uitofp_altpriority_encoder_3v7 altpriority_encoder25
(
.data(data[1:0]),
.q(wire_altpriority_encoder25_q));
acl_fp_uitofp_altpriority_encoder_3e8 altpriority_encoder26
(
.data(data[3:2]),
.q(wire_altpriority_encoder26_q),
.zero(wire_altpriority_encoder26_zero));
assign
q = {(~ wire_altpriority_encoder26_zero), ((wire_altpriority_encoder26_zero & wire_altpriority_encoder25_q) | ((~ wire_altpriority_encoder26_zero) & wire_altpriority_encoder26_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_6v7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_bv7
(
data,
q) ;
input [7:0] data;
output [2:0] q;
wire [1:0] wire_altpriority_encoder23_q;
wire [1:0] wire_altpriority_encoder24_q;
wire wire_altpriority_encoder24_zero;
acl_fp_uitofp_altpriority_encoder_6v7 altpriority_encoder23
(
.data(data[3:0]),
.q(wire_altpriority_encoder23_q));
acl_fp_uitofp_altpriority_encoder_6e8 altpriority_encoder24
(
.data(data[7:4]),
.q(wire_altpriority_encoder24_q),
.zero(wire_altpriority_encoder24_zero));
assign
q = {(~ wire_altpriority_encoder24_zero), (({2{wire_altpriority_encoder24_zero}} & wire_altpriority_encoder23_q) | ({2{(~ wire_altpriority_encoder24_zero)}} & wire_altpriority_encoder24_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_bv7
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_r08
(
data,
q) ;
input [15:0] data;
output [3:0] q;
wire [2:0] wire_altpriority_encoder21_q;
wire [2:0] wire_altpriority_encoder22_q;
wire wire_altpriority_encoder22_zero;
acl_fp_uitofp_altpriority_encoder_bv7 altpriority_encoder21
(
.data(data[7:0]),
.q(wire_altpriority_encoder21_q));
acl_fp_uitofp_altpriority_encoder_be8 altpriority_encoder22
(
.data(data[15:8]),
.q(wire_altpriority_encoder22_q),
.zero(wire_altpriority_encoder22_zero));
assign
q = {(~ wire_altpriority_encoder22_zero), (({3{wire_altpriority_encoder22_zero}} & wire_altpriority_encoder21_q) | ({3{(~ wire_altpriority_encoder22_zero)}} & wire_altpriority_encoder22_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_r08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_q08
(
data,
q) ;
input [31:0] data;
output [4:0] q;
wire [3:0] wire_altpriority_encoder19_q;
wire [3:0] wire_altpriority_encoder20_q;
wire wire_altpriority_encoder20_zero;
acl_fp_uitofp_altpriority_encoder_r08 altpriority_encoder19
(
.data(data[15:0]),
.q(wire_altpriority_encoder19_q));
acl_fp_uitofp_altpriority_encoder_rf8 altpriority_encoder20
(
.data(data[31:16]),
.q(wire_altpriority_encoder20_q),
.zero(wire_altpriority_encoder20_zero));
assign
q = {(~ wire_altpriority_encoder20_zero), (({4{wire_altpriority_encoder20_zero}} & wire_altpriority_encoder19_q) | ({4{(~ wire_altpriority_encoder20_zero)}} & wire_altpriority_encoder20_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_q08
//synthesis_resources =
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altpriority_encoder_0c6
(
data,
q) ;
input [63:0] data;
output [5:0] q;
wire [4:0] wire_altpriority_encoder10_q;
wire wire_altpriority_encoder10_zero;
wire [4:0] wire_altpriority_encoder9_q;
acl_fp_uitofp_altpriority_encoder_qf8 altpriority_encoder10
(
.data(data[63:32]),
.q(wire_altpriority_encoder10_q),
.zero(wire_altpriority_encoder10_zero));
acl_fp_uitofp_altpriority_encoder_q08 altpriority_encoder9
(
.data(data[31:0]),
.q(wire_altpriority_encoder9_q));
assign
q = {(~ wire_altpriority_encoder10_zero), (({5{wire_altpriority_encoder10_zero}} & wire_altpriority_encoder9_q) | ({5{(~ wire_altpriority_encoder10_zero)}} & wire_altpriority_encoder10_q))};
endmodule //acl_fp_uitofp_altpriority_encoder_0c6
//synthesis_resources = lpm_add_sub 5 lpm_compare 1 reg 253
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module acl_fp_uitofp_altfp_convert_0jn
(
clk_en,
clock,
dataa,
result) ;
input clk_en;
input clock;
input [32:0] dataa;
output [31:0] result;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri1 clk_en;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [32:0] wire_altbarrel_shift5_result;
wire [5:0] wire_altpriority_encoder2_q;
reg add_1_adder1_cout_reg;
reg [11:0] add_1_adder1_reg;
reg add_1_adder2_cout_reg;
reg [11:0] add_1_adder2_reg;
reg add_1_reg;
reg [7:0] exponent_bus_pre_reg;
reg [7:0] exponent_bus_pre_reg2;
reg [7:0] exponent_bus_pre_reg3;
reg [31:0] mag_int_a_reg;
reg [31:0] mag_int_a_reg2;
reg [23:0] mantissa_pre_round_reg;
reg [5:0] priority_encoder_reg;
reg [31:0] result_reg;
reg sign_int_a_reg1;
reg sign_int_a_reg2;
reg sign_int_a_reg3;
reg sign_int_a_reg4;
reg sign_int_a_reg5;
wire [31:0] wire_add_sub1_result;
wire [7:0] wire_add_sub3_result;
wire wire_add_sub6_cout;
wire [11:0] wire_add_sub6_result;
wire wire_add_sub7_cout;
wire [11:0] wire_add_sub7_result;
wire [7:0] wire_add_sub8_result;
wire wire_cmpr4_alb;
wire aclr;
wire [11:0] add_1_adder1_w;
wire [11:0] add_1_adder2_w;
wire [23:0] add_1_adder_w;
wire add_1_w;
wire [7:0] bias_value_w;
wire [7:0] const_bias_value_add_width_int_w;
wire [7:0] exceptions_value;
wire [7:0] exponent_bus;
wire [7:0] exponent_bus_pre;
wire [7:0] exponent_output_w;
wire [7:0] exponent_rounded;
wire [7:0] exponent_zero_w;
wire guard_bit_w;
wire [31:0] int_a;
wire [31:0] int_a_2s;
wire [31:0] invert_int_a;
wire [5:0] leading_zeroes;
wire [31:0] mag_int_a;
wire [22:0] mantissa_bus;
wire mantissa_overflow;
wire [23:0] mantissa_post_round;
wire [23:0] mantissa_pre_round;
wire [23:0] mantissa_rounded;
wire max_neg_value_selector;
wire [7:0] max_neg_value_w;
wire [7:0] minus_leading_zero;
wire [32:0] prio_mag_int_a;
wire [30:0] priority_pad_one_w;
wire [31:0] result_w;
wire round_bit_w;
wire [31:0] shifted_mag_int_a;
wire sign_bus;
wire sign_int_a;
wire [6:0] sticky_bit_bus;
wire [6:0] sticky_bit_or_w;
wire sticky_bit_w;
wire [1:0] zero_padding_w;
acl_fp_uitofp_altbarrel_shift_ssf altbarrel_shift5
(
.aclr(aclr),
.clk_en(clk_en),
.clock(clock),
.data({1'b0, mag_int_a_reg2}),
.distance(leading_zeroes),
.result(wire_altbarrel_shift5_result));
acl_fp_uitofp_altpriority_encoder_0c6 altpriority_encoder2
(
.data({prio_mag_int_a, priority_pad_one_w}),
.q(wire_altpriority_encoder2_q));
// synopsys translate_off
initial
add_1_adder1_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder1_cout_reg <= wire_add_sub6_cout;
// synopsys translate_off
initial
add_1_adder1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder1_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder1_reg <= wire_add_sub6_result;
// synopsys translate_off
initial
add_1_adder2_cout_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_cout_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_adder2_cout_reg <= wire_add_sub7_cout;
// synopsys translate_off
initial
add_1_adder2_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_adder2_reg <= 12'b0;
else if (clk_en == 1'b1) add_1_adder2_reg <= wire_add_sub7_result;
// synopsys translate_off
initial
add_1_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) add_1_reg <= 1'b0;
else if (clk_en == 1'b1) add_1_reg <= add_1_w;
// synopsys translate_off
initial
exponent_bus_pre_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg <= exponent_bus_pre_reg2;
// synopsys translate_off
initial
exponent_bus_pre_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg2 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg2 <= exponent_bus_pre_reg3;
// synopsys translate_off
initial
exponent_bus_pre_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) exponent_bus_pre_reg3 <= 8'b0;
else if (clk_en == 1'b1) exponent_bus_pre_reg3 <= exponent_bus_pre;
// synopsys translate_off
initial
mag_int_a_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg <= mag_int_a;
// synopsys translate_off
initial
mag_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mag_int_a_reg2 <= 32'b0;
else if (clk_en == 1'b1) mag_int_a_reg2 <= mag_int_a_reg;
// synopsys translate_off
initial
mantissa_pre_round_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) mantissa_pre_round_reg <= 24'b0;
else if (clk_en == 1'b1) mantissa_pre_round_reg <= mantissa_pre_round;
// synopsys translate_off
initial
priority_encoder_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) priority_encoder_reg <= 6'b0;
else if (clk_en == 1'b1) priority_encoder_reg <= wire_altpriority_encoder2_q;
// synopsys translate_off
initial
result_reg = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) result_reg <= 32'b0;
else if (clk_en == 1'b1) result_reg <= result_w;
// synopsys translate_off
initial
sign_int_a_reg1 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg1 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg1 <= sign_int_a;
// synopsys translate_off
initial
sign_int_a_reg2 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg2 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg2 <= sign_int_a_reg1;
// synopsys translate_off
initial
sign_int_a_reg3 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg3 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg3 <= sign_int_a_reg2;
// synopsys translate_off
initial
sign_int_a_reg4 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg4 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg4 <= sign_int_a_reg3;
// synopsys translate_off
initial
sign_int_a_reg5 = 0;
// synopsys translate_on
always @ ( posedge clock or posedge aclr)
if (aclr == 1'b1) sign_int_a_reg5 <= 1'b0;
else if (clk_en == 1'b1) sign_int_a_reg5 <= sign_int_a_reg4;
lpm_add_sub add_sub1
(
.cout(),
.dataa(invert_int_a),
.datab(32'b00000000000000000000000000000001),
.overflow(),
.result(wire_add_sub1_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub1.lpm_direction = "ADD",
add_sub1.lpm_width = 32,
add_sub1.lpm_type = "lpm_add_sub",
add_sub1.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub3
(
.cout(),
.dataa(const_bias_value_add_width_int_w),
.datab(minus_leading_zero),
.overflow(),
.result(wire_add_sub3_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub3.lpm_direction = "SUB",
add_sub3.lpm_width = 8,
add_sub3.lpm_type = "lpm_add_sub",
add_sub3.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub6
(
.cout(wire_add_sub6_cout),
.dataa(mantissa_pre_round[11:0]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub6_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub6.lpm_direction = "ADD",
add_sub6.lpm_width = 12,
add_sub6.lpm_type = "lpm_add_sub",
add_sub6.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub7
(
.cout(wire_add_sub7_cout),
.dataa(mantissa_pre_round[23:12]),
.datab(12'b000000000001),
.overflow(),
.result(wire_add_sub7_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub7.lpm_direction = "ADD",
add_sub7.lpm_width = 12,
add_sub7.lpm_type = "lpm_add_sub",
add_sub7.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_add_sub add_sub8
(
.cout(),
.dataa(exponent_bus_pre_reg),
.datab(8'b00000001),
.overflow(),
.result(wire_add_sub8_result)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.add_sub(1'b1),
.cin(),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
add_sub8.lpm_direction = "ADD",
add_sub8.lpm_width = 8,
add_sub8.lpm_type = "lpm_add_sub",
add_sub8.lpm_hint = "ONE_INPUT_IS_CONSTANT=YES";
lpm_compare cmpr4
(
.aeb(),
.agb(),
.ageb(),
.alb(wire_cmpr4_alb),
.aleb(),
.aneb(),
.dataa(exponent_output_w),
.datab(bias_value_w)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cmpr4.lpm_representation = "UNSIGNED",
cmpr4.lpm_width = 8,
cmpr4.lpm_type = "lpm_compare";
assign
aclr = 1'b0,
add_1_adder1_w = add_1_adder1_reg,
add_1_adder2_w = (({12{(~ add_1_adder1_cout_reg)}} & mantissa_pre_round_reg[23:12]) | ({12{add_1_adder1_cout_reg}} & add_1_adder2_reg)),
add_1_adder_w = {add_1_adder2_w, add_1_adder1_w},
add_1_w = ((((~ guard_bit_w) & round_bit_w) & sticky_bit_w) | (guard_bit_w & round_bit_w)),
bias_value_w = 8'b01111111,
const_bias_value_add_width_int_w = 8'b10011110,
exceptions_value = (({8{(~ max_neg_value_selector)}} & exponent_zero_w) | ({8{max_neg_value_selector}} & max_neg_value_w)),
exponent_bus = exponent_rounded,
exponent_bus_pre = (({8{(~ wire_cmpr4_alb)}} & exponent_output_w) | ({8{wire_cmpr4_alb}} & exceptions_value)),
exponent_output_w = wire_add_sub3_result,
exponent_rounded = (({8{(~ mantissa_overflow)}} & exponent_bus_pre_reg) | ({8{mantissa_overflow}} & wire_add_sub8_result)),
exponent_zero_w = {8{1'b0}},
guard_bit_w = shifted_mag_int_a[8],
int_a = dataa[31:0],
int_a_2s = wire_add_sub1_result,
invert_int_a = (~ int_a),
leading_zeroes = (~ priority_encoder_reg),
mag_int_a = (({32{(~ sign_int_a)}} & int_a) | ({32{sign_int_a}} & int_a_2s)),
mantissa_bus = mantissa_rounded[22:0],
mantissa_overflow = ((add_1_reg & add_1_adder1_cout_reg) & add_1_adder2_cout_reg),
mantissa_post_round = add_1_adder_w,
mantissa_pre_round = shifted_mag_int_a[31:8],
mantissa_rounded = (({24{(~ add_1_reg)}} & mantissa_pre_round_reg) | ({24{add_1_reg}} & mantissa_post_round)),
max_neg_value_selector = (wire_cmpr4_alb & sign_int_a_reg2),
max_neg_value_w = 8'b10011111,
minus_leading_zero = {zero_padding_w, leading_zeroes},
prio_mag_int_a = {mag_int_a_reg, 1'b1},
priority_pad_one_w = {31{1'b1}},
result = result_reg,
result_w = {sign_bus, exponent_bus, mantissa_bus},
round_bit_w = shifted_mag_int_a[7],
shifted_mag_int_a = wire_altbarrel_shift5_result[31:0],
sign_bus = sign_int_a_reg5,
sign_int_a = dataa[32],
sticky_bit_bus = shifted_mag_int_a[6:0],
sticky_bit_or_w = {(sticky_bit_or_w[5] | sticky_bit_bus[6]), (sticky_bit_or_w[4] | sticky_bit_bus[5]), (sticky_bit_or_w[3] | sticky_bit_bus[4]), (sticky_bit_or_w[2] | sticky_bit_bus[3]), (sticky_bit_or_w[1] | sticky_bit_bus[2]), (sticky_bit_or_w[0] | sticky_bit_bus[1]), sticky_bit_bus[0]},
sticky_bit_w = sticky_bit_or_w[6],
zero_padding_w = {2{1'b0}};
endmodule //acl_fp_uitofp_altfp_convert_0jn
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_uitofp (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
acl_fp_uitofp_altfp_convert_0jn acl_fp_uitofp_altfp_convert_0jn_component (
.clk_en (enable),
.clock (clock),
.dataa ({1'b0,dataa}),
.result (sub_wire0));
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix IV"
// Retrieval info: CONSTANT: LPM_HINT STRING "UNUSED"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altfp_convert"
// Retrieval info: CONSTANT: OPERATION STRING "INT2FLOAT"
// Retrieval info: CONSTANT: ROUNDING STRING "TO_NEAREST"
// Retrieval info: CONSTANT: WIDTH_DATA NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_EXP_INPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_EXP_OUTPUT NUMERIC "8"
// Retrieval info: CONSTANT: WIDTH_INT NUMERIC "33"
// Retrieval info: CONSTANT: WIDTH_MAN_INPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_MAN_OUTPUT NUMERIC "23"
// Retrieval info: CONSTANT: WIDTH_RESULT NUMERIC "32"
// Retrieval info: USED_PORT: clk_en 0 0 0 0 INPUT NODEFVAL "clk_en"
// Retrieval info: CONNECT: @clk_en 0 0 0 0 clk_en 0 0 0 0
// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
// Retrieval info: USED_PORT: dataa 0 0 33 0 INPUT NODEFVAL "dataa[32..0]"
// Retrieval info: CONNECT: @dataa 0 0 33 0 dataa 0 0 33 0
// Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL "result[31..0]"
// Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.qip TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.bsf TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_inst.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp_bb.v TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.inc TRUE TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL acl_fp_uitofp.cmp TRUE TRUE
// Retrieval info: LIB_FILE: lpm
|
module decoder_6b_40b_en(
addr_in,
en,
out);
input[5:0] addr_in;
wire[5:0] addr_in;
output[39:0] out;
wire[39:0] out;
input en;
wire en;
reg[39:0] decoded_out;
always@(addr_in)
begin
decoded_out = 40'd0;
case (addr_in)
0: decoded_out[0]=1'b1;
1: decoded_out[1]=1'b1;
2: decoded_out[2]=1'b1;
3: decoded_out[3]=1'b1;
4: decoded_out[4]=1'b1;
5: decoded_out[5]=1'b1;
6: decoded_out[6]=1'b1;
7: decoded_out[7]=1'b1;
8: decoded_out[8]=1'b1;
9: decoded_out[9]=1'b1;
10: decoded_out[10]=1'b1;
11: decoded_out[11]=1'b1;
12: decoded_out[12]=1'b1;
13: decoded_out[13]=1'b1;
14: decoded_out[14]=1'b1;
15: decoded_out[15]=1'b1;
16: decoded_out[16]=1'b1;
17: decoded_out[17]=1'b1;
18: decoded_out[18]=1'b1;
19: decoded_out[19]=1'b1;
20: decoded_out[20]=1'b1;
21: decoded_out[21]=1'b1;
22: decoded_out[22]=1'b1;
23: decoded_out[23]=1'b1;
24: decoded_out[24]=1'b1;
25: decoded_out[25]=1'b1;
26: decoded_out[26]=1'b1;
27: decoded_out[27]=1'b1;
28: decoded_out[28]=1'b1;
29: decoded_out[29]=1'b1;
30: decoded_out[30]=1'b1;
31: decoded_out[31]=1'b1;
32: decoded_out[32]=1'b1;
33: decoded_out[33]=1'b1;
34: decoded_out[34]=1'b1;
35: decoded_out[35]=1'b1;
36: decoded_out[36]=1'b1;
37: decoded_out[37]=1'b1;
38: decoded_out[38]=1'b1;
39: decoded_out[39]=1'b1;
default: decoded_out = 40'd0;
endcase
end
assign out = (en)?decoded_out:40'd0;
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PIO.v
// Version : 1.11
//
// Description: Programmed I/O module. Design implements 8 KBytes of programmable
//-- memory space. Host processor can access this memory space using
//-- Memory Read 32 and Memory Write 32 TLPs. Design accepts
//-- 1 Double Word (DW) payload length on Memory Write 32 TLP and
//-- responds to 1 DW length Memory Read 32 TLPs with a Completion
//-- with Data TLP (1DW payload).
//--
//--------------------------------------------------------------------------------
`timescale 1ps/1ps
module PIO #(
parameter C_DATA_WIDTH = 64, // RX/TX interface data width
// Do not override parameters below this line
parameter KEEP_WIDTH = C_DATA_WIDTH / 8, // TSTRB width
parameter TCQ = 1
)(
input user_clk,
input user_reset,
input user_lnk_up,
// AXIS
input s_axis_tx_tready,
output [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
output [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
output s_axis_tx_tlast,
output s_axis_tx_tvalid,
output tx_src_dsc,
input [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
input [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
input m_axis_rx_tlast,
input m_axis_rx_tvalid,
output m_axis_rx_tready,
input [21:0] m_axis_rx_tuser,
input cfg_to_turnoff,
output cfg_turnoff_ok,
input [15:0] cfg_completer_id
); // synthesis syn_hier = "hard"
// Local wires
wire req_compl;
wire compl_done;
reg pio_reset_n;
always @(posedge user_clk) begin
if (user_reset)
pio_reset_n <= #TCQ 1'b0;
else
pio_reset_n <= #TCQ user_lnk_up;
end
//
// PIO instance
//
PIO_EP #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH ),
.TCQ( TCQ )
) PIO_EP_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.s_axis_tx_tready( s_axis_tx_tready ), // I
.s_axis_tx_tdata( s_axis_tx_tdata ), // O
.s_axis_tx_tkeep( s_axis_tx_tkeep ), // O
.s_axis_tx_tlast( s_axis_tx_tlast ), // O
.s_axis_tx_tvalid( s_axis_tx_tvalid ), // O
.tx_src_dsc( tx_src_dsc ), // O
.m_axis_rx_tdata( m_axis_rx_tdata ), // I
.m_axis_rx_tkeep( m_axis_rx_tkeep ), // I
.m_axis_rx_tlast( m_axis_rx_tlast ), // I
.m_axis_rx_tvalid( m_axis_rx_tvalid ), // I
.m_axis_rx_tready( m_axis_rx_tready ), // O
.m_axis_rx_tuser ( m_axis_rx_tuser ), // I
.req_compl(req_compl), // O
.compl_done(compl_done), // O
.cfg_completer_id ( cfg_completer_id ) // I [15:0]
);
//
// Turn-Off controller
//
PIO_TO_CTRL #(
.TCQ( TCQ )
) PIO_TO_inst (
.clk( user_clk ), // I
.rst_n( pio_reset_n ), // I
.req_compl( req_compl ), // I
.compl_done( compl_done ), // I
.cfg_to_turnoff( cfg_to_turnoff ), // I
.cfg_turnoff_ok( cfg_turnoff_ok ) // O
);
endmodule // PIO
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DLRTP_LP_V
`define SKY130_FD_SC_LP__DLRTP_LP_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog wrapper for dlrtp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dlrtp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE ,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input RESET_B;
input D ;
input GATE ;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dlrtp_lp (
Q ,
RESET_B,
D ,
GATE
);
output Q ;
input RESET_B;
input D ;
input GATE ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dlrtp base (
.Q(Q),
.RESET_B(RESET_B),
.D(D),
.GATE(GATE)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DLRTP_LP_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// Top level module for pipelined memory access.
//
// Properties - Coalesced: No, Ordered: N/A, Hazard-Safe: Yes, Pipelined: Yes
// (see lsu_top.v for details)
//
// Description: Requests are submitted as soon as they are received.
// Pipelined access to memory so multiple requests can be
// in flight at a time.
// Pipelined read unit:
// Accept read requests on the upstream interface. When a request is
// received, store the requested byte address in the request fifo and
// pass the request through to the avalon interface. Response data
// is buffered in the response fifo and the appropriate word is muxed
// out of the response fifo based on the address in the request fifo.
// The response fifo has limited capacity, so a counter is used to track
// the number of pending responses to generate an upstream stall if
// we run out of room.
module lsu_pipelined_read
(
clk, reset, o_stall, i_valid, i_address, i_burstcount, i_stall, o_valid, o_readdata,
o_active, //Debugging signal
avm_address, avm_read, avm_readdata, avm_waitrequest, avm_byteenable,
avm_readdatavalid,
o_input_fifo_depth,
avm_burstcount
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access (bytes)
parameter MWIDTH_BYTES=32; // Width of the global memory bus (bytes)
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter KERNEL_SIDE_MEM_LATENCY=32; // The max number of live threads
parameter USEBURST=0;
parameter BURSTCOUNT_WIDTH=6; // Size of Avalon burst count port
parameter USEINPUTFIFO=1;
parameter USEOUTPUTFIFO=1;
parameter INPUTFIFOSIZE=32;
parameter PIPELINE_INPUT=0;
parameter SUPERPIPELINE=0; // Enable extremely aggressive pipelining of the LSU
parameter HIGH_FMAX=1;
localparam INPUTFIFO_USEDW_MAXBITS=$clog2(INPUTFIFOSIZE);
// Derived parameters
localparam MAX_BURST=2**(BURSTCOUNT_WIDTH-1);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
//
// We only o_stall if we have more than KERNEL_SIDE_MEM_LATENCY inflight requests
//
localparam RETURN_FIFO_SIZE=KERNEL_SIDE_MEM_LATENCY+(USEBURST ? 0 : 1);
localparam COUNTER_WIDTH=USEBURST ? $clog2(RETURN_FIFO_SIZE+1+MAX_BURST) : $clog2(RETURN_FIFO_SIZE+1);
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [BURSTCOUNT_WIDTH-1:0] i_burstcount;
// Downstream interface
input i_stall;
output o_valid;
output [WIDTH-1:0] o_readdata;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_read;
input [MWIDTH-1:0] avm_readdata;
input avm_waitrequest;
output [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_readdatavalid;
output [BURSTCOUNT_WIDTH-1:0] avm_burstcount;
// For profiler/performance monitor
output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;
/***************
* Architecture *
***************/
wire i_valid_from_fifo;
wire [AWIDTH-1:0] i_address_from_fifo;
wire o_stall_to_fifo;
wire [BURSTCOUNT_WIDTH-1:0] i_burstcount_from_fifo;
wire read_accepted;
wire read_used;
wire [BYTE_SELECT_BITS-1:0] byte_select;
wire ready;
wire out_fifo_wait;
localparam FIFO_DEPTH_BITS=USEINPUTFIFO ? $clog2(INPUTFIFOSIZE) : 0;
wire [FIFO_DEPTH_BITS-1:0] usedw_true_width;
generate
if (USEINPUTFIFO)
assign o_input_fifo_depth[FIFO_DEPTH_BITS-1:0] = usedw_true_width;
// Set unused bits to 0
genvar bit_index;
for(bit_index = FIFO_DEPTH_BITS; bit_index < INPUTFIFO_USEDW_MAXBITS; bit_index = bit_index + 1)
begin: read_fifo_depth_zero_assign
assign o_input_fifo_depth[bit_index] = 1'b0;
end
endgenerate
generate
if(USEINPUTFIFO && SUPERPIPELINE)
begin
wire int_stall;
wire int_valid;
wire [AWIDTH+BURSTCOUNT_WIDTH-1:0] int_data;
acl_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) input_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_burstcount} ),
.data_out( int_data ),
.valid_in( i_valid ),
.valid_out( int_valid ),
.stall_in( int_stall ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
// Add a pipeline and stall-breaking FIFO
// TODO: Consider making this parameterizeable
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_fifo_buffer (
.clock(clk),
.resetn(!reset),
.data_in( int_data ),
.valid_in( int_valid ),
.data_out( {i_address_from_fifo,i_burstcount_from_fifo} ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( int_stall )
);
end
else if(USEINPUTFIFO && !SUPERPIPELINE)
begin
acl_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) input_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_burstcount} ),
.data_out( {i_address_from_fifo,i_burstcount_from_fifo} ),
.valid_in( i_valid ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
end
else if(PIPELINE_INPUT)
begin
reg r_valid;
reg [AWIDTH-1:0] r_address;
reg [BURSTCOUNT_WIDTH-1:0] r_burstcount;
assign o_stall = r_valid && o_stall_to_fifo;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
r_valid <= 1'b0;
else
begin
if (!o_stall)
begin
r_valid <= i_valid;
r_address <= i_address;
r_burstcount <= i_burstcount;
end
end
end
assign i_valid_from_fifo = r_valid;
assign i_address_from_fifo = r_address;
assign i_burstcount_from_fifo = r_burstcount;
end
else
begin
assign i_valid_from_fifo = i_valid;
assign i_address_from_fifo = i_address;
assign o_stall = o_stall_to_fifo;
assign i_burstcount_from_fifo = i_burstcount;
end
endgenerate
// Track the number of transactions waiting in the pipeline here
reg [COUNTER_WIDTH-1:0] counter;
wire incr, decr;
assign incr = read_accepted;
assign decr = read_used;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
counter <= {COUNTER_WIDTH{1'b0}};
o_active <= 1'b0;
end
else
begin
o_active <= (counter != {COUNTER_WIDTH{1'b0}});
// incr - add one or i_burstcount_from_fifo; decr - subtr one;
if (USEBURST==1)
counter <= counter + (incr ? i_burstcount_from_fifo : 0) - decr;
else
counter <= counter + incr - decr;
end
end
generate
if(USEBURST)
// Use the burstcount to figure out if there is enough space
assign ready = ((counter+i_burstcount_from_fifo) <= RETURN_FIFO_SIZE);
//
// Can also use decr in this calaculation to make ready respond faster
// but this seems to hurt Fmax ( ie. not worth it )
//assign ready = ((counter+i_burstcount_from_fifo-decr) <= RETURN_FIFO_SIZE);
else
// Can we hold one more item
assign ready = (counter <= (RETURN_FIFO_SIZE-1));
endgenerate
assign o_stall_to_fifo = !ready || out_fifo_wait;
// Optional Pipeline register before return
//
reg r_avm_readdatavalid;
reg [MWIDTH-1:0] r_avm_readdata;
generate
if(SUPERPIPELINE)
begin
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
r_avm_readdata <= 'x;
r_avm_readdatavalid <= 1'b0;
end
else
begin
r_avm_readdata <= avm_readdata;
r_avm_readdatavalid <= avm_readdatavalid;
end
end
end
else
begin
// Don't register the return
always@(*)
begin
r_avm_readdata = avm_readdata;
r_avm_readdatavalid = avm_readdatavalid;
end
end
endgenerate
wire [WIDTH-1:0] rdata;
// Byte-addresses enter a FIFO so we can demux the appropriate data back out.
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_address_out;
wire [SEGMENT_SELECT_BITS-1:0] segment_address_in;
assign segment_address_in = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
acl_ll_fifo #(
.WIDTH(SEGMENT_SELECT_BITS),
.DEPTH(KERNEL_SIDE_MEM_LATENCY+1)
) req_fifo (
.clk(clk),
.reset(reset),
.data_in( segment_address_in ),
.data_out( segment_address_out ),
.write( read_accepted ),
.read( r_avm_readdatavalid ),
.empty(),
.full()
);
assign byte_select = (segment_address_out << ALIGNMENT_ABITS);
assign rdata = r_avm_readdata[8*byte_select +: WIDTH];
end
else
begin
assign byte_select = '0;
assign rdata = r_avm_readdata;
end
endgenerate
// Status bits
assign read_accepted = i_valid_from_fifo && ready && !out_fifo_wait;
assign read_used = o_valid && !i_stall;
assign avm_byteenable = {MWIDTH_BYTES{1'b1}};
// Optional: Pipelining FIFO on the AVM interface
//
generate
if(SUPERPIPELINE)
begin
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+BURSTCOUNT_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) avm_buffer (
.clock(clk),
.resetn(!reset),
.data_in({((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS),i_burstcount_from_fifo}),
.valid_in( i_valid_from_fifo && ready ),
.data_out( {avm_address,avm_burstcount} ),
.valid_out( avm_read ),
.stall_in( avm_waitrequest ),
.stall_out( out_fifo_wait )
);
end
else
begin
// No interface pipelining
assign out_fifo_wait = avm_waitrequest;
assign avm_address = ((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_read = i_valid_from_fifo && ready;
assign avm_burstcount = i_burstcount_from_fifo;
end
endgenerate
// ---------------------------------------------------------------------------------
// Output fifo - must be at least as deep as the maximum number of pending requests
// so that we can guarantee a place for the response data if the downstream blocks
// are stalling.
//
generate
if(USEOUTPUTFIFO)
begin
acl_data_fifo #(
.DATA_WIDTH(WIDTH),
.DEPTH(RETURN_FIFO_SIZE),
.IMPL((SUPERPIPELINE && HIGH_FMAX) ? "ram_plus_reg" : "ram")
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( rdata ),
.data_out( o_readdata ),
.valid_in( r_avm_readdatavalid ),
.valid_out( o_valid ),
.stall_in( i_stall ),
.stall_out()
);
end
else
begin
assign o_valid = r_avm_readdatavalid;
assign o_readdata = rdata;
end
endgenerate
endmodule
/******************************************************************************/
// Pipelined write unit:
// Accept write requests on the upstream interface. Mux the data into the
// appropriate word lines based on the segment select bits. Also toggle
// the appropriate byte-enable lines to preserve data we are not
// overwriting. A counter keeps track of how many requests have been
// send but not yet acknowledged by downstream blocks.
module lsu_pipelined_write
(
clk, reset, o_stall, i_valid, i_address, i_writedata, i_stall, o_valid, i_byteenable,
o_active, //Debugging signal
avm_address, avm_write, avm_writeack, avm_writedata, avm_byteenable, avm_waitrequest, o_input_fifo_depth
);
/*************
* Parameters *
*************/
parameter AWIDTH=32; // Address width (32-bits for Avalon)
parameter WIDTH_BYTES=4; // Width of the memory access
parameter MWIDTH_BYTES=32; // Width of the global memory bus
parameter ALIGNMENT_ABITS=2; // Request address alignment (address bits)
parameter COUNTER_WIDTH=6;
parameter KERNEL_SIDE_MEM_LATENCY=32;
parameter USEINPUTFIFO=1;
parameter USE_BYTE_EN=0;
parameter INPUTFIFOSIZE=32;
parameter INPUTFIFO_USEDW_MAXBITS=$clog2(INPUTFIFOSIZE);
localparam WIDTH=8*WIDTH_BYTES;
localparam MWIDTH=8*MWIDTH_BYTES;
localparam BYTE_SELECT_BITS=$clog2(MWIDTH_BYTES);
localparam SEGMENT_SELECT_BITS=BYTE_SELECT_BITS-ALIGNMENT_ABITS;
localparam NUM_SEGMENTS=2**SEGMENT_SELECT_BITS;
localparam SEGMENT_WIDTH=8*(2**ALIGNMENT_ABITS);
localparam SEGMENT_WIDTH_BYTES=(2**ALIGNMENT_ABITS);
/********
* Ports *
********/
// Standard global signals
input clk;
input reset;
// Upstream interface
output o_stall;
input i_valid;
input [AWIDTH-1:0] i_address;
input [WIDTH-1:0] i_writedata;
input [WIDTH_BYTES-1:0] i_byteenable;
// Downstream interface
input i_stall;
output o_valid;
output reg o_active;
// Avalon interface
output [AWIDTH-1:0] avm_address;
output avm_write;
input avm_writeack;
output reg [MWIDTH-1:0] avm_writedata;
output reg [MWIDTH_BYTES-1:0] avm_byteenable;
input avm_waitrequest;
// For profiler/performance monitor
output [INPUTFIFO_USEDW_MAXBITS-1:0] o_input_fifo_depth;
/***************
* Architecture *
***************/
reg transaction_complete;
wire write_accepted;
wire ready;
wire sr_stall;
wire i_valid_from_fifo;
wire [AWIDTH-1:0] i_address_from_fifo;
wire [WIDTH-1:0] i_writedata_from_fifo;
wire [WIDTH_BYTES-1:0] i_byteenable_from_fifo;
wire o_stall_to_fifo;
localparam FIFO_DEPTH_BITS=USEINPUTFIFO ? $clog2(INPUTFIFOSIZE) : 0;
wire [FIFO_DEPTH_BITS-1:0] usedw_true_width;
generate
if (USEINPUTFIFO)
assign o_input_fifo_depth[FIFO_DEPTH_BITS-1:0] = usedw_true_width;
// Set unused bits to 0
genvar bit_index;
for(bit_index = FIFO_DEPTH_BITS; bit_index < INPUTFIFO_USEDW_MAXBITS; bit_index = bit_index + 1)
begin: write_fifo_depth_zero_assign
assign o_input_fifo_depth[bit_index] = 1'b0;
end
endgenerate
localparam DATA_WIDTH = AWIDTH+WIDTH+(USE_BYTE_EN ? WIDTH_BYTES : 0);
generate
if(USEINPUTFIFO)
begin
wire valid_int;
wire stall_int;
wire [DATA_WIDTH-1:0] data_int;
if(!USE_BYTE_EN)
begin
acl_fifo #(
.DATA_WIDTH(AWIDTH+WIDTH),
.DEPTH(INPUTFIFOSIZE)
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_address,i_writedata} ),
.data_out( data_int ),
.valid_in( i_valid ),
.valid_out( valid_int ),
.stall_in( stall_int ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
acl_data_fifo #(
.DATA_WIDTH(AWIDTH+WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_buf (
.clock(clk),
.resetn(!reset),
.data_in( data_int ),
.data_out( {i_address_from_fifo,i_writedata_from_fifo} ),
.valid_in( valid_int ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( stall_int )
);
assign i_byteenable_from_fifo = {WIDTH_BYTES{1'b1}};
end else begin
acl_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(INPUTFIFOSIZE)
) data_fifo (
.clock(clk),
.resetn(!reset),
.data_in( {i_byteenable, i_address,i_writedata}),
.data_out( data_int ),
.valid_in( i_valid ),
.valid_out( valid_int ),
.stall_in( stall_int ),
.stall_out( o_stall ),
.usedw( usedw_true_width )
);
acl_data_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.DEPTH(2),
.IMPL("ll_reg")
) input_buf (
.clock(clk),
.resetn(!reset),
.data_in( data_int ),
.data_out({i_byteenable_from_fifo,i_address_from_fifo,i_writedata_from_fifo}),
.valid_in( valid_int ),
.valid_out( i_valid_from_fifo ),
.stall_in( o_stall_to_fifo ),
.stall_out( stall_int )
);
end
end
else
begin
assign i_valid_from_fifo = i_valid;
assign i_address_from_fifo = i_address;
assign i_writedata_from_fifo = i_writedata;
assign o_stall = o_stall_to_fifo;
assign i_byteenable_from_fifo = USE_BYTE_EN ? i_byteenable : {WIDTH_BYTES{1'b1}};
end
endgenerate
// Avalon interface
assign avm_address = ((i_address_from_fifo >> BYTE_SELECT_BITS) << BYTE_SELECT_BITS);
assign avm_write = ready && i_valid_from_fifo;
// Mux in the correct data
generate
if(SEGMENT_SELECT_BITS > 0)
begin
wire [SEGMENT_SELECT_BITS-1:0] segment_select;
assign segment_select = i_address_from_fifo[ALIGNMENT_ABITS +: BYTE_SELECT_BITS-ALIGNMENT_ABITS];
always@(*)
begin
avm_writedata = {MWIDTH{1'bx}};
avm_writedata[segment_select*SEGMENT_WIDTH +: WIDTH] = i_writedata_from_fifo;
avm_byteenable = {MWIDTH_BYTES{1'b0}};
avm_byteenable[segment_select*SEGMENT_WIDTH_BYTES +: WIDTH_BYTES] = i_byteenable_from_fifo;
end
end
else
begin
always@(*)
begin
avm_writedata = i_writedata_from_fifo;
avm_byteenable = i_byteenable_from_fifo;
end
end
endgenerate
// Control logic
reg [COUNTER_WIDTH-1:0] occ_counter; // occupancy counter
wire occ_incr, occ_decr;
reg [COUNTER_WIDTH-1:0] ack_counter; // acknowledge writes counter
wire ack_incr, ack_decr;
// Track the number of transactions waiting in the pipeline here
assign occ_incr = write_accepted;
assign occ_decr = o_valid && !i_stall;
assign ack_incr = avm_writeack;
assign ack_decr = o_valid && !i_stall;
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
occ_counter <= {COUNTER_WIDTH{1'b0}};
ack_counter <= {COUNTER_WIDTH{1'b0}};
o_active <= 1'b0;
end
else
begin
// incr - add one; decr - subtr one; both - stay the same
occ_counter <= occ_counter + { {(COUNTER_WIDTH-1){!occ_incr && occ_decr}}, (occ_incr ^ occ_decr) };
ack_counter <= ack_counter + { {(COUNTER_WIDTH-1){!ack_incr && ack_decr}}, (ack_incr ^ ack_decr) };
o_active <= (occ_counter != {COUNTER_WIDTH{1'b0}});
end
end
assign ready = (occ_counter != {COUNTER_WIDTH{1'b1}});
assign write_accepted = avm_write && !avm_waitrequest;
assign o_stall_to_fifo = !ready || avm_waitrequest;
assign o_valid = (ack_counter != {COUNTER_WIDTH{1'b0}});
endmodule
|
//Copyright (C) 1991-2003 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
module add32 (
dataa,
datab,
result)/* synthesis synthesis_clearbox = 1 */;
input [7:0] dataa;
input [7:0] datab;
output [7:0] result;
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sat May 27 20:55:50 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub
// c:/ZyboIP/examples/zed_camera_test/zed_camera_test.srcs/sources_1/bd/system/ip/system_g8_to_rgb888_0_0/system_g8_to_rgb888_0_0_stub.v
// Design : system_g8_to_rgb888_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "g8_to_rgb888,Vivado 2016.4" *)
module system_g8_to_rgb888_0_0(g8, rgb888)
/* synthesis syn_black_box black_box_pad_pin="g8[7:0],rgb888[23:0]" */;
input [7:0]g8;
output [23:0]rgb888;
endmodule
|
`timescale 1 ns / 1 ps
module axis_oscilloscope #
(
parameter integer AXIS_TDATA_WIDTH = 32,
parameter integer CNTR_WIDTH = 12
)
(
// System signals
input wire aclk,
input wire aresetn,
input wire run_flag,
input wire trg_flag,
input wire [CNTR_WIDTH-1:0] pre_data,
input wire [CNTR_WIDTH-1:0] tot_data,
output wire [CNTR_WIDTH:0] sts_data,
// Slave side
output wire s_axis_tready,
input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
input wire s_axis_tvalid,
// Master side
output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
output wire m_axis_tvalid
);
reg [CNTR_WIDTH-1:0] int_addr_reg, int_addr_next;
reg [CNTR_WIDTH-1:0] int_cntr_reg, int_cntr_next;
reg [1:0] int_case_reg, int_case_next;
reg int_enbl_reg, int_enbl_next;
always @(posedge aclk)
begin
if(~aresetn)
begin
int_addr_reg <= {(CNTR_WIDTH){1'b0}};
int_cntr_reg <= {(CNTR_WIDTH){1'b0}};
int_case_reg <= 2'd0;
int_enbl_reg <= 1'b0;
end
else
begin
int_addr_reg <= int_addr_next;
int_cntr_reg <= int_cntr_next;
int_case_reg <= int_case_next;
int_enbl_reg <= int_enbl_next;
end
end
always @*
begin
int_addr_next = int_addr_reg;
int_cntr_next = int_cntr_reg;
int_case_next = int_case_reg;
int_enbl_next = int_enbl_reg;
case(int_case_reg)
// idle
0:
begin
if(run_flag)
begin
int_addr_next = {(CNTR_WIDTH){1'b0}};
int_cntr_next = {(CNTR_WIDTH){1'b0}};
int_case_next = 2'd1;
int_enbl_next = 1'b1;
end
end
// pre-trigger recording
1:
begin
if(s_axis_tvalid)
begin
int_cntr_next = int_cntr_reg + 1'b1;
if(int_cntr_reg == pre_data)
begin
int_case_next = 2'd2;
end
end
end
// pre-trigger recording
2:
begin
if(s_axis_tvalid)
begin
int_cntr_next = int_cntr_reg + 1'b1;
if(trg_flag)
begin
int_addr_next = int_cntr_reg;
int_cntr_next = pre_data + int_cntr_reg[5:0];
int_case_next = 2'd3;
end
end
end
// post-trigger recording
3:
begin
if(s_axis_tvalid)
begin
if(int_cntr_reg < tot_data)
begin
int_cntr_next = int_cntr_reg + 1'b1;
end
else
begin
int_case_next = 2'd0;
int_enbl_next = 1'b0;
end
end
end
endcase
end
assign sts_data = {int_addr_reg, int_enbl_reg};
assign s_axis_tready = 1'b1;
assign m_axis_tdata = s_axis_tdata;
assign m_axis_tvalid = int_enbl_reg & s_axis_tvalid;
endmodule
|
/*
* Zet processor core
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
`include "defines.v"
module zet_core (
input clk,
input rst,
// interrupts
input intr,
output inta,
input nmi,
output nmia,
// interface to wishbone
output [19:0] cpu_adr_o,
input [15:0] iid_dat_i,
input [15:0] cpu_dat_i,
output [15:0] cpu_dat_o,
output cpu_byte_o,
input cpu_block,
output cpu_mem_op,
output cpu_m_io,
output cpu_we_o,
output [19:0] pc // for debugging purposes
);
// Net declarations
wire [`IR_SIZE-1:0] ir;
wire [15:0] off;
wire [15:0] imm;
wire wr_ip0;
wire [15:0] cs;
wire [15:0] ip;
wire of;
wire zf;
wire ifl;
wire iflm;
wire tfl;
wire tflm;
wire iflss;
wire wr_ss;
wire cx_zero;
wire div_exc;
wire [19:0] addr_exec;
wire byte_fetch;
wire byte_exec;
// wire decode - microcode
wire [`MICRO_ADDR_WIDTH-1:0] seq_addr;
wire [3:0] src;
wire [3:0] dst;
wire [3:0] base;
wire [3:0] index;
wire [1:0] seg;
wire end_seq;
wire [2:0] fdec;
wire div;
// wires fetch - decode
wire [7:0] opcode;
wire [7:0] modrm;
wire rep;
wire exec_st;
wire ld_base;
wire [2:0] sop_l;
wire need_modrm;
wire need_off;
wire need_imm;
wire off_size;
wire imm_size;
wire ext_int;
// wires fetch - microcode
wire [15:0] off_l;
wire [15:0] imm_l;
wire [15:0] imm_d;
wire [`IR_SIZE-1:0] rom_ir;
wire [5:0] ftype;
// wires fetch - exec
wire [15:0] imm_f;
// wires and regs for hlt
wire block_or_hlt;
wire hlt_op;
wire hlt_in;
wire hlt_out;
reg hlt_op_old;
reg hlt;
// regs for nmi
reg nmir;
reg nmi_old;
reg nmia_old;
// Module instantiations
zet_fetch fetch (
.clk (clk),
.rst (rst),
// to decode
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.exec_st (exec_st),
.ld_base (ld_base),
.sop_l (sop_l),
// from decode
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.ext_int (ext_int),
.end_seq (end_seq),
// to microcode
.off_l (off_l),
.imm_l (imm_l),
// from microcode
.ftype (ftype),
// to exec
.imm_f (imm_f),
.wr_ip0 (wr_ip0),
// from exec
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.iflm (iflm),
.tflm (tflm),
.iflss (iflss),
.cx_zero (cx_zero),
.div_exc (div_exc),
// to wb
.data (cpu_dat_i),
.pc (pc),
.bytefetch (byte_fetch),
.block (block_or_hlt),
.intr (intr),
.nmir (nmir)
);
zet_decode decode (
.clk (clk),
.rst (rst),
.opcode (opcode),
.modrm (modrm),
.rep (rep),
.block (block_or_hlt),
.exec_st (exec_st),
.div_exc (div_exc),
.ld_base (ld_base),
.div (div),
.tfl (tfl),
.tflm (tflm),
.need_modrm (need_modrm),
.need_off (need_off),
.need_imm (need_imm),
.off_size (off_size),
.imm_size (imm_size),
.sop_l (sop_l),
.intr (intr),
.ifl (ifl),
.iflm (iflm),
.inta (inta),
.ext_int (ext_int),
.nmir (nmir),
.nmia (nmia),
.wr_ss (wr_ss),
.iflss (iflss),
.seq_addr (seq_addr),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.f (fdec),
.end_seq (end_seq)
);
zet_micro_data micro_data (
// from decode
.n_micro (seq_addr),
.off_i (off_l),
.imm_i (imm_l),
.src (src),
.dst (dst),
.base (base),
.index (index),
.seg (seg),
.fdec (fdec),
.div (div),
.end_seq (end_seq),
// to exec
.ir (rom_ir),
.off_o (off),
.imm_o (imm_d)
);
zet_exec exec (
.clk (clk),
.rst (rst),
// from fetch
.ir (ir),
.off (off),
.imm (imm),
.wrip0 (wr_ip0),
// to fetch
.cs (cs),
.ip (ip),
.of (of),
.zf (zf),
.ifl (ifl),
.tfl (tfl),
.cx_zero (cx_zero),
.div_exc (div_exc),
.wr_ss (wr_ss),
// from wb
.memout (iid_dat_i),
.wr_data (cpu_dat_o),
.addr (addr_exec),
.we (cpu_we_o),
.m_io (cpu_m_io),
.byteop (byte_exec),
.block (block_or_hlt)
);
// Assignments
assign cpu_adr_o = exec_st ? addr_exec : pc;
assign cpu_byte_o = exec_st ? byte_exec : byte_fetch;
assign cpu_mem_op = ir[`MEM_OP];
assign ir = exec_st ? rom_ir : `ADD_IP;
assign imm = exec_st ? imm_d : imm_f;
assign ftype = rom_ir[28:23];
assign hlt_op = ((opcode == `OP_HLT) && exec_st);
assign hlt_in = (hlt_op && !hlt_op_old && !hlt_out);
assign hlt_out = (intr & ifl) | nmir;
assign block_or_hlt = cpu_block | hlt | hlt_in;
// Behaviour
always @(posedge clk)
if (rst)
hlt_op_old <= 1'b0;
else
if (hlt_op)
hlt_op_old <= 1'b1;
else
hlt_op_old <= 1'b0;
always @(posedge clk)
if (rst)
hlt <= 1'b0;
else
if (hlt_in)
hlt <= 1'b1;
else if (hlt_out)
hlt <= 1'b0;
always @(posedge clk)
if (rst)
begin
nmir <= 1'b0;
nmi_old <= 1'b0;
nmia_old <= 1'b0;
end
else
begin
nmi_old <= nmi;
nmia_old <= nmia;
if (nmi & ~nmi_old)
nmir <= 1'b1;
else if (nmia_old)
nmir <= 1'b0;
end
endmodule
|
// -------------------------------------------------------------
//
// Generated Architecture Declaration for rtl of inst_ef_e
//
// Generated
// by: wig
// on: Mon Apr 10 13:27:22 2006
// cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -nodelta ../../bitsplice.xls
//
// !!! Do not edit this file! Autogenerated by MIX !!!
// $Author: wig $
// $Id: inst_ef_e.v,v 1.1 2006/04/10 15:42:08 wig Exp $
// $Date: 2006/04/10 15:42:08 $
// $Log: inst_ef_e.v,v $
// Revision 1.1 2006/04/10 15:42:08 wig
// Updated testcase (__TOP__)
//
//
// Based on Mix Verilog Architecture Template built into RCSfile: MixWriter.pm,v
// Id: MixWriter.pm,v 1.79 2006/03/17 09:18:31 wig Exp
//
// Generator: mix_0.pl Revision: 1.44 , [email protected]
// (C) 2003,2005 Micronas GmbH
//
// --------------------------------------------------------------
`timescale 1ns/10ps
//
//
// Start of Generated Module rtl of inst_ef_e
//
// No user `defines in this module
module inst_ef_e
//
// Generated module inst_ef
//
(
);
// End of generated module header
// Internal signals
//
// Generated Signal List
//
//
// End of Generated Signal List
//
// %COMPILER_OPTS%
// Generated Signal Assignments
//
// Generated Instances
// wiring ...
// Generated Instances and Port Mappings
endmodule
//
// End of Generated Module rtl of inst_ef_e
//
//
//!End of Module/s
// --------------------------------------------------------------
|
/* ****************************************************************************
-- (C) Copyright 2016 Kevin M. Hubbard - All rights reserved.
-- Source file: sump2.v
-- Date: July 2016
-- Author: khubbard
-- Description: SUMP2 is a fast and simple logic analyzer.
-- It captures N/2 samples before and after a specified
-- positive edged trigger event where N is length of BRAM.
-- It is designed to be really small and simple for places where
-- SUMP-RLE is either too big or overly complicated. It also
-- runs much faster and wider than SUMP-RLE.
-- SUMP2 is NOT software compatible with SUMP-RLE.
-- Language: Verilog-2001
-- Simulation: Mentor-Modelsim
-- Synthesis: Xilint-XST,Xilinx-Vivado,Lattice-Synplify
-- License: This project is licensed with the CERN Open Hardware Licence
-- v1.2. You may redistribute and modify this project under the
-- terms of the CERN OHL v.1.2. (http://ohwr.org/cernohl).
-- This project is distributed WITHOUT ANY EXPRESS OR IMPLIED
-- WARRANTY, INCLUDING OF MERCHANTABILITY, SATISFACTORY QUALITY
-- AND FITNESS FOR A PARTICULAR PURPOSE. Please see the CERN OHL
-- v.1.2 for applicable Conditions.
--
-- Design Instance Parameters with examples:
-- depth_len = 1024 : Depth of RAM in number of cell, example 1024,4096
-- depth_bits = 10 : Number of RAM address lines, example 10,12
-- event_bytes = 4 : Number of event bytes 1,2,3 or 4
-- data_dwords = 16 : Number of DWORDs for Data 0,4,8,12 or 16
--
-- nonrle_en = 1 : If 0, removes Event RAM (for small RLE only designs)
-- rle_en = 1 : Adds logic for Event RLE captures.
-- pattern_en = 1 : Adds logic for 32bit event pattern triggers
-- trigger_nth_en = 1 : Adds logic for triggering on Nth trigger event
-- trigger_dly_en = 1 : Adds logic for triggering after a delay from trigger
--
-- freq_mhz = 16'd80 : Freq integer 0 MHz up to 65 GHz ( 16bit )
-- freq_fracts = 16'h0000 : Freq fraction bits, example C000 = 0.75 MHz
-- sump_id = 16'hABBA : Don't Change
-- sump_rev = 8'h02 : Don't Change
--
-- LocalBus 2 DWORD Register Interface
-- lb_cs_ctrl : PCI addr sel for Control
-- lb_cs_data : PCI addr sel for Data transfers. +0x4 offset from lb_cs_ctrl
--
-- clk_lb _/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_/ \_
-- lb_cs_ctrl _____/ \___/ \___________________________________________
-- lb_cs_data _________________________/ \_______________________________
-- lb_wr _____/ \__/ \___________________________________________
-- lb_rd _________________________/ \______________________________
-- lb_wr_d -----< >--< >-------------------------------------------
-- lb_rd_dy _________________________________________/ \______________
-- lb_rd_d -----------------------------------------< >--------------
-- |---------------| variable distance
--
-- Software Interface
-- 6bit Control Commands:
-- 0x00 : Idle + Read Status
-- 0x01 : ARM + Read Status
-- 0x02 : Reset
--
-- 0x04 : Load Trigger Type ( AND,OR,Ext )
-- 0x05 : Load Trigger Field ( AND/OR bits )
-- 0x06 : Load Trigger Delay & nth
-- 0x07 : Load Trigger Position ( Num Post Trigger Samples to capture ).
--
-- 0x08 : Load RLE Event Enable
-- 0x09 : Load Read Pointer
-- 0x0a : Load Read Page
--
-- 0x0b : Read HW ID + Revision
-- 0x0c : Read HW Config RAM Width+Length
-- 0x0d : Read HW Config Sample Clock Frequency
-- 0x0e : Read Trigger Location
-- 0x0f : Read RAM Data ( address auto incrementing )
--
-- 0x10 : Load User Controls
-- 0x11 : Load User Pattern0
-- 0x12 : Load User Pattern1
-- 0x13 : Load Data Enable Field
--
-- 0x18 : Read Deep-RAM Width+Length
-- 0x19 : Read Deep-RAM Trigger Location + Status
-- 0x1a : Read Deep-RAM Data ( address auto incrementing )
-- 0x1b : Load Deep-RAM Read Pointer
-- 0x1c : Load Deep-RAM Read Page
-- 0x1d : Load Deep-Sump User Control
-- 0x1e : Load Deep-Sump User Mask
-- 0x1f : Load Deep-Sump User Cfg
--
-- 0x20 - 0x3F : Reserved for future use
--
-- Trigger Types:
-- AND Rising = 0x00;
-- AND Falling = 0x01;
-- OR Rising = 0x02;
-- OR Falling = 0x03;
-- Pattern Rising = 0x04;
-- Pattern Falling = 0x05;
-- Input Trigger Rising = 0x06;
-- Input Trigger Falling = 0x07;
--
-- Revision History:
-- Ver# When Who What
-- ---- -------- -------- --------------------------------------------------
-- 0.1 07.01.16 khubbard Creation. Rev01
-- 0.2 05.14.18 khubbard Rev02 DeepSump support added. Ctrl from 5 to 6bits
-- ***************************************************************************/
`default_nettype none // Strictly enforce all nets to be declared
module sump2 #
(
parameter depth_len = 1024,
parameter depth_bits = 10,
parameter event_bytes = 4,
parameter data_dwords = 16,
parameter nonrle_en = 1,
parameter rle_en = 1,
parameter data_en = 1,
parameter pattern_en = 1,
parameter trigger_nth_en = 1,
parameter trigger_dly_en = 1,
parameter trigger_wd_en = 1,
parameter deep_sump_en = 0,
parameter freq_mhz = 16'd80,
parameter freq_fracts = 16'h0000,
parameter sump_id = 16'hABBA,
parameter sump_rev = 8'h02
)
(
input wire reset,
input wire clk_cap,
input wire clk_lb,
input wire lb_cs_ctrl,
input wire lb_cs_data,
input wire lb_wr,
input wire lb_rd,
input wire [31:0] lb_wr_d,
output reg [31:0] lb_rd_d,
output reg lb_rd_rdy,
output reg active,
output wire [31:0] user_ctrl,
output wire [31:0] user_pat0,
output wire [31:0] user_pat1,
input wire trigger_in,
output reg trigger_out,
output reg ds_trigger,
output reg [31:0] ds_events,
output wire [31:0] ds_user_ctrl,
output reg [5:0] ds_cmd_lb,
output reg [5:0] ds_cmd_cap,
output reg ds_rd_req,
output reg ds_wr_req,
output reg [31:0] ds_wr_d,
input wire [31:0] ds_rd_d,
input wire ds_rd_rdy,
input wire ds_rle_pre_done,
input wire ds_rle_post_done,
input wire [31:0] events_din,
input wire [127:0] dwords_3_0,
input wire [127:0] dwords_7_4,
input wire [127:0] dwords_11_8,
input wire [127:0] dwords_15_12
);
wire reset_loc;
wire [15:0] zeros;
wire [15:0] ones;
wire [7:0] cap_status;
wire [5:0] ctrl_cmd;
reg [5:0] ctrl_cmd_loc;
reg ctrl_cmd_xfer;
wire [4:0] ctrl_rd_page;
wire [15:0] ctrl_rd_ptr;
reg [5:0] ctrl_reg;
reg [31:0] events_loc;
reg trigger_loc;
reg trigger_or;
reg trigger_or_p1;
reg trigger_and;
reg trigger_and_p1;
reg trigger_pat;
reg trigger_pat_p1;
reg xfer_clr;
reg rd_inc;
reg armed_jk;
reg triggered_jk;
reg acquired_jk;
reg complete_jk;
reg [31:0] ctrl_04_reg;
reg [31:0] ctrl_05_reg;
reg [31:0] ctrl_06_reg;
reg [31:0] ctrl_07_reg;
reg [31:0] ctrl_08_reg;
reg [31:0] ctrl_09_reg;
reg [31:0] ctrl_0a_reg;
reg [31:0] ctrl_0b_reg;
reg [31:0] ctrl_10_reg;
reg [31:0] ctrl_11_reg;
reg [31:0] ctrl_12_reg;
reg [31:0] ctrl_13_reg;
reg [31:0] ctrl_14_reg;
reg [31:0] ctrl_1d_reg;
wire [31:0] watchdog_reg;
reg [31:0] watchdog_cnt;
reg wd_armed_jk;
reg trigger_wd;
wire [31:0] trigger_bits;
wire [3:0] trigger_type;
wire [31:0] trigger_pos;
wire [15:0] trigger_nth;
wire [15:0] trigger_delay;
reg [15:0] trigger_dly_cnt;
wire [31:0] rle_event_en;
reg [15:0] trigger_cnt;
reg [31:0] ram_rd_d;
reg [depth_bits-1:0] post_trig_cnt;
reg [depth_bits-1:0] trigger_ptr;
reg trigger_in_meta;
reg trigger_in_p1;
reg trigger_in_p2;
wire [31:0] pat0;
wire [31:0] pat1;
// Variable Size Capture BRAM
reg [31:0] event_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_ram_array[depth_len-1:0];
reg [127:0] dwords_7_4_ram_array[depth_len-1:0];
reg [127:0] dwords_11_8_ram_array[depth_len-1:0];
reg [127:0] dwords_15_12_ram_array[depth_len-1:0];
reg [127:0] dwords_3_0_p1;
reg [127:0] dwords_7_4_p1;
reg [127:0] dwords_11_8_p1;
reg [127:0] dwords_15_12_p1;
reg [127:0] dwords_3_0_p2;
reg [127:0] dwords_7_4_p2;
reg [127:0] dwords_11_8_p2;
reg [127:0] dwords_15_12_p2;
reg [127:0] dwords_3_0_do;
reg [127:0] dwords_7_4_do;
reg [127:0] dwords_11_8_do;
reg [127:0] dwords_15_12_do;
reg [depth_bits-1:0] c_addr;
reg [depth_bits-1:0] c_addr_p1;
reg c_we;
reg c_we_p1;
wire [31:0] c_di;
reg [31:0] c_di_p1;
reg [depth_bits-1:0] d_addr;
reg [31:0] d_do;
reg [63:0] rle_ram_array[depth_len-1:0];
reg [depth_bits-1:0] a_addr;
reg [depth_bits-1:0] a_addr_p1;
reg a_we;
reg a_we_p1;
reg [63:0] a_di;
reg [63:0] a_di_p1;
reg [depth_bits-1:0] b_addr;
reg [63:0] b_do;
wire [31:0] data_en_bits;
reg data_en_loc;
reg data_en_loc_p1;
reg [31:0] events_pre;
reg [31:0] events_p1;
reg [31:0] events_p2;
reg [31:0] rle_time;
reg [31:0] rle_time_p1;
reg rle_wd_sample;
reg rle_pre_jk;
reg rle_done_jk;
reg rle_done_loc;
reg rle_pre_done_loc;
wire [7:0] data_4x_dwords;
assign zeros = 16'd0;
assign ones = 16'hFFFF;
assign reset_loc = reset;
//assign cap_status = { rle_en, 1'b0, rle_done_loc, ~rle_pre_jk,
assign cap_status = { rle_en, 1'b0, rle_done_loc, rle_pre_done_loc,
complete_jk, acquired_jk, triggered_jk, armed_jk };
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_done
rle_done_loc <= rle_done_jk && ( deep_sump_en==0 || ds_rle_post_done==1);
rle_pre_done_loc <= ~rle_pre_jk && ( deep_sump_en==0 || ds_rle_pre_done==1);
end // proc_din
//-----------------------------------------------------------------------------
// Flop the input events and support reduction for much smaller designs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_din
if ( event_bytes == 1 ) begin
events_loc <= { 24'd0, events_din[7:0] };
end else if ( event_bytes == 2 ) begin
events_loc <= { 16'd0, events_din[15:0] };
end else if ( event_bytes == 3 ) begin
events_loc <= { 8'd0, events_din[23:0] };
end else begin
events_loc <= { events_din[31:0] };
end
if ( rle_en == 1 ) begin
events_pre <= events_loc[31:0] & rle_event_en[31:0];
events_p1 <= events_pre[31:0];
events_p2 <= events_p1[31:0];
end
end // proc_din
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( * ) begin : proc_data_en
if ( data_en_bits == 32'h00000000 || data_en == 0 ||
( data_en_bits[31:0] & events_din[31:0] ) != 32'h00000000 ) begin
data_en_loc <= 1;// Capture sample in time
end else begin
data_en_loc <= 0;// Prevent sample capture
end
end // proc_data_en
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
integer i;
always @ ( posedge clk_cap ) begin : proc_trig
trigger_in_meta <= trigger_in;
trigger_in_p1 <= trigger_in_meta;
trigger_in_p2 <= trigger_in_p1;
trigger_or <= 0;
trigger_and <= 0;
trigger_pat <= 0;
trigger_or_p1 <= trigger_or;
trigger_and_p1 <= trigger_and;
trigger_pat_p1 <= trigger_pat;
data_en_loc_p1 <= data_en_loc;
for ( i = 0; i <= 31; i=i+1 ) begin
if ( trigger_bits[i] == 1 && events_loc[i] == 1 ) begin
trigger_or <= 1;// This is a 32bit OR
end
end
if ( ( events_loc[31:0] & trigger_bits[31:0] ) == trigger_bits[31:0] ) begin
trigger_and <= 1;
end
if (
(( events_loc[31:0] & pat0[31:0] ) ^
( pat1[31:0] & pat0[31:0] ) ) == 32'h00000000 ) begin
if ( pattern_en == 1 ) begin
trigger_pat <= 1;// Exact 32bit Pattern Match
end
end
end // proc_trig
//-----------------------------------------------------------------------------
// Capture Logic. When armed, capture in a continuous loop until trigger is
// detected and then capture N/2 samples more.
// Note: Software Must go from Idle to Arm to clear the JKs.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_cap
c_we <= 0;
trigger_out <= 0;
trigger_loc <= 0;
trigger_wd <= 0;
active <= 0;
ds_trigger <= 0;
ds_events <= events_p1[31:0];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
active <= 1;
// Watchdog gets armed on 1st kick. Every kick after clears count.
// If count expires, assert trigger_wd.
if ( trigger_wd_en == 1 && ( trigger_or != trigger_or_p1 ) ) begin
wd_armed_jk <= 1;
end
if ( wd_armed_jk == 0 || ( trigger_or != trigger_or_p1 ) ) begin
watchdog_cnt <= 32'd0;
trigger_wd <= 0;
end else begin
watchdog_cnt <= watchdog_cnt[31:0] + 1;
if ( watchdog_cnt == watchdog_reg[31:0] ) begin
trigger_wd <= 1;
wd_armed_jk <= 0;
end
end
if ( triggered_jk == 0 && acquired_jk == 0 ) begin
// PreTrigger Acquire
armed_jk <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
end
if ( trigger_dly_cnt != 16'hFFFF ) begin
trigger_dly_cnt <= trigger_dly_cnt + 1;
end
if ( ( trigger_type==4'h0 && trigger_and==1 && trigger_and_p1==0 ) ||
( trigger_type==4'h1 && trigger_and==0 && trigger_and_p1==1 ) ||
( trigger_type==4'h2 && trigger_or ==1 && trigger_or_p1 ==0 ) ||
( trigger_type==4'h3 && trigger_or ==0 && trigger_or_p1 ==1 ) ||
( trigger_type==4'h4 && trigger_pat==1 && trigger_pat_p1==0 ) ||
( trigger_type==4'h5 && trigger_pat==0 && trigger_pat_p1==1 ) ||
( trigger_type==4'h6 && trigger_in_p1 ==1 && trigger_in_p2 ==0 ) ||
( trigger_type==4'h7 && trigger_in_p1 ==0 && trigger_in_p2 ==1 ) ||
( trigger_type==4'h8 && trigger_wd == 1 )
) begin
if ( trigger_dly_cnt == 16'hFFFF || trigger_dly_en==0 ) begin
trigger_dly_cnt <= 16'd0;
trigger_loc <= 1;// Only used if trigger delay is removed
c_we <= 1;// Store Trigger even if data_en_loc == 0
c_addr <= c_addr + 1;
end
end
// Don't allow trigger until pre-trig buffer is full
// If there is a deep_sump block, wait for it as well.
// if ( complete_jk == 1 ) begin
if ( complete_jk == 1 && ( deep_sump_en==0 || ds_rle_pre_done==1) ) begin
if ( ( trigger_dly_cnt == trigger_delay[15:0] ) ||
( trigger_dly_en==0 && trigger_loc == 1 ) ) begin
trigger_dly_cnt <= 16'hFFFF;
if ( trigger_cnt == trigger_nth[15:0] || trigger_nth_en==0 ) begin
armed_jk <= 0;
trigger_ptr <= c_addr[depth_bits-1:0];
trigger_out <= 1;
triggered_jk <= 1;
ds_trigger <= 1;
end
trigger_cnt <= trigger_cnt + 1;
end
end
end else if ( triggered_jk == 1 && acquired_jk == 0 ) begin
// PostTrigger Acquire
trigger_out <= 1;
if ( data_en_loc == 1 || data_en_loc_p1 == 1 ) begin
c_we <= 1;
c_addr <= c_addr + 1;
post_trig_cnt <= post_trig_cnt + 1;
end
if ( post_trig_cnt == trigger_pos[depth_bits-1:0] ) begin
acquired_jk <= 1;
c_we <= 0;
end
end
// If RAM has rolled, then pre-trigger buffer is full. Assert status bit.
// If RAM hasn't rolled, then pre-trigger samples start at 0x0.
if ( c_addr[depth_bits-1] == 0 && c_addr_p1[depth_bits-1] == 1 ) begin
complete_jk <= 1;
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
c_addr <= zeros[depth_bits-1:0];
post_trig_cnt <= zeros[depth_bits-1:0];
post_trig_cnt[1:0] <= 2'b11;// Subtracts 3 from trigger_pos for alignment
trigger_cnt <= 16'd1;
trigger_dly_cnt <= 16'hFFFF;
armed_jk <= 0;
triggered_jk <= 0;
acquired_jk <= 0;
complete_jk <= 0;
wd_armed_jk <= 0;
end
// Cleanly xfer clock domains
xfer_clr <= 0;
if ( ctrl_cmd_xfer == 1 ) begin
ctrl_cmd_loc <= ctrl_cmd[5:0];
xfer_clr <= 1;
end
ds_cmd_cap <= ctrl_cmd_loc[5:0];
end // proc_cap
assign c_di = events_loc[31:0];
//-----------------------------------------------------------------------------
// RLE Capture Logic. This captures and stores event changes along with
// time stamps to a x64 BRAM. 1st half of RAM is any pre-trigger activity.
// 2nd half of RAM is post-trigger activity. Pre-trig is circular and must
// be unrolled by software in correct order. Enabling RLE block is optional.
//-----------------------------------------------------------------------------
always @ ( posedge clk_cap ) begin : proc_rle
a_we <= 0;
rle_time_p1 <= rle_time[31:0];
// Prevent RLE from hanging in cases where no activity happens after the
// trigger event by storing a non-changing sample periodically every
// 2^24 clock cycles ( about 100ms at 100 MHz )
rle_wd_sample <= rle_time[15] & ~ rle_time_p1[15];
// CMD_ARM
if ( ctrl_cmd_loc == 6'h01 ) begin
rle_time <= rle_time[31:0] + 1;
if ( triggered_jk == 0 ) begin
a_addr[depth_bits-1] <= 0;// Pre-Trigger Half
// If the prebuffer is invalid, store everything, change or no change
// as to immediately fill up RAM with valid samples
// Once prebuffer is valid, only store event deltas ( RLE )
if ( rle_pre_jk == 1 || rle_wd_sample == 1 ||
( events_p1 != events_p2[31:0] ) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_pre_jk <= 0;// PreBuffer is completely valid - and rolling
end
end
end else if ( triggered_jk == 1 && rle_done_jk == 0 ) begin
if ( ( events_p1 != events_p2[31:0] ) || ( rle_wd_sample == 1) ) begin
a_we <= 1;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0] + 1;
// If previous write was to last address in RAM, then call it quits
if ( a_addr[depth_bits-2:0] == ones[depth_bits-2:0] ) begin
rle_done_jk <= 1;// Post-Trig RAM is full
a_we <= 0;
a_addr[depth_bits-2:0] <= a_addr[depth_bits-2:0];
end
// If previous cycle was pre-trig, set address to start of post trig
if ( a_addr[depth_bits-1] == 0 ) begin
a_addr[depth_bits-1] <= 1;// Post-Trigger Half
a_addr[depth_bits-2:0] <= zeros[depth_bits-2:0];
end
end
end
// CMD_RESET
end else if ( ctrl_cmd_loc == 6'h02 ) begin
rle_time <= 32'd0;// 43 seconds at 100 MHz
a_addr <= zeros[depth_bits-1:0];
rle_pre_jk <= 1;
rle_done_jk <= 0;
end
a_di[31:0] <= events_p1[31:0];
a_di[63:32] <= rle_time[31:0];
end // proc_rle
//-----------------------------------------------------------------------------
// Create write/read bus interface to the sump2_deep block
// 0x18 : Read Deep-RAM Width+Length
// 0x19 : Read Deep-RAM Trigger Location + Status
// 0x1a : Read Deep-RAM Data ( address auto incrementing )
// 0x1b : Load Deep-RAM Read Pointer
// 0x1c : Load Deep-RAM Read Page
// 0x1d : Load Deep-Sump User Control
// 0x1e : Load Deep-Sump User Mask
// 0x1f : Load Deep-Sump User Config
// Note: ds_user_ctrl is decoded locally here as it may be used to switch
// between multiple deep_sump.v instances, for example one may use fast
// on chip BRAM and another might use slower external DRAM. A user may
// decide to mux between the two with a ds_user_ctrl bit.
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_ds
ds_wr_req <= 0;
ds_rd_req <= 0;
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h1b ||
ctrl_cmd[5:0] == 6'h1c ||
ctrl_cmd[5:0] == 6'h1e ||
ctrl_cmd[5:0] == 6'h1f ) begin
ds_wr_req <= 1;
ds_wr_d <= lb_wr_d[31:0];
end
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd[5:0] == 6'h18 ||
ctrl_cmd[5:0] == 6'h19 ||
ctrl_cmd[5:0] == 6'h1a ) begin
ds_rd_req <= 1;
end
end
end
//-----------------------------------------------------------------------------
// LocalBus Write Ctrl register
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_wr
ds_cmd_lb <= ctrl_reg[5:0];
if ( lb_wr == 1 && lb_cs_ctrl == 1 ) begin
ctrl_reg[5:0] <= lb_wr_d[5:0];
ctrl_cmd_xfer <= 1;
end
if ( lb_wr == 1 && lb_cs_data == 1 ) begin
case( ctrl_cmd[5:0] )
6'h04 : ctrl_04_reg <= lb_wr_d[31:0];
6'h05 : ctrl_05_reg <= lb_wr_d[31:0];
6'h06 : ctrl_06_reg <= lb_wr_d[31:0];
6'h07 : ctrl_07_reg <= lb_wr_d[31:0];
6'h08 : ctrl_08_reg <= lb_wr_d[31:0];
6'h09 : ctrl_09_reg <= lb_wr_d[31:0];
6'h0A : ctrl_0a_reg <= lb_wr_d[31:0];
6'h0B : ctrl_0b_reg <= lb_wr_d[31:0];
6'h10 : ctrl_10_reg <= lb_wr_d[31:0];
6'h11 : ctrl_11_reg <= lb_wr_d[31:0];
6'h12 : ctrl_12_reg <= lb_wr_d[31:0];
6'h13 : ctrl_13_reg <= lb_wr_d[31:0];
6'h14 : ctrl_14_reg <= lb_wr_d[31:0];
6'h1d : ctrl_1d_reg <= lb_wr_d[31:0];
endcase
end
if ( xfer_clr == 1 ) begin
ctrl_cmd_xfer <= 0;
end
if ( ctrl_cmd == 6'h01 ) begin
d_addr <= c_addr[depth_bits-1:0];// When Acq stops, d_addr will be last
end
if ( lb_wr == 1 && lb_cs_data == 1 && ctrl_cmd == 6'h09 ) begin
d_addr <= lb_wr_d[depth_bits-1:0];// Load user specified address
end
if ( rd_inc == 1 ) begin
d_addr <= d_addr[depth_bits-1:0] + 1;// Auto Increment on each read
end
if ( reset_loc == 1 ) begin
ctrl_reg[5:0] <= 6'd0;
ctrl_cmd_xfer <= 1;// Flag to xfer ctrl_reg into other clock domain
end
end
assign ctrl_cmd[5:0] = ctrl_reg[5:0];
assign trigger_type = ctrl_04_reg[3:0];
assign trigger_bits = ctrl_05_reg[31:0];
assign trigger_nth = ctrl_06_reg[15:0];
assign trigger_delay = ctrl_06_reg[31:16];
assign trigger_pos = ctrl_07_reg[31:0];
assign rle_event_en = ctrl_08_reg[31:0];
assign user_ctrl[31:0] = ctrl_10_reg[31:0];
assign user_pat0[31:0] = ctrl_11_reg[31:0];
assign user_pat1[31:0] = ctrl_12_reg[31:0];
assign pat0[31:0] = ctrl_11_reg[31:0];
assign pat1[31:0] = ctrl_12_reg[31:0];
assign data_en_bits[31:0] = ctrl_13_reg[31:0];
assign watchdog_reg[31:0] = ctrl_14_reg[31:0];
assign ds_user_ctrl[31:0] = ctrl_1d_reg[31:0];
assign ctrl_rd_ptr[15:0] = ctrl_09_reg[15:0];
assign ctrl_rd_page[4:0] = ctrl_0a_reg[4:0];
assign data_4x_dwords = data_dwords;
//-----------------------------------------------------------------------------
// LocalBus readback of ctrl_reg and data_reg
//-----------------------------------------------------------------------------
always @ ( posedge clk_lb ) begin : proc_lb_rd
lb_rd_d <= 32'd0;
lb_rd_rdy <= 0;
rd_inc <= 0;
if ( lb_rd == 1 && lb_cs_ctrl == 1 ) begin
lb_rd_d[5:0] <= ctrl_reg[5:0];
lb_rd_rdy <= 1;
end
if ( ds_rd_rdy == 1 && deep_sump_en == 1 ) begin
lb_rd_d <= ds_rd_d[31:0];
lb_rd_rdy <= 1;
end
if ( lb_rd == 1 && lb_cs_data == 1 ) begin
if ( ctrl_cmd == 6'h00 ||
ctrl_cmd == 6'h01
) begin
lb_rd_d[7:0] <= cap_status[7:0];
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0b ) begin
lb_rd_d[31:16] <= sump_id;// Identification
lb_rd_d[15:8] <= sump_rev;// Revision
lb_rd_d[7] <= deep_sump_en;
lb_rd_d[6] <= data_en;
lb_rd_d[5] <= trigger_wd_en;
lb_rd_d[4] <= ~ nonrle_en;// Invert to disable backwards SW comptbl
lb_rd_d[3] <= rle_en;
lb_rd_d[2] <= pattern_en;
lb_rd_d[1] <= trigger_nth_en;
lb_rd_d[0] <= trigger_dly_en;
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0c ) begin
lb_rd_d[31:28] <= rle_en ;// 1 if RLE RAM exists
lb_rd_d[27:24] <= event_bytes;// How Many Event Bytes 1-4
lb_rd_d[23:16] <= data_4x_dwords[5:2];// How Many 32bit BRAMs data 4x
lb_rd_d[15:0] <= depth_len; // How deep RAMs are
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0d ) begin
lb_rd_d[15:0] <= freq_fracts;// Fractional MHz bits 1/2,1/4,etc.
lb_rd_d[31:16] <= freq_mhz ;// Integer MHz
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0e ) begin
lb_rd_d[depth_bits-1:0] <= trigger_ptr[depth_bits-1:0];// Where Trig Is
lb_rd_rdy <= 1;
end
if ( ctrl_cmd == 6'h0f ) begin
lb_rd_d <= ram_rd_d[31:0];
rd_inc <= 1;// Auto Increment RAM Address
lb_rd_rdy <= 1;
end
end
// Mux between the BRAMs
case( ctrl_rd_page[4:0] )
5'H02 : ram_rd_d <= b_do[31:0]; // RLE Data
5'H03 : ram_rd_d <= b_do[63:32]; // RLE Time
5'H10 : ram_rd_d <= dwords_3_0_do[31:0];
5'H11 : ram_rd_d <= dwords_3_0_do[63:32];
5'H12 : ram_rd_d <= dwords_3_0_do[95:64];
5'H13 : ram_rd_d <= dwords_3_0_do[127:96];
5'H14 : ram_rd_d <= dwords_7_4_do[31:0];
5'H15 : ram_rd_d <= dwords_7_4_do[63:32];
5'H16 : ram_rd_d <= dwords_7_4_do[95:64];
5'H17 : ram_rd_d <= dwords_7_4_do[127:96];
5'H18 : ram_rd_d <= dwords_11_8_do[31:0];
5'H19 : ram_rd_d <= dwords_11_8_do[63:32];
5'H1a : ram_rd_d <= dwords_11_8_do[95:64];
5'H1b : ram_rd_d <= dwords_11_8_do[127:96];
5'H1c : ram_rd_d <= dwords_15_12_do[31:0];
5'H1d : ram_rd_d <= dwords_15_12_do[63:32];
5'H1e : ram_rd_d <= dwords_15_12_do[95:64];
5'H1f : ram_rd_d <= dwords_15_12_do[127:96];
default : ram_rd_d <= d_do[31:0]; // Events
endcase
end // proc_lb_rd
//-----------------------------------------------------------------------------
// Data Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
c_we_p1 <= c_we;
c_addr_p1 <= c_addr;
c_di_p1 <= c_di;
if ( c_we_p1 ) begin
if ( nonrle_en == 1 ) begin
event_ram_array[c_addr_p1] <= c_di_p1;
end
end // if ( c_we )
dwords_3_0_p1 <= dwords_3_0[127:0];
dwords_7_4_p1 <= dwords_7_4[127:0];
dwords_11_8_p1 <= dwords_11_8[127:0];
dwords_15_12_p1 <= dwords_15_12[127:0];
dwords_3_0_p2 <= dwords_3_0_p1[127:0];
dwords_7_4_p2 <= dwords_7_4_p1[127:0];
dwords_11_8_p2 <= dwords_11_8_p1[127:0];
dwords_15_12_p2 <= dwords_15_12_p1[127:0];
if ( c_we_p1 ) begin
if ( data_dwords >= 4 ) begin
dwords_3_0_ram_array[ c_addr_p1 ] <= dwords_3_0_p2[127:0];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_ram_array[ c_addr_p1 ] <= dwords_7_4_p2[127:0];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_ram_array[ c_addr_p1 ] <= dwords_11_8_p2[127:0];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_ram_array[ c_addr_p1 ] <= dwords_15_12_p2[127:0];
end
end // if ( c_we )
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( nonrle_en == 1 ) begin
d_do <= event_ram_array[d_addr] ;
end
if ( data_dwords >= 4 ) begin
dwords_3_0_do <= dwords_3_0_ram_array[ d_addr ];
end
if ( data_dwords >= 8 ) begin
dwords_7_4_do <= dwords_7_4_ram_array[ d_addr ];
end
if ( data_dwords >= 12 ) begin
dwords_11_8_do <= dwords_11_8_ram_array[ d_addr ];
end
if ( data_dwords >= 16 ) begin
dwords_15_12_do <= dwords_15_12_ram_array[ d_addr ];
end
end // always
//-----------------------------------------------------------------------------
// RLE Dual Port RAM - Infer RAM here to make easy to change depth on the fly
//-----------------------------------------------------------------------------
always @( posedge clk_cap )
begin
if ( rle_en == 1 ) begin
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_we_p1 <= a_we;
a_addr_p1 <= a_addr;
a_di_p1 <= a_di;
if ( a_we_p1 ) begin
rle_ram_array[a_addr_p1] <= a_di_p1;
end // if ( a_we )
end
end // always
//-----------------------------------------------------------------------------
// 2nd Port of RAM is clocked from local bus
//-----------------------------------------------------------------------------
always @( posedge clk_lb )
begin
if ( rle_en == 1 ) begin
b_do <= rle_ram_array[d_addr];
end
end // always
endmodule // sump2
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2019 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2020.1
// \ \ Description : Xilinx Unified Simulation Library Component
// / / RFDAC
// /___/ /\ Filename : RFDAC.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module RFDAC #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter integer OPT_CLK_DIST = 0,
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter integer XPA_ACTIVE_DUTYCYCLE = 100,
parameter integer XPA_CFG0 = 0,
parameter integer XPA_CFG1 = 0,
parameter integer XPA_CFG2 = 0,
parameter integer XPA_NUM_DACS = 0,
parameter integer XPA_NUM_DUCS = 0,
parameter XPA_PLL_USED = "EXTERNAL",
parameter integer XPA_SAMPLE_RATE_MSPS = 0
)(
output CLK_DAC,
output CLK_DIST_OUT_NORTH,
output CLK_DIST_OUT_SOUTH,
output [15:0] DOUT,
output DRDY,
output PLL_DMON_OUT,
output PLL_REFCLK_OUT,
output [23:0] STATUS_COMMON,
output [23:0] STATUS_DAC0,
output [23:0] STATUS_DAC1,
output [23:0] STATUS_DAC2,
output [23:0] STATUS_DAC3,
output SYSREF_OUT_NORTH,
output SYSREF_OUT_SOUTH,
output T1_ALLOWED_SOUTH,
output VOUT0_N,
output VOUT0_P,
output VOUT1_N,
output VOUT1_P,
output VOUT2_N,
output VOUT2_P,
output VOUT3_N,
output VOUT3_P,
input CLK_DIST_IN_NORTH,
input CLK_DIST_IN_SOUTH,
input CLK_FIFO_LM,
input [15:0] CONTROL_COMMON,
input [15:0] CONTROL_DAC0,
input [15:0] CONTROL_DAC1,
input [15:0] CONTROL_DAC2,
input [15:0] CONTROL_DAC3,
input DAC_CLK_N,
input DAC_CLK_P,
input [11:0] DADDR,
input [255:0] DATA_DAC0,
input [255:0] DATA_DAC1,
input [255:0] DATA_DAC2,
input [255:0] DATA_DAC3,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input FABRIC_CLK,
input PLL_MONCLK,
input PLL_REFCLK_IN,
input SYSREF_IN_NORTH,
input SYSREF_IN_SOUTH,
input SYSREF_N,
input SYSREF_P,
input T1_ALLOWED_NORTH
);
// define constants
localparam MODULE_NAME = "RFDAC";
reg trig_attr;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "RFDAC_dr.v"
`else
reg [15:0] OPT_CLK_DIST_REG = OPT_CLK_DIST;
reg [152:1] SIM_DEVICE_REG = SIM_DEVICE;
reg [6:0] XPA_ACTIVE_DUTYCYCLE_REG = XPA_ACTIVE_DUTYCYCLE;
reg [15:0] XPA_CFG0_REG = XPA_CFG0;
reg [15:0] XPA_CFG1_REG = XPA_CFG1;
reg [15:0] XPA_CFG2_REG = XPA_CFG2;
reg [2:0] XPA_NUM_DACS_REG = XPA_NUM_DACS;
reg [2:0] XPA_NUM_DUCS_REG = XPA_NUM_DUCS;
reg [112:1] XPA_PLL_USED_REG = XPA_PLL_USED;
reg [13:0] XPA_SAMPLE_RATE_MSPS_REG = XPA_SAMPLE_RATE_MSPS;
`endif
`ifdef XIL_XECLIB
reg glblGSR = 1'b0;
`else
tri0 glblGSR = glbl.GSR;
`endif
wire CLK_DAC_SPARE_out;
wire CLK_DAC_out;
wire CLK_DIST_OUT_NORTH_out;
wire CLK_DIST_OUT_SOUTH_out;
wire DRDY_out;
wire PLL_DMON_OUT_out;
wire PLL_REFCLK_OUT_out;
wire SYSREF_OUT_NORTH_out;
wire SYSREF_OUT_SOUTH_out;
wire T1_ALLOWED_SOUTH_out;
wire VOUT0_N_out;
wire VOUT0_P_out;
wire VOUT1_N_out;
wire VOUT1_P_out;
wire VOUT2_N_out;
wire VOUT2_P_out;
wire VOUT3_N_out;
wire VOUT3_P_out;
wire [15:0] DOUT_out;
wire [15:0] TEST_STATUS_out;
wire [1:0] PLL_SCAN_OUT_B_FD_out;
wire [23:0] STATUS_COMMON_out;
wire [23:0] STATUS_DAC0_out;
wire [23:0] STATUS_DAC1_out;
wire [23:0] STATUS_DAC2_out;
wire [23:0] STATUS_DAC3_out;
wire [299:0] TEST_SO_out;
wire CLK_DIST_IN_NORTH_in;
wire CLK_DIST_IN_SOUTH_in;
wire CLK_FIFO_LM_in;
wire DAC_CLK_N_in;
wire DAC_CLK_P_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire FABRIC_CLK_in;
wire PLL_MONCLK_in;
wire PLL_REFCLK_IN_in;
wire PLL_SCAN_EN_B_FD_in;
wire PLL_SCAN_MODE_B_FD_in;
wire PLL_SCAN_RST_EN_FD_in;
wire SYSREF_IN_NORTH_in;
wire SYSREF_IN_SOUTH_in;
wire SYSREF_N_in;
wire SYSREF_P_in;
wire T1_ALLOWED_NORTH_in;
wire TEST_SCAN_MODE_B_in;
wire TEST_SCAN_RESET_in;
wire TEST_SE_B_in;
wire [11:0] DADDR_in;
wire [15:0] CONTROL_COMMON_in;
wire [15:0] CONTROL_DAC0_in;
wire [15:0] CONTROL_DAC1_in;
wire [15:0] CONTROL_DAC2_in;
wire [15:0] CONTROL_DAC3_in;
wire [15:0] DI_in;
wire [15:0] TEST_SCAN_CTRL_in;
wire [1:0] PLL_SCAN_CLK_FD_in;
wire [1:0] PLL_SCAN_IN_FD_in;
wire [255:0] DATA_DAC0_in;
wire [255:0] DATA_DAC1_in;
wire [255:0] DATA_DAC2_in;
wire [255:0] DATA_DAC3_in;
wire [299:0] TEST_SI_in;
wire [4:0] TEST_SCAN_CLK_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire FABRIC_CLK_delay;
wire [11:0] DADDR_delay;
wire [15:0] CONTROL_COMMON_delay;
wire [15:0] CONTROL_DAC0_delay;
wire [15:0] CONTROL_DAC1_delay;
wire [15:0] CONTROL_DAC2_delay;
wire [15:0] CONTROL_DAC3_delay;
wire [15:0] DI_delay;
wire [255:0] DATA_DAC0_delay;
wire [255:0] DATA_DAC1_delay;
wire [255:0] DATA_DAC2_delay;
wire [255:0] DATA_DAC3_delay;
`endif
real VOUT0_N_real;
real VOUT0_P_real;
real VOUT1_N_real;
real VOUT1_P_real;
real VOUT2_N_real;
real VOUT2_P_real;
real VOUT3_N_real;
real VOUT3_P_real;
assign CLK_DAC = CLK_DAC_out;
assign CLK_DIST_OUT_NORTH = CLK_DIST_OUT_NORTH_out;
assign CLK_DIST_OUT_SOUTH = CLK_DIST_OUT_SOUTH_out;
assign DOUT = DOUT_out;
assign DRDY = DRDY_out;
assign PLL_DMON_OUT = PLL_DMON_OUT_out;
assign PLL_REFCLK_OUT = PLL_REFCLK_OUT_out;
assign STATUS_COMMON = STATUS_COMMON_out;
assign STATUS_DAC0 = STATUS_DAC0_out;
assign STATUS_DAC1 = STATUS_DAC1_out;
assign STATUS_DAC2 = STATUS_DAC2_out;
assign STATUS_DAC3 = STATUS_DAC3_out;
assign SYSREF_OUT_NORTH = SYSREF_OUT_NORTH_out;
assign SYSREF_OUT_SOUTH = SYSREF_OUT_SOUTH_out;
assign T1_ALLOWED_SOUTH = T1_ALLOWED_SOUTH_out;
assign VOUT0_N = VOUT0_N_out;
assign VOUT0_P = VOUT0_P_out;
assign VOUT1_N = VOUT1_N_out;
assign VOUT1_P = VOUT1_P_out;
assign VOUT2_N = VOUT2_N_out;
assign VOUT2_P = VOUT2_P_out;
assign VOUT3_N = VOUT3_N_out;
assign VOUT3_P = VOUT3_P_out;
`ifdef XIL_TIMING
assign CONTROL_COMMON_in = CONTROL_COMMON_delay;
assign CONTROL_DAC0_in = CONTROL_DAC0_delay;
assign CONTROL_DAC1_in = CONTROL_DAC1_delay;
assign CONTROL_DAC2_in = CONTROL_DAC2_delay;
assign CONTROL_DAC3_in = CONTROL_DAC3_delay;
assign DADDR_in = DADDR_delay;
assign DATA_DAC0_in = DATA_DAC0_delay;
assign DATA_DAC1_in = DATA_DAC1_delay;
assign DATA_DAC2_in = DATA_DAC2_delay;
assign DATA_DAC3_in = DATA_DAC3_delay;
assign DCLK_in = DCLK_delay;
assign DEN_in = DEN_delay;
assign DI_in = DI_delay;
assign DWE_in = DWE_delay;
assign FABRIC_CLK_in = FABRIC_CLK_delay;
`else
assign CONTROL_COMMON_in = CONTROL_COMMON;
assign CONTROL_DAC0_in = CONTROL_DAC0;
assign CONTROL_DAC1_in = CONTROL_DAC1;
assign CONTROL_DAC2_in = CONTROL_DAC2;
assign CONTROL_DAC3_in = CONTROL_DAC3;
assign DADDR_in = DADDR;
assign DATA_DAC0_in = DATA_DAC0;
assign DATA_DAC1_in = DATA_DAC1;
assign DATA_DAC2_in = DATA_DAC2;
assign DATA_DAC3_in = DATA_DAC3;
assign DCLK_in = DCLK;
assign DEN_in = DEN;
assign DI_in = DI;
assign DWE_in = DWE;
assign FABRIC_CLK_in = FABRIC_CLK;
`endif
assign CLK_DIST_IN_NORTH_in = CLK_DIST_IN_NORTH;
assign CLK_DIST_IN_SOUTH_in = CLK_DIST_IN_SOUTH;
assign CLK_FIFO_LM_in = CLK_FIFO_LM;
assign DAC_CLK_N_in = DAC_CLK_N;
assign DAC_CLK_P_in = DAC_CLK_P;
assign PLL_MONCLK_in = PLL_MONCLK;
assign PLL_REFCLK_IN_in = PLL_REFCLK_IN;
assign SYSREF_IN_NORTH_in = SYSREF_IN_NORTH;
assign SYSREF_IN_SOUTH_in = SYSREF_IN_SOUTH;
assign SYSREF_N_in = SYSREF_N;
assign SYSREF_P_in = SYSREF_P;
assign T1_ALLOWED_NORTH_in = T1_ALLOWED_NORTH;
`ifndef XIL_XECLIB
reg attr_test;
reg attr_err;
initial begin
trig_attr = 1'b0;
`ifdef XIL_ATTR_TEST
attr_test = 1'b1;
`else
attr_test = 1'b0;
`endif
attr_err = 1'b0;
#1;
trig_attr = ~trig_attr;
end
`endif
`ifndef XIL_XECLIB
always @ (trig_attr) begin
#1;
if ((attr_test == 1'b1) ||
((OPT_CLK_DIST_REG < 0) || (OPT_CLK_DIST_REG > 65535))) begin
$display("Error: [Unisim %s-101] OPT_CLK_DIST attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, OPT_CLK_DIST_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SIM_DEVICE_REG != "ULTRASCALE_PLUS") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE_REG != "ULTRASCALE_PLUS_ES2"))) begin
$display("Error: [Unisim %s-102] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1 or ULTRASCALE_PLUS_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_ACTIVE_DUTYCYCLE_REG < 0) || (XPA_ACTIVE_DUTYCYCLE_REG > 100))) begin
$display("Error: [Unisim %s-103] XPA_ACTIVE_DUTYCYCLE attribute is set to %d. Legal values for this attribute are 0 to 100. Instance: %m", MODULE_NAME, XPA_ACTIVE_DUTYCYCLE_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_CFG0_REG < 0) || (XPA_CFG0_REG > 65535))) begin
$display("Error: [Unisim %s-104] XPA_CFG0 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG0_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_CFG1_REG < 0) || (XPA_CFG1_REG > 65535))) begin
$display("Error: [Unisim %s-105] XPA_CFG1 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG1_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_CFG2_REG < 0) || (XPA_CFG2_REG > 65535))) begin
$display("Error: [Unisim %s-106] XPA_CFG2 attribute is set to %d. Legal values for this attribute are 0 to 65535. Instance: %m", MODULE_NAME, XPA_CFG2_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_NUM_DACS_REG < 0) || (XPA_NUM_DACS_REG > 4))) begin
$display("Error: [Unisim %s-107] XPA_NUM_DACS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DACS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_NUM_DUCS_REG < 0) || (XPA_NUM_DUCS_REG > 4))) begin
$display("Error: [Unisim %s-108] XPA_NUM_DUCS attribute is set to %d. Legal values for this attribute are 0 to 4. Instance: %m", MODULE_NAME, XPA_NUM_DUCS_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_PLL_USED_REG != "EXTERNAL") &&
(XPA_PLL_USED_REG != "DISTRIBUTED_T1") &&
(XPA_PLL_USED_REG != "INTERNAL_PLL"))) begin
$display("Error: [Unisim %s-109] XPA_PLL_USED attribute is set to %s. Legal values for this attribute are EXTERNAL, DISTRIBUTED_T1 or INTERNAL_PLL. Instance: %m", MODULE_NAME, XPA_PLL_USED_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((XPA_SAMPLE_RATE_MSPS_REG < 0) || (XPA_SAMPLE_RATE_MSPS_REG > 10000))) begin
$display("Error: [Unisim %s-110] XPA_SAMPLE_RATE_MSPS attribute is set to %d. Legal values for this attribute are 0 to 10000. Instance: %m", MODULE_NAME, XPA_SAMPLE_RATE_MSPS_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1) #1 $finish;
end
`endif
assign PLL_SCAN_CLK_FD_in = 2'b11; // tie off
assign TEST_SCAN_CLK_in = 5'b11111; // tie off
assign PLL_SCAN_EN_B_FD_in = 1'b1; // tie off
assign PLL_SCAN_IN_FD_in = 2'b11; // tie off
assign PLL_SCAN_MODE_B_FD_in = 1'b1; // tie off
assign PLL_SCAN_RST_EN_FD_in = 1'b1; // tie off
assign TEST_SCAN_CTRL_in = 16'b1111111111111111; // tie off
assign TEST_SCAN_MODE_B_in = 1'b1; // tie off
assign TEST_SCAN_RESET_in = 1'b1; // tie off
assign TEST_SE_B_in = 1'b1; // tie off
assign TEST_SI_in = 300'b111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111111; // tie off
SIP_RFDAC SIP_RFDAC_INST (
.OPT_CLK_DIST (OPT_CLK_DIST_REG),
.SIM_DEVICE (SIM_DEVICE_REG),
.XPA_ACTIVE_DUTYCYCLE (XPA_ACTIVE_DUTYCYCLE_REG),
.XPA_CFG0 (XPA_CFG0_REG),
.XPA_CFG1 (XPA_CFG1_REG),
.XPA_CFG2 (XPA_CFG2_REG),
.XPA_NUM_DACS (XPA_NUM_DACS_REG),
.XPA_NUM_DUCS (XPA_NUM_DUCS_REG),
.XPA_PLL_USED (XPA_PLL_USED_REG),
.XPA_SAMPLE_RATE_MSPS (XPA_SAMPLE_RATE_MSPS_REG),
.CLK_DAC (CLK_DAC_out),
.CLK_DAC_SPARE (CLK_DAC_SPARE_out),
.CLK_DIST_OUT_NORTH (CLK_DIST_OUT_NORTH_out),
.CLK_DIST_OUT_SOUTH (CLK_DIST_OUT_SOUTH_out),
.DOUT (DOUT_out),
.DRDY (DRDY_out),
.PLL_DMON_OUT (PLL_DMON_OUT_out),
.PLL_REFCLK_OUT (PLL_REFCLK_OUT_out),
.PLL_SCAN_OUT_B_FD (PLL_SCAN_OUT_B_FD_out),
.STATUS_COMMON (STATUS_COMMON_out),
.STATUS_DAC0 (STATUS_DAC0_out),
.STATUS_DAC1 (STATUS_DAC1_out),
.STATUS_DAC2 (STATUS_DAC2_out),
.STATUS_DAC3 (STATUS_DAC3_out),
.SYSREF_OUT_NORTH (SYSREF_OUT_NORTH_out),
.SYSREF_OUT_SOUTH (SYSREF_OUT_SOUTH_out),
.T1_ALLOWED_SOUTH (T1_ALLOWED_SOUTH_out),
.TEST_SO (TEST_SO_out),
.TEST_STATUS (TEST_STATUS_out),
.VOUT0_N (VOUT0_N_real),
.VOUT0_P (VOUT0_P_real),
.VOUT1_N (VOUT1_N_real),
.VOUT1_P (VOUT1_P_real),
.VOUT2_N (VOUT2_N_real),
.VOUT2_P (VOUT2_P_real),
.VOUT3_N (VOUT3_N_real),
.VOUT3_P (VOUT3_P_real),
.CLK_DIST_IN_NORTH (CLK_DIST_IN_NORTH_in),
.CLK_DIST_IN_SOUTH (CLK_DIST_IN_SOUTH_in),
.CLK_FIFO_LM (CLK_FIFO_LM_in),
.CONTROL_COMMON (CONTROL_COMMON_in),
.CONTROL_DAC0 (CONTROL_DAC0_in),
.CONTROL_DAC1 (CONTROL_DAC1_in),
.CONTROL_DAC2 (CONTROL_DAC2_in),
.CONTROL_DAC3 (CONTROL_DAC3_in),
.DAC_CLK_N (DAC_CLK_N_in),
.DAC_CLK_P (DAC_CLK_P_in),
.DADDR (DADDR_in),
.DATA_DAC0 (DATA_DAC0_in),
.DATA_DAC1 (DATA_DAC1_in),
.DATA_DAC2 (DATA_DAC2_in),
.DATA_DAC3 (DATA_DAC3_in),
.DCLK (DCLK_in),
.DEN (DEN_in),
.DI (DI_in),
.DWE (DWE_in),
.FABRIC_CLK (FABRIC_CLK_in),
.PLL_MONCLK (PLL_MONCLK_in),
.PLL_REFCLK_IN (PLL_REFCLK_IN_in),
.PLL_SCAN_CLK_FD (PLL_SCAN_CLK_FD_in),
.PLL_SCAN_EN_B_FD (PLL_SCAN_EN_B_FD_in),
.PLL_SCAN_IN_FD (PLL_SCAN_IN_FD_in),
.PLL_SCAN_MODE_B_FD (PLL_SCAN_MODE_B_FD_in),
.PLL_SCAN_RST_EN_FD (PLL_SCAN_RST_EN_FD_in),
.SYSREF_IN_NORTH (SYSREF_IN_NORTH_in),
.SYSREF_IN_SOUTH (SYSREF_IN_SOUTH_in),
.SYSREF_N (SYSREF_N_in),
.SYSREF_P (SYSREF_P_in),
.T1_ALLOWED_NORTH (T1_ALLOWED_NORTH_in),
.TEST_SCAN_CLK (TEST_SCAN_CLK_in),
.TEST_SCAN_CTRL (TEST_SCAN_CTRL_in),
.TEST_SCAN_MODE_B (TEST_SCAN_MODE_B_in),
.TEST_SCAN_RESET (TEST_SCAN_RESET_in),
.TEST_SE_B (TEST_SE_B_in),
.TEST_SI (TEST_SI_in),
.GSR (glblGSR)
);
`ifdef XIL_TIMING
reg notifier;
`endif
`ifndef XIL_XECLIB
specify
(DCLK => DOUT[0]) = (100:100:100, 100:100:100);
(DCLK => DOUT[10]) = (100:100:100, 100:100:100);
(DCLK => DOUT[11]) = (100:100:100, 100:100:100);
(DCLK => DOUT[12]) = (100:100:100, 100:100:100);
(DCLK => DOUT[13]) = (100:100:100, 100:100:100);
(DCLK => DOUT[14]) = (100:100:100, 100:100:100);
(DCLK => DOUT[15]) = (100:100:100, 100:100:100);
(DCLK => DOUT[1]) = (100:100:100, 100:100:100);
(DCLK => DOUT[2]) = (100:100:100, 100:100:100);
(DCLK => DOUT[3]) = (100:100:100, 100:100:100);
(DCLK => DOUT[4]) = (100:100:100, 100:100:100);
(DCLK => DOUT[5]) = (100:100:100, 100:100:100);
(DCLK => DOUT[6]) = (100:100:100, 100:100:100);
(DCLK => DOUT[7]) = (100:100:100, 100:100:100);
(DCLK => DOUT[8]) = (100:100:100, 100:100:100);
(DCLK => DOUT[9]) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => STATUS_COMMON[6]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC0[10]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC0[11]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC0[12]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC0[8]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC0[9]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC1[10]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC1[11]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC1[12]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC1[8]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC1[9]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC2[10]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC2[11]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC2[12]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC2[8]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC2[9]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC3[10]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC3[11]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC3[12]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC3[8]) = (100:100:100, 100:100:100);
(FABRIC_CLK => STATUS_DAC3[9]) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CLK_DAC, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (negedge FABRIC_CLK, 0:0:0, notifier);
$period (negedge PLL_DMON_OUT, 0:0:0, notifier);
$period (negedge PLL_MONCLK, 0:0:0, notifier);
$period (negedge PLL_REFCLK_IN, 0:0:0, notifier);
$period (negedge PLL_REFCLK_OUT, 0:0:0, notifier);
$period (posedge CLK_DAC, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$period (posedge FABRIC_CLK, 0:0:0, notifier);
$period (posedge PLL_DMON_OUT, 0:0:0, notifier);
$period (posedge PLL_MONCLK, 0:0:0, notifier);
$period (posedge PLL_REFCLK_IN, 0:0:0, notifier);
$period (posedge PLL_REFCLK_OUT, 0:0:0, notifier);
$setuphold (posedge DCLK, negedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]);
$setuphold (posedge DCLK, negedge CONTROL_DAC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[13]);
$setuphold (posedge DCLK, negedge CONTROL_DAC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[14]);
$setuphold (posedge DCLK, negedge CONTROL_DAC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[13]);
$setuphold (posedge DCLK, negedge CONTROL_DAC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[14]);
$setuphold (posedge DCLK, negedge CONTROL_DAC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[13]);
$setuphold (posedge DCLK, negedge CONTROL_DAC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[14]);
$setuphold (posedge DCLK, negedge CONTROL_DAC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[13]);
$setuphold (posedge DCLK, negedge CONTROL_DAC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[14]);
$setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, negedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]);
$setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, negedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]);
$setuphold (posedge DCLK, negedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge CONTROL_COMMON[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_COMMON_delay[3]);
$setuphold (posedge DCLK, posedge CONTROL_DAC0[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[13]);
$setuphold (posedge DCLK, posedge CONTROL_DAC0[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC0_delay[14]);
$setuphold (posedge DCLK, posedge CONTROL_DAC1[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[13]);
$setuphold (posedge DCLK, posedge CONTROL_DAC1[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC1_delay[14]);
$setuphold (posedge DCLK, posedge CONTROL_DAC2[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[13]);
$setuphold (posedge DCLK, posedge CONTROL_DAC2[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC2_delay[14]);
$setuphold (posedge DCLK, posedge CONTROL_DAC3[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[13]);
$setuphold (posedge DCLK, posedge CONTROL_DAC3[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, CONTROL_DAC3_delay[14]);
$setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, posedge DADDR[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[10]);
$setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, posedge DADDR[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[8]);
$setuphold (posedge DCLK, posedge DADDR[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DADDR_delay[9]);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier, , , DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier, , , DCLK_delay, DWE_delay);
$setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[0]);
$setuphold (posedge FABRIC_CLK, negedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[0]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[100]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[101]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[102]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[103]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[104]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[105]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[106]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[107]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[108]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[109]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[10]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[110]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[111]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[112]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[113]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[114]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[115]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[116]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[117]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[118]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[119]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[11]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[120]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[121]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[122]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[123]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[124]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[125]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[126]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[127]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[128]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[129]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[12]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[130]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[131]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[132]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[133]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[134]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[135]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[136]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[137]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[138]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[139]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[13]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[140]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[141]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[142]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[143]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[144]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[145]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[146]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[147]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[148]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[149]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[14]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[150]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[151]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[152]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[153]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[154]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[155]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[156]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[157]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[158]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[159]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[15]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[160]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[161]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[162]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[163]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[164]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[165]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[166]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[167]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[168]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[169]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[16]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[170]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[171]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[172]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[173]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[174]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[175]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[176]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[177]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[178]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[179]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[17]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[180]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[181]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[182]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[183]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[184]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[185]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[186]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[187]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[188]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[189]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[18]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[190]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[191]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[192]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[193]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[194]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[195]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[196]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[197]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[198]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[199]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[19]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[1]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[200]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[201]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[202]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[203]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[204]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[205]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[206]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[207]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[208]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[209]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[20]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[210]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[211]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[212]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[213]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[214]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[215]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[216]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[217]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[218]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[219]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[21]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[220]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[221]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[222]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[223]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[224]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[225]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[226]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[227]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[228]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[229]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[22]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[230]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[231]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[232]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[233]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[234]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[235]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[236]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[237]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[238]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[239]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[23]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[240]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[241]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[242]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[243]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[244]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[245]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[246]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[247]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[248]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[249]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[24]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[250]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[251]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[252]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[253]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[254]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[255]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[25]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[26]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[27]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[28]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[29]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[2]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[30]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[31]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[32]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[33]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[34]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[35]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[36]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[37]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[38]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[39]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[3]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[40]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[41]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[42]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[43]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[44]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[45]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[46]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[47]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[48]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[49]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[4]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[50]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[51]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[52]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[53]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[54]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[55]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[56]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[57]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[58]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[59]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[5]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[60]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[61]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[62]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[63]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[64]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[65]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[66]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[67]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[68]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[69]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[6]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[70]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[71]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[72]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[73]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[74]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[75]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[76]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[77]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[78]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[79]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[7]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[80]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[81]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[82]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[83]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[84]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[85]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[86]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[87]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[88]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[89]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[8]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[90]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[91]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[92]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[93]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[94]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[95]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[96]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[97]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[98]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[99]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC0[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[9]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[0]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[100]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[101]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[102]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[103]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[104]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[105]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[106]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[107]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[108]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[109]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[10]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[110]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[111]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[112]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[113]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[114]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[115]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[116]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[117]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[118]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[119]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[11]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[120]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[121]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[122]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[123]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[124]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[125]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[126]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[127]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[128]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[129]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[12]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[130]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[131]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[132]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[133]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[134]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[135]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[136]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[137]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[138]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[139]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[13]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[140]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[141]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[142]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[143]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[144]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[145]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[146]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[147]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[148]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[149]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[14]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[150]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[151]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[152]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[153]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[154]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[155]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[156]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[157]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[158]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[159]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[15]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[160]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[161]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[162]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[163]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[164]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[165]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[166]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[167]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[168]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[169]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[16]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[170]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[171]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[172]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[173]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[174]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[175]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[176]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[177]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[178]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[179]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[17]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[180]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[181]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[182]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[183]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[184]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[185]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[186]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[187]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[188]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[189]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[18]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[190]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[191]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[192]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[193]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[194]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[195]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[196]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[197]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[198]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[199]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[19]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[1]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[200]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[201]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[202]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[203]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[204]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[205]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[206]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[207]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[208]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[209]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[20]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[210]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[211]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[212]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[213]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[214]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[215]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[216]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[217]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[218]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[219]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[21]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[220]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[221]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[222]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[223]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[224]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[225]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[226]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[227]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[228]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[229]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[22]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[230]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[231]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[232]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[233]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[234]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[235]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[236]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[237]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[238]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[239]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[23]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[240]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[241]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[242]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[243]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[244]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[245]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[246]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[247]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[248]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[249]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[24]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[250]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[251]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[252]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[253]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[254]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[255]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[25]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[26]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[27]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[28]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[29]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[2]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[30]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[31]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[32]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[33]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[34]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[35]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[36]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[37]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[38]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[39]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[3]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[40]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[41]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[42]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[43]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[44]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[45]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[46]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[47]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[48]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[49]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[4]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[50]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[51]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[52]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[53]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[54]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[55]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[56]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[57]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[58]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[59]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[5]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[60]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[61]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[62]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[63]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[64]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[65]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[66]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[67]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[68]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[69]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[6]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[70]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[71]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[72]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[73]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[74]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[75]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[76]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[77]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[78]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[79]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[7]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[80]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[81]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[82]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[83]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[84]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[85]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[86]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[87]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[88]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[89]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[8]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[90]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[91]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[92]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[93]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[94]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[95]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[96]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[97]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[98]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[99]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC1[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[9]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[0]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[100]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[101]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[102]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[103]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[104]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[105]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[106]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[107]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[108]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[109]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[10]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[110]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[111]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[112]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[113]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[114]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[115]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[116]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[117]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[118]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[119]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[11]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[120]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[121]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[122]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[123]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[124]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[125]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[126]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[127]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[128]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[129]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[12]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[130]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[131]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[132]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[133]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[134]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[135]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[136]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[137]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[138]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[139]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[13]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[140]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[141]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[142]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[143]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[144]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[145]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[146]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[147]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[148]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[149]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[14]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[150]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[151]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[152]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[153]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[154]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[155]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[156]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[157]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[158]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[159]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[15]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[160]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[161]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[162]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[163]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[164]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[165]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[166]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[167]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[168]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[169]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[16]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[170]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[171]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[172]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[173]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[174]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[175]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[176]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[177]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[178]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[179]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[17]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[180]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[181]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[182]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[183]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[184]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[185]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[186]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[187]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[188]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[189]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[18]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[190]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[191]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[192]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[193]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[194]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[195]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[196]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[197]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[198]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[199]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[19]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[1]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[200]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[201]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[202]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[203]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[204]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[205]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[206]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[207]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[208]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[209]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[20]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[210]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[211]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[212]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[213]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[214]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[215]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[216]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[217]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[218]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[219]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[21]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[220]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[221]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[222]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[223]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[224]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[225]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[226]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[227]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[228]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[229]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[22]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[230]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[231]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[232]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[233]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[234]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[235]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[236]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[237]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[238]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[239]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[23]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[240]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[241]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[242]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[243]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[244]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[245]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[246]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[247]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[248]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[249]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[24]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[250]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[251]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[252]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[253]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[254]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[255]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[25]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[26]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[27]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[28]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[29]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[2]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[30]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[31]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[32]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[33]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[34]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[35]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[36]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[37]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[38]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[39]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[3]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[40]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[41]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[42]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[43]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[44]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[45]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[46]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[47]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[48]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[49]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[4]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[50]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[51]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[52]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[53]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[54]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[55]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[56]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[57]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[58]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[59]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[5]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[60]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[61]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[62]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[63]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[64]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[65]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[66]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[67]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[68]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[69]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[6]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[70]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[71]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[72]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[73]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[74]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[75]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[76]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[77]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[78]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[79]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[7]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[80]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[81]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[82]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[83]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[84]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[85]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[86]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[87]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[88]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[89]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[8]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[90]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[91]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[92]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[93]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[94]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[95]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[96]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[97]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[98]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[99]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC2[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[9]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[0]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[100]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[101]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[102]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[103]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[104]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[105]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[106]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[107]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[108]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[109]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[10]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[110]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[111]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[112]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[113]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[114]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[115]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[116]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[117]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[118]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[119]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[11]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[120]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[121]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[122]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[123]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[124]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[125]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[126]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[127]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[128]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[129]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[12]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[130]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[131]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[132]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[133]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[134]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[135]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[136]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[137]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[138]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[139]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[13]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[140]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[141]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[142]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[143]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[144]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[145]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[146]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[147]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[148]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[149]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[14]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[150]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[151]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[152]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[153]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[154]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[155]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[156]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[157]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[158]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[159]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[15]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[160]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[161]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[162]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[163]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[164]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[165]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[166]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[167]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[168]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[169]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[16]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[170]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[171]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[172]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[173]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[174]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[175]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[176]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[177]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[178]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[179]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[17]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[180]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[181]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[182]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[183]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[184]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[185]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[186]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[187]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[188]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[189]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[18]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[190]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[191]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[192]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[193]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[194]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[195]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[196]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[197]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[198]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[199]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[19]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[1]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[200]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[201]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[202]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[203]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[204]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[205]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[206]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[207]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[208]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[209]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[20]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[210]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[211]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[212]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[213]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[214]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[215]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[216]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[217]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[218]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[219]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[21]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[220]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[221]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[222]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[223]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[224]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[225]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[226]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[227]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[228]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[229]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[22]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[230]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[231]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[232]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[233]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[234]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[235]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[236]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[237]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[238]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[239]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[23]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[240]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[241]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[242]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[243]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[244]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[245]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[246]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[247]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[248]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[249]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[24]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[250]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[251]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[252]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[253]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[254]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[255]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[25]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[26]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[27]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[28]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[29]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[2]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[30]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[31]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[32]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[33]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[34]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[35]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[36]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[37]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[38]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[39]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[3]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[40]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[41]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[42]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[43]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[44]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[45]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[46]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[47]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[48]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[49]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[4]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[50]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[51]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[52]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[53]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[54]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[55]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[56]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[57]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[58]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[59]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[5]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[60]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[61]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[62]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[63]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[64]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[65]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[66]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[67]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[68]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[69]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[6]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[70]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[71]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[72]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[73]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[74]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[75]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[76]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[77]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[78]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[79]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[7]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[80]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[81]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[82]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[83]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[84]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[85]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[86]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[87]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[88]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[89]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[8]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[90]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[91]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[92]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[93]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[94]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[95]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[96]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[97]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[98]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[99]);
$setuphold (posedge FABRIC_CLK, negedge DATA_DAC3[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[9]);
$setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[0]);
$setuphold (posedge FABRIC_CLK, posedge CONTROL_COMMON[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, CONTROL_COMMON_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[0]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[100]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[101]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[102]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[103]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[104]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[105]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[106]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[107]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[108]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[109]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[10]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[110]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[111]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[112]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[113]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[114]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[115]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[116]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[117]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[118]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[119]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[11]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[120]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[121]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[122]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[123]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[124]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[125]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[126]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[127]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[128]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[129]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[12]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[130]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[131]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[132]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[133]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[134]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[135]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[136]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[137]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[138]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[139]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[13]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[140]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[141]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[142]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[143]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[144]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[145]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[146]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[147]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[148]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[149]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[14]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[150]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[151]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[152]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[153]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[154]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[155]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[156]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[157]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[158]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[159]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[160]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[161]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[162]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[163]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[164]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[165]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[166]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[167]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[168]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[169]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[16]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[170]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[171]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[172]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[173]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[174]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[175]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[176]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[177]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[178]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[179]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[17]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[180]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[181]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[182]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[183]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[184]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[185]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[186]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[187]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[188]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[189]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[18]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[190]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[191]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[192]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[193]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[194]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[195]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[196]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[197]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[198]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[199]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[19]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[1]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[200]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[201]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[202]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[203]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[204]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[205]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[206]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[207]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[208]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[209]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[20]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[210]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[211]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[212]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[213]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[214]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[215]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[216]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[217]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[218]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[219]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[21]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[220]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[221]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[222]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[223]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[224]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[225]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[226]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[227]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[228]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[229]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[22]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[230]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[231]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[232]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[233]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[234]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[235]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[236]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[237]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[238]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[239]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[23]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[240]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[241]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[242]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[243]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[244]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[245]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[246]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[247]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[248]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[249]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[24]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[250]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[251]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[252]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[253]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[254]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[255]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[25]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[26]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[27]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[28]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[29]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[2]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[30]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[31]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[32]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[33]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[34]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[35]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[36]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[37]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[38]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[39]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[3]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[40]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[41]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[42]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[43]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[44]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[45]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[46]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[47]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[48]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[49]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[4]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[50]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[51]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[52]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[53]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[54]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[55]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[56]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[57]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[58]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[59]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[5]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[60]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[61]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[62]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[63]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[64]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[65]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[66]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[67]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[68]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[69]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[6]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[70]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[71]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[72]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[73]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[74]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[75]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[76]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[77]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[78]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[79]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[7]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[80]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[81]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[82]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[83]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[84]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[85]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[86]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[87]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[88]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[89]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[8]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[90]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[91]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[92]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[93]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[94]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[95]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[96]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[97]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[98]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[99]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC0[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC0_delay[9]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[0]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[100]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[101]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[102]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[103]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[104]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[105]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[106]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[107]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[108]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[109]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[10]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[110]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[111]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[112]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[113]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[114]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[115]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[116]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[117]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[118]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[119]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[11]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[120]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[121]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[122]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[123]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[124]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[125]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[126]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[127]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[128]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[129]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[12]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[130]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[131]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[132]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[133]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[134]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[135]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[136]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[137]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[138]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[139]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[13]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[140]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[141]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[142]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[143]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[144]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[145]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[146]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[147]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[148]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[149]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[14]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[150]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[151]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[152]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[153]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[154]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[155]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[156]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[157]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[158]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[159]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[160]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[161]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[162]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[163]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[164]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[165]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[166]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[167]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[168]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[169]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[16]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[170]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[171]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[172]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[173]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[174]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[175]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[176]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[177]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[178]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[179]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[17]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[180]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[181]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[182]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[183]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[184]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[185]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[186]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[187]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[188]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[189]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[18]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[190]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[191]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[192]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[193]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[194]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[195]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[196]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[197]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[198]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[199]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[19]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[1]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[200]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[201]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[202]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[203]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[204]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[205]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[206]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[207]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[208]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[209]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[20]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[210]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[211]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[212]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[213]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[214]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[215]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[216]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[217]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[218]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[219]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[21]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[220]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[221]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[222]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[223]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[224]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[225]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[226]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[227]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[228]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[229]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[22]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[230]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[231]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[232]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[233]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[234]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[235]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[236]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[237]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[238]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[239]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[23]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[240]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[241]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[242]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[243]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[244]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[245]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[246]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[247]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[248]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[249]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[24]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[250]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[251]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[252]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[253]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[254]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[255]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[25]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[26]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[27]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[28]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[29]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[2]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[30]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[31]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[32]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[33]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[34]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[35]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[36]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[37]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[38]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[39]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[3]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[40]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[41]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[42]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[43]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[44]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[45]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[46]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[47]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[48]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[49]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[4]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[50]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[51]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[52]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[53]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[54]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[55]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[56]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[57]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[58]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[59]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[5]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[60]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[61]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[62]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[63]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[64]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[65]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[66]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[67]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[68]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[69]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[6]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[70]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[71]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[72]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[73]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[74]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[75]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[76]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[77]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[78]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[79]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[7]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[80]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[81]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[82]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[83]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[84]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[85]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[86]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[87]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[88]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[89]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[8]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[90]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[91]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[92]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[93]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[94]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[95]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[96]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[97]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[98]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[99]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC1[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC1_delay[9]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[0]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[100]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[101]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[102]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[103]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[104]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[105]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[106]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[107]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[108]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[109]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[10]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[110]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[111]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[112]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[113]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[114]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[115]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[116]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[117]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[118]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[119]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[11]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[120]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[121]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[122]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[123]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[124]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[125]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[126]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[127]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[128]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[129]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[12]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[130]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[131]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[132]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[133]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[134]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[135]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[136]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[137]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[138]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[139]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[13]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[140]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[141]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[142]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[143]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[144]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[145]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[146]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[147]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[148]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[149]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[14]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[150]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[151]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[152]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[153]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[154]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[155]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[156]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[157]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[158]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[159]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[160]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[161]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[162]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[163]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[164]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[165]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[166]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[167]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[168]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[169]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[16]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[170]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[171]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[172]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[173]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[174]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[175]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[176]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[177]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[178]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[179]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[17]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[180]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[181]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[182]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[183]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[184]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[185]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[186]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[187]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[188]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[189]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[18]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[190]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[191]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[192]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[193]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[194]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[195]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[196]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[197]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[198]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[199]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[19]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[1]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[200]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[201]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[202]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[203]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[204]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[205]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[206]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[207]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[208]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[209]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[20]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[210]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[211]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[212]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[213]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[214]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[215]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[216]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[217]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[218]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[219]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[21]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[220]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[221]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[222]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[223]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[224]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[225]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[226]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[227]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[228]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[229]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[22]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[230]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[231]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[232]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[233]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[234]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[235]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[236]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[237]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[238]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[239]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[23]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[240]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[241]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[242]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[243]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[244]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[245]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[246]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[247]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[248]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[249]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[24]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[250]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[251]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[252]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[253]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[254]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[255]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[25]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[26]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[27]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[28]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[29]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[2]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[30]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[31]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[32]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[33]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[34]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[35]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[36]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[37]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[38]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[39]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[3]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[40]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[41]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[42]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[43]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[44]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[45]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[46]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[47]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[48]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[49]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[4]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[50]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[51]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[52]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[53]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[54]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[55]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[56]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[57]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[58]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[59]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[5]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[60]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[61]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[62]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[63]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[64]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[65]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[66]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[67]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[68]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[69]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[6]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[70]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[71]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[72]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[73]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[74]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[75]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[76]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[77]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[78]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[79]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[7]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[80]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[81]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[82]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[83]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[84]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[85]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[86]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[87]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[88]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[89]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[8]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[90]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[91]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[92]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[93]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[94]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[95]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[96]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[97]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[98]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[99]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC2[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC2_delay[9]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[0], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[0]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[100], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[100]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[101], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[101]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[102], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[102]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[103], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[103]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[104], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[104]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[105], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[105]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[106], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[106]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[107], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[107]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[108], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[108]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[109], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[109]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[10], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[10]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[110], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[110]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[111], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[111]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[112], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[112]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[113], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[113]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[114], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[114]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[115], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[115]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[116], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[116]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[117], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[117]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[118], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[118]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[119], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[119]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[11], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[11]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[120], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[120]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[121], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[121]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[122], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[122]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[123], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[123]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[124], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[124]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[125], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[125]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[126], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[126]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[127], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[127]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[128], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[128]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[129], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[129]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[12], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[12]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[130], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[130]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[131], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[131]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[132], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[132]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[133], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[133]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[134], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[134]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[135], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[135]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[136], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[136]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[137], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[137]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[138], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[138]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[139], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[139]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[13], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[13]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[140], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[140]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[141], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[141]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[142], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[142]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[143], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[143]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[144], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[144]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[145], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[145]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[146], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[146]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[147], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[147]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[148], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[148]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[149], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[149]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[14], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[14]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[150], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[150]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[151], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[151]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[152], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[152]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[153], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[153]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[154], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[154]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[155], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[155]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[156], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[156]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[157], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[157]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[158], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[158]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[159], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[159]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[15], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[15]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[160], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[160]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[161], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[161]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[162], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[162]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[163], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[163]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[164], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[164]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[165], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[165]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[166], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[166]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[167], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[167]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[168], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[168]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[169], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[169]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[16], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[16]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[170], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[170]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[171], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[171]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[172], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[172]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[173], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[173]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[174], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[174]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[175], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[175]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[176], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[176]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[177], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[177]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[178], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[178]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[179], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[179]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[17], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[17]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[180], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[180]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[181], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[181]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[182], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[182]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[183], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[183]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[184], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[184]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[185], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[185]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[186], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[186]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[187], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[187]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[188], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[188]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[189], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[189]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[18], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[18]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[190], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[190]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[191], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[191]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[192], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[192]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[193], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[193]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[194], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[194]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[195], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[195]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[196], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[196]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[197], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[197]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[198], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[198]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[199], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[199]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[19], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[19]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[1], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[1]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[200], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[200]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[201], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[201]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[202], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[202]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[203], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[203]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[204], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[204]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[205], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[205]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[206], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[206]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[207], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[207]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[208], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[208]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[209], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[209]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[20], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[20]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[210], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[210]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[211], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[211]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[212], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[212]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[213], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[213]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[214], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[214]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[215], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[215]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[216], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[216]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[217], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[217]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[218], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[218]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[219], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[219]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[21], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[21]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[220], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[220]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[221], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[221]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[222], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[222]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[223], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[223]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[224], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[224]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[225], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[225]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[226], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[226]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[227], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[227]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[228], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[228]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[229], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[229]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[22], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[22]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[230], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[230]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[231], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[231]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[232], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[232]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[233], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[233]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[234], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[234]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[235], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[235]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[236], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[236]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[237], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[237]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[238], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[238]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[239], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[239]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[23], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[23]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[240], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[240]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[241], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[241]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[242], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[242]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[243], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[243]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[244], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[244]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[245], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[245]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[246], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[246]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[247], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[247]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[248], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[248]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[249], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[249]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[24], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[24]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[250], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[250]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[251], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[251]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[252], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[252]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[253], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[253]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[254], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[254]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[255], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[255]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[25], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[25]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[26], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[26]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[27], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[27]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[28], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[28]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[29], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[29]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[2], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[2]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[30], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[30]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[31], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[31]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[32], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[32]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[33], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[33]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[34], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[34]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[35], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[35]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[36], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[36]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[37], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[37]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[38], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[38]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[39], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[39]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[3], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[3]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[40], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[40]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[41], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[41]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[42], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[42]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[43], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[43]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[44], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[44]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[45], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[45]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[46], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[46]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[47], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[47]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[48], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[48]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[49], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[49]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[4], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[4]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[50], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[50]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[51], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[51]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[52], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[52]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[53], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[53]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[54], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[54]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[55], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[55]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[56], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[56]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[57], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[57]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[58], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[58]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[59], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[59]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[5], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[5]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[60], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[60]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[61], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[61]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[62], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[62]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[63], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[63]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[64], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[64]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[65], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[65]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[66], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[66]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[67], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[67]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[68], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[68]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[69], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[69]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[6], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[6]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[70], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[70]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[71], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[71]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[72], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[72]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[73], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[73]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[74], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[74]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[75], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[75]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[76], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[76]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[77], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[77]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[78], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[78]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[79], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[79]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[7], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[7]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[80], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[80]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[81], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[81]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[82], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[82]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[83], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[83]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[84], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[84]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[85], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[85]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[86], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[86]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[87], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[87]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[88], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[88]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[89], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[89]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[8], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[8]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[90], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[90]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[91], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[91]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[92], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[92]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[93], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[93]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[94], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[94]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[95], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[95]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[96], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[96]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[97], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[97]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[98], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[98]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[99], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[99]);
$setuphold (posedge FABRIC_CLK, posedge DATA_DAC3[9], 0:0:0, 0:0:0, notifier, , , FABRIC_CLK_delay, DATA_DAC3_delay[9]);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (negedge FABRIC_CLK, 0:0:0, 0, notifier);
$width (negedge PLL_MONCLK, 0:0:0, 0, notifier);
$width (negedge PLL_REFCLK_IN, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
$width (posedge FABRIC_CLK, 0:0:0, 0, notifier);
$width (posedge PLL_MONCLK, 0:0:0, 0, notifier);
$width (posedge PLL_REFCLK_IN, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
// http://www.eg.bucknell.edu/~cs320/1995-fall/verilog-manual.html#RTFToC33
// Digital model of a traffic light
// By Dan Hyde August 10, 1995
module traffic;
parameter on = 1, off = 0, red_tics = 35,
amber_tics = 3, green_tics = 20;
reg clock, red, amber, green;
// will stop the simulation after 1000 time units
initial begin: stop_at
#1000; $stop;
end
// initialize the lights and set up monitoring of registers
initial begin: Init
red = off; amber = off; green = off;
$display(" Time green amber red");
$monitor("%3d %b %b %b", $time, green, amber, red);
end
// task to wait for 'tics' positive edge clocks
// before turning light off
task light;
output color;
input [31:0] tics;
begin
repeat(tics) // wait to detect tics positive edges on clock
@(posedge clock);
color = off;
end
endtask
// waveform for clock period of 2 time units
always begin: clock_wave
#1 clock = 0;
#1 clock = 1;
end
always begin: main_process
red = on;
light(red, red_tics); // call task to wait
green = on;
light(green, green_tics);
amber = on;
light(amber, amber_tics);
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : bank_compare.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// This block stores the request for this bank machine.
//
// All possible new requests are compared against the request stored
// here. The compare results are shared with the bank machines and
// is used to determine where to enqueue a new request.
`timescale 1ps/1ps
module bank_compare #
(parameter BANK_WIDTH = 3,
parameter TCQ = 100,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter ECC = "OFF",
parameter RANK_WIDTH = 2,
parameter RANKS = 4,
parameter ROW_WIDTH = 16)
(/*AUTOARG*/
// Outputs
req_data_buf_addr_r, req_periodic_rd_r, req_size_r, rd_wr_r,
req_rank_r, req_bank_r, req_row_r, req_wr_r, req_priority_r,
rb_hit_busy_r, rb_hit_busy_ns, row_hit_r, maint_hit, col_addr,
req_ras, req_cas, row_cmd_wr, row_addr, rank_busy_r,
// Inputs
clk, idle_ns, idle_r, data_buf_addr, periodic_rd_insert, size, cmd,
sending_col, rank, periodic_rd_rank_r, bank, row, col, hi_priority,
maint_rank_r, maint_zq_r, auto_pre_r, rd_half_rmw, act_wait_r
);
input clk;
input idle_ns;
input idle_r;
input [DATA_BUF_ADDR_WIDTH-1:0]data_buf_addr;
output reg [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_r;
wire [DATA_BUF_ADDR_WIDTH-1:0] req_data_buf_addr_ns =
idle_r
? data_buf_addr
: req_data_buf_addr_r;
always @(posedge clk) req_data_buf_addr_r <= #TCQ req_data_buf_addr_ns;
input periodic_rd_insert;
reg req_periodic_rd_r_lcl;
wire req_periodic_rd_ns = idle_ns
? periodic_rd_insert
: req_periodic_rd_r_lcl;
always @(posedge clk) req_periodic_rd_r_lcl <= #TCQ req_periodic_rd_ns;
output wire req_periodic_rd_r;
assign req_periodic_rd_r = req_periodic_rd_r_lcl;
input size;
wire req_size_r_lcl;
generate
if (BURST_MODE == "4") begin : burst_mode_4
assign req_size_r_lcl = 1'b0;
end
else
if (BURST_MODE == "8") begin : burst_mode_8
assign req_size_r_lcl = 1'b1;
end
else
if (BURST_MODE == "OTF") begin : burst_mode_otf
reg req_size;
wire req_size_ns = idle_ns
? (periodic_rd_insert || size)
: req_size;
always @(posedge clk) req_size <= #TCQ req_size_ns;
assign req_size_r_lcl = req_size;
end
endgenerate
output wire req_size_r;
assign req_size_r = req_size_r_lcl;
input [2:0] cmd;
reg [2:0] req_cmd_r;
wire [2:0] req_cmd_ns = idle_ns
? (periodic_rd_insert ? 3'b001 : cmd)
: req_cmd_r;
always @(posedge clk) req_cmd_r <= #TCQ req_cmd_ns;
`ifdef MC_SVA
rd_wr_only_wo_ecc: assert property
(@(posedge clk) ((ECC != "OFF") || idle_ns || ~|req_cmd_ns[2:1]));
`endif
input sending_col;
reg rd_wr_r_lcl;
wire rd_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || req_cmd_ns[0])
: ~sending_col && rd_wr_r_lcl;
always @(posedge clk) rd_wr_r_lcl <= #TCQ rd_wr_ns;
output wire rd_wr_r;
assign rd_wr_r = rd_wr_r_lcl;
input [RANK_WIDTH-1:0] rank;
input [RANK_WIDTH-1:0] periodic_rd_rank_r;
reg [RANK_WIDTH-1:0] req_rank_r_lcl = {RANK_WIDTH{1'b0}};
reg [RANK_WIDTH-1:0] req_rank_ns = {RANK_WIDTH{1'b0}};
generate
if (RANKS != 1) begin
always @(/*AS*/idle_ns or periodic_rd_insert
or periodic_rd_rank_r or rank or req_rank_r_lcl) req_rank_ns = idle_ns
? periodic_rd_insert
? periodic_rd_rank_r
: rank
: req_rank_r_lcl;
always @(posedge clk) req_rank_r_lcl <= #TCQ req_rank_ns;
end
endgenerate
output wire [RANK_WIDTH-1:0] req_rank_r;
assign req_rank_r = req_rank_r_lcl;
input [BANK_WIDTH-1:0] bank;
reg [BANK_WIDTH-1:0] req_bank_r_lcl;
wire [BANK_WIDTH-1:0] req_bank_ns = idle_ns ? bank : req_bank_r_lcl;
always @(posedge clk) req_bank_r_lcl <= #TCQ req_bank_ns;
output wire[BANK_WIDTH-1:0] req_bank_r;
assign req_bank_r = req_bank_r_lcl;
input [ROW_WIDTH-1:0] row;
reg [ROW_WIDTH-1:0] req_row_r_lcl;
wire [ROW_WIDTH-1:0] req_row_ns = idle_ns ? row : req_row_r_lcl;
always @(posedge clk) req_row_r_lcl <= #TCQ req_row_ns;
output wire [ROW_WIDTH-1:0] req_row_r;
assign req_row_r = req_row_r_lcl;
// Make req_col_r as wide as the max row address. This
// makes it easier to deal with indexing different column widths.
input [COL_WIDTH-1:0] col;
reg [15:0] req_col_r = 16'b0;
wire [COL_WIDTH-1:0] req_col_ns = idle_ns ? col : req_col_r[COL_WIDTH-1:0];
always @(posedge clk) req_col_r[COL_WIDTH-1:0] <= #TCQ req_col_ns;
reg req_wr_r_lcl;
wire req_wr_ns = idle_ns
? ((req_cmd_ns[1:0] == 2'b11) || ~req_cmd_ns[0])
: req_wr_r_lcl;
always @(posedge clk) req_wr_r_lcl <= #TCQ req_wr_ns;
output wire req_wr_r;
assign req_wr_r = req_wr_r_lcl;
input hi_priority;
output reg req_priority_r;
wire req_priority_ns = idle_ns ? hi_priority : req_priority_r;
always @(posedge clk) req_priority_r <= #TCQ req_priority_ns;
wire rank_hit = (req_rank_r_lcl == (periodic_rd_insert
? periodic_rd_rank_r
: rank));
wire bank_hit = (req_bank_r_lcl == bank);
wire rank_bank_hit = rank_hit && bank_hit;
output reg rb_hit_busy_r; // rank-bank hit on non idle row machine
wire rb_hit_busy_ns_lcl;
assign rb_hit_busy_ns_lcl = rank_bank_hit && ~idle_ns;
output wire rb_hit_busy_ns;
assign rb_hit_busy_ns = rb_hit_busy_ns_lcl;
wire row_hit_ns = (req_row_r_lcl == row);
output reg row_hit_r;
always @(posedge clk) rb_hit_busy_r <= #TCQ rb_hit_busy_ns_lcl;
always @(posedge clk) row_hit_r <= #TCQ row_hit_ns;
input [RANK_WIDTH-1:0] maint_rank_r;
input maint_zq_r;
output wire maint_hit;
assign maint_hit = (req_rank_r_lcl == maint_rank_r) || maint_zq_r;
// Assemble column address. Structure to be the same
// width as the row address. This makes it easier
// for the downstream muxing. Depending on the sizes
// of the row and column addresses, fill in as appropriate.
input auto_pre_r;
input rd_half_rmw;
reg [15:0] col_addr_template = 16'b0;
always @(/*AS*/auto_pre_r or rd_half_rmw or req_col_r
or req_size_r_lcl) begin
col_addr_template = req_col_r;
col_addr_template[10] = auto_pre_r && ~rd_half_rmw;
col_addr_template[11] = req_col_r[10];
col_addr_template[12] = req_size_r_lcl;
col_addr_template[13] = req_col_r[11];
end
output wire [ROW_WIDTH-1:0] col_addr;
assign col_addr = col_addr_template[ROW_WIDTH-1:0];
output wire req_ras;
output wire req_cas;
output wire row_cmd_wr;
input act_wait_r;
assign req_ras = 1'b0;
assign req_cas = 1'b1;
assign row_cmd_wr = act_wait_r;
output reg [ROW_WIDTH-1:0] row_addr;
always @(/*AS*/act_wait_r or req_row_r_lcl) begin
row_addr = req_row_r_lcl;
// This causes all precharges to be precharge single bank command.
if (~act_wait_r) row_addr[10] = 1'b0;
end
// Indicate which, if any, rank this bank machine is busy with.
// Not registering the result would probably be more accurate, but
// would create timing issues. This is used for refresh banking, perfect
// accuracy is not required.
localparam ONE = 1;
output reg [RANKS-1:0] rank_busy_r;
wire [RANKS-1:0] rank_busy_ns = {RANKS{~idle_ns}} & (ONE[RANKS-1:0] << req_rank_ns);
always @(posedge clk) rank_busy_r <= #TCQ rank_busy_ns;
endmodule // bank_compare
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
(* rom_style = "block" *) module Loop_loop_height_bkb_rom (
addr0, ce0, q0, addr1, ce1, q1, addr2, ce2, q2, clk);
parameter DWIDTH = 8;
parameter AWIDTH = 8;
parameter MEM_SIZE = 256;
input[AWIDTH-1:0] addr0;
input ce0;
output reg[DWIDTH-1:0] q0;
input[AWIDTH-1:0] addr1;
input ce1;
output reg[DWIDTH-1:0] q1;
input[AWIDTH-1:0] addr2;
input ce2;
output reg[DWIDTH-1:0] q2;
input clk;
(* ram_style = "block" *)reg [DWIDTH-1:0] ram0[0:MEM_SIZE-1];
(* ram_style = "block" *)reg [DWIDTH-1:0] ram1[0:MEM_SIZE-1];
initial begin
$readmemh("./Loop_loop_height_bkb_rom.dat", ram0);
$readmemh("./Loop_loop_height_bkb_rom.dat", ram1);
end
always @(posedge clk)
begin
if (ce0)
begin
q0 <= ram0[addr0];
end
end
always @(posedge clk)
begin
if (ce1)
begin
q1 <= ram0[addr1];
end
end
always @(posedge clk)
begin
if (ce2)
begin
q2 <= ram1[addr2];
end
end
endmodule
`timescale 1 ns / 1 ps
module Loop_loop_height_bkb(
reset,
clk,
address0,
ce0,
q0,
address1,
ce1,
q1,
address2,
ce2,
q2);
parameter DataWidth = 32'd8;
parameter AddressRange = 32'd256;
parameter AddressWidth = 32'd8;
input reset;
input clk;
input[AddressWidth - 1:0] address0;
input ce0;
output[DataWidth - 1:0] q0;
input[AddressWidth - 1:0] address1;
input ce1;
output[DataWidth - 1:0] q1;
input[AddressWidth - 1:0] address2;
input ce2;
output[DataWidth - 1:0] q2;
Loop_loop_height_bkb_rom Loop_loop_height_bkb_rom_U(
.clk( clk ),
.addr0( address0 ),
.ce0( ce0 ),
.q0( q0 ),
.addr1( address1 ),
.ce1( ce1 ),
.q1( q1 ),
.addr2( address2 ),
.ce2( ce2 ),
.q2( q2 ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Iztok Jeras.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
localparam NO = 10; // number of access events
// packed structures
struct packed {
logic e0;
logic [1:0] e1;
logic [3:0] e2;
logic [7:0] e3;
} struct_bg; // big endian structure
/* verilator lint_off LITENDIAN */
struct packed {
logic e0;
logic [0:1] e1;
logic [0:3] e2;
logic [0:7] e3;
} struct_lt; // little endian structure
/* verilator lint_on LITENDIAN */
localparam WS = 15; // $bits(struct_bg)
integer cnt = 0;
// event counter
always @ (posedge clk)
begin
cnt <= cnt + 1;
end
// finish report
always @ (posedge clk)
if ((cnt[30:2]==NO) && (cnt[1:0]==2'd0)) begin
$write("*-* All Finished *-*\n");
$finish;
end
// big endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_bg <= '0;
else if (cnt[30:2]==1) struct_bg <= '0;
else if (cnt[30:2]==2) struct_bg <= '0;
else if (cnt[30:2]==3) struct_bg <= '0;
else if (cnt[30:2]==4) struct_bg <= '0;
else if (cnt[30:2]==5) struct_bg <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_bg <= '1;
else if (cnt[30:2]==2) struct_bg.e0 <= '1;
else if (cnt[30:2]==3) struct_bg.e1 <= '1;
else if (cnt[30:2]==4) struct_bg.e2 <= '1;
else if (cnt[30:2]==5) struct_bg.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_bg !== 15'b000000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_bg !== 15'b111111111111111) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_bg !== 15'b100000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_bg !== 15'b011000000000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_bg !== 15'b000111100000000) begin $display("%b", struct_bg); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_bg !== 15'b000000011111111) begin $display("%b", struct_bg); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_bg !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_bg !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_bg.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_bg.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_bg.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_bg.e3 !== { 8{1'b1}}) $stop(); end
end
// little endian
always @ (posedge clk)
if (cnt[1:0]==2'd0) begin
// initialize to defaaults (all bits to 0)
if (cnt[30:2]==0) struct_lt <= '0;
else if (cnt[30:2]==1) struct_lt <= '0;
else if (cnt[30:2]==2) struct_lt <= '0;
else if (cnt[30:2]==3) struct_lt <= '0;
else if (cnt[30:2]==4) struct_lt <= '0;
else if (cnt[30:2]==5) struct_lt <= '0;
end else if (cnt[1:0]==2'd1) begin
// write value to structure
if (cnt[30:2]==0) begin end
else if (cnt[30:2]==1) struct_lt <= '1;
else if (cnt[30:2]==2) struct_lt.e0 <= '1;
else if (cnt[30:2]==3) struct_lt.e1 <= '1;
else if (cnt[30:2]==4) struct_lt.e2 <= '1;
else if (cnt[30:2]==5) struct_lt.e3 <= '1;
end else if (cnt[1:0]==2'd2) begin
// check structure value
if (cnt[30:2]==0) begin if (struct_lt !== 15'b000000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==1) begin if (struct_lt !== 15'b111111111111111) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==2) begin if (struct_lt !== 15'b100000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==3) begin if (struct_lt !== 15'b011000000000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==4) begin if (struct_lt !== 15'b000111100000000) begin $display("%b", struct_lt); $stop(); end end
else if (cnt[30:2]==5) begin if (struct_lt !== 15'b000000011111111) begin $display("%b", struct_lt); $stop(); end end
end else if (cnt[1:0]==2'd3) begin
// read value from structure (not a very good test for now)
if (cnt[30:2]==0) begin if (struct_lt !== {WS{1'b0}}) $stop(); end
else if (cnt[30:2]==1) begin if (struct_lt !== {WS{1'b1}}) $stop(); end
else if (cnt[30:2]==2) begin if (struct_lt.e0 !== { 1{1'b1}}) $stop(); end
else if (cnt[30:2]==3) begin if (struct_lt.e1 !== { 2{1'b1}}) $stop(); end
else if (cnt[30:2]==4) begin if (struct_lt.e2 !== { 4{1'b1}}) $stop(); end
else if (cnt[30:2]==5) begin if (struct_lt.e3 !== { 8{1'b1}}) $stop(); end
end
endmodule
|
// file: clk_wiz_v3_2.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// User entered comments
//----------------------------------------------------------------------------
// None
//
//----------------------------------------------------------------------------
// "Output Output Phase Duty Pk-to-Pk Phase"
// "Clock Freq (MHz) (degrees) Cycle (%) Jitter (ps) Error (ps)"
//----------------------------------------------------------------------------
// CLK_OUT1___200.000______0.000_______N/A______220.000________N/A
//
//----------------------------------------------------------------------------
// "Input Clock Freq (MHz) Input Jitter (UI)"
//----------------------------------------------------------------------------
// __primary_________100.000_____________0.01
`timescale 1ps/1ps
// Please set INPUT_FREQUENCY to the MHz of the incoming clock!!
// WARNING: This module will currently NOT handle anything other than a 100MHz
// clock because the CLKIN_PERIOD is not properly calculated.
//
// SYNTHESIS_FREQUENCY is used to determine at what frequency the design is
// synthesized for.
//
//
// NOTE: Internally, the divider is set to half of
// INPUT_FREQUENCY. This allows a greater range of output frequencies.
// So when you look at the COMM code, you'll see that it takes the requested
// frequency and divides by 2 to get the proper multiplier.
module dynamic_clock # (
parameter INPUT_FREQUENCY = 100,
parameter SYNTHESIS_FREQUENCY = 200
) (
input CLK_IN1,
output CLK_OUT1,
input PROGCLK,
input PROGDATA,
input PROGEN,
output PROGDONE
);
// Input buffering
//------------------------------------
/*IBUFG clkin1_buf
(.O (clkin1),
.I (CLK_IN1));*/
// Clocking primitive
//------------------------------------
// Instantiation of the DCM primitive
// * Unused inputs are tied off
wire clkfx;
DCM_CLKGEN
#(.CLKFXDV_DIVIDE (2),
.CLKFX_DIVIDE (INPUT_FREQUENCY >> 1),
.CLKFX_MULTIPLY (SYNTHESIS_FREQUENCY >> 1),
.SPREAD_SPECTRUM ("NONE"),
.STARTUP_WAIT ("FALSE"),
.CLKIN_PERIOD (10.0),
.CLKFX_MD_MAX (0.000))
dcm_clkgen_inst
// Input clock
(.CLKIN (CLK_IN1),
// Output clocks
.CLKFX (clkfx),
.CLKFX180 (),
.CLKFXDV (),
// Ports for dynamic reconfiguration
.PROGCLK (PROGCLK),
.PROGDATA (PROGDATA),
.PROGEN (PROGEN),
.PROGDONE (PROGDONE),
// Other control and status signals
.FREEZEDCM (1'b0),
.LOCKED (),
.STATUS (),
.RST (1'b0));
// Output buffering
//-----------------------------------
BUFG clkout1_buf
(.O (CLK_OUT1),
.I (clkfx));
endmodule
|
//-----------------------------------------------------------------------------
// ISO14443-A support for the Proxmark III
// Gerhard de Koning Gans, April 2008
//-----------------------------------------------------------------------------
// constants for the different modes:
`define SNIFFER 3'b000
`define TAGSIM_LISTEN 3'b001
`define TAGSIM_MOD 3'b010
`define READER_LISTEN 3'b011
`define READER_MOD 3'b100
module hi_iso14443a(
pck0, ck_1356meg, ck_1356megb,
pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4,
adc_d, adc_clk,
ssp_frame, ssp_din, ssp_dout, ssp_clk,
cross_hi, cross_lo,
dbg,
mod_type
);
input pck0, ck_1356meg, ck_1356megb;
output pwr_lo, pwr_hi, pwr_oe1, pwr_oe2, pwr_oe3, pwr_oe4;
input [7:0] adc_d;
output adc_clk;
input ssp_dout;
output ssp_frame, ssp_din, ssp_clk;
input cross_hi, cross_lo;
output dbg;
input [2:0] mod_type;
wire adc_clk = ck_1356meg;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3:
// detecting and shaping the reader's signal. Reader will modulate the carrier by 100% (signal is either on or off). Use a
// hysteresis (Schmitt Trigger) to avoid false triggers during slowly increasing or decreasing carrier amplitudes
reg after_hysteresis;
reg [11:0] has_been_low_for;
always @(negedge adc_clk)
begin
if(adc_d >= 16) after_hysteresis <= 1'b1; // U >= 1,14V -> after_hysteresis = 1
else if(adc_d < 8) after_hysteresis <= 1'b0; // U < 1,04V -> after_hysteresis = 0
// Note: was >= 3,53V and <= 1,19V. The new trigger values allow more reliable detection of the first bit
// (it might not reach 3,53V due to the high time constant of the high pass filter in the analogue RF part).
// In addition, the new values are more in line with ISO14443-2: "The PICC shall detect the ”End of Pause” after the field exceeds
// 5% of H_INITIAL and before it exceeds 60% of H_INITIAL." Depending on the signal strength, 60% might well be less than 3,53V.
// detecting a loss of reader's field (adc_d < 192 for 4096 clock cycles). If this is the case,
// set the detected reader signal (after_hysteresis) to '1' (unmodulated)
if(adc_d >= 192)
begin
has_been_low_for <= 12'd0;
end
else
begin
if(has_been_low_for == 12'd4095)
begin
has_been_low_for <= 12'd0;
after_hysteresis <= 1'b1;
end
else
begin
has_been_low_for <= has_been_low_for + 1;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Reader -> PM3
// detect when a reader is active (modulating). We assume that the reader is active, if we see the carrier off for at least 8
// carrier cycles. We assume that the reader is inactive, if the carrier stayed high for at least 256 carrier cycles.
reg deep_modulation;
reg [2:0] deep_counter;
reg [8:0] saw_deep_modulation;
always @(negedge adc_clk)
begin
if(~(| adc_d[7:0])) // if adc_d == 0 (U <= 0,94V)
begin
if(deep_counter == 3'd7) // adc_d == 0 for 8 adc_clk ticks -> deep_modulation (by reader)
begin
deep_modulation <= 1'b1;
saw_deep_modulation <= 8'd0;
end
else
deep_counter <= deep_counter + 1;
end
else
begin
deep_counter <= 3'd0;
if(saw_deep_modulation == 8'd255) // adc_d != 0 for 256 adc_clk ticks -> deep_modulation is over, probably waiting for tag's response
deep_modulation <= 1'b0;
else
saw_deep_modulation <= saw_deep_modulation + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3
// filter the input for a tag's signal. The filter box needs the 4 previous input values and is a gaussian derivative filter
// for noise reduction and edge detection.
// store 4 previous samples:
reg [7:0] input_prev_4, input_prev_3, input_prev_2, input_prev_1;
// convert to signed signals (and multiply by two for samples at t-4 and t)
wire signed [10:0] input_prev_4_times_2 = {0, 0, input_prev_4, 0};
wire signed [10:0] input_prev_3_times_1 = {0, 0, 0, input_prev_3};
wire signed [10:0] input_prev_1_times_1 = {0, 0, 0, input_prev_1};
wire signed [10:0] adc_d_times_2 = {0, 0, adc_d, 0};
wire signed [10:0] tmp_1, tmp_2;
wire signed [10:0] adc_d_filtered;
integer i;
assign tmp_1 = input_prev_4_times_2 + input_prev_3_times_1;
assign tmp_2 = input_prev_1_times_1 + adc_d_times_2;
always @(negedge adc_clk)
begin
// for (i = 3; i > 0; i = i - 1)
// begin
// input_shift[i] <= input_shift[i-1];
// end
// input_shift[0] <= adc_d;
input_prev_4 <= input_prev_3;
input_prev_3 <= input_prev_2;
input_prev_2 <= input_prev_1;
input_prev_1 <= adc_d;
end
// assign adc_d_filtered = (input_shift[3] << 1) + input_shift[2] - input_shift[0] - (adc_d << 1);
assign adc_d_filtered = tmp_1 - tmp_2;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// internal FPGA timing. Maximum required period is 128 carrier clock cycles for a full 8 Bit transfer to ARM. (i.e. we need a
// 7 bit counter). Adjust its frequency to external reader's clock when simulating a tag or sniffing.
reg pre_after_hysteresis;
reg [3:0] reader_falling_edge_time;
reg [6:0] negedge_cnt;
always @(negedge adc_clk)
begin
// detect a reader signal's falling edge and remember its timing:
pre_after_hysteresis <= after_hysteresis;
if (pre_after_hysteresis && ~after_hysteresis)
begin
reader_falling_edge_time[3:0] <= negedge_cnt[3:0];
end
// adjust internal timer counter if necessary:
if (negedge_cnt[3:0] == 4'd13 && (mod_type == `SNIFFER || mod_type == `TAGSIM_LISTEN) && deep_modulation)
begin
if (reader_falling_edge_time == 4'd1) // reader signal changes right after sampling. Better sample earlier next time.
begin
negedge_cnt <= negedge_cnt + 2; // time warp
end
else if (reader_falling_edge_time == 4'd0) // reader signal changes right before sampling. Better sample later next time.
begin
negedge_cnt <= negedge_cnt; // freeze time
end
else
begin
negedge_cnt <= negedge_cnt + 1; // Continue as usual
end
reader_falling_edge_time[3:0] <= 4'd8; // adjust only once per detected edge
end
else if (negedge_cnt == 7'd127) // normal operation: count from 0 to 127
begin
negedge_cnt <= 0;
end
else
begin
negedge_cnt <= negedge_cnt + 1;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// determine best possible time for starting/resetting the modulation detector.
reg [3:0] mod_detect_reset_time;
always @(negedge adc_clk)
begin
if (mod_type == `READER_LISTEN)
// (our) reader signal changes at t=1, tag response expected n*16+4 ticks later, further delayed by
// 3 ticks ADC conversion.
// 1 + 4 + 3 = 8
begin
mod_detect_reset_time <= 4'd8;
end
else
if (mod_type == `SNIFFER)
begin
// detect a rising edge of reader's signal and sync modulation detector to the tag's answer:
if (~pre_after_hysteresis && after_hysteresis && deep_modulation)
// reader signal rising edge detected at negedge_cnt[3:0]. This signal had been delayed
// 9 ticks by the RF part + 3 ticks by the A/D converter + 1 tick to assign to after_hysteresis.
// The tag will respond n*16 + 4 ticks later + 3 ticks A/D converter delay.
// - 9 - 3 - 1 + 4 + 3 = -6
begin
mod_detect_reset_time <= negedge_cnt[3:0] - 4'd4;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag -> PM3:
// modulation detector. Looks for the steepest falling and rising edges within a 16 clock period. If there is both a significant
// falling and rising edge (in any order), a modulation is detected.
reg signed [10:0] rx_mod_falling_edge_max;
reg signed [10:0] rx_mod_rising_edge_max;
reg curbit;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == mod_detect_reset_time)
begin
// detect modulation signal: if modulating, there must have been a falling AND a rising edge
if (rx_mod_falling_edge_max > 5 && rx_mod_rising_edge_max > 5)
curbit <= 1'b1; // modulation
else
curbit <= 1'b0; // no modulation
// reset modulation detector
rx_mod_rising_edge_max <= 0;
rx_mod_falling_edge_max <= 0;
end
else // look for steepest edges (slopes)
begin
if (adc_d_filtered > 0)
begin
if (adc_d_filtered > rx_mod_falling_edge_max)
rx_mod_falling_edge_max <= adc_d_filtered;
end
else
begin
if (-adc_d_filtered > rx_mod_rising_edge_max)
rx_mod_rising_edge_max <= -adc_d_filtered;
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Tag+Reader -> PM3
// sample 4 bits reader data and 4 bits tag data for sniffing
reg [3:0] reader_data;
reg [3:0] tag_data;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
reader_data[3:0] <= {reader_data[2:0], after_hysteresis};
tag_data[3:0] <= {tag_data[2:0], curbit};
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Tag:
// a delay line to ensure that we send the (emulated) tag's answer at the correct time according to ISO14443-3
reg [31:0] mod_sig_buf;
reg [4:0] mod_sig_ptr;
reg mod_sig;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0) // sample data at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
mod_sig_buf[31:2] <= mod_sig_buf[30:1]; // shift
if (~ssp_dout && ~mod_sig_buf[1])
mod_sig_buf[1] <= 1'b0; // delete the correction bit (a single 1 preceded and succeeded by 0)
else
mod_sig_buf[1] <= mod_sig_buf[0];
mod_sig_buf[0] <= ssp_dout; // add new data to the delay line
mod_sig = mod_sig_buf[mod_sig_ptr]; // the delayed signal.
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Tag, internal timing:
// a timer for the 1172 cycles fdt (Frame Delay Time). Start the timer with a rising edge of the reader's signal.
// set fdt_elapsed when we no longer need to delay data. Set fdt_indicator when we can start sending data.
// Note: the FPGA only takes care for the 1172 delay. To achieve an additional 1236-1172=64 ticks delay, the ARM must send
// a correction bit (before the start bit). The correction bit will be coded as 00010000, i.e. it adds 4 bits to the
// transmission stream, causing the required additional delay.
reg [10:0] fdt_counter;
reg fdt_indicator, fdt_elapsed;
reg [3:0] mod_sig_flip;
reg [3:0] sub_carrier_cnt;
// we want to achieve a delay of 1172. The RF part already has delayed the reader signals's rising edge
// by 9 ticks, the ADC took 3 ticks and there is always a delay of 32 ticks by the mod_sig_buf. Therefore need to
// count to 1172 - 9 - 3 - 32 = 1128
`define FDT_COUNT 11'd1128
// The ARM must not send too early, otherwise the mod_sig_buf will overflow, therefore signal that we are ready
// with fdt_indicator. The mod_sig_buf can buffer 29 excess data bits, i.e. a maximum delay of 29 * 16 = 464 adc_clk ticks.
// fdt_indicator could appear at ssp_din after 1 tick, the transfer needs 16 ticks, the ARM can send 128 ticks later.
// 1128 - 464 - 1 - 128 - 8 = 535
`define FDT_INDICATOR_COUNT 11'd535
// reset on a pause in listen mode. I.e. the counter starts when the pause is over:
assign fdt_reset = ~after_hysteresis && mod_type == `TAGSIM_LISTEN;
always @(negedge adc_clk)
begin
if (fdt_reset)
begin
fdt_counter <= 11'd0;
fdt_elapsed <= 1'b0;
fdt_indicator <= 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT)
begin
if(~fdt_elapsed) // just reached fdt.
begin
mod_sig_flip <= negedge_cnt[3:0]; // start modulation at this time
sub_carrier_cnt <= 4'd0; // subcarrier phase in sync with start of modulation
fdt_elapsed <= 1'b1;
end
else
begin
sub_carrier_cnt <= sub_carrier_cnt + 1;
end
end
else
begin
fdt_counter <= fdt_counter + 1;
end
end
if(fdt_counter == `FDT_INDICATOR_COUNT) fdt_indicator <= 1'b1;
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader or Tag
// assign a modulation signal to the antenna. This signal is either a delayed signal (to achieve fdt when sending to a reader)
// or undelayed when sending to a tag
reg mod_sig_coil;
always @(negedge adc_clk)
begin
if (mod_type == `TAGSIM_MOD) // need to take care of proper fdt timing
begin
if(fdt_counter == `FDT_COUNT)
begin
if(fdt_elapsed)
begin
if(negedge_cnt[3:0] == mod_sig_flip) mod_sig_coil <= mod_sig;
end
else
begin
mod_sig_coil <= mod_sig; // just reached fdt. Immediately assign signal to coil
end
end
end
else // other modes: don't delay
begin
mod_sig_coil <= ssp_dout;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// PM3 -> Reader
// determine the required delay in the mod_sig_buf (set mod_sig_ptr).
reg temp_buffer_reset;
always @(negedge adc_clk)
begin
if(fdt_reset)
begin
mod_sig_ptr <= 5'd0;
temp_buffer_reset = 1'b0;
end
else
begin
if(fdt_counter == `FDT_COUNT && ~fdt_elapsed) // if we just reached fdt
if(~(| mod_sig_ptr[4:0]))
mod_sig_ptr <= 5'd8; // ... but didn't buffer a 1 yet, delay next 1 by n*128 ticks.
else
temp_buffer_reset = 1'b1; // else no need for further delays.
if(negedge_cnt[3:0] == 4'd0) // at rising edge of ssp_clk - ssp_dout changes at the falling edge.
begin
if((ssp_dout || (| mod_sig_ptr[4:0])) && ~fdt_elapsed) // buffer a 1 (and all subsequent data) until fdt is reached.
if (mod_sig_ptr == 5'd31)
mod_sig_ptr <= 5'd0; // buffer overflow - data loss.
else
mod_sig_ptr <= mod_sig_ptr + 1; // increase buffer (= increase delay by 16 adc_clk ticks). mod_sig_ptr always points ahead of first 1.
else if(fdt_elapsed && ~temp_buffer_reset)
begin
// wait for the next 1 after fdt_elapsed before fixing the delay and starting modulation. This ensures that the response can only happen
// at intervals of 8 * 16 = 128 adc_clk ticks (as defined in ISO14443-3)
if(ssp_dout)
temp_buffer_reset = 1'b1;
if(mod_sig_ptr == 5'd1)
mod_sig_ptr <= 5'd8; // still nothing received, need to go for the next interval
else
mod_sig_ptr <= mod_sig_ptr - 1; // decrease buffer.
end
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// buffer 8 bits data to be sent to ARM. Shift them out bit by bit.
reg [7:0] to_arm;
always @(negedge adc_clk)
begin
if (negedge_cnt[5:0] == 6'd63) // fill the buffer
begin
if (mod_type == `SNIFFER)
begin
if(deep_modulation) // a reader is sending (or there's no field at all)
begin
to_arm <= {reader_data[3:0], 4'b0000}; // don't send tag data
end
else
begin
to_arm <= {reader_data[3:0], tag_data[3:0]};
end
end
else
begin
to_arm[7:0] <= {mod_sig_ptr[4:0], mod_sig_flip[3:1]}; // feedback timing information
end
end
if(negedge_cnt[2:0] == 3'b000 && mod_type == `SNIFFER) // shift at double speed
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[5:0] != 6'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
if(negedge_cnt[3:0] == 4'b0000 && mod_type != `SNIFFER)
begin
// Don't shift if we just loaded new data, obviously.
if(negedge_cnt[6:0] != 7'd0)
begin
to_arm[7:1] <= to_arm[6:0];
end
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// generate a ssp clock and ssp frame signal for the synchronous transfer from/to the ARM
reg ssp_clk;
reg ssp_frame;
reg [2:0] ssp_frame_counter;
always @(negedge adc_clk)
begin
if(mod_type == `SNIFFER)
// SNIFFER mode (ssp_clk = adc_clk / 8, ssp_frame clock = adc_clk / 64)):
begin
if(negedge_cnt[2:0] == 3'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[2:0] == 3'd4)
ssp_clk <= 1'b0;
if(negedge_cnt[5:0] == 6'd0) // ssp_frame rising edge indicates start of frame
ssp_frame <= 1'b1;
if(negedge_cnt[5:0] == 6'd8)
ssp_frame <= 1'b0;
end
else
// all other modes (ssp_clk = adc_clk / 16, ssp_frame clock = adc_clk / 128):
begin
if(negedge_cnt[3:0] == 4'd0)
ssp_clk <= 1'b1;
if(negedge_cnt[3:0] == 4'd8)
ssp_clk <= 1'b0;
if(negedge_cnt[6:0] == 7'd7) // ssp_frame rising edge indicates start of frame
ssp_frame <= 1'b1;
if(negedge_cnt[6:0] == 7'd23)
ssp_frame <= 1'b0;
end
end
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// FPGA -> ARM communication:
// select the data to be sent to ARM
reg bit_to_arm;
reg sendbit;
always @(negedge adc_clk)
begin
if(negedge_cnt[3:0] == 4'd0)
begin
// What do we communicate to the ARM
if(mod_type == `TAGSIM_LISTEN)
sendbit = after_hysteresis;
else if(mod_type == `TAGSIM_MOD)
/* if(fdt_counter > 11'd772) sendbit = mod_sig_coil; // huh?
else */
sendbit = fdt_indicator;
else if (mod_type == `READER_LISTEN)
sendbit = curbit;
else
sendbit = 1'b0;
end
if(mod_type == `SNIFFER)
// send sampled reader and tag data:
bit_to_arm = to_arm[7];
else if (mod_type == `TAGSIM_MOD && fdt_elapsed && temp_buffer_reset)
// send timing information:
bit_to_arm = to_arm[7];
else
// send data or fdt_indicator
bit_to_arm = sendbit;
end
assign ssp_din = bit_to_arm;
// Subcarrier (adc_clk/16, for TAGSIM_MOD only).
wire sub_carrier;
assign sub_carrier = ~sub_carrier_cnt[3];
// in READER_MOD: drop carrier for mod_sig_coil==1 (pause); in READER_LISTEN: carrier always on; in other modes: carrier always off
assign pwr_hi = (ck_1356megb & (((mod_type == `READER_MOD) & ~mod_sig_coil) || (mod_type == `READER_LISTEN)));
// Enable HF antenna drivers:
assign pwr_oe1 = 1'b0;
assign pwr_oe3 = 1'b0;
// TAGSIM_MOD: short circuit antenna with different resistances (modulated by sub_carrier modulated by mod_sig_coil)
// for pwr_oe4 = 1 (tristate): antenna load = 10k || 33 = 32,9 Ohms
// for pwr_oe4 = 0 (active): antenna load = 10k || 33 || 33 = 16,5 Ohms
assign pwr_oe4 = ~(mod_sig_coil & sub_carrier & (mod_type == `TAGSIM_MOD));
// This is all LF, so doesn't matter.
assign pwr_oe2 = 1'b0;
assign pwr_lo = 1'b0;
assign dbg = negedge_cnt[3];
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg [2*32-1:0] w2; initial w2 = {2 {32'h12345678}};
reg [9*32-1:0] w9; initial w9 = {9 {32'h12345678}};
reg [10*32-1:0] w10; initial w10 = {10{32'h12345678}};
reg [11*32-1:0] w11; initial w11 = {11{32'h12345678}};
reg [15*32-1:0] w15; initial w15 = {15{32'h12345678}};
reg [31*32-1:0] w31; initial w31 = {31{32'h12345678}};
reg [47*32-1:0] w47; initial w47 = {47{32'h12345678}};
reg [63*32-1:0] w63; initial w63 = {63{32'h12345678}};
// Aggregate outputs into a single result vector
wire [63:0] result = (w2[63:0]
^ w9[64:1]
^ w10[65:2]
^ w11[66:3]
^ w15[67:4]
^ w31[68:5]
^ w47[69:6]
^ w63[70:7]);
// What checksum will we end up with
`define EXPECTED_SUM 64'h184cb39122d8c6e3
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w2 <= w2 >> 1;
w9 <= w9 >> 1;
w10 <= w10 >> 1;
w11 <= w11 >> 1;
w15 <= w15 >> 1;
w31 <= w31 >> 1;
w47 <= w47 >> 1;
w63 <= w63 >> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
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