text
stringlengths 992
1.04M
|
|---|
//
// Copyright 2011 Ettus Research LLC
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
//
// Parameter LE tells us if we are little-endian.
// Little-endian means send lower 16 bits first.
// Default is big endian (network order), send upper bits first.
module fifo72_to_fifo36
#(parameter LE=0)
(input clk, input reset, input clear,
input [71:0] f72_datain,
input f72_src_rdy_i,
output f72_dst_rdy_o,
output [35:0] f36_dataout,
output f36_src_rdy_o,
input f36_dst_rdy_i );
wire [35:0] f36_data_int;
wire f36_src_rdy_int, f36_dst_rdy_int;
wire [71:0] f72_data_int;
wire f72_src_rdy_int, f72_dst_rdy_int;
// Shortfifo on input to guarantee no deadlock
fifo_short #(.WIDTH(72)) head_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f72_datain), .src_rdy_i(f72_src_rdy_i), .dst_rdy_o(f72_dst_rdy_o),
.dataout(f72_data_int), .src_rdy_o(f72_src_rdy_int), .dst_rdy_i(f72_dst_rdy_int),
.space(),.occupied() );
// Main fifo72_to_fifo36, needs shortfifos to guarantee no deadlock
wire [2:0] f72_occ_int = f72_data_int[68:66];
wire f72_sof_int = f72_data_int[64];
wire f72_eof_int = f72_data_int[65];
reg phase;
wire half_line = f72_eof_int & ( (f72_occ_int==1)|(f72_occ_int==2)|(f72_occ_int==3)|(f72_occ_int==4) );
assign f36_data_int[31:0] = (LE ^ phase) ? f72_data_int[31:0] : f72_data_int[63:32];
assign f36_data_int[32] = phase ? 0 : f72_sof_int;
assign f36_data_int[33] = phase ? f72_eof_int : half_line;
assign f36_data_int[35:34] = f36_data_int[33] ? f72_occ_int[1:0] : 2'b00;
assign f36_src_rdy_int = f72_src_rdy_int;
assign f72_dst_rdy_int = (phase | half_line) & f36_dst_rdy_int;
wire f36_xfer = f36_src_rdy_int & f36_dst_rdy_int;
wire f72_xfer = f72_src_rdy_int & f72_dst_rdy_int;
always @(posedge clk)
if(reset)
phase <= 0;
else if(f72_xfer)
phase <= 0;
else if(f36_xfer)
phase <= 1;
// Shortfifo on output to guarantee no deadlock
fifo_short #(.WIDTH(36)) tail_fifo
(.clk(clk),.reset(reset),.clear(clear),
.datain(f36_data_int), .src_rdy_i(f36_src_rdy_int), .dst_rdy_o(f36_dst_rdy_int),
.dataout(f36_dataout), .src_rdy_o(f36_src_rdy_o), .dst_rdy_i(f36_dst_rdy_i),
.space(),.occupied() );
endmodule // fifo72_to_fifo36
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2005 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg b;
wire vconst1 = 1'b0;
wire vconst2 = !(vconst1);
wire vconst3 = !vconst2;
wire vconst = vconst3;
wire qa;
wire qb;
wire qc;
wire qd;
wire qe;
ta ta (.b(b), .vconst(vconst), .q(qa));
tb tb (.clk(clk), .vconst(vconst), .q(qb));
tc tc (.b(b), .vconst(vconst), .q(qc));
td td (.b(b), .vconst(vconst), .q(qd));
te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$display("%b",{qa,qb,qc,qd,qe});
`endif
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
b <= 1'b1;
end
if (cyc==2) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
b <= 1'b0;
end
if (cyc==3) begin
if (qa!=1'b0) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b0) $stop;
b <= 1'b1;
end
if (cyc==4) begin
if (qa!=1'b1) $stop;
if (qb!=1'b0) $stop;
if (qd!=1'b0) $stop;
if (qe!=1'b1) $stop;
b <= 1'b0;
end
if (cyc==5) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module ta (
input vconst,
input b,
output reg q);
always @ (/*AS*/b or vconst) begin
q = vconst | b;
end
endmodule
module tb (
input vconst,
input clk,
output reg q);
always @ (posedge clk) begin
q <= vconst;
end
endmodule
module tc (
input vconst,
input b,
output reg q);
always @ (posedge vconst) begin
q <= b;
$stop;
end
endmodule
module td (
input vconst,
input b,
output reg q);
always @ (/*AS*/vconst) begin
q = vconst;
end
endmodule
module te (
input clk,
input vconst,
input b,
output reg q);
reg qmid;
always @ (posedge vconst or posedge clk) begin
qmid <= b;
end
always @ (posedge clk or posedge vconst) begin
q <= qmid;
end
endmodule
|
//Verilint 182 off // WARNING: Illegal statement for synthesis: $realtobits (in1)
//Verilint 311 off // WARNING: Converting real to unsigned: $realtobits (in1)
//Verilint 20 off // WARNING: Assign statement may not be synthesizable: assign out7[i] = ...;
//Verilint 599 off // WARNING: This construct is not supported by Synopsys
//Verilint 433 off // WARNING: More than one top level module
//Verilint 71 off // WARNING: Case statement without default clause
module testmodule (/*AUTOARG*/
// Outputs
out1, out2, out3, out4, out5, out7, out8, outb2, outb3, outb4, outb6, outb7, outb8, outb9,
outb10, outw1, outw2, outw3,
// Inputs
in1, in2, in3, in4, in5
);
function [2:0] ffs;
input [2:0] in;
ffs = in & 3'b010;
endfunction
task show;
input [2:0] in;
begin
$display ("Hi %x", in);
end
endtask
input [2:0] in1,in2,in3,in4,in5;
output [2:0] out1, out2,out3,out4,out5,out7,out8;
output outb2,outb3,outb4,outb6,outb7,outb8,outb9,outb10;
output [7:0] outw1,outw2,outw3;
reg [2:0] memarry [0:2];
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [2:0] out1;
reg [2:0] out2;
reg [2:0] out3;
reg [2:0] out4;
reg [2:0] out5;
reg [2:0] out8;
reg outb2;
reg outb3;
reg outb4;
reg outb6;
reg outb7;
reg [7:0] outw1;
reg [7:0] outw2;
reg [7:0] outw3;
// End of automatics
wire outb8=1'b1, outb9=|{in1[0],in2[0]}, outb10=1'b0;
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
:ignore_label
out1 = $realtobits(in1);
out2 = ffs(in1 | (in2) );
out3 = ffs /*check*/ (in2);
$display ("chk ", in1);
show (in4);
if (|in3) out4=1; else out4=0;
end
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in5) begin
casex ({in5[1:0], (3'b010==in2)})
3'bx_1_0: out5=3'b000;
3'bx_1_1: out5=3'b010;
3'bx_0_x: out5=3'b100;
endcase
casex ({in3[in1]})
1'bx: out5=3'b000;
endcase
end
/*AUTO_CONSTANT (`temp) */
`define temp 3'b010
always @(/*AUTOSENSE*/in3) begin
outb6 = (in3 == `temp);
end
integer i;
reg [2:0] out7;
always @ (/*AUTOSENSE*/in1) begin
for (i=0; i<3; i=i+1) begin
assign out7[i] = ~in1[i];
end
end
always @ (/*AUTOSENSE*/in1 or in2 or in3) begin
{outw1 [ffs(in1)], outw2 [ffs(in2)]} = 2'b10;
{outw3[(|in1)?in2:in3], outb2} = 2'b10;
end
initial memarry[0] = in2;
always @ (/*AUTOSENSE*/ /*memory or*/ in1) begin
$display (memarry[in1]);
end
always @(/*AUTOSENSE*/in1 or in2)
casex(in1[1:0]) // synopsys full_case parallel_case
2'b01 : out8 = 3'b001;
2'b10 : out8 = 3'b010;
default
out8 = in2;
endcase
parameter READ = 3'b111,
//WRITE = 3'b111,
CFG = 3'b010;
//supply1 one;
always @(/*AUTOSENSE*/in1 or in2) begin
outb7 = (in1==READ) || (in2==CFG);
end
always @(/*AUTOSENSE*/in1) begin
if (|in1) $display("We're at %t\n",$time);
end // case: default
`define shift_instr 5'b01011
always @(/*AUTOSENSE*/in1 or in2 or in3 or in4 or in5 or outw1)
/*AUTO_CONSTANT(`shift_instr)*/
begin: label_no_sense
casex (outw1) // synopsys full_case parallel_case
{`shift_instr,3'bxxx}:
outb3 = in3[0];
8'b00001x10: outb3 = in4[0];
8'b00110011:
if (in5[0])
outb3 = in1[0];
else
outb3 = in2[1];
default
outb3 = in4[0];
endcase
end
parameter WIDLE = 0; // No Manual Write Burst
always @ (/*AUTOSENSE*/in1 or in2 or in3 or in4) begin
case(1'b1)
in2[WIDLE]:
outb4 = in1[0];
in3[in4]:
outb4 = in1[0];
default:
outb4 = 1'bx;
endcase
end
endmodule
module darren_jones_2 (/*AUTOARG*/
// Outputs
next_WSTATE,
// Inputs
WSTATE
);
input [1:0] WSTATE;
output [1:0] next_WSTATE;
reg [1:0] next_WSTATE;
parameter
WIDLE = 0, // No Manual Write Burst
WCB0 = 1; // 1st of the 4 Manual Write Burst
always @ (/*AUTOSENSE*/WSTATE) begin
next_WSTATE = 2'b0;
case (1'b1)
WSTATE[WIDLE]:
next_WSTATE[1'b0] = 1'b1;
WSTATE[WCB0]:
next_WSTATE[WCB0] = 1'b1;
endcase
end
endmodule
module darren_jones_3 (/*AUTOARG*/
// Outputs
var1,
// Inputs
state
);
input [2:1] state;
output var1;
reg var1;
parameter
IDLE = 1,
CAS1 = 2;
always @(/*AUTOSENSE*/state) begin
case (1'b1)
state[IDLE] : begin
var1 = 1'b1;
end
state[CAS1] : begin
var1 = 1'b1;
end
default : begin
var1 = 1'b1;
end
endcase
end
always @(/*AUTOSENSE*/add or lo or mc_32pff or mc_losel or slo or var1) begin
case(mc_losel)
6'b000001: lo_mux = mc_32pff ? {add[39:0],lo[31:8]} :
{add[7:0],lo[63:8]};
6'b010000: lo_mux = lo;
6'b100000: lo_mux = var1 ? IDLE : slo;
endcase
end // always @ (...
endmodule
|
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt4gxb
// ============================================================
// File Name: altpcie_serdes_2agx_x1d_gen1_16p.v
// Megafunction Name(s):
// alt4gxb
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 9.0 Internal Build 85 12/04/2008 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2008 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt4gxb CBX_AUTO_BLACKBOX="ALL" device_family="Arria II GX" effective_data_rate="2500 Mbps" elec_idle_infer_enable="false" enable_0ppm="true" enable_lc_tx_pll="false" equalizer_ctrl_a_setting=0 equalizer_ctrl_b_setting=0 equalizer_ctrl_c_setting=0 equalizer_ctrl_d_setting=0 equalizer_ctrl_v_setting=1 equalizer_dcgain_setting=1 gen_reconfig_pll="false" gxb_analog_power="2.5v" gxb_powerdown_width=1 input_clock_frequency="100 MHz" intended_device_speed_grade="4" intended_device_variant="ANY" loopback_mode="none" number_of_channels=1 number_of_quads=1 operation_mode="duplex" pll_control_width=1 preemphasis_ctrl_1stposttap_setting=9 preemphasis_ctrl_2ndposttap_inv_setting="false" preemphasis_ctrl_2ndposttap_setting=0 preemphasis_ctrl_pretap_inv_setting="false" preemphasis_ctrl_pretap_setting=0 protocol="pcie" receiver_termination="OCT_100_OHMS" reconfig_calibration="true" reconfig_dprio_mode=0 reconfig_fromgxb_port_width=17 reconfig_togxb_port_width=4 rx_8b_10b_mode="normal" rx_align_pattern="0101111100" rx_align_pattern_length=10 rx_allow_align_polarity_inversion="false" rx_allow_pipe_polarity_inversion="true" rx_bitslip_enable="false" rx_byte_ordering_mode="none" rx_cdrctrl_enable="true" rx_channel_bonding="indv" rx_channel_width=16 rx_common_mode="0.82v" rx_cru_bandwidth_type="medium" rx_cru_data_rate=800 rx_cru_inclock0_period=10000 rx_cru_m_divider=25 rx_cru_n_divider=2 rx_cru_vco_post_scale_divider=2 rx_data_rate=2500 rx_data_rate_remainder=0 rx_datapath_protocol="pipe" rx_digitalreset_port_width=1 rx_dwidth_factor=2 rx_enable_bit_reversal="false" rx_enable_lock_to_data_sig="false" rx_enable_lock_to_refclk_sig="false" rx_enable_self_test_mode="false" rx_force_signal_detect="true" rx_ppmselect=32 rx_rate_match_fifo_mode="normal" rx_rate_match_pattern1="11010000111010000011" rx_rate_match_pattern2="00101111000101111100" rx_rate_match_pattern_size=20 rx_run_length=40 rx_run_length_enable="true" rx_use_align_state_machine="true" rx_use_clkout="false" rx_use_coreclk="false" rx_use_cruclk="true" rx_use_deserializer_double_data_mode="false" rx_use_deskew_fifo="false" rx_use_double_data_mode="true" rx_use_pipe8b10binvpolarity="true" rx_use_rate_match_pattern1_only="false" rx_word_aligner_num_byte=1 starting_channel_number=0 transmitter_termination="OCT_100_OHMS" tx_8b_10b_mode="normal" tx_allow_polarity_inversion="false" tx_analog_power="1.5v" tx_channel_bonding="indv" tx_channel_width=16 tx_clkout_width=1 tx_common_mode="0.65v" tx_data_rate=2500 tx_data_rate_remainder=0 tx_digitalreset_port_width=1 tx_dwidth_factor=2 tx_enable_bit_reversal="false" tx_enable_self_test_mode="false" tx_pll_bandwidth_type="high" tx_pll_clock_post_divider=1 tx_pll_data_rate=800 tx_pll_inclk0_period=10000 tx_pll_m_divider=25 tx_pll_n_divider=2 tx_pll_vco_data_rate=800 tx_pll_vco_post_scale_divider=2 tx_slew_rate="off" tx_transmit_protocol="pipe" tx_use_coreclk="false" tx_use_double_data_mode="true" tx_use_serializer_double_data_mode="false" use_calibration_block="true" vod_ctrl_setting=2 cal_blk_clk gxb_powerdown pipe8b10binvpolarity pipedatavalid pipeelecidle pipephydonestatus pipestatus pll_inclk pll_locked powerdn reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_cruclk rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_freqlocked rx_patterndetect rx_pll_locked rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_detectrxloop tx_digitalreset tx_forcedispcompliance tx_forceelecidle
//VERSION_BEGIN 9.0 cbx_alt4gxb 2008:12:03:02:19:40:SJ cbx_mgl 2008:11:20:17:03:51:SJ cbx_tgx 2008:05:29:12:23:14:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = arriaii_hssi_calibration_block 1 arriaii_hssi_clock_divider 1 arriaii_hssi_cmu 1 arriaii_hssi_pll 2 arriaii_hssi_rx_pcs 1 arriaii_hssi_rx_pma 1 arriaii_hssi_tx_pcs 1 arriaii_hssi_tx_pma 1
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
module altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a
(
cal_blk_clk,
gxb_powerdown,
pipe8b10binvpolarity,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_inclk,
pll_locked,
powerdn,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle) ;
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [0:0] pipe8b10binvpolarity;
output [0:0] pipedatavalid;
output [0:0] pipeelecidle;
output [0:0] pipephydonestatus;
output [2:0] pipestatus;
input pll_inclk;
output [0:0] pll_locked;
input [1:0] powerdn;
input reconfig_clk;
output [16:0] reconfig_fromgxb;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
output [1:0] rx_ctrldetect;
input [0:0] rx_datain;
output [15:0] rx_dataout;
input [0:0] rx_digitalreset;
output [0:0] rx_freqlocked;
output [1:0] rx_patterndetect;
output [0:0] rx_pll_locked;
output [1:0] rx_syncstatus;
output [0:0] tx_clkout;
input [1:0] tx_ctrlenable;
input [15:0] tx_datain;
output [0:0] tx_dataout;
input [0:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [0:0] tx_forcedispcompliance;
input [0:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 cal_blk_clk;
tri0 [0:0] gxb_powerdown;
tri0 [0:0] pipe8b10binvpolarity;
tri0 pll_inclk;
tri0 [1:0] powerdn;
tri0 reconfig_clk;
tri0 [3:0] reconfig_togxb;
tri0 [0:0] rx_analogreset;
tri0 [0:0] rx_cruclk;
tri0 [0:0] rx_datain;
tri0 [0:0] rx_digitalreset;
tri0 [1:0] tx_ctrlenable;
tri0 [15:0] tx_datain;
tri0 [0:0] tx_detectrxloop;
tri0 [0:0] tx_digitalreset;
tri0 [0:0] tx_forcedispcompliance;
tri0 [0:0] tx_forceelecidle;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire wire_cal_blk0_nonusertocmu;
wire [1:0] wire_ch_clk_div0_analogfastrefclkout;
wire [1:0] wire_ch_clk_div0_analogrefclkout;
wire wire_ch_clk_div0_analogrefclkpulse;
wire wire_cent_unit0_dprioout;
wire [1:0] wire_cent_unit0_pllpowerdn;
wire [1:0] wire_cent_unit0_pllresetout;
wire wire_cent_unit0_quadresetout;
wire [5:0] wire_cent_unit0_rxanalogresetout;
wire [5:0] wire_cent_unit0_rxcrupowerdown;
wire [5:0] wire_cent_unit0_rxcruresetout;
wire [3:0] wire_cent_unit0_rxdigitalresetout;
wire [5:0] wire_cent_unit0_rxibpowerdown;
wire [5:0] wire_cent_unit0_txanalogresetout;
wire [3:0] wire_cent_unit0_txctrlout;
wire [31:0] wire_cent_unit0_txdataout;
wire [5:0] wire_cent_unit0_txdetectrxpowerdown;
wire [3:0] wire_cent_unit0_txdigitalresetout;
wire [5:0] wire_cent_unit0_txobpowerdown;
wire [3:0] wire_rx_cdr_pll0_clk;
wire [1:0] wire_rx_cdr_pll0_dataout;
wire wire_rx_cdr_pll0_freqlocked;
wire wire_rx_cdr_pll0_locked;
wire wire_rx_cdr_pll0_pfdrefclkout;
wire [3:0] wire_tx_pll0_clk;
wire wire_tx_pll0_locked;
wire wire_receive_pcs0_cdrctrllocktorefclkout;
wire [3:0] wire_receive_pcs0_ctrldetect;
wire [39:0] wire_receive_pcs0_dataout;
wire [3:0] wire_receive_pcs0_patterndetect;
wire wire_receive_pcs0_pipedatavalid;
wire wire_receive_pcs0_pipeelecidle;
wire wire_receive_pcs0_pipephydonestatus;
wire wire_receive_pcs0_pipestatetransdoneout;
wire [2:0] wire_receive_pcs0_pipestatus;
wire [19:0] wire_receive_pcs0_revparallelfdbkdata;
wire wire_receive_pcs0_signaldetect;
wire [3:0] wire_receive_pcs0_syncstatus;
wire [7:0] wire_receive_pma0_analogtestbus;
wire wire_receive_pma0_clockout;
wire wire_receive_pma0_dataout;
wire wire_receive_pma0_locktorefout;
wire [63:0] wire_receive_pma0_recoverdataout;
wire wire_receive_pma0_signaldetect;
wire wire_transmit_pcs0_clkout;
wire [19:0] wire_transmit_pcs0_dataout;
wire wire_transmit_pcs0_forceelecidleout;
wire [2:0] wire_transmit_pcs0_grayelecidleinferselout;
wire [1:0] wire_transmit_pcs0_pipepowerdownout;
wire [3:0] wire_transmit_pcs0_pipepowerstateout;
wire wire_transmit_pcs0_txdetectrx;
wire wire_transmit_pma0_clockout;
wire wire_transmit_pma0_dataout;
wire wire_transmit_pma0_rxdetectvalidout;
wire wire_transmit_pma0_rxfoundout;
wire [1:0] analogfastrefclkout;
wire [1:0] analogrefclkout;
wire [0:0] analogrefclkpulse;
wire cal_blk_powerdown;
wire [1:0] cent_unit_pllpowerdn;
wire [1:0] cent_unit_pllresetout;
wire [0:0] cent_unit_quadresetout;
wire [5:0] cent_unit_rxcrupowerdn;
wire [5:0] cent_unit_rxibpowerdn;
wire [31:0] cent_unit_tx_xgmdataout;
wire [3:0] cent_unit_txctrlout;
wire [5:0] cent_unit_txdetectrxpowerdn;
wire [5:0] cent_unit_txobpowerdn;
wire [5:0] fixedclk_to_cmu;
wire [2:0] grayelecidleinfersel_from_tx;
wire [0:0] nonusertocmu_out;
wire [0:0] pipedatavalid_out;
wire [0:0] pipeelecidle_out;
wire [9:0] pll0_clkin;
wire [3:0] pll0_out;
wire [1:0] pll_ch_dataout_wire;
wire [0:0] pll_inclk_wire;
wire [0:0] pll_locked_out;
wire [0:0] pll_powerdown;
wire [1:0] pllpowerdn_in;
wire [1:0] pllreset_in;
wire [0:0] reconfig_togxb_busy;
wire [5:0] rx_analogreset_in;
wire [5:0] rx_analogreset_out;
wire [0:0] rx_coreclk_in;
wire [8:0] rx_cruclk_in;
wire [3:0] rx_deserclock_in;
wire [3:0] rx_digitalreset_in;
wire [3:0] rx_digitalreset_out;
wire [2:0] rx_elecidleinfersel;
wire [0:0] rx_enapatternalign;
wire [0:0] rx_freqlocked_wire;
wire [0:0] rx_locktodata;
wire [0:0] rx_locktodata_wire;
wire [0:0] rx_locktorefclk_wire;
wire [15:0] rx_out_wire;
wire [1:0] rx_pcs_rxfound_wire;
wire [1599:0] rx_pcsdprioin_wire;
wire [0:0] rx_phfifordenable;
wire [0:0] rx_phfiforeset;
wire [0:0] rx_phfifowrdisable;
wire [0:0] rx_pipestatetransdoneout;
wire [0:0] rx_pldcruclk_in;
wire [3:0] rx_pll_clkout;
wire [0:0] rx_pll_pfdrefclkout_wire;
wire [0:0] rx_plllocked_wire;
wire [16:0] rx_pma_analogtestbus;
wire [0:0] rx_pma_clockout;
wire [0:0] rx_pma_dataout;
wire [0:0] rx_pma_locktorefout;
wire [19:0] rx_pma_recoverdataout_wire;
wire [1799:0] rx_pmadprioin_wire;
wire [0:0] rx_powerdown;
wire [5:0] rx_powerdown_in;
wire [0:0] rx_prbscidenable;
wire [19:0] rx_revparallelfdbkdata;
wire [0:0] rx_rmfiforeset;
wire [5:0] rx_rxcruresetout;
wire [0:0] rx_signaldetect_wire;
wire [5:0] tx_analogreset_out;
wire [0:0] tx_clkout_int_wire;
wire [0:0] tx_core_clkout_wire;
wire [0:0] tx_coreclk_in;
wire [15:0] tx_datain_wire;
wire [43:0] tx_datainfull;
wire [19:0] tx_dataout_pcs_to_pma;
wire [3:0] tx_digitalreset_in;
wire [3:0] tx_digitalreset_out;
wire [1199:0] tx_dprioin_wire;
wire [1:0] tx_forcedisp_wire;
wire [0:0] tx_invpolarity;
wire [0:0] tx_localrefclk;
wire [0:0] tx_pcs_forceelecidleout;
wire [0:0] tx_phfiforeset;
wire [0:0] tx_pipedeemph;
wire [2:0] tx_pipemargin;
wire [1:0] tx_pipepowerdownout;
wire [3:0] tx_pipepowerstateout;
wire [0:0] tx_pipeswing;
wire [1799:0] tx_pmadprioin_wire;
wire [0:0] tx_revparallellpbken;
wire [0:0] tx_rxdetectvalidout;
wire [0:0] tx_rxfoundout;
wire [0:0] txdetectrxout;
arriaii_hssi_calibration_block cal_blk0
(
.calibrationstatus(),
.clk(cal_blk_clk),
.enabletestbus(1'b1),
.nonusertocmu(wire_cal_blk0_nonusertocmu),
.powerdn(cal_blk_powerdown)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.testctrl(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
arriaii_hssi_clock_divider ch_clk_div0
(
.analogfastrefclkout(wire_ch_clk_div0_analogfastrefclkout),
.analogfastrefclkoutshifted(),
.analogrefclkout(wire_ch_clk_div0_analogrefclkout),
.analogrefclkoutshifted(),
.analogrefclkpulse(wire_ch_clk_div0_analogrefclkpulse),
.analogrefclkpulseshifted(),
.clk0in(pll0_out[3:0]),
.coreclkout(),
.dpriodisable(1'b1),
.dprioout(),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchbaseclock(),
.rateswitchdone(),
.rateswitchout(),
.refclkout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.clk1in({4{1'b0}}),
.dprioin({100{1'b0}}),
.powerdn(1'b0),
.rateswitch(1'b0),
.rateswitchbaseclkin({2{1'b0}}),
.rateswitchdonein({2{1'b0}}),
.refclkdig(1'b0),
.refclkin({2{1'b0}}),
.vcobypassin(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
ch_clk_div0.channel_num = ((starting_channel_number + 0) % 4),
ch_clk_div0.data_rate = 800,
ch_clk_div0.divide_by = 5,
ch_clk_div0.divider_type = "CHANNEL_REGULAR",
ch_clk_div0.dprio_config_mode = 6'h00,
ch_clk_div0.effective_data_rate = "2500 Mbps",
ch_clk_div0.enable_dynamic_divider = "false",
ch_clk_div0.enable_refclk_out = "false",
ch_clk_div0.inclk_select = 0,
ch_clk_div0.logical_channel_address = (starting_channel_number + 0),
ch_clk_div0.pre_divide_by = 1,
ch_clk_div0.select_local_rate_switch_done = "false",
ch_clk_div0.sim_analogfastrefclkout_phase_shift = 0,
ch_clk_div0.sim_analogrefclkout_phase_shift = 0,
ch_clk_div0.sim_coreclkout_phase_shift = 0,
ch_clk_div0.sim_refclkout_phase_shift = 0,
ch_clk_div0.use_coreclk_out_post_divider = "true",
ch_clk_div0.use_refclk_post_divider = "false",
ch_clk_div0.use_vco_bypass = "false",
ch_clk_div0.lpm_type = "arriaii_hssi_clock_divider";
arriaii_hssi_cmu cent_unit0
(
.adet({4{1'b0}}),
.alignstatus(),
.autospdx4configsel(),
.autospdx4rateswitchout(),
.autospdx4spdchg(),
.clkdivpowerdn(),
.cmudividerdprioin({600{1'b0}}),
.cmudividerdprioout(),
.cmuplldprioin({1800{1'b0}}),
.cmuplldprioout(),
.digitaltestout(),
.dpclk(reconfig_clk),
.dpriodisable(1'b1),
.dpriodisableout(),
.dprioin(1'b0),
.dprioload(1'b0),
.dpriooe(),
.dprioout(wire_cent_unit0_dprioout),
.enabledeskew(),
.extra10gout(),
.fiforesetrd(),
.fixedclk({{5{1'b0}}, fixedclk_to_cmu[0]}),
.lccmutestbus(),
.nonuserfromcal(nonusertocmu_out[0]),
.phfifiox4ptrsreset(),
.pllpowerdn(wire_cent_unit0_pllpowerdn),
.pllresetout(wire_cent_unit0_pllresetout),
.quadreset(gxb_powerdown[0]),
.quadresetout(wire_cent_unit0_quadresetout),
.rdalign({4{1'b0}}),
.rdenablesync(1'b0),
.recovclk(1'b0),
.refclkdividerdprioin({2{1'b0}}),
.refclkdividerdprioout(),
.rxadcepowerdown(),
.rxadceresetout(),
.rxanalogreset({{2{1'b0}}, rx_analogreset_in[3:0]}),
.rxanalogresetout(wire_cent_unit0_rxanalogresetout),
.rxcrupowerdown(wire_cent_unit0_rxcrupowerdown),
.rxcruresetout(wire_cent_unit0_rxcruresetout),
.rxctrl({4{1'b0}}),
.rxctrlout(),
.rxdatain({32{1'b0}}),
.rxdataout(),
.rxdatavalid({4{1'b0}}),
.rxdigitalreset(rx_digitalreset_in[3:0]),
.rxdigitalresetout(wire_cent_unit0_rxdigitalresetout),
.rxibpowerdown(wire_cent_unit0_rxibpowerdown),
.rxpcsdprioin({1600{1'b0}}),
.rxpcsdprioout(),
.rxphfifox4byteselout(),
.rxphfifox4rdenableout(),
.rxphfifox4wrclkout(),
.rxphfifox4wrenableout(),
.rxpmadprioin({1800{1'b0}}),
.rxpmadprioout(),
.rxpowerdown({{2{1'b0}}, rx_powerdown_in[3:0]}),
.rxrunningdisp({4{1'b0}}),
.scanout(),
.syncstatus({4{1'b0}}),
.testout(),
.txanalogresetout(wire_cent_unit0_txanalogresetout),
.txctrl({4{1'b0}}),
.txctrlout(wire_cent_unit0_txctrlout),
.txdatain({32{1'b0}}),
.txdataout(wire_cent_unit0_txdataout),
.txdetectrxpowerdown(wire_cent_unit0_txdetectrxpowerdown),
.txdigitalreset(tx_digitalreset_in[3:0]),
.txdigitalresetout(wire_cent_unit0_txdigitalresetout),
.txdividerpowerdown(),
.txobpowerdown(wire_cent_unit0_txobpowerdown),
.txpcsdprioin({600{1'b0}}),
.txpcsdprioout(),
.txphfifox4byteselout(),
.txphfifox4rdclkout(),
.txphfifox4rdenableout(),
.txphfifox4wrenableout(),
.txpllreset({{1{1'b0}}, pll_powerdown[0]}),
.txpmadprioin({1800{1'b0}}),
.txpmadprioout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.extra10gin({7{1'b0}}),
.lccmurtestbussel({3{1'b0}}),
.pmacramtest(1'b0),
.rateswitch(1'b0),
.rateswitchdonein(1'b0),
.rxclk(1'b0),
.rxcoreclk(1'b0),
.rxphfifordenable(1'b1),
.rxphfiforeset(1'b0),
.rxphfifowrdisable(1'b0),
.scanclk(1'b0),
.scanin({23{1'b0}}),
.scanmode(1'b0),
.scanshift(1'b0),
.testin({10000{1'b0}}),
.txclk(1'b0),
.txcoreclk(1'b0),
.txphfiforddisable(1'b0),
.txphfiforeset(1'b0),
.txphfifowrenable(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
cent_unit0.auto_spd_deassert_ph_fifo_rst_count = 8,
cent_unit0.auto_spd_phystatus_notify_count = 14,
cent_unit0.bonded_quad_mode = "none",
cent_unit0.devaddr = ((((starting_channel_number / 4) + 0) % 32) + 1),
cent_unit0.in_xaui_mode = "false",
cent_unit0.offset_all_errors_align = "false",
cent_unit0.pipe_auto_speed_nego_enable = "false",
cent_unit0.pipe_freq_scale_mode = "Frequency",
cent_unit0.pma_done_count = 250000,
cent_unit0.portaddr = (((starting_channel_number + 0) / 128) + 1),
cent_unit0.rx0_auto_spd_self_switch_enable = "false",
cent_unit0.rx0_channel_bonding = "none",
cent_unit0.rx0_clk1_mux_select = "recovered clock",
cent_unit0.rx0_clk2_mux_select = "local reference clock",
cent_unit0.rx0_ph_fifo_reg_mode = "false",
cent_unit0.rx0_rd_clk_mux_select = "core clock",
cent_unit0.rx0_recovered_clk_mux_select = "recovered clock",
cent_unit0.rx0_reset_clock_output_during_digital_reset = "false",
cent_unit0.rx0_use_double_data_mode = "true",
cent_unit0.tx0_auto_spd_self_switch_enable = "false",
cent_unit0.tx0_channel_bonding = "none",
cent_unit0.tx0_ph_fifo_reg_mode = "false",
cent_unit0.tx0_rd_clk_mux_select = "cmu_clock_divider",
cent_unit0.tx0_use_double_data_mode = "true",
cent_unit0.tx0_wr_clk_mux_select = "core_clk",
cent_unit0.use_deskew_fifo = "false",
cent_unit0.vcceh_voltage = "2.5V",
cent_unit0.lpm_type = "arriaii_hssi_cmu";
arriaii_hssi_pll rx_cdr_pll0
(
.areset(rx_rxcruresetout[0]),
.clk(wire_rx_cdr_pll0_clk),
.datain(rx_pma_dataout[0]),
.dataout(wire_rx_cdr_pll0_dataout),
.dpriodisable(1'b1),
.dprioout(),
.freqlocked(wire_rx_cdr_pll0_freqlocked),
.inclk({{1{1'b0}}, rx_cruclk_in[8:0]}),
.locked(wire_rx_cdr_pll0_locked),
.locktorefclk(rx_pma_locktorefout[0]),
.pfdfbclkout(),
.pfdrefclkout(wire_rx_cdr_pll0_pfdrefclkout),
.powerdown(cent_unit_rxcrupowerdn[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.dprioin({300{1'b0}}),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rx_cdr_pll0.bandwidth_type = "Medium",
rx_cdr_pll0.channel_num = ((starting_channel_number + 0) % 4),
rx_cdr_pll0.dprio_config_mode = 6'h00,
rx_cdr_pll0.effective_data_rate = "2500 Mbps",
rx_cdr_pll0.inclk0_input_period = 10000,
rx_cdr_pll0.input_clock_frequency = "100 MHz",
rx_cdr_pll0.m = 25,
rx_cdr_pll0.n = 2,
rx_cdr_pll0.pfd_clk_select = 0,
rx_cdr_pll0.pll_type = "RX CDR",
rx_cdr_pll0.protocol_hint = "pcie",
rx_cdr_pll0.use_refclk_pin = "false",
rx_cdr_pll0.vco_data_rate = 800,
rx_cdr_pll0.vco_post_scale = 2,
rx_cdr_pll0.lpm_type = "arriaii_hssi_pll";
arriaii_hssi_pll tx_pll0
(
.areset(pllreset_in[0]),
.clk(wire_tx_pll0_clk),
.dataout(),
.dpriodisable(1'b1),
.dprioout(),
.freqlocked(),
.inclk({pll0_clkin[9:0]}),
.locked(wire_tx_pll0_locked),
.pfdfbclkout(),
.pfdrefclkout(),
.powerdown(pllpowerdn_in[0]),
.vcobypassout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datain(1'b0),
.dprioin({300{1'b0}}),
.earlyeios(1'b0),
.extra10gin({6{1'b0}}),
.locktorefclk(1'b1),
.pfdfbclk(1'b0),
.rateswitch(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
tx_pll0.bandwidth_type = "High",
tx_pll0.channel_num = 4,
tx_pll0.dprio_config_mode = 6'h00,
tx_pll0.inclk0_input_period = 10000,
tx_pll0.input_clock_frequency = "100 MHz",
tx_pll0.m = 25,
tx_pll0.n = 2,
tx_pll0.pfd_clk_select = 0,
tx_pll0.pfd_fb_select = "internal",
tx_pll0.pll_type = "CMU",
tx_pll0.protocol_hint = "pcie",
tx_pll0.use_refclk_pin = "false",
tx_pll0.vco_data_rate = 800,
tx_pll0.vco_post_scale = 2,
tx_pll0.lpm_type = "arriaii_hssi_pll";
arriaii_hssi_rx_pcs receive_pcs0
(
.a1a2size(1'b0),
.a1a2sizeout(),
.a1detect(),
.a2detect(),
.adetectdeskew(),
.alignstatus(1'b0),
.alignstatussync(1'b0),
.alignstatussyncout(),
.autospdrateswitchout(),
.autospdspdchgout(),
.bistdone(),
.bisterr(),
.bitslipboundaryselectout(),
.byteorderalignstatus(),
.cdrctrlearlyeios(),
.cdrctrllocktorefclkout(wire_receive_pcs0_cdrctrllocktorefclkout),
.clkout(),
.coreclk(rx_coreclk_in[0]),
.coreclkout(),
.ctrldetect(wire_receive_pcs0_ctrldetect),
.datain(rx_pma_recoverdataout_wire[19:0]),
.dataout(wire_receive_pcs0_dataout),
.dataoutfull(),
.digitalreset(rx_digitalreset_out[0]),
.digitaltestout(),
.disablefifordin(1'b0),
.disablefifordout(),
.disablefifowrin(1'b0),
.disablefifowrout(),
.disperr(),
.dpriodisable(1'b1),
.dprioin(rx_pcsdprioin_wire[399:0]),
.dprioout(),
.elecidleinfersel({3{1'b0}}),
.enabledeskew(1'b0),
.enabyteord(1'b0),
.enapatternalign(rx_enapatternalign[0]),
.errdetect(),
.fifordin(1'b0),
.fifordout(),
.fiforesetrd(1'b0),
.grayelecidleinferselfromtx(grayelecidleinfersel_from_tx[2:0]),
.hipdataout(),
.hipdatavalid(),
.hipelecidle(),
.hipphydonestatus(),
.hipstatus(),
.invpol(1'b0),
.iqpphfifobyteselout(),
.iqpphfifoptrsresetout(),
.iqpphfifordenableout(),
.iqpphfifowrclkout(),
.iqpphfifowrenableout(),
.k1detect(),
.k2detect(),
.localrefclk(tx_localrefclk[0]),
.masterclk(1'b0),
.parallelfdbk({20{1'b0}}),
.patterndetect(wire_receive_pcs0_patterndetect),
.phfifobyteselout(),
.phfifobyteserdisableout(),
.phfifooverflow(),
.phfifoptrsresetout(),
.phfifordenable(rx_phfifordenable[0]),
.phfifordenableout(),
.phfiforeset(rx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrclkout(),
.phfifowrdisable(rx_phfifowrdisable[0]),
.phfifowrdisableout(),
.phfifowrenableout(),
.pipe8b10binvpolarity(pipe8b10binvpolarity[0]),
.pipebufferstat(),
.pipedatavalid(wire_receive_pcs0_pipedatavalid),
.pipeelecidle(wire_receive_pcs0_pipeelecidle),
.pipephydonestatus(wire_receive_pcs0_pipephydonestatus),
.pipepowerdown(tx_pipepowerdownout[1:0]),
.pipepowerstate(tx_pipepowerstateout[3:0]),
.pipestatetransdoneout(wire_receive_pcs0_pipestatetransdoneout),
.pipestatus(wire_receive_pcs0_pipestatus),
.powerdn(powerdn[1:0]),
.prbscidenable(rx_prbscidenable[0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdalign(),
.recoveredclk(rx_pma_clockout[0]),
.revbitorderwa(1'b0),
.revbyteorderwa(1'b0),
.revparallelfdbkdata(wire_receive_pcs0_revparallelfdbkdata),
.rlv(),
.rmfifoalmostempty(),
.rmfifoalmostfull(),
.rmfifodatadeleted(),
.rmfifodatainserted(),
.rmfifoempty(),
.rmfifofull(),
.rmfifordena(1'b0),
.rmfiforeset(rx_rmfiforeset[0]),
.rmfifowrena(1'b0),
.runningdisp(),
.rxdetectvalid(tx_rxdetectvalidout[0]),
.rxfound(rx_pcs_rxfound_wire[1:0]),
.signaldetect(wire_receive_pcs0_signaldetect),
.signaldetected(rx_signaldetect_wire[0]),
.syncstatus(wire_receive_pcs0_syncstatus),
.syncstatusdeskew(),
.xauidelcondmetout(),
.xauififoovrout(),
.xauiinsertincompleteout(),
.xauilatencycompout(),
.xgmctrldet(),
.xgmctrlin(1'b0),
.xgmdatain({8{1'b0}}),
.xgmdataout(),
.xgmdatavalid(),
.xgmrunningdisp()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.autospdxnconfigsel({3{1'b0}}),
.autospdxnspdchg({3{1'b0}}),
.bitslip(1'b0),
.cdrctrllocktorefcl(1'b0),
.hip8b10binvpolarity(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hippowerdown({2{1'b0}}),
.hiprateswitch(1'b0),
.iqpautospdxnspgchg({2{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnptrsreset({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrclk({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifox4bytesel(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrclk(1'b0),
.phfifox4wrenable(1'b0),
.phfifox8bytesel(1'b0),
.phfifox8rdenable(1'b0),
.phfifox8wrclk(1'b0),
.phfifox8wrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxnwrclk({3{1'b0}}),
.phfifoxnwrenable({3{1'b0}}),
.pipeenrevparallellpbkfromtx(1'b0),
.pmatestbusin({8{1'b0}}),
.ppmdetectdividedclk(1'b0),
.ppmdetectrefclk(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0),
.rxelecidlerateswitch(1'b0),
.xauidelcondmet(1'b0),
.xauififoovr(1'b0),
.xauiinsertincomplete(1'b0),
.xauilatencycomp(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pcs0.align_pattern = "0101111100",
receive_pcs0.align_pattern_length = 10,
receive_pcs0.align_to_deskew_pattern_pos_disp_only = "false",
receive_pcs0.allow_align_polarity_inversion = "false",
receive_pcs0.allow_pipe_polarity_inversion = "true",
receive_pcs0.auto_spd_deassert_ph_fifo_rst_count = 8,
receive_pcs0.auto_spd_phystatus_notify_count = 14,
receive_pcs0.auto_spd_self_switch_enable = "false",
receive_pcs0.bit_slip_enable = "false",
receive_pcs0.byte_order_mode = "none",
receive_pcs0.byte_order_pad_pattern = "0",
receive_pcs0.byte_order_pattern = "0",
receive_pcs0.byte_order_pld_ctrl_enable = "false",
receive_pcs0.cdrctrl_bypass_ppm_detector_cycle = 1000,
receive_pcs0.cdrctrl_enable = "true",
receive_pcs0.cdrctrl_mask_cycle = 800,
receive_pcs0.cdrctrl_min_lock_to_ref_cycle = 63,
receive_pcs0.cdrctrl_rxvalid_mask = "true",
receive_pcs0.channel_bonding = "none",
receive_pcs0.channel_number = ((starting_channel_number + 0) % 4),
receive_pcs0.channel_width = 16,
receive_pcs0.clk1_mux_select = "recovered clock",
receive_pcs0.clk2_mux_select = "local reference clock",
receive_pcs0.core_clock_0ppm = "false",
receive_pcs0.datapath_low_latency_mode = "false",
receive_pcs0.datapath_protocol = "pipe",
receive_pcs0.dec_8b_10b_compatibility_mode = "true",
receive_pcs0.dec_8b_10b_mode = "normal",
receive_pcs0.dec_8b_10b_polarity_inv_enable = "true",
receive_pcs0.deskew_pattern = "0",
receive_pcs0.disable_auto_idle_insertion = "false",
receive_pcs0.disable_running_disp_in_word_align = "false",
receive_pcs0.disallow_kchar_after_pattern_ordered_set = "false",
receive_pcs0.dprio_config_mode = 6'h00,
receive_pcs0.elec_idle_infer_enable = "false",
receive_pcs0.elec_idle_num_com_detect = 3,
receive_pcs0.enable_bit_reversal = "false",
receive_pcs0.enable_deep_align = "false",
receive_pcs0.enable_deep_align_byte_swap = "false",
receive_pcs0.enable_self_test_mode = "false",
receive_pcs0.enable_true_complement_match_in_word_align = "false",
receive_pcs0.force_signal_detect_dig = "true",
receive_pcs0.hip_enable = "false",
receive_pcs0.infiniband_invalid_code = 0,
receive_pcs0.insert_pad_on_underflow = "false",
receive_pcs0.logical_channel_address = (starting_channel_number + 0),
receive_pcs0.num_align_code_groups_in_ordered_set = 0,
receive_pcs0.num_align_cons_good_data = 16,
receive_pcs0.num_align_cons_pat = 4,
receive_pcs0.num_align_loss_sync_error = 17,
receive_pcs0.ph_fifo_low_latency_enable = "true",
receive_pcs0.ph_fifo_reg_mode = "false",
receive_pcs0.ph_fifo_xn_mapping0 = "none",
receive_pcs0.ph_fifo_xn_mapping1 = "none",
receive_pcs0.ph_fifo_xn_mapping2 = "none",
receive_pcs0.ph_fifo_xn_select = 1,
receive_pcs0.pipe_auto_speed_nego_enable = "false",
receive_pcs0.pipe_freq_scale_mode = "Frequency",
receive_pcs0.pma_done_count = 250000,
receive_pcs0.protocol_hint = "pcie",
receive_pcs0.rate_match_almost_empty_threshold = 11,
receive_pcs0.rate_match_almost_full_threshold = 13,
receive_pcs0.rate_match_back_to_back = "false",
receive_pcs0.rate_match_delete_threshold = 6,
receive_pcs0.rate_match_empty_threshold = 5,
receive_pcs0.rate_match_fifo_mode = "true",
receive_pcs0.rate_match_full_threshold = 20,
receive_pcs0.rate_match_insert_threshold = 0,
receive_pcs0.rate_match_ordered_set_based = "false",
receive_pcs0.rate_match_pattern1 = "11010000111010000011",
receive_pcs0.rate_match_pattern2 = "00101111000101111100",
receive_pcs0.rate_match_pattern_size = 20,
receive_pcs0.rate_match_reset_enable = "false",
receive_pcs0.rate_match_skip_set_based = "true",
receive_pcs0.rate_match_start_threshold = 0,
receive_pcs0.rd_clk_mux_select = "core clock",
receive_pcs0.recovered_clk_mux_select = "recovered clock",
receive_pcs0.run_length = 40,
receive_pcs0.run_length_enable = "true",
receive_pcs0.rx_detect_bypass = "false",
receive_pcs0.rxstatus_error_report_mode = 0,
receive_pcs0.self_test_mode = "incremental",
receive_pcs0.use_alignment_state_machine = "true",
receive_pcs0.use_deserializer_double_data_mode = "false",
receive_pcs0.use_deskew_fifo = "false",
receive_pcs0.use_double_data_mode = "true",
receive_pcs0.use_parallel_loopback = "false",
receive_pcs0.use_rising_edge_triggered_pattern_align = "false",
receive_pcs0.lpm_type = "arriaii_hssi_rx_pcs";
arriaii_hssi_rx_pma receive_pma0
(
.adaptdone(),
.analogtestbus(wire_receive_pma0_analogtestbus),
.clockout(wire_receive_pma0_clockout),
.datain(rx_datain[0]),
.dataout(wire_receive_pma0_dataout),
.dataoutfull(),
.deserclock(rx_deserclock_in[3:0]),
.dpriodisable(1'b1),
.dprioin(rx_pmadprioin_wire[299:0]),
.dprioout(),
.freqlock(1'b0),
.ignorephslck(1'b0),
.locktodata(rx_locktodata_wire[0]),
.locktoref(rx_locktorefclk_wire[0]),
.locktorefout(wire_receive_pma0_locktorefout),
.offsetcancellationen(1'b0),
.plllocked(rx_plllocked_wire[0]),
.powerdn(cent_unit_rxibpowerdn[0]),
.ppmdetectclkrel(),
.ppmdetectrefclk(rx_pll_pfdrefclkout_wire[0]),
.recoverdatain(pll_ch_dataout_wire[1:0]),
.recoverdataout(wire_receive_pma0_recoverdataout),
.reverselpbkout(),
.revserialfdbkout(),
.rxpmareset(rx_analogreset_out[0]),
.seriallpbken(1'b0),
.seriallpbkin(1'b0),
.signaldetect(wire_receive_pma0_signaldetect)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.adaptcapture(1'b0),
.adcepowerdn(1'b0),
.adcereset(1'b0),
.adcestandby(1'b0),
.extra10gin({38{1'b0}}),
.ppmdetectdividedclk(1'b0),
.testbussel({4{1'b0}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
receive_pma0.allow_serial_loopback = "false",
receive_pma0.channel_number = ((starting_channel_number + 0) % 4),
receive_pma0.channel_type = "auto",
receive_pma0.common_mode = "0.82V",
receive_pma0.deserialization_factor = 10,
receive_pma0.dprio_config_mode = 6'h00,
receive_pma0.enable_ltd = "false",
receive_pma0.enable_ltr = "false",
receive_pma0.eq_dc_gain = 3,
receive_pma0.eqa_ctrl = 0,
receive_pma0.eqb_ctrl = 0,
receive_pma0.eqc_ctrl = 0,
receive_pma0.eqd_ctrl = 0,
receive_pma0.eqv_ctrl = 1,
receive_pma0.force_signal_detect = "true",
receive_pma0.logical_channel_address = (starting_channel_number + 0),
receive_pma0.low_speed_test_select = 0,
receive_pma0.offset_cancellation = 1,
receive_pma0.ppmselect = 32,
receive_pma0.protocol_hint = "pcie",
receive_pma0.send_direct_reverse_serial_loopback = "None",
receive_pma0.signal_detect_hysteresis_valid_threshold = 2,
receive_pma0.signal_detect_loss_threshold = 4,
receive_pma0.termination = "OCT 100 Ohms",
receive_pma0.use_deser_double_data_width = "false",
receive_pma0.use_pma_direct = "false",
receive_pma0.lpm_type = "arriaii_hssi_rx_pma";
arriaii_hssi_tx_pcs transmit_pcs0
(
.clkout(wire_transmit_pcs0_clkout),
.coreclk(tx_coreclk_in[0]),
.coreclkout(),
.ctrlenable({{2{1'b0}}, tx_ctrlenable[1:0]}),
.datain({{24{1'b0}}, tx_datain_wire[15:0]}),
.datainfull({tx_datainfull[43:0]}),
.dataout(wire_transmit_pcs0_dataout),
.detectrxloop(tx_detectrxloop[0]),
.digitalreset(tx_digitalreset_out[0]),
.dispval({{3{1'b0}}, tx_forceelecidle[0]}),
.dpriodisable(1'b1),
.dprioin(tx_dprioin_wire[149:0]),
.dprioout(),
.elecidleinfersel(rx_elecidleinfersel[2:0]),
.enrevparallellpbk(tx_revparallellpbken[0]),
.forcedisp({{2{1'b0}}, tx_forcedisp_wire[1:0]}),
.forcedispcompliance(1'b0),
.forceelecidle(tx_forceelecidle[0]),
.forceelecidleout(wire_transmit_pcs0_forceelecidleout),
.grayelecidleinferselout(wire_transmit_pcs0_grayelecidleinferselout),
.hiptxclkout(),
.invpol(tx_invpolarity[0]),
.iqpphfifobyteselout(),
.iqpphfifordclkout(),
.iqpphfifordenableout(),
.iqpphfifowrenableout(),
.localrefclk(tx_localrefclk[0]),
.parallelfdbkout(),
.phfifobyteselout(),
.phfifooverflow(),
.phfifordclkout(),
.phfiforddisable(1'b0),
.phfiforddisableout(),
.phfifordenableout(),
.phfiforeset(tx_phfiforeset[0]),
.phfiforesetout(),
.phfifounderflow(),
.phfifowrenable(1'b1),
.phfifowrenableout(),
.pipeenrevparallellpbkout(),
.pipepowerdownout(wire_transmit_pcs0_pipepowerdownout),
.pipepowerstateout(wire_transmit_pcs0_pipepowerstateout),
.pipestatetransdone(rx_pipestatetransdoneout[0]),
.pipetxdeemph(tx_pipedeemph[0]),
.pipetxmargin(tx_pipemargin[2:0]),
.pipetxswing(tx_pipeswing[0]),
.powerdn(powerdn[1:0]),
.quadreset(cent_unit_quadresetout[0]),
.rateswitchout(),
.rdenablesync(),
.revparallelfdbk(rx_revparallelfdbkdata[19:0]),
.txdetectrx(wire_transmit_pcs0_txdetectrx),
.xgmctrl(cent_unit_txctrlout[0]),
.xgmctrlenable(),
.xgmdatain(cent_unit_tx_xgmdataout[7:0]),
.xgmdataout()
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.bitslipboundaryselect({5{1'b0}}),
.freezptr(1'b0),
.hipdatain({10{1'b0}}),
.hipdetectrxloop(1'b0),
.hipelecidleinfersel({3{1'b0}}),
.hipforceelecidle(1'b0),
.hippowerdn({2{1'b0}}),
.hiptxdeemph(1'b0),
.hiptxmargin({3{1'b0}}),
.iqpphfifoxnbytesel({2{1'b0}}),
.iqpphfifoxnrdclk({2{1'b0}}),
.iqpphfifoxnrdenable({2{1'b0}}),
.iqpphfifoxnwrenable({2{1'b0}}),
.phfifobyteserdisable(1'b0),
.phfifoptrsreset(1'b0),
.phfifox4bytesel(1'b0),
.phfifox4rdclk(1'b0),
.phfifox4rdenable(1'b0),
.phfifox4wrenable(1'b0),
.phfifoxnbottombytesel(1'b0),
.phfifoxnbottomrdclk(1'b0),
.phfifoxnbottomrdenable(1'b0),
.phfifoxnbottomwrenable(1'b0),
.phfifoxnbytesel({3{1'b0}}),
.phfifoxnptrsreset({3{1'b0}}),
.phfifoxnrdclk({3{1'b0}}),
.phfifoxnrdenable({3{1'b0}}),
.phfifoxntopbytesel(1'b0),
.phfifoxntoprdclk(1'b0),
.phfifoxntoprdenable(1'b0),
.phfifoxntopwrenable(1'b0),
.phfifoxnwrenable({3{1'b0}}),
.prbscidenable(1'b0),
.rateswitch(1'b0),
.rateswitchisdone(1'b0),
.rateswitchxndone(1'b0),
.refclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pcs0.allow_polarity_inversion = "false",
transmit_pcs0.auto_spd_self_switch_enable = "false",
transmit_pcs0.channel_bonding = "none",
transmit_pcs0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pcs0.channel_width = 16,
transmit_pcs0.core_clock_0ppm = "false",
transmit_pcs0.datapath_low_latency_mode = "false",
transmit_pcs0.datapath_protocol = "pipe",
transmit_pcs0.disable_ph_low_latency_mode = "false",
transmit_pcs0.disparity_mode = "new",
transmit_pcs0.dprio_config_mode = 6'h00,
transmit_pcs0.elec_idle_delay = 6,
transmit_pcs0.enable_bit_reversal = "false",
transmit_pcs0.enable_idle_selection = "false",
transmit_pcs0.enable_reverse_parallel_loopback = "true",
transmit_pcs0.enable_self_test_mode = "false",
transmit_pcs0.enable_symbol_swap = "false",
transmit_pcs0.enc_8b_10b_compatibility_mode = "true",
transmit_pcs0.enc_8b_10b_mode = "normal",
transmit_pcs0.force_echar = "false",
transmit_pcs0.force_kchar = "false",
transmit_pcs0.hip_enable = "false",
transmit_pcs0.logical_channel_address = (starting_channel_number + 0),
transmit_pcs0.ph_fifo_reg_mode = "false",
transmit_pcs0.ph_fifo_xn_mapping0 = "none",
transmit_pcs0.ph_fifo_xn_mapping1 = "none",
transmit_pcs0.ph_fifo_xn_mapping2 = "none",
transmit_pcs0.ph_fifo_xn_select = 1,
transmit_pcs0.pipe_auto_speed_nego_enable = "false",
transmit_pcs0.pipe_freq_scale_mode = "Frequency",
transmit_pcs0.prbs_cid_pattern = "false",
transmit_pcs0.protocol_hint = "pcie",
transmit_pcs0.refclk_select = "local",
transmit_pcs0.self_test_mode = "incremental",
transmit_pcs0.use_double_data_mode = "true",
transmit_pcs0.use_serializer_double_data_mode = "false",
transmit_pcs0.wr_clk_mux_select = "core_clk",
transmit_pcs0.lpm_type = "arriaii_hssi_tx_pcs";
arriaii_hssi_tx_pma transmit_pma0
(
.clockout(wire_transmit_pma0_clockout),
.datain({44'b00000000000000000000000000000000000000000000, tx_dataout_pcs_to_pma[19:0]}),
.dataout(wire_transmit_pma0_dataout),
.detectrxpowerdown(cent_unit_txdetectrxpowerdn[0]),
.dftout(),
.dpriodisable(1'b1),
.dprioin(tx_pmadprioin_wire[299:0]),
.dprioout(),
.fastrefclk0in(analogfastrefclkout[1:0]),
.fastrefclk1in({2{1'b0}}),
.fastrefclk2in({2{1'b0}}),
.fastrefclk3in({2{1'b0}}),
.fastrefclk4in({2{1'b0}}),
.forceelecidle(tx_pcs_forceelecidleout[0]),
.powerdn(cent_unit_txobpowerdn[0]),
.refclk0in({analogrefclkout[1:0]}),
.refclk0inpulse(analogrefclkpulse[0]),
.refclk1in({2{1'b0}}),
.refclk1inpulse(1'b0),
.refclk2in({2{1'b0}}),
.refclk2inpulse(1'b0),
.refclk3in({2{1'b0}}),
.refclk3inpulse(1'b0),
.refclk4in({2{1'b0}}),
.refclk4inpulse(1'b0),
.revserialfdbk(1'b0),
.rxdetecten(txdetectrxout[0]),
.rxdetectvalidout(wire_transmit_pma0_rxdetectvalidout),
.rxfoundout(wire_transmit_pma0_rxfoundout),
.seriallpbkout(),
.txpmareset(tx_analogreset_out[0])
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.datainfull({20{1'b0}}),
.extra10gin({11{1'b0}}),
.pclk({5{1'b0}}),
.rxdetectclk(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
transmit_pma0.analog_power = "1.5V",
transmit_pma0.channel_number = ((starting_channel_number + 0) % 4),
transmit_pma0.channel_type = "auto",
transmit_pma0.clkin_select = 0,
transmit_pma0.clkmux_delay = "false",
transmit_pma0.common_mode = "0.65V",
transmit_pma0.dprio_config_mode = 6'h00,
transmit_pma0.enable_reverse_serial_loopback = "false",
transmit_pma0.logical_channel_address = (starting_channel_number + 0),
transmit_pma0.low_speed_test_select = 0,
transmit_pma0.physical_clkin0_mapping = "x1",
transmit_pma0.preemp_pretap = 0,
transmit_pma0.preemp_pretap_inv = "false",
transmit_pma0.preemp_tap_1 = 9,
transmit_pma0.preemp_tap_2 = 0,
transmit_pma0.preemp_tap_2_inv = "false",
transmit_pma0.protocol_hint = "pcie",
transmit_pma0.rx_detect = 0,
transmit_pma0.serialization_factor = 10,
transmit_pma0.slew_rate = "off",
transmit_pma0.termination = "OCT 100 Ohms",
transmit_pma0.use_pma_direct = "false",
transmit_pma0.use_ser_double_data_mode = "false",
transmit_pma0.vod_selection = 2,
transmit_pma0.lpm_type = "arriaii_hssi_tx_pma";
assign
analogfastrefclkout = {wire_ch_clk_div0_analogfastrefclkout},
analogrefclkout = {wire_ch_clk_div0_analogrefclkout},
analogrefclkpulse = {wire_ch_clk_div0_analogrefclkpulse},
cal_blk_powerdown = 1'b1,
cent_unit_pllpowerdn = {wire_cent_unit0_pllpowerdn[1:0]},
cent_unit_pllresetout = {wire_cent_unit0_pllresetout[1:0]},
cent_unit_quadresetout = {wire_cent_unit0_quadresetout},
cent_unit_rxcrupowerdn = {wire_cent_unit0_rxcrupowerdown[5:0]},
cent_unit_rxibpowerdn = {wire_cent_unit0_rxibpowerdown[5:0]},
cent_unit_tx_xgmdataout = {wire_cent_unit0_txdataout},
cent_unit_txctrlout = {wire_cent_unit0_txctrlout},
cent_unit_txdetectrxpowerdn = {wire_cent_unit0_txdetectrxpowerdown[5:0]},
cent_unit_txobpowerdn = {wire_cent_unit0_txobpowerdown[5:0]},
fixedclk_to_cmu = {6{reconfig_clk}},
grayelecidleinfersel_from_tx = {wire_transmit_pcs0_grayelecidleinferselout},
nonusertocmu_out = {wire_cal_blk0_nonusertocmu},
pipedatavalid = {pipedatavalid_out[0]},
pipedatavalid_out = {wire_receive_pcs0_pipedatavalid},
pipeelecidle = {pipeelecidle_out[0]},
pipeelecidle_out = {wire_receive_pcs0_pipeelecidle},
pipephydonestatus = {wire_receive_pcs0_pipephydonestatus},
pipestatus = {wire_receive_pcs0_pipestatus},
pll0_clkin = {9'b000000000, pll_inclk_wire[0]},
pll0_out = {wire_tx_pll0_clk[3:0]},
pll_ch_dataout_wire = {wire_rx_cdr_pll0_dataout},
pll_inclk_wire = {pll_inclk},
pll_locked = {pll_locked_out[0]},
pll_locked_out = {wire_tx_pll0_locked},
pll_powerdown = 1'b0,
pllpowerdn_in = {1'b0, cent_unit_pllpowerdn[0]},
pllreset_in = {1'b0, cent_unit_pllresetout[0]},
reconfig_fromgxb = {rx_pma_analogtestbus[16:1], wire_cent_unit0_dprioout},
reconfig_togxb_busy = reconfig_togxb[3],
rx_analogreset_in = {5'b00000, ((~ reconfig_togxb_busy) & rx_analogreset[0])},
rx_analogreset_out = {wire_cent_unit0_rxanalogresetout[5:0]},
rx_coreclk_in = {tx_core_clkout_wire[0]},
rx_cruclk_in = {8'b00000000, rx_pldcruclk_in[0]},
rx_ctrldetect = {wire_receive_pcs0_ctrldetect[1:0]},
rx_dataout = {rx_out_wire[15:0]},
rx_deserclock_in = {rx_pll_clkout[3:0]},
rx_digitalreset_in = {3'b000, rx_digitalreset[0]},
rx_digitalreset_out = {wire_cent_unit0_rxdigitalresetout},
rx_elecidleinfersel = {3{1'b0}},
rx_enapatternalign = 1'b0,
rx_freqlocked = {rx_freqlocked_wire[0]},
rx_freqlocked_wire = {wire_rx_cdr_pll0_freqlocked},
rx_locktodata = 1'b0,
rx_locktodata_wire = {((~ reconfig_togxb_busy) & rx_locktodata[0])},
rx_locktorefclk_wire = {wire_receive_pcs0_cdrctrllocktorefclkout},
rx_out_wire = {wire_receive_pcs0_dataout[15:0]},
rx_patterndetect = {wire_receive_pcs0_patterndetect[1:0]},
rx_pcs_rxfound_wire = {txdetectrxout[0], tx_rxfoundout[0]},
rx_pcsdprioin_wire = {1200'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 400'b0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
rx_phfifordenable = 1'b1,
rx_phfiforeset = 1'b0,
rx_phfifowrdisable = 1'b0,
rx_pipestatetransdoneout = {wire_receive_pcs0_pipestatetransdoneout},
rx_pldcruclk_in = {rx_cruclk[0]},
rx_pll_clkout = {wire_rx_cdr_pll0_clk},
rx_pll_locked = {rx_plllocked_wire[0]},
rx_pll_pfdrefclkout_wire = {wire_rx_cdr_pll0_pfdrefclkout},
rx_plllocked_wire = {wire_rx_cdr_pll0_locked},
rx_pma_analogtestbus = {12'b000000000000, wire_receive_pma0_analogtestbus[5:2], 1'b0},
rx_pma_clockout = {wire_receive_pma0_clockout},
rx_pma_dataout = {wire_receive_pma0_dataout},
rx_pma_locktorefout = {wire_receive_pma0_locktorefout},
rx_pma_recoverdataout_wire = {wire_receive_pma0_recoverdataout[19:0]},
rx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
rx_powerdown = 1'b0,
rx_powerdown_in = {5'b00000, rx_powerdown[0]},
rx_prbscidenable = 1'b0,
rx_revparallelfdbkdata = {wire_receive_pcs0_revparallelfdbkdata},
rx_rmfiforeset = 1'b0,
rx_rxcruresetout = {wire_cent_unit0_rxcruresetout[5:0]},
rx_signaldetect_wire = {wire_receive_pma0_signaldetect},
rx_syncstatus = {wire_receive_pcs0_syncstatus[1:0]},
tx_analogreset_out = {wire_cent_unit0_txanalogresetout[5:0]},
tx_clkout = {tx_core_clkout_wire[0]},
tx_clkout_int_wire = {wire_transmit_pcs0_clkout},
tx_core_clkout_wire = {tx_clkout_int_wire[0]},
tx_coreclk_in = {tx_core_clkout_wire[0]},
tx_datain_wire = {tx_datain[15:0]},
tx_datainfull = {44{1'b0}},
tx_dataout = {wire_transmit_pma0_dataout},
tx_dataout_pcs_to_pma = {wire_transmit_pcs0_dataout},
tx_digitalreset_in = {3'b000, tx_digitalreset[0]},
tx_digitalreset_out = {wire_cent_unit0_txdigitalresetout},
tx_dprioin_wire = {1050'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 150'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
tx_forcedisp_wire = {1'b0, tx_forcedispcompliance[0]},
tx_invpolarity = 1'b0,
tx_localrefclk = {wire_transmit_pma0_clockout},
tx_pcs_forceelecidleout = {wire_transmit_pcs0_forceelecidleout},
tx_phfiforeset = 1'b0,
tx_pipedeemph = 1'b0,
tx_pipemargin = {3{1'b0}},
tx_pipepowerdownout = {wire_transmit_pcs0_pipepowerdownout},
tx_pipepowerstateout = {wire_transmit_pcs0_pipepowerstateout},
tx_pipeswing = 1'b0,
tx_pmadprioin_wire = {1500'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000, 300'b000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000},
tx_revparallellpbken = 1'b0,
tx_rxdetectvalidout = {wire_transmit_pma0_rxdetectvalidout},
tx_rxfoundout = {wire_transmit_pma0_rxfoundout},
txdetectrxout = {wire_transmit_pcs0_txdetectrx};
endmodule //altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_serdes_2agx_x1d_gen1_16p (
cal_blk_clk,
gxb_powerdown,
pipe8b10binvpolarity,
pll_inclk,
powerdn,
reconfig_clk,
reconfig_togxb,
rx_analogreset,
rx_cruclk,
rx_datain,
rx_digitalreset,
tx_ctrlenable,
tx_datain,
tx_detectrxloop,
tx_digitalreset,
tx_forcedispcompliance,
tx_forceelecidle,
pipedatavalid,
pipeelecidle,
pipephydonestatus,
pipestatus,
pll_locked,
reconfig_fromgxb,
rx_ctrldetect,
rx_dataout,
rx_freqlocked,
rx_patterndetect,
rx_pll_locked,
rx_syncstatus,
tx_clkout,
tx_dataout);
input cal_blk_clk;
input [0:0] gxb_powerdown;
input [0:0] pipe8b10binvpolarity;
input pll_inclk;
input [1:0] powerdn;
input reconfig_clk;
input [3:0] reconfig_togxb;
input [0:0] rx_analogreset;
input [0:0] rx_cruclk;
input [0:0] rx_datain;
input [0:0] rx_digitalreset;
input [1:0] tx_ctrlenable;
input [15:0] tx_datain;
input [0:0] tx_detectrxloop;
input [0:0] tx_digitalreset;
input [0:0] tx_forcedispcompliance;
input [0:0] tx_forceelecidle;
output [0:0] pipedatavalid;
output [0:0] pipeelecidle;
output [0:0] pipephydonestatus;
output [2:0] pipestatus;
output [0:0] pll_locked;
output [16:0] reconfig_fromgxb;
output [1:0] rx_ctrldetect;
output [15:0] rx_dataout;
output [0:0] rx_freqlocked;
output [1:0] rx_patterndetect;
output [0:0] rx_pll_locked;
output [1:0] rx_syncstatus;
output [0:0] tx_clkout;
output [0:0] tx_dataout;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [0:0] rx_cruclk;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
parameter starting_channel_number = 0;
wire [1:0] sub_wire0;
wire [1:0] sub_wire1;
wire [0:0] sub_wire2;
wire [0:0] sub_wire3;
wire [0:0] sub_wire4;
wire [0:0] sub_wire5;
wire [0:0] sub_wire6;
wire [0:0] sub_wire7;
wire [2:0] sub_wire8;
wire [1:0] sub_wire9;
wire [0:0] sub_wire10;
wire [16:0] sub_wire11;
wire [0:0] sub_wire12;
wire [15:0] sub_wire13;
wire [1:0] rx_patterndetect = sub_wire0[1:0];
wire [1:0] rx_ctrldetect = sub_wire1[1:0];
wire [0:0] pipedatavalid = sub_wire2[0:0];
wire [0:0] pipephydonestatus = sub_wire3[0:0];
wire [0:0] rx_pll_locked = sub_wire4[0:0];
wire [0:0] rx_freqlocked = sub_wire5[0:0];
wire [0:0] tx_dataout = sub_wire6[0:0];
wire [0:0] pipeelecidle = sub_wire7[0:0];
wire [2:0] pipestatus = sub_wire8[2:0];
wire [1:0] rx_syncstatus = sub_wire9[1:0];
wire [0:0] tx_clkout = sub_wire10[0:0];
wire [16:0] reconfig_fromgxb = sub_wire11[16:0];
wire [0:0] pll_locked = sub_wire12[0:0];
wire [15:0] rx_dataout = sub_wire13[15:0];
altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a_component (
.tx_forceelecidle (tx_forceelecidle),
.pll_inclk (pll_inclk),
.gxb_powerdown (gxb_powerdown),
.tx_datain (tx_datain),
.rx_cruclk (rx_cruclk),
.cal_blk_clk (cal_blk_clk),
.powerdn (powerdn),
.reconfig_clk (reconfig_clk),
.rx_datain (rx_datain),
.reconfig_togxb (reconfig_togxb),
.tx_ctrlenable (tx_ctrlenable),
.rx_analogreset (rx_analogreset),
.pipe8b10binvpolarity (pipe8b10binvpolarity),
.rx_digitalreset (rx_digitalreset),
.tx_digitalreset (tx_digitalreset),
.tx_forcedispcompliance (tx_forcedispcompliance),
.tx_detectrxloop (tx_detectrxloop),
.rx_patterndetect (sub_wire0),
.rx_ctrldetect (sub_wire1),
.pipedatavalid (sub_wire2),
.pipephydonestatus (sub_wire3),
.rx_pll_locked (sub_wire4),
.rx_freqlocked (sub_wire5),
.tx_dataout (sub_wire6),
.pipeelecidle (sub_wire7),
.pipestatus (sub_wire8),
.rx_syncstatus (sub_wire9),
.tx_clkout (sub_wire10),
.reconfig_fromgxb (sub_wire11),
.pll_locked (sub_wire12),
.rx_dataout (sub_wire13));
defparam
altpcie_serdes_2agx_x1d_gen1_16p_alt4gxb_nb4a_component.starting_channel_number = starting_channel_number;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: PRIVATE: NUM_KEYS NUMERIC "0"
// Retrieval info: PRIVATE: RECONFIG_PROTOCOL STRING "BASIC"
// Retrieval info: PRIVATE: RECONFIG_SUBPROTOCOL STRING "none"
// Retrieval info: PRIVATE: RX_ENABLE_DC_COUPLING STRING "false"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE STRING "2500.00"
// Retrieval info: PRIVATE: WIZ_BASE_DATA_RATE_ENABLE STRING "0"
// Retrieval info: PRIVATE: WIZ_DATA_RATE STRING "2500"
// Retrieval info: PRIVATE: WIZ_DPRIO_INCLK_FREQ_ARRAY STRING "100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A STRING "2000"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_DPRIO_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK0_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK1_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK2_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK3_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK4_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK5_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_FREQ STRING "250"
// Retrieval info: PRIVATE: WIZ_DPRIO_REF_CLK6_PROTOCOL STRING "Basic"
// Retrieval info: PRIVATE: WIZ_ENABLE_EQUALIZER_CTRL NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_EQUALIZER_CTRL_SETTING NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_FORCE_DEFAULT_SETTINGS NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ STRING "100"
// Retrieval info: PRIVATE: WIZ_INCLK_FREQ_ARRAY STRING "100"
// Retrieval info: PRIVATE: WIZ_INPUT_A STRING "2500"
// Retrieval info: PRIVATE: WIZ_INPUT_A_UNIT STRING "Mbps"
// Retrieval info: PRIVATE: WIZ_INPUT_B STRING "100"
// Retrieval info: PRIVATE: WIZ_INPUT_B_UNIT STRING "MHz"
// Retrieval info: PRIVATE: WIZ_INPUT_SELECTION NUMERIC "0"
// Retrieval info: PRIVATE: WIZ_PROTOCOL STRING "PCI Express (PIPE)"
// Retrieval info: PRIVATE: WIZ_SUBPROTOCOL STRING "Gen 1-x1"
// Retrieval info: PRIVATE: WIZ_WORD_ALIGN_FLIP_PATTERN STRING "0"
// Retrieval info: PARAMETER: STARTING_CHANNEL_NUMBER NUMERIC "0"
// Retrieval info: CONSTANT: EFFECTIVE_DATA_RATE STRING "2500 Mbps"
// Retrieval info: CONSTANT: ENABLE_LC_TX_PLL STRING "false"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_A_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_B_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_C_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_D_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: EQUALIZER_CTRL_V_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: EQUALIZER_DCGAIN_SETTING NUMERIC "1"
// Retrieval info: CONSTANT: GEN_RECONFIG_PLL STRING "false"
// Retrieval info: CONSTANT: GXB_ANALOG_POWER STRING "2.5v"
// Retrieval info: CONSTANT: INPUT_CLOCK_FREQUENCY STRING "100 MHz"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Arria II GX"
// Retrieval info: CONSTANT: INTENDED_DEVICE_SPEED_GRADE STRING "4"
// Retrieval info: CONSTANT: INTENDED_DEVICE_VARIANT STRING "ANY"
// Retrieval info: CONSTANT: LOOPBACK_MODE STRING "none"
// Retrieval info: CONSTANT: LPM_TYPE STRING "alt4gxb"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "1"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "duplex"
// Retrieval info: CONSTANT: PLL_CONTROL_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_1STPOSTTAP_SETTING NUMERIC "9"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_2NDPOSTTAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_INV_SETTING STRING "false"
// Retrieval info: CONSTANT: PREEMPHASIS_CTRL_PRETAP_SETTING NUMERIC "0"
// Retrieval info: CONSTANT: PROTOCOL STRING "pcie"
// Retrieval info: CONSTANT: RECEIVER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: RECONFIG_DPRIO_MODE NUMERIC "0"
// Retrieval info: CONSTANT: RX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN STRING "0101111100"
// Retrieval info: CONSTANT: RX_ALIGN_PATTERN_LENGTH NUMERIC "10"
// Retrieval info: CONSTANT: RX_ALLOW_ALIGN_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: RX_ALLOW_PIPE_POLARITY_INVERSION STRING "true"
// Retrieval info: CONSTANT: RX_BITSLIP_ENABLE STRING "false"
// Retrieval info: CONSTANT: RX_BYTE_ORDERING_MODE STRING "NONE"
// Retrieval info: CONSTANT: RX_CHANNEL_BONDING STRING "indv"
// Retrieval info: CONSTANT: RX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: RX_COMMON_MODE STRING "0.82v"
// Retrieval info: CONSTANT: RX_CRU_BANDWIDTH_TYPE STRING "Medium"
// Retrieval info: CONSTANT: RX_CRU_INCLOCK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: RX_DATAPATH_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: RX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: RX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: RX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: RX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_DATA_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_LOCK_TO_REFCLK_SIG STRING "false"
// Retrieval info: CONSTANT: RX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: RX_FORCE_SIGNAL_DETECT STRING "true"
// Retrieval info: CONSTANT: RX_PPMSELECT NUMERIC "32"
// Retrieval info: CONSTANT: RX_RATE_MATCH_FIFO_MODE STRING "normal"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN1 STRING "11010000111010000011"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN2 STRING "00101111000101111100"
// Retrieval info: CONSTANT: RX_RATE_MATCH_PATTERN_SIZE NUMERIC "20"
// Retrieval info: CONSTANT: RX_RUN_LENGTH NUMERIC "40"
// Retrieval info: CONSTANT: RX_RUN_LENGTH_ENABLE STRING "true"
// Retrieval info: CONSTANT: RX_USE_ALIGN_STATE_MACHINE STRING "true"
// Retrieval info: CONSTANT: RX_USE_CLKOUT STRING "false"
// Retrieval info: CONSTANT: RX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: RX_USE_CRUCLK STRING "true"
// Retrieval info: CONSTANT: RX_USE_DESERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: RX_USE_DESKEW_FIFO STRING "false"
// Retrieval info: CONSTANT: RX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: RX_USE_PIPE8B10BINVPOLARITY STRING "true"
// Retrieval info: CONSTANT: RX_USE_RATE_MATCH_PATTERN1_ONLY STRING "false"
// Retrieval info: CONSTANT: TRANSMITTER_TERMINATION STRING "oct_100_ohms"
// Retrieval info: CONSTANT: TX_8B_10B_MODE STRING "normal"
// Retrieval info: CONSTANT: TX_ALLOW_POLARITY_INVERSION STRING "false"
// Retrieval info: CONSTANT: TX_ANALOG_POWER STRING "1.5v"
// Retrieval info: CONSTANT: TX_CHANNEL_BONDING STRING "indv"
// Retrieval info: CONSTANT: TX_CHANNEL_WIDTH NUMERIC "16"
// Retrieval info: CONSTANT: TX_CLKOUT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_COMMON_MODE STRING "0.65v"
// Retrieval info: CONSTANT: TX_DATA_RATE NUMERIC "2500"
// Retrieval info: CONSTANT: TX_DATA_RATE_REMAINDER NUMERIC "0"
// Retrieval info: CONSTANT: TX_DIGITALRESET_PORT_WIDTH NUMERIC "1"
// Retrieval info: CONSTANT: TX_ENABLE_BIT_REVERSAL STRING "false"
// Retrieval info: CONSTANT: TX_ENABLE_SELF_TEST_MODE STRING "false"
// Retrieval info: CONSTANT: TX_PLL_BANDWIDTH_TYPE STRING "High"
// Retrieval info: CONSTANT: TX_PLL_INCLK0_PERIOD NUMERIC "10000"
// Retrieval info: CONSTANT: TX_TRANSMIT_PROTOCOL STRING "pipe"
// Retrieval info: CONSTANT: TX_USE_CORECLK STRING "false"
// Retrieval info: CONSTANT: TX_USE_DOUBLE_DATA_MODE STRING "true"
// Retrieval info: CONSTANT: TX_USE_SERIALIZER_DOUBLE_DATA_MODE STRING "false"
// Retrieval info: CONSTANT: USE_CALIBRATION_BLOCK STRING "true"
// Retrieval info: CONSTANT: VOD_CTRL_SETTING NUMERIC "2"
// Retrieval info: CONSTANT: elec_idle_infer_enable STRING "false"
// Retrieval info: CONSTANT: enable_0ppm STRING "true"
// Retrieval info: CONSTANT: gxb_powerdown_width NUMERIC "1"
// Retrieval info: CONSTANT: number_of_quads NUMERIC "1"
// Retrieval info: CONSTANT: reconfig_calibration STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_port_width NUMERIC "17"
// Retrieval info: CONSTANT: reconfig_togxb_port_width NUMERIC "4"
// Retrieval info: CONSTANT: rx_cdrctrl_enable STRING "true"
// Retrieval info: CONSTANT: rx_cru_data_rate NUMERIC "800"
// Retrieval info: CONSTANT: rx_cru_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: rx_cru_n_divider NUMERIC "2"
// Retrieval info: CONSTANT: rx_cru_vco_post_scale_divider NUMERIC "2"
// Retrieval info: CONSTANT: rx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: rx_word_aligner_num_byte NUMERIC "1"
// Retrieval info: CONSTANT: tx_dwidth_factor NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_clock_post_divider NUMERIC "1"
// Retrieval info: CONSTANT: tx_pll_data_rate NUMERIC "800"
// Retrieval info: CONSTANT: tx_pll_m_divider NUMERIC "25"
// Retrieval info: CONSTANT: tx_pll_n_divider NUMERIC "2"
// Retrieval info: CONSTANT: tx_pll_vco_data_rate NUMERIC "800"
// Retrieval info: CONSTANT: tx_pll_vco_post_scale_divider NUMERIC "2"
// Retrieval info: CONSTANT: tx_slew_rate STRING "off"
// Retrieval info: USED_PORT: cal_blk_clk 0 0 0 0 INPUT NODEFVAL "cal_blk_clk"
// Retrieval info: USED_PORT: gxb_powerdown 0 0 1 0 INPUT NODEFVAL "gxb_powerdown[0..0]"
// Retrieval info: USED_PORT: pipe8b10binvpolarity 0 0 1 0 INPUT NODEFVAL "pipe8b10binvpolarity[0..0]"
// Retrieval info: USED_PORT: pipedatavalid 0 0 1 0 OUTPUT NODEFVAL "pipedatavalid[0..0]"
// Retrieval info: USED_PORT: pipeelecidle 0 0 1 0 OUTPUT NODEFVAL "pipeelecidle[0..0]"
// Retrieval info: USED_PORT: pipephydonestatus 0 0 1 0 OUTPUT NODEFVAL "pipephydonestatus[0..0]"
// Retrieval info: USED_PORT: pipestatus 0 0 3 0 OUTPUT NODEFVAL "pipestatus[2..0]"
// Retrieval info: USED_PORT: pll_inclk 0 0 0 0 INPUT NODEFVAL "pll_inclk"
// Retrieval info: USED_PORT: pll_locked 0 0 1 0 OUTPUT NODEFVAL "pll_locked[0..0]"
// Retrieval info: USED_PORT: powerdn 0 0 2 0 INPUT NODEFVAL "powerdn[1..0]"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 17 0 OUTPUT NODEFVAL "reconfig_fromgxb[16..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 INPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: USED_PORT: rx_analogreset 0 0 1 0 INPUT NODEFVAL "rx_analogreset[0..0]"
// Retrieval info: USED_PORT: rx_cruclk 0 0 1 0 INPUT GND "rx_cruclk[0..0]"
// Retrieval info: USED_PORT: rx_ctrldetect 0 0 2 0 OUTPUT NODEFVAL "rx_ctrldetect[1..0]"
// Retrieval info: USED_PORT: rx_datain 0 0 1 0 INPUT NODEFVAL "rx_datain[0..0]"
// Retrieval info: USED_PORT: rx_dataout 0 0 16 0 OUTPUT NODEFVAL "rx_dataout[15..0]"
// Retrieval info: USED_PORT: rx_digitalreset 0 0 1 0 INPUT NODEFVAL "rx_digitalreset[0..0]"
// Retrieval info: USED_PORT: rx_freqlocked 0 0 1 0 OUTPUT NODEFVAL "rx_freqlocked[0..0]"
// Retrieval info: USED_PORT: rx_patterndetect 0 0 2 0 OUTPUT NODEFVAL "rx_patterndetect[1..0]"
// Retrieval info: USED_PORT: rx_pll_locked 0 0 1 0 OUTPUT NODEFVAL "rx_pll_locked[0..0]"
// Retrieval info: USED_PORT: rx_syncstatus 0 0 2 0 OUTPUT NODEFVAL "rx_syncstatus[1..0]"
// Retrieval info: USED_PORT: tx_clkout 0 0 1 0 OUTPUT NODEFVAL "tx_clkout[0..0]"
// Retrieval info: USED_PORT: tx_ctrlenable 0 0 2 0 INPUT NODEFVAL "tx_ctrlenable[1..0]"
// Retrieval info: USED_PORT: tx_datain 0 0 16 0 INPUT NODEFVAL "tx_datain[15..0]"
// Retrieval info: USED_PORT: tx_dataout 0 0 1 0 OUTPUT NODEFVAL "tx_dataout[0..0]"
// Retrieval info: USED_PORT: tx_detectrxloop 0 0 1 0 INPUT NODEFVAL "tx_detectrxloop[0..0]"
// Retrieval info: USED_PORT: tx_digitalreset 0 0 1 0 INPUT NODEFVAL "tx_digitalreset[0..0]"
// Retrieval info: USED_PORT: tx_forcedispcompliance 0 0 1 0 INPUT NODEFVAL "tx_forcedispcompliance[0..0]"
// Retrieval info: USED_PORT: tx_forceelecidle 0 0 1 0 INPUT NODEFVAL "tx_forceelecidle[0..0]"
// Retrieval info: CONNECT: @tx_detectrxloop 0 0 1 0 tx_detectrxloop 0 0 1 0
// Retrieval info: CONNECT: @tx_forcedispcompliance 0 0 1 0 tx_forcedispcompliance 0 0 1 0
// Retrieval info: CONNECT: rx_patterndetect 0 0 2 0 @rx_patterndetect 0 0 2 0
// Retrieval info: CONNECT: pipedatavalid 0 0 1 0 @pipedatavalid 0 0 1 0
// Retrieval info: CONNECT: @rx_analogreset 0 0 1 0 rx_analogreset 0 0 1 0
// Retrieval info: CONNECT: @powerdn 0 0 2 0 powerdn 0 0 2 0
// Retrieval info: CONNECT: pipeelecidle 0 0 1 0 @pipeelecidle 0 0 1 0
// Retrieval info: CONNECT: rx_ctrldetect 0 0 2 0 @rx_ctrldetect 0 0 2 0
// Retrieval info: CONNECT: @gxb_powerdown 0 0 1 0 gxb_powerdown 0 0 1 0
// Retrieval info: CONNECT: rx_dataout 0 0 16 0 @rx_dataout 0 0 16 0
// Retrieval info: CONNECT: @cal_blk_clk 0 0 0 0 cal_blk_clk 0 0 0 0
// Retrieval info: CONNECT: pipestatus 0 0 3 0 @pipestatus 0 0 3 0
// Retrieval info: CONNECT: @tx_digitalreset 0 0 1 0 tx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: rx_pll_locked 0 0 1 0 @rx_pll_locked 0 0 1 0
// Retrieval info: CONNECT: rx_syncstatus 0 0 2 0 @rx_syncstatus 0 0 2 0
// Retrieval info: CONNECT: @pipe8b10binvpolarity 0 0 1 0 pipe8b10binvpolarity 0 0 1 0
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_togxb 0 0 4 0 reconfig_togxb 0 0 4 0
// Retrieval info: CONNECT: pll_locked 0 0 1 0 @pll_locked 0 0 1 0
// Retrieval info: CONNECT: @rx_digitalreset 0 0 1 0 rx_digitalreset 0 0 1 0
// Retrieval info: CONNECT: tx_clkout 0 0 1 0 @tx_clkout 0 0 1 0
// Retrieval info: CONNECT: @rx_cruclk 0 0 1 0 rx_cruclk 0 0 1 0
// Retrieval info: CONNECT: @pll_inclk 0 0 0 0 pll_inclk 0 0 0 0
// Retrieval info: CONNECT: @tx_ctrlenable 0 0 2 0 tx_ctrlenable 0 0 2 0
// Retrieval info: CONNECT: tx_dataout 0 0 1 0 @tx_dataout 0 0 1 0
// Retrieval info: CONNECT: @tx_datain 0 0 16 0 tx_datain 0 0 16 0
// Retrieval info: CONNECT: reconfig_fromgxb 0 0 17 0 @reconfig_fromgxb 0 0 17 0
// Retrieval info: CONNECT: rx_freqlocked 0 0 1 0 @rx_freqlocked 0 0 1 0
// Retrieval info: CONNECT: @rx_datain 0 0 1 0 rx_datain 0 0 1 0
// Retrieval info: CONNECT: pipephydonestatus 0 0 1 0 @pipephydonestatus 0 0 1 0
// Retrieval info: CONNECT: @tx_forceelecidle 0 0 1 0 tx_forceelecidle 0 0 1 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.ppf TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_serdes_2agx_x1d_gen1_16p_bb.v TRUE FALSE
|
//*****************************************************************************
// (c) Copyright 2008 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : mem_intfc.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Aug 03 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose : Top level memory interface block. Instantiates a clock
// and reset generator, the memory controller, the phy and
// the user interface blocks.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mem_intfc #
(
parameter TCQ = 100,
parameter PAYLOAD_WIDTH = 64,
parameter ADDR_CMD_MODE = "1T",
parameter AL = "0", // Additive Latency option
parameter BANK_WIDTH = 3, // # of bank bits
parameter BM_CNT_WIDTH = 2, // Bank machine counter width
parameter BURST_MODE = "8", // Burst length
parameter BURST_TYPE = "SEQ", // Burst type
parameter CK_WIDTH = 1, // # of CK/CK# outputs to memory
// five fields, one per possible I/O bank, 4 bits in each field, 1 per lane
// data=1/ctl=0
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
// defines the byte lanes in I/O banks being used in the interface
// 1- Used, 0- Unused
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
// defines the bit lanes in I/O banks being used in the interface. Each
// parameter = 1 I/O bank = 4 byte lanes = 48 bit lanes. 1-Used, 0-Unused
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// control/address/data pin mapping parameters
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// calibration Address. The address given below will be used for calibration
// read and write operations.
parameter CALIB_ROW_ADD = 16'h0000,// Calibration row address
parameter CALIB_COL_ADD = 12'h000, // Calibration column address
parameter CALIB_BA_ADD = 3'h0, // Calibration bank address
parameter CL = 5,
parameter COL_WIDTH = 12, // column address width
parameter CMD_PIPE_PLUS1 = "ON", // add pipeline stage between MC and PHY
parameter CS_WIDTH = 1, // # of unique CS outputs
parameter CKE_WIDTH = 1, // # of cke outputs
parameter CWL = 5,
parameter DATA_WIDTH = 64,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of DM (data mask)
parameter DQ_CNT_WIDTH = 6, // = ceil(log2(DQ_WIDTH))
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DQS_CNT_WIDTH = 3, // = ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DRAM_TYPE = "DDR3",
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter ECC = "OFF",
parameter ECC_WIDTH = 8,
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nAL = 0, // Additive latency (in clk cyc)
parameter nBANK_MACHS = 4,
parameter nCK_PER_CLK = 4, // # of memory CKs per fabric CLK
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter ORDERING = "NORM",
parameter PHASE_DETECT = "OFF" , // to phy_top
parameter IBUF_LPWR_MODE = "OFF", // to phy_top
parameter IODELAY_HP_MODE = "ON", // to phy_top
parameter IODELAY_GRP = "IODELAY_MIG", //to phy_top
parameter OUTPUT_DRV = "HIGH" , // to phy_top
parameter REG_CTRL = "OFF" , // to phy_top
parameter RTT_NOM = "60" , // to phy_top
parameter RTT_WR = "120" , // to phy_top
parameter STARVE_LIMIT = 2,
parameter tCK = 2500, // pS
parameter tFAW = 40000, // pS
parameter tPRDI = 1_000_000, // pS
parameter tRAS = 37500, // pS
parameter tRCD = 12500, // pS
parameter tREFI = 7800000, // pS
parameter tRFC = 110000, // pS
parameter tRP = 12500, // pS
parameter tRRD = 10000, // pS
parameter tRTP = 7500, // pS
parameter tWTR = 7500, // pS
parameter tZQI = 128_000_000, // nS
parameter tZQCS = 64, // CKs
parameter WRLVL = "OFF" , // to phy_top
parameter DEBUG_PORT = "OFF" , // to phy_top
parameter CAL_WIDTH = "HALF" , // to phy_top
parameter RANK_WIDTH = 1,
parameter RANKS = 4,
parameter ROW_WIDTH = 16, // DRAM address bus width
parameter [7:0] SLOT_0_CONFIG = 8'b0000_0001,
parameter [7:0] SLOT_1_CONFIG = 8'b0000_0000,
parameter SIM_BYPASS_INIT_CAL = "OFF",
parameter REFCLK_FREQ = 300.0,
parameter nDQS_COL0 = DQS_WIDTH,
parameter nDQS_COL1 = 0,
parameter nDQS_COL2 = 0,
parameter nDQS_COL3 = 0,
parameter DQS_LOC_COL0 = 144'h11100F0E0D0C0B0A09080706050403020100,
parameter DQS_LOC_COL1 = 0,
parameter DQS_LOC_COL2 = 0,
parameter DQS_LOC_COL3 = 0,
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1 // Support ODT output
)
(
input clk_ref,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input [BANK_WIDTH-1:0] bank, // To mc0 of mc.v
input clk ,
input [2:0] cmd, // To mc0 of mc.v
input [COL_WIDTH-1:0] col, // To mc0 of mc.v
input correct_en,
input [DATA_BUF_ADDR_WIDTH-1:0] data_buf_addr, // To mc0 of mc.v
input dbg_idel_down_all,
input dbg_idel_down_cpt,
input dbg_idel_up_all,
input dbg_idel_up_cpt,
input dbg_sel_all_idel_cpt,
input [DQS_CNT_WIDTH-1:0] dbg_sel_idel_cpt,
input hi_priority, // To mc0 of mc.v
input [RANK_WIDTH-1:0] rank, // To mc0 of mc.v
input [2*nCK_PER_CLK-1:0] raw_not_ecc,
input [ROW_WIDTH-1:0] row, // To mc0 of mc.v
input rst, // To mc0 of mc.v, ...
input size, // To mc0 of mc.v
input [7:0] slot_0_present, // To mc0 of mc.v
input [7:0] slot_1_present, // To mc0 of mc.v
input use_addr, // To mc0 of mc.v
input [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] wr_data,
input [2*nCK_PER_CLK*DATA_WIDTH/8-1:0] wr_data_mask,
output accept, // From mc0 of mc.v
output accept_ns, // From mc0 of mc.v
output [BM_CNT_WIDTH-1:0] bank_mach_next, // From mc0 of mc.v
output [255:0] dbg_calib_top,
output [5*DQS_WIDTH-1:0] dbg_cpt_first_edge_cnt,
output [5*DQS_WIDTH-1:0] dbg_cpt_second_edge_cnt,
output [255:0] dbg_phy_rdlvl,
output [99:0] dbg_phy_wrcal,
output [DQS_WIDTH-1:0] dbg_rd_data_edge_detect,
output [4*DQ_WIDTH-1:0] dbg_rddata,
output [1:0] dbg_rdlvl_done,
output [1:0] dbg_rdlvl_err,
output [1:0] dbg_rdlvl_start,
output [4:0] dbg_tap_cnt_during_wrlvl,
output dbg_wl_edge_detect_valid,
output dbg_wrlvl_done,
output dbg_wrlvl_err,
output dbg_wrlvl_start,
output [ROW_WIDTH-1:0] ddr_addr, // From phy_top0 of phy_top.v
output [BANK_WIDTH-1:0] ddr_ba, // From phy_top0 of phy_top.v
output ddr_cas_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck_n, // From phy_top0 of phy_top.v
output [CK_WIDTH-1:0] ddr_ck , // From phy_top0 of phy_top.v
output [CKE_WIDTH-1:0] ddr_cke, // From phy_top0 of phy_top.v
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n, // From phy_top0 of phy_top.v
output [DM_WIDTH-1:0] ddr_dm, // From phy_top0 of phy_top.v
output [RANKS-1:0] ddr_odt, // From phy_top0 of phy_top.v
output ddr_ras_n, // From phy_top0 of phy_top.v
output ddr_reset_n, // From phy_top0 of phy_top.v
output ddr_parity,
output ddr_we_n, // From phy_top0 of phy_top.v
output init_calib_complete,
output [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr,
output [2*nCK_PER_CLK-1:0] ecc_multiple,
output [2*nCK_PER_CLK-1:0] ecc_single,
output wire [2*nCK_PER_CLK*PAYLOAD_WIDTH-1:0] rd_data,
output [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr,
// From mc0 of mc.v
output rd_data_en, // From mc0 of mc.v
output rd_data_end, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset, // From mc0 of mc.v
output [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr, // From mc0 of mc.v
output wr_data_en, // From mc0 of mc.v
output [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset, // From mc0 of mc.v
inout [DQ_WIDTH-1:0] ddr_dq, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs_n, // To/From phy_top0 of phy_top.v
inout [DQS_WIDTH-1:0] ddr_dqs // To/From phy_top0 of phy_top.v
);
localparam nSLOTS = 1 + (|SLOT_1_CONFIG ? 1 : 0);
localparam SLOT_0_CONFIG_MC = (nSLOTS == 2)? 8'b0000_0101 : 8'b0000_1111;
localparam SLOT_1_CONFIG_MC = (nSLOTS == 2)? 8'b0000_1010 : 8'b0000_0000;
reg [7:0] slot_0_present_mc;
reg [7:0] slot_1_present_mc;
reg user_periodic_rd_req = 1'b0;
reg user_ref_req = 1'b0;
reg user_zq_req = 1'b0;
// MC/PHY interface
wire [nCK_PER_CLK-1:0] mc_ras_n;
wire [nCK_PER_CLK-1:0] mc_cas_n;
wire [nCK_PER_CLK-1:0] mc_we_n;
wire [nCK_PER_CLK*ROW_WIDTH-1:0] mc_address;
wire [nCK_PER_CLK*BANK_WIDTH-1:0] mc_bank;
wire [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mc_cs_n;
wire mc_reset_n;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] mc_wrdata;
wire [2*nCK_PER_CLK*DQ_WIDTH/8-1:0] mc_wrdata_mask;
wire mc_wrdata_en;
wire mc_cmd_wren;
wire mc_ctl_wren;
wire [2:0] mc_cmd;
wire [1:0] mc_cas_slot;
wire [5:0] mc_data_offset;
wire [3:0] mc_aux_out0;
wire [3:0] mc_aux_out1;
wire [1:0] mc_rank_cnt;
wire phy_mc_ctl_full;
wire phy_mc_cmd_full;
wire phy_mc_data_full;
wire [2*nCK_PER_CLK*DQ_WIDTH-1:0] phy_rd_data;
wire phy_rddata_valid;
wire [6*RANKS-1:0] calib_rd_data_offset;
// assigning CWL = CL -1 for DDR2. DDR2 customers will not know anything
// about CWL. There is also nCWL parameter. Need to clean it up.
localparam CWL_T = (DRAM_TYPE == "DDR3") ? CWL : CL-1;
generate
if (nSLOTS == 1) begin: gen_single_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_0_present[2] or slot_0_present[3]) begin
slot_0_present_mc = slot_0_present;
slot_1_present_mc = slot_1_present;
end
end else if (nSLOTS == 2) begin: gen_dual_slot_odt
always @ (slot_0_present[0] or slot_0_present[1]
or slot_1_present[0] or slot_1_present[1]) begin
case ({slot_0_present[0],slot_0_present[1],
slot_1_present[0],slot_1_present[1]})
//Two slot configuration, one slot present, single rank
4'b1000: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0000;
end
4'b0010: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_0010;
end
// Two slot configuration, one slot present, dual rank
4'b1100: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0000;
end
4'b0011: begin
slot_0_present_mc = 8'b0000_0000;
slot_1_present_mc = 8'b0000_1010;
end
// Two slot configuration, one rank per slot
4'b1010: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - One slot with dual rank and the other with single rank
4'b1011: begin
slot_0_present_mc = 8'b0000_0001;
slot_1_present_mc = 8'b0000_1010;
end
4'b1110: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_0010;
end
// Two Slots - two ranks per slot
4'b1111: begin
slot_0_present_mc = 8'b0000_0101;
slot_1_present_mc = 8'b0000_1010;
end
endcase
end
end
endgenerate
mc #
(
.TCQ (TCQ),
.PAYLOAD_WIDTH (PAYLOAD_WIDTH),
.MC_ERR_ADDR_WIDTH (MC_ERR_ADDR_WIDTH),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BANK_WIDTH (BANK_WIDTH),
.BM_CNT_WIDTH (BM_CNT_WIDTH),
.BURST_MODE (BURST_MODE),
.COL_WIDTH (COL_WIDTH),
.CMD_PIPE_PLUS1 (CMD_PIPE_PLUS1),
.CS_WIDTH (CS_WIDTH),
.DATA_WIDTH (DATA_WIDTH),
.DATA_BUF_ADDR_WIDTH (DATA_BUF_ADDR_WIDTH),
.DATA_BUF_OFFSET_WIDTH (DATA_BUF_OFFSET_WIDTH),
.DRAM_TYPE (DRAM_TYPE),
.DQS_WIDTH (DQS_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.ECC (ECC),
.ECC_WIDTH (ECC_WIDTH),
.nBANK_MACHS (nBANK_MACHS),
.nCK_PER_CLK (nCK_PER_CLK),
.nSLOTS (nSLOTS),
.CL (CL),
.nCS_PER_RANK (nCS_PER_RANK),
.CWL (CWL_T),
.ORDERING (ORDERING),
.RANK_WIDTH (RANK_WIDTH),
.RANKS (RANKS),
.REG_CTRL (REG_CTRL),
.ROW_WIDTH (ROW_WIDTH),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.STARVE_LIMIT (STARVE_LIMIT),
.SLOT_0_CONFIG (SLOT_0_CONFIG_MC),
.SLOT_1_CONFIG (SLOT_1_CONFIG_MC),
.tCK (tCK),
.tFAW (tFAW),
.tRAS (tRAS),
.tRCD (tRCD),
.tREFI (tREFI),
.tRFC (tRFC),
.tRP (tRP),
.tRRD (tRRD),
.tRTP (tRTP),
.tWTR (tWTR),
.tZQI (tZQI),
.tZQCS (tZQCS))
mc0
(.app_periodic_rd_req (1'b0),
.app_ref_req (1'b0),
.app_zq_req (1'b0),
.ecc_single (ecc_single),
.ecc_multiple (ecc_multiple),
.ecc_err_addr (ecc_err_addr),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_cas_slot (mc_cas_slot),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
// Outputs
.accept (accept),
.accept_ns (accept_ns),
.bank_mach_next (bank_mach_next[BM_CNT_WIDTH-1:0]),
.rd_data_addr (rd_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.rd_data_en (rd_data_en),
.rd_data_end (rd_data_end),
.rd_data_offset (rd_data_offset),
.wr_data_addr (wr_data_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.wr_data_en (wr_data_en),
.wr_data_offset (wr_data_offset),
.rd_data (rd_data),
.wr_data (wr_data),
.wr_data_mask (wr_data_mask),
// Inputs
.init_calib_complete (init_calib_complete),
.calib_rd_data_offset (calib_rd_data_offset),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.correct_en (correct_en),
.bank (bank[BANK_WIDTH-1:0]),
.clk (clk),
.cmd (cmd[2:0]),
.col (col[COL_WIDTH-1:0]),
.data_buf_addr (data_buf_addr[DATA_BUF_ADDR_WIDTH-1:0]),
.hi_priority (hi_priority),
.rank (rank[RANK_WIDTH-1:0]),
.raw_not_ecc (raw_not_ecc[2*nCK_PER_CLK-1 :0]),
.row (row[ROW_WIDTH-1:0]),
.rst (rst),
.size (size),
.slot_0_present (slot_0_present_mc[7:0]),
.slot_1_present (slot_1_present_mc[7:0]),
.use_addr (use_addr));
// following calculations should be moved inside PHY
// odt bus should be added to PHY.
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
localparam nCL = CL;
localparam nCWL = CWL_T;
`ifdef MC_SVA
ddr2_improper_CL: assert property
(@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL > 6) || (CL < 3)))));
// Not needed after the CWL fix for DDR2
// ddr2_improper_CWL: assert property
// (@(posedge clk) (~((DRAM_TYPE == "DDR2") && ((CL - CWL) != 1))));
`endif
phy_top #
(
.TCQ (TCQ),
.REFCLK_FREQ (REFCLK_FREQ),
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.CK_BYTE_MAP (CK_BYTE_MAP),
.ADDR_MAP (ADDR_MAP),
.BANK_MAP (BANK_MAP),
.CAS_MAP (CAS_MAP),
.CKE_ODT_BYTE_MAP (CKE_ODT_BYTE_MAP),
.CS_MAP (CS_MAP),
.PARITY_MAP (PARITY_MAP),
.RAS_MAP (RAS_MAP),
.WE_MAP (WE_MAP),
.DQS_BYTE_MAP (DQS_BYTE_MAP),
.DATA0_MAP (DATA0_MAP),
.DATA1_MAP (DATA1_MAP),
.DATA2_MAP (DATA2_MAP),
.DATA3_MAP (DATA3_MAP),
.DATA4_MAP (DATA4_MAP),
.DATA5_MAP (DATA5_MAP),
.DATA6_MAP (DATA6_MAP),
.DATA7_MAP (DATA7_MAP),
.DATA8_MAP (DATA8_MAP),
.DATA9_MAP (DATA9_MAP),
.DATA10_MAP (DATA10_MAP),
.DATA11_MAP (DATA11_MAP),
.DATA12_MAP (DATA12_MAP),
.DATA13_MAP (DATA13_MAP),
.DATA14_MAP (DATA14_MAP),
.DATA15_MAP (DATA15_MAP),
.DATA16_MAP (DATA16_MAP),
.DATA17_MAP (DATA17_MAP),
.MASK0_MAP (MASK0_MAP),
.MASK1_MAP (MASK1_MAP),
.CALIB_ROW_ADD (CALIB_ROW_ADD),
.CALIB_COL_ADD (CALIB_COL_ADD),
.CALIB_BA_ADD (CALIB_BA_ADD),
.nCS_PER_RANK (nCS_PER_RANK),
.CS_WIDTH (CS_WIDTH),
.nCK_PER_CLK (nCK_PER_CLK),
.CKE_WIDTH (CKE_WIDTH),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.DDR2_DQSN_ENABLE (DDR2_DQSN_ENABLE),
.DRAM_TYPE (DRAM_TYPE),
.BANK_WIDTH (BANK_WIDTH),
.CK_WIDTH (CK_WIDTH),
.COL_WIDTH (COL_WIDTH),
.DM_WIDTH (DM_WIDTH),
.DQ_WIDTH (DQ_WIDTH),
.DQS_CNT_WIDTH (DQS_CNT_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.PHYCTL_CMD_FIFO (PHYCTL_CMD_FIFO),
.ROW_WIDTH (ROW_WIDTH),
.AL (AL),
.ADDR_CMD_MODE (ADDR_CMD_MODE),
.BURST_MODE (BURST_MODE),
.BURST_TYPE (BURST_TYPE),
.CL (nCL),
.CWL (nCWL),
.tRFC (tRFC),
.tCK (tCK),
.OUTPUT_DRV (OUTPUT_DRV),
.RANKS (RANKS),
.REG_CTRL (REG_CTRL),
.RTT_NOM (RTT_NOM),
.RTT_WR (RTT_WR),
.SLOT_1_CONFIG (SLOT_1_CONFIG),
.WRLVL (WRLVL),
.IODELAY_HP_MODE (IODELAY_HP_MODE),
.IODELAY_GRP (IODELAY_GRP),
// Prevent the following simulation-related parameters from
// being overridden for synthesis - for synthesis only the
// default values of these parameters should be used
// synthesis translate_off
.SIM_BYPASS_INIT_CAL (SIM_BYPASS_INIT_CAL),
// synthesis translate_on
.USE_CS_PORT (USE_CS_PORT),
.USE_DM_PORT (USE_DM_PORT),
.USE_ODT_PORT (USE_ODT_PORT),
.DEBUG_PORT (DEBUG_PORT)
)
phy_top0
(
// Outputs
.calib_rd_data_offset (calib_rd_data_offset),
.ddr_ck (ddr_ck),
.ddr_ck_n (ddr_ck_n),
.ddr_addr (ddr_addr),
.ddr_ba (ddr_ba),
.ddr_ras_n (ddr_ras_n),
.ddr_cas_n (ddr_cas_n),
.ddr_we_n (ddr_we_n),
.ddr_cs_n (ddr_cs_n),
.ddr_cke (ddr_cke),
.ddr_odt (ddr_odt),
.ddr_reset_n (ddr_reset_n),
.ddr_parity (ddr_parity),
.ddr_dm (ddr_dm),
.dbg_calib_top (dbg_calib_top),
.dbg_cpt_first_edge_cnt (dbg_cpt_first_edge_cnt),
.dbg_cpt_second_edge_cnt (dbg_cpt_second_edge_cnt),
.dbg_phy_rdlvl (dbg_phy_rdlvl),
.dbg_phy_wrcal (dbg_phy_wrcal),
.dbg_rd_data_edge_detect (dbg_rd_data_edge_detect),
.dbg_rddata (dbg_rddata),
.dbg_rdlvl_done (dbg_rdlvl_done),
.dbg_rdlvl_err (dbg_rdlvl_err),
.dbg_rdlvl_start (dbg_rdlvl_start),
.dbg_tap_cnt_during_wrlvl (dbg_tap_cnt_during_wrlvl),
.dbg_wl_edge_detect_valid (dbg_wl_edge_detect_valid),
.dbg_wrlvl_done (dbg_wrlvl_done),
.dbg_wrlvl_err (dbg_wrlvl_err),
.dbg_wrlvl_start (dbg_wrlvl_start),
.init_calib_complete (init_calib_complete),
.mc_address (mc_address),
.mc_aux_out0 (mc_aux_out0),
.mc_aux_out1 (mc_aux_out1),
.mc_bank (mc_bank),
.mc_cas_n (mc_cas_n),
.mc_cmd (mc_cmd),
.mc_cmd_wren (mc_cmd_wren),
.mc_cas_slot (mc_cas_slot),
.mc_cs_n (mc_cs_n),
.mc_ctl_wren (mc_ctl_wren),
.mc_data_offset (mc_data_offset),
.mc_rank_cnt (mc_rank_cnt),
.mc_ras_n (mc_ras_n),
.mc_reset_n (mc_reset_n),
.mc_we_n (mc_we_n),
.mc_wrdata (mc_wrdata),
.mc_wrdata_en (mc_wrdata_en),
.mc_wrdata_mask (mc_wrdata_mask),
.mem_refclk (mem_refclk),
.phy_mc_ctl_full (phy_mc_ctl_full),
.phy_mc_cmd_full (phy_mc_cmd_full),
.phy_mc_data_full (phy_mc_data_full),
.phy_rd_data (phy_rd_data),
.phy_rddata_valid (phy_rddata_valid),
.pll_lock (pll_lock),
.sync_pulse (sync_pulse),
// Inouts
.ddr_dqs (ddr_dqs),
.ddr_dqs_n (ddr_dqs_n),
.ddr_dq (ddr_dq),
// Inputs
.clk_ref (clk_ref),
.freq_refclk (freq_refclk),
.clk (clk),
.rst (rst),
.slot_0_present (slot_0_present),
.slot_1_present (slot_1_present),
.dbg_idel_up_all (dbg_idel_up_all),
.dbg_idel_down_all (dbg_idel_down_all),
.dbg_idel_up_cpt (dbg_idel_up_cpt),
.dbg_idel_down_cpt (dbg_idel_down_cpt),
.dbg_sel_idel_cpt (dbg_sel_idel_cpt),
.dbg_sel_all_idel_cpt (dbg_sel_all_idel_cpt)
);
endmodule
|
/*******************************************************************************
* Module: simul_axi_hp_rd
* Date:2015-04-25
* Author: Andrey Filippov
* Description: Simplified model of AXI_HP read channel (64-bit only)
*
* Copyright (c) 2015 Elphel, Inc.
* simul_axi_hp_rd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_hp_rd.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_hp_rd #(
parameter [1:0] HP_PORT=0
)(
input rst,
// AXI signals
input aclk,
output aresetn, // do not use?
// read address
input [31:0] araddr,
input arvalid,
output arready,
input [ 5:0] arid,
input [ 1:0] arlock,
input [ 3:0] arcache,
input [ 2:0] arprot,
input [ 3:0] arlen,
input [ 1:0] arsize,
input [ 1:0] arburst,
input [ 3:0] arqos,
// read data
output [63:0] rdata,
output rvalid,
input rready,
output [ 5:0] rid,
output rlast,
output [ 1:0] rresp,
// PL extra (non-AXI) signals
output [ 7:0] rcount,
output [ 2:0] racount,
input rdissuecap1en,
// Simulation signals - use same aclk
output [31:0] sim_rd_address,
output [ 5:0] sim_rid,
input sim_rd_valid,
output sim_rd_ready,
input [63:0] sim_rd_data,
output [ 2:0] sim_rd_cap,
output [ 3:0] sim_rd_qos,
input [ 1:0] sim_rd_resp,
input [31:0] reg_addr,
input reg_wr,
input reg_rd,
input [31:0] reg_din,
output [31:0] reg_dout
);
localparam AFI_BASECTRL= 32'hf8008000+ (HP_PORT << 12);
localparam AFI_RDCHAN_CTRL= AFI_BASECTRL + 'h00;
localparam AFI_RDCHAN_ISSUINGCAP= AFI_BASECTRL + 'h4;
localparam AFI_RDQOS= AFI_BASECTRL + 'h8;
localparam AFI_RDDATAFIFO_LEVEL= AFI_BASECTRL + 'hc;
localparam AFI_RDDEBUG= AFI_BASECTRL + 'h10; // SuppressThisWarning VEditor - not yet used
localparam VALID_ARLOCK = 2'b0; // TODO
localparam VALID_ARCACHE = 4'b0011; //
localparam VALID_ARPROT = 3'b000;
localparam VALID_ARLOCK_MASK = 2'b11; // TODO
localparam VALID_ARCACHE_MASK = 4'b0011; //
localparam VALID_ARPROT_MASK = 3'b010;
assign aresetn= ~rst; // probably not needed at all - docs say "do not use"
reg rdQosHeadOfCmdQEn = 0;
reg rdFabricOutCmdEn = 0;
reg rdFabricQosEn = 0;
reg rd32BitEn = 0; // verify it i 0
reg [2:0] rdIssueCap1 = 0;
reg [2:0] rdIssueCap0 = 7;
reg [3:0] rdStaticQos = 0;
wire [3:0] rd_qos_in;
wire [3:0] rd_qos_out;
/*
wire aw_nempty;
wire w_nempty;
wire enough_data; // enough data to start a new burst
wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
reg [31:0] write_address;
wire fifo_wd_rd; // read data fifo
wire last_confirmed_write;
*/
wire [5:0] arid_out; // verify it matches wid_out when outputting data
wire [1:0] arburst_out;
wire [1:0] arsize_out; // verify it is 3'h3
wire [3:0] arlen_out;
wire [31:0] araddr_out;
wire ar_nempty;
wire r_nempty;
reg [7:0] fifo_with_requested=0; // fill level of data FIFO if all the requested data will arrive and nothing read
wire fifo_data_rd;
wire [7:0] next_with_requested;
wire start_read_burst_w;
reg was_data_fifo_read; // previos cycle was reading data from FIFO
reg was_data_fifo_write;// previos cycle was writing data to FIFO
reg was_addr_fifo_write; // previos cycle was writing addressto FIFO
wire read_in_progress_w; // should go inactive last confirmed upstream cycle
reg read_in_progress;
reg [3:0] read_left;
reg [1:0] rburst;
reg [3:0] rlen;
wire [11:3] next_rd_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit)
reg [31:0] read_address;
wire last_confirmed_read;
wire last_read;
// sim_rd_address =
assign sim_rd_qos = (rdQosHeadOfCmdQEn && (rd_qos_in > rd_qos_out))? rd_qos_in : rd_qos_out;
assign sim_rd_cap = (rdFabricOutCmdEn && rdissuecap1en) ? rdIssueCap1 : rdIssueCap0;
assign rd_qos_in = rdFabricQosEn?(arqos & {4{arvalid}}) : rdStaticQos;
//awqos & {4{awvalid}}
assign aresetn= ~rst; // probably not needed at all - docs say "do not use"
//Supported control register fields
assign reg_dout=(reg_rd && (reg_addr==AFI_RDDATAFIFO_LEVEL))?
{24'b0,rcount}:
( (reg_rd && (reg_addr==AFI_RDCHAN_CTRL))?
{28'b0,rdQosHeadOfCmdQEn,rdFabricOutCmdEn,rdFabricQosEn,rd32BitEn}:
( (reg_rd && (reg_addr==AFI_RDCHAN_ISSUINGCAP))?
{25'b0,rdIssueCap1,1'b0,rdIssueCap0}:
( (reg_rd && (reg_addr==AFI_RDQOS))?
{28'b0,rdStaticQos}:32'bz)));
always @ (posedge aclk or posedge rst) begin
if (rst) begin
rdQosHeadOfCmdQEn <= 0;
rdFabricOutCmdEn <= 0;
rdFabricQosEn <= 1;
rd32BitEn <= 0;
end else if (reg_wr && (reg_addr==AFI_RDCHAN_CTRL)) begin
rdQosHeadOfCmdQEn <= reg_din[3];
rdFabricOutCmdEn <= reg_din[2];
rdFabricQosEn <= reg_din[1];
rd32BitEn <= reg_din[0];
end
if (rst) begin
rdIssueCap1 <= 0;
rdIssueCap0 <= 7;
end else if (reg_wr && (reg_addr==AFI_RDCHAN_ISSUINGCAP)) begin
rdIssueCap1 <= reg_din[6:4];
rdIssueCap0 <= reg_din[2:0];
end
if (rst) begin
rdStaticQos <= 0;
end else if (reg_wr && (reg_addr==AFI_RDQOS)) begin
rdStaticQos <= reg_din[3:0];
end
end
assign fifo_data_rd = rvalid && rready;
assign next_with_requested= fifo_with_requested + {4'b0,arlen_out[3:0]} + {7'h0,~fifo_data_rd};
assign start_read_burst_w= ar_nempty && (next_with_requested <= 8'h80) &&
(! read_in_progress || last_confirmed_read);
assign read_in_progress_w= ar_nempty && (next_with_requested <= 8'h80) ||
(read_in_progress && !last_confirmed_read);
// assign rvalid= (|rcount[7:1]) || (rcount[0] && !was_data_fifo_read);
assign rvalid= r_nempty && ((|rcount[7:1]) || !was_data_fifo_read);
assign arready= !racount[2] && (!racount[1] || !racount[0] || !was_addr_fifo_write);
assign last_read = (read_left==0);
assign last_confirmed_read = (read_left==0) && sim_rd_valid && sim_rd_ready;
// AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer)
// in 64 bit mode - low 3 bits are preserved, next 9 are incremented
assign next_rd_address[11:3] =
rburst[1]?
(rburst[0]? {9'bx}:((read_address[11:3] + 1) & {5'h1f, ~rlen[3:0]})):
(rburst[0]? (read_address[11:3]+1):(read_address[11:3]));
assign sim_rd_address = read_address;
assign sim_rid = arid_out;
// Current model policy is not to initiate a new burst (read from simulation port) if it may overflow FIFO
// - maybe the real module is done this way to aggregate external accesses.
// So 'assign sim_rd_ready = read_in_progress;' should be sufficient, but if that will chnage - below is
// full vesion that does not depend on the assumption.
assign sim_rd_ready = read_in_progress &&
!rcount[7] && (!(&rcount[6:0]) || !was_data_fifo_write);
always @ (posedge aclk) begin
if (start_read_burst_w) begin
if (arsize_out != 2'h3) begin
$display ("%m: at time %t ERROR: arsize_out=%h, currently only 'h3 (8 bytes) is valid",$time,arsize_out);
$stop;
end
end
if (arvalid && arready) begin
if (((arlock ^ VALID_ARLOCK) & VALID_ARLOCK_MASK) != 0) begin
$display ("%m: at time %t ERROR: arlock = %h, valid %h with mask %h",$time, arlock, VALID_ARLOCK, VALID_ARLOCK_MASK);
$stop;
end
if (((arcache ^ VALID_ARCACHE) & VALID_ARCACHE_MASK) != 0) begin
$display ("%m: at time %t ERROR: arcache = %h, valid %h with mask %h",$time, arcache, VALID_ARCACHE, VALID_ARCACHE_MASK);
$stop;
end
if (((arprot ^ VALID_ARPROT) & VALID_ARPROT_MASK) != 0) begin
$display ("%m: at time %t ERROR: arprot = %h, valid %h with mask %h",$time, arprot, VALID_ARPROT, VALID_ARPROT_MASK);
$stop;
end
end
end
always @ (posedge aclk or posedge rst) begin
if (rst) fifo_with_requested <= 0;
else if (start_read_burst_w) fifo_with_requested <= next_with_requested;
else fifo_with_requested <= fifo_with_requested - {7'h0,fifo_data_rd};
if (rst) was_data_fifo_read <= 0;
else was_data_fifo_read <= rvalid && rready;
if (rst) was_addr_fifo_write <= 0;
else was_addr_fifo_write <= arvalid && arready;
if (rst) was_data_fifo_write <= 0;
else was_data_fifo_write <= sim_rd_valid && sim_rd_ready;
if (rst) rburst[1:0] <= 0;
else if (start_read_burst_w) rburst[1:0] <= arburst_out[1:0];
if (rst) rlen[3:0] <= 0;
else if (start_read_burst_w) rlen[3:0] <= arlen_out[3:0];
if (rst) read_in_progress <= 0;
else read_in_progress <= read_in_progress_w;
if (rst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (sim_rd_valid && sim_rd_ready) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) read_address <= 32'bx;
else if (start_read_burst_w) read_address <= araddr_out; // precedence over inc
else if (sim_rd_valid && sim_rd_ready) read_address <= {read_address[31:12],next_rd_address[11:3],read_address[2:0]};
end
fifo_same_clock_fill #( .DATA_WIDTH(50),.DATA_DEPTH(2)) // read - 4, write - 32?
raddr_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (arvalid && arready),
.re (start_read_burst_w),
.data_in ({arid[5:0], arburst[1:0], arsize[1:0], arlen[3:0], araddr[31:0], rd_qos_in[3:0]}),
.data_out ({arid_out[5:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[31:0], rd_qos_out[3:0]}),
.nempty (ar_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under), // output reg
.over (), //waddr_over), // output reg
.wcount (), //waddr_wcount), // output[3:0] reg
.rcount (), //waddr_rcount), // output[3:0] reg
.wnum_in_fifo (racount), // output[3:0]
.rnum_in_fifo () // output[3:0]
);
fifo_same_clock_fill #( .DATA_WIDTH(73),.DATA_DEPTH(7)) // read - 4, write - 32?
rdata_i (
.rst (rst),
.clk (aclk),
.sync_rst (1'b0),
.we (sim_rd_valid && sim_rd_ready),
.re (rvalid && rready),
.data_in ({last_read, arid_out[5:0], sim_rd_resp[1:0], sim_rd_data[63:0]}),
.data_out ({rlast, rid[5:0], rresp[1:0], rdata[63:0]}),
.nempty (r_nempty), //r_nempty),
.half_full (), //aw_half_full),
.under (), //waddr_under),
.over (), //waddr_over),
.wcount (), //waddr_wcount),
.rcount (), //waddr_rcount),
.wnum_in_fifo (),
.rnum_in_fifo (rcount)
);
endmodule
|
`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 02:10:17 05/08/2017
// Design Name: axi_spi_if
// Module Name: D:/Projects/Rendszerarch/axi_spi_master_if/axi_spi/axi_spi_test.v
// Project Name: axi_spi
// Target Device:
// Tool versions:
// Description:
//
// Verilog Test Fixture created by ISE for module: axi_spi_if
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////
module axi_spi_test;
// Inputs
reg clk_i;
reg reset_n_i;
reg awvalid_i;
reg [27:0] awaddr_i;
reg awprot_i;
reg wvalid_i;
reg [31:0] wdata_i;
reg [3:0] wstrb_i;
reg bready_i;
reg arvalid_i;
reg [27:0] araddr_i;
reg [2:0] arprot_i;
reg rready_i;
reg spi_miso_i;
// Outputs
wire awready_o;
wire wready_o;
wire bvalid_o;
wire [1:0] bresp_o;
wire arready_o;
wire rvalid_o;
wire [31:0] rdata_o;
wire [1:0] rresp_o;
wire [3:0] spi_ssel_o;
wire spi_sck_o;
wire spi_mosi_o;
// Instantiate the Unit Under Test (UUT)
axi_spi_if uut (
.clk_i(clk_i),
.reset_n_i(reset_n_i),
.awvalid_i(awvalid_i),
.awready_o(awready_o),
.awaddr_i(awaddr_i),
.awprot_i(awprot_i),
.wvalid_i(wvalid_i),
.wready_o(wready_o),
.wdata_i(wdata_i),
.wstrb_i(wstrb_i),
.bvalid_o(bvalid_o),
.bready_i(bready_i),
.bresp_o(bresp_o),
.arvalid_i(arvalid_i),
.arready_o(arready_o),
.araddr_i(araddr_i),
.arprot_i(arprot_i),
.rvalid_o(rvalid_o),
.rready_i(rready_i),
.rdata_o(rdata_o),
.rresp_o(rresp_o),
.spi_ssel_o(spi_ssel_o),
.spi_sck_o(spi_sck_o),
.spi_mosi_o(spi_mosi_o),
.spi_miso_i(spi_miso_i)
);
initial begin
// Initialize Inputs
clk_i = 0;
reset_n_i = 0;
awvalid_i = 0;
awaddr_i = 0;
awprot_i = 0;
wvalid_i = 0;
wdata_i = 0;
wstrb_i = 0;
bready_i = 0;
arvalid_i = 0;
araddr_i = 0;
arprot_i = 0;
rready_i = 0;
spi_miso_i = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset_n_i = 1;
spi_miso_i = 1;
/*
reg_control_i = 32'h0000_0602;
reg_trans_ctrl_i = 32'h0000_0002;
*/
wdata_i = 32'h0000_0602;
awaddr_i = 0;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#1000;
wdata_i = 32'h0000_0002;
awaddr_i = 1;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 3;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
wdata_i = 32'h0000_0073;
awaddr_i = 4;
awvalid_i = 1;
wvalid_i = 1;
wait(awready_o && wready_o);
@(posedge clk_i) #1;
awvalid_i = 0;
wvalid_i = 0;
#100;
end
always #5 clk_i = ~clk_i;
endmodule
|
(** * Rel: Properties of Relations *)
Require Export SfLib.
(** This short, optional chapter develops some basic definitions and a
few theorems about binary relations in Coq. The key definitions
are repeated where they are actually used (in the [Smallstep]
chapter), so readers who are already comfortable with these ideas
can safely skim or skip this chapter. However, relations are also
a good source of exercises for developing facility with Coq's
basic reasoning facilities, so it may be useful to look at it just
after the [Logic] chapter. *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Somewhat confusingly, the Coq standard library hijacks the generic
term "relation" for this specific instance. To maintain
consistency with the library, we will do the same. So, henceforth
the Coq identifier [relation] will always refer to a binary
relation between some set and itself, while the English word
"relation" can refer either to the specific Coq concept or the
more general concept of a relation between any number of possibly
different sets. The context of the discussion should always make
clear which is meant. *)
(** An example relation on [nat] is [le], the less-that-or-equal-to
relation which we usually write like this [n1 <= n2]. *)
Print le.
(* ====> Inductive le (n : nat) : nat -> Prop :=
le_n : n <= n
| le_S : forall m : nat, n <= m -> n <= S m *)
Check le : nat -> nat -> Prop.
Check le : relation nat.
(* ######################################################### *)
(** * Basic Properties of Relations *)
(** As anyone knows who has taken an undergraduate discrete math
course, there is a lot to be said about relations in general --
ways of classifying relations (are they reflexive, transitive,
etc.), theorems that can be proved generically about classes of
relations, constructions that build one relation from another,
etc. For example... *)
(** A relation [R] on a set [X] is a _partial function_ if, for every
[x], there is at most one [y] such that [R x y] -- i.e., if [R x
y1] and [R x y2] together imply [y1 = y2]. *)
Definition partial_function {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
(** For example, the [next_nat] relation defined earlier is a partial
function. *)
Print next_nat.
(* ====> Inductive next_nat (n : nat) : nat -> Prop :=
nn : next_nat n (S n) *)
Check next_nat : relation nat.
Theorem next_nat_partial_function :
partial_function next_nat.
Proof.
unfold partial_function.
intros x y1 y2 H1 H2.
inversion H1. inversion H2.
reflexivity. Qed.
(** However, the [<=] relation on numbers is not a partial function.
In short: Assume, for a contradiction, that [<=] is a partial
function. But then, since [0 <= 0] and [0 <= 1], it follows that
[0 = 1]. This is nonsense, so our assumption was
contradictory. *)
Theorem le_not_a_partial_function :
~ (partial_function le).
Proof.
unfold not. unfold partial_function. intros Hc.
assert (0 = 1) as Nonsense.
Case "Proof of assertion".
apply Hc with (x := 0).
apply le_n.
apply le_S. apply le_n.
inversion Nonsense. Qed.
(** **** Exercise: 2 stars, optional *)
(** Show that the [total_relation] defined in earlier is not a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Show that the [empty_relation] defined earlier is a partial
function. *)
(* FILL IN HERE *)
(** [] *)
(** A _reflexive_ relation on a set [X] is one for which every element
of [X] is related to itself. *)
Definition reflexive {X: Type} (R: relation X) :=
forall a : X, R a a.
Theorem le_reflexive :
reflexive le.
Proof.
unfold reflexive. intros n. apply le_n. Qed.
(** A relation [R] is _transitive_ if [R a c] holds whenever [R a b]
and [R b c] do. *)
Definition transitive {X: Type} (R: relation X) :=
forall a b c : X, (R a b) -> (R b c) -> (R a c).
Theorem le_trans :
transitive le.
Proof.
intros n m o Hnm Hmo.
induction Hmo.
Case "le_n". apply Hnm.
Case "le_S". apply le_S. apply IHHmo. Qed.
Theorem lt_trans:
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
apply le_S in Hnm.
apply le_trans with (a := (S n)) (b := (S m)) (c := o).
apply Hnm.
apply Hmo. Qed.
(** **** Exercise: 2 stars, optional *)
(** We can also prove [lt_trans] more laboriously by induction,
without using le_trans. Do this.*)
Theorem lt_trans' :
transitive lt.
Proof.
(* Prove this by induction on evidence that [m] is less than [o]. *)
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction Hmo as [| m' Hm'o].
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
(** Prove the same thing again by induction on [o]. *)
Theorem lt_trans'' :
transitive lt.
Proof.
unfold lt. unfold transitive.
intros n m o Hnm Hmo.
induction o as [| o'].
(* FILL IN HERE *) Admitted.
(** [] *)
(** The transitivity of [le], in turn, can be used to prove some facts
that will be useful later (e.g., for the proof of antisymmetry
below)... *)
Theorem le_Sn_le : forall n m, S n <= m -> n <= m.
Proof.
intros n m H. apply le_trans with (S n).
apply le_S. apply le_n.
apply H. Qed.
(** **** Exercise: 1 star, optional *)
Theorem le_S_n : forall n m,
(S n <= S m) -> (n <= m).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (le_Sn_n_inf) *)
(** Provide an informal proof of the following theorem:
Theorem: For every [n], [~(S n <= n)]
A formal proof of this is an optional exercise below, but try
the informal proof without doing the formal proof first.
Proof:
(* FILL IN HERE *)
[]
*)
(** **** Exercise: 1 star, optional *)
Theorem le_Sn_n : forall n,
~ (S n <= n).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Reflexivity and transitivity are the main concepts we'll need for
later chapters, but, for a bit of additional practice working with
relations in Coq, here are a few more common ones.
A relation [R] is _symmetric_ if [R a b] implies [R b a]. *)
Definition symmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a).
(** **** Exercise: 2 stars, optional *)
Theorem le_not_symmetric :
~ (symmetric le).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation [R] is _antisymmetric_ if [R a b] and [R b a] together
imply [a = b] -- that is, if the only "cycles" in [R] are trivial
ones. *)
Definition antisymmetric {X: Type} (R: relation X) :=
forall a b : X, (R a b) -> (R b a) -> a = b.
(** **** Exercise: 2 stars, optional *)
Theorem le_antisymmetric :
antisymmetric le.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional *)
Theorem le_step : forall n m p,
n < m ->
m <= S p ->
n <= p.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** A relation is an _equivalence_ if it's reflexive, symmetric, and
transitive. *)
Definition equivalence {X:Type} (R: relation X) :=
(reflexive R) /\ (symmetric R) /\ (transitive R).
(** A relation is a _partial order_ when it's reflexive,
_anti_-symmetric, and transitive. In the Coq standard library
it's called just "order" for short. *)
Definition order {X:Type} (R: relation X) :=
(reflexive R) /\ (antisymmetric R) /\ (transitive R).
(** A preorder is almost like a partial order, but doesn't have to be
antisymmetric. *)
Definition preorder {X:Type} (R: relation X) :=
(reflexive R) /\ (transitive R).
Theorem le_order :
order le.
Proof.
unfold order. split.
Case "refl". apply le_reflexive.
split.
Case "antisym". apply le_antisymmetric.
Case "transitive.". apply le_trans. Qed.
(* ########################################################### *)
(** * Reflexive, Transitive Closure *)
(** The _reflexive, transitive closure_ of a relation [R] is the
smallest relation that contains [R] and that is both reflexive and
transitive. Formally, it is defined like this in the Relations
module of the Coq standard library: *)
Inductive clos_refl_trans {A: Type} (R: relation A) : relation A :=
| rt_step : forall x y, R x y -> clos_refl_trans R x y
| rt_refl : forall x, clos_refl_trans R x x
| rt_trans : forall x y z,
clos_refl_trans R x y ->
clos_refl_trans R y z ->
clos_refl_trans R x z.
(** For example, the reflexive and transitive closure of the
[next_nat] relation coincides with the [le] relation. *)
Theorem next_nat_closure_is_le : forall n m,
(n <= m) <-> ((clos_refl_trans next_nat) n m).
Proof.
intros n m. split.
Case "->".
intro H. induction H.
SCase "le_n". apply rt_refl.
SCase "le_S".
apply rt_trans with m. apply IHle. apply rt_step. apply nn.
Case "<-".
intro H. induction H.
SCase "rt_step". inversion H. apply le_S. apply le_n.
SCase "rt_refl". apply le_n.
SCase "rt_trans".
apply le_trans with y.
apply IHclos_refl_trans1.
apply IHclos_refl_trans2. Qed.
(** The above definition of reflexive, transitive closure is
natural -- it says, explicitly, that the reflexive and transitive
closure of [R] is the least relation that includes [R] and that is
closed under rules of reflexivity and transitivity. But it turns
out that this definition is not very convenient for doing
proofs -- the "nondeterminism" of the [rt_trans] rule can sometimes
lead to tricky inductions.
Here is a more useful definition... *)
Inductive refl_step_closure {X:Type} (R: relation X) : relation X :=
| rsc_refl : forall (x : X), refl_step_closure R x x
| rsc_step : forall (x y z : X),
R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
(** (Note that, aside from the naming of the constructors, this
definition is the same as the [multi] step relation used in many
other chapters.) *)
(** (The following [Tactic Notation] definitions are explained in
another chapter. You can ignore them if you haven't read the
explanation yet.) *)
Tactic Notation "rt_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rt_step" | Case_aux c "rt_refl"
| Case_aux c "rt_trans" ].
Tactic Notation "rsc_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "rsc_refl" | Case_aux c "rsc_step" ].
(** Our new definition of reflexive, transitive closure "bundles"
the [rt_step] and [rt_trans] rules into the single rule step.
The left-hand premise of this step is a single use of [R],
leading to a much simpler induction principle.
Before we go on, we should check that the two definitions do
indeed define the same relation...
First, we prove two lemmas showing that [refl_step_closure] mimics
the behavior of the two "missing" [clos_refl_trans]
constructors. *)
Theorem rsc_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> refl_step_closure R x y.
Proof.
intros X R x y H.
apply rsc_step with y. apply H. apply rsc_refl. Qed.
(** **** Exercise: 2 stars, optional (rsc_trans) *)
Theorem rsc_trans :
forall (X:Type) (R: relation X) (x y z : X),
refl_step_closure R x y ->
refl_step_closure R y z ->
refl_step_closure R x z.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** Then we use these facts to prove that the two definitions of
reflexive, transitive closure do indeed define the same
relation. *)
(** **** Exercise: 3 stars, optional (rtc_rsc_coincide) *)
Theorem rtc_rsc_coincide :
forall (X:Type) (R: relation X) (x y : X),
clos_refl_trans R x y <-> refl_step_closure R x y.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
/* Generated by Yosys 0.7 (git sha1 61f6811, gcc 5.4.0-6ubuntu1~16.04.4 -O2 -fstack-protector-strong -fPIC -Os) */
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:1" *)
module control(start, clk, rst, data, data_out2, data_out, parameter_Block, parameter_Block2);
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0000_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0001_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0002_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [7:0] _0003_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [7:0] _0004_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0005_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0006_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0007_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0008_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0009_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0010_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
wire [4:0] _0011_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0012_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0013_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0014_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0015_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0016_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0017_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0018_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0019_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0020_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0021_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0022_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0023_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0024_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0025_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0026_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0027_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0028_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0029_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0030_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0031_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0032_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0033_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0034_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0035_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0036_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0037_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0038_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0039_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0040_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0041_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0042_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0043_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0044_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0045_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0046_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0047_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0048_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0049_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0050_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0051_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0052_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0053_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0054_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0055_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0056_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0057_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0058_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0059_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0060_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0061_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0062_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0063_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0064_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0065_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0066_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0067_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0068_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0069_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0070_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0071_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0072_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0073_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0074_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0075_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0076_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0077_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0078_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0079_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0080_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0081_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [7:0] _0082_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [7:0] _0083_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0084_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0085_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0086_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0087_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0088_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0089_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0090_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0091_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0092_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0093_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0094_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0095_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0096_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0097_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0098_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0099_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0100_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0101_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0102_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0103_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0104_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0105_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0106_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0107_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0108_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0109_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0110_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0111_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0112_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0113_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0114_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0115_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0116_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0117_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0118_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0119_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0120_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0121_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0122_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0123_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0124_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0125_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0126_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0127_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0128_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0129_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0130_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0131_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0132_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0133_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0134_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0135_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0136_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0137_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0138_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0139_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0140_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0141_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0142_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0143_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0144_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0145_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0146_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0147_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0148_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0149_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0150_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0151_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0152_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0153_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0154_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0155_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0156_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0157_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0158_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0159_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0160_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0161_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0162_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0163_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0164_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0165_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0166_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0167_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0168_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0169_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [63:0] _0170_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0171_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0172_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [15:0] _0173_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [31:0] _0174_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire [4:0] _0175_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
wire _0176_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:379" *)
wire [31:0] _0177_;
wire [1:0] _0178_;
wire _0179_;
wire [1:0] _0180_;
wire _0181_;
wire [1:0] _0182_;
wire _0183_;
wire [1:0] _0184_;
wire _0185_;
wire [1:0] _0186_;
wire _0187_;
wire [1:0] _0188_;
wire _0189_;
wire _0190_;
wire _0191_;
wire _0192_;
wire [15:0] _0193_;
wire [7:0] _0194_;
wire [3:0] _0195_;
wire [1:0] _0196_;
wire [15:0] _0197_;
wire [7:0] _0198_;
wire [3:0] _0199_;
wire [1:0] _0200_;
wire [15:0] _0201_;
wire [7:0] _0202_;
wire [3:0] _0203_;
wire [1:0] _0204_;
wire [15:0] _0205_;
wire [7:0] _0206_;
wire [3:0] _0207_;
wire [1:0] _0208_;
wire [15:0] _0209_;
wire [7:0] _0210_;
wire [3:0] _0211_;
wire [1:0] _0212_;
wire [15:0] _0213_;
wire [7:0] _0214_;
wire [3:0] _0215_;
wire [1:0] _0216_;
wire [15:0] _0217_;
wire [7:0] _0218_;
wire [3:0] _0219_;
wire [1:0] _0220_;
wire [15:0] _0221_;
wire [7:0] _0222_;
wire [3:0] _0223_;
wire [1:0] _0224_;
wire [15:0] _0225_;
wire [7:0] _0226_;
wire [3:0] _0227_;
wire [1:0] _0228_;
wire [2:0] _0229_;
wire [1:0] _0230_;
wire [2:0] _0231_;
wire [1:0] _0232_;
wire [2:0] _0233_;
wire [1:0] _0234_;
wire [2:0] _0235_;
wire [1:0] _0236_;
wire [2:0] _0237_;
wire [1:0] _0238_;
wire [2:0] _0239_;
wire [1:0] _0240_;
wire [1:0] _0241_;
wire [1:0] _0242_;
wire _0243_;
wire _0244_;
wire _0245_;
wire _0246_;
wire _0247_;
wire _0248_;
wire _0249_;
wire _0250_;
wire _0251_;
wire _0252_;
wire _0253_;
wire _0254_;
wire _0255_;
wire _0256_;
wire _0257_;
wire _0258_;
wire [3:0] _0259_;
wire [1:0] _0260_;
wire [3:0] _0261_;
wire [1:0] _0262_;
wire [3:0] _0263_;
wire [1:0] _0264_;
wire [3:0] _0265_;
wire [1:0] _0266_;
wire [3:0] _0267_;
wire [1:0] _0268_;
wire [1:0] _0269_;
wire [1:0] _0270_;
wire [3:0] _0271_;
wire [1:0] _0272_;
wire [1:0] _0273_;
wire [3:0] _0274_;
wire [1:0] _0275_;
wire [1:0] _0276_;
wire [7:0] _0277_;
wire [3:0] _0278_;
wire [1:0] _0279_;
wire [7:0] _0280_;
wire [3:0] _0281_;
wire [1:0] _0282_;
wire [7:0] _0283_;
wire [3:0] _0284_;
wire [1:0] _0285_;
wire [3:0] _0286_;
wire [1:0] _0287_;
wire [3:0] _0288_;
wire [1:0] _0289_;
wire [7:0] _0290_;
wire [3:0] _0291_;
wire [1:0] _0292_;
wire [7:0] _0293_;
wire [3:0] _0294_;
wire [1:0] _0295_;
wire [7:0] _0296_;
wire [3:0] _0297_;
wire [1:0] _0298_;
wire [3:0] _0299_;
wire [1:0] _0300_;
wire [7:0] _0301_;
wire [3:0] _0302_;
wire [1:0] _0303_;
wire [7:0] _0304_;
wire [3:0] _0305_;
wire [1:0] _0306_;
wire [7:0] _0307_;
wire [3:0] _0308_;
wire [1:0] _0309_;
wire _0310_;
wire [3:0] _0311_;
wire [1:0] _0312_;
wire _0313_;
wire [7:0] _0314_;
wire [3:0] _0315_;
wire [1:0] _0316_;
wire _0317_;
wire [7:0] _0318_;
wire [3:0] _0319_;
wire [1:0] _0320_;
wire _0321_;
wire [7:0] _0322_;
wire [3:0] _0323_;
wire [1:0] _0324_;
wire _0325_;
wire [4:0] _0326_;
wire [4:0] _0327_;
wire [4:0] _0328_;
wire [4:0] _0329_;
wire [7:0] _0330_;
wire [7:0] _0331_;
wire [7:0] _0332_;
wire [7:0] _0333_;
wire [7:0] _0334_;
wire [7:0] _0335_;
wire [15:0] _0336_;
wire [7:0] _0337_;
wire [7:0] _0338_;
wire [15:0] _0339_;
wire [15:0] _0340_;
wire _0341_;
wire _0342_;
wire _0343_;
wire _0344_;
wire _0345_;
wire _0346_;
wire _0347_;
wire _0348_;
wire _0349_;
wire _0350_;
wire _0351_;
wire _0352_;
wire _0353_;
wire _0354_;
wire _0355_;
wire _0356_;
wire _0357_;
wire _0358_;
wire _0359_;
wire _0360_;
wire _0361_;
wire _0362_;
wire _0363_;
wire _0364_;
wire _0365_;
wire _0366_;
wire _0367_;
wire _0368_;
wire _0369_;
wire _0370_;
wire _0371_;
wire _0372_;
wire _0373_;
wire _0374_;
wire _0375_;
wire _0376_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *)
wire _0377_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *)
wire _0378_;
wire _0379_;
wire [15:0] _0380_;
wire [15:0] _0381_;
wire [15:0] _0382_;
wire [15:0] _0383_;
wire [15:0] _0384_;
wire [15:0] _0385_;
wire _0386_;
wire _0387_;
wire _0388_;
wire _0389_;
wire _0390_;
wire _0391_;
wire [15:0] _0392_;
wire [15:0] _0393_;
wire [15:0] _0394_;
wire _0395_;
wire [15:0] _0396_;
wire [15:0] _0397_;
wire [15:0] _0398_;
wire _0399_;
wire _0400_;
wire [15:0] _0401_;
wire [15:0] _0402_;
wire [15:0] _0403_;
wire [15:0] _0404_;
wire [15:0] _0405_;
wire [15:0] _0406_;
wire [15:0] _0407_;
wire [15:0] _0408_;
wire [15:0] _0409_;
wire _0410_;
wire _0411_;
wire _0412_;
wire _0413_;
wire _0414_;
wire _0415_;
wire _0416_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:432" *)
wire [34:0] _0417_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:428" *)
wire [4:0] _0418_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:432" *)
wire [3:0] _0419_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:428" *)
wire _0420_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:432" *)
wire [127:0] _0421_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:428" *)
wire [63:0] _0422_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:432" *)
wire [47:0] _0423_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:428" *)
wire [15:0] _0424_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:432" *)
wire [63:0] _0425_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:428" *)
wire [31:0] _0426_;
wire [15:0] _0427_;
wire [15:0] _0428_;
wire [15:0] _0429_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:253" *)
wire [31:0] _0430_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:298" *)
wire [31:0] _0431_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:351" *)
wire [31:0] _0432_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:386" *)
wire [31:0] _0433_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:407" *)
wire [31:0] _0434_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:440" *)
wire [31:0] _0435_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:574" *)
wire [31:0] _0436_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:595" *)
wire [31:0] _0437_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:628" *)
wire [31:0] _0438_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0439_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0440_;
wire [31:0] _0441_;
wire _0442_;
wire _0443_;
wire _0444_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0445_;
wire [31:0] _0446_;
wire _0447_;
wire _0448_;
wire _0449_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0450_;
wire [31:0] _0451_;
wire _0452_;
wire _0453_;
wire _0454_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0455_;
wire [31:0] _0456_;
wire _0457_;
wire _0458_;
wire _0459_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0460_;
wire [31:0] _0461_;
wire _0462_;
wire _0463_;
wire _0464_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0465_;
wire [31:0] _0466_;
wire _0467_;
wire _0468_;
wire _0469_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0470_;
wire [31:0] _0471_;
wire _0472_;
wire _0473_;
wire _0474_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0475_;
wire [31:0] _0476_;
wire _0477_;
wire _0478_;
wire _0479_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0480_;
wire [31:0] _0481_;
wire _0482_;
wire _0483_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *)
wire _0484_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *)
wire _0485_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *)
wire _0486_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *)
wire _0487_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *)
wire _0488_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0489_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0490_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0491_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0492_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0493_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0494_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0495_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0496_;
(* src = "<techmap.v>:260|<techmap.v>:203" *)
wire [31:0] _0497_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0498_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0499_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0500_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0501_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0502_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0503_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0504_;
(* src = "<techmap.v>:260|<techmap.v>:222" *)
wire _0505_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0506_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0507_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0508_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0509_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0510_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0511_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0512_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0513_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0514_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0515_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0516_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0517_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0518_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0519_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0520_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0521_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0522_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0523_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0524_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0525_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0526_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0527_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0528_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0529_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0530_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0531_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0532_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0533_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0534_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0535_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0536_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0537_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0538_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0539_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0540_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0541_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0542_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0543_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0544_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0545_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0546_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0547_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0548_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0549_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0550_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0551_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0552_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0553_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0554_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0555_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0556_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0557_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0558_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0559_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0560_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0561_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0562_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0563_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0564_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0565_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0566_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0567_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0568_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0569_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0570_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0571_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0572_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0573_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0574_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0575_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0576_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0577_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0578_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0579_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0580_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0581_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0582_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0583_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0584_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0585_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0586_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0587_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0588_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0589_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0590_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0591_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0592_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0593_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0594_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0595_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0596_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0597_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0598_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0599_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0600_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0601_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0602_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0603_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0604_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0605_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0606_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0607_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0608_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0609_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0610_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0611_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0612_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0613_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0614_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0615_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0616_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0617_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0618_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0619_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0620_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0621_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0622_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0623_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0624_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0625_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0626_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0627_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0628_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0629_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0630_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0631_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0632_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0633_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0634_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0635_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0636_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0637_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0638_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0639_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0640_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0641_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0642_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0643_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0644_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0645_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0646_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0647_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0648_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0649_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0650_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0651_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0652_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0653_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0654_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0655_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0656_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0657_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0658_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0659_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0660_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0661_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0662_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0663_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0664_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0665_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0666_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0667_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0668_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0669_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0670_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0671_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0672_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0673_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0674_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0675_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0676_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0677_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0678_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0679_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0680_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0681_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0682_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0683_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0684_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0685_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0686_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0687_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0688_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0689_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0690_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0691_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0692_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0693_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0694_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0695_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0696_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0697_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0698_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0699_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0700_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0701_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0702_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0703_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0704_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0705_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0706_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0707_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0708_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0709_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0710_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0711_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0712_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0713_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0714_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0715_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0716_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0717_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0718_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0719_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0720_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0721_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0722_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0723_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0724_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0725_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0726_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0727_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0728_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0729_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0730_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0731_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0732_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0733_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0734_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0735_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0736_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0737_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0738_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0739_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0740_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0741_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0742_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0743_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0744_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0745_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0746_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0747_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0748_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0749_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0750_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0751_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0752_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0753_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0754_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0755_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0756_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0757_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0758_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0759_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0760_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0761_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0762_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0763_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0764_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0765_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0766_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0767_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0768_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0769_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0770_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0771_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0772_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0773_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0774_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0775_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0776_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0777_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0778_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0779_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0780_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0781_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0782_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0783_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0784_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0785_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0786_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0787_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0788_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0789_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0790_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0791_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0792_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0793_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0794_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0795_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0796_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0797_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0798_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0799_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0800_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0801_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0802_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0803_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0804_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0805_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0806_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0807_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0808_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0809_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0810_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0811_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0812_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0813_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0814_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0815_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0816_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0817_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0818_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0819_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0820_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0821_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0822_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0823_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0824_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0825_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0826_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0827_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0828_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0829_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0830_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0831_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0832_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0833_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0834_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0835_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0836_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0837_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0838_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0839_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0840_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0841_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0842_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0843_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0844_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0845_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0846_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0847_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0848_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0849_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0850_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0851_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0852_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0853_;
(* src = "<techmap.v>:260|<techmap.v>:221" *)
wire _0854_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0855_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0856_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0857_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0858_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0859_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0860_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0861_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0862_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0863_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0864_;
(* src = "<techmap.v>:260|<techmap.v>:229" *)
wire _0865_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:36" *)
reg [63:0] address;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:32" *)
reg [31:0] addresstemp1;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:33" *)
reg [31:0] addresstemp2;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:21" *)
reg [7:0] bRequest;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:20" *)
reg [7:0] bmRequestType;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:12" *)
input clk;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:22" *)
reg [15:0] count;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:14" *)
input [63:0] data;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:17" *)
output [31:0] data_out;
reg [31:0] data_out;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:18" *)
output [63:0] data_out2;
reg [63:0] data_out2;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:39" *)
reg [4:0] next_state;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:15" *)
input [31:0] parameter_Block;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:16" *)
input [63:0] parameter_Block2;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:28" *)
reg [31:0] readWrite;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:13" *)
input rst;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:34" *)
reg singl_data;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:11" *)
input start;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:39" *)
reg [4:0] state;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:30" *)
wire [15:0] wIndex;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:31" *)
reg [15:0] wLength;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:29" *)
wire [15:0] wValue;
assign _0341_ = _0179_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0342_ = _0181_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0343_ = _0183_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0184_[0] = _0327_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[1];
assign _0185_ = _0184_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0180_[1];
assign _0344_ = _0185_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0186_[1] = state[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0328_[3];
assign _0187_ = _0178_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0186_[1];
assign _0345_ = _0187_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0179_ = _0178_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0178_[1];
assign _0346_ = _0179_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0329_[4];
assign _0189_ = _0178_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0188_[1];
assign _0347_ = _0189_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0180_[0] = _0327_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0327_[1];
assign _0181_ = _0180_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0180_[1];
assign _0348_ = _0181_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0329_[4];
assign _0178_[1] = _0326_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[3];
assign _0190_ = _0182_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0178_[1];
assign _0349_ = _0190_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0188_[1] = _0326_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0328_[3];
assign _0191_ = _0182_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0188_[1];
assign _0350_ = _0191_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[4];
assign _0182_[0] = state[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0327_[1];
assign _0183_ = _0182_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0180_[1];
assign _0351_ = _0183_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0329_[4];
assign _0178_[0] = state[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[1];
assign _0180_[1] = state[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) state[3];
assign _0192_ = _0178_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0180_[1];
assign _0352_ = _0192_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0329_[4];
assign _0102_ = _0478_ | _0196_[0];
assign _0193_[0] = _0438_[0] & _0476_[1];
assign _0194_[0] = _0193_[0] & _0193_[1];
assign _0195_[0] = _0194_[0] & _0194_[1];
assign _0196_[0] = _0195_[0] & _0195_[1];
assign _0078_ = _0473_ | _0200_[0];
assign _0197_[0] = _0437_[0] & _0471_[1];
assign _0198_[0] = _0197_[0] & _0197_[1];
assign _0199_[0] = _0198_[0] & _0198_[1];
assign _0200_[0] = _0199_[0] & _0199_[1];
assign _0378_ = _0468_ | _0204_[0];
assign _0201_[0] = _0436_[0] & _0466_[1];
assign _0202_[0] = _0201_[0] & _0201_[1];
assign _0202_[2] = _0201_[4] & _0201_[5];
assign _0203_[0] = _0202_[0] & _0202_[1];
assign _0204_[0] = _0203_[0] & _0203_[1];
assign _0064_ = _0463_ | _0208_[0];
assign _0205_[0] = _0435_[0] & _0461_[1];
assign _0205_[3] = _0461_[6] & _0461_[7];
assign _0206_[0] = _0205_[0] & _0205_[1];
assign _0207_[0] = _0206_[0] & _0206_[1];
assign _0208_[0] = _0207_[0] & _0207_[1];
assign _0054_ = _0458_ | _0212_[0];
assign _0209_[0] = _0434_[0] & _0456_[1];
assign _0209_[4] = _0456_[8] & _0456_[9];
assign _0209_[6] = _0456_[12] & _0456_[13];
assign _0209_[7] = _0456_[14] & _0456_[15];
assign _0210_[0] = _0209_[0] & _0209_[1];
assign _0211_[0] = _0210_[0] & _0210_[1];
assign _0212_[0] = _0211_[0] & _0211_[1];
assign _0377_ = _0453_ | _0216_[0];
assign _0213_[0] = _0433_[0] & _0451_[1];
assign _0214_[0] = _0213_[0] & _0213_[1];
assign _0215_[0] = _0214_[0] & _0214_[1];
assign _0216_[0] = _0215_[0] & _0215_[1];
assign _0037_ = _0448_ | _0220_[0];
assign _0217_[0] = _0340_[0] & _0340_[1];
assign _0218_[0] = _0217_[0] & _0217_[1];
assign _0219_[0] = _0218_[0] & _0218_[1];
assign _0219_[1] = _0218_[2] & _0218_[3];
assign _0220_[0] = _0219_[0] & _0219_[1];
assign _0221_[0] = _0339_[0] & _0339_[1];
assign _0222_[0] = _0221_[0] & _0221_[1];
assign _0222_[1] = _0221_[2] & _0221_[3];
assign _0222_[3] = _0221_[6] & _0221_[7];
assign _0223_[0] = _0222_[0] & _0222_[1];
assign _0223_[1] = _0222_[2] & _0222_[3];
assign _0224_[0] = _0223_[0] & _0223_[1];
assign _0155_ = _0443_ | _0228_[0];
assign _0225_[0] = _0336_[0] & _0336_[1];
assign _0225_[1] = _0336_[2] & _0441_[3];
assign _0225_[2] = _0441_[4] & _0441_[5];
assign _0225_[5] = _0441_[10] & _0441_[11];
assign _0226_[0] = _0225_[0] & _0225_[1];
assign _0226_[1] = _0225_[2] & _0225_[3];
assign _0227_[0] = _0226_[0] & _0226_[1];
assign _0227_[1] = _0226_[2] & _0226_[3];
assign _0228_[0] = _0227_[0] & _0227_[1];
assign _0229_[0] = _0417_[3] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[8];
assign _0229_[1] = _0417_[13] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[18];
assign _0229_[2] = _0417_[23] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[28];
assign _0230_[0] = _0229_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0229_[1];
assign _0418_[3] = _0230_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0229_[2];
assign _0231_[0] = _0417_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[9];
assign _0231_[1] = _0417_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[19];
assign _0231_[2] = _0417_[24] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[29];
assign _0232_[0] = _0231_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0231_[1];
assign _0418_[4] = _0232_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0231_[2];
assign _0233_[0] = _0417_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[7];
assign _0233_[1] = _0417_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[17];
assign _0233_[2] = _0417_[22] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[27];
assign _0234_[0] = _0233_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0233_[1];
assign _0418_[2] = _0234_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0233_[2];
assign _0235_[0] = _0417_[1] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[6];
assign _0235_[1] = _0417_[11] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[16];
assign _0235_[2] = _0417_[21] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[26];
assign _0236_[0] = _0235_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0235_[1];
assign _0236_[1] = _0235_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[31];
assign _0418_[1] = _0236_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0236_[1];
assign _0237_[0] = _0417_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[5];
assign _0237_[1] = _0417_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[15];
assign _0237_[2] = _0417_[20] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[25];
assign _0238_[0] = _0237_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0237_[1];
assign _0238_[1] = _0237_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0417_[30];
assign _0418_[0] = _0238_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0238_[1];
assign _0239_[1] = _0400_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0413_;
assign _0239_[2] = _0414_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0415_;
assign _0240_[0] = _0239_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0239_[1];
assign _0240_[1] = _0239_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0416_;
assign _0484_ = _0240_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0240_[1];
assign _0241_[0] = _0419_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0419_[1];
assign _0241_[1] = _0419_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0419_[3];
assign _0420_ = _0241_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0241_[1];
assign _0242_[1] = _0400_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0416_;
assign _0485_ = _0239_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0242_[1];
assign _0422_[62] = _0421_[62] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[126];
assign _0422_[63] = _0421_[63] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[127];
assign _0422_[61] = _0421_[61] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[125];
assign _0422_[60] = _0421_[60] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[124];
assign _0422_[59] = _0421_[59] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[123];
assign _0422_[58] = _0421_[58] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[122];
assign _0422_[57] = _0421_[57] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[121];
assign _0422_[56] = _0421_[56] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[120];
assign _0422_[55] = _0421_[55] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[119];
assign _0422_[54] = _0421_[54] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[118];
assign _0422_[53] = _0421_[53] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[117];
assign _0422_[52] = _0421_[52] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[116];
assign _0422_[51] = _0421_[51] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[115];
assign _0422_[50] = _0421_[50] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[114];
assign _0422_[49] = _0421_[49] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[113];
assign _0422_[48] = _0421_[48] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[112];
assign _0422_[47] = _0421_[47] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[111];
assign _0422_[46] = _0421_[46] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[110];
assign _0422_[45] = _0421_[45] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[109];
assign _0422_[44] = _0421_[44] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[108];
assign _0422_[43] = _0421_[43] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[107];
assign _0422_[42] = _0421_[42] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[106];
assign _0422_[41] = _0421_[41] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[105];
assign _0422_[40] = _0421_[40] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[104];
assign _0422_[39] = _0421_[39] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[103];
assign _0422_[38] = _0421_[38] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[102];
assign _0422_[37] = _0421_[37] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[101];
assign _0422_[36] = _0421_[36] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[100];
assign _0422_[35] = _0421_[35] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[99];
assign _0422_[34] = _0421_[34] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[98];
assign _0422_[33] = _0421_[33] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[97];
assign _0422_[32] = _0421_[32] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[96];
assign _0422_[31] = _0421_[31] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[95];
assign _0422_[30] = _0421_[30] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[94];
assign _0422_[29] = _0421_[29] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[93];
assign _0422_[28] = _0421_[28] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[92];
assign _0422_[27] = _0421_[27] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[91];
assign _0422_[26] = _0421_[26] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[90];
assign _0422_[25] = _0421_[25] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[89];
assign _0422_[24] = _0421_[24] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[88];
assign _0422_[23] = _0421_[23] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[87];
assign _0422_[22] = _0421_[22] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[86];
assign _0422_[21] = _0421_[21] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[85];
assign _0422_[20] = _0421_[20] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[84];
assign _0422_[19] = _0421_[19] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[83];
assign _0422_[18] = _0421_[18] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[82];
assign _0422_[17] = _0421_[17] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[81];
assign _0422_[16] = _0421_[16] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[80];
assign _0422_[15] = _0421_[15] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[79];
assign _0422_[14] = _0421_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[78];
assign _0422_[13] = _0421_[13] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[77];
assign _0422_[12] = _0421_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[76];
assign _0422_[11] = _0421_[11] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[75];
assign _0422_[10] = _0421_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[74];
assign _0422_[9] = _0421_[9] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[73];
assign _0422_[8] = _0421_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[72];
assign _0422_[7] = _0421_[7] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[71];
assign _0422_[6] = _0421_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[70];
assign _0422_[5] = _0421_[5] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[69];
assign _0422_[4] = _0421_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[68];
assign _0422_[3] = _0421_[3] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[67];
assign _0422_[2] = _0421_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[66];
assign _0422_[1] = _0421_[1] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[65];
assign _0422_[0] = _0421_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0421_[64];
assign _0486_ = _0390_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0400_;
assign _0243_ = _0423_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[30];
assign _0424_[14] = _0243_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[46];
assign _0244_ = _0423_[15] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[31];
assign _0424_[15] = _0244_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[47];
assign _0245_ = _0423_[13] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[29];
assign _0424_[13] = _0245_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[45];
assign _0246_ = _0423_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[28];
assign _0424_[12] = _0246_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[44];
assign _0247_ = _0423_[11] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[27];
assign _0424_[11] = _0247_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[43];
assign _0248_ = _0423_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[26];
assign _0424_[10] = _0248_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[42];
assign _0249_ = _0423_[9] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[25];
assign _0424_[9] = _0249_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[41];
assign _0250_ = _0423_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[24];
assign _0424_[8] = _0250_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[40];
assign _0251_ = _0423_[7] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[23];
assign _0424_[7] = _0251_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[39];
assign _0252_ = _0423_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[22];
assign _0424_[6] = _0252_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[38];
assign _0253_ = _0423_[5] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[21];
assign _0424_[5] = _0253_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[37];
assign _0254_ = _0423_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[20];
assign _0424_[4] = _0254_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[36];
assign _0255_ = _0423_[3] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[19];
assign _0424_[3] = _0255_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[35];
assign _0256_ = _0423_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[18];
assign _0424_[2] = _0256_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[34];
assign _0257_ = _0423_[1] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[17];
assign _0424_[1] = _0257_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[33];
assign _0258_ = _0423_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[16];
assign _0424_[0] = _0258_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0423_[32];
assign _0239_[0] = _0379_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0391_;
assign _0487_ = _0239_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0400_;
assign _0426_[30] = _0425_[30] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[62];
assign _0426_[31] = _0425_[31] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[63];
assign _0426_[29] = _0425_[29] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[61];
assign _0426_[28] = _0425_[28] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[60];
assign _0426_[27] = _0425_[27] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[59];
assign _0426_[26] = _0425_[26] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[58];
assign _0426_[25] = _0425_[25] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[57];
assign _0426_[24] = _0425_[24] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[56];
assign _0426_[23] = _0425_[23] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[55];
assign _0426_[22] = _0425_[22] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[54];
assign _0426_[21] = _0425_[21] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[53];
assign _0426_[20] = _0425_[20] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[52];
assign _0426_[19] = _0425_[19] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[51];
assign _0426_[18] = _0425_[18] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[50];
assign _0426_[17] = _0425_[17] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[49];
assign _0426_[16] = _0425_[16] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[48];
assign _0426_[15] = _0425_[15] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[47];
assign _0426_[14] = _0425_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[46];
assign _0426_[13] = _0425_[13] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[45];
assign _0426_[12] = _0425_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[44];
assign _0426_[11] = _0425_[11] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[43];
assign _0426_[10] = _0425_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[42];
assign _0426_[9] = _0425_[9] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[41];
assign _0426_[8] = _0425_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[40];
assign _0426_[7] = _0425_[7] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[39];
assign _0426_[6] = _0425_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[38];
assign _0426_[5] = _0425_[5] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[37];
assign _0426_[4] = _0425_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[36];
assign _0426_[3] = _0425_[3] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[35];
assign _0426_[2] = _0425_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[34];
assign _0426_[1] = _0425_[1] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[33];
assign _0426_[0] = _0425_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:441" *) _0425_[32];
assign _0488_ = _0388_ |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0395_;
assign _0259_[0] = _0330_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) bmRequestType[1];
assign _0259_[1] = bmRequestType[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) bmRequestType[3];
assign _0259_[2] = bmRequestType[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) _0330_[5];
assign _0259_[3] = bmRequestType[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) bmRequestType[7];
assign _0260_[0] = _0259_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) _0259_[1];
assign _0260_[1] = _0259_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) _0259_[3];
assign _0353_ = _0260_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) _0260_[1];
assign _0354_ = _0262_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) _0262_[1];
assign _0355_ = _0264_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0262_[1];
assign _0356_ = _0266_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0262_[1];
assign _0357_ = _0268_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0262_[1];
assign _0358_ = _0269_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0262_[1];
assign _0359_ = _0270_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0262_[1];
assign _0272_[0] = _0261_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0271_[1];
assign _0360_ = _0272_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0262_[1];
assign _0271_[1] = bRequest[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0334_[3];
assign _0261_[3] = bRequest[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) bRequest[7];
assign _0273_[0] = _0263_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0271_[1];
assign _0262_[1] = _0261_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0261_[3];
assign _0361_ = _0273_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0262_[1];
assign _0262_[0] = _0261_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) _0261_[1];
assign _0362_ = _0262_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) _0275_[1];
assign _0264_[0] = _0263_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0261_[1];
assign _0363_ = _0264_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0275_[1];
assign _0261_[1] = bRequest[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) bRequest[3];
assign _0266_[0] = _0265_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0261_[1];
assign _0364_ = _0266_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0275_[1];
assign _0267_[0] = bRequest[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) bRequest[1];
assign _0268_[0] = _0267_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0267_[1];
assign _0365_ = _0268_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0275_[1];
assign _0261_[0] = _0331_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) bRequest[1];
assign _0269_[0] = _0261_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0267_[1];
assign _0366_ = _0269_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0275_[1];
assign _0263_[0] = bRequest[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0332_[1];
assign _0270_[0] = _0263_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0267_[1];
assign _0367_ = _0270_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0275_[1];
assign _0265_[0] = _0331_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0332_[1];
assign _0267_[1] = _0333_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) bRequest[3];
assign _0261_[2] = bRequest[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) bRequest[5];
assign _0274_[3] = bRequest[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0335_[7];
assign _0276_[0] = _0265_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0267_[1];
assign _0275_[1] = _0261_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0274_[3];
assign _0368_ = _0276_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0275_[1];
assign _0277_[0] = _0336_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) _0336_[1];
assign _0278_[0] = _0277_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) _0277_[1];
assign _0279_[0] = _0278_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) _0278_[1];
assign _0369_ = _0279_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) _0279_[1];
assign _0280_[0] = _0127_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) _0336_[1];
assign _0277_[1] = _0336_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) _0127_[3];
assign _0281_[0] = _0280_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) _0277_[1];
assign _0282_[0] = _0281_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) _0278_[1];
assign _0370_ = _0282_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) _0279_[1];
assign _0283_[0] = _0336_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:243" *) _0127_[1];
assign _0284_[0] = _0283_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:243" *) _0283_[1];
assign _0285_[0] = _0284_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:243" *) _0278_[1];
assign _0068_[0] = _0285_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:243" *) _0279_[1];
assign _0286_[0] = _0337_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:263" *) wValue[1];
assign _0287_[0] = _0286_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:263" *) _0286_[1];
assign _0371_ = _0287_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:263" *) _0287_[1];
assign _0288_[0] = wValue[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0338_[1];
assign _0286_[1] = wValue[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) wValue[3];
assign _0286_[2] = wValue[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) wValue[5];
assign _0286_[3] = wValue[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) wValue[7];
assign _0289_[0] = _0288_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0286_[1];
assign _0287_[1] = _0286_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0286_[3];
assign _0372_ = _0289_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0287_[1];
assign _0290_[0] = _0339_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0339_[1];
assign _0291_[0] = _0290_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0290_[1];
assign _0292_[0] = _0291_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0291_[1];
assign _0373_ = _0292_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0292_[1];
assign _0293_[0] = _0159_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0339_[1];
assign _0290_[1] = _0339_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0159_[3];
assign _0294_[0] = _0293_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0290_[1];
assign _0295_[0] = _0294_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0291_[1];
assign _0374_ = _0295_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0292_[1];
assign _0296_[0] = _0339_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:288" *) _0159_[1];
assign _0297_[0] = _0296_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:288" *) _0296_[1];
assign _0298_[0] = _0297_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:288" *) _0291_[1];
assign _0096_[0] = _0298_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:288" *) _0292_[1];
assign _0299_[0] = wIndex[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) wIndex[9];
assign _0299_[1] = wIndex[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) wIndex[11];
assign _0299_[2] = wIndex[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) wIndex[13];
assign _0299_[3] = wIndex[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) wIndex[15];
assign _0300_[0] = _0299_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0299_[1];
assign _0300_[1] = _0299_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0299_[3];
assign _0301_[0] = _0340_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0340_[1];
assign _0302_[0] = _0301_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0301_[1];
assign _0303_[0] = _0302_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0302_[1];
assign _0375_ = _0303_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0303_[1];
assign _0304_[0] = _0025_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0340_[1];
assign _0301_[1] = _0340_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0025_[3];
assign _0305_[0] = _0304_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0301_[1];
assign _0306_[0] = _0305_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0302_[1];
assign _0376_ = _0306_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0303_[1];
assign _0307_[0] = _0340_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:341" *) _0025_[1];
assign _0308_[0] = _0307_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:341" *) _0307_[1];
assign _0309_[0] = _0308_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:341" *) _0302_[1];
assign _0106_[0] = _0309_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:341" *) _0303_[1];
assign _0310_ = _0300_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) _0300_[1];
assign _0311_[0] = wValue[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) wValue[1];
assign _0312_[0] = _0311_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) _0286_[1];
assign _0313_ = _0312_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) _0287_[1];
assign _0314_[0] = _0127_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[1];
assign _0283_[1] = _0127_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[3];
assign _0277_[2] = _0127_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[5];
assign _0277_[3] = _0127_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[7];
assign _0277_[4] = _0127_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[9];
assign _0277_[5] = _0127_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[11];
assign _0277_[6] = _0127_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[13];
assign _0277_[7] = _0127_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0127_[15];
assign _0315_[0] = _0314_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0283_[1];
assign _0278_[1] = _0277_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0277_[3];
assign _0278_[2] = _0277_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0277_[5];
assign _0278_[3] = _0277_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0277_[7];
assign _0316_[0] = _0315_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0278_[1];
assign _0279_[1] = _0278_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0278_[3];
assign _0317_ = _0316_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0279_[1];
assign _0318_[0] = _0159_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[1];
assign _0296_[1] = _0159_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[3];
assign _0290_[2] = _0159_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[5];
assign _0290_[3] = _0159_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[7];
assign _0290_[4] = _0159_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[9];
assign _0290_[5] = _0159_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[11];
assign _0290_[6] = _0159_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[13];
assign _0290_[7] = _0159_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0159_[15];
assign _0319_[0] = _0318_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0296_[1];
assign _0291_[1] = _0290_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0290_[3];
assign _0291_[2] = _0290_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0290_[5];
assign _0291_[3] = _0290_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0290_[7];
assign _0320_[0] = _0319_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0291_[1];
assign _0292_[1] = _0291_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0291_[3];
assign _0321_ = _0320_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0292_[1];
assign _0322_[0] = _0025_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[1];
assign _0307_[1] = _0025_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[3];
assign _0301_[2] = _0025_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[5];
assign _0301_[3] = _0025_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[7];
assign _0301_[4] = _0025_[8] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[9];
assign _0301_[5] = _0025_[10] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[11];
assign _0301_[6] = _0025_[12] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[13];
assign _0301_[7] = _0025_[14] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0025_[15];
assign _0323_[0] = _0322_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0307_[1];
assign _0302_[1] = _0301_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0301_[3];
assign _0302_[2] = _0301_[4] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0301_[5];
assign _0302_[3] = _0301_[6] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0301_[7];
assign _0324_[0] = _0323_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0302_[1];
assign _0303_[1] = _0302_[2] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0302_[3];
assign _0325_ = _0324_[0] |(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0303_[1];
assign _0413_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0341_;
assign _0414_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0342_;
assign _0415_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0343_;
assign _0416_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0344_;
assign _0390_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0346_;
assign _0379_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0347_;
assign _0391_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0348_;
assign _0400_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0349_;
assign _0388_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0351_;
assign _0395_ = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) _0352_;
assign _0147_[56] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[24] : _0108_[56];
assign _0147_[57] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[25] : _0108_[57];
assign _0147_[58] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[26] : _0108_[58];
assign _0147_[59] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[27] : _0108_[59];
assign _0147_[60] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[28] : _0108_[60];
assign _0147_[61] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[29] : _0108_[61];
assign _0147_[62] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[30] : _0108_[62];
assign _0147_[63] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[31] : _0108_[63];
assign _0404_[0] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[0] : 1'b1;
assign _0404_[1] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[1] : 1'b1;
assign _0404_[2] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[2] : 1'b1;
assign _0404_[3] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[3] : 1'b0;
assign _0404_[4] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[4] : 1'b0;
assign _0404_[5] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[5] : 1'b0;
assign _0404_[6] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[6] : 1'b0;
assign _0404_[7] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[7] : 1'b0;
assign _0404_[8] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[8] : 1'b0;
assign _0404_[9] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[9] : 1'b0;
assign _0404_[10] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[10] : 1'b0;
assign _0404_[11] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[11] : 1'b0;
assign _0404_[12] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[12] : 1'b0;
assign _0404_[13] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[13] : 1'b0;
assign _0404_[14] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[14] : 1'b0;
assign _0404_[15] = _0132_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:271" *) _0111_[15] : 1'b0;
assign _0405_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[0];
assign _0405_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[1];
assign _0405_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[2];
assign _0405_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[3];
assign _0405_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[4];
assign _0405_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[5];
assign _0405_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[6];
assign _0405_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[7];
assign _0405_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[8];
assign _0405_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[9];
assign _0405_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[10];
assign _0405_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[11];
assign _0405_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[12];
assign _0405_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[13];
assign _0405_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[14];
assign _0405_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'bx : _0404_[15];
assign _0406_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[0];
assign _0406_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[1];
assign _0406_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[2];
assign _0406_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[3];
assign _0406_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[4];
assign _0406_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[5];
assign _0406_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[6];
assign _0406_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[7];
assign _0406_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[8];
assign _0406_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[9];
assign _0406_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[10];
assign _0406_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[11];
assign _0406_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[12];
assign _0406_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[13];
assign _0406_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[14];
assign _0406_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0405_[15];
assign _0159_[0] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[0];
assign _0159_[1] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[1];
assign _0159_[2] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[2];
assign _0159_[3] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[3];
assign _0159_[4] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[4];
assign _0159_[5] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[5];
assign _0159_[6] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[6];
assign _0159_[7] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[7];
assign _0159_[8] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[8];
assign _0159_[9] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[9];
assign _0159_[10] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[10];
assign _0159_[11] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[11];
assign _0159_[12] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[12];
assign _0159_[13] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[13];
assign _0159_[14] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[14];
assign _0159_[15] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0406_[15];
assign _0073_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0059_[0] : _0076_[0];
assign _0073_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0059_[1] : _0076_[2];
assign _0073_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0059_[2] : _0076_[2];
assign _0073_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0059_[3] : 1'b0;
assign _0073_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0059_[4] : 1'b0;
assign _0139_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[0] : _0147_[0];
assign _0139_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[1] : _0147_[1];
assign _0139_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[2] : _0147_[2];
assign _0139_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[3] : _0147_[3];
assign _0139_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[4] : _0147_[4];
assign _0139_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[5] : _0147_[5];
assign _0139_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[6] : _0147_[6];
assign _0139_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[7] : _0147_[7];
assign _0139_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[8] : _0147_[8];
assign _0139_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[9] : _0147_[9];
assign _0139_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[10] : _0147_[10];
assign _0139_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[11] : _0147_[11];
assign _0139_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[12] : _0147_[12];
assign _0139_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[13] : _0147_[13];
assign _0139_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[14] : _0147_[14];
assign _0139_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[15] : _0147_[15];
assign _0139_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[16] : _0147_[16];
assign _0139_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[17] : _0147_[17];
assign _0139_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[18] : _0147_[18];
assign _0139_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[19] : _0147_[19];
assign _0139_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[20] : _0147_[20];
assign _0139_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[21] : _0147_[21];
assign _0139_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[22] : _0147_[22];
assign _0139_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[23] : _0147_[23];
assign _0139_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[24] : _0147_[24];
assign _0139_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[25] : _0147_[25];
assign _0139_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[26] : _0147_[26];
assign _0139_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[27] : _0147_[27];
assign _0139_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[28] : _0147_[28];
assign _0139_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[29] : _0147_[29];
assign _0139_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[30] : _0147_[30];
assign _0139_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[31] : _0147_[31];
assign _0139_[32] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[32] : _0147_[32];
assign _0139_[33] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[33] : _0147_[33];
assign _0139_[34] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[34] : _0147_[34];
assign _0139_[35] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[35] : _0147_[35];
assign _0139_[36] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[36] : _0147_[36];
assign _0139_[37] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[37] : _0147_[37];
assign _0139_[38] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[38] : _0147_[38];
assign _0139_[39] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[39] : _0147_[39];
assign _0139_[40] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[40] : _0147_[40];
assign _0139_[41] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[41] : _0147_[41];
assign _0139_[42] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[42] : _0147_[42];
assign _0139_[43] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[43] : _0147_[43];
assign _0139_[44] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[44] : _0147_[44];
assign _0139_[45] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[45] : _0147_[45];
assign _0139_[46] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[46] : _0147_[46];
assign _0139_[47] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[47] : _0147_[47];
assign _0139_[48] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[48] : _0147_[48];
assign _0139_[49] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[49] : _0147_[49];
assign _0139_[50] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[50] : _0147_[50];
assign _0139_[51] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[51] : _0147_[51];
assign _0139_[52] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[52] : _0147_[52];
assign _0139_[53] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[53] : _0147_[53];
assign _0139_[54] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[54] : _0147_[54];
assign _0139_[55] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[55] : _0147_[55];
assign _0139_[56] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[56] : _0147_[56];
assign _0139_[57] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[57] : _0147_[57];
assign _0139_[58] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[58] : _0147_[58];
assign _0139_[59] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[59] : _0147_[59];
assign _0139_[60] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[60] : _0147_[60];
assign _0139_[61] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[61] : _0147_[61];
assign _0139_[62] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[62] : _0147_[62];
assign _0139_[63] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0108_[63] : _0147_[63];
assign _0163_ = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0132_ : _0176_;
assign _0149_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[0] : _0158_[0];
assign _0149_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[1] : _0158_[1];
assign _0149_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[2] : _0158_[2];
assign _0149_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[3] : _0158_[3];
assign _0149_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[4] : _0158_[4];
assign _0149_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[5] : _0158_[5];
assign _0149_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[6] : _0158_[6];
assign _0149_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[7] : _0158_[7];
assign _0149_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[8] : _0158_[8];
assign _0149_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[9] : _0158_[9];
assign _0149_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[10] : _0158_[10];
assign _0149_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[11] : _0158_[11];
assign _0149_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[12] : _0158_[12];
assign _0149_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[13] : _0158_[13];
assign _0149_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[14] : _0158_[14];
assign _0149_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[15] : _0158_[15];
assign _0149_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[16] : _0158_[16];
assign _0149_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[17] : _0158_[17];
assign _0149_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[18] : _0158_[18];
assign _0149_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[19] : _0158_[19];
assign _0149_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[20] : _0158_[20];
assign _0149_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[21] : _0158_[21];
assign _0149_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[22] : _0158_[22];
assign _0149_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[23] : _0158_[23];
assign _0149_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[24] : _0158_[24];
assign _0149_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[25] : _0158_[25];
assign _0149_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[26] : _0158_[26];
assign _0149_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[27] : _0158_[27];
assign _0149_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[28] : _0158_[28];
assign _0149_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[29] : _0158_[29];
assign _0149_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[30] : _0158_[30];
assign _0149_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0110_[31] : _0158_[31];
assign _0148_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[0] : _0157_[0];
assign _0148_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[1] : _0157_[1];
assign _0148_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[2] : _0157_[2];
assign _0148_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[3] : _0157_[3];
assign _0148_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[4] : _0157_[4];
assign _0148_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[5] : _0157_[5];
assign _0148_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[6] : _0157_[6];
assign _0148_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[7] : _0157_[7];
assign _0148_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[8] : _0157_[8];
assign _0148_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[9] : _0157_[9];
assign _0148_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[10] : _0157_[10];
assign _0148_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[11] : _0157_[11];
assign _0148_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[12] : _0157_[12];
assign _0148_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[13] : _0157_[13];
assign _0148_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[14] : _0157_[14];
assign _0148_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[15] : _0157_[15];
assign _0148_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[16] : _0157_[16];
assign _0148_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[17] : _0157_[17];
assign _0148_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[18] : _0157_[18];
assign _0148_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[19] : _0157_[19];
assign _0148_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[20] : _0157_[20];
assign _0148_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[21] : _0157_[21];
assign _0148_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[22] : _0157_[22];
assign _0148_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[23] : _0157_[23];
assign _0148_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[24] : _0157_[24];
assign _0148_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[25] : _0157_[25];
assign _0148_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[26] : _0157_[26];
assign _0148_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[27] : _0157_[27];
assign _0148_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[28] : _0157_[28];
assign _0148_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[29] : _0157_[29];
assign _0148_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[30] : _0157_[30];
assign _0148_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0109_[31] : _0157_[31];
assign _0150_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[0] : _0167_[0];
assign _0150_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[1] : _0167_[1];
assign _0150_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[2] : _0167_[2];
assign _0150_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[3] : _0167_[3];
assign _0150_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[4] : _0167_[4];
assign _0150_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[5] : _0167_[5];
assign _0150_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[6] : _0167_[6];
assign _0150_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[7] : _0167_[7];
assign _0150_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[8] : _0167_[8];
assign _0150_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[9] : _0167_[9];
assign _0150_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[10] : _0167_[10];
assign _0150_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[11] : _0167_[11];
assign _0150_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[12] : _0167_[12];
assign _0150_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[13] : _0167_[13];
assign _0150_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[14] : _0167_[14];
assign _0150_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) _0111_[15] : _0167_[15];
assign _0071_[0] = _0317_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0068_[0] : 1'b0;
assign _0071_[2] = _0317_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:248" *) _0068_[2] : 1'b1;
assign _0068_[2] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:243" *) _0068_[0];
assign _0141_[0] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[0] : parameter_Block[0];
assign _0141_[1] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[1] : parameter_Block[1];
assign _0141_[2] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[2] : parameter_Block[2];
assign _0141_[3] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[3] : parameter_Block[3];
assign _0141_[4] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[4] : parameter_Block[4];
assign _0141_[5] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[5] : parameter_Block[5];
assign _0141_[6] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[6] : parameter_Block[6];
assign _0141_[7] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[7] : parameter_Block[7];
assign _0141_[8] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[8] : parameter_Block[8];
assign _0141_[9] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[9] : parameter_Block[9];
assign _0141_[10] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[10] : parameter_Block[10];
assign _0141_[11] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[11] : parameter_Block[11];
assign _0141_[12] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[12] : parameter_Block[12];
assign _0141_[13] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[13] : parameter_Block[13];
assign _0141_[14] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[14] : parameter_Block[14];
assign _0141_[15] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[15] : parameter_Block[15];
assign _0141_[16] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[16] : parameter_Block[16];
assign _0141_[17] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[17] : parameter_Block[17];
assign _0141_[18] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[18] : parameter_Block[18];
assign _0141_[19] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[19] : parameter_Block[19];
assign _0141_[20] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[20] : parameter_Block[20];
assign _0141_[21] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[21] : parameter_Block[21];
assign _0141_[22] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[22] : parameter_Block[22];
assign _0141_[23] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[23] : parameter_Block[23];
assign _0141_[24] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[24] : parameter_Block[24];
assign _0141_[25] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[25] : parameter_Block[25];
assign _0141_[26] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[26] : parameter_Block[26];
assign _0141_[27] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[27] : parameter_Block[27];
assign _0141_[28] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[28] : parameter_Block[28];
assign _0141_[29] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[29] : parameter_Block[29];
assign _0141_[30] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[30] : parameter_Block[30];
assign _0141_[31] = _0370_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:238" *) addresstemp2[31] : parameter_Block[31];
assign _0140_[0] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[0] : parameter_Block[0];
assign _0140_[1] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[1] : parameter_Block[1];
assign _0140_[2] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[2] : parameter_Block[2];
assign _0140_[3] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[3] : parameter_Block[3];
assign _0140_[4] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[4] : parameter_Block[4];
assign _0140_[5] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[5] : parameter_Block[5];
assign _0140_[6] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[6] : parameter_Block[6];
assign _0140_[7] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[7] : parameter_Block[7];
assign _0140_[8] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[8] : parameter_Block[8];
assign _0140_[9] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[9] : parameter_Block[9];
assign _0140_[10] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[10] : parameter_Block[10];
assign _0140_[11] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[11] : parameter_Block[11];
assign _0140_[12] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[12] : parameter_Block[12];
assign _0140_[13] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[13] : parameter_Block[13];
assign _0140_[14] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[14] : parameter_Block[14];
assign _0140_[15] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[15] : parameter_Block[15];
assign _0140_[16] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[16] : parameter_Block[16];
assign _0140_[17] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[17] : parameter_Block[17];
assign _0140_[18] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[18] : parameter_Block[18];
assign _0140_[19] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[19] : parameter_Block[19];
assign _0140_[20] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[20] : parameter_Block[20];
assign _0140_[21] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[21] : parameter_Block[21];
assign _0140_[22] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[22] : parameter_Block[22];
assign _0140_[23] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[23] : parameter_Block[23];
assign _0140_[24] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[24] : parameter_Block[24];
assign _0140_[25] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[25] : parameter_Block[25];
assign _0140_[26] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[26] : parameter_Block[26];
assign _0140_[27] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[27] : parameter_Block[27];
assign _0140_[28] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[28] : parameter_Block[28];
assign _0140_[29] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[29] : parameter_Block[29];
assign _0140_[30] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[30] : parameter_Block[30];
assign _0140_[31] = _0369_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:233" *) addresstemp1[31] : parameter_Block[31];
assign _0142_[0] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0336_[0] : _0127_[0];
assign _0142_[1] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[1] : _0127_[1];
assign _0142_[2] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[2] : _0127_[2];
assign _0142_[3] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[3] : _0127_[3];
assign _0142_[4] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[4] : _0127_[4];
assign _0142_[5] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[5] : _0127_[5];
assign _0142_[6] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[6] : _0127_[6];
assign _0142_[7] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[7] : _0127_[7];
assign _0142_[8] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[8] : _0127_[8];
assign _0142_[9] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[9] : _0127_[9];
assign _0142_[10] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[10] : _0127_[10];
assign _0142_[11] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[11] : _0127_[11];
assign _0142_[12] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[12] : _0127_[12];
assign _0142_[13] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[13] : _0127_[13];
assign _0142_[14] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[14] : _0127_[14];
assign _0142_[15] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0430_[15] : _0127_[15];
assign _0062_[0] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0071_[0] : 1'b1;
assign _0062_[2] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0071_[2] : 1'b0;
assign _0126_[0] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[0] : addresstemp2[0];
assign _0126_[1] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[1] : addresstemp2[1];
assign _0126_[2] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[2] : addresstemp2[2];
assign _0126_[3] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[3] : addresstemp2[3];
assign _0126_[4] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[4] : addresstemp2[4];
assign _0126_[5] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[5] : addresstemp2[5];
assign _0126_[6] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[6] : addresstemp2[6];
assign _0126_[7] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[7] : addresstemp2[7];
assign _0126_[8] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[8] : addresstemp2[8];
assign _0126_[9] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[9] : addresstemp2[9];
assign _0126_[10] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[10] : addresstemp2[10];
assign _0126_[11] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[11] : addresstemp2[11];
assign _0126_[12] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[12] : addresstemp2[12];
assign _0126_[13] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[13] : addresstemp2[13];
assign _0126_[14] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[14] : addresstemp2[14];
assign _0126_[15] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[15] : addresstemp2[15];
assign _0126_[16] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[16] : addresstemp2[16];
assign _0126_[17] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[17] : addresstemp2[17];
assign _0126_[18] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[18] : addresstemp2[18];
assign _0126_[19] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[19] : addresstemp2[19];
assign _0126_[20] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[20] : addresstemp2[20];
assign _0126_[21] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[21] : addresstemp2[21];
assign _0126_[22] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[22] : addresstemp2[22];
assign _0126_[23] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[23] : addresstemp2[23];
assign _0126_[24] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[24] : addresstemp2[24];
assign _0126_[25] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[25] : addresstemp2[25];
assign _0126_[26] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[26] : addresstemp2[26];
assign _0126_[27] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[27] : addresstemp2[27];
assign _0126_[28] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[28] : addresstemp2[28];
assign _0126_[29] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[29] : addresstemp2[29];
assign _0126_[30] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[30] : addresstemp2[30];
assign _0126_[31] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0141_[31] : addresstemp2[31];
assign _0125_[0] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[0] : addresstemp1[0];
assign _0125_[1] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[1] : addresstemp1[1];
assign _0125_[2] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[2] : addresstemp1[2];
assign _0125_[3] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[3] : addresstemp1[3];
assign _0125_[4] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[4] : addresstemp1[4];
assign _0125_[5] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[5] : addresstemp1[5];
assign _0125_[6] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[6] : addresstemp1[6];
assign _0125_[7] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[7] : addresstemp1[7];
assign _0125_[8] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[8] : addresstemp1[8];
assign _0125_[9] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[9] : addresstemp1[9];
assign _0125_[10] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[10] : addresstemp1[10];
assign _0125_[11] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[11] : addresstemp1[11];
assign _0125_[12] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[12] : addresstemp1[12];
assign _0125_[13] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[13] : addresstemp1[13];
assign _0125_[14] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[14] : addresstemp1[14];
assign _0125_[15] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[15] : addresstemp1[15];
assign _0125_[16] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[16] : addresstemp1[16];
assign _0125_[17] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[17] : addresstemp1[17];
assign _0125_[18] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[18] : addresstemp1[18];
assign _0125_[19] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[19] : addresstemp1[19];
assign _0125_[20] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[20] : addresstemp1[20];
assign _0125_[21] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[21] : addresstemp1[21];
assign _0125_[22] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[22] : addresstemp1[22];
assign _0125_[23] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[23] : addresstemp1[23];
assign _0125_[24] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[24] : addresstemp1[24];
assign _0125_[25] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[25] : addresstemp1[25];
assign _0125_[26] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[26] : addresstemp1[26];
assign _0125_[27] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[27] : addresstemp1[27];
assign _0125_[28] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[28] : addresstemp1[28];
assign _0125_[29] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[29] : addresstemp1[29];
assign _0125_[30] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[30] : addresstemp1[30];
assign _0125_[31] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) _0140_[31] : addresstemp1[31];
assign _0124_[0] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[0] : addresstemp2[0];
assign _0124_[1] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[1] : addresstemp2[1];
assign _0124_[2] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[2] : addresstemp2[2];
assign _0124_[3] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[3] : addresstemp2[3];
assign _0124_[4] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[4] : addresstemp2[4];
assign _0124_[5] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[5] : addresstemp2[5];
assign _0124_[6] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[6] : addresstemp2[6];
assign _0124_[7] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[7] : addresstemp2[7];
assign _0124_[8] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[8] : addresstemp2[8];
assign _0124_[9] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[9] : addresstemp2[9];
assign _0124_[10] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[10] : addresstemp2[10];
assign _0124_[11] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[11] : addresstemp2[11];
assign _0124_[12] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[12] : addresstemp2[12];
assign _0124_[13] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[13] : addresstemp2[13];
assign _0124_[14] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[14] : addresstemp2[14];
assign _0124_[15] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[15] : addresstemp2[15];
assign _0124_[16] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[16] : addresstemp2[16];
assign _0124_[17] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[17] : addresstemp2[17];
assign _0124_[18] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[18] : addresstemp2[18];
assign _0124_[19] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[19] : addresstemp2[19];
assign _0124_[20] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[20] : addresstemp2[20];
assign _0124_[21] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[21] : addresstemp2[21];
assign _0124_[22] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[22] : addresstemp2[22];
assign _0124_[23] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[23] : addresstemp2[23];
assign _0124_[24] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[24] : addresstemp2[24];
assign _0124_[25] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[25] : addresstemp2[25];
assign _0124_[26] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[26] : addresstemp2[26];
assign _0124_[27] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[27] : addresstemp2[27];
assign _0124_[28] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[28] : addresstemp2[28];
assign _0124_[29] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[29] : addresstemp2[29];
assign _0124_[30] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[30] : addresstemp2[30];
assign _0124_[31] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[31] : addresstemp2[31];
assign _0124_[32] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[32] : addresstemp1[0];
assign _0124_[33] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[33] : addresstemp1[1];
assign _0124_[34] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[34] : addresstemp1[2];
assign _0124_[35] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[35] : addresstemp1[3];
assign _0124_[36] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[36] : addresstemp1[4];
assign _0124_[37] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[37] : addresstemp1[5];
assign _0124_[38] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[38] : addresstemp1[6];
assign _0124_[39] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[39] : addresstemp1[7];
assign _0124_[40] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[40] : addresstemp1[8];
assign _0124_[41] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[41] : addresstemp1[9];
assign _0124_[42] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[42] : addresstemp1[10];
assign _0124_[43] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[43] : addresstemp1[11];
assign _0124_[44] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[44] : addresstemp1[12];
assign _0124_[45] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[45] : addresstemp1[13];
assign _0124_[46] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[46] : addresstemp1[14];
assign _0124_[47] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[47] : addresstemp1[15];
assign _0124_[48] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[48] : addresstemp1[16];
assign _0124_[49] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[49] : addresstemp1[17];
assign _0124_[50] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[50] : addresstemp1[18];
assign _0124_[51] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[51] : addresstemp1[19];
assign _0124_[52] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[52] : addresstemp1[20];
assign _0124_[53] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[53] : addresstemp1[21];
assign _0124_[54] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[54] : addresstemp1[22];
assign _0124_[55] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[55] : addresstemp1[23];
assign _0124_[56] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[56] : addresstemp1[24];
assign _0124_[57] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[57] : addresstemp1[25];
assign _0124_[58] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[58] : addresstemp1[26];
assign _0124_[59] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[59] : addresstemp1[27];
assign _0124_[60] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[60] : addresstemp1[28];
assign _0124_[61] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[61] : addresstemp1[29];
assign _0124_[62] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[62] : addresstemp1[30];
assign _0124_[63] = _0155_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:231" *) address[63] : addresstemp1[31];
assign _0407_[0] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[0] : 1'b1;
assign _0407_[1] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[1] : 1'b1;
assign _0407_[2] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[2] : 1'b1;
assign _0407_[3] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[3] : 1'b0;
assign _0407_[4] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[4] : 1'b0;
assign _0407_[5] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[5] : 1'b0;
assign _0407_[6] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[6] : 1'b0;
assign _0407_[7] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[7] : 1'b0;
assign _0407_[8] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[8] : 1'b0;
assign _0407_[9] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[9] : 1'b0;
assign _0407_[10] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[10] : 1'b0;
assign _0407_[11] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[11] : 1'b0;
assign _0407_[12] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[12] : 1'b0;
assign _0407_[13] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[13] : 1'b0;
assign _0407_[14] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[14] : 1'b0;
assign _0407_[15] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:226" *) count[15] : 1'b0;
assign _0408_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[0];
assign _0408_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[1];
assign _0408_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[2];
assign _0408_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[3];
assign _0408_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[4];
assign _0408_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[5];
assign _0408_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[6];
assign _0408_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[7];
assign _0408_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[8];
assign _0408_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[9];
assign _0408_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[10];
assign _0408_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[11];
assign _0408_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[12];
assign _0408_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[13];
assign _0408_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[14];
assign _0408_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) 1'bx : _0407_[15];
assign _0409_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[0];
assign _0409_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[1];
assign _0409_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[2];
assign _0409_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[3];
assign _0409_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[4];
assign _0409_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[5];
assign _0409_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[6];
assign _0409_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[7];
assign _0409_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[8];
assign _0409_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[9];
assign _0409_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[10];
assign _0409_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[11];
assign _0409_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[12];
assign _0409_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[13];
assign _0409_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[14];
assign _0409_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0408_[15];
assign _0127_[0] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[0];
assign _0127_[1] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[1];
assign _0127_[2] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[2];
assign _0127_[3] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[3];
assign _0127_[4] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[4];
assign _0127_[5] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[5];
assign _0127_[6] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[6];
assign _0127_[7] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[7];
assign _0127_[8] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[8];
assign _0127_[9] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[9];
assign _0127_[10] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[10];
assign _0127_[11] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[11];
assign _0127_[12] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[12];
assign _0127_[13] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[13];
assign _0127_[14] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[14];
assign _0127_[15] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0409_[15];
assign _0059_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) next_state[0] : _0062_[0];
assign _0059_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) next_state[1] : _0062_[2];
assign _0059_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) next_state[2] : _0062_[2];
assign _0059_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) next_state[3] : 1'b0;
assign _0059_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) next_state[4] : 1'b0;
assign _0108_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[0] : _0124_[0];
assign _0108_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[1] : _0124_[1];
assign _0108_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[2] : _0124_[2];
assign _0108_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[3] : _0124_[3];
assign _0108_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[4] : _0124_[4];
assign _0108_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[5] : _0124_[5];
assign _0108_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[6] : _0124_[6];
assign _0108_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[7] : _0124_[7];
assign _0108_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[8] : _0124_[8];
assign _0108_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[9] : _0124_[9];
assign _0108_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[10] : _0124_[10];
assign _0108_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[11] : _0124_[11];
assign _0108_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[12] : _0124_[12];
assign _0108_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[13] : _0124_[13];
assign _0108_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[14] : _0124_[14];
assign _0108_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[15] : _0124_[15];
assign _0108_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[16] : _0124_[16];
assign _0108_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[17] : _0124_[17];
assign _0108_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[18] : _0124_[18];
assign _0108_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[19] : _0124_[19];
assign _0108_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[20] : _0124_[20];
assign _0108_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[21] : _0124_[21];
assign _0108_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[22] : _0124_[22];
assign _0108_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[23] : _0124_[23];
assign _0108_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[24] : _0124_[24];
assign _0108_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[25] : _0124_[25];
assign _0108_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[26] : _0124_[26];
assign _0108_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[27] : _0124_[27];
assign _0108_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[28] : _0124_[28];
assign _0108_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[29] : _0124_[29];
assign _0108_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[30] : _0124_[30];
assign _0108_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[31] : _0124_[31];
assign _0108_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[32] : _0124_[32];
assign _0108_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[33] : _0124_[33];
assign _0108_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[34] : _0124_[34];
assign _0108_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[35] : _0124_[35];
assign _0108_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[36] : _0124_[36];
assign _0108_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[37] : _0124_[37];
assign _0108_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[38] : _0124_[38];
assign _0108_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[39] : _0124_[39];
assign _0108_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[40] : _0124_[40];
assign _0108_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[41] : _0124_[41];
assign _0108_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[42] : _0124_[42];
assign _0108_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[43] : _0124_[43];
assign _0108_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[44] : _0124_[44];
assign _0108_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[45] : _0124_[45];
assign _0108_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[46] : _0124_[46];
assign _0108_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[47] : _0124_[47];
assign _0108_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[48] : _0124_[48];
assign _0108_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[49] : _0124_[49];
assign _0108_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[50] : _0124_[50];
assign _0108_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[51] : _0124_[51];
assign _0108_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[52] : _0124_[52];
assign _0108_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[53] : _0124_[53];
assign _0108_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[54] : _0124_[54];
assign _0108_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[55] : _0124_[55];
assign _0108_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[56] : _0124_[56];
assign _0108_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[57] : _0124_[57];
assign _0108_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[58] : _0124_[58];
assign _0108_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[59] : _0124_[59];
assign _0108_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[60] : _0124_[60];
assign _0108_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[61] : _0124_[61];
assign _0108_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[62] : _0124_[62];
assign _0108_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) address[63] : _0124_[63];
assign _0410_ = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) singl_data : _0155_;
assign _0411_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) 1'bx : _0410_;
assign _0132_ = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0411_;
assign _0110_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[0] : _0126_[0];
assign _0110_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[1] : _0126_[1];
assign _0110_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[2] : _0126_[2];
assign _0110_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[3] : _0126_[3];
assign _0110_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[4] : _0126_[4];
assign _0110_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[5] : _0126_[5];
assign _0110_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[6] : _0126_[6];
assign _0110_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[7] : _0126_[7];
assign _0110_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[8] : _0126_[8];
assign _0110_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[9] : _0126_[9];
assign _0110_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[10] : _0126_[10];
assign _0110_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[11] : _0126_[11];
assign _0110_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[12] : _0126_[12];
assign _0110_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[13] : _0126_[13];
assign _0110_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[14] : _0126_[14];
assign _0110_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[15] : _0126_[15];
assign _0110_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[16] : _0126_[16];
assign _0110_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[17] : _0126_[17];
assign _0110_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[18] : _0126_[18];
assign _0110_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[19] : _0126_[19];
assign _0110_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[20] : _0126_[20];
assign _0110_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[21] : _0126_[21];
assign _0110_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[22] : _0126_[22];
assign _0110_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[23] : _0126_[23];
assign _0110_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[24] : _0126_[24];
assign _0110_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[25] : _0126_[25];
assign _0110_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[26] : _0126_[26];
assign _0110_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[27] : _0126_[27];
assign _0110_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[28] : _0126_[28];
assign _0110_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[29] : _0126_[29];
assign _0110_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[30] : _0126_[30];
assign _0110_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp2[31] : _0126_[31];
assign _0109_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[0] : _0125_[0];
assign _0109_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[1] : _0125_[1];
assign _0109_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[2] : _0125_[2];
assign _0109_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[3] : _0125_[3];
assign _0109_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[4] : _0125_[4];
assign _0109_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[5] : _0125_[5];
assign _0109_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[6] : _0125_[6];
assign _0109_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[7] : _0125_[7];
assign _0109_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[8] : _0125_[8];
assign _0109_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[9] : _0125_[9];
assign _0109_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[10] : _0125_[10];
assign _0109_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[11] : _0125_[11];
assign _0109_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[12] : _0125_[12];
assign _0109_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[13] : _0125_[13];
assign _0109_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[14] : _0125_[14];
assign _0109_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[15] : _0125_[15];
assign _0109_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[16] : _0125_[16];
assign _0109_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[17] : _0125_[17];
assign _0109_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[18] : _0125_[18];
assign _0109_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[19] : _0125_[19];
assign _0109_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[20] : _0125_[20];
assign _0109_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[21] : _0125_[21];
assign _0109_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[22] : _0125_[22];
assign _0109_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[23] : _0125_[23];
assign _0109_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[24] : _0125_[24];
assign _0109_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[25] : _0125_[25];
assign _0109_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[26] : _0125_[26];
assign _0109_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[27] : _0125_[27];
assign _0109_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[28] : _0125_[28];
assign _0109_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[29] : _0125_[29];
assign _0109_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[30] : _0125_[30];
assign _0109_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) addresstemp1[31] : _0125_[31];
assign _0111_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[0] : _0142_[0];
assign _0111_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[1] : _0142_[1];
assign _0111_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[2] : _0142_[2];
assign _0111_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[3] : _0142_[3];
assign _0111_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[4] : _0142_[4];
assign _0111_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[5] : _0142_[5];
assign _0111_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[6] : _0142_[6];
assign _0111_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[7] : _0142_[7];
assign _0111_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[8] : _0142_[8];
assign _0111_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[9] : _0142_[9];
assign _0111_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[10] : _0142_[10];
assign _0111_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[11] : _0142_[11];
assign _0111_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[12] : _0142_[12];
assign _0111_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[13] : _0142_[13];
assign _0111_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[14] : _0142_[14];
assign _0111_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:223" *) count[15] : _0142_[15];
assign _0056_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) next_state[0] : _0073_[0];
assign _0056_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) next_state[1] : _0073_[1];
assign _0056_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) next_state[2] : _0073_[2];
assign _0056_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) next_state[3] : _0073_[3];
assign _0056_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) next_state[4] : _0073_[4];
assign _0079_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[0] : _0139_[0];
assign _0079_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[1] : _0139_[1];
assign _0079_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[2] : _0139_[2];
assign _0079_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[3] : _0139_[3];
assign _0079_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[4] : _0139_[4];
assign _0079_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[5] : _0139_[5];
assign _0079_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[6] : _0139_[6];
assign _0079_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[7] : _0139_[7];
assign _0079_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[8] : _0139_[8];
assign _0079_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[9] : _0139_[9];
assign _0079_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[10] : _0139_[10];
assign _0079_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[11] : _0139_[11];
assign _0079_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[12] : _0139_[12];
assign _0079_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[13] : _0139_[13];
assign _0079_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[14] : _0139_[14];
assign _0079_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[15] : _0139_[15];
assign _0079_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[16] : _0139_[16];
assign _0079_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[17] : _0139_[17];
assign _0079_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[18] : _0139_[18];
assign _0079_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[19] : _0139_[19];
assign _0079_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[20] : _0139_[20];
assign _0079_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[21] : _0139_[21];
assign _0079_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[22] : _0139_[22];
assign _0079_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[23] : _0139_[23];
assign _0079_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[24] : _0139_[24];
assign _0079_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[25] : _0139_[25];
assign _0079_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[26] : _0139_[26];
assign _0079_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[27] : _0139_[27];
assign _0079_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[28] : _0139_[28];
assign _0079_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[29] : _0139_[29];
assign _0079_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[30] : _0139_[30];
assign _0079_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[31] : _0139_[31];
assign _0079_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[32] : _0139_[32];
assign _0079_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[33] : _0139_[33];
assign _0079_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[34] : _0139_[34];
assign _0079_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[35] : _0139_[35];
assign _0079_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[36] : _0139_[36];
assign _0079_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[37] : _0139_[37];
assign _0079_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[38] : _0139_[38];
assign _0079_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[39] : _0139_[39];
assign _0079_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[40] : _0139_[40];
assign _0079_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[41] : _0139_[41];
assign _0079_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[42] : _0139_[42];
assign _0079_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[43] : _0139_[43];
assign _0079_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[44] : _0139_[44];
assign _0079_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[45] : _0139_[45];
assign _0079_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[46] : _0139_[46];
assign _0079_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[47] : _0139_[47];
assign _0079_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[48] : _0139_[48];
assign _0079_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[49] : _0139_[49];
assign _0079_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[50] : _0139_[50];
assign _0079_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[51] : _0139_[51];
assign _0079_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[52] : _0139_[52];
assign _0079_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[53] : _0139_[53];
assign _0079_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[54] : _0139_[54];
assign _0079_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[55] : _0139_[55];
assign _0079_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[56] : _0139_[56];
assign _0079_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[57] : _0139_[57];
assign _0079_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[58] : _0139_[58];
assign _0079_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[59] : _0139_[59];
assign _0079_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[60] : _0139_[60];
assign _0079_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[61] : _0139_[61];
assign _0079_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[62] : _0139_[62];
assign _0079_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) address[63] : _0139_[63];
assign _0412_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) singl_data : _0163_;
assign _0115_ = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0412_;
assign _0081_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[0] : _0149_[0];
assign _0081_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[1] : _0149_[1];
assign _0081_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[2] : _0149_[2];
assign _0081_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[3] : _0149_[3];
assign _0081_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[4] : _0149_[4];
assign _0081_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[5] : _0149_[5];
assign _0081_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[6] : _0149_[6];
assign _0081_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[7] : _0149_[7];
assign _0081_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[8] : _0149_[8];
assign _0081_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[9] : _0149_[9];
assign _0081_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[10] : _0149_[10];
assign _0081_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[11] : _0149_[11];
assign _0081_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[12] : _0149_[12];
assign _0081_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[13] : _0149_[13];
assign _0081_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[14] : _0149_[14];
assign _0081_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[15] : _0149_[15];
assign _0081_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[16] : _0149_[16];
assign _0081_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[17] : _0149_[17];
assign _0081_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[18] : _0149_[18];
assign _0081_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[19] : _0149_[19];
assign _0081_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[20] : _0149_[20];
assign _0081_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[21] : _0149_[21];
assign _0081_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[22] : _0149_[22];
assign _0081_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[23] : _0149_[23];
assign _0081_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[24] : _0149_[24];
assign _0081_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[25] : _0149_[25];
assign _0081_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[26] : _0149_[26];
assign _0081_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[27] : _0149_[27];
assign _0081_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[28] : _0149_[28];
assign _0081_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[29] : _0149_[29];
assign _0081_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[30] : _0149_[30];
assign _0081_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp2[31] : _0149_[31];
assign _0080_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[0] : _0148_[0];
assign _0080_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[1] : _0148_[1];
assign _0080_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[2] : _0148_[2];
assign _0080_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[3] : _0148_[3];
assign _0080_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[4] : _0148_[4];
assign _0080_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[5] : _0148_[5];
assign _0080_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[6] : _0148_[6];
assign _0080_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[7] : _0148_[7];
assign _0080_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[8] : _0148_[8];
assign _0080_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[9] : _0148_[9];
assign _0080_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[10] : _0148_[10];
assign _0080_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[11] : _0148_[11];
assign _0080_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[12] : _0148_[12];
assign _0080_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[13] : _0148_[13];
assign _0080_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[14] : _0148_[14];
assign _0080_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[15] : _0148_[15];
assign _0080_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[16] : _0148_[16];
assign _0080_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[17] : _0148_[17];
assign _0080_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[18] : _0148_[18];
assign _0080_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[19] : _0148_[19];
assign _0080_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[20] : _0148_[20];
assign _0080_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[21] : _0148_[21];
assign _0080_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[22] : _0148_[22];
assign _0080_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[23] : _0148_[23];
assign _0080_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[24] : _0148_[24];
assign _0080_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[25] : _0148_[25];
assign _0080_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[26] : _0148_[26];
assign _0080_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[27] : _0148_[27];
assign _0080_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[28] : _0148_[28];
assign _0080_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[29] : _0148_[29];
assign _0080_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[30] : _0148_[30];
assign _0080_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) addresstemp1[31] : _0148_[31];
assign _0084_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[0] : _0150_[0];
assign _0084_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[1] : _0150_[1];
assign _0084_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[2] : _0150_[2];
assign _0084_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[3] : _0150_[3];
assign _0084_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[4] : _0150_[4];
assign _0084_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[5] : _0150_[5];
assign _0084_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[6] : _0150_[6];
assign _0084_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[7] : _0150_[7];
assign _0084_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[8] : _0150_[8];
assign _0084_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[9] : _0150_[9];
assign _0084_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[10] : _0150_[10];
assign _0084_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[11] : _0150_[11];
assign _0084_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[12] : _0150_[12];
assign _0084_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[13] : _0150_[13];
assign _0084_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[14] : _0150_[14];
assign _0084_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:221" *) count[15] : _0150_[15];
assign _0053_[0] = _0368_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0051_[0] : 1'b0;
assign _0053_[1] = _0368_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0051_[1] : 1'b1;
assign _0053_[2] = _0368_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0051_[2] : 1'b0;
assign _0053_[3] = _0368_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0051_[3] : 1'b0;
assign _0053_[4] = _0368_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) _0051_[4] : 1'b1;
assign _0051_[0] = _0367_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0048_[0] : 1'b1;
assign _0051_[1] = _0367_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0048_[1] : 1'b0;
assign _0051_[2] = _0367_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0048_[2] : 1'b0;
assign _0051_[3] = _0367_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0048_[3] : 1'b0;
assign _0051_[4] = _0367_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:183" *) _0048_[4] : 1'b1;
assign _0048_[0] = _0366_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0046_[0] : 1'b0;
assign _0048_[1] = _0366_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0046_[1] : 1'b0;
assign _0048_[2] = _0366_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0046_[2] : 1'b0;
assign _0048_[3] = _0366_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0046_[3] : 1'b0;
assign _0048_[4] = _0366_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:179" *) _0046_[4] : 1'b1;
assign _0046_[0] = _0365_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0043_[0] : 1'b1;
assign _0046_[1] = _0365_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0043_[1] : 1'b1;
assign _0046_[2] = _0365_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0043_[2] : 1'b1;
assign _0046_[3] = _0365_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0043_[3] : 1'b1;
assign _0046_[4] = _0365_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:175" *) _0043_[4] : 1'b0;
assign _0043_[0] = _0364_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0040_[0] : 1'b0;
assign _0043_[1] = _0364_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0040_[1] : 1'b1;
assign _0043_[2] = _0364_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0040_[2] : 1'b1;
assign _0043_[3] = _0364_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0040_[3] : 1'b1;
assign _0043_[4] = _0364_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:171" *) _0040_[4] : 1'b0;
assign _0040_[0] = _0363_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0036_[0] : 1'b1;
assign _0040_[1] = _0363_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0036_[1] : 1'b0;
assign _0040_[2] = _0363_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0036_[2] : 1'b1;
assign _0040_[3] = _0363_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0036_[3] : 1'b1;
assign _0040_[4] = _0363_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:167" *) _0036_[4] : 1'b0;
assign _0036_[0] = _0362_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) next_state[0] : 1'b0;
assign _0036_[1] = _0362_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) next_state[1] : 1'b0;
assign _0036_[2] = _0362_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) next_state[2] : 1'b1;
assign _0036_[3] = _0362_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) next_state[3] : 1'b1;
assign _0036_[4] = _0362_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:163" *) next_state[4] : 1'b0;
assign _0033_[0] = _0361_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0027_[0] : 1'b1;
assign _0033_[1] = _0361_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0027_[1] : 1'b1;
assign _0033_[2] = _0361_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0027_[2] : 1'b0;
assign _0033_[3] = _0361_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0027_[3] : 1'b1;
assign _0033_[4] = _0361_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) _0027_[4] : 1'b0;
assign _0027_[0] = _0360_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0020_[0] : 1'b0;
assign _0027_[1] = _0360_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0020_[1] : 1'b1;
assign _0027_[2] = _0360_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0020_[2] : 1'b0;
assign _0027_[3] = _0360_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0020_[3] : 1'b1;
assign _0027_[4] = _0360_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:152" *) _0020_[4] : 1'b0;
assign _0020_[0] = _0359_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0175_[0] : 1'b1;
assign _0020_[1] = _0359_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0175_[1] : 1'b0;
assign _0020_[2] = _0359_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0175_[2] : 1'b0;
assign _0020_[3] = _0359_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0175_[3] : 1'b1;
assign _0020_[4] = _0359_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:147" *) _0175_[4] : 1'b0;
assign _0175_[0] = _0358_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0169_[0] : 1'b0;
assign _0175_[1] = _0358_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0169_[1] : 1'b0;
assign _0175_[2] = _0358_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0169_[2] : 1'b0;
assign _0175_[3] = _0358_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0169_[3] : 1'b1;
assign _0175_[4] = _0358_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:142" *) _0169_[4] : 1'b0;
assign _0169_[0] = _0357_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0162_[0] : 1'b1;
assign _0169_[1] = _0357_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0162_[1] : 1'b1;
assign _0169_[2] = _0357_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0162_[2] : 1'b1;
assign _0169_[3] = _0357_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0162_[3] : 1'b0;
assign _0169_[4] = _0357_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:138" *) _0162_[4] : 1'b0;
assign _0162_[0] = _0356_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0153_[0] : 1'b0;
assign _0162_[1] = _0356_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0153_[1] : 1'b0;
assign _0162_[2] = _0356_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0153_[2] : 1'b1;
assign _0162_[3] = _0356_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0153_[3] : 1'b0;
assign _0162_[4] = _0356_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:134" *) _0153_[4] : 1'b1;
assign _0153_[0] = _0355_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0145_[0] : 1'b0;
assign _0153_[1] = _0355_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0145_[1] : 1'b1;
assign _0153_[2] = _0355_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0145_[2] : 1'b1;
assign _0153_[3] = _0355_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0145_[3] : 1'b0;
assign _0153_[4] = _0355_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:129" *) _0145_[4] : 1'b0;
assign _0145_[0] = _0354_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) next_state[0] : 1'b1;
assign _0145_[1] = _0354_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) next_state[1] : 1'b1;
assign _0145_[2] = _0354_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) next_state[2] : 1'b0;
assign _0145_[3] = _0354_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) next_state[3] : 1'b0;
assign _0145_[4] = _0354_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:122" *) next_state[4] : 1'b1;
assign _0130_[0] = _0353_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:115" *) next_state[0] : 1'b0;
assign _0130_[1] = _0353_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:115" *) next_state[1] : 1'b0;
assign _0130_[2] = _0353_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:115" *) next_state[2] : 1'b1;
assign _0130_[3] = _0353_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:115" *) next_state[3] : 1'b0;
assign _0130_[4] = _0353_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:115" *) next_state[4] : 1'b0;
assign _0087_[0] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) start;
assign _0089_ = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) 1'b0 : singl_data;
assign _0091_[0] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[0] : wLength[0];
assign _0091_[1] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[1] : wLength[1];
assign _0091_[2] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[2] : wLength[2];
assign _0091_[3] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[3] : wLength[3];
assign _0091_[4] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[4] : wLength[4];
assign _0091_[5] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[5] : wLength[5];
assign _0091_[6] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[6] : wLength[6];
assign _0091_[7] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[7] : wLength[7];
assign _0091_[8] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[8] : wLength[8];
assign _0091_[9] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[9] : wLength[9];
assign _0091_[10] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[10] : wLength[10];
assign _0091_[11] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[11] : wLength[11];
assign _0091_[12] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[12] : wLength[12];
assign _0091_[13] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[13] : wLength[13];
assign _0091_[14] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[14] : wLength[14];
assign _0091_[15] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[15] : wLength[15];
assign _0090_[8] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[24] : wIndex[8];
assign _0090_[9] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[25] : wIndex[9];
assign _0090_[10] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[26] : wIndex[10];
assign _0090_[11] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[27] : wIndex[11];
assign _0090_[12] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[28] : wIndex[12];
assign _0090_[13] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[29] : wIndex[13];
assign _0090_[14] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[30] : wIndex[14];
assign _0090_[15] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[31] : wIndex[15];
assign _0092_[0] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[33] : wValue[0];
assign _0092_[1] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[34] : wValue[1];
assign _0092_[2] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[35] : wValue[2];
assign _0092_[3] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[36] : wValue[3];
assign _0092_[4] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[37] : wValue[4];
assign _0092_[5] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[38] : wValue[5];
assign _0092_[6] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[39] : wValue[6];
assign _0092_[7] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[40] : wValue[7];
assign _0082_[0] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[47] : bRequest[0];
assign _0082_[1] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[48] : bRequest[1];
assign _0082_[2] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[49] : bRequest[2];
assign _0082_[3] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[50] : bRequest[3];
assign _0082_[4] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[51] : bRequest[4];
assign _0082_[5] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[52] : bRequest[5];
assign _0082_[6] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[53] : bRequest[6];
assign _0082_[7] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[54] : bRequest[7];
assign _0083_[0] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[55] : bmRequestType[0];
assign _0083_[1] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[56] : bmRequestType[1];
assign _0083_[2] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[57] : bmRequestType[2];
assign _0083_[3] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[58] : bmRequestType[3];
assign _0083_[4] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[59] : bmRequestType[4];
assign _0083_[5] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[60] : bmRequestType[5];
assign _0083_[6] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[61] : bmRequestType[6];
assign _0083_[7] = start ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:97" *) data[62] : bmRequestType[7];
assign _0013_[0] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[0] : _0091_[0];
assign _0013_[1] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[1] : _0091_[1];
assign _0013_[2] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[2] : _0091_[2];
assign _0013_[3] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[3] : _0091_[3];
assign _0013_[4] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[4] : _0091_[4];
assign _0013_[5] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[5] : _0091_[5];
assign _0013_[6] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[6] : _0091_[6];
assign _0013_[7] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[7] : _0091_[7];
assign _0013_[8] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[8] : _0091_[8];
assign _0013_[9] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[9] : _0091_[9];
assign _0013_[10] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[10] : _0091_[10];
assign _0013_[11] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[11] : _0091_[11];
assign _0013_[12] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[12] : _0091_[12];
assign _0013_[13] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[13] : _0091_[13];
assign _0013_[14] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[14] : _0091_[14];
assign _0013_[15] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wLength[15] : _0091_[15];
assign _0012_[8] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[8] : _0090_[8];
assign _0012_[9] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[9] : _0090_[9];
assign _0012_[10] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[10] : _0090_[10];
assign _0012_[11] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[11] : _0090_[11];
assign _0012_[12] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[12] : _0090_[12];
assign _0012_[13] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[13] : _0090_[13];
assign _0012_[14] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[14] : _0090_[14];
assign _0012_[15] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wIndex[15] : _0090_[15];
assign _0014_[0] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[0] : _0092_[0];
assign _0014_[1] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[1] : _0092_[1];
assign _0014_[2] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[2] : _0092_[2];
assign _0014_[3] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[3] : _0092_[3];
assign _0014_[4] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[4] : _0092_[4];
assign _0014_[5] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[5] : _0092_[5];
assign _0014_[6] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[6] : _0092_[6];
assign _0014_[7] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) wValue[7] : _0092_[7];
assign _0003_[0] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[0] : _0082_[0];
assign _0003_[1] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[1] : _0082_[1];
assign _0003_[2] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[2] : _0082_[2];
assign _0003_[3] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[3] : _0082_[3];
assign _0003_[4] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[4] : _0082_[4];
assign _0003_[5] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[5] : _0082_[5];
assign _0003_[6] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[6] : _0082_[6];
assign _0003_[7] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bRequest[7] : _0082_[7];
assign _0004_[0] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[0] : _0083_[0];
assign _0004_[1] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[1] : _0083_[1];
assign _0004_[2] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[2] : _0083_[2];
assign _0004_[3] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[3] : _0083_[3];
assign _0004_[4] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[4] : _0083_[4];
assign _0004_[5] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[5] : _0083_[5];
assign _0004_[6] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[6] : _0083_[6];
assign _0004_[7] = _0344_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) bmRequestType[7] : _0083_[7];
assign _0002_[0] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[0] : _0172_[0];
assign _0002_[1] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[1] : _0172_[1];
assign _0002_[2] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[2] : _0172_[2];
assign _0002_[3] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[3] : _0172_[3];
assign _0002_[4] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[4] : _0172_[4];
assign _0002_[5] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[5] : _0172_[5];
assign _0002_[6] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[6] : _0172_[6];
assign _0002_[7] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[7] : _0172_[7];
assign _0002_[8] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[8] : _0172_[8];
assign _0002_[9] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[9] : _0172_[9];
assign _0002_[10] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[10] : _0172_[10];
assign _0002_[11] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[11] : _0172_[11];
assign _0002_[12] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[12] : _0172_[12];
assign _0002_[13] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[13] : _0172_[13];
assign _0002_[14] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[14] : _0172_[14];
assign _0002_[15] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[15] : _0172_[15];
assign _0002_[16] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[16] : _0172_[16];
assign _0002_[17] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[17] : _0172_[17];
assign _0002_[18] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[18] : _0172_[18];
assign _0002_[19] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[19] : _0172_[19];
assign _0002_[20] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[20] : _0172_[20];
assign _0002_[21] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[21] : _0172_[21];
assign _0002_[22] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[22] : _0172_[22];
assign _0002_[23] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[23] : _0172_[23];
assign _0002_[24] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[24] : _0172_[24];
assign _0002_[25] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[25] : _0172_[25];
assign _0002_[26] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[26] : _0172_[26];
assign _0002_[27] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[27] : _0172_[27];
assign _0002_[28] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[28] : _0172_[28];
assign _0002_[29] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[29] : _0172_[29];
assign _0002_[30] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[30] : _0172_[30];
assign _0002_[31] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp2[31] : _0172_[31];
assign _0001_[0] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[0] : _0171_[0];
assign _0001_[1] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[1] : _0171_[1];
assign _0001_[2] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[2] : _0171_[2];
assign _0001_[3] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[3] : _0171_[3];
assign _0001_[4] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[4] : _0171_[4];
assign _0001_[5] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[5] : _0171_[5];
assign _0001_[6] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[6] : _0171_[6];
assign _0001_[7] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[7] : _0171_[7];
assign _0001_[8] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[8] : _0171_[8];
assign _0001_[9] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[9] : _0171_[9];
assign _0001_[10] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[10] : _0171_[10];
assign _0001_[11] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[11] : _0171_[11];
assign _0001_[12] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[12] : _0171_[12];
assign _0001_[13] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[13] : _0171_[13];
assign _0001_[14] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[14] : _0171_[14];
assign _0001_[15] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[15] : _0171_[15];
assign _0001_[16] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[16] : _0171_[16];
assign _0001_[17] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[17] : _0171_[17];
assign _0001_[18] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[18] : _0171_[18];
assign _0001_[19] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[19] : _0171_[19];
assign _0001_[20] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[20] : _0171_[20];
assign _0001_[21] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[21] : _0171_[21];
assign _0001_[22] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[22] : _0171_[22];
assign _0001_[23] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[23] : _0171_[23];
assign _0001_[24] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[24] : _0171_[24];
assign _0001_[25] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[25] : _0171_[25];
assign _0001_[26] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[26] : _0171_[26];
assign _0001_[27] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[27] : _0171_[27];
assign _0001_[28] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[28] : _0171_[28];
assign _0001_[29] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[29] : _0171_[29];
assign _0001_[30] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[30] : _0171_[30];
assign _0001_[31] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) addresstemp1[31] : _0171_[31];
assign _0009_[0] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[0] : _0146_[0];
assign _0009_[1] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[1] : _0146_[1];
assign _0009_[2] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[2] : _0146_[2];
assign _0009_[3] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[3] : _0146_[3];
assign _0009_[4] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[4] : _0146_[4];
assign _0009_[5] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[5] : _0146_[5];
assign _0009_[6] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[6] : _0146_[6];
assign _0009_[7] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[7] : _0146_[7];
assign _0009_[8] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[8] : _0146_[8];
assign _0009_[9] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[9] : _0146_[9];
assign _0009_[10] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[10] : _0146_[10];
assign _0009_[11] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[11] : _0146_[11];
assign _0009_[12] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[12] : _0146_[12];
assign _0009_[13] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[13] : _0146_[13];
assign _0009_[14] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[14] : _0146_[14];
assign _0009_[15] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[15] : _0146_[15];
assign _0009_[16] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[16] : _0146_[16];
assign _0009_[17] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[17] : _0146_[17];
assign _0009_[18] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[18] : _0146_[18];
assign _0009_[19] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[19] : _0146_[19];
assign _0009_[20] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[20] : _0146_[20];
assign _0009_[21] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[21] : _0146_[21];
assign _0009_[22] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[22] : _0146_[22];
assign _0009_[23] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[23] : _0146_[23];
assign _0009_[24] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[24] : _0146_[24];
assign _0009_[25] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[25] : _0146_[25];
assign _0009_[26] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[26] : _0146_[26];
assign _0009_[27] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[27] : _0146_[27];
assign _0009_[28] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[28] : _0146_[28];
assign _0009_[29] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[29] : _0146_[29];
assign _0009_[30] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[30] : _0146_[30];
assign _0009_[31] = _0345_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) readWrite[31] : _0146_[31];
assign _0006_[0] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[0] : _0143_[0];
assign _0006_[1] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[1] : _0143_[1];
assign _0006_[2] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[2] : _0143_[2];
assign _0006_[3] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[3] : _0143_[3];
assign _0006_[4] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[4] : _0143_[4];
assign _0006_[5] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[5] : _0143_[5];
assign _0006_[6] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[6] : _0143_[6];
assign _0006_[7] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[7] : _0143_[7];
assign _0006_[8] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[8] : _0143_[8];
assign _0006_[9] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[9] : _0143_[9];
assign _0006_[10] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[10] : _0143_[10];
assign _0006_[11] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[11] : _0143_[11];
assign _0006_[12] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[12] : _0143_[12];
assign _0006_[13] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[13] : _0143_[13];
assign _0006_[14] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[14] : _0143_[14];
assign _0006_[15] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[15] : _0143_[15];
assign _0006_[16] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[16] : _0143_[16];
assign _0006_[17] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[17] : _0143_[17];
assign _0006_[18] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[18] : _0143_[18];
assign _0006_[19] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[19] : _0143_[19];
assign _0006_[20] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[20] : _0143_[20];
assign _0006_[21] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[21] : _0143_[21];
assign _0006_[22] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[22] : _0143_[22];
assign _0006_[23] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[23] : _0143_[23];
assign _0006_[24] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[24] : _0143_[24];
assign _0006_[25] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[25] : _0143_[25];
assign _0006_[26] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[26] : _0143_[26];
assign _0006_[27] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[27] : _0143_[27];
assign _0006_[28] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[28] : _0143_[28];
assign _0006_[29] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[29] : _0143_[29];
assign _0006_[30] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[30] : _0143_[30];
assign _0006_[31] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[31] : _0143_[31];
assign _0006_[32] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[32] : _0143_[32];
assign _0006_[33] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[33] : _0143_[33];
assign _0006_[34] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[34] : _0143_[34];
assign _0006_[35] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[35] : _0143_[35];
assign _0006_[36] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[36] : _0143_[36];
assign _0006_[37] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[37] : _0143_[37];
assign _0006_[38] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[38] : _0143_[38];
assign _0006_[39] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[39] : _0143_[39];
assign _0006_[40] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[40] : _0143_[40];
assign _0006_[41] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[41] : _0143_[41];
assign _0006_[42] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[42] : _0143_[42];
assign _0006_[43] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[43] : _0143_[43];
assign _0006_[44] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[44] : _0143_[44];
assign _0006_[45] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[45] : _0143_[45];
assign _0006_[46] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[46] : _0143_[46];
assign _0006_[47] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[47] : _0143_[47];
assign _0006_[48] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[48] : _0143_[48];
assign _0006_[49] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[49] : _0143_[49];
assign _0006_[50] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[50] : _0143_[50];
assign _0006_[51] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[51] : _0143_[51];
assign _0006_[52] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[52] : _0143_[52];
assign _0006_[53] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[53] : _0143_[53];
assign _0006_[54] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[54] : _0143_[54];
assign _0006_[55] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[55] : _0143_[55];
assign _0006_[56] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[56] : _0143_[56];
assign _0006_[57] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[57] : _0143_[57];
assign _0006_[58] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[58] : _0143_[58];
assign _0006_[59] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[59] : _0143_[59];
assign _0006_[60] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[60] : _0143_[60];
assign _0006_[61] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[61] : _0143_[61];
assign _0006_[62] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[62] : _0143_[62];
assign _0006_[63] = _0350_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) data_out2[63] : _0143_[63];
assign _0008_[0] = _0484_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0418_[0] : next_state[0];
assign _0008_[1] = _0484_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0418_[1] : next_state[1];
assign _0008_[2] = _0484_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0418_[2] : next_state[2];
assign _0008_[3] = _0484_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0418_[3] : next_state[3];
assign _0008_[4] = _0484_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0418_[4] : next_state[4];
assign _0010_ = _0485_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0420_ : singl_data;
assign _0000_[0] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[0] : address[0];
assign _0000_[1] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[1] : address[1];
assign _0000_[2] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[2] : address[2];
assign _0000_[3] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[3] : address[3];
assign _0000_[4] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[4] : address[4];
assign _0000_[5] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[5] : address[5];
assign _0000_[6] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[6] : address[6];
assign _0000_[7] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[7] : address[7];
assign _0000_[8] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[8] : address[8];
assign _0000_[9] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[9] : address[9];
assign _0000_[10] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[10] : address[10];
assign _0000_[11] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[11] : address[11];
assign _0000_[12] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[12] : address[12];
assign _0000_[13] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[13] : address[13];
assign _0000_[14] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[14] : address[14];
assign _0000_[15] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[15] : address[15];
assign _0000_[16] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[16] : address[16];
assign _0000_[17] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[17] : address[17];
assign _0000_[18] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[18] : address[18];
assign _0000_[19] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[19] : address[19];
assign _0000_[20] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[20] : address[20];
assign _0000_[21] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[21] : address[21];
assign _0000_[22] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[22] : address[22];
assign _0000_[23] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[23] : address[23];
assign _0000_[24] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[24] : address[24];
assign _0000_[25] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[25] : address[25];
assign _0000_[26] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[26] : address[26];
assign _0000_[27] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[27] : address[27];
assign _0000_[28] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[28] : address[28];
assign _0000_[29] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[29] : address[29];
assign _0000_[30] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[30] : address[30];
assign _0000_[31] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[31] : address[31];
assign _0000_[32] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[32] : address[32];
assign _0000_[33] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[33] : address[33];
assign _0000_[34] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[34] : address[34];
assign _0000_[35] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[35] : address[35];
assign _0000_[36] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[36] : address[36];
assign _0000_[37] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[37] : address[37];
assign _0000_[38] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[38] : address[38];
assign _0000_[39] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[39] : address[39];
assign _0000_[40] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[40] : address[40];
assign _0000_[41] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[41] : address[41];
assign _0000_[42] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[42] : address[42];
assign _0000_[43] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[43] : address[43];
assign _0000_[44] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[44] : address[44];
assign _0000_[45] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[45] : address[45];
assign _0000_[46] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[46] : address[46];
assign _0000_[47] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[47] : address[47];
assign _0000_[48] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[48] : address[48];
assign _0000_[49] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[49] : address[49];
assign _0000_[50] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[50] : address[50];
assign _0000_[51] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[51] : address[51];
assign _0000_[52] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[52] : address[52];
assign _0000_[53] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[53] : address[53];
assign _0000_[54] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[54] : address[54];
assign _0000_[55] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[55] : address[55];
assign _0000_[56] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[56] : address[56];
assign _0000_[57] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[57] : address[57];
assign _0000_[58] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[58] : address[58];
assign _0000_[59] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[59] : address[59];
assign _0000_[60] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[60] : address[60];
assign _0000_[61] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[61] : address[61];
assign _0000_[62] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[62] : address[62];
assign _0000_[63] = _0486_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0422_[63] : address[63];
assign _0005_[0] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[0] : count[0];
assign _0005_[1] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[1] : count[1];
assign _0005_[2] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[2] : count[2];
assign _0005_[3] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[3] : count[3];
assign _0005_[4] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[4] : count[4];
assign _0005_[5] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[5] : count[5];
assign _0005_[6] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[6] : count[6];
assign _0005_[7] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[7] : count[7];
assign _0005_[8] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[8] : count[8];
assign _0005_[9] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[9] : count[9];
assign _0005_[10] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[10] : count[10];
assign _0005_[11] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[11] : count[11];
assign _0005_[12] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[12] : count[12];
assign _0005_[13] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[13] : count[13];
assign _0005_[14] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[14] : count[14];
assign _0005_[15] = _0487_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0424_[15] : count[15];
assign _0007_[0] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[0] : data_out[0];
assign _0007_[1] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[1] : data_out[1];
assign _0007_[2] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[2] : data_out[2];
assign _0007_[3] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[3] : data_out[3];
assign _0007_[4] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[4] : data_out[4];
assign _0007_[5] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[5] : data_out[5];
assign _0007_[6] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[6] : data_out[6];
assign _0007_[7] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[7] : data_out[7];
assign _0007_[8] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[8] : data_out[8];
assign _0007_[9] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[9] : data_out[9];
assign _0007_[10] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[10] : data_out[10];
assign _0007_[11] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[11] : data_out[11];
assign _0007_[12] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[12] : data_out[12];
assign _0007_[13] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[13] : data_out[13];
assign _0007_[14] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[14] : data_out[14];
assign _0007_[15] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[15] : data_out[15];
assign _0007_[16] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[16] : data_out[16];
assign _0007_[17] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[17] : data_out[17];
assign _0007_[18] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[18] : data_out[18];
assign _0007_[19] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[19] : data_out[19];
assign _0007_[20] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[20] : data_out[20];
assign _0007_[21] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[21] : data_out[21];
assign _0007_[22] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[22] : data_out[22];
assign _0007_[23] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[23] : data_out[23];
assign _0007_[24] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[24] : data_out[24];
assign _0007_[25] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[25] : data_out[25];
assign _0007_[26] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[26] : data_out[26];
assign _0007_[27] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[27] : data_out[27];
assign _0007_[28] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[28] : data_out[28];
assign _0007_[29] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[29] : data_out[29];
assign _0007_[30] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[30] : data_out[30];
assign _0007_[31] = _0488_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:445" *) _0426_[31] : data_out[31];
assign _0011_[0] = rst ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:64" *) 1'b1 : next_state[0];
assign _0011_[1] = rst ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:64" *) 1'b0 : next_state[1];
assign _0011_[2] = rst ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:64" *) 1'b0 : next_state[2];
assign _0011_[3] = rst ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:64" *) 1'b0 : next_state[3];
assign _0011_[4] = rst ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:64" *) 1'b0 : next_state[4];
assign _0026_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[0] : 1'b1;
assign _0026_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[1] : 1'b1;
assign _0026_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[2] : 1'b1;
assign _0026_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[3] : 1'b1;
assign _0026_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[4] : 1'b1;
assign _0026_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[5] : 1'b0;
assign _0026_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[6] : 1'b0;
assign _0026_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[7] : 1'b1;
assign _0026_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[8] : 1'b1;
assign _0026_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[9] : 1'b0;
assign _0026_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[10] : 1'b0;
assign _0026_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[11] : 1'b0;
assign _0026_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[12] : 1'b0;
assign _0026_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[13] : 1'b1;
assign _0026_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[14] : 1'b0;
assign _0026_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[15] : 1'b0;
assign _0026_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[16] : 1'b0;
assign _0026_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[17] : 1'b0;
assign _0026_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[18] : 1'b0;
assign _0026_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[19] : 1'b0;
assign _0026_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[20] : 1'b0;
assign _0026_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[21] : 1'b0;
assign _0026_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[22] : 1'b0;
assign _0026_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[23] : 1'b0;
assign _0026_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[24] : 1'b0;
assign _0026_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[25] : 1'b0;
assign _0026_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[26] : 1'b0;
assign _0026_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[27] : 1'b0;
assign _0026_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[28] : 1'b0;
assign _0026_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[29] : 1'b0;
assign _0026_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[30] : 1'b0;
assign _0026_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:773" *) _0161_[31] : 1'b0;
assign _0019_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[0] : _0161_[0];
assign _0019_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[1] : _0161_[1];
assign _0019_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[2] : _0161_[2];
assign _0019_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[3] : _0161_[3];
assign _0019_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[4] : _0161_[4];
assign _0019_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[5] : _0161_[5];
assign _0019_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[6] : _0161_[6];
assign _0019_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[7] : _0161_[7];
assign _0019_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[8] : _0161_[8];
assign _0019_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[9] : _0161_[9];
assign _0019_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[10] : _0161_[10];
assign _0019_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[11] : _0161_[11];
assign _0019_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[12] : _0161_[12];
assign _0019_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[13] : _0161_[13];
assign _0019_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[14] : _0161_[14];
assign _0019_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[15] : _0161_[15];
assign _0019_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[16] : _0161_[16];
assign _0019_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[17] : _0161_[17];
assign _0019_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[18] : _0161_[18];
assign _0019_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[19] : _0161_[19];
assign _0019_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[20] : _0161_[20];
assign _0019_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[21] : _0161_[21];
assign _0019_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[22] : _0161_[22];
assign _0019_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[23] : _0161_[23];
assign _0019_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[24] : _0161_[24];
assign _0019_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[25] : _0161_[25];
assign _0019_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[26] : _0161_[26];
assign _0019_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[27] : _0161_[27];
assign _0019_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[28] : _0161_[28];
assign _0019_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[29] : _0161_[29];
assign _0019_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[30] : _0161_[30];
assign _0019_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:771" *) _0026_[31] : _0161_[31];
assign _0174_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[0] : 1'b1;
assign _0174_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[1] : 1'b1;
assign _0174_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[2] : 1'b1;
assign _0174_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[3] : 1'b1;
assign _0174_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[4] : 1'b1;
assign _0174_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[5] : 1'b0;
assign _0174_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[6] : 1'b0;
assign _0174_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[7] : 1'b1;
assign _0174_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[8] : 1'b1;
assign _0174_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[9] : 1'b0;
assign _0174_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[10] : 1'b0;
assign _0174_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[11] : 1'b0;
assign _0174_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[12] : 1'b0;
assign _0174_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[13] : 1'b1;
assign _0174_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[14] : 1'b0;
assign _0174_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[15] : 1'b0;
assign _0174_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[16] : 1'b0;
assign _0174_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[17] : 1'b0;
assign _0174_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[18] : 1'b0;
assign _0174_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[19] : 1'b0;
assign _0174_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[20] : 1'b0;
assign _0174_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[21] : 1'b0;
assign _0174_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[22] : 1'b0;
assign _0174_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[23] : 1'b0;
assign _0174_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[24] : 1'b0;
assign _0174_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[25] : 1'b0;
assign _0174_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[26] : 1'b0;
assign _0174_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[27] : 1'b0;
assign _0174_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[28] : 1'b0;
assign _0174_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[29] : 1'b0;
assign _0174_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[30] : 1'b0;
assign _0174_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:764" *) _0168_[31] : 1'b0;
assign _0168_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[0] : 1'b1;
assign _0168_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[1] : 1'b1;
assign _0168_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[2] : 1'b1;
assign _0168_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[3] : 1'b1;
assign _0168_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[4] : 1'b1;
assign _0168_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[5] : 1'b0;
assign _0168_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[6] : 1'b0;
assign _0168_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[7] : 1'b1;
assign _0168_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[8] : 1'b1;
assign _0168_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[9] : 1'b0;
assign _0168_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[10] : 1'b0;
assign _0168_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[11] : 1'b0;
assign _0168_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[12] : 1'b0;
assign _0168_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[13] : 1'b1;
assign _0168_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[14] : 1'b0;
assign _0168_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[15] : 1'b0;
assign _0168_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[16] : 1'b0;
assign _0168_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[17] : 1'b0;
assign _0168_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[18] : 1'b0;
assign _0168_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[19] : 1'b0;
assign _0168_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[20] : 1'b0;
assign _0168_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[21] : 1'b0;
assign _0168_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[22] : 1'b0;
assign _0168_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[23] : 1'b0;
assign _0168_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[24] : 1'b0;
assign _0168_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[25] : 1'b0;
assign _0168_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[26] : 1'b0;
assign _0168_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[27] : 1'b0;
assign _0168_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[28] : 1'b0;
assign _0168_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[29] : 1'b0;
assign _0168_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[30] : 1'b0;
assign _0168_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:758" *) data_out[31] : 1'b0;
assign _0161_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[0] : _0174_[0];
assign _0161_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[1] : _0174_[1];
assign _0161_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[2] : _0174_[2];
assign _0161_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[3] : _0174_[3];
assign _0161_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[4] : _0174_[4];
assign _0161_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[5] : _0174_[5];
assign _0161_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[6] : _0174_[6];
assign _0161_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[7] : _0174_[7];
assign _0161_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[8] : _0174_[8];
assign _0161_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[9] : _0174_[9];
assign _0161_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[10] : _0174_[10];
assign _0161_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[11] : _0174_[11];
assign _0161_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[12] : _0174_[12];
assign _0161_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[13] : _0174_[13];
assign _0161_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[14] : _0174_[14];
assign _0161_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[15] : _0174_[15];
assign _0161_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[16] : _0174_[16];
assign _0161_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[17] : _0174_[17];
assign _0161_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[18] : _0174_[18];
assign _0161_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[19] : _0174_[19];
assign _0161_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[20] : _0174_[20];
assign _0161_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[21] : _0174_[21];
assign _0161_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[22] : _0174_[22];
assign _0161_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[23] : _0174_[23];
assign _0161_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[24] : _0174_[24];
assign _0161_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[25] : _0174_[25];
assign _0161_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[26] : _0174_[26];
assign _0161_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[27] : _0174_[27];
assign _0161_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[28] : _0174_[28];
assign _0161_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[29] : _0174_[29];
assign _0161_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[30] : _0174_[30];
assign _0161_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:756" *) data_out[31] : _0174_[31];
assign _0152_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[0] : readWrite[0];
assign _0152_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[1] : readWrite[1];
assign _0152_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[2] : readWrite[2];
assign _0152_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[3] : readWrite[3];
assign _0152_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[4] : readWrite[4];
assign _0152_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[5] : readWrite[5];
assign _0152_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[6] : readWrite[6];
assign _0152_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[7] : readWrite[7];
assign _0152_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[8] : readWrite[8];
assign _0152_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[9] : readWrite[9];
assign _0152_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[10] : readWrite[10];
assign _0152_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[11] : readWrite[11];
assign _0152_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[12] : readWrite[12];
assign _0152_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[13] : readWrite[13];
assign _0152_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[14] : readWrite[14];
assign _0152_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[15] : readWrite[15];
assign _0152_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[16] : readWrite[16];
assign _0152_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[17] : readWrite[17];
assign _0152_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[18] : readWrite[18];
assign _0152_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[19] : readWrite[19];
assign _0152_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[20] : readWrite[20];
assign _0152_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[21] : readWrite[21];
assign _0152_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[22] : readWrite[22];
assign _0152_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[23] : readWrite[23];
assign _0152_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[24] : readWrite[24];
assign _0152_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[25] : readWrite[25];
assign _0152_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[26] : readWrite[26];
assign _0152_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[27] : readWrite[27];
assign _0152_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[28] : readWrite[28];
assign _0152_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[29] : readWrite[29];
assign _0152_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[30] : readWrite[30];
assign _0152_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:721" *) _0086_[31] : readWrite[31];
assign _0144_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[0] : _0086_[0];
assign _0144_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[1] : _0086_[1];
assign _0144_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[2] : _0086_[2];
assign _0144_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[3] : _0086_[3];
assign _0144_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[4] : _0086_[4];
assign _0144_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[5] : _0086_[5];
assign _0144_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[6] : _0086_[6];
assign _0144_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[7] : _0086_[7];
assign _0144_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[8] : _0086_[8];
assign _0144_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[9] : _0086_[9];
assign _0144_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[10] : _0086_[10];
assign _0144_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[11] : _0086_[11];
assign _0144_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[12] : _0086_[12];
assign _0144_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[13] : _0086_[13];
assign _0144_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[14] : _0086_[14];
assign _0144_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[15] : _0086_[15];
assign _0144_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[16] : _0086_[16];
assign _0144_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[17] : _0086_[17];
assign _0144_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[18] : _0086_[18];
assign _0144_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[19] : _0086_[19];
assign _0144_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[20] : _0086_[20];
assign _0144_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[21] : _0086_[21];
assign _0144_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[22] : _0086_[22];
assign _0144_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[23] : _0086_[23];
assign _0144_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[24] : _0086_[24];
assign _0144_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[25] : _0086_[25];
assign _0144_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[26] : _0086_[26];
assign _0144_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[27] : _0086_[27];
assign _0144_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[28] : _0086_[28];
assign _0144_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[29] : _0086_[29];
assign _0144_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[30] : _0086_[30];
assign _0144_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:719" *) _0152_[31] : _0086_[31];
assign _0129_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[0] : readWrite[0];
assign _0129_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[1] : readWrite[1];
assign _0129_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[2] : readWrite[2];
assign _0129_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[3] : readWrite[3];
assign _0129_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[4] : readWrite[4];
assign _0129_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[5] : readWrite[5];
assign _0129_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[6] : readWrite[6];
assign _0129_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[7] : readWrite[7];
assign _0129_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[8] : readWrite[8];
assign _0129_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[9] : readWrite[9];
assign _0129_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[10] : readWrite[10];
assign _0129_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[11] : readWrite[11];
assign _0129_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[12] : readWrite[12];
assign _0129_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[13] : readWrite[13];
assign _0129_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[14] : readWrite[14];
assign _0129_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[15] : readWrite[15];
assign _0129_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[16] : readWrite[16];
assign _0129_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[17] : readWrite[17];
assign _0129_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[18] : readWrite[18];
assign _0129_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[19] : readWrite[19];
assign _0129_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[20] : readWrite[20];
assign _0129_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[21] : readWrite[21];
assign _0129_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[22] : readWrite[22];
assign _0129_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[23] : readWrite[23];
assign _0129_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[24] : readWrite[24];
assign _0129_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[25] : readWrite[25];
assign _0129_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[26] : readWrite[26];
assign _0129_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[27] : readWrite[27];
assign _0129_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[28] : readWrite[28];
assign _0129_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[29] : readWrite[29];
assign _0129_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[30] : readWrite[30];
assign _0129_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:712" *) _0113_[31] : readWrite[31];
assign _0113_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[0] : readWrite[0];
assign _0113_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[1] : readWrite[1];
assign _0113_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[2] : readWrite[2];
assign _0113_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[3] : readWrite[3];
assign _0113_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[4] : readWrite[4];
assign _0113_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[5] : readWrite[5];
assign _0113_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[6] : readWrite[6];
assign _0113_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[7] : readWrite[7];
assign _0113_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[8] : readWrite[8];
assign _0113_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[9] : readWrite[9];
assign _0113_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[10] : readWrite[10];
assign _0113_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[11] : readWrite[11];
assign _0113_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[12] : readWrite[12];
assign _0113_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[13] : readWrite[13];
assign _0113_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[14] : readWrite[14];
assign _0113_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[15] : readWrite[15];
assign _0113_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[16] : readWrite[16];
assign _0113_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[17] : readWrite[17];
assign _0113_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[18] : readWrite[18];
assign _0113_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[19] : readWrite[19];
assign _0113_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[20] : readWrite[20];
assign _0113_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[21] : readWrite[21];
assign _0113_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[22] : readWrite[22];
assign _0113_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[23] : readWrite[23];
assign _0113_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[24] : readWrite[24];
assign _0113_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[25] : readWrite[25];
assign _0113_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[26] : readWrite[26];
assign _0113_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[27] : readWrite[27];
assign _0113_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[28] : readWrite[28];
assign _0113_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[29] : readWrite[29];
assign _0113_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[30] : readWrite[30];
assign _0113_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:706" *) data_out[31] : readWrite[31];
assign _0086_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[0] : _0129_[0];
assign _0086_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[1] : _0129_[1];
assign _0086_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[2] : _0129_[2];
assign _0086_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[3] : _0129_[3];
assign _0086_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[4] : _0129_[4];
assign _0086_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[5] : _0129_[5];
assign _0086_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[6] : _0129_[6];
assign _0086_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[7] : _0129_[7];
assign _0086_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[8] : _0129_[8];
assign _0086_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[9] : _0129_[9];
assign _0086_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[10] : _0129_[10];
assign _0086_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[11] : _0129_[11];
assign _0086_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[12] : _0129_[12];
assign _0086_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[13] : _0129_[13];
assign _0086_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[14] : _0129_[14];
assign _0086_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[15] : _0129_[15];
assign _0086_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[16] : _0129_[16];
assign _0086_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[17] : _0129_[17];
assign _0086_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[18] : _0129_[18];
assign _0086_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[19] : _0129_[19];
assign _0086_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[20] : _0129_[20];
assign _0086_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[21] : _0129_[21];
assign _0086_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[22] : _0129_[22];
assign _0086_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[23] : _0129_[23];
assign _0086_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[24] : _0129_[24];
assign _0086_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[25] : _0129_[25];
assign _0086_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[26] : _0129_[26];
assign _0086_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[27] : _0129_[27];
assign _0086_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[28] : _0129_[28];
assign _0086_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[29] : _0129_[29];
assign _0086_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[30] : _0129_[30];
assign _0086_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:704" *) data_out[31] : _0129_[31];
assign _0160_[0] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[0] : address[0];
assign _0160_[1] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[1] : address[1];
assign _0160_[2] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[2] : address[2];
assign _0160_[3] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[3] : address[3];
assign _0160_[4] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[4] : address[4];
assign _0160_[5] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[5] : address[5];
assign _0160_[6] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[6] : address[6];
assign _0160_[7] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[7] : address[7];
assign _0160_[8] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[8] : address[8];
assign _0160_[9] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[9] : address[9];
assign _0160_[10] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[10] : address[10];
assign _0160_[11] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[11] : address[11];
assign _0160_[12] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[12] : address[12];
assign _0160_[13] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[13] : address[13];
assign _0160_[14] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[14] : address[14];
assign _0160_[15] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[15] : address[15];
assign _0160_[16] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[16] : address[16];
assign _0160_[17] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[17] : address[17];
assign _0160_[18] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[18] : address[18];
assign _0160_[19] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[19] : address[19];
assign _0160_[20] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[20] : address[20];
assign _0160_[21] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[21] : address[21];
assign _0160_[22] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[22] : address[22];
assign _0160_[23] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[23] : address[23];
assign _0160_[24] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[24] : address[24];
assign _0160_[25] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[25] : address[25];
assign _0160_[26] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[26] : address[26];
assign _0160_[27] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[27] : address[27];
assign _0160_[28] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[28] : address[28];
assign _0160_[29] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[29] : address[29];
assign _0160_[30] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[30] : address[30];
assign _0160_[31] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[31] : address[31];
assign _0160_[32] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[32] : address[32];
assign _0160_[33] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[33] : address[33];
assign _0160_[34] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[34] : address[34];
assign _0160_[35] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[35] : address[35];
assign _0160_[36] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[36] : address[36];
assign _0160_[37] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[37] : address[37];
assign _0160_[38] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[38] : address[38];
assign _0160_[39] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[39] : address[39];
assign _0160_[40] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[40] : address[40];
assign _0160_[41] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[41] : address[41];
assign _0160_[42] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[42] : address[42];
assign _0160_[43] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[43] : address[43];
assign _0160_[44] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[44] : address[44];
assign _0160_[45] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[45] : address[45];
assign _0160_[46] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[46] : address[46];
assign _0160_[47] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[47] : address[47];
assign _0160_[48] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[48] : address[48];
assign _0160_[49] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[49] : address[49];
assign _0160_[50] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[50] : address[50];
assign _0160_[51] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[51] : address[51];
assign _0160_[52] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[52] : address[52];
assign _0160_[53] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[53] : address[53];
assign _0160_[54] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[54] : address[54];
assign _0160_[55] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[55] : address[55];
assign _0160_[56] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[56] : address[56];
assign _0160_[57] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[57] : address[57];
assign _0160_[58] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[58] : address[58];
assign _0160_[59] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[59] : address[59];
assign _0160_[60] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[60] : address[60];
assign _0160_[61] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[61] : address[61];
assign _0160_[62] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[62] : address[62];
assign _0160_[63] = _0371_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:685" *) _0151_[63] : address[63];
assign _0151_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[0] : address[0];
assign _0151_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[1] : address[1];
assign _0151_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[2] : address[2];
assign _0151_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[3] : address[3];
assign _0151_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[4] : address[4];
assign _0151_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[5] : address[5];
assign _0151_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[6] : address[6];
assign _0151_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[7] : address[7];
assign _0151_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[8] : address[8];
assign _0151_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[9] : address[9];
assign _0151_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[10] : address[10];
assign _0151_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[11] : address[11];
assign _0151_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[12] : address[12];
assign _0151_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[13] : address[13];
assign _0151_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[14] : address[14];
assign _0151_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[15] : address[15];
assign _0151_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[16] : address[16];
assign _0151_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[17] : address[17];
assign _0151_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[18] : address[18];
assign _0151_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[19] : address[19];
assign _0151_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[20] : address[20];
assign _0151_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[21] : address[21];
assign _0151_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[22] : address[22];
assign _0151_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[23] : address[23];
assign _0151_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[24] : address[24];
assign _0151_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[25] : address[25];
assign _0151_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[26] : address[26];
assign _0151_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[27] : address[27];
assign _0151_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[28] : address[28];
assign _0151_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[29] : address[29];
assign _0151_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[30] : address[30];
assign _0151_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[31] : address[31];
assign _0151_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[32] : address[32];
assign _0151_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[33] : address[33];
assign _0151_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[34] : address[34];
assign _0151_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[35] : address[35];
assign _0151_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[36] : address[36];
assign _0151_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[37] : address[37];
assign _0151_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[38] : address[38];
assign _0151_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[39] : address[39];
assign _0151_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[40] : address[40];
assign _0151_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[41] : address[41];
assign _0151_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[42] : address[42];
assign _0151_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[43] : address[43];
assign _0151_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[44] : address[44];
assign _0151_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[45] : address[45];
assign _0151_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[46] : address[46];
assign _0151_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[47] : address[47];
assign _0151_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[48] : address[48];
assign _0151_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[49] : address[49];
assign _0151_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[50] : address[50];
assign _0151_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[51] : address[51];
assign _0151_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[52] : address[52];
assign _0151_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[53] : address[53];
assign _0151_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[54] : address[54];
assign _0151_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[55] : address[55];
assign _0151_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[56] : address[56];
assign _0151_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[57] : address[57];
assign _0151_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[58] : address[58];
assign _0151_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[59] : address[59];
assign _0151_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[60] : address[60];
assign _0151_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[61] : address[61];
assign _0151_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[62] : address[62];
assign _0151_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:678" *) _0085_[63] : address[63];
assign _0143_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[0] : _0085_[0];
assign _0143_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[1] : _0085_[1];
assign _0143_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[2] : _0085_[2];
assign _0143_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[3] : _0085_[3];
assign _0143_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[4] : _0085_[4];
assign _0143_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[5] : _0085_[5];
assign _0143_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[6] : _0085_[6];
assign _0143_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[7] : _0085_[7];
assign _0143_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[8] : _0085_[8];
assign _0143_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[9] : _0085_[9];
assign _0143_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[10] : _0085_[10];
assign _0143_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[11] : _0085_[11];
assign _0143_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[12] : _0085_[12];
assign _0143_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[13] : _0085_[13];
assign _0143_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[14] : _0085_[14];
assign _0143_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[15] : _0085_[15];
assign _0143_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[16] : _0085_[16];
assign _0143_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[17] : _0085_[17];
assign _0143_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[18] : _0085_[18];
assign _0143_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[19] : _0085_[19];
assign _0143_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[20] : _0085_[20];
assign _0143_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[21] : _0085_[21];
assign _0143_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[22] : _0085_[22];
assign _0143_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[23] : _0085_[23];
assign _0143_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[24] : _0085_[24];
assign _0143_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[25] : _0085_[25];
assign _0143_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[26] : _0085_[26];
assign _0143_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[27] : _0085_[27];
assign _0143_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[28] : _0085_[28];
assign _0143_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[29] : _0085_[29];
assign _0143_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[30] : _0085_[30];
assign _0143_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[31] : _0085_[31];
assign _0143_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[32] : _0085_[32];
assign _0143_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[33] : _0085_[33];
assign _0143_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[34] : _0085_[34];
assign _0143_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[35] : _0085_[35];
assign _0143_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[36] : _0085_[36];
assign _0143_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[37] : _0085_[37];
assign _0143_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[38] : _0085_[38];
assign _0143_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[39] : _0085_[39];
assign _0143_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[40] : _0085_[40];
assign _0143_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[41] : _0085_[41];
assign _0143_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[42] : _0085_[42];
assign _0143_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[43] : _0085_[43];
assign _0143_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[44] : _0085_[44];
assign _0143_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[45] : _0085_[45];
assign _0143_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[46] : _0085_[46];
assign _0143_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[47] : _0085_[47];
assign _0143_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[48] : _0085_[48];
assign _0143_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[49] : _0085_[49];
assign _0143_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[50] : _0085_[50];
assign _0143_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[51] : _0085_[51];
assign _0143_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[52] : _0085_[52];
assign _0143_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[53] : _0085_[53];
assign _0143_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[54] : _0085_[54];
assign _0143_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[55] : _0085_[55];
assign _0143_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[56] : _0085_[56];
assign _0143_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[57] : _0085_[57];
assign _0143_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[58] : _0085_[58];
assign _0143_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[59] : _0085_[59];
assign _0143_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[60] : _0085_[60];
assign _0143_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[61] : _0085_[61];
assign _0143_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[62] : _0085_[62];
assign _0143_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:676" *) _0160_[63] : _0085_[63];
assign _0128_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[0] : address[0];
assign _0128_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[1] : address[1];
assign _0128_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[2] : address[2];
assign _0128_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[3] : address[3];
assign _0128_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[4] : address[4];
assign _0128_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[5] : address[5];
assign _0128_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[6] : address[6];
assign _0128_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[7] : address[7];
assign _0128_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[8] : address[8];
assign _0128_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[9] : address[9];
assign _0128_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[10] : address[10];
assign _0128_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[11] : address[11];
assign _0128_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[12] : address[12];
assign _0128_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[13] : address[13];
assign _0128_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[14] : address[14];
assign _0128_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[15] : address[15];
assign _0128_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[16] : address[16];
assign _0128_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[17] : address[17];
assign _0128_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[18] : address[18];
assign _0128_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[19] : address[19];
assign _0128_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[20] : address[20];
assign _0128_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[21] : address[21];
assign _0128_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[22] : address[22];
assign _0128_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[23] : address[23];
assign _0128_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[24] : address[24];
assign _0128_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[25] : address[25];
assign _0128_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[26] : address[26];
assign _0128_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[27] : address[27];
assign _0128_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[28] : address[28];
assign _0128_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[29] : address[29];
assign _0128_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[30] : address[30];
assign _0128_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[31] : address[31];
assign _0128_[32] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[32] : address[32];
assign _0128_[33] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[33] : address[33];
assign _0128_[34] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[34] : address[34];
assign _0128_[35] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[35] : address[35];
assign _0128_[36] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[36] : address[36];
assign _0128_[37] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[37] : address[37];
assign _0128_[38] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[38] : address[38];
assign _0128_[39] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[39] : address[39];
assign _0128_[40] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[40] : address[40];
assign _0128_[41] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[41] : address[41];
assign _0128_[42] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[42] : address[42];
assign _0128_[43] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[43] : address[43];
assign _0128_[44] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[44] : address[44];
assign _0128_[45] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[45] : address[45];
assign _0128_[46] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[46] : address[46];
assign _0128_[47] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[47] : address[47];
assign _0128_[48] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[48] : address[48];
assign _0128_[49] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[49] : address[49];
assign _0128_[50] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[50] : address[50];
assign _0128_[51] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[51] : address[51];
assign _0128_[52] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[52] : address[52];
assign _0128_[53] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[53] : address[53];
assign _0128_[54] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[54] : address[54];
assign _0128_[55] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[55] : address[55];
assign _0128_[56] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[56] : address[56];
assign _0128_[57] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[57] : address[57];
assign _0128_[58] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[58] : address[58];
assign _0128_[59] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[59] : address[59];
assign _0128_[60] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[60] : address[60];
assign _0128_[61] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[61] : address[61];
assign _0128_[62] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[62] : address[62];
assign _0128_[63] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:663" *) _0112_[63] : address[63];
assign _0112_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[0] : address[0];
assign _0112_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[1] : address[1];
assign _0112_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[2] : address[2];
assign _0112_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[3] : address[3];
assign _0112_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[4] : address[4];
assign _0112_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[5] : address[5];
assign _0112_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[6] : address[6];
assign _0112_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[7] : address[7];
assign _0112_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[8] : address[8];
assign _0112_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[9] : address[9];
assign _0112_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[10] : address[10];
assign _0112_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[11] : address[11];
assign _0112_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[12] : address[12];
assign _0112_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[13] : address[13];
assign _0112_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[14] : address[14];
assign _0112_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[15] : address[15];
assign _0112_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[16] : address[16];
assign _0112_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[17] : address[17];
assign _0112_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[18] : address[18];
assign _0112_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[19] : address[19];
assign _0112_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[20] : address[20];
assign _0112_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[21] : address[21];
assign _0112_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[22] : address[22];
assign _0112_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[23] : address[23];
assign _0112_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[24] : address[24];
assign _0112_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[25] : address[25];
assign _0112_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[26] : address[26];
assign _0112_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[27] : address[27];
assign _0112_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[28] : address[28];
assign _0112_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[29] : address[29];
assign _0112_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[30] : address[30];
assign _0112_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[31] : address[31];
assign _0112_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[32] : address[32];
assign _0112_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[33] : address[33];
assign _0112_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[34] : address[34];
assign _0112_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[35] : address[35];
assign _0112_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[36] : address[36];
assign _0112_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[37] : address[37];
assign _0112_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[38] : address[38];
assign _0112_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[39] : address[39];
assign _0112_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[40] : address[40];
assign _0112_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[41] : address[41];
assign _0112_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[42] : address[42];
assign _0112_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[43] : address[43];
assign _0112_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[44] : address[44];
assign _0112_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[45] : address[45];
assign _0112_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[46] : address[46];
assign _0112_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[47] : address[47];
assign _0112_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[48] : address[48];
assign _0112_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[49] : address[49];
assign _0112_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[50] : address[50];
assign _0112_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[51] : address[51];
assign _0112_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[52] : address[52];
assign _0112_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[53] : address[53];
assign _0112_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[54] : address[54];
assign _0112_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[55] : address[55];
assign _0112_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[56] : address[56];
assign _0112_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[57] : address[57];
assign _0112_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[58] : address[58];
assign _0112_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[59] : address[59];
assign _0112_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[60] : address[60];
assign _0112_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[61] : address[61];
assign _0112_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[62] : address[62];
assign _0112_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:653" *) data_out2[63] : address[63];
assign _0085_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[0] : _0128_[0];
assign _0085_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[1] : _0128_[1];
assign _0085_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[2] : _0128_[2];
assign _0085_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[3] : _0128_[3];
assign _0085_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[4] : _0128_[4];
assign _0085_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[5] : _0128_[5];
assign _0085_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[6] : _0128_[6];
assign _0085_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[7] : _0128_[7];
assign _0085_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[8] : _0128_[8];
assign _0085_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[9] : _0128_[9];
assign _0085_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[10] : _0128_[10];
assign _0085_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[11] : _0128_[11];
assign _0085_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[12] : _0128_[12];
assign _0085_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[13] : _0128_[13];
assign _0085_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[14] : _0128_[14];
assign _0085_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[15] : _0128_[15];
assign _0085_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[16] : _0128_[16];
assign _0085_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[17] : _0128_[17];
assign _0085_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[18] : _0128_[18];
assign _0085_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[19] : _0128_[19];
assign _0085_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[20] : _0128_[20];
assign _0085_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[21] : _0128_[21];
assign _0085_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[22] : _0128_[22];
assign _0085_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[23] : _0128_[23];
assign _0085_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[24] : _0128_[24];
assign _0085_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[25] : _0128_[25];
assign _0085_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[26] : _0128_[26];
assign _0085_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[27] : _0128_[27];
assign _0085_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[28] : _0128_[28];
assign _0085_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[29] : _0128_[29];
assign _0085_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[30] : _0128_[30];
assign _0085_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[31] : _0128_[31];
assign _0085_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[32] : _0128_[32];
assign _0085_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[33] : _0128_[33];
assign _0085_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[34] : _0128_[34];
assign _0085_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[35] : _0128_[35];
assign _0085_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[36] : _0128_[36];
assign _0085_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[37] : _0128_[37];
assign _0085_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[38] : _0128_[38];
assign _0085_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[39] : _0128_[39];
assign _0085_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[40] : _0128_[40];
assign _0085_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[41] : _0128_[41];
assign _0085_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[42] : _0128_[42];
assign _0085_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[43] : _0128_[43];
assign _0085_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[44] : _0128_[44];
assign _0085_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[45] : _0128_[45];
assign _0085_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[46] : _0128_[46];
assign _0085_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[47] : _0128_[47];
assign _0085_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[48] : _0128_[48];
assign _0085_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[49] : _0128_[49];
assign _0085_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[50] : _0128_[50];
assign _0085_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[51] : _0128_[51];
assign _0085_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[52] : _0128_[52];
assign _0085_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[53] : _0128_[53];
assign _0085_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[54] : _0128_[54];
assign _0085_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[55] : _0128_[55];
assign _0085_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[56] : _0128_[56];
assign _0085_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[57] : _0128_[57];
assign _0085_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[58] : _0128_[58];
assign _0085_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[59] : _0128_[59];
assign _0085_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[60] : _0128_[60];
assign _0085_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[61] : _0128_[61];
assign _0085_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[62] : _0128_[62];
assign _0085_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:651" *) data_out2[63] : _0128_[63];
assign _0138_[0] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0102_;
assign _0103_[0] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[0] : _0100_[0];
assign _0103_[1] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[1] : _0100_[1];
assign _0103_[2] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[2] : _0100_[2];
assign _0103_[3] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[3] : _0100_[3];
assign _0103_[4] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[4] : _0100_[4];
assign _0103_[5] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[5] : _0100_[5];
assign _0103_[6] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[6] : _0100_[6];
assign _0103_[7] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[7] : _0100_[7];
assign _0103_[8] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[8] : _0100_[8];
assign _0103_[9] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[9] : _0100_[9];
assign _0103_[10] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[10] : _0100_[10];
assign _0103_[11] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[11] : _0100_[11];
assign _0103_[12] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[12] : _0100_[12];
assign _0103_[13] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[13] : _0100_[13];
assign _0103_[14] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[14] : _0100_[14];
assign _0103_[15] = _0102_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:625" *) _0438_[15] : _0100_[15];
assign _0427_[0] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[0] : _0177_[0];
assign _0427_[1] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[1] : _0177_[1];
assign _0427_[2] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[2] : _0177_[2];
assign _0427_[3] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[3] : _0177_[3];
assign _0427_[4] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[4] : _0177_[4];
assign _0427_[5] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[5] : _0177_[5];
assign _0427_[6] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[6] : _0177_[6];
assign _0427_[7] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[7] : _0177_[7];
assign _0427_[8] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[8] : _0177_[8];
assign _0427_[9] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[9] : _0177_[9];
assign _0427_[10] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[10] : _0177_[10];
assign _0427_[11] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[11] : _0177_[11];
assign _0427_[12] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[12] : _0177_[12];
assign _0427_[13] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[13] : _0177_[13];
assign _0427_[14] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[14] : _0177_[14];
assign _0427_[15] = _0066_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:619" *) _0065_[15] : _0177_[15];
assign _0428_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[0];
assign _0428_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[1];
assign _0428_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[2];
assign _0428_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[3];
assign _0428_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[4];
assign _0428_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[5];
assign _0428_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[6];
assign _0428_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[7];
assign _0428_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[8];
assign _0428_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[9];
assign _0428_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[10];
assign _0428_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[11];
assign _0428_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[12];
assign _0428_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[13];
assign _0428_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[14];
assign _0428_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) 1'bx : _0427_[15];
assign _0429_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[0] : 1'bx;
assign _0429_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[1] : 1'bx;
assign _0429_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[2] : 1'bx;
assign _0429_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[3] : 1'bx;
assign _0429_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[4] : 1'bx;
assign _0429_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[5] : 1'bx;
assign _0429_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[6] : 1'bx;
assign _0429_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[7] : 1'bx;
assign _0429_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[8] : 1'bx;
assign _0429_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[9] : 1'bx;
assign _0429_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[10] : 1'bx;
assign _0429_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[11] : 1'bx;
assign _0429_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[12] : 1'bx;
assign _0429_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[13] : 1'bx;
assign _0429_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[14] : 1'bx;
assign _0429_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0428_[15] : 1'bx;
assign _0100_[0] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[0];
assign _0100_[1] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[1];
assign _0100_[2] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[2];
assign _0100_[3] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[3];
assign _0100_[4] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[4];
assign _0100_[5] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[5];
assign _0100_[6] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[6];
assign _0100_[7] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[7];
assign _0100_[8] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[8];
assign _0100_[9] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[9];
assign _0100_[10] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[10];
assign _0100_[11] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[11];
assign _0100_[12] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[12];
assign _0100_[13] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[13];
assign _0100_[14] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[14];
assign _0100_[15] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0429_[15];
assign _0137_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0122_[0] : _0138_[0];
assign _0137_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0122_[1] : 1'b0;
assign _0137_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0122_[2] : _0102_;
assign _0137_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0122_[3] : _0102_;
assign _0137_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0122_[4] : 1'b0;
assign _0097_ = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0066_ : _0102_;
assign _0098_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[0] : _0103_[0];
assign _0098_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[1] : _0103_[1];
assign _0098_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[2] : _0103_[2];
assign _0098_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[3] : _0103_[3];
assign _0098_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[4] : _0103_[4];
assign _0098_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[5] : _0103_[5];
assign _0098_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[6] : _0103_[6];
assign _0098_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[7] : _0103_[7];
assign _0098_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[8] : _0103_[8];
assign _0098_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[9] : _0103_[9];
assign _0098_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[10] : _0103_[10];
assign _0098_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[11] : _0103_[11];
assign _0098_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[12] : _0103_[12];
assign _0098_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[13] : _0103_[13];
assign _0098_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[14] : _0103_[14];
assign _0098_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:614" *) _0065_[15] : _0103_[15];
assign _0136_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0137_[0] : _0122_[0];
assign _0136_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0137_[1] : _0122_[1];
assign _0136_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0137_[2] : _0122_[2];
assign _0136_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0137_[3] : _0122_[3];
assign _0136_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0137_[4] : _0122_[4];
assign _0094_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0097_ : _0066_;
assign _0095_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[0] : _0065_[0];
assign _0095_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[1] : _0065_[1];
assign _0095_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[2] : _0065_[2];
assign _0095_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[3] : _0065_[3];
assign _0095_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[4] : _0065_[4];
assign _0095_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[5] : _0065_[5];
assign _0095_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[6] : _0065_[6];
assign _0095_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[7] : _0065_[7];
assign _0095_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[8] : _0065_[8];
assign _0095_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[9] : _0065_[9];
assign _0095_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[10] : _0065_[10];
assign _0095_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[11] : _0065_[11];
assign _0095_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[12] : _0065_[12];
assign _0095_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[13] : _0065_[13];
assign _0095_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[14] : _0065_[14];
assign _0095_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:612" *) _0098_[15] : _0065_[15];
assign _0135_[0] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0078_;
assign _0093_[0] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[0] : _0077_[0];
assign _0093_[1] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[1] : _0077_[1];
assign _0093_[2] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[2] : _0077_[2];
assign _0093_[3] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[3] : _0077_[3];
assign _0093_[4] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[4] : _0077_[4];
assign _0093_[5] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[5] : _0077_[5];
assign _0093_[6] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[6] : _0077_[6];
assign _0093_[7] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[7] : _0077_[7];
assign _0093_[8] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[8] : _0077_[8];
assign _0093_[9] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[9] : _0077_[9];
assign _0093_[10] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[10] : _0077_[10];
assign _0093_[11] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[11] : _0077_[11];
assign _0093_[12] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[12] : _0077_[12];
assign _0093_[13] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[13] : _0077_[13];
assign _0093_[14] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[14] : _0077_[14];
assign _0093_[15] = _0078_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:592" *) _0437_[15] : _0077_[15];
assign _0380_[0] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[0] : _0177_[0];
assign _0380_[1] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[1] : _0177_[1];
assign _0380_[2] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[2] : _0177_[2];
assign _0380_[3] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[3] : _0177_[3];
assign _0380_[4] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[4] : _0177_[4];
assign _0380_[5] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[5] : _0177_[5];
assign _0380_[6] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[6] : _0177_[6];
assign _0380_[7] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[7] : _0177_[7];
assign _0380_[8] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[8] : _0177_[8];
assign _0380_[9] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[9] : _0177_[9];
assign _0380_[10] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[10] : _0177_[10];
assign _0380_[11] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[11] : _0177_[11];
assign _0380_[12] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[12] : _0177_[12];
assign _0380_[13] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[13] : _0177_[13];
assign _0380_[14] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[14] : _0177_[14];
assign _0380_[15] = _0069_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:586" *) _0067_[15] : _0177_[15];
assign _0381_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[0];
assign _0381_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[1];
assign _0381_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[2];
assign _0381_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[3];
assign _0381_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[4];
assign _0381_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[5];
assign _0381_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[6];
assign _0381_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[7];
assign _0381_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[8];
assign _0381_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[9];
assign _0381_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[10];
assign _0381_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[11];
assign _0381_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[12];
assign _0381_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[13];
assign _0381_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[14];
assign _0381_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) 1'bx : _0380_[15];
assign _0382_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[0];
assign _0382_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[1];
assign _0382_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[2];
assign _0382_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[3];
assign _0382_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[4];
assign _0382_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[5];
assign _0382_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[6];
assign _0382_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[7];
assign _0382_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[8];
assign _0382_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[9];
assign _0382_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[10];
assign _0382_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[11];
assign _0382_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[12];
assign _0382_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[13];
assign _0382_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[14];
assign _0382_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) 1'bx : _0381_[15];
assign _0077_[0] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[0];
assign _0077_[1] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[1];
assign _0077_[2] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[2];
assign _0077_[3] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[3];
assign _0077_[4] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[4];
assign _0077_[5] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[5];
assign _0077_[6] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[6];
assign _0077_[7] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[7];
assign _0077_[8] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[8];
assign _0077_[9] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[9];
assign _0077_[10] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[10];
assign _0077_[11] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[11];
assign _0077_[12] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[12];
assign _0077_[13] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[13];
assign _0077_[14] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[14];
assign _0077_[15] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0382_[15];
assign _0134_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0123_[0] : _0135_[0];
assign _0134_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0123_[1] : 1'b0;
assign _0134_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0123_[2] : _0078_;
assign _0134_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0123_[3] : _0078_;
assign _0134_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0123_[4] : 1'b0;
assign _0074_ = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0069_ : _0078_;
assign _0075_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[0] : _0093_[0];
assign _0075_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[1] : _0093_[1];
assign _0075_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[2] : _0093_[2];
assign _0075_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[3] : _0093_[3];
assign _0075_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[4] : _0093_[4];
assign _0075_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[5] : _0093_[5];
assign _0075_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[6] : _0093_[6];
assign _0075_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[7] : _0093_[7];
assign _0075_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[8] : _0093_[8];
assign _0075_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[9] : _0093_[9];
assign _0075_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[10] : _0093_[10];
assign _0075_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[11] : _0093_[11];
assign _0075_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[12] : _0093_[12];
assign _0075_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[13] : _0093_[13];
assign _0075_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[14] : _0093_[14];
assign _0075_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:583" *) _0067_[15] : _0093_[15];
assign _0133_[0] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) 1'b0 : next_state[0];
assign _0133_[1] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) 1'b0 : next_state[1];
assign _0133_[2] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) 1'b1 : next_state[2];
assign _0133_[3] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) 1'b1 : next_state[3];
assign _0133_[4] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) 1'b0 : next_state[4];
assign _0072_[0] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[0] : _0070_[0];
assign _0072_[1] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[1] : _0070_[1];
assign _0072_[2] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[2] : _0070_[2];
assign _0072_[3] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[3] : _0070_[3];
assign _0072_[4] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[4] : _0070_[4];
assign _0072_[5] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[5] : _0070_[5];
assign _0072_[6] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[6] : _0070_[6];
assign _0072_[7] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[7] : _0070_[7];
assign _0072_[8] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[8] : _0070_[8];
assign _0072_[9] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[9] : _0070_[9];
assign _0072_[10] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[10] : _0070_[10];
assign _0072_[11] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[11] : _0070_[11];
assign _0072_[12] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[12] : _0070_[12];
assign _0072_[13] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[13] : _0070_[13];
assign _0072_[14] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[14] : _0070_[14];
assign _0072_[15] = _0378_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:571" *) _0436_[15] : _0070_[15];
assign _0070_[0] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[0];
assign _0070_[1] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[1];
assign _0070_[2] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[2];
assign _0070_[3] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[3];
assign _0070_[4] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[4];
assign _0070_[5] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[5];
assign _0070_[6] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[6];
assign _0070_[7] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[7];
assign _0070_[8] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[8];
assign _0070_[9] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[9];
assign _0070_[10] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[10];
assign _0070_[11] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[11];
assign _0070_[12] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[12];
assign _0070_[13] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[13];
assign _0070_[14] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[14];
assign _0070_[15] = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[15];
assign _0123_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) next_state[0] : _0133_[0];
assign _0123_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) next_state[1] : _0133_[1];
assign _0123_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) next_state[2] : _0133_[2];
assign _0123_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) next_state[3] : _0133_[3];
assign _0123_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) next_state[4] : _0133_[4];
assign _0067_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[0] : _0072_[0];
assign _0067_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[1] : _0072_[1];
assign _0067_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[2] : _0072_[2];
assign _0067_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[3] : _0072_[3];
assign _0067_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[4] : _0072_[4];
assign _0067_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[5] : _0072_[5];
assign _0067_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[6] : _0072_[6];
assign _0067_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[7] : _0072_[7];
assign _0067_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[8] : _0072_[8];
assign _0067_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[9] : _0072_[9];
assign _0067_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[10] : _0072_[10];
assign _0067_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[11] : _0072_[11];
assign _0067_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[12] : _0072_[12];
assign _0067_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[13] : _0072_[13];
assign _0067_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[14] : _0072_[14];
assign _0067_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:560" *) count[15] : _0072_[15];
assign _0069_ = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0387_;
assign _0122_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) next_state[0] : _0134_[0];
assign _0122_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) next_state[1] : _0134_[1];
assign _0122_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) next_state[2] : _0134_[2];
assign _0122_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) next_state[3] : _0134_[3];
assign _0122_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) next_state[4] : _0134_[4];
assign _0389_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) singl_data : _0074_;
assign _0066_ = _0347_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0389_;
assign _0065_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[0] : _0075_[0];
assign _0065_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[1] : _0075_[1];
assign _0065_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[2] : _0075_[2];
assign _0065_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[3] : _0075_[3];
assign _0065_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[4] : _0075_[4];
assign _0065_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[5] : _0075_[5];
assign _0065_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[6] : _0075_[6];
assign _0065_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[7] : _0075_[7];
assign _0065_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[8] : _0075_[8];
assign _0065_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[9] : _0075_[9];
assign _0065_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[10] : _0075_[10];
assign _0065_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[11] : _0075_[11];
assign _0065_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[12] : _0075_[12];
assign _0065_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[13] : _0075_[13];
assign _0065_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[14] : _0075_[14];
assign _0065_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:558" *) count[15] : _0075_[15];
assign _0154_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[0] : parameter_Block[0];
assign _0154_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[1] : parameter_Block[1];
assign _0154_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[2] : parameter_Block[2];
assign _0154_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[3] : parameter_Block[3];
assign _0154_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[4] : parameter_Block[4];
assign _0154_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[5] : parameter_Block[5];
assign _0154_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[6] : parameter_Block[6];
assign _0154_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[7] : parameter_Block[7];
assign _0154_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[8] : parameter_Block[8];
assign _0154_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[9] : parameter_Block[9];
assign _0154_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[10] : parameter_Block[10];
assign _0154_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[11] : parameter_Block[11];
assign _0154_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[12] : parameter_Block[12];
assign _0154_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[13] : parameter_Block[13];
assign _0154_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[14] : parameter_Block[14];
assign _0154_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[15] : parameter_Block[15];
assign _0154_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[16] : parameter_Block[16];
assign _0154_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[17] : parameter_Block[17];
assign _0154_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[18] : parameter_Block[18];
assign _0154_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[19] : parameter_Block[19];
assign _0154_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[20] : parameter_Block[20];
assign _0154_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[21] : parameter_Block[21];
assign _0154_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[22] : parameter_Block[22];
assign _0154_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[23] : parameter_Block[23];
assign _0154_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[24] : parameter_Block[24];
assign _0154_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[25] : parameter_Block[25];
assign _0154_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[26] : parameter_Block[26];
assign _0154_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[27] : parameter_Block[27];
assign _0154_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[28] : parameter_Block[28];
assign _0154_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[29] : parameter_Block[29];
assign _0154_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[30] : parameter_Block[30];
assign _0154_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:534" *) _0088_[31] : parameter_Block[31];
assign _0146_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[0] : _0088_[0];
assign _0146_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[1] : _0088_[1];
assign _0146_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[2] : _0088_[2];
assign _0146_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[3] : _0088_[3];
assign _0146_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[4] : _0088_[4];
assign _0146_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[5] : _0088_[5];
assign _0146_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[6] : _0088_[6];
assign _0146_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[7] : _0088_[7];
assign _0146_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[8] : _0088_[8];
assign _0146_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[9] : _0088_[9];
assign _0146_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[10] : _0088_[10];
assign _0146_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[11] : _0088_[11];
assign _0146_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[12] : _0088_[12];
assign _0146_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[13] : _0088_[13];
assign _0146_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[14] : _0088_[14];
assign _0146_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[15] : _0088_[15];
assign _0146_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[16] : _0088_[16];
assign _0146_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[17] : _0088_[17];
assign _0146_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[18] : _0088_[18];
assign _0146_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[19] : _0088_[19];
assign _0146_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[20] : _0088_[20];
assign _0146_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[21] : _0088_[21];
assign _0146_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[22] : _0088_[22];
assign _0146_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[23] : _0088_[23];
assign _0146_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[24] : _0088_[24];
assign _0146_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[25] : _0088_[25];
assign _0146_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[26] : _0088_[26];
assign _0146_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[27] : _0088_[27];
assign _0146_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[28] : _0088_[28];
assign _0146_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[29] : _0088_[29];
assign _0146_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[30] : _0088_[30];
assign _0146_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:532" *) _0154_[31] : _0088_[31];
assign _0131_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[0] : parameter_Block[0];
assign _0131_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[1] : parameter_Block[1];
assign _0131_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[2] : parameter_Block[2];
assign _0131_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[3] : parameter_Block[3];
assign _0131_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[4] : parameter_Block[4];
assign _0131_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[5] : parameter_Block[5];
assign _0131_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[6] : parameter_Block[6];
assign _0131_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[7] : parameter_Block[7];
assign _0131_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[8] : parameter_Block[8];
assign _0131_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[9] : parameter_Block[9];
assign _0131_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[10] : parameter_Block[10];
assign _0131_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[11] : parameter_Block[11];
assign _0131_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[12] : parameter_Block[12];
assign _0131_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[13] : parameter_Block[13];
assign _0131_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[14] : parameter_Block[14];
assign _0131_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[15] : parameter_Block[15];
assign _0131_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[16] : parameter_Block[16];
assign _0131_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[17] : parameter_Block[17];
assign _0131_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[18] : parameter_Block[18];
assign _0131_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[19] : parameter_Block[19];
assign _0131_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[20] : parameter_Block[20];
assign _0131_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[21] : parameter_Block[21];
assign _0131_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[22] : parameter_Block[22];
assign _0131_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[23] : parameter_Block[23];
assign _0131_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[24] : parameter_Block[24];
assign _0131_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[25] : parameter_Block[25];
assign _0131_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[26] : parameter_Block[26];
assign _0131_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[27] : parameter_Block[27];
assign _0131_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[28] : parameter_Block[28];
assign _0131_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[29] : parameter_Block[29];
assign _0131_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[30] : parameter_Block[30];
assign _0131_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:524" *) _0114_[31] : parameter_Block[31];
assign _0114_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[0] : parameter_Block[0];
assign _0114_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[1] : parameter_Block[1];
assign _0114_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[2] : parameter_Block[2];
assign _0114_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[3] : parameter_Block[3];
assign _0114_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[4] : parameter_Block[4];
assign _0114_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[5] : parameter_Block[5];
assign _0114_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[6] : parameter_Block[6];
assign _0114_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[7] : parameter_Block[7];
assign _0114_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[8] : parameter_Block[8];
assign _0114_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[9] : parameter_Block[9];
assign _0114_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[10] : parameter_Block[10];
assign _0114_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[11] : parameter_Block[11];
assign _0114_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[12] : parameter_Block[12];
assign _0114_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[13] : parameter_Block[13];
assign _0114_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[14] : parameter_Block[14];
assign _0114_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[15] : parameter_Block[15];
assign _0114_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[16] : parameter_Block[16];
assign _0114_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[17] : parameter_Block[17];
assign _0114_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[18] : parameter_Block[18];
assign _0114_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[19] : parameter_Block[19];
assign _0114_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[20] : parameter_Block[20];
assign _0114_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[21] : parameter_Block[21];
assign _0114_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[22] : parameter_Block[22];
assign _0114_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[23] : parameter_Block[23];
assign _0114_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[24] : parameter_Block[24];
assign _0114_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[25] : parameter_Block[25];
assign _0114_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[26] : parameter_Block[26];
assign _0114_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[27] : parameter_Block[27];
assign _0114_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[28] : parameter_Block[28];
assign _0114_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[29] : parameter_Block[29];
assign _0114_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[30] : parameter_Block[30];
assign _0114_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:517" *) readWrite[31] : parameter_Block[31];
assign _0088_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[0] : _0131_[0];
assign _0088_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[1] : _0131_[1];
assign _0088_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[2] : _0131_[2];
assign _0088_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[3] : _0131_[3];
assign _0088_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[4] : _0131_[4];
assign _0088_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[5] : _0131_[5];
assign _0088_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[6] : _0131_[6];
assign _0088_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[7] : _0131_[7];
assign _0088_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[8] : _0131_[8];
assign _0088_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[9] : _0131_[9];
assign _0088_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[10] : _0131_[10];
assign _0088_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[11] : _0131_[11];
assign _0088_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[12] : _0131_[12];
assign _0088_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[13] : _0131_[13];
assign _0088_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[14] : _0131_[14];
assign _0088_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[15] : _0131_[15];
assign _0088_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[16] : _0131_[16];
assign _0088_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[17] : _0131_[17];
assign _0088_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[18] : _0131_[18];
assign _0088_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[19] : _0131_[19];
assign _0088_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[20] : _0131_[20];
assign _0088_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[21] : _0131_[21];
assign _0088_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[22] : _0131_[22];
assign _0088_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[23] : _0131_[23];
assign _0088_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[24] : _0131_[24];
assign _0088_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[25] : _0131_[25];
assign _0088_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[26] : _0131_[26];
assign _0088_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[27] : _0131_[27];
assign _0088_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[28] : _0131_[28];
assign _0088_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[29] : _0131_[29];
assign _0088_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[30] : _0131_[30];
assign _0088_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:515" *) readWrite[31] : _0131_[31];
assign _0038_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[0] : parameter_Block2[0];
assign _0038_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[1] : parameter_Block2[1];
assign _0038_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[2] : parameter_Block2[2];
assign _0038_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[3] : parameter_Block2[3];
assign _0038_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[4] : parameter_Block2[4];
assign _0038_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[5] : parameter_Block2[5];
assign _0038_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[6] : parameter_Block2[6];
assign _0038_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[7] : parameter_Block2[7];
assign _0038_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[8] : parameter_Block2[8];
assign _0038_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[9] : parameter_Block2[9];
assign _0038_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[10] : parameter_Block2[10];
assign _0038_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[11] : parameter_Block2[11];
assign _0038_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[12] : parameter_Block2[12];
assign _0038_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[13] : parameter_Block2[13];
assign _0038_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[14] : parameter_Block2[14];
assign _0038_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[15] : parameter_Block2[15];
assign _0038_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[16] : parameter_Block2[16];
assign _0038_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[17] : parameter_Block2[17];
assign _0038_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[18] : parameter_Block2[18];
assign _0038_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[19] : parameter_Block2[19];
assign _0038_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[20] : parameter_Block2[20];
assign _0038_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[21] : parameter_Block2[21];
assign _0038_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[22] : parameter_Block2[22];
assign _0038_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[23] : parameter_Block2[23];
assign _0038_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[24] : parameter_Block2[24];
assign _0038_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[25] : parameter_Block2[25];
assign _0038_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[26] : parameter_Block2[26];
assign _0038_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[27] : parameter_Block2[27];
assign _0038_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[28] : parameter_Block2[28];
assign _0038_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[29] : parameter_Block2[29];
assign _0038_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[30] : parameter_Block2[30];
assign _0038_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[31] : parameter_Block2[31];
assign _0038_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[32] : parameter_Block2[32];
assign _0038_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[33] : parameter_Block2[33];
assign _0038_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[34] : parameter_Block2[34];
assign _0038_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[35] : parameter_Block2[35];
assign _0038_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[36] : parameter_Block2[36];
assign _0038_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[37] : parameter_Block2[37];
assign _0038_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[38] : parameter_Block2[38];
assign _0038_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[39] : parameter_Block2[39];
assign _0038_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[40] : parameter_Block2[40];
assign _0038_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[41] : parameter_Block2[41];
assign _0038_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[42] : parameter_Block2[42];
assign _0038_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[43] : parameter_Block2[43];
assign _0038_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[44] : parameter_Block2[44];
assign _0038_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[45] : parameter_Block2[45];
assign _0038_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[46] : parameter_Block2[46];
assign _0038_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[47] : parameter_Block2[47];
assign _0038_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[48] : parameter_Block2[48];
assign _0038_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[49] : parameter_Block2[49];
assign _0038_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[50] : parameter_Block2[50];
assign _0038_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[51] : parameter_Block2[51];
assign _0038_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[52] : parameter_Block2[52];
assign _0038_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[53] : parameter_Block2[53];
assign _0038_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[54] : parameter_Block2[54];
assign _0038_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[55] : parameter_Block2[55];
assign _0038_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[56] : parameter_Block2[56];
assign _0038_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[57] : parameter_Block2[57];
assign _0038_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[58] : parameter_Block2[58];
assign _0038_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[59] : parameter_Block2[59];
assign _0038_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[60] : parameter_Block2[60];
assign _0038_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[61] : parameter_Block2[61];
assign _0038_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[62] : parameter_Block2[62];
assign _0038_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:489" *) _0015_[63] : parameter_Block2[63];
assign _0034_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[0] : _0015_[0];
assign _0034_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[1] : _0015_[1];
assign _0034_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[2] : _0015_[2];
assign _0034_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[3] : _0015_[3];
assign _0034_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[4] : _0015_[4];
assign _0034_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[5] : _0015_[5];
assign _0034_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[6] : _0015_[6];
assign _0034_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[7] : _0015_[7];
assign _0034_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[8] : _0015_[8];
assign _0034_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[9] : _0015_[9];
assign _0034_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[10] : _0015_[10];
assign _0034_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[11] : _0015_[11];
assign _0034_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[12] : _0015_[12];
assign _0034_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[13] : _0015_[13];
assign _0034_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[14] : _0015_[14];
assign _0034_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[15] : _0015_[15];
assign _0034_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[16] : _0015_[16];
assign _0034_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[17] : _0015_[17];
assign _0034_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[18] : _0015_[18];
assign _0034_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[19] : _0015_[19];
assign _0034_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[20] : _0015_[20];
assign _0034_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[21] : _0015_[21];
assign _0034_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[22] : _0015_[22];
assign _0034_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[23] : _0015_[23];
assign _0034_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[24] : _0015_[24];
assign _0034_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[25] : _0015_[25];
assign _0034_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[26] : _0015_[26];
assign _0034_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[27] : _0015_[27];
assign _0034_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[28] : _0015_[28];
assign _0034_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[29] : _0015_[29];
assign _0034_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[30] : _0015_[30];
assign _0034_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[31] : _0015_[31];
assign _0034_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[32] : _0015_[32];
assign _0034_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[33] : _0015_[33];
assign _0034_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[34] : _0015_[34];
assign _0034_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[35] : _0015_[35];
assign _0034_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[36] : _0015_[36];
assign _0034_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[37] : _0015_[37];
assign _0034_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[38] : _0015_[38];
assign _0034_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[39] : _0015_[39];
assign _0034_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[40] : _0015_[40];
assign _0034_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[41] : _0015_[41];
assign _0034_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[42] : _0015_[42];
assign _0034_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[43] : _0015_[43];
assign _0034_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[44] : _0015_[44];
assign _0034_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[45] : _0015_[45];
assign _0034_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[46] : _0015_[46];
assign _0034_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[47] : _0015_[47];
assign _0034_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[48] : _0015_[48];
assign _0034_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[49] : _0015_[49];
assign _0034_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[50] : _0015_[50];
assign _0034_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[51] : _0015_[51];
assign _0034_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[52] : _0015_[52];
assign _0034_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[53] : _0015_[53];
assign _0034_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[54] : _0015_[54];
assign _0034_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[55] : _0015_[55];
assign _0034_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[56] : _0015_[56];
assign _0034_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[57] : _0015_[57];
assign _0034_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[58] : _0015_[58];
assign _0034_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[59] : _0015_[59];
assign _0034_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[60] : _0015_[60];
assign _0034_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[61] : _0015_[61];
assign _0034_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[62] : _0015_[62];
assign _0034_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:487" *) _0038_[63] : _0015_[63];
assign _0029_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[0] : parameter_Block2[0];
assign _0029_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[1] : parameter_Block2[1];
assign _0029_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[2] : parameter_Block2[2];
assign _0029_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[3] : parameter_Block2[3];
assign _0029_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[4] : parameter_Block2[4];
assign _0029_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[5] : parameter_Block2[5];
assign _0029_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[6] : parameter_Block2[6];
assign _0029_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[7] : parameter_Block2[7];
assign _0029_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[8] : parameter_Block2[8];
assign _0029_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[9] : parameter_Block2[9];
assign _0029_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[10] : parameter_Block2[10];
assign _0029_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[11] : parameter_Block2[11];
assign _0029_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[12] : parameter_Block2[12];
assign _0029_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[13] : parameter_Block2[13];
assign _0029_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[14] : parameter_Block2[14];
assign _0029_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[15] : parameter_Block2[15];
assign _0029_[16] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[16] : parameter_Block2[16];
assign _0029_[17] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[17] : parameter_Block2[17];
assign _0029_[18] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[18] : parameter_Block2[18];
assign _0029_[19] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[19] : parameter_Block2[19];
assign _0029_[20] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[20] : parameter_Block2[20];
assign _0029_[21] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[21] : parameter_Block2[21];
assign _0029_[22] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[22] : parameter_Block2[22];
assign _0029_[23] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[23] : parameter_Block2[23];
assign _0029_[24] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[24] : parameter_Block2[24];
assign _0029_[25] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[25] : parameter_Block2[25];
assign _0029_[26] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[26] : parameter_Block2[26];
assign _0029_[27] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[27] : parameter_Block2[27];
assign _0029_[28] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[28] : parameter_Block2[28];
assign _0029_[29] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[29] : parameter_Block2[29];
assign _0029_[30] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[30] : parameter_Block2[30];
assign _0029_[31] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[31] : parameter_Block2[31];
assign _0029_[32] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[32] : parameter_Block2[32];
assign _0029_[33] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[33] : parameter_Block2[33];
assign _0029_[34] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[34] : parameter_Block2[34];
assign _0029_[35] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[35] : parameter_Block2[35];
assign _0029_[36] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[36] : parameter_Block2[36];
assign _0029_[37] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[37] : parameter_Block2[37];
assign _0029_[38] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[38] : parameter_Block2[38];
assign _0029_[39] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[39] : parameter_Block2[39];
assign _0029_[40] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[40] : parameter_Block2[40];
assign _0029_[41] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[41] : parameter_Block2[41];
assign _0029_[42] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[42] : parameter_Block2[42];
assign _0029_[43] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[43] : parameter_Block2[43];
assign _0029_[44] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[44] : parameter_Block2[44];
assign _0029_[45] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[45] : parameter_Block2[45];
assign _0029_[46] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[46] : parameter_Block2[46];
assign _0029_[47] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[47] : parameter_Block2[47];
assign _0029_[48] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[48] : parameter_Block2[48];
assign _0029_[49] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[49] : parameter_Block2[49];
assign _0029_[50] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[50] : parameter_Block2[50];
assign _0029_[51] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[51] : parameter_Block2[51];
assign _0029_[52] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[52] : parameter_Block2[52];
assign _0029_[53] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[53] : parameter_Block2[53];
assign _0029_[54] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[54] : parameter_Block2[54];
assign _0029_[55] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[55] : parameter_Block2[55];
assign _0029_[56] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[56] : parameter_Block2[56];
assign _0029_[57] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[57] : parameter_Block2[57];
assign _0029_[58] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[58] : parameter_Block2[58];
assign _0029_[59] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[59] : parameter_Block2[59];
assign _0029_[60] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[60] : parameter_Block2[60];
assign _0029_[61] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[61] : parameter_Block2[61];
assign _0029_[62] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[62] : parameter_Block2[62];
assign _0029_[63] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:473" *) _0022_[63] : parameter_Block2[63];
assign _0022_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[0] : parameter_Block2[0];
assign _0022_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[1] : parameter_Block2[1];
assign _0022_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[2] : parameter_Block2[2];
assign _0022_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[3] : parameter_Block2[3];
assign _0022_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[4] : parameter_Block2[4];
assign _0022_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[5] : parameter_Block2[5];
assign _0022_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[6] : parameter_Block2[6];
assign _0022_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[7] : parameter_Block2[7];
assign _0022_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[8] : parameter_Block2[8];
assign _0022_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[9] : parameter_Block2[9];
assign _0022_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[10] : parameter_Block2[10];
assign _0022_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[11] : parameter_Block2[11];
assign _0022_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[12] : parameter_Block2[12];
assign _0022_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[13] : parameter_Block2[13];
assign _0022_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[14] : parameter_Block2[14];
assign _0022_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[15] : parameter_Block2[15];
assign _0022_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[16] : parameter_Block2[16];
assign _0022_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[17] : parameter_Block2[17];
assign _0022_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[18] : parameter_Block2[18];
assign _0022_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[19] : parameter_Block2[19];
assign _0022_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[20] : parameter_Block2[20];
assign _0022_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[21] : parameter_Block2[21];
assign _0022_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[22] : parameter_Block2[22];
assign _0022_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[23] : parameter_Block2[23];
assign _0022_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[24] : parameter_Block2[24];
assign _0022_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[25] : parameter_Block2[25];
assign _0022_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[26] : parameter_Block2[26];
assign _0022_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[27] : parameter_Block2[27];
assign _0022_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[28] : parameter_Block2[28];
assign _0022_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[29] : parameter_Block2[29];
assign _0022_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[30] : parameter_Block2[30];
assign _0022_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[31] : parameter_Block2[31];
assign _0022_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[32] : parameter_Block2[32];
assign _0022_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[33] : parameter_Block2[33];
assign _0022_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[34] : parameter_Block2[34];
assign _0022_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[35] : parameter_Block2[35];
assign _0022_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[36] : parameter_Block2[36];
assign _0022_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[37] : parameter_Block2[37];
assign _0022_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[38] : parameter_Block2[38];
assign _0022_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[39] : parameter_Block2[39];
assign _0022_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[40] : parameter_Block2[40];
assign _0022_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[41] : parameter_Block2[41];
assign _0022_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[42] : parameter_Block2[42];
assign _0022_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[43] : parameter_Block2[43];
assign _0022_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[44] : parameter_Block2[44];
assign _0022_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[45] : parameter_Block2[45];
assign _0022_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[46] : parameter_Block2[46];
assign _0022_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[47] : parameter_Block2[47];
assign _0022_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[48] : parameter_Block2[48];
assign _0022_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[49] : parameter_Block2[49];
assign _0022_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[50] : parameter_Block2[50];
assign _0022_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[51] : parameter_Block2[51];
assign _0022_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[52] : parameter_Block2[52];
assign _0022_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[53] : parameter_Block2[53];
assign _0022_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[54] : parameter_Block2[54];
assign _0022_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[55] : parameter_Block2[55];
assign _0022_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[56] : parameter_Block2[56];
assign _0022_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[57] : parameter_Block2[57];
assign _0022_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[58] : parameter_Block2[58];
assign _0022_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[59] : parameter_Block2[59];
assign _0022_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[60] : parameter_Block2[60];
assign _0022_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[61] : parameter_Block2[61];
assign _0022_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[62] : parameter_Block2[62];
assign _0022_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:463" *) address[63] : parameter_Block2[63];
assign _0015_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[0] : _0029_[0];
assign _0015_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[1] : _0029_[1];
assign _0015_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[2] : _0029_[2];
assign _0015_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[3] : _0029_[3];
assign _0015_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[4] : _0029_[4];
assign _0015_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[5] : _0029_[5];
assign _0015_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[6] : _0029_[6];
assign _0015_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[7] : _0029_[7];
assign _0015_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[8] : _0029_[8];
assign _0015_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[9] : _0029_[9];
assign _0015_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[10] : _0029_[10];
assign _0015_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[11] : _0029_[11];
assign _0015_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[12] : _0029_[12];
assign _0015_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[13] : _0029_[13];
assign _0015_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[14] : _0029_[14];
assign _0015_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[15] : _0029_[15];
assign _0015_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[16] : _0029_[16];
assign _0015_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[17] : _0029_[17];
assign _0015_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[18] : _0029_[18];
assign _0015_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[19] : _0029_[19];
assign _0015_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[20] : _0029_[20];
assign _0015_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[21] : _0029_[21];
assign _0015_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[22] : _0029_[22];
assign _0015_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[23] : _0029_[23];
assign _0015_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[24] : _0029_[24];
assign _0015_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[25] : _0029_[25];
assign _0015_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[26] : _0029_[26];
assign _0015_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[27] : _0029_[27];
assign _0015_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[28] : _0029_[28];
assign _0015_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[29] : _0029_[29];
assign _0015_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[30] : _0029_[30];
assign _0015_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[31] : _0029_[31];
assign _0015_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[32] : _0029_[32];
assign _0015_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[33] : _0029_[33];
assign _0015_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[34] : _0029_[34];
assign _0015_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[35] : _0029_[35];
assign _0015_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[36] : _0029_[36];
assign _0015_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[37] : _0029_[37];
assign _0015_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[38] : _0029_[38];
assign _0015_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[39] : _0029_[39];
assign _0015_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[40] : _0029_[40];
assign _0015_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[41] : _0029_[41];
assign _0015_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[42] : _0029_[42];
assign _0015_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[43] : _0029_[43];
assign _0015_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[44] : _0029_[44];
assign _0015_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[45] : _0029_[45];
assign _0015_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[46] : _0029_[46];
assign _0015_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[47] : _0029_[47];
assign _0015_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[48] : _0029_[48];
assign _0015_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[49] : _0029_[49];
assign _0015_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[50] : _0029_[50];
assign _0015_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[51] : _0029_[51];
assign _0015_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[52] : _0029_[52];
assign _0015_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[53] : _0029_[53];
assign _0015_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[54] : _0029_[54];
assign _0015_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[55] : _0029_[55];
assign _0015_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[56] : _0029_[56];
assign _0015_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[57] : _0029_[57];
assign _0015_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[58] : _0029_[58];
assign _0015_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[59] : _0029_[59];
assign _0015_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[60] : _0029_[60];
assign _0015_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[61] : _0029_[61];
assign _0015_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[62] : _0029_[62];
assign _0015_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:461" *) address[63] : _0029_[63];
assign _0063_[0] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[0] : _0061_[0];
assign _0063_[1] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[1] : _0061_[1];
assign _0063_[2] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[2] : _0061_[2];
assign _0063_[3] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[3] : _0061_[3];
assign _0063_[4] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[4] : _0061_[4];
assign _0063_[5] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[5] : _0061_[5];
assign _0063_[6] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[6] : _0061_[6];
assign _0063_[7] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[7] : _0061_[7];
assign _0063_[8] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[8] : _0061_[8];
assign _0063_[9] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[9] : _0061_[9];
assign _0063_[10] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[10] : _0061_[10];
assign _0063_[11] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[11] : _0061_[11];
assign _0063_[12] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[12] : _0061_[12];
assign _0063_[13] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[13] : _0061_[13];
assign _0063_[14] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[14] : _0061_[14];
assign _0063_[15] = _0064_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:437" *) _0435_[15] : _0061_[15];
assign _0392_[0] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[0] : _0177_[0];
assign _0392_[1] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[1] : _0177_[1];
assign _0392_[2] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[2] : _0177_[2];
assign _0392_[3] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[3] : _0177_[3];
assign _0392_[4] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[4] : _0177_[4];
assign _0392_[5] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[5] : _0177_[5];
assign _0392_[6] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[6] : _0177_[6];
assign _0392_[7] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[7] : _0177_[7];
assign _0392_[8] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[8] : _0177_[8];
assign _0392_[9] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[9] : _0177_[9];
assign _0392_[10] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[10] : _0177_[10];
assign _0392_[11] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[11] : _0177_[11];
assign _0392_[12] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[12] : _0177_[12];
assign _0392_[13] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[13] : _0177_[13];
assign _0392_[14] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[14] : _0177_[14];
assign _0392_[15] = _0041_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:431" *) _0035_[15] : _0177_[15];
assign _0393_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[0];
assign _0393_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[1];
assign _0393_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[2];
assign _0393_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[3];
assign _0393_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[4];
assign _0393_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[5];
assign _0393_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[6];
assign _0393_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[7];
assign _0393_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[8];
assign _0393_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[9];
assign _0393_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[10];
assign _0393_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[11];
assign _0393_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[12];
assign _0393_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[13];
assign _0393_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[14];
assign _0393_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) 1'bx : _0392_[15];
assign _0394_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[0] : 1'bx;
assign _0394_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[1] : 1'bx;
assign _0394_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[2] : 1'bx;
assign _0394_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[3] : 1'bx;
assign _0394_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[4] : 1'bx;
assign _0394_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[5] : 1'bx;
assign _0394_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[6] : 1'bx;
assign _0394_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[7] : 1'bx;
assign _0394_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[8] : 1'bx;
assign _0394_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[9] : 1'bx;
assign _0394_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[10] : 1'bx;
assign _0394_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[11] : 1'bx;
assign _0394_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[12] : 1'bx;
assign _0394_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[13] : 1'bx;
assign _0394_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[14] : 1'bx;
assign _0394_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0393_[15] : 1'bx;
assign _0061_[0] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[0];
assign _0061_[1] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[1];
assign _0061_[2] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[2];
assign _0061_[3] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[3];
assign _0061_[4] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[4];
assign _0061_[5] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[5];
assign _0061_[6] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[6];
assign _0061_[7] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[7];
assign _0061_[8] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[8];
assign _0061_[9] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[9];
assign _0061_[10] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[10];
assign _0061_[11] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[11];
assign _0061_[12] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[12];
assign _0061_[13] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[13];
assign _0061_[14] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[14];
assign _0061_[15] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0394_[15];
assign _0121_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0116_[0] : 1'b1;
assign _0121_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0116_[1] : _0064_;
assign _0121_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0116_[2] : 1'b0;
assign _0121_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0116_[3] : 1'b0;
assign _0121_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0116_[4] : _0064_;
assign _0060_ = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0041_ : _0064_;
assign _0058_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[0] : _0063_[0];
assign _0058_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[1] : _0063_[1];
assign _0058_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[2] : _0063_[2];
assign _0058_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[3] : _0063_[3];
assign _0058_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[4] : _0063_[4];
assign _0058_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[5] : _0063_[5];
assign _0058_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[6] : _0063_[6];
assign _0058_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[7] : _0063_[7];
assign _0058_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[8] : _0063_[8];
assign _0058_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[9] : _0063_[9];
assign _0058_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[10] : _0063_[10];
assign _0058_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[11] : _0063_[11];
assign _0058_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[12] : _0063_[12];
assign _0058_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[13] : _0063_[13];
assign _0058_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[14] : _0063_[14];
assign _0058_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:426" *) _0035_[15] : _0063_[15];
assign _0120_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0121_[0] : _0116_[0];
assign _0120_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0121_[1] : _0116_[1];
assign _0120_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0121_[2] : _0116_[2];
assign _0120_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0121_[3] : _0116_[3];
assign _0120_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0121_[4] : _0116_[4];
assign _0057_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0060_ : _0041_;
assign _0055_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[0] : _0035_[0];
assign _0055_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[1] : _0035_[1];
assign _0055_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[2] : _0035_[2];
assign _0055_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[3] : _0035_[3];
assign _0055_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[4] : _0035_[4];
assign _0055_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[5] : _0035_[5];
assign _0055_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[6] : _0035_[6];
assign _0055_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[7] : _0035_[7];
assign _0055_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[8] : _0035_[8];
assign _0055_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[9] : _0035_[9];
assign _0055_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[10] : _0035_[10];
assign _0055_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[11] : _0035_[11];
assign _0055_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[12] : _0035_[12];
assign _0055_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[13] : _0035_[13];
assign _0055_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[14] : _0035_[14];
assign _0055_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:424" *) _0058_[15] : _0035_[15];
assign _0052_[0] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[0] : _0050_[0];
assign _0052_[1] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[1] : _0050_[1];
assign _0052_[2] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[2] : _0050_[2];
assign _0052_[3] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[3] : _0050_[3];
assign _0052_[4] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[4] : _0050_[4];
assign _0052_[5] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[5] : _0050_[5];
assign _0052_[6] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[6] : _0050_[6];
assign _0052_[7] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[7] : _0050_[7];
assign _0052_[8] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[8] : _0050_[8];
assign _0052_[9] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[9] : _0050_[9];
assign _0052_[10] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[10] : _0050_[10];
assign _0052_[11] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[11] : _0050_[11];
assign _0052_[12] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[12] : _0050_[12];
assign _0052_[13] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[13] : _0050_[13];
assign _0052_[14] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[14] : _0050_[14];
assign _0052_[15] = _0054_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:404" *) _0434_[15] : _0050_[15];
assign _0396_[0] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[0] : _0177_[0];
assign _0396_[1] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[1] : _0177_[1];
assign _0396_[2] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[2] : _0177_[2];
assign _0396_[3] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[3] : _0177_[3];
assign _0396_[4] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[4] : _0177_[4];
assign _0396_[5] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[5] : _0177_[5];
assign _0396_[6] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[6] : _0177_[6];
assign _0396_[7] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[7] : _0177_[7];
assign _0396_[8] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[8] : _0177_[8];
assign _0396_[9] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[9] : _0177_[9];
assign _0396_[10] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[10] : _0177_[10];
assign _0396_[11] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[11] : _0177_[11];
assign _0396_[12] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[12] : _0177_[12];
assign _0396_[13] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[13] : _0177_[13];
assign _0396_[14] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[14] : _0177_[14];
assign _0396_[15] = _0044_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:398" *) _0039_[15] : _0177_[15];
assign _0397_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[0];
assign _0397_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[1];
assign _0397_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[2];
assign _0397_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[3];
assign _0397_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[4];
assign _0397_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[5];
assign _0397_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[6];
assign _0397_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[7];
assign _0397_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[8];
assign _0397_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[9];
assign _0397_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[10];
assign _0397_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[11];
assign _0397_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[12];
assign _0397_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[13];
assign _0397_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[14];
assign _0397_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) 1'bx : _0396_[15];
assign _0398_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[0];
assign _0398_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[1];
assign _0398_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[2];
assign _0398_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[3];
assign _0398_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[4];
assign _0398_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[5];
assign _0398_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[6];
assign _0398_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[7];
assign _0398_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[8];
assign _0398_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[9];
assign _0398_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[10];
assign _0398_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[11];
assign _0398_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[12];
assign _0398_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[13];
assign _0398_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[14];
assign _0398_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0397_[15];
assign _0050_[0] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[0];
assign _0050_[1] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[1];
assign _0050_[2] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[2];
assign _0050_[3] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[3];
assign _0050_[4] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[4];
assign _0050_[5] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[5];
assign _0050_[6] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[6];
assign _0050_[7] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[7];
assign _0050_[8] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[8];
assign _0050_[9] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[9];
assign _0050_[10] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[10];
assign _0050_[11] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[11];
assign _0050_[12] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[12];
assign _0050_[13] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[13];
assign _0050_[14] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[14];
assign _0050_[15] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0398_[15];
assign _0119_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0117_[0] : 1'b1;
assign _0119_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0117_[1] : _0054_;
assign _0119_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0117_[2] : 1'b0;
assign _0119_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0117_[3] : 1'b0;
assign _0119_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0117_[4] : _0054_;
assign _0049_ = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0044_ : _0054_;
assign _0047_[0] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[0] : _0052_[0];
assign _0047_[1] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[1] : _0052_[1];
assign _0047_[2] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[2] : _0052_[2];
assign _0047_[3] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[3] : _0052_[3];
assign _0047_[4] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[4] : _0052_[4];
assign _0047_[5] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[5] : _0052_[5];
assign _0047_[6] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[6] : _0052_[6];
assign _0047_[7] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[7] : _0052_[7];
assign _0047_[8] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[8] : _0052_[8];
assign _0047_[9] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[9] : _0052_[9];
assign _0047_[10] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[10] : _0052_[10];
assign _0047_[11] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[11] : _0052_[11];
assign _0047_[12] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[12] : _0052_[12];
assign _0047_[13] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[13] : _0052_[13];
assign _0047_[14] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[14] : _0052_[14];
assign _0047_[15] = _0372_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:395" *) _0039_[15] : _0052_[15];
assign _0118_[0] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) 1'b1 : next_state[0];
assign _0118_[1] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) 1'b1 : next_state[1];
assign _0118_[2] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) 1'b0 : next_state[2];
assign _0118_[3] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) 1'b0 : next_state[3];
assign _0118_[4] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) 1'b1 : next_state[4];
assign _0045_[0] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[0] : _0042_[0];
assign _0045_[1] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[1] : _0042_[1];
assign _0045_[2] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[2] : _0042_[2];
assign _0045_[3] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[3] : _0042_[3];
assign _0045_[4] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[4] : _0042_[4];
assign _0045_[5] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[5] : _0042_[5];
assign _0045_[6] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[6] : _0042_[6];
assign _0045_[7] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[7] : _0042_[7];
assign _0045_[8] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[8] : _0042_[8];
assign _0045_[9] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[9] : _0042_[9];
assign _0045_[10] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[10] : _0042_[10];
assign _0045_[11] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[11] : _0042_[11];
assign _0045_[12] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[12] : _0042_[12];
assign _0045_[13] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[13] : _0042_[13];
assign _0045_[14] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[14] : _0042_[14];
assign _0045_[15] = _0377_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:383" *) _0433_[15] : _0042_[15];
assign _0383_[0] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[0] : _0177_[0];
assign _0383_[1] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[1] : _0177_[1];
assign _0383_[2] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[2] : _0177_[2];
assign _0383_[3] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[3] : _0177_[3];
assign _0383_[4] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[4] : _0177_[4];
assign _0383_[5] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[5] : _0177_[5];
assign _0383_[6] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[6] : _0177_[6];
assign _0383_[7] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[7] : _0177_[7];
assign _0383_[8] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[8] : _0177_[8];
assign _0383_[9] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[9] : _0177_[9];
assign _0383_[10] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[10] : _0177_[10];
assign _0383_[11] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[11] : _0177_[11];
assign _0383_[12] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[12] : _0177_[12];
assign _0383_[13] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[13] : _0177_[13];
assign _0383_[14] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[14] : _0177_[14];
assign _0383_[15] = singl_data ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:377" *) count[15] : _0177_[15];
assign _0384_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[0];
assign _0384_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[1];
assign _0384_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[2];
assign _0384_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[3];
assign _0384_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[4];
assign _0384_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[5];
assign _0384_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[6];
assign _0384_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[7];
assign _0384_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[8];
assign _0384_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[9];
assign _0384_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[10];
assign _0384_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[11];
assign _0384_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[12];
assign _0384_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[13];
assign _0384_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[14];
assign _0384_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) 1'bx : _0383_[15];
assign _0385_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[0];
assign _0385_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[1];
assign _0385_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[2];
assign _0385_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[3];
assign _0385_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[4];
assign _0385_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[5];
assign _0385_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[6];
assign _0385_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[7];
assign _0385_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[8];
assign _0385_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[9];
assign _0385_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[10];
assign _0385_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[11];
assign _0385_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[12];
assign _0385_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[13];
assign _0385_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[14];
assign _0385_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0384_[15];
assign _0042_[0] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[0];
assign _0042_[1] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[1];
assign _0042_[2] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[2];
assign _0042_[3] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[3];
assign _0042_[4] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[4];
assign _0042_[5] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[5];
assign _0042_[6] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[6];
assign _0042_[7] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[7];
assign _0042_[8] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[8];
assign _0042_[9] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[9];
assign _0042_[10] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[10];
assign _0042_[11] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[11];
assign _0042_[12] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[12];
assign _0042_[13] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[13];
assign _0042_[14] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[14];
assign _0042_[15] = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0385_[15];
assign _0117_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) next_state[0] : _0118_[0];
assign _0117_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) next_state[1] : _0118_[1];
assign _0117_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) next_state[2] : _0118_[2];
assign _0117_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) next_state[3] : _0118_[3];
assign _0117_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) next_state[4] : _0118_[4];
assign _0039_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[0] : _0045_[0];
assign _0039_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[1] : _0045_[1];
assign _0039_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[2] : _0045_[2];
assign _0039_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[3] : _0045_[3];
assign _0039_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[4] : _0045_[4];
assign _0039_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[5] : _0045_[5];
assign _0039_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[6] : _0045_[6];
assign _0039_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[7] : _0045_[7];
assign _0039_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[8] : _0045_[8];
assign _0039_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[9] : _0045_[9];
assign _0039_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[10] : _0045_[10];
assign _0039_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[11] : _0045_[11];
assign _0039_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[12] : _0045_[12];
assign _0039_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[13] : _0045_[13];
assign _0039_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[14] : _0045_[14];
assign _0039_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) count[15] : _0045_[15];
assign _0386_ = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:374" *) singl_data : 1'b1;
assign _0387_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) 1'bx : _0386_;
assign _0044_ = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0387_;
assign _0116_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) next_state[0] : _0119_[0];
assign _0116_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) next_state[1] : _0119_[1];
assign _0116_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) next_state[2] : _0119_[2];
assign _0116_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) next_state[3] : _0119_[3];
assign _0116_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) next_state[4] : _0119_[4];
assign _0399_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) singl_data : _0049_;
assign _0041_ = _0348_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0399_;
assign _0035_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[0] : _0047_[0];
assign _0035_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[1] : _0047_[1];
assign _0035_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[2] : _0047_[2];
assign _0035_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[3] : _0047_[3];
assign _0035_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[4] : _0047_[4];
assign _0035_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[5] : _0047_[5];
assign _0035_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[6] : _0047_[6];
assign _0035_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[7] : _0047_[7];
assign _0035_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[8] : _0047_[8];
assign _0035_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[9] : _0047_[9];
assign _0035_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[10] : _0047_[10];
assign _0035_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[11] : _0047_[11];
assign _0035_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[12] : _0047_[12];
assign _0035_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[13] : _0047_[13];
assign _0035_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[14] : _0047_[14];
assign _0035_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:372" *) count[15] : _0047_[15];
assign _0107_[0] = _0325_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0106_[0] : 1'b0;
assign _0107_[2] = _0325_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:346" *) _0106_[2] : 1'b1;
assign _0106_[2] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:341" *) _0106_[0];
assign _0031_[0] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[0] : parameter_Block[0];
assign _0031_[1] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[1] : parameter_Block[1];
assign _0031_[2] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[2] : parameter_Block[2];
assign _0031_[3] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[3] : parameter_Block[3];
assign _0031_[4] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[4] : parameter_Block[4];
assign _0031_[5] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[5] : parameter_Block[5];
assign _0031_[6] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[6] : parameter_Block[6];
assign _0031_[7] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[7] : parameter_Block[7];
assign _0031_[8] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[8] : parameter_Block[8];
assign _0031_[9] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[9] : parameter_Block[9];
assign _0031_[10] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[10] : parameter_Block[10];
assign _0031_[11] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[11] : parameter_Block[11];
assign _0031_[12] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[12] : parameter_Block[12];
assign _0031_[13] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[13] : parameter_Block[13];
assign _0031_[14] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[14] : parameter_Block[14];
assign _0031_[15] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[15] : parameter_Block[15];
assign _0031_[16] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[16] : parameter_Block[16];
assign _0031_[17] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[17] : parameter_Block[17];
assign _0031_[18] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[18] : parameter_Block[18];
assign _0031_[19] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[19] : parameter_Block[19];
assign _0031_[20] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[20] : parameter_Block[20];
assign _0031_[21] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[21] : parameter_Block[21];
assign _0031_[22] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[22] : parameter_Block[22];
assign _0031_[23] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[23] : parameter_Block[23];
assign _0031_[24] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[24] : parameter_Block[24];
assign _0031_[25] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[25] : parameter_Block[25];
assign _0031_[26] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[26] : parameter_Block[26];
assign _0031_[27] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[27] : parameter_Block[27];
assign _0031_[28] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[28] : parameter_Block[28];
assign _0031_[29] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[29] : parameter_Block[29];
assign _0031_[30] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[30] : parameter_Block[30];
assign _0031_[31] = _0376_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:336" *) _0081_[31] : parameter_Block[31];
assign _0030_[0] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[0] : parameter_Block[0];
assign _0030_[1] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[1] : parameter_Block[1];
assign _0030_[2] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[2] : parameter_Block[2];
assign _0030_[3] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[3] : parameter_Block[3];
assign _0030_[4] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[4] : parameter_Block[4];
assign _0030_[5] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[5] : parameter_Block[5];
assign _0030_[6] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[6] : parameter_Block[6];
assign _0030_[7] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[7] : parameter_Block[7];
assign _0030_[8] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[8] : parameter_Block[8];
assign _0030_[9] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[9] : parameter_Block[9];
assign _0030_[10] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[10] : parameter_Block[10];
assign _0030_[11] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[11] : parameter_Block[11];
assign _0030_[12] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[12] : parameter_Block[12];
assign _0030_[13] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[13] : parameter_Block[13];
assign _0030_[14] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[14] : parameter_Block[14];
assign _0030_[15] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[15] : parameter_Block[15];
assign _0030_[16] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[16] : parameter_Block[16];
assign _0030_[17] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[17] : parameter_Block[17];
assign _0030_[18] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[18] : parameter_Block[18];
assign _0030_[19] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[19] : parameter_Block[19];
assign _0030_[20] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[20] : parameter_Block[20];
assign _0030_[21] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[21] : parameter_Block[21];
assign _0030_[22] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[22] : parameter_Block[22];
assign _0030_[23] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[23] : parameter_Block[23];
assign _0030_[24] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[24] : parameter_Block[24];
assign _0030_[25] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[25] : parameter_Block[25];
assign _0030_[26] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[26] : parameter_Block[26];
assign _0030_[27] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[27] : parameter_Block[27];
assign _0030_[28] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[28] : parameter_Block[28];
assign _0030_[29] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[29] : parameter_Block[29];
assign _0030_[30] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[30] : parameter_Block[30];
assign _0030_[31] = _0375_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:331" *) _0080_[31] : parameter_Block[31];
assign _0032_[0] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0340_[0] : _0025_[0];
assign _0032_[1] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[1] : _0025_[1];
assign _0032_[2] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[2] : _0025_[2];
assign _0032_[3] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[3] : _0025_[3];
assign _0032_[4] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[4] : _0025_[4];
assign _0032_[5] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[5] : _0025_[5];
assign _0032_[6] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[6] : _0025_[6];
assign _0032_[7] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[7] : _0025_[7];
assign _0032_[8] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[8] : _0025_[8];
assign _0032_[9] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[9] : _0025_[9];
assign _0032_[10] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[10] : _0025_[10];
assign _0032_[11] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[11] : _0025_[11];
assign _0032_[12] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[12] : _0025_[12];
assign _0032_[13] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[13] : _0025_[13];
assign _0032_[14] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[14] : _0025_[14];
assign _0032_[15] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0432_[15] : _0025_[15];
assign _0105_[0] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0107_[0] : 1'b1;
assign _0105_[2] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0107_[2] : 1'b0;
assign _0024_[0] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[0] : _0081_[0];
assign _0024_[1] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[1] : _0081_[1];
assign _0024_[2] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[2] : _0081_[2];
assign _0024_[3] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[3] : _0081_[3];
assign _0024_[4] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[4] : _0081_[4];
assign _0024_[5] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[5] : _0081_[5];
assign _0024_[6] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[6] : _0081_[6];
assign _0024_[7] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[7] : _0081_[7];
assign _0024_[8] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[8] : _0081_[8];
assign _0024_[9] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[9] : _0081_[9];
assign _0024_[10] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[10] : _0081_[10];
assign _0024_[11] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[11] : _0081_[11];
assign _0024_[12] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[12] : _0081_[12];
assign _0024_[13] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[13] : _0081_[13];
assign _0024_[14] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[14] : _0081_[14];
assign _0024_[15] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[15] : _0081_[15];
assign _0024_[16] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[16] : _0081_[16];
assign _0024_[17] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[17] : _0081_[17];
assign _0024_[18] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[18] : _0081_[18];
assign _0024_[19] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[19] : _0081_[19];
assign _0024_[20] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[20] : _0081_[20];
assign _0024_[21] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[21] : _0081_[21];
assign _0024_[22] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[22] : _0081_[22];
assign _0024_[23] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[23] : _0081_[23];
assign _0024_[24] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[24] : _0081_[24];
assign _0024_[25] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[25] : _0081_[25];
assign _0024_[26] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[26] : _0081_[26];
assign _0024_[27] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[27] : _0081_[27];
assign _0024_[28] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[28] : _0081_[28];
assign _0024_[29] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[29] : _0081_[29];
assign _0024_[30] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[30] : _0081_[30];
assign _0024_[31] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0031_[31] : _0081_[31];
assign _0023_[0] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[0] : _0080_[0];
assign _0023_[1] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[1] : _0080_[1];
assign _0023_[2] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[2] : _0080_[2];
assign _0023_[3] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[3] : _0080_[3];
assign _0023_[4] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[4] : _0080_[4];
assign _0023_[5] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[5] : _0080_[5];
assign _0023_[6] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[6] : _0080_[6];
assign _0023_[7] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[7] : _0080_[7];
assign _0023_[8] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[8] : _0080_[8];
assign _0023_[9] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[9] : _0080_[9];
assign _0023_[10] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[10] : _0080_[10];
assign _0023_[11] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[11] : _0080_[11];
assign _0023_[12] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[12] : _0080_[12];
assign _0023_[13] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[13] : _0080_[13];
assign _0023_[14] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[14] : _0080_[14];
assign _0023_[15] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[15] : _0080_[15];
assign _0023_[16] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[16] : _0080_[16];
assign _0023_[17] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[17] : _0080_[17];
assign _0023_[18] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[18] : _0080_[18];
assign _0023_[19] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[19] : _0080_[19];
assign _0023_[20] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[20] : _0080_[20];
assign _0023_[21] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[21] : _0080_[21];
assign _0023_[22] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[22] : _0080_[22];
assign _0023_[23] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[23] : _0080_[23];
assign _0023_[24] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[24] : _0080_[24];
assign _0023_[25] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[25] : _0080_[25];
assign _0023_[26] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[26] : _0080_[26];
assign _0023_[27] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[27] : _0080_[27];
assign _0023_[28] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[28] : _0080_[28];
assign _0023_[29] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[29] : _0080_[29];
assign _0023_[30] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[30] : _0080_[30];
assign _0023_[31] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0030_[31] : _0080_[31];
assign _0170_[0] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[0] : _0081_[0];
assign _0170_[1] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[1] : _0081_[1];
assign _0170_[2] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[2] : _0081_[2];
assign _0170_[3] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[3] : _0081_[3];
assign _0170_[4] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[4] : _0081_[4];
assign _0170_[5] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[5] : _0081_[5];
assign _0170_[6] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[6] : _0081_[6];
assign _0170_[7] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[7] : _0081_[7];
assign _0170_[8] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[8] : _0081_[8];
assign _0170_[9] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[9] : _0081_[9];
assign _0170_[10] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[10] : _0081_[10];
assign _0170_[11] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[11] : _0081_[11];
assign _0170_[12] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[12] : _0081_[12];
assign _0170_[13] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[13] : _0081_[13];
assign _0170_[14] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[14] : _0081_[14];
assign _0170_[15] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[15] : _0081_[15];
assign _0170_[16] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[16] : _0081_[16];
assign _0170_[17] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[17] : _0081_[17];
assign _0170_[18] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[18] : _0081_[18];
assign _0170_[19] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[19] : _0081_[19];
assign _0170_[20] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[20] : _0081_[20];
assign _0170_[21] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[21] : _0081_[21];
assign _0170_[22] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[22] : _0081_[22];
assign _0170_[23] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[23] : _0081_[23];
assign _0170_[24] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[24] : _0081_[24];
assign _0170_[25] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[25] : _0081_[25];
assign _0170_[26] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[26] : _0081_[26];
assign _0170_[27] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[27] : _0081_[27];
assign _0170_[28] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[28] : _0081_[28];
assign _0170_[29] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[29] : _0081_[29];
assign _0170_[30] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[30] : _0081_[30];
assign _0170_[31] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[31] : _0081_[31];
assign _0170_[32] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[32] : _0080_[0];
assign _0170_[33] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[33] : _0080_[1];
assign _0170_[34] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[34] : _0080_[2];
assign _0170_[35] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[35] : _0080_[3];
assign _0170_[36] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[36] : _0080_[4];
assign _0170_[37] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[37] : _0080_[5];
assign _0170_[38] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[38] : _0080_[6];
assign _0170_[39] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[39] : _0080_[7];
assign _0170_[40] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[40] : _0080_[8];
assign _0170_[41] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[41] : _0080_[9];
assign _0170_[42] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[42] : _0080_[10];
assign _0170_[43] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[43] : _0080_[11];
assign _0170_[44] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[44] : _0080_[12];
assign _0170_[45] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[45] : _0080_[13];
assign _0170_[46] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[46] : _0080_[14];
assign _0170_[47] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[47] : _0080_[15];
assign _0170_[48] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[48] : _0080_[16];
assign _0170_[49] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[49] : _0080_[17];
assign _0170_[50] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[50] : _0080_[18];
assign _0170_[51] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[51] : _0080_[19];
assign _0170_[52] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[52] : _0080_[20];
assign _0170_[53] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[53] : _0080_[21];
assign _0170_[54] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[54] : _0080_[22];
assign _0170_[55] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[55] : _0080_[23];
assign _0170_[56] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[56] : _0080_[24];
assign _0170_[57] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[57] : _0080_[25];
assign _0170_[58] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[58] : _0080_[26];
assign _0170_[59] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[59] : _0080_[27];
assign _0170_[60] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[60] : _0080_[28];
assign _0170_[61] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[61] : _0080_[29];
assign _0170_[62] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[62] : _0080_[30];
assign _0170_[63] = _0037_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:329" *) _0079_[63] : _0080_[31];
assign _0401_[0] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[0] : 1'b1;
assign _0401_[1] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[1] : 1'b1;
assign _0401_[2] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[2] : 1'b1;
assign _0401_[3] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[3] : 1'b0;
assign _0401_[4] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[4] : 1'b0;
assign _0401_[5] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[5] : 1'b0;
assign _0401_[6] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[6] : 1'b0;
assign _0401_[7] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[7] : 1'b0;
assign _0401_[8] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[8] : 1'b0;
assign _0401_[9] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[9] : 1'b0;
assign _0401_[10] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[10] : 1'b0;
assign _0401_[11] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[11] : 1'b0;
assign _0401_[12] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[12] : 1'b0;
assign _0401_[13] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[13] : 1'b0;
assign _0401_[14] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[14] : 1'b0;
assign _0401_[15] = _0115_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:324" *) _0084_[15] : 1'b0;
assign _0402_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[0];
assign _0402_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[1];
assign _0402_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[2];
assign _0402_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[3];
assign _0402_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[4];
assign _0402_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[5];
assign _0402_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[6];
assign _0402_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[7];
assign _0402_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[8];
assign _0402_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[9];
assign _0402_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[10];
assign _0402_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[11];
assign _0402_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[12];
assign _0402_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[13];
assign _0402_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[14];
assign _0402_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) 1'bx : _0401_[15];
assign _0403_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[0] : 1'bx;
assign _0403_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[1] : 1'bx;
assign _0403_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[2] : 1'bx;
assign _0403_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[3] : 1'bx;
assign _0403_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[4] : 1'bx;
assign _0403_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[5] : 1'bx;
assign _0403_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[6] : 1'bx;
assign _0403_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[7] : 1'bx;
assign _0403_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[8] : 1'bx;
assign _0403_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[9] : 1'bx;
assign _0403_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[10] : 1'bx;
assign _0403_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[11] : 1'bx;
assign _0403_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[12] : 1'bx;
assign _0403_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[13] : 1'bx;
assign _0403_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[14] : 1'bx;
assign _0403_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0402_[15] : 1'bx;
assign _0025_[0] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[0];
assign _0025_[1] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[1];
assign _0025_[2] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[2];
assign _0025_[3] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[3];
assign _0025_[4] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[4];
assign _0025_[5] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[5];
assign _0025_[6] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[6];
assign _0025_[7] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[7];
assign _0025_[8] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[8];
assign _0025_[9] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[9];
assign _0025_[10] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[10];
assign _0025_[11] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[11];
assign _0025_[12] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[12];
assign _0025_[13] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[13];
assign _0025_[14] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[14];
assign _0025_[15] = _0349_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'bx : _0403_[15];
assign _0104_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0056_[0] : _0105_[0];
assign _0104_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0056_[1] : _0105_[2];
assign _0104_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0056_[2] : _0105_[2];
assign _0104_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0056_[3] : 1'b0;
assign _0104_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0056_[4] : 1'b0;
assign _0164_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[0] : _0170_[0];
assign _0164_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[1] : _0170_[1];
assign _0164_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[2] : _0170_[2];
assign _0164_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[3] : _0170_[3];
assign _0164_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[4] : _0170_[4];
assign _0164_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[5] : _0170_[5];
assign _0164_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[6] : _0170_[6];
assign _0164_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[7] : _0170_[7];
assign _0164_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[8] : _0170_[8];
assign _0164_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[9] : _0170_[9];
assign _0164_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[10] : _0170_[10];
assign _0164_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[11] : _0170_[11];
assign _0164_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[12] : _0170_[12];
assign _0164_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[13] : _0170_[13];
assign _0164_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[14] : _0170_[14];
assign _0164_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[15] : _0170_[15];
assign _0164_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[16] : _0170_[16];
assign _0164_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[17] : _0170_[17];
assign _0164_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[18] : _0170_[18];
assign _0164_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[19] : _0170_[19];
assign _0164_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[20] : _0170_[20];
assign _0164_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[21] : _0170_[21];
assign _0164_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[22] : _0170_[22];
assign _0164_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[23] : _0170_[23];
assign _0164_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[24] : _0170_[24];
assign _0164_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[25] : _0170_[25];
assign _0164_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[26] : _0170_[26];
assign _0164_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[27] : _0170_[27];
assign _0164_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[28] : _0170_[28];
assign _0164_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[29] : _0170_[29];
assign _0164_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[30] : _0170_[30];
assign _0164_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[31] : _0170_[31];
assign _0164_[32] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[32] : _0170_[32];
assign _0164_[33] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[33] : _0170_[33];
assign _0164_[34] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[34] : _0170_[34];
assign _0164_[35] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[35] : _0170_[35];
assign _0164_[36] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[36] : _0170_[36];
assign _0164_[37] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[37] : _0170_[37];
assign _0164_[38] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[38] : _0170_[38];
assign _0164_[39] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[39] : _0170_[39];
assign _0164_[40] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[40] : _0170_[40];
assign _0164_[41] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[41] : _0170_[41];
assign _0164_[42] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[42] : _0170_[42];
assign _0164_[43] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[43] : _0170_[43];
assign _0164_[44] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[44] : _0170_[44];
assign _0164_[45] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[45] : _0170_[45];
assign _0164_[46] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[46] : _0170_[46];
assign _0164_[47] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[47] : _0170_[47];
assign _0164_[48] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[48] : _0170_[48];
assign _0164_[49] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[49] : _0170_[49];
assign _0164_[50] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[50] : _0170_[50];
assign _0164_[51] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[51] : _0170_[51];
assign _0164_[52] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[52] : _0170_[52];
assign _0164_[53] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[53] : _0170_[53];
assign _0164_[54] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[54] : _0170_[54];
assign _0164_[55] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[55] : _0170_[55];
assign _0164_[56] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[56] : _0170_[56];
assign _0164_[57] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[57] : _0170_[57];
assign _0164_[58] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[58] : _0170_[58];
assign _0164_[59] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[59] : _0170_[59];
assign _0164_[60] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[60] : _0170_[60];
assign _0164_[61] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[61] : _0170_[61];
assign _0164_[62] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[62] : _0170_[62];
assign _0164_[63] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0079_[63] : _0170_[63];
assign _0028_ = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0115_ : _0037_;
assign _0017_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[0] : _0024_[0];
assign _0017_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[1] : _0024_[1];
assign _0017_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[2] : _0024_[2];
assign _0017_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[3] : _0024_[3];
assign _0017_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[4] : _0024_[4];
assign _0017_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[5] : _0024_[5];
assign _0017_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[6] : _0024_[6];
assign _0017_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[7] : _0024_[7];
assign _0017_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[8] : _0024_[8];
assign _0017_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[9] : _0024_[9];
assign _0017_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[10] : _0024_[10];
assign _0017_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[11] : _0024_[11];
assign _0017_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[12] : _0024_[12];
assign _0017_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[13] : _0024_[13];
assign _0017_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[14] : _0024_[14];
assign _0017_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[15] : _0024_[15];
assign _0017_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[16] : _0024_[16];
assign _0017_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[17] : _0024_[17];
assign _0017_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[18] : _0024_[18];
assign _0017_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[19] : _0024_[19];
assign _0017_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[20] : _0024_[20];
assign _0017_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[21] : _0024_[21];
assign _0017_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[22] : _0024_[22];
assign _0017_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[23] : _0024_[23];
assign _0017_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[24] : _0024_[24];
assign _0017_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[25] : _0024_[25];
assign _0017_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[26] : _0024_[26];
assign _0017_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[27] : _0024_[27];
assign _0017_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[28] : _0024_[28];
assign _0017_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[29] : _0024_[29];
assign _0017_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[30] : _0024_[30];
assign _0017_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0081_[31] : _0024_[31];
assign _0016_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[0] : _0023_[0];
assign _0016_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[1] : _0023_[1];
assign _0016_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[2] : _0023_[2];
assign _0016_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[3] : _0023_[3];
assign _0016_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[4] : _0023_[4];
assign _0016_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[5] : _0023_[5];
assign _0016_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[6] : _0023_[6];
assign _0016_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[7] : _0023_[7];
assign _0016_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[8] : _0023_[8];
assign _0016_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[9] : _0023_[9];
assign _0016_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[10] : _0023_[10];
assign _0016_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[11] : _0023_[11];
assign _0016_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[12] : _0023_[12];
assign _0016_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[13] : _0023_[13];
assign _0016_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[14] : _0023_[14];
assign _0016_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[15] : _0023_[15];
assign _0016_[16] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[16] : _0023_[16];
assign _0016_[17] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[17] : _0023_[17];
assign _0016_[18] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[18] : _0023_[18];
assign _0016_[19] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[19] : _0023_[19];
assign _0016_[20] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[20] : _0023_[20];
assign _0016_[21] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[21] : _0023_[21];
assign _0016_[22] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[22] : _0023_[22];
assign _0016_[23] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[23] : _0023_[23];
assign _0016_[24] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[24] : _0023_[24];
assign _0016_[25] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[25] : _0023_[25];
assign _0016_[26] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[26] : _0023_[26];
assign _0016_[27] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[27] : _0023_[27];
assign _0016_[28] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[28] : _0023_[28];
assign _0016_[29] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[29] : _0023_[29];
assign _0016_[30] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[30] : _0023_[30];
assign _0016_[31] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0080_[31] : _0023_[31];
assign _0018_[0] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[0] : _0032_[0];
assign _0018_[1] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[1] : _0032_[1];
assign _0018_[2] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[2] : _0032_[2];
assign _0018_[3] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[3] : _0032_[3];
assign _0018_[4] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[4] : _0032_[4];
assign _0018_[5] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[5] : _0032_[5];
assign _0018_[6] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[6] : _0032_[6];
assign _0018_[7] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[7] : _0032_[7];
assign _0018_[8] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[8] : _0032_[8];
assign _0018_[9] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[9] : _0032_[9];
assign _0018_[10] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[10] : _0032_[10];
assign _0018_[11] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[11] : _0032_[11];
assign _0018_[12] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[12] : _0032_[12];
assign _0018_[13] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[13] : _0032_[13];
assign _0018_[14] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[14] : _0032_[14];
assign _0018_[15] = _0313_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:319" *) _0084_[15] : _0032_[15];
assign _0101_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0104_[0] : _0056_[0];
assign _0101_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0104_[1] : _0056_[1];
assign _0101_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0104_[2] : _0056_[2];
assign _0101_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0104_[3] : _0056_[3];
assign _0101_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0104_[4] : _0056_[4];
assign _0156_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[0] : _0079_[0];
assign _0156_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[1] : _0079_[1];
assign _0156_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[2] : _0079_[2];
assign _0156_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[3] : _0079_[3];
assign _0156_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[4] : _0079_[4];
assign _0156_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[5] : _0079_[5];
assign _0156_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[6] : _0079_[6];
assign _0156_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[7] : _0079_[7];
assign _0156_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[8] : _0079_[8];
assign _0156_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[9] : _0079_[9];
assign _0156_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[10] : _0079_[10];
assign _0156_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[11] : _0079_[11];
assign _0156_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[12] : _0079_[12];
assign _0156_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[13] : _0079_[13];
assign _0156_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[14] : _0079_[14];
assign _0156_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[15] : _0079_[15];
assign _0156_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[16] : _0079_[16];
assign _0156_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[17] : _0079_[17];
assign _0156_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[18] : _0079_[18];
assign _0156_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[19] : _0079_[19];
assign _0156_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[20] : _0079_[20];
assign _0156_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[21] : _0079_[21];
assign _0156_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[22] : _0079_[22];
assign _0156_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[23] : _0079_[23];
assign _0156_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[24] : _0079_[24];
assign _0156_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[25] : _0079_[25];
assign _0156_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[26] : _0079_[26];
assign _0156_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[27] : _0079_[27];
assign _0156_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[28] : _0079_[28];
assign _0156_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[29] : _0079_[29];
assign _0156_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[30] : _0079_[30];
assign _0156_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[31] : _0079_[31];
assign _0156_[32] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[32] : _0079_[32];
assign _0156_[33] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[33] : _0079_[33];
assign _0156_[34] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[34] : _0079_[34];
assign _0156_[35] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[35] : _0079_[35];
assign _0156_[36] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[36] : _0079_[36];
assign _0156_[37] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[37] : _0079_[37];
assign _0156_[38] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[38] : _0079_[38];
assign _0156_[39] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[39] : _0079_[39];
assign _0156_[40] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[40] : _0079_[40];
assign _0156_[41] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[41] : _0079_[41];
assign _0156_[42] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[42] : _0079_[42];
assign _0156_[43] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[43] : _0079_[43];
assign _0156_[44] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[44] : _0079_[44];
assign _0156_[45] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[45] : _0079_[45];
assign _0156_[46] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[46] : _0079_[46];
assign _0156_[47] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[47] : _0079_[47];
assign _0156_[48] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[48] : _0079_[48];
assign _0156_[49] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[49] : _0079_[49];
assign _0156_[50] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[50] : _0079_[50];
assign _0156_[51] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[51] : _0079_[51];
assign _0156_[52] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[52] : _0079_[52];
assign _0156_[53] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[53] : _0079_[53];
assign _0156_[54] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[54] : _0079_[54];
assign _0156_[55] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[55] : _0079_[55];
assign _0156_[56] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[56] : _0079_[56];
assign _0156_[57] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[57] : _0079_[57];
assign _0156_[58] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[58] : _0079_[58];
assign _0156_[59] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[59] : _0079_[59];
assign _0156_[60] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[60] : _0079_[60];
assign _0156_[61] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[61] : _0079_[61];
assign _0156_[62] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[62] : _0079_[62];
assign _0156_[63] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0164_[63] : _0079_[63];
assign _0021_ = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0028_ : _0115_;
assign _0172_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[0] : _0081_[0];
assign _0172_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[1] : _0081_[1];
assign _0172_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[2] : _0081_[2];
assign _0172_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[3] : _0081_[3];
assign _0172_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[4] : _0081_[4];
assign _0172_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[5] : _0081_[5];
assign _0172_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[6] : _0081_[6];
assign _0172_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[7] : _0081_[7];
assign _0172_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[8] : _0081_[8];
assign _0172_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[9] : _0081_[9];
assign _0172_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[10] : _0081_[10];
assign _0172_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[11] : _0081_[11];
assign _0172_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[12] : _0081_[12];
assign _0172_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[13] : _0081_[13];
assign _0172_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[14] : _0081_[14];
assign _0172_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[15] : _0081_[15];
assign _0172_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[16] : _0081_[16];
assign _0172_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[17] : _0081_[17];
assign _0172_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[18] : _0081_[18];
assign _0172_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[19] : _0081_[19];
assign _0172_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[20] : _0081_[20];
assign _0172_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[21] : _0081_[21];
assign _0172_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[22] : _0081_[22];
assign _0172_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[23] : _0081_[23];
assign _0172_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[24] : _0081_[24];
assign _0172_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[25] : _0081_[25];
assign _0172_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[26] : _0081_[26];
assign _0172_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[27] : _0081_[27];
assign _0172_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[28] : _0081_[28];
assign _0172_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[29] : _0081_[29];
assign _0172_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[30] : _0081_[30];
assign _0172_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0017_[31] : _0081_[31];
assign _0171_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[0] : _0080_[0];
assign _0171_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[1] : _0080_[1];
assign _0171_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[2] : _0080_[2];
assign _0171_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[3] : _0080_[3];
assign _0171_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[4] : _0080_[4];
assign _0171_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[5] : _0080_[5];
assign _0171_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[6] : _0080_[6];
assign _0171_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[7] : _0080_[7];
assign _0171_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[8] : _0080_[8];
assign _0171_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[9] : _0080_[9];
assign _0171_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[10] : _0080_[10];
assign _0171_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[11] : _0080_[11];
assign _0171_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[12] : _0080_[12];
assign _0171_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[13] : _0080_[13];
assign _0171_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[14] : _0080_[14];
assign _0171_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[15] : _0080_[15];
assign _0171_[16] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[16] : _0080_[16];
assign _0171_[17] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[17] : _0080_[17];
assign _0171_[18] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[18] : _0080_[18];
assign _0171_[19] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[19] : _0080_[19];
assign _0171_[20] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[20] : _0080_[20];
assign _0171_[21] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[21] : _0080_[21];
assign _0171_[22] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[22] : _0080_[22];
assign _0171_[23] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[23] : _0080_[23];
assign _0171_[24] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[24] : _0080_[24];
assign _0171_[25] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[25] : _0080_[25];
assign _0171_[26] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[26] : _0080_[26];
assign _0171_[27] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[27] : _0080_[27];
assign _0171_[28] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[28] : _0080_[28];
assign _0171_[29] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[29] : _0080_[29];
assign _0171_[30] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[30] : _0080_[30];
assign _0171_[31] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0016_[31] : _0080_[31];
assign _0173_[0] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[0] : _0084_[0];
assign _0173_[1] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[1] : _0084_[1];
assign _0173_[2] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[2] : _0084_[2];
assign _0173_[3] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[3] : _0084_[3];
assign _0173_[4] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[4] : _0084_[4];
assign _0173_[5] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[5] : _0084_[5];
assign _0173_[6] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[6] : _0084_[6];
assign _0173_[7] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[7] : _0084_[7];
assign _0173_[8] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[8] : _0084_[8];
assign _0173_[9] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[9] : _0084_[9];
assign _0173_[10] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[10] : _0084_[10];
assign _0173_[11] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[11] : _0084_[11];
assign _0173_[12] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[12] : _0084_[12];
assign _0173_[13] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[13] : _0084_[13];
assign _0173_[14] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[14] : _0084_[14];
assign _0173_[15] = _0310_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:317" *) _0018_[15] : _0084_[15];
assign _0099_[0] = _0321_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0096_[0] : 1'b0;
assign _0099_[2] = _0321_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:293" *) _0096_[2] : 1'b1;
assign _0096_[2] = ~(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:288" *) _0096_[0];
assign _0166_[0] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[0] : parameter_Block[0];
assign _0166_[1] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[1] : parameter_Block[1];
assign _0166_[2] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[2] : parameter_Block[2];
assign _0166_[3] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[3] : parameter_Block[3];
assign _0166_[4] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[4] : parameter_Block[4];
assign _0166_[5] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[5] : parameter_Block[5];
assign _0166_[6] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[6] : parameter_Block[6];
assign _0166_[7] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[7] : parameter_Block[7];
assign _0166_[8] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[8] : parameter_Block[8];
assign _0166_[9] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[9] : parameter_Block[9];
assign _0166_[10] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[10] : parameter_Block[10];
assign _0166_[11] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[11] : parameter_Block[11];
assign _0166_[12] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[12] : parameter_Block[12];
assign _0166_[13] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[13] : parameter_Block[13];
assign _0166_[14] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[14] : parameter_Block[14];
assign _0166_[15] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[15] : parameter_Block[15];
assign _0166_[16] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[16] : parameter_Block[16];
assign _0166_[17] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[17] : parameter_Block[17];
assign _0166_[18] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[18] : parameter_Block[18];
assign _0166_[19] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[19] : parameter_Block[19];
assign _0166_[20] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[20] : parameter_Block[20];
assign _0166_[21] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[21] : parameter_Block[21];
assign _0166_[22] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[22] : parameter_Block[22];
assign _0166_[23] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[23] : parameter_Block[23];
assign _0166_[24] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[24] : parameter_Block[24];
assign _0166_[25] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[25] : parameter_Block[25];
assign _0166_[26] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[26] : parameter_Block[26];
assign _0166_[27] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[27] : parameter_Block[27];
assign _0166_[28] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[28] : parameter_Block[28];
assign _0166_[29] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[29] : parameter_Block[29];
assign _0166_[30] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[30] : parameter_Block[30];
assign _0166_[31] = _0374_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:283" *) _0110_[31] : parameter_Block[31];
assign _0165_[0] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[0] : parameter_Block[0];
assign _0165_[1] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[1] : parameter_Block[1];
assign _0165_[2] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[2] : parameter_Block[2];
assign _0165_[3] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[3] : parameter_Block[3];
assign _0165_[4] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[4] : parameter_Block[4];
assign _0165_[5] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[5] : parameter_Block[5];
assign _0165_[6] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[6] : parameter_Block[6];
assign _0165_[7] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[7] : parameter_Block[7];
assign _0165_[8] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[8] : parameter_Block[8];
assign _0165_[9] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[9] : parameter_Block[9];
assign _0165_[10] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[10] : parameter_Block[10];
assign _0165_[11] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[11] : parameter_Block[11];
assign _0165_[12] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[12] : parameter_Block[12];
assign _0165_[13] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[13] : parameter_Block[13];
assign _0165_[14] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[14] : parameter_Block[14];
assign _0165_[15] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[15] : parameter_Block[15];
assign _0165_[16] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[16] : parameter_Block[16];
assign _0165_[17] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[17] : parameter_Block[17];
assign _0165_[18] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[18] : parameter_Block[18];
assign _0165_[19] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[19] : parameter_Block[19];
assign _0165_[20] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[20] : parameter_Block[20];
assign _0165_[21] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[21] : parameter_Block[21];
assign _0165_[22] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[22] : parameter_Block[22];
assign _0165_[23] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[23] : parameter_Block[23];
assign _0165_[24] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[24] : parameter_Block[24];
assign _0165_[25] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[25] : parameter_Block[25];
assign _0165_[26] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[26] : parameter_Block[26];
assign _0165_[27] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[27] : parameter_Block[27];
assign _0165_[28] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[28] : parameter_Block[28];
assign _0165_[29] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[29] : parameter_Block[29];
assign _0165_[30] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[30] : parameter_Block[30];
assign _0165_[31] = _0373_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:278" *) _0109_[31] : parameter_Block[31];
assign _0167_[0] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[0] : _0339_[0];
assign _0167_[1] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[1] : _0431_[1];
assign _0167_[2] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[2] : _0431_[2];
assign _0167_[3] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[3] : _0431_[3];
assign _0167_[4] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[4] : _0431_[4];
assign _0167_[5] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[5] : _0431_[5];
assign _0167_[6] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[6] : _0431_[6];
assign _0167_[7] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[7] : _0431_[7];
assign _0167_[8] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[8] : _0431_[8];
assign _0167_[9] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[9] : _0431_[9];
assign _0167_[10] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[10] : _0431_[10];
assign _0167_[11] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[11] : _0431_[11];
assign _0167_[12] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[12] : _0431_[12];
assign _0167_[13] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[13] : _0431_[13];
assign _0167_[14] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[14] : _0431_[14];
assign _0167_[15] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0159_[15] : _0431_[15];
assign _0076_[0] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) 1'b1 : _0099_[0];
assign _0076_[2] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) 1'b0 : _0099_[2];
assign _0158_[0] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[0] : _0166_[0];
assign _0158_[1] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[1] : _0166_[1];
assign _0158_[2] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[2] : _0166_[2];
assign _0158_[3] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[3] : _0166_[3];
assign _0158_[4] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[4] : _0166_[4];
assign _0158_[5] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[5] : _0166_[5];
assign _0158_[6] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[6] : _0166_[6];
assign _0158_[7] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[7] : _0166_[7];
assign _0158_[8] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[8] : _0166_[8];
assign _0158_[9] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[9] : _0166_[9];
assign _0158_[10] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[10] : _0166_[10];
assign _0158_[11] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[11] : _0166_[11];
assign _0158_[12] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[12] : _0166_[12];
assign _0158_[13] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[13] : _0166_[13];
assign _0158_[14] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[14] : _0166_[14];
assign _0158_[15] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[15] : _0166_[15];
assign _0158_[16] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[16] : _0166_[16];
assign _0158_[17] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[17] : _0166_[17];
assign _0158_[18] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[18] : _0166_[18];
assign _0158_[19] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[19] : _0166_[19];
assign _0158_[20] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[20] : _0166_[20];
assign _0158_[21] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[21] : _0166_[21];
assign _0158_[22] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[22] : _0166_[22];
assign _0158_[23] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[23] : _0166_[23];
assign _0158_[24] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[24] : _0166_[24];
assign _0158_[25] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[25] : _0166_[25];
assign _0158_[26] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[26] : _0166_[26];
assign _0158_[27] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[27] : _0166_[27];
assign _0158_[28] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[28] : _0166_[28];
assign _0158_[29] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[29] : _0166_[29];
assign _0158_[30] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[30] : _0166_[30];
assign _0158_[31] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[31] : _0166_[31];
assign _0157_[0] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[0] : _0165_[0];
assign _0157_[1] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[1] : _0165_[1];
assign _0157_[2] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[2] : _0165_[2];
assign _0157_[3] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[3] : _0165_[3];
assign _0157_[4] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[4] : _0165_[4];
assign _0157_[5] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[5] : _0165_[5];
assign _0157_[6] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[6] : _0165_[6];
assign _0157_[7] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[7] : _0165_[7];
assign _0157_[8] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[8] : _0165_[8];
assign _0157_[9] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[9] : _0165_[9];
assign _0157_[10] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[10] : _0165_[10];
assign _0157_[11] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[11] : _0165_[11];
assign _0157_[12] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[12] : _0165_[12];
assign _0157_[13] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[13] : _0165_[13];
assign _0157_[14] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[14] : _0165_[14];
assign _0157_[15] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[15] : _0165_[15];
assign _0157_[16] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[16] : _0165_[16];
assign _0157_[17] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[17] : _0165_[17];
assign _0157_[18] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[18] : _0165_[18];
assign _0157_[19] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[19] : _0165_[19];
assign _0157_[20] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[20] : _0165_[20];
assign _0157_[21] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[21] : _0165_[21];
assign _0157_[22] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[22] : _0165_[22];
assign _0157_[23] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[23] : _0165_[23];
assign _0157_[24] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[24] : _0165_[24];
assign _0157_[25] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[25] : _0165_[25];
assign _0157_[26] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[26] : _0165_[26];
assign _0157_[27] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[27] : _0165_[27];
assign _0157_[28] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[28] : _0165_[28];
assign _0157_[29] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[29] : _0165_[29];
assign _0157_[30] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[30] : _0165_[30];
assign _0157_[31] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[31] : _0165_[31];
assign _0147_[0] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[0] : _0108_[0];
assign _0147_[1] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[1] : _0108_[1];
assign _0147_[2] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[2] : _0108_[2];
assign _0147_[3] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[3] : _0108_[3];
assign _0147_[4] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[4] : _0108_[4];
assign _0147_[5] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[5] : _0108_[5];
assign _0147_[6] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[6] : _0108_[6];
assign _0147_[7] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[7] : _0108_[7];
assign _0147_[8] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[8] : _0108_[8];
assign _0147_[9] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[9] : _0108_[9];
assign _0147_[10] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[10] : _0108_[10];
assign _0147_[11] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[11] : _0108_[11];
assign _0147_[12] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[12] : _0108_[12];
assign _0147_[13] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[13] : _0108_[13];
assign _0147_[14] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[14] : _0108_[14];
assign _0147_[15] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[15] : _0108_[15];
assign _0147_[16] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[16] : _0108_[16];
assign _0147_[17] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[17] : _0108_[17];
assign _0147_[18] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[18] : _0108_[18];
assign _0147_[19] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[19] : _0108_[19];
assign _0147_[20] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[20] : _0108_[20];
assign _0147_[21] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[21] : _0108_[21];
assign _0147_[22] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[22] : _0108_[22];
assign _0147_[23] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[23] : _0108_[23];
assign _0147_[24] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[24] : _0108_[24];
assign _0147_[25] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[25] : _0108_[25];
assign _0147_[26] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[26] : _0108_[26];
assign _0147_[27] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[27] : _0108_[27];
assign _0147_[28] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[28] : _0108_[28];
assign _0147_[29] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[29] : _0108_[29];
assign _0147_[30] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[30] : _0108_[30];
assign _0147_[31] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0110_[31] : _0108_[31];
assign _0147_[32] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[0] : _0108_[32];
assign _0147_[33] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[1] : _0108_[33];
assign _0147_[34] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[2] : _0108_[34];
assign _0147_[35] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[3] : _0108_[35];
assign _0147_[36] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[4] : _0108_[36];
assign _0147_[37] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[5] : _0108_[37];
assign _0147_[38] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[6] : _0108_[38];
assign _0147_[39] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[7] : _0108_[39];
assign _0147_[40] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[8] : _0108_[40];
assign _0147_[41] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[9] : _0108_[41];
assign _0147_[42] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[10] : _0108_[42];
assign _0147_[43] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[11] : _0108_[43];
assign _0147_[44] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[12] : _0108_[44];
assign _0147_[45] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[13] : _0108_[45];
assign _0147_[46] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[14] : _0108_[46];
assign _0147_[47] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[15] : _0108_[47];
assign _0147_[48] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[16] : _0108_[48];
assign _0147_[49] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[17] : _0108_[49];
assign _0147_[50] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[18] : _0108_[50];
assign _0147_[51] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[19] : _0108_[51];
assign _0147_[52] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[20] : _0108_[52];
assign _0147_[53] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[21] : _0108_[53];
assign _0147_[54] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[22] : _0108_[54];
assign _0147_[55] = _0483_ ? (* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:276" *) _0109_[23] : _0108_[55];
assign _0477_ = ~_0475_[31];
assign _0478_ = ~_0479_;
assign _0472_ = ~_0470_[31];
assign _0473_ = ~_0474_;
assign _0468_ = ~_0469_;
assign _0467_ = ~_0465_[31];
assign _0462_ = ~_0460_[31];
assign _0463_ = ~_0464_;
assign _0457_ = ~_0455_[31];
assign _0458_ = ~_0459_;
assign _0452_ = ~_0450_[31];
assign _0453_ = ~_0454_;
assign _0447_ = ~_0445_[31];
assign _0448_ = ~_0449_;
assign _0176_ = ~_0483_;
assign _0482_ = ~_0480_[31];
assign _0442_ = ~_0440_[31];
assign _0443_ = ~_0444_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
always @(posedge clk)
state[0] <= _0011_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
always @(posedge clk)
state[1] <= _0011_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
always @(posedge clk)
state[2] <= _0011_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
always @(posedge clk)
state[3] <= _0011_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:63" *)
always @(posedge clk)
state[4] <= _0011_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[0] <= _0007_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[1] <= _0007_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[2] <= _0007_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[3] <= _0007_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[4] <= _0007_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[5] <= _0007_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[6] <= _0007_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[7] <= _0007_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[8] <= _0007_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[9] <= _0007_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[10] <= _0007_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[11] <= _0007_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[12] <= _0007_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[13] <= _0007_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[14] <= _0007_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[15] <= _0007_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[16] <= _0007_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[17] <= _0007_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[18] <= _0007_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[19] <= _0007_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[20] <= _0007_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[21] <= _0007_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[22] <= _0007_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[23] <= _0007_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[24] <= _0007_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[25] <= _0007_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[26] <= _0007_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[27] <= _0007_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[28] <= _0007_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[29] <= _0007_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[30] <= _0007_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out[31] <= _0007_[31];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[0] <= _0006_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[1] <= _0006_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[2] <= _0006_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[3] <= _0006_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[4] <= _0006_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[5] <= _0006_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[6] <= _0006_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[7] <= _0006_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[8] <= _0006_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[9] <= _0006_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[10] <= _0006_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[11] <= _0006_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[12] <= _0006_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[13] <= _0006_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[14] <= _0006_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[15] <= _0006_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[16] <= _0006_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[17] <= _0006_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[18] <= _0006_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[19] <= _0006_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[20] <= _0006_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[21] <= _0006_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[22] <= _0006_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[23] <= _0006_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[24] <= _0006_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[25] <= _0006_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[26] <= _0006_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[27] <= _0006_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[28] <= _0006_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[29] <= _0006_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[30] <= _0006_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[31] <= _0006_[31];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[32] <= _0006_[32];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[33] <= _0006_[33];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[34] <= _0006_[34];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[35] <= _0006_[35];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[36] <= _0006_[36];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[37] <= _0006_[37];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[38] <= _0006_[38];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[39] <= _0006_[39];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[40] <= _0006_[40];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[41] <= _0006_[41];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[42] <= _0006_[42];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[43] <= _0006_[43];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[44] <= _0006_[44];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[45] <= _0006_[45];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[46] <= _0006_[46];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[47] <= _0006_[47];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[48] <= _0006_[48];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[49] <= _0006_[49];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[50] <= _0006_[50];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[51] <= _0006_[51];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[52] <= _0006_[52];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[53] <= _0006_[53];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[54] <= _0006_[54];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[55] <= _0006_[55];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[56] <= _0006_[56];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[57] <= _0006_[57];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[58] <= _0006_[58];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[59] <= _0006_[59];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[60] <= _0006_[60];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[61] <= _0006_[61];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[62] <= _0006_[62];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
data_out2[63] <= _0006_[63];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[0] <= _0004_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[1] <= _0004_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[2] <= _0004_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[3] <= _0004_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[4] <= _0004_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[5] <= _0004_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[6] <= _0004_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bmRequestType[7] <= _0004_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[0] <= _0003_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[1] <= _0003_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[2] <= _0003_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[3] <= _0003_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[4] <= _0003_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[5] <= _0003_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[6] <= _0003_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
bRequest[7] <= _0003_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[0] <= _0005_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[1] <= _0005_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[2] <= _0005_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[3] <= _0005_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[4] <= _0005_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[5] <= _0005_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[6] <= _0005_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[7] <= _0005_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[8] <= _0005_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[9] <= _0005_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[10] <= _0005_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[11] <= _0005_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[12] <= _0005_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[13] <= _0005_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[14] <= _0005_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
count[15] <= _0005_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[0] <= _0009_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[1] <= _0009_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[2] <= _0009_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[3] <= _0009_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[4] <= _0009_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[5] <= _0009_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[6] <= _0009_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[7] <= _0009_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[8] <= _0009_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[9] <= _0009_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[10] <= _0009_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[11] <= _0009_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[12] <= _0009_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[13] <= _0009_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[14] <= _0009_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[15] <= _0009_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[16] <= _0009_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[17] <= _0009_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[18] <= _0009_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[19] <= _0009_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[20] <= _0009_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[21] <= _0009_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[22] <= _0009_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[23] <= _0009_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[24] <= _0009_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[25] <= _0009_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[26] <= _0009_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[27] <= _0009_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[28] <= _0009_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[29] <= _0009_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[30] <= _0009_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
readWrite[31] <= _0009_[31];
reg \wValue_reg[0] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[0] <= _0014_[0];
assign wValue[0] = \wValue_reg[0] ;
reg \wValue_reg[1] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[1] <= _0014_[1];
assign wValue[1] = \wValue_reg[1] ;
reg \wValue_reg[2] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[2] <= _0014_[2];
assign wValue[2] = \wValue_reg[2] ;
reg \wValue_reg[3] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[3] <= _0014_[3];
assign wValue[3] = \wValue_reg[3] ;
reg \wValue_reg[4] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[4] <= _0014_[4];
assign wValue[4] = \wValue_reg[4] ;
reg \wValue_reg[5] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[5] <= _0014_[5];
assign wValue[5] = \wValue_reg[5] ;
reg \wValue_reg[6] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[6] <= _0014_[6];
assign wValue[6] = \wValue_reg[6] ;
reg \wValue_reg[7] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wValue_reg[7] <= _0014_[7];
assign wValue[7] = \wValue_reg[7] ;
reg \wIndex_reg[8] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[8] <= _0012_[8];
assign wIndex[8] = \wIndex_reg[8] ;
reg \wIndex_reg[9] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[9] <= _0012_[9];
assign wIndex[9] = \wIndex_reg[9] ;
reg \wIndex_reg[10] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[10] <= _0012_[10];
assign wIndex[10] = \wIndex_reg[10] ;
reg \wIndex_reg[11] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[11] <= _0012_[11];
assign wIndex[11] = \wIndex_reg[11] ;
reg \wIndex_reg[12] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[12] <= _0012_[12];
assign wIndex[12] = \wIndex_reg[12] ;
reg \wIndex_reg[13] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[13] <= _0012_[13];
assign wIndex[13] = \wIndex_reg[13] ;
reg \wIndex_reg[14] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[14] <= _0012_[14];
assign wIndex[14] = \wIndex_reg[14] ;
reg \wIndex_reg[15] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
\wIndex_reg[15] <= _0012_[15];
assign wIndex[15] = \wIndex_reg[15] ;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[0] <= _0013_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[1] <= _0013_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[2] <= _0013_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[3] <= _0013_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[4] <= _0013_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[5] <= _0013_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[6] <= _0013_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[7] <= _0013_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[8] <= _0013_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[9] <= _0013_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[10] <= _0013_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[11] <= _0013_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[12] <= _0013_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[13] <= _0013_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[14] <= _0013_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
wLength[15] <= _0013_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[0] <= _0001_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[1] <= _0001_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[2] <= _0001_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[3] <= _0001_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[4] <= _0001_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[5] <= _0001_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[6] <= _0001_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[7] <= _0001_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[8] <= _0001_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[9] <= _0001_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[10] <= _0001_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[11] <= _0001_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[12] <= _0001_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[13] <= _0001_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[14] <= _0001_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[15] <= _0001_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[16] <= _0001_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[17] <= _0001_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[18] <= _0001_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[19] <= _0001_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[20] <= _0001_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[21] <= _0001_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[22] <= _0001_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[23] <= _0001_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[24] <= _0001_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[25] <= _0001_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[26] <= _0001_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[27] <= _0001_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[28] <= _0001_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[29] <= _0001_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[30] <= _0001_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp1[31] <= _0001_[31];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[0] <= _0002_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[1] <= _0002_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[2] <= _0002_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[3] <= _0002_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[4] <= _0002_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[5] <= _0002_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[6] <= _0002_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[7] <= _0002_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[8] <= _0002_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[9] <= _0002_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[10] <= _0002_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[11] <= _0002_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[12] <= _0002_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[13] <= _0002_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[14] <= _0002_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[15] <= _0002_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[16] <= _0002_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[17] <= _0002_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[18] <= _0002_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[19] <= _0002_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[20] <= _0002_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[21] <= _0002_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[22] <= _0002_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[23] <= _0002_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[24] <= _0002_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[25] <= _0002_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[26] <= _0002_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[27] <= _0002_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[28] <= _0002_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[29] <= _0002_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[30] <= _0002_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
addresstemp2[31] <= _0002_[31];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
singl_data <= _0010_;
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[0] <= _0000_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[1] <= _0000_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[2] <= _0000_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[3] <= _0000_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[4] <= _0000_[4];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[5] <= _0000_[5];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[6] <= _0000_[6];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[7] <= _0000_[7];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[8] <= _0000_[8];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[9] <= _0000_[9];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[10] <= _0000_[10];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[11] <= _0000_[11];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[12] <= _0000_[12];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[13] <= _0000_[13];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[14] <= _0000_[14];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[15] <= _0000_[15];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[16] <= _0000_[16];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[17] <= _0000_[17];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[18] <= _0000_[18];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[19] <= _0000_[19];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[20] <= _0000_[20];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[21] <= _0000_[21];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[22] <= _0000_[22];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[23] <= _0000_[23];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[24] <= _0000_[24];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[25] <= _0000_[25];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[26] <= _0000_[26];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[27] <= _0000_[27];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[28] <= _0000_[28];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[29] <= _0000_[29];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[30] <= _0000_[30];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[31] <= _0000_[31];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[32] <= _0000_[32];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[33] <= _0000_[33];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[34] <= _0000_[34];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[35] <= _0000_[35];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[36] <= _0000_[36];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[37] <= _0000_[37];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[38] <= _0000_[38];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[39] <= _0000_[39];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[40] <= _0000_[40];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[41] <= _0000_[41];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[42] <= _0000_[42];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[43] <= _0000_[43];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[44] <= _0000_[44];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[45] <= _0000_[45];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[46] <= _0000_[46];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[47] <= _0000_[47];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[48] <= _0000_[48];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[49] <= _0000_[49];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[50] <= _0000_[50];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[51] <= _0000_[51];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[52] <= _0000_[52];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[53] <= _0000_[53];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[54] <= _0000_[54];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[55] <= _0000_[55];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[56] <= _0000_[56];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[57] <= _0000_[57];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[58] <= _0000_[58];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[59] <= _0000_[59];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[60] <= _0000_[60];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[61] <= _0000_[61];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[62] <= _0000_[62];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
address[63] <= _0000_[63];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
next_state[0] <= _0008_[0];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
next_state[1] <= _0008_[1];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
next_state[2] <= _0008_[2];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
next_state[3] <= _0008_[3];
(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:69" *)
always @(posedge clk)
next_state[4] <= _0008_[4];
assign _0327_[0] = state[0] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'b1;
assign _0326_[2] = state[2] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'b1;
assign _0328_[3] = state[3] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'b1;
assign _0327_[1] = state[1] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'b1;
assign _0329_[4] = state[4] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94" *) 1'b1;
assign _0479_ = _0477_ | _0196_[0];
assign _0474_ = _0472_ | _0200_[0];
assign _0469_ = _0467_ | _0204_[0];
assign _0464_ = _0462_ | _0208_[0];
assign _0459_ = _0457_ | _0212_[0];
assign _0454_ = _0452_ | _0216_[0];
assign _0449_ = _0447_ | _0220_[0];
assign _0483_ = _0482_ | _0224_[0];
assign _0444_ = _0442_ | _0228_[0];
assign _0417_[30] = _0087_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0416_;
assign _0417_[31] = start &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0416_;
assign _0417_[25] = _0130_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0415_;
assign _0417_[26] = _0130_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0415_;
assign _0417_[27] = _0130_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0415_;
assign _0417_[28] = _0130_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0415_;
assign _0417_[29] = _0130_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0415_;
assign _0417_[20] = _0033_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0414_;
assign _0417_[21] = _0033_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0414_;
assign _0417_[22] = _0033_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0414_;
assign _0417_[23] = _0033_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0414_;
assign _0417_[24] = _0033_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0414_;
assign _0417_[15] = _0053_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0413_;
assign _0417_[16] = _0053_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0413_;
assign _0417_[17] = _0053_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0413_;
assign _0417_[18] = _0053_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0413_;
assign _0417_[19] = _0053_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0413_;
assign _0417_[10] = _0101_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0417_[11] = _0101_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0417_[12] = _0101_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0417_[13] = _0101_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0417_[14] = _0101_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0417_[5] = _0120_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0417_[6] = _0120_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0417_[7] = _0120_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0417_[8] = _0120_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0417_[9] = _0120_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0417_[0] = _0136_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0417_[1] = _0136_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0417_[2] = _0136_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0417_[3] = _0136_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0417_[4] = _0136_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0419_[3] = _0089_ &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0416_;
assign _0419_[2] = _0021_ &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0419_[1] = _0057_ &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0419_[0] = _0094_ &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0421_[64] = _0156_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[65] = _0156_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[66] = _0156_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[67] = _0156_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[68] = _0156_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[69] = _0156_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[70] = _0156_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[71] = _0156_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[72] = _0156_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[73] = _0156_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[74] = _0156_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[75] = _0156_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[76] = _0156_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[77] = _0156_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[78] = _0156_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[79] = _0156_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[80] = _0156_[16] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[81] = _0156_[17] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[82] = _0156_[18] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[83] = _0156_[19] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[84] = _0156_[20] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[85] = _0156_[21] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[86] = _0156_[22] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[87] = _0156_[23] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[88] = _0156_[24] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[89] = _0156_[25] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[90] = _0156_[26] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[91] = _0156_[27] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[92] = _0156_[28] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[93] = _0156_[29] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[94] = _0156_[30] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[95] = _0156_[31] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[96] = _0156_[32] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[97] = _0156_[33] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[98] = _0156_[34] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[99] = _0156_[35] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[100] = _0156_[36] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[101] = _0156_[37] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[102] = _0156_[38] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[103] = _0156_[39] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[104] = _0156_[40] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[105] = _0156_[41] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[106] = _0156_[42] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[107] = _0156_[43] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[108] = _0156_[44] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[109] = _0156_[45] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[110] = _0156_[46] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[111] = _0156_[47] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[112] = _0156_[48] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[113] = _0156_[49] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[114] = _0156_[50] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[115] = _0156_[51] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[116] = _0156_[52] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[117] = _0156_[53] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[118] = _0156_[54] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[119] = _0156_[55] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[120] = _0156_[56] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[121] = _0156_[57] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[122] = _0156_[58] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[123] = _0156_[59] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[124] = _0156_[60] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[125] = _0156_[61] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[126] = _0156_[62] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[127] = _0156_[63] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0421_[0] = _0034_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[1] = _0034_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[2] = _0034_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[3] = _0034_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[4] = _0034_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[5] = _0034_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[6] = _0034_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[7] = _0034_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[8] = _0034_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[9] = _0034_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[10] = _0034_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[11] = _0034_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[12] = _0034_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[13] = _0034_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[14] = _0034_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[15] = _0034_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[16] = _0034_[16] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[17] = _0034_[17] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[18] = _0034_[18] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[19] = _0034_[19] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[20] = _0034_[20] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[21] = _0034_[21] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[22] = _0034_[22] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[23] = _0034_[23] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[24] = _0034_[24] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[25] = _0034_[25] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[26] = _0034_[26] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[27] = _0034_[27] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[28] = _0034_[28] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[29] = _0034_[29] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[30] = _0034_[30] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[31] = _0034_[31] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[32] = _0034_[32] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[33] = _0034_[33] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[34] = _0034_[34] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[35] = _0034_[35] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[36] = _0034_[36] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[37] = _0034_[37] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[38] = _0034_[38] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[39] = _0034_[39] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[40] = _0034_[40] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[41] = _0034_[41] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[42] = _0034_[42] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[43] = _0034_[43] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[44] = _0034_[44] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[45] = _0034_[45] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[46] = _0034_[46] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[47] = _0034_[47] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[48] = _0034_[48] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[49] = _0034_[49] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[50] = _0034_[50] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[51] = _0034_[51] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[52] = _0034_[52] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[53] = _0034_[53] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[54] = _0034_[54] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[55] = _0034_[55] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[56] = _0034_[56] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[57] = _0034_[57] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[58] = _0034_[58] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[59] = _0034_[59] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[60] = _0034_[60] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[61] = _0034_[61] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[62] = _0034_[62] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0421_[63] = _0034_[63] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0390_;
assign _0423_[32] = _0173_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[33] = _0173_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[34] = _0173_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[35] = _0173_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[36] = _0173_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[37] = _0173_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[38] = _0173_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[39] = _0173_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[40] = _0173_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[41] = _0173_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[42] = _0173_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[43] = _0173_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[44] = _0173_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[45] = _0173_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[46] = _0173_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[47] = _0173_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0400_;
assign _0423_[16] = _0055_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[17] = _0055_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[18] = _0055_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[19] = _0055_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[20] = _0055_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[21] = _0055_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[22] = _0055_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[23] = _0055_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[24] = _0055_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[25] = _0055_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[26] = _0055_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[27] = _0055_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[28] = _0055_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[29] = _0055_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[30] = _0055_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[31] = _0055_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0391_;
assign _0423_[0] = _0095_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[1] = _0095_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[2] = _0095_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[3] = _0095_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[4] = _0095_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[5] = _0095_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[6] = _0095_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[7] = _0095_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[8] = _0095_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[9] = _0095_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[10] = _0095_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[11] = _0095_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[12] = _0095_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[13] = _0095_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[14] = _0095_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0423_[15] = _0095_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0379_;
assign _0425_[32] = _0144_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[33] = _0144_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[34] = _0144_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[35] = _0144_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[36] = _0144_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[37] = _0144_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[38] = _0144_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[39] = _0144_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[40] = _0144_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[41] = _0144_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[42] = _0144_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[43] = _0144_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[44] = _0144_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[45] = _0144_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[46] = _0144_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[47] = _0144_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[48] = _0144_[16] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[49] = _0144_[17] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[50] = _0144_[18] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[51] = _0144_[19] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[52] = _0144_[20] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[53] = _0144_[21] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[54] = _0144_[22] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[55] = _0144_[23] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[56] = _0144_[24] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[57] = _0144_[25] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[58] = _0144_[26] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[59] = _0144_[27] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[60] = _0144_[28] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[61] = _0144_[29] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[62] = _0144_[30] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[63] = _0144_[31] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0395_;
assign _0425_[0] = _0019_[0] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[1] = _0019_[1] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[2] = _0019_[2] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[3] = _0019_[3] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[4] = _0019_[4] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[5] = _0019_[5] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[6] = _0019_[6] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[7] = _0019_[7] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[8] = _0019_[8] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[9] = _0019_[9] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[10] = _0019_[10] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[11] = _0019_[11] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[12] = _0019_[12] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[13] = _0019_[13] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[14] = _0019_[14] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[15] = _0019_[15] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[16] = _0019_[16] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[17] = _0019_[17] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[18] = _0019_[18] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[19] = _0019_[19] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[20] = _0019_[20] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[21] = _0019_[21] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[22] = _0019_[22] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[23] = _0019_[23] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[24] = _0019_[24] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[25] = _0019_[25] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[26] = _0019_[26] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[27] = _0019_[27] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[28] = _0019_[28] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[29] = _0019_[29] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[30] = _0019_[30] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0425_[31] = _0019_[31] &(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:94|<techmap.v>:434" *) _0388_;
assign _0438_[1] = _0476_[1] ^(* src = "<techmap.v>:263" *) _0100_[0];
assign _0438_[2] = _0476_[2] ^(* src = "<techmap.v>:263" *) _0497_[1];
assign _0438_[3] = _0476_[3] ^(* src = "<techmap.v>:263" *) _0497_[2];
assign _0438_[4] = _0476_[4] ^(* src = "<techmap.v>:263" *) _0497_[3];
assign _0438_[5] = _0476_[5] ^(* src = "<techmap.v>:263" *) _0497_[4];
assign _0438_[6] = _0476_[6] ^(* src = "<techmap.v>:263" *) _0497_[5];
assign _0438_[7] = _0476_[7] ^(* src = "<techmap.v>:263" *) _0497_[6];
assign _0438_[8] = _0476_[8] ^(* src = "<techmap.v>:263" *) _0497_[7];
assign _0438_[9] = _0476_[9] ^(* src = "<techmap.v>:263" *) _0497_[8];
assign _0438_[10] = _0476_[10] ^(* src = "<techmap.v>:263" *) _0497_[9];
assign _0438_[11] = _0476_[11] ^(* src = "<techmap.v>:263" *) _0497_[10];
assign _0438_[12] = _0476_[12] ^(* src = "<techmap.v>:263" *) _0497_[11];
assign _0438_[13] = _0476_[13] ^(* src = "<techmap.v>:263" *) _0497_[12];
assign _0438_[14] = _0476_[14] ^(* src = "<techmap.v>:263" *) _0497_[13];
assign _0438_[15] = _0476_[15] ^(* src = "<techmap.v>:263" *) _0497_[14];
assign _0438_[0] = _0100_[0] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[1] = _0100_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[2] = _0100_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[3] = _0100_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[4] = _0100_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[5] = _0100_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[6] = _0100_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[7] = _0100_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[8] = _0100_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[9] = _0100_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[10] = _0100_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[11] = _0100_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[12] = _0100_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[13] = _0100_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[14] = _0100_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0476_[15] = _0100_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0437_[1] = _0471_[1] ^(* src = "<techmap.v>:263" *) _0077_[0];
assign _0437_[2] = _0471_[2] ^(* src = "<techmap.v>:263" *) _0496_[1];
assign _0437_[3] = _0471_[3] ^(* src = "<techmap.v>:263" *) _0496_[2];
assign _0437_[4] = _0471_[4] ^(* src = "<techmap.v>:263" *) _0496_[3];
assign _0437_[5] = _0471_[5] ^(* src = "<techmap.v>:263" *) _0496_[4];
assign _0437_[6] = _0471_[6] ^(* src = "<techmap.v>:263" *) _0496_[5];
assign _0437_[7] = _0471_[7] ^(* src = "<techmap.v>:263" *) _0496_[6];
assign _0437_[8] = _0471_[8] ^(* src = "<techmap.v>:263" *) _0496_[7];
assign _0437_[9] = _0471_[9] ^(* src = "<techmap.v>:263" *) _0496_[8];
assign _0437_[10] = _0471_[10] ^(* src = "<techmap.v>:263" *) _0496_[9];
assign _0437_[11] = _0471_[11] ^(* src = "<techmap.v>:263" *) _0496_[10];
assign _0437_[12] = _0471_[12] ^(* src = "<techmap.v>:263" *) _0496_[11];
assign _0437_[13] = _0471_[13] ^(* src = "<techmap.v>:263" *) _0496_[12];
assign _0437_[14] = _0471_[14] ^(* src = "<techmap.v>:263" *) _0496_[13];
assign _0437_[15] = _0471_[15] ^(* src = "<techmap.v>:263" *) _0496_[14];
assign _0437_[0] = _0077_[0] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[1] = _0077_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[2] = _0077_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[3] = _0077_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[4] = _0077_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[5] = _0077_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[6] = _0077_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[7] = _0077_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[8] = _0077_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[9] = _0077_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[10] = _0077_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[11] = _0077_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[12] = _0077_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[13] = _0077_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[14] = _0077_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0471_[15] = _0077_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[1] = _0070_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[2] = _0070_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[3] = _0070_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[4] = _0070_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[7] = _0070_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[8] = _0070_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[9] = _0070_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[10] = _0070_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[11] = _0070_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[13] = _0070_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[14] = _0070_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[15] = _0070_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0436_[0] = _0070_[0] ^(* src = "<techmap.v>:263" *) 1'b1;
assign _0436_[1] = _0466_[1] ^(* src = "<techmap.v>:263" *) _0070_[0];
assign _0436_[2] = _0466_[2] ^(* src = "<techmap.v>:263" *) _0495_[1];
assign _0436_[3] = _0466_[3] ^(* src = "<techmap.v>:263" *) _0495_[2];
assign _0436_[4] = _0466_[4] ^(* src = "<techmap.v>:263" *) _0495_[3];
assign _0436_[5] = _0466_[5] ^(* src = "<techmap.v>:263" *) _0495_[4];
assign _0436_[6] = _0466_[6] ^(* src = "<techmap.v>:263" *) _0495_[5];
assign _0436_[7] = _0466_[7] ^(* src = "<techmap.v>:263" *) _0495_[6];
assign _0436_[8] = _0466_[8] ^(* src = "<techmap.v>:263" *) _0495_[7];
assign _0436_[9] = _0466_[9] ^(* src = "<techmap.v>:263" *) _0495_[8];
assign _0436_[10] = _0466_[10] ^(* src = "<techmap.v>:263" *) _0495_[9];
assign _0436_[11] = _0466_[11] ^(* src = "<techmap.v>:263" *) _0495_[10];
assign _0436_[12] = _0466_[12] ^(* src = "<techmap.v>:263" *) _0495_[11];
assign _0436_[13] = _0466_[13] ^(* src = "<techmap.v>:263" *) _0495_[12];
assign _0436_[14] = _0466_[14] ^(* src = "<techmap.v>:263" *) _0495_[13];
assign _0436_[15] = _0466_[15] ^(* src = "<techmap.v>:263" *) _0495_[14];
assign _0466_[5] = _0070_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[6] = _0070_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0466_[12] = _0070_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[1] = _0061_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[2] = _0061_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[3] = _0061_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[6] = _0061_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[7] = _0061_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[8] = _0061_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[9] = _0061_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[11] = _0061_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[12] = _0061_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[13] = _0061_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[14] = _0061_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0435_[1] = _0461_[1] ^(* src = "<techmap.v>:263" *) _0061_[0];
assign _0435_[2] = _0461_[2] ^(* src = "<techmap.v>:263" *) _0494_[1];
assign _0435_[3] = _0461_[3] ^(* src = "<techmap.v>:263" *) _0494_[2];
assign _0435_[4] = _0461_[4] ^(* src = "<techmap.v>:263" *) _0494_[3];
assign _0435_[5] = _0461_[5] ^(* src = "<techmap.v>:263" *) _0494_[4];
assign _0435_[6] = _0461_[6] ^(* src = "<techmap.v>:263" *) _0494_[5];
assign _0435_[7] = _0461_[7] ^(* src = "<techmap.v>:263" *) _0494_[6];
assign _0435_[8] = _0461_[8] ^(* src = "<techmap.v>:263" *) _0494_[7];
assign _0435_[9] = _0461_[9] ^(* src = "<techmap.v>:263" *) _0494_[8];
assign _0435_[10] = _0461_[10] ^(* src = "<techmap.v>:263" *) _0494_[9];
assign _0435_[11] = _0461_[11] ^(* src = "<techmap.v>:263" *) _0494_[10];
assign _0435_[12] = _0461_[12] ^(* src = "<techmap.v>:263" *) _0494_[11];
assign _0435_[13] = _0461_[13] ^(* src = "<techmap.v>:263" *) _0494_[12];
assign _0435_[14] = _0461_[14] ^(* src = "<techmap.v>:263" *) _0494_[13];
assign _0435_[15] = _0461_[15] ^(* src = "<techmap.v>:263" *) _0494_[14];
assign _0435_[0] = _0061_[0] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[4] = _0061_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[5] = _0061_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[10] = _0061_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0461_[15] = _0061_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[1] = _0050_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[2] = _0050_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[4] = _0050_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[6] = _0050_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[9] = _0050_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[12] = _0050_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[13] = _0050_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0434_[1] = _0456_[1] ^(* src = "<techmap.v>:263" *) _0050_[0];
assign _0434_[2] = _0456_[2] ^(* src = "<techmap.v>:263" *) _0493_[1];
assign _0434_[3] = _0456_[3] ^(* src = "<techmap.v>:263" *) _0493_[2];
assign _0434_[4] = _0456_[4] ^(* src = "<techmap.v>:263" *) _0493_[3];
assign _0434_[5] = _0456_[5] ^(* src = "<techmap.v>:263" *) _0493_[4];
assign _0434_[6] = _0456_[6] ^(* src = "<techmap.v>:263" *) _0493_[5];
assign _0434_[7] = _0456_[7] ^(* src = "<techmap.v>:263" *) _0493_[6];
assign _0434_[8] = _0456_[8] ^(* src = "<techmap.v>:263" *) _0493_[7];
assign _0434_[9] = _0456_[9] ^(* src = "<techmap.v>:263" *) _0493_[8];
assign _0434_[10] = _0456_[10] ^(* src = "<techmap.v>:263" *) _0493_[9];
assign _0434_[11] = _0456_[11] ^(* src = "<techmap.v>:263" *) _0493_[10];
assign _0434_[12] = _0456_[12] ^(* src = "<techmap.v>:263" *) _0493_[11];
assign _0434_[13] = _0456_[13] ^(* src = "<techmap.v>:263" *) _0493_[12];
assign _0434_[14] = _0456_[14] ^(* src = "<techmap.v>:263" *) _0493_[13];
assign _0434_[15] = _0456_[15] ^(* src = "<techmap.v>:263" *) _0493_[14];
assign _0434_[0] = _0050_[0] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[3] = _0050_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[5] = _0050_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[7] = _0050_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[8] = _0050_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[10] = _0050_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[11] = _0050_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[14] = _0050_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0456_[15] = _0050_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[1] = _0042_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[2] = _0042_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[3] = _0042_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[4] = _0042_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[6] = _0042_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[7] = _0042_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[8] = _0042_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[9] = _0042_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[10] = _0042_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[11] = _0042_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[12] = _0042_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[13] = _0042_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[14] = _0042_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0451_[15] = _0042_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0433_[0] = _0042_[0] ^(* src = "<techmap.v>:263" *) 1'b1;
assign _0433_[1] = _0451_[1] ^(* src = "<techmap.v>:263" *) _0042_[0];
assign _0433_[2] = _0451_[2] ^(* src = "<techmap.v>:263" *) _0492_[1];
assign _0433_[3] = _0451_[3] ^(* src = "<techmap.v>:263" *) _0492_[2];
assign _0433_[4] = _0451_[4] ^(* src = "<techmap.v>:263" *) _0492_[3];
assign _0433_[5] = _0451_[5] ^(* src = "<techmap.v>:263" *) _0492_[4];
assign _0433_[6] = _0451_[6] ^(* src = "<techmap.v>:263" *) _0492_[5];
assign _0433_[7] = _0451_[7] ^(* src = "<techmap.v>:263" *) _0492_[6];
assign _0433_[8] = _0451_[8] ^(* src = "<techmap.v>:263" *) _0492_[7];
assign _0433_[9] = _0451_[9] ^(* src = "<techmap.v>:263" *) _0492_[8];
assign _0433_[10] = _0451_[10] ^(* src = "<techmap.v>:263" *) _0492_[9];
assign _0433_[11] = _0451_[11] ^(* src = "<techmap.v>:263" *) _0492_[10];
assign _0433_[12] = _0451_[12] ^(* src = "<techmap.v>:263" *) _0492_[11];
assign _0433_[13] = _0451_[13] ^(* src = "<techmap.v>:263" *) _0492_[12];
assign _0433_[14] = _0451_[14] ^(* src = "<techmap.v>:263" *) _0492_[13];
assign _0433_[15] = _0451_[15] ^(* src = "<techmap.v>:263" *) _0492_[14];
assign _0451_[5] = _0042_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0177_[0] = wLength[0] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0177_[1] = wLength[1] ^(* src = "<techmap.v>:263" *) wLength[0];
assign _0177_[2] = wLength[2] ^(* src = "<techmap.v>:263" *) _0439_[1];
assign _0177_[3] = wLength[3] ^(* src = "<techmap.v>:263" *) _0439_[2];
assign _0177_[4] = wLength[4] ^(* src = "<techmap.v>:263" *) _0439_[3];
assign _0177_[5] = wLength[5] ^(* src = "<techmap.v>:263" *) _0439_[4];
assign _0177_[6] = wLength[6] ^(* src = "<techmap.v>:263" *) _0439_[5];
assign _0177_[7] = wLength[7] ^(* src = "<techmap.v>:263" *) _0439_[6];
assign _0177_[8] = wLength[8] ^(* src = "<techmap.v>:263" *) _0439_[7];
assign _0177_[9] = wLength[9] ^(* src = "<techmap.v>:263" *) _0439_[8];
assign _0177_[10] = wLength[10] ^(* src = "<techmap.v>:263" *) _0439_[9];
assign _0177_[11] = wLength[11] ^(* src = "<techmap.v>:263" *) _0439_[10];
assign _0177_[12] = wLength[12] ^(* src = "<techmap.v>:263" *) _0439_[11];
assign _0177_[13] = wLength[13] ^(* src = "<techmap.v>:263" *) _0439_[12];
assign _0177_[14] = wLength[14] ^(* src = "<techmap.v>:263" *) _0439_[13];
assign _0177_[15] = wLength[15] ^(* src = "<techmap.v>:263" *) _0439_[14];
assign _0340_[1] = _0025_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[3] = _0025_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[4] = _0025_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[7] = _0025_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[8] = _0025_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[9] = _0025_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[10] = _0025_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[11] = _0025_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[12] = _0025_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0340_[0] = _0025_[0] ^(* src = "<techmap.v>:263" *) 1'b1;
assign _0432_[1] = _0340_[1] ^(* src = "<techmap.v>:263" *) _0025_[0];
assign _0432_[2] = _0340_[2] ^(* src = "<techmap.v>:263" *) _0491_[1];
assign _0432_[3] = _0446_[3] ^(* src = "<techmap.v>:263" *) _0491_[2];
assign _0432_[4] = _0446_[4] ^(* src = "<techmap.v>:263" *) _0491_[3];
assign _0432_[5] = _0446_[5] ^(* src = "<techmap.v>:263" *) _0491_[4];
assign _0432_[6] = _0446_[6] ^(* src = "<techmap.v>:263" *) _0491_[5];
assign _0432_[7] = _0446_[7] ^(* src = "<techmap.v>:263" *) _0491_[6];
assign _0432_[8] = _0446_[8] ^(* src = "<techmap.v>:263" *) _0491_[7];
assign _0432_[9] = _0446_[9] ^(* src = "<techmap.v>:263" *) _0491_[8];
assign _0432_[10] = _0446_[10] ^(* src = "<techmap.v>:263" *) _0491_[9];
assign _0432_[11] = _0446_[11] ^(* src = "<techmap.v>:263" *) _0491_[10];
assign _0432_[12] = _0446_[12] ^(* src = "<techmap.v>:263" *) _0491_[11];
assign _0432_[13] = _0446_[13] ^(* src = "<techmap.v>:263" *) _0491_[12];
assign _0432_[14] = _0446_[14] ^(* src = "<techmap.v>:263" *) _0491_[13];
assign _0432_[15] = _0446_[15] ^(* src = "<techmap.v>:263" *) _0491_[14];
assign _0340_[2] = _0025_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[5] = _0025_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[6] = _0025_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[13] = _0025_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[14] = _0025_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0446_[15] = _0025_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0339_[2] = _0159_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[3] = _0159_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[4] = _0159_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[5] = _0159_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[7] = _0159_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[8] = _0159_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[9] = _0159_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[10] = _0159_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[11] = _0159_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[12] = _0159_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[13] = _0159_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[14] = _0159_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[15] = _0159_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0339_[0] = _0159_[0] ^(* src = "<techmap.v>:263" *) 1'b1;
assign _0431_[1] = _0339_[1] ^(* src = "<techmap.v>:263" *) _0159_[0];
assign _0431_[2] = _0339_[2] ^(* src = "<techmap.v>:263" *) _0490_[1];
assign _0431_[3] = _0481_[3] ^(* src = "<techmap.v>:263" *) _0490_[2];
assign _0431_[4] = _0481_[4] ^(* src = "<techmap.v>:263" *) _0490_[3];
assign _0431_[5] = _0481_[5] ^(* src = "<techmap.v>:263" *) _0490_[4];
assign _0431_[6] = _0481_[6] ^(* src = "<techmap.v>:263" *) _0490_[5];
assign _0431_[7] = _0481_[7] ^(* src = "<techmap.v>:263" *) _0490_[6];
assign _0431_[8] = _0481_[8] ^(* src = "<techmap.v>:263" *) _0490_[7];
assign _0431_[9] = _0481_[9] ^(* src = "<techmap.v>:263" *) _0490_[8];
assign _0431_[10] = _0481_[10] ^(* src = "<techmap.v>:263" *) _0490_[9];
assign _0431_[11] = _0481_[11] ^(* src = "<techmap.v>:263" *) _0490_[10];
assign _0431_[12] = _0481_[12] ^(* src = "<techmap.v>:263" *) _0490_[11];
assign _0431_[13] = _0481_[13] ^(* src = "<techmap.v>:263" *) _0490_[12];
assign _0431_[14] = _0481_[14] ^(* src = "<techmap.v>:263" *) _0490_[13];
assign _0431_[15] = _0481_[15] ^(* src = "<techmap.v>:263" *) _0490_[14];
assign _0339_[1] = _0159_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0481_[6] = _0159_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0336_[2] = _0127_[2] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[4] = _0127_[4] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[5] = _0127_[5] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[6] = _0127_[6] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[8] = _0127_[8] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[10] = _0127_[10] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[12] = _0127_[12] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0336_[0] = _0127_[0] ^(* src = "<techmap.v>:263" *) 1'b1;
assign _0430_[1] = _0336_[1] ^(* src = "<techmap.v>:263" *) _0127_[0];
assign _0430_[2] = _0336_[2] ^(* src = "<techmap.v>:263" *) _0489_[1];
assign _0430_[3] = _0441_[3] ^(* src = "<techmap.v>:263" *) _0489_[2];
assign _0430_[4] = _0441_[4] ^(* src = "<techmap.v>:263" *) _0489_[3];
assign _0430_[5] = _0441_[5] ^(* src = "<techmap.v>:263" *) _0489_[4];
assign _0430_[6] = _0441_[6] ^(* src = "<techmap.v>:263" *) _0489_[5];
assign _0430_[7] = _0441_[7] ^(* src = "<techmap.v>:263" *) _0489_[6];
assign _0430_[8] = _0441_[8] ^(* src = "<techmap.v>:263" *) _0489_[7];
assign _0430_[9] = _0441_[9] ^(* src = "<techmap.v>:263" *) _0489_[8];
assign _0430_[10] = _0441_[10] ^(* src = "<techmap.v>:263" *) _0489_[9];
assign _0430_[11] = _0441_[11] ^(* src = "<techmap.v>:263" *) _0489_[10];
assign _0430_[12] = _0441_[12] ^(* src = "<techmap.v>:263" *) _0489_[11];
assign _0430_[13] = _0441_[13] ^(* src = "<techmap.v>:263" *) _0489_[12];
assign _0430_[14] = _0441_[14] ^(* src = "<techmap.v>:263" *) _0489_[13];
assign _0430_[15] = _0441_[15] ^(* src = "<techmap.v>:263" *) _0489_[14];
assign _0336_[1] = _0127_[1] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[3] = _0127_[3] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[7] = _0127_[7] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[9] = _0127_[9] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[11] = _0127_[11] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[13] = _0127_[13] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[14] = _0127_[14] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0441_[15] = _0127_[15] ^(* src = "<techmap.v>:262" *) 1'b1;
assign _0194_[3] = _0193_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0193_[6];
assign _0194_[2] = _0193_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0193_[4];
assign _0194_[1] = _0193_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0193_[2];
assign _0193_[7] = _0476_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[14];
assign _0193_[6] = _0476_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[12];
assign _0193_[5] = _0476_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[10];
assign _0193_[4] = _0476_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[8];
assign _0193_[3] = _0476_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[6];
assign _0193_[2] = _0476_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[4];
assign _0193_[1] = _0476_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0476_[2];
assign _0702_ = _0195_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0475_[7];
assign _0700_ = _0194_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0475_[3];
assign _0699_ = _0193_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0708_;
assign _0698_ = _0193_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0706_;
assign _0697_ = _0193_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0704_;
assign _0696_ = _0193_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0475_[1];
assign _0695_ = _0476_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[14];
assign _0694_ = _0476_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[12];
assign _0693_ = _0476_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[10];
assign _0692_ = _0476_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[8];
assign _0691_ = _0476_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[6];
assign _0690_ = _0476_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[4];
assign _0689_ = _0476_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[2];
assign _0688_ = _0476_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0475_[0];
assign _0497_[14] = _0100_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0865_;
assign _0497_[12] = _0100_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0864_;
assign _0497_[10] = _0100_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0863_;
assign _0497_[8] = _0100_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0862_;
assign _0497_[6] = _0100_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0861_;
assign _0497_[4] = _0100_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0860_;
assign _0497_[2] = _0100_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0859_;
assign _0497_[13] = _0708_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0858_;
assign _0497_[9] = _0706_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0857_;
assign _0497_[5] = _0704_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0856_;
assign _0497_[11] = _0711_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0855_;
assign _0713_ = _0712_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0701_;
assign _0497_[7] = _0710_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0854_;
assign _0712_ = _0709_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0699_;
assign _0711_ = _0707_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0698_;
assign _0710_ = _0705_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0697_;
assign _0497_[3] = _0703_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0853_;
assign _0497_[1] = _0100_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0852_;
assign _0865_ = _0476_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[13];
assign _0864_ = _0476_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[11];
assign _0863_ = _0476_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[9];
assign _0862_ = _0476_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[7];
assign _0861_ = _0476_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[5];
assign _0860_ = _0476_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[3];
assign _0859_ = _0476_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[1];
assign _0858_ = _0193_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[11];
assign _0857_ = _0193_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[7];
assign _0856_ = _0193_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[3];
assign _0855_ = _0194_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0497_[7];
assign _0195_[1] = _0194_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0194_[2];
assign _0701_ = _0194_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0711_;
assign _0854_ = _0194_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0497_[3];
assign _0853_ = _0193_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0497_[1];
assign _0852_ = _0476_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0100_[0];
assign _0475_[0] = _0100_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0438_[0];
assign _0475_[1] = _0100_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0688_;
assign _0703_ = _0100_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0689_;
assign _0704_ = _0100_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0690_;
assign _0705_ = _0100_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0691_;
assign _0706_ = _0100_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0692_;
assign _0707_ = _0100_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0693_;
assign _0708_ = _0100_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0694_;
assign _0709_ = _0100_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0695_;
assign _0475_[3] = _0703_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0696_;
assign _0475_[7] = _0710_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0700_;
assign _0475_[31] = _0713_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0702_;
assign _0838_ = _0471_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[0];
assign _0663_ = _0471_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[2];
assign _0664_ = _0471_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[4];
assign _0665_ = _0471_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[6];
assign _0666_ = _0471_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[8];
assign _0667_ = _0471_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[10];
assign _0668_ = _0471_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[12];
assign _0669_ = _0471_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0077_[14];
assign _0839_ = _0197_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0496_[1];
assign _0671_ = _0197_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0678_;
assign _0672_ = _0197_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0680_;
assign _0673_ = _0197_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0682_;
assign _0840_ = _0198_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0496_[3];
assign _0675_ = _0198_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0685_;
assign _0197_[1] = _0471_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[2];
assign _0197_[2] = _0471_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[4];
assign _0197_[3] = _0471_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[6];
assign _0197_[4] = _0471_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[8];
assign _0197_[5] = _0471_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[10];
assign _0197_[6] = _0471_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[12];
assign _0197_[7] = _0471_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0471_[14];
assign _0198_[1] = _0197_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0197_[2];
assign _0198_[2] = _0197_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0197_[4];
assign _0198_[3] = _0197_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0197_[6];
assign _0199_[1] = _0198_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0198_[2];
assign _0841_ = _0198_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[7];
assign _0842_ = _0197_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[3];
assign _0843_ = _0197_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[7];
assign _0844_ = _0197_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[11];
assign _0845_ = _0471_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[1];
assign _0846_ = _0471_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[3];
assign _0847_ = _0471_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[5];
assign _0848_ = _0471_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[7];
assign _0849_ = _0471_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[9];
assign _0850_ = _0471_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[11];
assign _0851_ = _0471_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0496_[13];
assign _0496_[1] = _0077_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0838_;
assign _0496_[3] = _0677_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0839_;
assign _0496_[7] = _0684_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0840_;
assign _0496_[11] = _0685_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0841_;
assign _0496_[5] = _0678_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0842_;
assign _0496_[9] = _0680_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0843_;
assign _0496_[13] = _0682_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0844_;
assign _0496_[2] = _0077_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0845_;
assign _0496_[4] = _0077_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0846_;
assign _0496_[6] = _0077_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0847_;
assign _0496_[8] = _0077_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0848_;
assign _0496_[10] = _0077_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0849_;
assign _0496_[12] = _0077_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0850_;
assign _0496_[14] = _0077_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0851_;
assign _0662_ = _0471_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0470_[0];
assign _0670_ = _0197_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0470_[1];
assign _0674_ = _0198_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0470_[3];
assign _0676_ = _0199_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0470_[7];
assign _0470_[0] = _0077_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0437_[0];
assign _0470_[1] = _0077_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0662_;
assign _0677_ = _0077_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0663_;
assign _0678_ = _0077_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0664_;
assign _0679_ = _0077_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0665_;
assign _0680_ = _0077_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0666_;
assign _0681_ = _0077_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0667_;
assign _0682_ = _0077_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0668_;
assign _0683_ = _0077_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0669_;
assign _0470_[3] = _0677_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0670_;
assign _0684_ = _0679_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0671_;
assign _0685_ = _0681_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0672_;
assign _0686_ = _0683_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0673_;
assign _0470_[7] = _0684_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0674_;
assign _0687_ = _0686_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0675_;
assign _0470_[31] = _0687_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0676_;
assign _0824_ = _0466_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[0];
assign _0637_ = _0466_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[2];
assign _0638_ = _0466_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[4];
assign _0639_ = _0466_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[6];
assign _0640_ = _0466_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[8];
assign _0641_ = _0466_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[10];
assign _0642_ = _0466_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[12];
assign _0643_ = _0466_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0070_[14];
assign _0825_ = _0201_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0495_[1];
assign _0826_ = _0202_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0495_[3];
assign _0649_ = _0202_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0659_;
assign _0201_[1] = _0466_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[2];
assign _0201_[2] = _0466_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[4];
assign _0201_[3] = _0466_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[6];
assign _0201_[4] = _0466_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[8];
assign _0201_[5] = _0466_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[10];
assign _0201_[6] = _0466_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[12];
assign _0827_ = _0202_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[7];
assign _0828_ = _0201_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[3];
assign _0829_ = _0201_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[7];
assign _0830_ = _0201_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[11];
assign _0831_ = _0466_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[1];
assign _0832_ = _0466_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[3];
assign _0833_ = _0466_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[5];
assign _0834_ = _0466_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[7];
assign _0835_ = _0466_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[9];
assign _0836_ = _0466_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[11];
assign _0837_ = _0466_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0495_[13];
assign _0495_[1] = _0070_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0824_;
assign _0653_ = _0070_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0639_;
assign _0656_ = _0070_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0642_;
assign _0495_[3] = _0651_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0825_;
assign _0659_ = _0655_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0646_;
assign _0495_[7] = _0658_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0826_;
assign _0661_ = _0660_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0649_;
assign _0495_[11] = _0659_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0827_;
assign _0495_[5] = _0652_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0828_;
assign _0495_[9] = _0654_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0829_;
assign _0495_[13] = _0656_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0830_;
assign _0495_[2] = _0070_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0831_;
assign _0495_[4] = _0070_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0832_;
assign _0495_[6] = _0070_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0833_;
assign _0495_[8] = _0070_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0834_;
assign _0495_[10] = _0070_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0835_;
assign _0495_[12] = _0070_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0836_;
assign _0495_[14] = _0070_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0837_;
assign _0636_ = _0466_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0465_[0];
assign _0644_ = _0201_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0465_[1];
assign _0645_ = _0201_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0652_;
assign _0646_ = _0201_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0654_;
assign _0647_ = _0201_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0656_;
assign _0648_ = _0202_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0465_[3];
assign _0650_ = _0203_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0465_[7];
assign _0201_[7] = _0466_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0466_[14];
assign _0202_[1] = _0201_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0201_[2];
assign _0202_[3] = _0201_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0201_[6];
assign _0203_[1] = _0202_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0202_[2];
assign _0465_[0] = _0070_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0436_[0];
assign _0465_[1] = _0070_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0636_;
assign _0651_ = _0070_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0637_;
assign _0652_ = _0070_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0638_;
assign _0654_ = _0070_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0640_;
assign _0655_ = _0070_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0641_;
assign _0657_ = _0070_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0643_;
assign _0465_[3] = _0651_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0644_;
assign _0658_ = _0653_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0645_;
assign _0660_ = _0657_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0647_;
assign _0465_[7] = _0658_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0648_;
assign _0465_[31] = _0661_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0650_;
assign _0810_ = _0461_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[0];
assign _0613_ = _0461_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[6];
assign _0614_ = _0461_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[8];
assign _0616_ = _0461_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[12];
assign _0811_ = _0205_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0494_[1];
assign _0621_ = _0205_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0630_;
assign _0812_ = _0206_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0494_[3];
assign _0623_ = _0206_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0633_;
assign _0205_[1] = _0461_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[2];
assign _0205_[2] = _0461_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[4];
assign _0205_[4] = _0461_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[8];
assign _0205_[5] = _0461_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[10];
assign _0205_[6] = _0461_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[12];
assign _0205_[7] = _0461_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0461_[14];
assign _0206_[1] = _0205_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0205_[2];
assign _0206_[2] = _0205_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0205_[4];
assign _0206_[3] = _0205_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0205_[6];
assign _0813_ = _0206_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[7];
assign _0814_ = _0205_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[3];
assign _0815_ = _0205_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[7];
assign _0816_ = _0205_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[11];
assign _0817_ = _0461_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[1];
assign _0818_ = _0461_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[3];
assign _0819_ = _0461_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[5];
assign _0820_ = _0461_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[7];
assign _0821_ = _0461_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[9];
assign _0822_ = _0461_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[11];
assign _0823_ = _0461_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0494_[13];
assign _0494_[1] = _0061_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0810_;
assign _0494_[3] = _0625_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0811_;
assign _0632_ = _0627_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0619_;
assign _0633_ = _0629_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0620_;
assign _0494_[7] = _0632_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0812_;
assign _0635_ = _0634_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0623_;
assign _0494_[11] = _0633_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0813_;
assign _0494_[5] = _0626_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0814_;
assign _0494_[9] = _0628_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0815_;
assign _0494_[13] = _0630_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0816_;
assign _0494_[2] = _0061_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0817_;
assign _0494_[4] = _0061_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0818_;
assign _0494_[6] = _0061_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0819_;
assign _0494_[8] = _0061_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0820_;
assign _0494_[10] = _0061_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0821_;
assign _0494_[12] = _0061_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0822_;
assign _0494_[14] = _0061_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0823_;
assign _0610_ = _0461_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0460_[0];
assign _0611_ = _0461_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[2];
assign _0612_ = _0461_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[4];
assign _0615_ = _0461_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[10];
assign _0617_ = _0461_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0061_[14];
assign _0618_ = _0205_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0460_[1];
assign _0619_ = _0205_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0626_;
assign _0620_ = _0205_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0628_;
assign _0622_ = _0206_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0460_[3];
assign _0624_ = _0207_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0460_[7];
assign _0207_[1] = _0206_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0206_[2];
assign _0460_[0] = _0061_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0435_[0];
assign _0460_[1] = _0061_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0610_;
assign _0625_ = _0061_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0611_;
assign _0626_ = _0061_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0612_;
assign _0627_ = _0061_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0613_;
assign _0628_ = _0061_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0614_;
assign _0629_ = _0061_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0615_;
assign _0630_ = _0061_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0616_;
assign _0631_ = _0061_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0617_;
assign _0460_[3] = _0625_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0618_;
assign _0634_ = _0631_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0621_;
assign _0460_[7] = _0632_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0622_;
assign _0460_[31] = _0635_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0624_;
assign _0796_ = _0456_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[0];
assign _0587_ = _0456_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[6];
assign _0797_ = _0209_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0493_[1];
assign _0593_ = _0209_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0600_;
assign _0594_ = _0209_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0602_;
assign _0595_ = _0209_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0604_;
assign _0798_ = _0210_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0493_[3];
assign _0209_[1] = _0456_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0456_[2];
assign _0210_[1] = _0209_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0209_[2];
assign _0210_[3] = _0209_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0209_[6];
assign _0799_ = _0210_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[7];
assign _0800_ = _0209_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[3];
assign _0801_ = _0209_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[7];
assign _0802_ = _0209_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[11];
assign _0803_ = _0456_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[1];
assign _0804_ = _0456_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[3];
assign _0805_ = _0456_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[5];
assign _0806_ = _0456_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[7];
assign _0807_ = _0456_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[9];
assign _0808_ = _0456_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[11];
assign _0809_ = _0456_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0493_[13];
assign _0493_[1] = _0050_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0796_;
assign _0601_ = _0050_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0587_;
assign _0605_ = _0050_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0591_;
assign _0493_[3] = _0599_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0797_;
assign _0608_ = _0605_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0595_;
assign _0493_[7] = _0606_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0798_;
assign _0609_ = _0608_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0597_;
assign _0493_[11] = _0607_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0799_;
assign _0493_[5] = _0600_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0800_;
assign _0493_[9] = _0602_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0801_;
assign _0493_[13] = _0604_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0802_;
assign _0493_[2] = _0050_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0803_;
assign _0493_[4] = _0050_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0804_;
assign _0493_[6] = _0050_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0805_;
assign _0493_[8] = _0050_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0806_;
assign _0493_[10] = _0050_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0807_;
assign _0493_[12] = _0050_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0808_;
assign _0493_[14] = _0050_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0809_;
assign _0584_ = _0456_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0455_[0];
assign _0585_ = _0456_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[2];
assign _0586_ = _0456_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[4];
assign _0588_ = _0456_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[8];
assign _0589_ = _0456_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[10];
assign _0590_ = _0456_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[12];
assign _0591_ = _0456_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0050_[14];
assign _0592_ = _0209_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0455_[1];
assign _0596_ = _0210_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0455_[3];
assign _0597_ = _0210_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0607_;
assign _0598_ = _0211_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0455_[7];
assign _0209_[2] = _0456_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0456_[4];
assign _0209_[3] = _0456_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0456_[6];
assign _0209_[5] = _0456_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0456_[10];
assign _0210_[2] = _0209_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0209_[4];
assign _0211_[1] = _0210_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0210_[2];
assign _0455_[0] = _0050_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0434_[0];
assign _0455_[1] = _0050_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0584_;
assign _0599_ = _0050_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0585_;
assign _0600_ = _0050_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0586_;
assign _0602_ = _0050_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0588_;
assign _0603_ = _0050_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0589_;
assign _0604_ = _0050_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0590_;
assign _0455_[3] = _0599_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0592_;
assign _0606_ = _0601_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0593_;
assign _0607_ = _0603_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0594_;
assign _0455_[7] = _0606_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0596_;
assign _0455_[31] = _0609_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0598_;
assign _0782_ = _0451_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[0];
assign _0559_ = _0451_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[2];
assign _0560_ = _0451_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[4];
assign _0561_ = _0451_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[6];
assign _0562_ = _0451_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[8];
assign _0563_ = _0451_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[10];
assign _0564_ = _0451_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[12];
assign _0783_ = _0213_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0492_[1];
assign _0567_ = _0213_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0574_;
assign _0568_ = _0213_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0576_;
assign _0569_ = _0213_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0578_;
assign _0784_ = _0214_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0492_[3];
assign _0571_ = _0214_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0581_;
assign _0213_[2] = _0451_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[4];
assign _0213_[3] = _0451_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[6];
assign _0213_[4] = _0451_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[8];
assign _0213_[5] = _0451_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[10];
assign _0213_[6] = _0451_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[12];
assign _0213_[7] = _0451_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[14];
assign _0214_[2] = _0213_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0213_[4];
assign _0214_[3] = _0213_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0213_[6];
assign _0215_[1] = _0214_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0214_[2];
assign _0785_ = _0214_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[7];
assign _0786_ = _0213_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[3];
assign _0787_ = _0213_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[7];
assign _0788_ = _0213_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[11];
assign _0789_ = _0451_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[1];
assign _0790_ = _0451_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[3];
assign _0791_ = _0451_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[5];
assign _0792_ = _0451_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[7];
assign _0793_ = _0451_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[9];
assign _0794_ = _0451_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[11];
assign _0795_ = _0451_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0492_[13];
assign _0492_[1] = _0042_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0782_;
assign _0575_ = _0042_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0561_;
assign _0576_ = _0042_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0562_;
assign _0492_[3] = _0573_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0783_;
assign _0492_[7] = _0580_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0784_;
assign _0492_[11] = _0581_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0785_;
assign _0492_[5] = _0574_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0786_;
assign _0492_[9] = _0576_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0787_;
assign _0492_[13] = _0578_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0788_;
assign _0492_[2] = _0042_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0789_;
assign _0492_[4] = _0042_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0790_;
assign _0492_[6] = _0042_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0791_;
assign _0492_[8] = _0042_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0792_;
assign _0492_[10] = _0042_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0793_;
assign _0492_[12] = _0042_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0794_;
assign _0492_[14] = _0042_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0795_;
assign _0558_ = _0451_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0450_[0];
assign _0565_ = _0451_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0042_[14];
assign _0566_ = _0213_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0450_[1];
assign _0570_ = _0214_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0450_[3];
assign _0572_ = _0215_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0450_[7];
assign _0213_[1] = _0451_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0451_[2];
assign _0214_[1] = _0213_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0213_[2];
assign _0450_[0] = _0042_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0433_[0];
assign _0450_[1] = _0042_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0558_;
assign _0573_ = _0042_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0559_;
assign _0574_ = _0042_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0560_;
assign _0577_ = _0042_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0563_;
assign _0578_ = _0042_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0564_;
assign _0579_ = _0042_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0565_;
assign _0450_[3] = _0573_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0566_;
assign _0580_ = _0575_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0567_;
assign _0581_ = _0577_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0568_;
assign _0582_ = _0579_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0569_;
assign _0450_[7] = _0580_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0570_;
assign _0583_ = _0582_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0571_;
assign _0450_[31] = _0583_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0572_;
assign _0439_[1] = wLength[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) wLength[0];
assign _0439_[3] = _0498_ &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0439_[1];
assign _0439_[7] = _0504_ &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0439_[3];
assign _0498_ = wLength[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[2];
assign _0499_ = wLength[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[4];
assign _0500_ = wLength[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[6];
assign _0501_ = wLength[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[8];
assign _0502_ = wLength[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[10];
assign _0503_ = wLength[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) wLength[12];
assign _0504_ = _0500_ &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0499_;
assign _0505_ = _0502_ &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0501_;
assign _0439_[11] = _0505_ &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[7];
assign _0439_[5] = _0499_ &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[3];
assign _0439_[9] = _0501_ &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[7];
assign _0439_[13] = _0503_ &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[11];
assign _0439_[2] = wLength[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[1];
assign _0439_[4] = wLength[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[3];
assign _0439_[6] = wLength[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[5];
assign _0439_[8] = wLength[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[7];
assign _0439_[10] = wLength[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[9];
assign _0439_[12] = wLength[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[11];
assign _0439_[14] = wLength[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0439_[13];
assign _0768_ = _0340_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[0];
assign _0534_ = _0446_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[4];
assign _0535_ = _0446_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[6];
assign _0769_ = _0217_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0491_[1];
assign _0541_ = _0217_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0548_;
assign _0770_ = _0218_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0491_[3];
assign _0545_ = _0218_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0555_;
assign _0771_ = _0218_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[7];
assign _0772_ = _0217_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[3];
assign _0773_ = _0217_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[7];
assign _0774_ = _0217_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[11];
assign _0775_ = _0340_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[1];
assign _0776_ = _0446_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[3];
assign _0777_ = _0446_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[5];
assign _0778_ = _0446_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[7];
assign _0779_ = _0446_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[9];
assign _0780_ = _0446_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[11];
assign _0781_ = _0446_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0491_[13];
assign _0491_[1] = _0025_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0768_;
assign _0547_ = _0025_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0533_;
assign _0548_ = _0025_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0534_;
assign _0550_ = _0025_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0536_;
assign _0551_ = _0025_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0537_;
assign _0553_ = _0025_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0539_;
assign _0491_[3] = _0547_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0769_;
assign _0556_ = _0553_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0543_;
assign _0491_[7] = _0554_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0770_;
assign _0491_[11] = _0555_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0771_;
assign _0491_[5] = _0548_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0772_;
assign _0491_[9] = _0550_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0773_;
assign _0491_[13] = _0552_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0774_;
assign _0491_[2] = _0025_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0775_;
assign _0491_[4] = _0025_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0776_;
assign _0491_[6] = _0025_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0777_;
assign _0491_[8] = _0025_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0778_;
assign _0491_[10] = _0025_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0779_;
assign _0491_[12] = _0025_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0780_;
assign _0491_[14] = _0025_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0781_;
assign _0532_ = _0340_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0445_[0];
assign _0533_ = _0446_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[2];
assign _0536_ = _0446_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[8];
assign _0537_ = _0446_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[10];
assign _0538_ = _0446_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[12];
assign _0539_ = _0446_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0025_[14];
assign _0540_ = _0217_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0445_[1];
assign _0542_ = _0217_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0550_;
assign _0543_ = _0217_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0552_;
assign _0544_ = _0218_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0445_[3];
assign _0546_ = _0219_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0445_[7];
assign _0217_[1] = _0446_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0340_[2];
assign _0217_[2] = _0446_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[4];
assign _0217_[3] = _0446_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[6];
assign _0217_[4] = _0446_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[8];
assign _0217_[5] = _0446_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[10];
assign _0217_[6] = _0446_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[12];
assign _0217_[7] = _0446_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0446_[14];
assign _0218_[1] = _0217_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0217_[2];
assign _0218_[2] = _0217_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0217_[4];
assign _0218_[3] = _0217_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0217_[6];
assign _0445_[0] = _0025_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0340_[0];
assign _0445_[1] = _0025_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0532_;
assign _0549_ = _0025_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0535_;
assign _0552_ = _0025_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0538_;
assign _0445_[3] = _0547_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0540_;
assign _0554_ = _0549_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0541_;
assign _0555_ = _0551_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0542_;
assign _0445_[7] = _0554_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0544_;
assign _0557_ = _0556_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0545_;
assign _0445_[31] = _0557_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0546_;
assign _0754_ = _0339_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[0];
assign _0715_ = _0481_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[2];
assign _0717_ = _0481_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[6];
assign _0721_ = _0481_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[14];
assign _0755_ = _0221_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0490_[1];
assign _0723_ = _0221_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0730_;
assign _0724_ = _0221_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0732_;
assign _0756_ = _0222_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0490_[3];
assign _0727_ = _0222_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0737_;
assign _0221_[2] = _0481_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[4];
assign _0221_[6] = _0481_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[12];
assign _0221_[7] = _0481_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[14];
assign _0222_[2] = _0221_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0221_[4];
assign _0757_ = _0222_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[7];
assign _0758_ = _0221_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[3];
assign _0759_ = _0221_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[7];
assign _0760_ = _0221_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[11];
assign _0761_ = _0339_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[1];
assign _0762_ = _0481_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[3];
assign _0763_ = _0481_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[5];
assign _0764_ = _0481_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[7];
assign _0765_ = _0481_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[9];
assign _0766_ = _0481_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[11];
assign _0767_ = _0481_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0490_[13];
assign _0490_[1] = _0159_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0754_;
assign _0729_ = _0159_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0715_;
assign _0730_ = _0159_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0716_;
assign _0731_ = _0159_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0717_;
assign _0733_ = _0159_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0719_;
assign _0734_ = _0159_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0720_;
assign _0735_ = _0159_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0721_;
assign _0490_[3] = _0729_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0755_;
assign _0736_ = _0731_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0723_;
assign _0737_ = _0733_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0724_;
assign _0738_ = _0735_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0725_;
assign _0490_[7] = _0736_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0756_;
assign _0739_ = _0738_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0727_;
assign _0490_[11] = _0737_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0757_;
assign _0490_[5] = _0730_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0758_;
assign _0490_[9] = _0732_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0759_;
assign _0490_[13] = _0734_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0760_;
assign _0490_[2] = _0159_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0761_;
assign _0490_[4] = _0159_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0762_;
assign _0490_[6] = _0159_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0763_;
assign _0490_[8] = _0159_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0764_;
assign _0490_[10] = _0159_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0765_;
assign _0490_[12] = _0159_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0766_;
assign _0490_[14] = _0159_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0767_;
assign _0714_ = _0339_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0480_[0];
assign _0716_ = _0481_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[4];
assign _0718_ = _0481_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[8];
assign _0719_ = _0481_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[10];
assign _0720_ = _0481_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0159_[12];
assign _0722_ = _0221_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0480_[1];
assign _0725_ = _0221_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0734_;
assign _0726_ = _0222_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0480_[3];
assign _0728_ = _0223_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0480_[7];
assign _0221_[1] = _0481_[3] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0339_[2];
assign _0221_[3] = _0481_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[6];
assign _0221_[4] = _0481_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[8];
assign _0221_[5] = _0481_[11] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0481_[10];
assign _0480_[0] = _0159_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0339_[0];
assign _0480_[1] = _0159_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0714_;
assign _0732_ = _0159_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0718_;
assign _0480_[3] = _0729_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0722_;
assign _0480_[7] = _0736_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0726_;
assign _0480_[31] = _0739_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0728_;
assign _0740_ = _0336_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[0];
assign _0512_ = _0441_[13] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[12];
assign _0741_ = _0225_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0489_[1];
assign _0742_ = _0226_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0489_[3];
assign _0519_ = _0226_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0529_;
assign _0226_[3] = _0225_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0225_[6];
assign _0743_ = _0226_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[7];
assign _0744_ = _0225_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[3];
assign _0745_ = _0225_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[7];
assign _0746_ = _0225_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[11];
assign _0747_ = _0336_[2] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[1];
assign _0748_ = _0441_[4] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[3];
assign _0749_ = _0441_[6] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[5];
assign _0750_ = _0441_[8] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[7];
assign _0751_ = _0441_[10] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[9];
assign _0752_ = _0441_[12] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[11];
assign _0753_ = _0441_[14] &(* src = "<techmap.v>:260|<techmap.v>:229" *) _0489_[13];
assign _0489_[1] = _0127_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0740_;
assign _0521_ = _0127_[3] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0507_;
assign _0523_ = _0127_[7] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0509_;
assign _0526_ = _0127_[13] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0512_;
assign _0527_ = _0127_[15] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0513_;
assign _0489_[3] = _0521_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0741_;
assign _0530_ = _0527_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0517_;
assign _0489_[7] = _0528_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0742_;
assign _0489_[11] = _0529_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0743_;
assign _0489_[5] = _0522_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0744_;
assign _0489_[9] = _0524_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0745_;
assign _0489_[13] = _0526_ |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0746_;
assign _0489_[2] = _0127_[2] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0747_;
assign _0489_[4] = _0127_[4] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0748_;
assign _0489_[6] = _0127_[6] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0749_;
assign _0489_[8] = _0127_[8] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0750_;
assign _0489_[10] = _0127_[10] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0751_;
assign _0489_[12] = _0127_[12] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0752_;
assign _0489_[14] = _0127_[14] |(* src = "<techmap.v>:260|<techmap.v>:229" *) _0753_;
assign _0506_ = _0336_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0440_[0];
assign _0507_ = _0441_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[2];
assign _0508_ = _0441_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[4];
assign _0509_ = _0441_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[6];
assign _0510_ = _0441_[9] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[8];
assign _0511_ = _0441_[11] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[10];
assign _0513_ = _0441_[15] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0127_[14];
assign _0514_ = _0225_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0440_[1];
assign _0515_ = _0225_[3] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0522_;
assign _0516_ = _0225_[5] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0524_;
assign _0517_ = _0225_[7] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0526_;
assign _0518_ = _0226_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0440_[3];
assign _0520_ = _0227_[1] &(* src = "<techmap.v>:260|<techmap.v>:221" *) _0440_[7];
assign _0225_[3] = _0441_[7] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0441_[6];
assign _0225_[4] = _0441_[9] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0441_[8];
assign _0225_[6] = _0441_[13] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0441_[12];
assign _0225_[7] = _0441_[15] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0441_[14];
assign _0226_[2] = _0225_[5] &(* src = "<techmap.v>:260|<techmap.v>:222" *) _0225_[4];
assign _0440_[0] = _0127_[0] |(* src = "<techmap.v>:260|<techmap.v>:212" *) _0336_[0];
assign _0440_[1] = _0127_[1] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0506_;
assign _0522_ = _0127_[5] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0508_;
assign _0524_ = _0127_[9] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0510_;
assign _0525_ = _0127_[11] |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0511_;
assign _0440_[3] = _0521_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0514_;
assign _0528_ = _0523_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0515_;
assign _0529_ = _0525_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0516_;
assign _0440_[7] = _0528_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0518_;
assign _0531_ = _0530_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0519_;
assign _0440_[31] = _0531_ |(* src = "<techmap.v>:260|<techmap.v>:221" *) _0520_;
assign _0330_[0] = bmRequestType[0] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) 1'b1;
assign _0330_[5] = bmRequestType[5] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:111" *) 1'b1;
assign _0334_[3] = bRequest[3] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:156" *) 1'b1;
assign _0331_[0] = bRequest[0] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) 1'b1;
assign _0332_[1] = bRequest[1] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) 1'b1;
assign _0333_[2] = bRequest[2] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) 1'b1;
assign _0335_[7] = bRequest[7] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:188" *) 1'b1;
assign _0337_[0] = wValue[0] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:263" *) 1'b1;
assign _0338_[1] = wValue[1] ^(* src = "/home/yoe/PROYECTO/bin/enpoint/Control/control.v:268" *) 1'b1;
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 21:16:09 07/10/2009
// Design Name:
// Module Name: spi
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module spi(
input clk,
input SCK,
input MOSI,
inout MISO,
input SSEL,
output cmd_ready,
output param_ready,
output [7:0] cmd_data,
output [7:0] param_data,
output endmessage,
output startmessage,
input [7:0] input_data,
output [31:0] byte_cnt,
output [2:0] bit_cnt
);
reg [7:0] cmd_data_r;
reg [7:0] param_data_r;
reg [2:0] SSELr;
reg [2:0] SSELSCKr;
always @(posedge clk) SSELr <= {SSELr[1:0], SSEL};
always @(posedge SCK) SSELSCKr <= {SSELSCKr[1:0], SSEL};
wire SSEL_inactive = SSELr[1];
wire SSEL_active = ~SSELr[1]; // SSEL is active low
wire SSEL_startmessage = (SSELr[2:1]==2'b10); // message starts at falling edge
wire SSEL_endmessage = (SSELr[2:1]==2'b01); // message stops at rising edge
assign endmessage = SSEL_endmessage;
assign startmessage = SSEL_startmessage;
// bit count for one SPI byte + byte count for the message
reg [2:0] bitcnt;
initial bitcnt = 3'b000;
wire bitcnt_msb = bitcnt[2];
reg [2:0] bitcnt_wrap_r;
always @(posedge clk) bitcnt_wrap_r <= {bitcnt_wrap_r[1:0], bitcnt_msb};
wire byte_received_sync = (bitcnt_wrap_r[2:1] == 2'b10);
reg [31:0] byte_cnt_r;
reg byte_received; // high when a byte has been received
reg [7:0] byte_data_received;
assign bit_cnt = bitcnt;
always @(posedge SCK) begin
if(SSELSCKr[1]) bitcnt <= 3'b000;
else bitcnt <= bitcnt + 3'b001;
end
always @(posedge SCK) begin
if(~SSELSCKr[1])
byte_data_received <= {byte_data_received[6:0], MOSI};
if(~SSELSCKr[1] && bitcnt==3'b111)
byte_received <= 1'b1;
else byte_received <= 1'b0;
end
//reg [2:0] byte_received_r;
//always @(posedge clk) byte_received_r <= {byte_received_r[1:0], byte_received};
//wire byte_received_sync = (byte_received_r[2:1] == 2'b01);
always @(posedge clk) begin
if(SSEL_inactive)
byte_cnt_r <= 16'h0000;
else if(byte_received_sync)
byte_cnt_r <= byte_cnt_r + 16'h0001;
end
reg [7:0] byte_data_sent;
assign MISO = ~SSEL ? input_data[7-bitcnt] : 1'bZ; // send MSB first
reg cmd_ready_r;
reg param_ready_r;
reg cmd_ready_r2;
reg param_ready_r2;
assign cmd_ready = cmd_ready_r;
assign param_ready = param_ready_r;
assign cmd_data = cmd_data_r;
assign param_data = param_data_r;
assign byte_cnt = byte_cnt_r;
always @(posedge clk) cmd_ready_r2 = byte_received_sync && byte_cnt_r == 32'h0;
always @(posedge clk) param_ready_r2 = byte_received_sync && byte_cnt_r > 32'h0;
// fill registers
always @(posedge clk) begin
if (SSEL_startmessage)
cmd_data_r <= 8'h00;
else if(cmd_ready_r2)
cmd_data_r <= byte_data_received;
else if(param_ready_r2)
param_data_r <= byte_data_received;
end
// delay ready signals by one clock
always @(posedge clk) begin
cmd_ready_r <= cmd_ready_r2;
param_ready_r <= param_ready_r2;
end
endmodule
|
// ***************** DELAY_CALC *********************************************
// v1.0 testbenched
//
// This module simply takes in three delay values and a synchronous strobe.
// When the strobe arrives, the 3 values are combined to calculate the tap setting
// of two IODELAY elements, with the two results being registered and stored
//
// data_offset_delay is used to vary the phase of the the data delays versus drdy
// In this way, constant offsets can be removed or sampling window measured
//
// For the ADC data IDELAYS, the formula is:
// data_offset_delay + delay_modifier - scan_delay
//
// For the ADC data and data ready IDELAYS, the formula is:
// delay_modifier - scan_delay
//
// Added a 32 count constant offset to data and drdy delays to allow -ve
// delay modifier
//
// For the ADC clock output ODELAY, the value is just scan_delay
//
// As scan_delay is increased, the phase between the logic 357 and the adc data
// is therefore preserved. If the phase drifts (temperature etc), then this is
// detected by the alignment monitor module which updates delay_modifier
//
// First, the register adc_data_delay_2s is written to. This contains the 2's comp
// result of the the arithmetic (9-bit). The output is based on this register,
// and saturates at 0 - 63.
module delay_calc (
clk40,
rst,
data_offset_delay,
delay_modifier,
scan_delay,
strb,
adc_clock_delay,
adc_data_delay,
adc_drdy_delay,
saturated
);
input clk40;
input rst;
input [6:0] data_offset_delay;
input [6:0] delay_modifier;
input [5:0] scan_delay;
input strb;
output [5:0] adc_clock_delay;
output [5:0] adc_data_delay;
output [5:0] adc_drdy_delay;
output saturated;
//Internal registers
reg [5:0] adc_clock_delay;
reg [7:0] adc_data_delay_2s;
reg [7:0] adc_drdy_delay_2s;
always @(posedge clk40) begin
if (rst) begin
adc_clock_delay <= 0;
adc_data_delay_2s <= 0;
adc_drdy_delay_2s <= 0;
end else begin
if (strb) begin
//Calculate the output delay values
//Note that data_offset_delay is signed and scan is unsigned, delay_modifier is twos complement
//The scan_delay is flipped to be negative here
//Adding together gives twos complement number from -127 to 126 (8 bit)
//therefore must pad the other numbers to 8-bit for the maths to work
//The 32 sets a middlepoint of the idelay as default
adc_data_delay_2s <= 8'd32 + {data_offset_delay[6],data_offset_delay} + {delay_modifier[6],delay_modifier} + (8'b1 + ~scan_delay);
adc_drdy_delay_2s <= 8'd32 + {delay_modifier[6],delay_modifier} + (8'b1 + ~scan_delay);
adc_clock_delay <= scan_delay;
end
end
end
//Check for saturation
assign adc_data_delay = (adc_data_delay_2s[7] ? 6'b0 : ( (adc_data_delay_2s[6:0] > 6'd63) ? 6'd63 : adc_data_delay_2s[5:0]));
assign adc_drdy_delay = (adc_drdy_delay_2s[7] ? 6'b0 : ( (adc_drdy_delay_2s[6:0] > 6'd63) ? 6'd63 : adc_drdy_delay_2s[5:0]));
assign saturated = ( (adc_data_delay_2s[7] ? 1 : ( (adc_data_delay_2s[6:0] > 6'd63) ? 1 : 0)) ||
(adc_drdy_delay_2s[7] ? 1 : ( (adc_drdy_delay_2s[6:0] > 6'd63) ? 1 : 0)) );
endmodule |
//////////////////////////////////////////////////////////////////////
//// ////
//// OR1200's 32x32 multiply for ASIC ////
//// ////
//// This file is part of the OpenRISC 1200 project ////
//// http://www.opencores.org/project,or1k ////
//// ////
//// Description ////
//// 32x32 multiply for ASIC ////
//// ////
//// To Do: ////
//// - make it smaller and faster ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// $Log: or1200_amultp2_32x32.v,v $
// Revision 2.0 2010/06/30 11:00:00 ORSoC
// No update
module PP_LOW ( ONEPOS, ONENEG, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = (ONEPOS & INA) | (ONENEG & INB) | TWONEG;
endmodule
module PP_MIDDLE ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, INC, IND, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
input INC;
input IND;
output PPBIT;
assign PPBIT = ~ (( ~ (INA & TWOPOS)) & ( ~ (INB & TWONEG)) & ( ~ (INC & ONEPOS)) & ( ~ (IND & ONENEG)));
endmodule
module PP_HIGH ( ONEPOS, ONENEG, TWOPOS, TWONEG, INA, INB, PPBIT );
input ONEPOS;
input ONENEG;
input TWOPOS;
input TWONEG;
input INA;
input INB;
output PPBIT;
assign PPBIT = ~ ((INA & ONEPOS) | (INB & ONENEG) | (INA & TWOPOS) | (INB & TWONEG));
endmodule
module R_GATE ( INA, INB, INC, PPBIT );
input INA;
input INB;
input INC;
output PPBIT;
assign PPBIT = ( ~ (INA & INB)) & INC;
endmodule
module DECODER ( INA, INB, INC, TWOPOS, TWONEG, ONEPOS, ONENEG );
input INA;
input INB;
input INC;
output TWOPOS;
output TWONEG;
output ONEPOS;
output ONENEG;
assign TWOPOS = ~ ( ~ (INA & INB & ( ~ INC)));
assign TWONEG = ~ ( ~ (( ~ INA) & ( ~ INB) & INC));
assign ONEPOS = (( ~ INA) & INB & ( ~ INC)) | (( ~ INC) & ( ~ INB) & INA);
assign ONENEG = (INA & ( ~ INB) & INC) | (INC & INB & ( ~ INA));
endmodule
module BOOTHCODER_33_32 ( OPA, OPB, SUMMAND );
input [0:32] OPA;
input [0:31] OPB;
output [0:575] SUMMAND;
wire [0:32] INV_MULTIPLICAND;
wire [0:63] INT_MULTIPLIER;
wire LOGIC_ONE, LOGIC_ZERO;
assign LOGIC_ONE = 1;
assign LOGIC_ZERO = 0;
DECODER DEC_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) );
assign INV_MULTIPLICAND[0] = ~ OPA[0];
PP_LOW PPL_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[0]) );
R_GATE RGATE_0 (.INA (LOGIC_ZERO) , .INB (OPB[0]) , .INC (OPB[1]) , .PPBIT (SUMMAND[1]) );
assign INV_MULTIPLICAND[1] = ~ OPA[1];
PP_MIDDLE PPM_0 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[2]) );
assign INV_MULTIPLICAND[2] = ~ OPA[2];
PP_MIDDLE PPM_1 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[3]) );
assign INV_MULTIPLICAND[3] = ~ OPA[3];
PP_MIDDLE PPM_2 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[6]) );
assign INV_MULTIPLICAND[4] = ~ OPA[4];
PP_MIDDLE PPM_3 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[8]) );
assign INV_MULTIPLICAND[5] = ~ OPA[5];
PP_MIDDLE PPM_4 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[12]) );
assign INV_MULTIPLICAND[6] = ~ OPA[6];
PP_MIDDLE PPM_5 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[15]) );
assign INV_MULTIPLICAND[7] = ~ OPA[7];
PP_MIDDLE PPM_6 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[20]) );
assign INV_MULTIPLICAND[8] = ~ OPA[8];
PP_MIDDLE PPM_7 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[24]) );
assign INV_MULTIPLICAND[9] = ~ OPA[9];
PP_MIDDLE PPM_8 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[30]) );
assign INV_MULTIPLICAND[10] = ~ OPA[10];
PP_MIDDLE PPM_9 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[35]) );
assign INV_MULTIPLICAND[11] = ~ OPA[11];
PP_MIDDLE PPM_10 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[42]) );
assign INV_MULTIPLICAND[12] = ~ OPA[12];
PP_MIDDLE PPM_11 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[48]) );
assign INV_MULTIPLICAND[13] = ~ OPA[13];
PP_MIDDLE PPM_12 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[56]) );
assign INV_MULTIPLICAND[14] = ~ OPA[14];
PP_MIDDLE PPM_13 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[63]) );
assign INV_MULTIPLICAND[15] = ~ OPA[15];
PP_MIDDLE PPM_14 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[72]) );
assign INV_MULTIPLICAND[16] = ~ OPA[16];
PP_MIDDLE PPM_15 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[80]) );
assign INV_MULTIPLICAND[17] = ~ OPA[17];
PP_MIDDLE PPM_16 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[90]) );
assign INV_MULTIPLICAND[18] = ~ OPA[18];
PP_MIDDLE PPM_17 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[99]) );
assign INV_MULTIPLICAND[19] = ~ OPA[19];
PP_MIDDLE PPM_18 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[110]) );
assign INV_MULTIPLICAND[20] = ~ OPA[20];
PP_MIDDLE PPM_19 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[120]) );
assign INV_MULTIPLICAND[21] = ~ OPA[21];
PP_MIDDLE PPM_20 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[132]) );
assign INV_MULTIPLICAND[22] = ~ OPA[22];
PP_MIDDLE PPM_21 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[143]) );
assign INV_MULTIPLICAND[23] = ~ OPA[23];
PP_MIDDLE PPM_22 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[156]) );
assign INV_MULTIPLICAND[24] = ~ OPA[24];
PP_MIDDLE PPM_23 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[168]) );
assign INV_MULTIPLICAND[25] = ~ OPA[25];
PP_MIDDLE PPM_24 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[182]) );
assign INV_MULTIPLICAND[26] = ~ OPA[26];
PP_MIDDLE PPM_25 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[195]) );
assign INV_MULTIPLICAND[27] = ~ OPA[27];
PP_MIDDLE PPM_26 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[210]) );
assign INV_MULTIPLICAND[28] = ~ OPA[28];
PP_MIDDLE PPM_27 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[224]) );
assign INV_MULTIPLICAND[29] = ~ OPA[29];
PP_MIDDLE PPM_28 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[240]) );
assign INV_MULTIPLICAND[30] = ~ OPA[30];
PP_MIDDLE PPM_29 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[255]) );
assign INV_MULTIPLICAND[31] = ~ OPA[31];
PP_MIDDLE PPM_30 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[272]) );
assign INV_MULTIPLICAND[32] = ~ OPA[32];
PP_MIDDLE PPM_31 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[288]) );
PP_HIGH PPH_0 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[0]) , .TWONEG (INT_MULTIPLIER[1]) , .ONEPOS (INT_MULTIPLIER[2]) , .ONENEG (INT_MULTIPLIER[3]) , .PPBIT (SUMMAND[304]) );
assign SUMMAND[305] = 1;
DECODER DEC_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) );
PP_LOW PPL_1 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[4]) );
R_GATE RGATE_1 (.INA (OPB[1]) , .INB (OPB[2]) , .INC (OPB[3]) , .PPBIT (SUMMAND[5]) );
PP_MIDDLE PPM_32 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[7]) );
PP_MIDDLE PPM_33 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[9]) );
PP_MIDDLE PPM_34 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[13]) );
PP_MIDDLE PPM_35 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[16]) );
PP_MIDDLE PPM_36 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[21]) );
PP_MIDDLE PPM_37 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[25]) );
PP_MIDDLE PPM_38 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[31]) );
PP_MIDDLE PPM_39 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[36]) );
PP_MIDDLE PPM_40 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[43]) );
PP_MIDDLE PPM_41 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[49]) );
PP_MIDDLE PPM_42 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[57]) );
PP_MIDDLE PPM_43 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[64]) );
PP_MIDDLE PPM_44 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[73]) );
PP_MIDDLE PPM_45 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[81]) );
PP_MIDDLE PPM_46 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[91]) );
PP_MIDDLE PPM_47 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[100]) );
PP_MIDDLE PPM_48 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[111]) );
PP_MIDDLE PPM_49 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[121]) );
PP_MIDDLE PPM_50 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[133]) );
PP_MIDDLE PPM_51 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[144]) );
PP_MIDDLE PPM_52 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[157]) );
PP_MIDDLE PPM_53 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[169]) );
PP_MIDDLE PPM_54 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[183]) );
PP_MIDDLE PPM_55 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[196]) );
PP_MIDDLE PPM_56 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[211]) );
PP_MIDDLE PPM_57 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[225]) );
PP_MIDDLE PPM_58 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[241]) );
PP_MIDDLE PPM_59 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[256]) );
PP_MIDDLE PPM_60 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[273]) );
PP_MIDDLE PPM_61 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[289]) );
PP_MIDDLE PPM_62 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[306]) );
PP_MIDDLE PPM_63 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[321]) );
assign SUMMAND[322] = LOGIC_ONE;
PP_HIGH PPH_1 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[4]) , .TWONEG (INT_MULTIPLIER[5]) , .ONEPOS (INT_MULTIPLIER[6]) , .ONENEG (INT_MULTIPLIER[7]) , .PPBIT (SUMMAND[337]) );
DECODER DEC_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) );
PP_LOW PPL_2 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[10]) );
R_GATE RGATE_2 (.INA (OPB[3]) , .INB (OPB[4]) , .INC (OPB[5]) , .PPBIT (SUMMAND[11]) );
PP_MIDDLE PPM_64 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[14]) );
PP_MIDDLE PPM_65 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[17]) );
PP_MIDDLE PPM_66 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[22]) );
PP_MIDDLE PPM_67 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[26]) );
PP_MIDDLE PPM_68 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[32]) );
PP_MIDDLE PPM_69 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[37]) );
PP_MIDDLE PPM_70 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[44]) );
PP_MIDDLE PPM_71 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[50]) );
PP_MIDDLE PPM_72 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[58]) );
PP_MIDDLE PPM_73 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[65]) );
PP_MIDDLE PPM_74 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[74]) );
PP_MIDDLE PPM_75 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[82]) );
PP_MIDDLE PPM_76 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[92]) );
PP_MIDDLE PPM_77 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[101]) );
PP_MIDDLE PPM_78 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[112]) );
PP_MIDDLE PPM_79 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[122]) );
PP_MIDDLE PPM_80 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[134]) );
PP_MIDDLE PPM_81 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[145]) );
PP_MIDDLE PPM_82 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[158]) );
PP_MIDDLE PPM_83 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[170]) );
PP_MIDDLE PPM_84 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[184]) );
PP_MIDDLE PPM_85 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[197]) );
PP_MIDDLE PPM_86 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[212]) );
PP_MIDDLE PPM_87 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[226]) );
PP_MIDDLE PPM_88 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[242]) );
PP_MIDDLE PPM_89 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[257]) );
PP_MIDDLE PPM_90 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[274]) );
PP_MIDDLE PPM_91 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[290]) );
PP_MIDDLE PPM_92 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[307]) );
PP_MIDDLE PPM_93 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[323]) );
PP_MIDDLE PPM_94 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[338]) );
PP_MIDDLE PPM_95 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[352]) );
assign SUMMAND[353] = LOGIC_ONE;
PP_HIGH PPH_2 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[8]) , .TWONEG (INT_MULTIPLIER[9]) , .ONEPOS (INT_MULTIPLIER[10]) , .ONENEG (INT_MULTIPLIER[11]) , .PPBIT (SUMMAND[367]) );
DECODER DEC_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) );
PP_LOW PPL_3 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[18]) );
R_GATE RGATE_3 (.INA (OPB[5]) , .INB (OPB[6]) , .INC (OPB[7]) , .PPBIT (SUMMAND[19]) );
PP_MIDDLE PPM_96 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[23]) );
PP_MIDDLE PPM_97 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[27]) );
PP_MIDDLE PPM_98 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[33]) );
PP_MIDDLE PPM_99 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[38]) );
PP_MIDDLE PPM_100 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[45]) );
PP_MIDDLE PPM_101 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[51]) );
PP_MIDDLE PPM_102 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[59]) );
PP_MIDDLE PPM_103 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[66]) );
PP_MIDDLE PPM_104 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[75]) );
PP_MIDDLE PPM_105 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[83]) );
PP_MIDDLE PPM_106 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[93]) );
PP_MIDDLE PPM_107 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[102]) );
PP_MIDDLE PPM_108 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[113]) );
PP_MIDDLE PPM_109 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[123]) );
PP_MIDDLE PPM_110 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[135]) );
PP_MIDDLE PPM_111 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[146]) );
PP_MIDDLE PPM_112 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[159]) );
PP_MIDDLE PPM_113 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[171]) );
PP_MIDDLE PPM_114 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[185]) );
PP_MIDDLE PPM_115 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[198]) );
PP_MIDDLE PPM_116 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[213]) );
PP_MIDDLE PPM_117 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[227]) );
PP_MIDDLE PPM_118 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[243]) );
PP_MIDDLE PPM_119 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[258]) );
PP_MIDDLE PPM_120 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[275]) );
PP_MIDDLE PPM_121 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[291]) );
PP_MIDDLE PPM_122 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[308]) );
PP_MIDDLE PPM_123 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[324]) );
PP_MIDDLE PPM_124 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[339]) );
PP_MIDDLE PPM_125 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[354]) );
PP_MIDDLE PPM_126 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[368]) );
PP_MIDDLE PPM_127 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[381]) );
assign SUMMAND[382] = LOGIC_ONE;
PP_HIGH PPH_3 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[12]) , .TWONEG (INT_MULTIPLIER[13]) , .ONEPOS (INT_MULTIPLIER[14]) , .ONENEG (INT_MULTIPLIER[15]) , .PPBIT (SUMMAND[395]) );
DECODER DEC_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) );
PP_LOW PPL_4 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[28]) );
R_GATE RGATE_4 (.INA (OPB[7]) , .INB (OPB[8]) , .INC (OPB[9]) , .PPBIT (SUMMAND[29]) );
PP_MIDDLE PPM_128 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[34]) );
PP_MIDDLE PPM_129 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[39]) );
PP_MIDDLE PPM_130 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[46]) );
PP_MIDDLE PPM_131 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[52]) );
PP_MIDDLE PPM_132 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[60]) );
PP_MIDDLE PPM_133 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[67]) );
PP_MIDDLE PPM_134 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[76]) );
PP_MIDDLE PPM_135 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[84]) );
PP_MIDDLE PPM_136 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[94]) );
PP_MIDDLE PPM_137 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[103]) );
PP_MIDDLE PPM_138 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[114]) );
PP_MIDDLE PPM_139 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[124]) );
PP_MIDDLE PPM_140 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[136]) );
PP_MIDDLE PPM_141 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[147]) );
PP_MIDDLE PPM_142 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[160]) );
PP_MIDDLE PPM_143 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[172]) );
PP_MIDDLE PPM_144 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[186]) );
PP_MIDDLE PPM_145 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[199]) );
PP_MIDDLE PPM_146 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[214]) );
PP_MIDDLE PPM_147 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[228]) );
PP_MIDDLE PPM_148 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[244]) );
PP_MIDDLE PPM_149 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[259]) );
PP_MIDDLE PPM_150 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[276]) );
PP_MIDDLE PPM_151 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[292]) );
PP_MIDDLE PPM_152 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[309]) );
PP_MIDDLE PPM_153 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[325]) );
PP_MIDDLE PPM_154 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[340]) );
PP_MIDDLE PPM_155 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[355]) );
PP_MIDDLE PPM_156 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[369]) );
PP_MIDDLE PPM_157 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[383]) );
PP_MIDDLE PPM_158 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[396]) );
PP_MIDDLE PPM_159 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[408]) );
assign SUMMAND[409] = LOGIC_ONE;
PP_HIGH PPH_4 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[16]) , .TWONEG (INT_MULTIPLIER[17]) , .ONEPOS (INT_MULTIPLIER[18]) , .ONENEG (INT_MULTIPLIER[19]) , .PPBIT (SUMMAND[421]) );
DECODER DEC_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) );
PP_LOW PPL_5 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[40]) );
R_GATE RGATE_5 (.INA (OPB[9]) , .INB (OPB[10]) , .INC (OPB[11]) , .PPBIT (SUMMAND[41]) );
PP_MIDDLE PPM_160 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[47]) );
PP_MIDDLE PPM_161 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[53]) );
PP_MIDDLE PPM_162 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[61]) );
PP_MIDDLE PPM_163 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[68]) );
PP_MIDDLE PPM_164 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[77]) );
PP_MIDDLE PPM_165 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[85]) );
PP_MIDDLE PPM_166 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[95]) );
PP_MIDDLE PPM_167 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[104]) );
PP_MIDDLE PPM_168 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[115]) );
PP_MIDDLE PPM_169 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[125]) );
PP_MIDDLE PPM_170 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[137]) );
PP_MIDDLE PPM_171 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[148]) );
PP_MIDDLE PPM_172 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[161]) );
PP_MIDDLE PPM_173 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[173]) );
PP_MIDDLE PPM_174 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[187]) );
PP_MIDDLE PPM_175 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[200]) );
PP_MIDDLE PPM_176 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[215]) );
PP_MIDDLE PPM_177 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[229]) );
PP_MIDDLE PPM_178 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[245]) );
PP_MIDDLE PPM_179 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[260]) );
PP_MIDDLE PPM_180 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[277]) );
PP_MIDDLE PPM_181 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[293]) );
PP_MIDDLE PPM_182 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[310]) );
PP_MIDDLE PPM_183 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[326]) );
PP_MIDDLE PPM_184 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[341]) );
PP_MIDDLE PPM_185 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[356]) );
PP_MIDDLE PPM_186 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[370]) );
PP_MIDDLE PPM_187 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[384]) );
PP_MIDDLE PPM_188 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[397]) );
PP_MIDDLE PPM_189 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[410]) );
PP_MIDDLE PPM_190 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[422]) );
PP_MIDDLE PPM_191 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[433]) );
assign SUMMAND[434] = LOGIC_ONE;
PP_HIGH PPH_5 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[20]) , .TWONEG (INT_MULTIPLIER[21]) , .ONEPOS (INT_MULTIPLIER[22]) , .ONENEG (INT_MULTIPLIER[23]) , .PPBIT (SUMMAND[445]) );
DECODER DEC_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) );
PP_LOW PPL_6 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[54]) );
R_GATE RGATE_6 (.INA (OPB[11]) , .INB (OPB[12]) , .INC (OPB[13]) , .PPBIT (SUMMAND[55]) );
PP_MIDDLE PPM_192 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[62]) );
PP_MIDDLE PPM_193 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[69]) );
PP_MIDDLE PPM_194 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[78]) );
PP_MIDDLE PPM_195 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[86]) );
PP_MIDDLE PPM_196 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[96]) );
PP_MIDDLE PPM_197 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[105]) );
PP_MIDDLE PPM_198 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[116]) );
PP_MIDDLE PPM_199 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[126]) );
PP_MIDDLE PPM_200 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[138]) );
PP_MIDDLE PPM_201 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[149]) );
PP_MIDDLE PPM_202 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[162]) );
PP_MIDDLE PPM_203 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[174]) );
PP_MIDDLE PPM_204 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[188]) );
PP_MIDDLE PPM_205 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[201]) );
PP_MIDDLE PPM_206 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[216]) );
PP_MIDDLE PPM_207 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[230]) );
PP_MIDDLE PPM_208 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[246]) );
PP_MIDDLE PPM_209 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[261]) );
PP_MIDDLE PPM_210 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[278]) );
PP_MIDDLE PPM_211 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[294]) );
PP_MIDDLE PPM_212 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[311]) );
PP_MIDDLE PPM_213 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[327]) );
PP_MIDDLE PPM_214 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[342]) );
PP_MIDDLE PPM_215 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[357]) );
PP_MIDDLE PPM_216 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[371]) );
PP_MIDDLE PPM_217 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[385]) );
PP_MIDDLE PPM_218 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[398]) );
PP_MIDDLE PPM_219 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[411]) );
PP_MIDDLE PPM_220 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[423]) );
PP_MIDDLE PPM_221 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[435]) );
PP_MIDDLE PPM_222 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[446]) );
PP_MIDDLE PPM_223 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[456]) );
assign SUMMAND[457] = LOGIC_ONE;
PP_HIGH PPH_6 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[24]) , .TWONEG (INT_MULTIPLIER[25]) , .ONEPOS (INT_MULTIPLIER[26]) , .ONENEG (INT_MULTIPLIER[27]) , .PPBIT (SUMMAND[467]) );
DECODER DEC_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) );
PP_LOW PPL_7 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[70]) );
R_GATE RGATE_7 (.INA (OPB[13]) , .INB (OPB[14]) , .INC (OPB[15]) , .PPBIT (SUMMAND[71]) );
PP_MIDDLE PPM_224 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[79]) );
PP_MIDDLE PPM_225 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[87]) );
PP_MIDDLE PPM_226 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[97]) );
PP_MIDDLE PPM_227 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[106]) );
PP_MIDDLE PPM_228 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[117]) );
PP_MIDDLE PPM_229 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[127]) );
PP_MIDDLE PPM_230 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[139]) );
PP_MIDDLE PPM_231 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[150]) );
PP_MIDDLE PPM_232 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[163]) );
PP_MIDDLE PPM_233 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[175]) );
PP_MIDDLE PPM_234 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[189]) );
PP_MIDDLE PPM_235 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[202]) );
PP_MIDDLE PPM_236 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[217]) );
PP_MIDDLE PPM_237 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[231]) );
PP_MIDDLE PPM_238 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[247]) );
PP_MIDDLE PPM_239 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[262]) );
PP_MIDDLE PPM_240 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[279]) );
PP_MIDDLE PPM_241 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[295]) );
PP_MIDDLE PPM_242 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[312]) );
PP_MIDDLE PPM_243 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[328]) );
PP_MIDDLE PPM_244 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[343]) );
PP_MIDDLE PPM_245 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[358]) );
PP_MIDDLE PPM_246 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[372]) );
PP_MIDDLE PPM_247 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[386]) );
PP_MIDDLE PPM_248 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[399]) );
PP_MIDDLE PPM_249 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[412]) );
PP_MIDDLE PPM_250 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[424]) );
PP_MIDDLE PPM_251 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[436]) );
PP_MIDDLE PPM_252 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[447]) );
PP_MIDDLE PPM_253 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[458]) );
PP_MIDDLE PPM_254 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[468]) );
PP_MIDDLE PPM_255 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[477]) );
assign SUMMAND[478] = LOGIC_ONE;
PP_HIGH PPH_7 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[28]) , .TWONEG (INT_MULTIPLIER[29]) , .ONEPOS (INT_MULTIPLIER[30]) , .ONENEG (INT_MULTIPLIER[31]) , .PPBIT (SUMMAND[487]) );
DECODER DEC_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) );
PP_LOW PPL_8 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[88]) );
R_GATE RGATE_8 (.INA (OPB[15]) , .INB (OPB[16]) , .INC (OPB[17]) , .PPBIT (SUMMAND[89]) );
PP_MIDDLE PPM_256 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[98]) );
PP_MIDDLE PPM_257 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[107]) );
PP_MIDDLE PPM_258 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[118]) );
PP_MIDDLE PPM_259 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[128]) );
PP_MIDDLE PPM_260 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[140]) );
PP_MIDDLE PPM_261 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[151]) );
PP_MIDDLE PPM_262 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[164]) );
PP_MIDDLE PPM_263 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[176]) );
PP_MIDDLE PPM_264 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[190]) );
PP_MIDDLE PPM_265 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[203]) );
PP_MIDDLE PPM_266 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[218]) );
PP_MIDDLE PPM_267 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[232]) );
PP_MIDDLE PPM_268 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[248]) );
PP_MIDDLE PPM_269 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[263]) );
PP_MIDDLE PPM_270 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[280]) );
PP_MIDDLE PPM_271 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[296]) );
PP_MIDDLE PPM_272 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[313]) );
PP_MIDDLE PPM_273 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[329]) );
PP_MIDDLE PPM_274 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[344]) );
PP_MIDDLE PPM_275 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[359]) );
PP_MIDDLE PPM_276 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[373]) );
PP_MIDDLE PPM_277 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[387]) );
PP_MIDDLE PPM_278 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[400]) );
PP_MIDDLE PPM_279 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[413]) );
PP_MIDDLE PPM_280 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[425]) );
PP_MIDDLE PPM_281 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[437]) );
PP_MIDDLE PPM_282 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[448]) );
PP_MIDDLE PPM_283 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[459]) );
PP_MIDDLE PPM_284 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[469]) );
PP_MIDDLE PPM_285 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[479]) );
PP_MIDDLE PPM_286 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[488]) );
PP_MIDDLE PPM_287 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[496]) );
assign SUMMAND[497] = LOGIC_ONE;
PP_HIGH PPH_8 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[32]) , .TWONEG (INT_MULTIPLIER[33]) , .ONEPOS (INT_MULTIPLIER[34]) , .ONENEG (INT_MULTIPLIER[35]) , .PPBIT (SUMMAND[505]) );
DECODER DEC_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) );
PP_LOW PPL_9 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[108]) );
R_GATE RGATE_9 (.INA (OPB[17]) , .INB (OPB[18]) , .INC (OPB[19]) , .PPBIT (SUMMAND[109]) );
PP_MIDDLE PPM_288 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[119]) );
PP_MIDDLE PPM_289 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[129]) );
PP_MIDDLE PPM_290 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[141]) );
PP_MIDDLE PPM_291 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[152]) );
PP_MIDDLE PPM_292 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[165]) );
PP_MIDDLE PPM_293 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[177]) );
PP_MIDDLE PPM_294 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[191]) );
PP_MIDDLE PPM_295 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[204]) );
PP_MIDDLE PPM_296 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[219]) );
PP_MIDDLE PPM_297 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[233]) );
PP_MIDDLE PPM_298 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[249]) );
PP_MIDDLE PPM_299 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[264]) );
PP_MIDDLE PPM_300 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[281]) );
PP_MIDDLE PPM_301 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[297]) );
PP_MIDDLE PPM_302 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[314]) );
PP_MIDDLE PPM_303 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[330]) );
PP_MIDDLE PPM_304 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[345]) );
PP_MIDDLE PPM_305 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[360]) );
PP_MIDDLE PPM_306 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[374]) );
PP_MIDDLE PPM_307 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[388]) );
PP_MIDDLE PPM_308 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[401]) );
PP_MIDDLE PPM_309 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[414]) );
PP_MIDDLE PPM_310 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[426]) );
PP_MIDDLE PPM_311 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[438]) );
PP_MIDDLE PPM_312 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[449]) );
PP_MIDDLE PPM_313 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[460]) );
PP_MIDDLE PPM_314 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[470]) );
PP_MIDDLE PPM_315 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[480]) );
PP_MIDDLE PPM_316 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[489]) );
PP_MIDDLE PPM_317 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[498]) );
PP_MIDDLE PPM_318 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[506]) );
PP_MIDDLE PPM_319 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[513]) );
assign SUMMAND[514] = LOGIC_ONE;
PP_HIGH PPH_9 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[36]) , .TWONEG (INT_MULTIPLIER[37]) , .ONEPOS (INT_MULTIPLIER[38]) , .ONENEG (INT_MULTIPLIER[39]) , .PPBIT (SUMMAND[521]) );
DECODER DEC_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) );
PP_LOW PPL_10 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[130]) );
R_GATE RGATE_10 (.INA (OPB[19]) , .INB (OPB[20]) , .INC (OPB[21]) , .PPBIT (SUMMAND[131]) );
PP_MIDDLE PPM_320 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[142]) );
PP_MIDDLE PPM_321 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[153]) );
PP_MIDDLE PPM_322 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[166]) );
PP_MIDDLE PPM_323 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[178]) );
PP_MIDDLE PPM_324 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[192]) );
PP_MIDDLE PPM_325 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[205]) );
PP_MIDDLE PPM_326 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[220]) );
PP_MIDDLE PPM_327 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[234]) );
PP_MIDDLE PPM_328 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[250]) );
PP_MIDDLE PPM_329 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[265]) );
PP_MIDDLE PPM_330 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[282]) );
PP_MIDDLE PPM_331 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[298]) );
PP_MIDDLE PPM_332 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[315]) );
PP_MIDDLE PPM_333 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[331]) );
PP_MIDDLE PPM_334 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[346]) );
PP_MIDDLE PPM_335 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[361]) );
PP_MIDDLE PPM_336 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[375]) );
PP_MIDDLE PPM_337 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[389]) );
PP_MIDDLE PPM_338 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[402]) );
PP_MIDDLE PPM_339 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[415]) );
PP_MIDDLE PPM_340 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[427]) );
PP_MIDDLE PPM_341 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[439]) );
PP_MIDDLE PPM_342 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[450]) );
PP_MIDDLE PPM_343 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[461]) );
PP_MIDDLE PPM_344 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[471]) );
PP_MIDDLE PPM_345 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[481]) );
PP_MIDDLE PPM_346 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[490]) );
PP_MIDDLE PPM_347 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[499]) );
PP_MIDDLE PPM_348 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[507]) );
PP_MIDDLE PPM_349 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[515]) );
PP_MIDDLE PPM_350 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[522]) );
PP_MIDDLE PPM_351 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[528]) );
assign SUMMAND[529] = LOGIC_ONE;
PP_HIGH PPH_10 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[40]) , .TWONEG (INT_MULTIPLIER[41]) , .ONEPOS (INT_MULTIPLIER[42]) , .ONENEG (INT_MULTIPLIER[43]) , .PPBIT (SUMMAND[535]) );
DECODER DEC_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) );
PP_LOW PPL_11 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[154]) );
R_GATE RGATE_11 (.INA (OPB[21]) , .INB (OPB[22]) , .INC (OPB[23]) , .PPBIT (SUMMAND[155]) );
PP_MIDDLE PPM_352 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[167]) );
PP_MIDDLE PPM_353 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[179]) );
PP_MIDDLE PPM_354 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[193]) );
PP_MIDDLE PPM_355 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[206]) );
PP_MIDDLE PPM_356 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[221]) );
PP_MIDDLE PPM_357 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[235]) );
PP_MIDDLE PPM_358 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[251]) );
PP_MIDDLE PPM_359 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[266]) );
PP_MIDDLE PPM_360 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[283]) );
PP_MIDDLE PPM_361 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[299]) );
PP_MIDDLE PPM_362 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[316]) );
PP_MIDDLE PPM_363 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[332]) );
PP_MIDDLE PPM_364 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[347]) );
PP_MIDDLE PPM_365 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[362]) );
PP_MIDDLE PPM_366 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[376]) );
PP_MIDDLE PPM_367 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[390]) );
PP_MIDDLE PPM_368 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[403]) );
PP_MIDDLE PPM_369 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[416]) );
PP_MIDDLE PPM_370 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[428]) );
PP_MIDDLE PPM_371 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[440]) );
PP_MIDDLE PPM_372 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[451]) );
PP_MIDDLE PPM_373 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[462]) );
PP_MIDDLE PPM_374 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[472]) );
PP_MIDDLE PPM_375 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[482]) );
PP_MIDDLE PPM_376 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[491]) );
PP_MIDDLE PPM_377 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[500]) );
PP_MIDDLE PPM_378 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[508]) );
PP_MIDDLE PPM_379 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[516]) );
PP_MIDDLE PPM_380 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[523]) );
PP_MIDDLE PPM_381 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[530]) );
PP_MIDDLE PPM_382 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[536]) );
PP_MIDDLE PPM_383 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[541]) );
assign SUMMAND[542] = LOGIC_ONE;
PP_HIGH PPH_11 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[44]) , .TWONEG (INT_MULTIPLIER[45]) , .ONEPOS (INT_MULTIPLIER[46]) , .ONENEG (INT_MULTIPLIER[47]) , .PPBIT (SUMMAND[547]) );
DECODER DEC_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) );
PP_LOW PPL_12 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[180]) );
R_GATE RGATE_12 (.INA (OPB[23]) , .INB (OPB[24]) , .INC (OPB[25]) , .PPBIT (SUMMAND[181]) );
PP_MIDDLE PPM_384 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[194]) );
PP_MIDDLE PPM_385 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[207]) );
PP_MIDDLE PPM_386 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[222]) );
PP_MIDDLE PPM_387 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[236]) );
PP_MIDDLE PPM_388 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[252]) );
PP_MIDDLE PPM_389 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[267]) );
PP_MIDDLE PPM_390 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[284]) );
PP_MIDDLE PPM_391 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[300]) );
PP_MIDDLE PPM_392 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[317]) );
PP_MIDDLE PPM_393 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[333]) );
PP_MIDDLE PPM_394 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[348]) );
PP_MIDDLE PPM_395 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[363]) );
PP_MIDDLE PPM_396 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[377]) );
PP_MIDDLE PPM_397 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[391]) );
PP_MIDDLE PPM_398 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[404]) );
PP_MIDDLE PPM_399 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[417]) );
PP_MIDDLE PPM_400 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[429]) );
PP_MIDDLE PPM_401 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[441]) );
PP_MIDDLE PPM_402 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[452]) );
PP_MIDDLE PPM_403 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[463]) );
PP_MIDDLE PPM_404 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[473]) );
PP_MIDDLE PPM_405 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[483]) );
PP_MIDDLE PPM_406 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[492]) );
PP_MIDDLE PPM_407 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[501]) );
PP_MIDDLE PPM_408 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[509]) );
PP_MIDDLE PPM_409 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[517]) );
PP_MIDDLE PPM_410 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[524]) );
PP_MIDDLE PPM_411 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[531]) );
PP_MIDDLE PPM_412 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[537]) );
PP_MIDDLE PPM_413 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[543]) );
PP_MIDDLE PPM_414 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[548]) );
PP_MIDDLE PPM_415 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[552]) );
assign SUMMAND[553] = LOGIC_ONE;
PP_HIGH PPH_12 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[48]) , .TWONEG (INT_MULTIPLIER[49]) , .ONEPOS (INT_MULTIPLIER[50]) , .ONENEG (INT_MULTIPLIER[51]) , .PPBIT (SUMMAND[557]) );
DECODER DEC_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) );
PP_LOW PPL_13 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[208]) );
R_GATE RGATE_13 (.INA (OPB[25]) , .INB (OPB[26]) , .INC (OPB[27]) , .PPBIT (SUMMAND[209]) );
PP_MIDDLE PPM_416 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[223]) );
PP_MIDDLE PPM_417 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[237]) );
PP_MIDDLE PPM_418 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[253]) );
PP_MIDDLE PPM_419 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[268]) );
PP_MIDDLE PPM_420 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[285]) );
PP_MIDDLE PPM_421 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[301]) );
PP_MIDDLE PPM_422 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[318]) );
PP_MIDDLE PPM_423 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[334]) );
PP_MIDDLE PPM_424 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[349]) );
PP_MIDDLE PPM_425 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[364]) );
PP_MIDDLE PPM_426 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[378]) );
PP_MIDDLE PPM_427 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[392]) );
PP_MIDDLE PPM_428 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[405]) );
PP_MIDDLE PPM_429 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[418]) );
PP_MIDDLE PPM_430 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[430]) );
PP_MIDDLE PPM_431 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[442]) );
PP_MIDDLE PPM_432 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[453]) );
PP_MIDDLE PPM_433 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[464]) );
PP_MIDDLE PPM_434 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[474]) );
PP_MIDDLE PPM_435 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[484]) );
PP_MIDDLE PPM_436 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[493]) );
PP_MIDDLE PPM_437 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[502]) );
PP_MIDDLE PPM_438 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[510]) );
PP_MIDDLE PPM_439 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[518]) );
PP_MIDDLE PPM_440 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[525]) );
PP_MIDDLE PPM_441 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[532]) );
PP_MIDDLE PPM_442 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[538]) );
PP_MIDDLE PPM_443 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[544]) );
PP_MIDDLE PPM_444 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[549]) );
PP_MIDDLE PPM_445 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[554]) );
PP_MIDDLE PPM_446 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[558]) );
PP_MIDDLE PPM_447 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[561]) );
assign SUMMAND[562] = LOGIC_ONE;
PP_HIGH PPH_13 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[52]) , .TWONEG (INT_MULTIPLIER[53]) , .ONEPOS (INT_MULTIPLIER[54]) , .ONENEG (INT_MULTIPLIER[55]) , .PPBIT (SUMMAND[565]) );
DECODER DEC_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) );
PP_LOW PPL_14 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[238]) );
R_GATE RGATE_14 (.INA (OPB[27]) , .INB (OPB[28]) , .INC (OPB[29]) , .PPBIT (SUMMAND[239]) );
PP_MIDDLE PPM_448 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[254]) );
PP_MIDDLE PPM_449 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[269]) );
PP_MIDDLE PPM_450 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[286]) );
PP_MIDDLE PPM_451 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[302]) );
PP_MIDDLE PPM_452 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[319]) );
PP_MIDDLE PPM_453 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[335]) );
PP_MIDDLE PPM_454 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[350]) );
PP_MIDDLE PPM_455 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[365]) );
PP_MIDDLE PPM_456 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[379]) );
PP_MIDDLE PPM_457 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[393]) );
PP_MIDDLE PPM_458 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[406]) );
PP_MIDDLE PPM_459 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[419]) );
PP_MIDDLE PPM_460 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[431]) );
PP_MIDDLE PPM_461 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[443]) );
PP_MIDDLE PPM_462 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[454]) );
PP_MIDDLE PPM_463 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[465]) );
PP_MIDDLE PPM_464 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[475]) );
PP_MIDDLE PPM_465 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[485]) );
PP_MIDDLE PPM_466 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[494]) );
PP_MIDDLE PPM_467 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[503]) );
PP_MIDDLE PPM_468 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[511]) );
PP_MIDDLE PPM_469 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[519]) );
PP_MIDDLE PPM_470 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[526]) );
PP_MIDDLE PPM_471 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[533]) );
PP_MIDDLE PPM_472 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[539]) );
PP_MIDDLE PPM_473 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[545]) );
PP_MIDDLE PPM_474 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[550]) );
PP_MIDDLE PPM_475 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[555]) );
PP_MIDDLE PPM_476 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[559]) );
PP_MIDDLE PPM_477 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[563]) );
PP_MIDDLE PPM_478 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[566]) );
PP_MIDDLE PPM_479 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[568]) );
assign SUMMAND[569] = LOGIC_ONE;
PP_HIGH PPH_14 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[56]) , .TWONEG (INT_MULTIPLIER[57]) , .ONEPOS (INT_MULTIPLIER[58]) , .ONENEG (INT_MULTIPLIER[59]) , .PPBIT (SUMMAND[571]) );
DECODER DEC_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) );
PP_LOW PPL_15 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[270]) );
R_GATE RGATE_15 (.INA (OPB[29]) , .INB (OPB[30]) , .INC (OPB[31]) , .PPBIT (SUMMAND[271]) );
PP_MIDDLE PPM_480 (.INA (OPA[0]) , .INB (INV_MULTIPLICAND[0]) , .INC (OPA[1]) , .IND (INV_MULTIPLICAND[1]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[287]) );
PP_MIDDLE PPM_481 (.INA (OPA[1]) , .INB (INV_MULTIPLICAND[1]) , .INC (OPA[2]) , .IND (INV_MULTIPLICAND[2]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[303]) );
PP_MIDDLE PPM_482 (.INA (OPA[2]) , .INB (INV_MULTIPLICAND[2]) , .INC (OPA[3]) , .IND (INV_MULTIPLICAND[3]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[320]) );
PP_MIDDLE PPM_483 (.INA (OPA[3]) , .INB (INV_MULTIPLICAND[3]) , .INC (OPA[4]) , .IND (INV_MULTIPLICAND[4]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[336]) );
PP_MIDDLE PPM_484 (.INA (OPA[4]) , .INB (INV_MULTIPLICAND[4]) , .INC (OPA[5]) , .IND (INV_MULTIPLICAND[5]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[351]) );
PP_MIDDLE PPM_485 (.INA (OPA[5]) , .INB (INV_MULTIPLICAND[5]) , .INC (OPA[6]) , .IND (INV_MULTIPLICAND[6]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[366]) );
PP_MIDDLE PPM_486 (.INA (OPA[6]) , .INB (INV_MULTIPLICAND[6]) , .INC (OPA[7]) , .IND (INV_MULTIPLICAND[7]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[380]) );
PP_MIDDLE PPM_487 (.INA (OPA[7]) , .INB (INV_MULTIPLICAND[7]) , .INC (OPA[8]) , .IND (INV_MULTIPLICAND[8]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[394]) );
PP_MIDDLE PPM_488 (.INA (OPA[8]) , .INB (INV_MULTIPLICAND[8]) , .INC (OPA[9]) , .IND (INV_MULTIPLICAND[9]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[407]) );
PP_MIDDLE PPM_489 (.INA (OPA[9]) , .INB (INV_MULTIPLICAND[9]) , .INC (OPA[10]) , .IND (INV_MULTIPLICAND[10]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[420]) );
PP_MIDDLE PPM_490 (.INA (OPA[10]) , .INB (INV_MULTIPLICAND[10]) , .INC (OPA[11]) , .IND (INV_MULTIPLICAND[11]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[432]) );
PP_MIDDLE PPM_491 (.INA (OPA[11]) , .INB (INV_MULTIPLICAND[11]) , .INC (OPA[12]) , .IND (INV_MULTIPLICAND[12]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[444]) );
PP_MIDDLE PPM_492 (.INA (OPA[12]) , .INB (INV_MULTIPLICAND[12]) , .INC (OPA[13]) , .IND (INV_MULTIPLICAND[13]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[455]) );
PP_MIDDLE PPM_493 (.INA (OPA[13]) , .INB (INV_MULTIPLICAND[13]) , .INC (OPA[14]) , .IND (INV_MULTIPLICAND[14]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[466]) );
PP_MIDDLE PPM_494 (.INA (OPA[14]) , .INB (INV_MULTIPLICAND[14]) , .INC (OPA[15]) , .IND (INV_MULTIPLICAND[15]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[476]) );
PP_MIDDLE PPM_495 (.INA (OPA[15]) , .INB (INV_MULTIPLICAND[15]) , .INC (OPA[16]) , .IND (INV_MULTIPLICAND[16]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[486]) );
PP_MIDDLE PPM_496 (.INA (OPA[16]) , .INB (INV_MULTIPLICAND[16]) , .INC (OPA[17]) , .IND (INV_MULTIPLICAND[17]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[495]) );
PP_MIDDLE PPM_497 (.INA (OPA[17]) , .INB (INV_MULTIPLICAND[17]) , .INC (OPA[18]) , .IND (INV_MULTIPLICAND[18]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[504]) );
PP_MIDDLE PPM_498 (.INA (OPA[18]) , .INB (INV_MULTIPLICAND[18]) , .INC (OPA[19]) , .IND (INV_MULTIPLICAND[19]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[512]) );
PP_MIDDLE PPM_499 (.INA (OPA[19]) , .INB (INV_MULTIPLICAND[19]) , .INC (OPA[20]) , .IND (INV_MULTIPLICAND[20]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[520]) );
PP_MIDDLE PPM_500 (.INA (OPA[20]) , .INB (INV_MULTIPLICAND[20]) , .INC (OPA[21]) , .IND (INV_MULTIPLICAND[21]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[527]) );
PP_MIDDLE PPM_501 (.INA (OPA[21]) , .INB (INV_MULTIPLICAND[21]) , .INC (OPA[22]) , .IND (INV_MULTIPLICAND[22]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[534]) );
PP_MIDDLE PPM_502 (.INA (OPA[22]) , .INB (INV_MULTIPLICAND[22]) , .INC (OPA[23]) , .IND (INV_MULTIPLICAND[23]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[540]) );
PP_MIDDLE PPM_503 (.INA (OPA[23]) , .INB (INV_MULTIPLICAND[23]) , .INC (OPA[24]) , .IND (INV_MULTIPLICAND[24]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[546]) );
PP_MIDDLE PPM_504 (.INA (OPA[24]) , .INB (INV_MULTIPLICAND[24]) , .INC (OPA[25]) , .IND (INV_MULTIPLICAND[25]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[551]) );
PP_MIDDLE PPM_505 (.INA (OPA[25]) , .INB (INV_MULTIPLICAND[25]) , .INC (OPA[26]) , .IND (INV_MULTIPLICAND[26]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[556]) );
PP_MIDDLE PPM_506 (.INA (OPA[26]) , .INB (INV_MULTIPLICAND[26]) , .INC (OPA[27]) , .IND (INV_MULTIPLICAND[27]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[560]) );
PP_MIDDLE PPM_507 (.INA (OPA[27]) , .INB (INV_MULTIPLICAND[27]) , .INC (OPA[28]) , .IND (INV_MULTIPLICAND[28]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[564]) );
PP_MIDDLE PPM_508 (.INA (OPA[28]) , .INB (INV_MULTIPLICAND[28]) , .INC (OPA[29]) , .IND (INV_MULTIPLICAND[29]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[567]) );
PP_MIDDLE PPM_509 (.INA (OPA[29]) , .INB (INV_MULTIPLICAND[29]) , .INC (OPA[30]) , .IND (INV_MULTIPLICAND[30]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[570]) );
PP_MIDDLE PPM_510 (.INA (OPA[30]) , .INB (INV_MULTIPLICAND[30]) , .INC (OPA[31]) , .IND (INV_MULTIPLICAND[31]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[572]) );
PP_MIDDLE PPM_511 (.INA (OPA[31]) , .INB (INV_MULTIPLICAND[31]) , .INC (OPA[32]) , .IND (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[573]) );
assign SUMMAND[574] = LOGIC_ONE;
PP_HIGH PPH_15 (.INA (OPA[32]) , .INB (INV_MULTIPLICAND[32]) , .TWOPOS (INT_MULTIPLIER[60]) , .TWONEG (INT_MULTIPLIER[61]) , .ONEPOS (INT_MULTIPLIER[62]) , .ONENEG (INT_MULTIPLIER[63]) , .PPBIT (SUMMAND[575]) );
endmodule
module FULL_ADDER ( DATA_A, DATA_B, DATA_C, SAVE, CARRY );
input DATA_A;
input DATA_B;
input DATA_C;
output SAVE;
output CARRY;
wire TMP;
assign TMP = DATA_A ^ DATA_B;
assign SAVE = TMP ^ DATA_C;
assign CARRY = ~ (( ~ (TMP & DATA_C)) & ( ~ (DATA_A & DATA_B)));
endmodule
module HALF_ADDER ( DATA_A, DATA_B, SAVE, CARRY );
input DATA_A;
input DATA_B;
output SAVE;
output CARRY;
assign SAVE = DATA_A ^ DATA_B;
assign CARRY = DATA_A & DATA_B;
endmodule
module FLIPFLOP ( DIN, RST, CLK, DOUT );
input DIN;
input RST;
input CLK;
output DOUT;
reg DOUT_reg;
always @ ( posedge RST or posedge CLK ) begin
if (RST)
DOUT_reg <= 1'b0;
else
DOUT_reg <= DIN;
end
assign DOUT = DOUT_reg;
endmodule
module WALLACE_33_32 ( SUMMAND, RST, CLK, CARRY, SUM );
input [0:575] SUMMAND;
input RST;
input CLK;
output [0:62] CARRY;
output [0:63] SUM;
wire [0:7] LATCHED_PP;
wire [0:523] INT_CARRY;
wire [0:669] INT_SUM;
HALF_ADDER HA_0 (.DATA_A (SUMMAND[0]) , .DATA_B (SUMMAND[1]) , .SAVE (INT_SUM[0]) , .CARRY (INT_CARRY[0]) );
FLIPFLOP LA_0 (.DIN (INT_SUM[0]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[0]) );
FLIPFLOP LA_1 (.DIN (INT_CARRY[0]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[0]) );
assign INT_SUM[1] = SUMMAND[2];
assign CARRY[1] = 0;
FLIPFLOP LA_2 (.DIN (INT_SUM[1]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[1]) );
FULL_ADDER FA_0 (.DATA_A (SUMMAND[3]) , .DATA_B (SUMMAND[4]) , .DATA_C (SUMMAND[5]) , .SAVE (INT_SUM[2]) , .CARRY (INT_CARRY[1]) );
FLIPFLOP LA_3 (.DIN (INT_SUM[2]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[2]) );
FLIPFLOP LA_4 (.DIN (INT_CARRY[1]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[2]) );
HALF_ADDER HA_1 (.DATA_A (SUMMAND[6]) , .DATA_B (SUMMAND[7]) , .SAVE (INT_SUM[3]) , .CARRY (INT_CARRY[2]) );
FLIPFLOP LA_5 (.DIN (INT_SUM[3]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[3]) );
FLIPFLOP LA_6 (.DIN (INT_CARRY[2]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[3]) );
FULL_ADDER FA_1 (.DATA_A (SUMMAND[8]) , .DATA_B (SUMMAND[9]) , .DATA_C (SUMMAND[10]) , .SAVE (INT_SUM[4]) , .CARRY (INT_CARRY[4]) );
assign INT_SUM[5] = SUMMAND[11];
HALF_ADDER HA_2 (.DATA_A (INT_SUM[4]) , .DATA_B (INT_SUM[5]) , .SAVE (INT_SUM[6]) , .CARRY (INT_CARRY[3]) );
FLIPFLOP LA_7 (.DIN (INT_SUM[6]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[4]) );
FLIPFLOP LA_8 (.DIN (INT_CARRY[3]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[4]) );
FULL_ADDER FA_2 (.DATA_A (SUMMAND[12]) , .DATA_B (SUMMAND[13]) , .DATA_C (SUMMAND[14]) , .SAVE (INT_SUM[7]) , .CARRY (INT_CARRY[6]) );
HALF_ADDER HA_3 (.DATA_A (INT_SUM[7]) , .DATA_B (INT_CARRY[4]) , .SAVE (INT_SUM[8]) , .CARRY (INT_CARRY[5]) );
FLIPFLOP LA_9 (.DIN (INT_SUM[8]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[5]) );
FLIPFLOP LA_10 (.DIN (INT_CARRY[5]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[5]) );
FULL_ADDER FA_3 (.DATA_A (SUMMAND[15]) , .DATA_B (SUMMAND[16]) , .DATA_C (SUMMAND[17]) , .SAVE (INT_SUM[9]) , .CARRY (INT_CARRY[8]) );
HALF_ADDER HA_4 (.DATA_A (SUMMAND[18]) , .DATA_B (SUMMAND[19]) , .SAVE (INT_SUM[10]) , .CARRY (INT_CARRY[9]) );
FULL_ADDER FA_4 (.DATA_A (INT_SUM[9]) , .DATA_B (INT_SUM[10]) , .DATA_C (INT_CARRY[6]) , .SAVE (INT_SUM[11]) , .CARRY (INT_CARRY[7]) );
FLIPFLOP LA_11 (.DIN (INT_SUM[11]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[6]) );
FLIPFLOP LA_12 (.DIN (INT_CARRY[7]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[6]) );
FULL_ADDER FA_5 (.DATA_A (SUMMAND[20]) , .DATA_B (SUMMAND[21]) , .DATA_C (SUMMAND[22]) , .SAVE (INT_SUM[12]) , .CARRY (INT_CARRY[11]) );
assign INT_SUM[13] = SUMMAND[23];
FULL_ADDER FA_6 (.DATA_A (INT_SUM[12]) , .DATA_B (INT_SUM[13]) , .DATA_C (INT_CARRY[8]) , .SAVE (INT_SUM[14]) , .CARRY (INT_CARRY[12]) );
assign INT_SUM[15] = INT_CARRY[9];
HALF_ADDER HA_5 (.DATA_A (INT_SUM[14]) , .DATA_B (INT_SUM[15]) , .SAVE (INT_SUM[16]) , .CARRY (INT_CARRY[10]) );
FLIPFLOP LA_13 (.DIN (INT_SUM[16]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[7]) );
FLIPFLOP LA_14 (.DIN (INT_CARRY[10]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[7]) );
FULL_ADDER FA_7 (.DATA_A (SUMMAND[24]) , .DATA_B (SUMMAND[25]) , .DATA_C (SUMMAND[26]) , .SAVE (INT_SUM[17]) , .CARRY (INT_CARRY[14]) );
FULL_ADDER FA_8 (.DATA_A (SUMMAND[27]) , .DATA_B (SUMMAND[28]) , .DATA_C (SUMMAND[29]) , .SAVE (INT_SUM[18]) , .CARRY (INT_CARRY[15]) );
FULL_ADDER FA_9 (.DATA_A (INT_SUM[17]) , .DATA_B (INT_SUM[18]) , .DATA_C (INT_CARRY[11]) , .SAVE (INT_SUM[19]) , .CARRY (INT_CARRY[16]) );
HALF_ADDER HA_6 (.DATA_A (INT_SUM[19]) , .DATA_B (INT_CARRY[12]) , .SAVE (INT_SUM[20]) , .CARRY (INT_CARRY[13]) );
FLIPFLOP LA_15 (.DIN (INT_SUM[20]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[8]) );
FLIPFLOP LA_16 (.DIN (INT_CARRY[13]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[8]) );
FULL_ADDER FA_10 (.DATA_A (SUMMAND[30]) , .DATA_B (SUMMAND[31]) , .DATA_C (SUMMAND[32]) , .SAVE (INT_SUM[21]) , .CARRY (INT_CARRY[18]) );
HALF_ADDER HA_7 (.DATA_A (SUMMAND[33]) , .DATA_B (SUMMAND[34]) , .SAVE (INT_SUM[22]) , .CARRY (INT_CARRY[19]) );
FULL_ADDER FA_11 (.DATA_A (INT_SUM[21]) , .DATA_B (INT_SUM[22]) , .DATA_C (INT_CARRY[14]) , .SAVE (INT_SUM[23]) , .CARRY (INT_CARRY[20]) );
assign INT_SUM[24] = INT_CARRY[15];
FULL_ADDER FA_12 (.DATA_A (INT_SUM[23]) , .DATA_B (INT_SUM[24]) , .DATA_C (INT_CARRY[16]) , .SAVE (INT_SUM[25]) , .CARRY (INT_CARRY[17]) );
FLIPFLOP LA_17 (.DIN (INT_SUM[25]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[9]) );
FLIPFLOP LA_18 (.DIN (INT_CARRY[17]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[9]) );
FULL_ADDER FA_13 (.DATA_A (SUMMAND[35]) , .DATA_B (SUMMAND[36]) , .DATA_C (SUMMAND[37]) , .SAVE (INT_SUM[26]) , .CARRY (INT_CARRY[22]) );
FULL_ADDER FA_14 (.DATA_A (SUMMAND[38]) , .DATA_B (SUMMAND[39]) , .DATA_C (SUMMAND[40]) , .SAVE (INT_SUM[27]) , .CARRY (INT_CARRY[23]) );
assign INT_SUM[28] = SUMMAND[41];
FULL_ADDER FA_15 (.DATA_A (INT_SUM[26]) , .DATA_B (INT_SUM[27]) , .DATA_C (INT_SUM[28]) , .SAVE (INT_SUM[29]) , .CARRY (INT_CARRY[24]) );
HALF_ADDER HA_8 (.DATA_A (INT_CARRY[18]) , .DATA_B (INT_CARRY[19]) , .SAVE (INT_SUM[30]) , .CARRY (INT_CARRY[25]) );
FULL_ADDER FA_16 (.DATA_A (INT_SUM[29]) , .DATA_B (INT_SUM[30]) , .DATA_C (INT_CARRY[20]) , .SAVE (INT_SUM[31]) , .CARRY (INT_CARRY[21]) );
FLIPFLOP LA_19 (.DIN (INT_SUM[31]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[10]) );
FLIPFLOP LA_20 (.DIN (INT_CARRY[21]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[10]) );
FULL_ADDER FA_17 (.DATA_A (SUMMAND[42]) , .DATA_B (SUMMAND[43]) , .DATA_C (SUMMAND[44]) , .SAVE (INT_SUM[32]) , .CARRY (INT_CARRY[27]) );
FULL_ADDER FA_18 (.DATA_A (SUMMAND[45]) , .DATA_B (SUMMAND[46]) , .DATA_C (SUMMAND[47]) , .SAVE (INT_SUM[33]) , .CARRY (INT_CARRY[28]) );
FULL_ADDER FA_19 (.DATA_A (INT_SUM[32]) , .DATA_B (INT_SUM[33]) , .DATA_C (INT_CARRY[22]) , .SAVE (INT_SUM[34]) , .CARRY (INT_CARRY[29]) );
assign INT_SUM[35] = INT_CARRY[23];
FULL_ADDER FA_20 (.DATA_A (INT_SUM[34]) , .DATA_B (INT_SUM[35]) , .DATA_C (INT_CARRY[24]) , .SAVE (INT_SUM[36]) , .CARRY (INT_CARRY[30]) );
assign INT_SUM[37] = INT_CARRY[25];
HALF_ADDER HA_9 (.DATA_A (INT_SUM[36]) , .DATA_B (INT_SUM[37]) , .SAVE (INT_SUM[38]) , .CARRY (INT_CARRY[26]) );
FLIPFLOP LA_21 (.DIN (INT_SUM[38]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[11]) );
FLIPFLOP LA_22 (.DIN (INT_CARRY[26]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[11]) );
FULL_ADDER FA_21 (.DATA_A (SUMMAND[48]) , .DATA_B (SUMMAND[49]) , .DATA_C (SUMMAND[50]) , .SAVE (INT_SUM[39]) , .CARRY (INT_CARRY[32]) );
FULL_ADDER FA_22 (.DATA_A (SUMMAND[51]) , .DATA_B (SUMMAND[52]) , .DATA_C (SUMMAND[53]) , .SAVE (INT_SUM[40]) , .CARRY (INT_CARRY[33]) );
assign INT_SUM[41] = SUMMAND[54];
assign INT_SUM[42] = SUMMAND[55];
FULL_ADDER FA_23 (.DATA_A (INT_SUM[39]) , .DATA_B (INT_SUM[40]) , .DATA_C (INT_SUM[41]) , .SAVE (INT_SUM[43]) , .CARRY (INT_CARRY[34]) );
FULL_ADDER FA_24 (.DATA_A (INT_SUM[42]) , .DATA_B (INT_CARRY[27]) , .DATA_C (INT_CARRY[28]) , .SAVE (INT_SUM[44]) , .CARRY (INT_CARRY[35]) );
FULL_ADDER FA_25 (.DATA_A (INT_SUM[43]) , .DATA_B (INT_SUM[44]) , .DATA_C (INT_CARRY[29]) , .SAVE (INT_SUM[45]) , .CARRY (INT_CARRY[36]) );
HALF_ADDER HA_10 (.DATA_A (INT_SUM[45]) , .DATA_B (INT_CARRY[30]) , .SAVE (INT_SUM[46]) , .CARRY (INT_CARRY[31]) );
FLIPFLOP LA_23 (.DIN (INT_SUM[46]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[12]) );
FLIPFLOP LA_24 (.DIN (INT_CARRY[31]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[12]) );
FULL_ADDER FA_26 (.DATA_A (SUMMAND[56]) , .DATA_B (SUMMAND[57]) , .DATA_C (SUMMAND[58]) , .SAVE (INT_SUM[47]) , .CARRY (INT_CARRY[38]) );
FULL_ADDER FA_27 (.DATA_A (SUMMAND[59]) , .DATA_B (SUMMAND[60]) , .DATA_C (SUMMAND[61]) , .SAVE (INT_SUM[48]) , .CARRY (INT_CARRY[39]) );
assign INT_SUM[49] = SUMMAND[62];
FULL_ADDER FA_28 (.DATA_A (INT_SUM[47]) , .DATA_B (INT_SUM[48]) , .DATA_C (INT_SUM[49]) , .SAVE (INT_SUM[50]) , .CARRY (INT_CARRY[40]) );
HALF_ADDER HA_11 (.DATA_A (INT_CARRY[32]) , .DATA_B (INT_CARRY[33]) , .SAVE (INT_SUM[51]) , .CARRY (INT_CARRY[41]) );
FULL_ADDER FA_29 (.DATA_A (INT_SUM[50]) , .DATA_B (INT_SUM[51]) , .DATA_C (INT_CARRY[34]) , .SAVE (INT_SUM[52]) , .CARRY (INT_CARRY[42]) );
assign INT_SUM[53] = INT_CARRY[35];
FULL_ADDER FA_30 (.DATA_A (INT_SUM[52]) , .DATA_B (INT_SUM[53]) , .DATA_C (INT_CARRY[36]) , .SAVE (INT_SUM[54]) , .CARRY (INT_CARRY[37]) );
FLIPFLOP LA_25 (.DIN (INT_SUM[54]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[13]) );
FLIPFLOP LA_26 (.DIN (INT_CARRY[37]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[13]) );
FULL_ADDER FA_31 (.DATA_A (SUMMAND[63]) , .DATA_B (SUMMAND[64]) , .DATA_C (SUMMAND[65]) , .SAVE (INT_SUM[55]) , .CARRY (INT_CARRY[44]) );
FULL_ADDER FA_32 (.DATA_A (SUMMAND[66]) , .DATA_B (SUMMAND[67]) , .DATA_C (SUMMAND[68]) , .SAVE (INT_SUM[56]) , .CARRY (INT_CARRY[45]) );
FULL_ADDER FA_33 (.DATA_A (SUMMAND[69]) , .DATA_B (SUMMAND[70]) , .DATA_C (SUMMAND[71]) , .SAVE (INT_SUM[57]) , .CARRY (INT_CARRY[46]) );
FULL_ADDER FA_34 (.DATA_A (INT_SUM[55]) , .DATA_B (INT_SUM[56]) , .DATA_C (INT_SUM[57]) , .SAVE (INT_SUM[58]) , .CARRY (INT_CARRY[47]) );
HALF_ADDER HA_12 (.DATA_A (INT_CARRY[38]) , .DATA_B (INT_CARRY[39]) , .SAVE (INT_SUM[59]) , .CARRY (INT_CARRY[48]) );
FULL_ADDER FA_35 (.DATA_A (INT_SUM[58]) , .DATA_B (INT_SUM[59]) , .DATA_C (INT_CARRY[40]) , .SAVE (INT_SUM[60]) , .CARRY (INT_CARRY[49]) );
assign INT_SUM[61] = INT_CARRY[41];
FULL_ADDER FA_36 (.DATA_A (INT_SUM[60]) , .DATA_B (INT_SUM[61]) , .DATA_C (INT_CARRY[42]) , .SAVE (INT_SUM[62]) , .CARRY (INT_CARRY[43]) );
FLIPFLOP LA_27 (.DIN (INT_SUM[62]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[14]) );
FLIPFLOP LA_28 (.DIN (INT_CARRY[43]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[14]) );
FULL_ADDER FA_37 (.DATA_A (SUMMAND[72]) , .DATA_B (SUMMAND[73]) , .DATA_C (SUMMAND[74]) , .SAVE (INT_SUM[63]) , .CARRY (INT_CARRY[51]) );
FULL_ADDER FA_38 (.DATA_A (SUMMAND[75]) , .DATA_B (SUMMAND[76]) , .DATA_C (SUMMAND[77]) , .SAVE (INT_SUM[64]) , .CARRY (INT_CARRY[52]) );
HALF_ADDER HA_13 (.DATA_A (SUMMAND[78]) , .DATA_B (SUMMAND[79]) , .SAVE (INT_SUM[65]) , .CARRY (INT_CARRY[53]) );
FULL_ADDER FA_39 (.DATA_A (INT_SUM[63]) , .DATA_B (INT_SUM[64]) , .DATA_C (INT_SUM[65]) , .SAVE (INT_SUM[66]) , .CARRY (INT_CARRY[54]) );
FULL_ADDER FA_40 (.DATA_A (INT_CARRY[44]) , .DATA_B (INT_CARRY[45]) , .DATA_C (INT_CARRY[46]) , .SAVE (INT_SUM[67]) , .CARRY (INT_CARRY[55]) );
FULL_ADDER FA_41 (.DATA_A (INT_SUM[66]) , .DATA_B (INT_SUM[67]) , .DATA_C (INT_CARRY[47]) , .SAVE (INT_SUM[68]) , .CARRY (INT_CARRY[56]) );
assign INT_SUM[69] = INT_CARRY[48];
FULL_ADDER FA_42 (.DATA_A (INT_SUM[68]) , .DATA_B (INT_SUM[69]) , .DATA_C (INT_CARRY[49]) , .SAVE (INT_SUM[70]) , .CARRY (INT_CARRY[50]) );
FLIPFLOP LA_29 (.DIN (INT_SUM[70]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[15]) );
FLIPFLOP LA_30 (.DIN (INT_CARRY[50]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[15]) );
FULL_ADDER FA_43 (.DATA_A (SUMMAND[80]) , .DATA_B (SUMMAND[81]) , .DATA_C (SUMMAND[82]) , .SAVE (INT_SUM[71]) , .CARRY (INT_CARRY[58]) );
FULL_ADDER FA_44 (.DATA_A (SUMMAND[83]) , .DATA_B (SUMMAND[84]) , .DATA_C (SUMMAND[85]) , .SAVE (INT_SUM[72]) , .CARRY (INT_CARRY[59]) );
FULL_ADDER FA_45 (.DATA_A (SUMMAND[86]) , .DATA_B (SUMMAND[87]) , .DATA_C (SUMMAND[88]) , .SAVE (INT_SUM[73]) , .CARRY (INT_CARRY[60]) );
assign INT_SUM[74] = SUMMAND[89];
FULL_ADDER FA_46 (.DATA_A (INT_SUM[71]) , .DATA_B (INT_SUM[72]) , .DATA_C (INT_SUM[73]) , .SAVE (INT_SUM[75]) , .CARRY (INT_CARRY[61]) );
FULL_ADDER FA_47 (.DATA_A (INT_SUM[74]) , .DATA_B (INT_CARRY[51]) , .DATA_C (INT_CARRY[52]) , .SAVE (INT_SUM[76]) , .CARRY (INT_CARRY[62]) );
assign INT_SUM[77] = INT_CARRY[53];
FULL_ADDER FA_48 (.DATA_A (INT_SUM[75]) , .DATA_B (INT_SUM[76]) , .DATA_C (INT_SUM[77]) , .SAVE (INT_SUM[78]) , .CARRY (INT_CARRY[63]) );
HALF_ADDER HA_14 (.DATA_A (INT_CARRY[54]) , .DATA_B (INT_CARRY[55]) , .SAVE (INT_SUM[79]) , .CARRY (INT_CARRY[64]) );
FULL_ADDER FA_49 (.DATA_A (INT_SUM[78]) , .DATA_B (INT_SUM[79]) , .DATA_C (INT_CARRY[56]) , .SAVE (INT_SUM[80]) , .CARRY (INT_CARRY[57]) );
FLIPFLOP LA_31 (.DIN (INT_SUM[80]) , .RST(RST), .CLK (CLK) , .DOUT (SUM[16]) );
FLIPFLOP LA_32 (.DIN (INT_CARRY[57]) , .RST(RST), .CLK (CLK) , .DOUT (CARRY[16]) );
FULL_ADDER FA_50 (.DATA_A (SUMMAND[90]) , .DATA_B (SUMMAND[91]) , .DATA_C (SUMMAND[92]) , .SAVE (INT_SUM[81]) , .CARRY (INT_CARRY[65]) );
FULL_ADDER FA_51 (.DATA_A (SUMMAND[93]) , .DATA_B (SUMMAND[94]) , .DATA_C (SUMMAND[95]) , .SAVE (INT_SUM[82]) , .CARRY (INT_CARRY[66]) );
FULL_ADDER FA_52 (.DATA_A (SUMMAND[96]) , .DATA_B (SUMMAND[97]) , .DATA_C (SUMMAND[98]) , .SAVE (INT_SUM[83]) , .CARRY (INT_CARRY[67]) );
FULL_ADDER FA_53 (.DATA_A (INT_SUM[81]) , .DATA_B (INT_SUM[82]) , .DATA_C (INT_SUM[83]) , .SAVE (INT_SUM[84]) , .CARRY (INT_CARRY[68]) );
FULL_ADDER FA_54 (.DATA_A (INT_CARRY[58]) , .DATA_B (INT_CARRY[59]) , .DATA_C (INT_CARRY[60]) , .SAVE (INT_SUM[85]) , .CARRY (INT_CARRY[69]) );
FULL_ADDER FA_55 (.DATA_A (INT_SUM[84]) , .DATA_B (INT_SUM[85]) , .DATA_C (INT_CARRY[61]) , .SAVE (INT_SUM[86]) , .CARRY (INT_CARRY[70]) );
assign INT_SUM[87] = INT_CARRY[62];
FULL_ADDER FA_56 (.DATA_A (INT_SUM[86]) , .DATA_B (INT_SUM[87]) , .DATA_C (INT_CARRY[63]) , .SAVE (INT_SUM[88]) , .CARRY (INT_CARRY[71]) );
assign INT_SUM[90] = INT_CARRY[64];
FLIPFLOP LA_33 (.DIN (INT_SUM[88]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[89]) );
FLIPFLOP LA_34 (.DIN (INT_SUM[90]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[91]) );
HALF_ADDER HA_15 (.DATA_A (INT_SUM[89]) , .DATA_B (INT_SUM[91]) , .SAVE (SUM[17]) , .CARRY (CARRY[17]) );
FULL_ADDER FA_57 (.DATA_A (SUMMAND[99]) , .DATA_B (SUMMAND[100]) , .DATA_C (SUMMAND[101]) , .SAVE (INT_SUM[92]) , .CARRY (INT_CARRY[73]) );
FULL_ADDER FA_58 (.DATA_A (SUMMAND[102]) , .DATA_B (SUMMAND[103]) , .DATA_C (SUMMAND[104]) , .SAVE (INT_SUM[93]) , .CARRY (INT_CARRY[74]) );
FULL_ADDER FA_59 (.DATA_A (SUMMAND[105]) , .DATA_B (SUMMAND[106]) , .DATA_C (SUMMAND[107]) , .SAVE (INT_SUM[94]) , .CARRY (INT_CARRY[75]) );
assign INT_SUM[95] = SUMMAND[108];
assign INT_SUM[96] = SUMMAND[109];
FULL_ADDER FA_60 (.DATA_A (INT_SUM[92]) , .DATA_B (INT_SUM[93]) , .DATA_C (INT_SUM[94]) , .SAVE (INT_SUM[97]) , .CARRY (INT_CARRY[76]) );
FULL_ADDER FA_61 (.DATA_A (INT_SUM[95]) , .DATA_B (INT_SUM[96]) , .DATA_C (INT_CARRY[65]) , .SAVE (INT_SUM[98]) , .CARRY (INT_CARRY[77]) );
assign INT_SUM[99] = INT_CARRY[66];
assign INT_SUM[100] = INT_CARRY[67];
FULL_ADDER FA_62 (.DATA_A (INT_SUM[97]) , .DATA_B (INT_SUM[98]) , .DATA_C (INT_SUM[99]) , .SAVE (INT_SUM[101]) , .CARRY (INT_CARRY[78]) );
FULL_ADDER FA_63 (.DATA_A (INT_SUM[100]) , .DATA_B (INT_CARRY[68]) , .DATA_C (INT_CARRY[69]) , .SAVE (INT_SUM[102]) , .CARRY (INT_CARRY[79]) );
FULL_ADDER FA_64 (.DATA_A (INT_SUM[101]) , .DATA_B (INT_SUM[102]) , .DATA_C (INT_CARRY[70]) , .SAVE (INT_SUM[103]) , .CARRY (INT_CARRY[80]) );
FLIPFLOP LA_35 (.DIN (INT_SUM[103]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[104]) );
FLIPFLOP LA_36 (.DIN (INT_CARRY[71]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[72]) );
HALF_ADDER HA_16 (.DATA_A (INT_SUM[104]) , .DATA_B (INT_CARRY[72]) , .SAVE (SUM[18]) , .CARRY (CARRY[18]) );
FULL_ADDER FA_65 (.DATA_A (SUMMAND[110]) , .DATA_B (SUMMAND[111]) , .DATA_C (SUMMAND[112]) , .SAVE (INT_SUM[105]) , .CARRY (INT_CARRY[82]) );
FULL_ADDER FA_66 (.DATA_A (SUMMAND[113]) , .DATA_B (SUMMAND[114]) , .DATA_C (SUMMAND[115]) , .SAVE (INT_SUM[106]) , .CARRY (INT_CARRY[83]) );
FULL_ADDER FA_67 (.DATA_A (SUMMAND[116]) , .DATA_B (SUMMAND[117]) , .DATA_C (SUMMAND[118]) , .SAVE (INT_SUM[107]) , .CARRY (INT_CARRY[84]) );
assign INT_SUM[108] = SUMMAND[119];
FULL_ADDER FA_68 (.DATA_A (INT_SUM[105]) , .DATA_B (INT_SUM[106]) , .DATA_C (INT_SUM[107]) , .SAVE (INT_SUM[109]) , .CARRY (INT_CARRY[85]) );
FULL_ADDER FA_69 (.DATA_A (INT_SUM[108]) , .DATA_B (INT_CARRY[73]) , .DATA_C (INT_CARRY[74]) , .SAVE (INT_SUM[110]) , .CARRY (INT_CARRY[86]) );
assign INT_SUM[111] = INT_CARRY[75];
FULL_ADDER FA_70 (.DATA_A (INT_SUM[109]) , .DATA_B (INT_SUM[110]) , .DATA_C (INT_SUM[111]) , .SAVE (INT_SUM[112]) , .CARRY (INT_CARRY[87]) );
HALF_ADDER HA_17 (.DATA_A (INT_CARRY[76]) , .DATA_B (INT_CARRY[77]) , .SAVE (INT_SUM[113]) , .CARRY (INT_CARRY[88]) );
FULL_ADDER FA_71 (.DATA_A (INT_SUM[112]) , .DATA_B (INT_SUM[113]) , .DATA_C (INT_CARRY[78]) , .SAVE (INT_SUM[114]) , .CARRY (INT_CARRY[89]) );
assign INT_SUM[116] = INT_CARRY[79];
FLIPFLOP LA_37 (.DIN (INT_SUM[114]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[115]) );
FLIPFLOP LA_38 (.DIN (INT_SUM[116]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[117]) );
FLIPFLOP LA_39 (.DIN (INT_CARRY[80]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[81]) );
FULL_ADDER FA_72 (.DATA_A (INT_SUM[115]) , .DATA_B (INT_SUM[117]) , .DATA_C (INT_CARRY[81]) , .SAVE (SUM[19]) , .CARRY (CARRY[19]) );
FULL_ADDER FA_73 (.DATA_A (SUMMAND[120]) , .DATA_B (SUMMAND[121]) , .DATA_C (SUMMAND[122]) , .SAVE (INT_SUM[118]) , .CARRY (INT_CARRY[91]) );
FULL_ADDER FA_74 (.DATA_A (SUMMAND[123]) , .DATA_B (SUMMAND[124]) , .DATA_C (SUMMAND[125]) , .SAVE (INT_SUM[119]) , .CARRY (INT_CARRY[92]) );
FULL_ADDER FA_75 (.DATA_A (SUMMAND[126]) , .DATA_B (SUMMAND[127]) , .DATA_C (SUMMAND[128]) , .SAVE (INT_SUM[120]) , .CARRY (INT_CARRY[93]) );
FULL_ADDER FA_76 (.DATA_A (SUMMAND[129]) , .DATA_B (SUMMAND[130]) , .DATA_C (SUMMAND[131]) , .SAVE (INT_SUM[121]) , .CARRY (INT_CARRY[94]) );
FULL_ADDER FA_77 (.DATA_A (INT_SUM[118]) , .DATA_B (INT_SUM[119]) , .DATA_C (INT_SUM[120]) , .SAVE (INT_SUM[122]) , .CARRY (INT_CARRY[95]) );
FULL_ADDER FA_78 (.DATA_A (INT_SUM[121]) , .DATA_B (INT_CARRY[82]) , .DATA_C (INT_CARRY[83]) , .SAVE (INT_SUM[123]) , .CARRY (INT_CARRY[96]) );
assign INT_SUM[124] = INT_CARRY[84];
FULL_ADDER FA_79 (.DATA_A (INT_SUM[122]) , .DATA_B (INT_SUM[123]) , .DATA_C (INT_SUM[124]) , .SAVE (INT_SUM[125]) , .CARRY (INT_CARRY[97]) );
HALF_ADDER HA_18 (.DATA_A (INT_CARRY[85]) , .DATA_B (INT_CARRY[86]) , .SAVE (INT_SUM[126]) , .CARRY (INT_CARRY[98]) );
FULL_ADDER FA_80 (.DATA_A (INT_SUM[125]) , .DATA_B (INT_SUM[126]) , .DATA_C (INT_CARRY[87]) , .SAVE (INT_SUM[127]) , .CARRY (INT_CARRY[99]) );
assign INT_SUM[129] = INT_CARRY[88];
FLIPFLOP LA_40 (.DIN (INT_SUM[127]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[128]) );
FLIPFLOP LA_41 (.DIN (INT_SUM[129]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[130]) );
FLIPFLOP LA_42 (.DIN (INT_CARRY[89]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[90]) );
FULL_ADDER FA_81 (.DATA_A (INT_SUM[128]) , .DATA_B (INT_SUM[130]) , .DATA_C (INT_CARRY[90]) , .SAVE (SUM[20]) , .CARRY (CARRY[20]) );
FULL_ADDER FA_82 (.DATA_A (SUMMAND[132]) , .DATA_B (SUMMAND[133]) , .DATA_C (SUMMAND[134]) , .SAVE (INT_SUM[131]) , .CARRY (INT_CARRY[101]) );
FULL_ADDER FA_83 (.DATA_A (SUMMAND[135]) , .DATA_B (SUMMAND[136]) , .DATA_C (SUMMAND[137]) , .SAVE (INT_SUM[132]) , .CARRY (INT_CARRY[102]) );
FULL_ADDER FA_84 (.DATA_A (SUMMAND[138]) , .DATA_B (SUMMAND[139]) , .DATA_C (SUMMAND[140]) , .SAVE (INT_SUM[133]) , .CARRY (INT_CARRY[103]) );
assign INT_SUM[134] = SUMMAND[141];
assign INT_SUM[135] = SUMMAND[142];
FULL_ADDER FA_85 (.DATA_A (INT_SUM[131]) , .DATA_B (INT_SUM[132]) , .DATA_C (INT_SUM[133]) , .SAVE (INT_SUM[136]) , .CARRY (INT_CARRY[104]) );
FULL_ADDER FA_86 (.DATA_A (INT_SUM[134]) , .DATA_B (INT_SUM[135]) , .DATA_C (INT_CARRY[91]) , .SAVE (INT_SUM[137]) , .CARRY (INT_CARRY[105]) );
FULL_ADDER FA_87 (.DATA_A (INT_CARRY[92]) , .DATA_B (INT_CARRY[93]) , .DATA_C (INT_CARRY[94]) , .SAVE (INT_SUM[138]) , .CARRY (INT_CARRY[106]) );
FULL_ADDER FA_88 (.DATA_A (INT_SUM[136]) , .DATA_B (INT_SUM[137]) , .DATA_C (INT_SUM[138]) , .SAVE (INT_SUM[139]) , .CARRY (INT_CARRY[107]) );
HALF_ADDER HA_19 (.DATA_A (INT_CARRY[95]) , .DATA_B (INT_CARRY[96]) , .SAVE (INT_SUM[140]) , .CARRY (INT_CARRY[108]) );
FULL_ADDER FA_89 (.DATA_A (INT_SUM[139]) , .DATA_B (INT_SUM[140]) , .DATA_C (INT_CARRY[97]) , .SAVE (INT_SUM[141]) , .CARRY (INT_CARRY[109]) );
assign INT_SUM[143] = INT_CARRY[98];
FLIPFLOP LA_43 (.DIN (INT_SUM[141]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[142]) );
FLIPFLOP LA_44 (.DIN (INT_SUM[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[144]) );
FLIPFLOP LA_45 (.DIN (INT_CARRY[99]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[100]) );
FULL_ADDER FA_90 (.DATA_A (INT_SUM[142]) , .DATA_B (INT_SUM[144]) , .DATA_C (INT_CARRY[100]) , .SAVE (SUM[21]) , .CARRY (CARRY[21]) );
FULL_ADDER FA_91 (.DATA_A (SUMMAND[143]) , .DATA_B (SUMMAND[144]) , .DATA_C (SUMMAND[145]) , .SAVE (INT_SUM[145]) , .CARRY (INT_CARRY[111]) );
FULL_ADDER FA_92 (.DATA_A (SUMMAND[146]) , .DATA_B (SUMMAND[147]) , .DATA_C (SUMMAND[148]) , .SAVE (INT_SUM[146]) , .CARRY (INT_CARRY[112]) );
FULL_ADDER FA_93 (.DATA_A (SUMMAND[149]) , .DATA_B (SUMMAND[150]) , .DATA_C (SUMMAND[151]) , .SAVE (INT_SUM[147]) , .CARRY (INT_CARRY[113]) );
FULL_ADDER FA_94 (.DATA_A (SUMMAND[152]) , .DATA_B (SUMMAND[153]) , .DATA_C (SUMMAND[154]) , .SAVE (INT_SUM[148]) , .CARRY (INT_CARRY[114]) );
assign INT_SUM[149] = SUMMAND[155];
FULL_ADDER FA_95 (.DATA_A (INT_SUM[145]) , .DATA_B (INT_SUM[146]) , .DATA_C (INT_SUM[147]) , .SAVE (INT_SUM[150]) , .CARRY (INT_CARRY[115]) );
FULL_ADDER FA_96 (.DATA_A (INT_SUM[148]) , .DATA_B (INT_SUM[149]) , .DATA_C (INT_CARRY[101]) , .SAVE (INT_SUM[151]) , .CARRY (INT_CARRY[116]) );
HALF_ADDER HA_20 (.DATA_A (INT_CARRY[102]) , .DATA_B (INT_CARRY[103]) , .SAVE (INT_SUM[152]) , .CARRY (INT_CARRY[117]) );
FULL_ADDER FA_97 (.DATA_A (INT_SUM[150]) , .DATA_B (INT_SUM[151]) , .DATA_C (INT_SUM[152]) , .SAVE (INT_SUM[153]) , .CARRY (INT_CARRY[118]) );
FULL_ADDER FA_98 (.DATA_A (INT_CARRY[104]) , .DATA_B (INT_CARRY[105]) , .DATA_C (INT_CARRY[106]) , .SAVE (INT_SUM[154]) , .CARRY (INT_CARRY[119]) );
FULL_ADDER FA_99 (.DATA_A (INT_SUM[153]) , .DATA_B (INT_SUM[154]) , .DATA_C (INT_CARRY[107]) , .SAVE (INT_SUM[155]) , .CARRY (INT_CARRY[120]) );
assign INT_SUM[157] = INT_CARRY[108];
FLIPFLOP LA_46 (.DIN (INT_SUM[155]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[156]) );
FLIPFLOP LA_47 (.DIN (INT_SUM[157]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[158]) );
FLIPFLOP LA_48 (.DIN (INT_CARRY[109]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[110]) );
FULL_ADDER FA_100 (.DATA_A (INT_SUM[156]) , .DATA_B (INT_SUM[158]) , .DATA_C (INT_CARRY[110]) , .SAVE (SUM[22]) , .CARRY (CARRY[22]) );
FULL_ADDER FA_101 (.DATA_A (SUMMAND[156]) , .DATA_B (SUMMAND[157]) , .DATA_C (SUMMAND[158]) , .SAVE (INT_SUM[159]) , .CARRY (INT_CARRY[122]) );
FULL_ADDER FA_102 (.DATA_A (SUMMAND[159]) , .DATA_B (SUMMAND[160]) , .DATA_C (SUMMAND[161]) , .SAVE (INT_SUM[160]) , .CARRY (INT_CARRY[123]) );
FULL_ADDER FA_103 (.DATA_A (SUMMAND[162]) , .DATA_B (SUMMAND[163]) , .DATA_C (SUMMAND[164]) , .SAVE (INT_SUM[161]) , .CARRY (INT_CARRY[124]) );
FULL_ADDER FA_104 (.DATA_A (SUMMAND[165]) , .DATA_B (SUMMAND[166]) , .DATA_C (SUMMAND[167]) , .SAVE (INT_SUM[162]) , .CARRY (INT_CARRY[125]) );
FULL_ADDER FA_105 (.DATA_A (INT_SUM[159]) , .DATA_B (INT_SUM[160]) , .DATA_C (INT_SUM[161]) , .SAVE (INT_SUM[163]) , .CARRY (INT_CARRY[126]) );
FULL_ADDER FA_106 (.DATA_A (INT_SUM[162]) , .DATA_B (INT_CARRY[111]) , .DATA_C (INT_CARRY[112]) , .SAVE (INT_SUM[164]) , .CARRY (INT_CARRY[127]) );
HALF_ADDER HA_21 (.DATA_A (INT_CARRY[113]) , .DATA_B (INT_CARRY[114]) , .SAVE (INT_SUM[165]) , .CARRY (INT_CARRY[128]) );
FULL_ADDER FA_107 (.DATA_A (INT_SUM[163]) , .DATA_B (INT_SUM[164]) , .DATA_C (INT_SUM[165]) , .SAVE (INT_SUM[166]) , .CARRY (INT_CARRY[129]) );
FULL_ADDER FA_108 (.DATA_A (INT_CARRY[115]) , .DATA_B (INT_CARRY[116]) , .DATA_C (INT_CARRY[117]) , .SAVE (INT_SUM[167]) , .CARRY (INT_CARRY[130]) );
FULL_ADDER FA_109 (.DATA_A (INT_SUM[166]) , .DATA_B (INT_SUM[167]) , .DATA_C (INT_CARRY[118]) , .SAVE (INT_SUM[168]) , .CARRY (INT_CARRY[131]) );
assign INT_SUM[170] = INT_CARRY[119];
FLIPFLOP LA_49 (.DIN (INT_SUM[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[169]) );
FLIPFLOP LA_50 (.DIN (INT_SUM[170]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[171]) );
FLIPFLOP LA_51 (.DIN (INT_CARRY[120]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[121]) );
FULL_ADDER FA_110 (.DATA_A (INT_SUM[169]) , .DATA_B (INT_SUM[171]) , .DATA_C (INT_CARRY[121]) , .SAVE (SUM[23]) , .CARRY (CARRY[23]) );
FULL_ADDER FA_111 (.DATA_A (SUMMAND[168]) , .DATA_B (SUMMAND[169]) , .DATA_C (SUMMAND[170]) , .SAVE (INT_SUM[172]) , .CARRY (INT_CARRY[133]) );
FULL_ADDER FA_112 (.DATA_A (SUMMAND[171]) , .DATA_B (SUMMAND[172]) , .DATA_C (SUMMAND[173]) , .SAVE (INT_SUM[173]) , .CARRY (INT_CARRY[134]) );
FULL_ADDER FA_113 (.DATA_A (SUMMAND[174]) , .DATA_B (SUMMAND[175]) , .DATA_C (SUMMAND[176]) , .SAVE (INT_SUM[174]) , .CARRY (INT_CARRY[135]) );
FULL_ADDER FA_114 (.DATA_A (SUMMAND[177]) , .DATA_B (SUMMAND[178]) , .DATA_C (SUMMAND[179]) , .SAVE (INT_SUM[175]) , .CARRY (INT_CARRY[136]) );
HALF_ADDER HA_22 (.DATA_A (SUMMAND[180]) , .DATA_B (SUMMAND[181]) , .SAVE (INT_SUM[176]) , .CARRY (INT_CARRY[137]) );
FULL_ADDER FA_115 (.DATA_A (INT_SUM[172]) , .DATA_B (INT_SUM[173]) , .DATA_C (INT_SUM[174]) , .SAVE (INT_SUM[177]) , .CARRY (INT_CARRY[138]) );
FULL_ADDER FA_116 (.DATA_A (INT_SUM[175]) , .DATA_B (INT_SUM[176]) , .DATA_C (INT_CARRY[122]) , .SAVE (INT_SUM[178]) , .CARRY (INT_CARRY[139]) );
FULL_ADDER FA_117 (.DATA_A (INT_CARRY[123]) , .DATA_B (INT_CARRY[124]) , .DATA_C (INT_CARRY[125]) , .SAVE (INT_SUM[179]) , .CARRY (INT_CARRY[140]) );
FULL_ADDER FA_118 (.DATA_A (INT_SUM[177]) , .DATA_B (INT_SUM[178]) , .DATA_C (INT_SUM[179]) , .SAVE (INT_SUM[180]) , .CARRY (INT_CARRY[141]) );
FULL_ADDER FA_119 (.DATA_A (INT_CARRY[126]) , .DATA_B (INT_CARRY[127]) , .DATA_C (INT_CARRY[128]) , .SAVE (INT_SUM[181]) , .CARRY (INT_CARRY[142]) );
FULL_ADDER FA_120 (.DATA_A (INT_SUM[180]) , .DATA_B (INT_SUM[181]) , .DATA_C (INT_CARRY[129]) , .SAVE (INT_SUM[182]) , .CARRY (INT_CARRY[143]) );
assign INT_SUM[184] = INT_CARRY[130];
FLIPFLOP LA_52 (.DIN (INT_SUM[182]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[183]) );
FLIPFLOP LA_53 (.DIN (INT_SUM[184]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[185]) );
FLIPFLOP LA_54 (.DIN (INT_CARRY[131]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[132]) );
FULL_ADDER FA_121 (.DATA_A (INT_SUM[183]) , .DATA_B (INT_SUM[185]) , .DATA_C (INT_CARRY[132]) , .SAVE (SUM[24]) , .CARRY (CARRY[24]) );
FULL_ADDER FA_122 (.DATA_A (SUMMAND[182]) , .DATA_B (SUMMAND[183]) , .DATA_C (SUMMAND[184]) , .SAVE (INT_SUM[186]) , .CARRY (INT_CARRY[145]) );
FULL_ADDER FA_123 (.DATA_A (SUMMAND[185]) , .DATA_B (SUMMAND[186]) , .DATA_C (SUMMAND[187]) , .SAVE (INT_SUM[187]) , .CARRY (INT_CARRY[146]) );
FULL_ADDER FA_124 (.DATA_A (SUMMAND[188]) , .DATA_B (SUMMAND[189]) , .DATA_C (SUMMAND[190]) , .SAVE (INT_SUM[188]) , .CARRY (INT_CARRY[147]) );
FULL_ADDER FA_125 (.DATA_A (SUMMAND[191]) , .DATA_B (SUMMAND[192]) , .DATA_C (SUMMAND[193]) , .SAVE (INT_SUM[189]) , .CARRY (INT_CARRY[148]) );
assign INT_SUM[190] = SUMMAND[194];
FULL_ADDER FA_126 (.DATA_A (INT_SUM[186]) , .DATA_B (INT_SUM[187]) , .DATA_C (INT_SUM[188]) , .SAVE (INT_SUM[191]) , .CARRY (INT_CARRY[149]) );
FULL_ADDER FA_127 (.DATA_A (INT_SUM[189]) , .DATA_B (INT_SUM[190]) , .DATA_C (INT_CARRY[133]) , .SAVE (INT_SUM[192]) , .CARRY (INT_CARRY[150]) );
FULL_ADDER FA_128 (.DATA_A (INT_CARRY[134]) , .DATA_B (INT_CARRY[135]) , .DATA_C (INT_CARRY[136]) , .SAVE (INT_SUM[193]) , .CARRY (INT_CARRY[151]) );
assign INT_SUM[194] = INT_CARRY[137];
FULL_ADDER FA_129 (.DATA_A (INT_SUM[191]) , .DATA_B (INT_SUM[192]) , .DATA_C (INT_SUM[193]) , .SAVE (INT_SUM[195]) , .CARRY (INT_CARRY[152]) );
FULL_ADDER FA_130 (.DATA_A (INT_SUM[194]) , .DATA_B (INT_CARRY[138]) , .DATA_C (INT_CARRY[139]) , .SAVE (INT_SUM[196]) , .CARRY (INT_CARRY[153]) );
assign INT_SUM[197] = INT_CARRY[140];
FULL_ADDER FA_131 (.DATA_A (INT_SUM[195]) , .DATA_B (INT_SUM[196]) , .DATA_C (INT_SUM[197]) , .SAVE (INT_SUM[198]) , .CARRY (INT_CARRY[154]) );
HALF_ADDER HA_23 (.DATA_A (INT_CARRY[141]) , .DATA_B (INT_CARRY[142]) , .SAVE (INT_SUM[200]) , .CARRY (INT_CARRY[156]) );
FLIPFLOP LA_55 (.DIN (INT_SUM[198]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[199]) );
FLIPFLOP LA_56 (.DIN (INT_SUM[200]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[201]) );
FLIPFLOP LA_57 (.DIN (INT_CARRY[143]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[144]) );
FULL_ADDER FA_132 (.DATA_A (INT_SUM[199]) , .DATA_B (INT_SUM[201]) , .DATA_C (INT_CARRY[144]) , .SAVE (SUM[25]) , .CARRY (CARRY[25]) );
FULL_ADDER FA_133 (.DATA_A (SUMMAND[195]) , .DATA_B (SUMMAND[196]) , .DATA_C (SUMMAND[197]) , .SAVE (INT_SUM[202]) , .CARRY (INT_CARRY[158]) );
FULL_ADDER FA_134 (.DATA_A (SUMMAND[198]) , .DATA_B (SUMMAND[199]) , .DATA_C (SUMMAND[200]) , .SAVE (INT_SUM[203]) , .CARRY (INT_CARRY[159]) );
FULL_ADDER FA_135 (.DATA_A (SUMMAND[201]) , .DATA_B (SUMMAND[202]) , .DATA_C (SUMMAND[203]) , .SAVE (INT_SUM[204]) , .CARRY (INT_CARRY[160]) );
FULL_ADDER FA_136 (.DATA_A (SUMMAND[204]) , .DATA_B (SUMMAND[205]) , .DATA_C (SUMMAND[206]) , .SAVE (INT_SUM[205]) , .CARRY (INT_CARRY[161]) );
FULL_ADDER FA_137 (.DATA_A (SUMMAND[207]) , .DATA_B (SUMMAND[208]) , .DATA_C (SUMMAND[209]) , .SAVE (INT_SUM[206]) , .CARRY (INT_CARRY[162]) );
FULL_ADDER FA_138 (.DATA_A (INT_SUM[202]) , .DATA_B (INT_SUM[203]) , .DATA_C (INT_SUM[204]) , .SAVE (INT_SUM[207]) , .CARRY (INT_CARRY[163]) );
FULL_ADDER FA_139 (.DATA_A (INT_SUM[205]) , .DATA_B (INT_SUM[206]) , .DATA_C (INT_CARRY[145]) , .SAVE (INT_SUM[208]) , .CARRY (INT_CARRY[164]) );
FULL_ADDER FA_140 (.DATA_A (INT_CARRY[146]) , .DATA_B (INT_CARRY[147]) , .DATA_C (INT_CARRY[148]) , .SAVE (INT_SUM[209]) , .CARRY (INT_CARRY[165]) );
FULL_ADDER FA_141 (.DATA_A (INT_SUM[207]) , .DATA_B (INT_SUM[208]) , .DATA_C (INT_SUM[209]) , .SAVE (INT_SUM[210]) , .CARRY (INT_CARRY[166]) );
FULL_ADDER FA_142 (.DATA_A (INT_CARRY[149]) , .DATA_B (INT_CARRY[150]) , .DATA_C (INT_CARRY[151]) , .SAVE (INT_SUM[211]) , .CARRY (INT_CARRY[167]) );
FULL_ADDER FA_143 (.DATA_A (INT_SUM[210]) , .DATA_B (INT_SUM[211]) , .DATA_C (INT_CARRY[152]) , .SAVE (INT_SUM[212]) , .CARRY (INT_CARRY[168]) );
assign INT_SUM[214] = INT_CARRY[153];
FLIPFLOP LA_58 (.DIN (INT_SUM[212]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[213]) );
FLIPFLOP LA_59 (.DIN (INT_SUM[214]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[215]) );
FLIPFLOP LA_60 (.DIN (INT_CARRY[154]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[155]) );
FULL_ADDER FA_144 (.DATA_A (INT_SUM[213]) , .DATA_B (INT_SUM[215]) , .DATA_C (INT_CARRY[155]) , .SAVE (INT_SUM[216]) , .CARRY (INT_CARRY[170]) );
FLIPFLOP LA_61 (.DIN (INT_CARRY[156]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[157]) );
assign INT_SUM[217] = INT_CARRY[157];
HALF_ADDER HA_24 (.DATA_A (INT_SUM[216]) , .DATA_B (INT_SUM[217]) , .SAVE (SUM[26]) , .CARRY (CARRY[26]) );
FULL_ADDER FA_145 (.DATA_A (SUMMAND[210]) , .DATA_B (SUMMAND[211]) , .DATA_C (SUMMAND[212]) , .SAVE (INT_SUM[218]) , .CARRY (INT_CARRY[171]) );
FULL_ADDER FA_146 (.DATA_A (SUMMAND[213]) , .DATA_B (SUMMAND[214]) , .DATA_C (SUMMAND[215]) , .SAVE (INT_SUM[219]) , .CARRY (INT_CARRY[172]) );
FULL_ADDER FA_147 (.DATA_A (SUMMAND[216]) , .DATA_B (SUMMAND[217]) , .DATA_C (SUMMAND[218]) , .SAVE (INT_SUM[220]) , .CARRY (INT_CARRY[173]) );
FULL_ADDER FA_148 (.DATA_A (SUMMAND[219]) , .DATA_B (SUMMAND[220]) , .DATA_C (SUMMAND[221]) , .SAVE (INT_SUM[221]) , .CARRY (INT_CARRY[174]) );
HALF_ADDER HA_25 (.DATA_A (SUMMAND[222]) , .DATA_B (SUMMAND[223]) , .SAVE (INT_SUM[222]) , .CARRY (INT_CARRY[175]) );
FULL_ADDER FA_149 (.DATA_A (INT_SUM[218]) , .DATA_B (INT_SUM[219]) , .DATA_C (INT_SUM[220]) , .SAVE (INT_SUM[223]) , .CARRY (INT_CARRY[176]) );
FULL_ADDER FA_150 (.DATA_A (INT_SUM[221]) , .DATA_B (INT_SUM[222]) , .DATA_C (INT_CARRY[158]) , .SAVE (INT_SUM[224]) , .CARRY (INT_CARRY[177]) );
FULL_ADDER FA_151 (.DATA_A (INT_CARRY[159]) , .DATA_B (INT_CARRY[160]) , .DATA_C (INT_CARRY[161]) , .SAVE (INT_SUM[225]) , .CARRY (INT_CARRY[178]) );
assign INT_SUM[226] = INT_CARRY[162];
FULL_ADDER FA_152 (.DATA_A (INT_SUM[223]) , .DATA_B (INT_SUM[224]) , .DATA_C (INT_SUM[225]) , .SAVE (INT_SUM[227]) , .CARRY (INT_CARRY[179]) );
FULL_ADDER FA_153 (.DATA_A (INT_SUM[226]) , .DATA_B (INT_CARRY[163]) , .DATA_C (INT_CARRY[164]) , .SAVE (INT_SUM[228]) , .CARRY (INT_CARRY[180]) );
assign INT_SUM[229] = INT_CARRY[165];
FULL_ADDER FA_154 (.DATA_A (INT_SUM[227]) , .DATA_B (INT_SUM[228]) , .DATA_C (INT_SUM[229]) , .SAVE (INT_SUM[230]) , .CARRY (INT_CARRY[181]) );
assign INT_SUM[232] = INT_CARRY[166];
assign INT_SUM[234] = INT_CARRY[167];
FLIPFLOP LA_62 (.DIN (INT_SUM[230]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[231]) );
FLIPFLOP LA_63 (.DIN (INT_SUM[232]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[233]) );
FLIPFLOP LA_64 (.DIN (INT_SUM[234]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[235]) );
FULL_ADDER FA_155 (.DATA_A (INT_SUM[231]) , .DATA_B (INT_SUM[233]) , .DATA_C (INT_SUM[235]) , .SAVE (INT_SUM[236]) , .CARRY (INT_CARRY[183]) );
FLIPFLOP LA_65 (.DIN (INT_CARRY[168]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[169]) );
assign INT_SUM[237] = INT_CARRY[169];
FULL_ADDER FA_156 (.DATA_A (INT_SUM[236]) , .DATA_B (INT_SUM[237]) , .DATA_C (INT_CARRY[170]) , .SAVE (SUM[27]) , .CARRY (CARRY[27]) );
FULL_ADDER FA_157 (.DATA_A (SUMMAND[224]) , .DATA_B (SUMMAND[225]) , .DATA_C (SUMMAND[226]) , .SAVE (INT_SUM[238]) , .CARRY (INT_CARRY[184]) );
FULL_ADDER FA_158 (.DATA_A (SUMMAND[227]) , .DATA_B (SUMMAND[228]) , .DATA_C (SUMMAND[229]) , .SAVE (INT_SUM[239]) , .CARRY (INT_CARRY[185]) );
FULL_ADDER FA_159 (.DATA_A (SUMMAND[230]) , .DATA_B (SUMMAND[231]) , .DATA_C (SUMMAND[232]) , .SAVE (INT_SUM[240]) , .CARRY (INT_CARRY[186]) );
FULL_ADDER FA_160 (.DATA_A (SUMMAND[233]) , .DATA_B (SUMMAND[234]) , .DATA_C (SUMMAND[235]) , .SAVE (INT_SUM[241]) , .CARRY (INT_CARRY[187]) );
FULL_ADDER FA_161 (.DATA_A (SUMMAND[236]) , .DATA_B (SUMMAND[237]) , .DATA_C (SUMMAND[238]) , .SAVE (INT_SUM[242]) , .CARRY (INT_CARRY[188]) );
assign INT_SUM[243] = SUMMAND[239];
FULL_ADDER FA_162 (.DATA_A (INT_SUM[238]) , .DATA_B (INT_SUM[239]) , .DATA_C (INT_SUM[240]) , .SAVE (INT_SUM[244]) , .CARRY (INT_CARRY[189]) );
FULL_ADDER FA_163 (.DATA_A (INT_SUM[241]) , .DATA_B (INT_SUM[242]) , .DATA_C (INT_SUM[243]) , .SAVE (INT_SUM[245]) , .CARRY (INT_CARRY[190]) );
FULL_ADDER FA_164 (.DATA_A (INT_CARRY[171]) , .DATA_B (INT_CARRY[172]) , .DATA_C (INT_CARRY[173]) , .SAVE (INT_SUM[246]) , .CARRY (INT_CARRY[191]) );
assign INT_SUM[247] = INT_CARRY[174];
assign INT_SUM[248] = INT_CARRY[175];
FULL_ADDER FA_165 (.DATA_A (INT_SUM[244]) , .DATA_B (INT_SUM[245]) , .DATA_C (INT_SUM[246]) , .SAVE (INT_SUM[249]) , .CARRY (INT_CARRY[192]) );
FULL_ADDER FA_166 (.DATA_A (INT_SUM[247]) , .DATA_B (INT_SUM[248]) , .DATA_C (INT_CARRY[176]) , .SAVE (INT_SUM[250]) , .CARRY (INT_CARRY[193]) );
assign INT_SUM[251] = INT_CARRY[177];
assign INT_SUM[252] = INT_CARRY[178];
FULL_ADDER FA_167 (.DATA_A (INT_SUM[249]) , .DATA_B (INT_SUM[250]) , .DATA_C (INT_SUM[251]) , .SAVE (INT_SUM[253]) , .CARRY (INT_CARRY[194]) );
FULL_ADDER FA_168 (.DATA_A (INT_SUM[252]) , .DATA_B (INT_CARRY[179]) , .DATA_C (INT_CARRY[180]) , .SAVE (INT_SUM[255]) , .CARRY (INT_CARRY[196]) );
FLIPFLOP LA_66 (.DIN (INT_SUM[253]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[254]) );
FLIPFLOP LA_67 (.DIN (INT_SUM[255]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[256]) );
FLIPFLOP LA_68 (.DIN (INT_CARRY[181]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[182]) );
FULL_ADDER FA_169 (.DATA_A (INT_SUM[254]) , .DATA_B (INT_SUM[256]) , .DATA_C (INT_CARRY[182]) , .SAVE (INT_SUM[257]) , .CARRY (INT_CARRY[198]) );
HALF_ADDER HA_26 (.DATA_A (INT_SUM[257]) , .DATA_B (INT_CARRY[183]) , .SAVE (SUM[28]) , .CARRY (CARRY[28]) );
FULL_ADDER FA_170 (.DATA_A (SUMMAND[240]) , .DATA_B (SUMMAND[241]) , .DATA_C (SUMMAND[242]) , .SAVE (INT_SUM[258]) , .CARRY (INT_CARRY[199]) );
FULL_ADDER FA_171 (.DATA_A (SUMMAND[243]) , .DATA_B (SUMMAND[244]) , .DATA_C (SUMMAND[245]) , .SAVE (INT_SUM[259]) , .CARRY (INT_CARRY[200]) );
FULL_ADDER FA_172 (.DATA_A (SUMMAND[246]) , .DATA_B (SUMMAND[247]) , .DATA_C (SUMMAND[248]) , .SAVE (INT_SUM[260]) , .CARRY (INT_CARRY[201]) );
FULL_ADDER FA_173 (.DATA_A (SUMMAND[249]) , .DATA_B (SUMMAND[250]) , .DATA_C (SUMMAND[251]) , .SAVE (INT_SUM[261]) , .CARRY (INT_CARRY[202]) );
FULL_ADDER FA_174 (.DATA_A (SUMMAND[252]) , .DATA_B (SUMMAND[253]) , .DATA_C (SUMMAND[254]) , .SAVE (INT_SUM[262]) , .CARRY (INT_CARRY[203]) );
FULL_ADDER FA_175 (.DATA_A (INT_SUM[258]) , .DATA_B (INT_SUM[259]) , .DATA_C (INT_SUM[260]) , .SAVE (INT_SUM[263]) , .CARRY (INT_CARRY[204]) );
FULL_ADDER FA_176 (.DATA_A (INT_SUM[261]) , .DATA_B (INT_SUM[262]) , .DATA_C (INT_CARRY[184]) , .SAVE (INT_SUM[264]) , .CARRY (INT_CARRY[205]) );
FULL_ADDER FA_177 (.DATA_A (INT_CARRY[185]) , .DATA_B (INT_CARRY[186]) , .DATA_C (INT_CARRY[187]) , .SAVE (INT_SUM[265]) , .CARRY (INT_CARRY[206]) );
assign INT_SUM[266] = INT_CARRY[188];
FULL_ADDER FA_178 (.DATA_A (INT_SUM[263]) , .DATA_B (INT_SUM[264]) , .DATA_C (INT_SUM[265]) , .SAVE (INT_SUM[267]) , .CARRY (INT_CARRY[207]) );
FULL_ADDER FA_179 (.DATA_A (INT_SUM[266]) , .DATA_B (INT_CARRY[189]) , .DATA_C (INT_CARRY[190]) , .SAVE (INT_SUM[268]) , .CARRY (INT_CARRY[208]) );
assign INT_SUM[269] = INT_CARRY[191];
FULL_ADDER FA_180 (.DATA_A (INT_SUM[267]) , .DATA_B (INT_SUM[268]) , .DATA_C (INT_SUM[269]) , .SAVE (INT_SUM[270]) , .CARRY (INT_CARRY[209]) );
HALF_ADDER HA_27 (.DATA_A (INT_CARRY[192]) , .DATA_B (INT_CARRY[193]) , .SAVE (INT_SUM[272]) , .CARRY (INT_CARRY[211]) );
FLIPFLOP LA_69 (.DIN (INT_SUM[270]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[271]) );
FLIPFLOP LA_70 (.DIN (INT_SUM[272]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[273]) );
FLIPFLOP LA_71 (.DIN (INT_CARRY[194]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[195]) );
FULL_ADDER FA_181 (.DATA_A (INT_SUM[271]) , .DATA_B (INT_SUM[273]) , .DATA_C (INT_CARRY[195]) , .SAVE (INT_SUM[274]) , .CARRY (INT_CARRY[213]) );
FLIPFLOP LA_72 (.DIN (INT_CARRY[196]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[197]) );
assign INT_SUM[275] = INT_CARRY[197];
FULL_ADDER FA_182 (.DATA_A (INT_SUM[274]) , .DATA_B (INT_SUM[275]) , .DATA_C (INT_CARRY[198]) , .SAVE (SUM[29]) , .CARRY (CARRY[29]) );
FULL_ADDER FA_183 (.DATA_A (SUMMAND[255]) , .DATA_B (SUMMAND[256]) , .DATA_C (SUMMAND[257]) , .SAVE (INT_SUM[276]) , .CARRY (INT_CARRY[214]) );
FULL_ADDER FA_184 (.DATA_A (SUMMAND[258]) , .DATA_B (SUMMAND[259]) , .DATA_C (SUMMAND[260]) , .SAVE (INT_SUM[277]) , .CARRY (INT_CARRY[215]) );
FULL_ADDER FA_185 (.DATA_A (SUMMAND[261]) , .DATA_B (SUMMAND[262]) , .DATA_C (SUMMAND[263]) , .SAVE (INT_SUM[278]) , .CARRY (INT_CARRY[216]) );
FULL_ADDER FA_186 (.DATA_A (SUMMAND[264]) , .DATA_B (SUMMAND[265]) , .DATA_C (SUMMAND[266]) , .SAVE (INT_SUM[279]) , .CARRY (INT_CARRY[217]) );
FULL_ADDER FA_187 (.DATA_A (SUMMAND[267]) , .DATA_B (SUMMAND[268]) , .DATA_C (SUMMAND[269]) , .SAVE (INT_SUM[280]) , .CARRY (INT_CARRY[218]) );
assign INT_SUM[281] = SUMMAND[270];
assign INT_SUM[282] = SUMMAND[271];
FULL_ADDER FA_188 (.DATA_A (INT_SUM[276]) , .DATA_B (INT_SUM[277]) , .DATA_C (INT_SUM[278]) , .SAVE (INT_SUM[283]) , .CARRY (INT_CARRY[219]) );
FULL_ADDER FA_189 (.DATA_A (INT_SUM[279]) , .DATA_B (INT_SUM[280]) , .DATA_C (INT_SUM[281]) , .SAVE (INT_SUM[284]) , .CARRY (INT_CARRY[220]) );
FULL_ADDER FA_190 (.DATA_A (INT_SUM[282]) , .DATA_B (INT_CARRY[199]) , .DATA_C (INT_CARRY[200]) , .SAVE (INT_SUM[285]) , .CARRY (INT_CARRY[221]) );
FULL_ADDER FA_191 (.DATA_A (INT_CARRY[201]) , .DATA_B (INT_CARRY[202]) , .DATA_C (INT_CARRY[203]) , .SAVE (INT_SUM[286]) , .CARRY (INT_CARRY[222]) );
FULL_ADDER FA_192 (.DATA_A (INT_SUM[283]) , .DATA_B (INT_SUM[284]) , .DATA_C (INT_SUM[285]) , .SAVE (INT_SUM[287]) , .CARRY (INT_CARRY[223]) );
FULL_ADDER FA_193 (.DATA_A (INT_SUM[286]) , .DATA_B (INT_CARRY[204]) , .DATA_C (INT_CARRY[205]) , .SAVE (INT_SUM[288]) , .CARRY (INT_CARRY[224]) );
assign INT_SUM[289] = INT_CARRY[206];
FULL_ADDER FA_194 (.DATA_A (INT_SUM[287]) , .DATA_B (INT_SUM[288]) , .DATA_C (INT_SUM[289]) , .SAVE (INT_SUM[290]) , .CARRY (INT_CARRY[225]) );
HALF_ADDER HA_28 (.DATA_A (INT_CARRY[207]) , .DATA_B (INT_CARRY[208]) , .SAVE (INT_SUM[292]) , .CARRY (INT_CARRY[227]) );
FLIPFLOP LA_73 (.DIN (INT_SUM[290]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[291]) );
FLIPFLOP LA_74 (.DIN (INT_SUM[292]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[293]) );
FLIPFLOP LA_75 (.DIN (INT_CARRY[209]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[210]) );
FULL_ADDER FA_195 (.DATA_A (INT_SUM[291]) , .DATA_B (INT_SUM[293]) , .DATA_C (INT_CARRY[210]) , .SAVE (INT_SUM[294]) , .CARRY (INT_CARRY[229]) );
FLIPFLOP LA_76 (.DIN (INT_CARRY[211]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[212]) );
assign INT_SUM[295] = INT_CARRY[212];
FULL_ADDER FA_196 (.DATA_A (INT_SUM[294]) , .DATA_B (INT_SUM[295]) , .DATA_C (INT_CARRY[213]) , .SAVE (SUM[30]) , .CARRY (CARRY[30]) );
FULL_ADDER FA_197 (.DATA_A (SUMMAND[272]) , .DATA_B (SUMMAND[273]) , .DATA_C (SUMMAND[274]) , .SAVE (INT_SUM[296]) , .CARRY (INT_CARRY[230]) );
FULL_ADDER FA_198 (.DATA_A (SUMMAND[275]) , .DATA_B (SUMMAND[276]) , .DATA_C (SUMMAND[277]) , .SAVE (INT_SUM[297]) , .CARRY (INT_CARRY[231]) );
FULL_ADDER FA_199 (.DATA_A (SUMMAND[278]) , .DATA_B (SUMMAND[279]) , .DATA_C (SUMMAND[280]) , .SAVE (INT_SUM[298]) , .CARRY (INT_CARRY[232]) );
FULL_ADDER FA_200 (.DATA_A (SUMMAND[281]) , .DATA_B (SUMMAND[282]) , .DATA_C (SUMMAND[283]) , .SAVE (INT_SUM[299]) , .CARRY (INT_CARRY[233]) );
FULL_ADDER FA_201 (.DATA_A (SUMMAND[284]) , .DATA_B (SUMMAND[285]) , .DATA_C (SUMMAND[286]) , .SAVE (INT_SUM[300]) , .CARRY (INT_CARRY[234]) );
assign INT_SUM[301] = SUMMAND[287];
FULL_ADDER FA_202 (.DATA_A (INT_SUM[296]) , .DATA_B (INT_SUM[297]) , .DATA_C (INT_SUM[298]) , .SAVE (INT_SUM[302]) , .CARRY (INT_CARRY[235]) );
FULL_ADDER FA_203 (.DATA_A (INT_SUM[299]) , .DATA_B (INT_SUM[300]) , .DATA_C (INT_SUM[301]) , .SAVE (INT_SUM[303]) , .CARRY (INT_CARRY[236]) );
FULL_ADDER FA_204 (.DATA_A (INT_CARRY[214]) , .DATA_B (INT_CARRY[215]) , .DATA_C (INT_CARRY[216]) , .SAVE (INT_SUM[304]) , .CARRY (INT_CARRY[237]) );
assign INT_SUM[305] = INT_CARRY[217];
assign INT_SUM[306] = INT_CARRY[218];
FULL_ADDER FA_205 (.DATA_A (INT_SUM[302]) , .DATA_B (INT_SUM[303]) , .DATA_C (INT_SUM[304]) , .SAVE (INT_SUM[307]) , .CARRY (INT_CARRY[238]) );
FULL_ADDER FA_206 (.DATA_A (INT_SUM[305]) , .DATA_B (INT_SUM[306]) , .DATA_C (INT_CARRY[219]) , .SAVE (INT_SUM[308]) , .CARRY (INT_CARRY[239]) );
FULL_ADDER FA_207 (.DATA_A (INT_CARRY[220]) , .DATA_B (INT_CARRY[221]) , .DATA_C (INT_CARRY[222]) , .SAVE (INT_SUM[309]) , .CARRY (INT_CARRY[240]) );
FULL_ADDER FA_208 (.DATA_A (INT_SUM[307]) , .DATA_B (INT_SUM[308]) , .DATA_C (INT_SUM[309]) , .SAVE (INT_SUM[310]) , .CARRY (INT_CARRY[241]) );
HALF_ADDER HA_29 (.DATA_A (INT_CARRY[223]) , .DATA_B (INT_CARRY[224]) , .SAVE (INT_SUM[312]) , .CARRY (INT_CARRY[243]) );
FLIPFLOP LA_77 (.DIN (INT_SUM[310]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[311]) );
FLIPFLOP LA_78 (.DIN (INT_SUM[312]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[313]) );
FLIPFLOP LA_79 (.DIN (INT_CARRY[225]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[226]) );
FULL_ADDER FA_209 (.DATA_A (INT_SUM[311]) , .DATA_B (INT_SUM[313]) , .DATA_C (INT_CARRY[226]) , .SAVE (INT_SUM[314]) , .CARRY (INT_CARRY[245]) );
FLIPFLOP LA_80 (.DIN (INT_CARRY[227]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[228]) );
assign INT_SUM[315] = INT_CARRY[228];
FULL_ADDER FA_210 (.DATA_A (INT_SUM[314]) , .DATA_B (INT_SUM[315]) , .DATA_C (INT_CARRY[229]) , .SAVE (SUM[31]) , .CARRY (CARRY[31]) );
FULL_ADDER FA_211 (.DATA_A (SUMMAND[288]) , .DATA_B (SUMMAND[289]) , .DATA_C (SUMMAND[290]) , .SAVE (INT_SUM[316]) , .CARRY (INT_CARRY[246]) );
FULL_ADDER FA_212 (.DATA_A (SUMMAND[291]) , .DATA_B (SUMMAND[292]) , .DATA_C (SUMMAND[293]) , .SAVE (INT_SUM[317]) , .CARRY (INT_CARRY[247]) );
FULL_ADDER FA_213 (.DATA_A (SUMMAND[294]) , .DATA_B (SUMMAND[295]) , .DATA_C (SUMMAND[296]) , .SAVE (INT_SUM[318]) , .CARRY (INT_CARRY[248]) );
FULL_ADDER FA_214 (.DATA_A (SUMMAND[297]) , .DATA_B (SUMMAND[298]) , .DATA_C (SUMMAND[299]) , .SAVE (INT_SUM[319]) , .CARRY (INT_CARRY[249]) );
FULL_ADDER FA_215 (.DATA_A (SUMMAND[300]) , .DATA_B (SUMMAND[301]) , .DATA_C (SUMMAND[302]) , .SAVE (INT_SUM[320]) , .CARRY (INT_CARRY[250]) );
assign INT_SUM[321] = SUMMAND[303];
FULL_ADDER FA_216 (.DATA_A (INT_SUM[316]) , .DATA_B (INT_SUM[317]) , .DATA_C (INT_SUM[318]) , .SAVE (INT_SUM[322]) , .CARRY (INT_CARRY[251]) );
FULL_ADDER FA_217 (.DATA_A (INT_SUM[319]) , .DATA_B (INT_SUM[320]) , .DATA_C (INT_SUM[321]) , .SAVE (INT_SUM[323]) , .CARRY (INT_CARRY[252]) );
FULL_ADDER FA_218 (.DATA_A (INT_CARRY[230]) , .DATA_B (INT_CARRY[231]) , .DATA_C (INT_CARRY[232]) , .SAVE (INT_SUM[324]) , .CARRY (INT_CARRY[253]) );
HALF_ADDER HA_30 (.DATA_A (INT_CARRY[233]) , .DATA_B (INT_CARRY[234]) , .SAVE (INT_SUM[325]) , .CARRY (INT_CARRY[254]) );
FULL_ADDER FA_219 (.DATA_A (INT_SUM[322]) , .DATA_B (INT_SUM[323]) , .DATA_C (INT_SUM[324]) , .SAVE (INT_SUM[326]) , .CARRY (INT_CARRY[255]) );
FULL_ADDER FA_220 (.DATA_A (INT_SUM[325]) , .DATA_B (INT_CARRY[235]) , .DATA_C (INT_CARRY[236]) , .SAVE (INT_SUM[327]) , .CARRY (INT_CARRY[256]) );
assign INT_SUM[328] = INT_CARRY[237];
FULL_ADDER FA_221 (.DATA_A (INT_SUM[326]) , .DATA_B (INT_SUM[327]) , .DATA_C (INT_SUM[328]) , .SAVE (INT_SUM[329]) , .CARRY (INT_CARRY[257]) );
FULL_ADDER FA_222 (.DATA_A (INT_CARRY[238]) , .DATA_B (INT_CARRY[239]) , .DATA_C (INT_CARRY[240]) , .SAVE (INT_SUM[331]) , .CARRY (INT_CARRY[259]) );
FLIPFLOP LA_81 (.DIN (INT_SUM[329]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[330]) );
FLIPFLOP LA_82 (.DIN (INT_SUM[331]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[332]) );
FLIPFLOP LA_83 (.DIN (INT_CARRY[241]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[242]) );
FULL_ADDER FA_223 (.DATA_A (INT_SUM[330]) , .DATA_B (INT_SUM[332]) , .DATA_C (INT_CARRY[242]) , .SAVE (INT_SUM[333]) , .CARRY (INT_CARRY[261]) );
FLIPFLOP LA_84 (.DIN (INT_CARRY[243]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[244]) );
assign INT_SUM[334] = INT_CARRY[244];
FULL_ADDER FA_224 (.DATA_A (INT_SUM[333]) , .DATA_B (INT_SUM[334]) , .DATA_C (INT_CARRY[245]) , .SAVE (SUM[32]) , .CARRY (CARRY[32]) );
FULL_ADDER FA_225 (.DATA_A (SUMMAND[304]) , .DATA_B (SUMMAND[305]) , .DATA_C (SUMMAND[306]) , .SAVE (INT_SUM[335]) , .CARRY (INT_CARRY[262]) );
FULL_ADDER FA_226 (.DATA_A (SUMMAND[307]) , .DATA_B (SUMMAND[308]) , .DATA_C (SUMMAND[309]) , .SAVE (INT_SUM[336]) , .CARRY (INT_CARRY[263]) );
FULL_ADDER FA_227 (.DATA_A (SUMMAND[310]) , .DATA_B (SUMMAND[311]) , .DATA_C (SUMMAND[312]) , .SAVE (INT_SUM[337]) , .CARRY (INT_CARRY[264]) );
FULL_ADDER FA_228 (.DATA_A (SUMMAND[313]) , .DATA_B (SUMMAND[314]) , .DATA_C (SUMMAND[315]) , .SAVE (INT_SUM[338]) , .CARRY (INT_CARRY[265]) );
FULL_ADDER FA_229 (.DATA_A (SUMMAND[316]) , .DATA_B (SUMMAND[317]) , .DATA_C (SUMMAND[318]) , .SAVE (INT_SUM[339]) , .CARRY (INT_CARRY[266]) );
assign INT_SUM[340] = SUMMAND[319];
assign INT_SUM[341] = SUMMAND[320];
FULL_ADDER FA_230 (.DATA_A (INT_SUM[335]) , .DATA_B (INT_SUM[336]) , .DATA_C (INT_SUM[337]) , .SAVE (INT_SUM[342]) , .CARRY (INT_CARRY[267]) );
FULL_ADDER FA_231 (.DATA_A (INT_SUM[338]) , .DATA_B (INT_SUM[339]) , .DATA_C (INT_SUM[340]) , .SAVE (INT_SUM[343]) , .CARRY (INT_CARRY[268]) );
FULL_ADDER FA_232 (.DATA_A (INT_SUM[341]) , .DATA_B (INT_CARRY[246]) , .DATA_C (INT_CARRY[247]) , .SAVE (INT_SUM[344]) , .CARRY (INT_CARRY[269]) );
FULL_ADDER FA_233 (.DATA_A (INT_CARRY[248]) , .DATA_B (INT_CARRY[249]) , .DATA_C (INT_CARRY[250]) , .SAVE (INT_SUM[345]) , .CARRY (INT_CARRY[270]) );
FULL_ADDER FA_234 (.DATA_A (INT_SUM[342]) , .DATA_B (INT_SUM[343]) , .DATA_C (INT_SUM[344]) , .SAVE (INT_SUM[346]) , .CARRY (INT_CARRY[271]) );
FULL_ADDER FA_235 (.DATA_A (INT_SUM[345]) , .DATA_B (INT_CARRY[251]) , .DATA_C (INT_CARRY[252]) , .SAVE (INT_SUM[347]) , .CARRY (INT_CARRY[272]) );
assign INT_SUM[348] = INT_CARRY[253];
assign INT_SUM[349] = INT_CARRY[254];
FULL_ADDER FA_236 (.DATA_A (INT_SUM[346]) , .DATA_B (INT_SUM[347]) , .DATA_C (INT_SUM[348]) , .SAVE (INT_SUM[350]) , .CARRY (INT_CARRY[273]) );
FULL_ADDER FA_237 (.DATA_A (INT_SUM[349]) , .DATA_B (INT_CARRY[255]) , .DATA_C (INT_CARRY[256]) , .SAVE (INT_SUM[352]) , .CARRY (INT_CARRY[275]) );
FLIPFLOP LA_85 (.DIN (INT_SUM[350]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[351]) );
FLIPFLOP LA_86 (.DIN (INT_SUM[352]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[353]) );
FLIPFLOP LA_87 (.DIN (INT_CARRY[257]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[258]) );
FULL_ADDER FA_238 (.DATA_A (INT_SUM[351]) , .DATA_B (INT_SUM[353]) , .DATA_C (INT_CARRY[258]) , .SAVE (INT_SUM[354]) , .CARRY (INT_CARRY[277]) );
FLIPFLOP LA_88 (.DIN (INT_CARRY[259]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[260]) );
assign INT_SUM[355] = INT_CARRY[260];
FULL_ADDER FA_239 (.DATA_A (INT_SUM[354]) , .DATA_B (INT_SUM[355]) , .DATA_C (INT_CARRY[261]) , .SAVE (SUM[33]) , .CARRY (CARRY[33]) );
FULL_ADDER FA_240 (.DATA_A (SUMMAND[321]) , .DATA_B (SUMMAND[322]) , .DATA_C (SUMMAND[323]) , .SAVE (INT_SUM[356]) , .CARRY (INT_CARRY[278]) );
FULL_ADDER FA_241 (.DATA_A (SUMMAND[324]) , .DATA_B (SUMMAND[325]) , .DATA_C (SUMMAND[326]) , .SAVE (INT_SUM[357]) , .CARRY (INT_CARRY[279]) );
FULL_ADDER FA_242 (.DATA_A (SUMMAND[327]) , .DATA_B (SUMMAND[328]) , .DATA_C (SUMMAND[329]) , .SAVE (INT_SUM[358]) , .CARRY (INT_CARRY[280]) );
FULL_ADDER FA_243 (.DATA_A (SUMMAND[330]) , .DATA_B (SUMMAND[331]) , .DATA_C (SUMMAND[332]) , .SAVE (INT_SUM[359]) , .CARRY (INT_CARRY[281]) );
FULL_ADDER FA_244 (.DATA_A (SUMMAND[333]) , .DATA_B (SUMMAND[334]) , .DATA_C (SUMMAND[335]) , .SAVE (INT_SUM[360]) , .CARRY (INT_CARRY[282]) );
assign INT_SUM[361] = SUMMAND[336];
FULL_ADDER FA_245 (.DATA_A (INT_SUM[356]) , .DATA_B (INT_SUM[357]) , .DATA_C (INT_SUM[358]) , .SAVE (INT_SUM[362]) , .CARRY (INT_CARRY[283]) );
FULL_ADDER FA_246 (.DATA_A (INT_SUM[359]) , .DATA_B (INT_SUM[360]) , .DATA_C (INT_SUM[361]) , .SAVE (INT_SUM[363]) , .CARRY (INT_CARRY[284]) );
FULL_ADDER FA_247 (.DATA_A (INT_CARRY[262]) , .DATA_B (INT_CARRY[263]) , .DATA_C (INT_CARRY[264]) , .SAVE (INT_SUM[364]) , .CARRY (INT_CARRY[285]) );
assign INT_SUM[365] = INT_CARRY[265];
assign INT_SUM[366] = INT_CARRY[266];
FULL_ADDER FA_248 (.DATA_A (INT_SUM[362]) , .DATA_B (INT_SUM[363]) , .DATA_C (INT_SUM[364]) , .SAVE (INT_SUM[367]) , .CARRY (INT_CARRY[286]) );
FULL_ADDER FA_249 (.DATA_A (INT_SUM[365]) , .DATA_B (INT_SUM[366]) , .DATA_C (INT_CARRY[267]) , .SAVE (INT_SUM[368]) , .CARRY (INT_CARRY[287]) );
FULL_ADDER FA_250 (.DATA_A (INT_CARRY[268]) , .DATA_B (INT_CARRY[269]) , .DATA_C (INT_CARRY[270]) , .SAVE (INT_SUM[369]) , .CARRY (INT_CARRY[288]) );
FULL_ADDER FA_251 (.DATA_A (INT_SUM[367]) , .DATA_B (INT_SUM[368]) , .DATA_C (INT_SUM[369]) , .SAVE (INT_SUM[370]) , .CARRY (INT_CARRY[289]) );
HALF_ADDER HA_31 (.DATA_A (INT_CARRY[271]) , .DATA_B (INT_CARRY[272]) , .SAVE (INT_SUM[372]) , .CARRY (INT_CARRY[291]) );
FLIPFLOP LA_89 (.DIN (INT_SUM[370]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[371]) );
FLIPFLOP LA_90 (.DIN (INT_SUM[372]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[373]) );
FLIPFLOP LA_91 (.DIN (INT_CARRY[273]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[274]) );
FULL_ADDER FA_252 (.DATA_A (INT_SUM[371]) , .DATA_B (INT_SUM[373]) , .DATA_C (INT_CARRY[274]) , .SAVE (INT_SUM[374]) , .CARRY (INT_CARRY[293]) );
FLIPFLOP LA_92 (.DIN (INT_CARRY[275]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[276]) );
assign INT_SUM[375] = INT_CARRY[276];
FULL_ADDER FA_253 (.DATA_A (INT_SUM[374]) , .DATA_B (INT_SUM[375]) , .DATA_C (INT_CARRY[277]) , .SAVE (SUM[34]) , .CARRY (CARRY[34]) );
FULL_ADDER FA_254 (.DATA_A (SUMMAND[337]) , .DATA_B (SUMMAND[338]) , .DATA_C (SUMMAND[339]) , .SAVE (INT_SUM[376]) , .CARRY (INT_CARRY[294]) );
FULL_ADDER FA_255 (.DATA_A (SUMMAND[340]) , .DATA_B (SUMMAND[341]) , .DATA_C (SUMMAND[342]) , .SAVE (INT_SUM[377]) , .CARRY (INT_CARRY[295]) );
FULL_ADDER FA_256 (.DATA_A (SUMMAND[343]) , .DATA_B (SUMMAND[344]) , .DATA_C (SUMMAND[345]) , .SAVE (INT_SUM[378]) , .CARRY (INT_CARRY[296]) );
FULL_ADDER FA_257 (.DATA_A (SUMMAND[346]) , .DATA_B (SUMMAND[347]) , .DATA_C (SUMMAND[348]) , .SAVE (INT_SUM[379]) , .CARRY (INT_CARRY[297]) );
FULL_ADDER FA_258 (.DATA_A (SUMMAND[349]) , .DATA_B (SUMMAND[350]) , .DATA_C (SUMMAND[351]) , .SAVE (INT_SUM[380]) , .CARRY (INT_CARRY[298]) );
FULL_ADDER FA_259 (.DATA_A (INT_SUM[376]) , .DATA_B (INT_SUM[377]) , .DATA_C (INT_SUM[378]) , .SAVE (INT_SUM[381]) , .CARRY (INT_CARRY[299]) );
FULL_ADDER FA_260 (.DATA_A (INT_SUM[379]) , .DATA_B (INT_SUM[380]) , .DATA_C (INT_CARRY[278]) , .SAVE (INT_SUM[382]) , .CARRY (INT_CARRY[300]) );
FULL_ADDER FA_261 (.DATA_A (INT_CARRY[279]) , .DATA_B (INT_CARRY[280]) , .DATA_C (INT_CARRY[281]) , .SAVE (INT_SUM[383]) , .CARRY (INT_CARRY[301]) );
assign INT_SUM[384] = INT_CARRY[282];
FULL_ADDER FA_262 (.DATA_A (INT_SUM[381]) , .DATA_B (INT_SUM[382]) , .DATA_C (INT_SUM[383]) , .SAVE (INT_SUM[385]) , .CARRY (INT_CARRY[302]) );
FULL_ADDER FA_263 (.DATA_A (INT_SUM[384]) , .DATA_B (INT_CARRY[283]) , .DATA_C (INT_CARRY[284]) , .SAVE (INT_SUM[386]) , .CARRY (INT_CARRY[303]) );
assign INT_SUM[387] = INT_CARRY[285];
FULL_ADDER FA_264 (.DATA_A (INT_SUM[385]) , .DATA_B (INT_SUM[386]) , .DATA_C (INT_SUM[387]) , .SAVE (INT_SUM[388]) , .CARRY (INT_CARRY[304]) );
FULL_ADDER FA_265 (.DATA_A (INT_CARRY[286]) , .DATA_B (INT_CARRY[287]) , .DATA_C (INT_CARRY[288]) , .SAVE (INT_SUM[390]) , .CARRY (INT_CARRY[306]) );
FLIPFLOP LA_93 (.DIN (INT_SUM[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[389]) );
FLIPFLOP LA_94 (.DIN (INT_SUM[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[391]) );
FLIPFLOP LA_95 (.DIN (INT_CARRY[289]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[290]) );
FULL_ADDER FA_266 (.DATA_A (INT_SUM[389]) , .DATA_B (INT_SUM[391]) , .DATA_C (INT_CARRY[290]) , .SAVE (INT_SUM[392]) , .CARRY (INT_CARRY[308]) );
FLIPFLOP LA_96 (.DIN (INT_CARRY[291]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[292]) );
assign INT_SUM[393] = INT_CARRY[292];
FULL_ADDER FA_267 (.DATA_A (INT_SUM[392]) , .DATA_B (INT_SUM[393]) , .DATA_C (INT_CARRY[293]) , .SAVE (SUM[35]) , .CARRY (CARRY[35]) );
FULL_ADDER FA_268 (.DATA_A (SUMMAND[352]) , .DATA_B (SUMMAND[353]) , .DATA_C (SUMMAND[354]) , .SAVE (INT_SUM[394]) , .CARRY (INT_CARRY[309]) );
FULL_ADDER FA_269 (.DATA_A (SUMMAND[355]) , .DATA_B (SUMMAND[356]) , .DATA_C (SUMMAND[357]) , .SAVE (INT_SUM[395]) , .CARRY (INT_CARRY[310]) );
FULL_ADDER FA_270 (.DATA_A (SUMMAND[358]) , .DATA_B (SUMMAND[359]) , .DATA_C (SUMMAND[360]) , .SAVE (INT_SUM[396]) , .CARRY (INT_CARRY[311]) );
FULL_ADDER FA_271 (.DATA_A (SUMMAND[361]) , .DATA_B (SUMMAND[362]) , .DATA_C (SUMMAND[363]) , .SAVE (INT_SUM[397]) , .CARRY (INT_CARRY[312]) );
FULL_ADDER FA_272 (.DATA_A (SUMMAND[364]) , .DATA_B (SUMMAND[365]) , .DATA_C (SUMMAND[366]) , .SAVE (INT_SUM[398]) , .CARRY (INT_CARRY[313]) );
FULL_ADDER FA_273 (.DATA_A (INT_SUM[394]) , .DATA_B (INT_SUM[395]) , .DATA_C (INT_SUM[396]) , .SAVE (INT_SUM[399]) , .CARRY (INT_CARRY[314]) );
FULL_ADDER FA_274 (.DATA_A (INT_SUM[397]) , .DATA_B (INT_SUM[398]) , .DATA_C (INT_CARRY[294]) , .SAVE (INT_SUM[400]) , .CARRY (INT_CARRY[315]) );
FULL_ADDER FA_275 (.DATA_A (INT_CARRY[295]) , .DATA_B (INT_CARRY[296]) , .DATA_C (INT_CARRY[297]) , .SAVE (INT_SUM[401]) , .CARRY (INT_CARRY[316]) );
assign INT_SUM[402] = INT_CARRY[298];
FULL_ADDER FA_276 (.DATA_A (INT_SUM[399]) , .DATA_B (INT_SUM[400]) , .DATA_C (INT_SUM[401]) , .SAVE (INT_SUM[403]) , .CARRY (INT_CARRY[317]) );
FULL_ADDER FA_277 (.DATA_A (INT_SUM[402]) , .DATA_B (INT_CARRY[299]) , .DATA_C (INT_CARRY[300]) , .SAVE (INT_SUM[404]) , .CARRY (INT_CARRY[318]) );
assign INT_SUM[405] = INT_CARRY[301];
FULL_ADDER FA_278 (.DATA_A (INT_SUM[403]) , .DATA_B (INT_SUM[404]) , .DATA_C (INT_SUM[405]) , .SAVE (INT_SUM[406]) , .CARRY (INT_CARRY[319]) );
HALF_ADDER HA_32 (.DATA_A (INT_CARRY[302]) , .DATA_B (INT_CARRY[303]) , .SAVE (INT_SUM[408]) , .CARRY (INT_CARRY[321]) );
FLIPFLOP LA_97 (.DIN (INT_SUM[406]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[407]) );
FLIPFLOP LA_98 (.DIN (INT_SUM[408]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[409]) );
FLIPFLOP LA_99 (.DIN (INT_CARRY[304]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[305]) );
FULL_ADDER FA_279 (.DATA_A (INT_SUM[407]) , .DATA_B (INT_SUM[409]) , .DATA_C (INT_CARRY[305]) , .SAVE (INT_SUM[410]) , .CARRY (INT_CARRY[323]) );
FLIPFLOP LA_100 (.DIN (INT_CARRY[306]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[307]) );
assign INT_SUM[411] = INT_CARRY[307];
FULL_ADDER FA_280 (.DATA_A (INT_SUM[410]) , .DATA_B (INT_SUM[411]) , .DATA_C (INT_CARRY[308]) , .SAVE (SUM[36]) , .CARRY (CARRY[36]) );
FULL_ADDER FA_281 (.DATA_A (SUMMAND[367]) , .DATA_B (SUMMAND[368]) , .DATA_C (SUMMAND[369]) , .SAVE (INT_SUM[412]) , .CARRY (INT_CARRY[324]) );
FULL_ADDER FA_282 (.DATA_A (SUMMAND[370]) , .DATA_B (SUMMAND[371]) , .DATA_C (SUMMAND[372]) , .SAVE (INT_SUM[413]) , .CARRY (INT_CARRY[325]) );
FULL_ADDER FA_283 (.DATA_A (SUMMAND[373]) , .DATA_B (SUMMAND[374]) , .DATA_C (SUMMAND[375]) , .SAVE (INT_SUM[414]) , .CARRY (INT_CARRY[326]) );
FULL_ADDER FA_284 (.DATA_A (SUMMAND[376]) , .DATA_B (SUMMAND[377]) , .DATA_C (SUMMAND[378]) , .SAVE (INT_SUM[415]) , .CARRY (INT_CARRY[327]) );
HALF_ADDER HA_33 (.DATA_A (SUMMAND[379]) , .DATA_B (SUMMAND[380]) , .SAVE (INT_SUM[416]) , .CARRY (INT_CARRY[328]) );
FULL_ADDER FA_285 (.DATA_A (INT_SUM[412]) , .DATA_B (INT_SUM[413]) , .DATA_C (INT_SUM[414]) , .SAVE (INT_SUM[417]) , .CARRY (INT_CARRY[329]) );
FULL_ADDER FA_286 (.DATA_A (INT_SUM[415]) , .DATA_B (INT_SUM[416]) , .DATA_C (INT_CARRY[309]) , .SAVE (INT_SUM[418]) , .CARRY (INT_CARRY[330]) );
FULL_ADDER FA_287 (.DATA_A (INT_CARRY[310]) , .DATA_B (INT_CARRY[311]) , .DATA_C (INT_CARRY[312]) , .SAVE (INT_SUM[419]) , .CARRY (INT_CARRY[331]) );
assign INT_SUM[420] = INT_CARRY[313];
FULL_ADDER FA_288 (.DATA_A (INT_SUM[417]) , .DATA_B (INT_SUM[418]) , .DATA_C (INT_SUM[419]) , .SAVE (INT_SUM[421]) , .CARRY (INT_CARRY[332]) );
FULL_ADDER FA_289 (.DATA_A (INT_SUM[420]) , .DATA_B (INT_CARRY[314]) , .DATA_C (INT_CARRY[315]) , .SAVE (INT_SUM[422]) , .CARRY (INT_CARRY[333]) );
assign INT_SUM[423] = INT_CARRY[316];
FULL_ADDER FA_290 (.DATA_A (INT_SUM[421]) , .DATA_B (INT_SUM[422]) , .DATA_C (INT_SUM[423]) , .SAVE (INT_SUM[424]) , .CARRY (INT_CARRY[334]) );
HALF_ADDER HA_34 (.DATA_A (INT_CARRY[317]) , .DATA_B (INT_CARRY[318]) , .SAVE (INT_SUM[426]) , .CARRY (INT_CARRY[336]) );
FLIPFLOP LA_101 (.DIN (INT_SUM[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[425]) );
FLIPFLOP LA_102 (.DIN (INT_SUM[426]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[427]) );
FLIPFLOP LA_103 (.DIN (INT_CARRY[319]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[320]) );
FULL_ADDER FA_291 (.DATA_A (INT_SUM[425]) , .DATA_B (INT_SUM[427]) , .DATA_C (INT_CARRY[320]) , .SAVE (INT_SUM[428]) , .CARRY (INT_CARRY[338]) );
FLIPFLOP LA_104 (.DIN (INT_CARRY[321]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[322]) );
assign INT_SUM[429] = INT_CARRY[322];
FULL_ADDER FA_292 (.DATA_A (INT_SUM[428]) , .DATA_B (INT_SUM[429]) , .DATA_C (INT_CARRY[323]) , .SAVE (SUM[37]) , .CARRY (CARRY[37]) );
FULL_ADDER FA_293 (.DATA_A (SUMMAND[381]) , .DATA_B (SUMMAND[382]) , .DATA_C (SUMMAND[383]) , .SAVE (INT_SUM[430]) , .CARRY (INT_CARRY[339]) );
FULL_ADDER FA_294 (.DATA_A (SUMMAND[384]) , .DATA_B (SUMMAND[385]) , .DATA_C (SUMMAND[386]) , .SAVE (INT_SUM[431]) , .CARRY (INT_CARRY[340]) );
FULL_ADDER FA_295 (.DATA_A (SUMMAND[387]) , .DATA_B (SUMMAND[388]) , .DATA_C (SUMMAND[389]) , .SAVE (INT_SUM[432]) , .CARRY (INT_CARRY[341]) );
FULL_ADDER FA_296 (.DATA_A (SUMMAND[390]) , .DATA_B (SUMMAND[391]) , .DATA_C (SUMMAND[392]) , .SAVE (INT_SUM[433]) , .CARRY (INT_CARRY[342]) );
HALF_ADDER HA_35 (.DATA_A (SUMMAND[393]) , .DATA_B (SUMMAND[394]) , .SAVE (INT_SUM[434]) , .CARRY (INT_CARRY[343]) );
FULL_ADDER FA_297 (.DATA_A (INT_SUM[430]) , .DATA_B (INT_SUM[431]) , .DATA_C (INT_SUM[432]) , .SAVE (INT_SUM[435]) , .CARRY (INT_CARRY[344]) );
FULL_ADDER FA_298 (.DATA_A (INT_SUM[433]) , .DATA_B (INT_SUM[434]) , .DATA_C (INT_CARRY[324]) , .SAVE (INT_SUM[436]) , .CARRY (INT_CARRY[345]) );
FULL_ADDER FA_299 (.DATA_A (INT_CARRY[325]) , .DATA_B (INT_CARRY[326]) , .DATA_C (INT_CARRY[327]) , .SAVE (INT_SUM[437]) , .CARRY (INT_CARRY[346]) );
assign INT_SUM[438] = INT_CARRY[328];
FULL_ADDER FA_300 (.DATA_A (INT_SUM[435]) , .DATA_B (INT_SUM[436]) , .DATA_C (INT_SUM[437]) , .SAVE (INT_SUM[439]) , .CARRY (INT_CARRY[347]) );
FULL_ADDER FA_301 (.DATA_A (INT_SUM[438]) , .DATA_B (INT_CARRY[329]) , .DATA_C (INT_CARRY[330]) , .SAVE (INT_SUM[440]) , .CARRY (INT_CARRY[348]) );
assign INT_SUM[441] = INT_CARRY[331];
FULL_ADDER FA_302 (.DATA_A (INT_SUM[439]) , .DATA_B (INT_SUM[440]) , .DATA_C (INT_SUM[441]) , .SAVE (INT_SUM[442]) , .CARRY (INT_CARRY[349]) );
HALF_ADDER HA_36 (.DATA_A (INT_CARRY[332]) , .DATA_B (INT_CARRY[333]) , .SAVE (INT_SUM[444]) , .CARRY (INT_CARRY[351]) );
FLIPFLOP LA_105 (.DIN (INT_SUM[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[443]) );
FLIPFLOP LA_106 (.DIN (INT_SUM[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[445]) );
FLIPFLOP LA_107 (.DIN (INT_CARRY[334]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[335]) );
FULL_ADDER FA_303 (.DATA_A (INT_SUM[443]) , .DATA_B (INT_SUM[445]) , .DATA_C (INT_CARRY[335]) , .SAVE (INT_SUM[446]) , .CARRY (INT_CARRY[353]) );
FLIPFLOP LA_108 (.DIN (INT_CARRY[336]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[337]) );
assign INT_SUM[447] = INT_CARRY[337];
FULL_ADDER FA_304 (.DATA_A (INT_SUM[446]) , .DATA_B (INT_SUM[447]) , .DATA_C (INT_CARRY[338]) , .SAVE (SUM[38]) , .CARRY (CARRY[38]) );
FULL_ADDER FA_305 (.DATA_A (SUMMAND[395]) , .DATA_B (SUMMAND[396]) , .DATA_C (SUMMAND[397]) , .SAVE (INT_SUM[448]) , .CARRY (INT_CARRY[354]) );
FULL_ADDER FA_306 (.DATA_A (SUMMAND[398]) , .DATA_B (SUMMAND[399]) , .DATA_C (SUMMAND[400]) , .SAVE (INT_SUM[449]) , .CARRY (INT_CARRY[355]) );
FULL_ADDER FA_307 (.DATA_A (SUMMAND[401]) , .DATA_B (SUMMAND[402]) , .DATA_C (SUMMAND[403]) , .SAVE (INT_SUM[450]) , .CARRY (INT_CARRY[356]) );
FULL_ADDER FA_308 (.DATA_A (SUMMAND[404]) , .DATA_B (SUMMAND[405]) , .DATA_C (SUMMAND[406]) , .SAVE (INT_SUM[451]) , .CARRY (INT_CARRY[357]) );
assign INT_SUM[452] = SUMMAND[407];
FULL_ADDER FA_309 (.DATA_A (INT_SUM[448]) , .DATA_B (INT_SUM[449]) , .DATA_C (INT_SUM[450]) , .SAVE (INT_SUM[453]) , .CARRY (INT_CARRY[358]) );
FULL_ADDER FA_310 (.DATA_A (INT_SUM[451]) , .DATA_B (INT_SUM[452]) , .DATA_C (INT_CARRY[339]) , .SAVE (INT_SUM[454]) , .CARRY (INT_CARRY[359]) );
FULL_ADDER FA_311 (.DATA_A (INT_CARRY[340]) , .DATA_B (INT_CARRY[341]) , .DATA_C (INT_CARRY[342]) , .SAVE (INT_SUM[455]) , .CARRY (INT_CARRY[360]) );
assign INT_SUM[456] = INT_CARRY[343];
FULL_ADDER FA_312 (.DATA_A (INT_SUM[453]) , .DATA_B (INT_SUM[454]) , .DATA_C (INT_SUM[455]) , .SAVE (INT_SUM[457]) , .CARRY (INT_CARRY[361]) );
FULL_ADDER FA_313 (.DATA_A (INT_SUM[456]) , .DATA_B (INT_CARRY[344]) , .DATA_C (INT_CARRY[345]) , .SAVE (INT_SUM[458]) , .CARRY (INT_CARRY[362]) );
assign INT_SUM[459] = INT_CARRY[346];
FULL_ADDER FA_314 (.DATA_A (INT_SUM[457]) , .DATA_B (INT_SUM[458]) , .DATA_C (INT_SUM[459]) , .SAVE (INT_SUM[460]) , .CARRY (INT_CARRY[363]) );
HALF_ADDER HA_37 (.DATA_A (INT_CARRY[347]) , .DATA_B (INT_CARRY[348]) , .SAVE (INT_SUM[462]) , .CARRY (INT_CARRY[365]) );
FLIPFLOP LA_109 (.DIN (INT_SUM[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[461]) );
FLIPFLOP LA_110 (.DIN (INT_SUM[462]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[463]) );
FLIPFLOP LA_111 (.DIN (INT_CARRY[349]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[350]) );
FULL_ADDER FA_315 (.DATA_A (INT_SUM[461]) , .DATA_B (INT_SUM[463]) , .DATA_C (INT_CARRY[350]) , .SAVE (INT_SUM[464]) , .CARRY (INT_CARRY[367]) );
FLIPFLOP LA_112 (.DIN (INT_CARRY[351]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[352]) );
assign INT_SUM[465] = INT_CARRY[352];
FULL_ADDER FA_316 (.DATA_A (INT_SUM[464]) , .DATA_B (INT_SUM[465]) , .DATA_C (INT_CARRY[353]) , .SAVE (SUM[39]) , .CARRY (CARRY[39]) );
FULL_ADDER FA_317 (.DATA_A (SUMMAND[408]) , .DATA_B (SUMMAND[409]) , .DATA_C (SUMMAND[410]) , .SAVE (INT_SUM[466]) , .CARRY (INT_CARRY[368]) );
FULL_ADDER FA_318 (.DATA_A (SUMMAND[411]) , .DATA_B (SUMMAND[412]) , .DATA_C (SUMMAND[413]) , .SAVE (INT_SUM[467]) , .CARRY (INT_CARRY[369]) );
FULL_ADDER FA_319 (.DATA_A (SUMMAND[414]) , .DATA_B (SUMMAND[415]) , .DATA_C (SUMMAND[416]) , .SAVE (INT_SUM[468]) , .CARRY (INT_CARRY[370]) );
FULL_ADDER FA_320 (.DATA_A (SUMMAND[417]) , .DATA_B (SUMMAND[418]) , .DATA_C (SUMMAND[419]) , .SAVE (INT_SUM[469]) , .CARRY (INT_CARRY[371]) );
FULL_ADDER FA_321 (.DATA_A (SUMMAND[420]) , .DATA_B (INT_CARRY[354]) , .DATA_C (INT_CARRY[355]) , .SAVE (INT_SUM[470]) , .CARRY (INT_CARRY[372]) );
assign INT_SUM[471] = INT_CARRY[356];
assign INT_SUM[472] = INT_CARRY[357];
FULL_ADDER FA_322 (.DATA_A (INT_SUM[466]) , .DATA_B (INT_SUM[467]) , .DATA_C (INT_SUM[468]) , .SAVE (INT_SUM[473]) , .CARRY (INT_CARRY[373]) );
FULL_ADDER FA_323 (.DATA_A (INT_SUM[469]) , .DATA_B (INT_SUM[470]) , .DATA_C (INT_SUM[471]) , .SAVE (INT_SUM[474]) , .CARRY (INT_CARRY[374]) );
FULL_ADDER FA_324 (.DATA_A (INT_SUM[472]) , .DATA_B (INT_CARRY[358]) , .DATA_C (INT_CARRY[359]) , .SAVE (INT_SUM[475]) , .CARRY (INT_CARRY[375]) );
assign INT_SUM[476] = INT_CARRY[360];
FULL_ADDER FA_325 (.DATA_A (INT_SUM[473]) , .DATA_B (INT_SUM[474]) , .DATA_C (INT_SUM[475]) , .SAVE (INT_SUM[477]) , .CARRY (INT_CARRY[376]) );
FULL_ADDER FA_326 (.DATA_A (INT_SUM[476]) , .DATA_B (INT_CARRY[361]) , .DATA_C (INT_CARRY[362]) , .SAVE (INT_SUM[479]) , .CARRY (INT_CARRY[378]) );
FLIPFLOP LA_113 (.DIN (INT_SUM[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[478]) );
FLIPFLOP LA_114 (.DIN (INT_SUM[479]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[480]) );
FLIPFLOP LA_115 (.DIN (INT_CARRY[363]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[364]) );
FULL_ADDER FA_327 (.DATA_A (INT_SUM[478]) , .DATA_B (INT_SUM[480]) , .DATA_C (INT_CARRY[364]) , .SAVE (INT_SUM[481]) , .CARRY (INT_CARRY[380]) );
FLIPFLOP LA_116 (.DIN (INT_CARRY[365]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[366]) );
assign INT_SUM[482] = INT_CARRY[366];
FULL_ADDER FA_328 (.DATA_A (INT_SUM[481]) , .DATA_B (INT_SUM[482]) , .DATA_C (INT_CARRY[367]) , .SAVE (SUM[40]) , .CARRY (CARRY[40]) );
FULL_ADDER FA_329 (.DATA_A (SUMMAND[421]) , .DATA_B (SUMMAND[422]) , .DATA_C (SUMMAND[423]) , .SAVE (INT_SUM[483]) , .CARRY (INT_CARRY[381]) );
FULL_ADDER FA_330 (.DATA_A (SUMMAND[424]) , .DATA_B (SUMMAND[425]) , .DATA_C (SUMMAND[426]) , .SAVE (INT_SUM[484]) , .CARRY (INT_CARRY[382]) );
FULL_ADDER FA_331 (.DATA_A (SUMMAND[427]) , .DATA_B (SUMMAND[428]) , .DATA_C (SUMMAND[429]) , .SAVE (INT_SUM[485]) , .CARRY (INT_CARRY[383]) );
FULL_ADDER FA_332 (.DATA_A (SUMMAND[430]) , .DATA_B (SUMMAND[431]) , .DATA_C (SUMMAND[432]) , .SAVE (INT_SUM[486]) , .CARRY (INT_CARRY[384]) );
FULL_ADDER FA_333 (.DATA_A (INT_SUM[483]) , .DATA_B (INT_SUM[484]) , .DATA_C (INT_SUM[485]) , .SAVE (INT_SUM[487]) , .CARRY (INT_CARRY[385]) );
FULL_ADDER FA_334 (.DATA_A (INT_SUM[486]) , .DATA_B (INT_CARRY[368]) , .DATA_C (INT_CARRY[369]) , .SAVE (INT_SUM[488]) , .CARRY (INT_CARRY[386]) );
FULL_ADDER FA_335 (.DATA_A (INT_CARRY[370]) , .DATA_B (INT_CARRY[371]) , .DATA_C (INT_CARRY[372]) , .SAVE (INT_SUM[489]) , .CARRY (INT_CARRY[387]) );
FULL_ADDER FA_336 (.DATA_A (INT_SUM[487]) , .DATA_B (INT_SUM[488]) , .DATA_C (INT_SUM[489]) , .SAVE (INT_SUM[490]) , .CARRY (INT_CARRY[388]) );
FULL_ADDER FA_337 (.DATA_A (INT_CARRY[373]) , .DATA_B (INT_CARRY[374]) , .DATA_C (INT_CARRY[375]) , .SAVE (INT_SUM[492]) , .CARRY (INT_CARRY[390]) );
FLIPFLOP LA_117 (.DIN (INT_SUM[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[491]) );
FLIPFLOP LA_118 (.DIN (INT_SUM[492]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[493]) );
FLIPFLOP LA_119 (.DIN (INT_CARRY[376]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[377]) );
FULL_ADDER FA_338 (.DATA_A (INT_SUM[491]) , .DATA_B (INT_SUM[493]) , .DATA_C (INT_CARRY[377]) , .SAVE (INT_SUM[494]) , .CARRY (INT_CARRY[392]) );
FLIPFLOP LA_120 (.DIN (INT_CARRY[378]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[379]) );
assign INT_SUM[495] = INT_CARRY[379];
FULL_ADDER FA_339 (.DATA_A (INT_SUM[494]) , .DATA_B (INT_SUM[495]) , .DATA_C (INT_CARRY[380]) , .SAVE (SUM[41]) , .CARRY (CARRY[41]) );
FULL_ADDER FA_340 (.DATA_A (SUMMAND[433]) , .DATA_B (SUMMAND[434]) , .DATA_C (SUMMAND[435]) , .SAVE (INT_SUM[496]) , .CARRY (INT_CARRY[393]) );
FULL_ADDER FA_341 (.DATA_A (SUMMAND[436]) , .DATA_B (SUMMAND[437]) , .DATA_C (SUMMAND[438]) , .SAVE (INT_SUM[497]) , .CARRY (INT_CARRY[394]) );
FULL_ADDER FA_342 (.DATA_A (SUMMAND[439]) , .DATA_B (SUMMAND[440]) , .DATA_C (SUMMAND[441]) , .SAVE (INT_SUM[498]) , .CARRY (INT_CARRY[395]) );
FULL_ADDER FA_343 (.DATA_A (SUMMAND[442]) , .DATA_B (SUMMAND[443]) , .DATA_C (SUMMAND[444]) , .SAVE (INT_SUM[499]) , .CARRY (INT_CARRY[396]) );
FULL_ADDER FA_344 (.DATA_A (INT_SUM[496]) , .DATA_B (INT_SUM[497]) , .DATA_C (INT_SUM[498]) , .SAVE (INT_SUM[500]) , .CARRY (INT_CARRY[397]) );
FULL_ADDER FA_345 (.DATA_A (INT_SUM[499]) , .DATA_B (INT_CARRY[381]) , .DATA_C (INT_CARRY[382]) , .SAVE (INT_SUM[501]) , .CARRY (INT_CARRY[398]) );
HALF_ADDER HA_38 (.DATA_A (INT_CARRY[383]) , .DATA_B (INT_CARRY[384]) , .SAVE (INT_SUM[502]) , .CARRY (INT_CARRY[399]) );
FULL_ADDER FA_346 (.DATA_A (INT_SUM[500]) , .DATA_B (INT_SUM[501]) , .DATA_C (INT_SUM[502]) , .SAVE (INT_SUM[503]) , .CARRY (INT_CARRY[400]) );
FULL_ADDER FA_347 (.DATA_A (INT_CARRY[385]) , .DATA_B (INT_CARRY[386]) , .DATA_C (INT_CARRY[387]) , .SAVE (INT_SUM[505]) , .CARRY (INT_CARRY[402]) );
FLIPFLOP LA_121 (.DIN (INT_SUM[503]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[504]) );
FLIPFLOP LA_122 (.DIN (INT_SUM[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[506]) );
FLIPFLOP LA_123 (.DIN (INT_CARRY[388]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[389]) );
FULL_ADDER FA_348 (.DATA_A (INT_SUM[504]) , .DATA_B (INT_SUM[506]) , .DATA_C (INT_CARRY[389]) , .SAVE (INT_SUM[507]) , .CARRY (INT_CARRY[404]) );
FLIPFLOP LA_124 (.DIN (INT_CARRY[390]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[391]) );
assign INT_SUM[508] = INT_CARRY[391];
FULL_ADDER FA_349 (.DATA_A (INT_SUM[507]) , .DATA_B (INT_SUM[508]) , .DATA_C (INT_CARRY[392]) , .SAVE (SUM[42]) , .CARRY (CARRY[42]) );
FULL_ADDER FA_350 (.DATA_A (SUMMAND[445]) , .DATA_B (SUMMAND[446]) , .DATA_C (SUMMAND[447]) , .SAVE (INT_SUM[509]) , .CARRY (INT_CARRY[405]) );
FULL_ADDER FA_351 (.DATA_A (SUMMAND[448]) , .DATA_B (SUMMAND[449]) , .DATA_C (SUMMAND[450]) , .SAVE (INT_SUM[510]) , .CARRY (INT_CARRY[406]) );
FULL_ADDER FA_352 (.DATA_A (SUMMAND[451]) , .DATA_B (SUMMAND[452]) , .DATA_C (SUMMAND[453]) , .SAVE (INT_SUM[511]) , .CARRY (INT_CARRY[407]) );
assign INT_SUM[512] = SUMMAND[454];
assign INT_SUM[513] = SUMMAND[455];
FULL_ADDER FA_353 (.DATA_A (INT_SUM[509]) , .DATA_B (INT_SUM[510]) , .DATA_C (INT_SUM[511]) , .SAVE (INT_SUM[514]) , .CARRY (INT_CARRY[408]) );
FULL_ADDER FA_354 (.DATA_A (INT_SUM[512]) , .DATA_B (INT_SUM[513]) , .DATA_C (INT_CARRY[393]) , .SAVE (INT_SUM[515]) , .CARRY (INT_CARRY[409]) );
FULL_ADDER FA_355 (.DATA_A (INT_CARRY[394]) , .DATA_B (INT_CARRY[395]) , .DATA_C (INT_CARRY[396]) , .SAVE (INT_SUM[516]) , .CARRY (INT_CARRY[410]) );
FULL_ADDER FA_356 (.DATA_A (INT_SUM[514]) , .DATA_B (INT_SUM[515]) , .DATA_C (INT_SUM[516]) , .SAVE (INT_SUM[517]) , .CARRY (INT_CARRY[411]) );
FULL_ADDER FA_357 (.DATA_A (INT_CARRY[397]) , .DATA_B (INT_CARRY[398]) , .DATA_C (INT_CARRY[399]) , .SAVE (INT_SUM[519]) , .CARRY (INT_CARRY[413]) );
FLIPFLOP LA_125 (.DIN (INT_SUM[517]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[518]) );
FLIPFLOP LA_126 (.DIN (INT_SUM[519]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[520]) );
FLIPFLOP LA_127 (.DIN (INT_CARRY[400]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[401]) );
FULL_ADDER FA_358 (.DATA_A (INT_SUM[518]) , .DATA_B (INT_SUM[520]) , .DATA_C (INT_CARRY[401]) , .SAVE (INT_SUM[521]) , .CARRY (INT_CARRY[415]) );
FLIPFLOP LA_128 (.DIN (INT_CARRY[402]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[403]) );
assign INT_SUM[522] = INT_CARRY[403];
FULL_ADDER FA_359 (.DATA_A (INT_SUM[521]) , .DATA_B (INT_SUM[522]) , .DATA_C (INT_CARRY[404]) , .SAVE (SUM[43]) , .CARRY (CARRY[43]) );
FULL_ADDER FA_360 (.DATA_A (SUMMAND[456]) , .DATA_B (SUMMAND[457]) , .DATA_C (SUMMAND[458]) , .SAVE (INT_SUM[523]) , .CARRY (INT_CARRY[416]) );
FULL_ADDER FA_361 (.DATA_A (SUMMAND[459]) , .DATA_B (SUMMAND[460]) , .DATA_C (SUMMAND[461]) , .SAVE (INT_SUM[524]) , .CARRY (INT_CARRY[417]) );
FULL_ADDER FA_362 (.DATA_A (SUMMAND[462]) , .DATA_B (SUMMAND[463]) , .DATA_C (SUMMAND[464]) , .SAVE (INT_SUM[525]) , .CARRY (INT_CARRY[418]) );
HALF_ADDER HA_39 (.DATA_A (SUMMAND[465]) , .DATA_B (SUMMAND[466]) , .SAVE (INT_SUM[526]) , .CARRY (INT_CARRY[419]) );
FULL_ADDER FA_363 (.DATA_A (INT_SUM[523]) , .DATA_B (INT_SUM[524]) , .DATA_C (INT_SUM[525]) , .SAVE (INT_SUM[527]) , .CARRY (INT_CARRY[420]) );
FULL_ADDER FA_364 (.DATA_A (INT_SUM[526]) , .DATA_B (INT_CARRY[405]) , .DATA_C (INT_CARRY[406]) , .SAVE (INT_SUM[528]) , .CARRY (INT_CARRY[421]) );
assign INT_SUM[529] = INT_CARRY[407];
FULL_ADDER FA_365 (.DATA_A (INT_SUM[527]) , .DATA_B (INT_SUM[528]) , .DATA_C (INT_SUM[529]) , .SAVE (INT_SUM[530]) , .CARRY (INT_CARRY[422]) );
FULL_ADDER FA_366 (.DATA_A (INT_CARRY[408]) , .DATA_B (INT_CARRY[409]) , .DATA_C (INT_CARRY[410]) , .SAVE (INT_SUM[532]) , .CARRY (INT_CARRY[424]) );
FLIPFLOP LA_129 (.DIN (INT_SUM[530]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[531]) );
FLIPFLOP LA_130 (.DIN (INT_SUM[532]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[533]) );
FLIPFLOP LA_131 (.DIN (INT_CARRY[411]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[412]) );
FULL_ADDER FA_367 (.DATA_A (INT_SUM[531]) , .DATA_B (INT_SUM[533]) , .DATA_C (INT_CARRY[412]) , .SAVE (INT_SUM[534]) , .CARRY (INT_CARRY[426]) );
FLIPFLOP LA_132 (.DIN (INT_CARRY[413]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[414]) );
assign INT_SUM[535] = INT_CARRY[414];
FULL_ADDER FA_368 (.DATA_A (INT_SUM[534]) , .DATA_B (INT_SUM[535]) , .DATA_C (INT_CARRY[415]) , .SAVE (SUM[44]) , .CARRY (CARRY[44]) );
FULL_ADDER FA_369 (.DATA_A (SUMMAND[467]) , .DATA_B (SUMMAND[468]) , .DATA_C (SUMMAND[469]) , .SAVE (INT_SUM[536]) , .CARRY (INT_CARRY[427]) );
FULL_ADDER FA_370 (.DATA_A (SUMMAND[470]) , .DATA_B (SUMMAND[471]) , .DATA_C (SUMMAND[472]) , .SAVE (INT_SUM[537]) , .CARRY (INT_CARRY[428]) );
FULL_ADDER FA_371 (.DATA_A (SUMMAND[473]) , .DATA_B (SUMMAND[474]) , .DATA_C (SUMMAND[475]) , .SAVE (INT_SUM[538]) , .CARRY (INT_CARRY[429]) );
assign INT_SUM[539] = SUMMAND[476];
FULL_ADDER FA_372 (.DATA_A (INT_SUM[536]) , .DATA_B (INT_SUM[537]) , .DATA_C (INT_SUM[538]) , .SAVE (INT_SUM[540]) , .CARRY (INT_CARRY[430]) );
FULL_ADDER FA_373 (.DATA_A (INT_SUM[539]) , .DATA_B (INT_CARRY[416]) , .DATA_C (INT_CARRY[417]) , .SAVE (INT_SUM[541]) , .CARRY (INT_CARRY[431]) );
assign INT_SUM[542] = INT_CARRY[418];
assign INT_SUM[543] = INT_CARRY[419];
FULL_ADDER FA_374 (.DATA_A (INT_SUM[540]) , .DATA_B (INT_SUM[541]) , .DATA_C (INT_SUM[542]) , .SAVE (INT_SUM[544]) , .CARRY (INT_CARRY[432]) );
FULL_ADDER FA_375 (.DATA_A (INT_SUM[543]) , .DATA_B (INT_CARRY[420]) , .DATA_C (INT_CARRY[421]) , .SAVE (INT_SUM[546]) , .CARRY (INT_CARRY[434]) );
FLIPFLOP LA_133 (.DIN (INT_SUM[544]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[545]) );
FLIPFLOP LA_134 (.DIN (INT_SUM[546]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[547]) );
FLIPFLOP LA_135 (.DIN (INT_CARRY[422]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[423]) );
FULL_ADDER FA_376 (.DATA_A (INT_SUM[545]) , .DATA_B (INT_SUM[547]) , .DATA_C (INT_CARRY[423]) , .SAVE (INT_SUM[548]) , .CARRY (INT_CARRY[436]) );
FLIPFLOP LA_136 (.DIN (INT_CARRY[424]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[425]) );
assign INT_SUM[549] = INT_CARRY[425];
FULL_ADDER FA_377 (.DATA_A (INT_SUM[548]) , .DATA_B (INT_SUM[549]) , .DATA_C (INT_CARRY[426]) , .SAVE (SUM[45]) , .CARRY (CARRY[45]) );
FULL_ADDER FA_378 (.DATA_A (SUMMAND[477]) , .DATA_B (SUMMAND[478]) , .DATA_C (SUMMAND[479]) , .SAVE (INT_SUM[550]) , .CARRY (INT_CARRY[437]) );
FULL_ADDER FA_379 (.DATA_A (SUMMAND[480]) , .DATA_B (SUMMAND[481]) , .DATA_C (SUMMAND[482]) , .SAVE (INT_SUM[551]) , .CARRY (INT_CARRY[438]) );
FULL_ADDER FA_380 (.DATA_A (SUMMAND[483]) , .DATA_B (SUMMAND[484]) , .DATA_C (SUMMAND[485]) , .SAVE (INT_SUM[552]) , .CARRY (INT_CARRY[439]) );
assign INT_SUM[553] = SUMMAND[486];
FULL_ADDER FA_381 (.DATA_A (INT_SUM[550]) , .DATA_B (INT_SUM[551]) , .DATA_C (INT_SUM[552]) , .SAVE (INT_SUM[554]) , .CARRY (INT_CARRY[440]) );
FULL_ADDER FA_382 (.DATA_A (INT_SUM[553]) , .DATA_B (INT_CARRY[427]) , .DATA_C (INT_CARRY[428]) , .SAVE (INT_SUM[555]) , .CARRY (INT_CARRY[441]) );
assign INT_SUM[556] = INT_CARRY[429];
FULL_ADDER FA_383 (.DATA_A (INT_SUM[554]) , .DATA_B (INT_SUM[555]) , .DATA_C (INT_SUM[556]) , .SAVE (INT_SUM[557]) , .CARRY (INT_CARRY[442]) );
HALF_ADDER HA_40 (.DATA_A (INT_CARRY[430]) , .DATA_B (INT_CARRY[431]) , .SAVE (INT_SUM[559]) , .CARRY (INT_CARRY[444]) );
FLIPFLOP LA_137 (.DIN (INT_SUM[557]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[558]) );
FLIPFLOP LA_138 (.DIN (INT_SUM[559]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[560]) );
FLIPFLOP LA_139 (.DIN (INT_CARRY[432]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[433]) );
FULL_ADDER FA_384 (.DATA_A (INT_SUM[558]) , .DATA_B (INT_SUM[560]) , .DATA_C (INT_CARRY[433]) , .SAVE (INT_SUM[561]) , .CARRY (INT_CARRY[446]) );
FLIPFLOP LA_140 (.DIN (INT_CARRY[434]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[435]) );
assign INT_SUM[562] = INT_CARRY[435];
FULL_ADDER FA_385 (.DATA_A (INT_SUM[561]) , .DATA_B (INT_SUM[562]) , .DATA_C (INT_CARRY[436]) , .SAVE (SUM[46]) , .CARRY (CARRY[46]) );
FULL_ADDER FA_386 (.DATA_A (SUMMAND[487]) , .DATA_B (SUMMAND[488]) , .DATA_C (SUMMAND[489]) , .SAVE (INT_SUM[563]) , .CARRY (INT_CARRY[447]) );
FULL_ADDER FA_387 (.DATA_A (SUMMAND[490]) , .DATA_B (SUMMAND[491]) , .DATA_C (SUMMAND[492]) , .SAVE (INT_SUM[564]) , .CARRY (INT_CARRY[448]) );
FULL_ADDER FA_388 (.DATA_A (SUMMAND[493]) , .DATA_B (SUMMAND[494]) , .DATA_C (SUMMAND[495]) , .SAVE (INT_SUM[565]) , .CARRY (INT_CARRY[449]) );
FULL_ADDER FA_389 (.DATA_A (INT_SUM[563]) , .DATA_B (INT_SUM[564]) , .DATA_C (INT_SUM[565]) , .SAVE (INT_SUM[566]) , .CARRY (INT_CARRY[450]) );
FULL_ADDER FA_390 (.DATA_A (INT_CARRY[437]) , .DATA_B (INT_CARRY[438]) , .DATA_C (INT_CARRY[439]) , .SAVE (INT_SUM[567]) , .CARRY (INT_CARRY[451]) );
FULL_ADDER FA_391 (.DATA_A (INT_SUM[566]) , .DATA_B (INT_SUM[567]) , .DATA_C (INT_CARRY[440]) , .SAVE (INT_SUM[568]) , .CARRY (INT_CARRY[452]) );
assign INT_SUM[570] = INT_CARRY[441];
FLIPFLOP LA_141 (.DIN (INT_SUM[568]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[569]) );
FLIPFLOP LA_142 (.DIN (INT_SUM[570]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[571]) );
FLIPFLOP LA_143 (.DIN (INT_CARRY[442]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[443]) );
FULL_ADDER FA_392 (.DATA_A (INT_SUM[569]) , .DATA_B (INT_SUM[571]) , .DATA_C (INT_CARRY[443]) , .SAVE (INT_SUM[572]) , .CARRY (INT_CARRY[454]) );
FLIPFLOP LA_144 (.DIN (INT_CARRY[444]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[445]) );
assign INT_SUM[573] = INT_CARRY[445];
FULL_ADDER FA_393 (.DATA_A (INT_SUM[572]) , .DATA_B (INT_SUM[573]) , .DATA_C (INT_CARRY[446]) , .SAVE (SUM[47]) , .CARRY (CARRY[47]) );
FULL_ADDER FA_394 (.DATA_A (SUMMAND[496]) , .DATA_B (SUMMAND[497]) , .DATA_C (SUMMAND[498]) , .SAVE (INT_SUM[574]) , .CARRY (INT_CARRY[455]) );
FULL_ADDER FA_395 (.DATA_A (SUMMAND[499]) , .DATA_B (SUMMAND[500]) , .DATA_C (SUMMAND[501]) , .SAVE (INT_SUM[575]) , .CARRY (INT_CARRY[456]) );
FULL_ADDER FA_396 (.DATA_A (SUMMAND[502]) , .DATA_B (SUMMAND[503]) , .DATA_C (SUMMAND[504]) , .SAVE (INT_SUM[576]) , .CARRY (INT_CARRY[457]) );
FULL_ADDER FA_397 (.DATA_A (INT_SUM[574]) , .DATA_B (INT_SUM[575]) , .DATA_C (INT_SUM[576]) , .SAVE (INT_SUM[577]) , .CARRY (INT_CARRY[458]) );
FULL_ADDER FA_398 (.DATA_A (INT_CARRY[447]) , .DATA_B (INT_CARRY[448]) , .DATA_C (INT_CARRY[449]) , .SAVE (INT_SUM[578]) , .CARRY (INT_CARRY[459]) );
FULL_ADDER FA_399 (.DATA_A (INT_SUM[577]) , .DATA_B (INT_SUM[578]) , .DATA_C (INT_CARRY[450]) , .SAVE (INT_SUM[579]) , .CARRY (INT_CARRY[460]) );
assign INT_SUM[581] = INT_CARRY[451];
FLIPFLOP LA_145 (.DIN (INT_SUM[579]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[580]) );
FLIPFLOP LA_146 (.DIN (INT_SUM[581]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[582]) );
FLIPFLOP LA_147 (.DIN (INT_CARRY[452]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[453]) );
FULL_ADDER FA_400 (.DATA_A (INT_SUM[580]) , .DATA_B (INT_SUM[582]) , .DATA_C (INT_CARRY[453]) , .SAVE (INT_SUM[583]) , .CARRY (INT_CARRY[462]) );
HALF_ADDER HA_41 (.DATA_A (INT_SUM[583]) , .DATA_B (INT_CARRY[454]) , .SAVE (SUM[48]) , .CARRY (CARRY[48]) );
FULL_ADDER FA_401 (.DATA_A (SUMMAND[505]) , .DATA_B (SUMMAND[506]) , .DATA_C (SUMMAND[507]) , .SAVE (INT_SUM[584]) , .CARRY (INT_CARRY[463]) );
FULL_ADDER FA_402 (.DATA_A (SUMMAND[508]) , .DATA_B (SUMMAND[509]) , .DATA_C (SUMMAND[510]) , .SAVE (INT_SUM[585]) , .CARRY (INT_CARRY[464]) );
FULL_ADDER FA_403 (.DATA_A (SUMMAND[511]) , .DATA_B (SUMMAND[512]) , .DATA_C (INT_CARRY[455]) , .SAVE (INT_SUM[586]) , .CARRY (INT_CARRY[465]) );
HALF_ADDER HA_42 (.DATA_A (INT_CARRY[456]) , .DATA_B (INT_CARRY[457]) , .SAVE (INT_SUM[587]) , .CARRY (INT_CARRY[466]) );
FULL_ADDER FA_404 (.DATA_A (INT_SUM[584]) , .DATA_B (INT_SUM[585]) , .DATA_C (INT_SUM[586]) , .SAVE (INT_SUM[588]) , .CARRY (INT_CARRY[467]) );
FULL_ADDER FA_405 (.DATA_A (INT_SUM[587]) , .DATA_B (INT_CARRY[458]) , .DATA_C (INT_CARRY[459]) , .SAVE (INT_SUM[590]) , .CARRY (INT_CARRY[469]) );
FLIPFLOP LA_148 (.DIN (INT_SUM[588]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[589]) );
FLIPFLOP LA_149 (.DIN (INT_SUM[590]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[591]) );
FLIPFLOP LA_150 (.DIN (INT_CARRY[460]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[461]) );
FULL_ADDER FA_406 (.DATA_A (INT_SUM[589]) , .DATA_B (INT_SUM[591]) , .DATA_C (INT_CARRY[461]) , .SAVE (INT_SUM[592]) , .CARRY (INT_CARRY[471]) );
HALF_ADDER HA_43 (.DATA_A (INT_SUM[592]) , .DATA_B (INT_CARRY[462]) , .SAVE (SUM[49]) , .CARRY (CARRY[49]) );
FULL_ADDER FA_407 (.DATA_A (SUMMAND[513]) , .DATA_B (SUMMAND[514]) , .DATA_C (SUMMAND[515]) , .SAVE (INT_SUM[593]) , .CARRY (INT_CARRY[472]) );
FULL_ADDER FA_408 (.DATA_A (SUMMAND[516]) , .DATA_B (SUMMAND[517]) , .DATA_C (SUMMAND[518]) , .SAVE (INT_SUM[594]) , .CARRY (INT_CARRY[473]) );
assign INT_SUM[595] = SUMMAND[519];
assign INT_SUM[596] = SUMMAND[520];
FULL_ADDER FA_409 (.DATA_A (INT_SUM[593]) , .DATA_B (INT_SUM[594]) , .DATA_C (INT_SUM[595]) , .SAVE (INT_SUM[597]) , .CARRY (INT_CARRY[474]) );
assign INT_SUM[598] = INT_SUM[596];
FULL_ADDER FA_410 (.DATA_A (INT_SUM[597]) , .DATA_B (INT_SUM[598]) , .DATA_C (INT_CARRY[463]) , .SAVE (INT_SUM[599]) , .CARRY (INT_CARRY[475]) );
FULL_ADDER FA_411 (.DATA_A (INT_CARRY[464]) , .DATA_B (INT_CARRY[465]) , .DATA_C (INT_CARRY[466]) , .SAVE (INT_SUM[601]) , .CARRY (INT_CARRY[477]) );
FLIPFLOP LA_151 (.DIN (INT_SUM[599]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[600]) );
FLIPFLOP LA_152 (.DIN (INT_SUM[601]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[602]) );
FLIPFLOP LA_153 (.DIN (INT_CARRY[467]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[468]) );
FULL_ADDER FA_412 (.DATA_A (INT_SUM[600]) , .DATA_B (INT_SUM[602]) , .DATA_C (INT_CARRY[468]) , .SAVE (INT_SUM[603]) , .CARRY (INT_CARRY[479]) );
FLIPFLOP LA_154 (.DIN (INT_CARRY[469]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[470]) );
assign INT_SUM[604] = INT_CARRY[470];
FULL_ADDER FA_413 (.DATA_A (INT_SUM[603]) , .DATA_B (INT_SUM[604]) , .DATA_C (INT_CARRY[471]) , .SAVE (SUM[50]) , .CARRY (CARRY[50]) );
FULL_ADDER FA_414 (.DATA_A (SUMMAND[521]) , .DATA_B (SUMMAND[522]) , .DATA_C (SUMMAND[523]) , .SAVE (INT_SUM[605]) , .CARRY (INT_CARRY[480]) );
FULL_ADDER FA_415 (.DATA_A (SUMMAND[524]) , .DATA_B (SUMMAND[525]) , .DATA_C (SUMMAND[526]) , .SAVE (INT_SUM[606]) , .CARRY (INT_CARRY[481]) );
FULL_ADDER FA_416 (.DATA_A (SUMMAND[527]) , .DATA_B (INT_CARRY[472]) , .DATA_C (INT_CARRY[473]) , .SAVE (INT_SUM[607]) , .CARRY (INT_CARRY[482]) );
FULL_ADDER FA_417 (.DATA_A (INT_SUM[605]) , .DATA_B (INT_SUM[606]) , .DATA_C (INT_SUM[607]) , .SAVE (INT_SUM[608]) , .CARRY (INT_CARRY[483]) );
assign INT_SUM[610] = INT_CARRY[474];
FLIPFLOP LA_155 (.DIN (INT_SUM[608]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[609]) );
FLIPFLOP LA_156 (.DIN (INT_SUM[610]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[611]) );
FLIPFLOP LA_157 (.DIN (INT_CARRY[475]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[476]) );
FULL_ADDER FA_418 (.DATA_A (INT_SUM[609]) , .DATA_B (INT_SUM[611]) , .DATA_C (INT_CARRY[476]) , .SAVE (INT_SUM[612]) , .CARRY (INT_CARRY[485]) );
FLIPFLOP LA_158 (.DIN (INT_CARRY[477]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[478]) );
assign INT_SUM[613] = INT_CARRY[478];
FULL_ADDER FA_419 (.DATA_A (INT_SUM[612]) , .DATA_B (INT_SUM[613]) , .DATA_C (INT_CARRY[479]) , .SAVE (SUM[51]) , .CARRY (CARRY[51]) );
FULL_ADDER FA_420 (.DATA_A (SUMMAND[528]) , .DATA_B (SUMMAND[529]) , .DATA_C (SUMMAND[530]) , .SAVE (INT_SUM[614]) , .CARRY (INT_CARRY[486]) );
FULL_ADDER FA_421 (.DATA_A (SUMMAND[531]) , .DATA_B (SUMMAND[532]) , .DATA_C (SUMMAND[533]) , .SAVE (INT_SUM[615]) , .CARRY (INT_CARRY[487]) );
assign INT_SUM[616] = SUMMAND[534];
FULL_ADDER FA_422 (.DATA_A (INT_SUM[614]) , .DATA_B (INT_SUM[615]) , .DATA_C (INT_SUM[616]) , .SAVE (INT_SUM[617]) , .CARRY (INT_CARRY[488]) );
FULL_ADDER FA_423 (.DATA_A (INT_CARRY[480]) , .DATA_B (INT_CARRY[481]) , .DATA_C (INT_CARRY[482]) , .SAVE (INT_SUM[619]) , .CARRY (INT_CARRY[490]) );
FLIPFLOP LA_159 (.DIN (INT_SUM[617]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[618]) );
FLIPFLOP LA_160 (.DIN (INT_SUM[619]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[620]) );
FLIPFLOP LA_161 (.DIN (INT_CARRY[483]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[484]) );
FULL_ADDER FA_424 (.DATA_A (INT_SUM[618]) , .DATA_B (INT_SUM[620]) , .DATA_C (INT_CARRY[484]) , .SAVE (INT_SUM[621]) , .CARRY (INT_CARRY[492]) );
HALF_ADDER HA_44 (.DATA_A (INT_SUM[621]) , .DATA_B (INT_CARRY[485]) , .SAVE (SUM[52]) , .CARRY (CARRY[52]) );
FULL_ADDER FA_425 (.DATA_A (SUMMAND[535]) , .DATA_B (SUMMAND[536]) , .DATA_C (SUMMAND[537]) , .SAVE (INT_SUM[622]) , .CARRY (INT_CARRY[493]) );
FULL_ADDER FA_426 (.DATA_A (SUMMAND[538]) , .DATA_B (SUMMAND[539]) , .DATA_C (SUMMAND[540]) , .SAVE (INT_SUM[623]) , .CARRY (INT_CARRY[494]) );
FULL_ADDER FA_427 (.DATA_A (INT_SUM[622]) , .DATA_B (INT_SUM[623]) , .DATA_C (INT_CARRY[486]) , .SAVE (INT_SUM[624]) , .CARRY (INT_CARRY[495]) );
assign INT_SUM[626] = INT_CARRY[487];
FLIPFLOP LA_162 (.DIN (INT_SUM[624]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[625]) );
FLIPFLOP LA_163 (.DIN (INT_SUM[626]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[627]) );
FLIPFLOP LA_164 (.DIN (INT_CARRY[488]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[489]) );
FULL_ADDER FA_428 (.DATA_A (INT_SUM[625]) , .DATA_B (INT_SUM[627]) , .DATA_C (INT_CARRY[489]) , .SAVE (INT_SUM[628]) , .CARRY (INT_CARRY[497]) );
FLIPFLOP LA_165 (.DIN (INT_CARRY[490]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[491]) );
assign INT_SUM[629] = INT_CARRY[491];
FULL_ADDER FA_429 (.DATA_A (INT_SUM[628]) , .DATA_B (INT_SUM[629]) , .DATA_C (INT_CARRY[492]) , .SAVE (SUM[53]) , .CARRY (CARRY[53]) );
FULL_ADDER FA_430 (.DATA_A (SUMMAND[541]) , .DATA_B (SUMMAND[542]) , .DATA_C (SUMMAND[543]) , .SAVE (INT_SUM[630]) , .CARRY (INT_CARRY[498]) );
FULL_ADDER FA_431 (.DATA_A (SUMMAND[544]) , .DATA_B (SUMMAND[545]) , .DATA_C (SUMMAND[546]) , .SAVE (INT_SUM[631]) , .CARRY (INT_CARRY[499]) );
FULL_ADDER FA_432 (.DATA_A (INT_SUM[630]) , .DATA_B (INT_SUM[631]) , .DATA_C (INT_CARRY[493]) , .SAVE (INT_SUM[632]) , .CARRY (INT_CARRY[500]) );
assign INT_SUM[634] = INT_CARRY[494];
FLIPFLOP LA_166 (.DIN (INT_SUM[632]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[633]) );
FLIPFLOP LA_167 (.DIN (INT_SUM[634]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[635]) );
FLIPFLOP LA_168 (.DIN (INT_CARRY[495]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[496]) );
FULL_ADDER FA_433 (.DATA_A (INT_SUM[633]) , .DATA_B (INT_SUM[635]) , .DATA_C (INT_CARRY[496]) , .SAVE (INT_SUM[636]) , .CARRY (INT_CARRY[502]) );
HALF_ADDER HA_45 (.DATA_A (INT_SUM[636]) , .DATA_B (INT_CARRY[497]) , .SAVE (SUM[54]) , .CARRY (CARRY[54]) );
FULL_ADDER FA_434 (.DATA_A (SUMMAND[547]) , .DATA_B (SUMMAND[548]) , .DATA_C (SUMMAND[549]) , .SAVE (INT_SUM[637]) , .CARRY (INT_CARRY[503]) );
HALF_ADDER HA_46 (.DATA_A (SUMMAND[550]) , .DATA_B (SUMMAND[551]) , .SAVE (INT_SUM[638]) , .CARRY (INT_CARRY[504]) );
FULL_ADDER FA_435 (.DATA_A (INT_SUM[637]) , .DATA_B (INT_SUM[638]) , .DATA_C (INT_CARRY[498]) , .SAVE (INT_SUM[639]) , .CARRY (INT_CARRY[505]) );
assign INT_SUM[641] = INT_CARRY[499];
FLIPFLOP LA_169 (.DIN (INT_SUM[639]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[640]) );
FLIPFLOP LA_170 (.DIN (INT_SUM[641]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[642]) );
FLIPFLOP LA_171 (.DIN (INT_CARRY[500]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[501]) );
FULL_ADDER FA_436 (.DATA_A (INT_SUM[640]) , .DATA_B (INT_SUM[642]) , .DATA_C (INT_CARRY[501]) , .SAVE (INT_SUM[643]) , .CARRY (INT_CARRY[507]) );
HALF_ADDER HA_47 (.DATA_A (INT_SUM[643]) , .DATA_B (INT_CARRY[502]) , .SAVE (SUM[55]) , .CARRY (CARRY[55]) );
FULL_ADDER FA_437 (.DATA_A (SUMMAND[552]) , .DATA_B (SUMMAND[553]) , .DATA_C (SUMMAND[554]) , .SAVE (INT_SUM[644]) , .CARRY (INT_CARRY[508]) );
HALF_ADDER HA_48 (.DATA_A (SUMMAND[555]) , .DATA_B (SUMMAND[556]) , .SAVE (INT_SUM[645]) , .CARRY (INT_CARRY[509]) );
FULL_ADDER FA_438 (.DATA_A (INT_SUM[644]) , .DATA_B (INT_SUM[645]) , .DATA_C (INT_CARRY[503]) , .SAVE (INT_SUM[646]) , .CARRY (INT_CARRY[510]) );
assign INT_SUM[648] = INT_CARRY[504];
FLIPFLOP LA_172 (.DIN (INT_SUM[646]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[647]) );
FLIPFLOP LA_173 (.DIN (INT_SUM[648]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[649]) );
FLIPFLOP LA_174 (.DIN (INT_CARRY[505]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[506]) );
FULL_ADDER FA_439 (.DATA_A (INT_SUM[647]) , .DATA_B (INT_SUM[649]) , .DATA_C (INT_CARRY[506]) , .SAVE (INT_SUM[650]) , .CARRY (INT_CARRY[512]) );
HALF_ADDER HA_49 (.DATA_A (INT_SUM[650]) , .DATA_B (INT_CARRY[507]) , .SAVE (SUM[56]) , .CARRY (CARRY[56]) );
FULL_ADDER FA_440 (.DATA_A (SUMMAND[557]) , .DATA_B (SUMMAND[558]) , .DATA_C (SUMMAND[559]) , .SAVE (INT_SUM[651]) , .CARRY (INT_CARRY[513]) );
FULL_ADDER FA_441 (.DATA_A (SUMMAND[560]) , .DATA_B (INT_CARRY[508]) , .DATA_C (INT_CARRY[509]) , .SAVE (INT_SUM[653]) , .CARRY (INT_CARRY[515]) );
FLIPFLOP LA_175 (.DIN (INT_SUM[651]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[652]) );
FLIPFLOP LA_176 (.DIN (INT_SUM[653]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[654]) );
FLIPFLOP LA_177 (.DIN (INT_CARRY[510]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[511]) );
FULL_ADDER FA_442 (.DATA_A (INT_SUM[652]) , .DATA_B (INT_SUM[654]) , .DATA_C (INT_CARRY[511]) , .SAVE (INT_SUM[655]) , .CARRY (INT_CARRY[517]) );
HALF_ADDER HA_50 (.DATA_A (INT_SUM[655]) , .DATA_B (INT_CARRY[512]) , .SAVE (SUM[57]) , .CARRY (CARRY[57]) );
FULL_ADDER FA_443 (.DATA_A (SUMMAND[561]) , .DATA_B (SUMMAND[562]) , .DATA_C (SUMMAND[563]) , .SAVE (INT_SUM[656]) , .CARRY (INT_CARRY[518]) );
assign INT_SUM[658] = SUMMAND[564];
FLIPFLOP LA_178 (.DIN (INT_SUM[656]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[657]) );
FLIPFLOP LA_179 (.DIN (INT_SUM[658]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[659]) );
FLIPFLOP LA_180 (.DIN (INT_CARRY[513]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[514]) );
FULL_ADDER FA_444 (.DATA_A (INT_SUM[657]) , .DATA_B (INT_SUM[659]) , .DATA_C (INT_CARRY[514]) , .SAVE (INT_SUM[660]) , .CARRY (INT_CARRY[520]) );
FLIPFLOP LA_181 (.DIN (INT_CARRY[515]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[516]) );
assign INT_SUM[661] = INT_CARRY[516];
FULL_ADDER FA_445 (.DATA_A (INT_SUM[660]) , .DATA_B (INT_SUM[661]) , .DATA_C (INT_CARRY[517]) , .SAVE (SUM[58]) , .CARRY (CARRY[58]) );
FULL_ADDER FA_446 (.DATA_A (SUMMAND[565]) , .DATA_B (SUMMAND[566]) , .DATA_C (SUMMAND[567]) , .SAVE (INT_SUM[662]) , .CARRY (INT_CARRY[521]) );
FLIPFLOP LA_182 (.DIN (INT_SUM[662]) , .RST(RST), .CLK (CLK) , .DOUT (INT_SUM[663]) );
assign INT_SUM[664] = INT_SUM[663];
FLIPFLOP LA_183 (.DIN (INT_CARRY[518]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[519]) );
assign INT_SUM[665] = INT_CARRY[519];
FULL_ADDER FA_447 (.DATA_A (INT_SUM[664]) , .DATA_B (INT_SUM[665]) , .DATA_C (INT_CARRY[520]) , .SAVE (SUM[59]) , .CARRY (CARRY[59]) );
FLIPFLOP LA_184 (.DIN (SUMMAND[568]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[0]) );
FLIPFLOP LA_185 (.DIN (SUMMAND[569]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[1]) );
FLIPFLOP LA_186 (.DIN (SUMMAND[570]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[2]) );
FULL_ADDER FA_448 (.DATA_A (LATCHED_PP[0]) , .DATA_B (LATCHED_PP[1]) , .DATA_C (LATCHED_PP[2]) , .SAVE (INT_SUM[666]) , .CARRY (INT_CARRY[523]) );
FLIPFLOP LA_187 (.DIN (INT_CARRY[521]) , .RST(RST), .CLK (CLK) , .DOUT (INT_CARRY[522]) );
assign INT_SUM[667] = INT_CARRY[522];
HALF_ADDER HA_51 (.DATA_A (INT_SUM[666]) , .DATA_B (INT_SUM[667]) , .SAVE (SUM[60]) , .CARRY (CARRY[60]) );
FLIPFLOP LA_188 (.DIN (SUMMAND[571]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[3]) );
assign INT_SUM[668] = LATCHED_PP[3];
FLIPFLOP LA_189 (.DIN (SUMMAND[572]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[4]) );
assign INT_SUM[669] = LATCHED_PP[4];
FULL_ADDER FA_449 (.DATA_A (INT_SUM[668]) , .DATA_B (INT_SUM[669]) , .DATA_C (INT_CARRY[523]) , .SAVE (SUM[61]) , .CARRY (CARRY[61]) );
FLIPFLOP LA_190 (.DIN (SUMMAND[573]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[5]) );
FLIPFLOP LA_191 (.DIN (SUMMAND[574]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[6]) );
HALF_ADDER HA_52 (.DATA_A (LATCHED_PP[5]) , .DATA_B (LATCHED_PP[6]) , .SAVE (SUM[62]) , .CARRY (CARRY[62]) );
FLIPFLOP LA_192 (.DIN (SUMMAND[575]) , .RST(RST), .CLK (CLK) , .DOUT (LATCHED_PP[7]) );
assign SUM[63] = LATCHED_PP[7];
endmodule
module INVBLOCK ( GIN, PHI, GOUT );
input GIN;
input PHI;
output GOUT;
assign GOUT = ~ GIN;
endmodule
module XXOR1 ( A, B, GIN, PHI, SUM );
input A;
input B;
input GIN;
input PHI;
output SUM;
assign SUM = ( ~ (A ^ B)) ^ GIN;
endmodule
module BLOCK0 ( A, B, PHI, POUT, GOUT );
input A;
input B;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (A | B);
assign GOUT = ~ (A & B);
endmodule
module BLOCK1 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 | PIN2);
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2 ( PIN1, PIN2, GIN1, GIN2, PHI, POUT, GOUT );
input PIN1;
input PIN2;
input GIN1;
input GIN2;
input PHI;
output POUT;
output GOUT;
assign POUT = ~ (PIN1 & PIN2);
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module BLOCK1A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 & (PIN2 | GIN1));
endmodule
module BLOCK2A ( PIN2, GIN1, GIN2, PHI, GOUT );
input PIN2;
input GIN1;
input GIN2;
input PHI;
output GOUT;
assign GOUT = ~ (GIN2 | (PIN2 & GIN1));
endmodule
module PRESTAGE_64 ( A, B, CIN, PHI, POUT, GOUT );
input [0:63] A;
input [0:63] B;
input CIN;
input PHI;
output [0:63] POUT;
output [0:64] GOUT;
BLOCK0 U10 (A[0] , B[0] , PHI , POUT[0] , GOUT[1] );
BLOCK0 U11 (A[1] , B[1] , PHI , POUT[1] , GOUT[2] );
BLOCK0 U12 (A[2] , B[2] , PHI , POUT[2] , GOUT[3] );
BLOCK0 U13 (A[3] , B[3] , PHI , POUT[3] , GOUT[4] );
BLOCK0 U14 (A[4] , B[4] , PHI , POUT[4] , GOUT[5] );
BLOCK0 U15 (A[5] , B[5] , PHI , POUT[5] , GOUT[6] );
BLOCK0 U16 (A[6] , B[6] , PHI , POUT[6] , GOUT[7] );
BLOCK0 U17 (A[7] , B[7] , PHI , POUT[7] , GOUT[8] );
BLOCK0 U18 (A[8] , B[8] , PHI , POUT[8] , GOUT[9] );
BLOCK0 U19 (A[9] , B[9] , PHI , POUT[9] , GOUT[10] );
BLOCK0 U110 (A[10] , B[10] , PHI , POUT[10] , GOUT[11] );
BLOCK0 U111 (A[11] , B[11] , PHI , POUT[11] , GOUT[12] );
BLOCK0 U112 (A[12] , B[12] , PHI , POUT[12] , GOUT[13] );
BLOCK0 U113 (A[13] , B[13] , PHI , POUT[13] , GOUT[14] );
BLOCK0 U114 (A[14] , B[14] , PHI , POUT[14] , GOUT[15] );
BLOCK0 U115 (A[15] , B[15] , PHI , POUT[15] , GOUT[16] );
BLOCK0 U116 (A[16] , B[16] , PHI , POUT[16] , GOUT[17] );
BLOCK0 U117 (A[17] , B[17] , PHI , POUT[17] , GOUT[18] );
BLOCK0 U118 (A[18] , B[18] , PHI , POUT[18] , GOUT[19] );
BLOCK0 U119 (A[19] , B[19] , PHI , POUT[19] , GOUT[20] );
BLOCK0 U120 (A[20] , B[20] , PHI , POUT[20] , GOUT[21] );
BLOCK0 U121 (A[21] , B[21] , PHI , POUT[21] , GOUT[22] );
BLOCK0 U122 (A[22] , B[22] , PHI , POUT[22] , GOUT[23] );
BLOCK0 U123 (A[23] , B[23] , PHI , POUT[23] , GOUT[24] );
BLOCK0 U124 (A[24] , B[24] , PHI , POUT[24] , GOUT[25] );
BLOCK0 U125 (A[25] , B[25] , PHI , POUT[25] , GOUT[26] );
BLOCK0 U126 (A[26] , B[26] , PHI , POUT[26] , GOUT[27] );
BLOCK0 U127 (A[27] , B[27] , PHI , POUT[27] , GOUT[28] );
BLOCK0 U128 (A[28] , B[28] , PHI , POUT[28] , GOUT[29] );
BLOCK0 U129 (A[29] , B[29] , PHI , POUT[29] , GOUT[30] );
BLOCK0 U130 (A[30] , B[30] , PHI , POUT[30] , GOUT[31] );
BLOCK0 U131 (A[31] , B[31] , PHI , POUT[31] , GOUT[32] );
BLOCK0 U132 (A[32] , B[32] , PHI , POUT[32] , GOUT[33] );
BLOCK0 U133 (A[33] , B[33] , PHI , POUT[33] , GOUT[34] );
BLOCK0 U134 (A[34] , B[34] , PHI , POUT[34] , GOUT[35] );
BLOCK0 U135 (A[35] , B[35] , PHI , POUT[35] , GOUT[36] );
BLOCK0 U136 (A[36] , B[36] , PHI , POUT[36] , GOUT[37] );
BLOCK0 U137 (A[37] , B[37] , PHI , POUT[37] , GOUT[38] );
BLOCK0 U138 (A[38] , B[38] , PHI , POUT[38] , GOUT[39] );
BLOCK0 U139 (A[39] , B[39] , PHI , POUT[39] , GOUT[40] );
BLOCK0 U140 (A[40] , B[40] , PHI , POUT[40] , GOUT[41] );
BLOCK0 U141 (A[41] , B[41] , PHI , POUT[41] , GOUT[42] );
BLOCK0 U142 (A[42] , B[42] , PHI , POUT[42] , GOUT[43] );
BLOCK0 U143 (A[43] , B[43] , PHI , POUT[43] , GOUT[44] );
BLOCK0 U144 (A[44] , B[44] , PHI , POUT[44] , GOUT[45] );
BLOCK0 U145 (A[45] , B[45] , PHI , POUT[45] , GOUT[46] );
BLOCK0 U146 (A[46] , B[46] , PHI , POUT[46] , GOUT[47] );
BLOCK0 U147 (A[47] , B[47] , PHI , POUT[47] , GOUT[48] );
BLOCK0 U148 (A[48] , B[48] , PHI , POUT[48] , GOUT[49] );
BLOCK0 U149 (A[49] , B[49] , PHI , POUT[49] , GOUT[50] );
BLOCK0 U150 (A[50] , B[50] , PHI , POUT[50] , GOUT[51] );
BLOCK0 U151 (A[51] , B[51] , PHI , POUT[51] , GOUT[52] );
BLOCK0 U152 (A[52] , B[52] , PHI , POUT[52] , GOUT[53] );
BLOCK0 U153 (A[53] , B[53] , PHI , POUT[53] , GOUT[54] );
BLOCK0 U154 (A[54] , B[54] , PHI , POUT[54] , GOUT[55] );
BLOCK0 U155 (A[55] , B[55] , PHI , POUT[55] , GOUT[56] );
BLOCK0 U156 (A[56] , B[56] , PHI , POUT[56] , GOUT[57] );
BLOCK0 U157 (A[57] , B[57] , PHI , POUT[57] , GOUT[58] );
BLOCK0 U158 (A[58] , B[58] , PHI , POUT[58] , GOUT[59] );
BLOCK0 U159 (A[59] , B[59] , PHI , POUT[59] , GOUT[60] );
BLOCK0 U160 (A[60] , B[60] , PHI , POUT[60] , GOUT[61] );
BLOCK0 U161 (A[61] , B[61] , PHI , POUT[61] , GOUT[62] );
BLOCK0 U162 (A[62] , B[62] , PHI , POUT[62] , GOUT[63] );
BLOCK0 U163 (A[63] , B[63] , PHI , POUT[63] , GOUT[64] );
INVBLOCK U2 (CIN , PHI , GOUT[0] );
endmodule
module DBLC_0_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:62] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
BLOCK1A U21 (PIN[0] , GIN[0] , GIN[1] , PHI , GOUT[1] );
BLOCK1 U32 (PIN[0] , PIN[1] , GIN[1] , GIN[2] , PHI , POUT[0] , GOUT[2] );
BLOCK1 U33 (PIN[1] , PIN[2] , GIN[2] , GIN[3] , PHI , POUT[1] , GOUT[3] );
BLOCK1 U34 (PIN[2] , PIN[3] , GIN[3] , GIN[4] , PHI , POUT[2] , GOUT[4] );
BLOCK1 U35 (PIN[3] , PIN[4] , GIN[4] , GIN[5] , PHI , POUT[3] , GOUT[5] );
BLOCK1 U36 (PIN[4] , PIN[5] , GIN[5] , GIN[6] , PHI , POUT[4] , GOUT[6] );
BLOCK1 U37 (PIN[5] , PIN[6] , GIN[6] , GIN[7] , PHI , POUT[5] , GOUT[7] );
BLOCK1 U38 (PIN[6] , PIN[7] , GIN[7] , GIN[8] , PHI , POUT[6] , GOUT[8] );
BLOCK1 U39 (PIN[7] , PIN[8] , GIN[8] , GIN[9] , PHI , POUT[7] , GOUT[9] );
BLOCK1 U310 (PIN[8] , PIN[9] , GIN[9] , GIN[10] , PHI , POUT[8] , GOUT[10] );
BLOCK1 U311 (PIN[9] , PIN[10] , GIN[10] , GIN[11] , PHI , POUT[9] , GOUT[11] );
BLOCK1 U312 (PIN[10] , PIN[11] , GIN[11] , GIN[12] , PHI , POUT[10] , GOUT[12] );
BLOCK1 U313 (PIN[11] , PIN[12] , GIN[12] , GIN[13] , PHI , POUT[11] , GOUT[13] );
BLOCK1 U314 (PIN[12] , PIN[13] , GIN[13] , GIN[14] , PHI , POUT[12] , GOUT[14] );
BLOCK1 U315 (PIN[13] , PIN[14] , GIN[14] , GIN[15] , PHI , POUT[13] , GOUT[15] );
BLOCK1 U316 (PIN[14] , PIN[15] , GIN[15] , GIN[16] , PHI , POUT[14] , GOUT[16] );
BLOCK1 U317 (PIN[15] , PIN[16] , GIN[16] , GIN[17] , PHI , POUT[15] , GOUT[17] );
BLOCK1 U318 (PIN[16] , PIN[17] , GIN[17] , GIN[18] , PHI , POUT[16] , GOUT[18] );
BLOCK1 U319 (PIN[17] , PIN[18] , GIN[18] , GIN[19] , PHI , POUT[17] , GOUT[19] );
BLOCK1 U320 (PIN[18] , PIN[19] , GIN[19] , GIN[20] , PHI , POUT[18] , GOUT[20] );
BLOCK1 U321 (PIN[19] , PIN[20] , GIN[20] , GIN[21] , PHI , POUT[19] , GOUT[21] );
BLOCK1 U322 (PIN[20] , PIN[21] , GIN[21] , GIN[22] , PHI , POUT[20] , GOUT[22] );
BLOCK1 U323 (PIN[21] , PIN[22] , GIN[22] , GIN[23] , PHI , POUT[21] , GOUT[23] );
BLOCK1 U324 (PIN[22] , PIN[23] , GIN[23] , GIN[24] , PHI , POUT[22] , GOUT[24] );
BLOCK1 U325 (PIN[23] , PIN[24] , GIN[24] , GIN[25] , PHI , POUT[23] , GOUT[25] );
BLOCK1 U326 (PIN[24] , PIN[25] , GIN[25] , GIN[26] , PHI , POUT[24] , GOUT[26] );
BLOCK1 U327 (PIN[25] , PIN[26] , GIN[26] , GIN[27] , PHI , POUT[25] , GOUT[27] );
BLOCK1 U328 (PIN[26] , PIN[27] , GIN[27] , GIN[28] , PHI , POUT[26] , GOUT[28] );
BLOCK1 U329 (PIN[27] , PIN[28] , GIN[28] , GIN[29] , PHI , POUT[27] , GOUT[29] );
BLOCK1 U330 (PIN[28] , PIN[29] , GIN[29] , GIN[30] , PHI , POUT[28] , GOUT[30] );
BLOCK1 U331 (PIN[29] , PIN[30] , GIN[30] , GIN[31] , PHI , POUT[29] , GOUT[31] );
BLOCK1 U332 (PIN[30] , PIN[31] , GIN[31] , GIN[32] , PHI , POUT[30] , GOUT[32] );
BLOCK1 U333 (PIN[31] , PIN[32] , GIN[32] , GIN[33] , PHI , POUT[31] , GOUT[33] );
BLOCK1 U334 (PIN[32] , PIN[33] , GIN[33] , GIN[34] , PHI , POUT[32] , GOUT[34] );
BLOCK1 U335 (PIN[33] , PIN[34] , GIN[34] , GIN[35] , PHI , POUT[33] , GOUT[35] );
BLOCK1 U336 (PIN[34] , PIN[35] , GIN[35] , GIN[36] , PHI , POUT[34] , GOUT[36] );
BLOCK1 U337 (PIN[35] , PIN[36] , GIN[36] , GIN[37] , PHI , POUT[35] , GOUT[37] );
BLOCK1 U338 (PIN[36] , PIN[37] , GIN[37] , GIN[38] , PHI , POUT[36] , GOUT[38] );
BLOCK1 U339 (PIN[37] , PIN[38] , GIN[38] , GIN[39] , PHI , POUT[37] , GOUT[39] );
BLOCK1 U340 (PIN[38] , PIN[39] , GIN[39] , GIN[40] , PHI , POUT[38] , GOUT[40] );
BLOCK1 U341 (PIN[39] , PIN[40] , GIN[40] , GIN[41] , PHI , POUT[39] , GOUT[41] );
BLOCK1 U342 (PIN[40] , PIN[41] , GIN[41] , GIN[42] , PHI , POUT[40] , GOUT[42] );
BLOCK1 U343 (PIN[41] , PIN[42] , GIN[42] , GIN[43] , PHI , POUT[41] , GOUT[43] );
BLOCK1 U344 (PIN[42] , PIN[43] , GIN[43] , GIN[44] , PHI , POUT[42] , GOUT[44] );
BLOCK1 U345 (PIN[43] , PIN[44] , GIN[44] , GIN[45] , PHI , POUT[43] , GOUT[45] );
BLOCK1 U346 (PIN[44] , PIN[45] , GIN[45] , GIN[46] , PHI , POUT[44] , GOUT[46] );
BLOCK1 U347 (PIN[45] , PIN[46] , GIN[46] , GIN[47] , PHI , POUT[45] , GOUT[47] );
BLOCK1 U348 (PIN[46] , PIN[47] , GIN[47] , GIN[48] , PHI , POUT[46] , GOUT[48] );
BLOCK1 U349 (PIN[47] , PIN[48] , GIN[48] , GIN[49] , PHI , POUT[47] , GOUT[49] );
BLOCK1 U350 (PIN[48] , PIN[49] , GIN[49] , GIN[50] , PHI , POUT[48] , GOUT[50] );
BLOCK1 U351 (PIN[49] , PIN[50] , GIN[50] , GIN[51] , PHI , POUT[49] , GOUT[51] );
BLOCK1 U352 (PIN[50] , PIN[51] , GIN[51] , GIN[52] , PHI , POUT[50] , GOUT[52] );
BLOCK1 U353 (PIN[51] , PIN[52] , GIN[52] , GIN[53] , PHI , POUT[51] , GOUT[53] );
BLOCK1 U354 (PIN[52] , PIN[53] , GIN[53] , GIN[54] , PHI , POUT[52] , GOUT[54] );
BLOCK1 U355 (PIN[53] , PIN[54] , GIN[54] , GIN[55] , PHI , POUT[53] , GOUT[55] );
BLOCK1 U356 (PIN[54] , PIN[55] , GIN[55] , GIN[56] , PHI , POUT[54] , GOUT[56] );
BLOCK1 U357 (PIN[55] , PIN[56] , GIN[56] , GIN[57] , PHI , POUT[55] , GOUT[57] );
BLOCK1 U358 (PIN[56] , PIN[57] , GIN[57] , GIN[58] , PHI , POUT[56] , GOUT[58] );
BLOCK1 U359 (PIN[57] , PIN[58] , GIN[58] , GIN[59] , PHI , POUT[57] , GOUT[59] );
BLOCK1 U360 (PIN[58] , PIN[59] , GIN[59] , GIN[60] , PHI , POUT[58] , GOUT[60] );
BLOCK1 U361 (PIN[59] , PIN[60] , GIN[60] , GIN[61] , PHI , POUT[59] , GOUT[61] );
BLOCK1 U362 (PIN[60] , PIN[61] , GIN[61] , GIN[62] , PHI , POUT[60] , GOUT[62] );
BLOCK1 U363 (PIN[61] , PIN[62] , GIN[62] , GIN[63] , PHI , POUT[61] , GOUT[63] );
BLOCK1 U364 (PIN[62] , PIN[63] , GIN[63] , GIN[64] , PHI , POUT[62] , GOUT[64] );
endmodule
module DBLC_1_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:62] PIN;
input [0:64] GIN;
input PHI;
output [0:60] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
BLOCK2A U22 (PIN[0] , GIN[0] , GIN[2] , PHI , GOUT[2] );
BLOCK2A U23 (PIN[1] , GIN[1] , GIN[3] , PHI , GOUT[3] );
BLOCK2 U34 (PIN[0] , PIN[2] , GIN[2] , GIN[4] , PHI , POUT[0] , GOUT[4] );
BLOCK2 U35 (PIN[1] , PIN[3] , GIN[3] , GIN[5] , PHI , POUT[1] , GOUT[5] );
BLOCK2 U36 (PIN[2] , PIN[4] , GIN[4] , GIN[6] , PHI , POUT[2] , GOUT[6] );
BLOCK2 U37 (PIN[3] , PIN[5] , GIN[5] , GIN[7] , PHI , POUT[3] , GOUT[7] );
BLOCK2 U38 (PIN[4] , PIN[6] , GIN[6] , GIN[8] , PHI , POUT[4] , GOUT[8] );
BLOCK2 U39 (PIN[5] , PIN[7] , GIN[7] , GIN[9] , PHI , POUT[5] , GOUT[9] );
BLOCK2 U310 (PIN[6] , PIN[8] , GIN[8] , GIN[10] , PHI , POUT[6] , GOUT[10] );
BLOCK2 U311 (PIN[7] , PIN[9] , GIN[9] , GIN[11] , PHI , POUT[7] , GOUT[11] );
BLOCK2 U312 (PIN[8] , PIN[10] , GIN[10] , GIN[12] , PHI , POUT[8] , GOUT[12] );
BLOCK2 U313 (PIN[9] , PIN[11] , GIN[11] , GIN[13] , PHI , POUT[9] , GOUT[13] );
BLOCK2 U314 (PIN[10] , PIN[12] , GIN[12] , GIN[14] , PHI , POUT[10] , GOUT[14] );
BLOCK2 U315 (PIN[11] , PIN[13] , GIN[13] , GIN[15] , PHI , POUT[11] , GOUT[15] );
BLOCK2 U316 (PIN[12] , PIN[14] , GIN[14] , GIN[16] , PHI , POUT[12] , GOUT[16] );
BLOCK2 U317 (PIN[13] , PIN[15] , GIN[15] , GIN[17] , PHI , POUT[13] , GOUT[17] );
BLOCK2 U318 (PIN[14] , PIN[16] , GIN[16] , GIN[18] , PHI , POUT[14] , GOUT[18] );
BLOCK2 U319 (PIN[15] , PIN[17] , GIN[17] , GIN[19] , PHI , POUT[15] , GOUT[19] );
BLOCK2 U320 (PIN[16] , PIN[18] , GIN[18] , GIN[20] , PHI , POUT[16] , GOUT[20] );
BLOCK2 U321 (PIN[17] , PIN[19] , GIN[19] , GIN[21] , PHI , POUT[17] , GOUT[21] );
BLOCK2 U322 (PIN[18] , PIN[20] , GIN[20] , GIN[22] , PHI , POUT[18] , GOUT[22] );
BLOCK2 U323 (PIN[19] , PIN[21] , GIN[21] , GIN[23] , PHI , POUT[19] , GOUT[23] );
BLOCK2 U324 (PIN[20] , PIN[22] , GIN[22] , GIN[24] , PHI , POUT[20] , GOUT[24] );
BLOCK2 U325 (PIN[21] , PIN[23] , GIN[23] , GIN[25] , PHI , POUT[21] , GOUT[25] );
BLOCK2 U326 (PIN[22] , PIN[24] , GIN[24] , GIN[26] , PHI , POUT[22] , GOUT[26] );
BLOCK2 U327 (PIN[23] , PIN[25] , GIN[25] , GIN[27] , PHI , POUT[23] , GOUT[27] );
BLOCK2 U328 (PIN[24] , PIN[26] , GIN[26] , GIN[28] , PHI , POUT[24] , GOUT[28] );
BLOCK2 U329 (PIN[25] , PIN[27] , GIN[27] , GIN[29] , PHI , POUT[25] , GOUT[29] );
BLOCK2 U330 (PIN[26] , PIN[28] , GIN[28] , GIN[30] , PHI , POUT[26] , GOUT[30] );
BLOCK2 U331 (PIN[27] , PIN[29] , GIN[29] , GIN[31] , PHI , POUT[27] , GOUT[31] );
BLOCK2 U332 (PIN[28] , PIN[30] , GIN[30] , GIN[32] , PHI , POUT[28] , GOUT[32] );
BLOCK2 U333 (PIN[29] , PIN[31] , GIN[31] , GIN[33] , PHI , POUT[29] , GOUT[33] );
BLOCK2 U334 (PIN[30] , PIN[32] , GIN[32] , GIN[34] , PHI , POUT[30] , GOUT[34] );
BLOCK2 U335 (PIN[31] , PIN[33] , GIN[33] , GIN[35] , PHI , POUT[31] , GOUT[35] );
BLOCK2 U336 (PIN[32] , PIN[34] , GIN[34] , GIN[36] , PHI , POUT[32] , GOUT[36] );
BLOCK2 U337 (PIN[33] , PIN[35] , GIN[35] , GIN[37] , PHI , POUT[33] , GOUT[37] );
BLOCK2 U338 (PIN[34] , PIN[36] , GIN[36] , GIN[38] , PHI , POUT[34] , GOUT[38] );
BLOCK2 U339 (PIN[35] , PIN[37] , GIN[37] , GIN[39] , PHI , POUT[35] , GOUT[39] );
BLOCK2 U340 (PIN[36] , PIN[38] , GIN[38] , GIN[40] , PHI , POUT[36] , GOUT[40] );
BLOCK2 U341 (PIN[37] , PIN[39] , GIN[39] , GIN[41] , PHI , POUT[37] , GOUT[41] );
BLOCK2 U342 (PIN[38] , PIN[40] , GIN[40] , GIN[42] , PHI , POUT[38] , GOUT[42] );
BLOCK2 U343 (PIN[39] , PIN[41] , GIN[41] , GIN[43] , PHI , POUT[39] , GOUT[43] );
BLOCK2 U344 (PIN[40] , PIN[42] , GIN[42] , GIN[44] , PHI , POUT[40] , GOUT[44] );
BLOCK2 U345 (PIN[41] , PIN[43] , GIN[43] , GIN[45] , PHI , POUT[41] , GOUT[45] );
BLOCK2 U346 (PIN[42] , PIN[44] , GIN[44] , GIN[46] , PHI , POUT[42] , GOUT[46] );
BLOCK2 U347 (PIN[43] , PIN[45] , GIN[45] , GIN[47] , PHI , POUT[43] , GOUT[47] );
BLOCK2 U348 (PIN[44] , PIN[46] , GIN[46] , GIN[48] , PHI , POUT[44] , GOUT[48] );
BLOCK2 U349 (PIN[45] , PIN[47] , GIN[47] , GIN[49] , PHI , POUT[45] , GOUT[49] );
BLOCK2 U350 (PIN[46] , PIN[48] , GIN[48] , GIN[50] , PHI , POUT[46] , GOUT[50] );
BLOCK2 U351 (PIN[47] , PIN[49] , GIN[49] , GIN[51] , PHI , POUT[47] , GOUT[51] );
BLOCK2 U352 (PIN[48] , PIN[50] , GIN[50] , GIN[52] , PHI , POUT[48] , GOUT[52] );
BLOCK2 U353 (PIN[49] , PIN[51] , GIN[51] , GIN[53] , PHI , POUT[49] , GOUT[53] );
BLOCK2 U354 (PIN[50] , PIN[52] , GIN[52] , GIN[54] , PHI , POUT[50] , GOUT[54] );
BLOCK2 U355 (PIN[51] , PIN[53] , GIN[53] , GIN[55] , PHI , POUT[51] , GOUT[55] );
BLOCK2 U356 (PIN[52] , PIN[54] , GIN[54] , GIN[56] , PHI , POUT[52] , GOUT[56] );
BLOCK2 U357 (PIN[53] , PIN[55] , GIN[55] , GIN[57] , PHI , POUT[53] , GOUT[57] );
BLOCK2 U358 (PIN[54] , PIN[56] , GIN[56] , GIN[58] , PHI , POUT[54] , GOUT[58] );
BLOCK2 U359 (PIN[55] , PIN[57] , GIN[57] , GIN[59] , PHI , POUT[55] , GOUT[59] );
BLOCK2 U360 (PIN[56] , PIN[58] , GIN[58] , GIN[60] , PHI , POUT[56] , GOUT[60] );
BLOCK2 U361 (PIN[57] , PIN[59] , GIN[59] , GIN[61] , PHI , POUT[57] , GOUT[61] );
BLOCK2 U362 (PIN[58] , PIN[60] , GIN[60] , GIN[62] , PHI , POUT[58] , GOUT[62] );
BLOCK2 U363 (PIN[59] , PIN[61] , GIN[61] , GIN[63] , PHI , POUT[59] , GOUT[63] );
BLOCK2 U364 (PIN[60] , PIN[62] , GIN[62] , GIN[64] , PHI , POUT[60] , GOUT[64] );
endmodule
module DBLC_2_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:60] PIN;
input [0:64] GIN;
input PHI;
output [0:56] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
BLOCK1A U24 (PIN[0] , GIN[0] , GIN[4] , PHI , GOUT[4] );
BLOCK1A U25 (PIN[1] , GIN[1] , GIN[5] , PHI , GOUT[5] );
BLOCK1A U26 (PIN[2] , GIN[2] , GIN[6] , PHI , GOUT[6] );
BLOCK1A U27 (PIN[3] , GIN[3] , GIN[7] , PHI , GOUT[7] );
BLOCK1 U38 (PIN[0] , PIN[4] , GIN[4] , GIN[8] , PHI , POUT[0] , GOUT[8] );
BLOCK1 U39 (PIN[1] , PIN[5] , GIN[5] , GIN[9] , PHI , POUT[1] , GOUT[9] );
BLOCK1 U310 (PIN[2] , PIN[6] , GIN[6] , GIN[10] , PHI , POUT[2] , GOUT[10] );
BLOCK1 U311 (PIN[3] , PIN[7] , GIN[7] , GIN[11] , PHI , POUT[3] , GOUT[11] );
BLOCK1 U312 (PIN[4] , PIN[8] , GIN[8] , GIN[12] , PHI , POUT[4] , GOUT[12] );
BLOCK1 U313 (PIN[5] , PIN[9] , GIN[9] , GIN[13] , PHI , POUT[5] , GOUT[13] );
BLOCK1 U314 (PIN[6] , PIN[10] , GIN[10] , GIN[14] , PHI , POUT[6] , GOUT[14] );
BLOCK1 U315 (PIN[7] , PIN[11] , GIN[11] , GIN[15] , PHI , POUT[7] , GOUT[15] );
BLOCK1 U316 (PIN[8] , PIN[12] , GIN[12] , GIN[16] , PHI , POUT[8] , GOUT[16] );
BLOCK1 U317 (PIN[9] , PIN[13] , GIN[13] , GIN[17] , PHI , POUT[9] , GOUT[17] );
BLOCK1 U318 (PIN[10] , PIN[14] , GIN[14] , GIN[18] , PHI , POUT[10] , GOUT[18] );
BLOCK1 U319 (PIN[11] , PIN[15] , GIN[15] , GIN[19] , PHI , POUT[11] , GOUT[19] );
BLOCK1 U320 (PIN[12] , PIN[16] , GIN[16] , GIN[20] , PHI , POUT[12] , GOUT[20] );
BLOCK1 U321 (PIN[13] , PIN[17] , GIN[17] , GIN[21] , PHI , POUT[13] , GOUT[21] );
BLOCK1 U322 (PIN[14] , PIN[18] , GIN[18] , GIN[22] , PHI , POUT[14] , GOUT[22] );
BLOCK1 U323 (PIN[15] , PIN[19] , GIN[19] , GIN[23] , PHI , POUT[15] , GOUT[23] );
BLOCK1 U324 (PIN[16] , PIN[20] , GIN[20] , GIN[24] , PHI , POUT[16] , GOUT[24] );
BLOCK1 U325 (PIN[17] , PIN[21] , GIN[21] , GIN[25] , PHI , POUT[17] , GOUT[25] );
BLOCK1 U326 (PIN[18] , PIN[22] , GIN[22] , GIN[26] , PHI , POUT[18] , GOUT[26] );
BLOCK1 U327 (PIN[19] , PIN[23] , GIN[23] , GIN[27] , PHI , POUT[19] , GOUT[27] );
BLOCK1 U328 (PIN[20] , PIN[24] , GIN[24] , GIN[28] , PHI , POUT[20] , GOUT[28] );
BLOCK1 U329 (PIN[21] , PIN[25] , GIN[25] , GIN[29] , PHI , POUT[21] , GOUT[29] );
BLOCK1 U330 (PIN[22] , PIN[26] , GIN[26] , GIN[30] , PHI , POUT[22] , GOUT[30] );
BLOCK1 U331 (PIN[23] , PIN[27] , GIN[27] , GIN[31] , PHI , POUT[23] , GOUT[31] );
BLOCK1 U332 (PIN[24] , PIN[28] , GIN[28] , GIN[32] , PHI , POUT[24] , GOUT[32] );
BLOCK1 U333 (PIN[25] , PIN[29] , GIN[29] , GIN[33] , PHI , POUT[25] , GOUT[33] );
BLOCK1 U334 (PIN[26] , PIN[30] , GIN[30] , GIN[34] , PHI , POUT[26] , GOUT[34] );
BLOCK1 U335 (PIN[27] , PIN[31] , GIN[31] , GIN[35] , PHI , POUT[27] , GOUT[35] );
BLOCK1 U336 (PIN[28] , PIN[32] , GIN[32] , GIN[36] , PHI , POUT[28] , GOUT[36] );
BLOCK1 U337 (PIN[29] , PIN[33] , GIN[33] , GIN[37] , PHI , POUT[29] , GOUT[37] );
BLOCK1 U338 (PIN[30] , PIN[34] , GIN[34] , GIN[38] , PHI , POUT[30] , GOUT[38] );
BLOCK1 U339 (PIN[31] , PIN[35] , GIN[35] , GIN[39] , PHI , POUT[31] , GOUT[39] );
BLOCK1 U340 (PIN[32] , PIN[36] , GIN[36] , GIN[40] , PHI , POUT[32] , GOUT[40] );
BLOCK1 U341 (PIN[33] , PIN[37] , GIN[37] , GIN[41] , PHI , POUT[33] , GOUT[41] );
BLOCK1 U342 (PIN[34] , PIN[38] , GIN[38] , GIN[42] , PHI , POUT[34] , GOUT[42] );
BLOCK1 U343 (PIN[35] , PIN[39] , GIN[39] , GIN[43] , PHI , POUT[35] , GOUT[43] );
BLOCK1 U344 (PIN[36] , PIN[40] , GIN[40] , GIN[44] , PHI , POUT[36] , GOUT[44] );
BLOCK1 U345 (PIN[37] , PIN[41] , GIN[41] , GIN[45] , PHI , POUT[37] , GOUT[45] );
BLOCK1 U346 (PIN[38] , PIN[42] , GIN[42] , GIN[46] , PHI , POUT[38] , GOUT[46] );
BLOCK1 U347 (PIN[39] , PIN[43] , GIN[43] , GIN[47] , PHI , POUT[39] , GOUT[47] );
BLOCK1 U348 (PIN[40] , PIN[44] , GIN[44] , GIN[48] , PHI , POUT[40] , GOUT[48] );
BLOCK1 U349 (PIN[41] , PIN[45] , GIN[45] , GIN[49] , PHI , POUT[41] , GOUT[49] );
BLOCK1 U350 (PIN[42] , PIN[46] , GIN[46] , GIN[50] , PHI , POUT[42] , GOUT[50] );
BLOCK1 U351 (PIN[43] , PIN[47] , GIN[47] , GIN[51] , PHI , POUT[43] , GOUT[51] );
BLOCK1 U352 (PIN[44] , PIN[48] , GIN[48] , GIN[52] , PHI , POUT[44] , GOUT[52] );
BLOCK1 U353 (PIN[45] , PIN[49] , GIN[49] , GIN[53] , PHI , POUT[45] , GOUT[53] );
BLOCK1 U354 (PIN[46] , PIN[50] , GIN[50] , GIN[54] , PHI , POUT[46] , GOUT[54] );
BLOCK1 U355 (PIN[47] , PIN[51] , GIN[51] , GIN[55] , PHI , POUT[47] , GOUT[55] );
BLOCK1 U356 (PIN[48] , PIN[52] , GIN[52] , GIN[56] , PHI , POUT[48] , GOUT[56] );
BLOCK1 U357 (PIN[49] , PIN[53] , GIN[53] , GIN[57] , PHI , POUT[49] , GOUT[57] );
BLOCK1 U358 (PIN[50] , PIN[54] , GIN[54] , GIN[58] , PHI , POUT[50] , GOUT[58] );
BLOCK1 U359 (PIN[51] , PIN[55] , GIN[55] , GIN[59] , PHI , POUT[51] , GOUT[59] );
BLOCK1 U360 (PIN[52] , PIN[56] , GIN[56] , GIN[60] , PHI , POUT[52] , GOUT[60] );
BLOCK1 U361 (PIN[53] , PIN[57] , GIN[57] , GIN[61] , PHI , POUT[53] , GOUT[61] );
BLOCK1 U362 (PIN[54] , PIN[58] , GIN[58] , GIN[62] , PHI , POUT[54] , GOUT[62] );
BLOCK1 U363 (PIN[55] , PIN[59] , GIN[59] , GIN[63] , PHI , POUT[55] , GOUT[63] );
BLOCK1 U364 (PIN[56] , PIN[60] , GIN[60] , GIN[64] , PHI , POUT[56] , GOUT[64] );
endmodule
module DBLC_3_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:56] PIN;
input [0:64] GIN;
input PHI;
output [0:48] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
BLOCK2A U28 (PIN[0] , GIN[0] , GIN[8] , PHI , GOUT[8] );
BLOCK2A U29 (PIN[1] , GIN[1] , GIN[9] , PHI , GOUT[9] );
BLOCK2A U210 (PIN[2] , GIN[2] , GIN[10] , PHI , GOUT[10] );
BLOCK2A U211 (PIN[3] , GIN[3] , GIN[11] , PHI , GOUT[11] );
BLOCK2A U212 (PIN[4] , GIN[4] , GIN[12] , PHI , GOUT[12] );
BLOCK2A U213 (PIN[5] , GIN[5] , GIN[13] , PHI , GOUT[13] );
BLOCK2A U214 (PIN[6] , GIN[6] , GIN[14] , PHI , GOUT[14] );
BLOCK2A U215 (PIN[7] , GIN[7] , GIN[15] , PHI , GOUT[15] );
BLOCK2 U316 (PIN[0] , PIN[8] , GIN[8] , GIN[16] , PHI , POUT[0] , GOUT[16] );
BLOCK2 U317 (PIN[1] , PIN[9] , GIN[9] , GIN[17] , PHI , POUT[1] , GOUT[17] );
BLOCK2 U318 (PIN[2] , PIN[10] , GIN[10] , GIN[18] , PHI , POUT[2] , GOUT[18] );
BLOCK2 U319 (PIN[3] , PIN[11] , GIN[11] , GIN[19] , PHI , POUT[3] , GOUT[19] );
BLOCK2 U320 (PIN[4] , PIN[12] , GIN[12] , GIN[20] , PHI , POUT[4] , GOUT[20] );
BLOCK2 U321 (PIN[5] , PIN[13] , GIN[13] , GIN[21] , PHI , POUT[5] , GOUT[21] );
BLOCK2 U322 (PIN[6] , PIN[14] , GIN[14] , GIN[22] , PHI , POUT[6] , GOUT[22] );
BLOCK2 U323 (PIN[7] , PIN[15] , GIN[15] , GIN[23] , PHI , POUT[7] , GOUT[23] );
BLOCK2 U324 (PIN[8] , PIN[16] , GIN[16] , GIN[24] , PHI , POUT[8] , GOUT[24] );
BLOCK2 U325 (PIN[9] , PIN[17] , GIN[17] , GIN[25] , PHI , POUT[9] , GOUT[25] );
BLOCK2 U326 (PIN[10] , PIN[18] , GIN[18] , GIN[26] , PHI , POUT[10] , GOUT[26] );
BLOCK2 U327 (PIN[11] , PIN[19] , GIN[19] , GIN[27] , PHI , POUT[11] , GOUT[27] );
BLOCK2 U328 (PIN[12] , PIN[20] , GIN[20] , GIN[28] , PHI , POUT[12] , GOUT[28] );
BLOCK2 U329 (PIN[13] , PIN[21] , GIN[21] , GIN[29] , PHI , POUT[13] , GOUT[29] );
BLOCK2 U330 (PIN[14] , PIN[22] , GIN[22] , GIN[30] , PHI , POUT[14] , GOUT[30] );
BLOCK2 U331 (PIN[15] , PIN[23] , GIN[23] , GIN[31] , PHI , POUT[15] , GOUT[31] );
BLOCK2 U332 (PIN[16] , PIN[24] , GIN[24] , GIN[32] , PHI , POUT[16] , GOUT[32] );
BLOCK2 U333 (PIN[17] , PIN[25] , GIN[25] , GIN[33] , PHI , POUT[17] , GOUT[33] );
BLOCK2 U334 (PIN[18] , PIN[26] , GIN[26] , GIN[34] , PHI , POUT[18] , GOUT[34] );
BLOCK2 U335 (PIN[19] , PIN[27] , GIN[27] , GIN[35] , PHI , POUT[19] , GOUT[35] );
BLOCK2 U336 (PIN[20] , PIN[28] , GIN[28] , GIN[36] , PHI , POUT[20] , GOUT[36] );
BLOCK2 U337 (PIN[21] , PIN[29] , GIN[29] , GIN[37] , PHI , POUT[21] , GOUT[37] );
BLOCK2 U338 (PIN[22] , PIN[30] , GIN[30] , GIN[38] , PHI , POUT[22] , GOUT[38] );
BLOCK2 U339 (PIN[23] , PIN[31] , GIN[31] , GIN[39] , PHI , POUT[23] , GOUT[39] );
BLOCK2 U340 (PIN[24] , PIN[32] , GIN[32] , GIN[40] , PHI , POUT[24] , GOUT[40] );
BLOCK2 U341 (PIN[25] , PIN[33] , GIN[33] , GIN[41] , PHI , POUT[25] , GOUT[41] );
BLOCK2 U342 (PIN[26] , PIN[34] , GIN[34] , GIN[42] , PHI , POUT[26] , GOUT[42] );
BLOCK2 U343 (PIN[27] , PIN[35] , GIN[35] , GIN[43] , PHI , POUT[27] , GOUT[43] );
BLOCK2 U344 (PIN[28] , PIN[36] , GIN[36] , GIN[44] , PHI , POUT[28] , GOUT[44] );
BLOCK2 U345 (PIN[29] , PIN[37] , GIN[37] , GIN[45] , PHI , POUT[29] , GOUT[45] );
BLOCK2 U346 (PIN[30] , PIN[38] , GIN[38] , GIN[46] , PHI , POUT[30] , GOUT[46] );
BLOCK2 U347 (PIN[31] , PIN[39] , GIN[39] , GIN[47] , PHI , POUT[31] , GOUT[47] );
BLOCK2 U348 (PIN[32] , PIN[40] , GIN[40] , GIN[48] , PHI , POUT[32] , GOUT[48] );
BLOCK2 U349 (PIN[33] , PIN[41] , GIN[41] , GIN[49] , PHI , POUT[33] , GOUT[49] );
BLOCK2 U350 (PIN[34] , PIN[42] , GIN[42] , GIN[50] , PHI , POUT[34] , GOUT[50] );
BLOCK2 U351 (PIN[35] , PIN[43] , GIN[43] , GIN[51] , PHI , POUT[35] , GOUT[51] );
BLOCK2 U352 (PIN[36] , PIN[44] , GIN[44] , GIN[52] , PHI , POUT[36] , GOUT[52] );
BLOCK2 U353 (PIN[37] , PIN[45] , GIN[45] , GIN[53] , PHI , POUT[37] , GOUT[53] );
BLOCK2 U354 (PIN[38] , PIN[46] , GIN[46] , GIN[54] , PHI , POUT[38] , GOUT[54] );
BLOCK2 U355 (PIN[39] , PIN[47] , GIN[47] , GIN[55] , PHI , POUT[39] , GOUT[55] );
BLOCK2 U356 (PIN[40] , PIN[48] , GIN[48] , GIN[56] , PHI , POUT[40] , GOUT[56] );
BLOCK2 U357 (PIN[41] , PIN[49] , GIN[49] , GIN[57] , PHI , POUT[41] , GOUT[57] );
BLOCK2 U358 (PIN[42] , PIN[50] , GIN[50] , GIN[58] , PHI , POUT[42] , GOUT[58] );
BLOCK2 U359 (PIN[43] , PIN[51] , GIN[51] , GIN[59] , PHI , POUT[43] , GOUT[59] );
BLOCK2 U360 (PIN[44] , PIN[52] , GIN[52] , GIN[60] , PHI , POUT[44] , GOUT[60] );
BLOCK2 U361 (PIN[45] , PIN[53] , GIN[53] , GIN[61] , PHI , POUT[45] , GOUT[61] );
BLOCK2 U362 (PIN[46] , PIN[54] , GIN[54] , GIN[62] , PHI , POUT[46] , GOUT[62] );
BLOCK2 U363 (PIN[47] , PIN[55] , GIN[55] , GIN[63] , PHI , POUT[47] , GOUT[63] );
BLOCK2 U364 (PIN[48] , PIN[56] , GIN[56] , GIN[64] , PHI , POUT[48] , GOUT[64] );
endmodule
module DBLC_4_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:48] PIN;
input [0:64] GIN;
input PHI;
output [0:32] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
BLOCK1A U216 (PIN[0] , GIN[0] , GIN[16] , PHI , GOUT[16] );
BLOCK1A U217 (PIN[1] , GIN[1] , GIN[17] , PHI , GOUT[17] );
BLOCK1A U218 (PIN[2] , GIN[2] , GIN[18] , PHI , GOUT[18] );
BLOCK1A U219 (PIN[3] , GIN[3] , GIN[19] , PHI , GOUT[19] );
BLOCK1A U220 (PIN[4] , GIN[4] , GIN[20] , PHI , GOUT[20] );
BLOCK1A U221 (PIN[5] , GIN[5] , GIN[21] , PHI , GOUT[21] );
BLOCK1A U222 (PIN[6] , GIN[6] , GIN[22] , PHI , GOUT[22] );
BLOCK1A U223 (PIN[7] , GIN[7] , GIN[23] , PHI , GOUT[23] );
BLOCK1A U224 (PIN[8] , GIN[8] , GIN[24] , PHI , GOUT[24] );
BLOCK1A U225 (PIN[9] , GIN[9] , GIN[25] , PHI , GOUT[25] );
BLOCK1A U226 (PIN[10] , GIN[10] , GIN[26] , PHI , GOUT[26] );
BLOCK1A U227 (PIN[11] , GIN[11] , GIN[27] , PHI , GOUT[27] );
BLOCK1A U228 (PIN[12] , GIN[12] , GIN[28] , PHI , GOUT[28] );
BLOCK1A U229 (PIN[13] , GIN[13] , GIN[29] , PHI , GOUT[29] );
BLOCK1A U230 (PIN[14] , GIN[14] , GIN[30] , PHI , GOUT[30] );
BLOCK1A U231 (PIN[15] , GIN[15] , GIN[31] , PHI , GOUT[31] );
BLOCK1 U332 (PIN[0] , PIN[16] , GIN[16] , GIN[32] , PHI , POUT[0] , GOUT[32] );
BLOCK1 U333 (PIN[1] , PIN[17] , GIN[17] , GIN[33] , PHI , POUT[1] , GOUT[33] );
BLOCK1 U334 (PIN[2] , PIN[18] , GIN[18] , GIN[34] , PHI , POUT[2] , GOUT[34] );
BLOCK1 U335 (PIN[3] , PIN[19] , GIN[19] , GIN[35] , PHI , POUT[3] , GOUT[35] );
BLOCK1 U336 (PIN[4] , PIN[20] , GIN[20] , GIN[36] , PHI , POUT[4] , GOUT[36] );
BLOCK1 U337 (PIN[5] , PIN[21] , GIN[21] , GIN[37] , PHI , POUT[5] , GOUT[37] );
BLOCK1 U338 (PIN[6] , PIN[22] , GIN[22] , GIN[38] , PHI , POUT[6] , GOUT[38] );
BLOCK1 U339 (PIN[7] , PIN[23] , GIN[23] , GIN[39] , PHI , POUT[7] , GOUT[39] );
BLOCK1 U340 (PIN[8] , PIN[24] , GIN[24] , GIN[40] , PHI , POUT[8] , GOUT[40] );
BLOCK1 U341 (PIN[9] , PIN[25] , GIN[25] , GIN[41] , PHI , POUT[9] , GOUT[41] );
BLOCK1 U342 (PIN[10] , PIN[26] , GIN[26] , GIN[42] , PHI , POUT[10] , GOUT[42] );
BLOCK1 U343 (PIN[11] , PIN[27] , GIN[27] , GIN[43] , PHI , POUT[11] , GOUT[43] );
BLOCK1 U344 (PIN[12] , PIN[28] , GIN[28] , GIN[44] , PHI , POUT[12] , GOUT[44] );
BLOCK1 U345 (PIN[13] , PIN[29] , GIN[29] , GIN[45] , PHI , POUT[13] , GOUT[45] );
BLOCK1 U346 (PIN[14] , PIN[30] , GIN[30] , GIN[46] , PHI , POUT[14] , GOUT[46] );
BLOCK1 U347 (PIN[15] , PIN[31] , GIN[31] , GIN[47] , PHI , POUT[15] , GOUT[47] );
BLOCK1 U348 (PIN[16] , PIN[32] , GIN[32] , GIN[48] , PHI , POUT[16] , GOUT[48] );
BLOCK1 U349 (PIN[17] , PIN[33] , GIN[33] , GIN[49] , PHI , POUT[17] , GOUT[49] );
BLOCK1 U350 (PIN[18] , PIN[34] , GIN[34] , GIN[50] , PHI , POUT[18] , GOUT[50] );
BLOCK1 U351 (PIN[19] , PIN[35] , GIN[35] , GIN[51] , PHI , POUT[19] , GOUT[51] );
BLOCK1 U352 (PIN[20] , PIN[36] , GIN[36] , GIN[52] , PHI , POUT[20] , GOUT[52] );
BLOCK1 U353 (PIN[21] , PIN[37] , GIN[37] , GIN[53] , PHI , POUT[21] , GOUT[53] );
BLOCK1 U354 (PIN[22] , PIN[38] , GIN[38] , GIN[54] , PHI , POUT[22] , GOUT[54] );
BLOCK1 U355 (PIN[23] , PIN[39] , GIN[39] , GIN[55] , PHI , POUT[23] , GOUT[55] );
BLOCK1 U356 (PIN[24] , PIN[40] , GIN[40] , GIN[56] , PHI , POUT[24] , GOUT[56] );
BLOCK1 U357 (PIN[25] , PIN[41] , GIN[41] , GIN[57] , PHI , POUT[25] , GOUT[57] );
BLOCK1 U358 (PIN[26] , PIN[42] , GIN[42] , GIN[58] , PHI , POUT[26] , GOUT[58] );
BLOCK1 U359 (PIN[27] , PIN[43] , GIN[43] , GIN[59] , PHI , POUT[27] , GOUT[59] );
BLOCK1 U360 (PIN[28] , PIN[44] , GIN[44] , GIN[60] , PHI , POUT[28] , GOUT[60] );
BLOCK1 U361 (PIN[29] , PIN[45] , GIN[45] , GIN[61] , PHI , POUT[29] , GOUT[61] );
BLOCK1 U362 (PIN[30] , PIN[46] , GIN[46] , GIN[62] , PHI , POUT[30] , GOUT[62] );
BLOCK1 U363 (PIN[31] , PIN[47] , GIN[47] , GIN[63] , PHI , POUT[31] , GOUT[63] );
BLOCK1 U364 (PIN[32] , PIN[48] , GIN[48] , GIN[64] , PHI , POUT[32] , GOUT[64] );
endmodule
module DBLC_5_64 ( PIN, GIN, PHI, POUT, GOUT );
input [0:32] PIN;
input [0:64] GIN;
input PHI;
output [0:0] POUT;
output [0:64] GOUT;
INVBLOCK U10 (GIN[0] , PHI , GOUT[0] );
INVBLOCK U11 (GIN[1] , PHI , GOUT[1] );
INVBLOCK U12 (GIN[2] , PHI , GOUT[2] );
INVBLOCK U13 (GIN[3] , PHI , GOUT[3] );
INVBLOCK U14 (GIN[4] , PHI , GOUT[4] );
INVBLOCK U15 (GIN[5] , PHI , GOUT[5] );
INVBLOCK U16 (GIN[6] , PHI , GOUT[6] );
INVBLOCK U17 (GIN[7] , PHI , GOUT[7] );
INVBLOCK U18 (GIN[8] , PHI , GOUT[8] );
INVBLOCK U19 (GIN[9] , PHI , GOUT[9] );
INVBLOCK U110 (GIN[10] , PHI , GOUT[10] );
INVBLOCK U111 (GIN[11] , PHI , GOUT[11] );
INVBLOCK U112 (GIN[12] , PHI , GOUT[12] );
INVBLOCK U113 (GIN[13] , PHI , GOUT[13] );
INVBLOCK U114 (GIN[14] , PHI , GOUT[14] );
INVBLOCK U115 (GIN[15] , PHI , GOUT[15] );
INVBLOCK U116 (GIN[16] , PHI , GOUT[16] );
INVBLOCK U117 (GIN[17] , PHI , GOUT[17] );
INVBLOCK U118 (GIN[18] , PHI , GOUT[18] );
INVBLOCK U119 (GIN[19] , PHI , GOUT[19] );
INVBLOCK U120 (GIN[20] , PHI , GOUT[20] );
INVBLOCK U121 (GIN[21] , PHI , GOUT[21] );
INVBLOCK U122 (GIN[22] , PHI , GOUT[22] );
INVBLOCK U123 (GIN[23] , PHI , GOUT[23] );
INVBLOCK U124 (GIN[24] , PHI , GOUT[24] );
INVBLOCK U125 (GIN[25] , PHI , GOUT[25] );
INVBLOCK U126 (GIN[26] , PHI , GOUT[26] );
INVBLOCK U127 (GIN[27] , PHI , GOUT[27] );
INVBLOCK U128 (GIN[28] , PHI , GOUT[28] );
INVBLOCK U129 (GIN[29] , PHI , GOUT[29] );
INVBLOCK U130 (GIN[30] , PHI , GOUT[30] );
INVBLOCK U131 (GIN[31] , PHI , GOUT[31] );
BLOCK2A U232 (PIN[0] , GIN[0] , GIN[32] , PHI , GOUT[32] );
BLOCK2A U233 (PIN[1] , GIN[1] , GIN[33] , PHI , GOUT[33] );
BLOCK2A U234 (PIN[2] , GIN[2] , GIN[34] , PHI , GOUT[34] );
BLOCK2A U235 (PIN[3] , GIN[3] , GIN[35] , PHI , GOUT[35] );
BLOCK2A U236 (PIN[4] , GIN[4] , GIN[36] , PHI , GOUT[36] );
BLOCK2A U237 (PIN[5] , GIN[5] , GIN[37] , PHI , GOUT[37] );
BLOCK2A U238 (PIN[6] , GIN[6] , GIN[38] , PHI , GOUT[38] );
BLOCK2A U239 (PIN[7] , GIN[7] , GIN[39] , PHI , GOUT[39] );
BLOCK2A U240 (PIN[8] , GIN[8] , GIN[40] , PHI , GOUT[40] );
BLOCK2A U241 (PIN[9] , GIN[9] , GIN[41] , PHI , GOUT[41] );
BLOCK2A U242 (PIN[10] , GIN[10] , GIN[42] , PHI , GOUT[42] );
BLOCK2A U243 (PIN[11] , GIN[11] , GIN[43] , PHI , GOUT[43] );
BLOCK2A U244 (PIN[12] , GIN[12] , GIN[44] , PHI , GOUT[44] );
BLOCK2A U245 (PIN[13] , GIN[13] , GIN[45] , PHI , GOUT[45] );
BLOCK2A U246 (PIN[14] , GIN[14] , GIN[46] , PHI , GOUT[46] );
BLOCK2A U247 (PIN[15] , GIN[15] , GIN[47] , PHI , GOUT[47] );
BLOCK2A U248 (PIN[16] , GIN[16] , GIN[48] , PHI , GOUT[48] );
BLOCK2A U249 (PIN[17] , GIN[17] , GIN[49] , PHI , GOUT[49] );
BLOCK2A U250 (PIN[18] , GIN[18] , GIN[50] , PHI , GOUT[50] );
BLOCK2A U251 (PIN[19] , GIN[19] , GIN[51] , PHI , GOUT[51] );
BLOCK2A U252 (PIN[20] , GIN[20] , GIN[52] , PHI , GOUT[52] );
BLOCK2A U253 (PIN[21] , GIN[21] , GIN[53] , PHI , GOUT[53] );
BLOCK2A U254 (PIN[22] , GIN[22] , GIN[54] , PHI , GOUT[54] );
BLOCK2A U255 (PIN[23] , GIN[23] , GIN[55] , PHI , GOUT[55] );
BLOCK2A U256 (PIN[24] , GIN[24] , GIN[56] , PHI , GOUT[56] );
BLOCK2A U257 (PIN[25] , GIN[25] , GIN[57] , PHI , GOUT[57] );
BLOCK2A U258 (PIN[26] , GIN[26] , GIN[58] , PHI , GOUT[58] );
BLOCK2A U259 (PIN[27] , GIN[27] , GIN[59] , PHI , GOUT[59] );
BLOCK2A U260 (PIN[28] , GIN[28] , GIN[60] , PHI , GOUT[60] );
BLOCK2A U261 (PIN[29] , GIN[29] , GIN[61] , PHI , GOUT[61] );
BLOCK2A U262 (PIN[30] , GIN[30] , GIN[62] , PHI , GOUT[62] );
BLOCK2A U263 (PIN[31] , GIN[31] , GIN[63] , PHI , GOUT[63] );
BLOCK2 U364 (PIN[0] , PIN[32] , GIN[32] , GIN[64] , PHI , POUT[0] , GOUT[64] );
endmodule
module XORSTAGE_64 ( A, B, PBIT, PHI, CARRY, SUM, COUT );
input [0:63] A;
input [0:63] B;
input PBIT;
input PHI;
input [0:64] CARRY;
output [0:63] SUM;
output COUT;
XXOR1 U20 (A[0] , B[0] , CARRY[0] , PHI , SUM[0] );
XXOR1 U21 (A[1] , B[1] , CARRY[1] , PHI , SUM[1] );
XXOR1 U22 (A[2] , B[2] , CARRY[2] , PHI , SUM[2] );
XXOR1 U23 (A[3] , B[3] , CARRY[3] , PHI , SUM[3] );
XXOR1 U24 (A[4] , B[4] , CARRY[4] , PHI , SUM[4] );
XXOR1 U25 (A[5] , B[5] , CARRY[5] , PHI , SUM[5] );
XXOR1 U26 (A[6] , B[6] , CARRY[6] , PHI , SUM[6] );
XXOR1 U27 (A[7] , B[7] , CARRY[7] , PHI , SUM[7] );
XXOR1 U28 (A[8] , B[8] , CARRY[8] , PHI , SUM[8] );
XXOR1 U29 (A[9] , B[9] , CARRY[9] , PHI , SUM[9] );
XXOR1 U210 (A[10] , B[10] , CARRY[10] , PHI , SUM[10] );
XXOR1 U211 (A[11] , B[11] , CARRY[11] , PHI , SUM[11] );
XXOR1 U212 (A[12] , B[12] , CARRY[12] , PHI , SUM[12] );
XXOR1 U213 (A[13] , B[13] , CARRY[13] , PHI , SUM[13] );
XXOR1 U214 (A[14] , B[14] , CARRY[14] , PHI , SUM[14] );
XXOR1 U215 (A[15] , B[15] , CARRY[15] , PHI , SUM[15] );
XXOR1 U216 (A[16] , B[16] , CARRY[16] , PHI , SUM[16] );
XXOR1 U217 (A[17] , B[17] , CARRY[17] , PHI , SUM[17] );
XXOR1 U218 (A[18] , B[18] , CARRY[18] , PHI , SUM[18] );
XXOR1 U219 (A[19] , B[19] , CARRY[19] , PHI , SUM[19] );
XXOR1 U220 (A[20] , B[20] , CARRY[20] , PHI , SUM[20] );
XXOR1 U221 (A[21] , B[21] , CARRY[21] , PHI , SUM[21] );
XXOR1 U222 (A[22] , B[22] , CARRY[22] , PHI , SUM[22] );
XXOR1 U223 (A[23] , B[23] , CARRY[23] , PHI , SUM[23] );
XXOR1 U224 (A[24] , B[24] , CARRY[24] , PHI , SUM[24] );
XXOR1 U225 (A[25] , B[25] , CARRY[25] , PHI , SUM[25] );
XXOR1 U226 (A[26] , B[26] , CARRY[26] , PHI , SUM[26] );
XXOR1 U227 (A[27] , B[27] , CARRY[27] , PHI , SUM[27] );
XXOR1 U228 (A[28] , B[28] , CARRY[28] , PHI , SUM[28] );
XXOR1 U229 (A[29] , B[29] , CARRY[29] , PHI , SUM[29] );
XXOR1 U230 (A[30] , B[30] , CARRY[30] , PHI , SUM[30] );
XXOR1 U231 (A[31] , B[31] , CARRY[31] , PHI , SUM[31] );
XXOR1 U232 (A[32] , B[32] , CARRY[32] , PHI , SUM[32] );
XXOR1 U233 (A[33] , B[33] , CARRY[33] , PHI , SUM[33] );
XXOR1 U234 (A[34] , B[34] , CARRY[34] , PHI , SUM[34] );
XXOR1 U235 (A[35] , B[35] , CARRY[35] , PHI , SUM[35] );
XXOR1 U236 (A[36] , B[36] , CARRY[36] , PHI , SUM[36] );
XXOR1 U237 (A[37] , B[37] , CARRY[37] , PHI , SUM[37] );
XXOR1 U238 (A[38] , B[38] , CARRY[38] , PHI , SUM[38] );
XXOR1 U239 (A[39] , B[39] , CARRY[39] , PHI , SUM[39] );
XXOR1 U240 (A[40] , B[40] , CARRY[40] , PHI , SUM[40] );
XXOR1 U241 (A[41] , B[41] , CARRY[41] , PHI , SUM[41] );
XXOR1 U242 (A[42] , B[42] , CARRY[42] , PHI , SUM[42] );
XXOR1 U243 (A[43] , B[43] , CARRY[43] , PHI , SUM[43] );
XXOR1 U244 (A[44] , B[44] , CARRY[44] , PHI , SUM[44] );
XXOR1 U245 (A[45] , B[45] , CARRY[45] , PHI , SUM[45] );
XXOR1 U246 (A[46] , B[46] , CARRY[46] , PHI , SUM[46] );
XXOR1 U247 (A[47] , B[47] , CARRY[47] , PHI , SUM[47] );
XXOR1 U248 (A[48] , B[48] , CARRY[48] , PHI , SUM[48] );
XXOR1 U249 (A[49] , B[49] , CARRY[49] , PHI , SUM[49] );
XXOR1 U250 (A[50] , B[50] , CARRY[50] , PHI , SUM[50] );
XXOR1 U251 (A[51] , B[51] , CARRY[51] , PHI , SUM[51] );
XXOR1 U252 (A[52] , B[52] , CARRY[52] , PHI , SUM[52] );
XXOR1 U253 (A[53] , B[53] , CARRY[53] , PHI , SUM[53] );
XXOR1 U254 (A[54] , B[54] , CARRY[54] , PHI , SUM[54] );
XXOR1 U255 (A[55] , B[55] , CARRY[55] , PHI , SUM[55] );
XXOR1 U256 (A[56] , B[56] , CARRY[56] , PHI , SUM[56] );
XXOR1 U257 (A[57] , B[57] , CARRY[57] , PHI , SUM[57] );
XXOR1 U258 (A[58] , B[58] , CARRY[58] , PHI , SUM[58] );
XXOR1 U259 (A[59] , B[59] , CARRY[59] , PHI , SUM[59] );
XXOR1 U260 (A[60] , B[60] , CARRY[60] , PHI , SUM[60] );
XXOR1 U261 (A[61] , B[61] , CARRY[61] , PHI , SUM[61] );
XXOR1 U262 (A[62] , B[62] , CARRY[62] , PHI , SUM[62] );
XXOR1 U263 (A[63] , B[63] , CARRY[63] , PHI , SUM[63] );
BLOCK1A U1 (PBIT , CARRY[0] , CARRY[64] , PHI , COUT );
endmodule
module DBLCTREE_64 ( PIN, GIN, PHI, GOUT, POUT );
input [0:63] PIN;
input [0:64] GIN;
input PHI;
output [0:64] GOUT;
output [0:0] POUT;
wire [0:62] INTPROP_0;
wire [0:64] INTGEN_0;
wire [0:60] INTPROP_1;
wire [0:64] INTGEN_1;
wire [0:56] INTPROP_2;
wire [0:64] INTGEN_2;
wire [0:48] INTPROP_3;
wire [0:64] INTGEN_3;
wire [0:32] INTPROP_4;
wire [0:64] INTGEN_4;
DBLC_0_64 U_0 (.PIN(PIN) , .GIN(GIN) , .PHI(PHI) , .POUT(INTPROP_0) , .GOUT(INTGEN_0) );
DBLC_1_64 U_1 (.PIN(INTPROP_0) , .GIN(INTGEN_0) , .PHI(PHI) , .POUT(INTPROP_1) , .GOUT(INTGEN_1) );
DBLC_2_64 U_2 (.PIN(INTPROP_1) , .GIN(INTGEN_1) , .PHI(PHI) , .POUT(INTPROP_2) , .GOUT(INTGEN_2) );
DBLC_3_64 U_3 (.PIN(INTPROP_2) , .GIN(INTGEN_2) , .PHI(PHI) , .POUT(INTPROP_3) , .GOUT(INTGEN_3) );
DBLC_4_64 U_4 (.PIN(INTPROP_3) , .GIN(INTGEN_3) , .PHI(PHI) , .POUT(INTPROP_4) , .GOUT(INTGEN_4) );
DBLC_5_64 U_5 (.PIN(INTPROP_4) , .GIN(INTGEN_4) , .PHI(PHI) , .POUT(POUT) , .GOUT(GOUT) );
endmodule
module DBLCADDER_64_64 ( OPA, OPB, CIN, PHI, SUM, COUT );
input [0:63] OPA;
input [0:63] OPB;
input CIN;
input PHI;
output [0:63] SUM;
output COUT;
wire [0:63] INTPROP;
wire [0:64] INTGEN;
wire [0:0] PBIT;
wire [0:64] CARRY;
PRESTAGE_64 U1 (OPA , OPB , CIN , PHI , INTPROP , INTGEN );
DBLCTREE_64 U2 (INTPROP , INTGEN , PHI , CARRY , PBIT );
XORSTAGE_64 U3 (OPA[0:63] , OPB[0:63] , PBIT[0] , PHI , CARRY[0:64] , SUM , COUT );
endmodule
module MULTIPLIER_33_32 ( MULTIPLICAND, MULTIPLIER, RST, CLK, PHI, RESULT );
input [0:32] MULTIPLICAND;
input [0:31] MULTIPLIER;
input RST;
input CLK;
input PHI;
output [0:63] RESULT;
wire [0:575] PPBIT;
wire [0:64] INT_CARRY;
wire [0:63] INT_SUM;
wire LOGIC_ZERO;
wire [0:63] ARESULT;
reg [0:63] RESULT;
assign LOGIC_ZERO = 0;
BOOTHCODER_33_32 B (.OPA(MULTIPLICAND[0:32]) , .OPB(MULTIPLIER[0:31]) , .SUMMAND(PPBIT[0:575]) );
WALLACE_33_32 W (.SUMMAND(PPBIT[0:575]) , .RST(RST), .CLK (CLK) , .CARRY(INT_CARRY[1:63]) , .SUM(INT_SUM[0:63]) );
assign INT_CARRY[0] = LOGIC_ZERO;
DBLCADDER_64_64 D (.OPA(INT_SUM[0:63]) , .OPB(INT_CARRY[0:63]) , .CIN (LOGIC_ZERO) , .PHI (PHI) , .SUM(ARESULT[0:63]), .COUT() );
always @(posedge CLK or posedge RST)
if (RST)
RESULT <= 64'h0000_0000_0000_0000;
else
RESULT <= ARESULT;
endmodule
// 32x32 multiplier, no input/output registers
// Registers inside Wallace trees every 8 full adder levels,
// with first pipeline after level 4
module amultp2_32x32 ( X, Y, RST, CLK, P );
input [31:0] X;
input [31:0] Y;
input RST;
input CLK;
output [63:0] P;
wire [0:32] A;
wire [0:31] B;
wire [0:63] Q;
assign A[0] = X[0];
assign A[1] = X[1];
assign A[2] = X[2];
assign A[3] = X[3];
assign A[4] = X[4];
assign A[5] = X[5];
assign A[6] = X[6];
assign A[7] = X[7];
assign A[8] = X[8];
assign A[9] = X[9];
assign A[10] = X[10];
assign A[11] = X[11];
assign A[12] = X[12];
assign A[13] = X[13];
assign A[14] = X[14];
assign A[15] = X[15];
assign A[16] = X[16];
assign A[17] = X[17];
assign A[18] = X[18];
assign A[19] = X[19];
assign A[20] = X[20];
assign A[21] = X[21];
assign A[22] = X[22];
assign A[23] = X[23];
assign A[24] = X[24];
assign A[25] = X[25];
assign A[26] = X[26];
assign A[27] = X[27];
assign A[28] = X[28];
assign A[29] = X[29];
assign A[30] = X[30];
assign A[31] = X[31];
assign A[32] = X[31];
assign B[0] = Y[0];
assign B[1] = Y[1];
assign B[2] = Y[2];
assign B[3] = Y[3];
assign B[4] = Y[4];
assign B[5] = Y[5];
assign B[6] = Y[6];
assign B[7] = Y[7];
assign B[8] = Y[8];
assign B[9] = Y[9];
assign B[10] = Y[10];
assign B[11] = Y[11];
assign B[12] = Y[12];
assign B[13] = Y[13];
assign B[14] = Y[14];
assign B[15] = Y[15];
assign B[16] = Y[16];
assign B[17] = Y[17];
assign B[18] = Y[18];
assign B[19] = Y[19];
assign B[20] = Y[20];
assign B[21] = Y[21];
assign B[22] = Y[22];
assign B[23] = Y[23];
assign B[24] = Y[24];
assign B[25] = Y[25];
assign B[26] = Y[26];
assign B[27] = Y[27];
assign B[28] = Y[28];
assign B[29] = Y[29];
assign B[30] = Y[30];
assign B[31] = Y[31];
assign P[0] = Q[0];
assign P[1] = Q[1];
assign P[2] = Q[2];
assign P[3] = Q[3];
assign P[4] = Q[4];
assign P[5] = Q[5];
assign P[6] = Q[6];
assign P[7] = Q[7];
assign P[8] = Q[8];
assign P[9] = Q[9];
assign P[10] = Q[10];
assign P[11] = Q[11];
assign P[12] = Q[12];
assign P[13] = Q[13];
assign P[14] = Q[14];
assign P[15] = Q[15];
assign P[16] = Q[16];
assign P[17] = Q[17];
assign P[18] = Q[18];
assign P[19] = Q[19];
assign P[20] = Q[20];
assign P[21] = Q[21];
assign P[22] = Q[22];
assign P[23] = Q[23];
assign P[24] = Q[24];
assign P[25] = Q[25];
assign P[26] = Q[26];
assign P[27] = Q[27];
assign P[28] = Q[28];
assign P[29] = Q[29];
assign P[30] = Q[30];
assign P[31] = Q[31];
assign P[32] = Q[32];
assign P[33] = Q[33];
assign P[34] = Q[34];
assign P[35] = Q[35];
assign P[36] = Q[36];
assign P[37] = Q[37];
assign P[38] = Q[38];
assign P[39] = Q[39];
assign P[40] = Q[40];
assign P[41] = Q[41];
assign P[42] = Q[42];
assign P[43] = Q[43];
assign P[44] = Q[44];
assign P[45] = Q[45];
assign P[46] = Q[46];
assign P[47] = Q[47];
assign P[48] = Q[48];
assign P[49] = Q[49];
assign P[50] = Q[50];
assign P[51] = Q[51];
assign P[52] = Q[52];
assign P[53] = Q[53];
assign P[54] = Q[54];
assign P[55] = Q[55];
assign P[56] = Q[56];
assign P[57] = Q[57];
assign P[58] = Q[58];
assign P[59] = Q[59];
assign P[60] = Q[60];
assign P[61] = Q[61];
assign P[62] = Q[62];
assign P[63] = Q[63];
MULTIPLIER_33_32 U1 (.MULTIPLICAND(A) , .MULTIPLIER(B) , .RST(RST), .CLK(CLK) , .PHI(1'b0) , .RESULT(Q) );
endmodule
|
module main;
reg [2:0] Q;
reg clk, clr, up, down;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
down = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
up = 0;
down = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
down = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP/DOWN counter. The up
* and down cases are enabled by up and down signals. If both
* signals are absent, the synthesizer should take the implicit
* case that Q <= Q;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr)
if (clr) begin
Q <= 0;
end else begin
if (up)
Q <= Q + 1;
else if (down)
Q <= Q - 1;
end
endmodule // main
|
/*
* Copyright (c) 2015-2018 The Ultiparc Project. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Behavioral memory model
*/
`include "common.vh"
`include "ocp_const.vh"
/*
* RAM
*/
module memory #(
parameter MEMWORDS = 1048576 /* Memory size (number of data words) */
)
(
clk,
nrst,
/* OCP interface */
i_MAddr,
i_MCmd,
i_MData,
i_MByteEn,
o_SCmdAccept,
o_SData,
o_SResp
);
/* Inputs and outputs */
input wire clk;
input wire nrst;
input wire [`ADDR_WIDTH-1:0] i_MAddr;
input wire [2:0] i_MCmd;
input wire [`DATA_WIDTH-1:0] i_MData;
input wire [`BEN_WIDTH-1:0] i_MByteEn;
output wire o_SCmdAccept;
output reg [`DATA_WIDTH-1:0] o_SData;
output reg [1:0] o_SResp;
/* RAM */
reg [`DATA_WIDTH-1:0] mem[0:MEMWORDS-1];
integer i;
/* Preinit memory */
initial
begin : memory_init
`ifndef VERILATOR
reg [65536*8-1:0] filepath;
`else
reg [256*8-1:0] filepath;
/** Verilator limits string length to 64 words (256*8/32 = 64) **/
`endif
for(i=0; i<MEMWORDS; i=i+1) begin
mem[i] = 0;
end
if($value$plusargs("MEMORY_FILE=%s", filepath))
begin
$readmemh(filepath, mem);
end
else
begin
`ifdef MEMORY_IMAGE
$readmemh(`MEMORY_IMAGE, mem);
`endif
end
end
assign o_SCmdAccept = 1'b1; /* Always accept command */
/* Bus logic */
always @(posedge clk or negedge nrst)
begin
if(!nrst)
begin
o_SData <= { (`DATA_WIDTH){1'b0} };
o_SResp <= `OCP_RESP_NULL;
end
else
begin
/* verilator lint_off WIDTH */
case(i_MCmd)
`OCP_CMD_WRITE: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
if(i_MByteEn[0]) mem[i_MAddr[`ADDR_WIDTH-1:2]][7:0] <= i_MData[7:0];
if(i_MByteEn[1]) mem[i_MAddr[`ADDR_WIDTH-1:2]][15:8] <= i_MData[15:8];
if(i_MByteEn[2]) mem[i_MAddr[`ADDR_WIDTH-1:2]][23:16] <= i_MData[23:16];
if(i_MByteEn[3]) mem[i_MAddr[`ADDR_WIDTH-1:2]][31:24] <= i_MData[31:24];
/* Note: Need to be modified if DATA_WIDTH/BEN_WIDTH changed. */
end
o_SResp <= `OCP_RESP_DVA;
end
`OCP_CMD_READ: begin
if(i_MAddr[`ADDR_WIDTH-1:2] < MEMWORDS)
begin
o_SData <= mem[i_MAddr[`ADDR_WIDTH-1:2]];
end
else
o_SData <= 32'hDEADDEAD;
o_SResp <= `OCP_RESP_DVA;
end
default: begin
o_SResp <= `OCP_RESP_NULL;
end
endcase
/* verilator lint_on WIDTH */
end
end
endmodule /* memory */
|
///////////////////////////////////////////////////////////////////////////////
//
// Project: Aurora 64B/66B
// Company: Xilinx
//
//
//
// (c) Copyright 2008 - 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//
////////////////////////////////////////////////////////////////////////////////
// Design Name: aurora_64b66b_0_gt_common_wrapper
//
// Module aurora_64b66b_0_gt_common_wrapper
`timescale 1ns / 1ps
(* core_generation_info = "aurora_64b66b_0,aurora_64b66b_v11_1_3,{c_aurora_lanes=1,c_column_used=left,c_gt_clock_1=GTXQ0,c_gt_clock_2=None,c_gt_loc_1=1,c_gt_loc_10=X,c_gt_loc_11=X,c_gt_loc_12=X,c_gt_loc_13=X,c_gt_loc_14=X,c_gt_loc_15=X,c_gt_loc_16=X,c_gt_loc_17=X,c_gt_loc_18=X,c_gt_loc_19=X,c_gt_loc_2=X,c_gt_loc_20=X,c_gt_loc_21=X,c_gt_loc_22=X,c_gt_loc_23=X,c_gt_loc_24=X,c_gt_loc_25=X,c_gt_loc_26=X,c_gt_loc_27=X,c_gt_loc_28=X,c_gt_loc_29=X,c_gt_loc_3=X,c_gt_loc_30=X,c_gt_loc_31=X,c_gt_loc_32=X,c_gt_loc_33=X,c_gt_loc_34=X,c_gt_loc_35=X,c_gt_loc_36=X,c_gt_loc_37=X,c_gt_loc_38=X,c_gt_loc_39=X,c_gt_loc_4=X,c_gt_loc_40=X,c_gt_loc_41=X,c_gt_loc_42=X,c_gt_loc_43=X,c_gt_loc_44=X,c_gt_loc_45=X,c_gt_loc_46=X,c_gt_loc_47=X,c_gt_loc_48=X,c_gt_loc_5=X,c_gt_loc_6=X,c_gt_loc_7=X,c_gt_loc_8=X,c_gt_loc_9=X,c_lane_width=4,c_line_rate=3.125,c_gt_type=gtx,c_qpll=false,c_nfc=false,c_nfc_mode=IMM,c_refclk_frequency=125.0,c_simplex=false,c_simplex_mode=TX,c_stream=true,c_ufc=true,c_user_k=false,flow_mode=UFC,interface_mode=Streaming,dataflow_config=Duplex}" *)
(* DowngradeIPIdentifiedWarnings="yes" *)
module aurora_64b66b_0_gt_common_wrapper
(
output gt_qpllclk_quad1_out,
output gt_qpllrefclk_quad1_out,
input GT0_GTREFCLK0_COMMON_IN,
//----------------------- Common Block - QPLL Ports ------------------------
output GT0_QPLLLOCK_OUT,
input GT0_QPLLLOCKDETCLK_IN,
output GT0_QPLLREFCLKLOST_OUT,
//----------------------- Common Block - DRP Ports ------------------------
input [7:0] qpll_drpaddr_in,
input [15:0] qpll_drpdi_in,
input qpll_drpclk_in,
input qpll_drpen_in,
input qpll_drpwe_in,
output [15:0] qpll_drpdo_out,
output qpll_drprdy_out
);
parameter WRAPPER_SIM_GTRESET_SPEEDUP = "TRUE"; // Set to "TRUE" to speed up sim reset
//***************************** Wire Declarations *****************************
wire tied_to_ground_i;
wire [63:0] tied_to_ground_vec_i;
wire tied_to_vcc_i;
//------------------------- Static signal Assigments ---------------------
assign tied_to_ground_i = 1'b0;
assign tied_to_ground_vec_i = 64'h0000000000000000;
assign tied_to_vcc_i = 1'b1;
//_________________________________________________________________________
//_________________________GTXE2_COMMON____________________________________
//_________________________________________________________________________
GTXE2_COMMON #
(
// Simulation attributes
.SIM_RESET_SPEEDUP (WRAPPER_SIM_GTRESET_SPEEDUP),
.SIM_QPLLREFCLK_SEL (3'b001),
.SIM_VERSION ("4.0"),
//----------------COMMON BLOCK---------------
.BIAS_CFG (64'h0000040000001000),
.COMMON_CFG (32'h00000000),
.QPLL_CFG (27'h06801C1),
.QPLL_CLKOUT_CFG (4'b0000),
.QPLL_COARSE_FREQ_OVRD (6'b010000),
.QPLL_COARSE_FREQ_OVRD_EN (1'b0),
.QPLL_CP (10'b0000011111),
.QPLL_CP_MONITOR_EN (1'b0),
.QPLL_DMONITOR_SEL (1'b0),
.QPLL_FBDIV (10'b0000100000),
.QPLL_FBDIV_MONITOR_EN (1'b0),
.QPLL_FBDIV_RATIO (1'b1),
.QPLL_INIT_CFG (24'h000006),
.QPLL_LOCK_CFG (16'h21E8),
.QPLL_LPF (4'b1111),
.QPLL_REFCLK_DIV (1)
)
gtxe2_common_i
(
//--------- Common Block - Dynamic Reconfiguration Port (DRP) -----------
.DRPADDR (qpll_drpaddr_in),
.DRPCLK (qpll_drpclk_in),
.DRPDI (qpll_drpdi_in),
.DRPDO (qpll_drpdo_out),
.DRPEN (qpll_drpen_in),
.DRPRDY (qpll_drprdy_out),
.DRPWE (qpll_drpwe_in),
//-------------------- Common Block - Ref Clock Ports ---------------------
.GTGREFCLK (tied_to_ground_i),
.GTNORTHREFCLK0 (tied_to_ground_i),
.GTNORTHREFCLK1 (tied_to_ground_i),
.GTREFCLK0 (GT0_GTREFCLK0_COMMON_IN),
.GTREFCLK1 (tied_to_ground_i),
.GTSOUTHREFCLK0 (tied_to_ground_i),
.GTSOUTHREFCLK1 (tied_to_ground_i),
//----------------------- Common Block - QPLL Ports ------------------------
.QPLLFBCLKLOST (),
.QPLLLOCK (GT0_QPLLLOCK_OUT),
.QPLLLOCKDETCLK (GT0_QPLLLOCKDETCLK_IN),
.QPLLLOCKEN (tied_to_vcc_i),
.QPLLOUTCLK (gt_qpllclk_quad1_out),
.QPLLOUTREFCLK (gt_qpllrefclk_quad1_out),
.QPLLOUTRESET (tied_to_ground_i),
.QPLLPD (tied_to_vcc_i),
.QPLLREFCLKLOST (GT0_QPLLREFCLKLOST_OUT),
.QPLLREFCLKSEL (3'b001),
.QPLLRESET (tied_to_ground_i),
.QPLLRSVD1 (16'b0000000000000000),
.QPLLRSVD2 (5'b11111),
.RCALENB (tied_to_vcc_i),
.REFCLKOUTMONITOR (),
//--------------------------- Common Block Ports ---------------------------
.BGBYPASSB (tied_to_vcc_i),
.BGMONITORENB (tied_to_vcc_i),
.BGPDB (tied_to_vcc_i),
.BGRCALOVRD (5'b11111),
.PMARSVD (8'b00000000),
.QPLLDMONITOR ()
);
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 01:33:05 12/07/2015
// Design Name:
// Module Name: Peripheral_clk_interruptor
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Peripheral_clk_interruptor(
input clk,
input rst,
input [15:0] d_in,
input cs,
input [3:0] addr,
input rd,
input wr,
output reg [15:0] d_out
);
//--------------------------------------
reg [5:0] s; //selector mux_4 and write registers
reg [31:0] limit;
reg [31:0] count;
reg en=0;
wire int_0;
wire done;
//----------------------------------------
always @(*) begin
case (addr)
4'h0:begin s = (cs && wr) ? 6'b000001 : 6'b000000 ;end //limit
4'h2:begin s = (cs && wr) ? 6'b000010 : 6'b000000 ;end //count
4'h4:begin s = (cs && wr) ? 6'b000100 : 6'b000000 ;end //init
4'h6:begin s = (cs && rd) ? 6'b001000 : 6'b000000 ;end //done
4'h8:begin s = (cs && rd) ? 6'b010000 : 6'b000000 ;end //clk_0
default:begin s = 6'b000000 ; end
endcase
end
//----------------------------------------
always @(negedge clk) begin
limit = (s[0]) ? d_in : limit; //Write Registers
count = (s[1]) ? d_in : count; //Write Registers
en = s[2] ; // (s[2]) ? d_in : init; //Write Registers
end
//----------------------------------------
always @(negedge clk) begin
case (s[5:3])
3'b001: d_out[0] = done ;
3'b010: d_out = int_0 ;
default: d_out = 0 ;
endcase
end//-----------------------------------------------mux_4
//----------------------------------------
clk_interruptor c_i ( .clk(clk), .rst(rst), .limit(limit), .count(count), .en(en), .int_0(int_0), .done(done) );
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc=1;
reg [31:0] a, b, c, d, e, f, g, h;
always @ (*) begin // Test Verilog 2001 (*)
// verilator lint_off COMBDLY
c <= a | b;
// verilator lint_on COMBDLY
end
always @ (posedge (clk)) begin // always bug 2008/4/18
d <= a | b;
end
always @ ((d)) begin // always bug 2008/4/18
e = d;
end
parameter CONSTANT = 1;
always @ (e, 1'b0, CONSTANT) begin // not technically legal, see bug412
f = e;
end
always @ (1'b0, CONSTANT, f) begin // not technically legal, see bug412
g = f;
end
always @ ({CONSTANT, g}) begin // bug745
h = g;
end
//always @ ((posedge b) or (a or b)) begin // note both illegal
always @ (posedge clk) begin
if (cyc!=0) begin
cyc<=cyc+1;
if (cyc==1) begin
a <= 32'hfeed0000;
b <= 32'h0000face;
end
if (cyc==2) begin
if (c != 32'hfeedface) $stop;
end
if (cyc==3) begin
if (h != 32'hfeedface) $stop;
end
if (cyc==7) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V
/**
* dfxtp: Delay flop, single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxtp (
Q ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q ;
reg notifier ;
wire D_delayed ;
wire CLK_delayed;
wire awake ;
// Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N dff0 (buf_Q , D_delayed, CLK_delayed, notifier, VPWR, VGND);
assign awake = ( VPWR === 1'b1 );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXTP_BEHAVIORAL_PP_V |
module scoreboard
(/*AUTOARG*/
// Outputs
lsu_source_reg1, lsu_source_reg2, lsu_source_reg3, lsu_dest_reg,
lsu_mem_sgpr, alu_source_reg1, alu_source_reg2, alu_source_reg3,
alu_dest_reg1, alu_dest_reg2, lsu_imm_value0, alu_imm_value0,
lsu_lds_base, lsu_imm_value1, lsu_opcode, alu_imm_value1,
alu_opcode, alu_instr_pc, lsu_instr_pc,
ready_array_data_dependencies, alu_branch,
// Inputs
clk, rst, f_decode_source_reg2, f_decode_source_reg3,
f_decode_dest_reg2, f_decode_source_reg1, f_decode_source_reg4,
f_decode_dest_reg1, f_decode_imm_value0, f_decode_lds_base,
f_decode_instr_pc, f_decode_opcode, f_decode_imm_value1,
f_decode_vcc_wr, f_decode_vcc_rd, f_decode_scc_wr, f_decode_scc_rd,
f_decode_exec_rd, f_decode_exec_wr, f_decode_m0_rd, f_decode_m0_wr,
f_decode_branch, f_decode_valid, issued_wfid, f_decode_wfid,
f_vgpr_alu_wr_done_wfid, f_vgpr_lsu_wr_done_wfid,
f_sgpr_alu_wr_done_wfid, f_sgpr_lsu_instr_done_wfid,
f_exec_salu_wr_wfid, f_exec_valu_wr_vcc_wfid,
f_exec_salu_wr_vcc_en, f_exec_salu_wr_exec_en,
f_exec_salu_wr_scc_en, f_exec_salu_wr_m0_en, f_exec_valu_wr_vcc_en,
f_sgpr_alu_dest_reg_addr, f_sgpr_lsu_dest_reg_addr,
f_sgpr_valu_dest_addr, f_vgpr_alu_dest_reg_addr,
f_vgpr_lsu_dest_reg_addr, f_vgpr_lsu_dest_reg_valid,
f_sgpr_lsu_dest_reg_valid, f_sgpr_alu_dest_reg_valid,
f_vgpr_alu_dest_reg_valid, f_sgpr_valu_dest_reg_valid, alu_valid,
lsu_valid, issued_valid
);
input clk, rst;
input[`OPERAND_LENGTH_2WORD-1:0] f_decode_source_reg2, f_decode_source_reg3,
f_decode_dest_reg2;
input [`OPERAND_LENGTH_4WORD-1:0] f_decode_source_reg1, f_decode_source_reg4,
f_decode_dest_reg1;
input [15:0] f_decode_imm_value0, f_decode_lds_base;
input [31:0] f_decode_instr_pc, f_decode_opcode, f_decode_imm_value1;
input f_decode_vcc_wr, f_decode_vcc_rd, f_decode_scc_wr,
f_decode_scc_rd, f_decode_exec_rd, f_decode_exec_wr,
f_decode_m0_rd, f_decode_m0_wr,
f_decode_branch, f_decode_valid;
input [`WF_ID_LENGTH-1:0] issued_wfid;
input [`WF_ID_LENGTH-1:0] f_decode_wfid, f_vgpr_alu_wr_done_wfid,
f_vgpr_lsu_wr_done_wfid, f_sgpr_alu_wr_done_wfid,
f_sgpr_lsu_instr_done_wfid, f_exec_salu_wr_wfid,
f_exec_valu_wr_vcc_wfid;
input f_exec_salu_wr_vcc_en, f_exec_salu_wr_exec_en, f_exec_salu_wr_scc_en,
f_exec_salu_wr_m0_en, f_exec_valu_wr_vcc_en;
input [`SGPR_ADDR_LENGTH-1:0] f_sgpr_alu_dest_reg_addr, f_sgpr_lsu_dest_reg_addr,
f_sgpr_valu_dest_addr;
input [`VGPR_ADDR_LENGTH-1:0] f_vgpr_alu_dest_reg_addr, f_vgpr_lsu_dest_reg_addr;
input [3:0] f_vgpr_lsu_dest_reg_valid, f_sgpr_lsu_dest_reg_valid;
input [1:0] f_sgpr_alu_dest_reg_valid;
input f_vgpr_alu_dest_reg_valid, f_sgpr_valu_dest_reg_valid;
input alu_valid, lsu_valid, issued_valid;
output [11:0] lsu_source_reg1, lsu_source_reg2, lsu_source_reg3,
lsu_dest_reg, lsu_mem_sgpr,
alu_source_reg1, alu_source_reg2, alu_source_reg3,
alu_dest_reg1, alu_dest_reg2;
output [15:0] lsu_imm_value0, alu_imm_value0, lsu_lds_base;
output [31:0] lsu_imm_value1, lsu_opcode, alu_imm_value1, alu_opcode,
alu_instr_pc, lsu_instr_pc;
output [`WF_PER_CU-1:0] ready_array_data_dependencies;
output alu_branch;
wire [`ISSUE_INSTR_INFO_LENGTH-1:0] sgpr_alu_rd_data, sgpr_lsu_rd_data,
vgpr_alu_rd_data, vgpr_lsu_rd_data;
wire [`ISSUE_INSTR_INFO_LENGTH-1:0] issued_rd_data;
wire [`WF_PER_CU-1:0] ready_arry_gpr, ready_arry_spr;
wire [3:0] decode_dest_reg1_busy_bits,
decode_source_reg1_busy_bits,
decode_source_reg4_busy_bits;
wire [1:0] decode_dest_reg2_busy_bits,
decode_source_reg2_busy_bits,
decode_source_reg3_busy_bits;
wire [`ISSUE_GPR_RD_BITS_LENGTH-1:0] sgpr_valu_set_data,
sgpr_alu_set_data, sgpr_lsu_set_data,
vgpr_alu_set_data, vgpr_lsu_set_data;
wire issue_alu_exec_wr, issue_alu_m0_wr,
issue_alu_scc_wr, issue_alu_vcc_wr,
issue_lsu_exec_wr, issue_lsu_m0_wr,
issue_lsu_scc_wr, issue_lsu_vcc_wr;
wire [`ISSUE_INSTR_INFO_LENGTH-1:0] decode_wr_data;
wire [`ISSUE_GPR_RD_BITS_LENGTH-1:0] decode_instr_data;
wire [11:0] lsu_source_reg1, lsu_source_reg2, lsu_source_reg3,
lsu_dest_reg, lsu_mem_sgpr,
alu_source_reg1, alu_source_reg2, alu_source_reg3,
alu_dest_reg1, alu_dest_reg2;
wire [15:0] lsu_imm_value0, alu_imm_value0;
wire [31:0] lsu_imm_value1, lsu_opcode, alu_imm_value1, alu_opcode,
alu_instr_pc, lsu_instr_pc;
wire [1:0] lsu_dest_reg_size;
wire alu_dest_reg1_size, alu_dest_reg2_size;
instr_info_table iit
(/*AUTOINST*/
// Outputs
.vgpr_alu_rd_data (vgpr_alu_rd_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
.vgpr_lsu_rd_data (vgpr_lsu_rd_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
.sgpr_alu_rd_data (sgpr_alu_rd_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
.sgpr_lsu_rd_data (sgpr_lsu_rd_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
.issued_rd_data (issued_rd_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
// Inputs
.f_decode_valid (f_decode_valid),
.clk (clk),
.rst (rst),
.f_decode_wfid (f_decode_wfid[`WF_ID_LENGTH-1:0]),
.decode_wr_data (decode_wr_data[`ISSUE_INSTR_INFO_LENGTH-1:0]),
.f_vgpr_alu_wr_done_wfid (f_vgpr_alu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_vgpr_lsu_wr_done_wfid (f_vgpr_lsu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_sgpr_alu_wr_done_wfid (f_sgpr_alu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_sgpr_lsu_instr_done_wfid (f_sgpr_lsu_instr_done_wfid[`WF_ID_LENGTH-1:0]),
.issued_wfid (issued_wfid[`WF_ID_LENGTH-1:0]));
assign decode_wr_data
= {f_decode_lds_base, f_decode_branch,
f_decode_vcc_wr,f_decode_scc_wr,
f_decode_exec_wr,f_decode_m0_wr,
f_decode_instr_pc,f_decode_opcode,
f_decode_imm_value0,f_decode_imm_value1,
f_decode_source_reg1,f_decode_source_reg2,
f_decode_source_reg3,f_decode_source_reg4,
f_decode_dest_reg1,f_decode_dest_reg2};
assign lsu_lds_base = issued_rd_data[`ISSUE_LDS_BASE_H:`ISSUE_LDS_BASE_L];
assign lsu_opcode = issued_rd_data[`ISSUE_OP_H:`ISSUE_OP_L];
assign lsu_instr_pc = issued_rd_data[`ISSUE_PC_H:`ISSUE_PC_L];
assign lsu_imm_value0 = issued_rd_data[`ISSUE_IM0_H:`ISSUE_IM0_L];
assign lsu_imm_value1 = issued_rd_data[`ISSUE_IM1_H:`ISSUE_IM1_L];
assign lsu_source_reg1 = issued_rd_data[`ISSUE_SRC1_H-2:`ISSUE_SRC1_L];
assign lsu_source_reg2 = issued_rd_data[`ISSUE_SRC2_H-1:`ISSUE_SRC2_L];
assign lsu_source_reg3 = issued_rd_data[`ISSUE_SRC3_H-1:`ISSUE_SRC3_L];
assign lsu_dest_reg_size = issued_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_H-1];
assign lsu_dest_reg = issued_rd_data[`ISSUE_DST1_H-2:`ISSUE_DST1_L];
assign lsu_mem_sgpr = issued_rd_data[`ISSUE_SRC4_H-2:`ISSUE_SRC4_L];
assign issue_lsu_vcc_wr = issued_rd_data[`ISSUE_VCC_WR];
assign issue_lsu_scc_wr = issued_rd_data[`ISSUE_SCC_WR];
assign issue_lsu_m0_wr = issued_rd_data[`ISSUE_M0_WR];
assign issue_lsu_exec_wr = issued_rd_data[`ISSUE_EXEC_WR];
assign alu_opcode = issued_rd_data[`ISSUE_OP_H:`ISSUE_OP_L];
assign alu_instr_pc = issued_rd_data[`ISSUE_PC_H:`ISSUE_PC_L];
assign alu_imm_value0 = issued_rd_data[`ISSUE_IM0_H:`ISSUE_IM0_L];
assign alu_imm_value1 = issued_rd_data[`ISSUE_IM1_H:`ISSUE_IM1_L];
assign alu_source_reg1 = issued_rd_data[`ISSUE_SRC1_H-2:`ISSUE_SRC1_L];
assign alu_source_reg2 = issued_rd_data[`ISSUE_SRC2_H-1:`ISSUE_SRC2_L];
assign alu_source_reg3 = issued_rd_data[`ISSUE_SRC3_H-1:`ISSUE_SRC3_L];
assign alu_dest_reg1_size = issued_rd_data[`ISSUE_DST1_H-1];
assign alu_dest_reg1 = issued_rd_data[`ISSUE_DST1_H-2:`ISSUE_DST1_L];
assign alu_dest_reg2_size = issued_rd_data[`ISSUE_DST2_H];
assign alu_dest_reg2 = issued_rd_data[`ISSUE_DST2_H-1:`ISSUE_DST2_L];
assign issue_alu_vcc_wr = issued_rd_data[`ISSUE_VCC_WR];
assign issue_alu_scc_wr = issued_rd_data[`ISSUE_SCC_WR];
assign issue_alu_m0_wr = issued_rd_data[`ISSUE_M0_WR];
assign issue_alu_exec_wr = issued_rd_data[`ISSUE_EXEC_WR];
assign alu_branch = issued_rd_data[`ISSUE_BRANCH];
busy_gpr_table bgt
(/*AUTOINST*/
// Outputs
.decode_dest_reg1_busy_bits (decode_dest_reg1_busy_bits[3:0]),
.decode_source_reg1_busy_bits (decode_source_reg1_busy_bits[3:0]),
.decode_source_reg4_busy_bits (decode_source_reg4_busy_bits[3:0]),
.decode_source_reg2_busy_bits (decode_source_reg2_busy_bits[1:0]),
.decode_source_reg3_busy_bits (decode_source_reg3_busy_bits[1:0]),
.decode_dest_reg2_busy_bits (decode_dest_reg2_busy_bits[1:0]),
// Inputs
.clk (clk),
.rst (rst),
.alu_valid (alu_valid),
.lsu_valid (lsu_valid),
.f_decode_source_reg2 (f_decode_source_reg2[`OPERAND_LENGTH_2WORD-1:0]),
.f_decode_source_reg3 (f_decode_source_reg3[`OPERAND_LENGTH_2WORD-1:0]),
.f_decode_dest_reg2 (f_decode_dest_reg2[`OPERAND_LENGTH_2WORD-1:0]),
.f_decode_dest_reg1 (f_decode_dest_reg1[`OPERAND_LENGTH_4WORD-1:0]),
.f_decode_source_reg1 (f_decode_source_reg1[`OPERAND_LENGTH_4WORD-1:0]),
.f_decode_source_reg4 (f_decode_source_reg4[`OPERAND_LENGTH_4WORD-1:0]),
.alu_dest_reg1 (alu_dest_reg1[11:0]),
.lsu_dest_reg (lsu_dest_reg[11:0]),
.lsu_dest_reg_size (lsu_dest_reg_size[1:0]),
.alu_dest_reg1_size (alu_dest_reg1_size),
.alu_dest_reg2 (alu_dest_reg2[11:0]),
.alu_dest_reg2_size (alu_dest_reg2_size),
.f_vgpr_alu_dest_reg_addr (f_vgpr_alu_dest_reg_addr[`VGPR_ADDR_LENGTH-1:0]),
.f_vgpr_lsu_dest_reg_addr (f_vgpr_lsu_dest_reg_addr[`VGPR_ADDR_LENGTH-1:0]),
.f_vgpr_lsu_dest_reg_valid (f_vgpr_lsu_dest_reg_valid[3:0]),
.f_vgpr_alu_dest_reg_valid (f_vgpr_alu_dest_reg_valid),
.f_sgpr_valu_dest_addr (f_sgpr_valu_dest_addr[`SGPR_ADDR_LENGTH-1:0]),
.f_sgpr_alu_dest_reg_addr (f_sgpr_alu_dest_reg_addr[`SGPR_ADDR_LENGTH-1:0]),
.f_sgpr_lsu_dest_reg_addr (f_sgpr_lsu_dest_reg_addr[`SGPR_ADDR_LENGTH-1:0]),
.f_sgpr_lsu_dest_reg_valid (f_sgpr_lsu_dest_reg_valid[3:0]),
.f_sgpr_alu_dest_reg_valid (f_sgpr_alu_dest_reg_valid[1:0]),
.f_sgpr_valu_dest_reg_valid (f_sgpr_valu_dest_reg_valid));
/*******************************************************************
* GPR comparators to fill the dependency table *
*******************************************************************/
vgpr_comparator vgpr_alu_cmp
(
// Outputs
.result (vgpr_alu_set_data),
// Inputs
.retired_operand_mask ({3'b0,f_vgpr_alu_dest_reg_valid}),
.retired_operand_addr (f_vgpr_alu_dest_reg_addr),
.src1_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC1_H:`ISSUE_SRC1_L]),
.src4_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC4_H:`ISSUE_SRC4_L]),
.dst1_gpr_info (vgpr_alu_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_L]),
.src2_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC2_H:`ISSUE_SRC2_L]),
.src3_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC3_H:`ISSUE_SRC3_L]),
.dst2_gpr_info (vgpr_alu_rd_data[`ISSUE_DST2_H:`ISSUE_DST2_L]));
vgpr_comparator vgpr_lsu_cmp
(
// Outputs
.result (vgpr_lsu_set_data),
// Inputs
.retired_operand_mask (f_vgpr_lsu_dest_reg_valid),
.retired_operand_addr (f_vgpr_lsu_dest_reg_addr),
.src1_gpr_info (vgpr_lsu_rd_data[`ISSUE_SRC1_H:`ISSUE_SRC1_L]),
.src4_gpr_info (vgpr_lsu_rd_data[`ISSUE_SRC4_H:`ISSUE_SRC4_L]),
.dst1_gpr_info (vgpr_lsu_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_L]),
.src2_gpr_info (vgpr_lsu_rd_data[`ISSUE_SRC2_H:`ISSUE_SRC2_L]),
.src3_gpr_info (vgpr_lsu_rd_data[`ISSUE_SRC3_H:`ISSUE_SRC3_L]),
.dst2_gpr_info (vgpr_lsu_rd_data[`ISSUE_DST2_H:`ISSUE_DST2_L]));
sgpr_comparator sgpr_alu_cmp
(
// Outputs
.result (sgpr_alu_set_data),
// Inputs
.retired_operand_mask ({2'b0,f_sgpr_alu_dest_reg_valid}),
.retired_operand_addr (f_sgpr_alu_dest_reg_addr),
.src1_gpr_info (sgpr_alu_rd_data[`ISSUE_SRC1_H:`ISSUE_SRC1_L]),
.src4_gpr_info (sgpr_alu_rd_data[`ISSUE_SRC4_H:`ISSUE_SRC4_L]),
.dst1_gpr_info (sgpr_alu_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_L]),
.src2_gpr_info (sgpr_alu_rd_data[`ISSUE_SRC2_H:`ISSUE_SRC2_L]),
.src3_gpr_info (sgpr_alu_rd_data[`ISSUE_SRC3_H:`ISSUE_SRC3_L]),
.dst2_gpr_info (sgpr_alu_rd_data[`ISSUE_DST2_H:`ISSUE_DST2_L]));
// This comparator uses the same WFID as the valu one, so it also uses the
// same data read from the instruction info table
sgpr_comparator sgpr_valu_cmp
(
// Outputs
.result (sgpr_valu_set_data),
// Inputs
.retired_operand_mask ({2'b0,f_sgpr_valu_dest_reg_valid, f_sgpr_valu_dest_reg_valid}),
.retired_operand_addr (f_sgpr_valu_dest_addr),
.src1_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC1_H:`ISSUE_SRC1_L]),
.src4_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC4_H:`ISSUE_SRC4_L]),
.dst1_gpr_info (vgpr_alu_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_L]),
.src2_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC2_H:`ISSUE_SRC2_L]),
.src3_gpr_info (vgpr_alu_rd_data[`ISSUE_SRC3_H:`ISSUE_SRC3_L]),
.dst2_gpr_info (vgpr_alu_rd_data[`ISSUE_DST2_H:`ISSUE_DST2_L]));
sgpr_comparator sgpr_lsu_cmp
(
// Outputs
.result (sgpr_lsu_set_data),
// Inputs
.retired_operand_mask (f_sgpr_lsu_dest_reg_valid),
.retired_operand_addr (f_sgpr_lsu_dest_reg_addr),
.src1_gpr_info (sgpr_lsu_rd_data[`ISSUE_SRC1_H:`ISSUE_SRC1_L]),
.src4_gpr_info (sgpr_lsu_rd_data[`ISSUE_SRC4_H:`ISSUE_SRC4_L]),
.dst1_gpr_info (sgpr_lsu_rd_data[`ISSUE_DST1_H:`ISSUE_DST1_L]),
.src2_gpr_info (sgpr_lsu_rd_data[`ISSUE_SRC2_H:`ISSUE_SRC2_L]),
.src3_gpr_info (sgpr_lsu_rd_data[`ISSUE_SRC3_H:`ISSUE_SRC3_L]),
.dst2_gpr_info (sgpr_lsu_rd_data[`ISSUE_DST2_H:`ISSUE_DST2_L]));
/**********************************************************************
* GPR dependency table *
**********************************************************************/
gpr_dependency_table gdt
(/*AUTOINST*/
// Outputs
.ready_arry_gpr (ready_arry_gpr[`WF_PER_CU-1:0]),
// Inputs
.clk (clk),
.rst (rst),
.vgpr_alu_set_data (vgpr_alu_set_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.vgpr_lsu_set_data (vgpr_lsu_set_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.sgpr_alu_set_data (sgpr_alu_set_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.sgpr_lsu_set_data (sgpr_lsu_set_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.sgpr_valu_set_data (sgpr_valu_set_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.decode_instr_data (decode_instr_data[`ISSUE_GPR_RD_BITS_LENGTH-1:0]),
.f_vgpr_alu_wr_done_wfid (f_vgpr_alu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_vgpr_lsu_wr_done_wfid (f_vgpr_lsu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_sgpr_alu_wr_done_wfid (f_sgpr_alu_wr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_sgpr_lsu_instr_done_wfid (f_sgpr_lsu_instr_done_wfid[`WF_ID_LENGTH-1:0]),
.f_decode_wfid (f_decode_wfid[`WF_ID_LENGTH-1:0]),
.f_decode_valid (f_decode_valid));
assign decode_instr_data = {decode_source_reg1_busy_bits, decode_source_reg2_busy_bits[1:0],
decode_source_reg3_busy_bits[1:0], decode_source_reg4_busy_bits,
decode_dest_reg1_busy_bits, decode_dest_reg2_busy_bits[1:0]};
/**********************************************************************
* SPR dependency table *
**********************************************************************/
spr_dependency_table sdt
(/*AUTOINST*/
// Outputs
.ready_arry_spr (ready_arry_spr[`WF_PER_CU-1:0]),
// Inputs
.f_decode_wfid (f_decode_wfid[`WF_ID_LENGTH-1:0]),
.f_exec_salu_wr_wfid (f_exec_salu_wr_wfid[`WF_ID_LENGTH-1:0]),
.f_exec_valu_wr_vcc_wfid (f_exec_valu_wr_vcc_wfid[`WF_ID_LENGTH-1:0]),
.issued_wfid (issued_wfid[`WF_ID_LENGTH-1:0]),
.f_decode_valid (f_decode_valid),
.f_decode_vcc_wr (f_decode_vcc_wr),
.f_decode_vcc_rd (f_decode_vcc_rd),
.f_decode_scc_wr (f_decode_scc_wr),
.f_decode_scc_rd (f_decode_scc_rd),
.f_decode_exec_rd (f_decode_exec_rd),
.f_decode_exec_wr (f_decode_exec_wr),
.f_decode_m0_rd (f_decode_m0_rd),
.f_decode_m0_wr (f_decode_m0_wr),
.f_exec_salu_wr_vcc_en (f_exec_salu_wr_vcc_en),
.f_exec_salu_wr_exec_en (f_exec_salu_wr_exec_en),
.f_exec_salu_wr_scc_en (f_exec_salu_wr_scc_en),
.f_exec_salu_wr_m0_en (f_exec_salu_wr_m0_en),
.f_exec_valu_wr_vcc_en (f_exec_valu_wr_vcc_en),
.alu_valid (alu_valid),
.lsu_valid (lsu_valid),
.issued_valid (issued_valid),
.issue_lsu_vcc_wr (issue_lsu_vcc_wr),
.issue_lsu_scc_wr (issue_lsu_scc_wr),
.issue_lsu_exec_wr (issue_lsu_exec_wr),
.issue_lsu_m0_wr (issue_lsu_m0_wr),
.issue_alu_vcc_wr (issue_alu_vcc_wr),
.issue_alu_scc_wr (issue_alu_scc_wr),
.issue_alu_exec_wr (issue_alu_exec_wr),
.issue_alu_m0_wr (issue_alu_m0_wr),
.clk (clk),
.rst (rst));
assign ready_array_data_dependencies = ready_arry_spr & ready_arry_gpr;
endmodule
|
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2016 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2016.3
// \ \ Description : Xilinx Unified Simulation Library Component
// / / Xilinx Analog-to-Digital Converter and System Monitor
// /___/ /\ Filename : SYSMONE4.v
// \ \ / \
// \___\/\___\
//
///////////////////////////////////////////////////////////////////////////////
// Revision:
//
// End Revision:
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps / 1ps
`celldefine
module SYSMONE4 #(
`ifdef XIL_TIMING
parameter LOC = "UNPLACED",
`endif
parameter [15:0] COMMON_N_SOURCE = 16'hFFFF,
parameter [15:0] INIT_40 = 16'h0000,
parameter [15:0] INIT_41 = 16'h0000,
parameter [15:0] INIT_42 = 16'h0000,
parameter [15:0] INIT_43 = 16'h0000,
parameter [15:0] INIT_44 = 16'h0000,
parameter [15:0] INIT_45 = 16'h0000,
parameter [15:0] INIT_46 = 16'h0000,
parameter [15:0] INIT_47 = 16'h0000,
parameter [15:0] INIT_48 = 16'h0000,
parameter [15:0] INIT_49 = 16'h0000,
parameter [15:0] INIT_4A = 16'h0000,
parameter [15:0] INIT_4B = 16'h0000,
parameter [15:0] INIT_4C = 16'h0000,
parameter [15:0] INIT_4D = 16'h0000,
parameter [15:0] INIT_4E = 16'h0000,
parameter [15:0] INIT_4F = 16'h0000,
parameter [15:0] INIT_50 = 16'h0000,
parameter [15:0] INIT_51 = 16'h0000,
parameter [15:0] INIT_52 = 16'h0000,
parameter [15:0] INIT_53 = 16'h0000,
parameter [15:0] INIT_54 = 16'h0000,
parameter [15:0] INIT_55 = 16'h0000,
parameter [15:0] INIT_56 = 16'h0000,
parameter [15:0] INIT_57 = 16'h0000,
parameter [15:0] INIT_58 = 16'h0000,
parameter [15:0] INIT_59 = 16'h0000,
parameter [15:0] INIT_5A = 16'h0000,
parameter [15:0] INIT_5B = 16'h0000,
parameter [15:0] INIT_5C = 16'h0000,
parameter [15:0] INIT_5D = 16'h0000,
parameter [15:0] INIT_5E = 16'h0000,
parameter [15:0] INIT_5F = 16'h0000,
parameter [15:0] INIT_60 = 16'h0000,
parameter [15:0] INIT_61 = 16'h0000,
parameter [15:0] INIT_62 = 16'h0000,
parameter [15:0] INIT_63 = 16'h0000,
parameter [15:0] INIT_64 = 16'h0000,
parameter [15:0] INIT_65 = 16'h0000,
parameter [15:0] INIT_66 = 16'h0000,
parameter [15:0] INIT_67 = 16'h0000,
parameter [15:0] INIT_68 = 16'h0000,
parameter [15:0] INIT_69 = 16'h0000,
parameter [15:0] INIT_6A = 16'h0000,
parameter [15:0] INIT_6B = 16'h0000,
parameter [15:0] INIT_6C = 16'h0000,
parameter [15:0] INIT_6D = 16'h0000,
parameter [15:0] INIT_6E = 16'h0000,
parameter [15:0] INIT_6F = 16'h0000,
parameter [15:0] INIT_70 = 16'h0000,
parameter [15:0] INIT_71 = 16'h0000,
parameter [15:0] INIT_72 = 16'h0000,
parameter [15:0] INIT_73 = 16'h0000,
parameter [15:0] INIT_74 = 16'h0000,
parameter [15:0] INIT_75 = 16'h0000,
parameter [15:0] INIT_76 = 16'h0000,
parameter [15:0] INIT_77 = 16'h0000,
parameter [15:0] INIT_78 = 16'h0000,
parameter [15:0] INIT_79 = 16'h0000,
parameter [15:0] INIT_7A = 16'h0000,
parameter [15:0] INIT_7B = 16'h0000,
parameter [15:0] INIT_7C = 16'h0000,
parameter [15:0] INIT_7D = 16'h0000,
parameter [15:0] INIT_7E = 16'h0000,
parameter [15:0] INIT_7F = 16'h0000,
parameter [0:0] IS_CONVSTCLK_INVERTED = 1'b0,
parameter [0:0] IS_DCLK_INVERTED = 1'b0,
parameter SIM_DEVICE = "ULTRASCALE_PLUS",
parameter SIM_MONITOR_FILE = "design.txt",
parameter integer SYSMON_VUSER0_BANK = 0,
parameter SYSMON_VUSER0_MONITOR = "NONE",
parameter integer SYSMON_VUSER1_BANK = 0,
parameter SYSMON_VUSER1_MONITOR = "NONE",
parameter integer SYSMON_VUSER2_BANK = 0,
parameter SYSMON_VUSER2_MONITOR = "NONE",
parameter integer SYSMON_VUSER3_BANK = 0,
parameter SYSMON_VUSER3_MONITOR = "NONE"
)(
output [15:0] ADC_DATA,
output [15:0] ALM,
output BUSY,
output [5:0] CHANNEL,
output [15:0] DO,
output DRDY,
output EOC,
output EOS,
output I2C_SCLK_TS,
output I2C_SDA_TS,
output JTAGBUSY,
output JTAGLOCKED,
output JTAGMODIFIED,
output [4:0] MUXADDR,
output OT,
output SMBALERT_TS,
input CONVST,
input CONVSTCLK,
input [7:0] DADDR,
input DCLK,
input DEN,
input [15:0] DI,
input DWE,
input I2C_SCLK,
input I2C_SDA,
input RESET,
input [15:0] VAUXN,
input [15:0] VAUXP,
input VN,
input VP
);
// define constants
localparam MODULE_NAME = "SYSMONE4";
// Parameter encodings and registers
//localparam SIM_DEVICE_ULTRASCALE_PLUS = 0;
//localparam SIM_DEVICE_ULTRASCALE_PLUS_ES1 = 1;
//localparam SIM_DEVICE_ZYNQ_ULTRASCALE = 2;
//localparam SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 = 3;
//localparam SIM_MONITOR_FILE_design_txt = 0;
//localparam SYSMON_VUSER0_MONITOR_NONE = 0;
//localparam SYSMON_VUSER1_MONITOR_NONE = 0;
//localparam SYSMON_VUSER2_MONITOR_NONE = 0;
//localparam SYSMON_VUSER3_MONITOR_NONE = 0;
reg trig_attr = 1'b0;
reg trig_dep_attr = 1'b0;
reg trig_i2c_addr = 1'b0;
// include dynamic registers - XILINX test only
`ifdef XIL_DR
`include "SYSMONE4_dr.v"
`else
localparam [15:0] COMMON_N_SOURCE_REG = COMMON_N_SOURCE;
localparam [15:0] INIT_40_REG = INIT_40;
localparam [15:0] INIT_41_REG = INIT_41;
localparam [15:0] INIT_42_REG = INIT_42;
localparam [15:0] INIT_43_REG = INIT_43;
localparam [15:0] INIT_44_REG = INIT_44;
localparam [15:0] INIT_45_REG = INIT_45;
localparam [15:0] INIT_46_REG = INIT_46;
localparam [15:0] INIT_47_REG = INIT_47;
localparam [15:0] INIT_48_REG = INIT_48;
localparam [15:0] INIT_49_REG = INIT_49;
localparam [15:0] INIT_4A_REG = INIT_4A;
localparam [15:0] INIT_4B_REG = INIT_4B;
localparam [15:0] INIT_4C_REG = INIT_4C;
localparam [15:0] INIT_4D_REG = INIT_4D;
localparam [15:0] INIT_4E_REG = INIT_4E;
localparam [15:0] INIT_4F_REG = INIT_4F;
localparam [15:0] INIT_50_REG = INIT_50;
localparam [15:0] INIT_51_REG = INIT_51;
localparam [15:0] INIT_52_REG = INIT_52;
localparam [15:0] INIT_53_REG = INIT_53;
localparam [15:0] INIT_54_REG = INIT_54;
localparam [15:0] INIT_55_REG = INIT_55;
localparam [15:0] INIT_56_REG = INIT_56;
localparam [15:0] INIT_57_REG = INIT_57;
localparam [15:0] INIT_58_REG = INIT_58;
localparam [15:0] INIT_59_REG = INIT_59;
localparam [15:0] INIT_5A_REG = INIT_5A;
localparam [15:0] INIT_5B_REG = INIT_5B;
localparam [15:0] INIT_5C_REG = INIT_5C;
localparam [15:0] INIT_5D_REG = INIT_5D;
localparam [15:0] INIT_5E_REG = INIT_5E;
localparam [15:0] INIT_5F_REG = INIT_5F;
localparam [15:0] INIT_60_REG = INIT_60;
localparam [15:0] INIT_61_REG = INIT_61;
localparam [15:0] INIT_62_REG = INIT_62;
localparam [15:0] INIT_63_REG = INIT_63;
localparam [15:0] INIT_64_REG = INIT_64;
localparam [15:0] INIT_65_REG = INIT_65;
localparam [15:0] INIT_66_REG = INIT_66;
localparam [15:0] INIT_67_REG = INIT_67;
localparam [15:0] INIT_68_REG = INIT_68;
localparam [15:0] INIT_69_REG = INIT_69;
localparam [15:0] INIT_6A_REG = INIT_6A;
localparam [15:0] INIT_6B_REG = INIT_6B;
localparam [15:0] INIT_6C_REG = INIT_6C;
localparam [15:0] INIT_6D_REG = INIT_6D;
localparam [15:0] INIT_6E_REG = INIT_6E;
localparam [15:0] INIT_6F_REG = INIT_6F;
localparam [15:0] INIT_70_REG = INIT_70;
localparam [15:0] INIT_71_REG = INIT_71;
localparam [15:0] INIT_72_REG = INIT_72;
localparam [15:0] INIT_73_REG = INIT_73;
localparam [15:0] INIT_74_REG = INIT_74;
localparam [15:0] INIT_75_REG = INIT_75;
localparam [15:0] INIT_76_REG = INIT_76;
localparam [15:0] INIT_77_REG = INIT_77;
localparam [15:0] INIT_78_REG = INIT_78;
localparam [15:0] INIT_79_REG = INIT_79;
localparam [15:0] INIT_7A_REG = INIT_7A;
localparam [15:0] INIT_7B_REG = INIT_7B;
localparam [15:0] INIT_7C_REG = INIT_7C;
localparam [15:0] INIT_7D_REG = INIT_7D;
localparam [15:0] INIT_7E_REG = INIT_7E;
localparam [15:0] INIT_7F_REG = INIT_7F;
localparam [0:0] IS_CONVSTCLK_INVERTED_REG = IS_CONVSTCLK_INVERTED;
localparam [0:0] IS_DCLK_INVERTED_REG = IS_DCLK_INVERTED;
localparam [152:1] SIM_DEVICE_REG = SIM_DEVICE;
localparam [80:1] SIM_MONITOR_FILE_REG = SIM_MONITOR_FILE;
localparam [9:0] SYSMON_VUSER0_BANK_REG = SYSMON_VUSER0_BANK;
localparam [32:1] SYSMON_VUSER0_MONITOR_REG = SYSMON_VUSER0_MONITOR;
localparam [9:0] SYSMON_VUSER1_BANK_REG = SYSMON_VUSER1_BANK;
localparam [32:1] SYSMON_VUSER1_MONITOR_REG = SYSMON_VUSER1_MONITOR;
localparam [9:0] SYSMON_VUSER2_BANK_REG = SYSMON_VUSER2_BANK;
localparam [32:1] SYSMON_VUSER2_MONITOR_REG = SYSMON_VUSER2_MONITOR;
localparam [9:0] SYSMON_VUSER3_BANK_REG = SYSMON_VUSER3_BANK;
localparam [32:1] SYSMON_VUSER3_MONITOR_REG = SYSMON_VUSER3_MONITOR;
`endif
wire [15:0] COMMON_N_SOURCE_BIN;
wire [15:0] INIT_40_BIN;
wire [15:0] INIT_41_BIN;
wire [15:0] INIT_42_BIN;
wire [15:0] INIT_43_BIN;
wire [15:0] INIT_44_BIN;
wire [15:0] INIT_45_BIN;
wire [15:0] INIT_46_BIN;
wire [15:0] INIT_47_BIN;
wire [15:0] INIT_48_BIN;
wire [15:0] INIT_49_BIN;
wire [15:0] INIT_4A_BIN;
wire [15:0] INIT_4B_BIN;
wire [15:0] INIT_4C_BIN;
wire [15:0] INIT_4D_BIN;
wire [15:0] INIT_4E_BIN;
wire [15:0] INIT_4F_BIN;
wire [15:0] INIT_50_BIN;
wire [15:0] INIT_51_BIN;
wire [15:0] INIT_52_BIN;
wire [15:0] INIT_53_BIN;
wire [15:0] INIT_54_BIN;
wire [15:0] INIT_55_BIN;
wire [15:0] INIT_56_BIN;
wire [15:0] INIT_57_BIN;
wire [15:0] INIT_58_BIN;
wire [15:0] INIT_59_BIN;
wire [15:0] INIT_5A_BIN;
wire [15:0] INIT_5B_BIN;
wire [15:0] INIT_5C_BIN;
wire [15:0] INIT_5D_BIN;
wire [15:0] INIT_5E_BIN;
wire [15:0] INIT_5F_BIN;
wire [15:0] INIT_60_BIN;
wire [15:0] INIT_61_BIN;
wire [15:0] INIT_62_BIN;
wire [15:0] INIT_63_BIN;
wire [15:0] INIT_64_BIN;
wire [15:0] INIT_65_BIN;
wire [15:0] INIT_66_BIN;
wire [15:0] INIT_67_BIN;
wire [15:0] INIT_68_BIN;
wire [15:0] INIT_69_BIN;
wire [15:0] INIT_6A_BIN;
wire [15:0] INIT_6B_BIN;
wire [15:0] INIT_6C_BIN;
wire [15:0] INIT_6D_BIN;
wire [15:0] INIT_6E_BIN;
wire [15:0] INIT_6F_BIN;
wire [15:0] INIT_70_BIN;
wire [15:0] INIT_71_BIN;
wire [15:0] INIT_72_BIN;
wire [15:0] INIT_73_BIN;
wire [15:0] INIT_74_BIN;
wire [15:0] INIT_75_BIN;
wire [15:0] INIT_76_BIN;
wire [15:0] INIT_77_BIN;
wire [15:0] INIT_78_BIN;
wire [15:0] INIT_79_BIN;
wire [15:0] INIT_7A_BIN;
wire [15:0] INIT_7B_BIN;
wire [15:0] INIT_7C_BIN;
wire [15:0] INIT_7D_BIN;
wire [15:0] INIT_7E_BIN;
wire [15:0] INIT_7F_BIN;
wire IS_CONVSTCLK_INVERTED_BIN;
wire IS_DCLK_INVERTED_BIN;
wire [1:0] SIM_DEVICE_BIN;
wire SIM_MONITOR_FILE_BIN;
wire [9:0] SYSMON_VUSER0_BANK_BIN;
wire SYSMON_VUSER0_MONITOR_BIN;
wire [9:0] SYSMON_VUSER1_BANK_BIN;
wire SYSMON_VUSER1_MONITOR_BIN;
wire [9:0] SYSMON_VUSER2_BANK_BIN;
wire SYSMON_VUSER2_MONITOR_BIN;
wire [9:0] SYSMON_VUSER3_BANK_BIN;
wire SYSMON_VUSER3_MONITOR_BIN;
`ifdef XIL_ATTR_TEST
reg attr_test = 1'b1;
`else
reg attr_test = 1'b0;
`endif
reg attr_err = 1'b0;
tri0 glblGSR = glbl.GSR;
reg BUSY_out;
reg DRDY_out;
reg EOC_out;
reg EOS_out;
wire I2C_SCLK_TS_out;
reg I2C_SDA_TS_out;
wire JTAGBUSY_out;
wire JTAGLOCKED_out;
wire JTAGMODIFIED_out;
reg OT_out;
reg SMBALERT_TS_out;
reg [15:0] ADC_DATA_out;
reg [15:0] ALM_out;
reg [15:0] DO_out;
reg [4:0] MUXADDR_out;
reg [5:0] CHANNEL_out;
wire CONVSTCLK_in;
wire CONVST_in;
wire DCLK_in;
wire DEN_in;
wire DWE_in;
wire I2C_SCLK_in;
wire I2C_SDA_in;
wire RESET_in;
wire VN_in;
wire VP_in;
wire [15:0] DI_in;
wire [15:0] VAUXN_in;
wire [15:0] VAUXP_in;
wire [7:0] DADDR_in;
`ifdef XIL_TIMING
wire DCLK_delay;
wire DEN_delay;
wire DWE_delay;
wire [15:0] DI_delay;
wire [7:0] DADDR_delay;
`endif
assign ADC_DATA = ADC_DATA_out;
assign ALM = ALM_out;
assign BUSY = BUSY_out;
assign CHANNEL = CHANNEL_out;
assign DO = DO_out;
assign DRDY = DRDY_out;
assign EOC = EOC_out;
assign EOS = EOS_out;
assign I2C_SCLK_TS = I2C_SCLK_TS_out;
assign I2C_SDA_TS = I2C_SDA_TS_out;
assign JTAGBUSY = JTAGBUSY_out;
assign JTAGLOCKED = JTAGLOCKED_out;
assign JTAGMODIFIED = JTAGMODIFIED_out;
assign MUXADDR = MUXADDR_out;
assign OT = OT_out;
assign SMBALERT_TS = SMBALERT_TS_out;
wire [7:0] DADDR_inv;
wire DCLK_inv;
wire DEN_inv;
wire DWE_inv;
wire RESET_in_inv;
wire [15:0] DI_inv;
wire I2C_SCLK_inv;
wire I2C_SDA_inv;
`ifdef XIL_TIMING
assign DADDR_inv = DADDR_delay;
assign DCLK_inv = DCLK_delay;
assign DEN_inv = DEN_delay;
assign DI_inv = DI_delay;
assign DWE_inv = DWE_delay;
`else
assign DADDR_inv = DADDR;
assign DCLK_inv = DCLK;
assign DEN_inv = DEN;
assign DI_inv = DI;
assign DWE_inv = DWE;
`endif
assign I2C_SCLK_inv = I2C_SCLK;
assign I2C_SDA_inv = I2C_SDA;
assign DADDR_in = DADDR_inv ^ 7'b0000000;
assign DCLK_in = DCLK_inv ^ IS_DCLK_INVERTED_BIN;
assign DEN_in = DEN_inv ^ 1'b0;
assign DI_in = DI_inv ^ 16'h0000;
assign DWE_in = DWE_inv ^ 1'b0;
assign RESET_in = RESET;
assign CONVSTCLK_in = CONVSTCLK ^ IS_CONVSTCLK_INVERTED_BIN;
assign CONVST_in = CONVST ^ 1'b0;
assign I2C_SCLK_in = I2C_SCLK_inv ^ 1'b0;
assign I2C_SDA_in = I2C_SDA_inv ^ 1'b0;
assign VAUXN_in = VAUXN;
assign VAUXP_in = VAUXP;
assign VN_in = VN;
assign VP_in = VP;
assign COMMON_N_SOURCE_BIN = COMMON_N_SOURCE_REG;
assign INIT_40_BIN = INIT_40_REG;
assign INIT_41_BIN = INIT_41_REG;
assign INIT_42_BIN = INIT_42_REG;
assign INIT_43_BIN = INIT_43_REG;
assign INIT_44_BIN = INIT_44_REG;
assign INIT_45_BIN = INIT_45_REG;
assign INIT_46_BIN = INIT_46_REG;
assign INIT_47_BIN = INIT_47_REG;
assign INIT_48_BIN = INIT_48_REG;
assign INIT_49_BIN = INIT_49_REG;
assign INIT_4A_BIN = INIT_4A_REG;
assign INIT_4B_BIN = INIT_4B_REG;
assign INIT_4C_BIN = INIT_4C_REG;
assign INIT_4D_BIN = INIT_4D_REG;
assign INIT_4E_BIN = INIT_4E_REG;
assign INIT_4F_BIN = INIT_4F_REG;
assign INIT_50_BIN = INIT_50_REG;
assign INIT_51_BIN = INIT_51_REG;
assign INIT_52_BIN = INIT_52_REG;
assign INIT_53_BIN = INIT_53_REG;
assign INIT_54_BIN = INIT_54_REG;
assign INIT_55_BIN = INIT_55_REG;
assign INIT_56_BIN = INIT_56_REG;
assign INIT_57_BIN = INIT_57_REG;
assign INIT_58_BIN = INIT_58_REG;
assign INIT_59_BIN = INIT_59_REG;
assign INIT_5A_BIN = INIT_5A_REG;
assign INIT_5B_BIN = INIT_5B_REG;
assign INIT_5C_BIN = INIT_5C_REG;
assign INIT_5D_BIN = INIT_5D_REG;
assign INIT_5E_BIN = INIT_5E_REG;
assign INIT_5F_BIN = INIT_5F_REG;
assign INIT_60_BIN = INIT_60_REG;
assign INIT_61_BIN = INIT_61_REG;
assign INIT_62_BIN = INIT_62_REG;
assign INIT_63_BIN = INIT_63_REG;
assign INIT_64_BIN = INIT_64_REG;
assign INIT_65_BIN = INIT_65_REG;
assign INIT_66_BIN = INIT_66_REG;
assign INIT_67_BIN = INIT_67_REG;
assign INIT_68_BIN = INIT_68_REG;
assign INIT_69_BIN = INIT_69_REG;
assign INIT_6A_BIN = INIT_6A_REG;
assign INIT_6B_BIN = INIT_6B_REG;
assign INIT_6C_BIN = INIT_6C_REG;
assign INIT_6D_BIN = INIT_6D_REG;
assign INIT_6E_BIN = INIT_6E_REG;
assign INIT_6F_BIN = INIT_6F_REG;
assign INIT_70_BIN = INIT_70_REG;
assign INIT_71_BIN = INIT_71_REG;
assign INIT_72_BIN = INIT_72_REG;
assign INIT_73_BIN = INIT_73_REG;
assign INIT_74_BIN = INIT_74_REG;
assign INIT_75_BIN = INIT_75_REG;
assign INIT_76_BIN = INIT_76_REG;
assign INIT_77_BIN = INIT_77_REG;
assign INIT_78_BIN = INIT_78_REG;
assign INIT_79_BIN = INIT_79_REG;
assign INIT_7A_BIN = INIT_7A_REG;
assign INIT_7B_BIN = INIT_7B_REG;
assign INIT_7C_BIN = INIT_7C_REG;
assign INIT_7D_BIN = INIT_7D_REG;
assign INIT_7E_BIN = INIT_7E_REG;
assign INIT_7F_BIN = INIT_7F_REG;
assign IS_CONVSTCLK_INVERTED_BIN = IS_CONVSTCLK_INVERTED_REG;
assign IS_DCLK_INVERTED_BIN = IS_DCLK_INVERTED_REG;
// assign SIM_DEVICE_BIN =
// (SIM_DEVICE_REG == "ULTRASCALE_PLUS") ? SIM_DEVICE_ULTRASCALE_PLUS :
// (SIM_DEVICE_REG == "ULTRASCALE_PLUS_ES1") ? SIM_DEVICE_ULTRASCALE_PLUS_ES1 :
// (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE") ? SIM_DEVICE_ZYNQ_ULTRASCALE :
// (SIM_DEVICE_REG == "ZYNQ_ULTRASCALE_ES1") ? SIM_DEVICE_ZYNQ_ULTRASCALE_ES1 :
// SIM_DEVICE_ULTRASCALE_PLUS;
//
// assign SIM_MONITOR_FILE_BIN =
// (SIM_MONITOR_FILE_REG == "design.txt") ? SIM_MONITOR_FILE_design_txt :
// SIM_MONITOR_FILE_design_txt;
//
assign SYSMON_VUSER0_BANK_BIN = SYSMON_VUSER0_BANK_REG;
// assign SYSMON_VUSER0_MONITOR_BIN =
// (SYSMON_VUSER0_MONITOR_REG == "NONE") ? SYSMON_VUSER0_MONITOR_NONE :
// SYSMON_VUSER0_MONITOR_NONE;
assign SYSMON_VUSER1_BANK_BIN = SYSMON_VUSER1_BANK_REG;
// assign SYSMON_VUSER1_MONITOR_BIN =
// (SYSMON_VUSER1_MONITOR_REG == "NONE") ? SYSMON_VUSER1_MONITOR_NONE :
// SYSMON_VUSER1_MONITOR_NONE;
assign SYSMON_VUSER2_BANK_BIN = SYSMON_VUSER2_BANK_REG;
// assign SYSMON_VUSER2_MONITOR_BIN =
// (SYSMON_VUSER2_MONITOR_REG == "NONE") ? SYSMON_VUSER2_MONITOR_NONE :
// SYSMON_VUSER2_MONITOR_NONE;
assign SYSMON_VUSER3_BANK_BIN = SYSMON_VUSER3_BANK_REG;
// assign SYSMON_VUSER3_MONITOR_BIN =
// (SYSMON_VUSER3_MONITOR_REG == "NONE") ? SYSMON_VUSER3_MONITOR_NONE :
// SYSMON_VUSER3_MONITOR_NONE;
initial begin
trig_attr = 0;
#1;
trig_i2c_addr = 1;
trig_attr = 1;
#2 trig_dep_attr = 1;
end
time time_check;
always @(posedge trig_attr) begin
#1;
time_check=$time;
if(time_check != 2)
$display("Warning: [Unisim %s-69] SYSMONE4 time resolution has been overridden. It should be left as picoseconds. The model will not function correctly this way.", MODULE_NAME);
if ((attr_test == 1'b1) ||
((SIM_DEVICE != "ULTRASCALE_PLUS") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES1") &&
(SIM_DEVICE != "ULTRASCALE_PLUS_ES2") &&
(SIM_DEVICE != "ZYNQ_ULTRASCALE") &&
(SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1") &&
(SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2")
)) begin
$display("Error: [Unisim %s-168] SIM_DEVICE attribute is set to %s. Legal values for this attribute are ULTRASCALE_PLUS, ULTRASCALE_PLUS_ES1, ULTRASCALE_PLUS_ES2, ZYNQ_ULTRASCALE, ZYNQ_ULTRASCALE_ES1, or ZYNQ_ULTRASCALE_ES2. Instance: %m", MODULE_NAME, SIM_DEVICE);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER0_BANK_REG < 0) || (SYSMON_VUSER0_BANK_REG > 999))) begin
$display("Error: [Unisim %s-170] SYSMON_VUSER0_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER0_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER1_BANK_REG < 0) || (SYSMON_VUSER1_BANK_REG > 999))) begin
$display("Error: [Unisim %s-172] SYSMON_VUSER1_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER1_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER2_BANK_REG < 0) || (SYSMON_VUSER2_BANK_REG > 999))) begin
$display("Error: [Unisim %s-174] SYSMON_VUSER2_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER2_BANK_REG);
attr_err = 1'b1;
end
if ((attr_test == 1'b1) ||
((SYSMON_VUSER3_BANK_REG < 0) || (SYSMON_VUSER3_BANK_REG > 999))) begin
$display("Error: [Unisim %s-176] SYSMON_VUSER3_BANK attribute is set to %d. Legal values for this attribute are 0 to 999. Instance: %m", MODULE_NAME, SYSMON_VUSER3_BANK_REG);
attr_err = 1'b1;
end
if (attr_err == 1'b1)
#1 $finish;
end // always @ (trig_attr)
always @(trig_dep_attr) begin
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[8]==1) && (INIT_40_BIN[5:0] != 6'b000011) && (INIT_40_BIN[5:0] < 6'b010000)))
$display("Warning: [Unisim %s-1] INIT_40 attribute is set to %x. Bit[8] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_40_BIN);
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]!=4'b0011) && (INIT_4E_BIN[10:0]!=11'd0) && (INIT_4E_BIN[15:12]!=4'd0)))
$display("Warning: [Unisim %s-2] INIT_4E attribute is set to %x. Bit[15:12] and bit[10:0] of this attribute must be set to 0. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, INIT_4E_BIN);
if ((attr_test == 1'b1) ||
((INIT_41_BIN[15:12]==4'b0011) && (INIT_40_BIN[13:12]!=2'b00) && (INIT_46_BIN != 16'h0000) && (INIT_48_BIN != 16'h0000) && (INIT_49_BIN != 16'h0000)))
$display("Warning: [Unisim %s-3] INIT_46, INIT_48 and INIT_49 attributes are set to %x, %x, and %x respectively. These attributes must be set to 0000h in single channel mode with averaging enabled. Instance: %m", MODULE_NAME, INIT_46_BIN, INIT_48_BIN, INIT_49_BIN);
if ((attr_test == 1'b1) || // CR 952216
(INIT_44_BIN[3:0]!=4'b0000))
$display("Info: [Unisim %s-59] INIT_44[3:0] is set to %0b. For related VUSER banks, where 0-6V range has been selected, analog input file must reflect the selected input range. Instance: %m", MODULE_NAME, INIT_44_BIN[3:0]);
end // always @ (trig_dep_attr)
// Total UNISIM %s- warning message next: 70
localparam CONV_CNT_P = 37;
localparam CONV_CNT = 48;
//sequencer operation
localparam [3:0] SEQ_DEFAULT_MODE = 4'b0000 ;
localparam [1:0] SEQ_DEFAULT_MODE2 = 2'b11 ;
localparam [3:0] SEQ_SINGLE_PASS = 4'b0001 ;
localparam [3:0] SEQ_CONT_CHAN = 4'b0010 ;
localparam [3:0] SEQ_SINGLE_CHAN = 4'b0011 ;//means sequencer is off
//lr_rate
localparam [1:0] LR_EVERY_OTHER = 2'b00;
localparam [1:0] LR_EVERY_4TH = 2'b01;
localparam [1:0] LR_EVERY_16TH = 2'b10;
localparam [1:0] LR_EVERY_64TH = 2'b11;
localparam [1:0] LR_EOS_HR_ONLY1 = 2'b00;
localparam [1:0] LR_EOS_LR_ONLY = 2'b01;
localparam [1:0] LR_EOS_HR_LR = 2'b10;
localparam [1:0] LR_EOS_HR_ONLY2 = 2'b11;
localparam OT_LIMIT_DEFAULT = 16'hCB03;
//adc_state
localparam ST_A_FIRST_CALIB = 0,
ST_A_CALIB = 1,
ST_A_WAIT = 2,
ST_A_CHAN = 3,
ST_A_ALM = 4,
ST_A_EOC = 5,
ST_A_WAIT_ED = 6;
localparam CMD_PAGE = 8'h00;
localparam CMD_CLEAR_FAULT = 8'h03;
localparam CMD_CAPABILITY = 8'h19;
localparam CMD_VOUT_MODE = 8'h20;
localparam CMD_VOUT_OV_FAULT_LIMIT = 8'h40;
localparam CMD_VOUT_UV_FAULT_LIMIT = 8'h44;
localparam CMD_OT_FAULT_LIMIT = 8'h4F;
localparam CMD_OT_WARNING_LIMIT = 8'h51;
localparam CMD_UT_WARNING_LIMIT = 8'h52;
localparam CMD_UT_FAULT_LIMIT = 8'h53;
localparam CMD_STATUS_BYTE = 8'h78;
localparam CMD_STATUS_WORD = 8'h79;
localparam CMD_STATUS_VOUT = 8'h7A;
localparam CMD_STATUS_TEMPERATURE = 8'h7D;
localparam CMD_STATUS_CML = 8'h7E;
localparam CMD_READ_VOUT = 8'h88;
localparam CMD_READ_TEMPERATURE_1 = 8'h8D;
localparam CMD_PMBUS_REVISION = 8'h98;
localparam CMD_MFR_ID = 8'h99;
localparam CMD_MFR_MODEL = 8'h9A;
localparam CMD_MFR_REVISION = 8'h9B;
localparam CMD_MFR_SELECT_REG = 8'hD0;
localparam CMD_MFR_ACCESS_REG = 8'hD1;
localparam CMD_MFR_READ_VOUT_MAX = 8'hD2;
localparam CMD_MFR_READ_VOUT_MIN = 8'hD3;
localparam CMD_MFR_ENABLE_VUSER_HR = 8'hD5;
localparam CMD_MFR_READ_TEMP_MAX = 8'hD6;
localparam CMD_MFR_READ_TEMP_MIN = 8'hD7;
localparam eoc_distance = 18;
localparam alm_distance = 15;
time time_out;
time prev_time_out;
integer temperature_index = -1;
integer time_index = -1;
integer vccaux_index = -1;
integer vccbram_index = -1;
integer vccint_index = -1;
integer vn_index = -1;
integer vp_index = -1;
integer vccpsintlp_index = -1;
integer vccpsintfp_index = -1;
integer vccpsaux_index = -1;
integer vauxp_idx[15:0];
integer vauxn_idx[15:0];
integer vuser0_index = -1;
integer vuser1_index = -1;
integer vuser2_index = -1;
integer vuser3_index = -1;
integer char_1;
integer char_2;
integer fs;
integer fd;
integer num_arg;
integer num_val;
integer adcclk_count;
reg adcclk_count_rst = 0;
wire adcclk_period_start;
wire adcclk_period_end;
reg adcclk_period_end_d;
wire [8:0] avg_amount;
wire avg_en;
wire [1:0] averaging;
wire avg_final_loop;
wire avg_final_loop_hr;
wire avg_final_loop_lr;
wire seq_lr_selected_p;
reg seq_lr_selected;
reg [1:0] seq_lr_selected_d;
reg add_channel_hr_p;
reg add_channel_lr_p;
reg add_channel;
integer conv_acc [63:0];
integer conv_result_int;
integer h, i, j, k, l, m, n, p;
integer file_line;
// string
reg [8*12:1] label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30, label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46;
reg [8*600:1] one_line;
reg [8*12:1] label [46:0];
reg [8*12:1] tmp_label;
reg end_of_file;
real tmp_va0;
real tmp_va1;
real column_real00;
real column_real100;
real column_real101;
real column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46;
// array of real numbers
reg [63:0] column_real [CONV_CNT-1 :0];
reg [63:0] chan_val [CONV_CNT_P-1:0];
reg [63:0] chan_val_tmp [CONV_CNT_P-1:0];
reg [63:0] chan_valn [CONV_CNT_P-1:0];
reg [63:0] chan_valn_tmp [CONV_CNT_P-1:0];
reg [63:0] mn_in_diff [CONV_CNT_P-1:0];
reg [63:0] mn_in2_diff [CONV_CNT_P-1:0];
reg [63:0] mn_in_uni [CONV_CNT_P-1:0];
reg [63:0] mn_in2_uni [CONV_CNT_P-1:0];
reg [63:0] mn_comm_in [CONV_CNT_P-1:0];
reg [63:0] mn_comm2_in [CONV_CNT_P-1:0];
real chan_val_p_tmp;
real chan_val_n_tmp;
real mn_mux_in;
real mn_in_tmp;
real mn_comm_in_tmp;
real mn_in_comm;
real tmp_v;
real tmp_v1;
real adc_temp_result;
real adc_intpwr_result;
real adc_ext_result;
reg init_rst;
reg [2:0] initialize;
reg int_rst_sync1;
reg int_rst_sync2;
wire int_rst_combined;
wire int_rst_combined_d;
reg alm_rst;
reg seq_rst;
reg soft_rst = 0;
reg en_data_flag;
wire [15:0] flag_reg0;
wire [15:0] flag_reg1;
reg [15:0] ot_limit_reg = OT_LIMIT_DEFAULT;
reg [15:0] tmp_otv;
reg [23:0] conv_acc_vec;
reg [15:0] conv_result;
reg [15:0] conv_result_reg;
reg [15:0] conv_acc_result;
wire [7:0] curr_clkdiv_sel;
reg [15:0] alm_out_reg;
reg [15:0] data_written;
reg [2:0] adc_state;
reg [2:0] adc_next_state;
reg [2:0] adc_state_d_dclk;
reg [2:0] adc_state_d;
reg st_first_calib_chan;
reg DRDY_out_pre1;
reg DRDY_out_pre2;
reg DRDY_out_pre3;
reg ot_out_reg;
reg ut_fault;
reg ut_warn;
reg ut_fault_reg; //under temperature fault register for PMBus capability.
reg ut_warn_reg; //under temperature warning register for PMBus capability.
reg [15:0] alm_ut_reg; //under temperature fault registers for PMBUS capability
reg [11:1] alm_ut;
reg [15:0] DO_out_rdtmp;
reg [15:0] data_reg [63:0];
reg [15:0] dr_sram [255:64];
reg sysclk;
reg adcclk_tmp;
wire adcclk;
wire adcclk_div1;
wire ext_mux;
wire ext_mux_en;
wire [5:0] ext_mux_chan_id;
wire [5:0] single_chan_id;
wire default_mode;
wire single_pass_mode;
wire single_pass_active;
wire cont_seq_mode;
wire single_chan_mode;
wire event_driven_mode;
wire cont_sampl_mode;
wire bipolar_mode;
reg single_pass_finished;
reg single_pass_finished_d;
wire single_pass_finished_pe;
reg sim_file_flag;
reg [7:0] DADDR_in_lat;
wire [3:0] op_mode;
reg [3:0] seq_bits;
reg ot_en;
reg [13:0] alm_en;
wire [15:0] seq_hr_chan_reg1;
wire [15:0] seq_hr_chan_reg2;
wire [15:0] seq_hr_chan_reg3;
wire [47:0] seq_hr_chan_reg_comb;
wire [15:0] seq_lr_chan_reg1;
wire [15:0] seq_lr_chan_reg2;
wire [15:0] seq_lr_chan_reg3;
wire [47:0] seq_lr_chan_reg_comb;
wire [15:0] seq_acq_ext_reg1;
wire [15:0] seq_acq_ext_reg2;
wire [47:0] seq_acq_ext_reg_comb;
wire [15:0] seq_avg_reg1;
wire [15:0] seq_avg_reg2;
wire [15:0] seq_avg_reg3;
wire [15:0] seq_bipolar_reg1;
wire [15:0] seq_bipolar_reg2;
wire [47:0] seq_bipolar_reg_comb;
reg [5:0] seq_curr_i, seq_curr_ia;
integer busy_rst_cnt;
reg [5:0] si;
integer kk;
integer hr_tot_chan;
integer lr_tot_chan;
wire [15:0] int_tot_per;
wire [15:0] hr_lr_tot_per;
wire [15:0] tot_per;
integer seq_hr_mem [CONV_CNT_P:0];
integer seq_lr_mem [CONV_CNT_P:0];
wire lr_chan_on;
wire cont_seq_only_hr;
reg lr_calib_on;
wire sysmon_rst;
wire [15:0] cfg_reg0;
wire [15:0] cfg_reg1;
wire [15:0] cfg_reg2;
wire [15:0] cfg_reg3;
wire [15:0] cfg_reg4;
reg reserved_addr_pre;
reg read_only_pre;
//blh tests related
wire blh_test=0;
integer blh_read_index=0;
reg RESERVED_ADDR;
reg READ_ONLY;
wire convst_in_ored;
wire convst_in_pre;
wire rst_in_not_seq;
wire gsr_in;
reg [1:0] lr_eos ;
reg [1:0] lr_rate;
real i2c_vpvn_addr_tmp;
integer i2c_conv_result_int;
reg i2c_en;
reg i2c_oride;
reg [6:0] i2c_device_addr;
reg [6:0] i2c_device_addr_vpvn;
reg [15:0] conv_result_i2c_addr;
wire i2c_wr_exec;
wire [15:0] i2c_drp_data;
wire [9:0] i2c_drp_addr;
wire pmb_en_bit;
wire pmb_en;
reg [7:0] pmb_sel_addr; //select address for MFR command
reg [7 :0] pmb_drsram_addr;
reg [15:0] pmb_drsram_wr_data;
reg [3:0] pmb_drsram_bit_idx;
reg [7:0] pmb_drsram_addr_page;
reg pmb_valid_page;
reg pmb_wr_exec;
reg [7:0] pmb_cmd_in;
reg [15:0] pmb_data_in;
wire [3:0] bank_sel_6V; //indicates if 6V bank has been selected for vuser0-3.
assign JTAGBUSY_out = 0;
assign JTAGLOCKED_out = 0;
assign JTAGMODIFIED_out = 0;
assign gsr_in = glblGSR;
//--------------------------------------------------
//--------------------------------------------------
integer out_counter;
integer ed_counter;
integer cs_counter;
integer cal_counter;
reg out_counter_inc;
reg ed_counter_inc;
wire chan_asrt_1;
wire chan_asrt_2;
wire chan_asrt_3;
reg chan_asrt_4;
reg chan_asrt_5;
reg chan_asrt_6;
wire alm_asrt;
wire eoc_asrt;
wire busy_start;
wire busy_end;
wire busy_end_out;
wire busy_start_ed;
wire busy_start_cs;
reg busy_start_cs_d;
wire busy_end_ed;
wire busy_end_ed_out;
wire busy_end_ed_wait;
wire busy_end_cs;
wire busy_end_cs_out;
reg busy_end_d;
reg busy_end_out_d;
wire busy_end_pe;
wire chan_asrt;
wire chan_asrt_ed;
wire chan_asrt_cs;
wire chan_asrt_pe;
wire chan_asrt_dclk;
reg chan_asrt_d;
wire conv_track;
wire conv_track_ed;
wire conv_track_cs;
wire cal_end_level;
reg cal_end_level_d;
wire cal_end;
wire convst_pre_dclk_pe;
wire convst_pre_adcclk_pe;
reg convst_saved;
reg convst_adcclk_d1;
reg convst_adcclk_d2;
reg convst_dclk_d1;
reg one_pass_end;
wire [3:0] cal_factor;
wire [3:0] cal_factor2;
wire [8:0] first_cal_limit;
wire [8:0] later_cal_limit;
wire [5:0] conv_period;
wire [4:0] busy_start_point;
wire [4:0] cs_count_tot;
wire [8:0] cal_limit;
reg conversion_before_calib;
reg tot_final_conversion;
reg hr_final_conversion;
reg lr_final_conversion;
wire acq_ext;
reg acq_ext_cur;
reg acq_ext_cur_d;
reg bipolar_cur;
reg avg_cur;
integer chan_reg_id_cur; // the index number for accessing configuration registers
integer chan_out_id_cur; // the number that shows up at the output
reg acq_ext_next;
reg bipolar_next;
reg avg_next;
integer chan_reg_id_next;
integer chan_out_id_next;
// initialize chan_val and chan_valn
integer ii, jj;
initial begin
for (ii = 0; ii < CONV_CNT_P; ii = ii + 1)
chan_val[ii] = 64'd0;
for (jj = 0; jj < 36; jj = jj + 1)
chan_valn[jj] = 64'd0;
end
// initialize vauxn_idx and vauxp_idx
integer mm, nn;
initial begin
for (mm = 0; mm < 16; mm = mm + 1)
vauxn_idx[mm] = -1;
for (nn = 0; nn < 16; nn = nn + 1)
vauxp_idx[nn] = -1;
end
initial begin
i2c_en = 1;
pmb_sel_addr = 0;
end
// I2C slave address mapping
always @(*) begin
i2c_oride = cfg_reg3[15];
i2c_device_addr = (i2c_oride) ? cfg_reg3[14:8]: i2c_device_addr_vpvn;
end
assign convst_in_ored = (CONVST_in===1 || CONVSTCLK_in===1) ? 1: 0;
assign convst_in_pre = sysmon_rst ? 0 : (convst_in_ored && event_driven_mode & ~BUSY_out);
integer dd;
always @(posedge trig_attr) begin
dr_sram[8'h40] = INIT_40_BIN;
dr_sram[8'h41] = INIT_41_BIN;
dr_sram[8'h42] = INIT_42_BIN;
dr_sram[8'h43] = INIT_43_BIN;
dr_sram[8'h44] = INIT_44_BIN;
dr_sram[8'h45] = INIT_45_BIN;
dr_sram[8'h46] = INIT_46_BIN;
dr_sram[8'h47] = INIT_47_BIN;
dr_sram[8'h48] = INIT_48_BIN;
dr_sram[8'h49] = INIT_49_BIN;
dr_sram[8'h4A] = INIT_4A_BIN;
dr_sram[8'h4B] = INIT_4B_BIN;
dr_sram[8'h4C] = INIT_4C_BIN;
dr_sram[8'h4D] = INIT_4D_BIN;
dr_sram[8'h4E] = INIT_4E_BIN;
dr_sram[8'h4F] = INIT_4F_BIN;
dr_sram[8'h50] = INIT_50_BIN;
dr_sram[8'h51] = INIT_51_BIN;
dr_sram[8'h52] = INIT_52_BIN;
// User can overwrite the ot_limit_reg only while enabling automatic shutdown.
// Otherwise default value will be kept.
tmp_otv = INIT_53_BIN;
if (tmp_otv [3:0] == 4'b0011) begin
dr_sram[8'h53] = INIT_53_BIN;
ot_limit_reg = INIT_53_BIN;
$display("Info: [Unisim %s-20] OT upper limit has been overwritten and automatic shutdown bits have been set 53h = h%0h. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, INIT_53_BIN, $time/1000.0,);
end
else begin
dr_sram[8'h53] = 16'hCB00;
ot_limit_reg = 16'hCB00; // default value for OT is 125C
end
dr_sram[8'h54] = INIT_54_BIN;
dr_sram[8'h55] = INIT_55_BIN;
dr_sram[8'h56] = INIT_56_BIN;
dr_sram[8'h57] = INIT_57_BIN;
dr_sram[8'h58] = INIT_58_BIN;
dr_sram[8'h59] = INIT_59_BIN;
dr_sram[8'h5A] = INIT_5A_BIN;
dr_sram[8'h5B] = INIT_5B_BIN;
dr_sram[8'h5C] = INIT_5C_BIN;
dr_sram[8'h5D] = INIT_5D_BIN;
dr_sram[8'h5E] = INIT_5E_BIN;
dr_sram[8'h5F] = INIT_5F_BIN;
dr_sram[8'h60] = INIT_60_BIN;
dr_sram[8'h61] = INIT_61_BIN;
dr_sram[8'h62] = INIT_62_BIN;
dr_sram[8'h63] = INIT_63_BIN;
dr_sram[8'h68] = INIT_68_BIN;
dr_sram[8'h69] = INIT_69_BIN;
dr_sram[8'h6A] = INIT_6A_BIN;
dr_sram[8'h6B] = INIT_6B_BIN;
dr_sram[8'h78] = INIT_78_BIN;
dr_sram[8'h79] = INIT_79_BIN;
dr_sram[8'h7A] = INIT_7A_BIN;
dr_sram[8'h7B] = INIT_7B_BIN;
dr_sram[8'h7C] = INIT_7C_BIN;
for (dd=8'h80; dd<8'hFF; dd=dd+1)
dr_sram[dd] = 0;
dr_sram[8'hA8] = 16'hFFFF; //min vuser0
dr_sram[8'hA9] = 16'hFFFF;
dr_sram[8'hAA] = 16'hFFFF;
dr_sram[8'hAB] = 16'hFFFF;
end // always @ (trig_attr)
// read input file
initial begin
char_1 = 0;
char_2 = 0;
time_out = 0;
sim_file_flag = 0;
file_line = -1;
end_of_file = 0;
fd = $fopen(SIM_MONITOR_FILE, "r");
if (fd == 0) begin
$display("Error: [Unisim %s-4] The analog data file %s was not found. Use the SIM_MONITOR_FILE parameter to specify the analog data file name or use the default name: design.txt. Instance: %m", MODULE_NAME, SIM_MONITOR_FILE);
sim_file_flag = 1;
#1 $finish;
end
if (sim_file_flag == 0) begin
while (end_of_file==0) begin
file_line = file_line + 1;
char_1 = $fgetc (fd);
char_2 = $fgetc (fd);
//if(char_2==`EOFile)
if(char_2== -1)
end_of_file = 1;
else begin // not end of file
// Ignore Comments
if ((char_1 == "/" & char_2 == "/") | char_1 == "#" | (char_1 == "-" & char_2 == "-")) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
// Getting labels
else if ((char_1 == "T" & char_2 == "I" ) ||
(char_1 == "T" & char_2 == "i" ) ||
(char_1 == "t" & char_2 == "i" ) || (char_1 == "t" & char_2 == "I" )) begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
num_arg = $sscanf (one_line, "%s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s %s ",
label0, label1, label2, label3, label4, label5, label6, label7, label8, label9, label10, label11, label12, label13, label14, label15, label16, label17, label18, label19, label20, label21, label22, label23, label24, label25, label26, label27, label28, label29, label30,label31, label32, label33, label34, label35, label36, label37, label38, label39, label40, label41, label42, label43, label44, label45, label46);
label[0] = label0;
label[1] = label1;
label[2] = label2;
label[3] = label3;
label[4] = label4;
label[5] = label5;
label[6] = label6;
label[7] = label7;
label[8] = label8;
label[9] = label9;
label[10] = label10;
label[11] = label11;
label[12] = label12;
label[13] = label13;
label[14] = label14;
label[15] = label15;
label[16] = label16;
label[17] = label17;
label[18] = label18;
label[19] = label19;
label[20] = label20;
label[21] = label21;
label[22] = label22;
label[23] = label23;
label[24] = label24;
label[25] = label25;
label[26] = label26;
label[27] = label27;
label[28] = label28;
label[29] = label29;
label[30] = label30;
label[31] = label31;
label[32] = label32;
label[33] = label33;
label[34] = label34;
label[35] = label35;
label[36] = label36;
label[37] = label37;
label[38] = label38;
label[39] = label39;
label[40] = label40;
label[41] = label41;
label[42] = label42;
label[43] = label43;
label[44] = label44;
label[45] = label45;
label[46] = label46;
for (m = 0; m < num_arg; m = m +1) begin
tmp_label = 96'b0;
tmp_label = to_upcase_label(label[m]);
case (tmp_label)
"TEMP" : temperature_index = m;
"TIME" : time_index = m;
"VCCAUX" : vccaux_index = m;
"VCCINT" : vccint_index = m;
"VCCBRAM" : vccbram_index = m;
"VCCPSINTLP",
"VCC_PSINTLP" :
begin
vccpsintlp_index = m;
if (SIM_DEVICE != "ZYNQ_ULTRASCALE" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2")
$display("Error: [Unisim %s-22] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label);
if ("VCCPSINTLP" == tmp_label)
$display("Error: [Unisim %s-47] The channel name %s is deprecated. Please use VCC_PSINTLP instead. Instance: %m", MODULE_NAME, tmp_label);
end
"VCCPSINTFP",
"VCC_PSINTFP" :
begin
vccpsintfp_index = m;
if (SIM_DEVICE != "ZYNQ_ULTRASCALE" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2")
$display("Error: [Unisim %s-23] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label);
if ("VCCPSINTFP" == tmp_label)
$display("Error: [Unisim %s-48] The channel name %s is deprecated. Please use VCC_PSINTFP instead. Instance: %m", MODULE_NAME, tmp_label);
end
"VCCPSAUX",
"VCC_PSAUX" : begin
vccpsaux_index = m;
if (SIM_DEVICE != "ZYNQ_ULTRASCALE" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES1" &&
SIM_DEVICE != "ZYNQ_ULTRASCALE_ES2")
$display("Error: [Unisim %s-24] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label);
if ("VCCPSAUX" == tmp_label)
$display("Error: [Unisim %s-49] The channel name %s is deprecated. Please use VCC_PSAUX instead. Instance: %m", MODULE_NAME, tmp_label);
end
"VN" : vn_index = m;
"VAUXN[0]" : vauxn_idx[0] = m;
"VAUXN[1]" : vauxn_idx[1] = m;
"VAUXN[2]" : vauxn_idx[2] = m;
"VAUXN[3]" : vauxn_idx[3] = m;
"VAUXN[4]" : vauxn_idx[4] = m;
"VAUXN[5]" : vauxn_idx[5] = m;
"VAUXN[6]" : vauxn_idx[6] = m;
"VAUXN[7]" : vauxn_idx[7] = m;
"VAUXN[8]" : vauxn_idx[8] = m;
"VAUXN[9]" : vauxn_idx[9] = m;
"VAUXN[10]" : vauxn_idx[10] = m;
"VAUXN[11]" : vauxn_idx[11] = m;
"VAUXN[12]" : vauxn_idx[12] = m;
"VAUXN[13]" : vauxn_idx[13] = m;
"VAUXN[14]" : vauxn_idx[14] = m;
"VAUXN[15]" : vauxn_idx[15] = m;
"VP" : vp_index = m;
"VAUXP[0]" : vauxp_idx[0] = m;
"VAUXP[1]" : vauxp_idx[1] = m;
"VAUXP[2]" : vauxp_idx[2] = m;
"VAUXP[3]" : vauxp_idx[3] = m;
"VAUXP[4]" : vauxp_idx[4] = m;
"VAUXP[5]" : vauxp_idx[5] = m;
"VAUXP[6]" : vauxp_idx[6] = m;
"VAUXP[7]" : vauxp_idx[7] = m;
"VAUXP[8]" : vauxp_idx[8] = m;
"VAUXP[9]" : vauxp_idx[9] = m;
"VAUXP[10]" : vauxp_idx[10] = m;
"VAUXP[11]" : vauxp_idx[11] = m;
"VAUXP[12]" : vauxp_idx[12] = m;
"VAUXP[13]" : vauxp_idx[13] = m;
"VAUXP[14]" : vauxp_idx[14] = m;
"VAUXP[15]" : vauxp_idx[15] = m;
"VUSER0" : vuser0_index = m;
"VUSER1" : vuser1_index = m;
"VUSER2" : vuser2_index = m;
"VUSER3" : vuser3_index = m;
//"VCCAMS" : vccams_index = m;
default : begin
$display("Error: [Unisim %s-5] The channel name %s is invalid in the input file. Instance: %m", MODULE_NAME, tmp_label);
infile_format;
end
endcase
end // for (m = 0; m < num_arg; m = m +1)
// COMMON_N_SOURCE
if(COMMON_N_SOURCE != 16'hFFFF && vauxn_idx[COMMON_N_SOURCE[3:0]] == -1) begin
$display("Warning: [Unisim %s-58]: Common-N Source is selected as VAUXN[%0d]. This input does not exist in the stimulus file. It must be provided.",
MODULE_NAME, COMMON_N_SOURCE[3:0]);
for (n = 0; n < 16; n = n + 1) begin
if ((vauxn_idx[n] == -1) && (vauxp_idx[n] != -1))
vauxn_idx[n] = vauxn_idx[COMMON_N_SOURCE[3:0]];
end // for
end
end // Getting labels
// Getting column values
else if (char_1 ==" " | char_1 == "0" | char_1 == "1" | char_1 == "2" | char_1 == "3" | char_1 == "4" | char_1 == "5" | char_1 == "6" | char_1 == "7" | char_1 == "8" | char_1 == "9") begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
column_real0 = 0.0;
column_real1 = 0.0;
column_real2 = 0.0;
column_real3 = 0.0;
column_real4 = 0.0;
column_real5 = 0.0;
column_real6 = 0.0;
column_real7 = 0.0;
column_real8 = 0.0;
column_real9 = 0.0;
column_real10 = 0.0;
column_real11 = 0.0;
column_real12 = 0.0;
column_real13 = 0.0;
column_real14 = 0.0;
column_real15 = 0.0;
column_real16 = 0.0;
column_real17 = 0.0;
column_real18 = 0.0;
column_real19 = 0.0;
column_real20 = 0.0;
column_real21 = 0.0;
column_real22 = 0.0;
column_real23 = 0.0;
column_real24 = 0.0;
column_real25 = 0.0;
column_real26 = 0.0;
column_real27 = 0.0;
column_real28 = 0.0;
column_real29 = 0.0;
column_real30 = 0.0;
column_real31 = 0.0;
column_real32 = 0.0;
column_real33 = 0.0;
column_real34 = 0.0;
column_real35 = 0.0;
column_real36 = 0.0;
column_real37 = 0.0;
column_real38 = 0.0;
column_real39 = 0.0;
column_real40 = 0.0;
column_real41 = 0.0;
column_real42 = 0.0;
column_real43 = 0.0;
column_real44 = 0.0;
column_real45 = 0.0;
column_real46 = 0.0;
num_val = $sscanf (one_line, "%f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f %f", column_real0, column_real1, column_real2, column_real3, column_real4, column_real5, column_real6, column_real7, column_real8, column_real9, column_real10, column_real11, column_real12, column_real13, column_real14, column_real15, column_real16, column_real17, column_real18, column_real19, column_real20, column_real21, column_real22, column_real23, column_real24, column_real25, column_real26, column_real27, column_real28, column_real29, column_real30, column_real31, column_real32, column_real33, column_real34, column_real35, column_real36, column_real37, column_real38, column_real39, column_real40, column_real41, column_real42, column_real43, column_real44, column_real45, column_real46);
column_real[0] = $realtobits(column_real0);
column_real[1] = $realtobits(column_real1);
column_real[2] = $realtobits(column_real2);
column_real[3] = $realtobits(column_real3);
column_real[4] = $realtobits(column_real4);
column_real[5] = $realtobits(column_real5);
column_real[6] = $realtobits(column_real6);
column_real[7] = $realtobits(column_real7);
column_real[8] = $realtobits(column_real8);
column_real[9] = $realtobits(column_real9);
column_real[10] = $realtobits(column_real10);
column_real[11] = $realtobits(column_real11);
column_real[12] = $realtobits(column_real12);
column_real[13] = $realtobits(column_real13);
column_real[14] = $realtobits(column_real14);
column_real[15] = $realtobits(column_real15);
column_real[16] = $realtobits(column_real16);
column_real[17] = $realtobits(column_real17);
column_real[18] = $realtobits(column_real18);
column_real[19] = $realtobits(column_real19);
column_real[20] = $realtobits(column_real20);
column_real[21] = $realtobits(column_real21);
column_real[22] = $realtobits(column_real22);
column_real[23] = $realtobits(column_real23);
column_real[24] = $realtobits(column_real24);
column_real[25] = $realtobits(column_real25);
column_real[26] = $realtobits(column_real26);
column_real[27] = $realtobits(column_real27);
column_real[28] = $realtobits(column_real28);
column_real[29] = $realtobits(column_real29);
column_real[30] = $realtobits(column_real30);
column_real[31] = $realtobits(column_real31);
column_real[32] = $realtobits(column_real32);
column_real[33] = $realtobits(column_real33);
column_real[34] = $realtobits(column_real34);
column_real[35] = $realtobits(column_real35);
column_real[36] = $realtobits(column_real36);
column_real[37] = $realtobits(column_real37);
column_real[38] = $realtobits(column_real38);
column_real[39] = $realtobits(column_real39);
column_real[40] = $realtobits(column_real40);
column_real[41] = $realtobits(column_real41);
column_real[42] = $realtobits(column_real42);
column_real[43] = $realtobits(column_real43);
column_real[44] = $realtobits(column_real44);
column_real[45] = $realtobits(column_real45);
column_real[46] = $realtobits(column_real46);
chan_val[0] = column_real[temperature_index];
chan_val[1] = column_real[vccint_index];
chan_val[2] = column_real[vccaux_index];
chan_val[3] = column_real[vp_index];
chan_val[6] = column_real[vccbram_index];
chan_val[13] = column_real[vccpsintlp_index];
chan_val[14] = column_real[vccpsintfp_index];
chan_val[15] = column_real[vccpsaux_index];
chan_val[16] = column_real[vauxp_idx[0]];
chan_val[17] = column_real[vauxp_idx[1]];
chan_val[18] = column_real[vauxp_idx[2]];
chan_val[19] = column_real[vauxp_idx[3]];
chan_val[20] = column_real[vauxp_idx[4]];
chan_val[21] = column_real[vauxp_idx[5]];
chan_val[22] = column_real[vauxp_idx[6]];
chan_val[23] = column_real[vauxp_idx[7]];
chan_val[24] = column_real[vauxp_idx[8]];
chan_val[25] = column_real[vauxp_idx[9]];
chan_val[26] = column_real[vauxp_idx[10]];
chan_val[27] = column_real[vauxp_idx[11]];
chan_val[28] = column_real[vauxp_idx[12]];
chan_val[29] = column_real[vauxp_idx[13]];
chan_val[30] = column_real[vauxp_idx[14]];
chan_val[31] = column_real[vauxp_idx[15]];
chan_val[32] = column_real[vuser0_index];
chan_val[33] = column_real[vuser1_index];
chan_val[34] = column_real[vuser2_index];
chan_val[35] = column_real[vuser3_index];
chan_valn[3] = column_real[vn_index];
chan_valn[16] = column_real[vauxn_idx[0]];
chan_valn[17] = column_real[vauxn_idx[1]];
chan_valn[18] = column_real[vauxn_idx[2]];
chan_valn[19] = column_real[vauxn_idx[3]];
chan_valn[20] = column_real[vauxn_idx[4]];
chan_valn[21] = column_real[vauxn_idx[5]];
chan_valn[22] = column_real[vauxn_idx[6]];
chan_valn[23] = column_real[vauxn_idx[7]];
chan_valn[24] = column_real[vauxn_idx[8]];
chan_valn[25] = column_real[vauxn_idx[9]];
chan_valn[26] = column_real[vauxn_idx[10]];
chan_valn[27] = column_real[vauxn_idx[11]];
chan_valn[28] = column_real[vauxn_idx[12]];
chan_valn[29] = column_real[vauxn_idx[13]];
chan_valn[30] = column_real[vauxn_idx[14]];
chan_valn[31] = column_real[vauxn_idx[15]];
// identify columns
if (time_index != -1) begin
prev_time_out = time_out;
time_out = $bitstoreal(column_real[time_index]);
if (prev_time_out > time_out) begin
$display("Error: [Unisim %s-6] Time value %f is invalid in the input file. Time value should be increasing. Instance: %m", MODULE_NAME, time_out);
infile_format;
end
end
else begin
$display("Error: [Unisim %s-7] No TIME label is found in the analog data file. Instance: %m", MODULE_NAME);
infile_format;
#1 $finish;
end
# ((time_out - prev_time_out) * 1000);
for (p = 0; p < CONV_CNT_P; p = p + 1) begin
// assign to real before minus - to work around a bug in modelsim
chan_val_tmp[p] = chan_val[p];
chan_valn_tmp[p] = chan_valn[p];
mn_in_tmp = $bitstoreal(chan_val[p]) - $bitstoreal(chan_valn[p]);
mn_in_diff[p] = $realtobits(mn_in_tmp);
mn_in_uni[p] = chan_val[p];
end
end // if (char_1 == "0" | char_1 == "9")
// Ignore any non-comment, label
else begin
fs = $ungetc (char_2, fd);
fs = $ungetc (char_1, fd);
fs = $fgets (one_line, fd);
end
end
end // while (end_file == 0)
end // if (sim_file_flag == 0)
end // initial begin
always@(posedge chan_asrt_1) begin
if(sysmon_rst==0 && blh_test==1) begin
blh_read_index = chan_out_id_next;
chan_val_tmp [blh_read_index] = chan_val[blh_read_index];
chan_valn_tmp[blh_read_index] = chan_valn[blh_read_index];
mn_in_tmp = $bitstoreal(chan_val [blh_read_index])
- $bitstoreal(chan_valn[blh_read_index]);
mn_in_diff[blh_read_index] = $realtobits(mn_in_tmp);
mn_in_uni[blh_read_index] = chan_val[blh_read_index];
end
end
// Obtain I2C slave address powerup value
always @(posedge trig_i2c_addr) begin
i2c_vpvn_addr_tmp = $bitstoreal(mn_in_uni[3]) * 65536.0;
if (i2c_vpvn_addr_tmp > 65535.0)
i2c_conv_result_int = 65535;
else if (i2c_vpvn_addr_tmp < 0.0)
i2c_conv_result_int = 0;
else begin
i2c_conv_result_int = $rtoi(i2c_vpvn_addr_tmp);
if (i2c_vpvn_addr_tmp - i2c_conv_result_int > 0.9999)
i2c_conv_result_int = i2c_conv_result_int + 1;
end
// I2C address measured and assigned at startup is recorded at address 38h
conv_result_i2c_addr = i2c_conv_result_int;
if(!i2c_oride)
data_reg[56] = i2c_conv_result_int;
// convert i2c address
case (conv_result_i2c_addr[15:12])
4'h0 : i2c_device_addr_vpvn = 7'b0110010;
4'h1 : i2c_device_addr_vpvn = 7'b0001011;
4'h2 : i2c_device_addr_vpvn = 7'b0010011;
4'h3 : i2c_device_addr_vpvn = 7'b0011011;
4'h4 : i2c_device_addr_vpvn = 7'b0100011;
4'h5 : i2c_device_addr_vpvn = 7'b0101011;
4'h6 : i2c_device_addr_vpvn = 7'b0110011;
4'h7 : i2c_device_addr_vpvn = 7'b0111011;
4'h8 : i2c_device_addr_vpvn = 7'b1000011;
4'h9 : i2c_device_addr_vpvn = 7'b1001011;
4'ha : i2c_device_addr_vpvn = 7'b1010011;
4'hb : i2c_device_addr_vpvn = 7'b1011011;
4'hc : i2c_device_addr_vpvn = 7'b1100011;
4'hd : i2c_device_addr_vpvn = 7'b1101011;
4'he : i2c_device_addr_vpvn = 7'b1110011;
4'hf : i2c_device_addr_vpvn = 7'b0111010;
default : begin
i2c_device_addr_vpvn = 7'b0000000;
//$display("Warning: [Unisim %s-25] Invalid I2C address is found. Instance: %m", MODULE_NAME);
end
endcase
end
task infile_format;
begin
$display("\n***** SYSMONE4 Simulation analog Data File Format *****\n");
$display("NAME: design.txt or user file name passed with parameter/generic SIM_MONITOR_FILE\n");
$display("FORMAT: First line is header line. Valid column name are: TIME TEMP VCCINT VCCAUX VCCBRAM VCC_PSINTLP VCC_PSINTFP VCC_PSAUX VP VN VAUXP[0] VAUXN[0] ..... \n");
$display("TIME must be in first column.\n");
$display("Time values need to be integer in ns scale.\n");
$display("Analog values need to be real and must contain a decimal point '.' , e.g. 0.0, 3.0\n");
$display("Each line including header line can not have extra space after the last character/digit.\n");
$display("Each data line must have the same number of columns as the header line.\n");
$display("Comment line can start with -- or //\n");
$display("Example:\n");
$display("TIME TEMP VCCINT VP VN VAUXP[0] VAUXN[0]\n");
$display("000 125.6 1.0 0.7 0.4 0.3 0.6\n");
$display("200 25.6 0.8 0.5 0.3 0.8 0.2\n");
end
endtask //task infile_format
function [12*8:1] to_upcase_label;
input [12*8:1] in_label;
reg [8:1] tmp_reg;
begin
for (i=0; i< 12; i=i+1) begin
for (j=1; j<=8; j= j+1)
tmp_reg[j] = in_label[i*8+j];
if ((tmp_reg >96) && (tmp_reg<123))
tmp_reg = tmp_reg -32;
for (j=1; j<=8; j= j+1)
to_upcase_label[i*8+j] = tmp_reg[j];
end
end
endfunction
// end read input file
//convert combined register index to channel output
//or vice-a-versa
function [5:0] conv_combregid_to_chanout;
input [5:0] combregid; //unsigned
begin
// invalid channel outputs are 7, 9-12, and >=36. They show up as selected via registers
if(combregid<=7)
conv_combregid_to_chanout = combregid+8;
else if(combregid>=8 && combregid<=15)
conv_combregid_to_chanout = combregid-8;
else
conv_combregid_to_chanout = combregid;
end
endfunction
always @(posedge DCLK_in or posedge sysmon_rst ) begin
if (sysmon_rst==1)
MUXADDR_out <= 5'b0;
else begin
if(ext_mux_en==0)
MUXADDR_out <= 5'b0;
else if((|initialize) || adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB)
MUXADDR_out <= 8; // stay in calibration until first channel conversion
else if(chan_asrt_6==1 || (CHANNEL_out==8 && busy_end_out_d ))
MUXADDR_out <= chan_out_id_next;
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst==1)
CHANNEL_out <= 8;
else begin
if((|initialize) || chan_asrt_6==1)
CHANNEL_out <= chan_out_id_cur;
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst==1)
ADC_DATA_out <= 0;
else if(eoc_asrt==1) begin
if (chan_out_id_cur >= 32)
ADC_DATA_out <= dr_sram[chan_out_id_cur + 96];
else if (chan_out_id_cur >= 0 && chan_out_id_cur <= 31)
ADC_DATA_out <= data_reg[chan_out_id_cur];
end
end
//-----------------------------------------------------------------
// internal reset generation
//-----------------------------------------------------------------
initial begin
alm_rst = 0;
init_rst = 1;
if (RESET_in == 1'b1) begin
@(negedge RESET_in);
end
repeat (2) @(posedge DCLK_in);
init_rst = 0;
alm_rst = 1;
repeat (2) @(posedge DCLK_in);
alm_rst = 0;
end
assign int_rst_combined = init_rst | soft_rst | seq_rst; //all internally generated
assign #10 int_rst_combined_d = int_rst_combined;
assign sysmon_rst = int_rst_sync2 | RESET_in | gsr_in; //combined reset
initial begin
int_rst_sync1 = 0;
int_rst_sync2 = 0;
end
//synchronize internally generated reset to adcclk
always@(posedge adcclk or posedge int_rst_combined_d) begin
if (int_rst_combined_d) begin
int_rst_sync1 <= 1;
int_rst_sync2 <= 1;
end
else begin
int_rst_sync1 <= int_rst_combined_d;
int_rst_sync2 <= int_rst_sync1;
end
end
always @(posedge sysmon_rst or posedge DCLK_in) begin
if(sysmon_rst )
initialize <= 3'b001;
else
initialize <= {initialize[1:0],1'b0};
end
initial begin
sysclk = 0;
adcclk_tmp = 0;
adcclk_count = -1;
//for (i = 0; i <=63; i = i +1) begin
// conv_acc[i] = 0;
//end
DADDR_in_lat = 0;
//data registers reset
for (k = 0; k <= 31; k = k + 1) begin
data_reg[k] = 16'h0000;
end
//min and max registers' reset value assignments
data_reg[32] = 16'h0000;
data_reg[33] = 16'h0000;
data_reg[34] = 16'h0000;
data_reg[35] = 16'h0000;
data_reg[36] = 16'hFFFF;
data_reg[37] = 16'hFFFF;
data_reg[38] = 16'hFFFF;
data_reg[39] = 16'hFFFF;
data_reg[40] = 16'h0000;
data_reg[41] = 16'h0000;
data_reg[42] = 16'h0000;
data_reg[43] = 16'h0000; //reserved
data_reg[44] = 16'hFFFF;
data_reg[45] = 16'hFFFF;
data_reg[46] = 16'hFFFF;
data_reg[47] = 16'h0000; //reserved
ot_out_reg = 0;
OT_out = 0;
alm_out_reg = 0;
ALM_out = 0;
hr_tot_chan = 0;
lr_tot_chan = 0;
ot_en = 1;
alm_en = 13'h1FFF;
DO_out_rdtmp = 0;
conv_result_int = 0;
conv_result = 0;
conv_result_reg = 0;
READ_ONLY = 0;
reserved_addr_pre = 0;
lr_calib_on = 0;
end //end of initial
//----------------------------------------------------------------
// ADC state machine
// to manage timing of output ports CHANNEL, BUSY, EOC, EOS, ALM
//----------------------------------------------------------------
always @(*) begin
if(sysmon_rst || (|initialize))
adc_next_state<= ST_A_FIRST_CALIB;
else begin
case (adc_state)
ST_A_FIRST_CALIB : if(cont_sampl_mode && cal_end && !single_pass_finished)
adc_next_state <= ST_A_CHAN;
else if(event_driven_mode && cal_end)
adc_next_state <= ST_A_WAIT_ED;
ST_A_CALIB : if(cont_sampl_mode && cal_end && !single_pass_mode)
adc_next_state <= ST_A_CHAN;
else if(event_driven_mode && cal_end) begin
if(convst_pre_adcclk_pe)
adc_next_state <= ST_A_CHAN;
else
adc_next_state <= ST_A_WAIT_ED;
end
ST_A_WAIT_ED : if(convst_pre_adcclk_pe)
adc_next_state <= ST_A_WAIT;
ST_A_WAIT : if(cont_sampl_mode && single_pass_mode && hr_final_conversion && acq_ext_cur) begin
if(BUSY_out)
adc_next_state <= ST_A_FIRST_CALIB;
else
adc_next_state <= ST_A_WAIT;
end
else if(conversion_before_calib && !single_chan_mode && chan_asrt_dclk )
adc_next_state <= ST_A_CALIB;
else if(chan_asrt_dclk)
adc_next_state <= ST_A_CHAN;
ST_A_CHAN : if(convst_pre_adcclk_pe )
adc_next_state <= ST_A_WAIT;
else if (alm_asrt)
adc_next_state <= ST_A_ALM;
ST_A_ALM : if(convst_pre_adcclk_pe )
adc_next_state <= ST_A_WAIT;
else if(eoc_asrt)
adc_next_state <= ST_A_EOC;
ST_A_EOC : if(convst_pre_adcclk_pe )
adc_next_state <= ST_A_WAIT;
else if(cont_sampl_mode && single_pass_mode && hr_final_conversion && !acq_ext_cur)
adc_next_state <= ST_A_FIRST_CALIB;
else if (event_driven_mode)
adc_next_state <= ST_A_WAIT_ED;
else
adc_next_state <= ST_A_WAIT;
default : adc_next_state <= ST_A_FIRST_CALIB;
endcase
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
adc_state <= ST_A_FIRST_CALIB;
else
adc_state <= adc_next_state;
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
adc_state_d_dclk <= ST_A_FIRST_CALIB;
else
adc_state_d_dclk <= adc_state;
end
always @(posedge adcclk or posedge sysmon_rst) begin
if(sysmon_rst)
adc_state_d = ST_A_FIRST_CALIB;
else begin
#1;
adc_state_d = adc_state;
end
end
// signal to stay high until the end of the first ST_A_CHAN
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
st_first_calib_chan <=1;
else begin
if(adc_state==ST_A_CHAN && adc_next_state!=ST_A_CHAN)
st_first_calib_chan <=0;
end
end
assign chan_asrt_1 = chan_asrt_pe;
assign #1 chan_asrt_2 = chan_asrt_1;
assign #1 chan_asrt_3 = chan_asrt_2;
assign alm_asrt = (out_counter == alm_distance) && !(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB);
assign eoc_asrt = (out_counter == eoc_distance) && !(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB);
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
chan_asrt_4 <= 0;
chan_asrt_5 <= 0;
chan_asrt_6 <= 0;
end
else begin
chan_asrt_4 <= chan_asrt_3;
chan_asrt_5 <= chan_asrt_4;
chan_asrt_6 <= busy_end_pe;
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
out_counter <= 0;
else begin
if(chan_asrt_dclk ||
(cal_end && (adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB)) ||
out_counter == eoc_distance)
out_counter <= 0;
else if(out_counter_inc)// && adc_state!=ST_A_CALIB)
out_counter <= out_counter + 1;
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
out_counter_inc <=0;
else begin
if (chan_asrt_dclk)
out_counter_inc <=1;
else if(out_counter == eoc_distance-1)
out_counter_inc <=0;
end
end
//acquisition extension
assign acq_ext = cfg_reg0[8];
//event driven mode busy generation
assign busy_start_ed = (ed_counter == 1 && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB);
assign busy_end_ed = (ed_counter == 22 || (busy_end_ed_wait && ~convst_saved)); //&&first calib or calib might be better.
assign busy_end_ed_out = (busy_end_ed && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB);
assign chan_asrt_ed = (ed_counter == 21);
assign conv_track_ed = ((ed_counter == 0||ed_counter==22) && CHANNEL_out!=8 );
assign busy_end_ed_wait = (adc_state == ST_A_WAIT_ED && adc_state_d_dclk != ST_A_WAIT_ED);
always @(posedge adcclk or posedge sysmon_rst or posedge convst_pre_dclk_pe) begin
if(sysmon_rst || convst_pre_dclk_pe)
ed_counter <= 0;
else begin
if(!ed_counter_inc || adc_state_d==ST_A_FIRST_CALIB || adc_state_d==ST_A_CALIB || adc_state==ST_A_WAIT_ED )
ed_counter <= 0;
else if(ed_counter_inc)
ed_counter <= ed_counter + 1;
end
end
always @(posedge sysmon_rst or posedge DCLK_in) begin
if(sysmon_rst)
ed_counter_inc <=0;
else begin
if(convst_pre_adcclk_pe && !(adc_state_d==ST_A_FIRST_CALIB || adc_state_d==ST_A_CALIB))
ed_counter_inc <=1;
else if(ed_counter==22)
ed_counter_inc <=0;
end
end
//continuous sampling mode busy generation
assign busy_start_point= (acq_ext_cur_d) ? 5'd10 : 5'd4;
assign cs_count_tot = (acq_ext_cur_d) ? 5'd31 : 5'd25;
assign busy_start_cs = (cs_counter == busy_start_point && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB) ||
(cal_counter==4 && adc_state==ST_A_CALIB) ;
assign busy_end_cs = (cs_counter == 0 && adc_state!=ST_A_FIRST_CALIB );
assign busy_end_cs_out = (cs_counter == 0 && adc_state!=ST_A_FIRST_CALIB && adc_state!=ST_A_CALIB);
assign chan_asrt_cs = (cs_counter == cs_count_tot);
assign conv_track_cs = (cs_counter == 0 && adc_state==ST_A_CHAN);
always @(posedge adcclk or posedge sysmon_rst) begin
if(sysmon_rst) begin
cs_counter <= 0;
acq_ext_cur_d <=0;
end
else begin
if(cs_counter==cs_count_tot || adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB) begin
cs_counter <= 0;
acq_ext_cur_d <= acq_ext_cur;
end
else if(cs_counter < cs_count_tot)
cs_counter <= cs_counter + 1;
end
end
assign busy_start = initialize[2] || (event_driven_mode && busy_start_ed) || (~event_driven_mode && busy_start_cs_d);
assign busy_end = (event_driven_mode && busy_end_ed) || (~event_driven_mode && busy_end_cs);
assign busy_end_out = (event_driven_mode && busy_end_ed_out)|| (~event_driven_mode && busy_end_cs_out);
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
BUSY_out <= 0;
else begin
if(busy_start)
BUSY_out <= 1;
else if (busy_end_out)
BUSY_out <= 0;
end
end
assign chan_asrt = (event_driven_mode && chan_asrt_ed) || (~event_driven_mode && chan_asrt_cs);
assign chan_asrt_pe = chan_asrt & ~chan_asrt_d;
assign chan_asrt_dclk = (curr_clkdiv_sel>2) ? (chan_asrt & adcclk_period_end_d) : (chan_asrt & chan_asrt_d) ;
assign busy_end_pe = busy_end & ~busy_end_d;
assign conv_track = event_driven_mode ? conv_track_ed : conv_track_cs;
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
chan_asrt_d <= 0;
busy_start_cs_d <= 0;
busy_end_d <= 0;
busy_end_out_d <= 0;
end
else begin
chan_asrt_d <= chan_asrt;
busy_start_cs_d <= busy_start_cs;
busy_end_d <= busy_end;
busy_end_out_d <= busy_end_out;
end
end
// BUSY should assert 1 dclk cycle after next adcclk posedge after convst_in_pre
assign convst_pre_adcclk_pe = convst_in_pre & ~convst_adcclk_d2;
assign convst_pre_dclk_pe = convst_in_pre & ~convst_dclk_d1;
always @(posedge adcclk or posedge sysmon_rst) begin
if(sysmon_rst) begin
convst_adcclk_d1 <= 0;
convst_adcclk_d2 <= 0;
end
else begin
convst_adcclk_d1 <= convst_in_pre ;
convst_adcclk_d2 <= convst_adcclk_d1 ;
end
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
convst_dclk_d1 <= 0;
else
convst_dclk_d1 <= convst_in_pre;
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
convst_saved <= 0;
end
else begin
if(convst_pre_adcclk_pe && (adc_state==ST_A_CHAN || adc_state==ST_A_ALM))
convst_saved <= 1;
else if (adc_state==ST_A_WAIT || busy_end)
convst_saved <= 0;
end
end
// Calibration timing
// calibration period in effect is cal_factor * conversion period
assign cal_factor = single_chan_mode? 1: 3; // short calibration for single channel mode to mimick coming out of reset
assign cal_factor2 = 3;
assign conv_period = event_driven_mode ? 22 : (26+(acq_ext_cur_d ? 6 : 0)) ;
assign first_cal_limit = (cal_factor -1)*conv_period +1;
assign later_cal_limit = (cal_factor2-1)*conv_period +2;
assign cal_limit = (adc_state==ST_A_FIRST_CALIB) ? first_cal_limit : later_cal_limit;
assign cal_end_level = (cal_counter==cal_limit-1) && BUSY_out;
//assign cal_end_pre = (cal_counter==cal_limit-2);
assign cal_end = cal_end_level && ~cal_end_level_d;
always @(posedge adcclk or posedge sysmon_rst) begin
if(sysmon_rst)
cal_counter <= 0;
else begin
if((conversion_before_calib && busy_end && adc_state!=ST_A_CALIB ) || adc_state==ST_A_WAIT_ED || adc_state==ST_A_WAIT)
cal_counter <= 0;
else if((adc_state==ST_A_FIRST_CALIB || adc_state==ST_A_CALIB) && cal_counter <= cal_limit-1 && BUSY_out)
cal_counter <= cal_counter + 1;
end
end
always @(posedge adcclk or posedge sysmon_rst) begin
if(sysmon_rst)
cal_end_level_d <= 0;
else
cal_end_level_d <= cal_end_level;
end
//-----------------------------------------------------------------------
// DRPORT - SRAM
//-----------------------------------------------------------------------
initial begin
DRDY_out = 0;
DRDY_out_pre1 = 0;
DRDY_out_pre2 = 0;
DRDY_out_pre3 = 0;
en_data_flag = 0;
DO_out = 16'b0;
end
// always @(posedge DRDY_out_pre3 or posedge gsr_in) begin
always @(DRDY_out_pre3 or posedge gsr_in) begin
if (gsr_in == 1)
DRDY_out <= 0;
// DRDY_out <= DRDY_out_pre3; // temp
else begin
// else if (DRDY_out_pre3) begin // temp
@(posedge DCLK_in)
DRDY_out <= 1;
@(posedge DCLK_in)
DRDY_out <= 0;
end
end
function is_reserved_address;
input [7:0] address_in;
reg is_reserved_address_pre;
begin
is_reserved_address_pre = ( address_in == 8'h07 ||
(address_in >= 8'h0B && address_in <= 8'h0C) ||
address_in == 8'h2B ||
(address_in >= 8'h2F && address_in <= 8'h37) ||
(address_in >= 8'h39 && address_in <= 8'h3D) ||
address_in == 8'h45 ||
(address_in >= 8'h64 && address_in <= 8'h67) ||
(address_in >= 8'h6C && address_in <= 8'h79) ||
(address_in >= 8'h7D && address_in <= 8'h7F) ||
(address_in >= 8'h84 && address_in <= 8'h9F) ||
(address_in >= 8'hA4 && address_in <= 8'hA7) ||
(address_in >= 8'hAC && address_in <= 8'hFF)
);
if(is_reserved_address_pre)
$display("Warning: [Unisim %s-11] The input address=h%x at time %.3f ns is accessing a RESERVED location. The data in this location is invalid. Instance: %m", MODULE_NAME, address_in, $time/1000.0);
is_reserved_address = is_reserved_address_pre;
end
endfunction
function is_readonly_address;
input [7:0] address_in;
reg is_readonly_address_pre;
begin
is_readonly_address_pre = ((address_in <= 8'h02) || // poke hole at 03 CR 993584
(address_in >= 8'h04 && address_in <= 8'h3F) ||
(address_in >= 8'h80 && address_in <= 8'hAB)
);
if(is_readonly_address_pre)
$display("Warning: [Unisim %s-19] The input address=h%x at time %.3f ns is accessing a READ ONLY location. The data won't be written. Instance: %m", MODULE_NAME, address_in, $time/1000.0);
is_readonly_address = is_readonly_address_pre;
end
endfunction
always @(posedge DCLK_in or posedge gsr_in) begin
if (gsr_in == 1) begin
DADDR_in_lat <= 8'b0;
DO_out <= 16'b0;
read_only_pre <= 0;
READ_ONLY <= 0;
RESERVED_ADDR <= 0;
// DRDY_out_pre1 <= DEN_in; // temp
// DRDY_out_pre2 <= DRDY_out_pre1; // temp
// DRDY_out_pre3 <= DRDY_out_pre2; // temp
end
else begin
if (DEN_in == 1'b1) begin
read_only_pre <= 0;
if (DRDY_out_pre1 == 1'b0) begin
DRDY_out_pre1 <= 1'b1;
en_data_flag = 1;
DADDR_in_lat <= DADDR_in;
end
else
$display("Warning: [Unisim %s-10] Input pin DEN can be high for 1 DCLK cycle only. Please wait for DRDY to be high for setting DEN to high again. Instance: %m, time: %.3f ns", MODULE_NAME, $time/1000.0);
end // if (DEN_in == 1'b1)
else
DRDY_out_pre1 <= 1'b0;
DRDY_out_pre2 <= DRDY_out_pre1;
DRDY_out_pre3 <= DRDY_out_pre2;
if (DRDY_out_pre1 == 1)
en_data_flag = 0;
if (DRDY_out_pre3 == 1) begin
RESERVED_ADDR <= reserved_addr_pre;
READ_ONLY <= read_only_pre;
if(DWE_in==0) begin
DO_out <= DO_out_rdtmp;
end
end
if (DEN_in == 1 && is_reserved_address(DADDR_in) )
reserved_addr_pre <= 1;
else if (DWE_in == 1'b1 && DEN_in == 1'b1 && en_data_flag == 1) begin
//write to all available and writable addresses.
//check write access
if (is_readonly_address(DADDR_in))
read_only_pre <= 1;
else begin
read_only_pre <= 0;
if (DADDR_in != 8'h03) begin // no dr_sram at addr 3
dr_sram[DADDR_in] <= DI_in;
end
end // not read only
end // dwe ==1
// CR-764936 in event driven mode, when doing one pass when a CONVST BUSY should assert and then an EOC be seen,
// the user can assert a CONVST again without having to write to the sequence register to start the sequence again.
// if continuous sampling, after one pass, the sequencer goes to single channel mode.
if(single_pass_finished_pe && !event_driven_mode) begin
dr_sram[8'h41][15:12] <= SEQ_SINGLE_CHAN ;//4'b0011; //from single pass, go to single channel
end
end // if (gsr == 1)
end //always
reg post_process;
reg [7:0] cfg_check_addr;
reg [15:0] cfg_in;
//post processing generalized.
always @(posedge DCLK_in or posedge gsr_in) begin
if(gsr_in) begin
post_process <= 0;
cfg_check_addr <= 0;
cfg_in <= 0;
end
else begin
if(initialize[2]) begin
post_process <= 0;
cfg_check_addr <= 0;
cfg_in <= 0;
end
else if(DEN_in && DWE_in) begin
post_process <= 1;
cfg_check_addr <= DADDR_in;
cfg_in <= DI_in;
end
else if(i2c_wr_exec) begin
post_process <= 1;
cfg_check_addr <= i2c_drp_addr[7:0];
cfg_in <= i2c_drp_data;
end
else if(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG) begin
post_process <= 1;
cfg_check_addr <= pmb_sel_addr;
cfg_in <= pmb_data_in;
end
else begin
post_process <= 0;
cfg_check_addr <= 0;
cfg_in <= 0;
end
end
end //always
//post processing generalized.
always @(posedge DCLK_in or posedge gsr_in) begin
if (gsr_in == 1) begin
soft_rst <= 0;
end
else begin
if(post_process) begin
if (cfg_check_addr == 8'h03)
soft_rst <= 1;
else if ( cfg_check_addr == 8'h53 && cfg_in[3:0] == 4'b0011)
ot_limit_reg <= cfg_in;// overwrite the OT upper limit
end
if (soft_rst == 1)
soft_rst <= 0;
end
end//always
always @(posedge post_process) begin
if(cfg_check_addr == 8'h40)
if (cfg_reg0[5:0] == 6'd7 || (cfg_reg0[5:0] >= 6'd9 && cfg_reg0[5:0] <= 6'd12) || cfg_reg0[5:0] >= 6'd36)
$display("Warning: [Unisim %s-14] Config register 0 bits [5:0] at 40h cannot not be set to an invalid analog channel value as %0b. Instance: %m", MODULE_NAME, cfg_reg0[5:0], $time/1000.0,);
if(cfg_check_addr == 8'h40 || cfg_check_addr==8'h41)
if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (cfg_reg0[8]==1) && (cfg_reg0[5:0] != 6'd3) && !(cfg_reg0[5:0] >= 6'd16 && cfg_reg0 <= 31))
$display("Warning: [Unisim %s-15] In single channel mode if the selected channel is not analog, config register 0 bit[8] must be set to 0. Long acqusition mode is only allowed for external channels, not in single channel mode. Instance: %m", MODULE_NAME, DI_in, DADDR_in, $time/1000.0);
if(cfg_check_addr==8'h41|| cfg_check_addr==8'h46|| cfg_check_addr==8'h48|| cfg_check_addr==8'h49)
if ((cfg_reg1[15:12]==SEQ_SINGLE_CHAN) && (seq_hr_chan_reg1 != 16'h0000) && (seq_hr_chan_reg2 != 16'h0000) && (seq_hr_chan_reg3 != 16'h0000))
$display("Info: [Unisim %s-16] In single channel mode, ADC channel selection registers 46h, 48h and 49h will be ignored; these are set to %x, %x and %x respectively. Instance: %m", MODULE_NAME, seq_hr_chan_reg3, seq_hr_chan_reg1, seq_hr_chan_reg2, $time/1000.0);
if(cfg_check_addr==8'h41|| cfg_check_addr==8'h7A|| cfg_check_addr==8'h7B|| cfg_check_addr==8'h7C)
if ((cfg_reg1[15:12]!=SEQ_CONT_CHAN) && (seq_lr_chan_reg1 != 16'h0000) && (seq_lr_chan_reg2 != 16'h0000) && (seq_lr_chan_reg3 != 16'h0000))
$display("Info: [Unisim %s-13] In modes other than continuous sequence mode, ADC slow rate channel selection registers 7Ah, 7Bh and 7Ch will be ignored; these are set to %x, %x and %x respectively. Instance: %m", MODULE_NAME, seq_lr_chan_reg3, seq_lr_chan_reg1, seq_lr_chan_reg2, $time/1000.0);
if(cfg_check_addr == 8'h4E || cfg_check_addr==8'h41)
if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4E][10:0]!=11'd0) || (dr_sram['h4E][15:12]!=4'd0)))
$display("Info: [Unisim %s-18] The Control Register 4Eh value set is to %x. Bits [15:12] and [10:0] of this register will be ignored. Long acquistion mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0);
if(cfg_check_addr == 8'h42)
if (cfg_reg2[4:0]!=5'd0)
$display("Warning: [Unisim %s-12] The config reg 2 =h%x is invalid. Bit [4:0] must be set to 5'b00000. Instance: %m", MODULE_NAME, cfg_reg2, $time/1000.0);
if(cfg_check_addr == 8'h40)
if(cfg_reg0[13:12]!=2'b00 && !avg_en )
$display("Info: [Unisim %s-61] When cfg_reg0[13:12] is set to have averaging on: Single pass mode doesn't allow it. Continuous mode needs to have at least one channel in the high rate or low rate sequence needs to have averaging enabled. Otherwise averaging is disabled. Instance: %m", MODULE_NAME, $time/1000.0);
if(cfg_check_addr == 8'h4C || cfg_check_addr==8'h41)
if ((cfg_reg1[15:12]!=SEQ_SINGLE_CHAN) && ((dr_sram['h4C][10:0]!=11'd0) || (dr_sram['h4C][15:12]!=4'd0)))
$display("Info: [Unisim %s-17] The Control Register 4Ch value set is to %x. Bits [15:12] and [10:0] of this register will be ignored. Bipolar mode is only allowed for external channels. Instance: %m", MODULE_NAME, dr_sram['h4E], $time/1000.0);
if(cfg_check_addr == 8'h53)
if(cfg_in[3:0]==4'b0011)
$display("Info: [Unisim %s-20] OT upper limit has been overwritten and automatic shutdown bits have been set by input h%0h. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, cfg_in, $time/1000.0,);
else // cfg_in[3:0] != 4'b0011
$display("Info: [Unisim %s-21] OT upper limit can only be overwritten while enabling automatic shutdown, hence input value h%0h will be ignored and the default value will be kept. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, cfg_in, $time/1000.0,);
if(cfg_check_addr == 8'h4A)
if(cfg_in[13:12]!=2'b00 || cfg_in[0] )
$display("Info: [Unisim %s-26] Calibration, VREFP, and VREFN channels do not allow averaging. Some or all of the bits 0,12,13 of 4A are set to 1 and they will be ignored. Instance: %m", MODULE_NAME, $time/1000.0);
end // post_process
initial begin
seq_rst = 0;
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst==1)
seq_rst <= 1'b0;
else begin
if((single_pass_finished_pe && ~event_driven_mode) || //single pass finished
(DWE_in==1 && DEN_in==1 && DADDR_in==8'h41 && (DI_in[15:12]!=cfg_reg1[15:12]) ) || // switching to a different operating mode
(i2c_wr_exec && i2c_drp_addr==10'h41 && i2c_drp_data[15:12]!=cfg_reg1[15:12]) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h41 && pmb_data_in[15:12]!=cfg_reg1[15:12]) ||
(single_chan_mode && DWE_in==1 && DEN_in==1 && DADDR_in==8'h40 && (DI_in[5:0] != cfg_reg0[5:0]) ) || //change the channel selection in single channel mode
(i2c_wr_exec && i2c_drp_addr==10'h40 && i2c_drp_data[5:0]!=cfg_reg0[5:0]) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h40 && pmb_data_in[5:0]!=cfg_reg0[5:0]) ||
(pmb_wr_exec && pmb_cmd_in==CMD_PAGE) //page command adds a new channel to the sequence hence the reset
)
seq_rst <= 1'b1;
else
seq_rst <= 1'b0;
end
end //always
// If user adds a new channel to the sequences, then it will be
// added after the EOS of the last
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst==1) begin
add_channel_hr_p <= 1'b0;
add_channel_lr_p <= 1'b0;
end
else begin
if((DWE_in==1 && DEN_in==1 && DADDR_in==8'h48 && DI_in!=seq_hr_chan_reg1 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h48 && i2c_drp_data!=seq_hr_chan_reg1 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h48 && pmb_data_in!=seq_hr_chan_reg1) ||
(DWE_in==1 && DEN_in==1 && DADDR_in==8'h49 && DI_in!=seq_hr_chan_reg2 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h49 && i2c_drp_data!=seq_hr_chan_reg2 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h49 && pmb_data_in!=seq_hr_chan_reg2) ||
(DWE_in==1 && DEN_in==1 && DADDR_in==8'h46 && DI_in!=seq_hr_chan_reg3 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h46 && i2c_drp_data!=seq_hr_chan_reg3 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h46 && pmb_data_in!=seq_hr_chan_reg3)
)
add_channel_hr_p <= 1;
else if(add_channel)
add_channel_hr_p <= 0;
if((DWE_in==1 && DEN_in==1 && DADDR_in==8'h7A && DI_in!=seq_lr_chan_reg1 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h7A && i2c_drp_data!=seq_lr_chan_reg1 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7A && pmb_data_in!=seq_lr_chan_reg1) ||
(DWE_in==1 && DEN_in==1 && DADDR_in==8'h7B && DI_in!=seq_lr_chan_reg2 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h7B && i2c_drp_data!=seq_lr_chan_reg2 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7B && pmb_data_in!=seq_lr_chan_reg2) ||
(DWE_in==1 && DEN_in==1 && DADDR_in==8'h7C && DI_in!=seq_lr_chan_reg3 ) ||
(i2c_wr_exec && i2c_drp_addr==10'h7C && i2c_drp_data!=seq_lr_chan_reg3 ) ||
(pmb_wr_exec && pmb_cmd_in==CMD_MFR_ACCESS_REG && pmb_sel_addr==8'h7C && pmb_data_in!=seq_lr_chan_reg3)
)
add_channel_lr_p <= 1;
else if(add_channel)
add_channel_lr_p <= 0;
end
end //always
// DO bus data out
assign flag_reg0 = {8'b0, ALM_out[6:3], OT_out, ALM_out[2:0]};
assign flag_reg1 = {10'b0, ALM_out[13:8]};
always @(posedge DCLK or posedge gsr_in ) begin
if(gsr_in==1 )
DO_out_rdtmp <= 0;
else if(DRDY_out_pre2) begin
reserved_addr_pre = is_reserved_address(DADDR_in_lat);
if(reserved_addr_pre)
DO_out_rdtmp <= 0;
else begin //readable addresses
if (DADDR_in_lat <= 8'h3D)
DO_out_rdtmp <= data_reg[DADDR_in_lat];
else if (DADDR_in_lat == 8'h3E)
DO_out_rdtmp <= flag_reg1;
else if (DADDR_in_lat == 8'h3F)
DO_out_rdtmp <= flag_reg0;
else begin
DO_out_rdtmp <= dr_sram[DADDR_in_lat];
end
end
end
end
//-----------------------------------------------------------------------
// END of DRPORT - SRAM
//-----------------------------------------------------------------------
//-----------------------------------------------------------------------
// Configuration and settings
//-----------------------------------------------------------------------
assign cfg_reg0 = dr_sram[8'h40];
assign cfg_reg1 = dr_sram[8'h41];
assign cfg_reg2 = dr_sram[8'h42];
assign cfg_reg3 = dr_sram[8'h43];
assign cfg_reg4 = dr_sram[8'h44];
assign seq_hr_chan_reg1 = dr_sram[8'h48] & 16'h7FE1; //ignore reserved bits
assign seq_hr_chan_reg2 = dr_sram[8'h49];
assign seq_hr_chan_reg3 = dr_sram[8'h46] & 16'h000F; //ignore reserved bits
assign seq_lr_chan_reg1 = dr_sram[8'h7A] & 16'h7FE1; //ignore reserved bits
assign seq_lr_chan_reg2 = dr_sram[8'h7B];
assign seq_lr_chan_reg3 = dr_sram[8'h7C] & 16'h000F; //ignore reserved bits
assign seq_avg_reg1 = dr_sram[8'h4A] & 16'h4FE0; //ignore reserved bits
assign seq_avg_reg2 = dr_sram[8'h4B];
assign seq_avg_reg3 = dr_sram[8'h47] & 16'h000F; //ignore reserved bits
assign seq_bipolar_reg1 = dr_sram[8'h4C] & 16'h0800; //ignore reserved bits
assign seq_bipolar_reg2 = dr_sram[8'h4D];
assign seq_acq_ext_reg1 = dr_sram[8'h4E] & 16'h0800; //ignore reserved bits
assign seq_acq_ext_reg2 = dr_sram[8'h4F];
assign seq_hr_chan_reg_comb = {seq_hr_chan_reg3, seq_hr_chan_reg2, seq_hr_chan_reg1};
assign seq_lr_chan_reg_comb = {seq_lr_chan_reg3, seq_lr_chan_reg2, seq_lr_chan_reg1};
assign seq_acq_ext_reg_comb = {16'h0000,seq_acq_ext_reg2,seq_acq_ext_reg1};
assign seq_bipolar_reg_comb = {16'h0000,seq_bipolar_reg2,seq_bipolar_reg1};
//
assign op_mode = cfg_reg1[15:12];
assign default_mode = (op_mode == 4'b0000 || op_mode[3:2] == 2'b11);
assign single_pass_mode = (op_mode == 4'b0001);
assign cont_seq_mode = (op_mode == 4'b0010);
assign single_chan_mode = (op_mode == 4'b0011);
assign single_chan_id = cfg_reg0[5:0];
assign ext_mux_chan_id = cfg_reg0[5:0];
assign ext_mux_en = cfg_reg0[11] && (~default_mode || single_chan_mode);
assign ext_mux = cfg_reg0[11];
assign event_driven_mode = cfg_reg0[9];
assign cont_sampl_mode = !event_driven_mode;
assign bipolar_mode = cfg_reg0[10];
assign single_pass_active = single_pass_mode && ~(single_pass_finished && cont_sampl_mode);
always @(posedge sysmon_rst or posedge DCLK_in) begin //at initialization or sequence restart
if( sysmon_rst) begin
alm_en <= 0;
ot_en <= 0;
end
else if(initialize[2] || single_pass_finished_pe || chan_asrt_5) begin
if (default_mode) begin
alm_en <= 0;
ot_en <= 1;
end
else begin
ot_en <= ~cfg_reg1[0];
alm_en[2:0] <= ~cfg_reg1[3:1];
alm_en[6:3] <= ~cfg_reg1[11:8];
alm_en[11:8] <= ~cfg_reg3[3:0];
end
end
end
//6V range support for VUSER0-3
//0: 0-3V, 1: 0-6V
assign bank_sel_6V[3:0] = cfg_reg4[3:0]; // CR 949547
assign single_pass_finished_pe = single_pass_finished & ~single_pass_finished_d;
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
single_pass_finished <= 0;
single_pass_finished_d <= 0;
end
else begin
if(|initialize )begin
single_pass_finished <= 0;
single_pass_finished_d <= 0;
end
else begin
if(single_pass_mode &&
((!acq_ext_cur && EOS_out)||
(acq_ext_cur && hr_final_conversion && adc_state==ST_A_WAIT && busy_start_cs)) )
single_pass_finished <= 1;
single_pass_finished_d <= single_pass_finished;
end
end
end
//-------------------------------------------------------------------------
//---- I2C logic start --------------------------------------------------
//---- PMBus logic start --------------------------------------------------
//-------------------------------------------------------------------------
parameter ST_I2C_IDLE = 2'd0,
ST_I2C_GET_ADDR = 2'd1,
ST_I2C_GET_CMD = 2'd2,
ST_I2C_READ = 2'd3;
localparam I2C_DRP_RD = 4'b0001; // read
localparam I2C_DRP_WR = 4'b0010; // write
localparam I2C_DRP_NO = 4'b0000; // no operation
parameter ST_PMB_IDLE = 3'd0,
ST_PMB_GET_ADDR = 3'd1,
ST_PMB_GET_CMD = 3'd2,
ST_PMB_WRITE = 3'd3,
ST_PMB_READ = 3'd4;
localparam PMB_ALERT_RESPONSE_ADDR = 7'b0001100;
reg [1:0] i2c_state;
reg i2c_start;
reg i2c_start_reset;
reg i2c_stop;
reg i2c_stop_reset;
reg [3:0] i2c_bit_counter;
reg [2:0] i2c_byte_counter;
wire i2c_lsb_bit;
wire i2c_ack_bit;
wire [3:0] i2c_drp_cmd ;
reg [31:0] i2c_cmd_in;
reg [7:0] i2c_data_in;
wire i2c_addr_match;
wire i2c_addr_match_wop;
wire i2c_rw_bit;
wire i2c_rd_cmd_pre;
reg i2c_rd_cmd;
reg i2c_ack_in; //ack from master to slave, negated.
wire i2c_cmd_end;
wire i2c_rd_end;
reg i2c_cmd_received;
reg [15:0] i2c_data_out;
reg [2:0] pmb_state;
reg [2:0] pmb_tot_bytes;
wire pmb_data_end;
wire [7:0] pmb_cmd_pre;
reg [31:0] pmb_data_out;
reg pmb_wr_exec_2;
reg pmb_wr_exec_d;
wire pmb_wr_exec_pe;
reg [7:0] pmb_curr_chan_id;
reg pmb_read_only_cmd;
reg [7:0] pmb_status_vout;
reg [7:0] pmb_status_temperature;
reg [7:0] pmb_status_cml;
reg [7:0] pmb_clr_status_vout;
reg [7:0] pmb_clr_status_temperature;
reg [7:0] pmb_clr_status_cml;
reg [7:0] pmb_status_word; //upper byte
reg [7:0] pmb_status_byte; //lower byte
reg pmb_unsp_cmd;
reg pmb_unsp_data;
reg pmb_paged;
reg pmb_selected;
reg [7:0] pmb_page_index;
reg [7:0] pmb_page_stat;
reg [7:0] pmb_page_max; //max stored value address
reg [7:0] pmb_page_min; //min stored value address
reg [7:0] pmb_page_up_l; //upper limit register address
reg [7:0] pmb_page_lo_l; //lower limit register address
reg [3:0] pmb_page_alm_id; //alarm index for over/under voltage
reg pmb_page_6V;
wire pmb_ara_rcvd;
reg pmb_ara; //alert response address
reg clear_faults;
wire pmb_clear;
//i2c or pmbus selection changes on the fly with i2c command address selection
//i2c_addr_match_wop -> i2c address match without protocol match
assign i2c_addr_match_wop = ((i2c_data_in[7:4]==i2c_device_addr[6:3]) && (i2c_data_in[2:1]==i2c_device_addr[1:0])) ? 1 : 0;
assign i2c_addr_match = ((i2c_oride && (i2c_data_in[7:1]==i2c_device_addr[6:0])) ||
(~i2c_oride && i2c_addr_match_wop ))
? 1 : 0;
assign pmb_en_bit = i2c_data_in[3] && i2c_ack_bit && (i2c_state==ST_I2C_GET_ADDR || pmb_state==ST_PMB_GET_ADDR); //0:i2c, 1:pmbus
assign pmb_ara_rcvd = ((i2c_data_in[6:0]==PMB_ALERT_RESPONSE_ADDR || i2c_data_in[7:1]==PMB_ALERT_RESPONSE_ADDR ) &&
(i2c_lsb_bit ||i2c_ack_bit));
assign pmb_clear = pmb_ara || clear_faults;
always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_stop) begin
if (RESET_in || i2c_stop )
pmb_ara <= 0; //this should be a pulse.
else begin
if (pmb_state==ST_PMB_IDLE)
pmb_ara <= 0; //this should be a pulse.
else
pmb_ara <= pmb_ara_rcvd && (pmb_state==ST_PMB_GET_ADDR) && i2c_rd_cmd_pre;
end
end
assign pmb_en = !i2c_en;
always @(posedge RESET_in or negedge I2C_SCLK_in) begin
if (RESET_in) begin
i2c_en <=1;
end
else begin
if(i2c_oride)
i2c_en <= ~cfg_reg3[10];
else if(i2c_ack_bit && (i2c_state==ST_I2C_GET_ADDR || pmb_state==ST_PMB_GET_ADDR) && i2c_addr_match_wop)
i2c_en <= ~i2c_data_in[3];
end
end
always @(posedge RESET_in or posedge i2c_start_reset or negedge I2C_SDA_in) begin
if(RESET_in || i2c_start_reset)
i2c_start <= 1'b0;
else
i2c_start <= I2C_SCLK_in;
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_start_reset <= 1'b0;
else
i2c_start_reset <= i2c_start;
end
always @(posedge RESET_in or posedge i2c_stop_reset or posedge I2C_SDA_in) begin
if(RESET_in || i2c_stop_reset)
i2c_stop <= 1'b0;
else
i2c_stop <= I2C_SCLK_in;
end
always @(posedge RESET_in or posedge i2c_stop) begin
if(RESET_in)
i2c_stop_reset = 1'b0;
else begin
repeat (16) @(posedge DCLK_in);
i2c_stop_reset = 1;
repeat (16) @(posedge DCLK_in);
i2c_stop_reset = 0;
end
end
assign i2c_lsb_bit = (i2c_bit_counter== 4'd7) && ~i2c_start;
assign i2c_ack_bit = (i2c_bit_counter== 4'd8) && ~i2c_start;
always @(posedge RESET_in or negedge I2C_SCLK_in or posedge i2c_start) begin
if(RESET_in || i2c_start)
i2c_bit_counter <= 'd0;
else begin
if (i2c_ack_bit)
i2c_bit_counter <= 'd0;
else
i2c_bit_counter <= i2c_bit_counter + 'd1;
end
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_data_in <= 'd0;
else if(!i2c_ack_bit)
i2c_data_in <= {i2c_data_in[6:0],I2C_SDA_in} ;
end
assign i2c_drp_data = i2c_cmd_in[15:0];
assign i2c_drp_addr = i2c_cmd_in[25:16];
assign i2c_drp_cmd = i2c_cmd_in[29:26];
always @(posedge I2C_SCLK_in) begin
//if(RESET_in)
// i2c_cmd_in <= 'd0;
//else if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD )
if(i2c_ack_bit && i2c_state == ST_I2C_GET_CMD )
i2c_cmd_in <= {i2c_data_in,i2c_cmd_in[31:8]} ;
end
assign pmb_cmd_pre = i2c_data_in[7:0];
always @(posedge I2C_SCLK_in) begin
//if(RESET_in)
// pmb_cmd_in <= 'd0;
//else if (i2c_ack_bit && pmb_state == ST_PMB_GET_CMD)
if (i2c_ack_bit && pmb_state == ST_PMB_GET_CMD)
pmb_cmd_in <= i2c_data_in;
end
assign i2c_rw_bit = i2c_lsb_bit && (i2c_state == ST_I2C_GET_ADDR || pmb_state ==ST_PMB_GET_ADDR);
assign i2c_rd_cmd_pre = i2c_rw_bit && I2C_SDA_in;
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)
i2c_rd_cmd <= 1'b0;
else begin
if (i2c_state==ST_I2C_IDLE && pmb_state==ST_PMB_IDLE)
i2c_rd_cmd <= 1'b0;
else if (i2c_rw_bit )
i2c_rd_cmd <= i2c_data_in[0] ;
end
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if(RESET_in)
i2c_ack_in <= 'd0;
else if(i2c_ack_bit)
i2c_ack_in <= ~I2C_SDA_in; //ACK from master to slave, negated.
else if ((i2c_state==ST_I2C_IDLE && pmb_state==ST_PMB_IDLE) || i2c_bit_counter=='d1)
i2c_ack_in <= 0;
end
assign i2c_cmd_end = i2c_ack_bit && (i2c_byte_counter==3'd3);
assign i2c_rd_end = i2c_ack_bit && (i2c_byte_counter==3'd1);
always @(posedge RESET_in or posedge i2c_stop or posedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)
i2c_cmd_received <= 0;
else if (i2c_cmd_end)
i2c_cmd_received <= 1;
else if (i2c_state==ST_I2C_READ)
i2c_cmd_received <= 0;
end
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_start || i2c_stop)
i2c_byte_counter <= 0;
else if(i2c_ack_bit && (i2c_state == ST_I2C_GET_CMD || i2c_state == ST_I2C_READ ||
pmb_state == ST_PMB_WRITE || pmb_state == ST_PMB_READ ))
i2c_byte_counter <= i2c_byte_counter + 1;
end
//I2C state machine.
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)// && ~i2c_en)
i2c_state <= ST_I2C_IDLE;
else if(i2c_start)
i2c_state <= ST_I2C_GET_ADDR;
else if (i2c_ack_bit)
case (i2c_state)
ST_I2C_GET_ADDR : begin
if(!(i2c_addr_match && !pmb_en_bit)) begin
i2c_state <= ST_I2C_IDLE;
$display("Info: [Unisim %s-54] I2C command address h%0X not matching the device address h%0X @time %0t",
MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time);
end
else if (~i2c_cmd_received)
i2c_state <= ST_I2C_GET_CMD;
else if(i2c_drp_cmd==I2C_DRP_RD) //if you received a command earlier, it had to be a drp read command.
i2c_state <= ST_I2C_READ;
else
i2c_state <= ST_I2C_IDLE;
end
ST_I2C_GET_CMD : begin
if (i2c_cmd_end) begin
i2c_state <= ST_I2C_IDLE;
$display("Info: [Unisim %s] I2C command received @time %0t", MODULE_NAME, $time);
end
end
ST_I2C_READ : begin
if(i2c_rd_end)
i2c_state <= ST_I2C_IDLE;
end
default : i2c_state <= ST_I2C_IDLE;
endcase
end
//i2c write command execute
assign i2c_wr_exec = (i2c_cmd_received && i2c_drp_cmd==I2C_DRP_WR);
always @(posedge DCLK_in ) begin
if(!sysmon_rst) begin
if(i2c_wr_exec &&
!(is_readonly_address(i2c_drp_addr)) && !is_reserved_address(i2c_drp_addr) )
dr_sram[i2c_drp_addr] <= i2c_drp_data;
end
end
//i2c read command execute
always @(negedge I2C_SCLK_in) begin
if(!RESET_in) begin
if(i2c_cmd_received && i2c_drp_cmd==I2C_DRP_RD && i2c_state==ST_I2C_GET_ADDR && !i2c_ack_bit) begin //fetch the data
if(i2c_drp_addr>='h40)
i2c_data_out <= dr_sram[i2c_drp_addr];
else
i2c_data_out <= data_reg[i2c_drp_addr];
end
else if(i2c_lsb_bit && i2c_state==ST_I2C_READ)
i2c_data_out <= {8'b0,i2c_data_out[15:8]};// shift the higher byte to lower.
else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out.
i2c_data_out <= {i2c_data_out[15:8],i2c_data_out[6:0],1'b0};
end
end
assign pmb_data_end = i2c_ack_bit && (i2c_byte_counter==(pmb_tot_bytes-1));
//Pull down SDA to transfer a zero to the master.
always@(posedge RESET_in or negedge I2C_SCLK_in) begin
if (RESET_in)
I2C_SDA_TS_out <= 1;
else begin
if (i2c_start)
I2C_SDA_TS_out <= 1;
else if (i2c_lsb_bit) //acknowledge the end of a 1 byte transfer from master
I2C_SDA_TS_out <= ! (((i2c_state==ST_I2C_GET_ADDR) && (i2c_addr_match || pmb_ara_rcvd)) || //will also be true for pmbus
((i2c_state==ST_I2C_GET_CMD ) && !(i2c_rd_cmd && i2c_byte_counter=='d3)) || //send NACK at the last byte of command, only if read command
(pmb_state==ST_PMB_GET_CMD) ||
(pmb_state==ST_PMB_WRITE) //send ACK for all write command bytes
);
else if ((i2c_ack_bit && //first bit of next slave to master transfer
((i2c_state==ST_I2C_GET_ADDR) && (i2c_drp_cmd==I2C_DRP_RD) )) ||
(i2c_state==ST_I2C_READ && !i2c_rd_end)) //or read continued
I2C_SDA_TS_out <= i2c_data_out[7];
else if(((i2c_ack_bit && pmb_state==ST_PMB_GET_ADDR) && i2c_rd_cmd) || //first bit of next slave to master transfer
(pmb_state==ST_PMB_READ && !pmb_data_end)) //or read continued
I2C_SDA_TS_out <= pmb_data_out[7];
else
I2C_SDA_TS_out <= 1;
end
end
// clock stretching
assign I2C_SCLK_TS_out = 1'b1;
//---- End of I2C logic ------------------------------------------------
//---- PMBUS only from here on -----------------------------------------
// PMBUS state machine
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in || i2c_stop)
pmb_state <= ST_PMB_IDLE;
else if(i2c_start)
pmb_state <= ST_PMB_GET_ADDR;
else if (i2c_ack_bit)
case (pmb_state)
ST_PMB_GET_ADDR : begin
if(!(i2c_addr_match && pmb_en_bit)) begin
if(pmb_ara_rcvd) begin
if(!i2c_rd_cmd) begin
pmb_state <= ST_PMB_IDLE;
$display("Info: [Unisim %s-57] PMBus Alert Response Address received together with a write bit instead of a read bit. It will be ignored. @time %0t",
MODULE_NAME, $time);
end
else //ARA received. Send the device address as a response
pmb_state <= ST_PMB_READ;
end
else begin
pmb_state <= ST_PMB_IDLE;
if(pmb_en_bit)
$display("Info: [Unisim %s-64] PMBus command address h%0X not matching the device address h%0X @time %0t",
MODULE_NAME, i2c_data_in[7:1], i2c_device_addr, $time);
end
end
else if (!i2c_rd_cmd) //write command comes only before command id.
pmb_state <= ST_PMB_GET_CMD;
else
pmb_state <= ST_PMB_READ;
end
ST_PMB_GET_CMD : begin
$display("Info: [Unisim %s] PMBus command received @time %0t", MODULE_NAME, $time);
if(pmb_cmd_pre==CMD_CLEAR_FAULT) //clear fault has 0 bytes of succeeding data, so go to idle.
pmb_state <= ST_PMB_IDLE;
else //get succeeding data. if it is a read command, restart will take it to ST_PMB_IDLE.
pmb_state <= ST_PMB_WRITE;
end
ST_PMB_WRITE : begin
if(pmb_data_end)
pmb_state <= ST_PMB_IDLE;
end
ST_PMB_READ : begin
if(pmb_data_end)
pmb_state <= ST_PMB_IDLE;
end
default : begin
pmb_state <= ST_PMB_IDLE;
end
endcase
end
//Parse PMB command
always @(posedge RESET_in or negedge I2C_SCLK_in) begin
if(RESET_in) begin
pmb_tot_bytes <= 'd0;
pmb_unsp_cmd <= 0;
pmb_paged <= 0;
pmb_selected <= 0;
end
else if(i2c_ack_bit && pmb_state==ST_PMB_GET_CMD) begin
pmb_unsp_cmd <= 0;
case (pmb_cmd_pre)
CMD_PAGE : begin
pmb_tot_bytes <= 'd1;
pmb_paged <= 1;
end
CMD_CLEAR_FAULT : begin
pmb_tot_bytes <= 'd0;
end
CMD_CAPABILITY,CMD_VOUT_MODE,CMD_STATUS_BYTE,
CMD_STATUS_VOUT, CMD_STATUS_TEMPERATURE, CMD_STATUS_CML,
CMD_PMBUS_REVISION, CMD_MFR_ENABLE_VUSER_HR
: begin
pmb_tot_bytes <= 'd1;
end
CMD_VOUT_OV_FAULT_LIMIT, CMD_VOUT_UV_FAULT_LIMIT,
CMD_OT_FAULT_LIMIT , CMD_OT_WARNING_LIMIT ,
CMD_UT_WARNING_LIMIT , CMD_UT_FAULT_LIMIT ,
CMD_STATUS_WORD , CMD_READ_VOUT ,
CMD_READ_TEMPERATURE_1 , CMD_MFR_ACCESS_REG ,
CMD_MFR_READ_VOUT_MAX , CMD_MFR_READ_VOUT_MIN ,
CMD_MFR_READ_TEMP_MAX , CMD_MFR_READ_TEMP_MIN
: begin
pmb_tot_bytes <= 'd2;
end
CMD_MFR_ID,CMD_MFR_MODEL: begin
pmb_tot_bytes <= 'd4;
end
CMD_MFR_REVISION : begin
pmb_tot_bytes <= 'd3;
end
CMD_MFR_SELECT_REG : begin
pmb_tot_bytes <= 'd2;
pmb_selected <= 1;
end
default: begin
pmb_unsp_cmd<=1; //Unsupported command
$display("Warning: [Unisim %s-56] PMBus received invalid command ID h%0X @ time %0t ", MODULE_NAME, pmb_cmd_pre, $time);
end
endcase
end
else if(pmb_ara_rcvd && pmb_state==ST_PMB_GET_ADDR) //Alert Response Address (ARA) has 1 byte response.
pmb_tot_bytes <= 1;
else begin
pmb_unsp_cmd <= 0;
end
end
always @(posedge RESET_in or posedge i2c_stop or negedge I2C_SCLK_in) begin
if(RESET_in ||i2c_stop)
clear_faults <= 0;
else if(i2c_ack_bit && pmb_state==ST_PMB_GET_CMD && pmb_cmd_pre==CMD_CLEAR_FAULT)
clear_faults <= 1;
else
clear_faults <= 0;
end
always @(posedge RESET_in or posedge I2C_SCLK_in) begin
if (RESET_in)
pmb_data_in <= 'd0;
else if(i2c_ack_bit && pmb_state == ST_PMB_WRITE)
if(pmb_tot_bytes>1)
pmb_data_in <= {i2c_data_in,pmb_data_in[15:8]} ; //Most significant byte arrives later.
else
pmb_data_in <= {8'd0,i2c_data_in} ; //1 byte, that's it.
end
//convert from linear 16 to drp format -> PMBus WRITE
function [15:0] linear16_to_drp;
input [15:0] mantissa; //unsigned
reg [16:0] linear17_to_drp;
begin
if(pmb_page_6V) // CR 949547
linear16_to_drp = (mantissa *2)/3;
else begin
linear17_to_drp = (mantissa *4)/3;
if(linear17_to_drp > 17'h0FFFF) begin
linear16_to_drp = 16'hFFFF;
if(pmb_wr_exec_pe) //display message only once.
$display("Warning: [Unisim %s-62] The maximum value you can write to a DRP supply register is 16'hFFFF. Hence for PMBus it is 16'hAAAA. The input value has been saturated to max.", MODULE_NAME, $time);
end
else
linear16_to_drp = linear17_to_drp[15:0];
end
//$display("linear16_to_drp: mantissa :h%0h, output=h%0h @%0t",mantissa , linear16_to_drp, $time);
end
endfunction
//convert from drp format to linear 16 -> PMBus READ
function [15:0] drp_to_linear16;
input [15:0] voltage_drp; //unsigned
reg [16:0] drp_to_linear17;
begin
if(pmb_page_6V) begin // CR 949547
drp_to_linear17 = (voltage_drp *3)/2;
if(drp_to_linear17 > 17'h0FFFF) begin
drp_to_linear16 = 16'hFFFF;
if(i2c_lsb_bit) //display message only once
$display("Warning: [Unisim %s-63] The maximum value you can read from a DRP supply register is 16'hFFFF. Hence for PMBus it is 16'hAAAA. The return value has been saturated to max.", MODULE_NAME, $time);
end
else
drp_to_linear16 = drp_to_linear17[15:0];
end
else
drp_to_linear16 = (voltage_drp *3)/4;
//$display("drp_to_linear16: voltage_drp=h%0h, output=h%0h, drp_to_linear17=h%0h @%0t",voltage_drp, drp_to_linear16, drp_to_linear17, $time);
end
endfunction
//convert from linear 11 to integer -> PMBus WRITE
function [15:0] linear11_to_drp;
input [15:0] exp_mants; //both signed
//input limit; // 0 if reading current or min/max value 1: reading temp limits
real exp;
real mants;
real temp_coeff;
real temp_offset;
real two_p_bits;
real real_result;
begin
exp =$signed(exp_mants[15:11]);
mants =$signed(exp_mants[10:0]);
//temp_coeff = limit ? 502.9098 : 491.2065 ;
//temp_offset = limit ? 273.8195 : 273.15 ;
//two_p_bits = limit ? 65536: 65535;
temp_coeff = 503.975 ;
temp_offset = 273.15 ;
two_p_bits = 65536;
real_result = (mants * (2** exp)); //mants * 2^exp
real_result = (real_result + temp_offset) * (two_p_bits / temp_coeff);
//linear11_to_drp = $rtoi(real_result);
linear11_to_drp = real_result;
//$display("linear11_to_drp: exp_mants=h%0h, mantissa=d%0d, exp:d%0d, real_result=g%0g, output=h%0h @%0t\n",
// exp_mants, mants, exp, real_result, linear11_to_drp, $time/1000);
end
endfunction
// Convert from integer to to linear 11 -> PMBus READ
// Exponent is -1 hard coded during PMBus reads.
function [15:0] drp_to_linear11;
input [15:0] drp_temp; //unsigned. temperature in drp format
//input limit;
real temp_coeff;
real temp_offset;
real two_p_bits;
real real_result;
reg signed [10:0] mantissa;
begin
//temp_coeff = limit ? 502.9098 : 491.2065 ;
//temp_offset = limit ? 273.8195 : 273.15 ;
//two_p_bits = limit ? 65536: 65535;
temp_coeff = 503.975;
temp_offset = 273.15;
two_p_bits = 65536;
real_result = 2* ((drp_temp * temp_coeff / two_p_bits) - temp_offset);
//mantissa = $rtoi (real_result);
mantissa = real_result;
drp_to_linear11 = {5'h1F,mantissa};
//$display("drp_to_linear11: drp_temp=h%0h, real_result = g%0g, real_result = h%0g, mantissa=h%0h, output= h%0h @%0t\n",
// drp_temp, real_result, real_result, mantissa, drp_to_linear11, $time/1000);
end
endfunction
always @(posedge RESET_in or posedge i2c_stop or posedge i2c_start or negedge I2C_SCLK_in) begin
if(RESET_in ||i2c_stop ||i2c_start )
pmb_wr_exec <= 0;
else if (pmb_state==ST_PMB_WRITE && pmb_data_end)
pmb_wr_exec <= 1;
else
pmb_wr_exec <= 0;
end
assign pmb_wr_exec_pe = pmb_wr_exec & ~pmb_wr_exec_d;
always @(posedge RESET_in or posedge i2c_stop or posedge i2c_start or posedge DCLK_in) begin
if(RESET_in ||i2c_stop ||i2c_start )
pmb_wr_exec_d <= 0;
else
pmb_wr_exec_d <= pmb_wr_exec;
end
always @(posedge DCLK_in) begin
@(posedge pmb_wr_exec);
if (pmb_cmd_in==CMD_PAGE ||
pmb_cmd_in==CMD_VOUT_UV_FAULT_LIMIT ||
pmb_cmd_in==CMD_VOUT_OV_FAULT_LIMIT ||
pmb_cmd_in==CMD_OT_FAULT_LIMIT ||
pmb_cmd_in==CMD_OT_WARNING_LIMIT ||
pmb_cmd_in==CMD_UT_FAULT_LIMIT ||
pmb_cmd_in==CMD_UT_WARNING_LIMIT ||
pmb_cmd_in==CMD_MFR_ACCESS_REG
)
@(negedge pmb_wr_exec);
@(posedge DCLK_in);
pmb_wr_exec_2 = 1;
@(posedge DCLK_in);
pmb_wr_exec_2 = 0;
end
//PMB write execute
always @(posedge RESET_in or posedge pmb_wr_exec or posedge DCLK_in) begin
if(RESET_in) begin
pmb_read_only_cmd <=0;
pmb_clr_status_vout <='d0;
pmb_clr_status_temperature <='d0;
pmb_clr_status_cml <='d0;
pmb_drsram_wr_data <='d0;
pmb_drsram_addr <='d0;
end
else if(pmb_wr_exec) begin
pmb_read_only_cmd <=0;
pmb_clr_status_vout <='d0;
pmb_clr_status_temperature <='d0;
pmb_clr_status_cml <='d0;
pmb_drsram_wr_data <='d0;
pmb_drsram_addr <='d0;
case (pmb_cmd_in)
CMD_PAGE : ; //seperated to another always block for readibility
CMD_CLEAR_FAULT : pmb_read_only_cmd <=1; //Error: Too many bytes
CMD_VOUT_OV_FAULT_LIMIT : begin
dr_sram[pmb_page_up_l] <= linear16_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear16_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= pmb_page_up_l;
end
CMD_VOUT_UV_FAULT_LIMIT : begin
dr_sram[pmb_page_lo_l] <= linear16_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear16_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= pmb_page_lo_l;
end
CMD_OT_FAULT_LIMIT : begin
dr_sram[8'h53] <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= 8'h53;
end
CMD_OT_WARNING_LIMIT : begin
dr_sram[8'h50] <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= 8'h50;
end
CMD_UT_WARNING_LIMIT : begin
dr_sram[8'h54] <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= 8'h54;
end
CMD_UT_FAULT_LIMIT : begin
dr_sram[8'h57] <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_wr_data <= linear11_to_drp(pmb_data_in[15:0]);
pmb_drsram_addr <= 8'h57;
end
CMD_STATUS_VOUT : pmb_clr_status_vout <= pmb_data_in[7:0];
CMD_STATUS_TEMPERATURE : pmb_clr_status_temperature <= pmb_data_in[7:0];
CMD_STATUS_CML : pmb_clr_status_cml <= pmb_data_in[7:0];
CMD_MFR_SELECT_REG : begin
pmb_sel_addr <= pmb_data_in[7:0];
// Checked reserved error message
if(is_reserved_address(pmb_sel_addr))
$display("Warning: [Unisim %s] PMBus MFR_SELECT_REG command is trying to point to a RESERVED location h%0X.", MODULE_NAME, pmb_sel_addr, $time/1000.0);
end
CMD_MFR_ACCESS_REG : begin
if(pmb_sel_addr >= 8'h40)
dr_sram[pmb_sel_addr] <= pmb_data_in[15:0];
pmb_drsram_addr <= pmb_sel_addr;
pmb_drsram_wr_data <= pmb_data_in[15:0];
end
CMD_CAPABILITY , CMD_VOUT_MODE ,
CMD_STATUS_BYTE , CMD_STATUS_WORD ,
CMD_READ_VOUT , CMD_READ_TEMPERATURE_1,
CMD_PMBUS_REVISION , CMD_MFR_ID ,
CMD_MFR_MODEL , CMD_MFR_REVISION ,
CMD_MFR_READ_VOUT_MAX , CMD_MFR_READ_VOUT_MIN ,
CMD_MFR_READ_TEMP_MAX , CMD_MFR_READ_TEMP_MIN ,
CMD_MFR_ENABLE_VUSER_HR:
begin
pmb_read_only_cmd <=1; //Error: Too many bytes
end
//default:
endcase
end //else if
else begin //pmb_wr_exec==0 and posedge (dclk_in)
pmb_read_only_cmd <=0;
pmb_clr_status_vout <='d0;
pmb_clr_status_temperature <='d0;
pmb_clr_status_cml <='d0;
// Keep pmb_drsram_addr and pmb_drsram_wr_data values
// as they will be used with delay
end
end //always
//PMB write execute for page command
always @(posedge RESET_in or posedge pmb_wr_exec or negedge I2C_SCLK_in) begin
if(RESET_in) begin
pmb_drsram_bit_idx <= 'd0;
pmb_drsram_addr_page <= 'd0;
pmb_page_index <= 'd0;
pmb_page_stat <= 'd0;
pmb_page_max <= 'd0;
pmb_page_min <= 'd0;
pmb_page_up_l <= 'd0;
pmb_page_lo_l <= 'd0;
pmb_page_alm_id <= 'd1;
pmb_valid_page <= 0;
pmb_page_6V <= 0;
end
else if(pmb_wr_exec && pmb_cmd_in==CMD_PAGE) begin // || pmb_cmd_in==CMD_MFR_SELECT_REG) begin
pmb_page_index <= pmb_data_in[7:0];
pmb_drsram_bit_idx <= 'd0;
pmb_drsram_addr_page<= 'd0;
case (pmb_data_in[7:0])
8'd1: begin //VCC INT
dr_sram[8'h48][9]<= 1'b1; //Add this channel to sequence
pmb_drsram_addr_page <= 8'h48;
pmb_drsram_bit_idx <= 'd9;
pmb_page_stat <= 8'h01;
pmb_page_max <= 8'h21;
pmb_page_min <= 8'h25;
pmb_page_up_l <= 8'h51;
pmb_page_lo_l <= 8'h55;
pmb_page_alm_id <= 'd1;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd2: begin //VCC AUX
dr_sram[8'h48][10]<= 1'b1;
pmb_drsram_addr_page <= 8'h48;
pmb_drsram_bit_idx <= 'd10;
pmb_page_stat <= 8'h02;
pmb_page_max <= 8'h22;
pmb_page_min <= 8'h26;
pmb_page_up_l <= 8'h52;
pmb_page_lo_l <= 8'h56;
pmb_page_alm_id <= 'd2;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd6: begin //VCC BRAM
dr_sram[8'h48][14]<= 1'b1;
pmb_drsram_addr_page <= 8'h48;
pmb_drsram_bit_idx <= 'd14;
pmb_page_stat <= 8'h06;
pmb_page_max <= 8'h23;
pmb_page_min <= 8'h27;
pmb_page_up_l <= 8'h58;
pmb_page_lo_l <= 8'h5C;
pmb_page_alm_id <= 'd3;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd13:begin // VCC PSINTLP
dr_sram[8'h48][7]<= 1'b1;
pmb_drsram_addr_page<= 8'h48;
pmb_drsram_bit_idx <= 'd7;
pmb_page_stat <= 8'h0D;
pmb_page_max <= 8'h28;
pmb_page_min <= 8'h2C;
pmb_page_up_l <= 8'h59;
pmb_page_lo_l <= 8'h5D;
pmb_page_alm_id <= 'd4;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd14:begin // VCC PSINTFP
dr_sram[8'h48][6]<= 1'b1;
pmb_drsram_addr_page<= 8'h48;
pmb_drsram_bit_idx <= 'd6;
pmb_page_stat <= 8'h0E;
pmb_page_max <= 8'h29;
pmb_page_min <= 8'h2D;
pmb_page_up_l <= 8'h5A;
pmb_page_lo_l <= 8'h5E;
pmb_page_alm_id <= 'd5;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd15:begin // VCC PSAUX
dr_sram[8'h48][5]<= 1'b1;
pmb_drsram_addr_page<= 8'h48;
pmb_drsram_bit_idx <= 'd5;
pmb_page_stat <= 8'h0F;
pmb_page_max <= 8'h2A;
pmb_page_min <= 8'h2E;
pmb_page_up_l <= 8'h5B;
pmb_page_lo_l <= 8'h5F;
pmb_page_alm_id <= 'd6;
pmb_valid_page <= 1;
pmb_page_6V <= 0;
end
8'd32:begin //VUSER 0
dr_sram[8'h46][0]<= 1'b1;
pmb_drsram_addr_page<= 8'h46;
pmb_drsram_bit_idx <= 'd0;
pmb_page_stat <= 8'h80;
pmb_page_max <= 8'hA0;
pmb_page_min <= 8'hA8;
pmb_page_up_l <= 8'h60;
pmb_page_lo_l <= 8'h68;
pmb_page_alm_id <= 'd8;
pmb_valid_page <= 1;
pmb_page_6V <= bank_sel_6V[0];
end
8'd33:begin //VUSER 1
dr_sram[8'h46][1]<= 1'b1;
pmb_drsram_addr_page<= 8'h46;
pmb_drsram_bit_idx <= 'd1;
pmb_page_stat <= 8'h81;
pmb_page_max <= 8'hA1;
pmb_page_min <= 8'hA9;
pmb_page_up_l <= 8'h61;
pmb_page_lo_l <= 8'h69;
pmb_page_alm_id <= 'd9;
pmb_valid_page <= 1;
pmb_page_6V <= bank_sel_6V[1];
end
8'd34:begin //VUSER 2
dr_sram[8'h46][2]<= 1'b1;
pmb_drsram_addr_page<= 8'h46;
pmb_drsram_bit_idx <= 'd2;
pmb_page_stat <= 8'h82;
pmb_page_max <= 8'hA2;
pmb_page_min <= 8'hAA;
pmb_page_up_l <= 8'h62;
pmb_page_lo_l <= 8'h6A;
pmb_page_alm_id <= 'd10;
pmb_valid_page <= 1;
pmb_page_6V <= bank_sel_6V[2];
end
8'd35:begin //VUSER 3
dr_sram[8'h46][3]<= 1'b1;
pmb_drsram_addr_page<= 8'h46;
pmb_drsram_bit_idx <= 'd3;
pmb_page_stat <= 8'h83;
pmb_page_max <= 8'hA3;
pmb_page_min <= 8'hAB;
pmb_page_up_l <= 8'h63;
pmb_page_lo_l <= 8'h6B;
pmb_page_alm_id <= 'd11;
pmb_valid_page <= 1;
pmb_page_6V <= bank_sel_6V[3];
end
default:begin
pmb_drsram_addr_page<= 'd0;
pmb_drsram_bit_idx <= 'd0;
pmb_page_stat <= 8'd0;
pmb_page_max <= 8'd0;
pmb_page_min <= 8'd0;
pmb_page_up_l <= 8'd0;
pmb_page_lo_l <= 8'd0;
pmb_page_alm_id <= 'd1;
pmb_valid_page <= 0;
pmb_page_6V <= 0;
$display("Warning: [Unisim %s-55] PMBus page command received an invalid Page index @ time %0t", MODULE_NAME, $time);
end
endcase
end // pmb_wr_exec
else begin
end
end //always
//PMBus read execute
always @(posedge RESET_in or negedge I2C_SCLK_in) begin
if(RESET_in)
pmb_unsp_data <= 0; //unsupported data // This is not a read command
else begin
// need to fetch before we know if we are going to get a read or write request
if(pmb_state==ST_PMB_GET_ADDR & !i2c_ack_bit) begin
pmb_data_out <= 32'h00000000;
case (pmb_cmd_in)
CMD_PAGE : pmb_data_out[7:0] <= pmb_page_index;
CMD_CLEAR_FAULT : begin
pmb_unsp_data <= 1; //unsupported data // This is not a read command. validate after
pmb_data_out[31:0] <= 31'hXXXXXXXX; //invalid command gets and x.
end
CMD_CAPABILITY : pmb_data_out[7:0] <= 8'h30;
CMD_VOUT_MODE : pmb_data_out[7:0] <= 8'h12;
CMD_VOUT_OV_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear16(dr_sram[pmb_page_up_l]);
CMD_VOUT_UV_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear16(dr_sram[pmb_page_lo_l]);
CMD_OT_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h53]);
CMD_OT_WARNING_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h50]);
CMD_UT_WARNING_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h54]);
CMD_UT_FAULT_LIMIT : pmb_data_out[15:0] <= drp_to_linear11(dr_sram[8'h57]);
CMD_STATUS_BYTE : pmb_data_out[7:0] <= pmb_status_byte;
CMD_STATUS_WORD : pmb_data_out[15:0] <= {pmb_status_word,pmb_status_byte};
CMD_STATUS_VOUT : pmb_data_out[7:0] <= pmb_status_vout;
CMD_STATUS_TEMPERATURE : pmb_data_out[7:0] <= pmb_status_temperature;
CMD_STATUS_CML : pmb_data_out[7:0] <= pmb_status_cml;
CMD_READ_VOUT : begin
if(pmb_page_stat >= 8'h40)
pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_stat]);
else
pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_stat]);
end
CMD_READ_TEMPERATURE_1 : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h00]);
CMD_PMBUS_REVISION : pmb_data_out[7:0] <= 8'h42;
CMD_MFR_ID : begin
pmb_data_out[7:0] <= 8'h03; //in block read, first byte is the length of the rest of the data
pmb_data_out[15:8] <= 8'h93;
pmb_data_out[23:16] <= 8'h00;
pmb_data_out[31:24] <= 8'h00;
end
CMD_MFR_MODEL : begin
pmb_data_out[7:0] <= 8'h03; //in block read, first byte is the length of the rest of the data
pmb_data_out[15:8] <= 8'h00;
pmb_data_out[23:16] <= 8'h00;
pmb_data_out[31:24] <= 8'h00;
end
CMD_MFR_REVISION : begin
pmb_data_out[7:0] <= 8'h02; //in block read, first byte is the length of the rest of the data
pmb_data_out[15:8] <= 8'h00;
pmb_data_out[23:16] <= 8'h00;
end
CMD_MFR_SELECT_REG : pmb_data_out[7:0] <= pmb_sel_addr;
CMD_MFR_ACCESS_REG : begin
if(pmb_sel_addr >= 8'h40)
pmb_data_out[15:0] <= dr_sram [pmb_sel_addr];
else
pmb_data_out[15:0] <= data_reg[pmb_sel_addr];
end
CMD_MFR_READ_VOUT_MAX : begin
if(pmb_page_max>='h40)
pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_max]);
else
pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_max]);
end
CMD_MFR_READ_VOUT_MIN : begin
if(pmb_page_min>='h40)
pmb_data_out[15:0] <= drp_to_linear16(dr_sram [pmb_page_min]);
else
pmb_data_out[15:0] <= drp_to_linear16(data_reg[pmb_page_min]);
end
CMD_MFR_ENABLE_VUSER_HR : pmb_data_out[3:0] <= cfg_reg4[3:0]; // as is
CMD_MFR_READ_TEMP_MAX : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h20]);
CMD_MFR_READ_TEMP_MIN : pmb_data_out[15:0] <= drp_to_linear11(data_reg[8'h24]);
default: begin
pmb_data_out[31:0] <= 32'h00000000; //invalid command
end
endcase
if (pmb_ara_rcvd ) begin //&& (pmb_state==ST_PMB_GET_ADDR)) begin
pmb_data_out[31:8] <= 24'd0;
pmb_data_out[7:1] <= i2c_device_addr | 7'b0000100;
pmb_data_out[0] <= 1'b0; //lsb of the response is don't care.
end
end
else if (i2c_lsb_bit && pmb_state==ST_PMB_READ )
pmb_data_out <= {8'b0,pmb_data_out[31:8]}; //shift the higher byte to lower
else //shift the data 1 bit at a time for only the lower byte. bit 7 is pushed out.
pmb_data_out <= {pmb_data_out[31:8],pmb_data_out[6:0],1'b0};
end
end //always
// PMBus fault handling
always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin
if(sysmon_rst || pmb_clear) begin
pmb_status_word <= 'd0;
pmb_status_byte <= 'd0;
end
else begin
pmb_status_word[7] <= |pmb_status_vout[7:0];
pmb_status_word[6:0] <= 7'd0; //Reserved
pmb_status_byte[7:6] <= 2'd0; //Reserved
pmb_status_byte[5] <= pmb_status_vout[7];
pmb_status_byte[4:3] <= 2'd0; //Reserved
pmb_status_byte[2] <= |pmb_status_temperature[7:0];
pmb_status_byte[1] <= |pmb_status_cml[7:0];
pmb_status_byte[0] <= 1'b0; //None of the above is undefined
end
end
always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin
if(sysmon_rst || pmb_clear)
pmb_status_temperature <='d0;
else begin
pmb_status_temperature[7] <= pmb_clr_status_temperature[7] ? 0 : (OT_out & !ut_fault);
pmb_status_temperature[6] <= pmb_clr_status_temperature[6] ? 0 : (ALM_out[0] & !ut_warn);
pmb_status_temperature[5] <= pmb_clr_status_temperature[5] ? 0 : ut_warn;
pmb_status_temperature[4] <= pmb_clr_status_temperature[4] ? 0 : ut_fault;
pmb_status_temperature[3:0] <= 4'd0;
end
end
always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin
if(sysmon_rst || pmb_clear)
pmb_status_vout <= 'd0;
else if (pmb_paged) begin
pmb_status_vout[7] <= pmb_clr_status_vout[7]? 0: (ALM_out[pmb_page_alm_id] && !alm_ut[pmb_page_alm_id]); //Over voltage
pmb_status_vout[6:5] <= 'd0; //Reserved
pmb_status_vout[4] <= pmb_clr_status_vout[4]? 0: alm_ut[pmb_page_alm_id]; //Under voltage
pmb_status_vout[3:0] <= 'd0; //Reserved
end
end
always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin
if(sysmon_rst || pmb_clear)
pmb_status_cml <= 'd0;
else begin
pmb_status_cml[7] <= pmb_clr_status_cml[7] ? 0 : pmb_unsp_cmd;
pmb_status_cml[6] <= pmb_clr_status_cml[6] ? 0 : (pmb_unsp_data || pmb_read_only_cmd);
pmb_status_cml[5:2] <= 'd0; //Reserved
pmb_status_cml[1] <= pmb_clr_status_cml[1] ? 0 : 0; //Other/TBD
pmb_status_cml[0] <= 'd0; //Reserved
end
end
always @(posedge sysmon_rst or posedge pmb_clear or posedge DCLK_in) begin
if(sysmon_rst || pmb_clear )
SMBALERT_TS_out <= 1; // active negative
else begin
SMBALERT_TS_out <= !((|pmb_status_word) || (|pmb_status_byte));
end
end
//---- End of PMBus logic ------------------------------------------------
//---------------------------------------------------------------------
// Clock divider, generate and adcclk
assign adcclk_period_end = (adcclk_count ==curr_clkdiv_sel-1);
assign adcclk_period_start = (adcclk_count == 0);
always @(posedge DCLK_in)
adcclk_period_end_d <= adcclk_period_end;
always @(posedge DCLK_in)
sysclk <= ~sysclk;
always @(posedge DCLK_in ) begin
if (curr_clkdiv_sel > 'd2 || adcclk_count_rst) begin
if ((adcclk_count >= curr_clkdiv_sel-1) || adcclk_count_rst)
adcclk_count <= 0;
else
adcclk_count <= adcclk_count + 1;
if(adcclk_count_rst)
adcclk_tmp <= 1;
else if(adcclk_count <= curr_clkdiv_sel/2 -1)
adcclk_tmp <= 1;
else
adcclk_tmp <= 0;
end
else
adcclk_tmp <= ~adcclk_tmp;
end
assign curr_clkdiv_sel = cfg_reg2[15:8];
assign adcclk_div1 = (curr_clkdiv_sel > 'd2) ? 0 : 1;
assign adcclk = (adcclk_div1) ? ~sysclk : adcclk_tmp;
// end clock divider
//-----------------------------------------------------------------
// sequence control
//-----------------------------------------------------------------
assign lr_chan_on = (lr_tot_chan>0) && cont_seq_mode;
assign cont_seq_only_hr = (lr_tot_chan==0) && cont_seq_mode;
// CR-961759 When channel selection registers are changed, the update is after end of the sequence.
// In dual channel, EOS is optional, hence EOS_out is not used.
always @(posedge sysmon_rst or posedge DCLK_in) begin
if( sysmon_rst)
add_channel <= 0;
else begin //it has to be the final EOS of the final channel in the big loop hence tot_final_conversion
if(eoc_asrt && (!avg_en||avg_final_loop) && tot_final_conversion && (add_channel_hr_p||add_channel_lr_p))
add_channel <= 1;
else
add_channel <= 0;
end
end
always @(posedge sysmon_rst or posedge DCLK_in) begin //at initialization or sequence restart
if( sysmon_rst) begin
for(kk=0; kk<=CONV_CNT_P; kk=kk+1) begin
seq_hr_mem[kk] = 0;
seq_lr_mem[kk] = 0;
hr_tot_chan = 0;
lr_tot_chan = 0;
lr_calib_on = 0;
end
end
else if(initialize[1] || add_channel) begin
lr_calib_on = 0;
if (single_pass_active || cont_seq_mode) begin //single pass or continuous sequence mode
// high rate sequence
hr_tot_chan = 0;
for (si=0; (si<= 47&&hr_tot_chan<=31); si=si+1) begin
if ((seq_hr_chan_reg_comb[si] ==1) //begin
|| (si==0 && seq_hr_chan_reg_comb[0]==0 && single_pass_active)) begin //calibration has to be added to single pass mode if not available
seq_hr_mem[hr_tot_chan] = si;
hr_tot_chan = hr_tot_chan + 1;
//seq_hr_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31.
if (hr_tot_chan==32)
$display ("Info: [Unisim %s-60] Max allowed channels are 31. Please check the high rate channel selection (46h,48h,49h). After 31, channels will be ignored.", MODULE_NAME);
end
end
if (cont_seq_mode) begin
//review for low rate high rate selection interaction
lr_tot_chan = 0;
for (si=0; si<= 47; si=si+1) begin
if (seq_lr_chan_reg_comb[si] ==1) begin
//low rate
if(seq_lr_chan_reg_comb[si]==seq_hr_chan_reg_comb[si] && !((si>=1 && si<=4)||si==15||(si>=36 && si<=47)) ) begin //CR 863886
//handle duplicates first
case (si)
6'h00 : begin
$display ("Info: [Unisim %s-29] In attribute INIT_7A[0], Calibration has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME);
lr_calib_on=0;
end
6'h05 : $display ("Info: [Unisim %s-30] In attribute INIT_7A[5], VCC_PSAUX has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h06 : $display ("Info: [Unisim %s-31] In attribute INIT_7A[6], VCC_PSINTFP has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h07 : $display ("Info: [Unisim %s-32] In attribute INIT_7A[7], VCC_PSINTLP has already been selected for the ADC channel sequence with INIT_48[0]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h08 : $display ("Info: [Unisim %s-33] In attribute INIT_7A[8], TEMPERATURE has already been selected for the ADC channel sequence with INIT_48[8]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h09 : $display ("Info: [Unisim %s-34] In attribute INIT_7A[9], INT_AVG has already been selected for the ADC channel sequence with INIT_48[9]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h0A : $display ("Info: [Unisim %s-35] In attribute INIT_7A[10], AUX_AVG has already been selected for the ADC channel sequence with INIT_48[10]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h0B : $display ("Info: [Unisim %s-36] In attribute INIT_7A[11], VpVn has already been selected for the ADC channel sequence with INIT_48[11]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h0C : $display ("Info: [Unisim %s-37] In attribute INIT_7A[12], VREFP has already been selected for the ADC channel sequence with INIT_48[12]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h0D : $display ("Info: [Unisim %s-38] In attribute INIT_7A[13], VREFN has already been selected for the ADC channel sequence with INIT_48[13]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h0E : $display ("Info: [Unisim %s-39] In attribute INIT_7A[14], BRAM has already been selected for the ADC channel sequence with INIT_48[14]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h10, 6'h11, 6'h12, 6'h13, 6'h14, 6'h15, 6'h16, 6'h17,6'h18, 6'h19, 6'h1A, 6'h1B,6'h1C, 6'h1D, 6'h1E, 6'h1F :
$display ("Info: [Unisim %s-41] In attribute INIT_7B[%0d], auxiliary analog input has already been selected for the ADC channel sequence with INIT_49[%0d]. It will be ignored in the low rate sequence.", MODULE_NAME, (si-16), (si-16));
6'h20 : $display ("Info: [Unisim %s-42] In attribute INIT_7C[0], USER0 has already been selected for the ADC channel sequence with INIT_46[0]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h21 : $display ("Info: [Unisim %s-43] In attribute INIT_7C[1], USER1 has already been selected for the ADC channel sequence with INIT_46[1]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h22 : $display ("Info: [Unisim %s-44] In attribute INIT_7C[2], USER2 has already been selected for the ADC channel sequence with INIT_46[2]. It will be ignored in the low rate sequence.", MODULE_NAME);
6'h23 : $display ("Info: [Unisim %s-45] In attribute INIT_7C[3], USER3 has already been selected for the ADC channel sequence with INIT_46[3]. It will be ignored in the low rate sequence.", MODULE_NAME);
default : $display ("Info: [Unisim %s-40] In attribute INIT_7A, INIT_7B or INIT_7C, same selections have already been selected for the ADC channel sequence with INIT_46[],INIT_48[], or INIT_49[]. They will be ignored in the low rate sequence.", MODULE_NAME);
endcase
end
else begin
//not duplicate in low and high rate, only in low rate. stays as is.
seq_lr_mem[lr_tot_chan] = si; //seq_lr_mem possible max is 33 - 1 = 32 max channels. Max allowed channels are 31.
lr_tot_chan = lr_tot_chan + 1;
if(si==0 && seq_lr_chan_reg_comb[0]==1)
lr_calib_on = 1;
end
end
else if(seq_hr_chan_reg_comb[si]==0 &&(si==0 || si==8)) begin
// handle missing ones
// seq_lr_chan_reg_comb[si]==0. Calibration and temperature are disabled in both by the user
seq_lr_mem[lr_tot_chan] = si;
lr_tot_chan = lr_tot_chan + 1;
if(si==0) begin
lr_calib_on = 1;
$display ("Info: [Unisim %s-51] Neither attribute INIT_7A[0] nor INIT_48[0] have been selected. Calibration will be enabled in the low rate sequence anyway.", MODULE_NAME);
end
else //si==8
$display ("Info: [Unisim %s-52] Neither attribute INIT_7A[8] nor INIT_48[8] have been selected. Temperature will be enabled in the low rate sequence anyway.", MODULE_NAME);
end
end
end //for
if(hr_tot_chan==0) begin
$display ("Error: [Unisim %s-65] No channel was selected for HR. This is not a valid option. Simulation exiting.", MODULE_NAME);
#1 $finish;
end
end //cont_seq_mode for low rate
else if (default_mode ) begin //default mode
if(ext_mux)
$display("Info: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in default mode. Instance: %m", MODULE_NAME);
if (SIM_DEVICE == "ULTRASCALE_PLUS" || SIM_DEVICE == "ULTRASCALE_PLUS_ES1" || SIM_DEVICE == "ULTRASCALE_PLUS_ES2") begin
hr_tot_chan = 5;
seq_hr_mem[0] = 0;
seq_hr_mem[1] = 8;
seq_hr_mem[2] = 9;
seq_hr_mem[3] = 10;
seq_hr_mem[4] = 14;
end
else if (SIM_DEVICE == "ZYNQ_ULTRASCALE" || SIM_DEVICE == "ZYNQ_ULTRASCALE_ES1" || SIM_DEVICE == "ZYNQ_ULTRASCALE_ES2") begin
hr_tot_chan = 8;
seq_hr_mem[0] = 0;
seq_hr_mem[1] = 5;
seq_hr_mem[2] = 6;
seq_hr_mem[3] = 7;
seq_hr_mem[4] = 8;
seq_hr_mem[5] = 9;
seq_hr_mem[6] = 10;
seq_hr_mem[7] = 14;
end
end // default_mode
else if(single_chan_mode && ext_mux)
$display("Info: [Unisim %s-50] External mux selection will be disregarded as SYSMON is in single channel mode. Instance: %m", MODULE_NAME);
end //initialize[1] || add_channel
end //always
wire [15:0] chan_avg_hr_reg1;
wire [15:0] chan_avg_hr_reg2;
wire [15:0] chan_avg_hr_reg3;
wire [47:0] seq_avg_hr_reg_comb ;
wire chan_avg_hr_set;
wire [15:0] chan_avg_lr_reg1;
wire [15:0] chan_avg_lr_reg2;
wire [15:0] chan_avg_lr_reg3;
wire [47:0] seq_avg_lr_reg_comb;
wire chan_avg_lr_set;
assign chan_avg_hr_reg1 = seq_hr_chan_reg1 & seq_avg_reg1;
assign chan_avg_hr_reg2 = seq_hr_chan_reg2 & seq_avg_reg2;
assign chan_avg_hr_reg3 = seq_hr_chan_reg3 & seq_avg_reg3;
assign seq_avg_hr_reg_comb = {chan_avg_hr_reg3, chan_avg_hr_reg2, chan_avg_hr_reg1};
assign chan_avg_hr_set = |seq_avg_hr_reg_comb;
assign chan_avg_lr_reg1 = seq_lr_chan_reg1 & seq_avg_reg1;
assign chan_avg_lr_reg2 = seq_lr_chan_reg2 & seq_avg_reg2;
assign chan_avg_lr_reg3 = seq_lr_chan_reg3 & seq_avg_reg3;
assign seq_avg_lr_reg_comb = {chan_avg_lr_reg3, chan_avg_lr_reg2, chan_avg_lr_reg1};
assign chan_avg_lr_set = |seq_avg_lr_reg_comb;
//hr_lr_tot_per is the total period of the combined high and low rate sequences
assign int_tot_per = (hr_tot_chan * (4 ** lr_rate)) +1;
assign hr_lr_tot_per = lr_chan_on ? (int_tot_per * lr_tot_chan) : hr_tot_chan ;
assign tot_per = cont_seq_mode ? hr_lr_tot_per:
(single_pass_active|| default_mode) ? hr_tot_chan :
1; //single_chan_mode
// or in unknown mode just calibrate
// CR-961533
// When SLOW_SEQ or SLOW_EOS are changed dynamically, the change should take place
// after mode change as per rtl design.
always @(posedge DCLK_in or posedge sysmon_rst) begin
if (sysmon_rst) begin
lr_eos <= 0;
lr_rate <= 0;
end
else if(initialize[0]) begin
lr_eos[1:0] <= cfg_reg4[11:10];
lr_rate[1:0] <= cfg_reg4[9:8];
end
end
integer conv_tot_count;
integer conv_hr_count;
integer conv_lr_count;
wire [15:0] conv_hr_count_p;
wire [15:0] conv_lr_count_p;
integer avg_loop_count_hr;
integer avg_loop_count_lr;
assign avg_final_loop = (!avg_en) ||
(!avg_cur) ||
(avg_final_loop_hr && !seq_lr_selected) ||
(avg_final_loop_lr && seq_lr_selected) ;
assign avg_final_loop_hr = (avg_loop_count_hr == avg_amount);
assign avg_final_loop_lr = (avg_loop_count_lr == avg_amount);
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
conversion_before_calib <= 0;
hr_final_conversion <= 0;
tot_final_conversion <= 0;
lr_final_conversion <= 0;
end
else begin
if(adc_state==ST_A_CALIB || adc_state==ST_A_FIRST_CALIB) begin
conversion_before_calib <= 0;
hr_final_conversion <= 0;
tot_final_conversion <= 0;
lr_final_conversion <= 0;
end
else if(conv_track)begin //check
conversion_before_calib <= (CHANNEL_out!=8) &&
~(event_driven_mode && single_pass_mode) &&
((lr_chan_on &&
((~lr_calib_on && conv_hr_count==hr_tot_chan-1 && seq_lr_selected) ||
( lr_calib_on && conv_tot_count==tot_per-1))) ||
(!lr_chan_on && conv_hr_count==hr_tot_chan-1) );
hr_final_conversion <= (((hr_tot_chan==1 && !lr_calib_on) || CHANNEL_out!=8) && (conv_hr_count==hr_tot_chan-1)) ||
(single_chan_mode && CHANNEL_out!=8);
tot_final_conversion <= (CHANNEL_out!=8) &&(conv_tot_count==tot_per-1);
lr_final_conversion <= (~lr_calib_on && conv_tot_count==tot_per-1) ||
(lr_calib_on && lr_tot_chan>1 && conv_tot_count==tot_per-int_tot_per) ||
(lr_calib_on && lr_tot_chan==1);
end
end
end //always
assign seq_lr_selected_p = lr_chan_on && //!seq_lr_selected &&
((lr_calib_on && ( conv_tot_count %int_tot_per)==int_tot_per-1) || //calibration being always on puts lr on first if calib is on lr channel.
(!lr_calib_on&& ( conv_tot_count %int_tot_per)==int_tot_per-2) ); //otherwise it is the last
//pre calculate
assign conv_hr_count_p = (conv_hr_count < hr_tot_chan-1) ? (conv_hr_count+1) : (event_driven_mode && single_pass_mode) ? 1 : 0;
assign conv_lr_count_p = (conv_lr_count < lr_tot_chan-1) ? (conv_lr_count+1) : 0;
always @(posedge sysmon_rst or posedge initialize[2] or posedge chan_asrt_1) begin
if(sysmon_rst) begin
conv_tot_count <= 0;
conv_hr_count <= 0;
conv_lr_count <= 0;
seq_lr_selected <= 0;
end
else begin
if( initialize[2] ) begin
conv_tot_count <= 0;
if(cont_seq_mode && lr_calib_on) begin
seq_lr_selected <= 1;
conv_hr_count <= 0;
conv_lr_count <= 0;
end
else begin
seq_lr_selected <= 0;
conv_hr_count <= 0;
conv_lr_count <= 0;
end
end
else if(chan_asrt_1 ) begin
//increase counters
if (conv_tot_count<tot_per-1)
conv_tot_count <= conv_tot_count+1;
else begin
conv_tot_count <= 0;
end
if(seq_lr_selected) begin
if(conv_lr_count < lr_tot_chan-1)
conv_lr_count <= conv_lr_count +1;
else
conv_lr_count <= 0;
end
if(!seq_lr_selected_p && !(seq_lr_selected && lr_calib_on && st_first_calib_chan)) begin
if(conv_hr_count < hr_tot_chan-1)
conv_hr_count <= conv_hr_count +1;
else if(event_driven_mode && single_pass_mode)
conv_hr_count <= 1;
else
conv_hr_count <= 0;
end
if(seq_lr_selected)
seq_lr_selected <= 0;
else if ( lr_chan_on &&
((lr_calib_on && (conv_tot_count%int_tot_per)==int_tot_per-1) || //calibration being always on puts lr on first if calib is on lr channel.
(!lr_calib_on&& (conv_tot_count%int_tot_per)==int_tot_per-2) ) //otherwise it is the last
)
seq_lr_selected <= 1;
end
end
end //always
//align seq_lr_selected to chan_asrt_3, delay 2 DCLK_in cycles
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
seq_lr_selected_d <= 0;
else
seq_lr_selected_d <= {seq_lr_selected_d[0], seq_lr_selected};
end
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
avg_loop_count_lr <= 0;
avg_loop_count_hr <= 0;
end
else begin
if( initialize[2] ) begin
avg_loop_count_lr <= 0;
avg_loop_count_hr <= 0;
end
else if(chan_asrt_3 ) begin
if(!seq_lr_selected_d[1] && hr_final_conversion) begin
if(single_pass_mode || !avg_en || ( avg_en && avg_loop_count_hr == avg_amount))
avg_loop_count_hr <= 0;
else
avg_loop_count_hr <= avg_loop_count_hr +1;
end
if(seq_lr_selected_d[1] && lr_final_conversion) begin
if(!avg_en || (avg_en && avg_loop_count_lr == avg_amount))
avg_loop_count_lr <= 0;
else
avg_loop_count_lr <= avg_loop_count_lr +1;
end
end
end
end //always
always @(posedge sysmon_rst or posedge initialize[2] or posedge chan_asrt_2) begin
if(sysmon_rst) begin
chan_reg_id_cur <= 0;
chan_out_id_cur <= 8;
acq_ext_cur <= 0;
bipolar_cur <= 0;
avg_cur <= 0;
chan_reg_id_next <= 0;
chan_out_id_next <= 8;
acq_ext_next <= 0;
bipolar_next <= 0;
avg_next <= 0;
end
else if(initialize[2] )begin
chan_reg_id_cur <= 0;
chan_out_id_cur <= 8;
acq_ext_cur <= 0;
bipolar_cur <= 0;
avg_cur <= 0;
if(cont_seq_mode ||single_pass_active ||default_mode) begin
if(cont_seq_mode && lr_calib_on) begin
chan_reg_id_next <= seq_hr_mem[0];
chan_out_id_next <= conv_combregid_to_chanout(seq_hr_mem[0]);
acq_ext_next <= seq_acq_ext_reg_comb[seq_hr_mem[0]];
bipolar_next <= seq_bipolar_reg_comb[seq_hr_mem[0]];
avg_next <= avg_en ? seq_avg_hr_reg_comb[seq_hr_mem[0]] : 0;
end
else if(cont_seq_mode && lr_chan_on && int_tot_per==2 ) begin //same as lr_rate==LR_EVERY_OTHER && hr_tot_chan==1
chan_reg_id_next <= seq_lr_mem[0];
chan_out_id_next <= conv_combregid_to_chanout(seq_lr_mem[0]);
acq_ext_next <= seq_acq_ext_reg_comb[seq_lr_mem[0]];
bipolar_next <= seq_bipolar_reg_comb[seq_lr_mem[0]];
avg_next <= seq_avg_lr_reg_comb[seq_lr_mem[0]];
end
else begin //single_pass_active, default_mode, or cont_seq_mode with next one on hr channel
chan_reg_id_next <= seq_hr_mem[1];
chan_out_id_next <= conv_combregid_to_chanout(seq_hr_mem[1]);
acq_ext_next <= seq_acq_ext_reg_comb[seq_hr_mem[1]];
bipolar_next <= seq_bipolar_reg_comb[seq_hr_mem[1]];
avg_next <= avg_en ? (default_mode ? 1: seq_avg_hr_reg_comb[seq_hr_mem[1]]) : 0;
end
end
else if(single_chan_mode) begin
//first 8, then the same channel continuously
chan_reg_id_next <= conv_combregid_to_chanout(single_chan_id);
chan_out_id_next <= single_chan_id;
// For single channel the user doesn't have to select via control registers.
// However acquisition extension and bipolar mode are only available to analog channels.
if(single_chan_id==3 || (single_chan_id>=16 && single_chan_id<=31)) begin
acq_ext_next <= acq_ext;
bipolar_next <= bipolar_mode;
end
else begin
acq_ext_next <= 0;
bipolar_next <= 0;
if(acq_ext || bipolar_mode)
$display("Info: [Unisim %s-68] In single channel mode, acquisition extension or bipolar mode cannot be enabled for non-analog channels. They will be ignored. Instance: %m", MODULE_NAME);
end
avg_next <= avg_en;
end
end //initialization
else if(chan_asrt_2) begin
//Update current *_cur <=*_next;
chan_reg_id_cur <= chan_reg_id_next;
chan_out_id_cur <= chan_out_id_next;
acq_ext_cur <= acq_ext_next;
bipolar_cur <= bipolar_next;
avg_cur <= avg_next;
//Update *_next
if(single_pass_active ||
default_mode ||
cont_seq_only_hr ||
(lr_chan_on && !seq_lr_selected_p)
) begin
chan_reg_id_next <= seq_hr_mem[conv_hr_count_p];
chan_out_id_next <= conv_combregid_to_chanout(seq_hr_mem[conv_hr_count_p]);
acq_ext_next <= seq_acq_ext_reg_comb[seq_hr_mem[conv_hr_count_p]];
bipolar_next <= seq_bipolar_reg_comb[seq_hr_mem[conv_hr_count_p]];
avg_next <= avg_en ? (default_mode ? 1: seq_avg_hr_reg_comb[seq_hr_mem[conv_hr_count_p]]) : 0;
end
else if (cont_seq_mode) begin// lr_tot_chan>0 && seq_lr_selected
chan_reg_id_next <= seq_lr_mem[conv_lr_count];
chan_out_id_next <= conv_combregid_to_chanout(seq_lr_mem[conv_lr_count]);
acq_ext_next <= seq_acq_ext_reg_comb[seq_lr_mem[conv_lr_count]];
bipolar_next <= seq_bipolar_reg_comb[seq_lr_mem[conv_lr_count]];
avg_next <= avg_en ? seq_avg_lr_reg_comb[seq_lr_mem[conv_lr_count]] : 0 ;
end
//else if single_chan_mode: in single channel mode no need to update the next.
end
end
//-----------------------------------------------------------
// EOC and EOS
//-----------------------------------------------------------
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst) begin
EOC_out <= 0;
EOS_out <= 0;
end
else begin
if(eoc_asrt && (!avg_en || !avg_cur || (avg_en && avg_cur && avg_final_loop) ) ) begin
EOC_out <= 1;
if(((!lr_chan_on && hr_final_conversion) || // eos selection is available only when lr chan is active. otherwise always on.
(lr_chan_on && hr_final_conversion && !seq_lr_selected && lr_eos!=LR_EOS_LR_ONLY) || //hr
(lr_chan_on && lr_final_conversion && seq_lr_selected && (lr_eos==LR_EOS_HR_LR || lr_eos==LR_EOS_LR_ONLY)) //lr
) && !single_chan_mode) //CR-1049898
EOS_out <= 1;
else
EOS_out <= 0;
end
else begin
EOC_out <= 0;
EOS_out <= 0;
end
end
end
//-----------------------------------------------------
// Conversion
//-----------------------------------------------------
always @(posedge sysmon_rst or posedge chan_asrt_1) begin
if (sysmon_rst == 1) begin
mn_mux_in <= 0.0;
end
else if(chan_asrt_1) begin
if ( chan_out_id_next == 7 || (chan_out_id_next >= 9 && chan_out_id_next <= 12) || chan_out_id_next >= 36)
$display("Warning: [Unisim %s-14] The analog channel %x at time %.3f ns is invalid. Check register 40h[5:0]. Instance: %m", MODULE_NAME, chan_out_id_next, $time/1000.0);
//K else if(bipolar_next) begin //can only be enabled for channels 3,16-31
else if ((chan_out_id_next == 3) || (chan_out_id_next >= 16 && chan_out_id_next <= 31)) begin
if (ext_mux_en) begin
tmp_v = $bitstoreal(mn_in_diff[ext_mux_chan_id]);
mn_mux_in <= tmp_v;
end
else begin
tmp_v = $bitstoreal(mn_in_diff[chan_out_id_next]);
mn_mux_in <= tmp_v;
end
end
else
mn_mux_in <= $bitstoreal(mn_in_uni[chan_out_id_next]);
end //chan_asrt_1
end //always
// Check if (Vp+Vn)/2 = 0.5 +/- 100 mv, unipolar only
//always @(posedge DCLK_in or posedge sysmon_rst ) begin
always @(posedge chan_asrt_3 ) begin
if (!sysmon_rst)
if( chan_asrt_3 && !bipolar_mode && ((chan_out_id_cur == 3) || (chan_out_id_cur >= 16 && chan_out_id_cur <= 31))) begin
chan_val_p_tmp = $bitstoreal(chan_val_tmp [chan_out_id_cur]);
chan_val_n_tmp = $bitstoreal(chan_valn_tmp[chan_out_id_cur]);
if (!bipolar_cur &&( chan_val_n_tmp > chan_val_p_tmp))
$display("Warning: [Unisim %s-8] The N input for external channel %x must be smaller than P input when in unipolar mode. (P=%0.2f N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
if (!bipolar_cur &&( chan_val_n_tmp > 0.5 || chan_val_n_tmp < 0.0))
$display("Warning: [Unisim %s-9] The range of N input for external channel %x should be between 0V to 0.5V when in unipolar mode. (N=%0.2f) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_n_tmp, $time/1000.0);
if (bipolar_cur && (((chan_val_p_tmp-chan_val_n_tmp) > 0.5)|| ((chan_val_p_tmp-chan_val_n_tmp) <-0.5)))
$display("Warning: [Unisim %s-56] Vp-Vn for external channel %x must be in [-0.5,0.5] V range when in bipolar mode. (P=%0.2f N=%0.2f ) at %.3f ns. Instance: %m", MODULE_NAME, chan_out_id_cur, chan_val_p_tmp, chan_val_n_tmp, $time/1000.0);
end
end
always @(posedge chan_asrt_3) begin
if (chan_out_id_cur == 0) begin // adc temperature conversion
if(SIM_DEVICE=="ULTRASCALE_PLUS" || SIM_DEVICE=="ZYNQ_ULTRASCALE" || SIM_DEVICE=="ULTRASCALE_PLUS_ES2" || SIM_DEVICE=="ZYNQ_ULTRASCALE_ES2")
adc_temp_result = (mn_mux_in + 280.2308787) * 0.00196343 * 65535.0; //CR 961722 10/20/2016. Internal reference
else // ES1
adc_temp_result = (mn_mux_in + 273.15) * 0.00203580 * 65535.0; //CR 912341
if (adc_temp_result >= 65535.0)
conv_result_int = 65535;
else if (adc_temp_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_temp_result);
if (adc_temp_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (chan_out_id_cur == 1 || chan_out_id_cur == 2 || chan_out_id_cur ==6 ||
chan_out_id_cur == 13 || chan_out_id_cur == 14 || chan_out_id_cur == 15 ||
(chan_out_id_cur >= 32 && chan_out_id_cur <= 35)) begin // internal power conversion
if((chan_out_id_cur >= 32 && chan_out_id_cur <= 35) &&
bank_sel_6V[chan_out_id_cur-32]==1) // CR 949547
adc_intpwr_result = mn_mux_in * 65536.0 / 6.0; //6V range is selected, only available for VUSER ports
else
adc_intpwr_result = mn_mux_in * 65536.0 / 3.0; //3V range, hence divide by 3
if (adc_intpwr_result >= 65535.0) // max value is 'hFFFF
conv_result_int = 65535;
else if (adc_intpwr_result < 0.0) // min value is 0
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_intpwr_result);
if (adc_intpwr_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else if (chan_out_id_cur == 3 || (chan_out_id_cur >=16 && chan_out_id_cur <= 31)) begin
adc_ext_result = (mn_mux_in) * 65536.0 ; //1V input range, hence divide by 1
if (bipolar_cur == 1) begin //bipolar maps -0.5V to 0.5V to -32768-32767 range
if (adc_ext_result > 32767.0) //+0.5V
conv_result_int = 32767;
else if (adc_ext_result < -32768.0) //-0.5V
conv_result_int = -32768;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
else begin //unipolar maps 0V to 1V to 0-65535 range
if (adc_ext_result > 65535.0)
conv_result_int = 65535;
else if (adc_ext_result < 0.0)
conv_result_int = 0;
else begin
conv_result_int = $rtoi(adc_ext_result);
if (adc_ext_result - conv_result_int > 0.9999)
conv_result_int = conv_result_int + 1;
end
end
end
else begin //invalid channel
conv_result_int = 0;
end
conv_result = conv_result_int;
end // always
always @(posedge DCLK_in or posedge sysmon_rst) begin
if (sysmon_rst == 1)
conv_result_reg <= 0;
else begin
if (chan_asrt_4)
conv_result_reg <= conv_result;
end
end
//---------------------------------------------------------
// average
//---------------------------------------------------------
assign averaging = default_mode ? 2'b01 : cfg_reg0[13:12];
assign avg_amount = averaging==2'b00 ? 0 :
averaging==2'b01 ? 15 :
averaging==2'b10 ? 63 :
averaging==2'b11 ? 255 :
0;
// In continuous mode, at least 1 channel in HR or LR should have averaging
// enabled so that averaging is practically enabled.
assign avg_en = single_pass_mode ? 0 :
default_mode ? 1 :
(averaging!=2'b00 && (single_chan_mode || chan_avg_hr_set || chan_avg_lr_set));
always @(posedge DCLK_in or posedge sysmon_rst) begin
if (sysmon_rst) begin
conv_acc_result = 16'd0;
conv_acc_vec = 24'd0;
for (j = 0; j <= 63; j = j + 1)
conv_acc[j] = 0;
end
else begin
if(EOC_out==1 && avg_cur && avg_final_loop) begin
conv_acc_result = 16'd0;
conv_acc_vec = 24'd0;
conv_acc[chan_out_id_cur] = 0;
end
else if (chan_asrt_4 && avg_cur) begin
conv_acc[chan_out_id_cur] = conv_acc[chan_out_id_cur] + conv_result_int;
conv_acc_vec = conv_acc[chan_out_id_cur];
case (averaging)
2'b00 : conv_acc_result = 16'd0;
2'b01 : conv_acc_result = conv_acc_vec[19:4];
2'b10 : conv_acc_result = conv_acc_vec[21:6];
2'b11 : conv_acc_result = conv_acc_vec[23:8];
endcase
end
end // if (sysmon_rst == 0)
end
// end average
always @( posedge DCLK_in or posedge alm_rst or posedge gsr_in ) begin
if(alm_rst ==1 || gsr_in==1) begin
data_reg[32] = 16'h0000;
data_reg[33] = 16'h0000;
data_reg[34] = 16'h0000;
data_reg[35] = 16'h0000;
data_reg[36] = 16'hFFFF;
data_reg[37] = 16'hFFFF;
data_reg[38] = 16'hFFFF;
data_reg[39] = 16'hFFFF;
data_reg[40] = 16'h0000;
data_reg[41] = 16'h0000;
data_reg[42] = 16'h0000;
data_reg[44] = 16'hFFFF;
data_reg[45] = 16'hFFFF;
data_reg[46] = 16'hFFFF;
dr_sram [160] = 16'h0000;
dr_sram [161] = 16'h0000;
dr_sram [162] = 16'h0000;
dr_sram [163] = 16'h0000;
dr_sram [168] = 16'hFFFF;
dr_sram [169] = 16'hFFFF;
dr_sram [170] = 16'hFFFF;
dr_sram [171] = 16'hFFFF;
end
else if (alm_asrt && avg_final_loop) begin
// current or averaged values' update to status registers
if ((chan_out_id_cur >= 0 && chan_out_id_cur <= 3) || (chan_out_id_cur == 6) ||
(chan_out_id_cur >= 13 && chan_out_id_cur <= 31)) begin
if (avg_cur == 0)
data_reg[chan_out_id_cur] <= conv_result_reg;
else if(avg_final_loop)
data_reg[chan_out_id_cur] <= conv_acc_result;
end
else if (chan_out_id_cur >= 32 && chan_out_id_cur <= 35) begin //VUser0-3
if (avg_cur == 0)
dr_sram[chan_out_id_cur + 96] <= conv_result_reg; //80h-83h
else if(avg_final_loop)
dr_sram[chan_out_id_cur + 96] <= conv_acc_result;
end
else if (chan_out_id_cur == 4) // VREFP
data_reg[chan_out_id_cur] <= 16'h0000; // CR-961722 Simulation always simulates the internal reference behavior. Hence VrefP=0V
else if (chan_out_id_cur == 5) // VREFN
data_reg[chan_out_id_cur] <= 16'h0000;
//min and max values' update
if (chan_out_id_cur == 0 || chan_out_id_cur == 1 || chan_out_id_cur == 2) begin //TEMPERATURE, VCCINT and VCCAUX max and min
if (avg_cur == 0) begin
if (conv_result_reg > data_reg[32 + chan_out_id_cur])
data_reg[32 + chan_out_id_cur] <= conv_result_reg;
if (conv_result_reg < data_reg[36 + chan_out_id_cur])
data_reg[36 + chan_out_id_cur] <= conv_result_reg;
end
else if(avg_final_loop) begin
if (conv_acc_result > data_reg[32 + chan_out_id_cur])
data_reg[32 + chan_out_id_cur] <= conv_acc_result;
if (conv_acc_result < data_reg[36 + chan_out_id_cur])
data_reg[36 + chan_out_id_cur] <= conv_acc_result;
end
end
else if (chan_out_id_cur == 6) begin //VCCBRAM max and min
if (avg_cur == 0) begin
if (conv_result_reg > data_reg[35])
data_reg[35] <= conv_result_reg;
if (conv_result_reg < data_reg[39])
data_reg[39] <= conv_result_reg;
end
else if(avg_final_loop) begin
if (conv_acc_result > data_reg[35])
data_reg[35] <= conv_acc_result;
if (conv_acc_result < data_reg[39])
data_reg[39] <= conv_acc_result;
end
end
else if (chan_out_id_cur >= 13 && chan_out_id_cur <= 15) begin // VPSINTLP, VPSINTFP , VPSAUX
if (avg_cur == 0) begin
if (conv_result_reg > data_reg[27+chan_out_id_cur])
data_reg[27+chan_out_id_cur] <= conv_result_reg;
if (conv_result_reg < data_reg[31+chan_out_id_cur])
data_reg[31+chan_out_id_cur] <= conv_result_reg;
end
else if(avg_final_loop) begin
if (conv_acc_result > data_reg[27+chan_out_id_cur])
data_reg[27+chan_out_id_cur] <= conv_acc_result;
if (conv_acc_result < data_reg[31+chan_out_id_cur])
data_reg[31+chan_out_id_cur] <= conv_acc_result;
end
end
else if (chan_out_id_cur >= 32 && chan_out_id_cur <=35) begin //Vuser0-3
if (avg_cur == 0) begin
if (conv_result_reg < dr_sram[chan_out_id_cur+136])
dr_sram[chan_out_id_cur+136] <= conv_result_reg;
if (conv_result_reg > dr_sram[chan_out_id_cur+128])
dr_sram[chan_out_id_cur+128] <= conv_result_reg;
end
else if(avg_final_loop) begin
if (conv_acc_result < dr_sram[chan_out_id_cur+136])
dr_sram[chan_out_id_cur+136] <= conv_acc_result;
if (conv_acc_result > dr_sram[chan_out_id_cur+128])
dr_sram[chan_out_id_cur+128] <= conv_acc_result;
end
end
end // ( rst_lock == 0)
end//always
always @(posedge DCLK_in or posedge sysmon_rst) begin
if(sysmon_rst)
data_written <= 0;
else if(chan_asrt_5) begin
if (avg_cur)
data_written <= conv_acc_result;
else
data_written <= conv_result_reg;
end
end
always @( posedge DCLK_in or posedge alm_rst or posedge gsr_in ) begin
if(alm_rst ==1 || gsr_in==1) begin
ot_out_reg <= 0;
alm_out_reg <= 8'b0;
end
else if (alm_asrt && avg_final_loop) begin
if (chan_out_id_cur == 0) begin // temperature
if (data_written[15:4] >= ot_limit_reg[15:4]) begin
ot_out_reg <= 1;
end else if (dr_sram[8'h57][0] == 1'b1) begin
if (data_written[15:1] < dr_sram[8'h57][15:1]) begin
ot_out_reg <= 1;
end else begin
ot_out_reg <= 0;
end
end else if (data_written[15:1] < dr_sram[8'h57][15:1]) begin
ot_out_reg <= 0;
end
if (data_written > dr_sram[8'h50]) begin
alm_out_reg[0] <= 1;
end else if (dr_sram[8'h54][0] == 1'b1) begin
if (data_written[15:1] < dr_sram[8'h54][15:1]) begin
alm_out_reg[0] <= 1;
end else begin
alm_out_reg[0] <= 0;
end
end else if (data_written[15:1] < dr_sram[8'h54][15:1]) begin
alm_out_reg[0] <= 0;
end
end
if (chan_out_id_cur == 1) begin // VCC INT
if (data_written > dr_sram[8'h51] || data_written < dr_sram[8'h55])
alm_out_reg[1] <= 1;
else
alm_out_reg[1] <= 0;
end
if (chan_out_id_cur == 2) begin //VCCAUX
if (data_written > dr_sram[8'h52] || data_written < dr_sram[8'h56])
alm_out_reg[2] <= 1;
else
alm_out_reg[2] <= 0;
end
if (chan_out_id_cur == 6) begin // VCC BRAM
if (data_written > dr_sram[8'h58] || data_written < dr_sram[8'h5C])
alm_out_reg[3] <= 1;
else
alm_out_reg[3] <= 0;
end
if (chan_out_id_cur == 13) begin //VCC PSINTLP
if (data_written > dr_sram[8'h59] || data_written < dr_sram[8'h5D])
alm_out_reg[4] <= 1;
else
alm_out_reg[4] <= 0;
end
if (chan_out_id_cur == 14) begin // VCC PSINTFP
if (data_written > dr_sram[8'h5A] || data_written < dr_sram[8'h5E])
alm_out_reg[5] <= 1;
else
alm_out_reg[5] <= 0;
end
if (chan_out_id_cur == 15) begin // VCC PSAUX
if (data_written > dr_sram[8'h5B] || data_written < dr_sram[8'h5F])
alm_out_reg[6] <= 1;
else
alm_out_reg[6] <= 0;
end
if (chan_out_id_cur == 32) begin // VUSER 0
if (data_written > dr_sram[8'h60] || data_written < dr_sram[8'h68])
alm_out_reg[8] <= 1;
else
alm_out_reg[8] <= 0;
end
if (chan_out_id_cur == 33) begin // VUSER 1
if (data_written > dr_sram[8'h61] || data_written < dr_sram[8'h69])
alm_out_reg[9] <= 1;
else
alm_out_reg[9] <= 0;
end
if (chan_out_id_cur == 34) begin // VUSER 2
if (data_written > dr_sram[8'h62] || data_written < dr_sram[8'h6A])
alm_out_reg[10] <= 1;
else
alm_out_reg[10] <= 0;
end
if (chan_out_id_cur == 35) begin // VUSER 3
if (data_written > dr_sram[8'h63] || data_written < dr_sram[8'h6B])
alm_out_reg[11] <= 1;
else
alm_out_reg[11] <= 0;
end
end//rst_lock
end // always
always @(*) begin
ut_fault = ut_fault_reg & ot_en;
ut_warn = ut_warn_reg & alm_en[0];
alm_ut[11:1] = alm_ut_reg[11:1] & alm_en[11:1];
end
always @( posedge DCLK_in or posedge sysmon_rst ) begin
if(sysmon_rst ==1 ) begin
ut_fault_reg <= 0;
ut_warn_reg <= 0;
alm_ut_reg <= 'd0;
end
else if (alm_asrt && avg_final_loop) begin
case (chan_out_id_cur)
'd0: begin //temperature
ut_fault_reg <= (data_written < dr_sram[8'h57]) ? 1 : 0;
ut_warn_reg <= (data_written < dr_sram[8'h54]) ? 1 : 0;
end
'd1: alm_ut_reg[1] <= (data_written < dr_sram[8'h55]) ? 1 : 0; // VCC INT
'd2: alm_ut_reg[2] <= (data_written < dr_sram[8'h56]) ? 1 : 0; // VCCAUX
'd6: alm_ut_reg[3] <= (data_written < dr_sram[8'h5C]) ? 1 : 0; // VCC BRAM
'd13: alm_ut_reg[4] <= (data_written < dr_sram[8'h5D]) ? 1 : 0; // VCC PSINTLP
'd14: alm_ut_reg[5] <= (data_written < dr_sram[8'h5E]) ? 1 : 0; // VCC PSINTFP
'd15: alm_ut_reg[6] <= (data_written < dr_sram[8'h5F]) ? 1 : 0; // VCC PSAUX
'd32: alm_ut_reg[8] <= (data_written < dr_sram[8'h68]) ? 1 : 0; // VUSER 0
'd33: alm_ut_reg[9] <= (data_written < dr_sram[8'h69]) ? 1 : 0; // VUSER 1
'd34: alm_ut_reg[10] <= (data_written < dr_sram[8'h6A]) ? 1 : 0; // VUSER 2
'd35: alm_ut_reg[11] <= (data_written < dr_sram[8'h6B]) ? 1 : 0; // VUSER 3
default: ; //do nothing
endcase
end
end//always
always @(*) begin
OT_out = ot_out_reg & ot_en;
ALM_out[6:0] = alm_out_reg[6:0] & alm_en[6:0];
ALM_out[7] = |ALM_out[6:0];
ALM_out[11:8] = alm_out_reg[11:8] & alm_en[11:8];
ALM_out[14:12] = 'd0; // Reserved
ALM_out[15] = (|ALM_out[11:8]) | (|ALM_out[6:0]);
end
always @(posedge OT_out) begin
if(sysmon_rst==0 && ot_limit_reg[3:0]==4'b0011)
$display("Warning: [Unisim %s-25] OT is high and automatic shutdown in 53h has been enabled. Please refer to the Thermal Management section of the User Guide. Instance: %m", MODULE_NAME, $time/1000.0,);
end
// end alarm
//*** Timing_Checks_Start_here
`ifdef XIL_TIMING
reg notifier;
wire dclk_en_n;
wire dclk_en_p;
assign dclk_en_n = IS_DCLK_INVERTED_BIN;
assign dclk_en_p = ~IS_DCLK_INVERTED_BIN;
reg notifier_do;
wire rst_en_n = ~RESET_in && dclk_en_n;
wire rst_en_p = ~RESET_in && dclk_en_p;
always @(notifier) begin
alm_out_reg = 16'bx;
OT_out = 1'bx;
BUSY_out = 1'bx;
EOC_out = 1'bx;
EOS_out = 1'bx;
DRDY_out = 1'bx;
DO_out = 16'bx;
end
always @(notifier_do) begin
DRDY_out = 1'bx;
DO_out = 16'bx;
end
`endif
specify
(DCLK => ADC_DATA[0]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[10]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[11]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[12]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[13]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[14]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[15]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[1]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[2]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[3]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[4]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[5]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[6]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[7]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[8]) = (100:100:100, 100:100:100);
(DCLK => ADC_DATA[9]) = (100:100:100, 100:100:100);
(DCLK => ALM[0]) = (100:100:100, 100:100:100);
(DCLK => ALM[10]) = (100:100:100, 100:100:100);
(DCLK => ALM[11]) = (100:100:100, 100:100:100);
(DCLK => ALM[12]) = (100:100:100, 100:100:100);
(DCLK => ALM[13]) = (100:100:100, 100:100:100);
(DCLK => ALM[15]) = (100:100:100, 100:100:100);
(DCLK => ALM[1]) = (100:100:100, 100:100:100);
(DCLK => ALM[2]) = (100:100:100, 100:100:100);
(DCLK => ALM[3]) = (100:100:100, 100:100:100);
(DCLK => ALM[4]) = (100:100:100, 100:100:100);
(DCLK => ALM[5]) = (100:100:100, 100:100:100);
(DCLK => ALM[6]) = (100:100:100, 100:100:100);
(DCLK => ALM[7]) = (100:100:100, 100:100:100);
(DCLK => ALM[8]) = (100:100:100, 100:100:100);
(DCLK => ALM[9]) = (100:100:100, 100:100:100);
(DCLK => BUSY) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[0]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[1]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[2]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[3]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[4]) = (100:100:100, 100:100:100);
(DCLK => CHANNEL[5]) = (100:100:100, 100:100:100);
(DCLK => DO[0]) = (100:100:100, 100:100:100);
(DCLK => DO[10]) = (100:100:100, 100:100:100);
(DCLK => DO[11]) = (100:100:100, 100:100:100);
(DCLK => DO[12]) = (100:100:100, 100:100:100);
(DCLK => DO[13]) = (100:100:100, 100:100:100);
(DCLK => DO[14]) = (100:100:100, 100:100:100);
(DCLK => DO[15]) = (100:100:100, 100:100:100);
(DCLK => DO[1]) = (100:100:100, 100:100:100);
(DCLK => DO[2]) = (100:100:100, 100:100:100);
(DCLK => DO[3]) = (100:100:100, 100:100:100);
(DCLK => DO[4]) = (100:100:100, 100:100:100);
(DCLK => DO[5]) = (100:100:100, 100:100:100);
(DCLK => DO[6]) = (100:100:100, 100:100:100);
(DCLK => DO[7]) = (100:100:100, 100:100:100);
(DCLK => DO[8]) = (100:100:100, 100:100:100);
(DCLK => DO[9]) = (100:100:100, 100:100:100);
(DCLK => DRDY) = (100:100:100, 100:100:100);
(DCLK => EOC) = (100:100:100, 100:100:100);
(DCLK => EOS) = (100:100:100, 100:100:100);
(DCLK => I2C_SCLK_TS) = (100:100:100, 100:100:100);
(DCLK => I2C_SDA_TS) = (100:100:100, 100:100:100);
(DCLK => JTAGBUSY) = (100:100:100, 100:100:100);
(DCLK => JTAGLOCKED) = (100:100:100, 100:100:100);
(DCLK => JTAGMODIFIED) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[0]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[1]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[2]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[3]) = (100:100:100, 100:100:100);
(DCLK => MUXADDR[4]) = (100:100:100, 100:100:100);
(DCLK => OT) = (100:100:100, 100:100:100);
(DCLK => SMBALERT_TS) = (100:100:100, 100:100:100);
(RESET => BUSY) = (0:0:0, 0:0:0);
(posedge RESET => (ADC_DATA[0] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[10] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[11] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[12] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[13] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[14] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[15] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[1] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[2] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[3] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[4] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[5] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[6] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[7] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[8] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ADC_DATA[9] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[0] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[10] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[11] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[12] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[13] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[15] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[1] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[2] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[3] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[4] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[5] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[6] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[7] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[8] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (ALM[9] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[0] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[1] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[2] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[3] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[4] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (CHANNEL[5] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (EOC +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (EOS +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (MUXADDR[0] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (MUXADDR[1] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (MUXADDR[2] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (MUXADDR[3] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (MUXADDR[4] +: 0)) = (100:100:100, 100:100:100);
(posedge RESET => (OT +: 0)) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
$period (negedge CONVST, 0:0:0, notifier);
$period (negedge CONVSTCLK, 0:0:0, notifier);
$period (negedge DCLK, 0:0:0, notifier);
$period (posedge CONVST, 0:0:0, notifier);
$period (posedge CONVSTCLK, 0:0:0, notifier);
$period (posedge DCLK, 0:0:0, notifier);
$setuphold (negedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]);
$setuphold (negedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]);
$setuphold (negedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]);
$setuphold (negedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]);
$setuphold (negedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]);
$setuphold (negedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]);
$setuphold (negedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]);
$setuphold (negedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]);
$setuphold (negedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay);
$setuphold (negedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]);
$setuphold (negedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]);
$setuphold (negedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]);
$setuphold (negedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]);
$setuphold (negedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]);
$setuphold (negedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]);
$setuphold (negedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]);
$setuphold (negedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]);
$setuphold (negedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[2]);
$setuphold (negedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay,DI_delay[3]);
$setuphold (negedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]);
$setuphold (negedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]);
$setuphold (negedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]);
$setuphold (negedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]);
$setuphold (negedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]);
$setuphold (negedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]);
$setuphold (negedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay);
$setuphold (negedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[0]);
$setuphold (negedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[1]);
$setuphold (negedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[2]);
$setuphold (negedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[3]);
$setuphold (negedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[4]);
$setuphold (negedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[5]);
$setuphold (negedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[6]);
$setuphold (negedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DADDR_delay[7]);
$setuphold (negedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DEN_delay);
$setuphold (negedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[0]);
$setuphold (negedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[10]);
$setuphold (negedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[11]);
$setuphold (negedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[12]);
$setuphold (negedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[13]);
$setuphold (negedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[14]);
$setuphold (negedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[15]);
$setuphold (negedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[1]);
$setuphold (negedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[2]);
$setuphold (negedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[3]);
$setuphold (negedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[4]);
$setuphold (negedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[5]);
$setuphold (negedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[6]);
$setuphold (negedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[7]);
$setuphold (negedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[8]);
$setuphold (negedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DI_delay[9]);
$setuphold (negedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_n, rst_en_n, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, negedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, negedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, negedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, negedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, negedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, negedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, negedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, negedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, negedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, negedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, negedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, negedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, negedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, negedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, negedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, negedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, negedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, negedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, negedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, negedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, negedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, negedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, negedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, negedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, negedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, negedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay);
$setuphold (posedge DCLK, posedge DADDR[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[0]);
$setuphold (posedge DCLK, posedge DADDR[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[1]);
$setuphold (posedge DCLK, posedge DADDR[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[2]);
$setuphold (posedge DCLK, posedge DADDR[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[3]);
$setuphold (posedge DCLK, posedge DADDR[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[4]);
$setuphold (posedge DCLK, posedge DADDR[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[5]);
$setuphold (posedge DCLK, posedge DADDR[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[6]);
$setuphold (posedge DCLK, posedge DADDR[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DADDR_delay[7]);
$setuphold (posedge DCLK, posedge DEN, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DEN_delay);
$setuphold (posedge DCLK, posedge DI[0], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[0]);
$setuphold (posedge DCLK, posedge DI[10], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[10]);
$setuphold (posedge DCLK, posedge DI[11], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[11]);
$setuphold (posedge DCLK, posedge DI[12], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[12]);
$setuphold (posedge DCLK, posedge DI[13], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[13]);
$setuphold (posedge DCLK, posedge DI[14], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[14]);
$setuphold (posedge DCLK, posedge DI[15], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[15]);
$setuphold (posedge DCLK, posedge DI[1], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[1]);
$setuphold (posedge DCLK, posedge DI[2], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[2]);
$setuphold (posedge DCLK, posedge DI[3], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[3]);
$setuphold (posedge DCLK, posedge DI[4], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[4]);
$setuphold (posedge DCLK, posedge DI[5], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[5]);
$setuphold (posedge DCLK, posedge DI[6], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[6]);
$setuphold (posedge DCLK, posedge DI[7], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[7]);
$setuphold (posedge DCLK, posedge DI[8], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[8]);
$setuphold (posedge DCLK, posedge DI[9], 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DI_delay[9]);
$setuphold (posedge DCLK, posedge DWE, 0:0:0, 0:0:0, notifier_do, rst_en_p, rst_en_p, DCLK_delay, DWE_delay);
$width (negedge CONVST, 0:0:0, 0, notifier);
$width (negedge CONVSTCLK, 0:0:0, 0, notifier);
$width (negedge DCLK, 0:0:0, 0, notifier);
$width (posedge CONVST, 0:0:0, 0, notifier);
$width (posedge CONVSTCLK, 0:0:0, 0, notifier);
$width (posedge DCLK, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__TAPVPWRVGND_SYMBOL_V
`define SKY130_FD_SC_HDLL__TAPVPWRVGND_SYMBOL_V
/**
* tapvpwrvgnd: Substrate and well tap cell.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__tapvpwrvgnd ();
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__TAPVPWRVGND_SYMBOL_V
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_avm_to_ic #(
parameter integer DATA_W = 256,
parameter integer WRITEDATA_W = 256,
parameter integer BURSTCOUNT_W = 6,
parameter integer ADDRESS_W = 32,
parameter integer BYTEENA_W = DATA_W / 8,
parameter integer ID_W = 1,
parameter ADDR_SHIFT=1 // shift the address?
)
(
// AVM interface
input logic avm_read,
input logic avm_write,
input logic [WRITEDATA_W-1:0] avm_writedata,
input logic [BURSTCOUNT_W-1:0] avm_burstcount,
input logic [ADDRESS_W-1:0] avm_address,
input logic [BYTEENA_W-1:0] avm_byteenable,
output logic avm_waitrequest,
output logic avm_readdatavalid,
output logic [WRITEDATA_W-1:0] avm_readdata,
output logic avm_writeack, // not a true Avalon signal
// IC interface
output logic ic_arb_request,
output logic ic_arb_read,
output logic ic_arb_write,
output logic [WRITEDATA_W-1:0] ic_arb_writedata,
output logic [BURSTCOUNT_W-1:0] ic_arb_burstcount,
output logic [ADDRESS_W-$clog2(DATA_W / 8)-1:0] ic_arb_address,
output logic [BYTEENA_W-1:0] ic_arb_byteenable,
output logic [ID_W-1:0] ic_arb_id,
input logic ic_arb_stall,
input logic ic_wrp_ack,
input logic ic_rrp_datavalid,
input logic [WRITEDATA_W-1:0] ic_rrp_data
);
// The logic for ic_arb_request (below) makes a MAJOR ASSUMPTION:
// avm_write will never be deasserted in the MIDDLE of a write burst
// (read bursts are fine since they are single cycle requests)
//
// For proper burst functionality, ic_arb_request must remain asserted
// for the ENTIRE duration of a burst request, otherwise the burst may be
// interrupted and lead to all sorts of chaos. At this time, LSUs do not
// deassert avm_write in the middle of a write burst, so this assumption
// is valid.
//
// If there comes a time when this assumption is no longer valid,
// logic needs to be added to detect when a burst begins/ends.
assign ic_arb_request = avm_read | avm_write;
assign ic_arb_read = avm_read;
assign ic_arb_write = avm_write;
assign ic_arb_writedata = avm_writedata;
assign ic_arb_burstcount = avm_burstcount;
generate
if(ADDR_SHIFT==1)
begin
assign ic_arb_address = avm_address[ADDRESS_W-1:$clog2(DATA_W / 8)];
end
else
begin
assign ic_arb_address = avm_address[ADDRESS_W-$clog2(DATA_W / 8)-1:0];
end
endgenerate
assign ic_arb_byteenable = avm_byteenable;
assign avm_waitrequest = ic_arb_stall;
assign avm_readdatavalid = ic_rrp_datavalid;
assign avm_readdata = ic_rrp_data;
assign avm_writeack = ic_wrp_ack;
endmodule
|
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Lane Brooks
module t (clk);
input clk;
reg [31:0] state; initial state=0;
wire A = state[0];
wire OE = state[1];
wire Z1, Z2, Z3, Z4, Z5, Z6, Z7, Z8, Z9;
wire [3:0] Z10;
wire Z11;
Test1 test1(/*AUTOINST*/
// Inouts
.Z1 (Z1),
// Inputs
.OE (OE),
.A (A));
Test2 test2(/*AUTOINST*/
// Inouts
.Z2 (Z2),
// Inputs
.OE (OE),
.A (A));
Test3 test3(/*AUTOINST*/
// Inouts
.Z3 (Z3),
// Inputs
.OE (OE),
.A (A));
Test4 test4(/*AUTOINST*/
// Outputs
.Z4 (Z4),
// Inouts
.Z5 (Z5));
Test5 test5(/*AUTOINST*/
// Inouts
.Z6 (Z6),
.Z7 (Z7),
.Z8 (Z8),
.Z9 (Z9),
// Inputs
.OE (OE));
Test6 test6(/*AUTOINST*/
// Inouts
.Z10 (Z10[3:0]),
// Inputs
.OE (OE));
Test7 test7(/*AUTOINST*/
// Outputs
.Z11 (Z11),
// Inputs
.state (state[2:0]));
always @(posedge clk) begin
state <= state + 1;
`ifdef TEST_VERBOSE
$write("[%0t] state=%d Z1=%b 2=%b 3=%b 4=%b 5=%b 6=%b 7=%b 8=%b 9=%b 10=%b 11=%b\n",
$time, state, Z1,Z2,Z3,Z4,Z5,Z6,Z7,Z8,Z9,Z10,Z11);
`endif
if(state == 0) begin
if(Z1 !== 1'b1) $stop; // tests pullups
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b1) $stop;
if(Z7 !== 1'b0) $stop;
if(Z8 !== 1'b0) $stop;
if(Z9 !== 1'b1) $stop;
if(Z10 !== 4'b0001) $stop;
if(Z11 !== 1'b0) $stop;
end
else if(state == 1) begin
if(Z1 !== 1'b1) $stop; // tests pullup
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b1) $stop;
if(Z7 !== 1'b0) $stop;
if(Z8 !== 1'b0) $stop;
if(Z9 !== 1'b1) $stop;
if(Z10 !== 4'b0001) $stop;
if(Z11 !== 1'b1) $stop;
end
else if(state == 2) begin
if(Z1 !== 1'b0) $stop; // tests output driver low
if(Z2 !== 1'b0) $stop;
if(Z3 !== 1'b1 && Z3 !== 1'bx) $stop; // Conflicts
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b0) $stop;
if(Z7 !== 1'b1) $stop;
if(Z8 !== 1'b1) $stop;
if(Z9 !== 1'b0) $stop;
if(Z10 !== 4'b0010) $stop;
//if(Z11 !== 1'bx) $stop; // Doesn't matter
end
else if(state == 3) begin
if(Z1 !== 1'b1) $stop; // tests output driver high
if(Z2 !== 1'b1) $stop;
if(Z3 !== 1'b1) $stop;
`ifndef VERILATOR
if(Z4 !== 1'b1) $stop;
`endif
if(Z5 !== 1'b1) $stop;
if(Z6 !== 1'b0) $stop;
if(Z7 !== 1'b1) $stop;
if(Z8 !== 1'b1) $stop;
if(Z9 !== 1'b0) $stop;
if(Z10 !== 4'b0010) $stop;
if(Z11 !== 1'b1) $stop;
end
else if(state == 4) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
pullup(Z1);
pullup(Z2);
pullup(Z3);
pullup(Z4);
pullup(Z5);
pullup(Z6);
pulldown(Z7);
pullup(Z8);
pulldown(Z9);
pulldown pd10[3:0] (Z10);
endmodule
module Test1(input OE, input A, inout Z1);
assign Z1 = (OE) ? A : 1'bz;
endmodule
module Test2(input OE, input A, inout Z2);
assign Z2 = (OE) ? A : 1'bz;
endmodule
// mixed low-Z and tristate
module Test3(input OE, input A, inout Z3);
assign Z3 = (OE) ? A : 1'bz;
assign Z3 = 1'b1;
endmodule
// floating output and inout
`ifndef VERILATOR
// Note verilator doesn't know to make Z4 a tristate unless marked an inout
`endif
module Test4(output Z4, inout Z5);
endmodule
// AND gate tristates
module Test5(input OE, inout Z6, inout Z7, inout Z8, inout Z9);
assign Z6 = (OE) ? 1'b0 : 1'bz;
assign Z7 = (OE) ? 1'b1 : 1'bz;
assign Z8 = (OE) ? 1'bz : 1'b0;
assign Z9 = (OE) ? 1'bz : 1'b1;
endmodule
// AND gate tristates
module Test6(input OE, inout [3:0] Z10);
wire [1:0] i;
Test6a a (.OE(OE), .Z({Z10[0],Z10[1]}));
Test6a b (.OE(~OE), .Z({Z10[2],Z10[0]}));
endmodule
module Test6a(input OE, inout [1:0] Z);
assign Z = (OE) ? 2'b01 : 2'bzz;
endmodule
module Test7(input [2:0] state, output reg Z11);
always @(*) begin
casez (state)
3'b000: Z11 = 1'b0;
3'b0?1: Z11 = 1'b1;
default: Z11 = 1'bx;
endcase
end
endmodule
// This is not implemented yet
//module Test3(input OE, input A, inout Z3);
// always @(*) begin
// if(OE) begin
// Z3 = A;
// end else begin
// Z3 = 1'bz;
// end
// end
//endmodule
|
//*****************************************************************************
// (c) Copyright 2008-2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: read_posted_fifo.v
// /___/ /\ Date Last Modified:
// \ \ / \ Date Created:
// \___\/\___\
//
//Device: Spartan6
//Design Name: DDR/DDR2/DDR3/LPDDR
//Purpose: This module instantiated by read_data_path module and sits between
// mcb_flow_control module and read_data_gen module to buffer up the
// commands that has sent to memory controller.
//Reference:
//Revision History:
// 2010/01/09/ Corrected dfifo_has_enough_room threshold logic.
// It has to set higher in Read Only port.
//*****************************************************************************
`timescale 1ps/1ps
module read_posted_fifo #
(
parameter TCQ = 100,
parameter FAMILY = "SPARTAN6",
parameter MEM_BURST_LEN = 4,
parameter ADDR_WIDTH = 32,
parameter BL_WIDTH = 6
)
(
input clk_i,
input rst_i,
output reg cmd_rdy_o,
input cmd_valid_i,
input data_valid_i,
input [ADDR_WIDTH-1:0] addr_i,
input [BL_WIDTH-1:0] bl_i,
input user_bl_cnt_is_1,
input [2:0] cmd_sent,
input [5:0] bl_sent ,
input cmd_en_i ,
input gen_rdy_i,
output gen_valid_o,
output [ADDR_WIDTH-1:0] gen_addr_o,
output [BL_WIDTH-1:0] gen_bl_o,
output [6:0] rd_buff_avail_o,
input rd_mdata_fifo_empty,
output rd_mdata_en
);
reg empty_r;
reg rd_first_data;
wire full;
wire empty;
wire wr_en;
reg rd_en;
reg data_valid_r;
reg user_bl_cnt_not_1;
reg [6:0] buf_avail_r;
reg [6:0] rd_data_received_counts;
reg [6:0] rd_data_counts_asked;
reg dfifo_has_enough_room;
reg [1:0] wait_cnt;
reg wait_done;
assign rd_mdata_en = rd_en;
assign rd_buff_avail_o = buf_avail_r;
always @ (posedge clk_i)
cmd_rdy_o <= #TCQ !full & dfifo_has_enough_room & wait_done;
always @ (posedge clk_i)
begin
if (rst_i)
wait_cnt <= #TCQ 'b0;
else if (cmd_rdy_o && cmd_valid_i)
wait_cnt <= #TCQ 2'b10;
else if (wait_cnt > 0)
wait_cnt <= #TCQ wait_cnt - 1;
end
always @(posedge clk_i)
begin
if (rst_i)
wait_done <= #TCQ 1'b1;
else if (cmd_rdy_o && cmd_valid_i)
wait_done <= #TCQ 1'b0;
else if (wait_cnt == 0)
wait_done <= #TCQ 1'b1;
else
wait_done <= #TCQ 1'b0;
end
reg dfifo_has_enough_room_d1;
always @ (posedge clk_i)
begin // prbs_blen from cmd_gen is random, it can be two 64 in consecutive
// the logic here to prevent cmd_gen send any further read command if
// any large bl command has been sent.
dfifo_has_enough_room <= #TCQ (buf_avail_r >= 62 ) ? 1'b1: 1'b0;
dfifo_has_enough_room_d1 <= #TCQ dfifo_has_enough_room ;
end
assign wr_en = cmd_valid_i & !full & dfifo_has_enough_room_d1 & wait_done;
always @ (posedge clk_i)
data_valid_r <= #TCQ data_valid_i;
always @ (posedge clk_i)
begin
if (data_valid_i && user_bl_cnt_is_1) // current count is 1 and data_is_valie, then next cycle is not 1
user_bl_cnt_not_1 <= #TCQ 1'b1;
else
user_bl_cnt_not_1 <= #TCQ 1'b0;
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_counts_asked <= #TCQ 'b0;
end
else if (cmd_en_i && cmd_sent[0] == 1) begin
rd_data_counts_asked <= #TCQ rd_data_counts_asked + (bl_sent + 7'b0000001) ;
end
end
always @ (posedge clk_i)
begin
if (rst_i) begin
rd_data_received_counts <= #TCQ 'b0;
end
else if (data_valid_i) begin
rd_data_received_counts <= #TCQ rd_data_received_counts + 1;
end
end
// calculate how many buf still available
always @ (posedge clk_i)
// MCB FIFO size is 64.
// buf_available is calculated by:
// FIFO DEPTH - ( Write Poitner - Read Pointer)
buf_avail_r <= #TCQ 64 - (rd_data_counts_asked - rd_data_received_counts);
always @(gen_rdy_i, empty,empty_r,rd_mdata_fifo_empty,rd_first_data ,data_valid_i,data_valid_r,user_bl_cnt_not_1)
begin
if (FAMILY == "SPARTAN6")
rd_en = gen_rdy_i & !empty;
else
if ( MEM_BURST_LEN == 4)
rd_en = (~empty & empty_r & ~rd_first_data) | (~rd_mdata_fifo_empty & ~empty ) | (user_bl_cnt_not_1 & data_valid_i);
else
rd_en = (data_valid_i & ~data_valid_r) | (user_bl_cnt_not_1 & data_valid_i);
end
always @ (posedge clk_i)
empty_r <= #TCQ empty;
always @ (posedge clk_i)
begin
if (rst_i)
rd_first_data <= #TCQ 1'b0;
else if (~empty && empty_r)
rd_first_data <= #TCQ 1'b1;
end
assign gen_valid_o = !empty;
afifo #
(
.TCQ (TCQ),
.DSIZE (BL_WIDTH+ADDR_WIDTH),
.FIFO_DEPTH (16),
.ASIZE (4),
.SYNC (1) // set the SYNC to 1 because rd_clk = wr_clk to reduce latency
)
rd_fifo
(
.wr_clk (clk_i),
.rst (rst_i),
.wr_en (wr_en),
.wr_data ({bl_i,addr_i}),
.rd_en (rd_en),
.rd_clk (clk_i),
.rd_data ({gen_bl_o,gen_addr_o}),
.full (full),
.empty (empty),
.almost_full ()
);
endmodule
|
//-----------------------------------------------------------------------------
//-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
//-- special, incidental, or consequential loss or damage
//-- (including loss of data, profits, goodwill, or any type of
//-- loss or damage suffered as a result of any action brought
//-- by a third party) even if such damage or loss was
//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
//-- CRITICAL APPLICATIONS
//-- Xilinx products are not designed or intended to be fail-
//-- safe, or for use in any application requiring fail-safe
//-- performance, such as life-support or safety devices or
//-- systems, Class III medical devices, nuclear facilities,
//-- applications related to the deployment of airbags, or any
//-- other applications that could lead to death, personal
//-- injury, or severe property or environmental damage
//-- (individually and collectively, "Critical
//-- Applications"). Customer assumes the sole risk and
//-- liability of any use of Xilinx products in Critical
//-- Applications, subject only to applicable laws and
//-- regulations governing limitations on product liability.
//--
//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//Purpose:
// Synchronous, shallow FIFO that uses simple as a DP Memory.
// This requires about 1/2 the resources as a Distributed RAM DPRAM
// implementation.
//
// This FIFO will have the current data on the output when data is contained
// in the FIFO. When the FIFO is empty, the output data is invalid.
//
//Reference:
//Revision History:
//
//-----------------------------------------------
//
// MODULE: axi_mc_fifo
//
// This is the simplest form of inferring the
// simple/SRL(16/32)CE in a Xilinx FPGA.
//
//-----------------------------------------------
`timescale 1ns / 100ps
`default_nettype none
module mig_7series_v4_0_axi_mc_fifo #
(
parameter C_WIDTH = 8,
parameter C_AWIDTH = 4,
parameter C_DEPTH = 16
)
(
input wire clk, // Main System Clock (Sync FIFO)
input wire rst, // FIFO Counter Reset (Clk
input wire wr_en, // FIFO Write Enable (Clk)
input wire rd_en, // FIFO Read Enable (Clk)
input wire [C_WIDTH-1:0] din, // FIFO Data Input (Clk)
output wire [C_WIDTH-1:0] dout, // FIFO Data Output (Clk)
output wire a_full,
output wire full, // FIFO FULL Status (Clk)
output wire a_empty,
output wire empty // FIFO EMPTY Status (Clk)
);
///////////////////////////////////////
// FIFO Local Parameters
///////////////////////////////////////
localparam [C_AWIDTH:0] C_EMPTY = ~(0);
localparam [C_AWIDTH-1:0] C_EMPTY_PRE = 0;
localparam [C_AWIDTH-1:0] C_FULL = C_DEPTH - 1;
localparam [C_AWIDTH-1:0] C_FULL_PRE = C_DEPTH -2;
///////////////////////////////////////
// FIFO Internal Signals
///////////////////////////////////////
reg [C_WIDTH-1:0] memory [C_DEPTH-1:0];
reg [C_AWIDTH:0] cnt_read;
reg [C_AWIDTH:0] next_cnt_read;
wire [C_AWIDTH:0] cnt_read_plus1;
wire [C_AWIDTH:0] cnt_read_minus1;
wire [C_AWIDTH-1:0] read_addr;
///////////////////////////////////////
// Main FIFO Array
///////////////////////////////////////
assign read_addr = cnt_read;
assign dout = memory[read_addr];
always @(posedge clk) begin : BLKSRL
integer i;
if (wr_en) begin
for (i = 0; i < C_DEPTH-1; i = i + 1) begin
memory[i+1] <= memory[i];
end
memory[0] <= din;
end
end
///////////////////////////////////////
// Read Index Counter
// Up/Down Counter
// *** Notice that there is no ***
// *** OVERRUN protection. ***
///////////////////////////////////////
always @(posedge clk) begin
if (rst) cnt_read <= C_EMPTY;
else cnt_read <= next_cnt_read;
end
assign cnt_read_plus1 = cnt_read + 1'b1;
assign cnt_read_minus1 = cnt_read - 1'b1;
always @(*) begin
next_cnt_read = cnt_read;
if ( wr_en & !rd_en) next_cnt_read = cnt_read_plus1;
else if (!wr_en & rd_en) next_cnt_read = cnt_read_minus1;
end
///////////////////////////////////////
// Status Flags / Outputs
// These could be registered, but would
// increase logic in order to pre-decode
// FULL/EMPTY status.
///////////////////////////////////////
assign full = (cnt_read == C_FULL);
assign empty = (cnt_read == C_EMPTY);
assign a_full = (cnt_read == C_FULL_PRE);
assign a_empty = (cnt_read == C_EMPTY_PRE);
endmodule // axi_mc_fifo
`default_nettype wire
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_bram_block_dp #(
parameter DATA = 32,
parameter ADDR = 7
) (
input wire a_clk,
input wire a_wr,
input wire [ADDR-1:0] a_addr,
input wire [DATA-1:0] a_din,
output reg [DATA-1:0] a_dout,
input wire b_clk,
input wire b_wr,
input wire [ADDR-1:0] b_addr,
input wire [DATA-1:0] b_din,
output reg [DATA-1:0] b_dout
);
reg [DATA-1:0] mem [(2**ADDR)-1:0];
always @(posedge a_clk) begin
if(a_wr) begin
a_dout <= a_din;
mem[a_addr] <= a_din;
end else
a_dout <= mem[a_addr];
end
always @(posedge b_clk) begin
if(b_wr) begin
b_dout <= b_din;
mem[b_addr] <= b_din;
end else
b_dout <= mem[b_addr];
end
endmodule
|
module reg_64page_1024x32b_3r_1w_fpga
(/*AUTOARG*/
// Outputs
rd0_data, rd1_data, rd2_data,
// Inputs
rd0_addr, rd1_addr, rd2_addr, wr0_addr, wr0_en, wr0_en_xoutof4,
wr0_data, clk, clk_double
);
output [8191:0] rd0_data;
output [2047:0] rd1_data;
output [2047:0] rd2_data;
input [9:0] rd0_addr;
input [9:0] rd1_addr;
input [9:0] rd2_addr;
input [9:0] wr0_addr;
input [63:0] wr0_en;
input [3:0] wr0_en_xoutof4;
input [8191:0] wr0_data;
input clk;
input clk_double;
//wire [255:0] effective_wr0_en;
reg [63:0] block_we;
reg [31:0] block_addr_a;
reg [31:0] block_addr_b;
wire [31:0] block_addr_c;
assign block_addr_c = {rd2_addr, 2'd0};
always @ (*) begin
if(clk) begin
block_we <= 64'd0;
block_addr_a <= {rd0_addr, 2'd0};
block_addr_b <= {rd1_addr, 2'd0};
end
else begin
block_we <= wr0_en;
block_addr_a <= {wr0_addr, 2'd0};
end
end
genvar index;
generate
for(index = 0; index < 64; index = index + 1) begin : block_ram_banks
block_ram bank0
(
.clka(clk_double), // input clka
//.rsta(rst), // input rsta
.wea({4{block_we[index]}}), // input [3 : 0] wea
.addra(block_addr_a), // input [31 : 0] addra
.dina(wr0_data[(31 + (index * 128)):(index * 128)]), // input [31 : 0] dina
.douta(rd0_data[31 + (index * 128):index * 128]), // output [31 : 0] douta
.clkb(clk_double), // input clkb
//.rstb(rst), // input rstb
.web(4'd0), // input [3 : 0] web
.addrb(block_addr_b), // input [31 : 0] addrb
.dinb(32'd0), // input [31 : 0] dinb
.doutb(rd1_data[31 + (index * 32):index * 32]) // output [31 : 0] doutb
);
block_ram bank1
(
.clka(clk_double), // input clka
//.rsta(rst), // input rsta
.wea(4'd0), // input [3 : 0] wea
.addra(block_addr_c), // input [31 : 0] addra
.dina(32'd0), // input [31 : 0] dina
.douta(rd2_data[31 + (index * 32):index * 32]), // output [31 : 0] douta
.clkb(clk_double), // input clkb
//.rstb(rst), // input rstb
.web({4{block_we[index]}}), // input [3 : 0] web
.addrb(block_addr_a), // input [31 : 0] addrb
.dinb(wr0_data[(31 + (index * 128)):(index * 128)]), // input [31 : 0] dinb
.doutb() // output [31 : 0] doutb
);
end
endgenerate
endmodule
|
// (C) 1992-2012 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// Low latency FIFO
// One cycle latency from all inputs to all outputs
// Storage implemented in registers, not memory.
module acl_iface_ll_fifo(clk, reset, data_in, write, data_out, read, empty, full);
/* Parameters */
parameter WIDTH = 32;
parameter DEPTH = 32;
/* Ports */
input clk;
input reset;
input [WIDTH-1:0] data_in;
input write;
output [WIDTH-1:0] data_out;
input read;
output empty;
output full;
/* Architecture */
// One-hot write-pointer bit (indicates next position to write at),
// last bit indicates the FIFO is full
reg [DEPTH:0] wptr;
// Replicated copy of the stall / valid logic
reg [DEPTH:0] wptr_copy /* synthesis dont_merge */;
// FIFO data registers
reg [DEPTH-1:0][WIDTH-1:0] data;
// Write pointer updates:
wire wptr_hold; // Hold the value
wire wptr_dir; // Direction to shift
// Data register updates:
wire [DEPTH-1:0] data_hold; // Hold the value
wire [DEPTH-1:0] data_new; // Write the new data value in
// Write location is constant unless the occupancy changes
assign wptr_hold = !(read ^ write);
assign wptr_dir = read;
// Hold the value unless we are reading, or writing to this
// location
genvar i;
generate
for(i = 0; i < DEPTH; i++)
begin : data_mux
assign data_hold[i] = !(read | (write & wptr[i]));
assign data_new[i] = !read | wptr[i+1];
end
endgenerate
// The data registers
generate
for(i = 0; i < DEPTH-1; i++)
begin : data_reg
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[i] <= {WIDTH{1'b0}};
else
data[i] <= data_hold[i] ? data[i] :
data_new[i] ? data_in : data[i+1];
end
end
endgenerate
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
data[DEPTH-1] <= {WIDTH{1'b0}};
else
data[DEPTH-1] <= data_hold[DEPTH-1] ? data[DEPTH-1] : data_in;
end
// The write pointer
always@(posedge clk or posedge reset)
begin
if(reset == 1'b1)
begin
wptr <= {{DEPTH{1'b0}}, 1'b1};
wptr_copy <= {{DEPTH{1'b0}}, 1'b1};
end
else
begin
wptr <= wptr_hold ? wptr :
wptr_dir ? {1'b0, wptr[DEPTH:1]} : {wptr[DEPTH-1:0], 1'b0};
wptr_copy <= wptr_hold ? wptr_copy :
wptr_dir ? {1'b0, wptr_copy[DEPTH:1]} : {wptr_copy[DEPTH-1:0], 1'b0};
end
end
// Outputs
assign empty = wptr_copy[0];
assign full = wptr_copy[DEPTH];
assign data_out = data[0];
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V
`define SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V
/**
* nor4: 4-input NOR.
*
* Y = !(A | B | C | D)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__nor4 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
// Local signals
wire nor0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out_Y , A, B, C, D );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, nor0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__NOR4_BEHAVIORAL_V |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Internal DMA Control and status register file for PCIE-DDR2 DMA
// design. This register file should only be used for dma transfers
// up to 4KB in size.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module internal_dma_ctrl
(
input clk,
input rst,
//interface from dma_ctrl_status_reg file;
//these inputs could also be directly driven from the host system if desired
//in which case the dma_ctrl_status_reg_file block should be removed from the
//design
input [31:0] reg_data_in,
input [6:0] reg_wr_addr,
input [6:0] reg_rd_addr,
input reg_wren,
output reg [31:0] reg_data_out, //reg_data_out is never used
//DMA parameter control outputs to TX and RX engines
output [63:0] dmaras, //Read address source (from host memory)
output reg [31:0] dmarad, //Read address destination (to backend memory)
output reg [31:0] dmarxs, //Read transfer size in bytes
output rd_dma_start, //read dma start control signal
input rd_dma_done, //read dma done signal from RX engine
//Performance counts from performance counter module
//Not used in this module because the copies in dma_ctrl_status_reg_file
//are used instead
input [31:0] dma_wr_count,
input [31:0] dma_rd_count
);
reg [31:0] dmaras_l, dmaras_u;
reg [31:0] dmacst;
//concatanate to form the 64 bit outputs
assign dmaras[63:0] = {dmaras_u,dmaras_l};
////assign wr_dma_start = dmacst[0];
assign rd_dma_start = dmacst[2];
//block for writing into the regfile
//--when reg_wren is asserted, reg_data_in will be written to one of the
//registers as chosen by reg_wr_addr selection signal
always@(posedge clk or posedge rst) begin
if(rst) begin
dmaras_l <= 0;
dmaras_u <= 0;
dmarad <= 0;
dmarxs <= 0;
end else begin
if(reg_wren) begin
case(reg_wr_addr)
7'b000_1100: dmaras_l <= reg_data_in; //0x0C
7'b001_0000: dmaras_u <= reg_data_in; //0x10
7'b001_0100: dmarad <= reg_data_in; //0x14
7'b001_1100: dmarxs <= reg_data_in; //0x1C
default: begin
dmaras_l <= dmaras_l;
dmaras_u <= dmaras_u;
dmarad <= dmarad;
dmarxs <= dmarxs;
end
endcase
end
end
end
//use a separate always block for dmacst[3:2] for clarity
//dmacst[2] == rd_dma_start; host sets this bit to start a dma transfer
// it is automatically cleared when the
// dma transfer completes
//dmacst[3] == rd_dma_done; asserted when the dma transfer is finished
// this bit can be polled by the host or it could
// be used to drive hardware block to generate
// an interrupt
// this bit must be cleared by the host by
// writing a "1" to it.
always@(posedge clk) begin
if(rst) begin
dmacst[3:2] <= 2'b00;
end else begin
if(rd_dma_done) begin //rd_dma_done from RX Engine
dmacst[2] <= 1'b0;
dmacst[3] <= 1'b1;
end else if(reg_wren) begin
case(reg_wr_addr)
7'b010_1000: begin //0x28
/// Jiansong:
//take care of the unused bits in this always
//block
dmacst[31:4] <= reg_data_in[31:4];
dmacst[1:0] <= reg_data_in[1:0];
//set the start bit if the host writes a 1
//the host cannot clear this bit
if(reg_data_in[2])
dmacst[2] <= 1'b1;
else
dmacst[2] <= dmacst[2];
//clear the done bit if the host writes a 1
//the host cannot set this bit
if(reg_data_in[3])
dmacst[3] <= 1'b0;
else
dmacst[3] <= dmacst[3];
end
default: begin
dmacst[3:2] <= dmacst[3:2];
end
endcase
end
end
end
// output register for cpu
// this is a read of the reg_file
// the case stmt is a mux which selects which reg location
// makes it to the output data bus
// Not used in this design
always@(posedge clk or posedge rst )
begin
if(rst)
begin
reg_data_out <= 0;
end
else
begin
case(reg_rd_addr[6:0])
7'b000_1100: reg_data_out <= dmaras_l;
7'b001_0000: reg_data_out <= dmaras_u;
7'b001_0100: reg_data_out <= dmarad;
7'b001_1100: reg_data_out <= dmarxs;
7'b010_1000: reg_data_out <= dmacst;
7'b011_0000: reg_data_out <= dma_wr_count;
7'b011_0100: reg_data_out <= dma_rd_count;
endcase
end
end
endmodule
|
(** * Stlc: The Simply Typed Lambda-Calculus *)
Require Export Types.
(* ###################################################################### *)
(** * The Simply Typed Lambda-Calculus *)
(** The simply typed lambda-calculus (STLC) is a tiny core calculus
embodying the key concept of _functional abstraction_, which shows
up in pretty much every real-world programming language in some
form (functions, procedures, methods, etc.).
We will follow exactly the same pattern as in the previous
chapter when formalizing this calculus (syntax, small-step
semantics, typing rules) and its main properties (progress and
preservation). The new technical challenges (which will take some
work to deal with) all arise from the mechanisms of _variable
binding_ and _substitution_. *)
(* ###################################################################### *)
(** ** Overview *)
(** The STLC is built on some collection of _base types_ -- booleans,
numbers, strings, etc. The exact choice of base types doesn't
matter -- the construction of the language and its theoretical
properties work out pretty much the same -- so for the sake of
brevity let's take just [Bool] for the moment. At the end of the
chapter we'll see how to add more base types, and in later
chapters we'll enrich the pure STLC with other useful constructs
like pairs, records, subtyping, and mutable state.
Starting from the booleans, we add three things:
- variables
- function abstractions
- application
This gives us the following collection of abstract syntax
constructors (written out here in informal BNF notation -- we'll
formalize it below).
*)
(** Informal concrete syntax:
t ::= x variable
| λx:T1.t2 abstraction
| t1 t2 application
| true constant true
| false constant false
| if t1 then t2 else t3 conditional
*)
(** The [λ] symbol (backslash, in ascii) in a function abstraction
[λx:T1.t2] is generally written as a greek letter "lambda" (hence
the name of the calculus). The variable [x] is called the
_parameter_ to the function; the term [t1] is its _body_. The
annotation [:T] specifies the type of arguments that the function
can be applied to. *)
(** Some examples:
- [λx:Bool. x]
The identity function for booleans.
- [(λx:Bool. x) true]
The identity function for booleans, applied to the boolean [true].
- [λx:Bool. if x then false else true]
The boolean "not" function.
- [λx:Bool. true]
The constant function that takes every (boolean) argument to
[true]. *)
(**
- [λx:Bool. λy:Bool. x]
A two-argument function that takes two booleans and returns
the first one. (Note that, as in Coq, a two-argument function
is really a one-argument function whose body is also a
one-argument function.)
- [(λx:Bool. λy:Bool. x) false true]
A two-argument function that takes two booleans and returns
the first one, applied to the booleans [false] and [true].
Note that, as in Coq, application associates to the left --
i.e., this expression is parsed as [((λx:Bool. λy:Bool. x)
false) true].
- [λf:Bool->Bool. f (f true)]
A higher-order function that takes a _function_ [f] (from
booleans to booleans) as an argument, applies [f] to [true],
and applies [f] again to the result.
- [(λf:Bool->Bool. f (f true)) (λx:Bool. false)]
The same higher-order function, applied to the constantly
[false] function. *)
(** As the last several examples show, the STLC is a language of
_higher-order_ functions: we can write down functions that take
other functions as arguments and/or return other functions as
results.
Another point to note is that the STLC doesn't provide any
primitive syntax for defining _named_ functions -- all functions
are "anonymous." We'll see in chapter [MoreStlc] that it is easy
to add named functions to what we've got -- indeed, the
fundamental naming and binding mechanisms are exactly the same.
The _types_ of the STLC include [Bool], which classifies the
boolean constants [true] and [false] as well as more complex
computations that yield booleans, plus _arrow types_ that classify
functions. *)
(**
T ::= Bool
| T1 -> T2
For example:
- [λx:Bool. false] has type [Bool->Bool]
- [λx:Bool. x] has type [Bool->Bool]
- [(λx:Bool. x) true] has type [Bool]
- [λx:Bool. λy:Bool. x] has type [Bool->Bool->Bool] (i.e. [Bool -> (Bool->Bool)])
- [(λx:Bool. λy:Bool. x) false] has type [Bool->Bool]
- [(λx:Bool. λy:Bool. x) false true] has type [Bool]
*)
(* ###################################################################### *)
(** ** Syntax *)
Module STLC.
(* ################################### *)
(** *** Types *)
Inductive ty : Type :=
| TBool : ty
| TArrow : ty -> ty -> ty.
(* ################################### *)
(** *** Terms *)
Inductive tm : Type :=
| tvar : id -> tm
| tapp : tm -> tm -> tm
| tabs : id -> ty -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "t_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "tvar" | Case_aux c "tapp"
| Case_aux c "tabs" | Case_aux c "ttrue"
| Case_aux c "tfalse" | Case_aux c "tif" ].
(** Note that an abstraction [λx:T.t] (formally, [tabs x T t]) is
always annotated with the type [T] of its parameter, in contrast
to Coq (and other functional languages like ML, Haskell, etc.),
which use _type inference_ to fill in missing annotations. We're
not considering type inference here, to keep things simple. *)
(** Some examples... *)
Definition x := (Id 0).
Definition y := (Id 1).
Definition z := (Id 2).
Hint Unfold x.
Hint Unfold y.
Hint Unfold z.
(** [idB = λx:Bool. x] *)
Notation idB :=
(tabs x TBool (tvar x)).
(** [idBB = λx:Bool->Bool. x] *)
Notation idBB :=
(tabs x (TArrow TBool TBool) (tvar x)).
(** [idBBBB = λx:(Bool->Bool) -> (Bool->Bool). x] *)
Notation idBBBB :=
(tabs x (TArrow (TArrow TBool TBool)
(TArrow TBool TBool))
(tvar x)).
(** [k = λx:Bool. λy:Bool. x] *)
Notation k := (tabs x TBool (tabs y TBool (tvar x))).
(** [notB = λx:Bool. if x then false else true] *)
Notation notB := (tabs x TBool (tif (tvar x) tfalse ttrue)).
(** (We write these as [Notation]s rather than [Definition]s to make
things easier for [auto].) *)
(* ###################################################################### *)
(** ** Operational Semantics *)
(** To define the small-step semantics of STLC terms, we begin -- as
always -- by defining the set of values. Next, we define the
critical notions of _free variables_ and _substitution_, which are
used in the reduction rule for application expressions. And
finally we give the small-step relation itself. *)
(* ################################### *)
(** *** Values *)
(** To define the values of the STLC, we have a few cases to consider.
First, for the boolean part of the language, the situation is
clear: [true] and [false] are the only values. An [if]
expression is never a value. *)
(** Second, an application is clearly not a value: It represents a
function being invoked on some argument, which clearly still has
work left to do. *)
(** Third, for abstractions, we have a choice:
- We can say that [λx:T.t1] is a value only when [t1] is a
value -- i.e., only if the function's body has been
reduced (as much as it can be without knowing what argument it
is going to be applied to).
- Or we can say that [λx:T.t1] is always a value, no matter
whether [t1] is one or not -- in other words, we can say that
reduction stops at abstractions.
Coq, in its built-in functional programming langauge, makes the
first choice -- for example,
Eval simpl in (fun x:bool => 3 + 4)
yields [fun x:bool => 7].
Most real-world functional programming languages make the second
choice -- reduction of a function's body only begins when the
function is actually applied to an argument. We also make the
second choice here. *)
Inductive value : tm -> Prop :=
| v_abs : forall x T t,
value (tabs x T t)
| v_true :
value ttrue
| v_false :
value tfalse.
Hint Constructors value.
(** Finally, we must consider what constitutes a _complete_ program.
Intuitively, a "complete" program must not refer to any undefined
variables. We'll see shortly how to define the "free" variables
in a STLC term. A program is "closed", that is, it contains no
free variables.
*)
(** Having made the choice not to reduce under abstractions,
we don't need to worry about whether variables are values, since
we'll always be reducing programs "from the outside in," and that
means the [step] relation will always be working with closed
terms (ones with no free variables). *)
(* ###################################################################### *)
(** *** Substitution *)
(** Now we come to the heart of the STLC: the operation of
substituting one term for a variable in another term.
This operation will be used below to define the operational
semantics of function application, where we will need to
substitute the argument term for the function parameter in the
function's body. For example, we reduce
(λx:Bool. if x then true else x) false
to
if false then true else false
]]
by substituting [false] for the parameter [x] in the body of the
function.
In general, we need to be able to substitute some given
term [s] for occurrences of some variable [x] in another term [t].
In informal discussions, this is usually written [ [x:=s]t ] and
pronounced "substitute [x] with [s] in [t]." *)
(** Here are some examples:
- [[x:=true] (if x then x else false)] yields [if true then true else false]
- [[x:=true] x] yields [true]
- [[x:=true] (if x then x else y)] yields [if true then true else y]
- [[x:=true] y] yields [y]
- [[x:=true] false] yields [false] (vacuous substitution)
- [[x:=true] (λy:Bool. if y then x else false)] yields [λy:Bool. if y then true else false]
- [[x:=true] (λy:Bool. x)] yields [λy:Bool. true]
- [[x:=true] (λy:Bool. y)] yields [λy:Bool. y]
- [[x:=true] (λx:Bool. x)] yields [λx:Bool. x]
The last example is very important: substituting [x] with [true] in
[λx:Bool. x] does _not_ yield [λx:Bool. true]! The reason for
this is that the [x] in the body of [λx:Bool. x] is _bound_ by the
abstraction: it is a new, local name that just happens to be
spelled the same as some global name [x]. *)
(** Here is the definition, informally...
[x:=s]x = s
[x:=s]y = y if x <> y
[x:=s](λx:T11.t12) = λx:T11. t12
[x:=s](λy:T11.t12) = λy:T11. [x:=s]t12 if x <> y
[x:=s](t1 t2) = ([x:=s]t1) ([x:=s]t2)
[x:=s]true = true
[x:=s]false = false
[x:=s](if t1 then t2 else t3) =
if [x:=s]t1 then [x:=s]t2 else [x:=s]t3
]]
*)
(** ... and formally: *)
Reserved Notation "'[' x ':=' s ']' t" (at level 20).
Fixpoint subst (x:id) (s:tm) (t:tm) : tm :=
match t with
| tvar x' =>
if eq_id_dec x x' then s else t
| tabs x' T t1 =>
tabs x' T (if eq_id_dec x x' then t1 else ([x:=s] t1))
| tapp t1 t2 =>
tapp ([x:=s] t1) ([x:=s] t2)
| ttrue =>
ttrue
| tfalse =>
tfalse
| tif t1 t2 t3 =>
tif ([x:=s] t1) ([x:=s] t2) ([x:=s] t3)
end
where "'[' x ':=' s ']' t" := (subst x s t).
(** _Technical note_: Substitution becomes trickier to define if we
consider the case where [s], the term being substituted for a
variable in some other term, may itself contain free variables.
Since we are only interested here in defining the [step] relation
on closed terms (i.e., terms like [λx:Bool. x], that do not mention
variables are not bound by some enclosing lambda), we can skip
this extra complexity here, but it must be dealt with when
formalizing richer languages. *)
(** *** *)
(** **** Exercise: 3 stars (substi) *)
(** The definition that we gave above uses Coq's [Fixpoint] facility
to define substitution as a _function_. Suppose, instead, we
wanted to define substitution as an inductive _relation_ [substi].
We've begun the definition by providing the [Inductive] header and
one of the constructors; your job is to fill in the rest of the
constructors. *)
Inductive substi (s:tm) (x:id) : tm -> tm -> Prop :=
| s_var1 : substi s x (tvar x) s
| s_var2 : forall y, y <> x -> substi s x (tvar y) (tvar y)
| s_abs1 : forall T tm, substi s x (tabs x T tm) (tabs x T tm)
| s_abs2 : forall y T tm tm', x <> y -> substi s x tm tm' ->
substi s x (tabs y T tm) (tabs y T tm')
| s_app : forall t1 t1' t2 t2',
substi s x t1 t1' -> substi s x t2 t2' ->
substi s x (tapp t1 t2) (tapp t1' t2')
| s_true : substi s x ttrue ttrue
| s_false : substi s x tfalse tfalse
| s_if : forall t1 t1' t2 t2' t3 t3',
substi s x t1 t1' -> substi s x t2 t2' -> substi s x t3 t3' ->
substi s x (tif t1 t2 t3) (tif t1' t2' t3')
.
Hint Constructors substi.
Theorem eq_ty_dec : forall (t1 t2 : ty), {t1 = t2} + {t1 <> t2}.
Proof. induction t1; destruct t2; [left; trivial | | |]; try (right; discriminate).
- destruct (IHt1_1 t2_1), (IHt1_2 t2_2); [ left | right | right | right ]; crush.
Qed.
Theorem eq_tm_dec : forall (t1 t2 : tm), {t1 = t2} + {t1 <> t2}.
Proof. induction t1; destruct t2; try (left; reflexivity); try (right; discriminate).
(* All that's left are cases with the same constructors *)
- Case "id"; destruct (eq_id_dec i i0); [left | right]; crush.
- Case "tapp";
destruct (IHt1_1 t2_1), (IHt1_2 t2_2); [left | right | right | right ]; crush.
- Case "tabs";
destruct (IHt1 t2), (eq_ty_dec t t0), (eq_id_dec i i0);
[ left | right | right | right | right | right | right | right ];
subst; eauto; injection 1; crush.
- Case "tif";
destruct (IHt1_1 t2_1), (IHt1_2 t2_2), (IHt1_3 t2_3);
[ left | right | right | right | right | right | right | right ];
subst; eauto; injection 1; crush.
Qed.
Theorem substi_correct : forall s x t t',
[x:=s]t = t' <-> substi s x t t'.
Proof. intros s x t t'; split.
- generalize dependent t'; induction t; crush; destruct (eq_id_dec x i); crush.
- induction 1; unfold subst; fold subst; try rewrite eq_id; try rewrite neq_id; crush.
Qed.
(** [] *)
(* ################################### *)
(** *** Reduction *)
(** The small-step reduction relation for STLC now follows the same
pattern as the ones we have seen before. Intuitively, to reduce a
function application, we first reduce its left-hand side until it
becomes a literal function; then we reduce its right-hand
side (the argument) until it is also a value; and finally we
substitute the argument for the bound variable in the body of the
function. This last rule, written informally as
(λx:T.t12) v2 ==> [x:=v2]t12
is traditionally called "beta-reduction". *)
(**
value v2
---------------------------- (ST_AppAbs)
(λx:T.t12) v2 ==> [x:=v2]t12
t1 ==> t1'
---------------- (ST_App1)
t1 t2 ==> t1' t2
value v1
t2 ==> t2'
---------------- (ST_App2)
v1 t2 ==> v1 t2'
*)
(** ... plus the usual rules for booleans:
-------------------------------- (ST_IfTrue)
(if true then t1 else t2) ==> t1
--------------------------------- (ST_IfFalse)
(if false then t1 else t2) ==> t2
t1 ==> t1'
---------------------------------------------------- (ST_If)
(if t1 then t2 else t3) ==> (if t1' then t2 else t3)
*)
Reserved Notation "t1 '==>' t2" (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_AppAbs : forall x T t12 v2,
value v2 ->
(tapp (tabs x T t12) v2) ==> [x:=v2]t12
| ST_App1 : forall t1 t1' t2,
t1 ==> t1' ->
tapp t1 t2 ==> tapp t1' t2
| ST_App2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
tapp v1 t2 ==> tapp v1 t2'
| ST_IfTrue : forall t1 t2,
(tif ttrue t1 t2) ==> t1
| ST_IfFalse : forall t1 t2,
(tif tfalse t1 t2) ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
(tif t1 t2 t3) ==> (tif t1' t2 t3)
where "t1 '==>' t2" := (step t1 t2).
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_AppAbs" | Case_aux c "ST_App1"
| Case_aux c "ST_App2" | Case_aux c "ST_IfTrue"
| Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
Hint Constructors step.
Notation multistep := (multi step).
Notation "t1 '==>*' t2" := (multistep t1 t2) (at level 40).
(* ##################################### *)
(** *** Examples *)
(** Example:
((λx:Bool->Bool. x) (λx:Bool. x)) ==>* (λx:Bool. x)
i.e.
(idBB idB) ==>* idB
*)
Lemma step_example1 :
(tapp idBB idB) ==>* idB.
Proof.
eapply multi_step.
apply ST_AppAbs.
apply v_abs.
simpl. apply multi_refl.
Qed.
(** Example:
((λx:Bool->Bool. x) ((λx:Bool->Bool. x) (λx:Bool. x)))
==>* (λx:Bool. x)
i.e.
(idBB (idBB idB)) ==>* idB.
*)
Lemma step_example2 :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto.
eapply multi_step.
apply ST_AppAbs. simpl. auto.
simpl. apply multi_refl. Qed.
(** Example:
((λx:Bool->Bool. x) (λx:Bool. if x then false
else true)) true)
==>* false
i.e.
((idBB notB) ttrue) ==>* tfalse.
*)
Lemma step_example3 :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App1. apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_IfTrue. apply multi_refl. Qed.
(** Example:
((λx:Bool->Bool. x) ((λx:Bool. if x then false
else true) true))
==>* false
i.e.
(idBB (notB ttrue)) ==>* tfalse.
*)
Lemma step_example4 :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof.
eapply multi_step.
apply ST_App2. auto.
apply ST_AppAbs. auto. simpl.
eapply multi_step.
apply ST_App2. auto.
apply ST_IfTrue.
eapply multi_step.
apply ST_AppAbs. auto. simpl.
apply multi_refl. Qed.
(** A more automatic proof *)
Lemma step_example1' :
(tapp idBB idB) ==>* idB.
Proof. normalize. Qed.
(** Again, we can use the [normalize] tactic from above to simplify
the proof. *)
Lemma step_example2' :
(tapp idBB (tapp idBB idB)) ==>* idB.
Proof.
normalize.
Qed.
Lemma step_example3' :
tapp (tapp idBB notB) ttrue ==>* tfalse.
Proof. normalize. Qed.
Lemma step_example4' :
tapp idBB (tapp notB ttrue) ==>* tfalse.
Proof. normalize. Qed.
(** **** Exercise: 2 stars (step_example3) *)
(** Try to do this one both with and without [normalize]. *)
Lemma step_example5 :
(tapp (tapp idBBBB idBB) idB)
==>* idB.
Proof. normalize. Qed.
Lemma step_exampple5' : (tapp (tapp idBBBB idBB) idB) ==>* idB.
Proof. repeat econstructor. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Typing *)
(* ################################### *)
(** *** Contexts *)
(** _Question_: What is the type of the term "[x y]"?
_Answer_: It depends on the types of [x] and [y]!
I.e., in order to assign a type to a term, we need to know
what assumptions we should make about the types of its free
variables.
This leads us to a three-place "typing judgment", informally
written [Gamma ⊢ t ∈ T], where [Gamma] is a
"typing context" -- a mapping from variables to their types. *)
(** We hide the definition of partial maps in a module since it is
actually defined in [SfLib]. *)
Module PartialMap.
Definition partial_map (A:Type) := id -> option A.
Definition empty {A:Type} : partial_map A := (fun _ => None).
(** Informally, we'll write [Gamma, x:T] for "extend the partial
function [Gamma] to also map [x] to [T]." Formally, we use the
function [extend] to add a binding to a partial map. *)
Definition extend {A:Type} (Gamma : partial_map A) (x:id) (T : A) :=
fun x' => if eq_id_dec x x' then Some T else Gamma x'.
Lemma extend_eq : forall A (ctxt: partial_map A) x T,
(extend ctxt x T) x = Some T.
Proof.
intros. unfold extend. rewrite eq_id. auto.
Qed.
Lemma extend_neq : forall A (ctxt: partial_map A) x1 T x2,
x2 <> x1 ->
(extend ctxt x2 T) x1 = ctxt x1.
Proof.
intros. unfold extend. rewrite neq_id; auto.
Qed.
End PartialMap.
Definition context := partial_map ty.
(* ################################### *)
(** *** Typing Relation *)
(**
Gamma x = T
-------------- (T_Var)
Gamma ⊢ x ∈ T
Gamma , x:T11 ⊢ t12 ∈ T12
---------------------------- (T_Abs)
Gamma ⊢ λx:T11.t12 ∈ T11->T12
Gamma ⊢ t1 ∈ T11->T12
Gamma ⊢ t2 ∈ T11
---------------------- (T_App)
Gamma ⊢ t1 t2 ∈ T12
-------------------- (T_True)
Gamma ⊢ true ∈ Bool
--------------------- (T_False)
Gamma ⊢ false ∈ Bool
Gamma ⊢ t1 ∈ Bool Gamma ⊢ t2 ∈ T Gamma ⊢ t3 ∈ T
-------------------------------------------------------- (T_If)
Gamma ⊢ if t1 then t2 else t3 ∈ T
We can read the three-place relation [Gamma ⊢ t ∈ T] as:
"to the term [t] we can assign the type [T] using as types for
the free variables of [t] the ones specified in the context
[Gamma]." *)
Reserved Notation "Gamma '⊢' t '∈' T" (at level 40).
Inductive has_type : context -> tm -> ty -> Prop :=
| T_Var : forall Gamma x T,
Gamma x = Some T ->
Gamma ⊢ tvar x ∈ T
| T_Abs : forall Gamma x T11 T12 t12,
extend Gamma x T11 ⊢ t12 ∈ T12 ->
Gamma ⊢ tabs x T11 t12 ∈ TArrow T11 T12
| T_App : forall T11 T12 Gamma t1 t2,
Gamma ⊢ t1 ∈ TArrow T11 T12 ->
Gamma ⊢ t2 ∈ T11 ->
Gamma ⊢ tapp t1 t2 ∈ T12
| T_True : forall Gamma,
Gamma ⊢ ttrue ∈ TBool
| T_False : forall Gamma,
Gamma ⊢ tfalse ∈ TBool
| T_If : forall t1 t2 t3 T Gamma,
Gamma ⊢ t1 ∈ TBool ->
Gamma ⊢ t2 ∈ T ->
Gamma ⊢ t3 ∈ T ->
Gamma ⊢ tif t1 t2 t3 ∈ T
where "Gamma '⊢' t '∈' T" := (has_type Gamma t T).
Tactic Notation "has_type_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "T_Var" | Case_aux c "T_Abs"
| Case_aux c "T_App" | Case_aux c "T_True"
| Case_aux c "T_False" | Case_aux c "T_If" ].
Hint Constructors has_type.
(* ################################### *)
(** *** Examples *)
Example typing_example_1 :
empty ⊢ tabs x TBool (tvar x) ∈ TArrow TBool TBool.
Proof. apply T_Abs. apply T_Var. reflexivity. Qed.
(** Note that since we added the [has_type] constructors to the hints
database, auto can actually solve this one immediately. *)
Example typing_example_1' :
empty ⊢ tabs x TBool (tvar x) ∈ TArrow TBool TBool.
Proof. auto. Qed.
(** Another example:
empty ⊢ λx:A. λy:A->A. y (y x))
∈ A -> (A->A) -> A.
*)
Example typing_example_2 :
empty ⊢
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) ∈
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof with auto using extend_eq.
repeat apply T_Abs.
eapply T_App. apply T_Var...
eapply T_App. apply T_Var...
apply T_Var...
Qed.
(** **** Exercise: 2 stars, optional (typing_example_2_full) *)
(** Prove the same result without using [auto], [eauto], or
[eapply]. *)
Example typing_example_2_full :
empty ⊢
(tabs x TBool
(tabs y (TArrow TBool TBool)
(tapp (tvar y) (tapp (tvar y) (tvar x))))) ∈
(TArrow TBool (TArrow (TArrow TBool TBool) TBool)).
Proof. repeat econstructor. Qed.
(** [] *)
(** **** Exercise: 2 stars (typing_example_3) *)
(** Formally prove the following typing derivation holds: *)
(**
empty ⊢ λx:Bool->B. λy:Bool->Bool. λz:Bool.
y (x z)
∈ T.
*)
Example typing_example_3 :
exists T,
empty ⊢
(tabs x (TArrow TBool TBool)
(tabs y (TArrow TBool TBool)
(tabs z TBool
(tapp (tvar y) (tapp (tvar x) (tvar z)))))) ∈
T.
Proof.
exists (TArrow (TArrow TBool TBool)
(TArrow (TArrow TBool TBool)
(TArrow TBool TBool))).
repeat econstructor.
Qed.
(** [] *)
(** We can also show that terms are _not_ typable. For example, let's
formally check that there is no typing derivation assigning a type
to the term [λx:Bool. λy:Bool, x y] -- i.e.,
~ exists T,
empty ⊢ λx:Bool. λy:Bool, x y : T.
*)
Example typing_nonexample_1 :
~ exists T,
empty ⊢
(tabs x TBool
(tabs y TBool
(tapp (tvar x) (tvar y)))) ∈
T.
Proof.
intros Hc. inversion Hc.
(* The [clear] tactic is useful here for tidying away bits of
the context that we're not going to need again. *)
inversion H. subst. clear H.
inversion H5. subst. clear H5.
inversion H4. subst. clear H4.
inversion H2. subst. clear H2.
inversion H5. subst. clear H5.
(* rewrite extend_neq in H1. rewrite extend_eq in H1. *)
inversion H1. Qed.
(** **** Exercise: 3 stars, optional (typing_nonexample_3) *)
(** Another nonexample:
~ (exists S, exists T,
empty ⊢ λx:S. x x : T).
*)
Example typing_nonexample_3 :
~ (exists S, exists T,
empty ⊢
(tabs x S
(tapp (tvar x) (tvar x))) ∈
T).
Proof.
intro Hc. inversion Hc.
inversion H; subst; clear H.
inversion H0; subst; clear H0.
inversion H5; subst; clear H5.
inversion H2; inversion H4; subst; clear H2; clear H4.
inversion H1; inversion H7; subst; clear H1; clear H7.
induction T11; inversion H2. induction H1. apply IHT11_1. apply H0.
Qed.
End STLC.
(* $Date: 2013-11-20 13:03:49 -0500 (Wed, 20 Nov 2013) $ *)
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__TAPVGND2_FUNCTIONAL_V
`define SKY130_FD_SC_LP__TAPVGND2_FUNCTIONAL_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection 2
* rows down.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
`celldefine
module sky130_fd_sc_lp__tapvgnd2 ();
// No contents.
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LP__TAPVGND2_FUNCTIONAL_V |
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_timing_param #
( parameter
CFG_DWIDTH_RATIO = 2,
CFG_CTL_ARBITER_TYPE = "ROWCOL",
// cfg: general
CFG_PORT_WIDTH_TYPE = 3,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
// cfg: timing parameters
CFG_PORT_WIDTH_CAS_WR_LAT = 4, // max will be 8 in DDR3
CFG_PORT_WIDTH_ADD_LAT = 3, // max will be 10 in DDR3
CFG_PORT_WIDTH_TCL = 4, // max will be 11 in DDR3
CFG_PORT_WIDTH_TRRD = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TFAW = 6, // 6 - 32 enough?
CFG_PORT_WIDTH_TRFC = 8, // 12-140 enough?
CFG_PORT_WIDTH_TREFI = 13, // 780 - 6240 enough?
CFG_PORT_WIDTH_TRCD = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TRP = 4, // 2 - 11 enough?
CFG_PORT_WIDTH_TWR = 4, // 2 - 12 enough?
CFG_PORT_WIDTH_TWTR = 4, // 1 - 10 enough?
CFG_PORT_WIDTH_TRTP = 4, // 2 - 8 enough?
CFG_PORT_WIDTH_TRAS = 5, // 4 - 29 enough?
CFG_PORT_WIDTH_TRC = 6, // 8 - 40 enough?
CFG_PORT_WIDTH_TCCD = 3, // max will be 4 in 4n prefetch architecture?
CFG_PORT_WIDTH_TMRD = 3, // 4 - ? enough?
CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10, // max will be 512 in DDR3
CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4, // 3 - ? enough?
CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16, // enough?
CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES = 4, // enough?
CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES = 4, // enough?
// cfg: extra timing parameters
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4,
CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4,
// Output - derived timing parameters width
T_PARAM_ACT_TO_RDWR_WIDTH = 6, // temporary
T_PARAM_ACT_TO_PCH_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_WIDTH = 6, // temporary
T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_BC_WIDTH = 6, // temporary
T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_RD_TO_PCH_WIDTH = 6, // temporary
T_PARAM_RD_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_WIDTH = 6, // temporary
T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_BC_WIDTH = 6, // temporary
T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH = 6, // temporary
T_PARAM_WR_TO_PCH_WIDTH = 6, // temporary
T_PARAM_WR_AP_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_TO_VALID_WIDTH = 6, // temporary
T_PARAM_PCH_ALL_TO_VALID_WIDTH = 6, // temporary
T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH = 6, // temporary
T_PARAM_FOUR_ACT_TO_ACT_WIDTH = 6, // temporary
T_PARAM_ARF_TO_VALID_WIDTH = 8, // temporary
T_PARAM_PDN_TO_VALID_WIDTH = 6, // temporary
T_PARAM_SRF_TO_VALID_WIDTH = 10, // temporary
T_PARAM_SRF_TO_ZQ_CAL_WIDTH = 10, // temporary
T_PARAM_ARF_PERIOD_WIDTH = 13, // temporary
T_PARAM_PDN_PERIOD_WIDTH = 16, // temporary
T_PARAM_POWER_SAVING_EXIT_WIDTH = 6, // temporary
T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH = 4 // temporary
)
(
ctl_clk,
ctl_reset_n,
// Input - configuration
cfg_burst_length,
cfg_type,
// Input - memory timing parameter
cfg_cas_wr_lat,
cfg_add_lat,
cfg_tcl,
cfg_trrd,
cfg_tfaw,
cfg_trfc,
cfg_trefi,
cfg_trcd,
cfg_trp,
cfg_twr,
cfg_twtr,
cfg_trtp,
cfg_tras,
cfg_trc,
cfg_tccd,
cfg_tmrd,
cfg_self_rfsh_exit_cycles,
cfg_pdn_exit_cycles,
cfg_auto_pd_cycles,
cfg_power_saving_exit_cycles,
cfg_mem_clk_entry_cycles,
// Input - extra derived timing parameter
cfg_extra_ctl_clk_act_to_rdwr,
cfg_extra_ctl_clk_act_to_pch,
cfg_extra_ctl_clk_act_to_act,
cfg_extra_ctl_clk_rd_to_rd,
cfg_extra_ctl_clk_rd_to_rd_diff_chip,
cfg_extra_ctl_clk_rd_to_wr,
cfg_extra_ctl_clk_rd_to_wr_bc,
cfg_extra_ctl_clk_rd_to_wr_diff_chip,
cfg_extra_ctl_clk_rd_to_pch,
cfg_extra_ctl_clk_rd_ap_to_valid,
cfg_extra_ctl_clk_wr_to_wr,
cfg_extra_ctl_clk_wr_to_wr_diff_chip,
cfg_extra_ctl_clk_wr_to_rd,
cfg_extra_ctl_clk_wr_to_rd_bc,
cfg_extra_ctl_clk_wr_to_rd_diff_chip,
cfg_extra_ctl_clk_wr_to_pch,
cfg_extra_ctl_clk_wr_ap_to_valid,
cfg_extra_ctl_clk_pch_to_valid,
cfg_extra_ctl_clk_pch_all_to_valid,
cfg_extra_ctl_clk_act_to_act_diff_bank,
cfg_extra_ctl_clk_four_act_to_act,
cfg_extra_ctl_clk_arf_to_valid,
cfg_extra_ctl_clk_pdn_to_valid,
cfg_extra_ctl_clk_srf_to_valid,
cfg_extra_ctl_clk_srf_to_zq_cal,
cfg_extra_ctl_clk_arf_period,
cfg_extra_ctl_clk_pdn_period,
// Output - derived timing parameters
t_param_act_to_rdwr,
t_param_act_to_pch,
t_param_act_to_act,
t_param_rd_to_rd,
t_param_rd_to_rd_diff_chip,
t_param_rd_to_wr,
t_param_rd_to_wr_bc,
t_param_rd_to_wr_diff_chip,
t_param_rd_to_pch,
t_param_rd_ap_to_valid,
t_param_wr_to_wr,
t_param_wr_to_wr_diff_chip,
t_param_wr_to_rd,
t_param_wr_to_rd_bc,
t_param_wr_to_rd_diff_chip,
t_param_wr_to_pch,
t_param_wr_ap_to_valid,
t_param_pch_to_valid,
t_param_pch_all_to_valid,
t_param_act_to_act_diff_bank,
t_param_four_act_to_act,
t_param_arf_to_valid,
t_param_pdn_to_valid,
t_param_srf_to_valid,
t_param_srf_to_zq_cal,
t_param_arf_period,
t_param_pdn_period,
t_param_power_saving_exit,
t_param_mem_clk_entry_cycles
);
input ctl_clk;
input ctl_reset_n;
// Input - configuration
input [CFG_PORT_WIDTH_BURST_LENGTH - 1 : 0] cfg_burst_length;
input [CFG_PORT_WIDTH_TYPE - 1 : 0] cfg_type;
// Input - memory timing parameter
input [CFG_PORT_WIDTH_CAS_WR_LAT - 1 : 0] cfg_cas_wr_lat;
input [CFG_PORT_WIDTH_ADD_LAT - 1 : 0] cfg_add_lat;
input [CFG_PORT_WIDTH_TCL - 1 : 0] cfg_tcl;
input [CFG_PORT_WIDTH_TRRD - 1 : 0] cfg_trrd;
input [CFG_PORT_WIDTH_TFAW - 1 : 0] cfg_tfaw;
input [CFG_PORT_WIDTH_TRFC - 1 : 0] cfg_trfc;
input [CFG_PORT_WIDTH_TREFI - 1 : 0] cfg_trefi;
input [CFG_PORT_WIDTH_TRCD - 1 : 0] cfg_trcd;
input [CFG_PORT_WIDTH_TRP - 1 : 0] cfg_trp;
input [CFG_PORT_WIDTH_TWR - 1 : 0] cfg_twr;
input [CFG_PORT_WIDTH_TWTR - 1 : 0] cfg_twtr;
input [CFG_PORT_WIDTH_TRTP - 1 : 0] cfg_trtp;
input [CFG_PORT_WIDTH_TRAS - 1 : 0] cfg_tras;
input [CFG_PORT_WIDTH_TRC - 1 : 0] cfg_trc;
input [CFG_PORT_WIDTH_TCCD - 1 : 0] cfg_tccd;
input [CFG_PORT_WIDTH_TMRD - 1 : 0] cfg_tmrd;
input [CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES - 1 : 0] cfg_self_rfsh_exit_cycles;
input [CFG_PORT_WIDTH_PDN_EXIT_CYCLES - 1 : 0] cfg_pdn_exit_cycles;
input [CFG_PORT_WIDTH_AUTO_PD_CYCLES - 1 : 0] cfg_auto_pd_cycles;
input [CFG_PORT_WIDTH_POWER_SAVING_EXIT_CYCLES - 1 : 0] cfg_power_saving_exit_cycles;
input [CFG_PORT_WIDTH_MEM_CLK_ENTRY_CYCLES - 1 : 0] cfg_mem_clk_entry_cycles;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR - 1 : 0] cfg_extra_ctl_clk_act_to_rdwr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH - 1 : 0] cfg_extra_ctl_clk_act_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD - 1 : 0] cfg_extra_ctl_clk_rd_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR - 1 : 0] cfg_extra_ctl_clk_rd_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_rd_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH - 1 : 0] cfg_extra_ctl_clk_rd_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_rd_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR - 1 : 0] cfg_extra_ctl_clk_wr_to_wr;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_wr_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD - 1 : 0] cfg_extra_ctl_clk_wr_to_rd;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_bc;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP - 1 : 0] cfg_extra_ctl_clk_wr_to_rd_diff_chip;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH - 1 : 0] cfg_extra_ctl_clk_wr_to_pch;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID - 1 : 0] cfg_extra_ctl_clk_wr_ap_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pch_all_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK - 1 : 0] cfg_extra_ctl_clk_act_to_act_diff_bank;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT - 1 : 0] cfg_extra_ctl_clk_four_act_to_act;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_arf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID - 1 : 0] cfg_extra_ctl_clk_pdn_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID - 1 : 0] cfg_extra_ctl_clk_srf_to_valid;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL - 1 : 0] cfg_extra_ctl_clk_srf_to_zq_cal;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD - 1 : 0] cfg_extra_ctl_clk_arf_period;
input [CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD - 1 : 0] cfg_extra_ctl_clk_pdn_period;
// Output - derived timing parameters
output [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
output [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
output [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
output [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
output [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
output [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
output [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
output [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
output [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
output [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
output [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
output [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
output [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
output [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
output [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
output [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
output [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
output [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
output [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
output [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
output [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
output [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
output [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
output [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
output [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
output [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
output [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
output [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
output [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
//--------------------------------------------------------------------------------------------------------
//
// [START] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
// Output
reg [T_PARAM_ACT_TO_RDWR_WIDTH - 1 : 0] t_param_act_to_rdwr;
reg [T_PARAM_ACT_TO_PCH_WIDTH - 1 : 0] t_param_act_to_pch;
reg [T_PARAM_ACT_TO_ACT_WIDTH - 1 : 0] t_param_act_to_act;
reg [T_PARAM_RD_TO_RD_WIDTH - 1 : 0] t_param_rd_to_rd;
reg [T_PARAM_RD_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_rd_diff_chip;
reg [T_PARAM_RD_TO_WR_WIDTH - 1 : 0] t_param_rd_to_wr;
reg [T_PARAM_RD_TO_WR_BC_WIDTH - 1 : 0] t_param_rd_to_wr_bc;
reg [T_PARAM_RD_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_rd_to_wr_diff_chip;
reg [T_PARAM_RD_TO_PCH_WIDTH - 1 : 0] t_param_rd_to_pch;
reg [T_PARAM_RD_AP_TO_VALID_WIDTH - 1 : 0] t_param_rd_ap_to_valid;
reg [T_PARAM_WR_TO_WR_WIDTH - 1 : 0] t_param_wr_to_wr;
reg [T_PARAM_WR_TO_WR_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_wr_diff_chip;
reg [T_PARAM_WR_TO_RD_WIDTH - 1 : 0] t_param_wr_to_rd;
reg [T_PARAM_WR_TO_RD_BC_WIDTH - 1 : 0] t_param_wr_to_rd_bc;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] t_param_wr_to_rd_diff_chip;
reg [T_PARAM_WR_TO_PCH_WIDTH - 1 : 0] t_param_wr_to_pch;
reg [T_PARAM_WR_AP_TO_VALID_WIDTH - 1 : 0] t_param_wr_ap_to_valid;
reg [T_PARAM_PCH_TO_VALID_WIDTH - 1 : 0] t_param_pch_to_valid;
reg [T_PARAM_PCH_ALL_TO_VALID_WIDTH - 1 : 0] t_param_pch_all_to_valid;
reg [T_PARAM_ACT_TO_ACT_DIFF_BANK_WIDTH - 1 : 0] t_param_act_to_act_diff_bank;
reg [T_PARAM_FOUR_ACT_TO_ACT_WIDTH - 1 : 0] t_param_four_act_to_act;
reg [T_PARAM_ARF_TO_VALID_WIDTH - 1 : 0] t_param_arf_to_valid;
reg [T_PARAM_PDN_TO_VALID_WIDTH - 1 : 0] t_param_pdn_to_valid;
reg [T_PARAM_SRF_TO_VALID_WIDTH - 1 : 0] t_param_srf_to_valid;
reg [T_PARAM_SRF_TO_ZQ_CAL_WIDTH - 1 : 0] t_param_srf_to_zq_cal;
reg [T_PARAM_ARF_PERIOD_WIDTH - 1 : 0] t_param_arf_period;
reg [T_PARAM_PDN_PERIOD_WIDTH - 1 : 0] t_param_pdn_period;
reg [T_PARAM_POWER_SAVING_EXIT_WIDTH - 1 : 0] t_param_power_saving_exit;
reg [T_PARAM_MEM_CLK_ENTRY_CYCLES_WIDTH - 1 : 0] t_param_mem_clk_entry_cycles;
reg [T_PARAM_WR_TO_RD_DIFF_CHIP_WIDTH - 1 : 0] temp_wr_to_rd_diff_chip;
//--------------------------------------------------------------------------------------------------------
//
// [END] Register & Wires
//
//--------------------------------------------------------------------------------------------------------
//--------------------------------------------------------------------------------------------------------
//
// [START] Timing Parameter Calculation
//
// Important Note:
//
// - Added "cfg_extra_ctl_clk_*" ports into our timing parameter calculation in order for us to
// tweak the timing parameter gaps in the future without changing the code
//
// - This will be very useful in HIP implementation
//
// - "cfg_extra_ctl_clk_*" must be set in term of controller clock cycles
//
//--------------------------------------------------------------------------------------------------------
// DIV is a divider for our timing parameters, DIV will be '1' in fullrate, '2' in halfrate
// and '4' in quarter rate
localparam DIV = CFG_DWIDTH_RATIO / 2;
// Use the following table to determine the optimum timing parameter
// ==========================================================================================================
// || Controller Rate || Arbiter Type || Command Transition || Remainder DIV || Offset ||
// ==========================================================================================================
// || FR || Don't care || Don't care || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || No || Yes ||
// -- HR -----------------------------------------------------------------------------------
// || || || Row -> Col || No || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes || No ||
// ----------------------------------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || No ||
// -- -- ROWCOL ---------------------------------------------------------------
// || || || Col -> Row || Yes* || Yes ||
// -- QR -----------------------------------------------------------------------------------
// || || || Row -> Col || Yes* || Yes ||
// -- -- COLROW ---------------------------------------------------------------
// || || || Col -> Row || Yes* || No ||
// ----------------------------------------------------------------------------------------------------------
// Footnote:
// * for calculation with remainder of '3' only
//---------------------------------------------------
// Remainder calculation
//---------------------------------------------------
// We need to remove the extra clock cycle in half and quarter rate
// for two subsequent different commands but remain for two subsequent same commands
// example of two subsequent different commands: ROW-TO-COL, COL-TO-ROW
// example of two subsequent same commands: ROW-TO-ROW, COL-TO-COL
// Self to self command require DIV
localparam DIV_ROW_TO_ROW = DIV;
localparam DIV_COL_TO_COL = DIV;
localparam DIV_SB_TO_SB = DIV;
localparam DIV_ROW_TO_COL = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? DIV : 1 // Only need DIV in ROWCOL arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_COL_TO_ROW = (
(CFG_DWIDTH_RATIO == 2 || CFG_DWIDTH_RATIO == 8) ?
(
DIV // Need DIV in full & quarter rate
) :
(
(CFG_DWIDTH_RATIO == 4) ?
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? DIV : 1 // Only need DIV in COLROW arbiter mode
) :
(
DIV // DIV is assigned by default
)
)
);
localparam DIV_SB_TO_ROW = DIV_COL_TO_ROW; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Remainder offset calculation
//---------------------------------------------------
// In QR, odd number calculation will only need to add extra offset when calculation's remainder is > 2
// Self to self command's remainder offset will be 0
localparam DIV_ROW_TO_ROW_OFFSET = 0;
localparam DIV_COL_TO_COL_OFFSET = 0;
localparam DIV_SB_TO_SB_OFFSET = 0;
localparam DIV_ROW_TO_COL_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_COL_TO_ROW_OFFSET = (CFG_DWIDTH_RATIO == 8) ? 2 : 0;
localparam DIV_SB_TO_ROW_OFFSET = DIV_COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//---------------------------------------------------
// Offset calculation
//---------------------------------------------------
// We need to offset timing parameter due to HR 1T and QR 2T support
// this is because we can issue a row and column command in one controller clock cycle
// Self to self command doesn't require offset
localparam ROW_TO_ROW_OFFSET = 0;
localparam COL_TO_COL_OFFSET = 0;
localparam SB_TO_SB_OFFSET = 0;
localparam ROW_TO_COL_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "ROWCOL") ? 0 : 1 // Need offset in ROWCOL arbiter mode
)
);
localparam COL_TO_ROW_OFFSET = (
(CFG_DWIDTH_RATIO == 2) ?
(
0 // Offset is not required in full rate
) :
(
(CFG_CTL_ARBITER_TYPE == "COLROW") ? 0 : 1 // Need offset in COLROW arbiter mode
)
);
localparam SB_TO_ROW_OFFSET = COL_TO_ROW_OFFSET; // Similar to COL_TO_ROW parameter
//----------------------------------------------------------------------------------------------------
// Common timing parameters, not memory type specific
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_act_to_rdwr <= 0;
t_param_act_to_pch <= 0;
t_param_act_to_act <= 0;
t_param_pch_to_valid <= 0;
t_param_act_to_act_diff_bank <= 0;
t_param_four_act_to_act <= 0;
t_param_arf_to_valid <= 0;
t_param_pdn_to_valid <= 0;
t_param_srf_to_valid <= 0;
t_param_arf_period <= 0;
t_param_pdn_period <= 0;
t_param_power_saving_exit <= 0;
t_param_mem_clk_entry_cycles <= 0;
end
else
begin
// Set act_to_rdwr to '0' when additive latency is enabled
if (cfg_add_lat >= (cfg_trcd - 1))
t_param_act_to_rdwr <= 0 + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ;
else
t_param_act_to_rdwr <= ((cfg_trcd - cfg_add_lat) / DIV) + (((cfg_trcd - cfg_add_lat) % DIV_ROW_TO_COL) > DIV_ROW_TO_COL_OFFSET ? 1 : 0) + ROW_TO_COL_OFFSET + cfg_extra_ctl_clk_act_to_rdwr ; // ACT to RD/WR - tRCD
t_param_act_to_pch <= (cfg_tras / DIV) + ((cfg_tras % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_pch ; // ACT to PCH - tRAS
t_param_act_to_act <= (cfg_trc / DIV) + ((cfg_trc % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act ; // ACT to ACT (same bank) - tRC
t_param_pch_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_to_valid ; // PCH to ACT - tRP
t_param_act_to_act_diff_bank <= (cfg_trrd / DIV) + ((cfg_trrd % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_act_to_act_diff_bank; // ACT to ACT (diff banks) - tRRD
t_param_four_act_to_act <= (cfg_tfaw / DIV) + ((cfg_tfaw % DIV_ROW_TO_ROW) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + ROW_TO_ROW_OFFSET + cfg_extra_ctl_clk_four_act_to_act ; // Valid window for 4 ACT - tFAW
t_param_arf_to_valid <= (cfg_trfc / DIV) + ((cfg_trfc % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_arf_to_valid ; // ARF to VALID - tRFC
t_param_pdn_to_valid <= (cfg_pdn_exit_cycles / DIV) + ((cfg_pdn_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pdn_to_valid ; // PDN to VALID - normally 3 clock cycles
t_param_srf_to_valid <= (cfg_self_rfsh_exit_cycles / DIV) + ((cfg_self_rfsh_exit_cycles % DIV_SB_TO_ROW ) > DIV_ROW_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_srf_to_valid ; // SRF to VALID - normally 200 clock cycles
t_param_arf_period <= (cfg_trefi / DIV) + ((cfg_trefi % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_arf_period ; // ARF period - tREFI
t_param_pdn_period <= cfg_auto_pd_cycles + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_pdn_period ; // PDN count after TBP is empty - specified by user
t_param_power_saving_exit <= (cfg_power_saving_exit_cycles / DIV) + ((cfg_power_saving_exit_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN exit cycles
t_param_mem_clk_entry_cycles <= (cfg_mem_clk_entry_cycles / DIV) + ((cfg_mem_clk_entry_cycles % DIV_SB_TO_SB ) > DIV_SB_TO_SB_OFFSET ? 1 : 0) + SB_TO_SB_OFFSET ; // SRF and PDN mem clock entry and exit cycles
end
end
//----------------------------------------------------------------------------------------------------
// Memory type specific timing parameters
//----------------------------------------------------------------------------------------------------
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
t_param_rd_to_rd <= 0;
t_param_rd_to_rd_diff_chip <= 0;
t_param_rd_to_wr <= 0;
t_param_rd_to_wr_bc <= 0;
t_param_rd_to_wr_diff_chip <= 0;
t_param_rd_to_pch <= 0;
t_param_rd_ap_to_valid <= 0;
t_param_wr_to_wr <= 0;
t_param_wr_to_wr_diff_chip <= 0;
t_param_wr_to_rd <= 0;
t_param_wr_to_rd_bc <= 0;
t_param_wr_to_rd_diff_chip <= 0;
t_param_wr_to_pch <= 0;
t_param_wr_ap_to_valid <= 0;
t_param_pch_all_to_valid <= 0;
t_param_srf_to_zq_cal <= 0;
temp_wr_to_rd_diff_chip <= 0;
end
else
begin
if (cfg_type == `MMR_TYPE_DDR1)
begin
// DDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR2)
begin
// DDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 1, (RL - WL) will always be '1'
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - 2 + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 1) / DIV) + ((((cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_tcl - 1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_DDR3)
begin
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
// Temp value to make sure value is always larger than tCL (guaranteed), else it might create problem in HIP
// BL will alyways be set to 8 and max difference between tCL and tCWL is 3
temp_wr_to_rd_diff_chip <= (cfg_cas_wr_lat + (cfg_burst_length / 2) + 2);
t_param_rd_to_rd <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 4) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - RL - WL + (BL/4) + 2
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + max(cfg_trtp, 4)) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + max(tRTP or 4)
t_param_rd_ap_to_valid <= ((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) / DIV) + (((cfg_add_lat + max(cfg_trtp, 4) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= ((cfg_burst_length / 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - BL/2, not tCCD because there is no burst interrupt support in DDR3
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 4)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - Same as WR to RD
t_param_wr_to_rd_diff_chip <= ((temp_wr_to_rd_diff_chip - cfg_tcl) / DIV) + (((temp_wr_to_rd_diff_chip - cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= (cfg_trp / DIV) + ((cfg_trp % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRP
t_param_srf_to_zq_cal <= ((cfg_self_rfsh_exit_cycles / 2) / DIV) + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - SRF exit time divided by 2
end
else if (cfg_type == `MMR_TYPE_LPDDR1)
begin
// LPDDR
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= (((cfg_burst_length / 2) + cfg_tcl) / DIV) + ((((cfg_burst_length / 2) + cfg_tcl) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL + (BL/2)
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + ((((cfg_burst_length / 2) + 2) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_burst_length / 2) / DIV) + (((cfg_burst_length / 2) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - (BL/2)
t_param_rd_ap_to_valid <= (((cfg_burst_length / 2) + cfg_trp) / DIV) + ((((cfg_burst_length / 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((1 + (cfg_burst_length / 2) + cfg_twtr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twtr) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + tWTR, WL always 1
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= (((cfg_burst_length / 2) + 3) / DIV) + ((((cfg_burst_length / 2) + 3) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - 1 + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((1 + (cfg_burst_length / 2) + cfg_twr) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) / DIV) + (((1 + (cfg_burst_length / 2) + cfg_twr + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
else if (cfg_type == `MMR_TYPE_LPDDR2)
begin
// LPDDR2
// ******************************
// Note, if the below formulas are changed then the formulas in the report_timing_core.tcl files need to be changed
// to remain consistent with the controller
// ******************************
// Temp value to precalculate difference between tCL and tCWL + 2 (dead cycle)
if ((cfg_tcl - cfg_cas_wr_lat) > 2)
begin
temp_wr_to_rd_diff_chip <= 0;
end
else
begin
temp_wr_to_rd_diff_chip <= (cfg_cas_wr_lat + 2) - cfg_tcl;
end
t_param_rd_to_rd <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd ; // RD to RD - tCCD
t_param_rd_to_rd_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_rd_diff_chip; // RD to RD diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_rd_to_wr <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr ; // RD to WR - RL - WL + (BL/2) + 2
t_param_rd_to_wr_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_bc ; // RDBC to WR - 0, DDR3 specific only
t_param_rd_to_wr_diff_chip <= ((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) / DIV) + (((cfg_tcl - cfg_cas_wr_lat + (cfg_burst_length / 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_rd_to_wr_diff_chip; // RD to WR diff rank - Same as RD to WR
t_param_rd_to_pch <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2)) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_to_pch ; // RD to PCH - AL + (BL/2) - 2 + max(tRTP or 2)
t_param_rd_ap_to_valid <= ((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) / DIV) + (((cfg_add_lat + (cfg_burst_length / 2) - cfg_tccd + max(cfg_trtp, 2) + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_rd_ap_to_valid ; // RDAP to VALID - RD to PCH + PCH to VALID
t_param_wr_to_wr <= (cfg_tccd / DIV) + ((cfg_tccd % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr ; // WR to WR - tCCD
t_param_wr_to_wr_diff_chip <= (((cfg_burst_length / 2) + 2) / DIV) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_wr_diff_chip; // WR to WR diff rank - (BL/2) + 2 (dead cycle), should be set to tCCD for burst interrupt support
t_param_wr_to_rd <= ((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) / DIV) + (((cfg_cas_wr_lat + (cfg_burst_length / 2) + max(cfg_twtr, 2) + 1) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd ; // WR to RD - WL + (BL/2) + max(tWTR or 4)
t_param_wr_to_rd_bc <= 0 + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_bc ; // WRBC to RD - 0, DDR3 specific only
t_param_wr_to_rd_diff_chip <= ((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) / DIV) + (((temp_wr_to_rd_diff_chip + (cfg_burst_length / 2)) % DIV_COL_TO_COL) > DIV_COL_TO_COL_OFFSET ? 1 : 0) + COL_TO_COL_OFFSET + cfg_extra_ctl_clk_wr_to_rd_diff_chip; // WR to RD diff rank - WL - RL + (BL/2) + 2, extra 2 dead cycles for DQS post and preamble
t_param_wr_to_pch <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_to_pch ; // WR to PCH - WL + (BL/2) + tWR
t_param_wr_ap_to_valid <= ((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) / DIV) + (((cfg_add_lat + cfg_cas_wr_lat + (cfg_burst_length / 2) + cfg_twr + 1 + cfg_trp) % DIV_COL_TO_ROW) > DIV_COL_TO_ROW_OFFSET ? 1 : 0) + COL_TO_ROW_OFFSET + cfg_extra_ctl_clk_wr_ap_to_valid ; // WRAP to VALID - WR to PCH + PCH to VALID
t_param_pch_all_to_valid <= ((cfg_trp + 1) / DIV) + (((cfg_trp + 1) % DIV_SB_TO_ROW ) > DIV_SB_TO_ROW_OFFSET ? 1 : 0) + SB_TO_ROW_OFFSET + cfg_extra_ctl_clk_pch_all_to_valid ; // PCHALL to VALID - tRPA = tRP + 1
t_param_srf_to_zq_cal <= 0 + SB_TO_SB_OFFSET + cfg_extra_ctl_clk_srf_to_zq_cal ; // SRF to ZQ CAL - 0, DDR3 specific only
end
end
end
// Function to determine max of 2 inputs
localparam MAX_FUNCTION_PORT_WIDTH = (CFG_PORT_WIDTH_TRTP > CFG_PORT_WIDTH_TWTR) ? CFG_PORT_WIDTH_TRTP : CFG_PORT_WIDTH_TWTR;
function [MAX_FUNCTION_PORT_WIDTH - 1 : 0] max;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value1;
input [MAX_FUNCTION_PORT_WIDTH - 1 : 0] value2;
begin
if (value1 > value2)
max = value1;
else
max = value2;
end
endfunction
//--------------------------------------------------------------------------------------------------------
//
// [END] Timing Parameter Calculation
//
//--------------------------------------------------------------------------------------------------------
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V
/**
* a32oi: 3-input AND into first input, and 2-input AND into
* 2nd input of 2-input NOR.
*
* Y = !((A1 & A2 & A3) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__a32oi (
VPWR,
VGND,
Y ,
A1 ,
A2 ,
A3 ,
B1 ,
B2
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A1 ;
input A2 ;
input A3 ;
input B1 ;
input B2 ;
// Local signals
wire B1 nand0_out ;
wire B1 nand1_out ;
wire and0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
nand nand0 (nand0_out , A2, A1, A3 );
nand nand1 (nand1_out , B2, B1 );
and and0 (and0_out_Y , nand0_out, nand1_out );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__A32OI_FUNCTIONAL_PP_V |
////////////////////////////////////////////////////////////////////////////////
// //
// This file is placed into the Public Domain, for any use, without warranty. //
// 2012 by Iztok Jeras //
// //
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// //
// This testbench contains a bus source and a bus drain. The source creates //
// address and data bus values, while the drain is the final destination of //
// such pairs. All source and drain transfers are logged into memories, which //
// are used at the end of simulation to check for data transfer correctness. //
// Inside the RLT wrapper there is a multiplexer and a demultiplexer, they //
// bus transfers into a 8bit data stream and back. Both stream input and //
// output are exposed, they are connected together into a loopback. //
// //
// ----------- --------------------- //
// | bso_mem | | wrap | //
// ----------- | | //
// ----------- | | ----------- | //
// | bsi src | ------------> | -> | mux | -> | -> - sto //
// ----------- | ----------- | \ //
// | | | loopback //
// ----------- | ----------- | / //
// | bso drn | <------------ | <- | demux | <- | <- - sti //
// ----------- | | ----------- | //
// ----------- | | //
// | bso_mem | | | //
// ----------- --------------------- //
// //
// PROTOCOL: //
// //
// The 'vld' signal is driven by the source to indicate valid data is //
// available, 'rdy' is used by the drain to indicate is is ready to accept //
// valid data. A data transfer only happens if both 'vld' & 'rdy' are active. //
// //
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns/1ps
// include RTL files
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_def.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_demux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_mux.sv"
`include "t_sv_bus_mux_demux/sv_bus_mux_demux_wrap.sv"
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
parameter SIZ = 10;
// system signals
//logic clk = 1'b1; // clock
logic rst = 1'b1; // reset
integer rst_cnt = 0;
// input bus
logic bsi_vld; // valid (chip select)
logic [31:0] bsi_adr; // address
logic [31:0] bsi_dat; // data
logic bsi_rdy; // ready (acknowledge)
logic bsi_trn; // data transfer
logic [31:0] bsi_mem [SIZ];
// output stream
logic sto_vld; // valid (chip select)
logic [7:0] sto_bus; // data bus
logic sto_rdy; // ready (acknowledge)
// input stream
logic sti_vld; // valid (chip select)
logic [7:0] sti_bus; // data bus
logic sti_rdy; // ready (acknowledge)
// output bus
logic bso_vld; // valid (chip select)
logic [31:0] bso_adr; // address
logic [31:0] bso_dat; // data
logic bso_rdy; // ready (acknowledge)
logic bso_trn; // data transfer
logic [31:0] bso_mem [SIZ];
integer bso_cnt = 0;
////////////////////////////////////////////////////////////////////////////////
// clock and reset
////////////////////////////////////////////////////////////////////////////////
// clock toggling
//always #5 clk = ~clk;
// reset is removed after a delay
always @ (posedge clk)
begin
rst_cnt <= rst_cnt + 1;
rst <= rst_cnt <= 3;
end
// reset is removed after a delay
always @ (posedge clk)
if (bso_cnt == SIZ) begin
if (bsi_mem === bso_mem) begin $write("*-* All Finished *-*\n"); $finish(); end
else begin $display ("FAILED"); $stop(); end
end
////////////////////////////////////////////////////////////////////////////////
// input data generator
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bsi_trn = bsi_vld & bsi_rdy;
// valid (for SIZ transfers)
always @ (posedge clk, posedge rst)
if (rst) bsi_vld = 1'b0;
else bsi_vld = (bsi_adr < SIZ);
// address (increments every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_adr <= 32'h00000000;
else if (bsi_trn) bsi_adr <= bsi_adr + 'd1;
// data (new random value generated after every transfer)
always @ (posedge clk, posedge rst)
if (rst) bsi_dat <= 32'h00000000;
else if (bsi_trn) bsi_dat <= $random();
// storing transferred data into memory for final check
always @ (posedge clk)
if (bsi_trn) bsi_mem [bsi_adr] <= bsi_dat;
////////////////////////////////////////////////////////////////////////////////
// RTL instance
////////////////////////////////////////////////////////////////////////////////
sv_bus_mux_demux_wrap wrap (
// system signals
.clk (clk),
.rst (rst),
// input bus
.bsi_vld (bsi_vld),
.bsi_adr (bsi_adr),
.bsi_dat (bsi_dat),
.bsi_rdy (bsi_rdy),
// output stream
.sto_vld (sto_vld),
.sto_bus (sto_bus),
.sto_rdy (sto_rdy),
// input stream
.sti_vld (sti_vld),
.sti_bus (sti_bus),
.sti_rdy (sti_rdy),
// output bus
.bso_vld (bso_vld),
.bso_adr (bso_adr),
.bso_dat (bso_dat),
.bso_rdy (bso_rdy)
);
// stream output from mux is looped back into stream input for demux
assign sti_vld = sto_vld;
assign sti_bus = sto_bus;
assign sto_rdy = sti_rdy;
////////////////////////////////////////////////////////////////////////////////
// output data monitor
////////////////////////////////////////////////////////////////////////////////
// input data transfer
assign bso_trn = bso_vld & bso_rdy;
// output transfer counter used to end the test
always @ (posedge clk, posedge rst)
if (rst) bso_cnt <= 0;
else if (bso_trn) bso_cnt <= bso_cnt + 1;
// storing transferred data into memory for final check
always @ (posedge clk)
if (bso_trn) bso_mem [bso_adr] <= bso_dat;
// every output transfer against expected value stored in memory
always @ (posedge clk)
if (bso_trn && (bsi_mem [bso_adr] !== bso_dat))
$display ("@%08h i:%08h o:%08h", bso_adr, bsi_mem [bso_adr], bso_dat);
// ready is active for SIZ transfers
always @ (posedge clk, posedge rst)
if (rst) bso_rdy = 1'b0;
else bso_rdy = 1'b1;
endmodule : sv_bus_mux_demux_tb
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__BUFBUF_8_V
`define SKY130_FD_SC_LS__BUFBUF_8_V
/**
* bufbuf: Double buffer.
*
* Verilog wrapper for bufbuf with size of 8 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__bufbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_8 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ls__bufbuf_8 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ls__bufbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LS__BUFBUF_8_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND2B_PP_BLACKBOX_V
`define SKY130_FD_SC_HS__NAND2B_PP_BLACKBOX_V
/**
* nand2b: 2-input NAND, first input inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__nand2b (
Y ,
A_N ,
B ,
VPWR,
VGND
);
output Y ;
input A_N ;
input B ;
input VPWR;
input VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND2B_PP_BLACKBOX_V
|
// -------------------------------------------------------------
//
// File Name: hdl_prj\hdlsrc\controllerPeripheralHdlAdi\controllerHdl\controllerHdl_Encoder_To_Position_And_Velocity.v
// Created: 2014-09-08 14:12:04
//
// Generated by MATLAB 8.2 and HDL Coder 3.3
//
// -------------------------------------------------------------
// -------------------------------------------------------------
//
// Module: controllerHdl_Encoder_To_Position_And_Velocity
// Source Path: controllerHdl/Encoder_To_Position_And_Velocity
// Hierarchy Level: 2
//
// -------------------------------------------------------------
`timescale 1 ns / 1 ns
module controllerHdl_Encoder_To_Position_And_Velocity
(
CLK_IN,
reset,
enb_1_2000_0,
encoder_valid,
encoder_counter,
param_zero_offset,
position_valid,
rotor_position,
electrical_position,
rotor_velocity
);
input CLK_IN;
input reset;
input enb_1_2000_0;
input encoder_valid;
input [15:0] encoder_counter; // uint16
input signed [17:0] param_zero_offset; // sfix18_En14
output position_valid;
output signed [17:0] rotor_position; // sfix18_En14
output signed [17:0] electrical_position; // sfix18_En14
output signed [17:0] rotor_velocity; // sfix18_En8
wire signed [17:0] Rotor_To_Electrical_Position_out1; // sfix18_En14
wire signed [17:0] Calculate_Rotor_Velocity_out1; // sfix18_En8
// Quadrature Encoder To Position And Velocity
assign position_valid = encoder_valid;
// <S2>/Encoder_To_Rotor_Position
controllerHdl_Encoder_To_Rotor_Position u_Encoder_To_Rotor_Position (.counter(encoder_counter), // uint16
.param_zero_offset(param_zero_offset), // sfix18_En14
.position(rotor_position) // sfix18_En14
);
// <S2>/Rotor_To_Electrical_Position
controllerHdl_Rotor_To_Electrical_Position u_Rotor_To_Electrical_Position (.R(rotor_position), // sfix18_En14
.E(Rotor_To_Electrical_Position_out1) // sfix18_En14
);
assign electrical_position = Rotor_To_Electrical_Position_out1;
// <S2>/Calculate_Rotor_Velocity
controllerHdl_Calculate_Rotor_Velocity u_Calculate_Rotor_Velocity (.CLK_IN(CLK_IN),
.reset(reset),
.enb_1_2000_0(enb_1_2000_0),
.valid(encoder_valid),
.position(rotor_position), // sfix18_En14
.rotor_velocity(Calculate_Rotor_Velocity_out1) // sfix18_En8
);
assign rotor_velocity = Calculate_Rotor_Velocity_out1;
endmodule // controllerHdl_Encoder_To_Position_And_Velocity
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Wishbone controller for ////
//// Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/minsoc/ ////
//// ////
//// Description ////
//// This Wishbone controller connects to the wrapper of ////
//// the single-port synchronous memory interface. ////
//// Besides universal memory due to onchip_ram it provides a ////
//// generic way to set the depth of the memory. ////
//// ////
//// To Do: ////
//// ////
//// Author(s): ////
//// - Raul Fajardo, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.gnu.org/licenses/lgpl.html ////
//// ////
//////////////////////////////////////////////////////////////////////
//
// Revision History
//
// Revision 1.1 2009/10/02 16:49 fajardo
// Not using the oe signal (output enable) from
// memories, instead multiplexing the outputs
// between the different instantiated blocks
//
//
// Revision 1.0 2009/08/18 15:15:00 fajardo
// Created interface and tested
//
`include "minsoc_defines.v"
module minsoc_onchip_ram_top (
wb_clk_i, wb_rst_i,
wb_dat_i, wb_dat_o, wb_adr_i, wb_sel_i, wb_we_i, wb_cyc_i,
wb_stb_i, wb_ack_o, wb_err_o
);
//
// Parameters
//
parameter adr_width = 13; //Memory address width, is composed by blocks of aw_int, is not allowed to be less than 12
localparam aw_int = 11; //11 = 2048
localparam blocks = (1<<(adr_width-aw_int)); //generated memory contains "blocks" memory blocks of 2048x32 2048 depth x32 bit data
//
// I/O Ports
//
input wb_clk_i;
input wb_rst_i;
//
// WB slave i/f
//
input [31:0] wb_dat_i;
output [31:0] wb_dat_o;
input [31:0] wb_adr_i;
input [3:0] wb_sel_i;
input wb_we_i;
input wb_cyc_i;
input wb_stb_i;
output wb_ack_o;
output wb_err_o;
//
// Internal regs and wires
//
wire we;
wire [3:0] be_i;
wire [31:0] wb_dat_o;
reg ack_we;
reg ack_re;
//
// Aliases and simple assignments
//
assign wb_ack_o = ack_re | ack_we;
assign wb_err_o = wb_cyc_i & wb_stb_i & (|wb_adr_i[23:adr_width+2]); // If Access to > (8-bit leading prefix ignored)
assign we = wb_cyc_i & wb_stb_i & wb_we_i & (|wb_sel_i[3:0]);
assign be_i = (wb_cyc_i & wb_stb_i) * wb_sel_i;
//
// Write acknowledge
//
always @ (negedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_we <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & wb_we_i & ~ack_we)
ack_we <= #1 1'b1;
else
ack_we <= #1 1'b0;
end
//
// read acknowledge
//
always @ (posedge wb_clk_i or posedge wb_rst_i)
begin
if (wb_rst_i)
ack_re <= 1'b0;
else
if (wb_cyc_i & wb_stb_i & ~wb_err_o & ~wb_we_i & ~ack_re)
ack_re <= #1 1'b1;
else
ack_re <= #1 1'b0;
end
//Generic (multiple inputs x 1 output) MUX
localparam mux_in_nr = blocks;
localparam slices = adr_width-aw_int;
localparam mux_out_nr = blocks-1;
wire [31:0] int_dat_o[0:mux_in_nr-1];
wire [31:0] mux_out[0:mux_out_nr-1];
generate
genvar j, k;
for (j=0; j<slices; j=j+1) begin : SLICES
for (k=0; k<(mux_in_nr>>(j+1)); k=k+1) begin : MUX
if (j==0) begin
mux21 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( int_dat_o[k*2] ),
.in2( int_dat_o[k*2+1] ),
.out( mux_out[k] )
);
end
else begin
mux21 #
(
.dw(32)
)
mux_int(
.sel( wb_adr_i[aw_int+2+j] ),
.in1( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2] ),
.in2( mux_out[(mux_in_nr-(mux_in_nr>>(j-1)))+k*2+1] ),
.out( mux_out[(mux_in_nr-(mux_in_nr>>j))+k] )
);
end
end
end
endgenerate
//last output = total output
assign wb_dat_o = mux_out[mux_out_nr-1];
//(mux_in_nr-(mux_in_nr>>j)):
//-Given sum of 2^i | i = x -> y series can be resumed to 2^(y+1)-2^x
//so, with this expression I'm evaluating how many times the internal loop has been run
wire [blocks-1:0] bank;
generate
genvar i;
for (i=0; i < blocks; i=i+1) begin : MEM
assign bank[i] = wb_adr_i[adr_width+1:aw_int+2] == i;
//BANK0
/* minsoc_onchip_ram block_ram_0 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[7:0]),
.doq(int_dat_o[i][7:0]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[0])
);
*/
RAMB16_S9 block_ram_0(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[7:0]),
.DIP(1'b0),
.EN(be_i[0]),
.WE(we & bank[i]),
.DO(int_dat_o[i][7:0]),
.DOP()
);
/*
minsoc_onchip_ram block_ram_1 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[15:8]),
.doq(int_dat_o[i][15:8]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[1])
);
*/
RAMB16_S9 block_ram_1(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[15:8]),
.DIP(1'b0),
.EN(be_i[1]),
.WE(we & bank[i]),
.DO(int_dat_o[i][15:8]),
.DOP()
);
/*
minsoc_onchip_ram block_ram_2 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[23:16]),
.doq(int_dat_o[i][23:16]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[2])
);
*/
RAMB16_S9 block_ram_2(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[23:16]),
.DIP(1'b0),
.EN(be_i[2]),
.WE(we & bank[i]),
.DO(int_dat_o[i][23:16]),
.DOP()
);
/*
minsoc_onchip_ram block_ram_3 (
.clk(wb_clk_i),
.rst(wb_rst_i),
.addr(wb_adr_i[aw_int+1:2]),
.di(wb_dat_i[31:24]),
.doq(int_dat_o[i][31:24]),
.we(we & bank[i]),
.oe(1'b1),
.ce(be_i[3])
);
*/
RAMB16_S9 block_ram_3(
.CLK(wb_clk_i),
.SSR(wb_rst_i),
.ADDR(wb_adr_i[aw_int+1:2]),
.DI(wb_dat_i[31:24]),
.DIP(1'b0),
.EN(be_i[3]),
.WE(we & bank[i]),
.DO(int_dat_o[i][31:24]),
.DOP()
);
end
endgenerate
`ifdef BLOCK_RAM_INIT
`include "block_ram.init"
`endif
endmodule
module mux21(sel,in1,in2,out);
parameter dw = 32;
input sel;
input [dw-1:0] in1, in2;
output reg [dw-1:0] out;
always @ (sel or in1 or in2)
begin
case (sel)
1'b0: out = in1;
1'b1: out = in2;
endcase
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2019 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// verilator lint_off WIDTH
typedef enum logic[2:0] {P=0, W=1'b1, E, N, S} Dirs;
typedef enum integer {UP=0, UW=1'b1} UNSIZED;
// verilator lint_on WIDTH
localparam LEN = 3;
localparam COL = 4;
localparam [59:0] SEQ = {LEN'(N), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(E), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(W), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(P)
,LEN'(S), LEN'(N), LEN'(E), LEN'(W)};
bit [59:0] SE2 = {N, E, W, P
,S, E, W, P
,S, N, W, P
,S, N, E, P
,S, N, E, W};
initial begin
if (SEQ != 60'o32104210431043204321) $stop;
if (SE2 != 60'o32104210431043204321) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
`define SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
/**
* probe_p: Virtual voltage probe point.
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__probe_p (
//# {{data|Data Signals}}
input A ,
output X ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__PROBE_P_PP_SYMBOL_V
|
/*******************************************************************
Company: UNSW
Original Author: Lingkan Gong
Project Name: XDRS
Create Date: 19/09/2010
Design Name: maximum
*******************************************************************/
`timescale 1ns/1ns
module maximum
#(parameter
C_CNT_BW = 32,
C_RETRY_DELAY = 16
)
(
input clk ,
input rstn ,
//-- to/from producer/consumer ----
output p_prdy ,
input p_crdy ,
input p_cerr ,
output [31:0] p_data ,
input c_prdy ,
output c_crdy ,
output c_cerr ,
input [31:0] c_data ,
//-- to/from reconfiguration controller----
input rc_reqn ,
output rc_ackn
);
//-------------------------------------------------------------------
// Signal Declaration
//-------------------------------------------------------------------
/* main data register: data1,2 */
wire data1_wr_en, data2_wr_en;
wire is_data_1; wire is_data_2;
reg [31:0] data1,data2;
/* retry & timeout counter */
reg [7:0] retrycnt; wire is_retry;
reg [3:0] tocnt;
/* main fsm */
reg [3:0] state_c, state_n;
localparam [3:0]
S_Rd1 = 4'd0,
S_Rd2 = 4'd1,
S_Wr = 4'd2,
S_ReTry = 4'd3,
S_IDLE = 4'd15;
//-------------------------------------------------------------------
// Datapath Registers
//-------------------------------------------------------------------
/* the retry & timeout counter */
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
retrycnt <= 8'h0;
end else begin
if (state_c == S_ReTry) retrycnt <= retrycnt+1'b1;
else if (state_c == S_Wr) retrycnt <= 'b0;
end
end
assign is_retry = (retrycnt == C_RETRY_DELAY-1);
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
tocnt <= 4'h0;
end else begin
if (c_prdy && ~c_crdy) tocnt <= tocnt + 'h1;
else tocnt <= 4'h0;
end
end
assign c_cerr = (tocnt == 4'hf) & (~c_crdy);
/* the data1,2 register */
assign data1_wr_en = c_prdy & c_crdy & is_data_1;
assign data2_wr_en = c_prdy & c_crdy & is_data_2;
always @(posedge clk or negedge rstn) begin
if (~rstn) begin
data1 <= 32'h0;
data2 <= 32'h0;
end else begin
if (data1_wr_en) data1 <= c_data;
if (data2_wr_en) data2 <= c_data;
end
end
/* assigning the output signals */
assign p_data = (data1 > data2)? data1: data2;
/* instantiate the stastical counter */
stat_cnt #(C_CNT_BW) stat_0(
.clk(clk),
.rstn(rstn),
//-- to/from the datapath to be monitored----
.din(c_data),
.din_valid(c_prdy & c_crdy),
.dout(p_data),
.dout_valid(p_prdy & p_crdy)
);
//-------------------------------------------------------------------
// Main FSM - Maximum fsm
//-------------------------------------------------------------------
always @(posedge clk or negedge rstn) begin
if (~rstn)
state_c <= S_IDLE;
else
state_c <= state_n;
end
always @(*) begin
case (state_c)
S_IDLE:begin state_n = (c_prdy)? S_Rd1:S_IDLE; end
S_Rd1:begin state_n = (c_prdy)? S_Rd2:S_Rd1; end
S_Rd2:begin state_n = (c_prdy)? S_Wr:S_Rd2; end
S_Wr: begin state_n = (p_crdy)? S_IDLE: (p_cerr)? S_ReTry:S_Wr; end
S_ReTry: begin state_n = (is_retry)? S_Wr: S_ReTry; end
default: begin state_n = S_IDLE; end
endcase
end
assign p_prdy = (state_c == S_Wr);
assign c_crdy = (state_c == S_Rd1) || (state_c == S_Rd2);
assign is_data_1 = (state_c == S_Rd1);
assign is_data_2 = (state_c == S_Rd2);
// synthesis translate_off
reg [8*20:1] state_ascii;
always @(*) begin
if (state_c==S_Rd1) state_ascii <= "RD1";
else if (state_c==S_Rd2) state_ascii <= "RD2";
else if (state_c==S_Wr) state_ascii <= "WR";
else if (state_c==S_ReTry) state_ascii <= "RETRY";
else if (state_c==S_IDLE) state_ascii <= "IDLE";
else state_ascii <= "ERROR";
end
// synthesis translate_on
//-------------------------------------------------------------------
// InternSync
//-------------------------------------------------------------------
/* intern_sync: synchronize by monitoring the internal idle signal */
wire rc_is_idle;
assign rc_is_idle = (state_c == S_IDLE);
/* instantiate the reconfiguration add-on: intern_sync */
intern_sync sync_0(
.clk(clk),
.rstn(rstn),
//-- to/from core----
.rc_is_idle(rc_is_idle),
//-- to/from reconfiguration controller----
.rc_reqn(rc_reqn),
.rc_ackn(rc_ackn)
);
//-------------------------------------------------------------------
// Assertions & Coverage
//-------------------------------------------------------------------
// synthesis translate_off
property maximum_operation;
logic [31:0] d1,d2;
@(posedge clk) disable iff(~rstn)
// Property for maximum operation:
// 1. start of operation: ((state_n == S_IDLE) && c_prdy)
// 2. read 2 data and write out the larger one
((state_c == S_IDLE) && c_prdy) |->
##[1:$] (c_prdy && c_crdy,d1=c_data) ##[1:$] (c_prdy && c_crdy,d2=c_data)
##[1:$] (p_prdy && p_crdy && (p_data==(d1>d2?d1:d2)));
endproperty
assert_maximum_operation : assert property (maximum_operation);
covergroup cvg_maximum_oprand @(p_prdy & p_crdy);
range: coverpoint p_data {
bins gt = {[0:'1]} iff(data1>data2);
bins eq = {[0:'1]} iff(data1==data2);
bins lt = {[0:'1]} iff(data1<data2);
}
endgroup
cvg_maximum_oprand cvg_0 = new;
covergroup cvg_maximum_cfg_req @(posedge clk);
// When the request of reconfiguration is detected
// probe the fsm. Should test reconfiguration at each fsm state
cfg: coverpoint state_c iff (~rc_reqn) {
bins cfg[] = {S_Rd1,S_Rd2,S_Wr,S_ReTry,S_IDLE};
illegal_bins other = default;
}
endgroup
cvg_maximum_cfg_req cvg_1 = new;
assert_maximum_cfg_ack : assert property (@(posedge clk) disable iff(~rstn)
// Reconfiguration can only be acknowledged when IDLE
// by using the intern_sync, the maximum module can only be reconfigured
// at S_IDLE state
//
// The corner case is acknowledge and start computation
// at the same time, and "un-intended" computation should be isolated correctly
(~rc_ackn) |-> (state_c == S_IDLE)
);
cov_maximum_cfg_ack : cover property (@(posedge clk) $fell(rc_ackn) |-> ((state_c==S_IDLE) ##1 (state_c!=S_IDLE)));
// Reset property:
// when reset, internal signals should go to default values (to test just a few)
cov_maximum_reset_0 : cover property (@(posedge clk) (~rstn) |-> (($past(state_c) !== S_IDLE) ##0 (state_c === S_IDLE)));
cov_maximum_reset_1 : cover property (@(posedge clk) (~rstn) |-> (($past(data1) !== 'h0) ##0 (data1 === 'h0)));
cov_maximum_reset_2 : cover property (@(posedge clk) (~rstn) |-> (($past(data2) !== 'h0) ##0 (data2 === 'h0)));
// Corner case:
// drive ready or error at the last cycle of time out
cov_maximum_crdy : cover property (@(posedge clk) (tocnt == 4'hf) |-> c_crdy );
cov_maximum_cerr : cover property (@(posedge clk) (tocnt == 4'hf) |-> c_cerr );
// synthesis translate_on
endmodule
|
`define clk_PERIOD 30.0
module PATTERN(
clk,
rst_n,
in_valid,
in,
in_mode,
out_valid,
out
);
integer seed1=100;
output reg clk;
output reg rst_n;
output reg in_valid;
output reg in_mode;
output reg[15:0]in;
input[35:0]out;
input out_valid;
reg[35:0] gold1[2:0];
integer gold2[15:0];
reg mode;
integer i,j;
real CYCLE ;
reg[3:0] a0,a1,a2,a3,b0,b1,b2,b3,c0,c1,c2,c3,d0,d1,d2,d3;
reg [15:0] A[2:0];
reg [15:0] B[2:0];
reg signed [35:0] c_multi;
reg signed [35:0] n[2:0];
always@(*)begin
A[0]={a0,a1,a2,a3};
A[1]={b0,b1,b2,b3};
A[2]=16'd0;
B[0]={c0,c1,c2,c3};
B[1]={d0,d1,d2,d3};
B[2]=16'd0;
end
initial begin
CYCLE = `clk_PERIOD;
clk = 0;
end
always #(CYCLE/2.0) clk = ~clk;
integer total_latency,lat;
initial begin
rst_n = 0;
in = 'dx;
in_valid = 0;
in_mode = 'dx;
total_latency = 0;
lat=0;
rst_n = 1;
repeat(2)@(posedge clk);
rst_n = 0;
rest_signal_task;
repeat(1)@(posedge clk);
mode = 1;
input_task;
wait_out_valid;
check_ans;
mode = 1;
input_task;
wait_out_valid;
check_ans;
PASS;
$finish;
end
task rest_signal_task; begin
if(out_valid!==0||out!==0)begin
//fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" output signal should be 0 after initial rst_n at %t ",$time);
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(1)@(posedge clk);
$finish;
end
end
endtask
integer patnum;
integer num;
integer array1[31:0];
integer array2[100:0];
integer check;
task random_task; begin
a0 = $random(seed1)%16;
a1 = $random(seed1)%16;
a2 = $random(seed1)%16;
a3 = $random(seed1)%16;
b0 = $random(seed1)%16;
b1 = $random(seed1)%16;
b2 = $random(seed1)%16;
b3 = $random(seed1)%16;
c0 = $random(seed1)%16;
c1 = $random(seed1)%16;
c2 = $random(seed1)%16;
c3 = $random(seed1)%16;
d0 = $random(seed1)%16;
d1 = $random(seed1)%16;
d2 = $random(seed1)%16;
d3 = $random(seed1)%16;
end
endtask
task input_task;
begin
for(i=0;i<3;i=i+1) begin
gold1[i]=0;
n[i]=0;
end
for(i=0;i<16;i=i+1)
gold2[i]=0;
random_task;
repeat(1)@(negedge clk);
in_valid = 1;
in = {a0,a1,a2,a3};
in_mode = mode;
repeat(1)@(negedge clk);
in_mode = 'dx;
in = {b0,b1,b2,b3};
@(negedge clk);
in = {c0,c1,c2,c3};
repeat(1)@(negedge clk);
in = {d0,d1,d2,d3};
@(negedge clk);
in = 'dx;
in_valid = 0;
//repeat(1)@(negedge clk);
execution;
end endtask
task comp_multi;
input [15:0] a;
input [15:0] b;
output reg [35:0]out_comp;
reg signed [7:0] ar,ai;
reg signed [7:0] br,bi;
reg signed [17:0] outr,outi;
begin
ar=a[15:8];
ai=a[7:0];
br=b[15:8];
bi=b[7:0];
outr=ar*br-ai*bi;
outi=ar*bi+ai*br;
out_comp={outr,outi};
end endtask
task comp_add;
input [35:0] a;
input [35:0] b;
output reg [35:0]out_comp;
reg signed [17:0] ar,ai;
reg signed [17:0] br,bi;
reg signed [17:0] outr,outi;
begin
ar=a[35:18];
ai=a[17:0];
br=b[35:18];
bi=b[17:0];
outr=ar+br;
outi=ai+bi;
out_comp={outr,outi};
end endtask
task conjugate;
input [35:0] c;
output reg [35:0] c_conj;
reg signed [17:0] temp;
begin
temp=c[17:0];
temp=~temp+1;
c_conj={c[35:18],temp};
end
endtask
task wait_out_valid;begin
while(out_valid!=1)begin
lat = lat+1;
if(lat==100)begin
// fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" The execution latency are over %d cycles ",lat);
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(2)@(negedge clk);
$finish;
end
@(negedge clk);
end
total_latency = total_latency + lat;
end
endtask
task check_ans;begin
i = 0;
lat=0;
while(out_valid)begin
if(lat>2&&mode==0)begin
fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 0, outvalid is more than 3 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
if(lat>5&&mode==1)begin
fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 1, outvalid is more than 6 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
if (mode==0&&out!==gold1[i])begin
fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 0 PATTERN NO.%4d ",i);
$display (" Ans(value): %d, Your output : %d at %8t ",gold1[i],out,$time);
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
if (mode==1&&out!==gold2[2*i])begin
fail;
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 1 PATTERN NO.%4d ",i);
$display (" Ans(value): %d, Your output : %d at %8t ",gold2[2*i],out,$time);
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
repeat(9) @(negedge clk);
$finish;
end
i = i+1;
lat= lat+1;
@(negedge clk);
end
if(lat<3&&mode==0)begin
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 0 Outvalid is less than 3 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$finish;
end
if(lat<6&&mode==1)begin
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$display (" FAIL! ");
$display (" MODE = 1 Outvalid is less than 6 cycles ");
$display ("--------------------------------------------------------------------------------------------------------------------------------------------");
$finish;
end
end
endtask
task execution;begin
for (i=0;i<3;i=i+1)begin
for (j=0;j<=i;j=j+1)begin
comp_multi(A[i-j],B[j],c_multi);
comp_add(n[i],c_multi,n[i]);
end
end
for (i=0;i<3;i=i+1)begin
conjugate(n[i],gold1[i]);
end
/////////
gold2[a0] = gold2[a0]+1;
gold2[a1] = gold2[a1]+1;
gold2[a2] = gold2[a2]+1;
gold2[a3] = gold2[a3]+1;
gold2[b0] = gold2[b0]+1;
gold2[b1] = gold2[b1]+1;
gold2[b2] = gold2[b2]+1;
gold2[b3] = gold2[b3]+1;
gold2[c0] = gold2[c0]+1;
gold2[c1] = gold2[c1]+1;
gold2[c2] = gold2[c2]+1;
gold2[c3] = gold2[c3]+1;
gold2[d0] = gold2[d0]+1;
gold2[d1] = gold2[d1]+1;
gold2[d2] = gold2[d2]+1;
gold2[d3] = gold2[d3]+1;
end
endtask
task PASS;begin
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8OOOOOOO8@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O .o8@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8:. .o@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o :O@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ .o8@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@888888@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88888888OOO88@@@@@@@@@@ :@@@@@@@");
$display("@@@@@@@@@@@@8o:. .o8@@@@@@@@@@@@@@@@@@@88Oo:. .:ooo o@@@@@@");
$display("@@@@@@@@@@8 .8@@@@@@@@@@@@8O:. ..::::::ooo:. .8@@@@@");
$display("@@@@@@@O. 8@@@@@8O:. .:O88@@@@@@@@@@@@@@@@@@@@@@@88Oo. :8@@@@@");
$display("@@@@@@o :8@@8. .:o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@OO: o@@@@@@");
$display("@@@@@8 :o. .O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88@@8o. 8@@@@@@");
$display("@@@@: o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: :OO. o@@@@@8@");
$display("@@@o. :O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. OO: :8@@@@@@@@");
$display("@@8. O8@@@@@@@@@@O:. .oO@@@@@@@@@@@@@@@@@@@@@@@. o88 O@@@@@@@@@@@");
$display("@@O. :O@@@@@@@@@@: o@@@@@@@@@@@@@@@@@@@@@@. .88o. oO@@@@@@@@@@@@");
$display("@@O. :8@@@@@@@@@@8: .O@@@@@@@@@@@@@@@@@@@@@o .@@8O: o8@@@@@8@@@@@@");
$display("@@@: 8@@@@@@@@@@O. :8@@@@@@@@@@@@@@@@@@@@8o O@@@@. 8@@@@@@@@@8@");
$display("@@@@o :@@@@@@@@@@o :8@@@@@@@@@@@@@@@@@@@@@@o O@@@@O: .O@@@@@@@@@@");
$display("@@@@@@. .O@@@@@@@@@@8 O@@@@@@@@@@@@@@@@@@@@@@@@@O .O@@@@@@@@o :@@@@@@@@@");
$display("@@@@@@@O:. .O@@@@@@@@@@@@o .8@@@@@@@@@@@@888O8@@@@@@@@@o. .o8@@@@@@@@@@o o8@@@@@@@");
$display("@@@@@@@@@@8. o@@@@@@@@@@@@@: o@@@@@@@O:. :O@@@@@@@@Oo. .:8@@@@@@@@@@@@@8 @@@@@@@");
$display("@@@@@@@@@@@@@@@@: 8@@@@@@@@@@@@@8 :8@@@@8: .O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@");
$display("@@@@@@@@@@@@@@@@ :@@@@@@@@@@@@@@@O. 8@@@@@8: o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8@@@ @@@@@@");
$display("@@@@@@@@@@@@@@@O :@@@@@@@@@@@@@@@@@@@8O:....:O8@@@@@@@@@@@o O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8@@@@ @@@@@");
$display("@@@@@@@@@@@@@@8: :O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Oo. .o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ @@@@");
$display("@@@@@@@@@@@@@8: o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8 :@@@@@@@@@@@@@@@@@@@@@@@8Ooo\033[0;40;31m:::::\033[0;40;37moOO8@@8OOo o@@@");
$display("@@@@@@@@@@@@@O O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. .8@@8o:O@@@@@@@@@@@@@8O\033[0;40;31m:::::::::::::::\033[0;40;37mO@@@O :@@@");
$display("@@@@@@@@@@@@@O O@@@@@@@@@@@@@@@@@@88888@@@@@@@@@@@@@@@@@@O:oO8@8. .: o@@@@@@@@@@@@O\033[0;40;31m::::::::::::::::::\033[0;40;37mo8@O :8@@");
$display("@@@@@@@@@@@@@O O@@@@@@@@@@@@@\033[1;40;31mO\033[0;40;31m:::::::::::::\033[0;40;37mo8@@@@@@@@@@@@8. :@@@@@@@@@@8o\033[0;40;31m::::::::::::::::::::\033[0;40;37mo8@: .@@");
$display("@@@@@@@@@@@@O. .8@@@@@@@@@@8Oo\033[0;40;31m.:::::::::::::::\033[0;40;37moO@@@@@@@@@@8: .@@@@@@@@@@O\033[0;40;31m::::::::::::::::::::::\033[0;40;37mo8O @@");
$display("@@@@@@@@@@@@o O@@@@@@@@@@8o\033[0;40;31m::::::::::::::::::::\033[0;40;37mo8@@@@@@@@@O .@@@@@@@@@@O\033[0;40;31m::::::::::::::::::::::\033[0;40;37mo8O @@");
$display("@@@@@@@@@@@@O. :8@@@@@@@@o\033[0;40;31m::::::::::::::::::::::::\033[0;40;37m8@@@@@@@@@ :@@@@@@@@@@8o\033[0;40;31m:::::::::::::::::::::\033[0;40;37mO@o @@");
$display("@@@@@@@@@@@@8: :8@@@@@@@8\033[0;40;31m:::::::::::::::::::::::::\033[0;40;37m8@@@@@@@@@ O@@@@@@@@@@@O\033[0;40;31m::::::::::::::::::::\033[0;40;37mo8@: :@@");
$display("@@@@@@@@@@@@@O O@@@@@@8O\033[0;40;31m:::::::::::::::::::::::::\033[0;40;37mo8@@@@@@@@O .8@@@@@@@@@@@@@8o\033[0;40;31m::::::::::::::::\033[0;40;37mo8@@@ .O@@");
$display("@@@@@@@@@@@@@O O8@@@@@8O\033[0;40;31m:::::::::::::::::::::::::\033[0;40;37mo8@@@@@@@@@8: .O@@@@@@@@@@@@@@@@@O\033[0;40;31m::::::::::::::\033[0;40;37mo@@@@8 .8@@");
$display("@@@@@@@@@@@@@O O@@@@@@@O\033[0;40;31m::::::::::::::::::::::::.\033[0;40;37mO8@@@@8OOooo:. :@@@@@@@@@@@@@@@@@@@@8OOo\033[0;40;31m::::::\033[0;40;37mooO8@@@@@o :@@@");
$display("@@@@@@@@@@@@@8. o8@@@@@@@\033[0;40;31m:::::::::::::::::::::::::\033[0;40;37m8@8O. .:O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8o o@@@@");
$display("@@@@@@@@@@@@@8: .O@@@@@@@O\033[0;40;31m:::::::::::::::::::::::\033[0;40;37mo@O. .:oOOOo::. .:OO8@@@@@@@@@@@@@@@@@@@@@@@@O. :8@@@@");
$display("@@@@@@@@@@@@@@8. :8@@@@@@@8o\033[0;40;31m:::::::::::::::::::\033[0;40;37mO8@O 8@@@@@@@@@@@@@@@@@8O.. :oO8@@@@@@@@@@@@@@@8o. .8@@@@@");
$display("@@@@@@@@@@@@@@@O :8@@@@@@@@8O\033[0;40;31m:::::::::::::::\033[0;40;37mO8@@@: .@@@@@@@@@@@@@@@@@@@@@@88Oo:. .:O8@@@@@@@@@@@. O@@@@@@");
$display("@@@@@@@@@@@@@@@8 O@@@@@@@@@@8Oo\033[0;40;31m::::::::\033[0;40;37mooO8@@@@@O. O@@@@@@@@@@@@@@@@@@@@@@@@@@@@8:. .o@@@@@@@@@o O@@@@@@@");
$display("@@@@@@@@@@@@@@@@o 8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: :O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o. :O@@@8o. .o@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@: :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: ...:oO8@@@@@@@@@@@@@@@@@@@@@@@@@O: .O8. .O@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@O: :@@@@@@@@@@@@@@@@@@@@@@@@@@@O. \033[0;40;33m...\033[0;40;37m O@@@@@@@@@@@@@@@@@@@@@@@O .O8@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@: :O@@@@@@@@@@@@@@@@@@@@@@@@@O \033[0;40;33m:O888Ooo:..\033[0;40;37m :8@@@@@@@@@@@@@@@@@@@@O: :O@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@8o .O8@@@@@@@@@@@@@@@@@@@@@O: \033[0;40;33m.o8888888888O.\033[0;40;37m .O@@@@@@@@@@@OO888@8O:. :O@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@O o8@@@@@@@@@@@@@@@@@@@o \033[0;40;33m:88888888888o\033[0;40;37m o8@@@@@@@: o8@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@: .:88@@@@@@@@@@@@@8: \033[0;40;33mo8888O88888O.\033[0;40;37m .8@@@@@@@O \033[1;40;33m..\033[0;40;37m .::O@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@O. .:o \033[0;40;33m8888\033[0;40;37m@@@@\033[0;40;33m888o.\033[0;40;37m o8@@@@@8o \033[0;40;33mo88o.\033[0;40;37m @@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@o .OOo:. \033[0;40;33mO88\033[0;40;37m@@@@@\033[0;40;33m888o.\033[0;40;37m :8@@@@@o \033[0;40;33m:O88.\033[0;40;37m .@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@8o :@@@@@O: \033[0;40;33m.O8\033[0;40;37m@@@@\033[0;40;33m8888O:\033[0;40;37m .O88O: \033[0;40;33m.O88O\033[0;40;37m O@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@: \033[0;40;33m.o8\033[0;40;37m@@@@\033[0;40;33m\033[0;40;33m888888O:\033[0;40;37m \033[0;40;33m.888O:\033[0;40;37m o8@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@8o \033[0;40;33m.O\033[0;40;37m@@@@\033[0;40;33m\888888888Oo:...ooO8888: \033[0;40;37m:8@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8o \033[0;40;33mo8\033[0;40;37m@@@@\033[0;40;33m888888888888888888888O.\033[0;40;37m :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o. \033[0;40;33m.8\033[0;40;37m@@@@\033[0;40;33m888888888888888888888O:\033[0;40;37m o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O:. \033[0;40;33m.o8\033[0;40;37m@@@@@\033[0;40;33m88888888888888888888Oo\033[0;40;37m :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8OOo::::::. \033[0;40;33mo888\033[0;40;37m@@@@@\033[0;40;33m88888888888888888888o.\033[0;40;37m @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: \033[0;40;33mo888\033[0;40;37m@@@@@\033[0;40;33m88888888888888888888.\033[0;40;37m .@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: \033[0;40;33mo888\033[0;40;37m@@@@@\033[0;40;33m88888888888888888888O\033[0;40;37m .O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. \033[0;40;33mO8888\033[0;40;37m@@@\033[0;40;33m88888888888888888888O.\033[0;40;37m O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o \033[0;40;33m8888888888888888888888888888o\033[0;40;37m o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. \033[0;40;33m. ..:oOO8888888888888888888o.\033[0;40;37m .8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. \033[0;40;33m..:oO8888888888888O.\033[0;40;37m .O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8OO. \033[0;40;33m.oOO88O.\033[0;40;37m O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88:.. \033[0;40;33m...\033[0;40;37m 8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88Ooo:. @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8OoOO@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display ("----------------------------------------------------------------------------------------------------------------------");
$display (" Congratulations! ");
$display (" You have passed all patterns! ");
//$display (" Your execution cycles = %5d cycles ", total_latency);
//$display (" Your clock period = %.1f ns ", CYCLE);
//$display (" Your total latency = %.1f ns ", total_latency*CYCLE);
$display ("----------------------------------------------------------------------------------------------------------------------");
$finish;
end
endtask
task fail;begin
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8Oo::::ooOOO8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o: ..::.. .:o88@@@@@@@@@@@8OOoo:::..::oooOO8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. :8@@@@@@@@@@@@Oo.. ..:.:.. .:O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. .8@@@@@@@@@@@@@@@@@@@@@@88888888888@@@@@@@@@@@@@@@@@8. :O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@:. .@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. :o@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o 8@@@@@@@@@@@@@8@@@@@@@@8o::o8@@@@@8ooO88@@@@@@@@@@@@@@@@@@@@@@@@8:. .:ooO8@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o :@@@@@@@@@@O :@@@O .. :O@@@: :@@@@OoO8@@@@@@@@@@@@@@@@Oo... ..:o@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ :8@@@@@@@@@: .@@88@@@8: o@@o :@@@. 0@@@. O@@@ .O8@@@@@@@@@@@@@@@@@@8OOo. O8@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ o@@@@@@@@@@O. :8@8: o@@O. .@@8 000o .8@@O O8O: .@@o .O@@@@@@@@@@@@@@@@@@@o. .o@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. :8@@@@@@@@@@@@@@@: .o8: o@@o. .@@O :: .O@@@O. o0o. :@@O. :8@8::8@@@@@@@@@@@@@@@8O .:8@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ o8@@@@@@@@@@@OO@@8. o@8 '' .O@@o O@: :O@@: :: .8@@@O. .: .8@@@@@@@@@@@@@@@@@@O 8@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. .O@@@@@@@@@@O .8@@@@Oo::oO@@@@O 8@8: :@8 :@O. :O@@@@8: .o@@@@@@@@@@@@@@@@@@@@@@o :8@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: 8@@@@@@@@@@@@8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o:8@8: :@@@@: .O@@@@@@@@@@@@@@@@@@@@@@@@8: o@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@: .8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@OoO@@@O :8@@@@@@@@@@@@@@@@@@@@@@@@@@8o 8@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8. o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88@@@@@@@@@@@@@@@@@@@8::@@@@@88@@@@@@@@@@@@@@@@@@@@@@@ :8@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. .:8@@@@@@@@@@@@@@@@@@@88OOoo::....:O88@@@@@@@@@@@@@@@@@@@@8o .8@@@@@@@@@@@@@@@@@@@@@@: o@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o. ..:o8888888OO::. ....:o:.. oO@@@@@@@@@@@@@@@@8O..@@ooO@@@@@@@@@@@@@@@@@@O. :@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@Oo::. ..:OO@@@@@@@@@@@@@@@@O: .o@@@@@@@@@@@@@@@@@@@O 8@@@@@@@@@@@@@@@@@. .O@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8O .8@@@@@@@@@@@@@@@@@@@@@O O@@@@@@@@@@@@@. o8@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O .O@@@@@@@@@@@@@@@@@@8..8@@@@@@@@@@@@@. .O@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O: ..:O88@888@@@@@@@@@@@@@@@@@@@@@@@O O@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o. ..:oO@@@@@@@@@@@@@@@o @@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. .o@@8O::. o8@@@@@@@@@@@O 8@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o :O@@@@@@@o. :O8@@@@@@@@8 o8@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@88OO888@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8888OOOOO8@@8888@@@@@O. .@@@@@@@@@:. :@@@@@@@@@. .O@");
$display("@@@@@@@@@@@@@@@@@@@@8o: O8@@@@@@@@@@@@@@@@@@@8OO:. .:: :8@@@@@@@@@. .O@@@@@@@o. o@");
$display("@@@@@@@@@@@@@@@@@@. o8@@@@@@@@@@@O:. .::oOOO8Oo:..::::.. o@@@@@@@@@@8: 8@@@@@@o. o@");
$display("@@@@@@@@@@@@@@@@: .@@@@@Oo. .:OO@@@@@@@@@@@@@@@@@@@@@@@@@o. O@@@@@@@@@@@@ o8@@@@@O. o@");
$display("@@@@@@@@@@@@@@: o88. ..O88@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@888O. .8@@@@@@@@@@@@ o8@@@@@: .O@");
$display("@@@@@@@@@@@@O: :o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@: .8@@@@@@@@@@@8o 8@@@@@O O@@");
$display("@@@@@@@@@@@O. :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o. :8@@@@@@@@@@8. .O@@@@o. :@@@");
$display("@@@@@@@@@@@: :O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O: .o@@@@@@@@@8o .o@@@8:. .@@@@@");
$display("@@@@@@@@@@@. O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. .o8@@@@@@@@@@O :O@@8o: .O@@@@@@@");
$display("@@@@@@@@@@@. :O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O: o8@@@@@@@@8 oO@@@@@@@@@@");
$display("@@@@@@@@@@@: o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@. .@@@@@@@O. .:o8@@@@@@@@@@@@@");
$display("@@@@@@@@@@@8o 8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o :@@@@O o8@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@8. .O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@: .@@@8..:8@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@8: .o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@8O. 8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ :@@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@8o o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@o O@@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@O O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O :@@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@8 :@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@: 8@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@8o :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@:.. .:o@@@@@@@@@@@@@@@@@@8. O@@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@8o :8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O. .:@@@@@@@@@@@@@@@@@: :O@@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@O. o@@@@@@@@@@@@@@@@@@@@@@8OOO8@@@@@@@@@@@@@@@@@@@@@@@@@@@8. .@@@@@@@@@@@@@@@@. .O@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@o. .@@@@@@@@@@@@@@@@@@@8:. :8@@@@@@@@@@@@@@@@@@@@@@@@8. o8@@@@@@@@@@@@@o. .:@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@o. :@@@@@@@@@@@@@@@@@O .@@@@@@@@@@@@@@@@@@@@@@@@@: .8@@@@@@@@@@@@O. :@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@O. .@@@@@@@@@@@@@@@@: .8@@@@@@@@@@@@@@@@@@@@@@@@O: o@@@@@@@@@@@@O: .@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@O. .@@@@@@@@@@@@@@8: 8@@@@@@@@@@@@@@@@@@@@@@@@@@. o@@@@@@@@@@@@O: .@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@O. .@@@@@@@@@@@@@o. 8@@@@@@@@@@@@@@@@@@@@@@@@@@8o .8@@@@@@@@@@@@O. .@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@8: .@@@@@@@@@@@@@ :@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8:. O8@@@@@@@@@@@@@@o. :@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@o 8@@@@@@@@@@@@. :8@@@@@@@@@ :8@@@@@@@@@@@8OoooO@@@@@@@@@@@@@@@@@@. .o@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@88O: O@@@@@@@@@@@@O: .@@@@@@@@O .8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8 :8@@@@@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@O:. :O8@@@@@@@@@@8o :O@@@@@@@8: :@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8: :o@@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@o ..:8@@@@@@@@@8o:::.:O8@@@@@@@@@@@8. :@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O:. o@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@8o :@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@:. .o@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8 o8@@@@@@@@@@@@@@@");
$display("8OOOooooOOoo:. :OOOOOOOOOO8888OOOOOOOOOOOoo:ooOOOo: .OOOOOOOOOO888OOooOO888OOOOOooO8: .:OOOOOOOOOOO88@@");
$display(" . ");
$display("@@@@@@@@@@@@@@8o .8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8 :8@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@8O. o8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@8o .@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@::. :O@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@O.. .:8@@@@@@@@@@@@@@@@@@");
$display("@@@@@@@@@@@@@@@@@@@@@@@@@88O8@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@88@@@@@@@@@@@@@@@@@@@@@@@@@@");
end
endtask
endmodule
|
`timescale 1 ns / 1 ps
module hapara_axis_id_dispatcher_v1_0 #
(
// Users to add parameters here
parameter integer NUM_SLAVES = 1,
parameter integer DATA_WIDTH = 32
// User parameters ends
)
(
// Users to add ports here
input wire [NUM_SLAVES-1: 0] priority_sel,
// User ports ends
// Do not modify the ports beyond this line
// Ports of Axi Slave Bus Interface S00_AXIS
input wire s00_axis_aclk,
input wire s00_axis_aresetn,
output wire s00_axis_tready,
input wire [DATA_WIDTH-1 : 0] s00_axis_tdata,
input wire s00_axis_tlast,
input wire s00_axis_tvalid,
// Ports of Axi Master Bus Interface M00_AXIS
input wire m00_axis_aclk,
input wire m00_axis_aresetn,
output wire m00_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m00_axis_tdata,
output wire m00_axis_tlast,
input wire m00_axis_tready,
// Ports of Axi Master Bus Interface M01_AXIS
input wire m01_axis_aclk,
input wire m01_axis_aresetn,
output wire m01_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m01_axis_tdata,
output wire m01_axis_tlast,
input wire m01_axis_tready,
// Ports of Axi Master Bus Interface M02_AXIS
input wire m02_axis_aclk,
input wire m02_axis_aresetn,
output wire m02_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m02_axis_tdata,
output wire m02_axis_tlast,
input wire m02_axis_tready,
// Ports of Axi Master Bus Interface M03_AXIS
input wire m03_axis_aclk,
input wire m03_axis_aresetn,
output wire m03_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m03_axis_tdata,
output wire m03_axis_tlast,
input wire m03_axis_tready,
// Ports of Axi Master Bus Interface M04_AXIS
input wire m04_axis_aclk,
input wire m04_axis_aresetn,
output wire m04_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m04_axis_tdata,
output wire m04_axis_tlast,
input wire m04_axis_tready,
// Ports of Axi Master Bus Interface M05_AXIS
input wire m05_axis_aclk,
input wire m05_axis_aresetn,
output wire m05_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m05_axis_tdata,
output wire m05_axis_tlast,
input wire m05_axis_tready,
// Ports of Axi Master Bus Interface M06_AXIS
input wire m06_axis_aclk,
input wire m06_axis_aresetn,
output wire m06_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m06_axis_tdata,
output wire m06_axis_tlast,
input wire m06_axis_tready,
// Ports of Axi Master Bus Interface M07_AXIS
input wire m07_axis_aclk,
input wire m07_axis_aresetn,
output wire m07_axis_tvalid,
output wire [DATA_WIDTH-1 : 0] m07_axis_tdata,
output wire m07_axis_tlast,
input wire m07_axis_tready
);
localparam dispatch = 4'b0001;
localparam waitslave = 4'b0010;
localparam terminate = 4'b0100;
localparam waitdata = 4'b1000;
reg [3 : 0] curr_state;
reg [3 : 0] next_state;
// Logic for curr_state
always @(posedge s00_axis_aclk) begin
if (!s00_axis_aresetn) begin
// reset
curr_state <= dispatch;
end
else begin
curr_state <= next_state;
end
end
wire slaves_ready;
// Logic for next_state
always @(s00_axis_tdata or slaves_ready or curr_state) begin
case (curr_state)
dispatch:
if (s00_axis_tdata == {DATA_WIDTH{1'b1}}) begin
next_state = waitslave;
end
else begin
next_state = dispatch;
end
waitslave:
if (slaves_ready) begin
next_state = terminate;
end
else begin
next_state = waitslave;
end
terminate:
next_state = waitdata;
waitdata:
if (s00_axis_tdata != {DATA_WIDTH{1'b1}}) begin
next_state = dispatch;
end
else begin
next_state = waitdata;
end
default:
next_state = 3'bxxx;
endcase
end
assign m00_axis_tdata = s00_axis_tdata;
assign m00_axis_tlast = s00_axis_tlast;
assign m01_axis_tdata = s00_axis_tdata;
assign m01_axis_tlast = s00_axis_tlast;
assign m02_axis_tdata = s00_axis_tdata;
assign m02_axis_tlast = s00_axis_tlast;
assign m03_axis_tdata = s00_axis_tdata;
assign m03_axis_tlast = s00_axis_tlast;
assign m04_axis_tdata = s00_axis_tdata;
assign m04_axis_tlast = s00_axis_tlast;
assign m05_axis_tdata = s00_axis_tdata;
assign m05_axis_tlast = s00_axis_tlast;
assign m06_axis_tdata = s00_axis_tdata;
assign m06_axis_tlast = s00_axis_tlast;
assign m07_axis_tdata = s00_axis_tdata;
assign m07_axis_tlast = s00_axis_tlast;
// Add user logic here
generate if (NUM_SLAVES == 1)
begin: NUM_SLAVES_1
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
m00_axis_tready;
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[0]);
assign slaves_ready = m00_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 2)
begin: NUM_SLAVES_2
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[1]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 3)
begin: NUM_SLAVES_3
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
s00_axis_tvalid &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[2]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 4)
begin: NUM_SLAVES_4
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[3]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 5)
begin: NUM_SLAVES_5
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[4]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 6)
begin: NUM_SLAVES_6
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[5]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 7)
begin: NUM_SLAVES_7
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[6]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready;
end
endgenerate
generate if (NUM_SLAVES == 8)
begin: NUM_SLAVES_8
assign s00_axis_tready = (curr_state == dispatch || curr_state == terminate) &&
(m00_axis_tready ||
m01_axis_tready ||
m02_axis_tready ||
m03_axis_tready ||
m04_axis_tready ||
m05_axis_tready ||
m06_axis_tready ||
m07_axis_tready);
assign m00_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
~priority_sel[1] &&
priority_sel[0]);
assign m01_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
~priority_sel[2] &&
priority_sel[1]);
assign m02_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
~priority_sel[3] &&
priority_sel[2]);
assign m03_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
~priority_sel[4] &&
priority_sel[3]);
assign m04_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
~priority_sel[5] &&
priority_sel[4]);
assign m05_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
~priority_sel[6] &&
priority_sel[5]);
assign m06_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
~priority_sel[7] &&
priority_sel[6]);
assign m07_axis_tvalid = (curr_state == terminate) ||
(curr_state == dispatch &&
s00_axis_tdata != {DATA_WIDTH{1'b1}} &&
s00_axis_tvalid &&
priority_sel[7]);
assign slaves_ready = m00_axis_tready &
m01_axis_tready &
m02_axis_tready &
m03_axis_tready &
m04_axis_tready &
m05_axis_tready &
m06_axis_tready &
m07_axis_tready;
end
endgenerate
// User logic ends
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__A2111O_M_V
`define SKY130_FD_SC_LP__A2111O_M_V
/**
* a2111o: 2-input AND into first input of 4-input OR.
*
* X = ((A1 & A2) | B1 | C1 | D1)
*
* Verilog wrapper for a2111o with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__a2111o.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_m (
X ,
A1 ,
A2 ,
B1 ,
C1 ,
D1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input C1 ;
input D1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__a2111o_m (
X ,
A1,
A2,
B1,
C1,
D1
);
output X ;
input A1;
input A2;
input B1;
input C1;
input D1;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__a2111o base (
.X(X),
.A1(A1),
.A2(A2),
.B1(B1),
.C1(C1),
.D1(D1)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__A2111O_M_V
|
/*
* Chain 4 memory interface for VGA
* Copyright (C) 2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module vga_c4_iface (
// Wishbone common signals
input wb_clk_i,
input wb_rst_i,
// Wishbone slave interface
input [16:1] wbs_adr_i,
input [ 1:0] wbs_sel_i,
input wbs_we_i,
input [15:0] wbs_dat_i,
output [15:0] wbs_dat_o,
input wbs_stb_i,
output wbs_ack_o,
// Wishbone master to SRAM
output [17:1] wbm_adr_o,
output [ 1:0] wbm_sel_o,
output wbm_we_o,
output [15:0] wbm_dat_o,
input [15:0] wbm_dat_i,
output reg wbm_stb_o,
input wbm_ack_i
);
// Registers and nets
reg plane_low;
reg [7:0] dat_low;
wire cont;
// Continuous assignments
assign wbs_ack_o = (plane_low & wbm_ack_i);
assign wbm_adr_o = { 1'b0, wbs_adr_i[15:2], wbs_adr_i[1], plane_low };
assign wbs_dat_o = { wbm_dat_i[7:0], dat_low };
assign wbm_sel_o = 2'b01;
assign wbm_dat_o = { 8'h0, plane_low ? wbs_dat_i[15:8] : wbs_dat_i[7:0] };
assign wbm_we_o = wbs_we_i & ((!plane_low & wbs_sel_i[0])
| (plane_low & wbs_sel_i[1]));
assign cont = wbm_ack_i && wbs_stb_i;
// Behaviour
// wbm_stb_o
always @(posedge wb_clk_i)
wbm_stb_o <= wb_rst_i ? 1'b0 : (wbm_stb_o ? ~wbs_ack_o : wbs_stb_i);
// plane_low
always @(posedge wb_clk_i)
plane_low <= wb_rst_i ? 1'b0 : (cont ? !plane_low : plane_low);
// dat_low
always @(posedge wb_clk_i)
dat_low <= wb_rst_i ? 8'h0
: ((wbm_ack_i && wbm_stb_o && !plane_low) ? wbm_dat_i[7:0] : dat_low);
endmodule
|
// Accellera Standard V2.5 Open Verification Library (OVL).
// Accellera Copyright (c) 2005-2010. All rights reserved.
parameter UNCHANGE_START = 1'b0;
parameter UNCHANGE_CHECK = 1'b1;
reg [width-1:0] r_test_expr;
reg r_state;
integer i;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
wire valid_start_event;
wire valid_test_expr;
assign valid_start_event = ~(start_event^start_event);
assign valid_test_expr = ~((^test_expr)^(^test_expr));
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_SYNTHESIS
`else
initial begin
r_state=UNCHANGE_START;
end
`endif
`ifdef OVL_SHARED_CODE
always @(posedge clk) begin
if (`OVL_RESET_SIGNAL != 1'b0) begin // active low reset
case (r_state)
UNCHANGE_START: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
if (start_event == 1'b1) begin
r_state <= UNCHANGE_CHECK;
r_test_expr <= test_expr;
i <= num_cks;
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_open covered");
end
end
`endif // OVL_COVER_ON
end
end
UNCHANGE_CHECK: begin
`ifdef OVL_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_IMPLICIT_XCHECK_OFF
//Do nothing
`else
`ifdef OVL_ASSERT_ON
// Do the x/z checking
if (action_on_new_start != `OVL_IGNORE_NEW_START)
begin
if (valid_start_event == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"start_event contains X or Z");
end
end
if (valid_test_expr == 1'b1)
begin
// Do nothing
end
else
begin
ovl_error_t(`OVL_FIRE_XCHECK,"test_expr contains X or Z");
end
`endif // OVL_ASSERT_ON
`endif // OVL_IMPLICIT_XCHECK_OFF
`endif // OVL_XCHECK_OFF
// Count clock ticks
if (start_event == 1'b1) begin
if (action_on_new_start == `OVL_IGNORE_NEW_START && i > 0)
i <= i-1;
else if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
i <= num_cks;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_CORNER_ON) begin //corner coverage
if (action_on_new_start == `OVL_RESET_ON_NEW_START) begin
ovl_cover_t("window_resets covered");
end
end
end
`endif // OVL_COVER_ON
end
else if (action_on_new_start == `OVL_ERROR_ON_NEW_START) begin
i <= i-1;
`ifdef OVL_ASSERT_ON
ovl_error_t(`OVL_FIRE_2STATE,"Illegal start event which has reoccured before completion of current window");
`endif // OVL_ASSERT_ON
end
end
else if (i > 0) begin
i <= i-1;
end
// go to start state on last check
if (i == 1 && !(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
r_state <= UNCHANGE_START;
`ifdef OVL_COVER_ON
if (coverage_level != `OVL_COVER_NONE) begin
if (OVL_COVER_BASIC_ON) begin //basic coverage
ovl_cover_t("window_close covered");
end
end
`endif // OVL_COVER_ON
end
// Check that the property is true
`ifdef OVL_ASSERT_ON
if ((r_test_expr != test_expr) &&
!(start_event == 1'b1 &&
action_on_new_start == `OVL_RESET_ON_NEW_START)) begin
ovl_error_t(`OVL_FIRE_2STATE,"Test expression changed value within num_cks from the start event asserted");
end
`endif // OVL_ASSERT_ON
r_test_expr <= test_expr;
end
endcase
end
else begin
r_state<=UNCHANGE_START;
i <= 0;
`ifdef OVL_INIT_REG
r_test_expr <= {width{1'b0}};
`endif
end
end // always
`endif // OVL_SHARED_CODE
|
/*
Copyright 2015, Google Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
module ftl_top (
input wire clk_50,
input wire reset_n,
output wire [9:0] dbg_phy_num_valid_blocks,
output wire dbg_phy_rebuilt_badblock,
output wire dbg_phy_remapped_runtime,
output wire err_phy_out_of_extras,
// slave wishbone interface (from SDHC)
input wire wbs_clk_i,
input wire [31:0] wbs_adr_i,
output wire [31:0] wbs_dat_o,
input wire [31:0] wbs_dat_i,
input wire [3:0] wbs_sel_i,
input wire wbs_cyc_i,
input wire wbs_stb_i,
input wire wbs_we_i,
output wire wbs_ack_o,
// master wishbone interface (to NANDC)
output wire wbm_clk_o,
output wire [2:0] wbm_cti_o, // type - cycle type identifier
output wire [1:0] wbm_bte_o, // exten - burst type extension
output wire [31:0] wbm_adr_o,
input wire [31:0] wbm_dat_i,
output wire [31:0] wbm_dat_o,
output wire [3:0] wbm_sel_o,
output wire wbm_cyc_o,
output wire wbm_stb_o,
output wire wbm_we_o,
input wire wbm_ack_i
);
wire reset_s;
synch_3 a(reset_n, reset_s, clk_50);
wire physical_init_done;
wire op_page_do;
wire [2:0] op_page_cmd;
wire [15:0] op_page_num;
wire [15:0] op_page_bram;
wire [41:0] op_page_spare_wr;
wire [41:0] op_page_spare_rd;
wire op_page_status;
wire op_page_ack;
wire op_page_done;
wire logical_init_done;
wire wb_read;
wire wb_write;
wire [9:0] wb_block;
wire wb_ack;
wire wb_done;
wire bram_wbs_clk;
wire [15:0] bram_wbs_addr;
wire bram_wbs_wren;
wire [31:0] bram_wbs_data;
wire [31:0] bram_wbs_q;
wire bram_physical_req;
wire bram_physical_ack;
wire [15:0] bram_physical_addr;
wire bram_physical_wren;
wire [31:0] bram_physical_data;
wire [31:0] bram_physical_q;
ftl_wbs ifw (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
// slave wishbone interface (from SDHC)
.wbs_clk_i ( wbs_clk_i ),
.wbs_adr_i ( wbs_adr_i ),
.wbs_dat_o ( wbs_dat_o ),
.wbs_dat_i ( wbs_dat_i ),
.wbs_sel_i ( wbs_sel_i ),
.wbs_cyc_i ( wbs_cyc_i ),
.wbs_stb_i ( wbs_stb_i ),
.wbs_we_i ( wbs_we_i ),
.wbs_ack_o ( wbs_ack_o ),
// port to cached block ram
.bram_wbs_clk ( bram_wbs_clk ),
.bram_wbs_addr ( bram_wbs_addr ),
.bram_wbs_wren ( bram_wbs_wren ),
.bram_wbs_data ( bram_wbs_data ),
.bram_wbs_q ( bram_wbs_q ),
.logical_init_done ( logical_init_done ),
.wb_read ( wb_read ),
.wb_write ( wb_write ),
.wb_block ( wb_block ),
.wb_ack ( wb_ack ),
.wb_done ( wb_done )
);
ftl_logical ilog (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.physical_init_done ( physical_init_done ),
.init_done ( logical_init_done ),
.wb_read ( wb_read ),
.wb_write ( wb_write ),
.wb_block ( wb_block ),
.wb_ack ( wb_ack ),
.wb_done ( wb_done ),
.op_page_do ( op_page_do ),
.op_page_cmd ( op_page_cmd ),
.op_page_num ( op_page_num ),
.op_page_bram ( op_page_bram ),
.op_page_spare_wr ( op_page_spare_wr ),
.op_page_spare_rd ( op_page_spare_rd ),
.op_page_status ( op_page_status ),
.op_page_ack ( op_page_ack ),
.op_page_done ( op_page_done )
);
ftl_buf ibuf (
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.bram_wbs_clk ( bram_wbs_clk ),
.bram_wbs_addr ( bram_wbs_addr ),
.bram_wbs_wren ( bram_wbs_wren ),
.bram_wbs_data ( bram_wbs_data ),
.bram_wbs_q ( bram_wbs_q ),
.bram_physical_addr ( bram_physical_addr ),
.bram_physical_wren ( bram_physical_wren ),
.bram_physical_data ( bram_physical_data ),
.bram_physical_q ( bram_physical_q )
);
ftl_physical iphy(
.clk_50 ( clk_50 ),
.reset_n ( reset_s ),
.init_done ( physical_init_done ),
.dbg_num_valid_blocks ( dbg_phy_num_valid_blocks ),
.dbg_rebuilt_badblock ( dbg_phy_rebuilt_badblock ),
.dbg_remapped_runtime ( dbg_phy_remapped_runtime ),
.err_out_of_extras ( err_phy_out_of_extras ),
.bram_page_addr ( bram_physical_addr ),
.bram_page_wren ( bram_physical_wren ),
.bram_page_data ( bram_physical_data ),
.bram_page_q ( bram_physical_q ),
.op_page_do ( op_page_do ),
.op_page_cmd ( op_page_cmd ),
.op_page_num ( op_page_num ),
.op_page_bram ( op_page_bram ),
.op_page_spare_wr ( op_page_spare_wr ),
.op_page_spare_rd ( op_page_spare_rd ),
.op_page_status ( op_page_status ),
.op_page_ack ( op_page_ack ),
.op_page_done ( op_page_done ),
.wbm_clk_o ( wbm_clk_o ),
.wbm_cti_o ( wbm_cti_o ),
.wbm_bte_o ( wbm_bte_o ),
.wbm_adr_o ( wbm_adr_o ),
.wbm_dat_i ( wbm_dat_i ),
.wbm_dat_o ( wbm_dat_o ),
.wbm_sel_o ( wbm_sel_o ),
.wbm_cyc_o ( wbm_cyc_o ),
.wbm_stb_o ( wbm_stb_o ),
.wbm_we_o ( wbm_we_o ),
.wbm_ack_i ( wbm_ack_i )
);
/*
(* mark_debug = "true" *) reg wb_read_reg;
(* mark_debug = "true" *) reg wb_write_reg;
(* mark_debug = "true" *) reg [9:0] wb_block_reg;
(* mark_debug = "true" *) reg wb_ack_reg;
(* mark_debug = "true" *) reg wb_done_reg;
(* mark_debug = "true" *) reg logical_init_done_reg;
(* mark_debug = "true" *) reg physical_init_done_reg;
always @(posedge clk_50) begin
wb_read_reg <= wb_read;
wb_write_reg <= wb_write;
wb_block_reg <= wb_block;
wb_ack_reg <= wb_ack;
wb_done_reg <= wb_done;
logical_init_done_reg <= logical_init_done;
physical_init_done_reg <= physical_init_done;
end
ila_0 ila_0 (
.clk(clk_50),
.probe0({
physical_init_done_reg,
logical_init_done_reg,
wb_done_reg,
wb_ack_reg,
wb_block_reg,
wb_write_reg,
wb_read_reg
})
);
*/
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2011 by Jeremy Bennett.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
wire [19:10] bitout;
wire [29:24] short_bitout;
wire [7:0] allbits;
wire [15:0] twobits;
sub
i_sub1 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14])),
i_sub2 [3:0] (.allbits (allbits),
.twobits (twobits[7:0]),
.bitout (bitout[13:10]));
sub
i_sub3 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (bitout[17:14]));
sub
i_sub4 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout (short_bitout[27:24]));
sub
i_sub5 [7:0] (.allbits (allbits),
.twobits (twobits),
.bitout (bitout[17:10]));
sub
i_sub6 [7:4] (.allbits (allbits),
.twobits (twobits[15:8]),
.bitout ({bitout[18+:2],short_bitout[28+:2]}));
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Signals under test
assign allbits = crc[7:0];
assign twobits = crc[15:0];
wire [63:0] result = {48'h0, short_bitout, bitout};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'ha1da9ff8082a4ff6
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule // t
module sub
( input wire [7:0] allbits,
input wire [1:0] twobits,
output wire bitout);
assign bitout = (^ twobits) ^ (^ allbits);
endmodule // sub
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_sel #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire S,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] V,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 1;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] v_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign v_local = {V, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign v_local = V;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (bit_cnt = 0; bit_cnt < C_NUM_LUT ; bit_cnt = bit_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[bit_cnt] = ( ( a_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b0 ) ) |
( ( b_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ==
v_local[bit_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) & ( S == 1'b1 ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[bit_cnt+1]),
.CIN (carry_local[bit_cnt]),
.S (sel[bit_cnt])
);
end // end for bit_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
module top (
input CLK,
input RX,
output TX,
output reg LED1,
output reg LED2,
output reg LED3,
output reg LED4,
output reg LED5
);
parameter integer BAUD_RATE = 9600;
parameter integer CLOCK_FREQ_HZ = 12000000;
localparam integer HALF_PERIOD = CLOCK_FREQ_HZ / (2 * BAUD_RATE);
reg [7:0] buffer;
reg buffer_valid;
reg [$clog2(3*HALF_PERIOD):0] cycle_cnt;
reg [3:0] bit_cnt = 0;
reg recv = 0;
initial begin
LED1 = 0;
LED2 = 0;
LED3 = 0;
LED4 = 0;
LED5 = 0;
end
always @(posedge CLK) begin
buffer_valid <= 0;
if (!recv) begin
if (!RX) begin
cycle_cnt <= HALF_PERIOD;
bit_cnt <= 0;
recv <= 1;
end
end else begin
if (cycle_cnt == 2*HALF_PERIOD) begin
cycle_cnt <= 0;
bit_cnt <= bit_cnt + 1;
if (bit_cnt == 9) begin
buffer_valid <= 1;
recv <= 0;
end else begin
buffer <= {RX, buffer[7:1]};
end
end else begin
cycle_cnt <= cycle_cnt + 1;
end
end
end
always @(posedge CLK) begin
if (buffer_valid) begin
if (buffer == "1") LED1 <= !LED1;
if (buffer == "2") LED2 <= !LED2;
if (buffer == "3") LED3 <= !LED3;
if (buffer == "4") LED4 <= !LED4;
if (buffer == "5") LED5 <= !LED5;
end
end
assign TX = RX;
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
// Date : Wed Sep 20 21:08:02 2017
// Host : EffulgentTome running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim
// c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/my_lab_1/my_lab_1.srcs/sources_1/bd/zqynq_lab_1_design/ip/zqynq_lab_1_design_axi_timer_0_0/zqynq_lab_1_design_axi_timer_0_0_sim_netlist.v
// Design : zqynq_lab_1_design_axi_timer_0_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "zqynq_lab_1_design_axi_timer_0_0,axi_timer,{}" *) (* downgradeipidentifiedwarnings = "yes" *) (* x_core_info = "axi_timer,Vivado 2017.2" *)
(* NotValidForBitStream *)
module zqynq_lab_1_design_axi_timer_0_0
(capturetrig0,
capturetrig1,
generateout0,
generateout1,
pwm0,
interrupt,
freeze,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready);
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
(* x_interface_info = "xilinx.com:signal:interrupt:1.0 INTERRUPT INTERRUPT" *) output interrupt;
input freeze;
(* x_interface_info = "xilinx.com:signal:clock:1.0 S_AXI_ACLK CLK" *) input s_axi_aclk;
(* x_interface_info = "xilinx.com:signal:reset:1.0 S_AXI_RST RST" *) input s_axi_aresetn;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [4:0]s_axi_awaddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [4:0]s_axi_araddr;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* x_interface_info = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) input s_axi_rready;
wire capturetrig0;
wire capturetrig1;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire pwm0;
wire s_axi_aclk;
wire [4:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [4:0]s_axi_awaddr;
wire s_axi_awready;
wire s_axi_awvalid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
(* C_COUNT_WIDTH = "32" *)
(* C_FAMILY = "zynq" *)
(* C_GEN0_ASSERT = "1'b1" *)
(* C_GEN1_ASSERT = "1'b1" *)
(* C_ONE_TIMER_ONLY = "0" *)
(* C_S_AXI_ADDR_WIDTH = "5" *)
(* C_S_AXI_DATA_WIDTH = "32" *)
(* C_TRIG0_ASSERT = "1'b1" *)
(* C_TRIG1_ASSERT = "1'b1" *)
(* downgradeipidentifiedwarnings = "yes" *)
zqynq_lab_1_design_axi_timer_0_0_axi_timer U0
(.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.pwm0(pwm0),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awready(s_axi_awready),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* ORIG_REF_NAME = "address_decoder" *)
module zqynq_lab_1_design_axi_timer_0_0_address_decoder
(\LOAD_REG_GEN[31].LOAD_REG_I ,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
pair0_Select,
s_axi_wready,
s_axi_arready,
D,
\s_axi_rdata_i_reg[11] ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_1 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_2,
s_axi_bvalid_i_reg,
\TCSR0_GENERATE[23].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[0]_0 ,
READ_DONE0_I,
READ_DONE1_I,
Q,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
state1__2,
s_axi_arvalid_0,
\state_reg[1] ,
s_axi_wdata,
s_axi_arvalid,
is_write_reg,
is_read,
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ,
s_axi_rready,
s_axi_rvalid_i_reg_3,
s_axi_bready,
s_axi_bvalid_i_reg_0,
bus2ip_rnw_i,
D_2,
read_done1,
\bus2ip_addr_i_reg[4] );
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output [1:0]D;
output \s_axi_rdata_i_reg[11] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output s_axi_rvalid_i_reg_2;
output s_axi_bvalid_i_reg;
output \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[0]_0 ;
output READ_DONE0_I;
output READ_DONE1_I;
input Q;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input state1__2;
input s_axi_arvalid_0;
input [1:0]\state_reg[1] ;
input [31:0]s_axi_wdata;
input s_axi_arvalid;
input is_write_reg;
input is_read;
input [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ;
input s_axi_rready;
input s_axi_rvalid_i_reg_3;
input s_axi_bready;
input s_axi_bvalid_i_reg_0;
input bus2ip_rnw_i;
input D_2;
input read_done1;
input [2:0]\bus2ip_addr_i_reg[4] ;
wire Bus_RNW_reg_i_1_n_0;
wire [1:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ;
wire [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] ;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire Q;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire bus2ip_rnw_i;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire ce_expnd_i_0;
wire ce_expnd_i_1;
wire ce_expnd_i_2;
wire ce_expnd_i_3;
wire ce_expnd_i_5;
wire ce_expnd_i_6;
wire ce_expnd_i_7;
wire cs_ce_clr;
wire eqOp__4;
wire is_read;
wire is_write_reg;
wire pair0_Select;
wire [87:0]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arready_INST_0_i_4_n_0;
wire s_axi_arvalid;
wire s_axi_arvalid_0;
wire s_axi_bready;
wire s_axi_bvalid_i_reg;
wire s_axi_bvalid_i_reg_0;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire s_axi_rvalid_i_reg_2;
wire s_axi_rvalid_i_reg_3;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wready_INST_0_i_1_n_0;
wire s_axi_wready_INST_0_i_2_n_0;
wire state1__2;
wire [1:0]\state_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hB8))
Bus_RNW_reg_i_1
(.I0(bus2ip_rnw_i),
.I1(Q),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(Bus_RNW_reg_i_1_n_0));
FDRE Bus_RNW_reg_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Bus_RNW_reg_i_1_n_0),
.Q(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.R(1'b0));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[84]),
.O(\s_axi_rdata_i_reg[31] ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[0] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[74]),
.O(\s_axi_rdata_i_reg[21] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[73]),
.O(\s_axi_rdata_i_reg[20] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[72]),
.O(\s_axi_rdata_i_reg[19] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[71]),
.O(\s_axi_rdata_i_reg[18] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[70]),
.O(\s_axi_rdata_i_reg[17] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[69]),
.O(\s_axi_rdata_i_reg[16] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[68]),
.O(\s_axi_rdata_i_reg[15] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[67]),
.O(\s_axi_rdata_i_reg[14] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[66]),
.O(\s_axi_rdata_i_reg[13] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[65]),
.O(\s_axi_rdata_i_reg[12] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[83]),
.O(\s_axi_rdata_i_reg[30] ));
LUT5 #(
.INIT(32'h0777FFFF))
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(read_Mux_In[64]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[87]),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h8))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\s_axi_rdata_i_reg[10] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[82]),
.O(\s_axi_rdata_i_reg[29] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[81]),
.O(\s_axi_rdata_i_reg[28] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[80]),
.O(\s_axi_rdata_i_reg[27] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[79]),
.O(\s_axi_rdata_i_reg[26] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[78]),
.O(\s_axi_rdata_i_reg[25] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[77]),
.O(\s_axi_rdata_i_reg[24] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[76]),
.O(\s_axi_rdata_i_reg[23] ));
LUT3 #(
.INIT(8'h7F))
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(read_Mux_In[75]),
.O(\s_axi_rdata_i_reg[22] ));
FDRE \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_7),
.Q(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.R(cs_ce_clr));
LUT4 #(
.INIT(16'h1000))
\GEN_BKEND_CE_REGISTERS[1].ce_out_i[1]_i_1
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [1]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_6));
FDRE \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_6),
.Q(\LOAD_REG_GEN[31].LOAD_REG_I ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_5),
.Q(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_3),
.Q(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_2),
.Q(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.R(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_1),
.Q(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.R(cs_ce_clr));
LUT3 #(
.INIT(8'hEF))
\GEN_BKEND_CE_REGISTERS[7].ce_out_i[7]_i_1
(.I0(s_axi_wready),
.I1(s_axi_arready),
.I2(s_axi_aresetn),
.O(cs_ce_clr));
FDRE \GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg[7]
(.C(s_axi_aclk),
.CE(Q),
.D(ce_expnd_i_0),
.Q(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.R(cs_ce_clr));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[0].LOAD_REG_I_i_2
(.I0(s_axi_wdata[31]),
.I1(read_Mux_In[31]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(D_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[0].LOAD_REG_I_i_2__0
(.I0(s_axi_wdata[31]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[63]),
.O(D_1));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT2 #(
.INIT(4'h2))
\LOAD_REG_GEN[0].LOAD_REG_I_i_7
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce__0));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[10].LOAD_REG_I_i_1
(.I0(s_axi_wdata[21]),
.I1(read_Mux_In[21]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[10].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[10].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[21]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[53]),
.O(\LOAD_REG_GEN[10].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[11].LOAD_REG_I_i_1
(.I0(s_axi_wdata[20]),
.I1(read_Mux_In[20]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[11].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[11].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[20]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[52]),
.O(\LOAD_REG_GEN[11].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[12].LOAD_REG_I_i_1
(.I0(s_axi_wdata[19]),
.I1(read_Mux_In[19]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[12].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[12].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[19]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[51]),
.O(\LOAD_REG_GEN[12].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[13].LOAD_REG_I_i_1
(.I0(s_axi_wdata[18]),
.I1(read_Mux_In[18]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[13].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[13].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[18]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[50]),
.O(\LOAD_REG_GEN[13].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[14].LOAD_REG_I_i_1
(.I0(s_axi_wdata[17]),
.I1(read_Mux_In[17]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[14].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[14].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[17]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[49]),
.O(\LOAD_REG_GEN[14].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[15].LOAD_REG_I_i_1
(.I0(s_axi_wdata[16]),
.I1(read_Mux_In[16]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[15].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[15].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[16]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[48]),
.O(\LOAD_REG_GEN[15].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[16].LOAD_REG_I_i_1
(.I0(s_axi_wdata[15]),
.I1(read_Mux_In[15]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[16].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[16].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[15]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[47]),
.O(\LOAD_REG_GEN[16].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[17].LOAD_REG_I_i_1
(.I0(s_axi_wdata[14]),
.I1(read_Mux_In[14]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[17].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[17].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[14]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[46]),
.O(\LOAD_REG_GEN[17].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[18].LOAD_REG_I_i_1
(.I0(s_axi_wdata[13]),
.I1(read_Mux_In[13]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[18].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[18].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[13]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[45]),
.O(\LOAD_REG_GEN[18].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[19].LOAD_REG_I_i_1
(.I0(s_axi_wdata[12]),
.I1(read_Mux_In[12]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[19].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[19].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[12]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[44]),
.O(\LOAD_REG_GEN[19].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[1].LOAD_REG_I_i_1
(.I0(s_axi_wdata[30]),
.I1(read_Mux_In[30]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[1].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[1].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[30]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[62]),
.O(\LOAD_REG_GEN[1].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[20].LOAD_REG_I_i_1
(.I0(s_axi_wdata[11]),
.I1(read_Mux_In[11]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[20].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[20].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[11]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[43]),
.O(\LOAD_REG_GEN[20].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[21].LOAD_REG_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[10]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[21].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[21].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[10]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[42]),
.O(\LOAD_REG_GEN[21].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[22].LOAD_REG_I_i_1
(.I0(s_axi_wdata[9]),
.I1(read_Mux_In[9]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[22].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[22].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[9]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[41]),
.O(\LOAD_REG_GEN[22].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[23].LOAD_REG_I_i_1
(.I0(s_axi_wdata[8]),
.I1(read_Mux_In[8]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[23].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[23].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[8]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[40]),
.O(\LOAD_REG_GEN[23].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[24].LOAD_REG_I_i_1
(.I0(s_axi_wdata[7]),
.I1(read_Mux_In[7]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[24].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[24].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[7]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[39]),
.O(\LOAD_REG_GEN[24].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[25].LOAD_REG_I_i_1
(.I0(s_axi_wdata[6]),
.I1(read_Mux_In[6]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[25].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[25].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[6]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[38]),
.O(\LOAD_REG_GEN[25].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[26].LOAD_REG_I_i_1
(.I0(s_axi_wdata[5]),
.I1(read_Mux_In[5]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[26].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[26].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[5]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[37]),
.O(\LOAD_REG_GEN[26].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[27].LOAD_REG_I_i_1
(.I0(s_axi_wdata[4]),
.I1(read_Mux_In[4]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[27].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[27].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[4]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[36]),
.O(\LOAD_REG_GEN[27].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[28].LOAD_REG_I_i_1
(.I0(s_axi_wdata[3]),
.I1(read_Mux_In[3]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[28].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[28].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[3]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[35]),
.O(\LOAD_REG_GEN[28].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[29].LOAD_REG_I_i_1
(.I0(s_axi_wdata[2]),
.I1(read_Mux_In[2]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[29].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[29].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[2]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[34]),
.O(\LOAD_REG_GEN[29].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[2].LOAD_REG_I_i_1
(.I0(s_axi_wdata[29]),
.I1(read_Mux_In[29]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[2].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[2].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[29]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[61]),
.O(\LOAD_REG_GEN[2].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[30].LOAD_REG_I_i_1
(.I0(s_axi_wdata[1]),
.I1(read_Mux_In[1]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[30].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[30].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[1]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[33]),
.O(\LOAD_REG_GEN[30].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[31].LOAD_REG_I_i_1
(.I0(s_axi_wdata[0]),
.I1(read_Mux_In[0]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[31].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[31].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[0]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[32]),
.O(\LOAD_REG_GEN[31].LOAD_REG_I_1 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[3].LOAD_REG_I_i_1
(.I0(s_axi_wdata[28]),
.I1(read_Mux_In[28]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[3].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[3].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[28]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[60]),
.O(\LOAD_REG_GEN[3].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[4].LOAD_REG_I_i_1
(.I0(s_axi_wdata[27]),
.I1(read_Mux_In[27]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[4].LOAD_REG_I ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[4].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[27]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[59]),
.O(\LOAD_REG_GEN[4].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[5].LOAD_REG_I_i_1
(.I0(s_axi_wdata[26]),
.I1(read_Mux_In[26]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[5].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[5].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[26]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[58]),
.O(\LOAD_REG_GEN[5].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[6].LOAD_REG_I_i_1
(.I0(s_axi_wdata[25]),
.I1(read_Mux_In[25]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[6].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[6].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[25]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[57]),
.O(\LOAD_REG_GEN[6].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[7].LOAD_REG_I_i_1
(.I0(s_axi_wdata[24]),
.I1(read_Mux_In[24]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[7].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[7].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[24]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[56]),
.O(\LOAD_REG_GEN[7].LOAD_REG_I_0 ));
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[8].LOAD_REG_I_i_1
(.I0(s_axi_wdata[23]),
.I1(read_Mux_In[23]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[8].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[8].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[23]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[55]),
.O(\LOAD_REG_GEN[8].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hCCAC))
\LOAD_REG_GEN[9].LOAD_REG_I_i_1
(.I0(s_axi_wdata[22]),
.I1(read_Mux_In[22]),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(\LOAD_REG_GEN[9].LOAD_REG_I ));
LUT4 #(
.INIT(16'hFB08))
\LOAD_REG_GEN[9].LOAD_REG_I_i_1__0
(.I0(s_axi_wdata[22]),
.I1(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(read_Mux_In[54]),
.O(\LOAD_REG_GEN[9].LOAD_REG_I_0 ));
zqynq_lab_1_design_axi_timer_0_0_pselect_f \MEM_DECODE_GEN[0].PER_CE_GEN[0].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_7(ce_expnd_i_7));
zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1 \MEM_DECODE_GEN[0].PER_CE_GEN[2].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_5(ce_expnd_i_5));
zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3 \MEM_DECODE_GEN[0].PER_CE_GEN[4].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_3(ce_expnd_i_3));
zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4 \MEM_DECODE_GEN[0].PER_CE_GEN[5].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_2(ce_expnd_i_2));
zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5 \MEM_DECODE_GEN[0].PER_CE_GEN[6].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_1(ce_expnd_i_1));
zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6 \MEM_DECODE_GEN[0].PER_CE_GEN[7].MULTIPLE_CES_THIS_CS_GEN.CE_I
(.Q(Q),
.\bus2ip_addr_i_reg[4] (\bus2ip_addr_i_reg[4] ),
.ce_expnd_i_0(ce_expnd_i_0));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT2 #(
.INIT(4'hE))
READ_DONE0_I_i_2
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(D_2),
.O(READ_DONE0_I));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'hE))
READ_DONE1_I_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(read_done1),
.O(READ_DONE1_I));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT2 #(
.INIT(4'h2))
\TCSR0_GENERATE[20].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce[1]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h32))
\TCSR0_GENERATE[21].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.O(pair0_Select));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h20FF))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(s_axi_wdata[8]),
.I3(s_axi_aresetn),
.O(\TCSR0_GENERATE[23].TCSR0_FF_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hEFEEEAEE))
\TCSR0_GENERATE[24].TCSR0_FF_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[86]),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.I4(s_axi_wdata[7]),
.O(\TCSR0_GENERATE[24].TCSR0_FF_I ));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT2 #(
.INIT(4'h2))
\TCSR1_GENERATE[22].TCSR1_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(bus2ip_wrce[0]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT4 #(
.INIT(16'h20FF))
\TCSR1_GENERATE[23].TCSR1_FF_I_i_1
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I2(s_axi_wdata[8]),
.I3(s_axi_aresetn),
.O(\TCSR1_GENERATE[23].TCSR1_FF_I ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hEFEEEAEE))
\TCSR1_GENERATE[24].TCSR1_FF_I_i_1
(.I0(s_axi_wdata[10]),
.I1(read_Mux_In[85]),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I4(s_axi_wdata[7]),
.O(\TCSR1_GENERATE[24].TCSR1_FF_I ));
LUT6 #(
.INIT(64'hFFFFFEFFFEFFFEFF))
s_axi_arready_INST_0
(.I0(s_axi_rvalid_i_reg),
.I1(s_axi_rvalid_i_reg_0),
.I2(s_axi_rvalid_i_reg_1),
.I3(s_axi_arready_INST_0_i_4_n_0),
.I4(is_read),
.I5(eqOp__4),
.O(s_axi_arready));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_1
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg_0));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT2 #(
.INIT(4'h8))
s_axi_arready_INST_0_i_3
(.I0(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.I1(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.O(s_axi_rvalid_i_reg_1));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00FF01FF))
s_axi_arready_INST_0_i_4
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(s_axi_arready_INST_0_i_4_n_0));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_bvalid_i_i_1
(.I0(s_axi_wready),
.I1(\state_reg[1] [1]),
.I2(\state_reg[1] [0]),
.I3(s_axi_bready),
.I4(s_axi_bvalid_i_reg_0),
.O(s_axi_bvalid_i_reg));
LUT5 #(
.INIT(32'h08FF0808))
s_axi_rvalid_i_i_1
(.I0(s_axi_arready),
.I1(\state_reg[1] [0]),
.I2(\state_reg[1] [1]),
.I3(s_axi_rready),
.I4(s_axi_rvalid_i_reg_3),
.O(s_axi_rvalid_i_reg_2));
LUT4 #(
.INIT(16'hF777))
s_axi_wready_INST_0
(.I0(s_axi_wready_INST_0_i_1_n_0),
.I1(s_axi_wready_INST_0_i_2_n_0),
.I2(is_write_reg),
.I3(eqOp__4),
.O(s_axi_wready));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'hF0F1))
s_axi_wready_INST_0_i_1
(.I0(\LOAD_REG_GEN[31].LOAD_REG_I ),
.I1(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg ),
.I2(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I3(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg ),
.O(s_axi_wready_INST_0_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'hFF00FF01))
s_axi_wready_INST_0_i_2
(.I0(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg ),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg ),
.I2(\GEN_BKEND_CE_REGISTERS[7].ce_out_i_reg ),
.I3(\TCSR0_GENERATE[23].TCSR0_FF_I ),
.I4(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg ),
.O(s_axi_wready_INST_0_i_2_n_0));
LUT6 #(
.INIT(64'h0000000000000100))
s_axi_wready_INST_0_i_3
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [4]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [2]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [3]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [5]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [0]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] [1]),
.O(eqOp__4));
LUT5 #(
.INIT(32'h77FC44FC))
\state[0]_i_1
(.I0(state1__2),
.I1(\state_reg[1] [0]),
.I2(s_axi_arvalid),
.I3(\state_reg[1] [1]),
.I4(s_axi_wready),
.O(D[0]));
LUT5 #(
.INIT(32'h5FFC50FC))
\state[1]_i_1
(.I0(state1__2),
.I1(s_axi_arvalid_0),
.I2(\state_reg[1] [1]),
.I3(\state_reg[1] [0]),
.I4(s_axi_arready),
.O(D[1]));
endmodule
(* ORIG_REF_NAME = "axi_lite_ipif" *)
module zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif
(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
Bus_RNW_reg,
s_axi_rvalid,
s_axi_bvalid,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
pair0_Select,
s_axi_wready,
s_axi_arready,
\s_axi_rdata_i_reg[11] ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[0]_0 ,
READ_DONE0_I,
READ_DONE1_I,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_rready,
s_axi_bready,
s_axi_wdata,
D_2,
read_done1,
D);
output \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
output Bus_RNW_reg;
output s_axi_rvalid;
output s_axi_bvalid;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output \s_axi_rdata_i_reg[11] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[0]_0 ;
output READ_DONE0_I;
output READ_DONE1_I;
output [31:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_rready;
input s_axi_bready;
input [31:0]s_axi_wdata;
input D_2;
input read_done1;
input [31:0]D;
wire Bus_RNW_reg;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire bus2ip_reset;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire pair0_Select;
wire [87:0]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_reg;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
zqynq_lab_1_design_axi_timer_0_0_slave_attachment I_SLAVE_ATTACHMENT
(.D(D),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.\LOAD_REG_GEN[10].LOAD_REG_I (\LOAD_REG_GEN[10].LOAD_REG_I ),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (\LOAD_REG_GEN[10].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[11].LOAD_REG_I (\LOAD_REG_GEN[11].LOAD_REG_I ),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (\LOAD_REG_GEN[11].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[12].LOAD_REG_I (\LOAD_REG_GEN[12].LOAD_REG_I ),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (\LOAD_REG_GEN[12].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[13].LOAD_REG_I (\LOAD_REG_GEN[13].LOAD_REG_I ),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (\LOAD_REG_GEN[13].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[14].LOAD_REG_I (\LOAD_REG_GEN[14].LOAD_REG_I ),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (\LOAD_REG_GEN[14].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[15].LOAD_REG_I (\LOAD_REG_GEN[15].LOAD_REG_I ),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (\LOAD_REG_GEN[15].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[16].LOAD_REG_I (\LOAD_REG_GEN[16].LOAD_REG_I ),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (\LOAD_REG_GEN[16].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[17].LOAD_REG_I (\LOAD_REG_GEN[17].LOAD_REG_I ),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (\LOAD_REG_GEN[17].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[18].LOAD_REG_I (\LOAD_REG_GEN[18].LOAD_REG_I ),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (\LOAD_REG_GEN[18].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[19].LOAD_REG_I (\LOAD_REG_GEN[19].LOAD_REG_I ),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (\LOAD_REG_GEN[19].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[1].LOAD_REG_I (\LOAD_REG_GEN[1].LOAD_REG_I ),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (\LOAD_REG_GEN[1].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (\LOAD_REG_GEN[20].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[21].LOAD_REG_I (\LOAD_REG_GEN[21].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (\LOAD_REG_GEN[21].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[22].LOAD_REG_I (\LOAD_REG_GEN[22].LOAD_REG_I ),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (\LOAD_REG_GEN[22].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[23].LOAD_REG_I (\LOAD_REG_GEN[23].LOAD_REG_I ),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (\LOAD_REG_GEN[23].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[24].LOAD_REG_I (\LOAD_REG_GEN[24].LOAD_REG_I ),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (\LOAD_REG_GEN[24].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[25].LOAD_REG_I (\LOAD_REG_GEN[25].LOAD_REG_I ),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (\LOAD_REG_GEN[25].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[26].LOAD_REG_I (\LOAD_REG_GEN[26].LOAD_REG_I ),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (\LOAD_REG_GEN[26].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[27].LOAD_REG_I (\LOAD_REG_GEN[27].LOAD_REG_I ),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (\LOAD_REG_GEN[27].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[28].LOAD_REG_I (\LOAD_REG_GEN[28].LOAD_REG_I ),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (\LOAD_REG_GEN[28].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[29].LOAD_REG_I (\LOAD_REG_GEN[29].LOAD_REG_I ),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (\LOAD_REG_GEN[29].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[2].LOAD_REG_I (\LOAD_REG_GEN[2].LOAD_REG_I ),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (\LOAD_REG_GEN[2].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[30].LOAD_REG_I (\LOAD_REG_GEN[30].LOAD_REG_I ),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (\LOAD_REG_GEN[30].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (\LOAD_REG_GEN[31].LOAD_REG_I ),
.\LOAD_REG_GEN[31].LOAD_REG_I_1 (\LOAD_REG_GEN[31].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[3].LOAD_REG_I (\LOAD_REG_GEN[3].LOAD_REG_I ),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (\LOAD_REG_GEN[3].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[4].LOAD_REG_I (\LOAD_REG_GEN[4].LOAD_REG_I ),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (\LOAD_REG_GEN[4].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[5].LOAD_REG_I (\LOAD_REG_GEN[5].LOAD_REG_I ),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (\LOAD_REG_GEN[5].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[6].LOAD_REG_I (\LOAD_REG_GEN[6].LOAD_REG_I ),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (\LOAD_REG_GEN[6].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[7].LOAD_REG_I (\LOAD_REG_GEN[7].LOAD_REG_I ),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (\LOAD_REG_GEN[7].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[8].LOAD_REG_I (\LOAD_REG_GEN[8].LOAD_REG_I ),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (\LOAD_REG_GEN[8].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[9].LOAD_REG_I (\LOAD_REG_GEN[9].LOAD_REG_I ),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (\LOAD_REG_GEN[9].LOAD_REG_I_0 ),
.READ_DONE0_I(READ_DONE0_I),
.READ_DONE1_I(READ_DONE1_I),
.\TCSR0_GENERATE[23].TCSR0_FF_I (Bus_RNW_reg),
.\TCSR0_GENERATE[23].TCSR0_FF_I_0 (\TCSR0_GENERATE[23].TCSR0_FF_I ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.pair0_Select(pair0_Select),
.read_Mux_In(read_Mux_In),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i_reg[0] ),
.\s_axi_rdata_i_reg[0]_1 (\s_axi_rdata_i_reg[0]_0 ),
.\s_axi_rdata_i_reg[10]_0 (\s_axi_rdata_i_reg[10] ),
.\s_axi_rdata_i_reg[11]_0 (\s_axi_rdata_i_reg[11] ),
.\s_axi_rdata_i_reg[12]_0 (\s_axi_rdata_i_reg[12] ),
.\s_axi_rdata_i_reg[13]_0 (\s_axi_rdata_i_reg[13] ),
.\s_axi_rdata_i_reg[14]_0 (\s_axi_rdata_i_reg[14] ),
.\s_axi_rdata_i_reg[15]_0 (\s_axi_rdata_i_reg[15] ),
.\s_axi_rdata_i_reg[16]_0 (\s_axi_rdata_i_reg[16] ),
.\s_axi_rdata_i_reg[17]_0 (\s_axi_rdata_i_reg[17] ),
.\s_axi_rdata_i_reg[18]_0 (\s_axi_rdata_i_reg[18] ),
.\s_axi_rdata_i_reg[19]_0 (\s_axi_rdata_i_reg[19] ),
.\s_axi_rdata_i_reg[20]_0 (\s_axi_rdata_i_reg[20] ),
.\s_axi_rdata_i_reg[21]_0 (\s_axi_rdata_i_reg[21] ),
.\s_axi_rdata_i_reg[22]_0 (\s_axi_rdata_i_reg[22] ),
.\s_axi_rdata_i_reg[23]_0 (\s_axi_rdata_i_reg[23] ),
.\s_axi_rdata_i_reg[24]_0 (\s_axi_rdata_i_reg[24] ),
.\s_axi_rdata_i_reg[25]_0 (\s_axi_rdata_i_reg[25] ),
.\s_axi_rdata_i_reg[26]_0 (\s_axi_rdata_i_reg[26] ),
.\s_axi_rdata_i_reg[27]_0 (\s_axi_rdata_i_reg[27] ),
.\s_axi_rdata_i_reg[28]_0 (\s_axi_rdata_i_reg[28] ),
.\s_axi_rdata_i_reg[29]_0 (\s_axi_rdata_i_reg[29] ),
.\s_axi_rdata_i_reg[30]_0 (\s_axi_rdata_i_reg[30] ),
.\s_axi_rdata_i_reg[31]_0 (\s_axi_rdata_i_reg[31] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg),
.s_axi_rvalid_i_reg_1(s_axi_rvalid_i_reg_0),
.s_axi_rvalid_i_reg_2(s_axi_rvalid_i_reg_1),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_COUNT_WIDTH = "32" *) (* C_FAMILY = "zynq" *) (* C_GEN0_ASSERT = "1'b1" *)
(* C_GEN1_ASSERT = "1'b1" *) (* C_ONE_TIMER_ONLY = "0" *) (* C_S_AXI_ADDR_WIDTH = "5" *)
(* C_S_AXI_DATA_WIDTH = "32" *) (* C_TRIG0_ASSERT = "1'b1" *) (* C_TRIG1_ASSERT = "1'b1" *)
(* ORIG_REF_NAME = "axi_timer" *) (* downgradeipidentifiedwarnings = "yes" *)
module zqynq_lab_1_design_axi_timer_0_0_axi_timer
(capturetrig0,
capturetrig1,
generateout0,
generateout1,
pwm0,
interrupt,
freeze,
s_axi_aclk,
s_axi_aresetn,
s_axi_awaddr,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wvalid,
s_axi_wready,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_araddr,
s_axi_arvalid,
s_axi_arready,
s_axi_rdata,
s_axi_rresp,
s_axi_rvalid,
s_axi_rready);
input capturetrig0;
input capturetrig1;
output generateout0;
output generateout1;
output pwm0;
output interrupt;
input freeze;
(* max_fanout = "10000" *) input s_axi_aclk;
(* max_fanout = "10000" *) input s_axi_aresetn;
input [4:0]s_axi_awaddr;
input s_axi_awvalid;
output s_axi_awready;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wvalid;
output s_axi_wready;
output [1:0]s_axi_bresp;
output s_axi_bvalid;
input s_axi_bready;
input [4:0]s_axi_araddr;
input s_axi_arvalid;
output s_axi_arready;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rvalid;
input s_axi_rready;
wire \<const0> ;
wire AXI4_LITE_I_n_10;
wire AXI4_LITE_I_n_100;
wire AXI4_LITE_I_n_101;
wire AXI4_LITE_I_n_102;
wire AXI4_LITE_I_n_103;
wire AXI4_LITE_I_n_104;
wire AXI4_LITE_I_n_105;
wire AXI4_LITE_I_n_106;
wire AXI4_LITE_I_n_11;
wire AXI4_LITE_I_n_12;
wire AXI4_LITE_I_n_13;
wire AXI4_LITE_I_n_14;
wire AXI4_LITE_I_n_15;
wire AXI4_LITE_I_n_16;
wire AXI4_LITE_I_n_17;
wire AXI4_LITE_I_n_18;
wire AXI4_LITE_I_n_19;
wire AXI4_LITE_I_n_20;
wire AXI4_LITE_I_n_21;
wire AXI4_LITE_I_n_22;
wire AXI4_LITE_I_n_23;
wire AXI4_LITE_I_n_27;
wire AXI4_LITE_I_n_28;
wire AXI4_LITE_I_n_29;
wire AXI4_LITE_I_n_30;
wire AXI4_LITE_I_n_31;
wire AXI4_LITE_I_n_32;
wire AXI4_LITE_I_n_33;
wire AXI4_LITE_I_n_34;
wire AXI4_LITE_I_n_35;
wire AXI4_LITE_I_n_36;
wire AXI4_LITE_I_n_37;
wire AXI4_LITE_I_n_38;
wire AXI4_LITE_I_n_39;
wire AXI4_LITE_I_n_4;
wire AXI4_LITE_I_n_40;
wire AXI4_LITE_I_n_41;
wire AXI4_LITE_I_n_42;
wire AXI4_LITE_I_n_43;
wire AXI4_LITE_I_n_44;
wire AXI4_LITE_I_n_45;
wire AXI4_LITE_I_n_46;
wire AXI4_LITE_I_n_47;
wire AXI4_LITE_I_n_48;
wire AXI4_LITE_I_n_49;
wire AXI4_LITE_I_n_5;
wire AXI4_LITE_I_n_50;
wire AXI4_LITE_I_n_51;
wire AXI4_LITE_I_n_52;
wire AXI4_LITE_I_n_53;
wire AXI4_LITE_I_n_54;
wire AXI4_LITE_I_n_55;
wire AXI4_LITE_I_n_56;
wire AXI4_LITE_I_n_57;
wire AXI4_LITE_I_n_58;
wire AXI4_LITE_I_n_59;
wire AXI4_LITE_I_n_6;
wire AXI4_LITE_I_n_60;
wire AXI4_LITE_I_n_65;
wire AXI4_LITE_I_n_66;
wire AXI4_LITE_I_n_67;
wire AXI4_LITE_I_n_68;
wire AXI4_LITE_I_n_69;
wire AXI4_LITE_I_n_7;
wire AXI4_LITE_I_n_70;
wire AXI4_LITE_I_n_71;
wire AXI4_LITE_I_n_72;
wire AXI4_LITE_I_n_73;
wire AXI4_LITE_I_n_74;
wire AXI4_LITE_I_n_75;
wire AXI4_LITE_I_n_76;
wire AXI4_LITE_I_n_77;
wire AXI4_LITE_I_n_78;
wire AXI4_LITE_I_n_79;
wire AXI4_LITE_I_n_8;
wire AXI4_LITE_I_n_80;
wire AXI4_LITE_I_n_81;
wire AXI4_LITE_I_n_82;
wire AXI4_LITE_I_n_83;
wire AXI4_LITE_I_n_84;
wire AXI4_LITE_I_n_85;
wire AXI4_LITE_I_n_86;
wire AXI4_LITE_I_n_87;
wire AXI4_LITE_I_n_88;
wire AXI4_LITE_I_n_89;
wire AXI4_LITE_I_n_9;
wire AXI4_LITE_I_n_90;
wire AXI4_LITE_I_n_91;
wire AXI4_LITE_I_n_92;
wire AXI4_LITE_I_n_93;
wire AXI4_LITE_I_n_94;
wire AXI4_LITE_I_n_95;
wire AXI4_LITE_I_n_97;
wire AXI4_LITE_I_n_98;
wire AXI4_LITE_I_n_99;
wire \COUNTER_0_I/D ;
wire \GEN_SECOND_TIMER.COUNTER_1_I/D ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ;
wire \I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \TIMER_CONTROL_I/D ;
wire \TIMER_CONTROL_I/pair0_Select ;
wire \TIMER_CONTROL_I/read_done1 ;
wire bus2ip_reset;
wire [0:4]bus2ip_wrce;
wire [5:5]bus2ip_wrce__0;
wire capturetrig0;
wire capturetrig1;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:31]ip2bus_data;
wire pwm0;
wire [20:191]read_Mux_In;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aclk;
wire [4:0]s_axi_araddr;
(* MAX_FANOUT = "10000" *) (* RTL_MAX_FANOUT = "found" *) wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [4:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire s_axi_rready;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
assign s_axi_awready = s_axi_wready;
assign s_axi_bresp[1] = \<const0> ;
assign s_axi_bresp[0] = \<const0> ;
assign s_axi_rresp[1] = \<const0> ;
assign s_axi_rresp[0] = \<const0> ;
zqynq_lab_1_design_axi_timer_0_0_axi_lite_ipif AXI4_LITE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.D({ip2bus_data[0],ip2bus_data[1],ip2bus_data[2],ip2bus_data[3],ip2bus_data[4],ip2bus_data[5],ip2bus_data[6],ip2bus_data[7],ip2bus_data[8],ip2bus_data[9],ip2bus_data[10],ip2bus_data[11],ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.D_0(\GEN_SECOND_TIMER.COUNTER_1_I/D ),
.D_1(\COUNTER_0_I/D ),
.D_2(\TIMER_CONTROL_I/D ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\LOAD_REG_GEN[10].LOAD_REG_I (AXI4_LITE_I_n_51),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (AXI4_LITE_I_n_86),
.\LOAD_REG_GEN[11].LOAD_REG_I (AXI4_LITE_I_n_50),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (AXI4_LITE_I_n_85),
.\LOAD_REG_GEN[12].LOAD_REG_I (AXI4_LITE_I_n_49),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (AXI4_LITE_I_n_84),
.\LOAD_REG_GEN[13].LOAD_REG_I (AXI4_LITE_I_n_48),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (AXI4_LITE_I_n_83),
.\LOAD_REG_GEN[14].LOAD_REG_I (AXI4_LITE_I_n_47),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (AXI4_LITE_I_n_82),
.\LOAD_REG_GEN[15].LOAD_REG_I (AXI4_LITE_I_n_46),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (AXI4_LITE_I_n_81),
.\LOAD_REG_GEN[16].LOAD_REG_I (AXI4_LITE_I_n_45),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (AXI4_LITE_I_n_80),
.\LOAD_REG_GEN[17].LOAD_REG_I (AXI4_LITE_I_n_44),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (AXI4_LITE_I_n_79),
.\LOAD_REG_GEN[18].LOAD_REG_I (AXI4_LITE_I_n_43),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (AXI4_LITE_I_n_78),
.\LOAD_REG_GEN[19].LOAD_REG_I (AXI4_LITE_I_n_42),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (AXI4_LITE_I_n_77),
.\LOAD_REG_GEN[1].LOAD_REG_I (AXI4_LITE_I_n_60),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (AXI4_LITE_I_n_95),
.\LOAD_REG_GEN[20].LOAD_REG_I (AXI4_LITE_I_n_41),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (AXI4_LITE_I_n_76),
.\LOAD_REG_GEN[21].LOAD_REG_I (AXI4_LITE_I_n_40),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (AXI4_LITE_I_n_75),
.\LOAD_REG_GEN[22].LOAD_REG_I (AXI4_LITE_I_n_39),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (AXI4_LITE_I_n_74),
.\LOAD_REG_GEN[23].LOAD_REG_I (AXI4_LITE_I_n_38),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (AXI4_LITE_I_n_73),
.\LOAD_REG_GEN[24].LOAD_REG_I (AXI4_LITE_I_n_37),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (AXI4_LITE_I_n_72),
.\LOAD_REG_GEN[25].LOAD_REG_I (AXI4_LITE_I_n_36),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (AXI4_LITE_I_n_71),
.\LOAD_REG_GEN[26].LOAD_REG_I (AXI4_LITE_I_n_35),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (AXI4_LITE_I_n_70),
.\LOAD_REG_GEN[27].LOAD_REG_I (AXI4_LITE_I_n_34),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (AXI4_LITE_I_n_69),
.\LOAD_REG_GEN[28].LOAD_REG_I (AXI4_LITE_I_n_33),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (AXI4_LITE_I_n_68),
.\LOAD_REG_GEN[29].LOAD_REG_I (AXI4_LITE_I_n_32),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (AXI4_LITE_I_n_67),
.\LOAD_REG_GEN[2].LOAD_REG_I (AXI4_LITE_I_n_59),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (AXI4_LITE_I_n_94),
.\LOAD_REG_GEN[30].LOAD_REG_I (AXI4_LITE_I_n_31),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (AXI4_LITE_I_n_66),
.\LOAD_REG_GEN[31].LOAD_REG_I (AXI4_LITE_I_n_30),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (AXI4_LITE_I_n_65),
.\LOAD_REG_GEN[3].LOAD_REG_I (AXI4_LITE_I_n_58),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (AXI4_LITE_I_n_93),
.\LOAD_REG_GEN[4].LOAD_REG_I (AXI4_LITE_I_n_57),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (AXI4_LITE_I_n_92),
.\LOAD_REG_GEN[5].LOAD_REG_I (AXI4_LITE_I_n_56),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (AXI4_LITE_I_n_91),
.\LOAD_REG_GEN[6].LOAD_REG_I (AXI4_LITE_I_n_55),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (AXI4_LITE_I_n_90),
.\LOAD_REG_GEN[7].LOAD_REG_I (AXI4_LITE_I_n_54),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (AXI4_LITE_I_n_89),
.\LOAD_REG_GEN[8].LOAD_REG_I (AXI4_LITE_I_n_53),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (AXI4_LITE_I_n_88),
.\LOAD_REG_GEN[9].LOAD_REG_I (AXI4_LITE_I_n_52),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (AXI4_LITE_I_n_87),
.READ_DONE0_I(AXI4_LITE_I_n_105),
.READ_DONE1_I(AXI4_LITE_I_n_106),
.\TCSR0_GENERATE[23].TCSR0_FF_I (AXI4_LITE_I_n_100),
.\TCSR0_GENERATE[24].TCSR0_FF_I (AXI4_LITE_I_n_28),
.\TCSR1_GENERATE[23].TCSR1_FF_I (AXI4_LITE_I_n_101),
.\TCSR1_GENERATE[24].TCSR1_FF_I (AXI4_LITE_I_n_29),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce({bus2ip_wrce[0],bus2ip_wrce[4]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.pair0_Select(\TIMER_CONTROL_I/pair0_Select ),
.read_Mux_In({read_Mux_In[20],read_Mux_In[24],read_Mux_In[56],read_Mux_In[64],read_Mux_In[65],read_Mux_In[66],read_Mux_In[67],read_Mux_In[68],read_Mux_In[69],read_Mux_In[70],read_Mux_In[71],read_Mux_In[72],read_Mux_In[73],read_Mux_In[74],read_Mux_In[75],read_Mux_In[76],read_Mux_In[77],read_Mux_In[78],read_Mux_In[79],read_Mux_In[80],read_Mux_In[81],read_Mux_In[82],read_Mux_In[83],read_Mux_In[84],read_Mux_In[128],read_Mux_In[129],read_Mux_In[130],read_Mux_In[131],read_Mux_In[132],read_Mux_In[133],read_Mux_In[134],read_Mux_In[135],read_Mux_In[136],read_Mux_In[137],read_Mux_In[138],read_Mux_In[139],read_Mux_In[140],read_Mux_In[141],read_Mux_In[142],read_Mux_In[143],read_Mux_In[144],read_Mux_In[145],read_Mux_In[146],read_Mux_In[147],read_Mux_In[148],read_Mux_In[149],read_Mux_In[150],read_Mux_In[151],read_Mux_In[152],read_Mux_In[153],read_Mux_In[154],read_Mux_In[155],read_Mux_In[156],read_Mux_In[157],read_Mux_In[158],read_Mux_In[159],read_Mux_In[160],read_Mux_In[161],read_Mux_In[162],read_Mux_In[163],read_Mux_In[164],read_Mux_In[165],read_Mux_In[166],read_Mux_In[167],read_Mux_In[168],read_Mux_In[169],read_Mux_In[170],read_Mux_In[171],read_Mux_In[172],read_Mux_In[173],read_Mux_In[174],read_Mux_In[175],read_Mux_In[176],read_Mux_In[177],read_Mux_In[178],read_Mux_In[179],read_Mux_In[180],read_Mux_In[181],read_Mux_In[182],read_Mux_In[183],read_Mux_In[184],read_Mux_In[185],read_Mux_In[186],read_Mux_In[187],read_Mux_In[188],read_Mux_In[189],read_Mux_In[190],read_Mux_In[191]}),
.read_done1(\TIMER_CONTROL_I/read_done1 ),
.s_axi_aclk(s_axi_aclk),
.s_axi_araddr(s_axi_araddr[4:2]),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr[4:2]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.\s_axi_rdata_i_reg[0] (AXI4_LITE_I_n_103),
.\s_axi_rdata_i_reg[0]_0 (AXI4_LITE_I_n_104),
.\s_axi_rdata_i_reg[10] (AXI4_LITE_I_n_102),
.\s_axi_rdata_i_reg[11] (AXI4_LITE_I_n_27),
.\s_axi_rdata_i_reg[12] (AXI4_LITE_I_n_4),
.\s_axi_rdata_i_reg[13] (AXI4_LITE_I_n_5),
.\s_axi_rdata_i_reg[14] (AXI4_LITE_I_n_6),
.\s_axi_rdata_i_reg[15] (AXI4_LITE_I_n_7),
.\s_axi_rdata_i_reg[16] (AXI4_LITE_I_n_8),
.\s_axi_rdata_i_reg[17] (AXI4_LITE_I_n_9),
.\s_axi_rdata_i_reg[18] (AXI4_LITE_I_n_10),
.\s_axi_rdata_i_reg[19] (AXI4_LITE_I_n_11),
.\s_axi_rdata_i_reg[20] (AXI4_LITE_I_n_12),
.\s_axi_rdata_i_reg[21] (AXI4_LITE_I_n_13),
.\s_axi_rdata_i_reg[22] (AXI4_LITE_I_n_14),
.\s_axi_rdata_i_reg[23] (AXI4_LITE_I_n_15),
.\s_axi_rdata_i_reg[24] (AXI4_LITE_I_n_16),
.\s_axi_rdata_i_reg[25] (AXI4_LITE_I_n_17),
.\s_axi_rdata_i_reg[26] (AXI4_LITE_I_n_18),
.\s_axi_rdata_i_reg[27] (AXI4_LITE_I_n_19),
.\s_axi_rdata_i_reg[28] (AXI4_LITE_I_n_20),
.\s_axi_rdata_i_reg[29] (AXI4_LITE_I_n_21),
.\s_axi_rdata_i_reg[30] (AXI4_LITE_I_n_22),
.\s_axi_rdata_i_reg[31] (AXI4_LITE_I_n_23),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_rvalid_i_reg(AXI4_LITE_I_n_97),
.s_axi_rvalid_i_reg_0(AXI4_LITE_I_n_98),
.s_axi_rvalid_i_reg_1(AXI4_LITE_I_n_99),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.s_axi_wvalid(s_axi_wvalid));
GND GND
(.G(\<const0> ));
zqynq_lab_1_design_axi_timer_0_0_tc_core TC_CORE_I
(.Bus_RNW_reg(\I_SLAVE_ATTACHMENT/I_DECODER/Bus_RNW_reg ),
.Bus_RNW_reg_reg(AXI4_LITE_I_n_23),
.Bus_RNW_reg_reg_0(AXI4_LITE_I_n_22),
.Bus_RNW_reg_reg_1(AXI4_LITE_I_n_21),
.Bus_RNW_reg_reg_10(AXI4_LITE_I_n_12),
.Bus_RNW_reg_reg_11(AXI4_LITE_I_n_11),
.Bus_RNW_reg_reg_12(AXI4_LITE_I_n_10),
.Bus_RNW_reg_reg_13(AXI4_LITE_I_n_9),
.Bus_RNW_reg_reg_14(AXI4_LITE_I_n_8),
.Bus_RNW_reg_reg_15(AXI4_LITE_I_n_7),
.Bus_RNW_reg_reg_16(AXI4_LITE_I_n_6),
.Bus_RNW_reg_reg_17(AXI4_LITE_I_n_5),
.Bus_RNW_reg_reg_18(AXI4_LITE_I_n_4),
.Bus_RNW_reg_reg_2(AXI4_LITE_I_n_20),
.Bus_RNW_reg_reg_3(AXI4_LITE_I_n_19),
.Bus_RNW_reg_reg_4(AXI4_LITE_I_n_18),
.Bus_RNW_reg_reg_5(AXI4_LITE_I_n_17),
.Bus_RNW_reg_reg_6(AXI4_LITE_I_n_16),
.Bus_RNW_reg_reg_7(AXI4_LITE_I_n_15),
.Bus_RNW_reg_reg_8(AXI4_LITE_I_n_14),
.Bus_RNW_reg_reg_9(AXI4_LITE_I_n_13),
.D({ip2bus_data[0],ip2bus_data[1],ip2bus_data[2],ip2bus_data[3],ip2bus_data[4],ip2bus_data[5],ip2bus_data[6],ip2bus_data[7],ip2bus_data[8],ip2bus_data[9],ip2bus_data[10],ip2bus_data[11],ip2bus_data[12],ip2bus_data[13],ip2bus_data[14],ip2bus_data[15],ip2bus_data[16],ip2bus_data[17],ip2bus_data[18],ip2bus_data[19],ip2bus_data[20],ip2bus_data[21],ip2bus_data[22],ip2bus_data[23],ip2bus_data[24],ip2bus_data[25],ip2bus_data[26],ip2bus_data[27],ip2bus_data[28],ip2bus_data[29],ip2bus_data[30],ip2bus_data[31]}),
.D_0(\TIMER_CONTROL_I/D ),
.D_1(\COUNTER_0_I/D ),
.D_2(\GEN_SECOND_TIMER.COUNTER_1_I/D ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (AXI4_LITE_I_n_100),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (AXI4_LITE_I_n_102),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\I_SLAVE_ATTACHMENT/I_DECODER/GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (AXI4_LITE_I_n_95),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (AXI4_LITE_I_n_94),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 (AXI4_LITE_I_n_93),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 (AXI4_LITE_I_n_84),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 (AXI4_LITE_I_n_83),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 (AXI4_LITE_I_n_82),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 (AXI4_LITE_I_n_81),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 (AXI4_LITE_I_n_80),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 (AXI4_LITE_I_n_79),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 (AXI4_LITE_I_n_78),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 (AXI4_LITE_I_n_77),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 (AXI4_LITE_I_n_76),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 (AXI4_LITE_I_n_75),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 (AXI4_LITE_I_n_92),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 (AXI4_LITE_I_n_74),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 (AXI4_LITE_I_n_73),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 (AXI4_LITE_I_n_72),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 (AXI4_LITE_I_n_71),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 (AXI4_LITE_I_n_70),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 (AXI4_LITE_I_n_69),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 (AXI4_LITE_I_n_68),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 (AXI4_LITE_I_n_67),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 (AXI4_LITE_I_n_66),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 (AXI4_LITE_I_n_65),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 (AXI4_LITE_I_n_91),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 (AXI4_LITE_I_n_105),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 (AXI4_LITE_I_n_97),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 (AXI4_LITE_I_n_90),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 (AXI4_LITE_I_n_89),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 (AXI4_LITE_I_n_88),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 (AXI4_LITE_I_n_87),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 (AXI4_LITE_I_n_86),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 (AXI4_LITE_I_n_85),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (AXI4_LITE_I_n_99),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (AXI4_LITE_I_n_101),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (AXI4_LITE_I_n_98),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (AXI4_LITE_I_n_106),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 (AXI4_LITE_I_n_103),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (AXI4_LITE_I_n_104),
.\INFERRED_GEN.icount_out_reg[0] ({read_Mux_In[20],read_Mux_In[24],read_Mux_In[56],read_Mux_In[64],read_Mux_In[65],read_Mux_In[66],read_Mux_In[67],read_Mux_In[68],read_Mux_In[69],read_Mux_In[70],read_Mux_In[71],read_Mux_In[72],read_Mux_In[73],read_Mux_In[74],read_Mux_In[75],read_Mux_In[76],read_Mux_In[77],read_Mux_In[78],read_Mux_In[79],read_Mux_In[80],read_Mux_In[81],read_Mux_In[82],read_Mux_In[83],read_Mux_In[84],read_Mux_In[128],read_Mux_In[129],read_Mux_In[130],read_Mux_In[131],read_Mux_In[132],read_Mux_In[133],read_Mux_In[134],read_Mux_In[135],read_Mux_In[136],read_Mux_In[137],read_Mux_In[138],read_Mux_In[139],read_Mux_In[140],read_Mux_In[141],read_Mux_In[142],read_Mux_In[143],read_Mux_In[144],read_Mux_In[145],read_Mux_In[146],read_Mux_In[147],read_Mux_In[148],read_Mux_In[149],read_Mux_In[150],read_Mux_In[151],read_Mux_In[152],read_Mux_In[153],read_Mux_In[154],read_Mux_In[155],read_Mux_In[156],read_Mux_In[157],read_Mux_In[158],read_Mux_In[159],read_Mux_In[160],read_Mux_In[161],read_Mux_In[162],read_Mux_In[163],read_Mux_In[164],read_Mux_In[165],read_Mux_In[166],read_Mux_In[167],read_Mux_In[168],read_Mux_In[169],read_Mux_In[170],read_Mux_In[171],read_Mux_In[172],read_Mux_In[173],read_Mux_In[174],read_Mux_In[175],read_Mux_In[176],read_Mux_In[177],read_Mux_In[178],read_Mux_In[179],read_Mux_In[180],read_Mux_In[181],read_Mux_In[182],read_Mux_In[183],read_Mux_In[184],read_Mux_In[185],read_Mux_In[186],read_Mux_In[187],read_Mux_In[188],read_Mux_In[189],read_Mux_In[190],read_Mux_In[191]}),
.\INFERRED_GEN.icount_out_reg[0]_0 (AXI4_LITE_I_n_30),
.\INFERRED_GEN.icount_out_reg[10] (AXI4_LITE_I_n_40),
.\INFERRED_GEN.icount_out_reg[11] (AXI4_LITE_I_n_41),
.\INFERRED_GEN.icount_out_reg[12] (AXI4_LITE_I_n_42),
.\INFERRED_GEN.icount_out_reg[13] (AXI4_LITE_I_n_43),
.\INFERRED_GEN.icount_out_reg[14] (AXI4_LITE_I_n_44),
.\INFERRED_GEN.icount_out_reg[15] (AXI4_LITE_I_n_45),
.\INFERRED_GEN.icount_out_reg[16] (AXI4_LITE_I_n_46),
.\INFERRED_GEN.icount_out_reg[17] (AXI4_LITE_I_n_47),
.\INFERRED_GEN.icount_out_reg[18] (AXI4_LITE_I_n_48),
.\INFERRED_GEN.icount_out_reg[19] (AXI4_LITE_I_n_49),
.\INFERRED_GEN.icount_out_reg[1] (AXI4_LITE_I_n_31),
.\INFERRED_GEN.icount_out_reg[20] (AXI4_LITE_I_n_50),
.\INFERRED_GEN.icount_out_reg[21] (AXI4_LITE_I_n_51),
.\INFERRED_GEN.icount_out_reg[22] (AXI4_LITE_I_n_52),
.\INFERRED_GEN.icount_out_reg[23] (AXI4_LITE_I_n_53),
.\INFERRED_GEN.icount_out_reg[24] (AXI4_LITE_I_n_54),
.\INFERRED_GEN.icount_out_reg[25] (AXI4_LITE_I_n_55),
.\INFERRED_GEN.icount_out_reg[26] (AXI4_LITE_I_n_56),
.\INFERRED_GEN.icount_out_reg[27] (AXI4_LITE_I_n_57),
.\INFERRED_GEN.icount_out_reg[28] (AXI4_LITE_I_n_58),
.\INFERRED_GEN.icount_out_reg[29] (AXI4_LITE_I_n_59),
.\INFERRED_GEN.icount_out_reg[2] (AXI4_LITE_I_n_32),
.\INFERRED_GEN.icount_out_reg[30] (AXI4_LITE_I_n_60),
.\INFERRED_GEN.icount_out_reg[3] (AXI4_LITE_I_n_33),
.\INFERRED_GEN.icount_out_reg[4] (AXI4_LITE_I_n_34),
.\INFERRED_GEN.icount_out_reg[5] (AXI4_LITE_I_n_35),
.\INFERRED_GEN.icount_out_reg[6] (AXI4_LITE_I_n_36),
.\INFERRED_GEN.icount_out_reg[7] (AXI4_LITE_I_n_37),
.\INFERRED_GEN.icount_out_reg[8] (AXI4_LITE_I_n_38),
.\INFERRED_GEN.icount_out_reg[9] (AXI4_LITE_I_n_39),
.\LOAD_REG_GEN[20].LOAD_REG_I (AXI4_LITE_I_n_27),
.\TCSR0_GENERATE[24].TCSR0_FF_I (AXI4_LITE_I_n_28),
.\TCSR1_GENERATE[24].TCSR1_FF_I (AXI4_LITE_I_n_29),
.bus2ip_reset(bus2ip_reset),
.bus2ip_wrce({bus2ip_wrce[0],bus2ip_wrce[4]}),
.bus2ip_wrce__0(bus2ip_wrce__0),
.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.pair0_Select(\TIMER_CONTROL_I/pair0_Select ),
.pwm0(pwm0),
.read_done1(\TIMER_CONTROL_I/read_done1 ),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_wdata({s_axi_wdata[11:9],s_axi_wdata[6:0]}));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_0_cdc_sync
(captureTrig0_d0,
read_Mux_In,
capturetrig0,
s_axi_aclk);
output captureTrig0_d0;
input [0:0]read_Mux_In;
input capturetrig0;
input s_axi_aclk;
wire CaptureTrig0_int;
wire captureTrig0_d0;
wire capturetrig0;
wire [0:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(capturetrig0),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(CaptureTrig0_int),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
captureTrig0_d_i_1
(.I0(read_Mux_In),
.I1(CaptureTrig0_int),
.O(captureTrig0_d0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1
(captureTrig1_d0,
read_Mux_In,
capturetrig1,
s_axi_aclk);
output captureTrig1_d0;
input [0:0]read_Mux_In;
input capturetrig1;
input s_axi_aclk;
wire CaptureTrig1_int;
wire captureTrig1_d0;
wire capturetrig1;
wire [0:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(capturetrig1),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(CaptureTrig1_int),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
captureTrig1_d_i_1
(.I0(read_Mux_In),
.I1(CaptureTrig1_int),
.O(captureTrig1_d0));
endmodule
(* ORIG_REF_NAME = "cdc_sync" *)
module zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2
(E,
\INFERRED_GEN.icount_out_reg[0] ,
S,
\INFERRED_GEN.icount_out_reg[4] ,
\TCSR0_GENERATE[20].TCSR0_FF_I ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
counter_TC,
read_Mux_In,
generateOutPre0,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
Load_Counter_Reg030_out,
Load_Counter_Reg031_out,
Load_Counter_Reg0__0,
Load_Counter_Reg028_out,
\INFERRED_GEN.icount_out_reg[1] ,
freeze,
s_axi_aclk);
output [0:0]E;
output [0:0]\INFERRED_GEN.icount_out_reg[0] ;
output [0:0]S;
output [0:0]\INFERRED_GEN.icount_out_reg[4] ;
input \TCSR0_GENERATE[20].TCSR0_FF_I ;
input \TCSR0_GENERATE[24].TCSR0_FF_I ;
input [0:1]counter_TC;
input [7:0]read_Mux_In;
input generateOutPre0;
input \TCSR1_GENERATE[24].TCSR1_FF_I ;
input Load_Counter_Reg030_out;
input Load_Counter_Reg031_out;
input Load_Counter_Reg0__0;
input Load_Counter_Reg028_out;
input [1:0]\INFERRED_GEN.icount_out_reg[1] ;
input freeze;
input s_axi_aclk;
wire Counter_En041_out__2;
wire Counter_En043_out__0;
wire Counter_En045_out__1;
wire Counter_En0__4;
wire [0:0]E;
wire Freeze_int;
wire [0:0]\INFERRED_GEN.icount_out_reg[0] ;
wire [1:0]\INFERRED_GEN.icount_out_reg[1] ;
wire [0:0]\INFERRED_GEN.icount_out_reg[4] ;
wire Load_Counter_Reg028_out;
wire Load_Counter_Reg030_out;
wire Load_Counter_Reg031_out;
wire Load_Counter_Reg0__0;
wire [0:0]S;
wire \TCSR0_GENERATE[20].TCSR0_FF_I ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [0:1]counter_En;
wire [0:1]counter_TC;
wire freeze;
wire generateOutPre0;
wire [7:0]read_Mux_In;
wire s_axi_aclk;
wire s_level_out_d1_cdc_to;
wire s_level_out_d2;
wire s_level_out_d3;
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_IN_cdc_to
(.C(s_axi_aclk),
.CE(1'b1),
.D(freeze),
.Q(s_level_out_d1_cdc_to),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d2
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d1_cdc_to),
.Q(s_level_out_d2),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d3
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d2),
.Q(s_level_out_d3),
.R(1'b0));
(* ASYNC_REG *)
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "FDR" *)
FDRE #(
.INIT(1'b0))
\GENERATE_LEVEL_P_S_CDC.SINGLE_BIT.CROSS_PLEVEL_IN2SCNDRY_s_level_out_d4
(.C(s_axi_aclk),
.CE(1'b1),
.D(s_level_out_d3),
.Q(Freeze_int),
.R(1'b0));
LUT5 #(
.INIT(32'hFCFFFCAA))
\INFERRED_GEN.icount_out[31]_i_1
(.I0(Load_Counter_Reg030_out),
.I1(Load_Counter_Reg031_out),
.I2(Counter_En043_out__0),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(Counter_En041_out__2),
.O(E));
LUT5 #(
.INIT(32'hFCFFFCAA))
\INFERRED_GEN.icount_out[31]_i_1__0
(.I0(Load_Counter_Reg0__0),
.I1(Load_Counter_Reg028_out),
.I2(Counter_En045_out__1),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(Counter_En0__4),
.O(\INFERRED_GEN.icount_out_reg[0] ));
LUT5 #(
.INIT(32'h00FB0000))
\INFERRED_GEN.icount_out[31]_i_5
(.I0(read_Mux_In[4]),
.I1(counter_TC[1]),
.I2(read_Mux_In[6]),
.I3(Freeze_int),
.I4(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.O(Counter_En043_out__0));
LUT6 #(
.INIT(64'h4040404040004040))
\INFERRED_GEN.icount_out[31]_i_5__0
(.I0(Freeze_int),
.I1(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.I2(generateOutPre0),
.I3(read_Mux_In[6]),
.I4(counter_TC[1]),
.I5(read_Mux_In[4]),
.O(Counter_En045_out__1));
LUT6 #(
.INIT(64'h4444444444444404))
\INFERRED_GEN.icount_out[31]_i_6
(.I0(Freeze_int),
.I1(\TCSR0_GENERATE[24].TCSR0_FF_I ),
.I2(counter_TC[0]),
.I3(read_Mux_In[7]),
.I4(read_Mux_In[6]),
.I5(read_Mux_In[4]),
.O(Counter_En041_out__2));
LUT6 #(
.INIT(64'h2222222222202222))
\INFERRED_GEN.icount_out[31]_i_6__0
(.I0(\TCSR1_GENERATE[24].TCSR1_FF_I ),
.I1(Freeze_int),
.I2(read_Mux_In[3]),
.I3(read_Mux_In[2]),
.I4(counter_TC[1]),
.I5(read_Mux_In[0]),
.O(Counter_En0__4));
LUT3 #(
.INIT(8'h6A))
icount_out0_carry_i_5
(.I0(\INFERRED_GEN.icount_out_reg[1] [1]),
.I1(counter_En[0]),
.I2(read_Mux_In[5]),
.O(S));
LUT5 #(
.INIT(32'h6A666AAA))
icount_out0_carry_i_5__0
(.I0(\INFERRED_GEN.icount_out_reg[1] [0]),
.I1(counter_En[1]),
.I2(read_Mux_In[5]),
.I3(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.I4(read_Mux_In[1]),
.O(\INFERRED_GEN.icount_out_reg[4] ));
MUXF7 icount_out0_carry_i_6
(.I0(Counter_En041_out__2),
.I1(Counter_En043_out__0),
.O(counter_En[0]),
.S(\TCSR0_GENERATE[20].TCSR0_FF_I ));
MUXF7 icount_out0_carry_i_6__0
(.I0(Counter_En0__4),
.I1(Counter_En045_out__1),
.O(counter_En[1]),
.S(\TCSR0_GENERATE[20].TCSR0_FF_I ));
endmodule
(* ORIG_REF_NAME = "count_module" *)
module zqynq_lab_1_design_axi_timer_0_0_count_module
(\INFERRED_GEN.icount_out_reg[31] ,
read_Mux_In,
generateOutPre0_reg,
counter_TC,
s_axi_aresetn_0,
\TCSR0_GENERATE[27].TCSR0_FF_I ,
D_1,
s_axi_aclk,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ,
S,
load_Counter_Reg,
Q,
E,
s_axi_aresetn);
output [52:0]\INFERRED_GEN.icount_out_reg[31] ;
output [10:0]read_Mux_In;
output generateOutPre0_reg;
output [0:0]counter_TC;
input s_axi_aresetn_0;
input \TCSR0_GENERATE[27].TCSR0_FF_I ;
input D_1;
input s_axi_aclk;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
input [0:0]S;
input [0:0]load_Counter_Reg;
input [0:0]Q;
input [0:0]E;
input s_axi_aresetn;
wire D_1;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
wire [52:0]\INFERRED_GEN.icount_out_reg[31] ;
wire [0:0]Q;
wire [0:0]S;
wire \TCSR0_GENERATE[27].TCSR0_FF_I ;
wire [0:0]counter_TC;
wire generateOutPre0_reg;
wire [0:0]load_Counter_Reg;
wire [10:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
zqynq_lab_1_design_axi_timer_0_0_counter_f_3 COUNTER_I
(.E(E),
.\LOAD_REG_GEN[0].LOAD_REG_I (\INFERRED_GEN.icount_out_reg[31] [31:0]),
.\LOAD_REG_GEN[0].LOAD_REG_I_0 (\INFERRED_GEN.icount_out_reg[31] [52:32]),
.Q(Q),
.S(S),
.counter_TC(counter_TC),
.generateOutPre0_reg(generateOutPre0_reg),
.load_Counter_Reg(load_Counter_Reg),
.read_Mux_In(read_Mux_In),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[0].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(D_1),
.Q(\INFERRED_GEN.icount_out_reg[31] [52]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[10].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [42]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[11].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [41]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[12].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [40]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[13].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [39]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[14].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [38]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[15].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [37]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[16].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [36]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[17].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [35]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[18].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [34]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[19].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [33]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[1].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(\INFERRED_GEN.icount_out_reg[31] [51]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[20].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [32]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[21].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ),
.Q(read_Mux_In[10]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[22].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ),
.Q(read_Mux_In[9]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[23].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ),
.Q(read_Mux_In[8]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[24].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ),
.Q(read_Mux_In[7]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[25].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ),
.Q(read_Mux_In[6]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[26].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ),
.Q(read_Mux_In[5]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[27].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ),
.Q(read_Mux_In[4]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[28].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ),
.Q(read_Mux_In[3]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[29].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ),
.Q(read_Mux_In[2]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[2].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [50]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[30].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ),
.Q(read_Mux_In[1]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[31].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ),
.Q(read_Mux_In[0]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[3].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [49]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[4].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [48]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[5].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [47]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[6].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [46]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[7].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [45]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[8].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [44]),
.R(s_axi_aresetn_0));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[9].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[27].TCSR0_FF_I ),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ),
.Q(\INFERRED_GEN.icount_out_reg[31] [43]),
.R(s_axi_aresetn_0));
endmodule
(* ORIG_REF_NAME = "count_module" *)
module zqynq_lab_1_design_axi_timer_0_0_count_module_0
(\INFERRED_GEN.icount_out_reg[31] ,
Q,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[11] ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
generateOutPre1_reg,
counter_TC,
\TCSR0_GENERATE[20].TCSR0_FF_I ,
D_2,
s_axi_aclk,
\INFERRED_GEN.icount_out_reg[30] ,
\INFERRED_GEN.icount_out_reg[29] ,
\INFERRED_GEN.icount_out_reg[28] ,
\INFERRED_GEN.icount_out_reg[27] ,
\INFERRED_GEN.icount_out_reg[26] ,
\INFERRED_GEN.icount_out_reg[25] ,
\INFERRED_GEN.icount_out_reg[24] ,
\INFERRED_GEN.icount_out_reg[23] ,
\INFERRED_GEN.icount_out_reg[22] ,
\INFERRED_GEN.icount_out_reg[21] ,
\INFERRED_GEN.icount_out_reg[20] ,
\INFERRED_GEN.icount_out_reg[19] ,
\INFERRED_GEN.icount_out_reg[18] ,
\INFERRED_GEN.icount_out_reg[17] ,
\INFERRED_GEN.icount_out_reg[16] ,
\INFERRED_GEN.icount_out_reg[15] ,
\INFERRED_GEN.icount_out_reg[14] ,
\INFERRED_GEN.icount_out_reg[13] ,
\INFERRED_GEN.icount_out_reg[12] ,
\INFERRED_GEN.icount_out_reg[11] ,
\INFERRED_GEN.icount_out_reg[10] ,
\INFERRED_GEN.icount_out_reg[9] ,
\INFERRED_GEN.icount_out_reg[8] ,
\INFERRED_GEN.icount_out_reg[7] ,
\INFERRED_GEN.icount_out_reg[6] ,
\INFERRED_GEN.icount_out_reg[5] ,
\INFERRED_GEN.icount_out_reg[4] ,
\INFERRED_GEN.icount_out_reg[3] ,
\INFERRED_GEN.icount_out_reg[2] ,
\INFERRED_GEN.icount_out_reg[1] ,
\INFERRED_GEN.icount_out_reg[0] ,
S,
load_Counter_Reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\INFERRED_GEN.icount_out_reg[31]_0 ,
\counter_TC_Reg_reg[1] ,
E);
output \INFERRED_GEN.icount_out_reg[31] ;
output [31:0]Q;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[11] ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output generateOutPre1_reg;
output [0:0]counter_TC;
input \TCSR0_GENERATE[20].TCSR0_FF_I ;
input D_2;
input s_axi_aclk;
input \INFERRED_GEN.icount_out_reg[30] ;
input \INFERRED_GEN.icount_out_reg[29] ;
input \INFERRED_GEN.icount_out_reg[28] ;
input \INFERRED_GEN.icount_out_reg[27] ;
input \INFERRED_GEN.icount_out_reg[26] ;
input \INFERRED_GEN.icount_out_reg[25] ;
input \INFERRED_GEN.icount_out_reg[24] ;
input \INFERRED_GEN.icount_out_reg[23] ;
input \INFERRED_GEN.icount_out_reg[22] ;
input \INFERRED_GEN.icount_out_reg[21] ;
input \INFERRED_GEN.icount_out_reg[20] ;
input \INFERRED_GEN.icount_out_reg[19] ;
input \INFERRED_GEN.icount_out_reg[18] ;
input \INFERRED_GEN.icount_out_reg[17] ;
input \INFERRED_GEN.icount_out_reg[16] ;
input \INFERRED_GEN.icount_out_reg[15] ;
input \INFERRED_GEN.icount_out_reg[14] ;
input \INFERRED_GEN.icount_out_reg[13] ;
input \INFERRED_GEN.icount_out_reg[12] ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \INFERRED_GEN.icount_out_reg[0] ;
input [0:0]S;
input [0:0]load_Counter_Reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
input [0:0]\counter_TC_Reg_reg[1] ;
input [0:0]E;
wire D_2;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[31] ;
wire [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire [31:0]Q;
wire [0:0]S;
wire \TCSR0_GENERATE[20].TCSR0_FF_I ;
wire [0:0]counter_TC;
wire [0:0]\counter_TC_Reg_reg[1] ;
wire generateOutPre1_reg;
wire [0:0]load_Counter_Reg;
wire [96:127]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
zqynq_lab_1_design_axi_timer_0_0_counter_f COUNTER_I
(.E(E),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.\INFERRED_GEN.icount_out_reg[31]_0 (\INFERRED_GEN.icount_out_reg[31]_0 ),
.Q(Q),
.S(S),
.SR(\INFERRED_GEN.icount_out_reg[31] ),
.counter_TC(counter_TC),
.\counter_TC_Reg_reg[1] (\counter_TC_Reg_reg[1] ),
.generateOutPre1_reg(generateOutPre1_reg),
.load_Counter_Reg(load_Counter_Reg),
.read_Mux_In({read_Mux_In[96],read_Mux_In[97],read_Mux_In[98],read_Mux_In[99],read_Mux_In[100],read_Mux_In[101],read_Mux_In[102],read_Mux_In[103],read_Mux_In[104],read_Mux_In[105],read_Mux_In[106],read_Mux_In[107],read_Mux_In[108],read_Mux_In[109],read_Mux_In[110],read_Mux_In[111],read_Mux_In[112],read_Mux_In[113],read_Mux_In[114],read_Mux_In[115],read_Mux_In[116],read_Mux_In[117],read_Mux_In[118],read_Mux_In[119],read_Mux_In[120],read_Mux_In[121],read_Mux_In[122],read_Mux_In[123],read_Mux_In[124],read_Mux_In[125],read_Mux_In[126],read_Mux_In[127]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata_i_reg[0] (\s_axi_rdata_i_reg[0] ),
.\s_axi_rdata_i_reg[10] (\s_axi_rdata_i_reg[10] ),
.\s_axi_rdata_i_reg[11] (\s_axi_rdata_i_reg[11] ),
.\s_axi_rdata_i_reg[12] (\s_axi_rdata_i_reg[12] ),
.\s_axi_rdata_i_reg[13] (\s_axi_rdata_i_reg[13] ),
.\s_axi_rdata_i_reg[14] (\s_axi_rdata_i_reg[14] ),
.\s_axi_rdata_i_reg[15] (\s_axi_rdata_i_reg[15] ),
.\s_axi_rdata_i_reg[16] (\s_axi_rdata_i_reg[16] ),
.\s_axi_rdata_i_reg[17] (\s_axi_rdata_i_reg[17] ),
.\s_axi_rdata_i_reg[18] (\s_axi_rdata_i_reg[18] ),
.\s_axi_rdata_i_reg[19] (\s_axi_rdata_i_reg[19] ),
.\s_axi_rdata_i_reg[1] (\s_axi_rdata_i_reg[1] ),
.\s_axi_rdata_i_reg[20] (\s_axi_rdata_i_reg[20] ),
.\s_axi_rdata_i_reg[21] (\s_axi_rdata_i_reg[21] ),
.\s_axi_rdata_i_reg[22] (\s_axi_rdata_i_reg[22] ),
.\s_axi_rdata_i_reg[23] (\s_axi_rdata_i_reg[23] ),
.\s_axi_rdata_i_reg[24] (\s_axi_rdata_i_reg[24] ),
.\s_axi_rdata_i_reg[25] (\s_axi_rdata_i_reg[25] ),
.\s_axi_rdata_i_reg[26] (\s_axi_rdata_i_reg[26] ),
.\s_axi_rdata_i_reg[27] (\s_axi_rdata_i_reg[27] ),
.\s_axi_rdata_i_reg[28] (\s_axi_rdata_i_reg[28] ),
.\s_axi_rdata_i_reg[29] (\s_axi_rdata_i_reg[29] ),
.\s_axi_rdata_i_reg[2] (\s_axi_rdata_i_reg[2] ),
.\s_axi_rdata_i_reg[30] (\s_axi_rdata_i_reg[30] ),
.\s_axi_rdata_i_reg[31] (\s_axi_rdata_i_reg[31] ),
.\s_axi_rdata_i_reg[3] (\s_axi_rdata_i_reg[3] ),
.\s_axi_rdata_i_reg[4] (\s_axi_rdata_i_reg[4] ),
.\s_axi_rdata_i_reg[5] (\s_axi_rdata_i_reg[5] ),
.\s_axi_rdata_i_reg[6] (\s_axi_rdata_i_reg[6] ),
.\s_axi_rdata_i_reg[7] (\s_axi_rdata_i_reg[7] ),
.\s_axi_rdata_i_reg[8] (\s_axi_rdata_i_reg[8] ),
.\s_axi_rdata_i_reg[9] (\s_axi_rdata_i_reg[9] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[0].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(D_2),
.Q(read_Mux_In[96]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[10].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[21] ),
.Q(read_Mux_In[106]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[11].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[20] ),
.Q(read_Mux_In[107]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[12].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[19] ),
.Q(read_Mux_In[108]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[13].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[18] ),
.Q(read_Mux_In[109]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[14].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[17] ),
.Q(read_Mux_In[110]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[15].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[16] ),
.Q(read_Mux_In[111]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[16].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[15] ),
.Q(read_Mux_In[112]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[17].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[14] ),
.Q(read_Mux_In[113]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[18].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[13] ),
.Q(read_Mux_In[114]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[19].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[12] ),
.Q(read_Mux_In[115]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[1].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[30] ),
.Q(read_Mux_In[97]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[20].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[11] ),
.Q(read_Mux_In[116]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[21].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[10] ),
.Q(read_Mux_In[117]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[22].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[9] ),
.Q(read_Mux_In[118]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[23].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[8] ),
.Q(read_Mux_In[119]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[24].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[7] ),
.Q(read_Mux_In[120]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[25].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[6] ),
.Q(read_Mux_In[121]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[26].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[5] ),
.Q(read_Mux_In[122]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[27].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[4] ),
.Q(read_Mux_In[123]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[28].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[3] ),
.Q(read_Mux_In[124]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[29].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[2] ),
.Q(read_Mux_In[125]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[2].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[29] ),
.Q(read_Mux_In[98]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[30].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[1] ),
.Q(read_Mux_In[126]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[31].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[0] ),
.Q(read_Mux_In[127]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[3].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[28] ),
.Q(read_Mux_In[99]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[4].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[27] ),
.Q(read_Mux_In[100]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[5].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[26] ),
.Q(read_Mux_In[101]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[6].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[25] ),
.Q(read_Mux_In[102]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[7].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[24] ),
.Q(read_Mux_In[103]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[8].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[23] ),
.Q(read_Mux_In[104]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
(* BOX_TYPE = "PRIMITIVE" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\LOAD_REG_GEN[9].LOAD_REG_I
(.C(s_axi_aclk),
.CE(\TCSR0_GENERATE[20].TCSR0_FF_I ),
.D(\INFERRED_GEN.icount_out_reg[22] ),
.Q(read_Mux_In[105]),
.R(\INFERRED_GEN.icount_out_reg[31] ));
endmodule
(* ORIG_REF_NAME = "counter_f" *)
module zqynq_lab_1_design_axi_timer_0_0_counter_f
(Q,
SR,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
\s_axi_rdata_i_reg[11] ,
\s_axi_rdata_i_reg[12] ,
\s_axi_rdata_i_reg[13] ,
\s_axi_rdata_i_reg[14] ,
\s_axi_rdata_i_reg[15] ,
\s_axi_rdata_i_reg[16] ,
\s_axi_rdata_i_reg[17] ,
\s_axi_rdata_i_reg[18] ,
\s_axi_rdata_i_reg[19] ,
\s_axi_rdata_i_reg[20] ,
\s_axi_rdata_i_reg[21] ,
\s_axi_rdata_i_reg[22] ,
\s_axi_rdata_i_reg[23] ,
\s_axi_rdata_i_reg[24] ,
\s_axi_rdata_i_reg[25] ,
\s_axi_rdata_i_reg[26] ,
\s_axi_rdata_i_reg[27] ,
\s_axi_rdata_i_reg[28] ,
\s_axi_rdata_i_reg[29] ,
\s_axi_rdata_i_reg[30] ,
\s_axi_rdata_i_reg[31] ,
generateOutPre1_reg,
counter_TC,
S,
read_Mux_In,
load_Counter_Reg,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\INFERRED_GEN.icount_out_reg[31]_0 ,
\counter_TC_Reg_reg[1] ,
E,
s_axi_aclk);
output [31:0]Q;
output [0:0]SR;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output \s_axi_rdata_i_reg[11] ;
output \s_axi_rdata_i_reg[12] ;
output \s_axi_rdata_i_reg[13] ;
output \s_axi_rdata_i_reg[14] ;
output \s_axi_rdata_i_reg[15] ;
output \s_axi_rdata_i_reg[16] ;
output \s_axi_rdata_i_reg[17] ;
output \s_axi_rdata_i_reg[18] ;
output \s_axi_rdata_i_reg[19] ;
output \s_axi_rdata_i_reg[20] ;
output \s_axi_rdata_i_reg[21] ;
output \s_axi_rdata_i_reg[22] ;
output \s_axi_rdata_i_reg[23] ;
output \s_axi_rdata_i_reg[24] ;
output \s_axi_rdata_i_reg[25] ;
output \s_axi_rdata_i_reg[26] ;
output \s_axi_rdata_i_reg[27] ;
output \s_axi_rdata_i_reg[28] ;
output \s_axi_rdata_i_reg[29] ;
output \s_axi_rdata_i_reg[30] ;
output \s_axi_rdata_i_reg[31] ;
output generateOutPre1_reg;
output [0:0]counter_TC;
input [0:0]S;
input [31:0]read_Mux_In;
input [0:0]load_Counter_Reg;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
input [0:0]\counter_TC_Reg_reg[1] ;
input [0:0]E;
input s_axi_aclk;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \INFERRED_GEN.icount_out[0]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[10]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[11]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[12]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[13]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[14]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[15]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[16]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[17]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[18]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[19]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[1]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[20]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[21]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[22]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[23]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[24]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[25]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[26]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[27]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[28]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[29]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[2]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[30]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[31]_i_2_n_0 ;
wire \INFERRED_GEN.icount_out[32]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[3]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[4]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[5]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[6]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[7]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[8]_i_1_n_0 ;
wire \INFERRED_GEN.icount_out[9]_i_1_n_0 ;
wire [31:0]\INFERRED_GEN.icount_out_reg[31]_0 ;
wire [31:0]Q;
wire [0:0]S;
wire [0:0]SR;
wire [0:0]counter_TC;
wire [0:0]\counter_TC_Reg_reg[1] ;
wire generateOutPre1_reg;
wire icount_out0_carry__0_i_1_n_0;
wire icount_out0_carry__0_i_2_n_0;
wire icount_out0_carry__0_i_3_n_0;
wire icount_out0_carry__0_i_4_n_0;
wire icount_out0_carry__0_n_0;
wire icount_out0_carry__0_n_1;
wire icount_out0_carry__0_n_2;
wire icount_out0_carry__0_n_3;
wire icount_out0_carry__0_n_4;
wire icount_out0_carry__0_n_5;
wire icount_out0_carry__0_n_6;
wire icount_out0_carry__0_n_7;
wire icount_out0_carry__1_i_1_n_0;
wire icount_out0_carry__1_i_2_n_0;
wire icount_out0_carry__1_i_3_n_0;
wire icount_out0_carry__1_i_4_n_0;
wire icount_out0_carry__1_n_0;
wire icount_out0_carry__1_n_1;
wire icount_out0_carry__1_n_2;
wire icount_out0_carry__1_n_3;
wire icount_out0_carry__1_n_4;
wire icount_out0_carry__1_n_5;
wire icount_out0_carry__1_n_6;
wire icount_out0_carry__1_n_7;
wire icount_out0_carry__2_i_1_n_0;
wire icount_out0_carry__2_i_2_n_0;
wire icount_out0_carry__2_i_3_n_0;
wire icount_out0_carry__2_i_4_n_0;
wire icount_out0_carry__2_n_0;
wire icount_out0_carry__2_n_1;
wire icount_out0_carry__2_n_2;
wire icount_out0_carry__2_n_3;
wire icount_out0_carry__2_n_4;
wire icount_out0_carry__2_n_5;
wire icount_out0_carry__2_n_6;
wire icount_out0_carry__2_n_7;
wire icount_out0_carry__3_i_1_n_0;
wire icount_out0_carry__3_i_2_n_0;
wire icount_out0_carry__3_i_3_n_0;
wire icount_out0_carry__3_i_4_n_0;
wire icount_out0_carry__3_n_0;
wire icount_out0_carry__3_n_1;
wire icount_out0_carry__3_n_2;
wire icount_out0_carry__3_n_3;
wire icount_out0_carry__3_n_4;
wire icount_out0_carry__3_n_5;
wire icount_out0_carry__3_n_6;
wire icount_out0_carry__3_n_7;
wire icount_out0_carry__4_i_1_n_0;
wire icount_out0_carry__4_i_2_n_0;
wire icount_out0_carry__4_i_3_n_0;
wire icount_out0_carry__4_i_4_n_0;
wire icount_out0_carry__4_n_0;
wire icount_out0_carry__4_n_1;
wire icount_out0_carry__4_n_2;
wire icount_out0_carry__4_n_3;
wire icount_out0_carry__4_n_4;
wire icount_out0_carry__4_n_5;
wire icount_out0_carry__4_n_6;
wire icount_out0_carry__4_n_7;
wire icount_out0_carry__5_i_1_n_0;
wire icount_out0_carry__5_i_2_n_0;
wire icount_out0_carry__5_i_3_n_0;
wire icount_out0_carry__5_i_4_n_0;
wire icount_out0_carry__5_n_0;
wire icount_out0_carry__5_n_1;
wire icount_out0_carry__5_n_2;
wire icount_out0_carry__5_n_3;
wire icount_out0_carry__5_n_4;
wire icount_out0_carry__5_n_5;
wire icount_out0_carry__5_n_6;
wire icount_out0_carry__5_n_7;
wire icount_out0_carry__6_i_1_n_0;
wire icount_out0_carry__6_i_2_n_0;
wire icount_out0_carry__6_i_3_n_0;
wire icount_out0_carry__6_i_4_n_0;
wire icount_out0_carry__6_n_1;
wire icount_out0_carry__6_n_2;
wire icount_out0_carry__6_n_3;
wire icount_out0_carry__6_n_4;
wire icount_out0_carry__6_n_5;
wire icount_out0_carry__6_n_6;
wire icount_out0_carry__6_n_7;
wire icount_out0_carry_i_1_n_0;
wire icount_out0_carry_i_2_n_0;
wire icount_out0_carry_i_3_n_0;
wire icount_out0_carry_i_4_n_0;
wire icount_out0_carry_n_0;
wire icount_out0_carry_n_1;
wire icount_out0_carry_n_2;
wire icount_out0_carry_n_3;
wire icount_out0_carry_n_4;
wire icount_out0_carry_n_5;
wire icount_out0_carry_n_6;
wire icount_out0_carry_n_7;
wire [0:0]load_Counter_Reg;
wire [31:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[11] ;
wire \s_axi_rdata_i_reg[12] ;
wire \s_axi_rdata_i_reg[13] ;
wire \s_axi_rdata_i_reg[14] ;
wire \s_axi_rdata_i_reg[15] ;
wire \s_axi_rdata_i_reg[16] ;
wire \s_axi_rdata_i_reg[17] ;
wire \s_axi_rdata_i_reg[18] ;
wire \s_axi_rdata_i_reg[19] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[20] ;
wire \s_axi_rdata_i_reg[21] ;
wire \s_axi_rdata_i_reg[22] ;
wire \s_axi_rdata_i_reg[23] ;
wire \s_axi_rdata_i_reg[24] ;
wire \s_axi_rdata_i_reg[25] ;
wire \s_axi_rdata_i_reg[26] ;
wire \s_axi_rdata_i_reg[27] ;
wire \s_axi_rdata_i_reg[28] ;
wire \s_axi_rdata_i_reg[29] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[30] ;
wire \s_axi_rdata_i_reg[31] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
wire [3:3]NLW_icount_out0_carry__6_CO_UNCONNECTED;
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[31]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[31]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [31]),
.O(\s_axi_rdata_i_reg[31] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[21]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[21]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [21]),
.O(\s_axi_rdata_i_reg[21] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[20]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[20]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [20]),
.O(\s_axi_rdata_i_reg[20] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[19]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[19]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [19]),
.O(\s_axi_rdata_i_reg[19] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[18]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[18]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [18]),
.O(\s_axi_rdata_i_reg[18] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[17]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[17]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [17]),
.O(\s_axi_rdata_i_reg[17] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[16]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[16]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [16]),
.O(\s_axi_rdata_i_reg[16] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[15]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[15]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [15]),
.O(\s_axi_rdata_i_reg[15] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[14]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[14]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [14]),
.O(\s_axi_rdata_i_reg[14] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[13]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[13]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [13]),
.O(\s_axi_rdata_i_reg[13] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[12]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[12]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [12]),
.O(\s_axi_rdata_i_reg[12] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[30]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[30]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [30]),
.O(\s_axi_rdata_i_reg[30] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[11]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[11]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [11]),
.O(\s_axi_rdata_i_reg[11] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[10]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[10]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [10]),
.O(\s_axi_rdata_i_reg[10] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[9]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[9]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [9]),
.O(\s_axi_rdata_i_reg[9] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[8]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[8]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [8]),
.O(\s_axi_rdata_i_reg[8] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[7]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[7]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [7]),
.O(\s_axi_rdata_i_reg[7] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[6]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[6]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [6]),
.O(\s_axi_rdata_i_reg[6] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[5]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[5]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [5]),
.O(\s_axi_rdata_i_reg[5] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[4]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[4]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [4]),
.O(\s_axi_rdata_i_reg[4] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[3]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[3]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [3]),
.O(\s_axi_rdata_i_reg[3] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[2]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[2]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [2]),
.O(\s_axi_rdata_i_reg[2] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[29]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[29]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [29]),
.O(\s_axi_rdata_i_reg[29] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[1]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[1]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [1]),
.O(\s_axi_rdata_i_reg[1] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[0]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[0]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [0]),
.O(\s_axi_rdata_i_reg[0] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[28]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[28]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [28]),
.O(\s_axi_rdata_i_reg[28] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[27]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[27]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [27]),
.O(\s_axi_rdata_i_reg[27] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[26]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[26]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [26]),
.O(\s_axi_rdata_i_reg[26] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[25]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[25]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [25]),
.O(\s_axi_rdata_i_reg[25] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[24]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[24]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [24]),
.O(\s_axi_rdata_i_reg[24] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[23]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[23]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [23]),
.O(\s_axi_rdata_i_reg[23] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[1].MUXCY_GEN.MUXCY_I_i_1
(.I0(Q[22]),
.I1(\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.I2(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.I3(read_Mux_In[22]),
.I4(\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.I5(\INFERRED_GEN.icount_out_reg[31]_0 [22]),
.O(\s_axi_rdata_i_reg[22] ));
LUT1 #(
.INIT(2'h1))
GenerateOut0_i_1
(.I0(s_axi_aresetn),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hA3))
\INFERRED_GEN.icount_out[0]_i_1
(.I0(read_Mux_In[0]),
.I1(Q[0]),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[0]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[10]_i_1
(.I0(read_Mux_In[10]),
.I1(icount_out0_carry__1_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[10]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[11]_i_1
(.I0(read_Mux_In[11]),
.I1(icount_out0_carry__1_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[12]_i_1
(.I0(read_Mux_In[12]),
.I1(icount_out0_carry__1_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[12]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[13]_i_1
(.I0(read_Mux_In[13]),
.I1(icount_out0_carry__2_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[13]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[14]_i_1
(.I0(read_Mux_In[14]),
.I1(icount_out0_carry__2_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[14]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[15]_i_1
(.I0(read_Mux_In[15]),
.I1(icount_out0_carry__2_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[15]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[16]_i_1
(.I0(read_Mux_In[16]),
.I1(icount_out0_carry__2_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[16]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[17]_i_1
(.I0(read_Mux_In[17]),
.I1(icount_out0_carry__3_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[17]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[18]_i_1
(.I0(read_Mux_In[18]),
.I1(icount_out0_carry__3_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[18]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[19]_i_1
(.I0(read_Mux_In[19]),
.I1(icount_out0_carry__3_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[19]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[1]_i_1
(.I0(read_Mux_In[1]),
.I1(icount_out0_carry_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[1]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[20]_i_1
(.I0(read_Mux_In[20]),
.I1(icount_out0_carry__3_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[20]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[21]_i_1
(.I0(read_Mux_In[21]),
.I1(icount_out0_carry__4_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[21]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[22]_i_1
(.I0(read_Mux_In[22]),
.I1(icount_out0_carry__4_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[22]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[23]_i_1
(.I0(read_Mux_In[23]),
.I1(icount_out0_carry__4_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[23]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[24]_i_1
(.I0(read_Mux_In[24]),
.I1(icount_out0_carry__4_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[24]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[25]_i_1
(.I0(read_Mux_In[25]),
.I1(icount_out0_carry__5_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[25]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[26]_i_1
(.I0(read_Mux_In[26]),
.I1(icount_out0_carry__5_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[26]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[27]_i_1
(.I0(read_Mux_In[27]),
.I1(icount_out0_carry__5_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[27]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[28]_i_1
(.I0(read_Mux_In[28]),
.I1(icount_out0_carry__5_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[28]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[29]_i_1
(.I0(read_Mux_In[29]),
.I1(icount_out0_carry__6_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[29]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[2]_i_1
(.I0(read_Mux_In[2]),
.I1(icount_out0_carry_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[2]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[30]_i_1
(.I0(read_Mux_In[30]),
.I1(icount_out0_carry__6_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[30]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[31]_i_2
(.I0(read_Mux_In[31]),
.I1(icount_out0_carry__6_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[31]_i_2_n_0 ));
LUT5 #(
.INIT(32'h0000E200))
\INFERRED_GEN.icount_out[32]_i_1
(.I0(counter_TC),
.I1(E),
.I2(icount_out0_carry__6_n_4),
.I3(s_axi_aresetn),
.I4(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[3]_i_1
(.I0(read_Mux_In[3]),
.I1(icount_out0_carry_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[3]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[4]_i_1
(.I0(read_Mux_In[4]),
.I1(icount_out0_carry_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[5]_i_1
(.I0(read_Mux_In[5]),
.I1(icount_out0_carry__0_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[6]_i_1
(.I0(read_Mux_In[6]),
.I1(icount_out0_carry__0_n_6),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[6]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[7]_i_1
(.I0(read_Mux_In[7]),
.I1(icount_out0_carry__0_n_5),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[7]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[8]_i_1
(.I0(read_Mux_In[8]),
.I1(icount_out0_carry__0_n_4),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[8]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\INFERRED_GEN.icount_out[9]_i_1
(.I0(read_Mux_In[9]),
.I1(icount_out0_carry__1_n_7),
.I2(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[9]_i_1_n_0 ));
FDRE \INFERRED_GEN.icount_out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[0]_i_1_n_0 ),
.Q(Q[0]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[10]_i_1_n_0 ),
.Q(Q[10]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[11]_i_1_n_0 ),
.Q(Q[11]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[12]_i_1_n_0 ),
.Q(Q[12]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[13]_i_1_n_0 ),
.Q(Q[13]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[14]_i_1_n_0 ),
.Q(Q[14]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[15]_i_1_n_0 ),
.Q(Q[15]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[16]_i_1_n_0 ),
.Q(Q[16]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[17]_i_1_n_0 ),
.Q(Q[17]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[18]_i_1_n_0 ),
.Q(Q[18]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[19]_i_1_n_0 ),
.Q(Q[19]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[1]_i_1_n_0 ),
.Q(Q[1]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[20]_i_1_n_0 ),
.Q(Q[20]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[21]_i_1_n_0 ),
.Q(Q[21]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[22]_i_1_n_0 ),
.Q(Q[22]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[23]_i_1_n_0 ),
.Q(Q[23]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[24]_i_1_n_0 ),
.Q(Q[24]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[25]_i_1_n_0 ),
.Q(Q[25]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[26]_i_1_n_0 ),
.Q(Q[26]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[27]_i_1_n_0 ),
.Q(Q[27]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[28]_i_1_n_0 ),
.Q(Q[28]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[29]_i_1_n_0 ),
.Q(Q[29]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[2]_i_1_n_0 ),
.Q(Q[2]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[30]_i_1_n_0 ),
.Q(Q[30]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[31]_i_2_n_0 ),
.Q(Q[31]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[32]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out[32]_i_1_n_0 ),
.Q(counter_TC),
.R(1'b0));
FDRE \INFERRED_GEN.icount_out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[3]_i_1_n_0 ),
.Q(Q[3]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[4]_i_1_n_0 ),
.Q(Q[4]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[5]_i_1_n_0 ),
.Q(Q[5]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[6]_i_1_n_0 ),
.Q(Q[6]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[7]_i_1_n_0 ),
.Q(Q[7]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[8]_i_1_n_0 ),
.Q(Q[8]),
.R(SR));
FDRE \INFERRED_GEN.icount_out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(\INFERRED_GEN.icount_out[9]_i_1_n_0 ),
.Q(Q[9]),
.R(SR));
LUT2 #(
.INIT(4'h2))
generateOutPre1_i_1
(.I0(counter_TC),
.I1(\counter_TC_Reg_reg[1] ),
.O(generateOutPre1_reg));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry
(.CI(1'b0),
.CO({icount_out0_carry_n_0,icount_out0_carry_n_1,icount_out0_carry_n_2,icount_out0_carry_n_3}),
.CYINIT(Q[0]),
.DI({Q[3:1],icount_out0_carry_i_1_n_0}),
.O({icount_out0_carry_n_4,icount_out0_carry_n_5,icount_out0_carry_n_6,icount_out0_carry_n_7}),
.S({icount_out0_carry_i_2_n_0,icount_out0_carry_i_3_n_0,icount_out0_carry_i_4_n_0,S}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__0
(.CI(icount_out0_carry_n_0),
.CO({icount_out0_carry__0_n_0,icount_out0_carry__0_n_1,icount_out0_carry__0_n_2,icount_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(Q[7:4]),
.O({icount_out0_carry__0_n_4,icount_out0_carry__0_n_5,icount_out0_carry__0_n_6,icount_out0_carry__0_n_7}),
.S({icount_out0_carry__0_i_1_n_0,icount_out0_carry__0_i_2_n_0,icount_out0_carry__0_i_3_n_0,icount_out0_carry__0_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_1
(.I0(Q[7]),
.I1(Q[8]),
.O(icount_out0_carry__0_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_2
(.I0(Q[6]),
.I1(Q[7]),
.O(icount_out0_carry__0_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_3
(.I0(Q[5]),
.I1(Q[6]),
.O(icount_out0_carry__0_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_4
(.I0(Q[4]),
.I1(Q[5]),
.O(icount_out0_carry__0_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__1
(.CI(icount_out0_carry__0_n_0),
.CO({icount_out0_carry__1_n_0,icount_out0_carry__1_n_1,icount_out0_carry__1_n_2,icount_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI(Q[11:8]),
.O({icount_out0_carry__1_n_4,icount_out0_carry__1_n_5,icount_out0_carry__1_n_6,icount_out0_carry__1_n_7}),
.S({icount_out0_carry__1_i_1_n_0,icount_out0_carry__1_i_2_n_0,icount_out0_carry__1_i_3_n_0,icount_out0_carry__1_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_1
(.I0(Q[11]),
.I1(Q[12]),
.O(icount_out0_carry__1_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_2
(.I0(Q[10]),
.I1(Q[11]),
.O(icount_out0_carry__1_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_3
(.I0(Q[9]),
.I1(Q[10]),
.O(icount_out0_carry__1_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_4
(.I0(Q[8]),
.I1(Q[9]),
.O(icount_out0_carry__1_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__2
(.CI(icount_out0_carry__1_n_0),
.CO({icount_out0_carry__2_n_0,icount_out0_carry__2_n_1,icount_out0_carry__2_n_2,icount_out0_carry__2_n_3}),
.CYINIT(1'b0),
.DI(Q[15:12]),
.O({icount_out0_carry__2_n_4,icount_out0_carry__2_n_5,icount_out0_carry__2_n_6,icount_out0_carry__2_n_7}),
.S({icount_out0_carry__2_i_1_n_0,icount_out0_carry__2_i_2_n_0,icount_out0_carry__2_i_3_n_0,icount_out0_carry__2_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_1
(.I0(Q[15]),
.I1(Q[16]),
.O(icount_out0_carry__2_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_2
(.I0(Q[14]),
.I1(Q[15]),
.O(icount_out0_carry__2_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_3
(.I0(Q[13]),
.I1(Q[14]),
.O(icount_out0_carry__2_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_4
(.I0(Q[12]),
.I1(Q[13]),
.O(icount_out0_carry__2_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__3
(.CI(icount_out0_carry__2_n_0),
.CO({icount_out0_carry__3_n_0,icount_out0_carry__3_n_1,icount_out0_carry__3_n_2,icount_out0_carry__3_n_3}),
.CYINIT(1'b0),
.DI(Q[19:16]),
.O({icount_out0_carry__3_n_4,icount_out0_carry__3_n_5,icount_out0_carry__3_n_6,icount_out0_carry__3_n_7}),
.S({icount_out0_carry__3_i_1_n_0,icount_out0_carry__3_i_2_n_0,icount_out0_carry__3_i_3_n_0,icount_out0_carry__3_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_1
(.I0(Q[19]),
.I1(Q[20]),
.O(icount_out0_carry__3_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_2
(.I0(Q[18]),
.I1(Q[19]),
.O(icount_out0_carry__3_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_3
(.I0(Q[17]),
.I1(Q[18]),
.O(icount_out0_carry__3_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_4
(.I0(Q[16]),
.I1(Q[17]),
.O(icount_out0_carry__3_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__4
(.CI(icount_out0_carry__3_n_0),
.CO({icount_out0_carry__4_n_0,icount_out0_carry__4_n_1,icount_out0_carry__4_n_2,icount_out0_carry__4_n_3}),
.CYINIT(1'b0),
.DI(Q[23:20]),
.O({icount_out0_carry__4_n_4,icount_out0_carry__4_n_5,icount_out0_carry__4_n_6,icount_out0_carry__4_n_7}),
.S({icount_out0_carry__4_i_1_n_0,icount_out0_carry__4_i_2_n_0,icount_out0_carry__4_i_3_n_0,icount_out0_carry__4_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_1
(.I0(Q[23]),
.I1(Q[24]),
.O(icount_out0_carry__4_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_2
(.I0(Q[22]),
.I1(Q[23]),
.O(icount_out0_carry__4_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_3
(.I0(Q[21]),
.I1(Q[22]),
.O(icount_out0_carry__4_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_4
(.I0(Q[20]),
.I1(Q[21]),
.O(icount_out0_carry__4_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__5
(.CI(icount_out0_carry__4_n_0),
.CO({icount_out0_carry__5_n_0,icount_out0_carry__5_n_1,icount_out0_carry__5_n_2,icount_out0_carry__5_n_3}),
.CYINIT(1'b0),
.DI(Q[27:24]),
.O({icount_out0_carry__5_n_4,icount_out0_carry__5_n_5,icount_out0_carry__5_n_6,icount_out0_carry__5_n_7}),
.S({icount_out0_carry__5_i_1_n_0,icount_out0_carry__5_i_2_n_0,icount_out0_carry__5_i_3_n_0,icount_out0_carry__5_i_4_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_1
(.I0(Q[27]),
.I1(Q[28]),
.O(icount_out0_carry__5_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_2
(.I0(Q[26]),
.I1(Q[27]),
.O(icount_out0_carry__5_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_3
(.I0(Q[25]),
.I1(Q[26]),
.O(icount_out0_carry__5_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_4
(.I0(Q[24]),
.I1(Q[25]),
.O(icount_out0_carry__5_i_4_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__6
(.CI(icount_out0_carry__5_n_0),
.CO({NLW_icount_out0_carry__6_CO_UNCONNECTED[3],icount_out0_carry__6_n_1,icount_out0_carry__6_n_2,icount_out0_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,Q[30:28]}),
.O({icount_out0_carry__6_n_4,icount_out0_carry__6_n_5,icount_out0_carry__6_n_6,icount_out0_carry__6_n_7}),
.S({icount_out0_carry__6_i_1_n_0,icount_out0_carry__6_i_2_n_0,icount_out0_carry__6_i_3_n_0,icount_out0_carry__6_i_4_n_0}));
LUT1 #(
.INIT(2'h1))
icount_out0_carry__6_i_1
(.I0(Q[31]),
.O(icount_out0_carry__6_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_2
(.I0(Q[30]),
.I1(Q[31]),
.O(icount_out0_carry__6_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_3
(.I0(Q[29]),
.I1(Q[30]),
.O(icount_out0_carry__6_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_4
(.I0(Q[28]),
.I1(Q[29]),
.O(icount_out0_carry__6_i_4_n_0));
LUT1 #(
.INIT(2'h1))
icount_out0_carry_i_1
(.I0(Q[1]),
.O(icount_out0_carry_i_1_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_2
(.I0(Q[3]),
.I1(Q[4]),
.O(icount_out0_carry_i_2_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_3
(.I0(Q[2]),
.I1(Q[3]),
.O(icount_out0_carry_i_3_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_4
(.I0(Q[1]),
.I1(Q[2]),
.O(icount_out0_carry_i_4_n_0));
endmodule
(* ORIG_REF_NAME = "counter_f" *)
module zqynq_lab_1_design_axi_timer_0_0_counter_f_3
(\LOAD_REG_GEN[0].LOAD_REG_I ,
generateOutPre0_reg,
counter_TC,
S,
read_Mux_In,
load_Counter_Reg,
\LOAD_REG_GEN[0].LOAD_REG_I_0 ,
Q,
s_axi_aresetn_0,
E,
s_axi_aclk,
s_axi_aresetn);
output [31:0]\LOAD_REG_GEN[0].LOAD_REG_I ;
output generateOutPre0_reg;
output [0:0]counter_TC;
input [0:0]S;
input [10:0]read_Mux_In;
input [0:0]load_Counter_Reg;
input [20:0]\LOAD_REG_GEN[0].LOAD_REG_I_0 ;
input [0:0]Q;
input s_axi_aresetn_0;
input [0:0]E;
input s_axi_aclk;
input s_axi_aresetn;
wire [0:0]E;
wire \INFERRED_GEN.icount_out[32]_i_1_n_0 ;
wire [31:0]\LOAD_REG_GEN[0].LOAD_REG_I ;
wire [20:0]\LOAD_REG_GEN[0].LOAD_REG_I_0 ;
wire [0:0]Q;
wire [0:0]S;
wire [0:0]counter_TC;
wire generateOutPre0_reg;
wire icount_out0_carry__0_i_1__0_n_0;
wire icount_out0_carry__0_i_2__0_n_0;
wire icount_out0_carry__0_i_3__0_n_0;
wire icount_out0_carry__0_i_4__0_n_0;
wire icount_out0_carry__0_n_0;
wire icount_out0_carry__0_n_1;
wire icount_out0_carry__0_n_2;
wire icount_out0_carry__0_n_3;
wire icount_out0_carry__0_n_4;
wire icount_out0_carry__0_n_5;
wire icount_out0_carry__0_n_6;
wire icount_out0_carry__0_n_7;
wire icount_out0_carry__1_i_1__0_n_0;
wire icount_out0_carry__1_i_2__0_n_0;
wire icount_out0_carry__1_i_3__0_n_0;
wire icount_out0_carry__1_i_4__0_n_0;
wire icount_out0_carry__1_n_0;
wire icount_out0_carry__1_n_1;
wire icount_out0_carry__1_n_2;
wire icount_out0_carry__1_n_3;
wire icount_out0_carry__1_n_4;
wire icount_out0_carry__1_n_5;
wire icount_out0_carry__1_n_6;
wire icount_out0_carry__1_n_7;
wire icount_out0_carry__2_i_1__0_n_0;
wire icount_out0_carry__2_i_2__0_n_0;
wire icount_out0_carry__2_i_3__0_n_0;
wire icount_out0_carry__2_i_4__0_n_0;
wire icount_out0_carry__2_n_0;
wire icount_out0_carry__2_n_1;
wire icount_out0_carry__2_n_2;
wire icount_out0_carry__2_n_3;
wire icount_out0_carry__2_n_4;
wire icount_out0_carry__2_n_5;
wire icount_out0_carry__2_n_6;
wire icount_out0_carry__2_n_7;
wire icount_out0_carry__3_i_1__0_n_0;
wire icount_out0_carry__3_i_2__0_n_0;
wire icount_out0_carry__3_i_3__0_n_0;
wire icount_out0_carry__3_i_4__0_n_0;
wire icount_out0_carry__3_n_0;
wire icount_out0_carry__3_n_1;
wire icount_out0_carry__3_n_2;
wire icount_out0_carry__3_n_3;
wire icount_out0_carry__3_n_4;
wire icount_out0_carry__3_n_5;
wire icount_out0_carry__3_n_6;
wire icount_out0_carry__3_n_7;
wire icount_out0_carry__4_i_1__0_n_0;
wire icount_out0_carry__4_i_2__0_n_0;
wire icount_out0_carry__4_i_3__0_n_0;
wire icount_out0_carry__4_i_4__0_n_0;
wire icount_out0_carry__4_n_0;
wire icount_out0_carry__4_n_1;
wire icount_out0_carry__4_n_2;
wire icount_out0_carry__4_n_3;
wire icount_out0_carry__4_n_4;
wire icount_out0_carry__4_n_5;
wire icount_out0_carry__4_n_6;
wire icount_out0_carry__4_n_7;
wire icount_out0_carry__5_i_1__0_n_0;
wire icount_out0_carry__5_i_2__0_n_0;
wire icount_out0_carry__5_i_3__0_n_0;
wire icount_out0_carry__5_i_4__0_n_0;
wire icount_out0_carry__5_n_0;
wire icount_out0_carry__5_n_1;
wire icount_out0_carry__5_n_2;
wire icount_out0_carry__5_n_3;
wire icount_out0_carry__5_n_4;
wire icount_out0_carry__5_n_5;
wire icount_out0_carry__5_n_6;
wire icount_out0_carry__5_n_7;
wire icount_out0_carry__6_i_1__0_n_0;
wire icount_out0_carry__6_i_2__0_n_0;
wire icount_out0_carry__6_i_3__0_n_0;
wire icount_out0_carry__6_i_4__0_n_0;
wire icount_out0_carry__6_n_1;
wire icount_out0_carry__6_n_2;
wire icount_out0_carry__6_n_3;
wire icount_out0_carry__6_n_4;
wire icount_out0_carry__6_n_5;
wire icount_out0_carry__6_n_6;
wire icount_out0_carry__6_n_7;
wire icount_out0_carry_i_1__0_n_0;
wire icount_out0_carry_i_2__0_n_0;
wire icount_out0_carry_i_3__0_n_0;
wire icount_out0_carry_i_4__0_n_0;
wire icount_out0_carry_n_0;
wire icount_out0_carry_n_1;
wire icount_out0_carry_n_2;
wire icount_out0_carry_n_3;
wire icount_out0_carry_n_4;
wire icount_out0_carry_n_5;
wire icount_out0_carry_n_6;
wire icount_out0_carry_n_7;
wire [0:0]load_Counter_Reg;
wire [31:0]p_1_in;
wire [10:0]read_Mux_In;
wire s_axi_aclk;
wire s_axi_aresetn;
wire s_axi_aresetn_0;
wire [3:3]NLW_icount_out0_carry__6_CO_UNCONNECTED;
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'h8B))
\INFERRED_GEN.icount_out[0]_i_1__0
(.I0(read_Mux_In[0]),
.I1(load_Counter_Reg),
.I2(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[10]_i_1__0
(.I0(read_Mux_In[10]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_6),
.O(p_1_in[10]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[11]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [0]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_5),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[12]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [1]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_4),
.O(p_1_in[12]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[13]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [2]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_7),
.O(p_1_in[13]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[14]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [3]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_6),
.O(p_1_in[14]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[15]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [4]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_5),
.O(p_1_in[15]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[16]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [5]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__2_n_4),
.O(p_1_in[16]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[17]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [6]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_7),
.O(p_1_in[17]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[18]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [7]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_6),
.O(p_1_in[18]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[19]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [8]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_5),
.O(p_1_in[19]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[1]_i_1__0
(.I0(read_Mux_In[1]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_7),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[20]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [9]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__3_n_4),
.O(p_1_in[20]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[21]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [10]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_7),
.O(p_1_in[21]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[22]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [11]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_6),
.O(p_1_in[22]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[23]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [12]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_5),
.O(p_1_in[23]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[24]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [13]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__4_n_4),
.O(p_1_in[24]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[25]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [14]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_7),
.O(p_1_in[25]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[26]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [15]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_6),
.O(p_1_in[26]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[27]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [16]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_5),
.O(p_1_in[27]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[28]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [17]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__5_n_4),
.O(p_1_in[28]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[29]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [18]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_7),
.O(p_1_in[29]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[2]_i_1__0
(.I0(read_Mux_In[2]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_6),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[30]_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [19]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_6),
.O(p_1_in[30]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[31]_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_0 [20]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__6_n_5),
.O(p_1_in[31]));
LUT5 #(
.INIT(32'h0000E200))
\INFERRED_GEN.icount_out[32]_i_1
(.I0(counter_TC),
.I1(E),
.I2(icount_out0_carry__6_n_4),
.I3(s_axi_aresetn),
.I4(load_Counter_Reg),
.O(\INFERRED_GEN.icount_out[32]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[3]_i_1__0
(.I0(read_Mux_In[3]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_5),
.O(p_1_in[3]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[4]_i_1__0
(.I0(read_Mux_In[4]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry_n_4),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[5]_i_1__0
(.I0(read_Mux_In[5]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_7),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[6]_i_1__0
(.I0(read_Mux_In[6]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_6),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[7]_i_1__0
(.I0(read_Mux_In[7]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_5),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[8]_i_1__0
(.I0(read_Mux_In[8]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__0_n_4),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\INFERRED_GEN.icount_out[9]_i_1__0
(.I0(read_Mux_In[9]),
.I1(load_Counter_Reg),
.I2(icount_out0_carry__1_n_7),
.O(p_1_in[9]));
FDRE \INFERRED_GEN.icount_out_reg[0]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[0]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[10]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[10]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[11]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[11]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[12]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[12]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[13]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[13]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[14]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[14]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[15]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[15]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[16]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[16]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[17]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[17]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[18]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[18]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[19]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[19]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[1]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[1]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[20]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[20]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[21]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[21]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[22]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[22]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[23]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[23]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[24]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[24]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[25]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[25]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[26]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[26]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[27]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[27]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[28]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[28]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[29]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[29]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[2]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[2]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[30]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[30]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[31]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[31]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[32]
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out[32]_i_1_n_0 ),
.Q(counter_TC),
.R(1'b0));
FDRE \INFERRED_GEN.icount_out_reg[3]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[3]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[4]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[4]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[5]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[5]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[6]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[6]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[7]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[7]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[8]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[8]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.R(s_axi_aresetn_0));
FDRE \INFERRED_GEN.icount_out_reg[9]
(.C(s_axi_aclk),
.CE(E),
.D(p_1_in[9]),
.Q(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.R(s_axi_aresetn_0));
LUT2 #(
.INIT(4'h2))
generateOutPre0_i_1
(.I0(counter_TC),
.I1(Q),
.O(generateOutPre0_reg));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry
(.CI(1'b0),
.CO({icount_out0_carry_n_0,icount_out0_carry_n_1,icount_out0_carry_n_2,icount_out0_carry_n_3}),
.CYINIT(\LOAD_REG_GEN[0].LOAD_REG_I [0]),
.DI({\LOAD_REG_GEN[0].LOAD_REG_I [3:1],icount_out0_carry_i_1__0_n_0}),
.O({icount_out0_carry_n_4,icount_out0_carry_n_5,icount_out0_carry_n_6,icount_out0_carry_n_7}),
.S({icount_out0_carry_i_2__0_n_0,icount_out0_carry_i_3__0_n_0,icount_out0_carry_i_4__0_n_0,S}));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__0
(.CI(icount_out0_carry_n_0),
.CO({icount_out0_carry__0_n_0,icount_out0_carry__0_n_1,icount_out0_carry__0_n_2,icount_out0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [7:4]),
.O({icount_out0_carry__0_n_4,icount_out0_carry__0_n_5,icount_out0_carry__0_n_6,icount_out0_carry__0_n_7}),
.S({icount_out0_carry__0_i_1__0_n_0,icount_out0_carry__0_i_2__0_n_0,icount_out0_carry__0_i_3__0_n_0,icount_out0_carry__0_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.O(icount_out0_carry__0_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [7]),
.O(icount_out0_carry__0_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [6]),
.O(icount_out0_carry__0_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__0_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [5]),
.O(icount_out0_carry__0_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__1
(.CI(icount_out0_carry__0_n_0),
.CO({icount_out0_carry__1_n_0,icount_out0_carry__1_n_1,icount_out0_carry__1_n_2,icount_out0_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [11:8]),
.O({icount_out0_carry__1_n_4,icount_out0_carry__1_n_5,icount_out0_carry__1_n_6,icount_out0_carry__1_n_7}),
.S({icount_out0_carry__1_i_1__0_n_0,icount_out0_carry__1_i_2__0_n_0,icount_out0_carry__1_i_3__0_n_0,icount_out0_carry__1_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.O(icount_out0_carry__1_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [11]),
.O(icount_out0_carry__1_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [10]),
.O(icount_out0_carry__1_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__1_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [8]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [9]),
.O(icount_out0_carry__1_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__2
(.CI(icount_out0_carry__1_n_0),
.CO({icount_out0_carry__2_n_0,icount_out0_carry__2_n_1,icount_out0_carry__2_n_2,icount_out0_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [15:12]),
.O({icount_out0_carry__2_n_4,icount_out0_carry__2_n_5,icount_out0_carry__2_n_6,icount_out0_carry__2_n_7}),
.S({icount_out0_carry__2_i_1__0_n_0,icount_out0_carry__2_i_2__0_n_0,icount_out0_carry__2_i_3__0_n_0,icount_out0_carry__2_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.O(icount_out0_carry__2_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [15]),
.O(icount_out0_carry__2_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [14]),
.O(icount_out0_carry__2_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__2_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [12]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [13]),
.O(icount_out0_carry__2_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__3
(.CI(icount_out0_carry__2_n_0),
.CO({icount_out0_carry__3_n_0,icount_out0_carry__3_n_1,icount_out0_carry__3_n_2,icount_out0_carry__3_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [19:16]),
.O({icount_out0_carry__3_n_4,icount_out0_carry__3_n_5,icount_out0_carry__3_n_6,icount_out0_carry__3_n_7}),
.S({icount_out0_carry__3_i_1__0_n_0,icount_out0_carry__3_i_2__0_n_0,icount_out0_carry__3_i_3__0_n_0,icount_out0_carry__3_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.O(icount_out0_carry__3_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [19]),
.O(icount_out0_carry__3_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [18]),
.O(icount_out0_carry__3_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__3_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [16]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [17]),
.O(icount_out0_carry__3_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__4
(.CI(icount_out0_carry__3_n_0),
.CO({icount_out0_carry__4_n_0,icount_out0_carry__4_n_1,icount_out0_carry__4_n_2,icount_out0_carry__4_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [23:20]),
.O({icount_out0_carry__4_n_4,icount_out0_carry__4_n_5,icount_out0_carry__4_n_6,icount_out0_carry__4_n_7}),
.S({icount_out0_carry__4_i_1__0_n_0,icount_out0_carry__4_i_2__0_n_0,icount_out0_carry__4_i_3__0_n_0,icount_out0_carry__4_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.O(icount_out0_carry__4_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [23]),
.O(icount_out0_carry__4_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [22]),
.O(icount_out0_carry__4_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__4_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [20]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [21]),
.O(icount_out0_carry__4_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__5
(.CI(icount_out0_carry__4_n_0),
.CO({icount_out0_carry__5_n_0,icount_out0_carry__5_n_1,icount_out0_carry__5_n_2,icount_out0_carry__5_n_3}),
.CYINIT(1'b0),
.DI(\LOAD_REG_GEN[0].LOAD_REG_I [27:24]),
.O({icount_out0_carry__5_n_4,icount_out0_carry__5_n_5,icount_out0_carry__5_n_6,icount_out0_carry__5_n_7}),
.S({icount_out0_carry__5_i_1__0_n_0,icount_out0_carry__5_i_2__0_n_0,icount_out0_carry__5_i_3__0_n_0,icount_out0_carry__5_i_4__0_n_0}));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.O(icount_out0_carry__5_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [27]),
.O(icount_out0_carry__5_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [26]),
.O(icount_out0_carry__5_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__5_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [24]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [25]),
.O(icount_out0_carry__5_i_4__0_n_0));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 icount_out0_carry__6
(.CI(icount_out0_carry__5_n_0),
.CO({NLW_icount_out0_carry__6_CO_UNCONNECTED[3],icount_out0_carry__6_n_1,icount_out0_carry__6_n_2,icount_out0_carry__6_n_3}),
.CYINIT(1'b0),
.DI({1'b0,\LOAD_REG_GEN[0].LOAD_REG_I [30:28]}),
.O({icount_out0_carry__6_n_4,icount_out0_carry__6_n_5,icount_out0_carry__6_n_6,icount_out0_carry__6_n_7}),
.S({icount_out0_carry__6_i_1__0_n_0,icount_out0_carry__6_i_2__0_n_0,icount_out0_carry__6_i_3__0_n_0,icount_out0_carry__6_i_4__0_n_0}));
LUT1 #(
.INIT(2'h1))
icount_out0_carry__6_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.O(icount_out0_carry__6_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [31]),
.O(icount_out0_carry__6_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [30]),
.O(icount_out0_carry__6_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry__6_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [28]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [29]),
.O(icount_out0_carry__6_i_4__0_n_0));
LUT1 #(
.INIT(2'h1))
icount_out0_carry_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.O(icount_out0_carry_i_1__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_2__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [4]),
.O(icount_out0_carry_i_2__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_3__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [3]),
.O(icount_out0_carry_i_3__0_n_0));
LUT2 #(
.INIT(4'h9))
icount_out0_carry_i_4__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I [1]),
.I1(\LOAD_REG_GEN[0].LOAD_REG_I [2]),
.O(icount_out0_carry_i_4__0_n_0));
endmodule
(* ORIG_REF_NAME = "mux_onehot_f" *)
module zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f
(D,
Bus_RNW_reg_reg,
\INFERRED_GEN.icount_out_reg[31] ,
Bus_RNW_reg_reg_0,
\INFERRED_GEN.icount_out_reg[30] ,
Bus_RNW_reg_reg_1,
\INFERRED_GEN.icount_out_reg[29] ,
Bus_RNW_reg_reg_2,
\INFERRED_GEN.icount_out_reg[28] ,
Bus_RNW_reg_reg_3,
\INFERRED_GEN.icount_out_reg[27] ,
Bus_RNW_reg_reg_4,
\INFERRED_GEN.icount_out_reg[26] ,
Bus_RNW_reg_reg_5,
\INFERRED_GEN.icount_out_reg[25] ,
Bus_RNW_reg_reg_6,
\INFERRED_GEN.icount_out_reg[24] ,
Bus_RNW_reg_reg_7,
\INFERRED_GEN.icount_out_reg[23] ,
Bus_RNW_reg_reg_8,
\INFERRED_GEN.icount_out_reg[22] ,
Bus_RNW_reg_reg_9,
\INFERRED_GEN.icount_out_reg[21] ,
Bus_RNW_reg_reg_10,
\INFERRED_GEN.icount_out_reg[20] ,
Bus_RNW_reg_reg_11,
\INFERRED_GEN.icount_out_reg[19] ,
Bus_RNW_reg_reg_12,
\INFERRED_GEN.icount_out_reg[18] ,
Bus_RNW_reg_reg_13,
\INFERRED_GEN.icount_out_reg[17] ,
Bus_RNW_reg_reg_14,
\INFERRED_GEN.icount_out_reg[16] ,
Bus_RNW_reg_reg_15,
\INFERRED_GEN.icount_out_reg[15] ,
Bus_RNW_reg_reg_16,
\INFERRED_GEN.icount_out_reg[14] ,
Bus_RNW_reg_reg_17,
\INFERRED_GEN.icount_out_reg[13] ,
Bus_RNW_reg_reg_18,
\INFERRED_GEN.icount_out_reg[12] ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[11] ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[10] ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[9] ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[8] ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[7] ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[6] ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[5] ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[4] ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[3] ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[2] ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[1] ,
\LOAD_REG_GEN[31].LOAD_REG_I ,
\INFERRED_GEN.icount_out_reg[0] );
output [31:0]D;
input Bus_RNW_reg_reg;
input \INFERRED_GEN.icount_out_reg[31] ;
input Bus_RNW_reg_reg_0;
input \INFERRED_GEN.icount_out_reg[30] ;
input Bus_RNW_reg_reg_1;
input \INFERRED_GEN.icount_out_reg[29] ;
input Bus_RNW_reg_reg_2;
input \INFERRED_GEN.icount_out_reg[28] ;
input Bus_RNW_reg_reg_3;
input \INFERRED_GEN.icount_out_reg[27] ;
input Bus_RNW_reg_reg_4;
input \INFERRED_GEN.icount_out_reg[26] ;
input Bus_RNW_reg_reg_5;
input \INFERRED_GEN.icount_out_reg[25] ;
input Bus_RNW_reg_reg_6;
input \INFERRED_GEN.icount_out_reg[24] ;
input Bus_RNW_reg_reg_7;
input \INFERRED_GEN.icount_out_reg[23] ;
input Bus_RNW_reg_reg_8;
input \INFERRED_GEN.icount_out_reg[22] ;
input Bus_RNW_reg_reg_9;
input \INFERRED_GEN.icount_out_reg[21] ;
input Bus_RNW_reg_reg_10;
input \INFERRED_GEN.icount_out_reg[20] ;
input Bus_RNW_reg_reg_11;
input \INFERRED_GEN.icount_out_reg[19] ;
input Bus_RNW_reg_reg_12;
input \INFERRED_GEN.icount_out_reg[18] ;
input Bus_RNW_reg_reg_13;
input \INFERRED_GEN.icount_out_reg[17] ;
input Bus_RNW_reg_reg_14;
input \INFERRED_GEN.icount_out_reg[16] ;
input Bus_RNW_reg_reg_15;
input \INFERRED_GEN.icount_out_reg[15] ;
input Bus_RNW_reg_reg_16;
input \INFERRED_GEN.icount_out_reg[14] ;
input Bus_RNW_reg_reg_17;
input \INFERRED_GEN.icount_out_reg[13] ;
input Bus_RNW_reg_reg_18;
input \INFERRED_GEN.icount_out_reg[12] ;
input \LOAD_REG_GEN[20].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \LOAD_REG_GEN[21].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \LOAD_REG_GEN[22].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \LOAD_REG_GEN[23].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \LOAD_REG_GEN[24].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \LOAD_REG_GEN[25].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \LOAD_REG_GEN[26].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \LOAD_REG_GEN[27].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \LOAD_REG_GEN[28].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \LOAD_REG_GEN[29].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \LOAD_REG_GEN[30].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \LOAD_REG_GEN[31].LOAD_REG_I ;
input \INFERRED_GEN.icount_out_reg[0] ;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_10;
wire Bus_RNW_reg_reg_11;
wire Bus_RNW_reg_reg_12;
wire Bus_RNW_reg_reg_13;
wire Bus_RNW_reg_reg_14;
wire Bus_RNW_reg_reg_15;
wire Bus_RNW_reg_reg_16;
wire Bus_RNW_reg_reg_17;
wire Bus_RNW_reg_reg_18;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire Bus_RNW_reg_reg_7;
wire Bus_RNW_reg_reg_8;
wire Bus_RNW_reg_reg_9;
wire [31:0]D;
wire \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 ;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[31] ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire cyout_1;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED ;
wire [3:0]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED ;
wire [3:2]\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED ;
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[31],cyout_1}),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[0].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[31] ,Bus_RNW_reg_reg}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[21],\GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[10].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[21] ,Bus_RNW_reg_reg_9}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[20],\GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[11].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[20] ,Bus_RNW_reg_reg_10}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[19],\GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[12].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[19] ,Bus_RNW_reg_reg_11}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[18],\GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[13].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[18] ,Bus_RNW_reg_reg_12}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[17],\GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[14].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[17] ,Bus_RNW_reg_reg_13}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[16],\GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[15].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[16] ,Bus_RNW_reg_reg_14}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[15],\GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[16].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[15] ,Bus_RNW_reg_reg_15}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[14],\GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[17].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[14] ,Bus_RNW_reg_reg_16}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[13],\GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[18].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[13] ,Bus_RNW_reg_reg_17}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[12],\GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[19].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[12] ,Bus_RNW_reg_reg_18}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[30],\GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[1].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[30] ,Bus_RNW_reg_reg_0}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[11],\GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[20].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[11] ,\LOAD_REG_GEN[20].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[10],\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[10] ,\LOAD_REG_GEN[21].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[9],\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[9] ,\LOAD_REG_GEN[22].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[8],\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[8] ,\LOAD_REG_GEN[23].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[7],\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[7] ,\LOAD_REG_GEN[24].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[6],\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[6] ,\LOAD_REG_GEN[25].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[5],\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[5] ,\LOAD_REG_GEN[26].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[4],\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[4] ,\LOAD_REG_GEN[27].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[3],\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[3] ,\LOAD_REG_GEN[28].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[2],\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[2] ,\LOAD_REG_GEN[29].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[29],\GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[2].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[29] ,Bus_RNW_reg_reg_1}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[1],\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[1] ,\LOAD_REG_GEN[30].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[0],\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[0] ,\LOAD_REG_GEN[31].LOAD_REG_I }));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[28],\GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[3].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[28] ,Bus_RNW_reg_reg_2}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[27],\GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[4].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[27] ,Bus_RNW_reg_reg_3}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[26],\GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[5].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[26] ,Bus_RNW_reg_reg_4}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[25],\GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[6].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[25] ,Bus_RNW_reg_reg_5}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[24],\GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[7].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[24] ,Bus_RNW_reg_reg_6}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[23],\GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[8].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[23] ,Bus_RNW_reg_reg_7}));
(* BOX_TYPE = "PRIMITIVE" *)
(* XILINX_LEGACY_PRIM = "(MUXCY,XORCY)" *)
CARRY4 \GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4
(.CI(1'b0),
.CO({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_CO_UNCONNECTED [3:2],D[22],\GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_n_0 }),
.CYINIT(1'b0),
.DI({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_DI_UNCONNECTED [3:2],1'b1,1'b1}),
.O(\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_O_UNCONNECTED [3:0]),
.S({\NLW_GEN.DATA_WIDTH_GEN[9].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_CARRY4_S_UNCONNECTED [3:2],\INFERRED_GEN.icount_out_reg[22] ,Bus_RNW_reg_reg_8}));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f
(ce_expnd_i_7,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_7;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_7;
LUT4 #(
.INIT(16'h0010))
CS
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [1]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_7));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized1
(ce_expnd_i_5,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_5;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_5;
LUT4 #(
.INIT(16'h1000))
CS
(.I0(\bus2ip_addr_i_reg[4] [2]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [1]),
.O(ce_expnd_i_5));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized3
(ce_expnd_i_3,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_3;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_3;
LUT4 #(
.INIT(16'h1000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(\bus2ip_addr_i_reg[4] [2]),
.I3(Q),
.O(ce_expnd_i_3));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized4
(ce_expnd_i_2,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_2;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_2;
LUT4 #(
.INIT(16'h4000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [2]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [0]),
.O(ce_expnd_i_2));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized5
(ce_expnd_i_1,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_1;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_1;
LUT4 #(
.INIT(16'h4000))
CS
(.I0(\bus2ip_addr_i_reg[4] [0]),
.I1(\bus2ip_addr_i_reg[4] [2]),
.I2(Q),
.I3(\bus2ip_addr_i_reg[4] [1]),
.O(ce_expnd_i_1));
endmodule
(* ORIG_REF_NAME = "pselect_f" *)
module zqynq_lab_1_design_axi_timer_0_0_pselect_f__parameterized6
(ce_expnd_i_0,
\bus2ip_addr_i_reg[4] ,
Q);
output ce_expnd_i_0;
input [2:0]\bus2ip_addr_i_reg[4] ;
input Q;
wire Q;
wire [2:0]\bus2ip_addr_i_reg[4] ;
wire ce_expnd_i_0;
LUT4 #(
.INIT(16'h8000))
CS
(.I0(\bus2ip_addr_i_reg[4] [1]),
.I1(\bus2ip_addr_i_reg[4] [0]),
.I2(\bus2ip_addr_i_reg[4] [2]),
.I3(Q),
.O(ce_expnd_i_0));
endmodule
(* ORIG_REF_NAME = "slave_attachment" *)
module zqynq_lab_1_design_axi_timer_0_0_slave_attachment
(\LOAD_REG_GEN[31].LOAD_REG_I ,
\TCSR0_GENERATE[23].TCSR0_FF_I ,
s_axi_rvalid,
s_axi_bvalid,
\s_axi_rdata_i_reg[12]_0 ,
\s_axi_rdata_i_reg[13]_0 ,
\s_axi_rdata_i_reg[14]_0 ,
\s_axi_rdata_i_reg[15]_0 ,
\s_axi_rdata_i_reg[16]_0 ,
\s_axi_rdata_i_reg[17]_0 ,
\s_axi_rdata_i_reg[18]_0 ,
\s_axi_rdata_i_reg[19]_0 ,
\s_axi_rdata_i_reg[20]_0 ,
\s_axi_rdata_i_reg[21]_0 ,
\s_axi_rdata_i_reg[22]_0 ,
\s_axi_rdata_i_reg[23]_0 ,
\s_axi_rdata_i_reg[24]_0 ,
\s_axi_rdata_i_reg[25]_0 ,
\s_axi_rdata_i_reg[26]_0 ,
\s_axi_rdata_i_reg[27]_0 ,
\s_axi_rdata_i_reg[28]_0 ,
\s_axi_rdata_i_reg[29]_0 ,
\s_axi_rdata_i_reg[30]_0 ,
\s_axi_rdata_i_reg[31]_0 ,
pair0_Select,
s_axi_wready,
s_axi_arready,
\s_axi_rdata_i_reg[11]_0 ,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\LOAD_REG_GEN[31].LOAD_REG_I_0 ,
\LOAD_REG_GEN[30].LOAD_REG_I ,
\LOAD_REG_GEN[29].LOAD_REG_I ,
\LOAD_REG_GEN[28].LOAD_REG_I ,
\LOAD_REG_GEN[27].LOAD_REG_I ,
\LOAD_REG_GEN[26].LOAD_REG_I ,
\LOAD_REG_GEN[25].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[23].LOAD_REG_I ,
\LOAD_REG_GEN[22].LOAD_REG_I ,
\LOAD_REG_GEN[21].LOAD_REG_I ,
\LOAD_REG_GEN[20].LOAD_REG_I ,
\LOAD_REG_GEN[19].LOAD_REG_I ,
\LOAD_REG_GEN[18].LOAD_REG_I ,
\LOAD_REG_GEN[17].LOAD_REG_I ,
\LOAD_REG_GEN[16].LOAD_REG_I ,
\LOAD_REG_GEN[15].LOAD_REG_I ,
\LOAD_REG_GEN[14].LOAD_REG_I ,
\LOAD_REG_GEN[13].LOAD_REG_I ,
\LOAD_REG_GEN[12].LOAD_REG_I ,
\LOAD_REG_GEN[11].LOAD_REG_I ,
\LOAD_REG_GEN[10].LOAD_REG_I ,
\LOAD_REG_GEN[9].LOAD_REG_I ,
\LOAD_REG_GEN[8].LOAD_REG_I ,
\LOAD_REG_GEN[7].LOAD_REG_I ,
\LOAD_REG_GEN[6].LOAD_REG_I ,
\LOAD_REG_GEN[5].LOAD_REG_I ,
\LOAD_REG_GEN[4].LOAD_REG_I ,
\LOAD_REG_GEN[3].LOAD_REG_I ,
\LOAD_REG_GEN[2].LOAD_REG_I ,
\LOAD_REG_GEN[1].LOAD_REG_I ,
D_0,
bus2ip_wrce__0,
bus2ip_wrce,
\LOAD_REG_GEN[31].LOAD_REG_I_1 ,
\LOAD_REG_GEN[30].LOAD_REG_I_0 ,
\LOAD_REG_GEN[29].LOAD_REG_I_0 ,
\LOAD_REG_GEN[28].LOAD_REG_I_0 ,
\LOAD_REG_GEN[27].LOAD_REG_I_0 ,
\LOAD_REG_GEN[26].LOAD_REG_I_0 ,
\LOAD_REG_GEN[25].LOAD_REG_I_0 ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\LOAD_REG_GEN[23].LOAD_REG_I_0 ,
\LOAD_REG_GEN[22].LOAD_REG_I_0 ,
\LOAD_REG_GEN[21].LOAD_REG_I_0 ,
\LOAD_REG_GEN[20].LOAD_REG_I_0 ,
\LOAD_REG_GEN[19].LOAD_REG_I_0 ,
\LOAD_REG_GEN[18].LOAD_REG_I_0 ,
\LOAD_REG_GEN[17].LOAD_REG_I_0 ,
\LOAD_REG_GEN[16].LOAD_REG_I_0 ,
\LOAD_REG_GEN[15].LOAD_REG_I_0 ,
\LOAD_REG_GEN[14].LOAD_REG_I_0 ,
\LOAD_REG_GEN[13].LOAD_REG_I_0 ,
\LOAD_REG_GEN[12].LOAD_REG_I_0 ,
\LOAD_REG_GEN[11].LOAD_REG_I_0 ,
\LOAD_REG_GEN[10].LOAD_REG_I_0 ,
\LOAD_REG_GEN[9].LOAD_REG_I_0 ,
\LOAD_REG_GEN[8].LOAD_REG_I_0 ,
\LOAD_REG_GEN[7].LOAD_REG_I_0 ,
\LOAD_REG_GEN[6].LOAD_REG_I_0 ,
\LOAD_REG_GEN[5].LOAD_REG_I_0 ,
\LOAD_REG_GEN[4].LOAD_REG_I_0 ,
\LOAD_REG_GEN[3].LOAD_REG_I_0 ,
\LOAD_REG_GEN[2].LOAD_REG_I_0 ,
\LOAD_REG_GEN[1].LOAD_REG_I_0 ,
D_1,
s_axi_rvalid_i_reg_0,
s_axi_rvalid_i_reg_1,
s_axi_rvalid_i_reg_2,
\TCSR0_GENERATE[23].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I ,
\s_axi_rdata_i_reg[10]_0 ,
\s_axi_rdata_i_reg[0]_0 ,
\s_axi_rdata_i_reg[0]_1 ,
READ_DONE0_I,
READ_DONE1_I,
s_axi_rdata,
bus2ip_reset,
s_axi_aclk,
read_Mux_In,
s_axi_aresetn,
s_axi_arvalid,
s_axi_awvalid,
s_axi_wvalid,
s_axi_araddr,
s_axi_awaddr,
s_axi_rready,
s_axi_bready,
s_axi_wdata,
D_2,
read_done1,
D);
output \LOAD_REG_GEN[31].LOAD_REG_I ;
output \TCSR0_GENERATE[23].TCSR0_FF_I ;
output s_axi_rvalid;
output s_axi_bvalid;
output \s_axi_rdata_i_reg[12]_0 ;
output \s_axi_rdata_i_reg[13]_0 ;
output \s_axi_rdata_i_reg[14]_0 ;
output \s_axi_rdata_i_reg[15]_0 ;
output \s_axi_rdata_i_reg[16]_0 ;
output \s_axi_rdata_i_reg[17]_0 ;
output \s_axi_rdata_i_reg[18]_0 ;
output \s_axi_rdata_i_reg[19]_0 ;
output \s_axi_rdata_i_reg[20]_0 ;
output \s_axi_rdata_i_reg[21]_0 ;
output \s_axi_rdata_i_reg[22]_0 ;
output \s_axi_rdata_i_reg[23]_0 ;
output \s_axi_rdata_i_reg[24]_0 ;
output \s_axi_rdata_i_reg[25]_0 ;
output \s_axi_rdata_i_reg[26]_0 ;
output \s_axi_rdata_i_reg[27]_0 ;
output \s_axi_rdata_i_reg[28]_0 ;
output \s_axi_rdata_i_reg[29]_0 ;
output \s_axi_rdata_i_reg[30]_0 ;
output \s_axi_rdata_i_reg[31]_0 ;
output pair0_Select;
output s_axi_wready;
output s_axi_arready;
output \s_axi_rdata_i_reg[11]_0 ;
output \TCSR0_GENERATE[24].TCSR0_FF_I ;
output \TCSR1_GENERATE[24].TCSR1_FF_I ;
output \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[30].LOAD_REG_I ;
output \LOAD_REG_GEN[29].LOAD_REG_I ;
output \LOAD_REG_GEN[28].LOAD_REG_I ;
output \LOAD_REG_GEN[27].LOAD_REG_I ;
output \LOAD_REG_GEN[26].LOAD_REG_I ;
output \LOAD_REG_GEN[25].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[23].LOAD_REG_I ;
output \LOAD_REG_GEN[22].LOAD_REG_I ;
output \LOAD_REG_GEN[21].LOAD_REG_I ;
output \LOAD_REG_GEN[20].LOAD_REG_I ;
output \LOAD_REG_GEN[19].LOAD_REG_I ;
output \LOAD_REG_GEN[18].LOAD_REG_I ;
output \LOAD_REG_GEN[17].LOAD_REG_I ;
output \LOAD_REG_GEN[16].LOAD_REG_I ;
output \LOAD_REG_GEN[15].LOAD_REG_I ;
output \LOAD_REG_GEN[14].LOAD_REG_I ;
output \LOAD_REG_GEN[13].LOAD_REG_I ;
output \LOAD_REG_GEN[12].LOAD_REG_I ;
output \LOAD_REG_GEN[11].LOAD_REG_I ;
output \LOAD_REG_GEN[10].LOAD_REG_I ;
output \LOAD_REG_GEN[9].LOAD_REG_I ;
output \LOAD_REG_GEN[8].LOAD_REG_I ;
output \LOAD_REG_GEN[7].LOAD_REG_I ;
output \LOAD_REG_GEN[6].LOAD_REG_I ;
output \LOAD_REG_GEN[5].LOAD_REG_I ;
output \LOAD_REG_GEN[4].LOAD_REG_I ;
output \LOAD_REG_GEN[3].LOAD_REG_I ;
output \LOAD_REG_GEN[2].LOAD_REG_I ;
output \LOAD_REG_GEN[1].LOAD_REG_I ;
output D_0;
output [0:0]bus2ip_wrce__0;
output [1:0]bus2ip_wrce;
output \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
output \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
output \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
output D_1;
output s_axi_rvalid_i_reg_0;
output s_axi_rvalid_i_reg_1;
output s_axi_rvalid_i_reg_2;
output \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I ;
output \s_axi_rdata_i_reg[10]_0 ;
output \s_axi_rdata_i_reg[0]_0 ;
output \s_axi_rdata_i_reg[0]_1 ;
output READ_DONE0_I;
output READ_DONE1_I;
output [31:0]s_axi_rdata;
input bus2ip_reset;
input s_axi_aclk;
input [87:0]read_Mux_In;
input s_axi_aresetn;
input s_axi_arvalid;
input s_axi_awvalid;
input s_axi_wvalid;
input [2:0]s_axi_araddr;
input [2:0]s_axi_awaddr;
input s_axi_rready;
input s_axi_bready;
input [31:0]s_axi_wdata;
input D_2;
input read_done1;
input [31:0]D;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire [5:0]\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ;
wire I_DECODER_n_100;
wire I_DECODER_n_101;
wire I_DECODER_n_25;
wire I_DECODER_n_26;
wire \LOAD_REG_GEN[10].LOAD_REG_I ;
wire \LOAD_REG_GEN[10].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[11].LOAD_REG_I ;
wire \LOAD_REG_GEN[11].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[12].LOAD_REG_I ;
wire \LOAD_REG_GEN[12].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[13].LOAD_REG_I ;
wire \LOAD_REG_GEN[13].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[14].LOAD_REG_I ;
wire \LOAD_REG_GEN[14].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[15].LOAD_REG_I ;
wire \LOAD_REG_GEN[15].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[16].LOAD_REG_I ;
wire \LOAD_REG_GEN[16].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[17].LOAD_REG_I ;
wire \LOAD_REG_GEN[17].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[18].LOAD_REG_I ;
wire \LOAD_REG_GEN[18].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[19].LOAD_REG_I ;
wire \LOAD_REG_GEN[19].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[1].LOAD_REG_I ;
wire \LOAD_REG_GEN[1].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire \LOAD_REG_GEN[20].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[21].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[22].LOAD_REG_I ;
wire \LOAD_REG_GEN[22].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[23].LOAD_REG_I ;
wire \LOAD_REG_GEN[23].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[25].LOAD_REG_I ;
wire \LOAD_REG_GEN[25].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[26].LOAD_REG_I ;
wire \LOAD_REG_GEN[26].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[27].LOAD_REG_I ;
wire \LOAD_REG_GEN[27].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[28].LOAD_REG_I ;
wire \LOAD_REG_GEN[28].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[29].LOAD_REG_I ;
wire \LOAD_REG_GEN[29].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[2].LOAD_REG_I ;
wire \LOAD_REG_GEN[2].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[30].LOAD_REG_I ;
wire \LOAD_REG_GEN[30].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[31].LOAD_REG_I_1 ;
wire \LOAD_REG_GEN[3].LOAD_REG_I ;
wire \LOAD_REG_GEN[3].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[4].LOAD_REG_I ;
wire \LOAD_REG_GEN[4].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[5].LOAD_REG_I ;
wire \LOAD_REG_GEN[5].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[6].LOAD_REG_I ;
wire \LOAD_REG_GEN[6].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[7].LOAD_REG_I ;
wire \LOAD_REG_GEN[7].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[8].LOAD_REG_I ;
wire \LOAD_REG_GEN[8].LOAD_REG_I_0 ;
wire \LOAD_REG_GEN[9].LOAD_REG_I ;
wire \LOAD_REG_GEN[9].LOAD_REG_I_0 ;
wire READ_DONE0_I;
wire READ_DONE1_I;
wire \TCSR0_GENERATE[23].TCSR0_FF_I ;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire [0:2]bus2ip_addr;
wire \bus2ip_addr_i[2]_i_1_n_0 ;
wire \bus2ip_addr_i[3]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_1_n_0 ;
wire \bus2ip_addr_i[4]_i_2_n_0 ;
wire bus2ip_reset;
wire bus2ip_rnw_i;
wire bus2ip_rnw_i06_out;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire clear;
wire is_read;
wire is_read_i_1_n_0;
wire is_write;
wire is_write_i_1_n_0;
wire is_write_reg_n_0;
wire pair0_Select;
wire [5:0]plusOp;
wire [87:0]read_Mux_In;
wire read_done1;
wire rst;
wire s_axi_aclk;
wire [2:0]s_axi_araddr;
wire s_axi_aresetn;
wire s_axi_arready;
wire s_axi_arvalid;
wire [2:0]s_axi_awaddr;
wire s_axi_awvalid;
wire s_axi_bready;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire \s_axi_rdata_i[31]_i_1_n_0 ;
wire \s_axi_rdata_i_reg[0]_0 ;
wire \s_axi_rdata_i_reg[0]_1 ;
wire \s_axi_rdata_i_reg[10]_0 ;
wire \s_axi_rdata_i_reg[11]_0 ;
wire \s_axi_rdata_i_reg[12]_0 ;
wire \s_axi_rdata_i_reg[13]_0 ;
wire \s_axi_rdata_i_reg[14]_0 ;
wire \s_axi_rdata_i_reg[15]_0 ;
wire \s_axi_rdata_i_reg[16]_0 ;
wire \s_axi_rdata_i_reg[17]_0 ;
wire \s_axi_rdata_i_reg[18]_0 ;
wire \s_axi_rdata_i_reg[19]_0 ;
wire \s_axi_rdata_i_reg[20]_0 ;
wire \s_axi_rdata_i_reg[21]_0 ;
wire \s_axi_rdata_i_reg[22]_0 ;
wire \s_axi_rdata_i_reg[23]_0 ;
wire \s_axi_rdata_i_reg[24]_0 ;
wire \s_axi_rdata_i_reg[25]_0 ;
wire \s_axi_rdata_i_reg[26]_0 ;
wire \s_axi_rdata_i_reg[27]_0 ;
wire \s_axi_rdata_i_reg[28]_0 ;
wire \s_axi_rdata_i_reg[29]_0 ;
wire \s_axi_rdata_i_reg[30]_0 ;
wire \s_axi_rdata_i_reg[31]_0 ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_axi_rvalid_i_reg_0;
wire s_axi_rvalid_i_reg_1;
wire s_axi_rvalid_i_reg_2;
wire [31:0]s_axi_wdata;
wire s_axi_wready;
wire s_axi_wvalid;
wire start2;
wire start2_i_1_n_0;
wire [1:0]state;
wire state1__2;
wire \state[1]_i_3_n_0 ;
LUT1 #(
.INIT(2'h1))
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.O(plusOp[0]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT2 #(
.INIT(4'h6))
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.O(plusOp[1]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h78))
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.O(plusOp[2]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'h7F80))
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.O(plusOp[3]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT5 #(
.INIT(32'h7FFF8000))
\INCLUDE_DPHASE_TIMER.dpto_cnt[4]_i_1
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.O(plusOp[4]));
LUT2 #(
.INIT(4'h9))
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(clear));
LUT6 #(
.INIT(64'h7FFFFFFF80000000))
\INCLUDE_DPHASE_TIMER.dpto_cnt[5]_i_2
(.I0(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.I1(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.I2(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.I3(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.I4(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.I5(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]),
.O(plusOp[5]));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[0]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [0]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[1]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [1]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[2]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [2]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[3]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [3]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[4]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[4]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [4]),
.R(clear));
FDRE \INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5]
(.C(s_axi_aclk),
.CE(1'b1),
.D(plusOp[5]),
.Q(\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 [5]),
.R(clear));
zqynq_lab_1_design_axi_timer_0_0_address_decoder I_DECODER
(.D({I_DECODER_n_25,I_DECODER_n_26}),
.D_0(D_0),
.D_1(D_1),
.D_2(D_2),
.\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[5] (\INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0 ),
.\LOAD_REG_GEN[10].LOAD_REG_I (\LOAD_REG_GEN[10].LOAD_REG_I ),
.\LOAD_REG_GEN[10].LOAD_REG_I_0 (\LOAD_REG_GEN[10].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[11].LOAD_REG_I (\LOAD_REG_GEN[11].LOAD_REG_I ),
.\LOAD_REG_GEN[11].LOAD_REG_I_0 (\LOAD_REG_GEN[11].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[12].LOAD_REG_I (\LOAD_REG_GEN[12].LOAD_REG_I ),
.\LOAD_REG_GEN[12].LOAD_REG_I_0 (\LOAD_REG_GEN[12].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[13].LOAD_REG_I (\LOAD_REG_GEN[13].LOAD_REG_I ),
.\LOAD_REG_GEN[13].LOAD_REG_I_0 (\LOAD_REG_GEN[13].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[14].LOAD_REG_I (\LOAD_REG_GEN[14].LOAD_REG_I ),
.\LOAD_REG_GEN[14].LOAD_REG_I_0 (\LOAD_REG_GEN[14].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[15].LOAD_REG_I (\LOAD_REG_GEN[15].LOAD_REG_I ),
.\LOAD_REG_GEN[15].LOAD_REG_I_0 (\LOAD_REG_GEN[15].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[16].LOAD_REG_I (\LOAD_REG_GEN[16].LOAD_REG_I ),
.\LOAD_REG_GEN[16].LOAD_REG_I_0 (\LOAD_REG_GEN[16].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[17].LOAD_REG_I (\LOAD_REG_GEN[17].LOAD_REG_I ),
.\LOAD_REG_GEN[17].LOAD_REG_I_0 (\LOAD_REG_GEN[17].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[18].LOAD_REG_I (\LOAD_REG_GEN[18].LOAD_REG_I ),
.\LOAD_REG_GEN[18].LOAD_REG_I_0 (\LOAD_REG_GEN[18].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[19].LOAD_REG_I (\LOAD_REG_GEN[19].LOAD_REG_I ),
.\LOAD_REG_GEN[19].LOAD_REG_I_0 (\LOAD_REG_GEN[19].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[1].LOAD_REG_I (\LOAD_REG_GEN[1].LOAD_REG_I ),
.\LOAD_REG_GEN[1].LOAD_REG_I_0 (\LOAD_REG_GEN[1].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[20].LOAD_REG_I_0 (\LOAD_REG_GEN[20].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[21].LOAD_REG_I (\LOAD_REG_GEN[21].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I_0 (\LOAD_REG_GEN[21].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[22].LOAD_REG_I (\LOAD_REG_GEN[22].LOAD_REG_I ),
.\LOAD_REG_GEN[22].LOAD_REG_I_0 (\LOAD_REG_GEN[22].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[23].LOAD_REG_I (\LOAD_REG_GEN[23].LOAD_REG_I ),
.\LOAD_REG_GEN[23].LOAD_REG_I_0 (\LOAD_REG_GEN[23].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[24].LOAD_REG_I (\LOAD_REG_GEN[24].LOAD_REG_I ),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (\LOAD_REG_GEN[24].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[25].LOAD_REG_I (\LOAD_REG_GEN[25].LOAD_REG_I ),
.\LOAD_REG_GEN[25].LOAD_REG_I_0 (\LOAD_REG_GEN[25].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[26].LOAD_REG_I (\LOAD_REG_GEN[26].LOAD_REG_I ),
.\LOAD_REG_GEN[26].LOAD_REG_I_0 (\LOAD_REG_GEN[26].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[27].LOAD_REG_I (\LOAD_REG_GEN[27].LOAD_REG_I ),
.\LOAD_REG_GEN[27].LOAD_REG_I_0 (\LOAD_REG_GEN[27].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[28].LOAD_REG_I (\LOAD_REG_GEN[28].LOAD_REG_I ),
.\LOAD_REG_GEN[28].LOAD_REG_I_0 (\LOAD_REG_GEN[28].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[29].LOAD_REG_I (\LOAD_REG_GEN[29].LOAD_REG_I ),
.\LOAD_REG_GEN[29].LOAD_REG_I_0 (\LOAD_REG_GEN[29].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[2].LOAD_REG_I (\LOAD_REG_GEN[2].LOAD_REG_I ),
.\LOAD_REG_GEN[2].LOAD_REG_I_0 (\LOAD_REG_GEN[2].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[30].LOAD_REG_I (\LOAD_REG_GEN[30].LOAD_REG_I ),
.\LOAD_REG_GEN[30].LOAD_REG_I_0 (\LOAD_REG_GEN[30].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I (\LOAD_REG_GEN[31].LOAD_REG_I ),
.\LOAD_REG_GEN[31].LOAD_REG_I_0 (\LOAD_REG_GEN[31].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[31].LOAD_REG_I_1 (\LOAD_REG_GEN[31].LOAD_REG_I_1 ),
.\LOAD_REG_GEN[3].LOAD_REG_I (\LOAD_REG_GEN[3].LOAD_REG_I ),
.\LOAD_REG_GEN[3].LOAD_REG_I_0 (\LOAD_REG_GEN[3].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[4].LOAD_REG_I (\LOAD_REG_GEN[4].LOAD_REG_I ),
.\LOAD_REG_GEN[4].LOAD_REG_I_0 (\LOAD_REG_GEN[4].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[5].LOAD_REG_I (\LOAD_REG_GEN[5].LOAD_REG_I ),
.\LOAD_REG_GEN[5].LOAD_REG_I_0 (\LOAD_REG_GEN[5].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[6].LOAD_REG_I (\LOAD_REG_GEN[6].LOAD_REG_I ),
.\LOAD_REG_GEN[6].LOAD_REG_I_0 (\LOAD_REG_GEN[6].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[7].LOAD_REG_I (\LOAD_REG_GEN[7].LOAD_REG_I ),
.\LOAD_REG_GEN[7].LOAD_REG_I_0 (\LOAD_REG_GEN[7].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[8].LOAD_REG_I (\LOAD_REG_GEN[8].LOAD_REG_I ),
.\LOAD_REG_GEN[8].LOAD_REG_I_0 (\LOAD_REG_GEN[8].LOAD_REG_I_0 ),
.\LOAD_REG_GEN[9].LOAD_REG_I (\LOAD_REG_GEN[9].LOAD_REG_I ),
.\LOAD_REG_GEN[9].LOAD_REG_I_0 (\LOAD_REG_GEN[9].LOAD_REG_I_0 ),
.Q(start2),
.READ_DONE0_I(READ_DONE0_I),
.READ_DONE1_I(READ_DONE1_I),
.\TCSR0_GENERATE[23].TCSR0_FF_I (\TCSR0_GENERATE[23].TCSR0_FF_I ),
.\TCSR0_GENERATE[23].TCSR0_FF_I_0 (\TCSR0_GENERATE[23].TCSR0_FF_I_0 ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.\bus2ip_addr_i_reg[4] ({bus2ip_addr[0],bus2ip_addr[1],bus2ip_addr[2]}),
.bus2ip_rnw_i(bus2ip_rnw_i),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.is_read(is_read),
.is_write_reg(is_write_reg_n_0),
.pair0_Select(pair0_Select),
.read_Mux_In(read_Mux_In),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_arready(s_axi_arready),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_arvalid_0(\state[1]_i_3_n_0 ),
.s_axi_bready(s_axi_bready),
.s_axi_bvalid_i_reg(I_DECODER_n_101),
.s_axi_bvalid_i_reg_0(s_axi_bvalid),
.\s_axi_rdata_i_reg[0] (\s_axi_rdata_i_reg[0]_0 ),
.\s_axi_rdata_i_reg[0]_0 (\s_axi_rdata_i_reg[0]_1 ),
.\s_axi_rdata_i_reg[10] (\s_axi_rdata_i_reg[10]_0 ),
.\s_axi_rdata_i_reg[11] (\s_axi_rdata_i_reg[11]_0 ),
.\s_axi_rdata_i_reg[12] (\s_axi_rdata_i_reg[12]_0 ),
.\s_axi_rdata_i_reg[13] (\s_axi_rdata_i_reg[13]_0 ),
.\s_axi_rdata_i_reg[14] (\s_axi_rdata_i_reg[14]_0 ),
.\s_axi_rdata_i_reg[15] (\s_axi_rdata_i_reg[15]_0 ),
.\s_axi_rdata_i_reg[16] (\s_axi_rdata_i_reg[16]_0 ),
.\s_axi_rdata_i_reg[17] (\s_axi_rdata_i_reg[17]_0 ),
.\s_axi_rdata_i_reg[18] (\s_axi_rdata_i_reg[18]_0 ),
.\s_axi_rdata_i_reg[19] (\s_axi_rdata_i_reg[19]_0 ),
.\s_axi_rdata_i_reg[20] (\s_axi_rdata_i_reg[20]_0 ),
.\s_axi_rdata_i_reg[21] (\s_axi_rdata_i_reg[21]_0 ),
.\s_axi_rdata_i_reg[22] (\s_axi_rdata_i_reg[22]_0 ),
.\s_axi_rdata_i_reg[23] (\s_axi_rdata_i_reg[23]_0 ),
.\s_axi_rdata_i_reg[24] (\s_axi_rdata_i_reg[24]_0 ),
.\s_axi_rdata_i_reg[25] (\s_axi_rdata_i_reg[25]_0 ),
.\s_axi_rdata_i_reg[26] (\s_axi_rdata_i_reg[26]_0 ),
.\s_axi_rdata_i_reg[27] (\s_axi_rdata_i_reg[27]_0 ),
.\s_axi_rdata_i_reg[28] (\s_axi_rdata_i_reg[28]_0 ),
.\s_axi_rdata_i_reg[29] (\s_axi_rdata_i_reg[29]_0 ),
.\s_axi_rdata_i_reg[30] (\s_axi_rdata_i_reg[30]_0 ),
.\s_axi_rdata_i_reg[31] (\s_axi_rdata_i_reg[31]_0 ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid_i_reg(s_axi_rvalid_i_reg_0),
.s_axi_rvalid_i_reg_0(s_axi_rvalid_i_reg_1),
.s_axi_rvalid_i_reg_1(s_axi_rvalid_i_reg_2),
.s_axi_rvalid_i_reg_2(I_DECODER_n_100),
.s_axi_rvalid_i_reg_3(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wready(s_axi_wready),
.state1__2(state1__2),
.\state_reg[1] (state));
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[2]_i_1
(.I0(s_axi_araddr[0]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[0]),
.O(\bus2ip_addr_i[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[3]_i_1
(.I0(s_axi_araddr[1]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[1]),
.O(\bus2ip_addr_i[3]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000EA))
\bus2ip_addr_i[4]_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(state[0]),
.O(\bus2ip_addr_i[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hFEFF0200))
\bus2ip_addr_i[4]_i_2
(.I0(s_axi_araddr[2]),
.I1(state[0]),
.I2(state[1]),
.I3(s_axi_arvalid),
.I4(s_axi_awaddr[2]),
.O(\bus2ip_addr_i[4]_i_2_n_0 ));
FDRE \bus2ip_addr_i_reg[2]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[2]_i_1_n_0 ),
.Q(bus2ip_addr[2]),
.R(rst));
FDRE \bus2ip_addr_i_reg[3]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[3]_i_1_n_0 ),
.Q(bus2ip_addr[1]),
.R(rst));
FDRE \bus2ip_addr_i_reg[4]
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(\bus2ip_addr_i[4]_i_2_n_0 ),
.Q(bus2ip_addr[0]),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h10))
bus2ip_rnw_i_i_1
(.I0(state[0]),
.I1(state[1]),
.I2(s_axi_arvalid),
.O(bus2ip_rnw_i06_out));
FDRE bus2ip_rnw_i_reg
(.C(s_axi_aclk),
.CE(\bus2ip_addr_i[4]_i_1_n_0 ),
.D(bus2ip_rnw_i06_out),
.Q(bus2ip_rnw_i),
.R(rst));
LUT5 #(
.INIT(32'h3FFA000A))
is_read_i_1
(.I0(s_axi_arvalid),
.I1(state1__2),
.I2(state[0]),
.I3(state[1]),
.I4(is_read),
.O(is_read_i_1_n_0));
FDRE is_read_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_read_i_1_n_0),
.Q(is_read),
.R(rst));
LUT6 #(
.INIT(64'h0040FFFF00400000))
is_write_i_1
(.I0(s_axi_arvalid),
.I1(s_axi_awvalid),
.I2(s_axi_wvalid),
.I3(state[1]),
.I4(is_write),
.I5(is_write_reg_n_0),
.O(is_write_i_1_n_0));
LUT6 #(
.INIT(64'hF88800000000FFFF))
is_write_i_2
(.I0(s_axi_rvalid),
.I1(s_axi_rready),
.I2(s_axi_bvalid),
.I3(s_axi_bready),
.I4(state[0]),
.I5(state[1]),
.O(is_write));
FDRE is_write_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(is_write_i_1_n_0),
.Q(is_write_reg_n_0),
.R(rst));
FDRE rst_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(bus2ip_reset),
.Q(rst),
.R(1'b0));
FDRE #(
.INIT(1'b0))
s_axi_bvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_101),
.Q(s_axi_bvalid),
.R(rst));
LUT2 #(
.INIT(4'h2))
\s_axi_rdata_i[31]_i_1
(.I0(state[0]),
.I1(state[1]),
.O(\s_axi_rdata_i[31]_i_1_n_0 ));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[0]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[0]),
.Q(s_axi_rdata[0]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[10]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[10]),
.Q(s_axi_rdata[10]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[11]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[11]),
.Q(s_axi_rdata[11]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[12]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[12]),
.Q(s_axi_rdata[12]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[13]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[13]),
.Q(s_axi_rdata[13]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[14]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[14]),
.Q(s_axi_rdata[14]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[15]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[15]),
.Q(s_axi_rdata[15]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[16]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[16]),
.Q(s_axi_rdata[16]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[17]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[17]),
.Q(s_axi_rdata[17]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[18]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[18]),
.Q(s_axi_rdata[18]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[19]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[19]),
.Q(s_axi_rdata[19]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[1]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[1]),
.Q(s_axi_rdata[1]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[20]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[20]),
.Q(s_axi_rdata[20]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[21]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[21]),
.Q(s_axi_rdata[21]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[22]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[22]),
.Q(s_axi_rdata[22]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[23]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[23]),
.Q(s_axi_rdata[23]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[24]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[24]),
.Q(s_axi_rdata[24]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[25]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[25]),
.Q(s_axi_rdata[25]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[26]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[26]),
.Q(s_axi_rdata[26]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[27]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[27]),
.Q(s_axi_rdata[27]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[28]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[28]),
.Q(s_axi_rdata[28]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[29]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[29]),
.Q(s_axi_rdata[29]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[2]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[2]),
.Q(s_axi_rdata[2]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[30]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[30]),
.Q(s_axi_rdata[30]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[31]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[31]),
.Q(s_axi_rdata[31]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[3]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[3]),
.Q(s_axi_rdata[3]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[4]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[4]),
.Q(s_axi_rdata[4]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[5]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[5]),
.Q(s_axi_rdata[5]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[6]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[6]),
.Q(s_axi_rdata[6]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[7]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[7]),
.Q(s_axi_rdata[7]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[8]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[8]),
.Q(s_axi_rdata[8]),
.R(rst));
FDRE #(
.INIT(1'b0))
\s_axi_rdata_i_reg[9]
(.C(s_axi_aclk),
.CE(\s_axi_rdata_i[31]_i_1_n_0 ),
.D(D[9]),
.Q(s_axi_rdata[9]),
.R(rst));
FDRE #(
.INIT(1'b0))
s_axi_rvalid_i_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_100),
.Q(s_axi_rvalid),
.R(rst));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT5 #(
.INIT(32'h000000F8))
start2_i_1
(.I0(s_axi_awvalid),
.I1(s_axi_wvalid),
.I2(s_axi_arvalid),
.I3(state[1]),
.I4(state[0]),
.O(start2_i_1_n_0));
FDRE start2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(start2_i_1_n_0),
.Q(start2),
.R(rst));
LUT4 #(
.INIT(16'hF888))
\state[1]_i_2
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(state1__2));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h08))
\state[1]_i_3
(.I0(s_axi_wvalid),
.I1(s_axi_awvalid),
.I2(s_axi_arvalid),
.O(\state[1]_i_3_n_0 ));
FDRE \state_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_26),
.Q(state[0]),
.R(rst));
FDRE \state_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(I_DECODER_n_25),
.Q(state[1]),
.R(rst));
endmodule
(* ORIG_REF_NAME = "tc_core" *)
module zqynq_lab_1_design_axi_timer_0_0_tc_core
(D,
\INFERRED_GEN.icount_out_reg[0] ,
bus2ip_reset,
generateout0,
generateout1,
interrupt,
D_0,
read_done1,
pwm0,
Bus_RNW_reg_reg,
Bus_RNW_reg_reg_0,
Bus_RNW_reg_reg_1,
Bus_RNW_reg_reg_2,
Bus_RNW_reg_reg_3,
Bus_RNW_reg_reg_4,
Bus_RNW_reg_reg_5,
Bus_RNW_reg_reg_6,
Bus_RNW_reg_reg_7,
Bus_RNW_reg_reg_8,
Bus_RNW_reg_reg_9,
Bus_RNW_reg_reg_10,
Bus_RNW_reg_reg_11,
Bus_RNW_reg_reg_12,
Bus_RNW_reg_reg_13,
Bus_RNW_reg_reg_14,
Bus_RNW_reg_reg_15,
Bus_RNW_reg_reg_16,
Bus_RNW_reg_reg_17,
Bus_RNW_reg_reg_18,
\LOAD_REG_GEN[20].LOAD_REG_I ,
D_1,
s_axi_aclk,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ,
D_2,
\INFERRED_GEN.icount_out_reg[30] ,
\INFERRED_GEN.icount_out_reg[29] ,
\INFERRED_GEN.icount_out_reg[28] ,
\INFERRED_GEN.icount_out_reg[27] ,
\INFERRED_GEN.icount_out_reg[26] ,
\INFERRED_GEN.icount_out_reg[25] ,
\INFERRED_GEN.icount_out_reg[24] ,
\INFERRED_GEN.icount_out_reg[23] ,
\INFERRED_GEN.icount_out_reg[22] ,
\INFERRED_GEN.icount_out_reg[21] ,
\INFERRED_GEN.icount_out_reg[20] ,
\INFERRED_GEN.icount_out_reg[19] ,
\INFERRED_GEN.icount_out_reg[18] ,
\INFERRED_GEN.icount_out_reg[17] ,
\INFERRED_GEN.icount_out_reg[16] ,
\INFERRED_GEN.icount_out_reg[15] ,
\INFERRED_GEN.icount_out_reg[14] ,
\INFERRED_GEN.icount_out_reg[13] ,
\INFERRED_GEN.icount_out_reg[12] ,
\INFERRED_GEN.icount_out_reg[11] ,
\INFERRED_GEN.icount_out_reg[10] ,
\INFERRED_GEN.icount_out_reg[9] ,
\INFERRED_GEN.icount_out_reg[8] ,
\INFERRED_GEN.icount_out_reg[7] ,
\INFERRED_GEN.icount_out_reg[6] ,
\INFERRED_GEN.icount_out_reg[5] ,
\INFERRED_GEN.icount_out_reg[4] ,
\INFERRED_GEN.icount_out_reg[3] ,
\INFERRED_GEN.icount_out_reg[2] ,
\INFERRED_GEN.icount_out_reg[1] ,
\INFERRED_GEN.icount_out_reg[0]_0 ,
bus2ip_wrce,
s_axi_wdata,
pair0_Select,
\TCSR0_GENERATE[24].TCSR0_FF_I ,
\TCSR1_GENERATE[24].TCSR1_FF_I ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
s_axi_aresetn,
\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ,
\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
bus2ip_wrce__0,
freeze,
capturetrig0,
capturetrig1);
output [31:0]D;
output [87:0]\INFERRED_GEN.icount_out_reg[0] ;
output bus2ip_reset;
output generateout0;
output generateout1;
output interrupt;
output D_0;
output read_done1;
output pwm0;
input Bus_RNW_reg_reg;
input Bus_RNW_reg_reg_0;
input Bus_RNW_reg_reg_1;
input Bus_RNW_reg_reg_2;
input Bus_RNW_reg_reg_3;
input Bus_RNW_reg_reg_4;
input Bus_RNW_reg_reg_5;
input Bus_RNW_reg_reg_6;
input Bus_RNW_reg_reg_7;
input Bus_RNW_reg_reg_8;
input Bus_RNW_reg_reg_9;
input Bus_RNW_reg_reg_10;
input Bus_RNW_reg_reg_11;
input Bus_RNW_reg_reg_12;
input Bus_RNW_reg_reg_13;
input Bus_RNW_reg_reg_14;
input Bus_RNW_reg_reg_15;
input Bus_RNW_reg_reg_16;
input Bus_RNW_reg_reg_17;
input Bus_RNW_reg_reg_18;
input \LOAD_REG_GEN[20].LOAD_REG_I ;
input D_1;
input s_axi_aclk;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
input D_2;
input \INFERRED_GEN.icount_out_reg[30] ;
input \INFERRED_GEN.icount_out_reg[29] ;
input \INFERRED_GEN.icount_out_reg[28] ;
input \INFERRED_GEN.icount_out_reg[27] ;
input \INFERRED_GEN.icount_out_reg[26] ;
input \INFERRED_GEN.icount_out_reg[25] ;
input \INFERRED_GEN.icount_out_reg[24] ;
input \INFERRED_GEN.icount_out_reg[23] ;
input \INFERRED_GEN.icount_out_reg[22] ;
input \INFERRED_GEN.icount_out_reg[21] ;
input \INFERRED_GEN.icount_out_reg[20] ;
input \INFERRED_GEN.icount_out_reg[19] ;
input \INFERRED_GEN.icount_out_reg[18] ;
input \INFERRED_GEN.icount_out_reg[17] ;
input \INFERRED_GEN.icount_out_reg[16] ;
input \INFERRED_GEN.icount_out_reg[15] ;
input \INFERRED_GEN.icount_out_reg[14] ;
input \INFERRED_GEN.icount_out_reg[13] ;
input \INFERRED_GEN.icount_out_reg[12] ;
input \INFERRED_GEN.icount_out_reg[11] ;
input \INFERRED_GEN.icount_out_reg[10] ;
input \INFERRED_GEN.icount_out_reg[9] ;
input \INFERRED_GEN.icount_out_reg[8] ;
input \INFERRED_GEN.icount_out_reg[7] ;
input \INFERRED_GEN.icount_out_reg[6] ;
input \INFERRED_GEN.icount_out_reg[5] ;
input \INFERRED_GEN.icount_out_reg[4] ;
input \INFERRED_GEN.icount_out_reg[3] ;
input \INFERRED_GEN.icount_out_reg[2] ;
input \INFERRED_GEN.icount_out_reg[1] ;
input \INFERRED_GEN.icount_out_reg[0]_0 ;
input [1:0]bus2ip_wrce;
input [9:0]s_axi_wdata;
input pair0_Select;
input \TCSR0_GENERATE[24].TCSR0_FF_I ;
input \TCSR1_GENERATE[24].TCSR1_FF_I ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input s_axi_aresetn;
input \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ;
input \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input [0:0]bus2ip_wrce__0;
input freeze;
input capturetrig0;
input capturetrig1;
wire Bus_RNW_reg;
wire Bus_RNW_reg_reg;
wire Bus_RNW_reg_reg_0;
wire Bus_RNW_reg_reg_1;
wire Bus_RNW_reg_reg_10;
wire Bus_RNW_reg_reg_11;
wire Bus_RNW_reg_reg_12;
wire Bus_RNW_reg_reg_13;
wire Bus_RNW_reg_reg_14;
wire Bus_RNW_reg_reg_15;
wire Bus_RNW_reg_reg_16;
wire Bus_RNW_reg_reg_17;
wire Bus_RNW_reg_reg_18;
wire Bus_RNW_reg_reg_2;
wire Bus_RNW_reg_reg_3;
wire Bus_RNW_reg_reg_4;
wire Bus_RNW_reg_reg_5;
wire Bus_RNW_reg_reg_6;
wire Bus_RNW_reg_reg_7;
wire Bus_RNW_reg_reg_8;
wire Bus_RNW_reg_reg_9;
wire COUNTER_0_I_n_64;
wire [31:0]D;
wire D_0;
wire D_1;
wire D_2;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ;
wire \GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ;
wire \GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_33 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_34 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_35 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_36 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_37 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_38 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_39 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_40 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_41 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_42 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_43 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_44 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_45 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_46 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_47 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_48 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_49 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_50 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_51 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_52 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_53 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_54 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_55 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_56 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_57 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_58 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_59 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_60 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_61 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_62 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_63 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_64 ;
wire \GEN_SECOND_TIMER.COUNTER_1_I_n_65 ;
wire [87:0]\INFERRED_GEN.icount_out_reg[0] ;
wire \INFERRED_GEN.icount_out_reg[0]_0 ;
wire \INFERRED_GEN.icount_out_reg[10] ;
wire \INFERRED_GEN.icount_out_reg[11] ;
wire \INFERRED_GEN.icount_out_reg[12] ;
wire \INFERRED_GEN.icount_out_reg[13] ;
wire \INFERRED_GEN.icount_out_reg[14] ;
wire \INFERRED_GEN.icount_out_reg[15] ;
wire \INFERRED_GEN.icount_out_reg[16] ;
wire \INFERRED_GEN.icount_out_reg[17] ;
wire \INFERRED_GEN.icount_out_reg[18] ;
wire \INFERRED_GEN.icount_out_reg[19] ;
wire \INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[20] ;
wire \INFERRED_GEN.icount_out_reg[21] ;
wire \INFERRED_GEN.icount_out_reg[22] ;
wire \INFERRED_GEN.icount_out_reg[23] ;
wire \INFERRED_GEN.icount_out_reg[24] ;
wire \INFERRED_GEN.icount_out_reg[25] ;
wire \INFERRED_GEN.icount_out_reg[26] ;
wire \INFERRED_GEN.icount_out_reg[27] ;
wire \INFERRED_GEN.icount_out_reg[28] ;
wire \INFERRED_GEN.icount_out_reg[29] ;
wire \INFERRED_GEN.icount_out_reg[2] ;
wire \INFERRED_GEN.icount_out_reg[30] ;
wire \INFERRED_GEN.icount_out_reg[3] ;
wire \INFERRED_GEN.icount_out_reg[4] ;
wire \INFERRED_GEN.icount_out_reg[5] ;
wire \INFERRED_GEN.icount_out_reg[6] ;
wire \INFERRED_GEN.icount_out_reg[7] ;
wire \INFERRED_GEN.icount_out_reg[8] ;
wire \INFERRED_GEN.icount_out_reg[9] ;
wire \LOAD_REG_GEN[20].LOAD_REG_I ;
wire R;
wire \TCSR0_GENERATE[24].TCSR0_FF_I ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I ;
wire TIMER_CONTROL_I_n_12;
wire TIMER_CONTROL_I_n_13;
wire TIMER_CONTROL_I_n_14;
wire TIMER_CONTROL_I_n_15;
wire TIMER_CONTROL_I_n_16;
wire TIMER_CONTROL_I_n_17;
wire TIMER_CONTROL_I_n_18;
wire TIMER_CONTROL_I_n_19;
wire TIMER_CONTROL_I_n_20;
wire TIMER_CONTROL_I_n_21;
wire TIMER_CONTROL_I_n_22;
wire TIMER_CONTROL_I_n_24;
wire TIMER_CONTROL_I_n_25;
wire TIMER_CONTROL_I_n_26;
wire TIMER_CONTROL_I_n_27;
wire TIMER_CONTROL_I_n_28;
wire TIMER_CONTROL_I_n_29;
wire TIMER_CONTROL_I_n_3;
wire TIMER_CONTROL_I_n_30;
wire TIMER_CONTROL_I_n_4;
wire bus2ip_reset;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire capturetrig0;
wire capturetrig1;
wire [0:1]counter_TC;
wire freeze;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:1]load_Counter_Reg;
wire pair0_Select;
wire pwm0;
wire [85:95]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire s_axi_aresetn;
wire [9:0]s_axi_wdata;
zqynq_lab_1_design_axi_timer_0_0_count_module COUNTER_0_I
(.D_1(D_1),
.E(TIMER_CONTROL_I_n_24),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_1 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_10 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_11 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_12 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_13 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_14 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_15 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_16 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_17 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_18 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_19 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_2 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_20 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_21 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_22 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_23 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_24 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_25 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_26 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_27 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_28 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_29 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_3 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_4 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_5 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_6 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_7 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_8 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_9 ),
.\INFERRED_GEN.icount_out_reg[31] (\INFERRED_GEN.icount_out_reg[0] [84:32]),
.Q(TIMER_CONTROL_I_n_3),
.S(TIMER_CONTROL_I_n_27),
.\TCSR0_GENERATE[27].TCSR0_FF_I (TIMER_CONTROL_I_n_28),
.counter_TC(counter_TC[0]),
.generateOutPre0_reg(COUNTER_0_I_n_64),
.load_Counter_Reg(load_Counter_Reg[0]),
.read_Mux_In({read_Mux_In[85],read_Mux_In[86],read_Mux_In[87],read_Mux_In[88],read_Mux_In[89],read_Mux_In[90],read_Mux_In[91],read_Mux_In[92],read_Mux_In[93],read_Mux_In[94],read_Mux_In[95]}),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.s_axi_aresetn_0(bus2ip_reset));
zqynq_lab_1_design_axi_timer_0_0_count_module_0 \GEN_SECOND_TIMER.COUNTER_1_I
(.D_2(D_2),
.E(TIMER_CONTROL_I_n_25),
.\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] (\GEN_BKEND_CE_REGISTERS[2].ce_out_i_reg[2] ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5]_0 ),
.\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] (\GEN_BKEND_CE_REGISTERS[6].ce_out_i_reg[6] ),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0]_0 ),
.\INFERRED_GEN.icount_out_reg[10] (\INFERRED_GEN.icount_out_reg[10] ),
.\INFERRED_GEN.icount_out_reg[11] (\INFERRED_GEN.icount_out_reg[11] ),
.\INFERRED_GEN.icount_out_reg[12] (\INFERRED_GEN.icount_out_reg[12] ),
.\INFERRED_GEN.icount_out_reg[13] (\INFERRED_GEN.icount_out_reg[13] ),
.\INFERRED_GEN.icount_out_reg[14] (\INFERRED_GEN.icount_out_reg[14] ),
.\INFERRED_GEN.icount_out_reg[15] (\INFERRED_GEN.icount_out_reg[15] ),
.\INFERRED_GEN.icount_out_reg[16] (\INFERRED_GEN.icount_out_reg[16] ),
.\INFERRED_GEN.icount_out_reg[17] (\INFERRED_GEN.icount_out_reg[17] ),
.\INFERRED_GEN.icount_out_reg[18] (\INFERRED_GEN.icount_out_reg[18] ),
.\INFERRED_GEN.icount_out_reg[19] (\INFERRED_GEN.icount_out_reg[19] ),
.\INFERRED_GEN.icount_out_reg[1] (\INFERRED_GEN.icount_out_reg[1] ),
.\INFERRED_GEN.icount_out_reg[20] (\INFERRED_GEN.icount_out_reg[20] ),
.\INFERRED_GEN.icount_out_reg[21] (\INFERRED_GEN.icount_out_reg[21] ),
.\INFERRED_GEN.icount_out_reg[22] (\INFERRED_GEN.icount_out_reg[22] ),
.\INFERRED_GEN.icount_out_reg[23] (\INFERRED_GEN.icount_out_reg[23] ),
.\INFERRED_GEN.icount_out_reg[24] (\INFERRED_GEN.icount_out_reg[24] ),
.\INFERRED_GEN.icount_out_reg[25] (\INFERRED_GEN.icount_out_reg[25] ),
.\INFERRED_GEN.icount_out_reg[26] (\INFERRED_GEN.icount_out_reg[26] ),
.\INFERRED_GEN.icount_out_reg[27] (\INFERRED_GEN.icount_out_reg[27] ),
.\INFERRED_GEN.icount_out_reg[28] (\INFERRED_GEN.icount_out_reg[28] ),
.\INFERRED_GEN.icount_out_reg[29] (\INFERRED_GEN.icount_out_reg[29] ),
.\INFERRED_GEN.icount_out_reg[2] (\INFERRED_GEN.icount_out_reg[2] ),
.\INFERRED_GEN.icount_out_reg[30] (\INFERRED_GEN.icount_out_reg[30] ),
.\INFERRED_GEN.icount_out_reg[31] (bus2ip_reset),
.\INFERRED_GEN.icount_out_reg[31]_0 (\INFERRED_GEN.icount_out_reg[0] [63:32]),
.\INFERRED_GEN.icount_out_reg[3] (\INFERRED_GEN.icount_out_reg[3] ),
.\INFERRED_GEN.icount_out_reg[4] (\INFERRED_GEN.icount_out_reg[4] ),
.\INFERRED_GEN.icount_out_reg[5] (\INFERRED_GEN.icount_out_reg[5] ),
.\INFERRED_GEN.icount_out_reg[6] (\INFERRED_GEN.icount_out_reg[6] ),
.\INFERRED_GEN.icount_out_reg[7] (\INFERRED_GEN.icount_out_reg[7] ),
.\INFERRED_GEN.icount_out_reg[8] (\INFERRED_GEN.icount_out_reg[8] ),
.\INFERRED_GEN.icount_out_reg[9] (\INFERRED_GEN.icount_out_reg[9] ),
.Q(\INFERRED_GEN.icount_out_reg[0] [31:0]),
.S(TIMER_CONTROL_I_n_30),
.\TCSR0_GENERATE[20].TCSR0_FF_I (TIMER_CONTROL_I_n_29),
.counter_TC(counter_TC[1]),
.\counter_TC_Reg_reg[1] (TIMER_CONTROL_I_n_4),
.generateOutPre1_reg(\GEN_SECOND_TIMER.COUNTER_1_I_n_65 ),
.load_Counter_Reg(load_Counter_Reg[1]),
.s_axi_aclk(s_axi_aclk),
.s_axi_aresetn(s_axi_aresetn),
.\s_axi_rdata_i_reg[0] (\GEN_SECOND_TIMER.COUNTER_1_I_n_33 ),
.\s_axi_rdata_i_reg[10] (\GEN_SECOND_TIMER.COUNTER_1_I_n_43 ),
.\s_axi_rdata_i_reg[11] (\GEN_SECOND_TIMER.COUNTER_1_I_n_44 ),
.\s_axi_rdata_i_reg[12] (\GEN_SECOND_TIMER.COUNTER_1_I_n_45 ),
.\s_axi_rdata_i_reg[13] (\GEN_SECOND_TIMER.COUNTER_1_I_n_46 ),
.\s_axi_rdata_i_reg[14] (\GEN_SECOND_TIMER.COUNTER_1_I_n_47 ),
.\s_axi_rdata_i_reg[15] (\GEN_SECOND_TIMER.COUNTER_1_I_n_48 ),
.\s_axi_rdata_i_reg[16] (\GEN_SECOND_TIMER.COUNTER_1_I_n_49 ),
.\s_axi_rdata_i_reg[17] (\GEN_SECOND_TIMER.COUNTER_1_I_n_50 ),
.\s_axi_rdata_i_reg[18] (\GEN_SECOND_TIMER.COUNTER_1_I_n_51 ),
.\s_axi_rdata_i_reg[19] (\GEN_SECOND_TIMER.COUNTER_1_I_n_52 ),
.\s_axi_rdata_i_reg[1] (\GEN_SECOND_TIMER.COUNTER_1_I_n_34 ),
.\s_axi_rdata_i_reg[20] (\GEN_SECOND_TIMER.COUNTER_1_I_n_53 ),
.\s_axi_rdata_i_reg[21] (\GEN_SECOND_TIMER.COUNTER_1_I_n_54 ),
.\s_axi_rdata_i_reg[22] (\GEN_SECOND_TIMER.COUNTER_1_I_n_55 ),
.\s_axi_rdata_i_reg[23] (\GEN_SECOND_TIMER.COUNTER_1_I_n_56 ),
.\s_axi_rdata_i_reg[24] (\GEN_SECOND_TIMER.COUNTER_1_I_n_57 ),
.\s_axi_rdata_i_reg[25] (\GEN_SECOND_TIMER.COUNTER_1_I_n_58 ),
.\s_axi_rdata_i_reg[26] (\GEN_SECOND_TIMER.COUNTER_1_I_n_59 ),
.\s_axi_rdata_i_reg[27] (\GEN_SECOND_TIMER.COUNTER_1_I_n_60 ),
.\s_axi_rdata_i_reg[28] (\GEN_SECOND_TIMER.COUNTER_1_I_n_61 ),
.\s_axi_rdata_i_reg[29] (\GEN_SECOND_TIMER.COUNTER_1_I_n_62 ),
.\s_axi_rdata_i_reg[2] (\GEN_SECOND_TIMER.COUNTER_1_I_n_35 ),
.\s_axi_rdata_i_reg[30] (\GEN_SECOND_TIMER.COUNTER_1_I_n_63 ),
.\s_axi_rdata_i_reg[31] (\GEN_SECOND_TIMER.COUNTER_1_I_n_64 ),
.\s_axi_rdata_i_reg[3] (\GEN_SECOND_TIMER.COUNTER_1_I_n_36 ),
.\s_axi_rdata_i_reg[4] (\GEN_SECOND_TIMER.COUNTER_1_I_n_37 ),
.\s_axi_rdata_i_reg[5] (\GEN_SECOND_TIMER.COUNTER_1_I_n_38 ),
.\s_axi_rdata_i_reg[6] (\GEN_SECOND_TIMER.COUNTER_1_I_n_39 ),
.\s_axi_rdata_i_reg[7] (\GEN_SECOND_TIMER.COUNTER_1_I_n_40 ),
.\s_axi_rdata_i_reg[8] (\GEN_SECOND_TIMER.COUNTER_1_I_n_41 ),
.\s_axi_rdata_i_reg[9] (\GEN_SECOND_TIMER.COUNTER_1_I_n_42 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
PWM_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(TIMER_CONTROL_I_n_26),
.Q(pwm0),
.R(R));
zqynq_lab_1_design_axi_timer_0_0_mux_onehot_f READ_MUX_I
(.Bus_RNW_reg_reg(Bus_RNW_reg_reg),
.Bus_RNW_reg_reg_0(Bus_RNW_reg_reg_0),
.Bus_RNW_reg_reg_1(Bus_RNW_reg_reg_1),
.Bus_RNW_reg_reg_10(Bus_RNW_reg_reg_10),
.Bus_RNW_reg_reg_11(Bus_RNW_reg_reg_11),
.Bus_RNW_reg_reg_12(Bus_RNW_reg_reg_12),
.Bus_RNW_reg_reg_13(Bus_RNW_reg_reg_13),
.Bus_RNW_reg_reg_14(Bus_RNW_reg_reg_14),
.Bus_RNW_reg_reg_15(Bus_RNW_reg_reg_15),
.Bus_RNW_reg_reg_16(Bus_RNW_reg_reg_16),
.Bus_RNW_reg_reg_17(Bus_RNW_reg_reg_17),
.Bus_RNW_reg_reg_18(Bus_RNW_reg_reg_18),
.Bus_RNW_reg_reg_2(Bus_RNW_reg_reg_2),
.Bus_RNW_reg_reg_3(Bus_RNW_reg_reg_3),
.Bus_RNW_reg_reg_4(Bus_RNW_reg_reg_4),
.Bus_RNW_reg_reg_5(Bus_RNW_reg_reg_5),
.Bus_RNW_reg_reg_6(Bus_RNW_reg_reg_6),
.Bus_RNW_reg_reg_7(Bus_RNW_reg_reg_7),
.Bus_RNW_reg_reg_8(Bus_RNW_reg_reg_8),
.Bus_RNW_reg_reg_9(Bus_RNW_reg_reg_9),
.D(D),
.\INFERRED_GEN.icount_out_reg[0] (\GEN_SECOND_TIMER.COUNTER_1_I_n_33 ),
.\INFERRED_GEN.icount_out_reg[10] (\GEN_SECOND_TIMER.COUNTER_1_I_n_43 ),
.\INFERRED_GEN.icount_out_reg[11] (\GEN_SECOND_TIMER.COUNTER_1_I_n_44 ),
.\INFERRED_GEN.icount_out_reg[12] (\GEN_SECOND_TIMER.COUNTER_1_I_n_45 ),
.\INFERRED_GEN.icount_out_reg[13] (\GEN_SECOND_TIMER.COUNTER_1_I_n_46 ),
.\INFERRED_GEN.icount_out_reg[14] (\GEN_SECOND_TIMER.COUNTER_1_I_n_47 ),
.\INFERRED_GEN.icount_out_reg[15] (\GEN_SECOND_TIMER.COUNTER_1_I_n_48 ),
.\INFERRED_GEN.icount_out_reg[16] (\GEN_SECOND_TIMER.COUNTER_1_I_n_49 ),
.\INFERRED_GEN.icount_out_reg[17] (\GEN_SECOND_TIMER.COUNTER_1_I_n_50 ),
.\INFERRED_GEN.icount_out_reg[18] (\GEN_SECOND_TIMER.COUNTER_1_I_n_51 ),
.\INFERRED_GEN.icount_out_reg[19] (\GEN_SECOND_TIMER.COUNTER_1_I_n_52 ),
.\INFERRED_GEN.icount_out_reg[1] (\GEN_SECOND_TIMER.COUNTER_1_I_n_34 ),
.\INFERRED_GEN.icount_out_reg[20] (\GEN_SECOND_TIMER.COUNTER_1_I_n_53 ),
.\INFERRED_GEN.icount_out_reg[21] (\GEN_SECOND_TIMER.COUNTER_1_I_n_54 ),
.\INFERRED_GEN.icount_out_reg[22] (\GEN_SECOND_TIMER.COUNTER_1_I_n_55 ),
.\INFERRED_GEN.icount_out_reg[23] (\GEN_SECOND_TIMER.COUNTER_1_I_n_56 ),
.\INFERRED_GEN.icount_out_reg[24] (\GEN_SECOND_TIMER.COUNTER_1_I_n_57 ),
.\INFERRED_GEN.icount_out_reg[25] (\GEN_SECOND_TIMER.COUNTER_1_I_n_58 ),
.\INFERRED_GEN.icount_out_reg[26] (\GEN_SECOND_TIMER.COUNTER_1_I_n_59 ),
.\INFERRED_GEN.icount_out_reg[27] (\GEN_SECOND_TIMER.COUNTER_1_I_n_60 ),
.\INFERRED_GEN.icount_out_reg[28] (\GEN_SECOND_TIMER.COUNTER_1_I_n_61 ),
.\INFERRED_GEN.icount_out_reg[29] (\GEN_SECOND_TIMER.COUNTER_1_I_n_62 ),
.\INFERRED_GEN.icount_out_reg[2] (\GEN_SECOND_TIMER.COUNTER_1_I_n_35 ),
.\INFERRED_GEN.icount_out_reg[30] (\GEN_SECOND_TIMER.COUNTER_1_I_n_63 ),
.\INFERRED_GEN.icount_out_reg[31] (\GEN_SECOND_TIMER.COUNTER_1_I_n_64 ),
.\INFERRED_GEN.icount_out_reg[3] (\GEN_SECOND_TIMER.COUNTER_1_I_n_36 ),
.\INFERRED_GEN.icount_out_reg[4] (\GEN_SECOND_TIMER.COUNTER_1_I_n_37 ),
.\INFERRED_GEN.icount_out_reg[5] (\GEN_SECOND_TIMER.COUNTER_1_I_n_38 ),
.\INFERRED_GEN.icount_out_reg[6] (\GEN_SECOND_TIMER.COUNTER_1_I_n_39 ),
.\INFERRED_GEN.icount_out_reg[7] (\GEN_SECOND_TIMER.COUNTER_1_I_n_40 ),
.\INFERRED_GEN.icount_out_reg[8] (\GEN_SECOND_TIMER.COUNTER_1_I_n_41 ),
.\INFERRED_GEN.icount_out_reg[9] (\GEN_SECOND_TIMER.COUNTER_1_I_n_42 ),
.\LOAD_REG_GEN[20].LOAD_REG_I (\LOAD_REG_GEN[20].LOAD_REG_I ),
.\LOAD_REG_GEN[21].LOAD_REG_I (TIMER_CONTROL_I_n_22),
.\LOAD_REG_GEN[22].LOAD_REG_I (TIMER_CONTROL_I_n_21),
.\LOAD_REG_GEN[23].LOAD_REG_I (TIMER_CONTROL_I_n_20),
.\LOAD_REG_GEN[24].LOAD_REG_I (TIMER_CONTROL_I_n_19),
.\LOAD_REG_GEN[25].LOAD_REG_I (TIMER_CONTROL_I_n_18),
.\LOAD_REG_GEN[26].LOAD_REG_I (TIMER_CONTROL_I_n_17),
.\LOAD_REG_GEN[27].LOAD_REG_I (TIMER_CONTROL_I_n_16),
.\LOAD_REG_GEN[28].LOAD_REG_I (TIMER_CONTROL_I_n_15),
.\LOAD_REG_GEN[29].LOAD_REG_I (TIMER_CONTROL_I_n_14),
.\LOAD_REG_GEN[30].LOAD_REG_I (TIMER_CONTROL_I_n_13),
.\LOAD_REG_GEN[31].LOAD_REG_I (TIMER_CONTROL_I_n_12));
zqynq_lab_1_design_axi_timer_0_0_timer_control TIMER_CONTROL_I
(.Bus_RNW_reg(Bus_RNW_reg),
.D_0(D_0),
.E(TIMER_CONTROL_I_n_24),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ),
.\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 (\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_30 ),
.\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 (\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_31 ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ),
.\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 (\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] (\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0] [87]),
.\INFERRED_GEN.icount_out_reg[0]_0 (TIMER_CONTROL_I_n_25),
.\INFERRED_GEN.icount_out_reg[1] ({\INFERRED_GEN.icount_out_reg[0] [33],\INFERRED_GEN.icount_out_reg[0] [1]}),
.\INFERRED_GEN.icount_out_reg[32] (\GEN_SECOND_TIMER.COUNTER_1_I_n_65 ),
.\INFERRED_GEN.icount_out_reg[32]_0 (COUNTER_0_I_n_64),
.\INFERRED_GEN.icount_out_reg[4] (TIMER_CONTROL_I_n_30),
.\LOAD_REG_GEN[21].LOAD_REG_I ({read_Mux_In[85],read_Mux_In[86],read_Mux_In[87],read_Mux_In[88],read_Mux_In[89],read_Mux_In[90],read_Mux_In[91],read_Mux_In[92],read_Mux_In[93],read_Mux_In[94],read_Mux_In[95]}),
.\LOAD_REG_GEN[24].LOAD_REG_I (TIMER_CONTROL_I_n_28),
.\LOAD_REG_GEN[24].LOAD_REG_I_0 (TIMER_CONTROL_I_n_29),
.PWM_FF_I(TIMER_CONTROL_I_n_26),
.Q({TIMER_CONTROL_I_n_3,TIMER_CONTROL_I_n_4}),
.R(R),
.S(TIMER_CONTROL_I_n_27),
.SR(bus2ip_reset),
.\TCSR0_GENERATE[24].TCSR0_FF_I_0 (\INFERRED_GEN.icount_out_reg[0] [86]),
.\TCSR0_GENERATE[24].TCSR0_FF_I_1 (\TCSR0_GENERATE[24].TCSR0_FF_I ),
.\TCSR1_GENERATE[23].TCSR1_FF_I_0 (\INFERRED_GEN.icount_out_reg[0] [85]),
.\TCSR1_GENERATE[24].TCSR1_FF_I_0 (\TCSR1_GENERATE[24].TCSR1_FF_I ),
.bus2ip_wrce(bus2ip_wrce),
.bus2ip_wrce__0(bus2ip_wrce__0),
.capturetrig0(capturetrig0),
.capturetrig1(capturetrig1),
.counter_TC(counter_TC),
.freeze(freeze),
.generateout0(generateout0),
.generateout1(generateout1),
.interrupt(interrupt),
.load_Counter_Reg(load_Counter_Reg),
.pair0_Select(pair0_Select),
.pwm0(pwm0),
.read_done1(read_done1),
.s_axi_aclk(s_axi_aclk),
.\s_axi_rdata_i_reg[0] (TIMER_CONTROL_I_n_12),
.\s_axi_rdata_i_reg[10] (TIMER_CONTROL_I_n_22),
.\s_axi_rdata_i_reg[1] (TIMER_CONTROL_I_n_13),
.\s_axi_rdata_i_reg[2] (TIMER_CONTROL_I_n_14),
.\s_axi_rdata_i_reg[3] (TIMER_CONTROL_I_n_15),
.\s_axi_rdata_i_reg[4] (TIMER_CONTROL_I_n_16),
.\s_axi_rdata_i_reg[5] (TIMER_CONTROL_I_n_17),
.\s_axi_rdata_i_reg[6] (TIMER_CONTROL_I_n_18),
.\s_axi_rdata_i_reg[7] (TIMER_CONTROL_I_n_19),
.\s_axi_rdata_i_reg[8] (TIMER_CONTROL_I_n_20),
.\s_axi_rdata_i_reg[9] (TIMER_CONTROL_I_n_21),
.s_axi_wdata(s_axi_wdata));
endmodule
(* ORIG_REF_NAME = "timer_control" *)
module zqynq_lab_1_design_axi_timer_0_0_timer_control
(generateout0,
generateout1,
interrupt,
Q,
\INFERRED_GEN.icount_out_reg[0] ,
\TCSR0_GENERATE[24].TCSR0_FF_I_0 ,
\TCSR1_GENERATE[23].TCSR1_FF_I_0 ,
D_0,
read_done1,
load_Counter_Reg,
\s_axi_rdata_i_reg[0] ,
\s_axi_rdata_i_reg[1] ,
\s_axi_rdata_i_reg[2] ,
\s_axi_rdata_i_reg[3] ,
\s_axi_rdata_i_reg[4] ,
\s_axi_rdata_i_reg[5] ,
\s_axi_rdata_i_reg[6] ,
\s_axi_rdata_i_reg[7] ,
\s_axi_rdata_i_reg[8] ,
\s_axi_rdata_i_reg[9] ,
\s_axi_rdata_i_reg[10] ,
R,
E,
\INFERRED_GEN.icount_out_reg[0]_0 ,
PWM_FF_I,
S,
\LOAD_REG_GEN[24].LOAD_REG_I ,
\LOAD_REG_GEN[24].LOAD_REG_I_0 ,
\INFERRED_GEN.icount_out_reg[4] ,
SR,
\INFERRED_GEN.icount_out_reg[32] ,
s_axi_aclk,
\INFERRED_GEN.icount_out_reg[32]_0 ,
bus2ip_wrce,
s_axi_wdata,
\LOAD_REG_GEN[21].LOAD_REG_I ,
pair0_Select,
\TCSR0_GENERATE[24].TCSR0_FF_I_1 ,
\TCSR1_GENERATE[24].TCSR1_FF_I_0 ,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ,
\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ,
counter_TC,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ,
\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ,
\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ,
pwm0,
\INFERRED_GEN.icount_out_reg[1] ,
Bus_RNW_reg,
\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ,
bus2ip_wrce__0,
freeze,
capturetrig0,
capturetrig1);
output generateout0;
output generateout1;
output interrupt;
output [1:0]Q;
output \INFERRED_GEN.icount_out_reg[0] ;
output \TCSR0_GENERATE[24].TCSR0_FF_I_0 ;
output \TCSR1_GENERATE[23].TCSR1_FF_I_0 ;
output D_0;
output read_done1;
output [0:1]load_Counter_Reg;
output \s_axi_rdata_i_reg[0] ;
output \s_axi_rdata_i_reg[1] ;
output \s_axi_rdata_i_reg[2] ;
output \s_axi_rdata_i_reg[3] ;
output \s_axi_rdata_i_reg[4] ;
output \s_axi_rdata_i_reg[5] ;
output \s_axi_rdata_i_reg[6] ;
output \s_axi_rdata_i_reg[7] ;
output \s_axi_rdata_i_reg[8] ;
output \s_axi_rdata_i_reg[9] ;
output \s_axi_rdata_i_reg[10] ;
output R;
output [0:0]E;
output [0:0]\INFERRED_GEN.icount_out_reg[0]_0 ;
output PWM_FF_I;
output [0:0]S;
output \LOAD_REG_GEN[24].LOAD_REG_I ;
output \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
output [0:0]\INFERRED_GEN.icount_out_reg[4] ;
input [0:0]SR;
input \INFERRED_GEN.icount_out_reg[32] ;
input s_axi_aclk;
input \INFERRED_GEN.icount_out_reg[32]_0 ;
input [1:0]bus2ip_wrce;
input [9:0]s_axi_wdata;
input [10:0]\LOAD_REG_GEN[21].LOAD_REG_I ;
input pair0_Select;
input \TCSR0_GENERATE[24].TCSR0_FF_I_1 ;
input \TCSR1_GENERATE[24].TCSR1_FF_I_0 ;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
input \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
input [0:1]counter_TC;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
input \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
input \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
input pwm0;
input [1:0]\INFERRED_GEN.icount_out_reg[1] ;
input Bus_RNW_reg;
input \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
input [0:0]bus2ip_wrce__0;
input freeze;
input capturetrig0;
input capturetrig1;
wire Bus_RNW_reg;
wire D_0;
wire [0:0]E;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ;
wire \GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ;
wire \GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ;
wire \GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ;
wire \GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ;
wire GenerateOut00;
wire GenerateOut10;
wire \INFERRED_GEN.icount_out_reg[0] ;
wire [0:0]\INFERRED_GEN.icount_out_reg[0]_0 ;
wire [1:0]\INFERRED_GEN.icount_out_reg[1] ;
wire \INFERRED_GEN.icount_out_reg[32] ;
wire \INFERRED_GEN.icount_out_reg[32]_0 ;
wire [0:0]\INFERRED_GEN.icount_out_reg[4] ;
wire Interrupt0;
wire \LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ;
wire \LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ;
wire [10:0]\LOAD_REG_GEN[21].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I ;
wire \LOAD_REG_GEN[24].LOAD_REG_I_0 ;
wire Load_Counter_Reg028_out;
wire Load_Counter_Reg030_out;
wire Load_Counter_Reg031_out;
wire Load_Counter_Reg0__0;
wire PWM_FF_I;
wire [1:0]Q;
wire R;
wire READ_DONE0_I_i_3_n_0;
wire READ_DONE1_I_i_1_n_0;
wire READ_DONE1_I_i_3_n_0;
wire R_0;
wire [0:0]S;
wire [0:0]SR;
wire \TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I_0 ;
wire \TCSR0_GENERATE[24].TCSR0_FF_I_1 ;
wire TCSR0_Set2__0;
wire \TCSR1_GENERATE[23].TCSR1_FF_I_0 ;
wire \TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ;
wire \TCSR1_GENERATE[24].TCSR1_FF_I_0 ;
wire [1:0]bus2ip_wrce;
wire [0:0]bus2ip_wrce__0;
wire captureTrig0_d;
wire captureTrig0_d0;
wire captureTrig0_d2;
wire captureTrig0_pulse_d1;
wire captureTrig0_pulse_d1_i_1_n_0;
wire captureTrig0_pulse_d2;
wire captureTrig1_d;
wire captureTrig1_d0;
wire captureTrig1_d2;
wire capturetrig0;
wire capturetrig1;
wire [0:1]counter_TC;
wire counter_TC_Reg2;
wire freeze;
wire generateOutPre0;
wire generateOutPre1;
wire generateout0;
wire generateout1;
wire interrupt;
wire [0:1]load_Counter_Reg;
wire p_33_in;
wire p_38_in;
wire pair0_Select;
wire pwm0;
wire [21:63]read_Mux_In;
wire read_done1;
wire s_axi_aclk;
wire \s_axi_rdata_i_reg[0] ;
wire \s_axi_rdata_i_reg[10] ;
wire \s_axi_rdata_i_reg[1] ;
wire \s_axi_rdata_i_reg[2] ;
wire \s_axi_rdata_i_reg[3] ;
wire \s_axi_rdata_i_reg[4] ;
wire \s_axi_rdata_i_reg[5] ;
wire \s_axi_rdata_i_reg[6] ;
wire \s_axi_rdata_i_reg[7] ;
wire \s_axi_rdata_i_reg[8] ;
wire \s_axi_rdata_i_reg[9] ;
wire [9:0]s_axi_wdata;
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[21].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [10]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[21]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[53]),
.O(\s_axi_rdata_i_reg[10] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[22].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [9]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[22]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[54]),
.O(\s_axi_rdata_i_reg[9] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[23].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [8]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[23]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[55]),
.O(\s_axi_rdata_i_reg[8] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[24].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [7]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.O(\s_axi_rdata_i_reg[7] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[25].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [6]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[25]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[57]),
.O(\s_axi_rdata_i_reg[6] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[26].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [5]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[26]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[58]),
.O(\s_axi_rdata_i_reg[5] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[27].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [4]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[27]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[59]),
.O(\s_axi_rdata_i_reg[4] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[28].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [3]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[28]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[60]),
.O(\s_axi_rdata_i_reg[3] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[29].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [2]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[29]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[61]),
.O(\s_axi_rdata_i_reg[2] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[30].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [1]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[30]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[62]),
.O(\s_axi_rdata_i_reg[1] ));
LUT6 #(
.INIT(64'h0000077707770777))
\GEN.DATA_WIDTH_GEN[31].NUM_BUSES_GEN[0].MUXCY_GEN.MUXCY_I_i_1
(.I0(\LOAD_REG_GEN[21].LOAD_REG_I [0]),
.I1(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1]_0 ),
.I2(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0]_0 ),
.I3(read_Mux_In[31]),
.I4(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4]_0 ),
.I5(read_Mux_In[63]),
.O(\s_axi_rdata_i_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT4 #(
.INIT(16'hB800))
GenerateOut0_i_2
(.I0(generateOutPre1),
.I1(\INFERRED_GEN.icount_out_reg[0] ),
.I2(generateOutPre0),
.I3(read_Mux_In[29]),
.O(GenerateOut00));
FDRE GenerateOut0_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GenerateOut00),
.Q(generateout0),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT5 #(
.INIT(32'h8F808080))
GenerateOut1_i_1
(.I0(generateOutPre0),
.I1(read_Mux_In[29]),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(read_Mux_In[61]),
.I4(generateOutPre1),
.O(GenerateOut10));
FDRE GenerateOut1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(GenerateOut10),
.Q(generateout1),
.R(SR));
LUT5 #(
.INIT(32'hAAFEAAAA))
\INFERRED_GEN.icount_out[31]_i_3
(.I0(read_Mux_In[26]),
.I1(read_Mux_In[22]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[31]),
.I4(counter_TC[0]),
.O(Load_Counter_Reg030_out));
LUT6 #(
.INIT(64'hFFFFAAEAAAAAAAEA))
\INFERRED_GEN.icount_out[31]_i_3__0
(.I0(read_Mux_In[58]),
.I1(counter_TC[1]),
.I2(read_Mux_In[59]),
.I3(read_Mux_In[63]),
.I4(read_Mux_In[54]),
.I5(counter_TC[0]),
.O(Load_Counter_Reg0__0));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hFF40))
\INFERRED_GEN.icount_out[31]_i_4
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[58]),
.O(Load_Counter_Reg028_out));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT4 #(
.INIT(16'hFF40))
\INFERRED_GEN.icount_out[31]_i_4__0
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[26]),
.O(Load_Counter_Reg031_out));
LUT6 #(
.INIT(64'hFF40FFFFFF400000))
\INFERRED_GEN.icount_out[31]_i_7
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[58]),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(Load_Counter_Reg0__0),
.O(load_Counter_Reg[1]));
LUT6 #(
.INIT(64'hFF40FFFFFF400000))
\INFERRED_GEN.icount_out[31]_i_7__0
(.I0(read_Mux_In[31]),
.I1(counter_TC[1]),
.I2(read_Mux_In[27]),
.I3(read_Mux_In[26]),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(Load_Counter_Reg030_out),
.O(load_Counter_Reg[0]));
zqynq_lab_1_design_axi_timer_0_0_cdc_sync INPUT_DOUBLE_REGS
(.captureTrig0_d0(captureTrig0_d0),
.capturetrig0(capturetrig0),
.read_Mux_In(read_Mux_In[28]),
.s_axi_aclk(s_axi_aclk));
zqynq_lab_1_design_axi_timer_0_0_cdc_sync_1 INPUT_DOUBLE_REGS2
(.captureTrig1_d0(captureTrig1_d0),
.capturetrig1(capturetrig1),
.read_Mux_In(read_Mux_In[60]),
.s_axi_aclk(s_axi_aclk));
zqynq_lab_1_design_axi_timer_0_0_cdc_sync_2 INPUT_DOUBLE_REGS3
(.E(E),
.\INFERRED_GEN.icount_out_reg[0] (\INFERRED_GEN.icount_out_reg[0]_0 ),
.\INFERRED_GEN.icount_out_reg[1] (\INFERRED_GEN.icount_out_reg[1] ),
.\INFERRED_GEN.icount_out_reg[4] (\INFERRED_GEN.icount_out_reg[4] ),
.Load_Counter_Reg028_out(Load_Counter_Reg028_out),
.Load_Counter_Reg030_out(Load_Counter_Reg030_out),
.Load_Counter_Reg031_out(Load_Counter_Reg031_out),
.Load_Counter_Reg0__0(Load_Counter_Reg0__0),
.S(S),
.\TCSR0_GENERATE[20].TCSR0_FF_I (\INFERRED_GEN.icount_out_reg[0] ),
.\TCSR0_GENERATE[24].TCSR0_FF_I (\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.\TCSR1_GENERATE[24].TCSR1_FF_I (\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.counter_TC(counter_TC),
.freeze(freeze),
.generateOutPre0(generateOutPre0),
.read_Mux_In({read_Mux_In[22],read_Mux_In[27],read_Mux_In[30],read_Mux_In[31],read_Mux_In[54],read_Mux_In[59],read_Mux_In[62],read_Mux_In[63]}),
.s_axi_aclk(s_axi_aclk));
LUT4 #(
.INIT(16'hF888))
Interrupt_i_1
(.I0(read_Mux_In[25]),
.I1(read_Mux_In[23]),
.I2(read_Mux_In[57]),
.I3(read_Mux_In[55]),
.O(Interrupt0));
FDRE Interrupt_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Interrupt0),
.Q(interrupt),
.R(SR));
LUT6 #(
.INIT(64'hE000FFFFE000E000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_1
(.I0(read_Mux_In[27]),
.I1(D_0),
.I2(R_0),
.I3(read_Mux_In[31]),
.I4(Bus_RNW_reg),
.I5(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg ),
.O(\LOAD_REG_GEN[24].LOAD_REG_I ));
LUT6 #(
.INIT(64'hFFFFFFFFF8080808))
\LOAD_REG_GEN[0].LOAD_REG_I_i_1__0
(.I0(\LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ),
.I1(p_38_in),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(\LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ),
.I4(p_33_in),
.I5(bus2ip_wrce__0),
.O(\LOAD_REG_GEN[24].LOAD_REG_I_0 ));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT2 #(
.INIT(4'hE))
\LOAD_REG_GEN[0].LOAD_REG_I_i_3
(.I0(read_Mux_In[59]),
.I1(read_done1),
.O(\LOAD_REG_GEN[0].LOAD_REG_I_i_3_n_0 ));
LUT6 #(
.INIT(64'hF4F4F40400000000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_4
(.I0(captureTrig1_d2),
.I1(captureTrig1_d),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(READ_DONE1_I_i_3_n_0),
.I4(READ_DONE0_I_i_3_n_0),
.I5(read_Mux_In[63]),
.O(p_38_in));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT2 #(
.INIT(4'hE))
\LOAD_REG_GEN[0].LOAD_REG_I_i_5
(.I0(read_Mux_In[27]),
.I1(read_done1),
.O(\LOAD_REG_GEN[0].LOAD_REG_I_i_5_n_0 ));
LUT6 #(
.INIT(64'hF4F4F40400000000))
\LOAD_REG_GEN[0].LOAD_REG_I_i_6
(.I0(captureTrig1_d2),
.I1(captureTrig1_d),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(READ_DONE1_I_i_3_n_0),
.I4(READ_DONE0_I_i_3_n_0),
.I5(read_Mux_In[31]),
.O(p_33_in));
LUT3 #(
.INIT(8'hAB))
PWM_FF_I_i_1
(.I0(generateout1),
.I1(read_Mux_In[22]),
.I2(read_Mux_In[54]),
.O(R));
LUT2 #(
.INIT(4'hE))
PWM_FF_I_i_2
(.I0(generateout0),
.I1(pwm0),
.O(PWM_FF_I));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
READ_DONE0_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[1].ce_out_i_reg[1] ),
.Q(D_0),
.R(R_0));
LUT6 #(
.INIT(64'hAA00AA00ABFFAA00))
READ_DONE0_I_i_1
(.I0(READ_DONE0_I_i_3_n_0),
.I1(Q[1]),
.I2(counter_TC[0]),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(captureTrig0_d),
.I5(captureTrig0_d2),
.O(R_0));
LUT3 #(
.INIT(8'hA8))
READ_DONE0_I_i_3
(.I0(counter_TC_Reg2),
.I1(captureTrig0_pulse_d2),
.I2(captureTrig0_pulse_d1),
.O(READ_DONE0_I_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
READ_DONE1_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\GEN_BKEND_CE_REGISTERS[5].ce_out_i_reg[5] ),
.Q(read_done1),
.R(READ_DONE1_I_i_1_n_0));
LUT5 #(
.INIT(32'hE0E0EFE0))
READ_DONE1_I_i_1
(.I0(READ_DONE0_I_i_3_n_0),
.I1(READ_DONE1_I_i_3_n_0),
.I2(\INFERRED_GEN.icount_out_reg[0] ),
.I3(captureTrig1_d),
.I4(captureTrig1_d2),
.O(READ_DONE1_I_i_1_n_0));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT4 #(
.INIT(16'h0004))
READ_DONE1_I_i_3
(.I0(captureTrig0_d2),
.I1(captureTrig0_d),
.I2(counter_TC[0]),
.I3(Q[1]),
.O(READ_DONE1_I_i_3_n_0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[20].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[9]),
.Q(\INFERRED_GEN.icount_out_reg[0] ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[21].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(s_axi_wdata[8]),
.Q(read_Mux_In[21]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[22].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[7]),
.Q(read_Mux_In[22]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[23].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ),
.Q(read_Mux_In[23]),
.R(\GEN_BKEND_CE_REGISTERS[0].ce_out_i_reg[0] ));
LUT6 #(
.INIT(64'hFFFFFFFFF3F2F0F2))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_2
(.I0(generateOutPre0),
.I1(read_Mux_In[31]),
.I2(TCSR0_Set2__0),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(generateOutPre1),
.I5(read_Mux_In[23]),
.O(\TCSR0_GENERATE[23].TCSR0_FF_I_i_2_n_0 ));
LUT6 #(
.INIT(64'hA8AAA80000000000))
\TCSR0_GENERATE[23].TCSR0_FF_I_i_3
(.I0(read_Mux_In[31]),
.I1(READ_DONE0_I_i_3_n_0),
.I2(READ_DONE1_I_i_3_n_0),
.I3(\INFERRED_GEN.icount_out_reg[0] ),
.I4(captureTrig0_pulse_d1_i_1_n_0),
.I5(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.O(TCSR0_Set2__0));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[24].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(\TCSR0_GENERATE[24].TCSR0_FF_I_1 ),
.Q(\TCSR0_GENERATE[24].TCSR0_FF_I_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[25].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[6]),
.Q(read_Mux_In[25]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[26].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[5]),
.Q(read_Mux_In[26]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[27].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[4]),
.Q(read_Mux_In[27]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[28].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[3]),
.Q(read_Mux_In[28]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[29].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[2]),
.Q(read_Mux_In[29]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[30].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[1]),
.Q(read_Mux_In[30]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR0_GENERATE[31].TCSR0_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[1]),
.D(s_axi_wdata[0]),
.Q(read_Mux_In[31]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[21].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(s_axi_wdata[8]),
.Q(read_Mux_In[53]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[22].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[7]),
.Q(read_Mux_In[54]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[23].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(1'b1),
.D(\TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ),
.Q(read_Mux_In[55]),
.R(\GEN_BKEND_CE_REGISTERS[4].ce_out_i_reg[4] ));
LUT6 #(
.INIT(64'hFFFFFFFF00008F80))
\TCSR1_GENERATE[23].TCSR1_FF_I_i_2
(.I0(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.I1(READ_DONE1_I_i_1_n_0),
.I2(read_Mux_In[63]),
.I3(generateOutPre1),
.I4(\INFERRED_GEN.icount_out_reg[0] ),
.I5(read_Mux_In[55]),
.O(\TCSR1_GENERATE[23].TCSR1_FF_I_i_2_n_0 ));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[24].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(pair0_Select),
.D(\TCSR1_GENERATE[24].TCSR1_FF_I_0 ),
.Q(\TCSR1_GENERATE[23].TCSR1_FF_I_0 ),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[25].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[6]),
.Q(read_Mux_In[57]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[26].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[5]),
.Q(read_Mux_In[58]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[27].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[4]),
.Q(read_Mux_In[59]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[28].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[3]),
.Q(read_Mux_In[60]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[29].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[2]),
.Q(read_Mux_In[61]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[30].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[1]),
.Q(read_Mux_In[62]),
.R(SR));
(* BOX_TYPE = "PRIMITIVE" *)
(* IS_CE_INVERTED = "1'b0" *)
(* IS_S_INVERTED = "1'b0" *)
FDRE #(
.INIT(1'b0),
.IS_C_INVERTED(1'b0),
.IS_D_INVERTED(1'b0),
.IS_R_INVERTED(1'b0))
\TCSR1_GENERATE[31].TCSR1_FF_I
(.C(s_axi_aclk),
.CE(bus2ip_wrce[0]),
.D(s_axi_wdata[0]),
.Q(read_Mux_In[63]),
.R(SR));
FDRE captureTrig0_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_d),
.Q(captureTrig0_d2),
.R(SR));
FDRE captureTrig0_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_d0),
.Q(captureTrig0_d),
.R(SR));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT2 #(
.INIT(4'h2))
captureTrig0_pulse_d1_i_1
(.I0(captureTrig0_d),
.I1(captureTrig0_d2),
.O(captureTrig0_pulse_d1_i_1_n_0));
FDRE captureTrig0_pulse_d1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_pulse_d1_i_1_n_0),
.Q(captureTrig0_pulse_d1),
.R(SR));
FDRE captureTrig0_pulse_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig0_pulse_d1),
.Q(captureTrig0_pulse_d2),
.R(SR));
FDRE captureTrig1_d2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig1_d),
.Q(captureTrig1_d2),
.R(SR));
FDRE captureTrig1_d_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(captureTrig1_d0),
.Q(captureTrig1_d),
.R(SR));
FDRE counter_TC_Reg2_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(Q[1]),
.Q(counter_TC_Reg2),
.R(SR));
FDRE \counter_TC_Reg_reg[0]
(.C(s_axi_aclk),
.CE(1'b1),
.D(counter_TC[0]),
.Q(Q[1]),
.R(SR));
FDRE \counter_TC_Reg_reg[1]
(.C(s_axi_aclk),
.CE(1'b1),
.D(counter_TC[1]),
.Q(Q[0]),
.R(SR));
FDRE generateOutPre0_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out_reg[32]_0 ),
.Q(generateOutPre0),
.R(SR));
FDRE generateOutPre1_reg
(.C(s_axi_aclk),
.CE(1'b1),
.D(\INFERRED_GEN.icount_out_reg[32] ),
.Q(generateOutPre1),
.R(SR));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//////////////////////////////////////////////////////////////////////////////////
// NPCG_Toggle_Top for Cosmos OpenSSD
// Copyright (c) 2015 Hanyang University ENC Lab.
// Contributed by Ilyong Jung <[email protected]>
// Yong Ho Song <[email protected]>
//
// This file is part of Cosmos OpenSSD.
//
// Cosmos OpenSSD is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 3, or (at your option)
// any later version.
//
// Cosmos OpenSSD is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
// See the GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with Cosmos OpenSSD; see the file COPYING.
// If not, see <http://www.gnu.org/licenses/>.
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Company: ENC Lab. <http://enc.hanyang.ac.kr>
// Engineer: Ilyong Jung <[email protected]>
//
// Project Name: Cosmos OpenSSD
// Design Name: NPCG_Toggle_Top
// Module Name: NPCG_Toggle_Top
// File Name: NPCG_Toggle_Top.v
//
// Version: v1.0.0
//
// Description: NFC PCG layer top
//
//////////////////////////////////////////////////////////////////////////////////
//////////////////////////////////////////////////////////////////////////////////
// Revision History:
//
// * v1.0.0
// - first draft
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module NPCG_Toggle_Top
#
(
parameter NumberOfWays = 4
)
(
iSystemClock ,
iReset ,
iOpcode ,
iTargetID ,
iSourceID ,
iAddress ,
iLength ,
iCMDValid ,
oCMDReady ,
iWriteData ,
iWriteLast ,
iWriteValid ,
oWriteReady ,
oReadData ,
oReadLast ,
oReadValid ,
iReadReady ,
oReadyBusy ,
iPM_Ready ,
iPM_LastStep ,
oPM_PCommand ,
oPM_PCommandOption ,
oPM_TargetWay ,
oPM_NumOfData ,
oPM_CEHold ,
oPM_NANDPowerOnEvent ,
oPM_CASelect ,
oPM_CAData ,
oPM_WriteData ,
oPM_WriteLast ,
oPM_WriteValid ,
iPM_WriteReady ,
iPM_ReadData ,
iPM_ReadLast ,
iPM_ReadValid ,
oPM_ReadReady ,
iReadyBusy
);
// Primitive Command Genertor (P.C.G.)
// ID: 00100, 00101
// about R/B- signal ...
// R/B- signal is unused because of debouncing. (reported by Huh-huhtae)
//
// solution 1. add physical lpf in circuit level
// solution 2. add logical lpf to register (maybe memory mapped)
// solution 3. use "status check" command instead of R/B- signal
// (status register has R/B- bit)
// 필요 외부 모듈
//
// -> page read (AW) (30h)
// -> page read (DT) (00h)
// -> page program (10h)
// -> block erase (D0h)
//
// -> set features
// -> read ID
// -> read status
// -> reset: NAND initializing
//
// -> PHY. reset: PO
// -> PHY. reset: PI
// -> NAND Power-ON Event
//
// -> bus high-Z delay
// iPCommand[7:0]: not support parallel primitive command execution
// must set only 1 bit
//
// iPCommand[7]: .......... (reserved)
// iPCommand[6]: PHY Buffer Reset
// iPCommand[5]: PO Reset
// iPCommand[4]: PI Reset
// iPCommand[3]: C/A Latch
// iPCommand[2]: Data Out
// iPCommand[1]: Data In
// iPCommand[0]: Timer
//parameter NumofbCMD = 12; // number of blocking commands
// [11]: MNC_getFT, get features (100101)
// [10]: SCC_N_poe, NAND Power-ON Event (111110)
// [ 9]: SCC_PI_reset, PHY. reset: PI (110010)
// [ 8]: SCC_PO_reset, PHY. reset: PO (110000)
// [ 7]: MNC_N_init, reset: NAND initializing (101100)
// [ 6]: MNC_readST, read status (DDR) (101001)
// [ 5]: MNC_readID, read ID (101011 + length[7:0](option, 00h/40h))
// [ 4]: MNC_setFT, set features (SDR/DDR) (100000/100001 + length[7:0](option, 01h/02h/10h/30h))
// [ 3]: BNC_B_erase, block erase: address write, execute (D0h) (001000)
// [ 2]: BNC_P_program, page program: address write, data transfer (10h) (000100 + length[15:0](length, word))
// [ 1]: BNC_P_read_DT00h, page read (DT): data transfer after read status (00h) (000011 + length[15:0](length, word))
// [ 0]: BNC_P_read_AW30h, page read (AW): address write (30h) (000000)
input iSystemClock ;
input iReset ;
input [5:0] iOpcode ;
input [4:0] iTargetID ;
input [4:0] iSourceID ;
input [31:0] iAddress ;
input [15:0] iLength ;
input iCMDValid ;
output oCMDReady ;
input [31:0] iWriteData ;
input iWriteLast ;
input iWriteValid ;
output oWriteReady ;
output [31:0] oReadData ;
output oReadLast ;
output oReadValid ;
input iReadReady ;
output [NumberOfWays - 1:0] oReadyBusy ;
input [7:0] iPM_Ready ;
input [7:0] iPM_LastStep ;
output [7:0] oPM_PCommand ;
output [2:0] oPM_PCommandOption ;
output [NumberOfWays - 1:0] oPM_TargetWay ;
output [15:0] oPM_NumOfData ;
output oPM_CEHold ;
output oPM_NANDPowerOnEvent ;
output oPM_CASelect ;
output [7:0] oPM_CAData ;
output [31:0] oPM_WriteData ;
output oPM_WriteLast ;
output oPM_WriteValid ;
input iPM_WriteReady ;
input [31:0] iPM_ReadData ;
input iPM_ReadLast ;
input iPM_ReadValid ;
output oPM_ReadReady ;
input [NumberOfWays - 1:0] iReadyBusy ;
localparam NumofbCMD = 12;
// Internal Wires/Regs
reg rNANDPOE ;
reg [3:0] rNANDPOECounter ;
wire wNANDPOECounterDone ;
reg rPM_NANDPowerOnEvent ;
reg [7:0] rTargetWay1B ;
reg [15:0] rColAddr2B ;
reg [23:0] rRowAddr3B ;
wire [15:0] wLength_m1 ;
wire wTGC_waySELECT ;
wire wTGC_colADDR ;
wire wTGC_rowADDR ;
wire isNonbCMD ;
wire [5:0] wOpcode_bCMD ;
wire [4:0] wTargetID_bCMD ;
wire [4:0] wSourceID_bCMD ;
wire wCMDValid_NPOE ;
wire wCMDValid_bCMD ;
wire wCMDReady_bCMD ;
wire [NumberOfWays - 1:0] wTargetWay ;
wire [15:0] wTargetCol ;
wire [23:0] wTargetRow ;
wire [NumofbCMD - 1:0] wbCMDReadySet ;
wire [NumofbCMD - 1:0] wbCMDStartSet ;
wire [NumofbCMD - 1:0] wbCMDLastSet ;
wire wbCMDReady ; // "AND"
wire wbCMDStart ; // "OR"
wire wbCMDLast ; // "OR"
wire wbCMDLast_SCC ; // "OR"
wire [NumberOfWays - 1:0] wWorkingWay ;
wire wCMDHold ;
// bCMD wires
// - IDLE codition
wire wIDLE_WriteReady ;
wire [31:0] wIDLE_ReadData ;
wire wIDLE_ReadLast ;
wire wIDLE_ReadValid ;
wire [7:0] wIDLE_PM_PCommand ;
wire [2:0] wIDLE_PM_PCommandOption ;
wire [NumberOfWays - 1:0] wIDLE_PM_TargetWay ;
wire [15:0] wIDLE_PM_NumOfData ;
wire wIDLE_PM_CASelect ;
wire [7:0] wIDLE_PM_CAData ;
wire [31:0] wIDLE_PM_WriteData ;
wire wIDLE_PM_WriteLast ;
wire wIDLE_PM_WriteValid ;
wire wIDLE_PM_ReadReady ;
// - State Machine: MNC_getFT
wire wMNC_getFT_Ready ;
wire wMNC_getFT_Start ;
wire wMNC_getFT_Last ;
wire [31:0] wMNC_getFT_ReadData ;
wire wMNC_getFT_ReadLast ;
wire wMNC_getFT_ReadValid ;
wire [7:0] wMNC_getFT_PM_PCommand ;
wire [2:0] wMNC_getFT_PM_PCommandOption;
wire [NumberOfWays - 1:0] wMNC_getFT_PM_TargetWay ;
wire [15:0] wMNC_getFT_PM_NumOfData ;
wire wMNC_getFT_PM_CASelect ;
wire [7:0] wMNC_getFT_PM_CAData ;
wire wMNC_getFT_PM_ReadReady ;
// - State Machine: SCC_N_poe
wire wSCC_N_poe_Ready ;
wire wSCC_N_poe_Start ;
wire wSCC_N_poe_Last ;
wire [7:0] wSCC_N_poe_PM_PCommand ;
wire [2:0] wSCC_N_poe_PM_PCommandOption;
wire [15:0] wSCC_N_poe_PM_NumOfData;
// - State Machine: SCC_PI_reset
wire wSCC_PI_reset_Ready ;
wire wSCC_PI_reset_Start ;
wire wSCC_PI_reset_Last ;
wire [7:0] wSCC_PI_reset_PM_PCommand ;
// - State Machine: SCC_PO_reset
wire wSCC_PO_reset_Ready ;
wire wSCC_PO_reset_Start ;
wire wSCC_PO_reset_Last ;
wire [7:0] wSCC_PO_reset_PM_PCommand ;
// - State Machine: MNC_N_init
wire wMNC_N_init_Ready ;
wire wMNC_N_init_Start ;
wire wMNC_N_init_Last ;
wire [7:0] wMNC_N_init_PM_PCommand ;
wire [2:0] wMNC_N_init_PM_PCommandOption;
wire [NumberOfWays - 1:0] wMNC_N_init_PM_TargetWay;
wire [15:0] wMNC_N_init_PM_NumOfData;
wire wMNC_N_init_PM_CASelect ;
wire [7:0] wMNC_N_init_PM_CAData ;
// - State Machine: MNC_readST
wire wMNC_readST_Ready ;
wire wMNC_readST_Start ;
wire wMNC_readST_Last ;
wire [31:0] wMNC_readST_ReadData ;
wire wMNC_readST_ReadLast ;
wire wMNC_readST_ReadValid ;
wire [7:0] wMNC_readST_PM_PCommand ;
wire [2:0] wMNC_readST_PM_PCommandOption;
wire [NumberOfWays - 1:0] wMNC_readST_PM_TargetWay;
wire [15:0] wMNC_readST_PM_NumOfData;
wire wMNC_readST_PM_CASelect ;
wire [7:0] wMNC_readST_PM_CAData ;
wire wMNC_readST_PM_ReadReady;
// - State Machine: MNC_readID
// - State Machine: MNC_setFT
wire wMNC_setFT_Ready ;
wire wMNC_setFT_Start ;
wire wMNC_setFT_Last ;
wire wMNC_setFT_WriteReady ;
wire [7:0] wMNC_setFT_PM_PCommand ;
wire [2:0] wMNC_setFT_PM_PCommandOption ;
wire [NumberOfWays - 1:0] wMNC_setFT_PM_TargetWay ;
wire [15:0] wMNC_setFT_PM_NumOfData ;
wire wMNC_setFT_PM_CASelect ;
wire [7:0] wMNC_setFT_PM_CAData ;
wire [31:0] wMNC_setFT_PM_WriteData ;
wire wMNC_setFT_PM_WriteLast ;
wire wMNC_setFT_PM_WriteValid ;
// - State Machine: BNC_B_erase
wire wBNC_B_erase_Ready ;
wire wBNC_B_erase_Start ;
wire wBNC_B_erase_Last ;
wire [7:0] wBNC_B_erase_PM_PCommand ;
wire [2:0] wBNC_B_erase_PM_PCommandOption;
wire [NumberOfWays - 1:0] wBNC_B_erase_PM_TargetWay;
wire [15:0] wBNC_B_erase_PM_NumOfData;
wire wBNC_B_erase_PM_CASelect ;
wire [7:0] wBNC_B_erase_PM_CAData ;
// - State Machine: BNC_P_program
wire wBNC_P_prog_Ready ;
wire wBNC_P_prog_Start ;
wire wBNC_P_prog_Last ;
wire wBNC_P_prog_WriteReady ;
wire [7:0] wBNC_P_prog_PM_PCommand ;
wire [2:0] wBNC_P_prog_PM_PCommandOption ;
wire [NumberOfWays - 1:0] wBNC_P_prog_PM_TargetWay ;
wire [15:0] wBNC_P_prog_PM_NumOfData ;
wire wBNC_P_prog_PM_CASelect ;
wire [7:0] wBNC_P_prog_PM_CAData ;
wire [31:0] wBNC_P_prog_PM_WriteData ;
wire wBNC_P_prog_PM_WriteLast ;
wire wBNC_P_prog_PM_WriteValid ;
// - State Machine: BNC_P_read_DT00h
wire wBNC_P_read_DT00h_Ready ;
wire wBNC_P_read_DT00h_Start ;
wire wBNC_P_read_DT00h_Last ;
wire [31:0] wBNC_P_read_DT00h_ReadData ;
wire wBNC_P_read_DT00h_ReadLast ;
wire wBNC_P_read_DT00h_ReadValid ;
wire [7:0] wBNC_P_read_DT00h_PM_PCommand ;
wire [2:0] wBNC_P_read_DT00h_PM_PCommandOption;
wire [NumberOfWays - 1:0] wBNC_P_read_DT00h_PM_TargetWay;
wire [15:0] wBNC_P_read_DT00h_PM_NumOfData;
wire wBNC_P_read_DT00h_PM_CASelect ;
wire [7:0] wBNC_P_read_DT00h_PM_CAData ;
wire wBNC_P_read_DT00h_PM_ReadReady;
// - State Machine: BNC_P_read_AW30h
wire wBNC_P_read_AW30h_Ready ;
wire wBNC_P_read_AW30h_Start ;
wire wBNC_P_read_AW30h_Last ;
wire [7:0] wBNC_P_read_AW30h_PM_PCommand ;
wire [2:0] wBNC_P_read_AW30h_PM_PCommandOption;
wire [NumberOfWays - 1:0] wBNC_P_read_AW30h_PM_TargetWay;
wire [15:0] wBNC_P_read_AW30h_PM_NumOfData;
wire wBNC_P_read_AW30h_PM_CASelect ;
wire [7:0] wBNC_P_read_AW30h_PM_CAData ;
// Control Signals
assign wTGC_waySELECT = (iTargetID[4:0] == 5'b00100) & (iOpcode[5:0] == 6'b000000) & (iCMDValid);
assign wTGC_colADDR = (iTargetID[4:0] == 5'b00100) & (iOpcode[5:0] == 6'b000010) & (iCMDValid);
assign wTGC_rowADDR = (iTargetID[4:0] == 5'b00100) & (iOpcode[5:0] == 6'b000100) & (iCMDValid);
assign isNonbCMD = wTGC_waySELECT // write way select
| wTGC_colADDR // write col addr
| wTGC_rowADDR ; // write row addr
assign oCMDReady = (isNonbCMD)? (1'b1):(wCMDReady_bCMD);
assign wTargetWay[NumberOfWays - 1:0] = rTargetWay1B[NumberOfWays - 1:0];
assign wTargetCol[15:0] = rColAddr2B[15:0];
assign wTargetRow[23:0] = rRowAddr3B[23:0];
assign wNANDPOECounterDone = &(rNANDPOECounter[3:0]);
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rNANDPOE <= 1'b1;
rNANDPOECounter[3:0] <= 4'b0000;
rPM_NANDPowerOnEvent <= 1'b1;
end else begin
rNANDPOE <= (rNANDPOE)? ((wbCMDLastSet[10])? 1'b0:1'b1):1'b0;
rNANDPOECounter[3:0] <= (wNANDPOECounterDone)? (rNANDPOECounter[3:0]):(rNANDPOECounter[3:0] + 1'b1);
rPM_NANDPowerOnEvent <= (wNANDPOECounterDone)? 1'b0:1'b1;
end
end
always @ (posedge iSystemClock, posedge iReset) begin
if (iReset) begin
rTargetWay1B[7:0] <= 0;
rColAddr2B[15:0] <= 0;
rRowAddr3B[23:0] <= 0;
end else begin
if (wTGC_waySELECT) begin
rTargetWay1B[7:0] <= iAddress[7:0];
rColAddr2B[15:0] <= rColAddr2B[15:0];
rRowAddr3B[23:0] <= rRowAddr3B[23:0];
end else if (wTGC_colADDR) begin
rTargetWay1B[7:0] <= rTargetWay1B[7:0];
rColAddr2B[15:0] <= iAddress[15:0];
rRowAddr3B[23:0] <= rRowAddr3B[23:0];
end else if (wTGC_rowADDR) begin
rTargetWay1B[7:0] <= rTargetWay1B[7:0];
rColAddr2B[15:0] <= rColAddr2B[15:0];
rRowAddr3B[23:0] <= iAddress[23:0];
end else begin
rTargetWay1B[7:0] <= rTargetWay1B[7:0];
rColAddr2B[15:0] <= rColAddr2B[15:0];
rRowAddr3B[23:0] <= rRowAddr3B[23:0];
end
end
end
assign wLength_m1[15:0] = iLength[15:0] - 1'b1;
NPCG_Toggle_way_CE_timer
#
(
.NumberOfWays (NumberOfWays )
)
way_CE_condition_timer
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iWorkingWay (wWorkingWay ),
.ibCMDLast (wbCMDLast ),
.ibCMDLast_SCC (wbCMDLast_SCC ),
.iTargetWay (wTargetWay ),
.oCMDHold (wCMDHold )
);
NPCG_Toggle_bCMD_manager
#
(
.NumberOfWays (NumberOfWays )
)
blocking_CMD_manager
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iTargetWay (wTargetWay ),
.ibCMDStart (wbCMDStart ),
.ibCMDLast (wbCMDLast ),
.ibCMDLast_SCC (wbCMDLast_SCC ),
.iNANDPOE (rNANDPOE ),
.iCMDHold (wCMDHold ),
.iOpcode (iOpcode ),
.iTargetID (iTargetID ),
.iSourceID (iSourceID ),
.oOpcode_out (wOpcode_bCMD ),
.oTargetID_out (wTargetID_bCMD ),
.oSourceID_out (wSourceID_bCMD ),
.iCMDValid_in (iCMDValid ),
.oCMDValid_out_NPOE (wCMDValid_NPOE ),
.oCMDValid_out (wCMDValid_bCMD ),
.oCMDReady_out (wCMDReady_bCMD ),
.iCMDReady_in (wbCMDReady ),
.oWorkingWay (wWorkingWay )
);
assign wbCMDReadySet[NumofbCMD-1:0] = { wMNC_getFT_Ready, wSCC_N_poe_Ready, wSCC_PI_reset_Ready, wSCC_PO_reset_Ready, wMNC_N_init_Ready, wMNC_readST_Ready, 1'b1, wMNC_setFT_Ready, wBNC_B_erase_Ready, wBNC_P_prog_Ready, wBNC_P_read_DT00h_Ready, wBNC_P_read_AW30h_Ready };
assign wbCMDStartSet[NumofbCMD-1:0] = { wMNC_getFT_Start, wSCC_N_poe_Start, wSCC_PI_reset_Start, wSCC_PO_reset_Start, wMNC_N_init_Start, wMNC_readST_Start, 1'b0, wMNC_setFT_Start, wBNC_B_erase_Start, wBNC_P_prog_Start, wBNC_P_read_DT00h_Start, wBNC_P_read_AW30h_Start };
assign wbCMDLastSet[NumofbCMD-1:0] = { wMNC_getFT_Last, wSCC_N_poe_Last, wSCC_PI_reset_Last, wSCC_PO_reset_Last, wMNC_N_init_Last, wMNC_readST_Last, 1'b0, wMNC_setFT_Last, wBNC_B_erase_Last, wBNC_P_prog_Last, wBNC_P_read_DT00h_Last, wBNC_P_read_AW30h_Last };
assign wbCMDReady = &(wbCMDReadySet); // "AND" all blocking CMD machine's ready
assign wbCMDStart = |(wbCMDStartSet); // "OR" all blocking CMD machine's start
assign wbCMDLast = |(wbCMDLastSet); // "OR" all blocking CMD machine's last
assign wbCMDLast_SCC = |({ wSCC_N_poe_Last, wSCC_PI_reset_Last, wSCC_PO_reset_Last });
// IDLE codition
NPCG_Toggle_bCMD_IDLE
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_IDLE
(
.oWriteReady (wIDLE_WriteReady ),
.oReadData (wIDLE_ReadData ),
.oReadLast (wIDLE_ReadLast ),
.oReadValid (wIDLE_ReadValid ),
.oPM_PCommand (wIDLE_PM_PCommand ),
.oPM_PCommandOption (wIDLE_PM_PCommandOption),
.oPM_TargetWay (wIDLE_PM_TargetWay ),
.oPM_NumOfData (wIDLE_PM_NumOfData ),
.oPM_CASelect (wIDLE_PM_CASelect ),
.oPM_CAData (wIDLE_PM_CAData ),
.oPM_WriteData (wIDLE_PM_WriteData ),
.oPM_WriteLast (wIDLE_PM_WriteLast ),
.oPM_WriteValid (wIDLE_PM_WriteValid ),
.oPM_ReadReady (wIDLE_PM_ReadReady )
);
// State Machine: MNC_getFT
NPCG_Toggle_MNC_getFT
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_MNC_getFT
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iLength (iLength[7:0] ), // shrinked
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wMNC_getFT_Ready ),
.oReadData (wMNC_getFT_ReadData ),
.oReadLast (wMNC_getFT_ReadLast ),
.oReadValid (wMNC_getFT_ReadValid ),
.iReadReady (iReadReady ),
.iWaySelect (wTargetWay ),
.oStart (wMNC_getFT_Start ),
.oLastStep (wMNC_getFT_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wMNC_getFT_PM_PCommand ),
.oPM_PCommandOption (wMNC_getFT_PM_PCommandOption),
.oPM_TargetWay (wMNC_getFT_PM_TargetWay),
.oPM_NumOfData (wMNC_getFT_PM_NumOfData),
.oPM_CASelect (wMNC_getFT_PM_CASelect ),
.oPM_CAData (wMNC_getFT_PM_CAData ),
.iPM_ReadData (iPM_ReadData ),
.iPM_ReadLast (iPM_ReadLast ),
.iPM_ReadValid (iPM_ReadValid ),
.oPM_ReadReady (wMNC_getFT_PM_ReadReady)
);
// State Machine: SCC_N_poe
NPCG_Toggle_SCC_N_poe
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_SCC_N_poe
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
//.iCMDValid (wCMDValid_bCMD ),
.iCMDValid (wCMDValid_NPOE ),
.oCMDReady (wSCC_N_poe_Ready ),
.oStart (wSCC_N_poe_Start ),
.oLastStep (wSCC_N_poe_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wSCC_N_poe_PM_PCommand ),
.oPM_PCommandOption (wSCC_N_poe_PM_PCommandOption),
.oPM_NumOfData (wSCC_N_poe_PM_NumOfData)
);
// State Machine: SCC_PI_reset
NPCG_Toggle_SCC_PI_reset
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_SCC_PI_reset
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wSCC_PI_reset_Ready ),
.oStart (wSCC_PI_reset_Start ),
.oLastStep (wSCC_PI_reset_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wSCC_PI_reset_PM_PCommand)
);
// State Machine: SCC_PO_reset
NPCG_Toggle_SCC_PO_reset
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_SCC_PO_reset
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wSCC_PO_reset_Ready ),
.oStart (wSCC_PO_reset_Start ),
.oLastStep (wSCC_PO_reset_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wSCC_PO_reset_PM_PCommand)
);
// State Machine: MNC_N_init
NPCG_Toggle_MNC_N_init
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_MNC_N_init
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wMNC_N_init_Ready ),
.iWaySelect (wTargetWay ),
.oStart (wMNC_N_init_Start ),
.oLastStep (wMNC_N_init_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wMNC_N_init_PM_PCommand),
.oPM_PCommandOption (wMNC_N_init_PM_PCommandOption),
.oPM_TargetWay (wMNC_N_init_PM_TargetWay),
.oPM_NumOfData (wMNC_N_init_PM_NumOfData),
.oPM_CASelect (wMNC_N_init_PM_CASelect),
.oPM_CAData (wMNC_N_init_PM_CAData )
);
// State Machine: MNC_readST
NPCG_Toggle_MNC_readST
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_MNC_readST
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wMNC_readST_Ready ),
.oReadData (wMNC_readST_ReadData ),
.oReadLast (wMNC_readST_ReadLast ),
.oReadValid (wMNC_readST_ReadValid ),
.iReadReady (iReadReady ),
.iWaySelect (wTargetWay ),
.oStart (wMNC_readST_Start ),
.oLastStep (wMNC_readST_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wMNC_readST_PM_PCommand),
.oPM_PCommandOption (wMNC_readST_PM_PCommandOption),
.oPM_TargetWay (wMNC_readST_PM_TargetWay),
.oPM_NumOfData (wMNC_readST_PM_NumOfData),
.oPM_CASelect (wMNC_readST_PM_CASelect),
.oPM_CAData (wMNC_readST_PM_CAData ),
.iPM_ReadData (iPM_ReadData ),
.iPM_ReadLast (iPM_ReadLast ),
.iPM_ReadValid (iPM_ReadValid ),
.oPM_ReadReady (wMNC_readST_PM_ReadReady)
);
// State Machine: MNC_readID
// State Machine: MNC_setFT
NPCG_Toggle_MNC_setFT
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_MNC_setFT
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iLength (iLength[7:0] ), // shrinked
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wMNC_setFT_Ready ),
.iWriteData (iWriteData ),
.iWriteLast (iWriteLast ),
.iWriteValid (iWriteValid ),
.oWriteReady (wMNC_setFT_WriteReady ),
.iWaySelect (wTargetWay ),
.oStart (wMNC_setFT_Start ),
.oLastStep (wMNC_setFT_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wMNC_setFT_PM_PCommand ),
.oPM_PCommandOption (wMNC_setFT_PM_PCommandOption),
.oPM_TargetWay (wMNC_setFT_PM_TargetWay),
.oPM_NumOfData (wMNC_setFT_PM_NumOfData),
.oPM_CASelect (wMNC_setFT_PM_CASelect ),
.oPM_CAData (wMNC_setFT_PM_CAData ),
.oPM_WriteData (wMNC_setFT_PM_WriteData),
.oPM_WriteLast (wMNC_setFT_PM_WriteLast),
.oPM_WriteValid (wMNC_setFT_PM_WriteValid),
.iPM_WriteReady (iPM_WriteReady )
);
// State Machine: BNC_B_erase
NPCG_Toggle_BNC_B_erase
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_BNC_B_erase
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wBNC_B_erase_Ready ),
.iWaySelect (wTargetWay ),
.iColAddress (wTargetCol ),
.iRowAddress (wTargetRow ),
.oStart (wBNC_B_erase_Start ),
.oLastStep (wBNC_B_erase_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wBNC_B_erase_PM_PCommand),
.oPM_PCommandOption (wBNC_B_erase_PM_PCommandOption),
.oPM_TargetWay (wBNC_B_erase_PM_TargetWay),
.oPM_NumOfData (wBNC_B_erase_PM_NumOfData),
.oPM_CASelect (wBNC_B_erase_PM_CASelect),
.oPM_CAData (wBNC_B_erase_PM_CAData )
);
// State Machine: BNC_P_program
NPCG_Toggle_BNC_P_program
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_BNC_P_program
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iLength (wLength_m1 ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wBNC_P_prog_Ready ),
.iWriteData (iWriteData ),
.iWriteLast (iWriteLast ),
.iWriteValid (iWriteValid ),
.oWriteReady (wBNC_P_prog_WriteReady ),
.iWaySelect (wTargetWay ),
.iColAddress (wTargetCol ),
.iRowAddress (wTargetRow ),
.oStart (wBNC_P_prog_Start ),
.oLastStep (wBNC_P_prog_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wBNC_P_prog_PM_PCommand),
.oPM_PCommandOption (wBNC_P_prog_PM_PCommandOption),
.oPM_TargetWay (wBNC_P_prog_PM_TargetWay),
.oPM_NumOfData (wBNC_P_prog_PM_NumOfData),
.oPM_CASelect (wBNC_P_prog_PM_CASelect),
.oPM_CAData (wBNC_P_prog_PM_CAData ),
.oPM_WriteData (wBNC_P_prog_PM_WriteData),
.oPM_WriteLast (wBNC_P_prog_PM_WriteLast),
.oPM_WriteValid (wBNC_P_prog_PM_WriteValid),
.iPM_WriteReady (iPM_WriteReady )
);
// State Machine: BNC_P_read_DT00h
NPCG_Toggle_BNC_P_read_DT00h
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_BNC_P_read_DT00h
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iLength (wLength_m1 ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wBNC_P_read_DT00h_Ready),
.oReadData (wBNC_P_read_DT00h_ReadData),
.oReadLast (wBNC_P_read_DT00h_ReadLast),
.oReadValid (wBNC_P_read_DT00h_ReadValid),
.iReadReady (iReadReady ),
.iWaySelect (wTargetWay ),
.iColAddress (wTargetCol ),
.iRowAddress (wTargetRow ),
.oStart (wBNC_P_read_DT00h_Start),
.oLastStep (wBNC_P_read_DT00h_Last),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wBNC_P_read_DT00h_PM_PCommand),
.oPM_PCommandOption (wBNC_P_read_DT00h_PM_PCommandOption),
.oPM_TargetWay (wBNC_P_read_DT00h_PM_TargetWay),
.oPM_NumOfData (wBNC_P_read_DT00h_PM_NumOfData),
.oPM_CASelect (wBNC_P_read_DT00h_PM_CASelect),
.oPM_CAData (wBNC_P_read_DT00h_PM_CAData),
.iPM_ReadData (iPM_ReadData ),
.iPM_ReadLast (iPM_ReadLast ),
.iPM_ReadValid (iPM_ReadValid ),
.oPM_ReadReady (wBNC_P_read_DT00h_PM_ReadReady)
);
// State Machine: BNC_P_read_AW30h
NPCG_Toggle_BNC_P_read_AW30h
#
(
.NumberOfWays (NumberOfWays )
)
bCMD_BNC_P_read_AW30h
(
.iSystemClock (iSystemClock ),
.iReset (iReset ),
.iOpcode (wOpcode_bCMD ),
.iTargetID (wTargetID_bCMD ),
.iSourceID (wSourceID_bCMD ),
.iCMDValid (wCMDValid_bCMD ),
.oCMDReady (wBNC_P_read_AW30h_Ready),
.iWaySelect (wTargetWay ),
.iColAddress (wTargetCol ),
.iRowAddress (wTargetRow ),
.oStart (wBNC_P_read_AW30h_Start),
.oLastStep (wBNC_P_read_AW30h_Last ),
.iPM_Ready (iPM_Ready ),
.iPM_LastStep (iPM_LastStep ),
.oPM_PCommand (wBNC_P_read_AW30h_PM_PCommand),
.oPM_PCommandOption (wBNC_P_read_AW30h_PM_PCommandOption),
.oPM_TargetWay (wBNC_P_read_AW30h_PM_TargetWay),
.oPM_NumOfData (wBNC_P_read_AW30h_PM_NumOfData),
.oPM_CASelect (wBNC_P_read_AW30h_PM_CASelect),
.oPM_CAData (wBNC_P_read_AW30h_PM_CAData)
);
NPCG_Toggle_bCMDMux
#
(
.NumofbCMD (NumofbCMD ),
.NumberOfWays (NumberOfWays )
)
bCMD_Mux
(
.ibCMDReadySet (wbCMDReadySet ),
// State Machines Output
// - IDLE codition
.iIDLE_WriteReady (wIDLE_WriteReady ),
.iIDLE_ReadData (wIDLE_ReadData ),
.iIDLE_ReadLast (wIDLE_ReadLast ),
.iIDLE_ReadValid (wIDLE_ReadValid ),
.iIDLE_PM_PCommand (wIDLE_PM_PCommand ),
.iIDLE_PM_PCommandOption(wIDLE_PM_PCommandOption),
.iIDLE_PM_TargetWay (wIDLE_PM_TargetWay ),
.iIDLE_PM_NumOfData (wIDLE_PM_NumOfData ),
.iIDLE_PM_CASelect (wIDLE_PM_CASelect ),
.iIDLE_PM_CAData (wIDLE_PM_CAData ),
.iIDLE_PM_WriteData (wIDLE_PM_WriteData ),
.iIDLE_PM_WriteLast (wIDLE_PM_WriteLast ),
.iIDLE_PM_WriteValid (wIDLE_PM_WriteValid ),
.iIDLE_PM_ReadReady (wIDLE_PM_ReadReady ),
// - State Machine: MNC_getFT
.iMNC_getFT_ReadData (wMNC_getFT_ReadData ),
.iMNC_getFT_ReadLast (wMNC_getFT_ReadLast ),
.iMNC_getFT_ReadValid (wMNC_getFT_ReadValid ),
.iMNC_getFT_PM_PCommand (wMNC_getFT_PM_PCommand ),
.iMNC_getFT_PM_PCommandOption(wMNC_getFT_PM_PCommandOption),
.iMNC_getFT_PM_TargetWay(wMNC_getFT_PM_TargetWay),
.iMNC_getFT_PM_NumOfData(wMNC_getFT_PM_NumOfData),
.iMNC_getFT_PM_CASelect (wMNC_getFT_PM_CASelect ),
.iMNC_getFT_PM_CAData (wMNC_getFT_PM_CAData ),
.iMNC_getFT_PM_ReadReady(wMNC_getFT_PM_ReadReady),
// - State Machine: SCC_N_poe
.iSCC_N_poe_PM_PCommand (wSCC_N_poe_PM_PCommand ),
.iSCC_N_poe_PM_PCommandOption(wSCC_N_poe_PM_PCommandOption),
.iSCC_N_poe_PM_NumOfData(wSCC_N_poe_PM_NumOfData),
// - State Machine: SCC_PI_reset
.iSCC_PI_reset_PM_PCommand(wSCC_PI_reset_PM_PCommand),
// - State Machine: SCC_PO_reset
.iSCC_PO_reset_PM_PCommand(wSCC_PO_reset_PM_PCommand),
// - State Machine: MNC_N_init
.iMNC_N_init_PM_PCommand(wMNC_N_init_PM_PCommand),
.iMNC_N_init_PM_PCommandOption(wMNC_N_init_PM_PCommandOption),
.iMNC_N_init_PM_TargetWay(wMNC_N_init_PM_TargetWay),
.iMNC_N_init_PM_NumOfData(wMNC_N_init_PM_NumOfData),
.iMNC_N_init_PM_CASelect(wMNC_N_init_PM_CASelect),
.iMNC_N_init_PM_CAData(wMNC_N_init_PM_CAData),
// - State Machine: MNC_readST
.iMNC_readST_ReadData (wMNC_readST_ReadData ),
.iMNC_readST_ReadLast (wMNC_readST_ReadLast ),
.iMNC_readST_ReadValid (wMNC_readST_ReadValid ),
.iMNC_readST_PM_PCommand(wMNC_readST_PM_PCommand),
.iMNC_readST_PM_PCommandOption(wMNC_readST_PM_PCommandOption),
.iMNC_readST_PM_TargetWay(wMNC_readST_PM_TargetWay),
.iMNC_readST_PM_NumOfData(wMNC_readST_PM_NumOfData),
.iMNC_readST_PM_CASelect(wMNC_readST_PM_CASelect),
.iMNC_readST_PM_CAData (wMNC_readST_PM_CAData ),
.iMNC_readST_PM_ReadReady(wMNC_readST_PM_ReadReady),
// - State Machine: MNC_readID
// - State Machine: MNC_setFT
.iMNC_setFT_WriteReady (wMNC_setFT_WriteReady),
.iMNC_setFT_PM_PCommand(wMNC_setFT_PM_PCommand),
.iMNC_setFT_PM_PCommandOption(wMNC_setFT_PM_PCommandOption),
.iMNC_setFT_PM_TargetWay(wMNC_setFT_PM_TargetWay),
.iMNC_setFT_PM_NumOfData(wMNC_setFT_PM_NumOfData),
.iMNC_setFT_PM_CASelect(wMNC_setFT_PM_CASelect),
.iMNC_setFT_PM_CAData (wMNC_setFT_PM_CAData ),
.iMNC_setFT_PM_WriteData(wMNC_setFT_PM_WriteData),
.iMNC_setFT_PM_WriteLast(wMNC_setFT_PM_WriteLast),
.iMNC_setFT_PM_WriteValid(wMNC_setFT_PM_WriteValid),
// - State Machine: BNC_B_erase
.iBNC_B_erase_PM_PCommand(wBNC_B_erase_PM_PCommand),
.iBNC_B_erase_PM_PCommandOption(wBNC_B_erase_PM_PCommandOption),
.iBNC_B_erase_PM_TargetWay(wBNC_B_erase_PM_TargetWay),
.iBNC_B_erase_PM_NumOfData(wBNC_B_erase_PM_NumOfData),
.iBNC_B_erase_PM_CASelect(wBNC_B_erase_PM_CASelect),
.iBNC_B_erase_PM_CAData (wBNC_B_erase_PM_CAData),
// - State Machine: BNC_P_program
.iBNC_P_prog_WriteReady (wBNC_P_prog_WriteReady),
.iBNC_P_prog_PM_PCommand(wBNC_P_prog_PM_PCommand),
.iBNC_P_prog_PM_PCommandOption(wBNC_P_prog_PM_PCommandOption),
.iBNC_P_prog_PM_TargetWay(wBNC_P_prog_PM_TargetWay),
.iBNC_P_prog_PM_NumOfData(wBNC_P_prog_PM_NumOfData),
.iBNC_P_prog_PM_CASelect(wBNC_P_prog_PM_CASelect),
.iBNC_P_prog_PM_CAData (wBNC_P_prog_PM_CAData ),
.iBNC_P_prog_PM_WriteData(wBNC_P_prog_PM_WriteData),
.iBNC_P_prog_PM_WriteLast(wBNC_P_prog_PM_WriteLast),
.iBNC_P_prog_PM_WriteValid(wBNC_P_prog_PM_WriteValid),
// - State Machine: BNC_P_read_DT00h
.iBNC_P_read_DT00h_ReadData (wBNC_P_read_DT00h_ReadData ),
.iBNC_P_read_DT00h_ReadLast (wBNC_P_read_DT00h_ReadLast ),
.iBNC_P_read_DT00h_ReadValid (wBNC_P_read_DT00h_ReadValid ),
.iBNC_P_read_DT00h_PM_PCommand(wBNC_P_read_DT00h_PM_PCommand),
.iBNC_P_read_DT00h_PM_PCommandOption(wBNC_P_read_DT00h_PM_PCommandOption),
.iBNC_P_read_DT00h_PM_TargetWay(wBNC_P_read_DT00h_PM_TargetWay),
.iBNC_P_read_DT00h_PM_NumOfData(wBNC_P_read_DT00h_PM_NumOfData),
.iBNC_P_read_DT00h_PM_CASelect(wBNC_P_read_DT00h_PM_CASelect),
.iBNC_P_read_DT00h_PM_CAData (wBNC_P_read_DT00h_PM_CAData ),
.iBNC_P_read_DT00h_PM_ReadReady(wBNC_P_read_DT00h_PM_ReadReady),
// - State Machine: BNC_P_read_AW30h
.iBNC_P_read_AW30h_PM_PCommand(wBNC_P_read_AW30h_PM_PCommand),
.iBNC_P_read_AW30h_PM_PCommandOption(wBNC_P_read_AW30h_PM_PCommandOption),
.iBNC_P_read_AW30h_PM_TargetWay(wBNC_P_read_AW30h_PM_TargetWay),
.iBNC_P_read_AW30h_PM_NumOfData(wBNC_P_read_AW30h_PM_NumOfData),
.iBNC_P_read_AW30h_PM_CASelect(wBNC_P_read_AW30h_PM_CASelect),
.iBNC_P_read_AW30h_PM_CAData(wBNC_P_read_AW30h_PM_CAData),
// Mux Output
// - Dispatcher Interface
// - Data Write Channel
.oWriteReady (oWriteReady),
// - Data Read Channel
.oReadData (oReadData),
.oReadLast (oReadLast),
.oReadValid (oReadValid),
// - NPCG_Toggle Interface
.oPM_PCommand (oPM_PCommand),
.oPM_PCommandOption (oPM_PCommandOption),
.oPM_TargetWay (oPM_TargetWay),
.oPM_NumOfData (oPM_NumOfData),
.oPM_CASelect (oPM_CASelect),
.oPM_CAData (oPM_CAData),
.oPM_WriteData (oPM_WriteData),
.oPM_WriteLast (oPM_WriteLast),
.oPM_WriteValid (oPM_WriteValid),
.oPM_ReadReady (oPM_ReadReady)
);
// Output
assign oPM_CEHold = 1'b0;
assign oPM_NANDPowerOnEvent = rPM_NANDPowerOnEvent;
assign oReadyBusy = iReadyBusy;
endmodule
|
/*
* Copyright (c) 2000 Steven Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This test looks for != operation in a continuous assignment.
*/
module test;
integer a;
integer b;
wire result;
integer error;
assign result = (a != b);
initial
begin
a = 0;
b = 0;
error = 0;
#5 ;
if( result === 1'b1)
error =1;
a = 1;
#5;
if( result === 1'b0)
error =1;
b = 1;
#5 ;
if( result === 1'b1)
error =1;
a = 1002;
b = 1001;
#5 ;
if( result === 1'b0)
error =1;
a = 1001;
#5 ;
if( result === 1'b1)
error =1;
if(error === 0)
$display("PASSED");
else
$display("FAILED");
end
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.will need a Picture Elements Binary Software
* License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program catches some glitches in the MUXZ that Icarus Verilog
* uses to implement the ?: in structural cases.
*/
module main;
reg [6:0] a, b;
reg sel;
wire [6:0] test = sel? a : b;
wire [7:0] test2 = test;
initial begin
sel = 0;
// At this point, test2 should be x.
#1 $display("sel=%b, test2=%b", sel, test2);
b = 0;
#1 $display("sel=b, test2=%b", sel, test2);
if (test2 !== 8'b0_0000000) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
(* Copyright © 1998-2006
* Henk Barendregt
* Luís Cruz-Filipe
* Herman Geuvers
* Mariusz Giero
* Rik van Ginneken
* Dimitri Hendriks
* Sébastien Hinderer
* Bart Kirkels
* Pierre Letouzey
* Iris Loeb
* Lionel Mamane
* Milad Niqui
* Russell O’Connor
* Randy Pollack
* Nickolay V. Shmyrev
* Bas Spitters
* Dan Synek
* Freek Wiedijk
* Jan Zwanenburg
*
* This work is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This work is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this work; if not, write to the Free Software Foundation, Inc.,
* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
*)
(** printing [-S-] %\ensuremath{\int}% #∫# *)
Require Export MoreIntegrals.
Require Export CalculusTheorems.
Opaque Min.
Section Indefinite_Integral.
(**
* The Fundamental Theorem of Calculus
Finally we can prove the fundamental theorem of calculus and its most
important corollaries, which are the main tools to formalize most of
real analysis.
** Indefinite Integrals
We define the indefinite integral of a function in a proper interval
in the obvious way; we just need to state a first lemma so that the
continuity proofs become unnecessary.
%\begin{convention}% Let [I : interval], [F : PartIR] be continuous in [I]
and [a] be a point in [I].
%\end{convention}%
*)
Variable I : interval.
Variable F : PartIR.
Hypothesis contF : Continuous I F.
Variable a : IR.
Hypothesis Ha : I a.
Lemma prim_lemma : forall x : IR, I x -> Continuous_I (Min_leEq_Max a x) F.
Proof.
intros.
elim contF; intros incI contI.
Included.
Qed.
Lemma Fprim_strext : forall x y Hx Hy,
Integral (prim_lemma x Hx) [#] Integral (prim_lemma y Hy) -> x [#] y.
Proof.
intros x y Hx Hy H.
elim (Integral_strext' _ _ _ _ _ _ _ _ _ H).
intro; elimtype False.
generalize a0; apply ap_irreflexive_unfolded.
auto.
Qed.
Definition Fprim : PartIR.
apply Build_PartFunct with (pfpfun := fun (x : IR) (Hx : I x) => Integral (prim_lemma x Hx)).
Proof.
apply iprop_wd.
exact Fprim_strext.
Defined.
End Indefinite_Integral.
Implicit Arguments Fprim [I F].
Notation "[-S-] F" := (Fprim F) (at level 20).
Section FTC.
(**
** The FTC
We can now prove our main theorem. We begin by remarking that the
primitive function is always continuous.
%\begin{convention}% Assume that [J : interval], [F : PartIR] is
continuous in [J] and [x0] is a point in [J]. Denote by [G] the
indefinite integral of [F] from [x0].
%\end{convention}%
*)
Variable J : interval.
Variable F : PartIR.
Hypothesis contF : Continuous J F.
Variable x0 : IR.
Hypothesis Hx0 : J x0.
(* begin hide *)
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
Lemma Continuous_prim : Continuous J G.
Proof.
split.
Included.
intros a b Hab H. split.
Included.
intros e H0.
simpl in |- *; simpl in H.
exists (e[/] _[//] max_one_ap_zero (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H))).
apply div_resp_pos.
apply pos_max_one.
assumption.
intros x y H1 H2 Hx Hy H3.
cut (included (Compact (Min_leEq_Max y x)) (Compact Hab)).
intro Hinc.
cut (Continuous_I (Min_leEq_Max y x) F). intro H4.
apply leEq_wdl with (AbsIR (Integral H4)).
eapply leEq_transitive.
apply Integral_leEq_norm.
apply leEq_transitive with (Max (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H)) [1][*]
AbsIR (x[-]y)).
apply mult_resp_leEq_rht.
apply leEq_transitive with (Norm_Funct (included_imp_Continuous _ _ contF _ _ _ H)).
apply leEq_Norm_Funct.
intros.
apply norm_bnd_AbsIR.
apply Hinc; auto.
apply lft_leEq_Max.
apply AbsIR_nonneg.
eapply shift_mult_leEq'.
apply pos_max_one.
apply H3.
apply AbsIR_wd.
rstepl (Integral (prim_lemma J F contF x0 Hx0 y Hy) [+]Integral H4[-]
Integral (prim_lemma J F contF x0 Hx0 y Hy)).
apply cg_minus_wd.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x y).
apply included_imp_Continuous with J; auto.
apply included3_interval; auto.
apply Integral_wd.
apply Feq_reflexive.
apply (included_trans _ (Compact (Min_leEq_Max x0 y)) J); Included.
apply included_imp_Continuous with J; auto.
Included.
Included.
Qed.
(**
The derivative of [G] is simply [F].
*)
Hypothesis pJ : proper J.
Theorem FTC1 : Derivative J pJ G F.
Proof.
split; Included.
split; Included.
intros; apply Derivative_I_char.
Included.
inversion_clear contF.
Included.
intros.
red in contF.
inversion_clear contF.
elim (contin_prop _ _ _ _ (X2 _ _ _ X) e X0); intros d H3 H4.
exists d.
assumption.
intros x y X3 X4 Hx Hy Hx' H.
simpl in |- *.
rename Hab into Hab'.
set (Hab := less_leEq _ _ _ Hab') in *.
cut (included (Compact (Min_leEq_Max x y)) (Compact Hab)).
intro Hinc.
cut (Continuous_I (Min_leEq_Max x y) F).
2: apply included_imp_Continuous with J; auto.
intro H8.
apply leEq_wdl with (AbsIR (Integral H8[-]
Integral (Continuous_I_const _ _ (Min_leEq_Max x y) (F x Hx')))).
apply leEq_wdl with (AbsIR (Integral (Continuous_I_minus _ _ _ _ _ H8
(Continuous_I_const _ _ _ (F x Hx'))))).
eapply leEq_transitive.
apply Integral_leEq_norm.
apply mult_resp_leEq_rht.
2: apply AbsIR_nonneg.
apply leEq_Norm_Funct.
intros z Hz Hz1.
simpl in |- *.
apply leEq_wdl with (AbsIR (F z (X1 z (X z (Hinc z Hz))) [-]F x Hx')).
2: apply AbsIR_wd; algebra.
apply H4; auto.
eapply leEq_transitive.
2: apply H.
eapply leEq_wdr.
2: apply eq_symmetric_unfolded; apply Abs_Max.
eapply leEq_wdr.
2: apply AbsIR_eq_x; apply shift_leEq_minus.
2: astepl (Min x y); apply Min_leEq_Max.
apply compact_elements with (Min_leEq_Max x y); auto.
apply compact_Min_lft.
apply AbsIR_wd; apply Integral_minus.
apply AbsIR_wd; apply cg_minus_wd.
rstepl (Integral (prim_lemma _ _ contF x0 Hx0 _ Hx) [+]Integral H8[-]
Integral (prim_lemma _ _ contF x0 Hx0 _ Hx)).
apply cg_minus_wd.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 y x).
apply included_imp_Continuous with J; auto.
apply included3_interval; auto.
apply Integral_wd. apply Feq_reflexive.
apply (included_trans _ (Compact (Min_leEq_Max x0 x)) J); try apply included_interval; auto.
apply Integral_const.
Included.
Included.
Qed.
(**
Any other function [G0] with derivative [F] must differ from [G] by a constant.
*)
Variable G0 : PartIR.
Hypothesis derG0 : Derivative J pJ G0 F.
Theorem FTC2 : {c : IR | Feq J (G{-}G0) [-C-]c}.
Proof.
apply FConst_prop with pJ.
apply Derivative_wdr with (F{-}F).
FEQ.
apply Derivative_minus; auto.
apply FTC1.
Qed.
(**
The following is another statement of the Fundamental Theorem of Calculus, also known as Barrow's rule.
*)
(* begin hide *)
Let G0_inc := Derivative_imp_inc _ _ _ _ derG0.
(* end hide *)
End FTC.
Theorem Barrow : forall J F (contF : Continuous J F)
(pJ:proper J) G0 (derG0 : Derivative J pJ G0 F)
a b (H : Continuous_I (Min_leEq_Max a b) F) Ha Hb,
let Ha' := Derivative_imp_inc _ _ _ _ derG0 a Ha in let Hb' := Derivative_imp_inc _ _ _ _ derG0 b Hb in Integral H [=] G0 b Hb'[-]G0 a Ha'.
Proof.
(* begin hide *)
intros J F contF pJ G0 derG0 a b H1 Ha Hb; intros.
pose (x0:=a).
pose (Hx0:=Ha).
set (G := ( [-S-]contF) x0 Hx0).
elim (@FTC2 J F contF x0 Hx0 pJ G0 derG0); intros c Hc.
elim Hc; intros H2 H.
elim H; clear H Hc; intros H3 H0.
(* Allow G0a to be G0 of a.
Allow G0b to be G0 of b. *)
set (G0a := G0 a Ha') in *.
set (G0b := G0 b Hb') in *.
rstepr (G0b[+]c[-] (G0a[+]c)).
(* Allow Ga to be G of a.
Allow Gb to be G of b.*)
set (Ga := G a Ha) in *.
set (Gb := G b Hb) in *.
apply eq_transitive_unfolded with (Gb[-]Ga).
unfold Ga, Gb, G in |- *; simpl in |- *.
cut (forall x y z : IR, z [=] x[+]y -> y [=] z[-]x). intro H5.
apply H5.
apply Integral_plus_Integral with (Min3_leEq_Max3 x0 b a).
apply included_imp_Continuous with J.
auto.
apply included3_interval; auto.
intros; apply eq_symmetric_unfolded.
rstepr (x[+]y[-]x); algebra.
cut (forall x y z : IR, x[-]y [=] z -> x [=] y[+]z); intros.
fold G in H0.
apply cg_minus_wd; unfold Ga, Gb, G0a, G0b in |- *; apply H; auto.
simpl in H0.
apply eq_transitive_unfolded with ((G{-}G0) b (Hb, Hb')).
2: apply H0 with (Hx := (Hb, Hb')).
simpl.
apply cg_minus_wd.
apply Integral_wd.
apply Feq_reflexive.
destruct H1 as [H1 _].
apply H1.
algebra.
auto.
auto.
change c with ([-C-]c a I).
apply eq_transitive_unfolded with ((G{-}G0) a (Ha, Ha')).
2: apply H0 with (Hx := (Ha, Ha')).
simpl.
apply cg_minus_wd.
apply Integral_wd.
apply Feq_reflexive.
destruct H1 as [H1 _].
intros y Hy.
apply H1.
apply (compact_wd _ _ (Min_leEq_Max a b) a).
apply compact_Min_lft.
unfold compact, x0 in Hy.
destruct Hy.
apply leEq_imp_eq.
astepl (Min a a). assumption.
apply Min_id.
stepr(Max a a). assumption.
apply Max_id.
algebra.
auto.
rstepl (y[+] (x[-]y)).
algebra.
Qed.
(* end hide *)
Hint Resolve Continuous_prim: continuous.
Hint Resolve FTC1: derivate.
Section Limit_of_Integral_Seq.
(**
** Corollaries
With these tools in our hand, we can prove several useful results.
%\begin{convention}% From this point onwards:
- [J : interval];
- [f : nat->PartIR] is a sequence of continuous functions (in [J]);
- [F : PartIR] is continuous in [J].
%\end{convention}%
In the first place, if a sequence of continuous functions converges
then the sequence of their primitives also converges, and the limit
commutes with the indefinite integral.
*)
Variable J : interval.
Variable f : nat -> PartIR.
Variable F : PartIR.
Hypothesis contf : forall n : nat, Continuous J (f n).
Hypothesis contF : Continuous J F.
Section Compact.
(**
We need to prove this result first for compact intervals.
%\begin{convention}% Assume that [a, b, x0 : IR] with [(f n)] and [F]
continuous in [[a,b]], $x0\in[a,b]$#x0∈[a,b]#; denote by
[(g n)] and [G] the indefinite integrals respectively of [(f n)] and
[F] with origin [x0].
%\end{convention}%
*)
Variables a b : IR.
Hypothesis Hab : a [<=] b.
Hypothesis contIf : forall n : nat, Continuous_I Hab (f n).
Hypothesis contIF : Continuous_I Hab F.
(* begin show *)
Hypothesis convF : conv_fun_seq' a b Hab f F contIf contIF.
(* end show *)
Variable x0 : IR.
Hypothesis Hx0 : J x0.
Hypothesis Hx0' : Compact Hab x0.
(* begin hide *)
Let g (n : nat) := ( [-S-]contf n) x0 Hx0.
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
(* begin show *)
Hypothesis contg : forall n : nat, Continuous_I Hab (g n).
Hypothesis contG : Continuous_I Hab G.
(* end show *)
Lemma fun_lim_seq_integral : conv_fun_seq' a b Hab g G contg contG.
Proof.
assert (H : conv_norm_fun_seq _ _ _ _ _ contIf contIF).
apply conv_fun_seq'_norm; assumption.
intros e H0.
elim (Archimedes (AbsIR (b[-]a) [/] _[//]pos_ap_zero _ _ H0)); intros k Hk.
elim (H k); intros N HN.
exists N; intros.
assert (H2 : included (Compact (Min_leEq_Max x0 x)) (Compact Hab)).
apply included2_compact; auto.
simpl in |- *.
apply leEq_wdl with (AbsIR (Integral (Continuous_I_minus _ _ _ _ _ (prim_lemma _ _ (contf n) x0 Hx0 _
(contin_imp_inc _ _ _ _ (contg n) _ Hx)) (prim_lemma _ _ contF x0 Hx0 _
(contin_imp_inc _ _ _ _ contG _ Hx))))).
2: apply AbsIR_wd; apply Integral_minus.
eapply leEq_transitive.
apply Integral_leEq_norm.
apply leEq_transitive with (one_div_succ k[*]AbsIR (b[-]a)).
apply mult_resp_leEq_both.
apply positive_norm.
apply AbsIR_nonneg.
eapply leEq_transitive.
2: apply (HN n H1).
apply leEq_Norm_Funct; intros.
apply norm_bnd_AbsIR.
apply H2; auto.
apply compact_elements with Hab; auto.
unfold one_div_succ, Snring in |- *.
rstepl (AbsIR (b[-]a) [/] _[//]nring_ap_zero _ _ (sym_not_eq (O_S k))).
apply shift_div_leEq.
apply pos_nring_S.
eapply shift_leEq_mult'.
assumption.
apply less_leEq; eapply leEq_less_trans.
apply Hk.
simpl in |- *.
apply less_plusOne.
Qed.
End Compact.
(**
And now we can generalize it step by step.
*)
Lemma limit_of_integral : conv_fun_seq'_IR J f F contf contF -> forall x y Hxy,
included (Compact Hxy) J -> forall Hf HF,
Cauchy_Lim_prop2 (fun n => integral x y Hxy (f n) (Hf n)) (integral x y Hxy F HF).
Proof.
intros H x y Hxy H0 Hf HF.
assert (Hx : J x). apply H0; apply compact_inc_lft.
assert (Hy : J y). apply H0; apply compact_inc_rht.
set (g := fun n : nat => ( [-S-]contf n) x Hx) in *.
set (G := ( [-S-]contF) x Hx) in *.
set (Hxg := fun n : nat => Hy) in *.
apply Lim_wd with (Part G y Hy).
simpl in |- *; apply Integral_integral.
apply Cauchy_Lim_prop2_wd with (fun n : nat => Part (g n) y (Hxg n)).
2: intro; simpl in |- *; apply Integral_integral.
cut (forall n : nat, Continuous_I Hxy (g n)). intro H1.
cut (Continuous_I Hxy G). intro H2.
apply fun_conv_imp_seq_conv with (contf := H1) (contF := H2).
set (H4 := fun n : nat => included_imp_Continuous _ _ (contf n) _ _ _ H0) in *.
set (H5 := included_imp_Continuous _ _ contF _ _ _ H0) in *.
unfold g, G in |- *.
apply fun_lim_seq_integral with H4 H5.
unfold H4, H5 in |- *.
apply H; auto.
apply compact_inc_lft.
apply compact_inc_rht.
unfold G in |- *; apply included_imp_Continuous with J; Contin.
intro; unfold g in |- *; apply included_imp_Continuous with J; Contin.
Qed.
Lemma limit_of_Integral : conv_fun_seq'_IR J f F contf contF -> forall x y,
included (Compact (Min_leEq_Max x y)) J -> forall Hxy Hf HF,
Cauchy_Lim_prop2 (fun n => Integral (a:=x) (b:=y) (Hab:=Hxy) (F:=f n) (Hf n))
(Integral (Hab:=Hxy) (F:=F) HF).
Proof.
intros convF x y H.
set (x0 := Min x y) in *.
intros.
assert (Hx0 : J x0).
apply H; apply compact_inc_lft.
assert (Hx0' : Compact Hxy x0).
apply compact_inc_lft.
set (g := fun n : nat => ( [-S-]contf n) x0 Hx0) in *.
set (G := ( [-S-]contF) x0 Hx0) in *.
unfold Integral in |- *; fold x0 in |- *.
apply (Cauchy_Lim_minus (fun n : nat => integral _ _ _ _ (Integral_inc2 _ _ _ _ (Hf n)))
(fun n : nat => integral _ _ _ _ (Integral_inc1 _ _ _ _ (Hf n)))); fold x0 in |- *.
apply limit_of_integral with (Hf := fun n : nat => Integral_inc2 _ _ Hxy _ (Hf n)); auto.
apply included_trans with (Compact (Min_leEq_Max x y)); Included.
apply included_compact.
apply compact_inc_lft.
apply compact_Min_rht.
apply limit_of_integral with (Hf := fun n : nat => Integral_inc1 _ _ Hxy _ (Hf n)); auto.
apply included_trans with (Compact (Min_leEq_Max x y)); auto.
apply included_compact.
apply compact_inc_lft.
apply compact_Min_lft.
Qed.
Section General.
(**
Finally, with [x0, g, G] as before,
*)
(* begin show *)
Hypothesis convF : conv_fun_seq'_IR J f F contf contF.
(* end show *)
Variable x0 : IR.
Hypothesis Hx0 : J x0.
(* begin hide *)
Let g (n : nat) := ( [-S-]contf n) x0 Hx0.
Let G := ( [-S-]contF) x0 Hx0.
(* end hide *)
Hypothesis contg : forall n : nat, Continuous J (g n).
Hypothesis contG : Continuous J G.
Lemma fun_lim_seq_integral_IR : conv_fun_seq'_IR J g G contg contG.
Proof.
red in |- *; intros.
unfold g, G in |- *.
cut (J a). intro H.
set (h := fun n : nat => [-C-] (Integral (prim_lemma _ _ (contf n) x0 Hx0 a H))) in *.
set (g' := fun n : nat => h n{+} ( [-S-]contf n) a H) in *.
set (G' := [-C-] (Integral (prim_lemma _ _ contF x0 Hx0 a H)) {+} ( [-S-]contF) a H) in *.
assert (H0 : forall n : nat, Continuous_I Hab (h n)).
intro; unfold h in |- *; Contin.
cut (forall n : nat, Continuous_I Hab (( [-S-]contf n) a H)). intro H1.
assert (H2 : forall n : nat, Continuous_I Hab (g' n)).
intro; unfold g' in |- *; Contin.
cut (Continuous_I Hab (( [-S-]contF) a H)). intro H3.
assert (H4 : Continuous_I Hab G').
unfold G' in |- *; Contin.
apply conv_fun_seq'_wdl with g' H2 (included_imp_Continuous _ _ contG _ _ _ Hinc).
intro; FEQ.
simpl in |- *.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x a).
apply included_imp_Continuous with J; Contin.
apply conv_fun_seq'_wdr with H2 G' H4.
FEQ.
simpl in |- *.
apply eq_symmetric_unfolded; apply Integral_plus_Integral with (Min3_leEq_Max3 x0 x a).
apply included_imp_Continuous with J; Contin.
unfold g', G' in |- *.
apply conv_fun_seq'_wdl with (f := g')
(contf := fun n : nat => Continuous_I_plus _ _ _ _ _ (H0 n) (H1 n)) (contF := H4).
unfold g' in H2.
intro; apply Feq_reflexive; Included.
unfold g', G' in |- *.
apply (fun_Lim_seq_plus' _ _ Hab h (fun n : nat => ( [-S-]contf n) a H) H0 H1 _ _
(Continuous_I_const _ _ _ (Integral (prim_lemma _ _ contF x0 Hx0 a H))) H3).
unfold h in |- *.
apply seq_conv_imp_fun_conv
with (x := fun n : nat => Integral (prim_lemma _ _ (contf n) x0 Hx0 a H)).
apply limit_of_Integral with (Hf := fun n : nat => prim_lemma _ _ (contf n) x0 Hx0 a H); auto.
Included.
apply fun_lim_seq_integral with (fun n : nat => included_imp_Continuous _ _ (contf n) _ _ _ Hinc)
(included_imp_Continuous _ _ contF _ _ _ Hinc).
apply convF; auto.
apply compact_inc_lft.
apply included_imp_Continuous with J; Contin.
intro; apply included_imp_Continuous with J; Contin.
apply Hinc; apply compact_inc_lft.
Qed.
End General.
End Limit_of_Integral_Seq.
Section Limit_of_Derivative_Seq.
(**
Similar results hold for the sequence of derivatives of a converging sequence; this time the proof is easier, as we can do it directly for any kind of interval.
%\begin{convention}% Let [g] be the sequence of derivatives of [f] and [G] be the derivative of [F].
%\end{convention}%
*)
Variable J : interval.
Hypothesis pJ : proper J.
Variables f g : nat -> PartIR.
Variables F G : PartIR.
Hypothesis contf : forall n : nat, Continuous J (f n).
Hypothesis contF : Continuous J F.
Hypothesis convF : conv_fun_seq'_IR J f F contf contF.
Hypothesis contg : forall n : nat, Continuous J (g n).
Hypothesis contG : Continuous J G.
Hypothesis convG : conv_fun_seq'_IR J g G contg contG.
Hypothesis derf : forall n : nat, Derivative J pJ (f n) (g n).
Lemma fun_lim_seq_derivative : Derivative J pJ F G.
Proof.
elim (nonvoid_point _ (proper_nonvoid _ pJ)); intros a Ha.
set (h := fun n : nat => ( [-S-]contg n) a Ha) in *.
set (H := ( [-S-]contG) a Ha) in *.
assert (H0 : Derivative J pJ H G). unfold H in |- *; apply FTC1.
assert (H1 : forall n : nat, Derivative J pJ (h n) (g n)). intro; unfold h in |- *; apply FTC1.
assert (H2 : conv_fun_seq'_IR J _ _ (fun n : nat => Derivative_imp_Continuous _ _ _ _ (H1 n))
(Derivative_imp_Continuous _ _ _ _ H0)).
unfold h, H in |- *. eapply fun_lim_seq_integral_IR with (contf := contg); auto.
cut {c : IR | Feq J (F{-}H) [-C-]c}.
intro H3.
elim H3; clear H3; intros c Hc.
apply Derivative_wdl with (H{+} [-C-]c).
apply Feq_transitive with (H{+} (F{-}H)).
apply Feq_plus.
apply Feq_reflexive; Included.
apply Feq_symmetric; assumption.
clear Hc H2 H1; clearbody H.
FEQ.
apply Derivative_wdr with (G{+} [-C-][0]).
FEQ.
apply Derivative_plus; auto.
apply Derivative_const.
assert (H3 : forall n : nat, {c : IR | Feq J (f n{-}h n) [-C-]c}).
intro; apply FConst_prop with pJ.
apply Derivative_wdr with (g n{-}g n). FEQ. apply Derivative_minus; auto.
assert (contw : forall n : nat, Continuous J (f n{-}h n)). unfold h in |- *; Contin.
assert (contW : Continuous J (F{-}H)). unfold H in |- *; Contin.
apply fun_const_Lim with (fun n : nat => f n{-}h n) contw contW.
auto.
eapply fun_Lim_seq_minus'_IR.
apply convF.
apply H2.
assumption.
Qed.
End Limit_of_Derivative_Seq.
Section Derivative_Series.
(**
As a very important case of this result, we get a rule for deriving series.
*)
Variable J : interval.
Hypothesis pJ : proper J.
Variables f g : nat -> PartIR.
(* begin show *)
Hypothesis convF : fun_series_convergent_IR J f.
Hypothesis convG : fun_series_convergent_IR J g.
(* end show *)
Hypothesis derF : forall n : nat, Derivative J pJ (f n) (g n).
Lemma Derivative_FSeries : Derivative J pJ (FSeries_Sum convF) (FSeries_Sum convG).
Proof.
apply fun_lim_seq_derivative with (f := fun n : nat => FSum0 n f)
(contf := Continuous_Sum0 _ _ (convergent_imp_Continuous _ _ convF))
(contF := Continuous_FSeries_Sum _ _ convF) (g := fun n : nat => FSum0 n g)
(contg := Continuous_Sum0 _ _ (convergent_imp_Continuous _ _ convG))
(contG := Continuous_FSeries_Sum _ _ convG).
3: Deriv.
apply FSeries_conv.
apply FSeries_conv.
Qed.
End Derivative_Series.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
`define SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V
/**
* clkdlyinv3sd1: Clock Delay Inverter 3-stage 0.15um length inner
* stage gate.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__clkdlyinv3sd1 (
Y ,
A ,
VPWR,
VGND
);
// Module ports
output Y ;
input A ;
input VPWR;
input VGND;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__CLKDLYINV3SD1_BEHAVIORAL_V |
// DESCRIPTION: Verilator: Simple test of CLkDATA
//
// Trigger the CLKDATA detection
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2015 by Jie Xu.
localparam ID_MSB = 1;
module t (/*AUTOARG*/
// Inputs
clk,
res,
res8,
res16
);
input clk;
output res;
output [7:0] res8;
output [15:0] res16;
wire [7:0] clkSet;
wire clk_1;
wire [2:0] clk_3;
wire [3:0] clk_4;
wire clk_final;
reg [7:0] count;
assign clkSet = {8{clk}};
assign clk_4 = clkSet[7:4];
assign clk_1 = clk_4[0];;
// arraysel
assign clk_3 = {3{clk_1}};
assign clk_final = clk_3[0];
// the following two assignment triggers the CLKDATA warning
// because on LHS there are a mix of signals both CLOCK and
// DATA
/* verilator lint_off CLKDATA */
assign res8 = {clk_3, 1'b0, clk_4};
assign res16 = {count, clk_3, clk_1, clk_4};
/* verilator lint_on CLKDATA */
initial
count = 0;
always @(posedge clk_final or negedge clk_final) begin
count = count + 1;
// the following assignment should trigger the CLKDATA warning
// because CLOCK signal is used as DATA in sequential block
/* verilator lint_off CLKDATA */
res <= clk_final;
/* verilator lint_on CLKDATA */
if ( count == 8'hf) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/*******************************************************************************
* Module: simul_axi_slow_ready
* Date:2014-03-24
* Author: Andrey Filippov
* Description: Simulation model for AXI: slow ready generation
*
* Copyright (c) 2014 Elphel, Inc..
* simul_axi_slow_ready.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_axi_slow_ready.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
`timescale 1ns/1ps
module simul_axi_slow_ready(
input clk,
input reset,
input [3:0] delay,
input valid,
output ready
);
reg [14:0] rdy_reg;
assign ready=(delay==0)?1'b1: ((((rdy_reg[14:0] >> (delay-1)) & 1) != 0)?1'b1:1'b0);
always @ (posedge clk or posedge reset) begin
if (reset) rdy_reg <=0;
else if (!valid || ready) rdy_reg <=0;
else rdy_reg <={rdy_reg[13:0],valid};
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_cq_req # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
output hcmd_cq_rd_en,
input [34:0] hcmd_cq_rd_data,
input hcmd_cq_empty_n,
output [6:0] hcmd_cid_rd_addr,
input [19:0] hcmd_cid_rd_data,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] sq_valid,
input [8:0] cq_rst_n,
input [8:0] cq_valid,
input [7:0] admin_cq_size,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_cq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
output [7:0] admin_cq_tail_ptr,
output [7:0] io_cq1_tail_ptr,
output [7:0] io_cq2_tail_ptr,
output [7:0] io_cq3_tail_ptr,
output [7:0] io_cq4_tail_ptr,
output [7:0] io_cq5_tail_ptr,
output [7:0] io_cq6_tail_ptr,
output [7:0] io_cq7_tail_ptr,
output [7:0] io_cq8_tail_ptr,
input [7:0] admin_sq_head_ptr,
input [7:0] io_sq1_head_ptr,
input [7:0] io_sq2_head_ptr,
input [7:0] io_sq3_head_ptr,
input [7:0] io_sq4_head_ptr,
input [7:0] io_sq5_head_ptr,
input [7:0] io_sq6_head_ptr,
input [7:0] io_sq7_head_ptr,
input [7:0] io_sq8_head_ptr,
output hcmd_slot_free_en,
output [6:0] hcmd_slot_invalid_tag,
output tx_cq_mwr_req,
output [7:0] tx_cq_mwr_tag,
output [11:2] tx_cq_mwr_len,
output [C_PCIE_ADDR_WIDTH-1:2] tx_cq_mwr_addr,
input tx_cq_mwr_req_ack,
input tx_cq_mwr_rd_en,
output [C_PCIE_DATA_WIDTH-1:0] tx_cq_mwr_rd_data,
input tx_cq_mwr_data_last
);
localparam LP_CPL_PCIE_TAG_PREFIX = 8'b00000000;
localparam LP_CPL_SIZE = 10'h04;
localparam S_IDLE = 11'b00000000001;
localparam S_CPL_STATUS0 = 11'b00000000010;
localparam S_CPL_STATUS1 = 11'b00000000100;
localparam S_CPL_STATUS2 = 11'b00000001000;
localparam S_CPL_STATUS3 = 11'b00000010000;
localparam S_HEAD_PTR = 11'b00000100000;
localparam S_PCIE_ADDR = 11'b00001000000;
localparam S_PCIE_MWR_REQ = 11'b00010000000;
localparam S_PCIE_MWR_DATA_LAST = 11'b00100000000;
localparam S_PCIE_MWR_DONE = 11'b01000000000;
localparam S_PCIE_SLOT_RELEASE = 11'b10000000000;
reg [10:0] cur_state;
reg [10:0] next_state;
reg r_sq_is_valid;
reg r_cq_is_valid;
reg [7:0] r_admin_cq_tail_ptr;
reg [7:0] r_io_cq1_tail_ptr;
reg [7:0] r_io_cq2_tail_ptr;
reg [7:0] r_io_cq3_tail_ptr;
reg [7:0] r_io_cq4_tail_ptr;
reg [7:0] r_io_cq5_tail_ptr;
reg [7:0] r_io_cq6_tail_ptr;
reg [7:0] r_io_cq7_tail_ptr;
reg [7:0] r_io_cq8_tail_ptr;
reg [8:0] r_cq_phase_tag;
reg [3:0] r_sq_cq_vec;
reg [8:0] r_cq_valid_entry;
reg [8:0] r_cq_update_entry;
reg r_hcmd_cq_rd_en;
wire [6:0] w_hcmd_slot_tag;
reg r_hcmd_slot_free_en;
reg [1:0] r_cql_type;
reg [19:0] r_cql_info;
reg [3:0] r_cpl_sq_qid;
reg [15:0] r_cpl_cid;
reg [14:0] r_cpl_status;
reg [31:0] r_cpl_specific;
reg [7:0] r_cq_tail_ptr;
reg [7:0] r_sq_head_ptr;
reg r_phase_tag;
reg r_tx_cq_mwr_req;
reg [C_PCIE_ADDR_WIDTH-1:2] r_tx_cq_mwr_addr;
wire [31:0] w_cpl_dw0;
wire [31:0] w_cpl_dw1;
wire [31:0] w_cpl_dw2;
wire [31:0] w_cpl_dw3;
wire [8:0] w_cq_rst_n;
assign admin_cq_tail_ptr = r_admin_cq_tail_ptr;
assign io_cq1_tail_ptr = r_io_cq1_tail_ptr;
assign io_cq2_tail_ptr = r_io_cq2_tail_ptr;
assign io_cq3_tail_ptr = r_io_cq3_tail_ptr;
assign io_cq4_tail_ptr = r_io_cq4_tail_ptr;
assign io_cq5_tail_ptr = r_io_cq5_tail_ptr;
assign io_cq6_tail_ptr = r_io_cq6_tail_ptr;
assign io_cq7_tail_ptr = r_io_cq7_tail_ptr;
assign io_cq8_tail_ptr = r_io_cq8_tail_ptr;
assign hcmd_cq_rd_en = r_hcmd_cq_rd_en;
assign hcmd_cid_rd_addr = w_hcmd_slot_tag;
assign hcmd_slot_free_en = r_hcmd_slot_free_en;
assign hcmd_slot_invalid_tag = w_hcmd_slot_tag;
assign w_cpl_dw0 = r_cpl_specific;
assign w_cpl_dw1 = 0;
assign w_cpl_dw2 = {12'b0, r_cpl_sq_qid, 8'b0, r_sq_head_ptr};
assign w_cpl_dw3 = {r_cpl_status, r_phase_tag, r_cpl_cid};
assign tx_cq_mwr_req = r_tx_cq_mwr_req;
assign tx_cq_mwr_tag = LP_CPL_PCIE_TAG_PREFIX;
assign tx_cq_mwr_len = LP_CPL_SIZE;
assign tx_cq_mwr_addr = r_tx_cq_mwr_addr;
assign tx_cq_mwr_rd_data = {w_cpl_dw3, w_cpl_dw2, w_cpl_dw1, w_cpl_dw0};
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if(hcmd_cq_empty_n == 1)
next_state <= S_CPL_STATUS0;
else
next_state <= S_IDLE;
end
S_CPL_STATUS0: begin
next_state <= S_CPL_STATUS1;
end
S_CPL_STATUS1: begin
if(r_cql_type[0] == 1)
next_state <= S_CPL_STATUS2;
else if(r_cql_type[1] == 1)
next_state <= S_PCIE_SLOT_RELEASE;
else
next_state <= S_CPL_STATUS3;
end
S_CPL_STATUS2: begin
next_state <= S_CPL_STATUS3;
end
S_CPL_STATUS3: begin
next_state <= S_HEAD_PTR;
end
S_HEAD_PTR: begin
if(r_sq_is_valid == 1)
next_state <= S_PCIE_ADDR;
else
next_state <= S_IDLE;
end
S_PCIE_ADDR: begin
if(r_cq_is_valid == 1)
next_state <= S_PCIE_MWR_REQ;
else
next_state <= S_IDLE;
end
S_PCIE_MWR_REQ: begin
next_state <= S_PCIE_MWR_DATA_LAST;
end
S_PCIE_MWR_DATA_LAST: begin
if(tx_cq_mwr_data_last == 1)
next_state <= S_PCIE_MWR_DONE;
else
next_state <= S_PCIE_MWR_DATA_LAST;
end
S_PCIE_MWR_DONE: begin
if(r_cql_type[0] == 1)
next_state <= S_PCIE_SLOT_RELEASE;
else
next_state <= S_IDLE;
end
S_PCIE_SLOT_RELEASE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
assign w_hcmd_slot_tag = r_cql_info[6:0];
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_IDLE: begin
end
S_CPL_STATUS0: begin
r_cql_type <= hcmd_cq_rd_data[1:0];
r_cql_info <= hcmd_cq_rd_data[21:2];
r_cpl_status[12:0] <= hcmd_cq_rd_data[34:22];
end
S_CPL_STATUS1: begin
r_cpl_cid <= r_cql_info[15:0];
r_cpl_sq_qid <= r_cql_info[19:16];
r_cpl_status[14:13] <= hcmd_cq_rd_data[1:0];
r_cpl_specific[31:0] <= hcmd_cq_rd_data[33:2];
end
S_CPL_STATUS2: begin
r_cpl_cid <= hcmd_cid_rd_data[15:0];
r_cpl_sq_qid <= hcmd_cid_rd_data[19:16];
end
S_CPL_STATUS3: begin
case(r_cpl_sq_qid) // synthesis parallel_case full_case
4'h0: begin
r_sq_is_valid <= sq_valid[0];
r_sq_cq_vec <= 4'h0;
r_sq_head_ptr <= admin_sq_head_ptr;
end
4'h1: begin
r_sq_is_valid <= sq_valid[1];
r_sq_cq_vec <= io_sq1_cq_vec;
r_sq_head_ptr <= io_sq1_head_ptr;
end
4'h2: begin
r_sq_is_valid <= sq_valid[2];
r_sq_cq_vec <= io_sq2_cq_vec;
r_sq_head_ptr <= io_sq2_head_ptr;
end
4'h3: begin
r_sq_is_valid <= sq_valid[3];
r_sq_cq_vec <= io_sq3_cq_vec;
r_sq_head_ptr <= io_sq3_head_ptr;
end
4'h4: begin
r_sq_is_valid <= sq_valid[4];
r_sq_cq_vec <= io_sq4_cq_vec;
r_sq_head_ptr <= io_sq4_head_ptr;
end
4'h5: begin
r_sq_is_valid <= sq_valid[5];
r_sq_cq_vec <= io_sq5_cq_vec;
r_sq_head_ptr <= io_sq5_head_ptr;
end
4'h6: begin
r_sq_is_valid <= sq_valid[6];
r_sq_cq_vec <= io_sq6_cq_vec;
r_sq_head_ptr <= io_sq6_head_ptr;
end
4'h7: begin
r_sq_is_valid <= sq_valid[7];
r_sq_cq_vec <= io_sq7_cq_vec;
r_sq_head_ptr <= io_sq7_head_ptr;
end
4'h8: begin
r_sq_is_valid <= sq_valid[8];
r_sq_cq_vec <= io_sq8_cq_vec;
r_sq_head_ptr <= io_sq8_head_ptr;
end
endcase
end
S_HEAD_PTR: begin
case(r_sq_cq_vec) // synthesis parallel_case full_case
4'h0: begin
r_cq_is_valid <= cq_valid[0];
r_tx_cq_mwr_addr <= admin_cq_bs_addr;
r_cq_tail_ptr <= r_admin_cq_tail_ptr;
r_phase_tag <= r_cq_phase_tag[0];
r_cq_valid_entry <= 9'b000000001;
end
4'h1: begin
r_cq_is_valid <= cq_valid[1];
r_tx_cq_mwr_addr <= io_cq1_bs_addr;
r_cq_tail_ptr <= r_io_cq1_tail_ptr;
r_phase_tag <= r_cq_phase_tag[1];
r_cq_valid_entry <= 9'b000000010;
end
4'h2: begin
r_cq_is_valid <= cq_valid[2];
r_tx_cq_mwr_addr <= io_cq2_bs_addr;
r_cq_tail_ptr <= r_io_cq2_tail_ptr;
r_phase_tag <= r_cq_phase_tag[2];
r_sq_head_ptr <= io_sq2_head_ptr;
r_cq_valid_entry <= 9'b000000100;
end
4'h3: begin
r_cq_is_valid <= cq_valid[3];
r_tx_cq_mwr_addr <= io_cq3_bs_addr;
r_cq_tail_ptr <= r_io_cq3_tail_ptr;
r_phase_tag <= r_cq_phase_tag[3];
r_sq_head_ptr <= io_sq3_head_ptr;
r_cq_valid_entry <= 9'b000001000;
end
4'h4: begin
r_cq_is_valid <= cq_valid[4];
r_tx_cq_mwr_addr <= io_cq4_bs_addr;
r_cq_tail_ptr <= r_io_cq4_tail_ptr;
r_phase_tag <= r_cq_phase_tag[4];
r_sq_head_ptr <= io_sq4_head_ptr;
r_cq_valid_entry <= 9'b000010000;
end
4'h5: begin
r_cq_is_valid <= cq_valid[5];
r_tx_cq_mwr_addr <= io_cq5_bs_addr;
r_cq_tail_ptr <= r_io_cq5_tail_ptr;
r_phase_tag <= r_cq_phase_tag[5];
r_sq_head_ptr <= io_sq5_head_ptr;
r_cq_valid_entry <= 9'b000100000;
end
4'h6: begin
r_cq_is_valid <= cq_valid[6];
r_tx_cq_mwr_addr <= io_cq6_bs_addr;
r_cq_tail_ptr <= r_io_cq6_tail_ptr;
r_phase_tag <= r_cq_phase_tag[6];
r_sq_head_ptr <= io_sq6_head_ptr;
r_cq_valid_entry <= 9'b001000000;
end
4'h7: begin
r_cq_is_valid <= cq_valid[7];
r_tx_cq_mwr_addr <= io_cq7_bs_addr;
r_cq_tail_ptr <= r_io_cq7_tail_ptr;
r_phase_tag <= r_cq_phase_tag[7];
r_sq_head_ptr <= io_sq7_head_ptr;
r_cq_valid_entry <= 9'b010000000;
end
4'h8: begin
r_cq_is_valid <= cq_valid[8];
r_tx_cq_mwr_addr <= io_cq8_bs_addr;
r_cq_tail_ptr <= r_io_cq8_tail_ptr;
r_phase_tag <= r_cq_phase_tag[8];
r_sq_head_ptr <= io_sq8_head_ptr;
r_cq_valid_entry <= 9'b100000000;
end
endcase
end
S_PCIE_ADDR: begin
r_tx_cq_mwr_addr <= r_tx_cq_mwr_addr + {r_cq_tail_ptr, 2'b0};
r_cq_tail_ptr <= r_cq_tail_ptr + 1;
end
S_PCIE_MWR_REQ: begin
end
S_PCIE_MWR_DATA_LAST: begin
end
S_PCIE_MWR_DONE: begin
end
S_PCIE_SLOT_RELEASE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS0: begin
r_hcmd_cq_rd_en <= 1;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS1: begin
r_hcmd_cq_rd_en <= 1;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS2: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_CPL_STATUS3: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_HEAD_PTR: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_ADDR: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_REQ: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 1;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_DATA_LAST: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_MWR_DONE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= r_cq_valid_entry;
r_hcmd_slot_free_en <= 0;
end
S_PCIE_SLOT_RELEASE: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 1;
end
default: begin
r_hcmd_cq_rd_en <= 0;
r_tx_cq_mwr_req <= 0;
r_cq_update_entry <= 0;
r_hcmd_slot_free_en <= 0;
end
endcase
end
assign w_cq_rst_n[0] = pcie_user_rst_n & cq_rst_n[0];
assign w_cq_rst_n[1] = pcie_user_rst_n & cq_rst_n[1];
assign w_cq_rst_n[2] = pcie_user_rst_n & cq_rst_n[2];
assign w_cq_rst_n[3] = pcie_user_rst_n & cq_rst_n[3];
assign w_cq_rst_n[4] = pcie_user_rst_n & cq_rst_n[4];
assign w_cq_rst_n[5] = pcie_user_rst_n & cq_rst_n[5];
assign w_cq_rst_n[6] = pcie_user_rst_n & cq_rst_n[6];
assign w_cq_rst_n[7] = pcie_user_rst_n & cq_rst_n[7];
assign w_cq_rst_n[8] = pcie_user_rst_n & cq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[0])
begin
if(w_cq_rst_n[0] == 0) begin
r_admin_cq_tail_ptr <= 0;
r_cq_phase_tag[0] <= 1;
end
else begin
if(r_cq_update_entry[0] == 1) begin
if(r_admin_cq_tail_ptr == admin_cq_size) begin
r_admin_cq_tail_ptr <= 0;
r_cq_phase_tag[0] <= ~r_cq_phase_tag[0];
end
else begin
r_admin_cq_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[1])
begin
if(w_cq_rst_n[1] == 0) begin
r_io_cq1_tail_ptr <= 0;
r_cq_phase_tag[1] <= 1;
end
else begin
if(r_cq_update_entry[1] == 1) begin
if(r_io_cq1_tail_ptr == io_cq1_size) begin
r_io_cq1_tail_ptr <= 0;
r_cq_phase_tag[1] <= ~r_cq_phase_tag[1];
end
else begin
r_io_cq1_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[2])
begin
if(w_cq_rst_n[2] == 0) begin
r_io_cq2_tail_ptr <= 0;
r_cq_phase_tag[2] <= 1;
end
else begin
if(r_cq_update_entry[2] == 1) begin
if(r_io_cq2_tail_ptr == io_cq2_size) begin
r_io_cq2_tail_ptr <= 0;
r_cq_phase_tag[2] <= ~r_cq_phase_tag[2];
end
else begin
r_io_cq2_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[3])
begin
if(w_cq_rst_n[3] == 0) begin
r_io_cq3_tail_ptr <= 0;
r_cq_phase_tag[3] <= 1;
end
else begin
if(r_cq_update_entry[3] == 1) begin
if(r_io_cq3_tail_ptr == io_cq3_size) begin
r_io_cq3_tail_ptr <= 0;
r_cq_phase_tag[3] <= ~r_cq_phase_tag[3];
end
else begin
r_io_cq3_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[4])
begin
if(w_cq_rst_n[4] == 0) begin
r_io_cq4_tail_ptr <= 0;
r_cq_phase_tag[4] <= 1;
end
else begin
if(r_cq_update_entry[4] == 1) begin
if(r_io_cq4_tail_ptr == io_cq4_size) begin
r_io_cq4_tail_ptr <= 0;
r_cq_phase_tag[4] <= ~r_cq_phase_tag[4];
end
else begin
r_io_cq4_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[5])
begin
if(w_cq_rst_n[5] == 0) begin
r_io_cq5_tail_ptr <= 0;
r_cq_phase_tag[5] <= 1;
end
else begin
if(r_cq_update_entry[5] == 1) begin
if(r_io_cq5_tail_ptr == io_cq5_size) begin
r_io_cq5_tail_ptr <= 0;
r_cq_phase_tag[5] <= ~r_cq_phase_tag[5];
end
else begin
r_io_cq5_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[6])
begin
if(w_cq_rst_n[6] == 0) begin
r_io_cq6_tail_ptr <= 0;
r_cq_phase_tag[6] <= 1;
end
else begin
if(r_cq_update_entry[6] == 1) begin
if(r_io_cq6_tail_ptr == io_cq6_size) begin
r_io_cq6_tail_ptr <= 0;
r_cq_phase_tag[6] <= ~r_cq_phase_tag[6];
end
else begin
r_io_cq6_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[7])
begin
if(w_cq_rst_n[7] == 0) begin
r_io_cq7_tail_ptr <= 0;
r_cq_phase_tag[7] <= 1;
end
else begin
if(r_cq_update_entry[7] == 1) begin
if(r_io_cq7_tail_ptr == io_cq7_size) begin
r_io_cq7_tail_ptr <= 0;
r_cq_phase_tag[7] <= ~r_cq_phase_tag[7];
end
else begin
r_io_cq7_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_cq_rst_n[8])
begin
if(w_cq_rst_n[8] == 0) begin
r_io_cq8_tail_ptr <= 0;
r_cq_phase_tag[8] <= 1;
end
else begin
if(r_cq_update_entry[8] == 1) begin
if(r_io_cq8_tail_ptr == io_cq8_size) begin
r_io_cq8_tail_ptr <= 0;
r_cq_phase_tag[8] <= ~r_cq_phase_tag[8];
end
else begin
r_io_cq8_tail_ptr <= r_cq_tail_ptr;
end
end
end
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2013.4
// Copyright (C) 2013 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5(clk, reset, ce, a, b, s);
// ---- input/output ports list here ----
input clk;
input reset;
input ce;
input [17 - 1 : 0] a;
input [17 - 1 : 0] b;
output [17 - 1 : 0] s;
// ---- register and wire type variables list here ----
// wire for the primary inputs
wire [17 - 1 : 0] a_reg;
wire [17 - 1 : 0] b_reg;
// wires for each small adder
wire [5 - 1 : 0] a0_cb;
wire [5 - 1 : 0] b0_cb;
wire [10 - 1 : 5] a1_cb;
wire [10 - 1 : 5] b1_cb;
wire [15 - 1 : 10] a2_cb;
wire [15 - 1 : 10] b2_cb;
wire [17 - 1 : 15] a3_cb;
wire [17 - 1 : 15] b3_cb;
// registers for input register array
reg [5 - 1 : 0] a1_cb_regi1[1 - 1 : 0];
reg [5 - 1 : 0] b1_cb_regi1[1 - 1 : 0];
reg [5 - 1 : 0] a2_cb_regi2[2 - 1 : 0];
reg [5 - 1 : 0] b2_cb_regi2[2 - 1 : 0];
reg [2 - 1 : 0] a3_cb_regi3[3 - 1 : 0];
reg [2 - 1 : 0] b3_cb_regi3[3 - 1 : 0];
// wires for each full adder sum
wire [17 - 1 : 0] fas;
// wires and register for carry out bit
wire faccout_ini;
wire faccout0_co0;
wire faccout1_co1;
wire faccout2_co2;
wire faccout3_co3;
reg faccout0_co0_reg;
reg faccout1_co1_reg;
reg faccout2_co2_reg;
// registers for output register array
reg [5 - 1 : 0] s0_ca_rego0[2 - 0 : 0];
reg [5 - 1 : 0] s1_ca_rego1[2 - 1 : 0];
reg [5 - 1 : 0] s2_ca_rego2[2 - 2 : 0];
// wire for the temporary output
wire [17 - 1 : 0] s_tmp;
// ---- RTL code for assignment statements/always blocks/module instantiations here ----
assign a_reg = a;
assign b_reg = b;
// small adder input assigments
assign a0_cb = a_reg[5 - 1 : 0];
assign b0_cb = b_reg[5 - 1 : 0];
assign a1_cb = a_reg[10 - 1 : 5];
assign b1_cb = b_reg[10 - 1 : 5];
assign a2_cb = a_reg[15 - 1 : 10];
assign b2_cb = b_reg[15 - 1 : 10];
assign a3_cb = a_reg[17 - 1 : 15];
assign b3_cb = b_reg[17 - 1 : 15];
// input register array
always @ (posedge clk) begin
if (ce) begin
a1_cb_regi1 [0] <= a1_cb;
b1_cb_regi1 [0] <= b1_cb;
a2_cb_regi2 [0] <= a2_cb;
b2_cb_regi2 [0] <= b2_cb;
a3_cb_regi3 [0] <= a3_cb;
b3_cb_regi3 [0] <= b3_cb;
a2_cb_regi2 [1] <= a2_cb_regi2 [0];
b2_cb_regi2 [1] <= b2_cb_regi2 [0];
a3_cb_regi3 [1] <= a3_cb_regi3 [0];
b3_cb_regi3 [1] <= b3_cb_regi3 [0];
a3_cb_regi3 [2] <= a3_cb_regi3 [1];
b3_cb_regi3 [2] <= b3_cb_regi3 [1];
end
end
// carry out bit processing
always @ (posedge clk) begin
if (ce) begin
faccout0_co0_reg <= faccout0_co0;
faccout1_co1_reg <= faccout1_co1;
faccout2_co2_reg <= faccout2_co2;
end
end
// small adder generation
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u0 (
.faa ( a0_cb ),
.fab ( b0_cb ),
.facin ( faccout_ini ),
.fas ( fas[4:0] ),
.facout ( faccout0_co0 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u1 (
.faa ( a1_cb_regi1[0] ),
.fab ( b1_cb_regi1[0] ),
.facin ( faccout0_co0_reg),
.fas ( fas[9:5] ),
.facout ( faccout1_co1 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder u2 (
.faa ( a2_cb_regi2[1] ),
.fab ( b2_cb_regi2[1] ),
.facin ( faccout1_co1_reg),
.fas ( fas[14:10] ),
.facout ( faccout2_co2 )
);
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f u3 (
.faa ( a3_cb_regi3[2] ),
.fab ( b3_cb_regi3[2] ),
.facin ( faccout2_co2_reg ),
.fas ( fas[16 :15] ),
.facout ( faccout3_co3 )
);
assign faccout_ini = 1'b0;
// output register array
always @ (posedge clk) begin
if (ce) begin
s0_ca_rego0 [0] <= fas[5-1 : 0];
s1_ca_rego1 [0] <= fas[10-1 : 5];
s2_ca_rego2 [0] <= fas[15-1 : 10];
s0_ca_rego0 [1] <= s0_ca_rego0 [0];
s0_ca_rego0 [2] <= s0_ca_rego0 [1];
s1_ca_rego1 [1] <= s1_ca_rego1 [0];
end
end
// get the s_tmp, assign it to the primary output
assign s_tmp[5-1 : 0] = s0_ca_rego0[2];
assign s_tmp[10-1 : 5] = s1_ca_rego1[1];
assign s_tmp[15-1 : 10] = s2_ca_rego2[0];
assign s_tmp[17 - 1 : 15] = fas[16 :15];
assign s = s_tmp;
endmodule
// short adder
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder
#(parameter
N = 5
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
// the final stage short adder
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_fadder_f
#(parameter
N = 2
)(
input [N-1 : 0] faa,
input [N-1 : 0] fab,
input wire facin,
output [N-1 : 0] fas,
output wire facout
);
assign {facout, fas} = faa + fab + facin;
endmodule
`timescale 1 ns / 1 ps
module nfa_accept_samples_generic_hw_add_17ns_17s_17_4(
clk,
reset,
ce,
din0,
din1,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input clk;
input reset;
input ce;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
output[dout_WIDTH - 1:0] dout;
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5 nfa_accept_samples_generic_hw_add_17ns_17s_17_4_AddSubnS_5_U(
.clk( clk ),
.reset( reset ),
.ce( ce ),
.a( din0 ),
.b( din1 ),
.s( dout ));
endmodule
|
// wasca_mm_interconnect_0.v
// This file was auto-generated from altera_mm_interconnect_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 15.1 193
`timescale 1 ps / 1 ps
module wasca_mm_interconnect_0 (
input wire altpll_0_c0_clk, // altpll_0_c0.clk
input wire clk_0_clk_clk, // clk_0_clk.clk
input wire abus_slave_0_reset_reset_bridge_in_reset_reset, // abus_slave_0_reset_reset_bridge_in_reset.reset
input wire altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset, // altpll_0_inclk_interface_reset_reset_bridge_in_reset.reset
input wire [27:0] abus_slave_0_avalon_master_address, // abus_slave_0_avalon_master.address
output wire abus_slave_0_avalon_master_waitrequest, // .waitrequest
input wire [0:0] abus_slave_0_avalon_master_burstcount, // .burstcount
input wire [1:0] abus_slave_0_avalon_master_byteenable, // .byteenable
input wire abus_slave_0_avalon_master_read, // .read
output wire [15:0] abus_slave_0_avalon_master_readdata, // .readdata
output wire abus_slave_0_avalon_master_readdatavalid, // .readdatavalid
input wire abus_slave_0_avalon_master_write, // .write
input wire [15:0] abus_slave_0_avalon_master_writedata, // .writedata
input wire [27:0] nios2_gen2_0_data_master_address, // nios2_gen2_0_data_master.address
output wire nios2_gen2_0_data_master_waitrequest, // .waitrequest
input wire [3:0] nios2_gen2_0_data_master_byteenable, // .byteenable
input wire nios2_gen2_0_data_master_read, // .read
output wire [31:0] nios2_gen2_0_data_master_readdata, // .readdata
input wire nios2_gen2_0_data_master_write, // .write
input wire [31:0] nios2_gen2_0_data_master_writedata, // .writedata
input wire nios2_gen2_0_data_master_debugaccess, // .debugaccess
input wire [27:0] nios2_gen2_0_instruction_master_address, // nios2_gen2_0_instruction_master.address
output wire nios2_gen2_0_instruction_master_waitrequest, // .waitrequest
input wire nios2_gen2_0_instruction_master_read, // .read
output wire [31:0] nios2_gen2_0_instruction_master_readdata, // .readdata
output wire [7:0] abus_demux_0_avalon_nios_address, // abus_demux_0_avalon_nios.address
output wire abus_demux_0_avalon_nios_write, // .write
output wire abus_demux_0_avalon_nios_read, // .read
input wire [31:0] abus_demux_0_avalon_nios_readdata, // .readdata
output wire [31:0] abus_demux_0_avalon_nios_writedata, // .writedata
output wire [0:0] abus_demux_0_avalon_nios_burstcount, // .burstcount
input wire abus_demux_0_avalon_nios_readdatavalid, // .readdatavalid
input wire abus_demux_0_avalon_nios_waitrequest, // .waitrequest
output wire [7:0] abus_slave_0_avalon_nios_address, // abus_slave_0_avalon_nios.address
output wire abus_slave_0_avalon_nios_write, // .write
output wire abus_slave_0_avalon_nios_read, // .read
input wire [31:0] abus_slave_0_avalon_nios_readdata, // .readdata
output wire [31:0] abus_slave_0_avalon_nios_writedata, // .writedata
output wire [0:0] abus_slave_0_avalon_nios_burstcount, // .burstcount
input wire abus_slave_0_avalon_nios_readdatavalid, // .readdatavalid
input wire abus_slave_0_avalon_nios_waitrequest, // .waitrequest
output wire [1:0] altpll_0_pll_slave_address, // altpll_0_pll_slave.address
output wire altpll_0_pll_slave_write, // .write
output wire altpll_0_pll_slave_read, // .read
input wire [31:0] altpll_0_pll_slave_readdata, // .readdata
output wire [31:0] altpll_0_pll_slave_writedata, // .writedata
output wire [24:0] external_sdram_controller_s1_address, // external_sdram_controller_s1.address
output wire external_sdram_controller_s1_write, // .write
output wire external_sdram_controller_s1_read, // .read
input wire [15:0] external_sdram_controller_s1_readdata, // .readdata
output wire [15:0] external_sdram_controller_s1_writedata, // .writedata
output wire [1:0] external_sdram_controller_s1_byteenable, // .byteenable
input wire external_sdram_controller_s1_readdatavalid, // .readdatavalid
input wire external_sdram_controller_s1_waitrequest, // .waitrequest
output wire external_sdram_controller_s1_chipselect, // .chipselect
output wire [1:0] extra_leds_s1_address, // extra_leds_s1.address
output wire extra_leds_s1_write, // .write
input wire [31:0] extra_leds_s1_readdata, // .readdata
output wire [31:0] extra_leds_s1_writedata, // .writedata
output wire extra_leds_s1_chipselect, // .chipselect
output wire [1:0] hex0_s1_address, // hex0_s1.address
output wire hex0_s1_write, // .write
input wire [31:0] hex0_s1_readdata, // .readdata
output wire [31:0] hex0_s1_writedata, // .writedata
output wire hex0_s1_chipselect, // .chipselect
output wire [1:0] hex1_s1_address, // hex1_s1.address
output wire hex1_s1_write, // .write
input wire [31:0] hex1_s1_readdata, // .readdata
output wire [31:0] hex1_s1_writedata, // .writedata
output wire hex1_s1_chipselect, // .chipselect
output wire [1:0] hex2_s1_address, // hex2_s1.address
output wire hex2_s1_write, // .write
input wire [31:0] hex2_s1_readdata, // .readdata
output wire [31:0] hex2_s1_writedata, // .writedata
output wire hex2_s1_chipselect, // .chipselect
output wire [1:0] hex3_s1_address, // hex3_s1.address
output wire hex3_s1_write, // .write
input wire [31:0] hex3_s1_readdata, // .readdata
output wire [31:0] hex3_s1_writedata, // .writedata
output wire hex3_s1_chipselect, // .chipselect
output wire [1:0] hex4_s1_address, // hex4_s1.address
output wire hex4_s1_write, // .write
input wire [31:0] hex4_s1_readdata, // .readdata
output wire [31:0] hex4_s1_writedata, // .writedata
output wire hex4_s1_chipselect, // .chipselect
output wire [1:0] hex5_s1_address, // hex5_s1.address
output wire hex5_s1_write, // .write
input wire [31:0] hex5_s1_readdata, // .readdata
output wire [31:0] hex5_s1_writedata, // .writedata
output wire hex5_s1_chipselect, // .chipselect
output wire [1:0] hexdot_s1_address, // hexdot_s1.address
output wire hexdot_s1_write, // .write
input wire [31:0] hexdot_s1_readdata, // .readdata
output wire [31:0] hexdot_s1_writedata, // .writedata
output wire hexdot_s1_chipselect, // .chipselect
output wire [1:0] leds_s1_address, // leds_s1.address
output wire leds_s1_write, // .write
input wire [31:0] leds_s1_readdata, // .readdata
output wire [31:0] leds_s1_writedata, // .writedata
output wire leds_s1_chipselect, // .chipselect
output wire [8:0] nios2_gen2_0_debug_mem_slave_address, // nios2_gen2_0_debug_mem_slave.address
output wire nios2_gen2_0_debug_mem_slave_write, // .write
output wire nios2_gen2_0_debug_mem_slave_read, // .read
input wire [31:0] nios2_gen2_0_debug_mem_slave_readdata, // .readdata
output wire [31:0] nios2_gen2_0_debug_mem_slave_writedata, // .writedata
output wire [3:0] nios2_gen2_0_debug_mem_slave_byteenable, // .byteenable
input wire nios2_gen2_0_debug_mem_slave_waitrequest, // .waitrequest
output wire nios2_gen2_0_debug_mem_slave_debugaccess, // .debugaccess
output wire [0:0] onchip_flash_0_csr_address, // onchip_flash_0_csr.address
output wire onchip_flash_0_csr_write, // .write
output wire onchip_flash_0_csr_read, // .read
input wire [31:0] onchip_flash_0_csr_readdata, // .readdata
output wire [31:0] onchip_flash_0_csr_writedata, // .writedata
output wire [18:0] onchip_flash_0_data_address, // onchip_flash_0_data.address
output wire onchip_flash_0_data_write, // .write
output wire onchip_flash_0_data_read, // .read
input wire [31:0] onchip_flash_0_data_readdata, // .readdata
output wire [31:0] onchip_flash_0_data_writedata, // .writedata
output wire [3:0] onchip_flash_0_data_burstcount, // .burstcount
input wire onchip_flash_0_data_readdatavalid, // .readdatavalid
input wire onchip_flash_0_data_waitrequest, // .waitrequest
output wire [12:0] onchip_memory2_0_s1_address, // onchip_memory2_0_s1.address
output wire onchip_memory2_0_s1_write, // .write
input wire [31:0] onchip_memory2_0_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_0_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_0_s1_byteenable, // .byteenable
output wire onchip_memory2_0_s1_chipselect, // .chipselect
output wire onchip_memory2_0_s1_clken, // .clken
output wire [9:0] onchip_memory2_1_s1_address, // onchip_memory2_1_s1.address
output wire onchip_memory2_1_s1_write, // .write
input wire [31:0] onchip_memory2_1_s1_readdata, // .readdata
output wire [31:0] onchip_memory2_1_s1_writedata, // .writedata
output wire [3:0] onchip_memory2_1_s1_byteenable, // .byteenable
output wire onchip_memory2_1_s1_chipselect, // .chipselect
output wire onchip_memory2_1_s1_clken, // .clken
output wire [2:0] performance_counter_0_control_slave_address, // performance_counter_0_control_slave.address
output wire performance_counter_0_control_slave_write, // .write
input wire [31:0] performance_counter_0_control_slave_readdata, // .readdata
output wire [31:0] performance_counter_0_control_slave_writedata, // .writedata
output wire performance_counter_0_control_slave_begintransfer, // .begintransfer
output wire [2:0] spi_stm32_spi_control_port_address, // spi_stm32_spi_control_port.address
output wire spi_stm32_spi_control_port_write, // .write
output wire spi_stm32_spi_control_port_read, // .read
input wire [15:0] spi_stm32_spi_control_port_readdata, // .readdata
output wire [15:0] spi_stm32_spi_control_port_writedata, // .writedata
output wire spi_stm32_spi_control_port_chipselect, // .chipselect
output wire [1:0] spi_sync_s1_address, // spi_sync_s1.address
input wire [31:0] spi_sync_s1_readdata, // .readdata
output wire [1:0] switches_s1_address, // switches_s1.address
input wire [31:0] switches_s1_readdata, // .readdata
output wire [2:0] uart_0_s1_address, // uart_0_s1.address
output wire uart_0_s1_write, // .write
output wire uart_0_s1_read, // .read
input wire [15:0] uart_0_s1_readdata, // .readdata
output wire [15:0] uart_0_s1_writedata, // .writedata
output wire uart_0_s1_begintransfer, // .begintransfer
output wire uart_0_s1_chipselect // .chipselect
);
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest; // abus_slave_0_avalon_master_agent:av_waitrequest -> abus_slave_0_avalon_master_translator:uav_waitrequest
wire [15:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata; // abus_slave_0_avalon_master_agent:av_readdata -> abus_slave_0_avalon_master_translator:uav_readdata
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess; // abus_slave_0_avalon_master_translator:uav_debugaccess -> abus_slave_0_avalon_master_agent:av_debugaccess
wire [27:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_address; // abus_slave_0_avalon_master_translator:uav_address -> abus_slave_0_avalon_master_agent:av_address
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_read; // abus_slave_0_avalon_master_translator:uav_read -> abus_slave_0_avalon_master_agent:av_read
wire [1:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable; // abus_slave_0_avalon_master_translator:uav_byteenable -> abus_slave_0_avalon_master_agent:av_byteenable
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid; // abus_slave_0_avalon_master_agent:av_readdatavalid -> abus_slave_0_avalon_master_translator:uav_readdatavalid
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock; // abus_slave_0_avalon_master_translator:uav_lock -> abus_slave_0_avalon_master_agent:av_lock
wire abus_slave_0_avalon_master_translator_avalon_universal_master_0_write; // abus_slave_0_avalon_master_translator:uav_write -> abus_slave_0_avalon_master_agent:av_write
wire [15:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata; // abus_slave_0_avalon_master_translator:uav_writedata -> abus_slave_0_avalon_master_agent:av_writedata
wire [1:0] abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount; // abus_slave_0_avalon_master_translator:uav_burstcount -> abus_slave_0_avalon_master_agent:av_burstcount
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_data_master_agent:av_waitrequest -> nios2_gen2_0_data_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_data_master_agent:av_readdata -> nios2_gen2_0_data_master_translator:uav_readdata
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_data_master_translator:uav_debugaccess -> nios2_gen2_0_data_master_agent:av_debugaccess
wire [27:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_data_master_translator:uav_address -> nios2_gen2_0_data_master_agent:av_address
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_data_master_translator:uav_read -> nios2_gen2_0_data_master_agent:av_read
wire [3:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_data_master_translator:uav_byteenable -> nios2_gen2_0_data_master_agent:av_byteenable
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_data_master_agent:av_readdatavalid -> nios2_gen2_0_data_master_translator:uav_readdatavalid
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_data_master_translator:uav_lock -> nios2_gen2_0_data_master_agent:av_lock
wire nios2_gen2_0_data_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_data_master_translator:uav_write -> nios2_gen2_0_data_master_agent:av_write
wire [31:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_data_master_translator:uav_writedata -> nios2_gen2_0_data_master_agent:av_writedata
wire [2:0] nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_data_master_translator:uav_burstcount -> nios2_gen2_0_data_master_agent:av_burstcount
wire rsp_mux_001_src_valid; // rsp_mux_001:src_valid -> nios2_gen2_0_data_master_agent:rp_valid
wire [110:0] rsp_mux_001_src_data; // rsp_mux_001:src_data -> nios2_gen2_0_data_master_agent:rp_data
wire rsp_mux_001_src_ready; // nios2_gen2_0_data_master_agent:rp_ready -> rsp_mux_001:src_ready
wire [22:0] rsp_mux_001_src_channel; // rsp_mux_001:src_channel -> nios2_gen2_0_data_master_agent:rp_channel
wire rsp_mux_001_src_startofpacket; // rsp_mux_001:src_startofpacket -> nios2_gen2_0_data_master_agent:rp_startofpacket
wire rsp_mux_001_src_endofpacket; // rsp_mux_001:src_endofpacket -> nios2_gen2_0_data_master_agent:rp_endofpacket
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest; // nios2_gen2_0_instruction_master_agent:av_waitrequest -> nios2_gen2_0_instruction_master_translator:uav_waitrequest
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata; // nios2_gen2_0_instruction_master_agent:av_readdata -> nios2_gen2_0_instruction_master_translator:uav_readdata
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess; // nios2_gen2_0_instruction_master_translator:uav_debugaccess -> nios2_gen2_0_instruction_master_agent:av_debugaccess
wire [27:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address; // nios2_gen2_0_instruction_master_translator:uav_address -> nios2_gen2_0_instruction_master_agent:av_address
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read; // nios2_gen2_0_instruction_master_translator:uav_read -> nios2_gen2_0_instruction_master_agent:av_read
wire [3:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable; // nios2_gen2_0_instruction_master_translator:uav_byteenable -> nios2_gen2_0_instruction_master_agent:av_byteenable
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid; // nios2_gen2_0_instruction_master_agent:av_readdatavalid -> nios2_gen2_0_instruction_master_translator:uav_readdatavalid
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock; // nios2_gen2_0_instruction_master_translator:uav_lock -> nios2_gen2_0_instruction_master_agent:av_lock
wire nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write; // nios2_gen2_0_instruction_master_translator:uav_write -> nios2_gen2_0_instruction_master_agent:av_write
wire [31:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata; // nios2_gen2_0_instruction_master_translator:uav_writedata -> nios2_gen2_0_instruction_master_agent:av_writedata
wire [2:0] nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount; // nios2_gen2_0_instruction_master_translator:uav_burstcount -> nios2_gen2_0_instruction_master_agent:av_burstcount
wire rsp_mux_002_src_valid; // rsp_mux_002:src_valid -> nios2_gen2_0_instruction_master_agent:rp_valid
wire [110:0] rsp_mux_002_src_data; // rsp_mux_002:src_data -> nios2_gen2_0_instruction_master_agent:rp_data
wire rsp_mux_002_src_ready; // nios2_gen2_0_instruction_master_agent:rp_ready -> rsp_mux_002:src_ready
wire [22:0] rsp_mux_002_src_channel; // rsp_mux_002:src_channel -> nios2_gen2_0_instruction_master_agent:rp_channel
wire rsp_mux_002_src_startofpacket; // rsp_mux_002:src_startofpacket -> nios2_gen2_0_instruction_master_agent:rp_startofpacket
wire rsp_mux_002_src_endofpacket; // rsp_mux_002:src_endofpacket -> nios2_gen2_0_instruction_master_agent:rp_endofpacket
wire [15:0] external_sdram_controller_s1_agent_m0_readdata; // external_sdram_controller_s1_translator:uav_readdata -> external_sdram_controller_s1_agent:m0_readdata
wire external_sdram_controller_s1_agent_m0_waitrequest; // external_sdram_controller_s1_translator:uav_waitrequest -> external_sdram_controller_s1_agent:m0_waitrequest
wire external_sdram_controller_s1_agent_m0_debugaccess; // external_sdram_controller_s1_agent:m0_debugaccess -> external_sdram_controller_s1_translator:uav_debugaccess
wire [27:0] external_sdram_controller_s1_agent_m0_address; // external_sdram_controller_s1_agent:m0_address -> external_sdram_controller_s1_translator:uav_address
wire [1:0] external_sdram_controller_s1_agent_m0_byteenable; // external_sdram_controller_s1_agent:m0_byteenable -> external_sdram_controller_s1_translator:uav_byteenable
wire external_sdram_controller_s1_agent_m0_read; // external_sdram_controller_s1_agent:m0_read -> external_sdram_controller_s1_translator:uav_read
wire external_sdram_controller_s1_agent_m0_readdatavalid; // external_sdram_controller_s1_translator:uav_readdatavalid -> external_sdram_controller_s1_agent:m0_readdatavalid
wire external_sdram_controller_s1_agent_m0_lock; // external_sdram_controller_s1_agent:m0_lock -> external_sdram_controller_s1_translator:uav_lock
wire [15:0] external_sdram_controller_s1_agent_m0_writedata; // external_sdram_controller_s1_agent:m0_writedata -> external_sdram_controller_s1_translator:uav_writedata
wire external_sdram_controller_s1_agent_m0_write; // external_sdram_controller_s1_agent:m0_write -> external_sdram_controller_s1_translator:uav_write
wire [1:0] external_sdram_controller_s1_agent_m0_burstcount; // external_sdram_controller_s1_agent:m0_burstcount -> external_sdram_controller_s1_translator:uav_burstcount
wire external_sdram_controller_s1_agent_rf_source_valid; // external_sdram_controller_s1_agent:rf_source_valid -> external_sdram_controller_s1_agent_rsp_fifo:in_valid
wire [93:0] external_sdram_controller_s1_agent_rf_source_data; // external_sdram_controller_s1_agent:rf_source_data -> external_sdram_controller_s1_agent_rsp_fifo:in_data
wire external_sdram_controller_s1_agent_rf_source_ready; // external_sdram_controller_s1_agent_rsp_fifo:in_ready -> external_sdram_controller_s1_agent:rf_source_ready
wire external_sdram_controller_s1_agent_rf_source_startofpacket; // external_sdram_controller_s1_agent:rf_source_startofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_startofpacket
wire external_sdram_controller_s1_agent_rf_source_endofpacket; // external_sdram_controller_s1_agent:rf_source_endofpacket -> external_sdram_controller_s1_agent_rsp_fifo:in_endofpacket
wire external_sdram_controller_s1_agent_rsp_fifo_out_valid; // external_sdram_controller_s1_agent_rsp_fifo:out_valid -> external_sdram_controller_s1_agent:rf_sink_valid
wire [93:0] external_sdram_controller_s1_agent_rsp_fifo_out_data; // external_sdram_controller_s1_agent_rsp_fifo:out_data -> external_sdram_controller_s1_agent:rf_sink_data
wire external_sdram_controller_s1_agent_rsp_fifo_out_ready; // external_sdram_controller_s1_agent:rf_sink_ready -> external_sdram_controller_s1_agent_rsp_fifo:out_ready
wire external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket; // external_sdram_controller_s1_agent_rsp_fifo:out_startofpacket -> external_sdram_controller_s1_agent:rf_sink_startofpacket
wire external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket; // external_sdram_controller_s1_agent_rsp_fifo:out_endofpacket -> external_sdram_controller_s1_agent:rf_sink_endofpacket
wire external_sdram_controller_s1_agent_rdata_fifo_src_valid; // external_sdram_controller_s1_agent:rdata_fifo_src_valid -> external_sdram_controller_s1_agent_rdata_fifo:in_valid
wire [17:0] external_sdram_controller_s1_agent_rdata_fifo_src_data; // external_sdram_controller_s1_agent:rdata_fifo_src_data -> external_sdram_controller_s1_agent_rdata_fifo:in_data
wire external_sdram_controller_s1_agent_rdata_fifo_src_ready; // external_sdram_controller_s1_agent_rdata_fifo:in_ready -> external_sdram_controller_s1_agent:rdata_fifo_src_ready
wire [31:0] onchip_memory2_1_s1_agent_m0_readdata; // onchip_memory2_1_s1_translator:uav_readdata -> onchip_memory2_1_s1_agent:m0_readdata
wire onchip_memory2_1_s1_agent_m0_waitrequest; // onchip_memory2_1_s1_translator:uav_waitrequest -> onchip_memory2_1_s1_agent:m0_waitrequest
wire onchip_memory2_1_s1_agent_m0_debugaccess; // onchip_memory2_1_s1_agent:m0_debugaccess -> onchip_memory2_1_s1_translator:uav_debugaccess
wire [27:0] onchip_memory2_1_s1_agent_m0_address; // onchip_memory2_1_s1_agent:m0_address -> onchip_memory2_1_s1_translator:uav_address
wire [3:0] onchip_memory2_1_s1_agent_m0_byteenable; // onchip_memory2_1_s1_agent:m0_byteenable -> onchip_memory2_1_s1_translator:uav_byteenable
wire onchip_memory2_1_s1_agent_m0_read; // onchip_memory2_1_s1_agent:m0_read -> onchip_memory2_1_s1_translator:uav_read
wire onchip_memory2_1_s1_agent_m0_readdatavalid; // onchip_memory2_1_s1_translator:uav_readdatavalid -> onchip_memory2_1_s1_agent:m0_readdatavalid
wire onchip_memory2_1_s1_agent_m0_lock; // onchip_memory2_1_s1_agent:m0_lock -> onchip_memory2_1_s1_translator:uav_lock
wire [31:0] onchip_memory2_1_s1_agent_m0_writedata; // onchip_memory2_1_s1_agent:m0_writedata -> onchip_memory2_1_s1_translator:uav_writedata
wire onchip_memory2_1_s1_agent_m0_write; // onchip_memory2_1_s1_agent:m0_write -> onchip_memory2_1_s1_translator:uav_write
wire [2:0] onchip_memory2_1_s1_agent_m0_burstcount; // onchip_memory2_1_s1_agent:m0_burstcount -> onchip_memory2_1_s1_translator:uav_burstcount
wire onchip_memory2_1_s1_agent_rf_source_valid; // onchip_memory2_1_s1_agent:rf_source_valid -> onchip_memory2_1_s1_agent_rsp_fifo:in_valid
wire [111:0] onchip_memory2_1_s1_agent_rf_source_data; // onchip_memory2_1_s1_agent:rf_source_data -> onchip_memory2_1_s1_agent_rsp_fifo:in_data
wire onchip_memory2_1_s1_agent_rf_source_ready; // onchip_memory2_1_s1_agent_rsp_fifo:in_ready -> onchip_memory2_1_s1_agent:rf_source_ready
wire onchip_memory2_1_s1_agent_rf_source_startofpacket; // onchip_memory2_1_s1_agent:rf_source_startofpacket -> onchip_memory2_1_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_1_s1_agent_rf_source_endofpacket; // onchip_memory2_1_s1_agent:rf_source_endofpacket -> onchip_memory2_1_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_1_s1_agent_rsp_fifo_out_valid; // onchip_memory2_1_s1_agent_rsp_fifo:out_valid -> onchip_memory2_1_s1_agent:rf_sink_valid
wire [111:0] onchip_memory2_1_s1_agent_rsp_fifo_out_data; // onchip_memory2_1_s1_agent_rsp_fifo:out_data -> onchip_memory2_1_s1_agent:rf_sink_data
wire onchip_memory2_1_s1_agent_rsp_fifo_out_ready; // onchip_memory2_1_s1_agent:rf_sink_ready -> onchip_memory2_1_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_1_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_1_s1_agent:rf_sink_startofpacket
wire onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_1_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_1_s1_agent:rf_sink_endofpacket
wire cmd_mux_001_src_valid; // cmd_mux_001:src_valid -> onchip_memory2_1_s1_agent:cp_valid
wire [110:0] cmd_mux_001_src_data; // cmd_mux_001:src_data -> onchip_memory2_1_s1_agent:cp_data
wire cmd_mux_001_src_ready; // onchip_memory2_1_s1_agent:cp_ready -> cmd_mux_001:src_ready
wire [22:0] cmd_mux_001_src_channel; // cmd_mux_001:src_channel -> onchip_memory2_1_s1_agent:cp_channel
wire cmd_mux_001_src_startofpacket; // cmd_mux_001:src_startofpacket -> onchip_memory2_1_s1_agent:cp_startofpacket
wire cmd_mux_001_src_endofpacket; // cmd_mux_001:src_endofpacket -> onchip_memory2_1_s1_agent:cp_endofpacket
wire [31:0] abus_slave_0_avalon_nios_agent_m0_readdata; // abus_slave_0_avalon_nios_translator:uav_readdata -> abus_slave_0_avalon_nios_agent:m0_readdata
wire abus_slave_0_avalon_nios_agent_m0_waitrequest; // abus_slave_0_avalon_nios_translator:uav_waitrequest -> abus_slave_0_avalon_nios_agent:m0_waitrequest
wire abus_slave_0_avalon_nios_agent_m0_debugaccess; // abus_slave_0_avalon_nios_agent:m0_debugaccess -> abus_slave_0_avalon_nios_translator:uav_debugaccess
wire [27:0] abus_slave_0_avalon_nios_agent_m0_address; // abus_slave_0_avalon_nios_agent:m0_address -> abus_slave_0_avalon_nios_translator:uav_address
wire [3:0] abus_slave_0_avalon_nios_agent_m0_byteenable; // abus_slave_0_avalon_nios_agent:m0_byteenable -> abus_slave_0_avalon_nios_translator:uav_byteenable
wire abus_slave_0_avalon_nios_agent_m0_read; // abus_slave_0_avalon_nios_agent:m0_read -> abus_slave_0_avalon_nios_translator:uav_read
wire abus_slave_0_avalon_nios_agent_m0_readdatavalid; // abus_slave_0_avalon_nios_translator:uav_readdatavalid -> abus_slave_0_avalon_nios_agent:m0_readdatavalid
wire abus_slave_0_avalon_nios_agent_m0_lock; // abus_slave_0_avalon_nios_agent:m0_lock -> abus_slave_0_avalon_nios_translator:uav_lock
wire [31:0] abus_slave_0_avalon_nios_agent_m0_writedata; // abus_slave_0_avalon_nios_agent:m0_writedata -> abus_slave_0_avalon_nios_translator:uav_writedata
wire abus_slave_0_avalon_nios_agent_m0_write; // abus_slave_0_avalon_nios_agent:m0_write -> abus_slave_0_avalon_nios_translator:uav_write
wire [2:0] abus_slave_0_avalon_nios_agent_m0_burstcount; // abus_slave_0_avalon_nios_agent:m0_burstcount -> abus_slave_0_avalon_nios_translator:uav_burstcount
wire abus_slave_0_avalon_nios_agent_rf_source_valid; // abus_slave_0_avalon_nios_agent:rf_source_valid -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_valid
wire [111:0] abus_slave_0_avalon_nios_agent_rf_source_data; // abus_slave_0_avalon_nios_agent:rf_source_data -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_data
wire abus_slave_0_avalon_nios_agent_rf_source_ready; // abus_slave_0_avalon_nios_agent_rsp_fifo:in_ready -> abus_slave_0_avalon_nios_agent:rf_source_ready
wire abus_slave_0_avalon_nios_agent_rf_source_startofpacket; // abus_slave_0_avalon_nios_agent:rf_source_startofpacket -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_startofpacket
wire abus_slave_0_avalon_nios_agent_rf_source_endofpacket; // abus_slave_0_avalon_nios_agent:rf_source_endofpacket -> abus_slave_0_avalon_nios_agent_rsp_fifo:in_endofpacket
wire abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid; // abus_slave_0_avalon_nios_agent_rsp_fifo:out_valid -> abus_slave_0_avalon_nios_agent:rf_sink_valid
wire [111:0] abus_slave_0_avalon_nios_agent_rsp_fifo_out_data; // abus_slave_0_avalon_nios_agent_rsp_fifo:out_data -> abus_slave_0_avalon_nios_agent:rf_sink_data
wire abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready; // abus_slave_0_avalon_nios_agent:rf_sink_ready -> abus_slave_0_avalon_nios_agent_rsp_fifo:out_ready
wire abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket; // abus_slave_0_avalon_nios_agent_rsp_fifo:out_startofpacket -> abus_slave_0_avalon_nios_agent:rf_sink_startofpacket
wire abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket; // abus_slave_0_avalon_nios_agent_rsp_fifo:out_endofpacket -> abus_slave_0_avalon_nios_agent:rf_sink_endofpacket
wire cmd_mux_002_src_valid; // cmd_mux_002:src_valid -> abus_slave_0_avalon_nios_agent:cp_valid
wire [110:0] cmd_mux_002_src_data; // cmd_mux_002:src_data -> abus_slave_0_avalon_nios_agent:cp_data
wire cmd_mux_002_src_ready; // abus_slave_0_avalon_nios_agent:cp_ready -> cmd_mux_002:src_ready
wire [22:0] cmd_mux_002_src_channel; // cmd_mux_002:src_channel -> abus_slave_0_avalon_nios_agent:cp_channel
wire cmd_mux_002_src_startofpacket; // cmd_mux_002:src_startofpacket -> abus_slave_0_avalon_nios_agent:cp_startofpacket
wire cmd_mux_002_src_endofpacket; // cmd_mux_002:src_endofpacket -> abus_slave_0_avalon_nios_agent:cp_endofpacket
wire [31:0] abus_demux_0_avalon_nios_agent_m0_readdata; // abus_demux_0_avalon_nios_translator:uav_readdata -> abus_demux_0_avalon_nios_agent:m0_readdata
wire abus_demux_0_avalon_nios_agent_m0_waitrequest; // abus_demux_0_avalon_nios_translator:uav_waitrequest -> abus_demux_0_avalon_nios_agent:m0_waitrequest
wire abus_demux_0_avalon_nios_agent_m0_debugaccess; // abus_demux_0_avalon_nios_agent:m0_debugaccess -> abus_demux_0_avalon_nios_translator:uav_debugaccess
wire [27:0] abus_demux_0_avalon_nios_agent_m0_address; // abus_demux_0_avalon_nios_agent:m0_address -> abus_demux_0_avalon_nios_translator:uav_address
wire [3:0] abus_demux_0_avalon_nios_agent_m0_byteenable; // abus_demux_0_avalon_nios_agent:m0_byteenable -> abus_demux_0_avalon_nios_translator:uav_byteenable
wire abus_demux_0_avalon_nios_agent_m0_read; // abus_demux_0_avalon_nios_agent:m0_read -> abus_demux_0_avalon_nios_translator:uav_read
wire abus_demux_0_avalon_nios_agent_m0_readdatavalid; // abus_demux_0_avalon_nios_translator:uav_readdatavalid -> abus_demux_0_avalon_nios_agent:m0_readdatavalid
wire abus_demux_0_avalon_nios_agent_m0_lock; // abus_demux_0_avalon_nios_agent:m0_lock -> abus_demux_0_avalon_nios_translator:uav_lock
wire [31:0] abus_demux_0_avalon_nios_agent_m0_writedata; // abus_demux_0_avalon_nios_agent:m0_writedata -> abus_demux_0_avalon_nios_translator:uav_writedata
wire abus_demux_0_avalon_nios_agent_m0_write; // abus_demux_0_avalon_nios_agent:m0_write -> abus_demux_0_avalon_nios_translator:uav_write
wire [2:0] abus_demux_0_avalon_nios_agent_m0_burstcount; // abus_demux_0_avalon_nios_agent:m0_burstcount -> abus_demux_0_avalon_nios_translator:uav_burstcount
wire abus_demux_0_avalon_nios_agent_rf_source_valid; // abus_demux_0_avalon_nios_agent:rf_source_valid -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_valid
wire [111:0] abus_demux_0_avalon_nios_agent_rf_source_data; // abus_demux_0_avalon_nios_agent:rf_source_data -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_data
wire abus_demux_0_avalon_nios_agent_rf_source_ready; // abus_demux_0_avalon_nios_agent_rsp_fifo:in_ready -> abus_demux_0_avalon_nios_agent:rf_source_ready
wire abus_demux_0_avalon_nios_agent_rf_source_startofpacket; // abus_demux_0_avalon_nios_agent:rf_source_startofpacket -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_startofpacket
wire abus_demux_0_avalon_nios_agent_rf_source_endofpacket; // abus_demux_0_avalon_nios_agent:rf_source_endofpacket -> abus_demux_0_avalon_nios_agent_rsp_fifo:in_endofpacket
wire abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid; // abus_demux_0_avalon_nios_agent_rsp_fifo:out_valid -> abus_demux_0_avalon_nios_agent:rf_sink_valid
wire [111:0] abus_demux_0_avalon_nios_agent_rsp_fifo_out_data; // abus_demux_0_avalon_nios_agent_rsp_fifo:out_data -> abus_demux_0_avalon_nios_agent:rf_sink_data
wire abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready; // abus_demux_0_avalon_nios_agent:rf_sink_ready -> abus_demux_0_avalon_nios_agent_rsp_fifo:out_ready
wire abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket; // abus_demux_0_avalon_nios_agent_rsp_fifo:out_startofpacket -> abus_demux_0_avalon_nios_agent:rf_sink_startofpacket
wire abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket; // abus_demux_0_avalon_nios_agent_rsp_fifo:out_endofpacket -> abus_demux_0_avalon_nios_agent:rf_sink_endofpacket
wire cmd_mux_003_src_valid; // cmd_mux_003:src_valid -> abus_demux_0_avalon_nios_agent:cp_valid
wire [110:0] cmd_mux_003_src_data; // cmd_mux_003:src_data -> abus_demux_0_avalon_nios_agent:cp_data
wire cmd_mux_003_src_ready; // abus_demux_0_avalon_nios_agent:cp_ready -> cmd_mux_003:src_ready
wire [22:0] cmd_mux_003_src_channel; // cmd_mux_003:src_channel -> abus_demux_0_avalon_nios_agent:cp_channel
wire cmd_mux_003_src_startofpacket; // cmd_mux_003:src_startofpacket -> abus_demux_0_avalon_nios_agent:cp_startofpacket
wire cmd_mux_003_src_endofpacket; // cmd_mux_003:src_endofpacket -> abus_demux_0_avalon_nios_agent:cp_endofpacket
wire [31:0] performance_counter_0_control_slave_agent_m0_readdata; // performance_counter_0_control_slave_translator:uav_readdata -> performance_counter_0_control_slave_agent:m0_readdata
wire performance_counter_0_control_slave_agent_m0_waitrequest; // performance_counter_0_control_slave_translator:uav_waitrequest -> performance_counter_0_control_slave_agent:m0_waitrequest
wire performance_counter_0_control_slave_agent_m0_debugaccess; // performance_counter_0_control_slave_agent:m0_debugaccess -> performance_counter_0_control_slave_translator:uav_debugaccess
wire [27:0] performance_counter_0_control_slave_agent_m0_address; // performance_counter_0_control_slave_agent:m0_address -> performance_counter_0_control_slave_translator:uav_address
wire [3:0] performance_counter_0_control_slave_agent_m0_byteenable; // performance_counter_0_control_slave_agent:m0_byteenable -> performance_counter_0_control_slave_translator:uav_byteenable
wire performance_counter_0_control_slave_agent_m0_read; // performance_counter_0_control_slave_agent:m0_read -> performance_counter_0_control_slave_translator:uav_read
wire performance_counter_0_control_slave_agent_m0_readdatavalid; // performance_counter_0_control_slave_translator:uav_readdatavalid -> performance_counter_0_control_slave_agent:m0_readdatavalid
wire performance_counter_0_control_slave_agent_m0_lock; // performance_counter_0_control_slave_agent:m0_lock -> performance_counter_0_control_slave_translator:uav_lock
wire [31:0] performance_counter_0_control_slave_agent_m0_writedata; // performance_counter_0_control_slave_agent:m0_writedata -> performance_counter_0_control_slave_translator:uav_writedata
wire performance_counter_0_control_slave_agent_m0_write; // performance_counter_0_control_slave_agent:m0_write -> performance_counter_0_control_slave_translator:uav_write
wire [2:0] performance_counter_0_control_slave_agent_m0_burstcount; // performance_counter_0_control_slave_agent:m0_burstcount -> performance_counter_0_control_slave_translator:uav_burstcount
wire performance_counter_0_control_slave_agent_rf_source_valid; // performance_counter_0_control_slave_agent:rf_source_valid -> performance_counter_0_control_slave_agent_rsp_fifo:in_valid
wire [111:0] performance_counter_0_control_slave_agent_rf_source_data; // performance_counter_0_control_slave_agent:rf_source_data -> performance_counter_0_control_slave_agent_rsp_fifo:in_data
wire performance_counter_0_control_slave_agent_rf_source_ready; // performance_counter_0_control_slave_agent_rsp_fifo:in_ready -> performance_counter_0_control_slave_agent:rf_source_ready
wire performance_counter_0_control_slave_agent_rf_source_startofpacket; // performance_counter_0_control_slave_agent:rf_source_startofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_startofpacket
wire performance_counter_0_control_slave_agent_rf_source_endofpacket; // performance_counter_0_control_slave_agent:rf_source_endofpacket -> performance_counter_0_control_slave_agent_rsp_fifo:in_endofpacket
wire performance_counter_0_control_slave_agent_rsp_fifo_out_valid; // performance_counter_0_control_slave_agent_rsp_fifo:out_valid -> performance_counter_0_control_slave_agent:rf_sink_valid
wire [111:0] performance_counter_0_control_slave_agent_rsp_fifo_out_data; // performance_counter_0_control_slave_agent_rsp_fifo:out_data -> performance_counter_0_control_slave_agent:rf_sink_data
wire performance_counter_0_control_slave_agent_rsp_fifo_out_ready; // performance_counter_0_control_slave_agent:rf_sink_ready -> performance_counter_0_control_slave_agent_rsp_fifo:out_ready
wire performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket; // performance_counter_0_control_slave_agent_rsp_fifo:out_startofpacket -> performance_counter_0_control_slave_agent:rf_sink_startofpacket
wire performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket; // performance_counter_0_control_slave_agent_rsp_fifo:out_endofpacket -> performance_counter_0_control_slave_agent:rf_sink_endofpacket
wire cmd_mux_004_src_valid; // cmd_mux_004:src_valid -> performance_counter_0_control_slave_agent:cp_valid
wire [110:0] cmd_mux_004_src_data; // cmd_mux_004:src_data -> performance_counter_0_control_slave_agent:cp_data
wire cmd_mux_004_src_ready; // performance_counter_0_control_slave_agent:cp_ready -> cmd_mux_004:src_ready
wire [22:0] cmd_mux_004_src_channel; // cmd_mux_004:src_channel -> performance_counter_0_control_slave_agent:cp_channel
wire cmd_mux_004_src_startofpacket; // cmd_mux_004:src_startofpacket -> performance_counter_0_control_slave_agent:cp_startofpacket
wire cmd_mux_004_src_endofpacket; // cmd_mux_004:src_endofpacket -> performance_counter_0_control_slave_agent:cp_endofpacket
wire [31:0] onchip_flash_0_csr_agent_m0_readdata; // onchip_flash_0_csr_translator:uav_readdata -> onchip_flash_0_csr_agent:m0_readdata
wire onchip_flash_0_csr_agent_m0_waitrequest; // onchip_flash_0_csr_translator:uav_waitrequest -> onchip_flash_0_csr_agent:m0_waitrequest
wire onchip_flash_0_csr_agent_m0_debugaccess; // onchip_flash_0_csr_agent:m0_debugaccess -> onchip_flash_0_csr_translator:uav_debugaccess
wire [27:0] onchip_flash_0_csr_agent_m0_address; // onchip_flash_0_csr_agent:m0_address -> onchip_flash_0_csr_translator:uav_address
wire [3:0] onchip_flash_0_csr_agent_m0_byteenable; // onchip_flash_0_csr_agent:m0_byteenable -> onchip_flash_0_csr_translator:uav_byteenable
wire onchip_flash_0_csr_agent_m0_read; // onchip_flash_0_csr_agent:m0_read -> onchip_flash_0_csr_translator:uav_read
wire onchip_flash_0_csr_agent_m0_readdatavalid; // onchip_flash_0_csr_translator:uav_readdatavalid -> onchip_flash_0_csr_agent:m0_readdatavalid
wire onchip_flash_0_csr_agent_m0_lock; // onchip_flash_0_csr_agent:m0_lock -> onchip_flash_0_csr_translator:uav_lock
wire [31:0] onchip_flash_0_csr_agent_m0_writedata; // onchip_flash_0_csr_agent:m0_writedata -> onchip_flash_0_csr_translator:uav_writedata
wire onchip_flash_0_csr_agent_m0_write; // onchip_flash_0_csr_agent:m0_write -> onchip_flash_0_csr_translator:uav_write
wire [2:0] onchip_flash_0_csr_agent_m0_burstcount; // onchip_flash_0_csr_agent:m0_burstcount -> onchip_flash_0_csr_translator:uav_burstcount
wire onchip_flash_0_csr_agent_rf_source_valid; // onchip_flash_0_csr_agent:rf_source_valid -> onchip_flash_0_csr_agent_rsp_fifo:in_valid
wire [111:0] onchip_flash_0_csr_agent_rf_source_data; // onchip_flash_0_csr_agent:rf_source_data -> onchip_flash_0_csr_agent_rsp_fifo:in_data
wire onchip_flash_0_csr_agent_rf_source_ready; // onchip_flash_0_csr_agent_rsp_fifo:in_ready -> onchip_flash_0_csr_agent:rf_source_ready
wire onchip_flash_0_csr_agent_rf_source_startofpacket; // onchip_flash_0_csr_agent:rf_source_startofpacket -> onchip_flash_0_csr_agent_rsp_fifo:in_startofpacket
wire onchip_flash_0_csr_agent_rf_source_endofpacket; // onchip_flash_0_csr_agent:rf_source_endofpacket -> onchip_flash_0_csr_agent_rsp_fifo:in_endofpacket
wire onchip_flash_0_csr_agent_rsp_fifo_out_valid; // onchip_flash_0_csr_agent_rsp_fifo:out_valid -> onchip_flash_0_csr_agent:rf_sink_valid
wire [111:0] onchip_flash_0_csr_agent_rsp_fifo_out_data; // onchip_flash_0_csr_agent_rsp_fifo:out_data -> onchip_flash_0_csr_agent:rf_sink_data
wire onchip_flash_0_csr_agent_rsp_fifo_out_ready; // onchip_flash_0_csr_agent:rf_sink_ready -> onchip_flash_0_csr_agent_rsp_fifo:out_ready
wire onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket; // onchip_flash_0_csr_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_csr_agent:rf_sink_startofpacket
wire onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket; // onchip_flash_0_csr_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_csr_agent:rf_sink_endofpacket
wire cmd_mux_005_src_valid; // cmd_mux_005:src_valid -> onchip_flash_0_csr_agent:cp_valid
wire [110:0] cmd_mux_005_src_data; // cmd_mux_005:src_data -> onchip_flash_0_csr_agent:cp_data
wire cmd_mux_005_src_ready; // onchip_flash_0_csr_agent:cp_ready -> cmd_mux_005:src_ready
wire [22:0] cmd_mux_005_src_channel; // cmd_mux_005:src_channel -> onchip_flash_0_csr_agent:cp_channel
wire cmd_mux_005_src_startofpacket; // cmd_mux_005:src_startofpacket -> onchip_flash_0_csr_agent:cp_startofpacket
wire cmd_mux_005_src_endofpacket; // cmd_mux_005:src_endofpacket -> onchip_flash_0_csr_agent:cp_endofpacket
wire [31:0] onchip_flash_0_data_agent_m0_readdata; // onchip_flash_0_data_translator:uav_readdata -> onchip_flash_0_data_agent:m0_readdata
wire onchip_flash_0_data_agent_m0_waitrequest; // onchip_flash_0_data_translator:uav_waitrequest -> onchip_flash_0_data_agent:m0_waitrequest
wire onchip_flash_0_data_agent_m0_debugaccess; // onchip_flash_0_data_agent:m0_debugaccess -> onchip_flash_0_data_translator:uav_debugaccess
wire [27:0] onchip_flash_0_data_agent_m0_address; // onchip_flash_0_data_agent:m0_address -> onchip_flash_0_data_translator:uav_address
wire [3:0] onchip_flash_0_data_agent_m0_byteenable; // onchip_flash_0_data_agent:m0_byteenable -> onchip_flash_0_data_translator:uav_byteenable
wire onchip_flash_0_data_agent_m0_read; // onchip_flash_0_data_agent:m0_read -> onchip_flash_0_data_translator:uav_read
wire onchip_flash_0_data_agent_m0_readdatavalid; // onchip_flash_0_data_translator:uav_readdatavalid -> onchip_flash_0_data_agent:m0_readdatavalid
wire onchip_flash_0_data_agent_m0_lock; // onchip_flash_0_data_agent:m0_lock -> onchip_flash_0_data_translator:uav_lock
wire [31:0] onchip_flash_0_data_agent_m0_writedata; // onchip_flash_0_data_agent:m0_writedata -> onchip_flash_0_data_translator:uav_writedata
wire onchip_flash_0_data_agent_m0_write; // onchip_flash_0_data_agent:m0_write -> onchip_flash_0_data_translator:uav_write
wire [5:0] onchip_flash_0_data_agent_m0_burstcount; // onchip_flash_0_data_agent:m0_burstcount -> onchip_flash_0_data_translator:uav_burstcount
wire onchip_flash_0_data_agent_rf_source_valid; // onchip_flash_0_data_agent:rf_source_valid -> onchip_flash_0_data_agent_rsp_fifo:in_valid
wire [111:0] onchip_flash_0_data_agent_rf_source_data; // onchip_flash_0_data_agent:rf_source_data -> onchip_flash_0_data_agent_rsp_fifo:in_data
wire onchip_flash_0_data_agent_rf_source_ready; // onchip_flash_0_data_agent_rsp_fifo:in_ready -> onchip_flash_0_data_agent:rf_source_ready
wire onchip_flash_0_data_agent_rf_source_startofpacket; // onchip_flash_0_data_agent:rf_source_startofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_startofpacket
wire onchip_flash_0_data_agent_rf_source_endofpacket; // onchip_flash_0_data_agent:rf_source_endofpacket -> onchip_flash_0_data_agent_rsp_fifo:in_endofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_valid; // onchip_flash_0_data_agent_rsp_fifo:out_valid -> onchip_flash_0_data_agent:rf_sink_valid
wire [111:0] onchip_flash_0_data_agent_rsp_fifo_out_data; // onchip_flash_0_data_agent_rsp_fifo:out_data -> onchip_flash_0_data_agent:rf_sink_data
wire onchip_flash_0_data_agent_rsp_fifo_out_ready; // onchip_flash_0_data_agent:rf_sink_ready -> onchip_flash_0_data_agent_rsp_fifo:out_ready
wire onchip_flash_0_data_agent_rsp_fifo_out_startofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_startofpacket -> onchip_flash_0_data_agent:rf_sink_startofpacket
wire onchip_flash_0_data_agent_rsp_fifo_out_endofpacket; // onchip_flash_0_data_agent_rsp_fifo:out_endofpacket -> onchip_flash_0_data_agent:rf_sink_endofpacket
wire cmd_mux_006_src_valid; // cmd_mux_006:src_valid -> onchip_flash_0_data_agent:cp_valid
wire [110:0] cmd_mux_006_src_data; // cmd_mux_006:src_data -> onchip_flash_0_data_agent:cp_data
wire cmd_mux_006_src_ready; // onchip_flash_0_data_agent:cp_ready -> cmd_mux_006:src_ready
wire [22:0] cmd_mux_006_src_channel; // cmd_mux_006:src_channel -> onchip_flash_0_data_agent:cp_channel
wire cmd_mux_006_src_startofpacket; // cmd_mux_006:src_startofpacket -> onchip_flash_0_data_agent:cp_startofpacket
wire cmd_mux_006_src_endofpacket; // cmd_mux_006:src_endofpacket -> onchip_flash_0_data_agent:cp_endofpacket
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_readdata; // nios2_gen2_0_debug_mem_slave_translator:uav_readdata -> nios2_gen2_0_debug_mem_slave_agent:m0_readdata
wire nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest; // nios2_gen2_0_debug_mem_slave_translator:uav_waitrequest -> nios2_gen2_0_debug_mem_slave_agent:m0_waitrequest
wire nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess; // nios2_gen2_0_debug_mem_slave_agent:m0_debugaccess -> nios2_gen2_0_debug_mem_slave_translator:uav_debugaccess
wire [27:0] nios2_gen2_0_debug_mem_slave_agent_m0_address; // nios2_gen2_0_debug_mem_slave_agent:m0_address -> nios2_gen2_0_debug_mem_slave_translator:uav_address
wire [3:0] nios2_gen2_0_debug_mem_slave_agent_m0_byteenable; // nios2_gen2_0_debug_mem_slave_agent:m0_byteenable -> nios2_gen2_0_debug_mem_slave_translator:uav_byteenable
wire nios2_gen2_0_debug_mem_slave_agent_m0_read; // nios2_gen2_0_debug_mem_slave_agent:m0_read -> nios2_gen2_0_debug_mem_slave_translator:uav_read
wire nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid; // nios2_gen2_0_debug_mem_slave_translator:uav_readdatavalid -> nios2_gen2_0_debug_mem_slave_agent:m0_readdatavalid
wire nios2_gen2_0_debug_mem_slave_agent_m0_lock; // nios2_gen2_0_debug_mem_slave_agent:m0_lock -> nios2_gen2_0_debug_mem_slave_translator:uav_lock
wire [31:0] nios2_gen2_0_debug_mem_slave_agent_m0_writedata; // nios2_gen2_0_debug_mem_slave_agent:m0_writedata -> nios2_gen2_0_debug_mem_slave_translator:uav_writedata
wire nios2_gen2_0_debug_mem_slave_agent_m0_write; // nios2_gen2_0_debug_mem_slave_agent:m0_write -> nios2_gen2_0_debug_mem_slave_translator:uav_write
wire [2:0] nios2_gen2_0_debug_mem_slave_agent_m0_burstcount; // nios2_gen2_0_debug_mem_slave_agent:m0_burstcount -> nios2_gen2_0_debug_mem_slave_translator:uav_burstcount
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_valid; // nios2_gen2_0_debug_mem_slave_agent:rf_source_valid -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_valid
wire [111:0] nios2_gen2_0_debug_mem_slave_agent_rf_source_data; // nios2_gen2_0_debug_mem_slave_agent:rf_source_data -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_data
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_ready; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_ready -> nios2_gen2_0_debug_mem_slave_agent:rf_source_ready
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_startofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rf_source_endofpacket -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:in_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_valid -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_valid
wire [111:0] nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_data -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready; // nios2_gen2_0_debug_mem_slave_agent:rf_sink_ready -> nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_ready
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket; // nios2_gen2_0_debug_mem_slave_agent_rsp_fifo:out_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:rf_sink_endofpacket
wire cmd_mux_007_src_valid; // cmd_mux_007:src_valid -> nios2_gen2_0_debug_mem_slave_agent:cp_valid
wire [110:0] cmd_mux_007_src_data; // cmd_mux_007:src_data -> nios2_gen2_0_debug_mem_slave_agent:cp_data
wire cmd_mux_007_src_ready; // nios2_gen2_0_debug_mem_slave_agent:cp_ready -> cmd_mux_007:src_ready
wire [22:0] cmd_mux_007_src_channel; // cmd_mux_007:src_channel -> nios2_gen2_0_debug_mem_slave_agent:cp_channel
wire cmd_mux_007_src_startofpacket; // cmd_mux_007:src_startofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_startofpacket
wire cmd_mux_007_src_endofpacket; // cmd_mux_007:src_endofpacket -> nios2_gen2_0_debug_mem_slave_agent:cp_endofpacket
wire [31:0] altpll_0_pll_slave_agent_m0_readdata; // altpll_0_pll_slave_translator:uav_readdata -> altpll_0_pll_slave_agent:m0_readdata
wire altpll_0_pll_slave_agent_m0_waitrequest; // altpll_0_pll_slave_translator:uav_waitrequest -> altpll_0_pll_slave_agent:m0_waitrequest
wire altpll_0_pll_slave_agent_m0_debugaccess; // altpll_0_pll_slave_agent:m0_debugaccess -> altpll_0_pll_slave_translator:uav_debugaccess
wire [27:0] altpll_0_pll_slave_agent_m0_address; // altpll_0_pll_slave_agent:m0_address -> altpll_0_pll_slave_translator:uav_address
wire [3:0] altpll_0_pll_slave_agent_m0_byteenable; // altpll_0_pll_slave_agent:m0_byteenable -> altpll_0_pll_slave_translator:uav_byteenable
wire altpll_0_pll_slave_agent_m0_read; // altpll_0_pll_slave_agent:m0_read -> altpll_0_pll_slave_translator:uav_read
wire altpll_0_pll_slave_agent_m0_readdatavalid; // altpll_0_pll_slave_translator:uav_readdatavalid -> altpll_0_pll_slave_agent:m0_readdatavalid
wire altpll_0_pll_slave_agent_m0_lock; // altpll_0_pll_slave_agent:m0_lock -> altpll_0_pll_slave_translator:uav_lock
wire [31:0] altpll_0_pll_slave_agent_m0_writedata; // altpll_0_pll_slave_agent:m0_writedata -> altpll_0_pll_slave_translator:uav_writedata
wire altpll_0_pll_slave_agent_m0_write; // altpll_0_pll_slave_agent:m0_write -> altpll_0_pll_slave_translator:uav_write
wire [2:0] altpll_0_pll_slave_agent_m0_burstcount; // altpll_0_pll_slave_agent:m0_burstcount -> altpll_0_pll_slave_translator:uav_burstcount
wire altpll_0_pll_slave_agent_rf_source_valid; // altpll_0_pll_slave_agent:rf_source_valid -> altpll_0_pll_slave_agent_rsp_fifo:in_valid
wire [111:0] altpll_0_pll_slave_agent_rf_source_data; // altpll_0_pll_slave_agent:rf_source_data -> altpll_0_pll_slave_agent_rsp_fifo:in_data
wire altpll_0_pll_slave_agent_rf_source_ready; // altpll_0_pll_slave_agent_rsp_fifo:in_ready -> altpll_0_pll_slave_agent:rf_source_ready
wire altpll_0_pll_slave_agent_rf_source_startofpacket; // altpll_0_pll_slave_agent:rf_source_startofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_startofpacket
wire altpll_0_pll_slave_agent_rf_source_endofpacket; // altpll_0_pll_slave_agent:rf_source_endofpacket -> altpll_0_pll_slave_agent_rsp_fifo:in_endofpacket
wire altpll_0_pll_slave_agent_rsp_fifo_out_valid; // altpll_0_pll_slave_agent_rsp_fifo:out_valid -> altpll_0_pll_slave_agent:rf_sink_valid
wire [111:0] altpll_0_pll_slave_agent_rsp_fifo_out_data; // altpll_0_pll_slave_agent_rsp_fifo:out_data -> altpll_0_pll_slave_agent:rf_sink_data
wire altpll_0_pll_slave_agent_rsp_fifo_out_ready; // altpll_0_pll_slave_agent:rf_sink_ready -> altpll_0_pll_slave_agent_rsp_fifo:out_ready
wire altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket; // altpll_0_pll_slave_agent_rsp_fifo:out_startofpacket -> altpll_0_pll_slave_agent:rf_sink_startofpacket
wire altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket; // altpll_0_pll_slave_agent_rsp_fifo:out_endofpacket -> altpll_0_pll_slave_agent:rf_sink_endofpacket
wire altpll_0_pll_slave_agent_rdata_fifo_src_valid; // altpll_0_pll_slave_agent:rdata_fifo_src_valid -> altpll_0_pll_slave_agent_rdata_fifo:in_valid
wire [33:0] altpll_0_pll_slave_agent_rdata_fifo_src_data; // altpll_0_pll_slave_agent:rdata_fifo_src_data -> altpll_0_pll_slave_agent_rdata_fifo:in_data
wire altpll_0_pll_slave_agent_rdata_fifo_src_ready; // altpll_0_pll_slave_agent_rdata_fifo:in_ready -> altpll_0_pll_slave_agent:rdata_fifo_src_ready
wire cmd_mux_008_src_valid; // cmd_mux_008:src_valid -> altpll_0_pll_slave_agent:cp_valid
wire [110:0] cmd_mux_008_src_data; // cmd_mux_008:src_data -> altpll_0_pll_slave_agent:cp_data
wire cmd_mux_008_src_ready; // altpll_0_pll_slave_agent:cp_ready -> cmd_mux_008:src_ready
wire [22:0] cmd_mux_008_src_channel; // cmd_mux_008:src_channel -> altpll_0_pll_slave_agent:cp_channel
wire cmd_mux_008_src_startofpacket; // cmd_mux_008:src_startofpacket -> altpll_0_pll_slave_agent:cp_startofpacket
wire cmd_mux_008_src_endofpacket; // cmd_mux_008:src_endofpacket -> altpll_0_pll_slave_agent:cp_endofpacket
wire [31:0] onchip_memory2_0_s1_agent_m0_readdata; // onchip_memory2_0_s1_translator:uav_readdata -> onchip_memory2_0_s1_agent:m0_readdata
wire onchip_memory2_0_s1_agent_m0_waitrequest; // onchip_memory2_0_s1_translator:uav_waitrequest -> onchip_memory2_0_s1_agent:m0_waitrequest
wire onchip_memory2_0_s1_agent_m0_debugaccess; // onchip_memory2_0_s1_agent:m0_debugaccess -> onchip_memory2_0_s1_translator:uav_debugaccess
wire [27:0] onchip_memory2_0_s1_agent_m0_address; // onchip_memory2_0_s1_agent:m0_address -> onchip_memory2_0_s1_translator:uav_address
wire [3:0] onchip_memory2_0_s1_agent_m0_byteenable; // onchip_memory2_0_s1_agent:m0_byteenable -> onchip_memory2_0_s1_translator:uav_byteenable
wire onchip_memory2_0_s1_agent_m0_read; // onchip_memory2_0_s1_agent:m0_read -> onchip_memory2_0_s1_translator:uav_read
wire onchip_memory2_0_s1_agent_m0_readdatavalid; // onchip_memory2_0_s1_translator:uav_readdatavalid -> onchip_memory2_0_s1_agent:m0_readdatavalid
wire onchip_memory2_0_s1_agent_m0_lock; // onchip_memory2_0_s1_agent:m0_lock -> onchip_memory2_0_s1_translator:uav_lock
wire [31:0] onchip_memory2_0_s1_agent_m0_writedata; // onchip_memory2_0_s1_agent:m0_writedata -> onchip_memory2_0_s1_translator:uav_writedata
wire onchip_memory2_0_s1_agent_m0_write; // onchip_memory2_0_s1_agent:m0_write -> onchip_memory2_0_s1_translator:uav_write
wire [2:0] onchip_memory2_0_s1_agent_m0_burstcount; // onchip_memory2_0_s1_agent:m0_burstcount -> onchip_memory2_0_s1_translator:uav_burstcount
wire onchip_memory2_0_s1_agent_rf_source_valid; // onchip_memory2_0_s1_agent:rf_source_valid -> onchip_memory2_0_s1_agent_rsp_fifo:in_valid
wire [111:0] onchip_memory2_0_s1_agent_rf_source_data; // onchip_memory2_0_s1_agent:rf_source_data -> onchip_memory2_0_s1_agent_rsp_fifo:in_data
wire onchip_memory2_0_s1_agent_rf_source_ready; // onchip_memory2_0_s1_agent_rsp_fifo:in_ready -> onchip_memory2_0_s1_agent:rf_source_ready
wire onchip_memory2_0_s1_agent_rf_source_startofpacket; // onchip_memory2_0_s1_agent:rf_source_startofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_startofpacket
wire onchip_memory2_0_s1_agent_rf_source_endofpacket; // onchip_memory2_0_s1_agent:rf_source_endofpacket -> onchip_memory2_0_s1_agent_rsp_fifo:in_endofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_valid; // onchip_memory2_0_s1_agent_rsp_fifo:out_valid -> onchip_memory2_0_s1_agent:rf_sink_valid
wire [111:0] onchip_memory2_0_s1_agent_rsp_fifo_out_data; // onchip_memory2_0_s1_agent_rsp_fifo:out_data -> onchip_memory2_0_s1_agent:rf_sink_data
wire onchip_memory2_0_s1_agent_rsp_fifo_out_ready; // onchip_memory2_0_s1_agent:rf_sink_ready -> onchip_memory2_0_s1_agent_rsp_fifo:out_ready
wire onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_startofpacket -> onchip_memory2_0_s1_agent:rf_sink_startofpacket
wire onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket; // onchip_memory2_0_s1_agent_rsp_fifo:out_endofpacket -> onchip_memory2_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_009_src_valid; // cmd_mux_009:src_valid -> onchip_memory2_0_s1_agent:cp_valid
wire [110:0] cmd_mux_009_src_data; // cmd_mux_009:src_data -> onchip_memory2_0_s1_agent:cp_data
wire cmd_mux_009_src_ready; // onchip_memory2_0_s1_agent:cp_ready -> cmd_mux_009:src_ready
wire [22:0] cmd_mux_009_src_channel; // cmd_mux_009:src_channel -> onchip_memory2_0_s1_agent:cp_channel
wire cmd_mux_009_src_startofpacket; // cmd_mux_009:src_startofpacket -> onchip_memory2_0_s1_agent:cp_startofpacket
wire cmd_mux_009_src_endofpacket; // cmd_mux_009:src_endofpacket -> onchip_memory2_0_s1_agent:cp_endofpacket
wire [31:0] switches_s1_agent_m0_readdata; // switches_s1_translator:uav_readdata -> switches_s1_agent:m0_readdata
wire switches_s1_agent_m0_waitrequest; // switches_s1_translator:uav_waitrequest -> switches_s1_agent:m0_waitrequest
wire switches_s1_agent_m0_debugaccess; // switches_s1_agent:m0_debugaccess -> switches_s1_translator:uav_debugaccess
wire [27:0] switches_s1_agent_m0_address; // switches_s1_agent:m0_address -> switches_s1_translator:uav_address
wire [3:0] switches_s1_agent_m0_byteenable; // switches_s1_agent:m0_byteenable -> switches_s1_translator:uav_byteenable
wire switches_s1_agent_m0_read; // switches_s1_agent:m0_read -> switches_s1_translator:uav_read
wire switches_s1_agent_m0_readdatavalid; // switches_s1_translator:uav_readdatavalid -> switches_s1_agent:m0_readdatavalid
wire switches_s1_agent_m0_lock; // switches_s1_agent:m0_lock -> switches_s1_translator:uav_lock
wire [31:0] switches_s1_agent_m0_writedata; // switches_s1_agent:m0_writedata -> switches_s1_translator:uav_writedata
wire switches_s1_agent_m0_write; // switches_s1_agent:m0_write -> switches_s1_translator:uav_write
wire [2:0] switches_s1_agent_m0_burstcount; // switches_s1_agent:m0_burstcount -> switches_s1_translator:uav_burstcount
wire switches_s1_agent_rf_source_valid; // switches_s1_agent:rf_source_valid -> switches_s1_agent_rsp_fifo:in_valid
wire [111:0] switches_s1_agent_rf_source_data; // switches_s1_agent:rf_source_data -> switches_s1_agent_rsp_fifo:in_data
wire switches_s1_agent_rf_source_ready; // switches_s1_agent_rsp_fifo:in_ready -> switches_s1_agent:rf_source_ready
wire switches_s1_agent_rf_source_startofpacket; // switches_s1_agent:rf_source_startofpacket -> switches_s1_agent_rsp_fifo:in_startofpacket
wire switches_s1_agent_rf_source_endofpacket; // switches_s1_agent:rf_source_endofpacket -> switches_s1_agent_rsp_fifo:in_endofpacket
wire switches_s1_agent_rsp_fifo_out_valid; // switches_s1_agent_rsp_fifo:out_valid -> switches_s1_agent:rf_sink_valid
wire [111:0] switches_s1_agent_rsp_fifo_out_data; // switches_s1_agent_rsp_fifo:out_data -> switches_s1_agent:rf_sink_data
wire switches_s1_agent_rsp_fifo_out_ready; // switches_s1_agent:rf_sink_ready -> switches_s1_agent_rsp_fifo:out_ready
wire switches_s1_agent_rsp_fifo_out_startofpacket; // switches_s1_agent_rsp_fifo:out_startofpacket -> switches_s1_agent:rf_sink_startofpacket
wire switches_s1_agent_rsp_fifo_out_endofpacket; // switches_s1_agent_rsp_fifo:out_endofpacket -> switches_s1_agent:rf_sink_endofpacket
wire cmd_mux_010_src_valid; // cmd_mux_010:src_valid -> switches_s1_agent:cp_valid
wire [110:0] cmd_mux_010_src_data; // cmd_mux_010:src_data -> switches_s1_agent:cp_data
wire cmd_mux_010_src_ready; // switches_s1_agent:cp_ready -> cmd_mux_010:src_ready
wire [22:0] cmd_mux_010_src_channel; // cmd_mux_010:src_channel -> switches_s1_agent:cp_channel
wire cmd_mux_010_src_startofpacket; // cmd_mux_010:src_startofpacket -> switches_s1_agent:cp_startofpacket
wire cmd_mux_010_src_endofpacket; // cmd_mux_010:src_endofpacket -> switches_s1_agent:cp_endofpacket
wire [31:0] leds_s1_agent_m0_readdata; // leds_s1_translator:uav_readdata -> leds_s1_agent:m0_readdata
wire leds_s1_agent_m0_waitrequest; // leds_s1_translator:uav_waitrequest -> leds_s1_agent:m0_waitrequest
wire leds_s1_agent_m0_debugaccess; // leds_s1_agent:m0_debugaccess -> leds_s1_translator:uav_debugaccess
wire [27:0] leds_s1_agent_m0_address; // leds_s1_agent:m0_address -> leds_s1_translator:uav_address
wire [3:0] leds_s1_agent_m0_byteenable; // leds_s1_agent:m0_byteenable -> leds_s1_translator:uav_byteenable
wire leds_s1_agent_m0_read; // leds_s1_agent:m0_read -> leds_s1_translator:uav_read
wire leds_s1_agent_m0_readdatavalid; // leds_s1_translator:uav_readdatavalid -> leds_s1_agent:m0_readdatavalid
wire leds_s1_agent_m0_lock; // leds_s1_agent:m0_lock -> leds_s1_translator:uav_lock
wire [31:0] leds_s1_agent_m0_writedata; // leds_s1_agent:m0_writedata -> leds_s1_translator:uav_writedata
wire leds_s1_agent_m0_write; // leds_s1_agent:m0_write -> leds_s1_translator:uav_write
wire [2:0] leds_s1_agent_m0_burstcount; // leds_s1_agent:m0_burstcount -> leds_s1_translator:uav_burstcount
wire leds_s1_agent_rf_source_valid; // leds_s1_agent:rf_source_valid -> leds_s1_agent_rsp_fifo:in_valid
wire [111:0] leds_s1_agent_rf_source_data; // leds_s1_agent:rf_source_data -> leds_s1_agent_rsp_fifo:in_data
wire leds_s1_agent_rf_source_ready; // leds_s1_agent_rsp_fifo:in_ready -> leds_s1_agent:rf_source_ready
wire leds_s1_agent_rf_source_startofpacket; // leds_s1_agent:rf_source_startofpacket -> leds_s1_agent_rsp_fifo:in_startofpacket
wire leds_s1_agent_rf_source_endofpacket; // leds_s1_agent:rf_source_endofpacket -> leds_s1_agent_rsp_fifo:in_endofpacket
wire leds_s1_agent_rsp_fifo_out_valid; // leds_s1_agent_rsp_fifo:out_valid -> leds_s1_agent:rf_sink_valid
wire [111:0] leds_s1_agent_rsp_fifo_out_data; // leds_s1_agent_rsp_fifo:out_data -> leds_s1_agent:rf_sink_data
wire leds_s1_agent_rsp_fifo_out_ready; // leds_s1_agent:rf_sink_ready -> leds_s1_agent_rsp_fifo:out_ready
wire leds_s1_agent_rsp_fifo_out_startofpacket; // leds_s1_agent_rsp_fifo:out_startofpacket -> leds_s1_agent:rf_sink_startofpacket
wire leds_s1_agent_rsp_fifo_out_endofpacket; // leds_s1_agent_rsp_fifo:out_endofpacket -> leds_s1_agent:rf_sink_endofpacket
wire cmd_mux_011_src_valid; // cmd_mux_011:src_valid -> leds_s1_agent:cp_valid
wire [110:0] cmd_mux_011_src_data; // cmd_mux_011:src_data -> leds_s1_agent:cp_data
wire cmd_mux_011_src_ready; // leds_s1_agent:cp_ready -> cmd_mux_011:src_ready
wire [22:0] cmd_mux_011_src_channel; // cmd_mux_011:src_channel -> leds_s1_agent:cp_channel
wire cmd_mux_011_src_startofpacket; // cmd_mux_011:src_startofpacket -> leds_s1_agent:cp_startofpacket
wire cmd_mux_011_src_endofpacket; // cmd_mux_011:src_endofpacket -> leds_s1_agent:cp_endofpacket
wire [31:0] uart_0_s1_agent_m0_readdata; // uart_0_s1_translator:uav_readdata -> uart_0_s1_agent:m0_readdata
wire uart_0_s1_agent_m0_waitrequest; // uart_0_s1_translator:uav_waitrequest -> uart_0_s1_agent:m0_waitrequest
wire uart_0_s1_agent_m0_debugaccess; // uart_0_s1_agent:m0_debugaccess -> uart_0_s1_translator:uav_debugaccess
wire [27:0] uart_0_s1_agent_m0_address; // uart_0_s1_agent:m0_address -> uart_0_s1_translator:uav_address
wire [3:0] uart_0_s1_agent_m0_byteenable; // uart_0_s1_agent:m0_byteenable -> uart_0_s1_translator:uav_byteenable
wire uart_0_s1_agent_m0_read; // uart_0_s1_agent:m0_read -> uart_0_s1_translator:uav_read
wire uart_0_s1_agent_m0_readdatavalid; // uart_0_s1_translator:uav_readdatavalid -> uart_0_s1_agent:m0_readdatavalid
wire uart_0_s1_agent_m0_lock; // uart_0_s1_agent:m0_lock -> uart_0_s1_translator:uav_lock
wire [31:0] uart_0_s1_agent_m0_writedata; // uart_0_s1_agent:m0_writedata -> uart_0_s1_translator:uav_writedata
wire uart_0_s1_agent_m0_write; // uart_0_s1_agent:m0_write -> uart_0_s1_translator:uav_write
wire [2:0] uart_0_s1_agent_m0_burstcount; // uart_0_s1_agent:m0_burstcount -> uart_0_s1_translator:uav_burstcount
wire uart_0_s1_agent_rf_source_valid; // uart_0_s1_agent:rf_source_valid -> uart_0_s1_agent_rsp_fifo:in_valid
wire [111:0] uart_0_s1_agent_rf_source_data; // uart_0_s1_agent:rf_source_data -> uart_0_s1_agent_rsp_fifo:in_data
wire uart_0_s1_agent_rf_source_ready; // uart_0_s1_agent_rsp_fifo:in_ready -> uart_0_s1_agent:rf_source_ready
wire uart_0_s1_agent_rf_source_startofpacket; // uart_0_s1_agent:rf_source_startofpacket -> uart_0_s1_agent_rsp_fifo:in_startofpacket
wire uart_0_s1_agent_rf_source_endofpacket; // uart_0_s1_agent:rf_source_endofpacket -> uart_0_s1_agent_rsp_fifo:in_endofpacket
wire uart_0_s1_agent_rsp_fifo_out_valid; // uart_0_s1_agent_rsp_fifo:out_valid -> uart_0_s1_agent:rf_sink_valid
wire [111:0] uart_0_s1_agent_rsp_fifo_out_data; // uart_0_s1_agent_rsp_fifo:out_data -> uart_0_s1_agent:rf_sink_data
wire uart_0_s1_agent_rsp_fifo_out_ready; // uart_0_s1_agent:rf_sink_ready -> uart_0_s1_agent_rsp_fifo:out_ready
wire uart_0_s1_agent_rsp_fifo_out_startofpacket; // uart_0_s1_agent_rsp_fifo:out_startofpacket -> uart_0_s1_agent:rf_sink_startofpacket
wire uart_0_s1_agent_rsp_fifo_out_endofpacket; // uart_0_s1_agent_rsp_fifo:out_endofpacket -> uart_0_s1_agent:rf_sink_endofpacket
wire cmd_mux_012_src_valid; // cmd_mux_012:src_valid -> uart_0_s1_agent:cp_valid
wire [110:0] cmd_mux_012_src_data; // cmd_mux_012:src_data -> uart_0_s1_agent:cp_data
wire cmd_mux_012_src_ready; // uart_0_s1_agent:cp_ready -> cmd_mux_012:src_ready
wire [22:0] cmd_mux_012_src_channel; // cmd_mux_012:src_channel -> uart_0_s1_agent:cp_channel
wire cmd_mux_012_src_startofpacket; // cmd_mux_012:src_startofpacket -> uart_0_s1_agent:cp_startofpacket
wire cmd_mux_012_src_endofpacket; // cmd_mux_012:src_endofpacket -> uart_0_s1_agent:cp_endofpacket
wire [31:0] hex0_s1_agent_m0_readdata; // hex0_s1_translator:uav_readdata -> hex0_s1_agent:m0_readdata
wire hex0_s1_agent_m0_waitrequest; // hex0_s1_translator:uav_waitrequest -> hex0_s1_agent:m0_waitrequest
wire hex0_s1_agent_m0_debugaccess; // hex0_s1_agent:m0_debugaccess -> hex0_s1_translator:uav_debugaccess
wire [27:0] hex0_s1_agent_m0_address; // hex0_s1_agent:m0_address -> hex0_s1_translator:uav_address
wire [3:0] hex0_s1_agent_m0_byteenable; // hex0_s1_agent:m0_byteenable -> hex0_s1_translator:uav_byteenable
wire hex0_s1_agent_m0_read; // hex0_s1_agent:m0_read -> hex0_s1_translator:uav_read
wire hex0_s1_agent_m0_readdatavalid; // hex0_s1_translator:uav_readdatavalid -> hex0_s1_agent:m0_readdatavalid
wire hex0_s1_agent_m0_lock; // hex0_s1_agent:m0_lock -> hex0_s1_translator:uav_lock
wire [31:0] hex0_s1_agent_m0_writedata; // hex0_s1_agent:m0_writedata -> hex0_s1_translator:uav_writedata
wire hex0_s1_agent_m0_write; // hex0_s1_agent:m0_write -> hex0_s1_translator:uav_write
wire [2:0] hex0_s1_agent_m0_burstcount; // hex0_s1_agent:m0_burstcount -> hex0_s1_translator:uav_burstcount
wire hex0_s1_agent_rf_source_valid; // hex0_s1_agent:rf_source_valid -> hex0_s1_agent_rsp_fifo:in_valid
wire [111:0] hex0_s1_agent_rf_source_data; // hex0_s1_agent:rf_source_data -> hex0_s1_agent_rsp_fifo:in_data
wire hex0_s1_agent_rf_source_ready; // hex0_s1_agent_rsp_fifo:in_ready -> hex0_s1_agent:rf_source_ready
wire hex0_s1_agent_rf_source_startofpacket; // hex0_s1_agent:rf_source_startofpacket -> hex0_s1_agent_rsp_fifo:in_startofpacket
wire hex0_s1_agent_rf_source_endofpacket; // hex0_s1_agent:rf_source_endofpacket -> hex0_s1_agent_rsp_fifo:in_endofpacket
wire hex0_s1_agent_rsp_fifo_out_valid; // hex0_s1_agent_rsp_fifo:out_valid -> hex0_s1_agent:rf_sink_valid
wire [111:0] hex0_s1_agent_rsp_fifo_out_data; // hex0_s1_agent_rsp_fifo:out_data -> hex0_s1_agent:rf_sink_data
wire hex0_s1_agent_rsp_fifo_out_ready; // hex0_s1_agent:rf_sink_ready -> hex0_s1_agent_rsp_fifo:out_ready
wire hex0_s1_agent_rsp_fifo_out_startofpacket; // hex0_s1_agent_rsp_fifo:out_startofpacket -> hex0_s1_agent:rf_sink_startofpacket
wire hex0_s1_agent_rsp_fifo_out_endofpacket; // hex0_s1_agent_rsp_fifo:out_endofpacket -> hex0_s1_agent:rf_sink_endofpacket
wire cmd_mux_013_src_valid; // cmd_mux_013:src_valid -> hex0_s1_agent:cp_valid
wire [110:0] cmd_mux_013_src_data; // cmd_mux_013:src_data -> hex0_s1_agent:cp_data
wire cmd_mux_013_src_ready; // hex0_s1_agent:cp_ready -> cmd_mux_013:src_ready
wire [22:0] cmd_mux_013_src_channel; // cmd_mux_013:src_channel -> hex0_s1_agent:cp_channel
wire cmd_mux_013_src_startofpacket; // cmd_mux_013:src_startofpacket -> hex0_s1_agent:cp_startofpacket
wire cmd_mux_013_src_endofpacket; // cmd_mux_013:src_endofpacket -> hex0_s1_agent:cp_endofpacket
wire [31:0] hex1_s1_agent_m0_readdata; // hex1_s1_translator:uav_readdata -> hex1_s1_agent:m0_readdata
wire hex1_s1_agent_m0_waitrequest; // hex1_s1_translator:uav_waitrequest -> hex1_s1_agent:m0_waitrequest
wire hex1_s1_agent_m0_debugaccess; // hex1_s1_agent:m0_debugaccess -> hex1_s1_translator:uav_debugaccess
wire [27:0] hex1_s1_agent_m0_address; // hex1_s1_agent:m0_address -> hex1_s1_translator:uav_address
wire [3:0] hex1_s1_agent_m0_byteenable; // hex1_s1_agent:m0_byteenable -> hex1_s1_translator:uav_byteenable
wire hex1_s1_agent_m0_read; // hex1_s1_agent:m0_read -> hex1_s1_translator:uav_read
wire hex1_s1_agent_m0_readdatavalid; // hex1_s1_translator:uav_readdatavalid -> hex1_s1_agent:m0_readdatavalid
wire hex1_s1_agent_m0_lock; // hex1_s1_agent:m0_lock -> hex1_s1_translator:uav_lock
wire [31:0] hex1_s1_agent_m0_writedata; // hex1_s1_agent:m0_writedata -> hex1_s1_translator:uav_writedata
wire hex1_s1_agent_m0_write; // hex1_s1_agent:m0_write -> hex1_s1_translator:uav_write
wire [2:0] hex1_s1_agent_m0_burstcount; // hex1_s1_agent:m0_burstcount -> hex1_s1_translator:uav_burstcount
wire hex1_s1_agent_rf_source_valid; // hex1_s1_agent:rf_source_valid -> hex1_s1_agent_rsp_fifo:in_valid
wire [111:0] hex1_s1_agent_rf_source_data; // hex1_s1_agent:rf_source_data -> hex1_s1_agent_rsp_fifo:in_data
wire hex1_s1_agent_rf_source_ready; // hex1_s1_agent_rsp_fifo:in_ready -> hex1_s1_agent:rf_source_ready
wire hex1_s1_agent_rf_source_startofpacket; // hex1_s1_agent:rf_source_startofpacket -> hex1_s1_agent_rsp_fifo:in_startofpacket
wire hex1_s1_agent_rf_source_endofpacket; // hex1_s1_agent:rf_source_endofpacket -> hex1_s1_agent_rsp_fifo:in_endofpacket
wire hex1_s1_agent_rsp_fifo_out_valid; // hex1_s1_agent_rsp_fifo:out_valid -> hex1_s1_agent:rf_sink_valid
wire [111:0] hex1_s1_agent_rsp_fifo_out_data; // hex1_s1_agent_rsp_fifo:out_data -> hex1_s1_agent:rf_sink_data
wire hex1_s1_agent_rsp_fifo_out_ready; // hex1_s1_agent:rf_sink_ready -> hex1_s1_agent_rsp_fifo:out_ready
wire hex1_s1_agent_rsp_fifo_out_startofpacket; // hex1_s1_agent_rsp_fifo:out_startofpacket -> hex1_s1_agent:rf_sink_startofpacket
wire hex1_s1_agent_rsp_fifo_out_endofpacket; // hex1_s1_agent_rsp_fifo:out_endofpacket -> hex1_s1_agent:rf_sink_endofpacket
wire cmd_mux_014_src_valid; // cmd_mux_014:src_valid -> hex1_s1_agent:cp_valid
wire [110:0] cmd_mux_014_src_data; // cmd_mux_014:src_data -> hex1_s1_agent:cp_data
wire cmd_mux_014_src_ready; // hex1_s1_agent:cp_ready -> cmd_mux_014:src_ready
wire [22:0] cmd_mux_014_src_channel; // cmd_mux_014:src_channel -> hex1_s1_agent:cp_channel
wire cmd_mux_014_src_startofpacket; // cmd_mux_014:src_startofpacket -> hex1_s1_agent:cp_startofpacket
wire cmd_mux_014_src_endofpacket; // cmd_mux_014:src_endofpacket -> hex1_s1_agent:cp_endofpacket
wire [31:0] hex2_s1_agent_m0_readdata; // hex2_s1_translator:uav_readdata -> hex2_s1_agent:m0_readdata
wire hex2_s1_agent_m0_waitrequest; // hex2_s1_translator:uav_waitrequest -> hex2_s1_agent:m0_waitrequest
wire hex2_s1_agent_m0_debugaccess; // hex2_s1_agent:m0_debugaccess -> hex2_s1_translator:uav_debugaccess
wire [27:0] hex2_s1_agent_m0_address; // hex2_s1_agent:m0_address -> hex2_s1_translator:uav_address
wire [3:0] hex2_s1_agent_m0_byteenable; // hex2_s1_agent:m0_byteenable -> hex2_s1_translator:uav_byteenable
wire hex2_s1_agent_m0_read; // hex2_s1_agent:m0_read -> hex2_s1_translator:uav_read
wire hex2_s1_agent_m0_readdatavalid; // hex2_s1_translator:uav_readdatavalid -> hex2_s1_agent:m0_readdatavalid
wire hex2_s1_agent_m0_lock; // hex2_s1_agent:m0_lock -> hex2_s1_translator:uav_lock
wire [31:0] hex2_s1_agent_m0_writedata; // hex2_s1_agent:m0_writedata -> hex2_s1_translator:uav_writedata
wire hex2_s1_agent_m0_write; // hex2_s1_agent:m0_write -> hex2_s1_translator:uav_write
wire [2:0] hex2_s1_agent_m0_burstcount; // hex2_s1_agent:m0_burstcount -> hex2_s1_translator:uav_burstcount
wire hex2_s1_agent_rf_source_valid; // hex2_s1_agent:rf_source_valid -> hex2_s1_agent_rsp_fifo:in_valid
wire [111:0] hex2_s1_agent_rf_source_data; // hex2_s1_agent:rf_source_data -> hex2_s1_agent_rsp_fifo:in_data
wire hex2_s1_agent_rf_source_ready; // hex2_s1_agent_rsp_fifo:in_ready -> hex2_s1_agent:rf_source_ready
wire hex2_s1_agent_rf_source_startofpacket; // hex2_s1_agent:rf_source_startofpacket -> hex2_s1_agent_rsp_fifo:in_startofpacket
wire hex2_s1_agent_rf_source_endofpacket; // hex2_s1_agent:rf_source_endofpacket -> hex2_s1_agent_rsp_fifo:in_endofpacket
wire hex2_s1_agent_rsp_fifo_out_valid; // hex2_s1_agent_rsp_fifo:out_valid -> hex2_s1_agent:rf_sink_valid
wire [111:0] hex2_s1_agent_rsp_fifo_out_data; // hex2_s1_agent_rsp_fifo:out_data -> hex2_s1_agent:rf_sink_data
wire hex2_s1_agent_rsp_fifo_out_ready; // hex2_s1_agent:rf_sink_ready -> hex2_s1_agent_rsp_fifo:out_ready
wire hex2_s1_agent_rsp_fifo_out_startofpacket; // hex2_s1_agent_rsp_fifo:out_startofpacket -> hex2_s1_agent:rf_sink_startofpacket
wire hex2_s1_agent_rsp_fifo_out_endofpacket; // hex2_s1_agent_rsp_fifo:out_endofpacket -> hex2_s1_agent:rf_sink_endofpacket
wire cmd_mux_015_src_valid; // cmd_mux_015:src_valid -> hex2_s1_agent:cp_valid
wire [110:0] cmd_mux_015_src_data; // cmd_mux_015:src_data -> hex2_s1_agent:cp_data
wire cmd_mux_015_src_ready; // hex2_s1_agent:cp_ready -> cmd_mux_015:src_ready
wire [22:0] cmd_mux_015_src_channel; // cmd_mux_015:src_channel -> hex2_s1_agent:cp_channel
wire cmd_mux_015_src_startofpacket; // cmd_mux_015:src_startofpacket -> hex2_s1_agent:cp_startofpacket
wire cmd_mux_015_src_endofpacket; // cmd_mux_015:src_endofpacket -> hex2_s1_agent:cp_endofpacket
wire [31:0] hex3_s1_agent_m0_readdata; // hex3_s1_translator:uav_readdata -> hex3_s1_agent:m0_readdata
wire hex3_s1_agent_m0_waitrequest; // hex3_s1_translator:uav_waitrequest -> hex3_s1_agent:m0_waitrequest
wire hex3_s1_agent_m0_debugaccess; // hex3_s1_agent:m0_debugaccess -> hex3_s1_translator:uav_debugaccess
wire [27:0] hex3_s1_agent_m0_address; // hex3_s1_agent:m0_address -> hex3_s1_translator:uav_address
wire [3:0] hex3_s1_agent_m0_byteenable; // hex3_s1_agent:m0_byteenable -> hex3_s1_translator:uav_byteenable
wire hex3_s1_agent_m0_read; // hex3_s1_agent:m0_read -> hex3_s1_translator:uav_read
wire hex3_s1_agent_m0_readdatavalid; // hex3_s1_translator:uav_readdatavalid -> hex3_s1_agent:m0_readdatavalid
wire hex3_s1_agent_m0_lock; // hex3_s1_agent:m0_lock -> hex3_s1_translator:uav_lock
wire [31:0] hex3_s1_agent_m0_writedata; // hex3_s1_agent:m0_writedata -> hex3_s1_translator:uav_writedata
wire hex3_s1_agent_m0_write; // hex3_s1_agent:m0_write -> hex3_s1_translator:uav_write
wire [2:0] hex3_s1_agent_m0_burstcount; // hex3_s1_agent:m0_burstcount -> hex3_s1_translator:uav_burstcount
wire hex3_s1_agent_rf_source_valid; // hex3_s1_agent:rf_source_valid -> hex3_s1_agent_rsp_fifo:in_valid
wire [111:0] hex3_s1_agent_rf_source_data; // hex3_s1_agent:rf_source_data -> hex3_s1_agent_rsp_fifo:in_data
wire hex3_s1_agent_rf_source_ready; // hex3_s1_agent_rsp_fifo:in_ready -> hex3_s1_agent:rf_source_ready
wire hex3_s1_agent_rf_source_startofpacket; // hex3_s1_agent:rf_source_startofpacket -> hex3_s1_agent_rsp_fifo:in_startofpacket
wire hex3_s1_agent_rf_source_endofpacket; // hex3_s1_agent:rf_source_endofpacket -> hex3_s1_agent_rsp_fifo:in_endofpacket
wire hex3_s1_agent_rsp_fifo_out_valid; // hex3_s1_agent_rsp_fifo:out_valid -> hex3_s1_agent:rf_sink_valid
wire [111:0] hex3_s1_agent_rsp_fifo_out_data; // hex3_s1_agent_rsp_fifo:out_data -> hex3_s1_agent:rf_sink_data
wire hex3_s1_agent_rsp_fifo_out_ready; // hex3_s1_agent:rf_sink_ready -> hex3_s1_agent_rsp_fifo:out_ready
wire hex3_s1_agent_rsp_fifo_out_startofpacket; // hex3_s1_agent_rsp_fifo:out_startofpacket -> hex3_s1_agent:rf_sink_startofpacket
wire hex3_s1_agent_rsp_fifo_out_endofpacket; // hex3_s1_agent_rsp_fifo:out_endofpacket -> hex3_s1_agent:rf_sink_endofpacket
wire cmd_mux_016_src_valid; // cmd_mux_016:src_valid -> hex3_s1_agent:cp_valid
wire [110:0] cmd_mux_016_src_data; // cmd_mux_016:src_data -> hex3_s1_agent:cp_data
wire cmd_mux_016_src_ready; // hex3_s1_agent:cp_ready -> cmd_mux_016:src_ready
wire [22:0] cmd_mux_016_src_channel; // cmd_mux_016:src_channel -> hex3_s1_agent:cp_channel
wire cmd_mux_016_src_startofpacket; // cmd_mux_016:src_startofpacket -> hex3_s1_agent:cp_startofpacket
wire cmd_mux_016_src_endofpacket; // cmd_mux_016:src_endofpacket -> hex3_s1_agent:cp_endofpacket
wire [31:0] hex4_s1_agent_m0_readdata; // hex4_s1_translator:uav_readdata -> hex4_s1_agent:m0_readdata
wire hex4_s1_agent_m0_waitrequest; // hex4_s1_translator:uav_waitrequest -> hex4_s1_agent:m0_waitrequest
wire hex4_s1_agent_m0_debugaccess; // hex4_s1_agent:m0_debugaccess -> hex4_s1_translator:uav_debugaccess
wire [27:0] hex4_s1_agent_m0_address; // hex4_s1_agent:m0_address -> hex4_s1_translator:uav_address
wire [3:0] hex4_s1_agent_m0_byteenable; // hex4_s1_agent:m0_byteenable -> hex4_s1_translator:uav_byteenable
wire hex4_s1_agent_m0_read; // hex4_s1_agent:m0_read -> hex4_s1_translator:uav_read
wire hex4_s1_agent_m0_readdatavalid; // hex4_s1_translator:uav_readdatavalid -> hex4_s1_agent:m0_readdatavalid
wire hex4_s1_agent_m0_lock; // hex4_s1_agent:m0_lock -> hex4_s1_translator:uav_lock
wire [31:0] hex4_s1_agent_m0_writedata; // hex4_s1_agent:m0_writedata -> hex4_s1_translator:uav_writedata
wire hex4_s1_agent_m0_write; // hex4_s1_agent:m0_write -> hex4_s1_translator:uav_write
wire [2:0] hex4_s1_agent_m0_burstcount; // hex4_s1_agent:m0_burstcount -> hex4_s1_translator:uav_burstcount
wire hex4_s1_agent_rf_source_valid; // hex4_s1_agent:rf_source_valid -> hex4_s1_agent_rsp_fifo:in_valid
wire [111:0] hex4_s1_agent_rf_source_data; // hex4_s1_agent:rf_source_data -> hex4_s1_agent_rsp_fifo:in_data
wire hex4_s1_agent_rf_source_ready; // hex4_s1_agent_rsp_fifo:in_ready -> hex4_s1_agent:rf_source_ready
wire hex4_s1_agent_rf_source_startofpacket; // hex4_s1_agent:rf_source_startofpacket -> hex4_s1_agent_rsp_fifo:in_startofpacket
wire hex4_s1_agent_rf_source_endofpacket; // hex4_s1_agent:rf_source_endofpacket -> hex4_s1_agent_rsp_fifo:in_endofpacket
wire hex4_s1_agent_rsp_fifo_out_valid; // hex4_s1_agent_rsp_fifo:out_valid -> hex4_s1_agent:rf_sink_valid
wire [111:0] hex4_s1_agent_rsp_fifo_out_data; // hex4_s1_agent_rsp_fifo:out_data -> hex4_s1_agent:rf_sink_data
wire hex4_s1_agent_rsp_fifo_out_ready; // hex4_s1_agent:rf_sink_ready -> hex4_s1_agent_rsp_fifo:out_ready
wire hex4_s1_agent_rsp_fifo_out_startofpacket; // hex4_s1_agent_rsp_fifo:out_startofpacket -> hex4_s1_agent:rf_sink_startofpacket
wire hex4_s1_agent_rsp_fifo_out_endofpacket; // hex4_s1_agent_rsp_fifo:out_endofpacket -> hex4_s1_agent:rf_sink_endofpacket
wire cmd_mux_017_src_valid; // cmd_mux_017:src_valid -> hex4_s1_agent:cp_valid
wire [110:0] cmd_mux_017_src_data; // cmd_mux_017:src_data -> hex4_s1_agent:cp_data
wire cmd_mux_017_src_ready; // hex4_s1_agent:cp_ready -> cmd_mux_017:src_ready
wire [22:0] cmd_mux_017_src_channel; // cmd_mux_017:src_channel -> hex4_s1_agent:cp_channel
wire cmd_mux_017_src_startofpacket; // cmd_mux_017:src_startofpacket -> hex4_s1_agent:cp_startofpacket
wire cmd_mux_017_src_endofpacket; // cmd_mux_017:src_endofpacket -> hex4_s1_agent:cp_endofpacket
wire [31:0] hex5_s1_agent_m0_readdata; // hex5_s1_translator:uav_readdata -> hex5_s1_agent:m0_readdata
wire hex5_s1_agent_m0_waitrequest; // hex5_s1_translator:uav_waitrequest -> hex5_s1_agent:m0_waitrequest
wire hex5_s1_agent_m0_debugaccess; // hex5_s1_agent:m0_debugaccess -> hex5_s1_translator:uav_debugaccess
wire [27:0] hex5_s1_agent_m0_address; // hex5_s1_agent:m0_address -> hex5_s1_translator:uav_address
wire [3:0] hex5_s1_agent_m0_byteenable; // hex5_s1_agent:m0_byteenable -> hex5_s1_translator:uav_byteenable
wire hex5_s1_agent_m0_read; // hex5_s1_agent:m0_read -> hex5_s1_translator:uav_read
wire hex5_s1_agent_m0_readdatavalid; // hex5_s1_translator:uav_readdatavalid -> hex5_s1_agent:m0_readdatavalid
wire hex5_s1_agent_m0_lock; // hex5_s1_agent:m0_lock -> hex5_s1_translator:uav_lock
wire [31:0] hex5_s1_agent_m0_writedata; // hex5_s1_agent:m0_writedata -> hex5_s1_translator:uav_writedata
wire hex5_s1_agent_m0_write; // hex5_s1_agent:m0_write -> hex5_s1_translator:uav_write
wire [2:0] hex5_s1_agent_m0_burstcount; // hex5_s1_agent:m0_burstcount -> hex5_s1_translator:uav_burstcount
wire hex5_s1_agent_rf_source_valid; // hex5_s1_agent:rf_source_valid -> hex5_s1_agent_rsp_fifo:in_valid
wire [111:0] hex5_s1_agent_rf_source_data; // hex5_s1_agent:rf_source_data -> hex5_s1_agent_rsp_fifo:in_data
wire hex5_s1_agent_rf_source_ready; // hex5_s1_agent_rsp_fifo:in_ready -> hex5_s1_agent:rf_source_ready
wire hex5_s1_agent_rf_source_startofpacket; // hex5_s1_agent:rf_source_startofpacket -> hex5_s1_agent_rsp_fifo:in_startofpacket
wire hex5_s1_agent_rf_source_endofpacket; // hex5_s1_agent:rf_source_endofpacket -> hex5_s1_agent_rsp_fifo:in_endofpacket
wire hex5_s1_agent_rsp_fifo_out_valid; // hex5_s1_agent_rsp_fifo:out_valid -> hex5_s1_agent:rf_sink_valid
wire [111:0] hex5_s1_agent_rsp_fifo_out_data; // hex5_s1_agent_rsp_fifo:out_data -> hex5_s1_agent:rf_sink_data
wire hex5_s1_agent_rsp_fifo_out_ready; // hex5_s1_agent:rf_sink_ready -> hex5_s1_agent_rsp_fifo:out_ready
wire hex5_s1_agent_rsp_fifo_out_startofpacket; // hex5_s1_agent_rsp_fifo:out_startofpacket -> hex5_s1_agent:rf_sink_startofpacket
wire hex5_s1_agent_rsp_fifo_out_endofpacket; // hex5_s1_agent_rsp_fifo:out_endofpacket -> hex5_s1_agent:rf_sink_endofpacket
wire cmd_mux_018_src_valid; // cmd_mux_018:src_valid -> hex5_s1_agent:cp_valid
wire [110:0] cmd_mux_018_src_data; // cmd_mux_018:src_data -> hex5_s1_agent:cp_data
wire cmd_mux_018_src_ready; // hex5_s1_agent:cp_ready -> cmd_mux_018:src_ready
wire [22:0] cmd_mux_018_src_channel; // cmd_mux_018:src_channel -> hex5_s1_agent:cp_channel
wire cmd_mux_018_src_startofpacket; // cmd_mux_018:src_startofpacket -> hex5_s1_agent:cp_startofpacket
wire cmd_mux_018_src_endofpacket; // cmd_mux_018:src_endofpacket -> hex5_s1_agent:cp_endofpacket
wire [31:0] hexdot_s1_agent_m0_readdata; // hexdot_s1_translator:uav_readdata -> hexdot_s1_agent:m0_readdata
wire hexdot_s1_agent_m0_waitrequest; // hexdot_s1_translator:uav_waitrequest -> hexdot_s1_agent:m0_waitrequest
wire hexdot_s1_agent_m0_debugaccess; // hexdot_s1_agent:m0_debugaccess -> hexdot_s1_translator:uav_debugaccess
wire [27:0] hexdot_s1_agent_m0_address; // hexdot_s1_agent:m0_address -> hexdot_s1_translator:uav_address
wire [3:0] hexdot_s1_agent_m0_byteenable; // hexdot_s1_agent:m0_byteenable -> hexdot_s1_translator:uav_byteenable
wire hexdot_s1_agent_m0_read; // hexdot_s1_agent:m0_read -> hexdot_s1_translator:uav_read
wire hexdot_s1_agent_m0_readdatavalid; // hexdot_s1_translator:uav_readdatavalid -> hexdot_s1_agent:m0_readdatavalid
wire hexdot_s1_agent_m0_lock; // hexdot_s1_agent:m0_lock -> hexdot_s1_translator:uav_lock
wire [31:0] hexdot_s1_agent_m0_writedata; // hexdot_s1_agent:m0_writedata -> hexdot_s1_translator:uav_writedata
wire hexdot_s1_agent_m0_write; // hexdot_s1_agent:m0_write -> hexdot_s1_translator:uav_write
wire [2:0] hexdot_s1_agent_m0_burstcount; // hexdot_s1_agent:m0_burstcount -> hexdot_s1_translator:uav_burstcount
wire hexdot_s1_agent_rf_source_valid; // hexdot_s1_agent:rf_source_valid -> hexdot_s1_agent_rsp_fifo:in_valid
wire [111:0] hexdot_s1_agent_rf_source_data; // hexdot_s1_agent:rf_source_data -> hexdot_s1_agent_rsp_fifo:in_data
wire hexdot_s1_agent_rf_source_ready; // hexdot_s1_agent_rsp_fifo:in_ready -> hexdot_s1_agent:rf_source_ready
wire hexdot_s1_agent_rf_source_startofpacket; // hexdot_s1_agent:rf_source_startofpacket -> hexdot_s1_agent_rsp_fifo:in_startofpacket
wire hexdot_s1_agent_rf_source_endofpacket; // hexdot_s1_agent:rf_source_endofpacket -> hexdot_s1_agent_rsp_fifo:in_endofpacket
wire hexdot_s1_agent_rsp_fifo_out_valid; // hexdot_s1_agent_rsp_fifo:out_valid -> hexdot_s1_agent:rf_sink_valid
wire [111:0] hexdot_s1_agent_rsp_fifo_out_data; // hexdot_s1_agent_rsp_fifo:out_data -> hexdot_s1_agent:rf_sink_data
wire hexdot_s1_agent_rsp_fifo_out_ready; // hexdot_s1_agent:rf_sink_ready -> hexdot_s1_agent_rsp_fifo:out_ready
wire hexdot_s1_agent_rsp_fifo_out_startofpacket; // hexdot_s1_agent_rsp_fifo:out_startofpacket -> hexdot_s1_agent:rf_sink_startofpacket
wire hexdot_s1_agent_rsp_fifo_out_endofpacket; // hexdot_s1_agent_rsp_fifo:out_endofpacket -> hexdot_s1_agent:rf_sink_endofpacket
wire cmd_mux_019_src_valid; // cmd_mux_019:src_valid -> hexdot_s1_agent:cp_valid
wire [110:0] cmd_mux_019_src_data; // cmd_mux_019:src_data -> hexdot_s1_agent:cp_data
wire cmd_mux_019_src_ready; // hexdot_s1_agent:cp_ready -> cmd_mux_019:src_ready
wire [22:0] cmd_mux_019_src_channel; // cmd_mux_019:src_channel -> hexdot_s1_agent:cp_channel
wire cmd_mux_019_src_startofpacket; // cmd_mux_019:src_startofpacket -> hexdot_s1_agent:cp_startofpacket
wire cmd_mux_019_src_endofpacket; // cmd_mux_019:src_endofpacket -> hexdot_s1_agent:cp_endofpacket
wire [31:0] spi_sync_s1_agent_m0_readdata; // spi_sync_s1_translator:uav_readdata -> spi_sync_s1_agent:m0_readdata
wire spi_sync_s1_agent_m0_waitrequest; // spi_sync_s1_translator:uav_waitrequest -> spi_sync_s1_agent:m0_waitrequest
wire spi_sync_s1_agent_m0_debugaccess; // spi_sync_s1_agent:m0_debugaccess -> spi_sync_s1_translator:uav_debugaccess
wire [27:0] spi_sync_s1_agent_m0_address; // spi_sync_s1_agent:m0_address -> spi_sync_s1_translator:uav_address
wire [3:0] spi_sync_s1_agent_m0_byteenable; // spi_sync_s1_agent:m0_byteenable -> spi_sync_s1_translator:uav_byteenable
wire spi_sync_s1_agent_m0_read; // spi_sync_s1_agent:m0_read -> spi_sync_s1_translator:uav_read
wire spi_sync_s1_agent_m0_readdatavalid; // spi_sync_s1_translator:uav_readdatavalid -> spi_sync_s1_agent:m0_readdatavalid
wire spi_sync_s1_agent_m0_lock; // spi_sync_s1_agent:m0_lock -> spi_sync_s1_translator:uav_lock
wire [31:0] spi_sync_s1_agent_m0_writedata; // spi_sync_s1_agent:m0_writedata -> spi_sync_s1_translator:uav_writedata
wire spi_sync_s1_agent_m0_write; // spi_sync_s1_agent:m0_write -> spi_sync_s1_translator:uav_write
wire [2:0] spi_sync_s1_agent_m0_burstcount; // spi_sync_s1_agent:m0_burstcount -> spi_sync_s1_translator:uav_burstcount
wire spi_sync_s1_agent_rf_source_valid; // spi_sync_s1_agent:rf_source_valid -> spi_sync_s1_agent_rsp_fifo:in_valid
wire [111:0] spi_sync_s1_agent_rf_source_data; // spi_sync_s1_agent:rf_source_data -> spi_sync_s1_agent_rsp_fifo:in_data
wire spi_sync_s1_agent_rf_source_ready; // spi_sync_s1_agent_rsp_fifo:in_ready -> spi_sync_s1_agent:rf_source_ready
wire spi_sync_s1_agent_rf_source_startofpacket; // spi_sync_s1_agent:rf_source_startofpacket -> spi_sync_s1_agent_rsp_fifo:in_startofpacket
wire spi_sync_s1_agent_rf_source_endofpacket; // spi_sync_s1_agent:rf_source_endofpacket -> spi_sync_s1_agent_rsp_fifo:in_endofpacket
wire spi_sync_s1_agent_rsp_fifo_out_valid; // spi_sync_s1_agent_rsp_fifo:out_valid -> spi_sync_s1_agent:rf_sink_valid
wire [111:0] spi_sync_s1_agent_rsp_fifo_out_data; // spi_sync_s1_agent_rsp_fifo:out_data -> spi_sync_s1_agent:rf_sink_data
wire spi_sync_s1_agent_rsp_fifo_out_ready; // spi_sync_s1_agent:rf_sink_ready -> spi_sync_s1_agent_rsp_fifo:out_ready
wire spi_sync_s1_agent_rsp_fifo_out_startofpacket; // spi_sync_s1_agent_rsp_fifo:out_startofpacket -> spi_sync_s1_agent:rf_sink_startofpacket
wire spi_sync_s1_agent_rsp_fifo_out_endofpacket; // spi_sync_s1_agent_rsp_fifo:out_endofpacket -> spi_sync_s1_agent:rf_sink_endofpacket
wire cmd_mux_020_src_valid; // cmd_mux_020:src_valid -> spi_sync_s1_agent:cp_valid
wire [110:0] cmd_mux_020_src_data; // cmd_mux_020:src_data -> spi_sync_s1_agent:cp_data
wire cmd_mux_020_src_ready; // spi_sync_s1_agent:cp_ready -> cmd_mux_020:src_ready
wire [22:0] cmd_mux_020_src_channel; // cmd_mux_020:src_channel -> spi_sync_s1_agent:cp_channel
wire cmd_mux_020_src_startofpacket; // cmd_mux_020:src_startofpacket -> spi_sync_s1_agent:cp_startofpacket
wire cmd_mux_020_src_endofpacket; // cmd_mux_020:src_endofpacket -> spi_sync_s1_agent:cp_endofpacket
wire [31:0] extra_leds_s1_agent_m0_readdata; // extra_leds_s1_translator:uav_readdata -> extra_leds_s1_agent:m0_readdata
wire extra_leds_s1_agent_m0_waitrequest; // extra_leds_s1_translator:uav_waitrequest -> extra_leds_s1_agent:m0_waitrequest
wire extra_leds_s1_agent_m0_debugaccess; // extra_leds_s1_agent:m0_debugaccess -> extra_leds_s1_translator:uav_debugaccess
wire [27:0] extra_leds_s1_agent_m0_address; // extra_leds_s1_agent:m0_address -> extra_leds_s1_translator:uav_address
wire [3:0] extra_leds_s1_agent_m0_byteenable; // extra_leds_s1_agent:m0_byteenable -> extra_leds_s1_translator:uav_byteenable
wire extra_leds_s1_agent_m0_read; // extra_leds_s1_agent:m0_read -> extra_leds_s1_translator:uav_read
wire extra_leds_s1_agent_m0_readdatavalid; // extra_leds_s1_translator:uav_readdatavalid -> extra_leds_s1_agent:m0_readdatavalid
wire extra_leds_s1_agent_m0_lock; // extra_leds_s1_agent:m0_lock -> extra_leds_s1_translator:uav_lock
wire [31:0] extra_leds_s1_agent_m0_writedata; // extra_leds_s1_agent:m0_writedata -> extra_leds_s1_translator:uav_writedata
wire extra_leds_s1_agent_m0_write; // extra_leds_s1_agent:m0_write -> extra_leds_s1_translator:uav_write
wire [2:0] extra_leds_s1_agent_m0_burstcount; // extra_leds_s1_agent:m0_burstcount -> extra_leds_s1_translator:uav_burstcount
wire extra_leds_s1_agent_rf_source_valid; // extra_leds_s1_agent:rf_source_valid -> extra_leds_s1_agent_rsp_fifo:in_valid
wire [111:0] extra_leds_s1_agent_rf_source_data; // extra_leds_s1_agent:rf_source_data -> extra_leds_s1_agent_rsp_fifo:in_data
wire extra_leds_s1_agent_rf_source_ready; // extra_leds_s1_agent_rsp_fifo:in_ready -> extra_leds_s1_agent:rf_source_ready
wire extra_leds_s1_agent_rf_source_startofpacket; // extra_leds_s1_agent:rf_source_startofpacket -> extra_leds_s1_agent_rsp_fifo:in_startofpacket
wire extra_leds_s1_agent_rf_source_endofpacket; // extra_leds_s1_agent:rf_source_endofpacket -> extra_leds_s1_agent_rsp_fifo:in_endofpacket
wire extra_leds_s1_agent_rsp_fifo_out_valid; // extra_leds_s1_agent_rsp_fifo:out_valid -> extra_leds_s1_agent:rf_sink_valid
wire [111:0] extra_leds_s1_agent_rsp_fifo_out_data; // extra_leds_s1_agent_rsp_fifo:out_data -> extra_leds_s1_agent:rf_sink_data
wire extra_leds_s1_agent_rsp_fifo_out_ready; // extra_leds_s1_agent:rf_sink_ready -> extra_leds_s1_agent_rsp_fifo:out_ready
wire extra_leds_s1_agent_rsp_fifo_out_startofpacket; // extra_leds_s1_agent_rsp_fifo:out_startofpacket -> extra_leds_s1_agent:rf_sink_startofpacket
wire extra_leds_s1_agent_rsp_fifo_out_endofpacket; // extra_leds_s1_agent_rsp_fifo:out_endofpacket -> extra_leds_s1_agent:rf_sink_endofpacket
wire cmd_mux_021_src_valid; // cmd_mux_021:src_valid -> extra_leds_s1_agent:cp_valid
wire [110:0] cmd_mux_021_src_data; // cmd_mux_021:src_data -> extra_leds_s1_agent:cp_data
wire cmd_mux_021_src_ready; // extra_leds_s1_agent:cp_ready -> cmd_mux_021:src_ready
wire [22:0] cmd_mux_021_src_channel; // cmd_mux_021:src_channel -> extra_leds_s1_agent:cp_channel
wire cmd_mux_021_src_startofpacket; // cmd_mux_021:src_startofpacket -> extra_leds_s1_agent:cp_startofpacket
wire cmd_mux_021_src_endofpacket; // cmd_mux_021:src_endofpacket -> extra_leds_s1_agent:cp_endofpacket
wire [31:0] spi_stm32_spi_control_port_agent_m0_readdata; // spi_stm32_spi_control_port_translator:uav_readdata -> spi_stm32_spi_control_port_agent:m0_readdata
wire spi_stm32_spi_control_port_agent_m0_waitrequest; // spi_stm32_spi_control_port_translator:uav_waitrequest -> spi_stm32_spi_control_port_agent:m0_waitrequest
wire spi_stm32_spi_control_port_agent_m0_debugaccess; // spi_stm32_spi_control_port_agent:m0_debugaccess -> spi_stm32_spi_control_port_translator:uav_debugaccess
wire [27:0] spi_stm32_spi_control_port_agent_m0_address; // spi_stm32_spi_control_port_agent:m0_address -> spi_stm32_spi_control_port_translator:uav_address
wire [3:0] spi_stm32_spi_control_port_agent_m0_byteenable; // spi_stm32_spi_control_port_agent:m0_byteenable -> spi_stm32_spi_control_port_translator:uav_byteenable
wire spi_stm32_spi_control_port_agent_m0_read; // spi_stm32_spi_control_port_agent:m0_read -> spi_stm32_spi_control_port_translator:uav_read
wire spi_stm32_spi_control_port_agent_m0_readdatavalid; // spi_stm32_spi_control_port_translator:uav_readdatavalid -> spi_stm32_spi_control_port_agent:m0_readdatavalid
wire spi_stm32_spi_control_port_agent_m0_lock; // spi_stm32_spi_control_port_agent:m0_lock -> spi_stm32_spi_control_port_translator:uav_lock
wire [31:0] spi_stm32_spi_control_port_agent_m0_writedata; // spi_stm32_spi_control_port_agent:m0_writedata -> spi_stm32_spi_control_port_translator:uav_writedata
wire spi_stm32_spi_control_port_agent_m0_write; // spi_stm32_spi_control_port_agent:m0_write -> spi_stm32_spi_control_port_translator:uav_write
wire [2:0] spi_stm32_spi_control_port_agent_m0_burstcount; // spi_stm32_spi_control_port_agent:m0_burstcount -> spi_stm32_spi_control_port_translator:uav_burstcount
wire spi_stm32_spi_control_port_agent_rf_source_valid; // spi_stm32_spi_control_port_agent:rf_source_valid -> spi_stm32_spi_control_port_agent_rsp_fifo:in_valid
wire [111:0] spi_stm32_spi_control_port_agent_rf_source_data; // spi_stm32_spi_control_port_agent:rf_source_data -> spi_stm32_spi_control_port_agent_rsp_fifo:in_data
wire spi_stm32_spi_control_port_agent_rf_source_ready; // spi_stm32_spi_control_port_agent_rsp_fifo:in_ready -> spi_stm32_spi_control_port_agent:rf_source_ready
wire spi_stm32_spi_control_port_agent_rf_source_startofpacket; // spi_stm32_spi_control_port_agent:rf_source_startofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_startofpacket
wire spi_stm32_spi_control_port_agent_rf_source_endofpacket; // spi_stm32_spi_control_port_agent:rf_source_endofpacket -> spi_stm32_spi_control_port_agent_rsp_fifo:in_endofpacket
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_valid; // spi_stm32_spi_control_port_agent_rsp_fifo:out_valid -> spi_stm32_spi_control_port_agent:rf_sink_valid
wire [111:0] spi_stm32_spi_control_port_agent_rsp_fifo_out_data; // spi_stm32_spi_control_port_agent_rsp_fifo:out_data -> spi_stm32_spi_control_port_agent:rf_sink_data
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_ready; // spi_stm32_spi_control_port_agent:rf_sink_ready -> spi_stm32_spi_control_port_agent_rsp_fifo:out_ready
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket; // spi_stm32_spi_control_port_agent_rsp_fifo:out_startofpacket -> spi_stm32_spi_control_port_agent:rf_sink_startofpacket
wire spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket; // spi_stm32_spi_control_port_agent_rsp_fifo:out_endofpacket -> spi_stm32_spi_control_port_agent:rf_sink_endofpacket
wire cmd_mux_022_src_valid; // cmd_mux_022:src_valid -> spi_stm32_spi_control_port_agent:cp_valid
wire [110:0] cmd_mux_022_src_data; // cmd_mux_022:src_data -> spi_stm32_spi_control_port_agent:cp_data
wire cmd_mux_022_src_ready; // spi_stm32_spi_control_port_agent:cp_ready -> cmd_mux_022:src_ready
wire [22:0] cmd_mux_022_src_channel; // cmd_mux_022:src_channel -> spi_stm32_spi_control_port_agent:cp_channel
wire cmd_mux_022_src_startofpacket; // cmd_mux_022:src_startofpacket -> spi_stm32_spi_control_port_agent:cp_startofpacket
wire cmd_mux_022_src_endofpacket; // cmd_mux_022:src_endofpacket -> spi_stm32_spi_control_port_agent:cp_endofpacket
wire abus_slave_0_avalon_master_agent_cp_valid; // abus_slave_0_avalon_master_agent:cp_valid -> router:sink_valid
wire [92:0] abus_slave_0_avalon_master_agent_cp_data; // abus_slave_0_avalon_master_agent:cp_data -> router:sink_data
wire abus_slave_0_avalon_master_agent_cp_ready; // router:sink_ready -> abus_slave_0_avalon_master_agent:cp_ready
wire abus_slave_0_avalon_master_agent_cp_startofpacket; // abus_slave_0_avalon_master_agent:cp_startofpacket -> router:sink_startofpacket
wire abus_slave_0_avalon_master_agent_cp_endofpacket; // abus_slave_0_avalon_master_agent:cp_endofpacket -> router:sink_endofpacket
wire nios2_gen2_0_data_master_agent_cp_valid; // nios2_gen2_0_data_master_agent:cp_valid -> router_001:sink_valid
wire [110:0] nios2_gen2_0_data_master_agent_cp_data; // nios2_gen2_0_data_master_agent:cp_data -> router_001:sink_data
wire nios2_gen2_0_data_master_agent_cp_ready; // router_001:sink_ready -> nios2_gen2_0_data_master_agent:cp_ready
wire nios2_gen2_0_data_master_agent_cp_startofpacket; // nios2_gen2_0_data_master_agent:cp_startofpacket -> router_001:sink_startofpacket
wire nios2_gen2_0_data_master_agent_cp_endofpacket; // nios2_gen2_0_data_master_agent:cp_endofpacket -> router_001:sink_endofpacket
wire router_001_src_valid; // router_001:src_valid -> cmd_demux_001:sink_valid
wire [110:0] router_001_src_data; // router_001:src_data -> cmd_demux_001:sink_data
wire router_001_src_ready; // cmd_demux_001:sink_ready -> router_001:src_ready
wire [22:0] router_001_src_channel; // router_001:src_channel -> cmd_demux_001:sink_channel
wire router_001_src_startofpacket; // router_001:src_startofpacket -> cmd_demux_001:sink_startofpacket
wire router_001_src_endofpacket; // router_001:src_endofpacket -> cmd_demux_001:sink_endofpacket
wire nios2_gen2_0_instruction_master_agent_cp_valid; // nios2_gen2_0_instruction_master_agent:cp_valid -> router_002:sink_valid
wire [110:0] nios2_gen2_0_instruction_master_agent_cp_data; // nios2_gen2_0_instruction_master_agent:cp_data -> router_002:sink_data
wire nios2_gen2_0_instruction_master_agent_cp_ready; // router_002:sink_ready -> nios2_gen2_0_instruction_master_agent:cp_ready
wire nios2_gen2_0_instruction_master_agent_cp_startofpacket; // nios2_gen2_0_instruction_master_agent:cp_startofpacket -> router_002:sink_startofpacket
wire nios2_gen2_0_instruction_master_agent_cp_endofpacket; // nios2_gen2_0_instruction_master_agent:cp_endofpacket -> router_002:sink_endofpacket
wire router_002_src_valid; // router_002:src_valid -> cmd_demux_002:sink_valid
wire [110:0] router_002_src_data; // router_002:src_data -> cmd_demux_002:sink_data
wire router_002_src_ready; // cmd_demux_002:sink_ready -> router_002:src_ready
wire [22:0] router_002_src_channel; // router_002:src_channel -> cmd_demux_002:sink_channel
wire router_002_src_startofpacket; // router_002:src_startofpacket -> cmd_demux_002:sink_startofpacket
wire router_002_src_endofpacket; // router_002:src_endofpacket -> cmd_demux_002:sink_endofpacket
wire external_sdram_controller_s1_agent_rp_valid; // external_sdram_controller_s1_agent:rp_valid -> router_003:sink_valid
wire [92:0] external_sdram_controller_s1_agent_rp_data; // external_sdram_controller_s1_agent:rp_data -> router_003:sink_data
wire external_sdram_controller_s1_agent_rp_ready; // router_003:sink_ready -> external_sdram_controller_s1_agent:rp_ready
wire external_sdram_controller_s1_agent_rp_startofpacket; // external_sdram_controller_s1_agent:rp_startofpacket -> router_003:sink_startofpacket
wire external_sdram_controller_s1_agent_rp_endofpacket; // external_sdram_controller_s1_agent:rp_endofpacket -> router_003:sink_endofpacket
wire router_003_src_valid; // router_003:src_valid -> rsp_demux:sink_valid
wire [92:0] router_003_src_data; // router_003:src_data -> rsp_demux:sink_data
wire router_003_src_ready; // rsp_demux:sink_ready -> router_003:src_ready
wire [22:0] router_003_src_channel; // router_003:src_channel -> rsp_demux:sink_channel
wire router_003_src_startofpacket; // router_003:src_startofpacket -> rsp_demux:sink_startofpacket
wire router_003_src_endofpacket; // router_003:src_endofpacket -> rsp_demux:sink_endofpacket
wire onchip_memory2_1_s1_agent_rp_valid; // onchip_memory2_1_s1_agent:rp_valid -> router_004:sink_valid
wire [110:0] onchip_memory2_1_s1_agent_rp_data; // onchip_memory2_1_s1_agent:rp_data -> router_004:sink_data
wire onchip_memory2_1_s1_agent_rp_ready; // router_004:sink_ready -> onchip_memory2_1_s1_agent:rp_ready
wire onchip_memory2_1_s1_agent_rp_startofpacket; // onchip_memory2_1_s1_agent:rp_startofpacket -> router_004:sink_startofpacket
wire onchip_memory2_1_s1_agent_rp_endofpacket; // onchip_memory2_1_s1_agent:rp_endofpacket -> router_004:sink_endofpacket
wire router_004_src_valid; // router_004:src_valid -> rsp_demux_001:sink_valid
wire [110:0] router_004_src_data; // router_004:src_data -> rsp_demux_001:sink_data
wire router_004_src_ready; // rsp_demux_001:sink_ready -> router_004:src_ready
wire [22:0] router_004_src_channel; // router_004:src_channel -> rsp_demux_001:sink_channel
wire router_004_src_startofpacket; // router_004:src_startofpacket -> rsp_demux_001:sink_startofpacket
wire router_004_src_endofpacket; // router_004:src_endofpacket -> rsp_demux_001:sink_endofpacket
wire abus_slave_0_avalon_nios_agent_rp_valid; // abus_slave_0_avalon_nios_agent:rp_valid -> router_005:sink_valid
wire [110:0] abus_slave_0_avalon_nios_agent_rp_data; // abus_slave_0_avalon_nios_agent:rp_data -> router_005:sink_data
wire abus_slave_0_avalon_nios_agent_rp_ready; // router_005:sink_ready -> abus_slave_0_avalon_nios_agent:rp_ready
wire abus_slave_0_avalon_nios_agent_rp_startofpacket; // abus_slave_0_avalon_nios_agent:rp_startofpacket -> router_005:sink_startofpacket
wire abus_slave_0_avalon_nios_agent_rp_endofpacket; // abus_slave_0_avalon_nios_agent:rp_endofpacket -> router_005:sink_endofpacket
wire router_005_src_valid; // router_005:src_valid -> rsp_demux_002:sink_valid
wire [110:0] router_005_src_data; // router_005:src_data -> rsp_demux_002:sink_data
wire router_005_src_ready; // rsp_demux_002:sink_ready -> router_005:src_ready
wire [22:0] router_005_src_channel; // router_005:src_channel -> rsp_demux_002:sink_channel
wire router_005_src_startofpacket; // router_005:src_startofpacket -> rsp_demux_002:sink_startofpacket
wire router_005_src_endofpacket; // router_005:src_endofpacket -> rsp_demux_002:sink_endofpacket
wire abus_demux_0_avalon_nios_agent_rp_valid; // abus_demux_0_avalon_nios_agent:rp_valid -> router_006:sink_valid
wire [110:0] abus_demux_0_avalon_nios_agent_rp_data; // abus_demux_0_avalon_nios_agent:rp_data -> router_006:sink_data
wire abus_demux_0_avalon_nios_agent_rp_ready; // router_006:sink_ready -> abus_demux_0_avalon_nios_agent:rp_ready
wire abus_demux_0_avalon_nios_agent_rp_startofpacket; // abus_demux_0_avalon_nios_agent:rp_startofpacket -> router_006:sink_startofpacket
wire abus_demux_0_avalon_nios_agent_rp_endofpacket; // abus_demux_0_avalon_nios_agent:rp_endofpacket -> router_006:sink_endofpacket
wire router_006_src_valid; // router_006:src_valid -> rsp_demux_003:sink_valid
wire [110:0] router_006_src_data; // router_006:src_data -> rsp_demux_003:sink_data
wire router_006_src_ready; // rsp_demux_003:sink_ready -> router_006:src_ready
wire [22:0] router_006_src_channel; // router_006:src_channel -> rsp_demux_003:sink_channel
wire router_006_src_startofpacket; // router_006:src_startofpacket -> rsp_demux_003:sink_startofpacket
wire router_006_src_endofpacket; // router_006:src_endofpacket -> rsp_demux_003:sink_endofpacket
wire performance_counter_0_control_slave_agent_rp_valid; // performance_counter_0_control_slave_agent:rp_valid -> router_007:sink_valid
wire [110:0] performance_counter_0_control_slave_agent_rp_data; // performance_counter_0_control_slave_agent:rp_data -> router_007:sink_data
wire performance_counter_0_control_slave_agent_rp_ready; // router_007:sink_ready -> performance_counter_0_control_slave_agent:rp_ready
wire performance_counter_0_control_slave_agent_rp_startofpacket; // performance_counter_0_control_slave_agent:rp_startofpacket -> router_007:sink_startofpacket
wire performance_counter_0_control_slave_agent_rp_endofpacket; // performance_counter_0_control_slave_agent:rp_endofpacket -> router_007:sink_endofpacket
wire router_007_src_valid; // router_007:src_valid -> rsp_demux_004:sink_valid
wire [110:0] router_007_src_data; // router_007:src_data -> rsp_demux_004:sink_data
wire router_007_src_ready; // rsp_demux_004:sink_ready -> router_007:src_ready
wire [22:0] router_007_src_channel; // router_007:src_channel -> rsp_demux_004:sink_channel
wire router_007_src_startofpacket; // router_007:src_startofpacket -> rsp_demux_004:sink_startofpacket
wire router_007_src_endofpacket; // router_007:src_endofpacket -> rsp_demux_004:sink_endofpacket
wire onchip_flash_0_csr_agent_rp_valid; // onchip_flash_0_csr_agent:rp_valid -> router_008:sink_valid
wire [110:0] onchip_flash_0_csr_agent_rp_data; // onchip_flash_0_csr_agent:rp_data -> router_008:sink_data
wire onchip_flash_0_csr_agent_rp_ready; // router_008:sink_ready -> onchip_flash_0_csr_agent:rp_ready
wire onchip_flash_0_csr_agent_rp_startofpacket; // onchip_flash_0_csr_agent:rp_startofpacket -> router_008:sink_startofpacket
wire onchip_flash_0_csr_agent_rp_endofpacket; // onchip_flash_0_csr_agent:rp_endofpacket -> router_008:sink_endofpacket
wire router_008_src_valid; // router_008:src_valid -> rsp_demux_005:sink_valid
wire [110:0] router_008_src_data; // router_008:src_data -> rsp_demux_005:sink_data
wire router_008_src_ready; // rsp_demux_005:sink_ready -> router_008:src_ready
wire [22:0] router_008_src_channel; // router_008:src_channel -> rsp_demux_005:sink_channel
wire router_008_src_startofpacket; // router_008:src_startofpacket -> rsp_demux_005:sink_startofpacket
wire router_008_src_endofpacket; // router_008:src_endofpacket -> rsp_demux_005:sink_endofpacket
wire onchip_flash_0_data_agent_rp_valid; // onchip_flash_0_data_agent:rp_valid -> router_009:sink_valid
wire [110:0] onchip_flash_0_data_agent_rp_data; // onchip_flash_0_data_agent:rp_data -> router_009:sink_data
wire onchip_flash_0_data_agent_rp_ready; // router_009:sink_ready -> onchip_flash_0_data_agent:rp_ready
wire onchip_flash_0_data_agent_rp_startofpacket; // onchip_flash_0_data_agent:rp_startofpacket -> router_009:sink_startofpacket
wire onchip_flash_0_data_agent_rp_endofpacket; // onchip_flash_0_data_agent:rp_endofpacket -> router_009:sink_endofpacket
wire router_009_src_valid; // router_009:src_valid -> rsp_demux_006:sink_valid
wire [110:0] router_009_src_data; // router_009:src_data -> rsp_demux_006:sink_data
wire router_009_src_ready; // rsp_demux_006:sink_ready -> router_009:src_ready
wire [22:0] router_009_src_channel; // router_009:src_channel -> rsp_demux_006:sink_channel
wire router_009_src_startofpacket; // router_009:src_startofpacket -> rsp_demux_006:sink_startofpacket
wire router_009_src_endofpacket; // router_009:src_endofpacket -> rsp_demux_006:sink_endofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_valid; // nios2_gen2_0_debug_mem_slave_agent:rp_valid -> router_010:sink_valid
wire [110:0] nios2_gen2_0_debug_mem_slave_agent_rp_data; // nios2_gen2_0_debug_mem_slave_agent:rp_data -> router_010:sink_data
wire nios2_gen2_0_debug_mem_slave_agent_rp_ready; // router_010:sink_ready -> nios2_gen2_0_debug_mem_slave_agent:rp_ready
wire nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_startofpacket -> router_010:sink_startofpacket
wire nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket; // nios2_gen2_0_debug_mem_slave_agent:rp_endofpacket -> router_010:sink_endofpacket
wire router_010_src_valid; // router_010:src_valid -> rsp_demux_007:sink_valid
wire [110:0] router_010_src_data; // router_010:src_data -> rsp_demux_007:sink_data
wire router_010_src_ready; // rsp_demux_007:sink_ready -> router_010:src_ready
wire [22:0] router_010_src_channel; // router_010:src_channel -> rsp_demux_007:sink_channel
wire router_010_src_startofpacket; // router_010:src_startofpacket -> rsp_demux_007:sink_startofpacket
wire router_010_src_endofpacket; // router_010:src_endofpacket -> rsp_demux_007:sink_endofpacket
wire altpll_0_pll_slave_agent_rp_valid; // altpll_0_pll_slave_agent:rp_valid -> router_011:sink_valid
wire [110:0] altpll_0_pll_slave_agent_rp_data; // altpll_0_pll_slave_agent:rp_data -> router_011:sink_data
wire altpll_0_pll_slave_agent_rp_ready; // router_011:sink_ready -> altpll_0_pll_slave_agent:rp_ready
wire altpll_0_pll_slave_agent_rp_startofpacket; // altpll_0_pll_slave_agent:rp_startofpacket -> router_011:sink_startofpacket
wire altpll_0_pll_slave_agent_rp_endofpacket; // altpll_0_pll_slave_agent:rp_endofpacket -> router_011:sink_endofpacket
wire router_011_src_valid; // router_011:src_valid -> rsp_demux_008:sink_valid
wire [110:0] router_011_src_data; // router_011:src_data -> rsp_demux_008:sink_data
wire router_011_src_ready; // rsp_demux_008:sink_ready -> router_011:src_ready
wire [22:0] router_011_src_channel; // router_011:src_channel -> rsp_demux_008:sink_channel
wire router_011_src_startofpacket; // router_011:src_startofpacket -> rsp_demux_008:sink_startofpacket
wire router_011_src_endofpacket; // router_011:src_endofpacket -> rsp_demux_008:sink_endofpacket
wire onchip_memory2_0_s1_agent_rp_valid; // onchip_memory2_0_s1_agent:rp_valid -> router_012:sink_valid
wire [110:0] onchip_memory2_0_s1_agent_rp_data; // onchip_memory2_0_s1_agent:rp_data -> router_012:sink_data
wire onchip_memory2_0_s1_agent_rp_ready; // router_012:sink_ready -> onchip_memory2_0_s1_agent:rp_ready
wire onchip_memory2_0_s1_agent_rp_startofpacket; // onchip_memory2_0_s1_agent:rp_startofpacket -> router_012:sink_startofpacket
wire onchip_memory2_0_s1_agent_rp_endofpacket; // onchip_memory2_0_s1_agent:rp_endofpacket -> router_012:sink_endofpacket
wire router_012_src_valid; // router_012:src_valid -> rsp_demux_009:sink_valid
wire [110:0] router_012_src_data; // router_012:src_data -> rsp_demux_009:sink_data
wire router_012_src_ready; // rsp_demux_009:sink_ready -> router_012:src_ready
wire [22:0] router_012_src_channel; // router_012:src_channel -> rsp_demux_009:sink_channel
wire router_012_src_startofpacket; // router_012:src_startofpacket -> rsp_demux_009:sink_startofpacket
wire router_012_src_endofpacket; // router_012:src_endofpacket -> rsp_demux_009:sink_endofpacket
wire switches_s1_agent_rp_valid; // switches_s1_agent:rp_valid -> router_013:sink_valid
wire [110:0] switches_s1_agent_rp_data; // switches_s1_agent:rp_data -> router_013:sink_data
wire switches_s1_agent_rp_ready; // router_013:sink_ready -> switches_s1_agent:rp_ready
wire switches_s1_agent_rp_startofpacket; // switches_s1_agent:rp_startofpacket -> router_013:sink_startofpacket
wire switches_s1_agent_rp_endofpacket; // switches_s1_agent:rp_endofpacket -> router_013:sink_endofpacket
wire router_013_src_valid; // router_013:src_valid -> rsp_demux_010:sink_valid
wire [110:0] router_013_src_data; // router_013:src_data -> rsp_demux_010:sink_data
wire router_013_src_ready; // rsp_demux_010:sink_ready -> router_013:src_ready
wire [22:0] router_013_src_channel; // router_013:src_channel -> rsp_demux_010:sink_channel
wire router_013_src_startofpacket; // router_013:src_startofpacket -> rsp_demux_010:sink_startofpacket
wire router_013_src_endofpacket; // router_013:src_endofpacket -> rsp_demux_010:sink_endofpacket
wire leds_s1_agent_rp_valid; // leds_s1_agent:rp_valid -> router_014:sink_valid
wire [110:0] leds_s1_agent_rp_data; // leds_s1_agent:rp_data -> router_014:sink_data
wire leds_s1_agent_rp_ready; // router_014:sink_ready -> leds_s1_agent:rp_ready
wire leds_s1_agent_rp_startofpacket; // leds_s1_agent:rp_startofpacket -> router_014:sink_startofpacket
wire leds_s1_agent_rp_endofpacket; // leds_s1_agent:rp_endofpacket -> router_014:sink_endofpacket
wire router_014_src_valid; // router_014:src_valid -> rsp_demux_011:sink_valid
wire [110:0] router_014_src_data; // router_014:src_data -> rsp_demux_011:sink_data
wire router_014_src_ready; // rsp_demux_011:sink_ready -> router_014:src_ready
wire [22:0] router_014_src_channel; // router_014:src_channel -> rsp_demux_011:sink_channel
wire router_014_src_startofpacket; // router_014:src_startofpacket -> rsp_demux_011:sink_startofpacket
wire router_014_src_endofpacket; // router_014:src_endofpacket -> rsp_demux_011:sink_endofpacket
wire uart_0_s1_agent_rp_valid; // uart_0_s1_agent:rp_valid -> router_015:sink_valid
wire [110:0] uart_0_s1_agent_rp_data; // uart_0_s1_agent:rp_data -> router_015:sink_data
wire uart_0_s1_agent_rp_ready; // router_015:sink_ready -> uart_0_s1_agent:rp_ready
wire uart_0_s1_agent_rp_startofpacket; // uart_0_s1_agent:rp_startofpacket -> router_015:sink_startofpacket
wire uart_0_s1_agent_rp_endofpacket; // uart_0_s1_agent:rp_endofpacket -> router_015:sink_endofpacket
wire router_015_src_valid; // router_015:src_valid -> rsp_demux_012:sink_valid
wire [110:0] router_015_src_data; // router_015:src_data -> rsp_demux_012:sink_data
wire router_015_src_ready; // rsp_demux_012:sink_ready -> router_015:src_ready
wire [22:0] router_015_src_channel; // router_015:src_channel -> rsp_demux_012:sink_channel
wire router_015_src_startofpacket; // router_015:src_startofpacket -> rsp_demux_012:sink_startofpacket
wire router_015_src_endofpacket; // router_015:src_endofpacket -> rsp_demux_012:sink_endofpacket
wire hex0_s1_agent_rp_valid; // hex0_s1_agent:rp_valid -> router_016:sink_valid
wire [110:0] hex0_s1_agent_rp_data; // hex0_s1_agent:rp_data -> router_016:sink_data
wire hex0_s1_agent_rp_ready; // router_016:sink_ready -> hex0_s1_agent:rp_ready
wire hex0_s1_agent_rp_startofpacket; // hex0_s1_agent:rp_startofpacket -> router_016:sink_startofpacket
wire hex0_s1_agent_rp_endofpacket; // hex0_s1_agent:rp_endofpacket -> router_016:sink_endofpacket
wire router_016_src_valid; // router_016:src_valid -> rsp_demux_013:sink_valid
wire [110:0] router_016_src_data; // router_016:src_data -> rsp_demux_013:sink_data
wire router_016_src_ready; // rsp_demux_013:sink_ready -> router_016:src_ready
wire [22:0] router_016_src_channel; // router_016:src_channel -> rsp_demux_013:sink_channel
wire router_016_src_startofpacket; // router_016:src_startofpacket -> rsp_demux_013:sink_startofpacket
wire router_016_src_endofpacket; // router_016:src_endofpacket -> rsp_demux_013:sink_endofpacket
wire hex1_s1_agent_rp_valid; // hex1_s1_agent:rp_valid -> router_017:sink_valid
wire [110:0] hex1_s1_agent_rp_data; // hex1_s1_agent:rp_data -> router_017:sink_data
wire hex1_s1_agent_rp_ready; // router_017:sink_ready -> hex1_s1_agent:rp_ready
wire hex1_s1_agent_rp_startofpacket; // hex1_s1_agent:rp_startofpacket -> router_017:sink_startofpacket
wire hex1_s1_agent_rp_endofpacket; // hex1_s1_agent:rp_endofpacket -> router_017:sink_endofpacket
wire router_017_src_valid; // router_017:src_valid -> rsp_demux_014:sink_valid
wire [110:0] router_017_src_data; // router_017:src_data -> rsp_demux_014:sink_data
wire router_017_src_ready; // rsp_demux_014:sink_ready -> router_017:src_ready
wire [22:0] router_017_src_channel; // router_017:src_channel -> rsp_demux_014:sink_channel
wire router_017_src_startofpacket; // router_017:src_startofpacket -> rsp_demux_014:sink_startofpacket
wire router_017_src_endofpacket; // router_017:src_endofpacket -> rsp_demux_014:sink_endofpacket
wire hex2_s1_agent_rp_valid; // hex2_s1_agent:rp_valid -> router_018:sink_valid
wire [110:0] hex2_s1_agent_rp_data; // hex2_s1_agent:rp_data -> router_018:sink_data
wire hex2_s1_agent_rp_ready; // router_018:sink_ready -> hex2_s1_agent:rp_ready
wire hex2_s1_agent_rp_startofpacket; // hex2_s1_agent:rp_startofpacket -> router_018:sink_startofpacket
wire hex2_s1_agent_rp_endofpacket; // hex2_s1_agent:rp_endofpacket -> router_018:sink_endofpacket
wire router_018_src_valid; // router_018:src_valid -> rsp_demux_015:sink_valid
wire [110:0] router_018_src_data; // router_018:src_data -> rsp_demux_015:sink_data
wire router_018_src_ready; // rsp_demux_015:sink_ready -> router_018:src_ready
wire [22:0] router_018_src_channel; // router_018:src_channel -> rsp_demux_015:sink_channel
wire router_018_src_startofpacket; // router_018:src_startofpacket -> rsp_demux_015:sink_startofpacket
wire router_018_src_endofpacket; // router_018:src_endofpacket -> rsp_demux_015:sink_endofpacket
wire hex3_s1_agent_rp_valid; // hex3_s1_agent:rp_valid -> router_019:sink_valid
wire [110:0] hex3_s1_agent_rp_data; // hex3_s1_agent:rp_data -> router_019:sink_data
wire hex3_s1_agent_rp_ready; // router_019:sink_ready -> hex3_s1_agent:rp_ready
wire hex3_s1_agent_rp_startofpacket; // hex3_s1_agent:rp_startofpacket -> router_019:sink_startofpacket
wire hex3_s1_agent_rp_endofpacket; // hex3_s1_agent:rp_endofpacket -> router_019:sink_endofpacket
wire router_019_src_valid; // router_019:src_valid -> rsp_demux_016:sink_valid
wire [110:0] router_019_src_data; // router_019:src_data -> rsp_demux_016:sink_data
wire router_019_src_ready; // rsp_demux_016:sink_ready -> router_019:src_ready
wire [22:0] router_019_src_channel; // router_019:src_channel -> rsp_demux_016:sink_channel
wire router_019_src_startofpacket; // router_019:src_startofpacket -> rsp_demux_016:sink_startofpacket
wire router_019_src_endofpacket; // router_019:src_endofpacket -> rsp_demux_016:sink_endofpacket
wire hex4_s1_agent_rp_valid; // hex4_s1_agent:rp_valid -> router_020:sink_valid
wire [110:0] hex4_s1_agent_rp_data; // hex4_s1_agent:rp_data -> router_020:sink_data
wire hex4_s1_agent_rp_ready; // router_020:sink_ready -> hex4_s1_agent:rp_ready
wire hex4_s1_agent_rp_startofpacket; // hex4_s1_agent:rp_startofpacket -> router_020:sink_startofpacket
wire hex4_s1_agent_rp_endofpacket; // hex4_s1_agent:rp_endofpacket -> router_020:sink_endofpacket
wire router_020_src_valid; // router_020:src_valid -> rsp_demux_017:sink_valid
wire [110:0] router_020_src_data; // router_020:src_data -> rsp_demux_017:sink_data
wire router_020_src_ready; // rsp_demux_017:sink_ready -> router_020:src_ready
wire [22:0] router_020_src_channel; // router_020:src_channel -> rsp_demux_017:sink_channel
wire router_020_src_startofpacket; // router_020:src_startofpacket -> rsp_demux_017:sink_startofpacket
wire router_020_src_endofpacket; // router_020:src_endofpacket -> rsp_demux_017:sink_endofpacket
wire hex5_s1_agent_rp_valid; // hex5_s1_agent:rp_valid -> router_021:sink_valid
wire [110:0] hex5_s1_agent_rp_data; // hex5_s1_agent:rp_data -> router_021:sink_data
wire hex5_s1_agent_rp_ready; // router_021:sink_ready -> hex5_s1_agent:rp_ready
wire hex5_s1_agent_rp_startofpacket; // hex5_s1_agent:rp_startofpacket -> router_021:sink_startofpacket
wire hex5_s1_agent_rp_endofpacket; // hex5_s1_agent:rp_endofpacket -> router_021:sink_endofpacket
wire router_021_src_valid; // router_021:src_valid -> rsp_demux_018:sink_valid
wire [110:0] router_021_src_data; // router_021:src_data -> rsp_demux_018:sink_data
wire router_021_src_ready; // rsp_demux_018:sink_ready -> router_021:src_ready
wire [22:0] router_021_src_channel; // router_021:src_channel -> rsp_demux_018:sink_channel
wire router_021_src_startofpacket; // router_021:src_startofpacket -> rsp_demux_018:sink_startofpacket
wire router_021_src_endofpacket; // router_021:src_endofpacket -> rsp_demux_018:sink_endofpacket
wire hexdot_s1_agent_rp_valid; // hexdot_s1_agent:rp_valid -> router_022:sink_valid
wire [110:0] hexdot_s1_agent_rp_data; // hexdot_s1_agent:rp_data -> router_022:sink_data
wire hexdot_s1_agent_rp_ready; // router_022:sink_ready -> hexdot_s1_agent:rp_ready
wire hexdot_s1_agent_rp_startofpacket; // hexdot_s1_agent:rp_startofpacket -> router_022:sink_startofpacket
wire hexdot_s1_agent_rp_endofpacket; // hexdot_s1_agent:rp_endofpacket -> router_022:sink_endofpacket
wire router_022_src_valid; // router_022:src_valid -> rsp_demux_019:sink_valid
wire [110:0] router_022_src_data; // router_022:src_data -> rsp_demux_019:sink_data
wire router_022_src_ready; // rsp_demux_019:sink_ready -> router_022:src_ready
wire [22:0] router_022_src_channel; // router_022:src_channel -> rsp_demux_019:sink_channel
wire router_022_src_startofpacket; // router_022:src_startofpacket -> rsp_demux_019:sink_startofpacket
wire router_022_src_endofpacket; // router_022:src_endofpacket -> rsp_demux_019:sink_endofpacket
wire spi_sync_s1_agent_rp_valid; // spi_sync_s1_agent:rp_valid -> router_023:sink_valid
wire [110:0] spi_sync_s1_agent_rp_data; // spi_sync_s1_agent:rp_data -> router_023:sink_data
wire spi_sync_s1_agent_rp_ready; // router_023:sink_ready -> spi_sync_s1_agent:rp_ready
wire spi_sync_s1_agent_rp_startofpacket; // spi_sync_s1_agent:rp_startofpacket -> router_023:sink_startofpacket
wire spi_sync_s1_agent_rp_endofpacket; // spi_sync_s1_agent:rp_endofpacket -> router_023:sink_endofpacket
wire router_023_src_valid; // router_023:src_valid -> rsp_demux_020:sink_valid
wire [110:0] router_023_src_data; // router_023:src_data -> rsp_demux_020:sink_data
wire router_023_src_ready; // rsp_demux_020:sink_ready -> router_023:src_ready
wire [22:0] router_023_src_channel; // router_023:src_channel -> rsp_demux_020:sink_channel
wire router_023_src_startofpacket; // router_023:src_startofpacket -> rsp_demux_020:sink_startofpacket
wire router_023_src_endofpacket; // router_023:src_endofpacket -> rsp_demux_020:sink_endofpacket
wire extra_leds_s1_agent_rp_valid; // extra_leds_s1_agent:rp_valid -> router_024:sink_valid
wire [110:0] extra_leds_s1_agent_rp_data; // extra_leds_s1_agent:rp_data -> router_024:sink_data
wire extra_leds_s1_agent_rp_ready; // router_024:sink_ready -> extra_leds_s1_agent:rp_ready
wire extra_leds_s1_agent_rp_startofpacket; // extra_leds_s1_agent:rp_startofpacket -> router_024:sink_startofpacket
wire extra_leds_s1_agent_rp_endofpacket; // extra_leds_s1_agent:rp_endofpacket -> router_024:sink_endofpacket
wire router_024_src_valid; // router_024:src_valid -> rsp_demux_021:sink_valid
wire [110:0] router_024_src_data; // router_024:src_data -> rsp_demux_021:sink_data
wire router_024_src_ready; // rsp_demux_021:sink_ready -> router_024:src_ready
wire [22:0] router_024_src_channel; // router_024:src_channel -> rsp_demux_021:sink_channel
wire router_024_src_startofpacket; // router_024:src_startofpacket -> rsp_demux_021:sink_startofpacket
wire router_024_src_endofpacket; // router_024:src_endofpacket -> rsp_demux_021:sink_endofpacket
wire spi_stm32_spi_control_port_agent_rp_valid; // spi_stm32_spi_control_port_agent:rp_valid -> router_025:sink_valid
wire [110:0] spi_stm32_spi_control_port_agent_rp_data; // spi_stm32_spi_control_port_agent:rp_data -> router_025:sink_data
wire spi_stm32_spi_control_port_agent_rp_ready; // router_025:sink_ready -> spi_stm32_spi_control_port_agent:rp_ready
wire spi_stm32_spi_control_port_agent_rp_startofpacket; // spi_stm32_spi_control_port_agent:rp_startofpacket -> router_025:sink_startofpacket
wire spi_stm32_spi_control_port_agent_rp_endofpacket; // spi_stm32_spi_control_port_agent:rp_endofpacket -> router_025:sink_endofpacket
wire router_025_src_valid; // router_025:src_valid -> rsp_demux_022:sink_valid
wire [110:0] router_025_src_data; // router_025:src_data -> rsp_demux_022:sink_data
wire router_025_src_ready; // rsp_demux_022:sink_ready -> router_025:src_ready
wire [22:0] router_025_src_channel; // router_025:src_channel -> rsp_demux_022:sink_channel
wire router_025_src_startofpacket; // router_025:src_startofpacket -> rsp_demux_022:sink_startofpacket
wire router_025_src_endofpacket; // router_025:src_endofpacket -> rsp_demux_022:sink_endofpacket
wire router_src_valid; // router:src_valid -> abus_slave_0_avalon_master_limiter:cmd_sink_valid
wire [92:0] router_src_data; // router:src_data -> abus_slave_0_avalon_master_limiter:cmd_sink_data
wire router_src_ready; // abus_slave_0_avalon_master_limiter:cmd_sink_ready -> router:src_ready
wire [22:0] router_src_channel; // router:src_channel -> abus_slave_0_avalon_master_limiter:cmd_sink_channel
wire router_src_startofpacket; // router:src_startofpacket -> abus_slave_0_avalon_master_limiter:cmd_sink_startofpacket
wire router_src_endofpacket; // router:src_endofpacket -> abus_slave_0_avalon_master_limiter:cmd_sink_endofpacket
wire [92:0] abus_slave_0_avalon_master_limiter_cmd_src_data; // abus_slave_0_avalon_master_limiter:cmd_src_data -> cmd_demux:sink_data
wire abus_slave_0_avalon_master_limiter_cmd_src_ready; // cmd_demux:sink_ready -> abus_slave_0_avalon_master_limiter:cmd_src_ready
wire [22:0] abus_slave_0_avalon_master_limiter_cmd_src_channel; // abus_slave_0_avalon_master_limiter:cmd_src_channel -> cmd_demux:sink_channel
wire abus_slave_0_avalon_master_limiter_cmd_src_startofpacket; // abus_slave_0_avalon_master_limiter:cmd_src_startofpacket -> cmd_demux:sink_startofpacket
wire abus_slave_0_avalon_master_limiter_cmd_src_endofpacket; // abus_slave_0_avalon_master_limiter:cmd_src_endofpacket -> cmd_demux:sink_endofpacket
wire rsp_mux_src_valid; // rsp_mux:src_valid -> abus_slave_0_avalon_master_limiter:rsp_sink_valid
wire [92:0] rsp_mux_src_data; // rsp_mux:src_data -> abus_slave_0_avalon_master_limiter:rsp_sink_data
wire rsp_mux_src_ready; // abus_slave_0_avalon_master_limiter:rsp_sink_ready -> rsp_mux:src_ready
wire [22:0] rsp_mux_src_channel; // rsp_mux:src_channel -> abus_slave_0_avalon_master_limiter:rsp_sink_channel
wire rsp_mux_src_startofpacket; // rsp_mux:src_startofpacket -> abus_slave_0_avalon_master_limiter:rsp_sink_startofpacket
wire rsp_mux_src_endofpacket; // rsp_mux:src_endofpacket -> abus_slave_0_avalon_master_limiter:rsp_sink_endofpacket
wire abus_slave_0_avalon_master_limiter_rsp_src_valid; // abus_slave_0_avalon_master_limiter:rsp_src_valid -> abus_slave_0_avalon_master_agent:rp_valid
wire [92:0] abus_slave_0_avalon_master_limiter_rsp_src_data; // abus_slave_0_avalon_master_limiter:rsp_src_data -> abus_slave_0_avalon_master_agent:rp_data
wire abus_slave_0_avalon_master_limiter_rsp_src_ready; // abus_slave_0_avalon_master_agent:rp_ready -> abus_slave_0_avalon_master_limiter:rsp_src_ready
wire [22:0] abus_slave_0_avalon_master_limiter_rsp_src_channel; // abus_slave_0_avalon_master_limiter:rsp_src_channel -> abus_slave_0_avalon_master_agent:rp_channel
wire abus_slave_0_avalon_master_limiter_rsp_src_startofpacket; // abus_slave_0_avalon_master_limiter:rsp_src_startofpacket -> abus_slave_0_avalon_master_agent:rp_startofpacket
wire abus_slave_0_avalon_master_limiter_rsp_src_endofpacket; // abus_slave_0_avalon_master_limiter:rsp_src_endofpacket -> abus_slave_0_avalon_master_agent:rp_endofpacket
wire cmd_mux_src_valid; // cmd_mux:src_valid -> external_sdram_controller_s1_burst_adapter:sink0_valid
wire [92:0] cmd_mux_src_data; // cmd_mux:src_data -> external_sdram_controller_s1_burst_adapter:sink0_data
wire cmd_mux_src_ready; // external_sdram_controller_s1_burst_adapter:sink0_ready -> cmd_mux:src_ready
wire [22:0] cmd_mux_src_channel; // cmd_mux:src_channel -> external_sdram_controller_s1_burst_adapter:sink0_channel
wire cmd_mux_src_startofpacket; // cmd_mux:src_startofpacket -> external_sdram_controller_s1_burst_adapter:sink0_startofpacket
wire cmd_mux_src_endofpacket; // cmd_mux:src_endofpacket -> external_sdram_controller_s1_burst_adapter:sink0_endofpacket
wire external_sdram_controller_s1_burst_adapter_source0_valid; // external_sdram_controller_s1_burst_adapter:source0_valid -> external_sdram_controller_s1_agent:cp_valid
wire [92:0] external_sdram_controller_s1_burst_adapter_source0_data; // external_sdram_controller_s1_burst_adapter:source0_data -> external_sdram_controller_s1_agent:cp_data
wire external_sdram_controller_s1_burst_adapter_source0_ready; // external_sdram_controller_s1_agent:cp_ready -> external_sdram_controller_s1_burst_adapter:source0_ready
wire [22:0] external_sdram_controller_s1_burst_adapter_source0_channel; // external_sdram_controller_s1_burst_adapter:source0_channel -> external_sdram_controller_s1_agent:cp_channel
wire external_sdram_controller_s1_burst_adapter_source0_startofpacket; // external_sdram_controller_s1_burst_adapter:source0_startofpacket -> external_sdram_controller_s1_agent:cp_startofpacket
wire external_sdram_controller_s1_burst_adapter_source0_endofpacket; // external_sdram_controller_s1_burst_adapter:source0_endofpacket -> external_sdram_controller_s1_agent:cp_endofpacket
wire cmd_demux_src0_valid; // cmd_demux:src0_valid -> cmd_mux:sink0_valid
wire [92:0] cmd_demux_src0_data; // cmd_demux:src0_data -> cmd_mux:sink0_data
wire cmd_demux_src0_ready; // cmd_mux:sink0_ready -> cmd_demux:src0_ready
wire [22:0] cmd_demux_src0_channel; // cmd_demux:src0_channel -> cmd_mux:sink0_channel
wire cmd_demux_src0_startofpacket; // cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
wire cmd_demux_src0_endofpacket; // cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
wire cmd_demux_001_src1_valid; // cmd_demux_001:src1_valid -> cmd_mux_001:sink1_valid
wire [110:0] cmd_demux_001_src1_data; // cmd_demux_001:src1_data -> cmd_mux_001:sink1_data
wire cmd_demux_001_src1_ready; // cmd_mux_001:sink1_ready -> cmd_demux_001:src1_ready
wire [22:0] cmd_demux_001_src1_channel; // cmd_demux_001:src1_channel -> cmd_mux_001:sink1_channel
wire cmd_demux_001_src1_startofpacket; // cmd_demux_001:src1_startofpacket -> cmd_mux_001:sink1_startofpacket
wire cmd_demux_001_src1_endofpacket; // cmd_demux_001:src1_endofpacket -> cmd_mux_001:sink1_endofpacket
wire cmd_demux_001_src2_valid; // cmd_demux_001:src2_valid -> cmd_mux_002:sink0_valid
wire [110:0] cmd_demux_001_src2_data; // cmd_demux_001:src2_data -> cmd_mux_002:sink0_data
wire cmd_demux_001_src2_ready; // cmd_mux_002:sink0_ready -> cmd_demux_001:src2_ready
wire [22:0] cmd_demux_001_src2_channel; // cmd_demux_001:src2_channel -> cmd_mux_002:sink0_channel
wire cmd_demux_001_src2_startofpacket; // cmd_demux_001:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
wire cmd_demux_001_src2_endofpacket; // cmd_demux_001:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
wire cmd_demux_001_src3_valid; // cmd_demux_001:src3_valid -> cmd_mux_003:sink0_valid
wire [110:0] cmd_demux_001_src3_data; // cmd_demux_001:src3_data -> cmd_mux_003:sink0_data
wire cmd_demux_001_src3_ready; // cmd_mux_003:sink0_ready -> cmd_demux_001:src3_ready
wire [22:0] cmd_demux_001_src3_channel; // cmd_demux_001:src3_channel -> cmd_mux_003:sink0_channel
wire cmd_demux_001_src3_startofpacket; // cmd_demux_001:src3_startofpacket -> cmd_mux_003:sink0_startofpacket
wire cmd_demux_001_src3_endofpacket; // cmd_demux_001:src3_endofpacket -> cmd_mux_003:sink0_endofpacket
wire cmd_demux_001_src4_valid; // cmd_demux_001:src4_valid -> cmd_mux_004:sink0_valid
wire [110:0] cmd_demux_001_src4_data; // cmd_demux_001:src4_data -> cmd_mux_004:sink0_data
wire cmd_demux_001_src4_ready; // cmd_mux_004:sink0_ready -> cmd_demux_001:src4_ready
wire [22:0] cmd_demux_001_src4_channel; // cmd_demux_001:src4_channel -> cmd_mux_004:sink0_channel
wire cmd_demux_001_src4_startofpacket; // cmd_demux_001:src4_startofpacket -> cmd_mux_004:sink0_startofpacket
wire cmd_demux_001_src4_endofpacket; // cmd_demux_001:src4_endofpacket -> cmd_mux_004:sink0_endofpacket
wire cmd_demux_001_src5_valid; // cmd_demux_001:src5_valid -> cmd_mux_005:sink0_valid
wire [110:0] cmd_demux_001_src5_data; // cmd_demux_001:src5_data -> cmd_mux_005:sink0_data
wire cmd_demux_001_src5_ready; // cmd_mux_005:sink0_ready -> cmd_demux_001:src5_ready
wire [22:0] cmd_demux_001_src5_channel; // cmd_demux_001:src5_channel -> cmd_mux_005:sink0_channel
wire cmd_demux_001_src5_startofpacket; // cmd_demux_001:src5_startofpacket -> cmd_mux_005:sink0_startofpacket
wire cmd_demux_001_src5_endofpacket; // cmd_demux_001:src5_endofpacket -> cmd_mux_005:sink0_endofpacket
wire cmd_demux_001_src6_valid; // cmd_demux_001:src6_valid -> cmd_mux_006:sink0_valid
wire [110:0] cmd_demux_001_src6_data; // cmd_demux_001:src6_data -> cmd_mux_006:sink0_data
wire cmd_demux_001_src6_ready; // cmd_mux_006:sink0_ready -> cmd_demux_001:src6_ready
wire [22:0] cmd_demux_001_src6_channel; // cmd_demux_001:src6_channel -> cmd_mux_006:sink0_channel
wire cmd_demux_001_src6_startofpacket; // cmd_demux_001:src6_startofpacket -> cmd_mux_006:sink0_startofpacket
wire cmd_demux_001_src6_endofpacket; // cmd_demux_001:src6_endofpacket -> cmd_mux_006:sink0_endofpacket
wire cmd_demux_001_src7_valid; // cmd_demux_001:src7_valid -> cmd_mux_007:sink0_valid
wire [110:0] cmd_demux_001_src7_data; // cmd_demux_001:src7_data -> cmd_mux_007:sink0_data
wire cmd_demux_001_src7_ready; // cmd_mux_007:sink0_ready -> cmd_demux_001:src7_ready
wire [22:0] cmd_demux_001_src7_channel; // cmd_demux_001:src7_channel -> cmd_mux_007:sink0_channel
wire cmd_demux_001_src7_startofpacket; // cmd_demux_001:src7_startofpacket -> cmd_mux_007:sink0_startofpacket
wire cmd_demux_001_src7_endofpacket; // cmd_demux_001:src7_endofpacket -> cmd_mux_007:sink0_endofpacket
wire cmd_demux_001_src9_valid; // cmd_demux_001:src9_valid -> cmd_mux_009:sink0_valid
wire [110:0] cmd_demux_001_src9_data; // cmd_demux_001:src9_data -> cmd_mux_009:sink0_data
wire cmd_demux_001_src9_ready; // cmd_mux_009:sink0_ready -> cmd_demux_001:src9_ready
wire [22:0] cmd_demux_001_src9_channel; // cmd_demux_001:src9_channel -> cmd_mux_009:sink0_channel
wire cmd_demux_001_src9_startofpacket; // cmd_demux_001:src9_startofpacket -> cmd_mux_009:sink0_startofpacket
wire cmd_demux_001_src9_endofpacket; // cmd_demux_001:src9_endofpacket -> cmd_mux_009:sink0_endofpacket
wire cmd_demux_001_src10_valid; // cmd_demux_001:src10_valid -> cmd_mux_010:sink0_valid
wire [110:0] cmd_demux_001_src10_data; // cmd_demux_001:src10_data -> cmd_mux_010:sink0_data
wire cmd_demux_001_src10_ready; // cmd_mux_010:sink0_ready -> cmd_demux_001:src10_ready
wire [22:0] cmd_demux_001_src10_channel; // cmd_demux_001:src10_channel -> cmd_mux_010:sink0_channel
wire cmd_demux_001_src10_startofpacket; // cmd_demux_001:src10_startofpacket -> cmd_mux_010:sink0_startofpacket
wire cmd_demux_001_src10_endofpacket; // cmd_demux_001:src10_endofpacket -> cmd_mux_010:sink0_endofpacket
wire cmd_demux_001_src11_valid; // cmd_demux_001:src11_valid -> cmd_mux_011:sink0_valid
wire [110:0] cmd_demux_001_src11_data; // cmd_demux_001:src11_data -> cmd_mux_011:sink0_data
wire cmd_demux_001_src11_ready; // cmd_mux_011:sink0_ready -> cmd_demux_001:src11_ready
wire [22:0] cmd_demux_001_src11_channel; // cmd_demux_001:src11_channel -> cmd_mux_011:sink0_channel
wire cmd_demux_001_src11_startofpacket; // cmd_demux_001:src11_startofpacket -> cmd_mux_011:sink0_startofpacket
wire cmd_demux_001_src11_endofpacket; // cmd_demux_001:src11_endofpacket -> cmd_mux_011:sink0_endofpacket
wire cmd_demux_001_src12_valid; // cmd_demux_001:src12_valid -> cmd_mux_012:sink0_valid
wire [110:0] cmd_demux_001_src12_data; // cmd_demux_001:src12_data -> cmd_mux_012:sink0_data
wire cmd_demux_001_src12_ready; // cmd_mux_012:sink0_ready -> cmd_demux_001:src12_ready
wire [22:0] cmd_demux_001_src12_channel; // cmd_demux_001:src12_channel -> cmd_mux_012:sink0_channel
wire cmd_demux_001_src12_startofpacket; // cmd_demux_001:src12_startofpacket -> cmd_mux_012:sink0_startofpacket
wire cmd_demux_001_src12_endofpacket; // cmd_demux_001:src12_endofpacket -> cmd_mux_012:sink0_endofpacket
wire cmd_demux_001_src13_valid; // cmd_demux_001:src13_valid -> cmd_mux_013:sink0_valid
wire [110:0] cmd_demux_001_src13_data; // cmd_demux_001:src13_data -> cmd_mux_013:sink0_data
wire cmd_demux_001_src13_ready; // cmd_mux_013:sink0_ready -> cmd_demux_001:src13_ready
wire [22:0] cmd_demux_001_src13_channel; // cmd_demux_001:src13_channel -> cmd_mux_013:sink0_channel
wire cmd_demux_001_src13_startofpacket; // cmd_demux_001:src13_startofpacket -> cmd_mux_013:sink0_startofpacket
wire cmd_demux_001_src13_endofpacket; // cmd_demux_001:src13_endofpacket -> cmd_mux_013:sink0_endofpacket
wire cmd_demux_001_src14_valid; // cmd_demux_001:src14_valid -> cmd_mux_014:sink0_valid
wire [110:0] cmd_demux_001_src14_data; // cmd_demux_001:src14_data -> cmd_mux_014:sink0_data
wire cmd_demux_001_src14_ready; // cmd_mux_014:sink0_ready -> cmd_demux_001:src14_ready
wire [22:0] cmd_demux_001_src14_channel; // cmd_demux_001:src14_channel -> cmd_mux_014:sink0_channel
wire cmd_demux_001_src14_startofpacket; // cmd_demux_001:src14_startofpacket -> cmd_mux_014:sink0_startofpacket
wire cmd_demux_001_src14_endofpacket; // cmd_demux_001:src14_endofpacket -> cmd_mux_014:sink0_endofpacket
wire cmd_demux_001_src15_valid; // cmd_demux_001:src15_valid -> cmd_mux_015:sink0_valid
wire [110:0] cmd_demux_001_src15_data; // cmd_demux_001:src15_data -> cmd_mux_015:sink0_data
wire cmd_demux_001_src15_ready; // cmd_mux_015:sink0_ready -> cmd_demux_001:src15_ready
wire [22:0] cmd_demux_001_src15_channel; // cmd_demux_001:src15_channel -> cmd_mux_015:sink0_channel
wire cmd_demux_001_src15_startofpacket; // cmd_demux_001:src15_startofpacket -> cmd_mux_015:sink0_startofpacket
wire cmd_demux_001_src15_endofpacket; // cmd_demux_001:src15_endofpacket -> cmd_mux_015:sink0_endofpacket
wire cmd_demux_001_src16_valid; // cmd_demux_001:src16_valid -> cmd_mux_016:sink0_valid
wire [110:0] cmd_demux_001_src16_data; // cmd_demux_001:src16_data -> cmd_mux_016:sink0_data
wire cmd_demux_001_src16_ready; // cmd_mux_016:sink0_ready -> cmd_demux_001:src16_ready
wire [22:0] cmd_demux_001_src16_channel; // cmd_demux_001:src16_channel -> cmd_mux_016:sink0_channel
wire cmd_demux_001_src16_startofpacket; // cmd_demux_001:src16_startofpacket -> cmd_mux_016:sink0_startofpacket
wire cmd_demux_001_src16_endofpacket; // cmd_demux_001:src16_endofpacket -> cmd_mux_016:sink0_endofpacket
wire cmd_demux_001_src17_valid; // cmd_demux_001:src17_valid -> cmd_mux_017:sink0_valid
wire [110:0] cmd_demux_001_src17_data; // cmd_demux_001:src17_data -> cmd_mux_017:sink0_data
wire cmd_demux_001_src17_ready; // cmd_mux_017:sink0_ready -> cmd_demux_001:src17_ready
wire [22:0] cmd_demux_001_src17_channel; // cmd_demux_001:src17_channel -> cmd_mux_017:sink0_channel
wire cmd_demux_001_src17_startofpacket; // cmd_demux_001:src17_startofpacket -> cmd_mux_017:sink0_startofpacket
wire cmd_demux_001_src17_endofpacket; // cmd_demux_001:src17_endofpacket -> cmd_mux_017:sink0_endofpacket
wire cmd_demux_001_src18_valid; // cmd_demux_001:src18_valid -> cmd_mux_018:sink0_valid
wire [110:0] cmd_demux_001_src18_data; // cmd_demux_001:src18_data -> cmd_mux_018:sink0_data
wire cmd_demux_001_src18_ready; // cmd_mux_018:sink0_ready -> cmd_demux_001:src18_ready
wire [22:0] cmd_demux_001_src18_channel; // cmd_demux_001:src18_channel -> cmd_mux_018:sink0_channel
wire cmd_demux_001_src18_startofpacket; // cmd_demux_001:src18_startofpacket -> cmd_mux_018:sink0_startofpacket
wire cmd_demux_001_src18_endofpacket; // cmd_demux_001:src18_endofpacket -> cmd_mux_018:sink0_endofpacket
wire cmd_demux_001_src19_valid; // cmd_demux_001:src19_valid -> cmd_mux_019:sink0_valid
wire [110:0] cmd_demux_001_src19_data; // cmd_demux_001:src19_data -> cmd_mux_019:sink0_data
wire cmd_demux_001_src19_ready; // cmd_mux_019:sink0_ready -> cmd_demux_001:src19_ready
wire [22:0] cmd_demux_001_src19_channel; // cmd_demux_001:src19_channel -> cmd_mux_019:sink0_channel
wire cmd_demux_001_src19_startofpacket; // cmd_demux_001:src19_startofpacket -> cmd_mux_019:sink0_startofpacket
wire cmd_demux_001_src19_endofpacket; // cmd_demux_001:src19_endofpacket -> cmd_mux_019:sink0_endofpacket
wire cmd_demux_001_src20_valid; // cmd_demux_001:src20_valid -> cmd_mux_020:sink0_valid
wire [110:0] cmd_demux_001_src20_data; // cmd_demux_001:src20_data -> cmd_mux_020:sink0_data
wire cmd_demux_001_src20_ready; // cmd_mux_020:sink0_ready -> cmd_demux_001:src20_ready
wire [22:0] cmd_demux_001_src20_channel; // cmd_demux_001:src20_channel -> cmd_mux_020:sink0_channel
wire cmd_demux_001_src20_startofpacket; // cmd_demux_001:src20_startofpacket -> cmd_mux_020:sink0_startofpacket
wire cmd_demux_001_src20_endofpacket; // cmd_demux_001:src20_endofpacket -> cmd_mux_020:sink0_endofpacket
wire cmd_demux_001_src21_valid; // cmd_demux_001:src21_valid -> cmd_mux_021:sink0_valid
wire [110:0] cmd_demux_001_src21_data; // cmd_demux_001:src21_data -> cmd_mux_021:sink0_data
wire cmd_demux_001_src21_ready; // cmd_mux_021:sink0_ready -> cmd_demux_001:src21_ready
wire [22:0] cmd_demux_001_src21_channel; // cmd_demux_001:src21_channel -> cmd_mux_021:sink0_channel
wire cmd_demux_001_src21_startofpacket; // cmd_demux_001:src21_startofpacket -> cmd_mux_021:sink0_startofpacket
wire cmd_demux_001_src21_endofpacket; // cmd_demux_001:src21_endofpacket -> cmd_mux_021:sink0_endofpacket
wire cmd_demux_001_src22_valid; // cmd_demux_001:src22_valid -> cmd_mux_022:sink0_valid
wire [110:0] cmd_demux_001_src22_data; // cmd_demux_001:src22_data -> cmd_mux_022:sink0_data
wire cmd_demux_001_src22_ready; // cmd_mux_022:sink0_ready -> cmd_demux_001:src22_ready
wire [22:0] cmd_demux_001_src22_channel; // cmd_demux_001:src22_channel -> cmd_mux_022:sink0_channel
wire cmd_demux_001_src22_startofpacket; // cmd_demux_001:src22_startofpacket -> cmd_mux_022:sink0_startofpacket
wire cmd_demux_001_src22_endofpacket; // cmd_demux_001:src22_endofpacket -> cmd_mux_022:sink0_endofpacket
wire cmd_demux_002_src0_valid; // cmd_demux_002:src0_valid -> cmd_mux_001:sink2_valid
wire [110:0] cmd_demux_002_src0_data; // cmd_demux_002:src0_data -> cmd_mux_001:sink2_data
wire cmd_demux_002_src0_ready; // cmd_mux_001:sink2_ready -> cmd_demux_002:src0_ready
wire [22:0] cmd_demux_002_src0_channel; // cmd_demux_002:src0_channel -> cmd_mux_001:sink2_channel
wire cmd_demux_002_src0_startofpacket; // cmd_demux_002:src0_startofpacket -> cmd_mux_001:sink2_startofpacket
wire cmd_demux_002_src0_endofpacket; // cmd_demux_002:src0_endofpacket -> cmd_mux_001:sink2_endofpacket
wire cmd_demux_002_src1_valid; // cmd_demux_002:src1_valid -> cmd_mux_006:sink1_valid
wire [110:0] cmd_demux_002_src1_data; // cmd_demux_002:src1_data -> cmd_mux_006:sink1_data
wire cmd_demux_002_src1_ready; // cmd_mux_006:sink1_ready -> cmd_demux_002:src1_ready
wire [22:0] cmd_demux_002_src1_channel; // cmd_demux_002:src1_channel -> cmd_mux_006:sink1_channel
wire cmd_demux_002_src1_startofpacket; // cmd_demux_002:src1_startofpacket -> cmd_mux_006:sink1_startofpacket
wire cmd_demux_002_src1_endofpacket; // cmd_demux_002:src1_endofpacket -> cmd_mux_006:sink1_endofpacket
wire cmd_demux_002_src2_valid; // cmd_demux_002:src2_valid -> cmd_mux_007:sink1_valid
wire [110:0] cmd_demux_002_src2_data; // cmd_demux_002:src2_data -> cmd_mux_007:sink1_data
wire cmd_demux_002_src2_ready; // cmd_mux_007:sink1_ready -> cmd_demux_002:src2_ready
wire [22:0] cmd_demux_002_src2_channel; // cmd_demux_002:src2_channel -> cmd_mux_007:sink1_channel
wire cmd_demux_002_src2_startofpacket; // cmd_demux_002:src2_startofpacket -> cmd_mux_007:sink1_startofpacket
wire cmd_demux_002_src2_endofpacket; // cmd_demux_002:src2_endofpacket -> cmd_mux_007:sink1_endofpacket
wire cmd_demux_002_src3_valid; // cmd_demux_002:src3_valid -> cmd_mux_009:sink1_valid
wire [110:0] cmd_demux_002_src3_data; // cmd_demux_002:src3_data -> cmd_mux_009:sink1_data
wire cmd_demux_002_src3_ready; // cmd_mux_009:sink1_ready -> cmd_demux_002:src3_ready
wire [22:0] cmd_demux_002_src3_channel; // cmd_demux_002:src3_channel -> cmd_mux_009:sink1_channel
wire cmd_demux_002_src3_startofpacket; // cmd_demux_002:src3_startofpacket -> cmd_mux_009:sink1_startofpacket
wire cmd_demux_002_src3_endofpacket; // cmd_demux_002:src3_endofpacket -> cmd_mux_009:sink1_endofpacket
wire rsp_demux_src0_valid; // rsp_demux:src0_valid -> rsp_mux:sink0_valid
wire [92:0] rsp_demux_src0_data; // rsp_demux:src0_data -> rsp_mux:sink0_data
wire rsp_demux_src0_ready; // rsp_mux:sink0_ready -> rsp_demux:src0_ready
wire [22:0] rsp_demux_src0_channel; // rsp_demux:src0_channel -> rsp_mux:sink0_channel
wire rsp_demux_src0_startofpacket; // rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
wire rsp_demux_src0_endofpacket; // rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
wire rsp_demux_001_src1_valid; // rsp_demux_001:src1_valid -> rsp_mux_001:sink1_valid
wire [110:0] rsp_demux_001_src1_data; // rsp_demux_001:src1_data -> rsp_mux_001:sink1_data
wire rsp_demux_001_src1_ready; // rsp_mux_001:sink1_ready -> rsp_demux_001:src1_ready
wire [22:0] rsp_demux_001_src1_channel; // rsp_demux_001:src1_channel -> rsp_mux_001:sink1_channel
wire rsp_demux_001_src1_startofpacket; // rsp_demux_001:src1_startofpacket -> rsp_mux_001:sink1_startofpacket
wire rsp_demux_001_src1_endofpacket; // rsp_demux_001:src1_endofpacket -> rsp_mux_001:sink1_endofpacket
wire rsp_demux_001_src2_valid; // rsp_demux_001:src2_valid -> rsp_mux_002:sink0_valid
wire [110:0] rsp_demux_001_src2_data; // rsp_demux_001:src2_data -> rsp_mux_002:sink0_data
wire rsp_demux_001_src2_ready; // rsp_mux_002:sink0_ready -> rsp_demux_001:src2_ready
wire [22:0] rsp_demux_001_src2_channel; // rsp_demux_001:src2_channel -> rsp_mux_002:sink0_channel
wire rsp_demux_001_src2_startofpacket; // rsp_demux_001:src2_startofpacket -> rsp_mux_002:sink0_startofpacket
wire rsp_demux_001_src2_endofpacket; // rsp_demux_001:src2_endofpacket -> rsp_mux_002:sink0_endofpacket
wire rsp_demux_002_src0_valid; // rsp_demux_002:src0_valid -> rsp_mux_001:sink2_valid
wire [110:0] rsp_demux_002_src0_data; // rsp_demux_002:src0_data -> rsp_mux_001:sink2_data
wire rsp_demux_002_src0_ready; // rsp_mux_001:sink2_ready -> rsp_demux_002:src0_ready
wire [22:0] rsp_demux_002_src0_channel; // rsp_demux_002:src0_channel -> rsp_mux_001:sink2_channel
wire rsp_demux_002_src0_startofpacket; // rsp_demux_002:src0_startofpacket -> rsp_mux_001:sink2_startofpacket
wire rsp_demux_002_src0_endofpacket; // rsp_demux_002:src0_endofpacket -> rsp_mux_001:sink2_endofpacket
wire rsp_demux_003_src0_valid; // rsp_demux_003:src0_valid -> rsp_mux_001:sink3_valid
wire [110:0] rsp_demux_003_src0_data; // rsp_demux_003:src0_data -> rsp_mux_001:sink3_data
wire rsp_demux_003_src0_ready; // rsp_mux_001:sink3_ready -> rsp_demux_003:src0_ready
wire [22:0] rsp_demux_003_src0_channel; // rsp_demux_003:src0_channel -> rsp_mux_001:sink3_channel
wire rsp_demux_003_src0_startofpacket; // rsp_demux_003:src0_startofpacket -> rsp_mux_001:sink3_startofpacket
wire rsp_demux_003_src0_endofpacket; // rsp_demux_003:src0_endofpacket -> rsp_mux_001:sink3_endofpacket
wire rsp_demux_004_src0_valid; // rsp_demux_004:src0_valid -> rsp_mux_001:sink4_valid
wire [110:0] rsp_demux_004_src0_data; // rsp_demux_004:src0_data -> rsp_mux_001:sink4_data
wire rsp_demux_004_src0_ready; // rsp_mux_001:sink4_ready -> rsp_demux_004:src0_ready
wire [22:0] rsp_demux_004_src0_channel; // rsp_demux_004:src0_channel -> rsp_mux_001:sink4_channel
wire rsp_demux_004_src0_startofpacket; // rsp_demux_004:src0_startofpacket -> rsp_mux_001:sink4_startofpacket
wire rsp_demux_004_src0_endofpacket; // rsp_demux_004:src0_endofpacket -> rsp_mux_001:sink4_endofpacket
wire rsp_demux_005_src0_valid; // rsp_demux_005:src0_valid -> rsp_mux_001:sink5_valid
wire [110:0] rsp_demux_005_src0_data; // rsp_demux_005:src0_data -> rsp_mux_001:sink5_data
wire rsp_demux_005_src0_ready; // rsp_mux_001:sink5_ready -> rsp_demux_005:src0_ready
wire [22:0] rsp_demux_005_src0_channel; // rsp_demux_005:src0_channel -> rsp_mux_001:sink5_channel
wire rsp_demux_005_src0_startofpacket; // rsp_demux_005:src0_startofpacket -> rsp_mux_001:sink5_startofpacket
wire rsp_demux_005_src0_endofpacket; // rsp_demux_005:src0_endofpacket -> rsp_mux_001:sink5_endofpacket
wire rsp_demux_006_src0_valid; // rsp_demux_006:src0_valid -> rsp_mux_001:sink6_valid
wire [110:0] rsp_demux_006_src0_data; // rsp_demux_006:src0_data -> rsp_mux_001:sink6_data
wire rsp_demux_006_src0_ready; // rsp_mux_001:sink6_ready -> rsp_demux_006:src0_ready
wire [22:0] rsp_demux_006_src0_channel; // rsp_demux_006:src0_channel -> rsp_mux_001:sink6_channel
wire rsp_demux_006_src0_startofpacket; // rsp_demux_006:src0_startofpacket -> rsp_mux_001:sink6_startofpacket
wire rsp_demux_006_src0_endofpacket; // rsp_demux_006:src0_endofpacket -> rsp_mux_001:sink6_endofpacket
wire rsp_demux_006_src1_valid; // rsp_demux_006:src1_valid -> rsp_mux_002:sink1_valid
wire [110:0] rsp_demux_006_src1_data; // rsp_demux_006:src1_data -> rsp_mux_002:sink1_data
wire rsp_demux_006_src1_ready; // rsp_mux_002:sink1_ready -> rsp_demux_006:src1_ready
wire [22:0] rsp_demux_006_src1_channel; // rsp_demux_006:src1_channel -> rsp_mux_002:sink1_channel
wire rsp_demux_006_src1_startofpacket; // rsp_demux_006:src1_startofpacket -> rsp_mux_002:sink1_startofpacket
wire rsp_demux_006_src1_endofpacket; // rsp_demux_006:src1_endofpacket -> rsp_mux_002:sink1_endofpacket
wire rsp_demux_007_src0_valid; // rsp_demux_007:src0_valid -> rsp_mux_001:sink7_valid
wire [110:0] rsp_demux_007_src0_data; // rsp_demux_007:src0_data -> rsp_mux_001:sink7_data
wire rsp_demux_007_src0_ready; // rsp_mux_001:sink7_ready -> rsp_demux_007:src0_ready
wire [22:0] rsp_demux_007_src0_channel; // rsp_demux_007:src0_channel -> rsp_mux_001:sink7_channel
wire rsp_demux_007_src0_startofpacket; // rsp_demux_007:src0_startofpacket -> rsp_mux_001:sink7_startofpacket
wire rsp_demux_007_src0_endofpacket; // rsp_demux_007:src0_endofpacket -> rsp_mux_001:sink7_endofpacket
wire rsp_demux_007_src1_valid; // rsp_demux_007:src1_valid -> rsp_mux_002:sink2_valid
wire [110:0] rsp_demux_007_src1_data; // rsp_demux_007:src1_data -> rsp_mux_002:sink2_data
wire rsp_demux_007_src1_ready; // rsp_mux_002:sink2_ready -> rsp_demux_007:src1_ready
wire [22:0] rsp_demux_007_src1_channel; // rsp_demux_007:src1_channel -> rsp_mux_002:sink2_channel
wire rsp_demux_007_src1_startofpacket; // rsp_demux_007:src1_startofpacket -> rsp_mux_002:sink2_startofpacket
wire rsp_demux_007_src1_endofpacket; // rsp_demux_007:src1_endofpacket -> rsp_mux_002:sink2_endofpacket
wire rsp_demux_009_src0_valid; // rsp_demux_009:src0_valid -> rsp_mux_001:sink9_valid
wire [110:0] rsp_demux_009_src0_data; // rsp_demux_009:src0_data -> rsp_mux_001:sink9_data
wire rsp_demux_009_src0_ready; // rsp_mux_001:sink9_ready -> rsp_demux_009:src0_ready
wire [22:0] rsp_demux_009_src0_channel; // rsp_demux_009:src0_channel -> rsp_mux_001:sink9_channel
wire rsp_demux_009_src0_startofpacket; // rsp_demux_009:src0_startofpacket -> rsp_mux_001:sink9_startofpacket
wire rsp_demux_009_src0_endofpacket; // rsp_demux_009:src0_endofpacket -> rsp_mux_001:sink9_endofpacket
wire rsp_demux_009_src1_valid; // rsp_demux_009:src1_valid -> rsp_mux_002:sink3_valid
wire [110:0] rsp_demux_009_src1_data; // rsp_demux_009:src1_data -> rsp_mux_002:sink3_data
wire rsp_demux_009_src1_ready; // rsp_mux_002:sink3_ready -> rsp_demux_009:src1_ready
wire [22:0] rsp_demux_009_src1_channel; // rsp_demux_009:src1_channel -> rsp_mux_002:sink3_channel
wire rsp_demux_009_src1_startofpacket; // rsp_demux_009:src1_startofpacket -> rsp_mux_002:sink3_startofpacket
wire rsp_demux_009_src1_endofpacket; // rsp_demux_009:src1_endofpacket -> rsp_mux_002:sink3_endofpacket
wire rsp_demux_010_src0_valid; // rsp_demux_010:src0_valid -> rsp_mux_001:sink10_valid
wire [110:0] rsp_demux_010_src0_data; // rsp_demux_010:src0_data -> rsp_mux_001:sink10_data
wire rsp_demux_010_src0_ready; // rsp_mux_001:sink10_ready -> rsp_demux_010:src0_ready
wire [22:0] rsp_demux_010_src0_channel; // rsp_demux_010:src0_channel -> rsp_mux_001:sink10_channel
wire rsp_demux_010_src0_startofpacket; // rsp_demux_010:src0_startofpacket -> rsp_mux_001:sink10_startofpacket
wire rsp_demux_010_src0_endofpacket; // rsp_demux_010:src0_endofpacket -> rsp_mux_001:sink10_endofpacket
wire rsp_demux_011_src0_valid; // rsp_demux_011:src0_valid -> rsp_mux_001:sink11_valid
wire [110:0] rsp_demux_011_src0_data; // rsp_demux_011:src0_data -> rsp_mux_001:sink11_data
wire rsp_demux_011_src0_ready; // rsp_mux_001:sink11_ready -> rsp_demux_011:src0_ready
wire [22:0] rsp_demux_011_src0_channel; // rsp_demux_011:src0_channel -> rsp_mux_001:sink11_channel
wire rsp_demux_011_src0_startofpacket; // rsp_demux_011:src0_startofpacket -> rsp_mux_001:sink11_startofpacket
wire rsp_demux_011_src0_endofpacket; // rsp_demux_011:src0_endofpacket -> rsp_mux_001:sink11_endofpacket
wire rsp_demux_012_src0_valid; // rsp_demux_012:src0_valid -> rsp_mux_001:sink12_valid
wire [110:0] rsp_demux_012_src0_data; // rsp_demux_012:src0_data -> rsp_mux_001:sink12_data
wire rsp_demux_012_src0_ready; // rsp_mux_001:sink12_ready -> rsp_demux_012:src0_ready
wire [22:0] rsp_demux_012_src0_channel; // rsp_demux_012:src0_channel -> rsp_mux_001:sink12_channel
wire rsp_demux_012_src0_startofpacket; // rsp_demux_012:src0_startofpacket -> rsp_mux_001:sink12_startofpacket
wire rsp_demux_012_src0_endofpacket; // rsp_demux_012:src0_endofpacket -> rsp_mux_001:sink12_endofpacket
wire rsp_demux_013_src0_valid; // rsp_demux_013:src0_valid -> rsp_mux_001:sink13_valid
wire [110:0] rsp_demux_013_src0_data; // rsp_demux_013:src0_data -> rsp_mux_001:sink13_data
wire rsp_demux_013_src0_ready; // rsp_mux_001:sink13_ready -> rsp_demux_013:src0_ready
wire [22:0] rsp_demux_013_src0_channel; // rsp_demux_013:src0_channel -> rsp_mux_001:sink13_channel
wire rsp_demux_013_src0_startofpacket; // rsp_demux_013:src0_startofpacket -> rsp_mux_001:sink13_startofpacket
wire rsp_demux_013_src0_endofpacket; // rsp_demux_013:src0_endofpacket -> rsp_mux_001:sink13_endofpacket
wire rsp_demux_014_src0_valid; // rsp_demux_014:src0_valid -> rsp_mux_001:sink14_valid
wire [110:0] rsp_demux_014_src0_data; // rsp_demux_014:src0_data -> rsp_mux_001:sink14_data
wire rsp_demux_014_src0_ready; // rsp_mux_001:sink14_ready -> rsp_demux_014:src0_ready
wire [22:0] rsp_demux_014_src0_channel; // rsp_demux_014:src0_channel -> rsp_mux_001:sink14_channel
wire rsp_demux_014_src0_startofpacket; // rsp_demux_014:src0_startofpacket -> rsp_mux_001:sink14_startofpacket
wire rsp_demux_014_src0_endofpacket; // rsp_demux_014:src0_endofpacket -> rsp_mux_001:sink14_endofpacket
wire rsp_demux_015_src0_valid; // rsp_demux_015:src0_valid -> rsp_mux_001:sink15_valid
wire [110:0] rsp_demux_015_src0_data; // rsp_demux_015:src0_data -> rsp_mux_001:sink15_data
wire rsp_demux_015_src0_ready; // rsp_mux_001:sink15_ready -> rsp_demux_015:src0_ready
wire [22:0] rsp_demux_015_src0_channel; // rsp_demux_015:src0_channel -> rsp_mux_001:sink15_channel
wire rsp_demux_015_src0_startofpacket; // rsp_demux_015:src0_startofpacket -> rsp_mux_001:sink15_startofpacket
wire rsp_demux_015_src0_endofpacket; // rsp_demux_015:src0_endofpacket -> rsp_mux_001:sink15_endofpacket
wire rsp_demux_016_src0_valid; // rsp_demux_016:src0_valid -> rsp_mux_001:sink16_valid
wire [110:0] rsp_demux_016_src0_data; // rsp_demux_016:src0_data -> rsp_mux_001:sink16_data
wire rsp_demux_016_src0_ready; // rsp_mux_001:sink16_ready -> rsp_demux_016:src0_ready
wire [22:0] rsp_demux_016_src0_channel; // rsp_demux_016:src0_channel -> rsp_mux_001:sink16_channel
wire rsp_demux_016_src0_startofpacket; // rsp_demux_016:src0_startofpacket -> rsp_mux_001:sink16_startofpacket
wire rsp_demux_016_src0_endofpacket; // rsp_demux_016:src0_endofpacket -> rsp_mux_001:sink16_endofpacket
wire rsp_demux_017_src0_valid; // rsp_demux_017:src0_valid -> rsp_mux_001:sink17_valid
wire [110:0] rsp_demux_017_src0_data; // rsp_demux_017:src0_data -> rsp_mux_001:sink17_data
wire rsp_demux_017_src0_ready; // rsp_mux_001:sink17_ready -> rsp_demux_017:src0_ready
wire [22:0] rsp_demux_017_src0_channel; // rsp_demux_017:src0_channel -> rsp_mux_001:sink17_channel
wire rsp_demux_017_src0_startofpacket; // rsp_demux_017:src0_startofpacket -> rsp_mux_001:sink17_startofpacket
wire rsp_demux_017_src0_endofpacket; // rsp_demux_017:src0_endofpacket -> rsp_mux_001:sink17_endofpacket
wire rsp_demux_018_src0_valid; // rsp_demux_018:src0_valid -> rsp_mux_001:sink18_valid
wire [110:0] rsp_demux_018_src0_data; // rsp_demux_018:src0_data -> rsp_mux_001:sink18_data
wire rsp_demux_018_src0_ready; // rsp_mux_001:sink18_ready -> rsp_demux_018:src0_ready
wire [22:0] rsp_demux_018_src0_channel; // rsp_demux_018:src0_channel -> rsp_mux_001:sink18_channel
wire rsp_demux_018_src0_startofpacket; // rsp_demux_018:src0_startofpacket -> rsp_mux_001:sink18_startofpacket
wire rsp_demux_018_src0_endofpacket; // rsp_demux_018:src0_endofpacket -> rsp_mux_001:sink18_endofpacket
wire rsp_demux_019_src0_valid; // rsp_demux_019:src0_valid -> rsp_mux_001:sink19_valid
wire [110:0] rsp_demux_019_src0_data; // rsp_demux_019:src0_data -> rsp_mux_001:sink19_data
wire rsp_demux_019_src0_ready; // rsp_mux_001:sink19_ready -> rsp_demux_019:src0_ready
wire [22:0] rsp_demux_019_src0_channel; // rsp_demux_019:src0_channel -> rsp_mux_001:sink19_channel
wire rsp_demux_019_src0_startofpacket; // rsp_demux_019:src0_startofpacket -> rsp_mux_001:sink19_startofpacket
wire rsp_demux_019_src0_endofpacket; // rsp_demux_019:src0_endofpacket -> rsp_mux_001:sink19_endofpacket
wire rsp_demux_020_src0_valid; // rsp_demux_020:src0_valid -> rsp_mux_001:sink20_valid
wire [110:0] rsp_demux_020_src0_data; // rsp_demux_020:src0_data -> rsp_mux_001:sink20_data
wire rsp_demux_020_src0_ready; // rsp_mux_001:sink20_ready -> rsp_demux_020:src0_ready
wire [22:0] rsp_demux_020_src0_channel; // rsp_demux_020:src0_channel -> rsp_mux_001:sink20_channel
wire rsp_demux_020_src0_startofpacket; // rsp_demux_020:src0_startofpacket -> rsp_mux_001:sink20_startofpacket
wire rsp_demux_020_src0_endofpacket; // rsp_demux_020:src0_endofpacket -> rsp_mux_001:sink20_endofpacket
wire rsp_demux_021_src0_valid; // rsp_demux_021:src0_valid -> rsp_mux_001:sink21_valid
wire [110:0] rsp_demux_021_src0_data; // rsp_demux_021:src0_data -> rsp_mux_001:sink21_data
wire rsp_demux_021_src0_ready; // rsp_mux_001:sink21_ready -> rsp_demux_021:src0_ready
wire [22:0] rsp_demux_021_src0_channel; // rsp_demux_021:src0_channel -> rsp_mux_001:sink21_channel
wire rsp_demux_021_src0_startofpacket; // rsp_demux_021:src0_startofpacket -> rsp_mux_001:sink21_startofpacket
wire rsp_demux_021_src0_endofpacket; // rsp_demux_021:src0_endofpacket -> rsp_mux_001:sink21_endofpacket
wire rsp_demux_022_src0_valid; // rsp_demux_022:src0_valid -> rsp_mux_001:sink22_valid
wire [110:0] rsp_demux_022_src0_data; // rsp_demux_022:src0_data -> rsp_mux_001:sink22_data
wire rsp_demux_022_src0_ready; // rsp_mux_001:sink22_ready -> rsp_demux_022:src0_ready
wire [22:0] rsp_demux_022_src0_channel; // rsp_demux_022:src0_channel -> rsp_mux_001:sink22_channel
wire rsp_demux_022_src0_startofpacket; // rsp_demux_022:src0_startofpacket -> rsp_mux_001:sink22_startofpacket
wire rsp_demux_022_src0_endofpacket; // rsp_demux_022:src0_endofpacket -> rsp_mux_001:sink22_endofpacket
wire cmd_demux_src1_valid; // cmd_demux:src1_valid -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_valid
wire [92:0] cmd_demux_src1_data; // cmd_demux:src1_data -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_data
wire cmd_demux_src1_ready; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_ready -> cmd_demux:src1_ready
wire [22:0] cmd_demux_src1_channel; // cmd_demux:src1_channel -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_channel
wire cmd_demux_src1_startofpacket; // cmd_demux:src1_startofpacket -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_src1_endofpacket; // cmd_demux:src1_endofpacket -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:in_endofpacket
wire abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_valid -> cmd_mux_001:sink0_valid
wire [110:0] abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_data -> cmd_mux_001:sink0_data
wire abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready; // cmd_mux_001:sink0_ready -> abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_ready
wire [22:0] abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_channel -> cmd_mux_001:sink0_channel
wire abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_startofpacket -> cmd_mux_001:sink0_startofpacket
wire abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket; // abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter:out_endofpacket -> cmd_mux_001:sink0_endofpacket
wire cmd_demux_001_src0_valid; // cmd_demux_001:src0_valid -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_valid
wire [110:0] cmd_demux_001_src0_data; // cmd_demux_001:src0_data -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_data
wire cmd_demux_001_src0_ready; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_ready -> cmd_demux_001:src0_ready
wire [22:0] cmd_demux_001_src0_channel; // cmd_demux_001:src0_channel -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_channel
wire cmd_demux_001_src0_startofpacket; // cmd_demux_001:src0_startofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_startofpacket
wire cmd_demux_001_src0_endofpacket; // cmd_demux_001:src0_endofpacket -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:in_endofpacket
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_valid -> cmd_mux:sink1_valid
wire [92:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_data -> cmd_mux:sink1_data
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready; // cmd_mux:sink1_ready -> nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_ready
wire [22:0] nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_channel -> cmd_mux:sink1_channel
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_startofpacket -> cmd_mux:sink1_startofpacket
wire nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket; // nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter:out_endofpacket -> cmd_mux:sink1_endofpacket
wire rsp_demux_src1_valid; // rsp_demux:src1_valid -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_valid
wire [92:0] rsp_demux_src1_data; // rsp_demux:src1_data -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_data
wire rsp_demux_src1_ready; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_ready -> rsp_demux:src1_ready
wire [22:0] rsp_demux_src1_channel; // rsp_demux:src1_channel -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_channel
wire rsp_demux_src1_startofpacket; // rsp_demux:src1_startofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_src1_endofpacket; // rsp_demux:src1_endofpacket -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:in_endofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_valid -> rsp_mux_001:sink0_valid
wire [110:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_data -> rsp_mux_001:sink0_data
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready; // rsp_mux_001:sink0_ready -> external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_ready
wire [22:0] external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_channel -> rsp_mux_001:sink0_channel
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_startofpacket -> rsp_mux_001:sink0_startofpacket
wire external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket; // external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter:out_endofpacket -> rsp_mux_001:sink0_endofpacket
wire rsp_demux_001_src0_valid; // rsp_demux_001:src0_valid -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_valid
wire [110:0] rsp_demux_001_src0_data; // rsp_demux_001:src0_data -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_data
wire rsp_demux_001_src0_ready; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_ready -> rsp_demux_001:src0_ready
wire [22:0] rsp_demux_001_src0_channel; // rsp_demux_001:src0_channel -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_channel
wire rsp_demux_001_src0_startofpacket; // rsp_demux_001:src0_startofpacket -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_startofpacket
wire rsp_demux_001_src0_endofpacket; // rsp_demux_001:src0_endofpacket -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:in_endofpacket
wire onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_valid -> rsp_mux:sink1_valid
wire [92:0] onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_data -> rsp_mux:sink1_data
wire onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready; // rsp_mux:sink1_ready -> onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_ready
wire [22:0] onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_channel -> rsp_mux:sink1_channel
wire onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_startofpacket -> rsp_mux:sink1_startofpacket
wire onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket; // onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter:out_endofpacket -> rsp_mux:sink1_endofpacket
wire cmd_demux_001_src8_valid; // cmd_demux_001:src8_valid -> crosser:in_valid
wire [110:0] cmd_demux_001_src8_data; // cmd_demux_001:src8_data -> crosser:in_data
wire cmd_demux_001_src8_ready; // crosser:in_ready -> cmd_demux_001:src8_ready
wire [22:0] cmd_demux_001_src8_channel; // cmd_demux_001:src8_channel -> crosser:in_channel
wire cmd_demux_001_src8_startofpacket; // cmd_demux_001:src8_startofpacket -> crosser:in_startofpacket
wire cmd_demux_001_src8_endofpacket; // cmd_demux_001:src8_endofpacket -> crosser:in_endofpacket
wire crosser_out_valid; // crosser:out_valid -> cmd_mux_008:sink0_valid
wire [110:0] crosser_out_data; // crosser:out_data -> cmd_mux_008:sink0_data
wire crosser_out_ready; // cmd_mux_008:sink0_ready -> crosser:out_ready
wire [22:0] crosser_out_channel; // crosser:out_channel -> cmd_mux_008:sink0_channel
wire crosser_out_startofpacket; // crosser:out_startofpacket -> cmd_mux_008:sink0_startofpacket
wire crosser_out_endofpacket; // crosser:out_endofpacket -> cmd_mux_008:sink0_endofpacket
wire rsp_demux_008_src0_valid; // rsp_demux_008:src0_valid -> crosser_001:in_valid
wire [110:0] rsp_demux_008_src0_data; // rsp_demux_008:src0_data -> crosser_001:in_data
wire rsp_demux_008_src0_ready; // crosser_001:in_ready -> rsp_demux_008:src0_ready
wire [22:0] rsp_demux_008_src0_channel; // rsp_demux_008:src0_channel -> crosser_001:in_channel
wire rsp_demux_008_src0_startofpacket; // rsp_demux_008:src0_startofpacket -> crosser_001:in_startofpacket
wire rsp_demux_008_src0_endofpacket; // rsp_demux_008:src0_endofpacket -> crosser_001:in_endofpacket
wire crosser_001_out_valid; // crosser_001:out_valid -> rsp_mux_001:sink8_valid
wire [110:0] crosser_001_out_data; // crosser_001:out_data -> rsp_mux_001:sink8_data
wire crosser_001_out_ready; // rsp_mux_001:sink8_ready -> crosser_001:out_ready
wire [22:0] crosser_001_out_channel; // crosser_001:out_channel -> rsp_mux_001:sink8_channel
wire crosser_001_out_startofpacket; // crosser_001:out_startofpacket -> rsp_mux_001:sink8_startofpacket
wire crosser_001_out_endofpacket; // crosser_001:out_endofpacket -> rsp_mux_001:sink8_endofpacket
wire [22:0] abus_slave_0_avalon_master_limiter_cmd_valid_data; // abus_slave_0_avalon_master_limiter:cmd_src_valid -> cmd_demux:sink_valid
wire external_sdram_controller_s1_agent_rdata_fifo_out_valid; // external_sdram_controller_s1_agent_rdata_fifo:out_valid -> avalon_st_adapter:in_0_valid
wire [17:0] external_sdram_controller_s1_agent_rdata_fifo_out_data; // external_sdram_controller_s1_agent_rdata_fifo:out_data -> avalon_st_adapter:in_0_data
wire external_sdram_controller_s1_agent_rdata_fifo_out_ready; // avalon_st_adapter:in_0_ready -> external_sdram_controller_s1_agent_rdata_fifo:out_ready
wire avalon_st_adapter_out_0_valid; // avalon_st_adapter:out_0_valid -> external_sdram_controller_s1_agent:rdata_fifo_sink_valid
wire [17:0] avalon_st_adapter_out_0_data; // avalon_st_adapter:out_0_data -> external_sdram_controller_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_out_0_ready; // external_sdram_controller_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
wire [0:0] avalon_st_adapter_out_0_error; // avalon_st_adapter:out_0_error -> external_sdram_controller_s1_agent:rdata_fifo_sink_error
wire onchip_memory2_1_s1_agent_rdata_fifo_src_valid; // onchip_memory2_1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
wire [33:0] onchip_memory2_1_s1_agent_rdata_fifo_src_data; // onchip_memory2_1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
wire onchip_memory2_1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_001:in_0_ready -> onchip_memory2_1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_001_out_0_valid; // avalon_st_adapter_001:out_0_valid -> onchip_memory2_1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_001_out_0_data; // avalon_st_adapter_001:out_0_data -> onchip_memory2_1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_001_out_0_ready; // onchip_memory2_1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
wire [0:0] avalon_st_adapter_001_out_0_error; // avalon_st_adapter_001:out_0_error -> onchip_memory2_1_s1_agent:rdata_fifo_sink_error
wire abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid; // abus_slave_0_avalon_nios_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
wire [33:0] abus_slave_0_avalon_nios_agent_rdata_fifo_src_data; // abus_slave_0_avalon_nios_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
wire abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready; // avalon_st_adapter_002:in_0_ready -> abus_slave_0_avalon_nios_agent:rdata_fifo_src_ready
wire avalon_st_adapter_002_out_0_valid; // avalon_st_adapter_002:out_0_valid -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_002_out_0_data; // avalon_st_adapter_002:out_0_data -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_data
wire avalon_st_adapter_002_out_0_ready; // abus_slave_0_avalon_nios_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
wire [0:0] avalon_st_adapter_002_out_0_error; // avalon_st_adapter_002:out_0_error -> abus_slave_0_avalon_nios_agent:rdata_fifo_sink_error
wire abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid; // abus_demux_0_avalon_nios_agent:rdata_fifo_src_valid -> avalon_st_adapter_003:in_0_valid
wire [33:0] abus_demux_0_avalon_nios_agent_rdata_fifo_src_data; // abus_demux_0_avalon_nios_agent:rdata_fifo_src_data -> avalon_st_adapter_003:in_0_data
wire abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready; // avalon_st_adapter_003:in_0_ready -> abus_demux_0_avalon_nios_agent:rdata_fifo_src_ready
wire avalon_st_adapter_003_out_0_valid; // avalon_st_adapter_003:out_0_valid -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_003_out_0_data; // avalon_st_adapter_003:out_0_data -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_data
wire avalon_st_adapter_003_out_0_ready; // abus_demux_0_avalon_nios_agent:rdata_fifo_sink_ready -> avalon_st_adapter_003:out_0_ready
wire [0:0] avalon_st_adapter_003_out_0_error; // avalon_st_adapter_003:out_0_error -> abus_demux_0_avalon_nios_agent:rdata_fifo_sink_error
wire performance_counter_0_control_slave_agent_rdata_fifo_src_valid; // performance_counter_0_control_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_004:in_0_valid
wire [33:0] performance_counter_0_control_slave_agent_rdata_fifo_src_data; // performance_counter_0_control_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_004:in_0_data
wire performance_counter_0_control_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_004:in_0_ready -> performance_counter_0_control_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_004_out_0_valid; // avalon_st_adapter_004:out_0_valid -> performance_counter_0_control_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_004_out_0_data; // avalon_st_adapter_004:out_0_data -> performance_counter_0_control_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_004_out_0_ready; // performance_counter_0_control_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_004:out_0_ready
wire [0:0] avalon_st_adapter_004_out_0_error; // avalon_st_adapter_004:out_0_error -> performance_counter_0_control_slave_agent:rdata_fifo_sink_error
wire onchip_flash_0_csr_agent_rdata_fifo_src_valid; // onchip_flash_0_csr_agent:rdata_fifo_src_valid -> avalon_st_adapter_005:in_0_valid
wire [33:0] onchip_flash_0_csr_agent_rdata_fifo_src_data; // onchip_flash_0_csr_agent:rdata_fifo_src_data -> avalon_st_adapter_005:in_0_data
wire onchip_flash_0_csr_agent_rdata_fifo_src_ready; // avalon_st_adapter_005:in_0_ready -> onchip_flash_0_csr_agent:rdata_fifo_src_ready
wire avalon_st_adapter_005_out_0_valid; // avalon_st_adapter_005:out_0_valid -> onchip_flash_0_csr_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_005_out_0_data; // avalon_st_adapter_005:out_0_data -> onchip_flash_0_csr_agent:rdata_fifo_sink_data
wire avalon_st_adapter_005_out_0_ready; // onchip_flash_0_csr_agent:rdata_fifo_sink_ready -> avalon_st_adapter_005:out_0_ready
wire [0:0] avalon_st_adapter_005_out_0_error; // avalon_st_adapter_005:out_0_error -> onchip_flash_0_csr_agent:rdata_fifo_sink_error
wire onchip_flash_0_data_agent_rdata_fifo_src_valid; // onchip_flash_0_data_agent:rdata_fifo_src_valid -> avalon_st_adapter_006:in_0_valid
wire [33:0] onchip_flash_0_data_agent_rdata_fifo_src_data; // onchip_flash_0_data_agent:rdata_fifo_src_data -> avalon_st_adapter_006:in_0_data
wire onchip_flash_0_data_agent_rdata_fifo_src_ready; // avalon_st_adapter_006:in_0_ready -> onchip_flash_0_data_agent:rdata_fifo_src_ready
wire avalon_st_adapter_006_out_0_valid; // avalon_st_adapter_006:out_0_valid -> onchip_flash_0_data_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_006_out_0_data; // avalon_st_adapter_006:out_0_data -> onchip_flash_0_data_agent:rdata_fifo_sink_data
wire avalon_st_adapter_006_out_0_ready; // onchip_flash_0_data_agent:rdata_fifo_sink_ready -> avalon_st_adapter_006:out_0_ready
wire [0:0] avalon_st_adapter_006_out_0_error; // avalon_st_adapter_006:out_0_error -> onchip_flash_0_data_agent:rdata_fifo_sink_error
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_valid -> avalon_st_adapter_007:in_0_valid
wire [33:0] nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_data -> avalon_st_adapter_007:in_0_data
wire nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready; // avalon_st_adapter_007:in_0_ready -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_src_ready
wire avalon_st_adapter_007_out_0_valid; // avalon_st_adapter_007:out_0_valid -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_007_out_0_data; // avalon_st_adapter_007:out_0_data -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_007_out_0_ready; // nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_007:out_0_ready
wire [0:0] avalon_st_adapter_007_out_0_error; // avalon_st_adapter_007:out_0_error -> nios2_gen2_0_debug_mem_slave_agent:rdata_fifo_sink_error
wire altpll_0_pll_slave_agent_rdata_fifo_out_valid; // altpll_0_pll_slave_agent_rdata_fifo:out_valid -> avalon_st_adapter_008:in_0_valid
wire [33:0] altpll_0_pll_slave_agent_rdata_fifo_out_data; // altpll_0_pll_slave_agent_rdata_fifo:out_data -> avalon_st_adapter_008:in_0_data
wire altpll_0_pll_slave_agent_rdata_fifo_out_ready; // avalon_st_adapter_008:in_0_ready -> altpll_0_pll_slave_agent_rdata_fifo:out_ready
wire avalon_st_adapter_008_out_0_valid; // avalon_st_adapter_008:out_0_valid -> altpll_0_pll_slave_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_008_out_0_data; // avalon_st_adapter_008:out_0_data -> altpll_0_pll_slave_agent:rdata_fifo_sink_data
wire avalon_st_adapter_008_out_0_ready; // altpll_0_pll_slave_agent:rdata_fifo_sink_ready -> avalon_st_adapter_008:out_0_ready
wire [0:0] avalon_st_adapter_008_out_0_error; // avalon_st_adapter_008:out_0_error -> altpll_0_pll_slave_agent:rdata_fifo_sink_error
wire onchip_memory2_0_s1_agent_rdata_fifo_src_valid; // onchip_memory2_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_009:in_0_valid
wire [33:0] onchip_memory2_0_s1_agent_rdata_fifo_src_data; // onchip_memory2_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_009:in_0_data
wire onchip_memory2_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_009:in_0_ready -> onchip_memory2_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_009_out_0_valid; // avalon_st_adapter_009:out_0_valid -> onchip_memory2_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_009_out_0_data; // avalon_st_adapter_009:out_0_data -> onchip_memory2_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_009_out_0_ready; // onchip_memory2_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_009:out_0_ready
wire [0:0] avalon_st_adapter_009_out_0_error; // avalon_st_adapter_009:out_0_error -> onchip_memory2_0_s1_agent:rdata_fifo_sink_error
wire switches_s1_agent_rdata_fifo_src_valid; // switches_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_010:in_0_valid
wire [33:0] switches_s1_agent_rdata_fifo_src_data; // switches_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_010:in_0_data
wire switches_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_010:in_0_ready -> switches_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_010_out_0_valid; // avalon_st_adapter_010:out_0_valid -> switches_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_010_out_0_data; // avalon_st_adapter_010:out_0_data -> switches_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_010_out_0_ready; // switches_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_010:out_0_ready
wire [0:0] avalon_st_adapter_010_out_0_error; // avalon_st_adapter_010:out_0_error -> switches_s1_agent:rdata_fifo_sink_error
wire leds_s1_agent_rdata_fifo_src_valid; // leds_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_011:in_0_valid
wire [33:0] leds_s1_agent_rdata_fifo_src_data; // leds_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_011:in_0_data
wire leds_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_011:in_0_ready -> leds_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_011_out_0_valid; // avalon_st_adapter_011:out_0_valid -> leds_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_011_out_0_data; // avalon_st_adapter_011:out_0_data -> leds_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_011_out_0_ready; // leds_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_011:out_0_ready
wire [0:0] avalon_st_adapter_011_out_0_error; // avalon_st_adapter_011:out_0_error -> leds_s1_agent:rdata_fifo_sink_error
wire uart_0_s1_agent_rdata_fifo_src_valid; // uart_0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_012:in_0_valid
wire [33:0] uart_0_s1_agent_rdata_fifo_src_data; // uart_0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_012:in_0_data
wire uart_0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_012:in_0_ready -> uart_0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_012_out_0_valid; // avalon_st_adapter_012:out_0_valid -> uart_0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_012_out_0_data; // avalon_st_adapter_012:out_0_data -> uart_0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_012_out_0_ready; // uart_0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_012:out_0_ready
wire [0:0] avalon_st_adapter_012_out_0_error; // avalon_st_adapter_012:out_0_error -> uart_0_s1_agent:rdata_fifo_sink_error
wire hex0_s1_agent_rdata_fifo_src_valid; // hex0_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_013:in_0_valid
wire [33:0] hex0_s1_agent_rdata_fifo_src_data; // hex0_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_013:in_0_data
wire hex0_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_013:in_0_ready -> hex0_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_013_out_0_valid; // avalon_st_adapter_013:out_0_valid -> hex0_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_013_out_0_data; // avalon_st_adapter_013:out_0_data -> hex0_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_013_out_0_ready; // hex0_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_013:out_0_ready
wire [0:0] avalon_st_adapter_013_out_0_error; // avalon_st_adapter_013:out_0_error -> hex0_s1_agent:rdata_fifo_sink_error
wire hex1_s1_agent_rdata_fifo_src_valid; // hex1_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_014:in_0_valid
wire [33:0] hex1_s1_agent_rdata_fifo_src_data; // hex1_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_014:in_0_data
wire hex1_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_014:in_0_ready -> hex1_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_014_out_0_valid; // avalon_st_adapter_014:out_0_valid -> hex1_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_014_out_0_data; // avalon_st_adapter_014:out_0_data -> hex1_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_014_out_0_ready; // hex1_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_014:out_0_ready
wire [0:0] avalon_st_adapter_014_out_0_error; // avalon_st_adapter_014:out_0_error -> hex1_s1_agent:rdata_fifo_sink_error
wire hex2_s1_agent_rdata_fifo_src_valid; // hex2_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_015:in_0_valid
wire [33:0] hex2_s1_agent_rdata_fifo_src_data; // hex2_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_015:in_0_data
wire hex2_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_015:in_0_ready -> hex2_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_015_out_0_valid; // avalon_st_adapter_015:out_0_valid -> hex2_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_015_out_0_data; // avalon_st_adapter_015:out_0_data -> hex2_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_015_out_0_ready; // hex2_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_015:out_0_ready
wire [0:0] avalon_st_adapter_015_out_0_error; // avalon_st_adapter_015:out_0_error -> hex2_s1_agent:rdata_fifo_sink_error
wire hex3_s1_agent_rdata_fifo_src_valid; // hex3_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_016:in_0_valid
wire [33:0] hex3_s1_agent_rdata_fifo_src_data; // hex3_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_016:in_0_data
wire hex3_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_016:in_0_ready -> hex3_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_016_out_0_valid; // avalon_st_adapter_016:out_0_valid -> hex3_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_016_out_0_data; // avalon_st_adapter_016:out_0_data -> hex3_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_016_out_0_ready; // hex3_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_016:out_0_ready
wire [0:0] avalon_st_adapter_016_out_0_error; // avalon_st_adapter_016:out_0_error -> hex3_s1_agent:rdata_fifo_sink_error
wire hex4_s1_agent_rdata_fifo_src_valid; // hex4_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_017:in_0_valid
wire [33:0] hex4_s1_agent_rdata_fifo_src_data; // hex4_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_017:in_0_data
wire hex4_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_017:in_0_ready -> hex4_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_017_out_0_valid; // avalon_st_adapter_017:out_0_valid -> hex4_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_017_out_0_data; // avalon_st_adapter_017:out_0_data -> hex4_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_017_out_0_ready; // hex4_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_017:out_0_ready
wire [0:0] avalon_st_adapter_017_out_0_error; // avalon_st_adapter_017:out_0_error -> hex4_s1_agent:rdata_fifo_sink_error
wire hex5_s1_agent_rdata_fifo_src_valid; // hex5_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_018:in_0_valid
wire [33:0] hex5_s1_agent_rdata_fifo_src_data; // hex5_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_018:in_0_data
wire hex5_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_018:in_0_ready -> hex5_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_018_out_0_valid; // avalon_st_adapter_018:out_0_valid -> hex5_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_018_out_0_data; // avalon_st_adapter_018:out_0_data -> hex5_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_018_out_0_ready; // hex5_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_018:out_0_ready
wire [0:0] avalon_st_adapter_018_out_0_error; // avalon_st_adapter_018:out_0_error -> hex5_s1_agent:rdata_fifo_sink_error
wire hexdot_s1_agent_rdata_fifo_src_valid; // hexdot_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_019:in_0_valid
wire [33:0] hexdot_s1_agent_rdata_fifo_src_data; // hexdot_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_019:in_0_data
wire hexdot_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_019:in_0_ready -> hexdot_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_019_out_0_valid; // avalon_st_adapter_019:out_0_valid -> hexdot_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_019_out_0_data; // avalon_st_adapter_019:out_0_data -> hexdot_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_019_out_0_ready; // hexdot_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_019:out_0_ready
wire [0:0] avalon_st_adapter_019_out_0_error; // avalon_st_adapter_019:out_0_error -> hexdot_s1_agent:rdata_fifo_sink_error
wire spi_sync_s1_agent_rdata_fifo_src_valid; // spi_sync_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_020:in_0_valid
wire [33:0] spi_sync_s1_agent_rdata_fifo_src_data; // spi_sync_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_020:in_0_data
wire spi_sync_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_020:in_0_ready -> spi_sync_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_020_out_0_valid; // avalon_st_adapter_020:out_0_valid -> spi_sync_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_020_out_0_data; // avalon_st_adapter_020:out_0_data -> spi_sync_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_020_out_0_ready; // spi_sync_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_020:out_0_ready
wire [0:0] avalon_st_adapter_020_out_0_error; // avalon_st_adapter_020:out_0_error -> spi_sync_s1_agent:rdata_fifo_sink_error
wire extra_leds_s1_agent_rdata_fifo_src_valid; // extra_leds_s1_agent:rdata_fifo_src_valid -> avalon_st_adapter_021:in_0_valid
wire [33:0] extra_leds_s1_agent_rdata_fifo_src_data; // extra_leds_s1_agent:rdata_fifo_src_data -> avalon_st_adapter_021:in_0_data
wire extra_leds_s1_agent_rdata_fifo_src_ready; // avalon_st_adapter_021:in_0_ready -> extra_leds_s1_agent:rdata_fifo_src_ready
wire avalon_st_adapter_021_out_0_valid; // avalon_st_adapter_021:out_0_valid -> extra_leds_s1_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_021_out_0_data; // avalon_st_adapter_021:out_0_data -> extra_leds_s1_agent:rdata_fifo_sink_data
wire avalon_st_adapter_021_out_0_ready; // extra_leds_s1_agent:rdata_fifo_sink_ready -> avalon_st_adapter_021:out_0_ready
wire [0:0] avalon_st_adapter_021_out_0_error; // avalon_st_adapter_021:out_0_error -> extra_leds_s1_agent:rdata_fifo_sink_error
wire spi_stm32_spi_control_port_agent_rdata_fifo_src_valid; // spi_stm32_spi_control_port_agent:rdata_fifo_src_valid -> avalon_st_adapter_022:in_0_valid
wire [33:0] spi_stm32_spi_control_port_agent_rdata_fifo_src_data; // spi_stm32_spi_control_port_agent:rdata_fifo_src_data -> avalon_st_adapter_022:in_0_data
wire spi_stm32_spi_control_port_agent_rdata_fifo_src_ready; // avalon_st_adapter_022:in_0_ready -> spi_stm32_spi_control_port_agent:rdata_fifo_src_ready
wire avalon_st_adapter_022_out_0_valid; // avalon_st_adapter_022:out_0_valid -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_valid
wire [33:0] avalon_st_adapter_022_out_0_data; // avalon_st_adapter_022:out_0_data -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_data
wire avalon_st_adapter_022_out_0_ready; // spi_stm32_spi_control_port_agent:rdata_fifo_sink_ready -> avalon_st_adapter_022:out_0_ready
wire [0:0] avalon_st_adapter_022_out_0_error; // avalon_st_adapter_022:out_0_error -> spi_stm32_spi_control_port_agent:rdata_fifo_sink_error
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (2),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (1),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (0)
) abus_slave_0_avalon_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_slave_0_avalon_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (abus_slave_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.uav_write (abus_slave_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (abus_slave_0_avalon_master_address), // avalon_anti_master_0.address
.av_waitrequest (abus_slave_0_avalon_master_waitrequest), // .waitrequest
.av_burstcount (abus_slave_0_avalon_master_burstcount), // .burstcount
.av_byteenable (abus_slave_0_avalon_master_byteenable), // .byteenable
.av_read (abus_slave_0_avalon_master_read), // .read
.av_readdata (abus_slave_0_avalon_master_readdata), // .readdata
.av_readdatavalid (abus_slave_0_avalon_master_readdatavalid), // .readdatavalid
.av_write (abus_slave_0_avalon_master_write), // .write
.av_writedata (abus_slave_0_avalon_master_writedata), // .writedata
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (1),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (0),
.AV_REGISTERINCOMINGSIGNALS (1)
) nios2_gen2_0_data_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_data_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_data_master_waitrequest), // .waitrequest
.av_byteenable (nios2_gen2_0_data_master_byteenable), // .byteenable
.av_read (nios2_gen2_0_data_master_read), // .read
.av_readdata (nios2_gen2_0_data_master_readdata), // .readdata
.av_write (nios2_gen2_0_data_master_write), // .write
.av_writedata (nios2_gen2_0_data_master_writedata), // .writedata
.av_debugaccess (nios2_gen2_0_data_master_debugaccess), // .debugaccess
.av_burstcount (1'b1), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_lock (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_translator #(
.AV_ADDRESS_W (28),
.AV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.USE_READ (1),
.USE_WRITE (0),
.USE_BEGINBURSTTRANSFER (0),
.USE_BEGINTRANSFER (0),
.USE_CHIPSELECT (0),
.USE_BURSTCOUNT (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (1),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_LINEWRAPBURSTS (1),
.AV_REGISTERINCOMINGSIGNALS (0)
) nios2_gen2_0_instruction_master_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // avalon_universal_master_0.address
.uav_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.uav_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.uav_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.uav_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_instruction_master_address), // avalon_anti_master_0.address
.av_waitrequest (nios2_gen2_0_instruction_master_waitrequest), // .waitrequest
.av_read (nios2_gen2_0_instruction_master_read), // .read
.av_readdata (nios2_gen2_0_instruction_master_readdata), // .readdata
.av_burstcount (1'b1), // (terminated)
.av_byteenable (4'b1111), // (terminated)
.av_beginbursttransfer (1'b0), // (terminated)
.av_begintransfer (1'b0), // (terminated)
.av_chipselect (1'b0), // (terminated)
.av_readdatavalid (), // (terminated)
.av_write (1'b0), // (terminated)
.av_writedata (32'b00000000000000000000000000000000), // (terminated)
.av_lock (1'b0), // (terminated)
.av_debugaccess (1'b0), // (terminated)
.uav_clken (), // (terminated)
.av_clken (1'b1), // (terminated)
.uav_response (2'b00), // (terminated)
.av_response (), // (terminated)
.uav_writeresponsevalid (1'b0), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (25),
.AV_DATA_W (16),
.UAV_DATA_W (16),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (2),
.UAV_BYTEENABLE_W (2),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (2),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (2),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) external_sdram_controller_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (external_sdram_controller_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (external_sdram_controller_s1_agent_m0_burstcount), // .burstcount
.uav_read (external_sdram_controller_s1_agent_m0_read), // .read
.uav_write (external_sdram_controller_s1_agent_m0_write), // .write
.uav_waitrequest (external_sdram_controller_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (external_sdram_controller_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (external_sdram_controller_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (external_sdram_controller_s1_agent_m0_readdata), // .readdata
.uav_writedata (external_sdram_controller_s1_agent_m0_writedata), // .writedata
.uav_lock (external_sdram_controller_s1_agent_m0_lock), // .lock
.uav_debugaccess (external_sdram_controller_s1_agent_m0_debugaccess), // .debugaccess
.av_address (external_sdram_controller_s1_address), // avalon_anti_slave_0.address
.av_write (external_sdram_controller_s1_write), // .write
.av_read (external_sdram_controller_s1_read), // .read
.av_readdata (external_sdram_controller_s1_readdata), // .readdata
.av_writedata (external_sdram_controller_s1_writedata), // .writedata
.av_byteenable (external_sdram_controller_s1_byteenable), // .byteenable
.av_readdatavalid (external_sdram_controller_s1_readdatavalid), // .readdatavalid
.av_waitrequest (external_sdram_controller_s1_waitrequest), // .waitrequest
.av_chipselect (external_sdram_controller_s1_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (10),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_1_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_1_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_1_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_1_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_1_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_1_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_1_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_1_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_1_s1_write), // .write
.av_readdata (onchip_memory2_1_s1_readdata), // .readdata
.av_writedata (onchip_memory2_1_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_1_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_1_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_1_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_slave_0_avalon_nios_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_slave_0_avalon_nios_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_slave_0_avalon_nios_agent_m0_burstcount), // .burstcount
.uav_read (abus_slave_0_avalon_nios_agent_m0_read), // .read
.uav_write (abus_slave_0_avalon_nios_agent_m0_write), // .write
.uav_waitrequest (abus_slave_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_slave_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_slave_0_avalon_nios_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_slave_0_avalon_nios_agent_m0_readdata), // .readdata
.uav_writedata (abus_slave_0_avalon_nios_agent_m0_writedata), // .writedata
.uav_lock (abus_slave_0_avalon_nios_agent_m0_lock), // .lock
.uav_debugaccess (abus_slave_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.av_address (abus_slave_0_avalon_nios_address), // avalon_anti_slave_0.address
.av_write (abus_slave_0_avalon_nios_write), // .write
.av_read (abus_slave_0_avalon_nios_read), // .read
.av_readdata (abus_slave_0_avalon_nios_readdata), // .readdata
.av_writedata (abus_slave_0_avalon_nios_writedata), // .writedata
.av_burstcount (abus_slave_0_avalon_nios_burstcount), // .burstcount
.av_readdatavalid (abus_slave_0_avalon_nios_readdatavalid), // .readdatavalid
.av_waitrequest (abus_slave_0_avalon_nios_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (8),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) abus_demux_0_avalon_nios_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (abus_demux_0_avalon_nios_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (abus_demux_0_avalon_nios_agent_m0_burstcount), // .burstcount
.uav_read (abus_demux_0_avalon_nios_agent_m0_read), // .read
.uav_write (abus_demux_0_avalon_nios_agent_m0_write), // .write
.uav_waitrequest (abus_demux_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (abus_demux_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (abus_demux_0_avalon_nios_agent_m0_byteenable), // .byteenable
.uav_readdata (abus_demux_0_avalon_nios_agent_m0_readdata), // .readdata
.uav_writedata (abus_demux_0_avalon_nios_agent_m0_writedata), // .writedata
.uav_lock (abus_demux_0_avalon_nios_agent_m0_lock), // .lock
.uav_debugaccess (abus_demux_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.av_address (abus_demux_0_avalon_nios_address), // avalon_anti_slave_0.address
.av_write (abus_demux_0_avalon_nios_write), // .write
.av_read (abus_demux_0_avalon_nios_read), // .read
.av_readdata (abus_demux_0_avalon_nios_readdata), // .readdata
.av_writedata (abus_demux_0_avalon_nios_writedata), // .writedata
.av_burstcount (abus_demux_0_avalon_nios_burstcount), // .burstcount
.av_readdatavalid (abus_demux_0_avalon_nios_readdatavalid), // .readdatavalid
.av_waitrequest (abus_demux_0_avalon_nios_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) performance_counter_0_control_slave_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (performance_counter_0_control_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (performance_counter_0_control_slave_agent_m0_burstcount), // .burstcount
.uav_read (performance_counter_0_control_slave_agent_m0_read), // .read
.uav_write (performance_counter_0_control_slave_agent_m0_write), // .write
.uav_waitrequest (performance_counter_0_control_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (performance_counter_0_control_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (performance_counter_0_control_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (performance_counter_0_control_slave_agent_m0_readdata), // .readdata
.uav_writedata (performance_counter_0_control_slave_agent_m0_writedata), // .writedata
.uav_lock (performance_counter_0_control_slave_agent_m0_lock), // .lock
.uav_debugaccess (performance_counter_0_control_slave_agent_m0_debugaccess), // .debugaccess
.av_address (performance_counter_0_control_slave_address), // avalon_anti_slave_0.address
.av_write (performance_counter_0_control_slave_write), // .write
.av_readdata (performance_counter_0_control_slave_readdata), // .readdata
.av_writedata (performance_counter_0_control_slave_writedata), // .writedata
.av_begintransfer (performance_counter_0_control_slave_begintransfer), // .begintransfer
.av_read (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (1),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_flash_0_csr_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_flash_0_csr_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_flash_0_csr_agent_m0_burstcount), // .burstcount
.uav_read (onchip_flash_0_csr_agent_m0_read), // .read
.uav_write (onchip_flash_0_csr_agent_m0_write), // .write
.uav_waitrequest (onchip_flash_0_csr_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_flash_0_csr_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_flash_0_csr_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_flash_0_csr_agent_m0_readdata), // .readdata
.uav_writedata (onchip_flash_0_csr_agent_m0_writedata), // .writedata
.uav_lock (onchip_flash_0_csr_agent_m0_lock), // .lock
.uav_debugaccess (onchip_flash_0_csr_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_flash_0_csr_address), // avalon_anti_slave_0.address
.av_write (onchip_flash_0_csr_write), // .write
.av_read (onchip_flash_0_csr_read), // .read
.av_readdata (onchip_flash_0_csr_readdata), // .readdata
.av_writedata (onchip_flash_0_csr_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (19),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (4),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (6),
.AV_READLATENCY (0),
.USE_READDATAVALID (1),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_flash_0_data_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_flash_0_data_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.uav_read (onchip_flash_0_data_agent_m0_read), // .read
.uav_write (onchip_flash_0_data_agent_m0_write), // .write
.uav_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.uav_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.uav_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.uav_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_flash_0_data_address), // avalon_anti_slave_0.address
.av_write (onchip_flash_0_data_write), // .write
.av_read (onchip_flash_0_data_read), // .read
.av_readdata (onchip_flash_0_data_readdata), // .readdata
.av_writedata (onchip_flash_0_data_writedata), // .writedata
.av_burstcount (onchip_flash_0_data_burstcount), // .burstcount
.av_readdatavalid (onchip_flash_0_data_readdatavalid), // .readdatavalid
.av_waitrequest (onchip_flash_0_data_waitrequest), // .waitrequest
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_byteenable (), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (9),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (1),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) nios2_gen2_0_debug_mem_slave_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.uav_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.uav_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.uav_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.uav_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.uav_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.uav_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.av_address (nios2_gen2_0_debug_mem_slave_address), // avalon_anti_slave_0.address
.av_write (nios2_gen2_0_debug_mem_slave_write), // .write
.av_read (nios2_gen2_0_debug_mem_slave_read), // .read
.av_readdata (nios2_gen2_0_debug_mem_slave_readdata), // .readdata
.av_writedata (nios2_gen2_0_debug_mem_slave_writedata), // .writedata
.av_byteenable (nios2_gen2_0_debug_mem_slave_byteenable), // .byteenable
.av_waitrequest (nios2_gen2_0_debug_mem_slave_waitrequest), // .waitrequest
.av_debugaccess (nios2_gen2_0_debug_mem_slave_debugaccess), // .debugaccess
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) altpll_0_pll_slave_translator (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (altpll_0_pll_slave_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (altpll_0_pll_slave_agent_m0_burstcount), // .burstcount
.uav_read (altpll_0_pll_slave_agent_m0_read), // .read
.uav_write (altpll_0_pll_slave_agent_m0_write), // .write
.uav_waitrequest (altpll_0_pll_slave_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (altpll_0_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (altpll_0_pll_slave_agent_m0_byteenable), // .byteenable
.uav_readdata (altpll_0_pll_slave_agent_m0_readdata), // .readdata
.uav_writedata (altpll_0_pll_slave_agent_m0_writedata), // .writedata
.uav_lock (altpll_0_pll_slave_agent_m0_lock), // .lock
.uav_debugaccess (altpll_0_pll_slave_agent_m0_debugaccess), // .debugaccess
.av_address (altpll_0_pll_slave_address), // avalon_anti_slave_0.address
.av_write (altpll_0_pll_slave_write), // .write
.av_read (altpll_0_pll_slave_read), // .read
.av_readdata (altpll_0_pll_slave_readdata), // .readdata
.av_writedata (altpll_0_pll_slave_writedata), // .writedata
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (13),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (4),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (1),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (0),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) onchip_memory2_0_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (onchip_memory2_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (onchip_memory2_0_s1_agent_m0_read), // .read
.uav_write (onchip_memory2_0_s1_agent_m0_write), // .write
.uav_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.uav_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (onchip_memory2_0_s1_address), // avalon_anti_slave_0.address
.av_write (onchip_memory2_0_s1_write), // .write
.av_readdata (onchip_memory2_0_s1_readdata), // .readdata
.av_writedata (onchip_memory2_0_s1_writedata), // .writedata
.av_byteenable (onchip_memory2_0_s1_byteenable), // .byteenable
.av_chipselect (onchip_memory2_0_s1_chipselect), // .chipselect
.av_clken (onchip_memory2_0_s1_clken), // .clken
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) switches_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (switches_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.uav_read (switches_s1_agent_m0_read), // .read
.uav_write (switches_s1_agent_m0_write), // .write
.uav_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (switches_s1_agent_m0_readdata), // .readdata
.uav_writedata (switches_s1_agent_m0_writedata), // .writedata
.uav_lock (switches_s1_agent_m0_lock), // .lock
.uav_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.av_address (switches_s1_address), // avalon_anti_slave_0.address
.av_readdata (switches_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) leds_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (leds_s1_agent_m0_read), // .read
.uav_write (leds_s1_agent_m0_write), // .write
.uav_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (leds_s1_agent_m0_writedata), // .writedata
.uav_lock (leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (leds_s1_address), // avalon_anti_slave_0.address
.av_write (leds_s1_write), // .write
.av_readdata (leds_s1_readdata), // .readdata
.av_writedata (leds_s1_writedata), // .writedata
.av_chipselect (leds_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) uart_0_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (uart_0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.uav_read (uart_0_s1_agent_m0_read), // .read
.uav_write (uart_0_s1_agent_m0_write), // .write
.uav_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.uav_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.uav_lock (uart_0_s1_agent_m0_lock), // .lock
.uav_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (uart_0_s1_address), // avalon_anti_slave_0.address
.av_write (uart_0_s1_write), // .write
.av_read (uart_0_s1_read), // .read
.av_readdata (uart_0_s1_readdata), // .readdata
.av_writedata (uart_0_s1_writedata), // .writedata
.av_begintransfer (uart_0_s1_begintransfer), // .begintransfer
.av_chipselect (uart_0_s1_chipselect), // .chipselect
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex0_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex0_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex0_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex0_s1_agent_m0_read), // .read
.uav_write (hex0_s1_agent_m0_write), // .write
.uav_waitrequest (hex0_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex0_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex0_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex0_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex0_s1_agent_m0_writedata), // .writedata
.uav_lock (hex0_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex0_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex0_s1_address), // avalon_anti_slave_0.address
.av_write (hex0_s1_write), // .write
.av_readdata (hex0_s1_readdata), // .readdata
.av_writedata (hex0_s1_writedata), // .writedata
.av_chipselect (hex0_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex1_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex1_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex1_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex1_s1_agent_m0_read), // .read
.uav_write (hex1_s1_agent_m0_write), // .write
.uav_waitrequest (hex1_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex1_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex1_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex1_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex1_s1_agent_m0_writedata), // .writedata
.uav_lock (hex1_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex1_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex1_s1_address), // avalon_anti_slave_0.address
.av_write (hex1_s1_write), // .write
.av_readdata (hex1_s1_readdata), // .readdata
.av_writedata (hex1_s1_writedata), // .writedata
.av_chipselect (hex1_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex2_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex2_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex2_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex2_s1_agent_m0_read), // .read
.uav_write (hex2_s1_agent_m0_write), // .write
.uav_waitrequest (hex2_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex2_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex2_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex2_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex2_s1_agent_m0_writedata), // .writedata
.uav_lock (hex2_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex2_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex2_s1_address), // avalon_anti_slave_0.address
.av_write (hex2_s1_write), // .write
.av_readdata (hex2_s1_readdata), // .readdata
.av_writedata (hex2_s1_writedata), // .writedata
.av_chipselect (hex2_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex3_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex3_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex3_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex3_s1_agent_m0_read), // .read
.uav_write (hex3_s1_agent_m0_write), // .write
.uav_waitrequest (hex3_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex3_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex3_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex3_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex3_s1_agent_m0_writedata), // .writedata
.uav_lock (hex3_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex3_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex3_s1_address), // avalon_anti_slave_0.address
.av_write (hex3_s1_write), // .write
.av_readdata (hex3_s1_readdata), // .readdata
.av_writedata (hex3_s1_writedata), // .writedata
.av_chipselect (hex3_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex4_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex4_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex4_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex4_s1_agent_m0_read), // .read
.uav_write (hex4_s1_agent_m0_write), // .write
.uav_waitrequest (hex4_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex4_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex4_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex4_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex4_s1_agent_m0_writedata), // .writedata
.uav_lock (hex4_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex4_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex4_s1_address), // avalon_anti_slave_0.address
.av_write (hex4_s1_write), // .write
.av_readdata (hex4_s1_readdata), // .readdata
.av_writedata (hex4_s1_writedata), // .writedata
.av_chipselect (hex4_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hex5_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hex5_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hex5_s1_agent_m0_burstcount), // .burstcount
.uav_read (hex5_s1_agent_m0_read), // .read
.uav_write (hex5_s1_agent_m0_write), // .write
.uav_waitrequest (hex5_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hex5_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hex5_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hex5_s1_agent_m0_readdata), // .readdata
.uav_writedata (hex5_s1_agent_m0_writedata), // .writedata
.uav_lock (hex5_s1_agent_m0_lock), // .lock
.uav_debugaccess (hex5_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hex5_s1_address), // avalon_anti_slave_0.address
.av_write (hex5_s1_write), // .write
.av_readdata (hex5_s1_readdata), // .readdata
.av_writedata (hex5_s1_writedata), // .writedata
.av_chipselect (hex5_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) hexdot_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (hexdot_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (hexdot_s1_agent_m0_burstcount), // .burstcount
.uav_read (hexdot_s1_agent_m0_read), // .read
.uav_write (hexdot_s1_agent_m0_write), // .write
.uav_waitrequest (hexdot_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (hexdot_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (hexdot_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (hexdot_s1_agent_m0_readdata), // .readdata
.uav_writedata (hexdot_s1_agent_m0_writedata), // .writedata
.uav_lock (hexdot_s1_agent_m0_lock), // .lock
.uav_debugaccess (hexdot_s1_agent_m0_debugaccess), // .debugaccess
.av_address (hexdot_s1_address), // avalon_anti_slave_0.address
.av_write (hexdot_s1_write), // .write
.av_readdata (hexdot_s1_readdata), // .readdata
.av_writedata (hexdot_s1_writedata), // .writedata
.av_chipselect (hexdot_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) spi_sync_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (spi_sync_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (spi_sync_s1_agent_m0_burstcount), // .burstcount
.uav_read (spi_sync_s1_agent_m0_read), // .read
.uav_write (spi_sync_s1_agent_m0_write), // .write
.uav_waitrequest (spi_sync_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (spi_sync_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (spi_sync_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (spi_sync_s1_agent_m0_readdata), // .readdata
.uav_writedata (spi_sync_s1_agent_m0_writedata), // .writedata
.uav_lock (spi_sync_s1_agent_m0_lock), // .lock
.uav_debugaccess (spi_sync_s1_agent_m0_debugaccess), // .debugaccess
.av_address (spi_sync_s1_address), // avalon_anti_slave_0.address
.av_readdata (spi_sync_s1_readdata), // .readdata
.av_write (), // (terminated)
.av_read (), // (terminated)
.av_writedata (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_chipselect (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (2),
.AV_DATA_W (32),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (0),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) extra_leds_s1_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (extra_leds_s1_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (extra_leds_s1_agent_m0_burstcount), // .burstcount
.uav_read (extra_leds_s1_agent_m0_read), // .read
.uav_write (extra_leds_s1_agent_m0_write), // .write
.uav_waitrequest (extra_leds_s1_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (extra_leds_s1_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (extra_leds_s1_agent_m0_byteenable), // .byteenable
.uav_readdata (extra_leds_s1_agent_m0_readdata), // .readdata
.uav_writedata (extra_leds_s1_agent_m0_writedata), // .writedata
.uav_lock (extra_leds_s1_agent_m0_lock), // .lock
.uav_debugaccess (extra_leds_s1_agent_m0_debugaccess), // .debugaccess
.av_address (extra_leds_s1_address), // avalon_anti_slave_0.address
.av_write (extra_leds_s1_write), // .write
.av_readdata (extra_leds_s1_readdata), // .readdata
.av_writedata (extra_leds_s1_writedata), // .writedata
.av_chipselect (extra_leds_s1_chipselect), // .chipselect
.av_read (), // (terminated)
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_slave_translator #(
.AV_ADDRESS_W (3),
.AV_DATA_W (16),
.UAV_DATA_W (32),
.AV_BURSTCOUNT_W (1),
.AV_BYTEENABLE_W (1),
.UAV_BYTEENABLE_W (4),
.UAV_ADDRESS_W (28),
.UAV_BURSTCOUNT_W (3),
.AV_READLATENCY (0),
.USE_READDATAVALID (0),
.USE_WAITREQUEST (0),
.USE_UAV_CLKEN (0),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.AV_SYMBOLS_PER_WORD (4),
.AV_ADDRESS_SYMBOLS (0),
.AV_BURSTCOUNT_SYMBOLS (0),
.AV_CONSTANT_BURST_BEHAVIOR (0),
.UAV_CONSTANT_BURST_BEHAVIOR (0),
.AV_REQUIRE_UNALIGNED_ADDRESSES (0),
.CHIPSELECT_THROUGH_READLATENCY (0),
.AV_READ_WAIT_CYCLES (1),
.AV_WRITE_WAIT_CYCLES (1),
.AV_SETUP_WAIT_CYCLES (0),
.AV_DATA_HOLD_CYCLES (0)
) spi_stm32_spi_control_port_translator (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // reset.reset
.uav_address (spi_stm32_spi_control_port_agent_m0_address), // avalon_universal_slave_0.address
.uav_burstcount (spi_stm32_spi_control_port_agent_m0_burstcount), // .burstcount
.uav_read (spi_stm32_spi_control_port_agent_m0_read), // .read
.uav_write (spi_stm32_spi_control_port_agent_m0_write), // .write
.uav_waitrequest (spi_stm32_spi_control_port_agent_m0_waitrequest), // .waitrequest
.uav_readdatavalid (spi_stm32_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.uav_byteenable (spi_stm32_spi_control_port_agent_m0_byteenable), // .byteenable
.uav_readdata (spi_stm32_spi_control_port_agent_m0_readdata), // .readdata
.uav_writedata (spi_stm32_spi_control_port_agent_m0_writedata), // .writedata
.uav_lock (spi_stm32_spi_control_port_agent_m0_lock), // .lock
.uav_debugaccess (spi_stm32_spi_control_port_agent_m0_debugaccess), // .debugaccess
.av_address (spi_stm32_spi_control_port_address), // avalon_anti_slave_0.address
.av_write (spi_stm32_spi_control_port_write), // .write
.av_read (spi_stm32_spi_control_port_read), // .read
.av_readdata (spi_stm32_spi_control_port_readdata), // .readdata
.av_writedata (spi_stm32_spi_control_port_writedata), // .writedata
.av_chipselect (spi_stm32_spi_control_port_chipselect), // .chipselect
.av_begintransfer (), // (terminated)
.av_beginbursttransfer (), // (terminated)
.av_burstcount (), // (terminated)
.av_byteenable (), // (terminated)
.av_readdatavalid (1'b0), // (terminated)
.av_waitrequest (1'b0), // (terminated)
.av_writebyteenable (), // (terminated)
.av_lock (), // (terminated)
.av_clken (), // (terminated)
.uav_clken (1'b0), // (terminated)
.av_debugaccess (), // (terminated)
.av_outputenable (), // (terminated)
.uav_response (), // (terminated)
.av_response (2'b00), // (terminated)
.uav_writeresponsevalid (), // (terminated)
.av_writeresponsevalid (1'b0) // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (92),
.PKT_ORI_BURST_SIZE_L (90),
.PKT_RESPONSE_STATUS_H (89),
.PKT_RESPONSE_STATUS_L (88),
.PKT_QOS_H (69),
.PKT_QOS_L (69),
.PKT_DATA_SIDEBAND_H (67),
.PKT_DATA_SIDEBAND_L (67),
.PKT_ADDR_SIDEBAND_H (66),
.PKT_ADDR_SIDEBAND_L (66),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_CACHE_H (87),
.PKT_CACHE_L (84),
.PKT_THREAD_ID_H (80),
.PKT_THREAD_ID_L (80),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_EXCLUSIVE (51),
.PKT_TRANS_LOCK (50),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (83),
.PKT_PROTECTION_L (81),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (79),
.PKT_DEST_ID_L (75),
.ST_DATA_W (93),
.ST_CHANNEL_W (23),
.AV_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_RSP (1),
.ID (0),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) abus_slave_0_avalon_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (abus_slave_0_avalon_master_translator_avalon_universal_master_0_address), // av.address
.av_write (abus_slave_0_avalon_master_translator_avalon_universal_master_0_write), // .write
.av_read (abus_slave_0_avalon_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (abus_slave_0_avalon_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (abus_slave_0_avalon_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (abus_slave_0_avalon_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (abus_slave_0_avalon_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (abus_slave_0_avalon_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (abus_slave_0_avalon_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (abus_slave_0_avalon_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (abus_slave_0_avalon_master_agent_cp_valid), // cp.valid
.cp_data (abus_slave_0_avalon_master_agent_cp_data), // .data
.cp_startofpacket (abus_slave_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (abus_slave_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (abus_slave_0_avalon_master_agent_cp_ready), // .ready
.rp_valid (abus_slave_0_avalon_master_limiter_rsp_src_valid), // rp.valid
.rp_data (abus_slave_0_avalon_master_limiter_rsp_src_data), // .data
.rp_channel (abus_slave_0_avalon_master_limiter_rsp_src_channel), // .channel
.rp_startofpacket (abus_slave_0_avalon_master_limiter_rsp_src_startofpacket), // .startofpacket
.rp_endofpacket (abus_slave_0_avalon_master_limiter_rsp_src_endofpacket), // .endofpacket
.rp_ready (abus_slave_0_avalon_master_limiter_rsp_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (105),
.PKT_CACHE_L (102),
.PKT_THREAD_ID_H (98),
.PKT_THREAD_ID_L (98),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (69),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.ST_DATA_W (111),
.ST_CHANNEL_W (23),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (1),
.BURSTWRAP_VALUE (7),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_data_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_data_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_data_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_data_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_data_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_data_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_data_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_data_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_data_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_data_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_data_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_data_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_001_src_valid), // rp.valid
.rp_data (rsp_mux_001_src_data), // .data
.rp_channel (rsp_mux_001_src_channel), // .channel
.rp_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_001_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_master_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_QOS_H (87),
.PKT_QOS_L (87),
.PKT_DATA_SIDEBAND_H (85),
.PKT_DATA_SIDEBAND_L (85),
.PKT_ADDR_SIDEBAND_H (84),
.PKT_ADDR_SIDEBAND_L (84),
.PKT_BURST_TYPE_H (83),
.PKT_BURST_TYPE_L (82),
.PKT_CACHE_H (105),
.PKT_CACHE_L (102),
.PKT_THREAD_ID_H (98),
.PKT_THREAD_ID_L (98),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_EXCLUSIVE (69),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.ST_DATA_W (111),
.ST_CHANNEL_W (23),
.AV_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_RSP (0),
.ID (2),
.BURSTWRAP_VALUE (3),
.CACHE_VALUE (0),
.SECURE_ACCESS_BIT (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0)
) nios2_gen2_0_instruction_master_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.av_address (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_address), // av.address
.av_write (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_write), // .write
.av_read (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_read), // .read
.av_writedata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_writedata), // .writedata
.av_readdata (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdata), // .readdata
.av_waitrequest (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_waitrequest), // .waitrequest
.av_readdatavalid (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_readdatavalid), // .readdatavalid
.av_byteenable (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_byteenable), // .byteenable
.av_burstcount (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_burstcount), // .burstcount
.av_debugaccess (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_debugaccess), // .debugaccess
.av_lock (nios2_gen2_0_instruction_master_translator_avalon_universal_master_0_lock), // .lock
.cp_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // cp.valid
.cp_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.cp_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.cp_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.cp_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // .ready
.rp_valid (rsp_mux_002_src_valid), // rp.valid
.rp_data (rsp_mux_002_src_data), // .data
.rp_channel (rsp_mux_002_src_channel), // .channel
.rp_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.rp_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.rp_ready (rsp_mux_002_src_ready), // .ready
.av_response (), // (terminated)
.av_writeresponsevalid () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (92),
.PKT_ORI_BURST_SIZE_L (90),
.PKT_RESPONSE_STATUS_H (89),
.PKT_RESPONSE_STATUS_L (88),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_TRANS_LOCK (50),
.PKT_BEGIN_BURST (68),
.PKT_PROTECTION_H (83),
.PKT_PROTECTION_L (81),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.PKT_DATA_H (15),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (70),
.PKT_DEST_ID_H (79),
.PKT_DEST_ID_L (75),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (93),
.AVS_BURSTCOUNT_W (2),
.SUPPRESS_0_BYTEEN_CMD (1),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) external_sdram_controller_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (external_sdram_controller_s1_agent_m0_address), // m0.address
.m0_burstcount (external_sdram_controller_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (external_sdram_controller_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (external_sdram_controller_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (external_sdram_controller_s1_agent_m0_lock), // .lock
.m0_readdata (external_sdram_controller_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (external_sdram_controller_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (external_sdram_controller_s1_agent_m0_read), // .read
.m0_waitrequest (external_sdram_controller_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (external_sdram_controller_s1_agent_m0_writedata), // .writedata
.m0_write (external_sdram_controller_s1_agent_m0_write), // .write
.rp_endofpacket (external_sdram_controller_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (external_sdram_controller_s1_agent_rp_ready), // .ready
.rp_valid (external_sdram_controller_s1_agent_rp_valid), // .valid
.rp_data (external_sdram_controller_s1_agent_rp_data), // .data
.rp_startofpacket (external_sdram_controller_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (external_sdram_controller_s1_burst_adapter_source0_ready), // cp.ready
.cp_valid (external_sdram_controller_s1_burst_adapter_source0_valid), // .valid
.cp_data (external_sdram_controller_s1_burst_adapter_source0_data), // .data
.cp_startofpacket (external_sdram_controller_s1_burst_adapter_source0_startofpacket), // .startofpacket
.cp_endofpacket (external_sdram_controller_s1_burst_adapter_source0_endofpacket), // .endofpacket
.cp_channel (external_sdram_controller_s1_burst_adapter_source0_channel), // .channel
.rf_sink_ready (external_sdram_controller_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (external_sdram_controller_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (external_sdram_controller_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (external_sdram_controller_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (external_sdram_controller_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (external_sdram_controller_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (external_sdram_controller_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (external_sdram_controller_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_out_0_error), // .error
.rdata_fifo_src_ready (external_sdram_controller_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (external_sdram_controller_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (external_sdram_controller_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (94),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) external_sdram_controller_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (external_sdram_controller_s1_agent_rf_source_data), // in.data
.in_valid (external_sdram_controller_s1_agent_rf_source_valid), // .valid
.in_ready (external_sdram_controller_s1_agent_rf_source_ready), // .ready
.in_startofpacket (external_sdram_controller_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (external_sdram_controller_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (external_sdram_controller_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (external_sdram_controller_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (external_sdram_controller_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (external_sdram_controller_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (18),
.FIFO_DEPTH (8),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (3),
.USE_MEMORY_BLOCKS (1),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) external_sdram_controller_s1_agent_rdata_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (external_sdram_controller_s1_agent_rdata_fifo_src_data), // in.data
.in_valid (external_sdram_controller_s1_agent_rdata_fifo_src_valid), // .valid
.in_ready (external_sdram_controller_s1_agent_rdata_fifo_src_ready), // .ready
.out_data (external_sdram_controller_s1_agent_rdata_fifo_out_data), // out.data
.out_valid (external_sdram_controller_s1_agent_rdata_fifo_out_valid), // .valid
.out_ready (external_sdram_controller_s1_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_1_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_1_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_1_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_1_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_1_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_1_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_1_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_1_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_1_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_001_src_ready), // cp.ready
.cp_valid (cmd_mux_001_src_valid), // .valid
.cp_data (cmd_mux_001_src_data), // .data
.cp_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_001_src_channel), // .channel
.rf_sink_ready (onchip_memory2_1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_001_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_001_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_001_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_001_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_1_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_1_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_1_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_slave_0_avalon_nios_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_slave_0_avalon_nios_agent_m0_address), // m0.address
.m0_burstcount (abus_slave_0_avalon_nios_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_slave_0_avalon_nios_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_slave_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_slave_0_avalon_nios_agent_m0_lock), // .lock
.m0_readdata (abus_slave_0_avalon_nios_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_slave_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_slave_0_avalon_nios_agent_m0_read), // .read
.m0_waitrequest (abus_slave_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_slave_0_avalon_nios_agent_m0_writedata), // .writedata
.m0_write (abus_slave_0_avalon_nios_agent_m0_write), // .write
.rp_endofpacket (abus_slave_0_avalon_nios_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_slave_0_avalon_nios_agent_rp_ready), // .ready
.rp_valid (abus_slave_0_avalon_nios_agent_rp_valid), // .valid
.rp_data (abus_slave_0_avalon_nios_agent_rp_data), // .data
.rp_startofpacket (abus_slave_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_002_src_ready), // cp.ready
.cp_valid (cmd_mux_002_src_valid), // .valid
.cp_data (cmd_mux_002_src_data), // .data
.cp_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_002_src_channel), // .channel
.rf_sink_ready (abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_slave_0_avalon_nios_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_slave_0_avalon_nios_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_slave_0_avalon_nios_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_slave_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_slave_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_slave_0_avalon_nios_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_002_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_002_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_002_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_002_out_0_error), // .error
.rdata_fifo_src_ready (abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_slave_0_avalon_nios_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_slave_0_avalon_nios_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_slave_0_avalon_nios_agent_rf_source_data), // in.data
.in_valid (abus_slave_0_avalon_nios_agent_rf_source_valid), // .valid
.in_ready (abus_slave_0_avalon_nios_agent_rf_source_ready), // .ready
.in_startofpacket (abus_slave_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_slave_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_slave_0_avalon_nios_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_slave_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_slave_0_avalon_nios_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_slave_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_slave_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) abus_demux_0_avalon_nios_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (abus_demux_0_avalon_nios_agent_m0_address), // m0.address
.m0_burstcount (abus_demux_0_avalon_nios_agent_m0_burstcount), // .burstcount
.m0_byteenable (abus_demux_0_avalon_nios_agent_m0_byteenable), // .byteenable
.m0_debugaccess (abus_demux_0_avalon_nios_agent_m0_debugaccess), // .debugaccess
.m0_lock (abus_demux_0_avalon_nios_agent_m0_lock), // .lock
.m0_readdata (abus_demux_0_avalon_nios_agent_m0_readdata), // .readdata
.m0_readdatavalid (abus_demux_0_avalon_nios_agent_m0_readdatavalid), // .readdatavalid
.m0_read (abus_demux_0_avalon_nios_agent_m0_read), // .read
.m0_waitrequest (abus_demux_0_avalon_nios_agent_m0_waitrequest), // .waitrequest
.m0_writedata (abus_demux_0_avalon_nios_agent_m0_writedata), // .writedata
.m0_write (abus_demux_0_avalon_nios_agent_m0_write), // .write
.rp_endofpacket (abus_demux_0_avalon_nios_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (abus_demux_0_avalon_nios_agent_rp_ready), // .ready
.rp_valid (abus_demux_0_avalon_nios_agent_rp_valid), // .valid
.rp_data (abus_demux_0_avalon_nios_agent_rp_data), // .data
.rp_startofpacket (abus_demux_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_003_src_ready), // cp.ready
.cp_valid (cmd_mux_003_src_valid), // .valid
.cp_data (cmd_mux_003_src_data), // .data
.cp_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_003_src_channel), // .channel
.rf_sink_ready (abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (abus_demux_0_avalon_nios_agent_rsp_fifo_out_data), // .data
.rf_source_ready (abus_demux_0_avalon_nios_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (abus_demux_0_avalon_nios_agent_rf_source_valid), // .valid
.rf_source_startofpacket (abus_demux_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (abus_demux_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (abus_demux_0_avalon_nios_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_003_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_003_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_003_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_003_out_0_error), // .error
.rdata_fifo_src_ready (abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (abus_demux_0_avalon_nios_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) abus_demux_0_avalon_nios_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (abus_demux_0_avalon_nios_agent_rf_source_data), // in.data
.in_valid (abus_demux_0_avalon_nios_agent_rf_source_valid), // .valid
.in_ready (abus_demux_0_avalon_nios_agent_rf_source_ready), // .ready
.in_startofpacket (abus_demux_0_avalon_nios_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (abus_demux_0_avalon_nios_agent_rf_source_endofpacket), // .endofpacket
.out_data (abus_demux_0_avalon_nios_agent_rsp_fifo_out_data), // out.data
.out_valid (abus_demux_0_avalon_nios_agent_rsp_fifo_out_valid), // .valid
.out_ready (abus_demux_0_avalon_nios_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (abus_demux_0_avalon_nios_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (abus_demux_0_avalon_nios_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) performance_counter_0_control_slave_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (performance_counter_0_control_slave_agent_m0_address), // m0.address
.m0_burstcount (performance_counter_0_control_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (performance_counter_0_control_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (performance_counter_0_control_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (performance_counter_0_control_slave_agent_m0_lock), // .lock
.m0_readdata (performance_counter_0_control_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (performance_counter_0_control_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (performance_counter_0_control_slave_agent_m0_read), // .read
.m0_waitrequest (performance_counter_0_control_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (performance_counter_0_control_slave_agent_m0_writedata), // .writedata
.m0_write (performance_counter_0_control_slave_agent_m0_write), // .write
.rp_endofpacket (performance_counter_0_control_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (performance_counter_0_control_slave_agent_rp_ready), // .ready
.rp_valid (performance_counter_0_control_slave_agent_rp_valid), // .valid
.rp_data (performance_counter_0_control_slave_agent_rp_data), // .data
.rp_startofpacket (performance_counter_0_control_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_004_src_ready), // cp.ready
.cp_valid (cmd_mux_004_src_valid), // .valid
.cp_data (cmd_mux_004_src_data), // .data
.cp_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_004_src_channel), // .channel
.rf_sink_ready (performance_counter_0_control_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (performance_counter_0_control_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (performance_counter_0_control_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (performance_counter_0_control_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (performance_counter_0_control_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (performance_counter_0_control_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (performance_counter_0_control_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (performance_counter_0_control_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_004_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_004_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_004_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_004_out_0_error), // .error
.rdata_fifo_src_ready (performance_counter_0_control_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (performance_counter_0_control_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (performance_counter_0_control_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) performance_counter_0_control_slave_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (performance_counter_0_control_slave_agent_rf_source_data), // in.data
.in_valid (performance_counter_0_control_slave_agent_rf_source_valid), // .valid
.in_ready (performance_counter_0_control_slave_agent_rf_source_ready), // .ready
.in_startofpacket (performance_counter_0_control_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (performance_counter_0_control_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (performance_counter_0_control_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (performance_counter_0_control_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (performance_counter_0_control_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (performance_counter_0_control_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_flash_0_csr_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_flash_0_csr_agent_m0_address), // m0.address
.m0_burstcount (onchip_flash_0_csr_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_flash_0_csr_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_flash_0_csr_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_flash_0_csr_agent_m0_lock), // .lock
.m0_readdata (onchip_flash_0_csr_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_flash_0_csr_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_flash_0_csr_agent_m0_read), // .read
.m0_waitrequest (onchip_flash_0_csr_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_flash_0_csr_agent_m0_writedata), // .writedata
.m0_write (onchip_flash_0_csr_agent_m0_write), // .write
.rp_endofpacket (onchip_flash_0_csr_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_flash_0_csr_agent_rp_ready), // .ready
.rp_valid (onchip_flash_0_csr_agent_rp_valid), // .valid
.rp_data (onchip_flash_0_csr_agent_rp_data), // .data
.rp_startofpacket (onchip_flash_0_csr_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_005_src_ready), // cp.ready
.cp_valid (cmd_mux_005_src_valid), // .valid
.cp_data (cmd_mux_005_src_data), // .data
.cp_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_005_src_channel), // .channel
.rf_sink_ready (onchip_flash_0_csr_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_flash_0_csr_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_flash_0_csr_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_flash_0_csr_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_flash_0_csr_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_flash_0_csr_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_flash_0_csr_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_flash_0_csr_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_005_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_005_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_005_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_005_out_0_error), // .error
.rdata_fifo_src_ready (onchip_flash_0_csr_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_flash_0_csr_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_flash_0_csr_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_flash_0_csr_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_flash_0_csr_agent_rf_source_data), // in.data
.in_valid (onchip_flash_0_csr_agent_rf_source_valid), // .valid
.in_ready (onchip_flash_0_csr_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_flash_0_csr_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_flash_0_csr_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_flash_0_csr_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_flash_0_csr_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_flash_0_csr_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_flash_0_csr_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_flash_0_csr_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (6),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_flash_0_data_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_flash_0_data_agent_m0_address), // m0.address
.m0_burstcount (onchip_flash_0_data_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_flash_0_data_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_flash_0_data_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_flash_0_data_agent_m0_lock), // .lock
.m0_readdata (onchip_flash_0_data_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_flash_0_data_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_flash_0_data_agent_m0_read), // .read
.m0_waitrequest (onchip_flash_0_data_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_flash_0_data_agent_m0_writedata), // .writedata
.m0_write (onchip_flash_0_data_agent_m0_write), // .write
.rp_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_flash_0_data_agent_rp_ready), // .ready
.rp_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.rp_data (onchip_flash_0_data_agent_rp_data), // .data
.rp_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_006_src_ready), // cp.ready
.cp_valid (cmd_mux_006_src_valid), // .valid
.cp_data (cmd_mux_006_src_data), // .data
.cp_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_006_src_channel), // .channel
.rf_sink_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_flash_0_data_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_flash_0_data_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_006_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_006_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_006_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_006_out_0_error), // .error
.rdata_fifo_src_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_flash_0_data_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_flash_0_data_agent_rf_source_data), // in.data
.in_valid (onchip_flash_0_data_agent_rf_source_valid), // .valid
.in_ready (onchip_flash_0_data_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_flash_0_data_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_flash_0_data_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_flash_0_data_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_flash_0_data_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_flash_0_data_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_flash_0_data_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_flash_0_data_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) nios2_gen2_0_debug_mem_slave_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (nios2_gen2_0_debug_mem_slave_agent_m0_address), // m0.address
.m0_burstcount (nios2_gen2_0_debug_mem_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (nios2_gen2_0_debug_mem_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (nios2_gen2_0_debug_mem_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (nios2_gen2_0_debug_mem_slave_agent_m0_lock), // .lock
.m0_readdata (nios2_gen2_0_debug_mem_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (nios2_gen2_0_debug_mem_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (nios2_gen2_0_debug_mem_slave_agent_m0_read), // .read
.m0_waitrequest (nios2_gen2_0_debug_mem_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (nios2_gen2_0_debug_mem_slave_agent_m0_writedata), // .writedata
.m0_write (nios2_gen2_0_debug_mem_slave_agent_m0_write), // .write
.rp_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // .ready
.rp_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.rp_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.rp_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_007_src_ready), // cp.ready
.cp_valid (cmd_mux_007_src_valid), // .valid
.cp_data (cmd_mux_007_src_data), // .data
.cp_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_007_src_channel), // .channel
.rf_sink_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_007_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_007_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_007_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_007_out_0_error), // .error
.rdata_fifo_src_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) nios2_gen2_0_debug_mem_slave_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (nios2_gen2_0_debug_mem_slave_agent_rf_source_data), // in.data
.in_valid (nios2_gen2_0_debug_mem_slave_agent_rf_source_valid), // .valid
.in_ready (nios2_gen2_0_debug_mem_slave_agent_rf_source_ready), // .ready
.in_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) altpll_0_pll_slave_agent (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (altpll_0_pll_slave_agent_m0_address), // m0.address
.m0_burstcount (altpll_0_pll_slave_agent_m0_burstcount), // .burstcount
.m0_byteenable (altpll_0_pll_slave_agent_m0_byteenable), // .byteenable
.m0_debugaccess (altpll_0_pll_slave_agent_m0_debugaccess), // .debugaccess
.m0_lock (altpll_0_pll_slave_agent_m0_lock), // .lock
.m0_readdata (altpll_0_pll_slave_agent_m0_readdata), // .readdata
.m0_readdatavalid (altpll_0_pll_slave_agent_m0_readdatavalid), // .readdatavalid
.m0_read (altpll_0_pll_slave_agent_m0_read), // .read
.m0_waitrequest (altpll_0_pll_slave_agent_m0_waitrequest), // .waitrequest
.m0_writedata (altpll_0_pll_slave_agent_m0_writedata), // .writedata
.m0_write (altpll_0_pll_slave_agent_m0_write), // .write
.rp_endofpacket (altpll_0_pll_slave_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (altpll_0_pll_slave_agent_rp_ready), // .ready
.rp_valid (altpll_0_pll_slave_agent_rp_valid), // .valid
.rp_data (altpll_0_pll_slave_agent_rp_data), // .data
.rp_startofpacket (altpll_0_pll_slave_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_008_src_ready), // cp.ready
.cp_valid (cmd_mux_008_src_valid), // .valid
.cp_data (cmd_mux_008_src_data), // .data
.cp_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_008_src_channel), // .channel
.rf_sink_ready (altpll_0_pll_slave_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (altpll_0_pll_slave_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (altpll_0_pll_slave_agent_rsp_fifo_out_data), // .data
.rf_source_ready (altpll_0_pll_slave_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (altpll_0_pll_slave_agent_rf_source_valid), // .valid
.rf_source_startofpacket (altpll_0_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (altpll_0_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (altpll_0_pll_slave_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_008_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_008_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_008_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_008_out_0_error), // .error
.rdata_fifo_src_ready (altpll_0_pll_slave_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (altpll_0_pll_slave_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (altpll_0_pll_slave_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_agent_rsp_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_agent_rf_source_data), // in.data
.in_valid (altpll_0_pll_slave_agent_rf_source_valid), // .valid
.in_ready (altpll_0_pll_slave_agent_rf_source_ready), // .ready
.in_startofpacket (altpll_0_pll_slave_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (altpll_0_pll_slave_agent_rf_source_endofpacket), // .endofpacket
.out_data (altpll_0_pll_slave_agent_rsp_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_agent_rsp_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (altpll_0_pll_slave_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (34),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (0),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (0),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) altpll_0_pll_slave_agent_rdata_fifo (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (altpll_0_pll_slave_agent_rdata_fifo_src_data), // in.data
.in_valid (altpll_0_pll_slave_agent_rdata_fifo_src_valid), // .valid
.in_ready (altpll_0_pll_slave_agent_rdata_fifo_src_ready), // .ready
.out_data (altpll_0_pll_slave_agent_rdata_fifo_out_data), // out.data
.out_valid (altpll_0_pll_slave_agent_rdata_fifo_out_valid), // .valid
.out_ready (altpll_0_pll_slave_agent_rdata_fifo_out_ready), // .ready
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_startofpacket (1'b0), // (terminated)
.in_endofpacket (1'b0), // (terminated)
.out_startofpacket (), // (terminated)
.out_endofpacket (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) onchip_memory2_0_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (onchip_memory2_0_s1_agent_m0_address), // m0.address
.m0_burstcount (onchip_memory2_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (onchip_memory2_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (onchip_memory2_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (onchip_memory2_0_s1_agent_m0_lock), // .lock
.m0_readdata (onchip_memory2_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (onchip_memory2_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (onchip_memory2_0_s1_agent_m0_read), // .read
.m0_waitrequest (onchip_memory2_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (onchip_memory2_0_s1_agent_m0_writedata), // .writedata
.m0_write (onchip_memory2_0_s1_agent_m0_write), // .write
.rp_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (onchip_memory2_0_s1_agent_rp_ready), // .ready
.rp_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.rp_data (onchip_memory2_0_s1_agent_rp_data), // .data
.rp_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_009_src_ready), // cp.ready
.cp_valid (cmd_mux_009_src_valid), // .valid
.cp_data (cmd_mux_009_src_data), // .data
.cp_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_009_src_channel), // .channel
.rf_sink_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (onchip_memory2_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (onchip_memory2_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_009_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_009_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_009_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_009_out_0_error), // .error
.rdata_fifo_src_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) onchip_memory2_0_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (onchip_memory2_0_s1_agent_rf_source_data), // in.data
.in_valid (onchip_memory2_0_s1_agent_rf_source_valid), // .valid
.in_ready (onchip_memory2_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (onchip_memory2_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (onchip_memory2_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (onchip_memory2_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (onchip_memory2_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (onchip_memory2_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (onchip_memory2_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) switches_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (switches_s1_agent_m0_address), // m0.address
.m0_burstcount (switches_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (switches_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (switches_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (switches_s1_agent_m0_lock), // .lock
.m0_readdata (switches_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (switches_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (switches_s1_agent_m0_read), // .read
.m0_waitrequest (switches_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (switches_s1_agent_m0_writedata), // .writedata
.m0_write (switches_s1_agent_m0_write), // .write
.rp_endofpacket (switches_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (switches_s1_agent_rp_ready), // .ready
.rp_valid (switches_s1_agent_rp_valid), // .valid
.rp_data (switches_s1_agent_rp_data), // .data
.rp_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_010_src_ready), // cp.ready
.cp_valid (cmd_mux_010_src_valid), // .valid
.cp_data (cmd_mux_010_src_data), // .data
.cp_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_010_src_channel), // .channel
.rf_sink_ready (switches_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (switches_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (switches_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (switches_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (switches_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_010_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_010_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_010_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_010_out_0_error), // .error
.rdata_fifo_src_ready (switches_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (switches_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) switches_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (switches_s1_agent_rf_source_data), // in.data
.in_valid (switches_s1_agent_rf_source_valid), // .valid
.in_ready (switches_s1_agent_rf_source_ready), // .ready
.in_startofpacket (switches_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (switches_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (switches_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (switches_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (switches_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (switches_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (switches_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) leds_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (leds_s1_agent_m0_address), // m0.address
.m0_burstcount (leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (leds_s1_agent_m0_lock), // .lock
.m0_readdata (leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (leds_s1_agent_m0_read), // .read
.m0_waitrequest (leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (leds_s1_agent_m0_writedata), // .writedata
.m0_write (leds_s1_agent_m0_write), // .write
.rp_endofpacket (leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (leds_s1_agent_rp_ready), // .ready
.rp_valid (leds_s1_agent_rp_valid), // .valid
.rp_data (leds_s1_agent_rp_data), // .data
.rp_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_011_src_ready), // cp.ready
.cp_valid (cmd_mux_011_src_valid), // .valid
.cp_data (cmd_mux_011_src_data), // .data
.cp_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_011_src_channel), // .channel
.rf_sink_ready (leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_011_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_011_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_011_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_011_out_0_error), // .error
.rdata_fifo_src_ready (leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) leds_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (leds_s1_agent_rf_source_data), // in.data
.in_valid (leds_s1_agent_rf_source_valid), // .valid
.in_ready (leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) uart_0_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (uart_0_s1_agent_m0_address), // m0.address
.m0_burstcount (uart_0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (uart_0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (uart_0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (uart_0_s1_agent_m0_lock), // .lock
.m0_readdata (uart_0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (uart_0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (uart_0_s1_agent_m0_read), // .read
.m0_waitrequest (uart_0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (uart_0_s1_agent_m0_writedata), // .writedata
.m0_write (uart_0_s1_agent_m0_write), // .write
.rp_endofpacket (uart_0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (uart_0_s1_agent_rp_ready), // .ready
.rp_valid (uart_0_s1_agent_rp_valid), // .valid
.rp_data (uart_0_s1_agent_rp_data), // .data
.rp_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_012_src_ready), // cp.ready
.cp_valid (cmd_mux_012_src_valid), // .valid
.cp_data (cmd_mux_012_src_data), // .data
.cp_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_012_src_channel), // .channel
.rf_sink_ready (uart_0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (uart_0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (uart_0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (uart_0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (uart_0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_012_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_012_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_012_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_012_out_0_error), // .error
.rdata_fifo_src_ready (uart_0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (uart_0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) uart_0_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (uart_0_s1_agent_rf_source_data), // in.data
.in_valid (uart_0_s1_agent_rf_source_valid), // .valid
.in_ready (uart_0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (uart_0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (uart_0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (uart_0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (uart_0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (uart_0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (uart_0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (uart_0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex0_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex0_s1_agent_m0_address), // m0.address
.m0_burstcount (hex0_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex0_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex0_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex0_s1_agent_m0_lock), // .lock
.m0_readdata (hex0_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex0_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex0_s1_agent_m0_read), // .read
.m0_waitrequest (hex0_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex0_s1_agent_m0_writedata), // .writedata
.m0_write (hex0_s1_agent_m0_write), // .write
.rp_endofpacket (hex0_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex0_s1_agent_rp_ready), // .ready
.rp_valid (hex0_s1_agent_rp_valid), // .valid
.rp_data (hex0_s1_agent_rp_data), // .data
.rp_startofpacket (hex0_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_013_src_ready), // cp.ready
.cp_valid (cmd_mux_013_src_valid), // .valid
.cp_data (cmd_mux_013_src_data), // .data
.cp_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_013_src_channel), // .channel
.rf_sink_ready (hex0_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex0_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex0_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex0_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex0_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex0_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex0_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex0_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_013_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_013_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_013_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_013_out_0_error), // .error
.rdata_fifo_src_ready (hex0_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex0_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex0_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex0_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex0_s1_agent_rf_source_data), // in.data
.in_valid (hex0_s1_agent_rf_source_valid), // .valid
.in_ready (hex0_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex0_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex0_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex0_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex0_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex0_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex0_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex0_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex1_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex1_s1_agent_m0_address), // m0.address
.m0_burstcount (hex1_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex1_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex1_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex1_s1_agent_m0_lock), // .lock
.m0_readdata (hex1_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex1_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex1_s1_agent_m0_read), // .read
.m0_waitrequest (hex1_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex1_s1_agent_m0_writedata), // .writedata
.m0_write (hex1_s1_agent_m0_write), // .write
.rp_endofpacket (hex1_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex1_s1_agent_rp_ready), // .ready
.rp_valid (hex1_s1_agent_rp_valid), // .valid
.rp_data (hex1_s1_agent_rp_data), // .data
.rp_startofpacket (hex1_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_014_src_ready), // cp.ready
.cp_valid (cmd_mux_014_src_valid), // .valid
.cp_data (cmd_mux_014_src_data), // .data
.cp_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_014_src_channel), // .channel
.rf_sink_ready (hex1_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex1_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex1_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex1_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex1_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex1_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex1_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex1_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_014_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_014_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_014_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_014_out_0_error), // .error
.rdata_fifo_src_ready (hex1_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex1_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex1_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex1_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex1_s1_agent_rf_source_data), // in.data
.in_valid (hex1_s1_agent_rf_source_valid), // .valid
.in_ready (hex1_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex1_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex1_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex1_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex1_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex1_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex1_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex1_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex2_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex2_s1_agent_m0_address), // m0.address
.m0_burstcount (hex2_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex2_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex2_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex2_s1_agent_m0_lock), // .lock
.m0_readdata (hex2_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex2_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex2_s1_agent_m0_read), // .read
.m0_waitrequest (hex2_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex2_s1_agent_m0_writedata), // .writedata
.m0_write (hex2_s1_agent_m0_write), // .write
.rp_endofpacket (hex2_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex2_s1_agent_rp_ready), // .ready
.rp_valid (hex2_s1_agent_rp_valid), // .valid
.rp_data (hex2_s1_agent_rp_data), // .data
.rp_startofpacket (hex2_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_015_src_ready), // cp.ready
.cp_valid (cmd_mux_015_src_valid), // .valid
.cp_data (cmd_mux_015_src_data), // .data
.cp_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_015_src_channel), // .channel
.rf_sink_ready (hex2_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex2_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex2_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex2_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex2_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex2_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex2_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex2_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_015_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_015_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_015_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_015_out_0_error), // .error
.rdata_fifo_src_ready (hex2_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex2_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex2_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex2_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex2_s1_agent_rf_source_data), // in.data
.in_valid (hex2_s1_agent_rf_source_valid), // .valid
.in_ready (hex2_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex2_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex2_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex2_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex2_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex2_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex2_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex2_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex3_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex3_s1_agent_m0_address), // m0.address
.m0_burstcount (hex3_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex3_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex3_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex3_s1_agent_m0_lock), // .lock
.m0_readdata (hex3_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex3_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex3_s1_agent_m0_read), // .read
.m0_waitrequest (hex3_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex3_s1_agent_m0_writedata), // .writedata
.m0_write (hex3_s1_agent_m0_write), // .write
.rp_endofpacket (hex3_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex3_s1_agent_rp_ready), // .ready
.rp_valid (hex3_s1_agent_rp_valid), // .valid
.rp_data (hex3_s1_agent_rp_data), // .data
.rp_startofpacket (hex3_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_016_src_ready), // cp.ready
.cp_valid (cmd_mux_016_src_valid), // .valid
.cp_data (cmd_mux_016_src_data), // .data
.cp_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_016_src_channel), // .channel
.rf_sink_ready (hex3_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex3_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex3_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex3_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex3_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex3_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex3_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex3_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_016_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_016_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_016_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_016_out_0_error), // .error
.rdata_fifo_src_ready (hex3_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex3_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex3_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex3_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex3_s1_agent_rf_source_data), // in.data
.in_valid (hex3_s1_agent_rf_source_valid), // .valid
.in_ready (hex3_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex3_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex3_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex3_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex3_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex3_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex3_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex3_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex4_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex4_s1_agent_m0_address), // m0.address
.m0_burstcount (hex4_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex4_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex4_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex4_s1_agent_m0_lock), // .lock
.m0_readdata (hex4_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex4_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex4_s1_agent_m0_read), // .read
.m0_waitrequest (hex4_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex4_s1_agent_m0_writedata), // .writedata
.m0_write (hex4_s1_agent_m0_write), // .write
.rp_endofpacket (hex4_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex4_s1_agent_rp_ready), // .ready
.rp_valid (hex4_s1_agent_rp_valid), // .valid
.rp_data (hex4_s1_agent_rp_data), // .data
.rp_startofpacket (hex4_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_017_src_ready), // cp.ready
.cp_valid (cmd_mux_017_src_valid), // .valid
.cp_data (cmd_mux_017_src_data), // .data
.cp_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_017_src_channel), // .channel
.rf_sink_ready (hex4_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex4_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex4_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex4_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex4_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex4_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex4_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex4_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_017_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_017_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_017_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_017_out_0_error), // .error
.rdata_fifo_src_ready (hex4_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex4_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex4_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex4_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex4_s1_agent_rf_source_data), // in.data
.in_valid (hex4_s1_agent_rf_source_valid), // .valid
.in_ready (hex4_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex4_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex4_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex4_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex4_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex4_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex4_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex4_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hex5_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hex5_s1_agent_m0_address), // m0.address
.m0_burstcount (hex5_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hex5_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hex5_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hex5_s1_agent_m0_lock), // .lock
.m0_readdata (hex5_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hex5_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hex5_s1_agent_m0_read), // .read
.m0_waitrequest (hex5_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hex5_s1_agent_m0_writedata), // .writedata
.m0_write (hex5_s1_agent_m0_write), // .write
.rp_endofpacket (hex5_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hex5_s1_agent_rp_ready), // .ready
.rp_valid (hex5_s1_agent_rp_valid), // .valid
.rp_data (hex5_s1_agent_rp_data), // .data
.rp_startofpacket (hex5_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_018_src_ready), // cp.ready
.cp_valid (cmd_mux_018_src_valid), // .valid
.cp_data (cmd_mux_018_src_data), // .data
.cp_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_018_src_channel), // .channel
.rf_sink_ready (hex5_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hex5_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hex5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hex5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hex5_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hex5_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hex5_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hex5_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hex5_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hex5_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_018_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_018_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_018_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_018_out_0_error), // .error
.rdata_fifo_src_ready (hex5_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hex5_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hex5_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hex5_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hex5_s1_agent_rf_source_data), // in.data
.in_valid (hex5_s1_agent_rf_source_valid), // .valid
.in_ready (hex5_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hex5_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hex5_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hex5_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hex5_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hex5_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hex5_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hex5_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) hexdot_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (hexdot_s1_agent_m0_address), // m0.address
.m0_burstcount (hexdot_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (hexdot_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (hexdot_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (hexdot_s1_agent_m0_lock), // .lock
.m0_readdata (hexdot_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (hexdot_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (hexdot_s1_agent_m0_read), // .read
.m0_waitrequest (hexdot_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (hexdot_s1_agent_m0_writedata), // .writedata
.m0_write (hexdot_s1_agent_m0_write), // .write
.rp_endofpacket (hexdot_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (hexdot_s1_agent_rp_ready), // .ready
.rp_valid (hexdot_s1_agent_rp_valid), // .valid
.rp_data (hexdot_s1_agent_rp_data), // .data
.rp_startofpacket (hexdot_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_019_src_ready), // cp.ready
.cp_valid (cmd_mux_019_src_valid), // .valid
.cp_data (cmd_mux_019_src_data), // .data
.cp_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_019_src_channel), // .channel
.rf_sink_ready (hexdot_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (hexdot_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (hexdot_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (hexdot_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (hexdot_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (hexdot_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (hexdot_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (hexdot_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (hexdot_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (hexdot_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_019_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_019_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_019_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_019_out_0_error), // .error
.rdata_fifo_src_ready (hexdot_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (hexdot_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (hexdot_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) hexdot_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (hexdot_s1_agent_rf_source_data), // in.data
.in_valid (hexdot_s1_agent_rf_source_valid), // .valid
.in_ready (hexdot_s1_agent_rf_source_ready), // .ready
.in_startofpacket (hexdot_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (hexdot_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (hexdot_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (hexdot_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (hexdot_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (hexdot_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (hexdot_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) spi_sync_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (spi_sync_s1_agent_m0_address), // m0.address
.m0_burstcount (spi_sync_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (spi_sync_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (spi_sync_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (spi_sync_s1_agent_m0_lock), // .lock
.m0_readdata (spi_sync_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (spi_sync_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (spi_sync_s1_agent_m0_read), // .read
.m0_waitrequest (spi_sync_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (spi_sync_s1_agent_m0_writedata), // .writedata
.m0_write (spi_sync_s1_agent_m0_write), // .write
.rp_endofpacket (spi_sync_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (spi_sync_s1_agent_rp_ready), // .ready
.rp_valid (spi_sync_s1_agent_rp_valid), // .valid
.rp_data (spi_sync_s1_agent_rp_data), // .data
.rp_startofpacket (spi_sync_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_020_src_ready), // cp.ready
.cp_valid (cmd_mux_020_src_valid), // .valid
.cp_data (cmd_mux_020_src_data), // .data
.cp_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_020_src_channel), // .channel
.rf_sink_ready (spi_sync_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (spi_sync_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (spi_sync_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (spi_sync_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (spi_sync_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (spi_sync_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (spi_sync_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (spi_sync_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (spi_sync_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (spi_sync_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_020_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_020_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_020_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_020_out_0_error), // .error
.rdata_fifo_src_ready (spi_sync_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (spi_sync_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (spi_sync_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) spi_sync_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (spi_sync_s1_agent_rf_source_data), // in.data
.in_valid (spi_sync_s1_agent_rf_source_valid), // .valid
.in_ready (spi_sync_s1_agent_rf_source_ready), // .ready
.in_startofpacket (spi_sync_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (spi_sync_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (spi_sync_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (spi_sync_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (spi_sync_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (spi_sync_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (spi_sync_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) extra_leds_s1_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (extra_leds_s1_agent_m0_address), // m0.address
.m0_burstcount (extra_leds_s1_agent_m0_burstcount), // .burstcount
.m0_byteenable (extra_leds_s1_agent_m0_byteenable), // .byteenable
.m0_debugaccess (extra_leds_s1_agent_m0_debugaccess), // .debugaccess
.m0_lock (extra_leds_s1_agent_m0_lock), // .lock
.m0_readdata (extra_leds_s1_agent_m0_readdata), // .readdata
.m0_readdatavalid (extra_leds_s1_agent_m0_readdatavalid), // .readdatavalid
.m0_read (extra_leds_s1_agent_m0_read), // .read
.m0_waitrequest (extra_leds_s1_agent_m0_waitrequest), // .waitrequest
.m0_writedata (extra_leds_s1_agent_m0_writedata), // .writedata
.m0_write (extra_leds_s1_agent_m0_write), // .write
.rp_endofpacket (extra_leds_s1_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (extra_leds_s1_agent_rp_ready), // .ready
.rp_valid (extra_leds_s1_agent_rp_valid), // .valid
.rp_data (extra_leds_s1_agent_rp_data), // .data
.rp_startofpacket (extra_leds_s1_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_021_src_ready), // cp.ready
.cp_valid (cmd_mux_021_src_valid), // .valid
.cp_data (cmd_mux_021_src_data), // .data
.cp_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_021_src_channel), // .channel
.rf_sink_ready (extra_leds_s1_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (extra_leds_s1_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (extra_leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (extra_leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (extra_leds_s1_agent_rsp_fifo_out_data), // .data
.rf_source_ready (extra_leds_s1_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (extra_leds_s1_agent_rf_source_valid), // .valid
.rf_source_startofpacket (extra_leds_s1_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (extra_leds_s1_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (extra_leds_s1_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_021_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_021_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_021_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_021_out_0_error), // .error
.rdata_fifo_src_ready (extra_leds_s1_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (extra_leds_s1_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (extra_leds_s1_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) extra_leds_s1_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (extra_leds_s1_agent_rf_source_data), // in.data
.in_valid (extra_leds_s1_agent_rf_source_valid), // .valid
.in_ready (extra_leds_s1_agent_rf_source_ready), // .ready
.in_startofpacket (extra_leds_s1_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (extra_leds_s1_agent_rf_source_endofpacket), // .endofpacket
.out_data (extra_leds_s1_agent_rsp_fifo_out_data), // out.data
.out_valid (extra_leds_s1_agent_rsp_fifo_out_valid), // .valid
.out_ready (extra_leds_s1_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (extra_leds_s1_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (extra_leds_s1_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
altera_merlin_slave_agent #(
.PKT_ORI_BURST_SIZE_H (110),
.PKT_ORI_BURST_SIZE_L (108),
.PKT_RESPONSE_STATUS_H (107),
.PKT_RESPONSE_STATUS_L (106),
.PKT_BURST_SIZE_H (81),
.PKT_BURST_SIZE_L (79),
.PKT_TRANS_LOCK (68),
.PKT_BEGIN_BURST (86),
.PKT_PROTECTION_H (101),
.PKT_PROTECTION_L (99),
.PKT_BURSTWRAP_H (78),
.PKT_BURSTWRAP_L (76),
.PKT_BYTE_CNT_H (75),
.PKT_BYTE_CNT_L (70),
.PKT_ADDR_H (63),
.PKT_ADDR_L (36),
.PKT_TRANS_COMPRESSED_READ (64),
.PKT_TRANS_POSTED (65),
.PKT_TRANS_WRITE (66),
.PKT_TRANS_READ (67),
.PKT_DATA_H (31),
.PKT_DATA_L (0),
.PKT_BYTEEN_H (35),
.PKT_BYTEEN_L (32),
.PKT_SRC_ID_H (92),
.PKT_SRC_ID_L (88),
.PKT_DEST_ID_H (97),
.PKT_DEST_ID_L (93),
.PKT_SYMBOL_W (8),
.ST_CHANNEL_W (23),
.ST_DATA_W (111),
.AVS_BURSTCOUNT_W (3),
.SUPPRESS_0_BYTEEN_CMD (0),
.PREVENT_FIFO_OVERFLOW (1),
.USE_READRESPONSE (0),
.USE_WRITERESPONSE (0),
.ECC_ENABLE (0)
) spi_stm32_spi_control_port_agent (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.m0_address (spi_stm32_spi_control_port_agent_m0_address), // m0.address
.m0_burstcount (spi_stm32_spi_control_port_agent_m0_burstcount), // .burstcount
.m0_byteenable (spi_stm32_spi_control_port_agent_m0_byteenable), // .byteenable
.m0_debugaccess (spi_stm32_spi_control_port_agent_m0_debugaccess), // .debugaccess
.m0_lock (spi_stm32_spi_control_port_agent_m0_lock), // .lock
.m0_readdata (spi_stm32_spi_control_port_agent_m0_readdata), // .readdata
.m0_readdatavalid (spi_stm32_spi_control_port_agent_m0_readdatavalid), // .readdatavalid
.m0_read (spi_stm32_spi_control_port_agent_m0_read), // .read
.m0_waitrequest (spi_stm32_spi_control_port_agent_m0_waitrequest), // .waitrequest
.m0_writedata (spi_stm32_spi_control_port_agent_m0_writedata), // .writedata
.m0_write (spi_stm32_spi_control_port_agent_m0_write), // .write
.rp_endofpacket (spi_stm32_spi_control_port_agent_rp_endofpacket), // rp.endofpacket
.rp_ready (spi_stm32_spi_control_port_agent_rp_ready), // .ready
.rp_valid (spi_stm32_spi_control_port_agent_rp_valid), // .valid
.rp_data (spi_stm32_spi_control_port_agent_rp_data), // .data
.rp_startofpacket (spi_stm32_spi_control_port_agent_rp_startofpacket), // .startofpacket
.cp_ready (cmd_mux_022_src_ready), // cp.ready
.cp_valid (cmd_mux_022_src_valid), // .valid
.cp_data (cmd_mux_022_src_data), // .data
.cp_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.cp_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.cp_channel (cmd_mux_022_src_channel), // .channel
.rf_sink_ready (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready), // rf_sink.ready
.rf_sink_valid (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.rf_sink_startofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.rf_sink_endofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.rf_sink_data (spi_stm32_spi_control_port_agent_rsp_fifo_out_data), // .data
.rf_source_ready (spi_stm32_spi_control_port_agent_rf_source_ready), // rf_source.ready
.rf_source_valid (spi_stm32_spi_control_port_agent_rf_source_valid), // .valid
.rf_source_startofpacket (spi_stm32_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.rf_source_endofpacket (spi_stm32_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.rf_source_data (spi_stm32_spi_control_port_agent_rf_source_data), // .data
.rdata_fifo_sink_ready (avalon_st_adapter_022_out_0_ready), // rdata_fifo_sink.ready
.rdata_fifo_sink_valid (avalon_st_adapter_022_out_0_valid), // .valid
.rdata_fifo_sink_data (avalon_st_adapter_022_out_0_data), // .data
.rdata_fifo_sink_error (avalon_st_adapter_022_out_0_error), // .error
.rdata_fifo_src_ready (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready), // rdata_fifo_src.ready
.rdata_fifo_src_valid (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.rdata_fifo_src_data (spi_stm32_spi_control_port_agent_rdata_fifo_src_data), // .data
.m0_response (2'b00), // (terminated)
.m0_writeresponsevalid (1'b0) // (terminated)
);
altera_avalon_sc_fifo #(
.SYMBOLS_PER_BEAT (1),
.BITS_PER_SYMBOL (112),
.FIFO_DEPTH (2),
.CHANNEL_WIDTH (0),
.ERROR_WIDTH (0),
.USE_PACKETS (1),
.USE_FILL_LEVEL (0),
.EMPTY_LATENCY (1),
.USE_MEMORY_BLOCKS (0),
.USE_STORE_FORWARD (0),
.USE_ALMOST_FULL_IF (0),
.USE_ALMOST_EMPTY_IF (0)
) spi_stm32_spi_control_port_agent_rsp_fifo (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_data (spi_stm32_spi_control_port_agent_rf_source_data), // in.data
.in_valid (spi_stm32_spi_control_port_agent_rf_source_valid), // .valid
.in_ready (spi_stm32_spi_control_port_agent_rf_source_ready), // .ready
.in_startofpacket (spi_stm32_spi_control_port_agent_rf_source_startofpacket), // .startofpacket
.in_endofpacket (spi_stm32_spi_control_port_agent_rf_source_endofpacket), // .endofpacket
.out_data (spi_stm32_spi_control_port_agent_rsp_fifo_out_data), // out.data
.out_valid (spi_stm32_spi_control_port_agent_rsp_fifo_out_valid), // .valid
.out_ready (spi_stm32_spi_control_port_agent_rsp_fifo_out_ready), // .ready
.out_startofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_startofpacket), // .startofpacket
.out_endofpacket (spi_stm32_spi_control_port_agent_rsp_fifo_out_endofpacket), // .endofpacket
.csr_address (2'b00), // (terminated)
.csr_read (1'b0), // (terminated)
.csr_write (1'b0), // (terminated)
.csr_readdata (), // (terminated)
.csr_writedata (32'b00000000000000000000000000000000), // (terminated)
.almost_full_data (), // (terminated)
.almost_empty_data (), // (terminated)
.in_empty (1'b0), // (terminated)
.out_empty (), // (terminated)
.in_error (1'b0), // (terminated)
.out_error (), // (terminated)
.in_channel (1'b0), // (terminated)
.out_channel () // (terminated)
);
wasca_mm_interconnect_0_router router (
.sink_ready (abus_slave_0_avalon_master_agent_cp_ready), // sink.ready
.sink_valid (abus_slave_0_avalon_master_agent_cp_valid), // .valid
.sink_data (abus_slave_0_avalon_master_agent_cp_data), // .data
.sink_startofpacket (abus_slave_0_avalon_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (abus_slave_0_avalon_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_src_ready), // src.ready
.src_valid (router_src_valid), // .valid
.src_data (router_src_data), // .data
.src_channel (router_src_channel), // .channel
.src_startofpacket (router_src_startofpacket), // .startofpacket
.src_endofpacket (router_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_001 router_001 (
.sink_ready (nios2_gen2_0_data_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_data_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_data_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_data_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_data_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_001_src_ready), // src.ready
.src_valid (router_001_src_valid), // .valid
.src_data (router_001_src_data), // .data
.src_channel (router_001_src_channel), // .channel
.src_startofpacket (router_001_src_startofpacket), // .startofpacket
.src_endofpacket (router_001_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_002 router_002 (
.sink_ready (nios2_gen2_0_instruction_master_agent_cp_ready), // sink.ready
.sink_valid (nios2_gen2_0_instruction_master_agent_cp_valid), // .valid
.sink_data (nios2_gen2_0_instruction_master_agent_cp_data), // .data
.sink_startofpacket (nios2_gen2_0_instruction_master_agent_cp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_instruction_master_agent_cp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_002_src_ready), // src.ready
.src_valid (router_002_src_valid), // .valid
.src_data (router_002_src_data), // .data
.src_channel (router_002_src_channel), // .channel
.src_startofpacket (router_002_src_startofpacket), // .startofpacket
.src_endofpacket (router_002_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_003 router_003 (
.sink_ready (external_sdram_controller_s1_agent_rp_ready), // sink.ready
.sink_valid (external_sdram_controller_s1_agent_rp_valid), // .valid
.sink_data (external_sdram_controller_s1_agent_rp_data), // .data
.sink_startofpacket (external_sdram_controller_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (external_sdram_controller_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_003_src_ready), // src.ready
.src_valid (router_003_src_valid), // .valid
.src_data (router_003_src_data), // .data
.src_channel (router_003_src_channel), // .channel
.src_startofpacket (router_003_src_startofpacket), // .startofpacket
.src_endofpacket (router_003_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_004 router_004 (
.sink_ready (onchip_memory2_1_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_1_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_1_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_1_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_004_src_ready), // src.ready
.src_valid (router_004_src_valid), // .valid
.src_data (router_004_src_data), // .data
.src_channel (router_004_src_channel), // .channel
.src_startofpacket (router_004_src_startofpacket), // .startofpacket
.src_endofpacket (router_004_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_005 (
.sink_ready (abus_slave_0_avalon_nios_agent_rp_ready), // sink.ready
.sink_valid (abus_slave_0_avalon_nios_agent_rp_valid), // .valid
.sink_data (abus_slave_0_avalon_nios_agent_rp_data), // .data
.sink_startofpacket (abus_slave_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_slave_0_avalon_nios_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_005_src_ready), // src.ready
.src_valid (router_005_src_valid), // .valid
.src_data (router_005_src_data), // .data
.src_channel (router_005_src_channel), // .channel
.src_startofpacket (router_005_src_startofpacket), // .startofpacket
.src_endofpacket (router_005_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_006 (
.sink_ready (abus_demux_0_avalon_nios_agent_rp_ready), // sink.ready
.sink_valid (abus_demux_0_avalon_nios_agent_rp_valid), // .valid
.sink_data (abus_demux_0_avalon_nios_agent_rp_data), // .data
.sink_startofpacket (abus_demux_0_avalon_nios_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (abus_demux_0_avalon_nios_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_006_src_ready), // src.ready
.src_valid (router_006_src_valid), // .valid
.src_data (router_006_src_data), // .data
.src_channel (router_006_src_channel), // .channel
.src_startofpacket (router_006_src_startofpacket), // .startofpacket
.src_endofpacket (router_006_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_007 (
.sink_ready (performance_counter_0_control_slave_agent_rp_ready), // sink.ready
.sink_valid (performance_counter_0_control_slave_agent_rp_valid), // .valid
.sink_data (performance_counter_0_control_slave_agent_rp_data), // .data
.sink_startofpacket (performance_counter_0_control_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (performance_counter_0_control_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_007_src_ready), // src.ready
.src_valid (router_007_src_valid), // .valid
.src_data (router_007_src_data), // .data
.src_channel (router_007_src_channel), // .channel
.src_startofpacket (router_007_src_startofpacket), // .startofpacket
.src_endofpacket (router_007_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_008 (
.sink_ready (onchip_flash_0_csr_agent_rp_ready), // sink.ready
.sink_valid (onchip_flash_0_csr_agent_rp_valid), // .valid
.sink_data (onchip_flash_0_csr_agent_rp_data), // .data
.sink_startofpacket (onchip_flash_0_csr_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_flash_0_csr_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_008_src_ready), // src.ready
.src_valid (router_008_src_valid), // .valid
.src_data (router_008_src_data), // .data
.src_channel (router_008_src_channel), // .channel
.src_startofpacket (router_008_src_startofpacket), // .startofpacket
.src_endofpacket (router_008_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_009 router_009 (
.sink_ready (onchip_flash_0_data_agent_rp_ready), // sink.ready
.sink_valid (onchip_flash_0_data_agent_rp_valid), // .valid
.sink_data (onchip_flash_0_data_agent_rp_data), // .data
.sink_startofpacket (onchip_flash_0_data_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_flash_0_data_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_009_src_ready), // src.ready
.src_valid (router_009_src_valid), // .valid
.src_data (router_009_src_data), // .data
.src_channel (router_009_src_channel), // .channel
.src_startofpacket (router_009_src_startofpacket), // .startofpacket
.src_endofpacket (router_009_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_009 router_010 (
.sink_ready (nios2_gen2_0_debug_mem_slave_agent_rp_ready), // sink.ready
.sink_valid (nios2_gen2_0_debug_mem_slave_agent_rp_valid), // .valid
.sink_data (nios2_gen2_0_debug_mem_slave_agent_rp_data), // .data
.sink_startofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (nios2_gen2_0_debug_mem_slave_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_010_src_ready), // src.ready
.src_valid (router_010_src_valid), // .valid
.src_data (router_010_src_data), // .data
.src_channel (router_010_src_channel), // .channel
.src_startofpacket (router_010_src_startofpacket), // .startofpacket
.src_endofpacket (router_010_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_011 (
.sink_ready (altpll_0_pll_slave_agent_rp_ready), // sink.ready
.sink_valid (altpll_0_pll_slave_agent_rp_valid), // .valid
.sink_data (altpll_0_pll_slave_agent_rp_data), // .data
.sink_startofpacket (altpll_0_pll_slave_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (altpll_0_pll_slave_agent_rp_endofpacket), // .endofpacket
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_011_src_ready), // src.ready
.src_valid (router_011_src_valid), // .valid
.src_data (router_011_src_data), // .data
.src_channel (router_011_src_channel), // .channel
.src_startofpacket (router_011_src_startofpacket), // .startofpacket
.src_endofpacket (router_011_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_009 router_012 (
.sink_ready (onchip_memory2_0_s1_agent_rp_ready), // sink.ready
.sink_valid (onchip_memory2_0_s1_agent_rp_valid), // .valid
.sink_data (onchip_memory2_0_s1_agent_rp_data), // .data
.sink_startofpacket (onchip_memory2_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (onchip_memory2_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_012_src_ready), // src.ready
.src_valid (router_012_src_valid), // .valid
.src_data (router_012_src_data), // .data
.src_channel (router_012_src_channel), // .channel
.src_startofpacket (router_012_src_startofpacket), // .startofpacket
.src_endofpacket (router_012_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_013 (
.sink_ready (switches_s1_agent_rp_ready), // sink.ready
.sink_valid (switches_s1_agent_rp_valid), // .valid
.sink_data (switches_s1_agent_rp_data), // .data
.sink_startofpacket (switches_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (switches_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_013_src_ready), // src.ready
.src_valid (router_013_src_valid), // .valid
.src_data (router_013_src_data), // .data
.src_channel (router_013_src_channel), // .channel
.src_startofpacket (router_013_src_startofpacket), // .startofpacket
.src_endofpacket (router_013_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_014 (
.sink_ready (leds_s1_agent_rp_ready), // sink.ready
.sink_valid (leds_s1_agent_rp_valid), // .valid
.sink_data (leds_s1_agent_rp_data), // .data
.sink_startofpacket (leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_014_src_ready), // src.ready
.src_valid (router_014_src_valid), // .valid
.src_data (router_014_src_data), // .data
.src_channel (router_014_src_channel), // .channel
.src_startofpacket (router_014_src_startofpacket), // .startofpacket
.src_endofpacket (router_014_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_015 (
.sink_ready (uart_0_s1_agent_rp_ready), // sink.ready
.sink_valid (uart_0_s1_agent_rp_valid), // .valid
.sink_data (uart_0_s1_agent_rp_data), // .data
.sink_startofpacket (uart_0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (uart_0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_015_src_ready), // src.ready
.src_valid (router_015_src_valid), // .valid
.src_data (router_015_src_data), // .data
.src_channel (router_015_src_channel), // .channel
.src_startofpacket (router_015_src_startofpacket), // .startofpacket
.src_endofpacket (router_015_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_016 (
.sink_ready (hex0_s1_agent_rp_ready), // sink.ready
.sink_valid (hex0_s1_agent_rp_valid), // .valid
.sink_data (hex0_s1_agent_rp_data), // .data
.sink_startofpacket (hex0_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex0_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_016_src_ready), // src.ready
.src_valid (router_016_src_valid), // .valid
.src_data (router_016_src_data), // .data
.src_channel (router_016_src_channel), // .channel
.src_startofpacket (router_016_src_startofpacket), // .startofpacket
.src_endofpacket (router_016_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_017 (
.sink_ready (hex1_s1_agent_rp_ready), // sink.ready
.sink_valid (hex1_s1_agent_rp_valid), // .valid
.sink_data (hex1_s1_agent_rp_data), // .data
.sink_startofpacket (hex1_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex1_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_017_src_ready), // src.ready
.src_valid (router_017_src_valid), // .valid
.src_data (router_017_src_data), // .data
.src_channel (router_017_src_channel), // .channel
.src_startofpacket (router_017_src_startofpacket), // .startofpacket
.src_endofpacket (router_017_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_018 (
.sink_ready (hex2_s1_agent_rp_ready), // sink.ready
.sink_valid (hex2_s1_agent_rp_valid), // .valid
.sink_data (hex2_s1_agent_rp_data), // .data
.sink_startofpacket (hex2_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex2_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_018_src_ready), // src.ready
.src_valid (router_018_src_valid), // .valid
.src_data (router_018_src_data), // .data
.src_channel (router_018_src_channel), // .channel
.src_startofpacket (router_018_src_startofpacket), // .startofpacket
.src_endofpacket (router_018_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_019 (
.sink_ready (hex3_s1_agent_rp_ready), // sink.ready
.sink_valid (hex3_s1_agent_rp_valid), // .valid
.sink_data (hex3_s1_agent_rp_data), // .data
.sink_startofpacket (hex3_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex3_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_019_src_ready), // src.ready
.src_valid (router_019_src_valid), // .valid
.src_data (router_019_src_data), // .data
.src_channel (router_019_src_channel), // .channel
.src_startofpacket (router_019_src_startofpacket), // .startofpacket
.src_endofpacket (router_019_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_020 (
.sink_ready (hex4_s1_agent_rp_ready), // sink.ready
.sink_valid (hex4_s1_agent_rp_valid), // .valid
.sink_data (hex4_s1_agent_rp_data), // .data
.sink_startofpacket (hex4_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex4_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_020_src_ready), // src.ready
.src_valid (router_020_src_valid), // .valid
.src_data (router_020_src_data), // .data
.src_channel (router_020_src_channel), // .channel
.src_startofpacket (router_020_src_startofpacket), // .startofpacket
.src_endofpacket (router_020_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_021 (
.sink_ready (hex5_s1_agent_rp_ready), // sink.ready
.sink_valid (hex5_s1_agent_rp_valid), // .valid
.sink_data (hex5_s1_agent_rp_data), // .data
.sink_startofpacket (hex5_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hex5_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_021_src_ready), // src.ready
.src_valid (router_021_src_valid), // .valid
.src_data (router_021_src_data), // .data
.src_channel (router_021_src_channel), // .channel
.src_startofpacket (router_021_src_startofpacket), // .startofpacket
.src_endofpacket (router_021_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_022 (
.sink_ready (hexdot_s1_agent_rp_ready), // sink.ready
.sink_valid (hexdot_s1_agent_rp_valid), // .valid
.sink_data (hexdot_s1_agent_rp_data), // .data
.sink_startofpacket (hexdot_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (hexdot_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_022_src_ready), // src.ready
.src_valid (router_022_src_valid), // .valid
.src_data (router_022_src_data), // .data
.src_channel (router_022_src_channel), // .channel
.src_startofpacket (router_022_src_startofpacket), // .startofpacket
.src_endofpacket (router_022_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_023 (
.sink_ready (spi_sync_s1_agent_rp_ready), // sink.ready
.sink_valid (spi_sync_s1_agent_rp_valid), // .valid
.sink_data (spi_sync_s1_agent_rp_data), // .data
.sink_startofpacket (spi_sync_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (spi_sync_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_023_src_ready), // src.ready
.src_valid (router_023_src_valid), // .valid
.src_data (router_023_src_data), // .data
.src_channel (router_023_src_channel), // .channel
.src_startofpacket (router_023_src_startofpacket), // .startofpacket
.src_endofpacket (router_023_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_024 (
.sink_ready (extra_leds_s1_agent_rp_ready), // sink.ready
.sink_valid (extra_leds_s1_agent_rp_valid), // .valid
.sink_data (extra_leds_s1_agent_rp_data), // .data
.sink_startofpacket (extra_leds_s1_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (extra_leds_s1_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_024_src_ready), // src.ready
.src_valid (router_024_src_valid), // .valid
.src_data (router_024_src_data), // .data
.src_channel (router_024_src_channel), // .channel
.src_startofpacket (router_024_src_startofpacket), // .startofpacket
.src_endofpacket (router_024_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_router_005 router_025 (
.sink_ready (spi_stm32_spi_control_port_agent_rp_ready), // sink.ready
.sink_valid (spi_stm32_spi_control_port_agent_rp_valid), // .valid
.sink_data (spi_stm32_spi_control_port_agent_rp_data), // .data
.sink_startofpacket (spi_stm32_spi_control_port_agent_rp_startofpacket), // .startofpacket
.sink_endofpacket (spi_stm32_spi_control_port_agent_rp_endofpacket), // .endofpacket
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (router_025_src_ready), // src.ready
.src_valid (router_025_src_valid), // .valid
.src_data (router_025_src_data), // .data
.src_channel (router_025_src_channel), // .channel
.src_startofpacket (router_025_src_startofpacket), // .startofpacket
.src_endofpacket (router_025_src_endofpacket) // .endofpacket
);
altera_merlin_traffic_limiter #(
.PKT_DEST_ID_H (79),
.PKT_DEST_ID_L (75),
.PKT_SRC_ID_H (74),
.PKT_SRC_ID_L (70),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_TRANS_POSTED (47),
.PKT_TRANS_WRITE (48),
.MAX_OUTSTANDING_RESPONSES (9),
.PIPELINED (0),
.ST_DATA_W (93),
.ST_CHANNEL_W (23),
.VALID_WIDTH (23),
.ENFORCE_ORDER (1),
.PREVENT_HAZARDS (0),
.SUPPORTS_POSTED_WRITES (1),
.SUPPORTS_NONPOSTED_WRITES (0),
.REORDER (0)
) abus_slave_0_avalon_master_limiter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.cmd_sink_ready (router_src_ready), // cmd_sink.ready
.cmd_sink_valid (router_src_valid), // .valid
.cmd_sink_data (router_src_data), // .data
.cmd_sink_channel (router_src_channel), // .channel
.cmd_sink_startofpacket (router_src_startofpacket), // .startofpacket
.cmd_sink_endofpacket (router_src_endofpacket), // .endofpacket
.cmd_src_ready (abus_slave_0_avalon_master_limiter_cmd_src_ready), // cmd_src.ready
.cmd_src_data (abus_slave_0_avalon_master_limiter_cmd_src_data), // .data
.cmd_src_channel (abus_slave_0_avalon_master_limiter_cmd_src_channel), // .channel
.cmd_src_startofpacket (abus_slave_0_avalon_master_limiter_cmd_src_startofpacket), // .startofpacket
.cmd_src_endofpacket (abus_slave_0_avalon_master_limiter_cmd_src_endofpacket), // .endofpacket
.rsp_sink_ready (rsp_mux_src_ready), // rsp_sink.ready
.rsp_sink_valid (rsp_mux_src_valid), // .valid
.rsp_sink_channel (rsp_mux_src_channel), // .channel
.rsp_sink_data (rsp_mux_src_data), // .data
.rsp_sink_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.rsp_sink_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.rsp_src_ready (abus_slave_0_avalon_master_limiter_rsp_src_ready), // rsp_src.ready
.rsp_src_valid (abus_slave_0_avalon_master_limiter_rsp_src_valid), // .valid
.rsp_src_data (abus_slave_0_avalon_master_limiter_rsp_src_data), // .data
.rsp_src_channel (abus_slave_0_avalon_master_limiter_rsp_src_channel), // .channel
.rsp_src_startofpacket (abus_slave_0_avalon_master_limiter_rsp_src_startofpacket), // .startofpacket
.rsp_src_endofpacket (abus_slave_0_avalon_master_limiter_rsp_src_endofpacket), // .endofpacket
.cmd_src_valid (abus_slave_0_avalon_master_limiter_cmd_valid_data) // cmd_valid.data
);
altera_merlin_burst_adapter #(
.PKT_ADDR_H (45),
.PKT_ADDR_L (18),
.PKT_BEGIN_BURST (68),
.PKT_BYTE_CNT_H (57),
.PKT_BYTE_CNT_L (52),
.PKT_BYTEEN_H (17),
.PKT_BYTEEN_L (16),
.PKT_BURST_SIZE_H (63),
.PKT_BURST_SIZE_L (61),
.PKT_BURST_TYPE_H (65),
.PKT_BURST_TYPE_L (64),
.PKT_BURSTWRAP_H (60),
.PKT_BURSTWRAP_L (58),
.PKT_TRANS_COMPRESSED_READ (46),
.PKT_TRANS_WRITE (48),
.PKT_TRANS_READ (49),
.OUT_NARROW_SIZE (0),
.IN_NARROW_SIZE (0),
.OUT_FIXED (0),
.OUT_COMPLETE_WRAP (0),
.ST_DATA_W (93),
.ST_CHANNEL_W (23),
.OUT_BYTE_CNT_H (53),
.OUT_BURSTWRAP_H (60),
.COMPRESSED_READ_SUPPORT (0),
.BYTEENABLE_SYNTHESIS (1),
.PIPE_INPUTS (0),
.NO_WRAP_SUPPORT (0),
.INCOMPLETE_WRAP_SUPPORT (0),
.BURSTWRAP_CONST_MASK (7),
.BURSTWRAP_CONST_VALUE (7),
.ADAPTER_VERSION ("13.1")
) external_sdram_controller_s1_burst_adapter (
.clk (altpll_0_c0_clk), // cr0.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // cr0_reset.reset
.sink0_valid (cmd_mux_src_valid), // sink0.valid
.sink0_data (cmd_mux_src_data), // .data
.sink0_channel (cmd_mux_src_channel), // .channel
.sink0_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_mux_src_ready), // .ready
.source0_valid (external_sdram_controller_s1_burst_adapter_source0_valid), // source0.valid
.source0_data (external_sdram_controller_s1_burst_adapter_source0_data), // .data
.source0_channel (external_sdram_controller_s1_burst_adapter_source0_channel), // .channel
.source0_startofpacket (external_sdram_controller_s1_burst_adapter_source0_startofpacket), // .startofpacket
.source0_endofpacket (external_sdram_controller_s1_burst_adapter_source0_endofpacket), // .endofpacket
.source0_ready (external_sdram_controller_s1_burst_adapter_source0_ready) // .ready
);
wasca_mm_interconnect_0_cmd_demux cmd_demux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (abus_slave_0_avalon_master_limiter_cmd_src_ready), // sink.ready
.sink_channel (abus_slave_0_avalon_master_limiter_cmd_src_channel), // .channel
.sink_data (abus_slave_0_avalon_master_limiter_cmd_src_data), // .data
.sink_startofpacket (abus_slave_0_avalon_master_limiter_cmd_src_startofpacket), // .startofpacket
.sink_endofpacket (abus_slave_0_avalon_master_limiter_cmd_src_endofpacket), // .endofpacket
.sink_valid (abus_slave_0_avalon_master_limiter_cmd_valid_data), // sink_valid.data
.src0_ready (cmd_demux_src0_ready), // src0.ready
.src0_valid (cmd_demux_src0_valid), // .valid
.src0_data (cmd_demux_src0_data), // .data
.src0_channel (cmd_demux_src0_channel), // .channel
.src0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_src1_ready), // src1.ready
.src1_valid (cmd_demux_src1_valid), // .valid
.src1_data (cmd_demux_src1_data), // .data
.src1_channel (cmd_demux_src1_channel), // .channel
.src1_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_001 cmd_demux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_001_src_ready), // sink.ready
.sink_channel (router_001_src_channel), // .channel
.sink_data (router_001_src_data), // .data
.sink_startofpacket (router_001_src_startofpacket), // .startofpacket
.sink_endofpacket (router_001_src_endofpacket), // .endofpacket
.sink_valid (router_001_src_valid), // .valid
.src0_ready (cmd_demux_001_src0_ready), // src0.ready
.src0_valid (cmd_demux_001_src0_valid), // .valid
.src0_data (cmd_demux_001_src0_data), // .data
.src0_channel (cmd_demux_001_src0_channel), // .channel
.src0_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_001_src1_ready), // src1.ready
.src1_valid (cmd_demux_001_src1_valid), // .valid
.src1_data (cmd_demux_001_src1_data), // .data
.src1_channel (cmd_demux_001_src1_channel), // .channel
.src1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_001_src2_ready), // src2.ready
.src2_valid (cmd_demux_001_src2_valid), // .valid
.src2_data (cmd_demux_001_src2_data), // .data
.src2_channel (cmd_demux_001_src2_channel), // .channel
.src2_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_001_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_001_src3_ready), // src3.ready
.src3_valid (cmd_demux_001_src3_valid), // .valid
.src3_data (cmd_demux_001_src3_data), // .data
.src3_channel (cmd_demux_001_src3_channel), // .channel
.src3_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_001_src3_endofpacket), // .endofpacket
.src4_ready (cmd_demux_001_src4_ready), // src4.ready
.src4_valid (cmd_demux_001_src4_valid), // .valid
.src4_data (cmd_demux_001_src4_data), // .data
.src4_channel (cmd_demux_001_src4_channel), // .channel
.src4_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.src4_endofpacket (cmd_demux_001_src4_endofpacket), // .endofpacket
.src5_ready (cmd_demux_001_src5_ready), // src5.ready
.src5_valid (cmd_demux_001_src5_valid), // .valid
.src5_data (cmd_demux_001_src5_data), // .data
.src5_channel (cmd_demux_001_src5_channel), // .channel
.src5_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.src5_endofpacket (cmd_demux_001_src5_endofpacket), // .endofpacket
.src6_ready (cmd_demux_001_src6_ready), // src6.ready
.src6_valid (cmd_demux_001_src6_valid), // .valid
.src6_data (cmd_demux_001_src6_data), // .data
.src6_channel (cmd_demux_001_src6_channel), // .channel
.src6_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.src6_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.src7_ready (cmd_demux_001_src7_ready), // src7.ready
.src7_valid (cmd_demux_001_src7_valid), // .valid
.src7_data (cmd_demux_001_src7_data), // .data
.src7_channel (cmd_demux_001_src7_channel), // .channel
.src7_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.src7_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.src8_ready (cmd_demux_001_src8_ready), // src8.ready
.src8_valid (cmd_demux_001_src8_valid), // .valid
.src8_data (cmd_demux_001_src8_data), // .data
.src8_channel (cmd_demux_001_src8_channel), // .channel
.src8_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.src8_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
.src9_ready (cmd_demux_001_src9_ready), // src9.ready
.src9_valid (cmd_demux_001_src9_valid), // .valid
.src9_data (cmd_demux_001_src9_data), // .data
.src9_channel (cmd_demux_001_src9_channel), // .channel
.src9_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.src9_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
.src10_ready (cmd_demux_001_src10_ready), // src10.ready
.src10_valid (cmd_demux_001_src10_valid), // .valid
.src10_data (cmd_demux_001_src10_data), // .data
.src10_channel (cmd_demux_001_src10_channel), // .channel
.src10_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.src10_endofpacket (cmd_demux_001_src10_endofpacket), // .endofpacket
.src11_ready (cmd_demux_001_src11_ready), // src11.ready
.src11_valid (cmd_demux_001_src11_valid), // .valid
.src11_data (cmd_demux_001_src11_data), // .data
.src11_channel (cmd_demux_001_src11_channel), // .channel
.src11_startofpacket (cmd_demux_001_src11_startofpacket), // .startofpacket
.src11_endofpacket (cmd_demux_001_src11_endofpacket), // .endofpacket
.src12_ready (cmd_demux_001_src12_ready), // src12.ready
.src12_valid (cmd_demux_001_src12_valid), // .valid
.src12_data (cmd_demux_001_src12_data), // .data
.src12_channel (cmd_demux_001_src12_channel), // .channel
.src12_startofpacket (cmd_demux_001_src12_startofpacket), // .startofpacket
.src12_endofpacket (cmd_demux_001_src12_endofpacket), // .endofpacket
.src13_ready (cmd_demux_001_src13_ready), // src13.ready
.src13_valid (cmd_demux_001_src13_valid), // .valid
.src13_data (cmd_demux_001_src13_data), // .data
.src13_channel (cmd_demux_001_src13_channel), // .channel
.src13_startofpacket (cmd_demux_001_src13_startofpacket), // .startofpacket
.src13_endofpacket (cmd_demux_001_src13_endofpacket), // .endofpacket
.src14_ready (cmd_demux_001_src14_ready), // src14.ready
.src14_valid (cmd_demux_001_src14_valid), // .valid
.src14_data (cmd_demux_001_src14_data), // .data
.src14_channel (cmd_demux_001_src14_channel), // .channel
.src14_startofpacket (cmd_demux_001_src14_startofpacket), // .startofpacket
.src14_endofpacket (cmd_demux_001_src14_endofpacket), // .endofpacket
.src15_ready (cmd_demux_001_src15_ready), // src15.ready
.src15_valid (cmd_demux_001_src15_valid), // .valid
.src15_data (cmd_demux_001_src15_data), // .data
.src15_channel (cmd_demux_001_src15_channel), // .channel
.src15_startofpacket (cmd_demux_001_src15_startofpacket), // .startofpacket
.src15_endofpacket (cmd_demux_001_src15_endofpacket), // .endofpacket
.src16_ready (cmd_demux_001_src16_ready), // src16.ready
.src16_valid (cmd_demux_001_src16_valid), // .valid
.src16_data (cmd_demux_001_src16_data), // .data
.src16_channel (cmd_demux_001_src16_channel), // .channel
.src16_startofpacket (cmd_demux_001_src16_startofpacket), // .startofpacket
.src16_endofpacket (cmd_demux_001_src16_endofpacket), // .endofpacket
.src17_ready (cmd_demux_001_src17_ready), // src17.ready
.src17_valid (cmd_demux_001_src17_valid), // .valid
.src17_data (cmd_demux_001_src17_data), // .data
.src17_channel (cmd_demux_001_src17_channel), // .channel
.src17_startofpacket (cmd_demux_001_src17_startofpacket), // .startofpacket
.src17_endofpacket (cmd_demux_001_src17_endofpacket), // .endofpacket
.src18_ready (cmd_demux_001_src18_ready), // src18.ready
.src18_valid (cmd_demux_001_src18_valid), // .valid
.src18_data (cmd_demux_001_src18_data), // .data
.src18_channel (cmd_demux_001_src18_channel), // .channel
.src18_startofpacket (cmd_demux_001_src18_startofpacket), // .startofpacket
.src18_endofpacket (cmd_demux_001_src18_endofpacket), // .endofpacket
.src19_ready (cmd_demux_001_src19_ready), // src19.ready
.src19_valid (cmd_demux_001_src19_valid), // .valid
.src19_data (cmd_demux_001_src19_data), // .data
.src19_channel (cmd_demux_001_src19_channel), // .channel
.src19_startofpacket (cmd_demux_001_src19_startofpacket), // .startofpacket
.src19_endofpacket (cmd_demux_001_src19_endofpacket), // .endofpacket
.src20_ready (cmd_demux_001_src20_ready), // src20.ready
.src20_valid (cmd_demux_001_src20_valid), // .valid
.src20_data (cmd_demux_001_src20_data), // .data
.src20_channel (cmd_demux_001_src20_channel), // .channel
.src20_startofpacket (cmd_demux_001_src20_startofpacket), // .startofpacket
.src20_endofpacket (cmd_demux_001_src20_endofpacket), // .endofpacket
.src21_ready (cmd_demux_001_src21_ready), // src21.ready
.src21_valid (cmd_demux_001_src21_valid), // .valid
.src21_data (cmd_demux_001_src21_data), // .data
.src21_channel (cmd_demux_001_src21_channel), // .channel
.src21_startofpacket (cmd_demux_001_src21_startofpacket), // .startofpacket
.src21_endofpacket (cmd_demux_001_src21_endofpacket), // .endofpacket
.src22_ready (cmd_demux_001_src22_ready), // src22.ready
.src22_valid (cmd_demux_001_src22_valid), // .valid
.src22_data (cmd_demux_001_src22_data), // .data
.src22_channel (cmd_demux_001_src22_channel), // .channel
.src22_startofpacket (cmd_demux_001_src22_startofpacket), // .startofpacket
.src22_endofpacket (cmd_demux_001_src22_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_demux_002 cmd_demux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_002_src_ready), // sink.ready
.sink_channel (router_002_src_channel), // .channel
.sink_data (router_002_src_data), // .data
.sink_startofpacket (router_002_src_startofpacket), // .startofpacket
.sink_endofpacket (router_002_src_endofpacket), // .endofpacket
.sink_valid (router_002_src_valid), // .valid
.src0_ready (cmd_demux_002_src0_ready), // src0.ready
.src0_valid (cmd_demux_002_src0_valid), // .valid
.src0_data (cmd_demux_002_src0_data), // .data
.src0_channel (cmd_demux_002_src0_channel), // .channel
.src0_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (cmd_demux_002_src0_endofpacket), // .endofpacket
.src1_ready (cmd_demux_002_src1_ready), // src1.ready
.src1_valid (cmd_demux_002_src1_valid), // .valid
.src1_data (cmd_demux_002_src1_data), // .data
.src1_channel (cmd_demux_002_src1_channel), // .channel
.src1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.src1_endofpacket (cmd_demux_002_src1_endofpacket), // .endofpacket
.src2_ready (cmd_demux_002_src2_ready), // src2.ready
.src2_valid (cmd_demux_002_src2_valid), // .valid
.src2_data (cmd_demux_002_src2_data), // .data
.src2_channel (cmd_demux_002_src2_channel), // .channel
.src2_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.src2_endofpacket (cmd_demux_002_src2_endofpacket), // .endofpacket
.src3_ready (cmd_demux_002_src3_ready), // src3.ready
.src3_valid (cmd_demux_002_src3_valid), // .valid
.src3_data (cmd_demux_002_src3_data), // .data
.src3_channel (cmd_demux_002_src3_channel), // .channel
.src3_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.src3_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux cmd_mux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_src_ready), // src.ready
.src_valid (cmd_mux_src_valid), // .valid
.src_data (cmd_mux_src_data), // .data
.src_channel (cmd_mux_src_channel), // .channel
.src_startofpacket (cmd_mux_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_src0_ready), // sink0.ready
.sink0_valid (cmd_demux_src0_valid), // .valid
.sink0_channel (cmd_demux_src0_channel), // .channel
.sink0_data (cmd_demux_src0_data), // .data
.sink0_startofpacket (cmd_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_src0_endofpacket), // .endofpacket
.sink1_ready (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // sink1.ready
.sink1_valid (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.sink1_channel (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.sink1_data (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.sink1_startofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink1_endofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_001 cmd_mux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_001_src_ready), // src.ready
.src_valid (cmd_mux_001_src_valid), // .valid
.src_data (cmd_mux_001_src_data), // .data
.src_channel (cmd_mux_001_src_channel), // .channel
.src_startofpacket (cmd_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready), // sink0.ready
.sink0_valid (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid), // .valid
.sink0_channel (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel), // .channel
.sink0_data (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data), // .data
.sink0_startofpacket (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_001_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_001_src1_valid), // .valid
.sink1_channel (cmd_demux_001_src1_channel), // .channel
.sink1_data (cmd_demux_001_src1_data), // .data
.sink1_startofpacket (cmd_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (cmd_demux_002_src0_ready), // sink2.ready
.sink2_valid (cmd_demux_002_src0_valid), // .valid
.sink2_channel (cmd_demux_002_src0_channel), // .channel
.sink2_data (cmd_demux_002_src0_data), // .data
.sink2_startofpacket (cmd_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (cmd_demux_002_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_002_src_ready), // src.ready
.src_valid (cmd_mux_002_src_valid), // .valid
.src_data (cmd_mux_002_src_data), // .data
.src_channel (cmd_mux_002_src_channel), // .channel
.src_startofpacket (cmd_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src2_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src2_valid), // .valid
.sink0_channel (cmd_demux_001_src2_channel), // .channel
.sink0_data (cmd_demux_001_src2_data), // .data
.sink0_startofpacket (cmd_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_003 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_003_src_ready), // src.ready
.src_valid (cmd_mux_003_src_valid), // .valid
.src_data (cmd_mux_003_src_data), // .data
.src_channel (cmd_mux_003_src_channel), // .channel
.src_startofpacket (cmd_mux_003_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_003_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src3_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src3_valid), // .valid
.sink0_channel (cmd_demux_001_src3_channel), // .channel
.sink0_data (cmd_demux_001_src3_data), // .data
.sink0_startofpacket (cmd_demux_001_src3_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_004 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_004_src_ready), // src.ready
.src_valid (cmd_mux_004_src_valid), // .valid
.src_data (cmd_mux_004_src_data), // .data
.src_channel (cmd_mux_004_src_channel), // .channel
.src_startofpacket (cmd_mux_004_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_004_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src4_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src4_valid), // .valid
.sink0_channel (cmd_demux_001_src4_channel), // .channel
.sink0_data (cmd_demux_001_src4_data), // .data
.sink0_startofpacket (cmd_demux_001_src4_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src4_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_005 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_005_src_ready), // src.ready
.src_valid (cmd_mux_005_src_valid), // .valid
.src_data (cmd_mux_005_src_data), // .data
.src_channel (cmd_mux_005_src_channel), // .channel
.src_startofpacket (cmd_mux_005_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_005_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src5_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src5_valid), // .valid
.sink0_channel (cmd_demux_001_src5_channel), // .channel
.sink0_data (cmd_demux_001_src5_data), // .data
.sink0_startofpacket (cmd_demux_001_src5_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src5_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_006 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_006_src_ready), // src.ready
.src_valid (cmd_mux_006_src_valid), // .valid
.src_data (cmd_mux_006_src_data), // .data
.src_channel (cmd_mux_006_src_channel), // .channel
.src_startofpacket (cmd_mux_006_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_006_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src6_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src6_valid), // .valid
.sink0_channel (cmd_demux_001_src6_channel), // .channel
.sink0_data (cmd_demux_001_src6_data), // .data
.sink0_startofpacket (cmd_demux_001_src6_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src6_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src1_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src1_valid), // .valid
.sink1_channel (cmd_demux_002_src1_channel), // .channel
.sink1_data (cmd_demux_002_src1_data), // .data
.sink1_startofpacket (cmd_demux_002_src1_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_007 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_007_src_ready), // src.ready
.src_valid (cmd_mux_007_src_valid), // .valid
.src_data (cmd_mux_007_src_data), // .data
.src_channel (cmd_mux_007_src_channel), // .channel
.src_startofpacket (cmd_mux_007_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_007_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src7_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src7_valid), // .valid
.sink0_channel (cmd_demux_001_src7_channel), // .channel
.sink0_data (cmd_demux_001_src7_data), // .data
.sink0_startofpacket (cmd_demux_001_src7_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src7_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src2_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src2_valid), // .valid
.sink1_channel (cmd_demux_002_src2_channel), // .channel
.sink1_data (cmd_demux_002_src2_data), // .data
.sink1_startofpacket (cmd_demux_002_src2_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_008_src_ready), // src.ready
.src_valid (cmd_mux_008_src_valid), // .valid
.src_data (cmd_mux_008_src_data), // .data
.src_channel (cmd_mux_008_src_channel), // .channel
.src_startofpacket (cmd_mux_008_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_008_src_endofpacket), // .endofpacket
.sink0_ready (crosser_out_ready), // sink0.ready
.sink0_valid (crosser_out_valid), // .valid
.sink0_channel (crosser_out_channel), // .channel
.sink0_data (crosser_out_data), // .data
.sink0_startofpacket (crosser_out_startofpacket), // .startofpacket
.sink0_endofpacket (crosser_out_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_006 cmd_mux_009 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_009_src_ready), // src.ready
.src_valid (cmd_mux_009_src_valid), // .valid
.src_data (cmd_mux_009_src_data), // .data
.src_channel (cmd_mux_009_src_channel), // .channel
.src_startofpacket (cmd_mux_009_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_009_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src9_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src9_valid), // .valid
.sink0_channel (cmd_demux_001_src9_channel), // .channel
.sink0_data (cmd_demux_001_src9_data), // .data
.sink0_startofpacket (cmd_demux_001_src9_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src9_endofpacket), // .endofpacket
.sink1_ready (cmd_demux_002_src3_ready), // sink1.ready
.sink1_valid (cmd_demux_002_src3_valid), // .valid
.sink1_channel (cmd_demux_002_src3_channel), // .channel
.sink1_data (cmd_demux_002_src3_data), // .data
.sink1_startofpacket (cmd_demux_002_src3_startofpacket), // .startofpacket
.sink1_endofpacket (cmd_demux_002_src3_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_010 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_010_src_ready), // src.ready
.src_valid (cmd_mux_010_src_valid), // .valid
.src_data (cmd_mux_010_src_data), // .data
.src_channel (cmd_mux_010_src_channel), // .channel
.src_startofpacket (cmd_mux_010_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_010_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src10_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src10_valid), // .valid
.sink0_channel (cmd_demux_001_src10_channel), // .channel
.sink0_data (cmd_demux_001_src10_data), // .data
.sink0_startofpacket (cmd_demux_001_src10_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src10_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_011 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_011_src_ready), // src.ready
.src_valid (cmd_mux_011_src_valid), // .valid
.src_data (cmd_mux_011_src_data), // .data
.src_channel (cmd_mux_011_src_channel), // .channel
.src_startofpacket (cmd_mux_011_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_011_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src11_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src11_valid), // .valid
.sink0_channel (cmd_demux_001_src11_channel), // .channel
.sink0_data (cmd_demux_001_src11_data), // .data
.sink0_startofpacket (cmd_demux_001_src11_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src11_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_012 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_012_src_ready), // src.ready
.src_valid (cmd_mux_012_src_valid), // .valid
.src_data (cmd_mux_012_src_data), // .data
.src_channel (cmd_mux_012_src_channel), // .channel
.src_startofpacket (cmd_mux_012_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_012_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src12_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src12_valid), // .valid
.sink0_channel (cmd_demux_001_src12_channel), // .channel
.sink0_data (cmd_demux_001_src12_data), // .data
.sink0_startofpacket (cmd_demux_001_src12_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src12_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_013 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_013_src_ready), // src.ready
.src_valid (cmd_mux_013_src_valid), // .valid
.src_data (cmd_mux_013_src_data), // .data
.src_channel (cmd_mux_013_src_channel), // .channel
.src_startofpacket (cmd_mux_013_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_013_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src13_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src13_valid), // .valid
.sink0_channel (cmd_demux_001_src13_channel), // .channel
.sink0_data (cmd_demux_001_src13_data), // .data
.sink0_startofpacket (cmd_demux_001_src13_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src13_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_014 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_014_src_ready), // src.ready
.src_valid (cmd_mux_014_src_valid), // .valid
.src_data (cmd_mux_014_src_data), // .data
.src_channel (cmd_mux_014_src_channel), // .channel
.src_startofpacket (cmd_mux_014_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_014_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src14_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src14_valid), // .valid
.sink0_channel (cmd_demux_001_src14_channel), // .channel
.sink0_data (cmd_demux_001_src14_data), // .data
.sink0_startofpacket (cmd_demux_001_src14_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src14_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_015 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_015_src_ready), // src.ready
.src_valid (cmd_mux_015_src_valid), // .valid
.src_data (cmd_mux_015_src_data), // .data
.src_channel (cmd_mux_015_src_channel), // .channel
.src_startofpacket (cmd_mux_015_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_015_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src15_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src15_valid), // .valid
.sink0_channel (cmd_demux_001_src15_channel), // .channel
.sink0_data (cmd_demux_001_src15_data), // .data
.sink0_startofpacket (cmd_demux_001_src15_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src15_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_016 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_016_src_ready), // src.ready
.src_valid (cmd_mux_016_src_valid), // .valid
.src_data (cmd_mux_016_src_data), // .data
.src_channel (cmd_mux_016_src_channel), // .channel
.src_startofpacket (cmd_mux_016_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_016_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src16_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src16_valid), // .valid
.sink0_channel (cmd_demux_001_src16_channel), // .channel
.sink0_data (cmd_demux_001_src16_data), // .data
.sink0_startofpacket (cmd_demux_001_src16_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src16_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_017 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_017_src_ready), // src.ready
.src_valid (cmd_mux_017_src_valid), // .valid
.src_data (cmd_mux_017_src_data), // .data
.src_channel (cmd_mux_017_src_channel), // .channel
.src_startofpacket (cmd_mux_017_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_017_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src17_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src17_valid), // .valid
.sink0_channel (cmd_demux_001_src17_channel), // .channel
.sink0_data (cmd_demux_001_src17_data), // .data
.sink0_startofpacket (cmd_demux_001_src17_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src17_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_018 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_018_src_ready), // src.ready
.src_valid (cmd_mux_018_src_valid), // .valid
.src_data (cmd_mux_018_src_data), // .data
.src_channel (cmd_mux_018_src_channel), // .channel
.src_startofpacket (cmd_mux_018_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_018_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src18_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src18_valid), // .valid
.sink0_channel (cmd_demux_001_src18_channel), // .channel
.sink0_data (cmd_demux_001_src18_data), // .data
.sink0_startofpacket (cmd_demux_001_src18_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src18_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_019 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_019_src_ready), // src.ready
.src_valid (cmd_mux_019_src_valid), // .valid
.src_data (cmd_mux_019_src_data), // .data
.src_channel (cmd_mux_019_src_channel), // .channel
.src_startofpacket (cmd_mux_019_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_019_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src19_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src19_valid), // .valid
.sink0_channel (cmd_demux_001_src19_channel), // .channel
.sink0_data (cmd_demux_001_src19_data), // .data
.sink0_startofpacket (cmd_demux_001_src19_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src19_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_020 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_020_src_ready), // src.ready
.src_valid (cmd_mux_020_src_valid), // .valid
.src_data (cmd_mux_020_src_data), // .data
.src_channel (cmd_mux_020_src_channel), // .channel
.src_startofpacket (cmd_mux_020_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_020_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src20_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src20_valid), // .valid
.sink0_channel (cmd_demux_001_src20_channel), // .channel
.sink0_data (cmd_demux_001_src20_data), // .data
.sink0_startofpacket (cmd_demux_001_src20_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src20_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_021 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_021_src_ready), // src.ready
.src_valid (cmd_mux_021_src_valid), // .valid
.src_data (cmd_mux_021_src_data), // .data
.src_channel (cmd_mux_021_src_channel), // .channel
.src_startofpacket (cmd_mux_021_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_021_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src21_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src21_valid), // .valid
.sink0_channel (cmd_demux_001_src21_channel), // .channel
.sink0_data (cmd_demux_001_src21_data), // .data
.sink0_startofpacket (cmd_demux_001_src21_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src21_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_cmd_mux_002 cmd_mux_022 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (cmd_mux_022_src_ready), // src.ready
.src_valid (cmd_mux_022_src_valid), // .valid
.src_data (cmd_mux_022_src_data), // .data
.src_channel (cmd_mux_022_src_channel), // .channel
.src_startofpacket (cmd_mux_022_src_startofpacket), // .startofpacket
.src_endofpacket (cmd_mux_022_src_endofpacket), // .endofpacket
.sink0_ready (cmd_demux_001_src22_ready), // sink0.ready
.sink0_valid (cmd_demux_001_src22_valid), // .valid
.sink0_channel (cmd_demux_001_src22_channel), // .channel
.sink0_data (cmd_demux_001_src22_data), // .data
.sink0_startofpacket (cmd_demux_001_src22_startofpacket), // .startofpacket
.sink0_endofpacket (cmd_demux_001_src22_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux rsp_demux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_003_src_ready), // sink.ready
.sink_channel (router_003_src_channel), // .channel
.sink_data (router_003_src_data), // .data
.sink_startofpacket (router_003_src_startofpacket), // .startofpacket
.sink_endofpacket (router_003_src_endofpacket), // .endofpacket
.sink_valid (router_003_src_valid), // .valid
.src0_ready (rsp_demux_src0_ready), // src0.ready
.src0_valid (rsp_demux_src0_valid), // .valid
.src0_data (rsp_demux_src0_data), // .data
.src0_channel (rsp_demux_src0_channel), // .channel
.src0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_src1_ready), // src1.ready
.src1_valid (rsp_demux_src1_valid), // .valid
.src1_data (rsp_demux_src1_data), // .data
.src1_channel (rsp_demux_src1_channel), // .channel
.src1_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_001 rsp_demux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_004_src_ready), // sink.ready
.sink_channel (router_004_src_channel), // .channel
.sink_data (router_004_src_data), // .data
.sink_startofpacket (router_004_src_startofpacket), // .startofpacket
.sink_endofpacket (router_004_src_endofpacket), // .endofpacket
.sink_valid (router_004_src_valid), // .valid
.src0_ready (rsp_demux_001_src0_ready), // src0.ready
.src0_valid (rsp_demux_001_src0_valid), // .valid
.src0_data (rsp_demux_001_src0_data), // .data
.src0_channel (rsp_demux_001_src0_channel), // .channel
.src0_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_001_src1_ready), // src1.ready
.src1_valid (rsp_demux_001_src1_valid), // .valid
.src1_data (rsp_demux_001_src1_data), // .data
.src1_channel (rsp_demux_001_src1_channel), // .channel
.src1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.src2_ready (rsp_demux_001_src2_ready), // src2.ready
.src2_valid (rsp_demux_001_src2_valid), // .valid
.src2_data (rsp_demux_001_src2_data), // .data
.src2_channel (rsp_demux_001_src2_channel), // .channel
.src2_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.src2_endofpacket (rsp_demux_001_src2_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_005_src_ready), // sink.ready
.sink_channel (router_005_src_channel), // .channel
.sink_data (router_005_src_data), // .data
.sink_startofpacket (router_005_src_startofpacket), // .startofpacket
.sink_endofpacket (router_005_src_endofpacket), // .endofpacket
.sink_valid (router_005_src_valid), // .valid
.src0_ready (rsp_demux_002_src0_ready), // src0.ready
.src0_valid (rsp_demux_002_src0_valid), // .valid
.src0_data (rsp_demux_002_src0_data), // .data
.src0_channel (rsp_demux_002_src0_channel), // .channel
.src0_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_002_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_003 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_006_src_ready), // sink.ready
.sink_channel (router_006_src_channel), // .channel
.sink_data (router_006_src_data), // .data
.sink_startofpacket (router_006_src_startofpacket), // .startofpacket
.sink_endofpacket (router_006_src_endofpacket), // .endofpacket
.sink_valid (router_006_src_valid), // .valid
.src0_ready (rsp_demux_003_src0_ready), // src0.ready
.src0_valid (rsp_demux_003_src0_valid), // .valid
.src0_data (rsp_demux_003_src0_data), // .data
.src0_channel (rsp_demux_003_src0_channel), // .channel
.src0_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_003_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_004 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_007_src_ready), // sink.ready
.sink_channel (router_007_src_channel), // .channel
.sink_data (router_007_src_data), // .data
.sink_startofpacket (router_007_src_startofpacket), // .startofpacket
.sink_endofpacket (router_007_src_endofpacket), // .endofpacket
.sink_valid (router_007_src_valid), // .valid
.src0_ready (rsp_demux_004_src0_ready), // src0.ready
.src0_valid (rsp_demux_004_src0_valid), // .valid
.src0_data (rsp_demux_004_src0_data), // .data
.src0_channel (rsp_demux_004_src0_channel), // .channel
.src0_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_004_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_005 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_008_src_ready), // sink.ready
.sink_channel (router_008_src_channel), // .channel
.sink_data (router_008_src_data), // .data
.sink_startofpacket (router_008_src_startofpacket), // .startofpacket
.sink_endofpacket (router_008_src_endofpacket), // .endofpacket
.sink_valid (router_008_src_valid), // .valid
.src0_ready (rsp_demux_005_src0_ready), // src0.ready
.src0_valid (rsp_demux_005_src0_valid), // .valid
.src0_data (rsp_demux_005_src0_data), // .data
.src0_channel (rsp_demux_005_src0_channel), // .channel
.src0_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_005_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_006 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_009_src_ready), // sink.ready
.sink_channel (router_009_src_channel), // .channel
.sink_data (router_009_src_data), // .data
.sink_startofpacket (router_009_src_startofpacket), // .startofpacket
.sink_endofpacket (router_009_src_endofpacket), // .endofpacket
.sink_valid (router_009_src_valid), // .valid
.src0_ready (rsp_demux_006_src0_ready), // src0.ready
.src0_valid (rsp_demux_006_src0_valid), // .valid
.src0_data (rsp_demux_006_src0_data), // .data
.src0_channel (rsp_demux_006_src0_channel), // .channel
.src0_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_006_src1_ready), // src1.ready
.src1_valid (rsp_demux_006_src1_valid), // .valid
.src1_data (rsp_demux_006_src1_data), // .data
.src1_channel (rsp_demux_006_src1_channel), // .channel
.src1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_006_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_007 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_010_src_ready), // sink.ready
.sink_channel (router_010_src_channel), // .channel
.sink_data (router_010_src_data), // .data
.sink_startofpacket (router_010_src_startofpacket), // .startofpacket
.sink_endofpacket (router_010_src_endofpacket), // .endofpacket
.sink_valid (router_010_src_valid), // .valid
.src0_ready (rsp_demux_007_src0_ready), // src0.ready
.src0_valid (rsp_demux_007_src0_valid), // .valid
.src0_data (rsp_demux_007_src0_data), // .data
.src0_channel (rsp_demux_007_src0_channel), // .channel
.src0_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_007_src1_ready), // src1.ready
.src1_valid (rsp_demux_007_src1_valid), // .valid
.src1_data (rsp_demux_007_src1_data), // .data
.src1_channel (rsp_demux_007_src1_channel), // .channel
.src1_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_007_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_008 rsp_demux_008 (
.clk (clk_0_clk_clk), // clk.clk
.reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_011_src_ready), // sink.ready
.sink_channel (router_011_src_channel), // .channel
.sink_data (router_011_src_data), // .data
.sink_startofpacket (router_011_src_startofpacket), // .startofpacket
.sink_endofpacket (router_011_src_endofpacket), // .endofpacket
.sink_valid (router_011_src_valid), // .valid
.src0_ready (rsp_demux_008_src0_ready), // src0.ready
.src0_valid (rsp_demux_008_src0_valid), // .valid
.src0_data (rsp_demux_008_src0_data), // .data
.src0_channel (rsp_demux_008_src0_channel), // .channel
.src0_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_008_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_006 rsp_demux_009 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_012_src_ready), // sink.ready
.sink_channel (router_012_src_channel), // .channel
.sink_data (router_012_src_data), // .data
.sink_startofpacket (router_012_src_startofpacket), // .startofpacket
.sink_endofpacket (router_012_src_endofpacket), // .endofpacket
.sink_valid (router_012_src_valid), // .valid
.src0_ready (rsp_demux_009_src0_ready), // src0.ready
.src0_valid (rsp_demux_009_src0_valid), // .valid
.src0_data (rsp_demux_009_src0_data), // .data
.src0_channel (rsp_demux_009_src0_channel), // .channel
.src0_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.src1_ready (rsp_demux_009_src1_ready), // src1.ready
.src1_valid (rsp_demux_009_src1_valid), // .valid
.src1_data (rsp_demux_009_src1_data), // .data
.src1_channel (rsp_demux_009_src1_channel), // .channel
.src1_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.src1_endofpacket (rsp_demux_009_src1_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_010 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_013_src_ready), // sink.ready
.sink_channel (router_013_src_channel), // .channel
.sink_data (router_013_src_data), // .data
.sink_startofpacket (router_013_src_startofpacket), // .startofpacket
.sink_endofpacket (router_013_src_endofpacket), // .endofpacket
.sink_valid (router_013_src_valid), // .valid
.src0_ready (rsp_demux_010_src0_ready), // src0.ready
.src0_valid (rsp_demux_010_src0_valid), // .valid
.src0_data (rsp_demux_010_src0_data), // .data
.src0_channel (rsp_demux_010_src0_channel), // .channel
.src0_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_010_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_011 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_014_src_ready), // sink.ready
.sink_channel (router_014_src_channel), // .channel
.sink_data (router_014_src_data), // .data
.sink_startofpacket (router_014_src_startofpacket), // .startofpacket
.sink_endofpacket (router_014_src_endofpacket), // .endofpacket
.sink_valid (router_014_src_valid), // .valid
.src0_ready (rsp_demux_011_src0_ready), // src0.ready
.src0_valid (rsp_demux_011_src0_valid), // .valid
.src0_data (rsp_demux_011_src0_data), // .data
.src0_channel (rsp_demux_011_src0_channel), // .channel
.src0_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_011_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_012 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_015_src_ready), // sink.ready
.sink_channel (router_015_src_channel), // .channel
.sink_data (router_015_src_data), // .data
.sink_startofpacket (router_015_src_startofpacket), // .startofpacket
.sink_endofpacket (router_015_src_endofpacket), // .endofpacket
.sink_valid (router_015_src_valid), // .valid
.src0_ready (rsp_demux_012_src0_ready), // src0.ready
.src0_valid (rsp_demux_012_src0_valid), // .valid
.src0_data (rsp_demux_012_src0_data), // .data
.src0_channel (rsp_demux_012_src0_channel), // .channel
.src0_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_012_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_013 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_016_src_ready), // sink.ready
.sink_channel (router_016_src_channel), // .channel
.sink_data (router_016_src_data), // .data
.sink_startofpacket (router_016_src_startofpacket), // .startofpacket
.sink_endofpacket (router_016_src_endofpacket), // .endofpacket
.sink_valid (router_016_src_valid), // .valid
.src0_ready (rsp_demux_013_src0_ready), // src0.ready
.src0_valid (rsp_demux_013_src0_valid), // .valid
.src0_data (rsp_demux_013_src0_data), // .data
.src0_channel (rsp_demux_013_src0_channel), // .channel
.src0_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_013_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_014 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_017_src_ready), // sink.ready
.sink_channel (router_017_src_channel), // .channel
.sink_data (router_017_src_data), // .data
.sink_startofpacket (router_017_src_startofpacket), // .startofpacket
.sink_endofpacket (router_017_src_endofpacket), // .endofpacket
.sink_valid (router_017_src_valid), // .valid
.src0_ready (rsp_demux_014_src0_ready), // src0.ready
.src0_valid (rsp_demux_014_src0_valid), // .valid
.src0_data (rsp_demux_014_src0_data), // .data
.src0_channel (rsp_demux_014_src0_channel), // .channel
.src0_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_014_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_015 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_018_src_ready), // sink.ready
.sink_channel (router_018_src_channel), // .channel
.sink_data (router_018_src_data), // .data
.sink_startofpacket (router_018_src_startofpacket), // .startofpacket
.sink_endofpacket (router_018_src_endofpacket), // .endofpacket
.sink_valid (router_018_src_valid), // .valid
.src0_ready (rsp_demux_015_src0_ready), // src0.ready
.src0_valid (rsp_demux_015_src0_valid), // .valid
.src0_data (rsp_demux_015_src0_data), // .data
.src0_channel (rsp_demux_015_src0_channel), // .channel
.src0_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_015_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_016 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_019_src_ready), // sink.ready
.sink_channel (router_019_src_channel), // .channel
.sink_data (router_019_src_data), // .data
.sink_startofpacket (router_019_src_startofpacket), // .startofpacket
.sink_endofpacket (router_019_src_endofpacket), // .endofpacket
.sink_valid (router_019_src_valid), // .valid
.src0_ready (rsp_demux_016_src0_ready), // src0.ready
.src0_valid (rsp_demux_016_src0_valid), // .valid
.src0_data (rsp_demux_016_src0_data), // .data
.src0_channel (rsp_demux_016_src0_channel), // .channel
.src0_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_016_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_017 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_020_src_ready), // sink.ready
.sink_channel (router_020_src_channel), // .channel
.sink_data (router_020_src_data), // .data
.sink_startofpacket (router_020_src_startofpacket), // .startofpacket
.sink_endofpacket (router_020_src_endofpacket), // .endofpacket
.sink_valid (router_020_src_valid), // .valid
.src0_ready (rsp_demux_017_src0_ready), // src0.ready
.src0_valid (rsp_demux_017_src0_valid), // .valid
.src0_data (rsp_demux_017_src0_data), // .data
.src0_channel (rsp_demux_017_src0_channel), // .channel
.src0_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_017_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_018 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_021_src_ready), // sink.ready
.sink_channel (router_021_src_channel), // .channel
.sink_data (router_021_src_data), // .data
.sink_startofpacket (router_021_src_startofpacket), // .startofpacket
.sink_endofpacket (router_021_src_endofpacket), // .endofpacket
.sink_valid (router_021_src_valid), // .valid
.src0_ready (rsp_demux_018_src0_ready), // src0.ready
.src0_valid (rsp_demux_018_src0_valid), // .valid
.src0_data (rsp_demux_018_src0_data), // .data
.src0_channel (rsp_demux_018_src0_channel), // .channel
.src0_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_018_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_019 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_022_src_ready), // sink.ready
.sink_channel (router_022_src_channel), // .channel
.sink_data (router_022_src_data), // .data
.sink_startofpacket (router_022_src_startofpacket), // .startofpacket
.sink_endofpacket (router_022_src_endofpacket), // .endofpacket
.sink_valid (router_022_src_valid), // .valid
.src0_ready (rsp_demux_019_src0_ready), // src0.ready
.src0_valid (rsp_demux_019_src0_valid), // .valid
.src0_data (rsp_demux_019_src0_data), // .data
.src0_channel (rsp_demux_019_src0_channel), // .channel
.src0_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_019_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_020 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_023_src_ready), // sink.ready
.sink_channel (router_023_src_channel), // .channel
.sink_data (router_023_src_data), // .data
.sink_startofpacket (router_023_src_startofpacket), // .startofpacket
.sink_endofpacket (router_023_src_endofpacket), // .endofpacket
.sink_valid (router_023_src_valid), // .valid
.src0_ready (rsp_demux_020_src0_ready), // src0.ready
.src0_valid (rsp_demux_020_src0_valid), // .valid
.src0_data (rsp_demux_020_src0_data), // .data
.src0_channel (rsp_demux_020_src0_channel), // .channel
.src0_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_020_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_021 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_024_src_ready), // sink.ready
.sink_channel (router_024_src_channel), // .channel
.sink_data (router_024_src_data), // .data
.sink_startofpacket (router_024_src_startofpacket), // .startofpacket
.sink_endofpacket (router_024_src_endofpacket), // .endofpacket
.sink_valid (router_024_src_valid), // .valid
.src0_ready (rsp_demux_021_src0_ready), // src0.ready
.src0_valid (rsp_demux_021_src0_valid), // .valid
.src0_data (rsp_demux_021_src0_data), // .data
.src0_channel (rsp_demux_021_src0_channel), // .channel
.src0_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_021_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_demux_002 rsp_demux_022 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.sink_ready (router_025_src_ready), // sink.ready
.sink_channel (router_025_src_channel), // .channel
.sink_data (router_025_src_data), // .data
.sink_startofpacket (router_025_src_startofpacket), // .startofpacket
.sink_endofpacket (router_025_src_endofpacket), // .endofpacket
.sink_valid (router_025_src_valid), // .valid
.src0_ready (rsp_demux_022_src0_ready), // src0.ready
.src0_valid (rsp_demux_022_src0_valid), // .valid
.src0_data (rsp_demux_022_src0_data), // .data
.src0_channel (rsp_demux_022_src0_channel), // .channel
.src0_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.src0_endofpacket (rsp_demux_022_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux rsp_mux (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_src_ready), // src.ready
.src_valid (rsp_mux_src_valid), // .valid
.src_data (rsp_mux_src_data), // .data
.src_channel (rsp_mux_src_channel), // .channel
.src_startofpacket (rsp_mux_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_src0_ready), // sink0.ready
.sink0_valid (rsp_demux_src0_valid), // .valid
.sink0_channel (rsp_demux_src0_channel), // .channel
.sink0_data (rsp_demux_src0_data), // .data
.sink0_startofpacket (rsp_demux_src0_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_src0_endofpacket), // .endofpacket
.sink1_ready (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready), // sink1.ready
.sink1_valid (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid), // .valid
.sink1_channel (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel), // .channel
.sink1_data (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data), // .data
.sink1_startofpacket (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink1_endofpacket (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_001 rsp_mux_001 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_001_src_ready), // src.ready
.src_valid (rsp_mux_001_src_valid), // .valid
.src_data (rsp_mux_001_src_data), // .data
.src_channel (rsp_mux_001_src_channel), // .channel
.src_startofpacket (rsp_mux_001_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_001_src_endofpacket), // .endofpacket
.sink0_ready (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // sink0.ready
.sink0_valid (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.sink0_channel (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.sink0_data (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.sink0_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.sink0_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_001_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_001_src1_valid), // .valid
.sink1_channel (rsp_demux_001_src1_channel), // .channel
.sink1_data (rsp_demux_001_src1_data), // .data
.sink1_startofpacket (rsp_demux_001_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_001_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_002_src0_ready), // sink2.ready
.sink2_valid (rsp_demux_002_src0_valid), // .valid
.sink2_channel (rsp_demux_002_src0_channel), // .channel
.sink2_data (rsp_demux_002_src0_data), // .data
.sink2_startofpacket (rsp_demux_002_src0_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_002_src0_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_003_src0_ready), // sink3.ready
.sink3_valid (rsp_demux_003_src0_valid), // .valid
.sink3_channel (rsp_demux_003_src0_channel), // .channel
.sink3_data (rsp_demux_003_src0_data), // .data
.sink3_startofpacket (rsp_demux_003_src0_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_003_src0_endofpacket), // .endofpacket
.sink4_ready (rsp_demux_004_src0_ready), // sink4.ready
.sink4_valid (rsp_demux_004_src0_valid), // .valid
.sink4_channel (rsp_demux_004_src0_channel), // .channel
.sink4_data (rsp_demux_004_src0_data), // .data
.sink4_startofpacket (rsp_demux_004_src0_startofpacket), // .startofpacket
.sink4_endofpacket (rsp_demux_004_src0_endofpacket), // .endofpacket
.sink5_ready (rsp_demux_005_src0_ready), // sink5.ready
.sink5_valid (rsp_demux_005_src0_valid), // .valid
.sink5_channel (rsp_demux_005_src0_channel), // .channel
.sink5_data (rsp_demux_005_src0_data), // .data
.sink5_startofpacket (rsp_demux_005_src0_startofpacket), // .startofpacket
.sink5_endofpacket (rsp_demux_005_src0_endofpacket), // .endofpacket
.sink6_ready (rsp_demux_006_src0_ready), // sink6.ready
.sink6_valid (rsp_demux_006_src0_valid), // .valid
.sink6_channel (rsp_demux_006_src0_channel), // .channel
.sink6_data (rsp_demux_006_src0_data), // .data
.sink6_startofpacket (rsp_demux_006_src0_startofpacket), // .startofpacket
.sink6_endofpacket (rsp_demux_006_src0_endofpacket), // .endofpacket
.sink7_ready (rsp_demux_007_src0_ready), // sink7.ready
.sink7_valid (rsp_demux_007_src0_valid), // .valid
.sink7_channel (rsp_demux_007_src0_channel), // .channel
.sink7_data (rsp_demux_007_src0_data), // .data
.sink7_startofpacket (rsp_demux_007_src0_startofpacket), // .startofpacket
.sink7_endofpacket (rsp_demux_007_src0_endofpacket), // .endofpacket
.sink8_ready (crosser_001_out_ready), // sink8.ready
.sink8_valid (crosser_001_out_valid), // .valid
.sink8_channel (crosser_001_out_channel), // .channel
.sink8_data (crosser_001_out_data), // .data
.sink8_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.sink8_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.sink9_ready (rsp_demux_009_src0_ready), // sink9.ready
.sink9_valid (rsp_demux_009_src0_valid), // .valid
.sink9_channel (rsp_demux_009_src0_channel), // .channel
.sink9_data (rsp_demux_009_src0_data), // .data
.sink9_startofpacket (rsp_demux_009_src0_startofpacket), // .startofpacket
.sink9_endofpacket (rsp_demux_009_src0_endofpacket), // .endofpacket
.sink10_ready (rsp_demux_010_src0_ready), // sink10.ready
.sink10_valid (rsp_demux_010_src0_valid), // .valid
.sink10_channel (rsp_demux_010_src0_channel), // .channel
.sink10_data (rsp_demux_010_src0_data), // .data
.sink10_startofpacket (rsp_demux_010_src0_startofpacket), // .startofpacket
.sink10_endofpacket (rsp_demux_010_src0_endofpacket), // .endofpacket
.sink11_ready (rsp_demux_011_src0_ready), // sink11.ready
.sink11_valid (rsp_demux_011_src0_valid), // .valid
.sink11_channel (rsp_demux_011_src0_channel), // .channel
.sink11_data (rsp_demux_011_src0_data), // .data
.sink11_startofpacket (rsp_demux_011_src0_startofpacket), // .startofpacket
.sink11_endofpacket (rsp_demux_011_src0_endofpacket), // .endofpacket
.sink12_ready (rsp_demux_012_src0_ready), // sink12.ready
.sink12_valid (rsp_demux_012_src0_valid), // .valid
.sink12_channel (rsp_demux_012_src0_channel), // .channel
.sink12_data (rsp_demux_012_src0_data), // .data
.sink12_startofpacket (rsp_demux_012_src0_startofpacket), // .startofpacket
.sink12_endofpacket (rsp_demux_012_src0_endofpacket), // .endofpacket
.sink13_ready (rsp_demux_013_src0_ready), // sink13.ready
.sink13_valid (rsp_demux_013_src0_valid), // .valid
.sink13_channel (rsp_demux_013_src0_channel), // .channel
.sink13_data (rsp_demux_013_src0_data), // .data
.sink13_startofpacket (rsp_demux_013_src0_startofpacket), // .startofpacket
.sink13_endofpacket (rsp_demux_013_src0_endofpacket), // .endofpacket
.sink14_ready (rsp_demux_014_src0_ready), // sink14.ready
.sink14_valid (rsp_demux_014_src0_valid), // .valid
.sink14_channel (rsp_demux_014_src0_channel), // .channel
.sink14_data (rsp_demux_014_src0_data), // .data
.sink14_startofpacket (rsp_demux_014_src0_startofpacket), // .startofpacket
.sink14_endofpacket (rsp_demux_014_src0_endofpacket), // .endofpacket
.sink15_ready (rsp_demux_015_src0_ready), // sink15.ready
.sink15_valid (rsp_demux_015_src0_valid), // .valid
.sink15_channel (rsp_demux_015_src0_channel), // .channel
.sink15_data (rsp_demux_015_src0_data), // .data
.sink15_startofpacket (rsp_demux_015_src0_startofpacket), // .startofpacket
.sink15_endofpacket (rsp_demux_015_src0_endofpacket), // .endofpacket
.sink16_ready (rsp_demux_016_src0_ready), // sink16.ready
.sink16_valid (rsp_demux_016_src0_valid), // .valid
.sink16_channel (rsp_demux_016_src0_channel), // .channel
.sink16_data (rsp_demux_016_src0_data), // .data
.sink16_startofpacket (rsp_demux_016_src0_startofpacket), // .startofpacket
.sink16_endofpacket (rsp_demux_016_src0_endofpacket), // .endofpacket
.sink17_ready (rsp_demux_017_src0_ready), // sink17.ready
.sink17_valid (rsp_demux_017_src0_valid), // .valid
.sink17_channel (rsp_demux_017_src0_channel), // .channel
.sink17_data (rsp_demux_017_src0_data), // .data
.sink17_startofpacket (rsp_demux_017_src0_startofpacket), // .startofpacket
.sink17_endofpacket (rsp_demux_017_src0_endofpacket), // .endofpacket
.sink18_ready (rsp_demux_018_src0_ready), // sink18.ready
.sink18_valid (rsp_demux_018_src0_valid), // .valid
.sink18_channel (rsp_demux_018_src0_channel), // .channel
.sink18_data (rsp_demux_018_src0_data), // .data
.sink18_startofpacket (rsp_demux_018_src0_startofpacket), // .startofpacket
.sink18_endofpacket (rsp_demux_018_src0_endofpacket), // .endofpacket
.sink19_ready (rsp_demux_019_src0_ready), // sink19.ready
.sink19_valid (rsp_demux_019_src0_valid), // .valid
.sink19_channel (rsp_demux_019_src0_channel), // .channel
.sink19_data (rsp_demux_019_src0_data), // .data
.sink19_startofpacket (rsp_demux_019_src0_startofpacket), // .startofpacket
.sink19_endofpacket (rsp_demux_019_src0_endofpacket), // .endofpacket
.sink20_ready (rsp_demux_020_src0_ready), // sink20.ready
.sink20_valid (rsp_demux_020_src0_valid), // .valid
.sink20_channel (rsp_demux_020_src0_channel), // .channel
.sink20_data (rsp_demux_020_src0_data), // .data
.sink20_startofpacket (rsp_demux_020_src0_startofpacket), // .startofpacket
.sink20_endofpacket (rsp_demux_020_src0_endofpacket), // .endofpacket
.sink21_ready (rsp_demux_021_src0_ready), // sink21.ready
.sink21_valid (rsp_demux_021_src0_valid), // .valid
.sink21_channel (rsp_demux_021_src0_channel), // .channel
.sink21_data (rsp_demux_021_src0_data), // .data
.sink21_startofpacket (rsp_demux_021_src0_startofpacket), // .startofpacket
.sink21_endofpacket (rsp_demux_021_src0_endofpacket), // .endofpacket
.sink22_ready (rsp_demux_022_src0_ready), // sink22.ready
.sink22_valid (rsp_demux_022_src0_valid), // .valid
.sink22_channel (rsp_demux_022_src0_channel), // .channel
.sink22_data (rsp_demux_022_src0_data), // .data
.sink22_startofpacket (rsp_demux_022_src0_startofpacket), // .startofpacket
.sink22_endofpacket (rsp_demux_022_src0_endofpacket) // .endofpacket
);
wasca_mm_interconnect_0_rsp_mux_002 rsp_mux_002 (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.src_ready (rsp_mux_002_src_ready), // src.ready
.src_valid (rsp_mux_002_src_valid), // .valid
.src_data (rsp_mux_002_src_data), // .data
.src_channel (rsp_mux_002_src_channel), // .channel
.src_startofpacket (rsp_mux_002_src_startofpacket), // .startofpacket
.src_endofpacket (rsp_mux_002_src_endofpacket), // .endofpacket
.sink0_ready (rsp_demux_001_src2_ready), // sink0.ready
.sink0_valid (rsp_demux_001_src2_valid), // .valid
.sink0_channel (rsp_demux_001_src2_channel), // .channel
.sink0_data (rsp_demux_001_src2_data), // .data
.sink0_startofpacket (rsp_demux_001_src2_startofpacket), // .startofpacket
.sink0_endofpacket (rsp_demux_001_src2_endofpacket), // .endofpacket
.sink1_ready (rsp_demux_006_src1_ready), // sink1.ready
.sink1_valid (rsp_demux_006_src1_valid), // .valid
.sink1_channel (rsp_demux_006_src1_channel), // .channel
.sink1_data (rsp_demux_006_src1_data), // .data
.sink1_startofpacket (rsp_demux_006_src1_startofpacket), // .startofpacket
.sink1_endofpacket (rsp_demux_006_src1_endofpacket), // .endofpacket
.sink2_ready (rsp_demux_007_src1_ready), // sink2.ready
.sink2_valid (rsp_demux_007_src1_valid), // .valid
.sink2_channel (rsp_demux_007_src1_channel), // .channel
.sink2_data (rsp_demux_007_src1_data), // .data
.sink2_startofpacket (rsp_demux_007_src1_startofpacket), // .startofpacket
.sink2_endofpacket (rsp_demux_007_src1_endofpacket), // .endofpacket
.sink3_ready (rsp_demux_009_src1_ready), // sink3.ready
.sink3_valid (rsp_demux_009_src1_valid), // .valid
.sink3_channel (rsp_demux_009_src1_channel), // .channel
.sink3_data (rsp_demux_009_src1_data), // .data
.sink3_startofpacket (rsp_demux_009_src1_startofpacket), // .startofpacket
.sink3_endofpacket (rsp_demux_009_src1_endofpacket) // .endofpacket
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (45),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (57),
.IN_PKT_BYTE_CNT_L (52),
.IN_PKT_TRANS_COMPRESSED_READ (46),
.IN_PKT_TRANS_WRITE (48),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (58),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (89),
.IN_PKT_RESPONSE_STATUS_L (88),
.IN_PKT_TRANS_EXCLUSIVE (51),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (90),
.IN_PKT_ORI_BURST_SIZE_H (92),
.IN_ST_DATA_W (93),
.OUT_PKT_ADDR_H (63),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (70),
.OUT_PKT_TRANS_COMPRESSED_READ (64),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (107),
.OUT_PKT_RESPONSE_STATUS_L (106),
.OUT_PKT_TRANS_EXCLUSIVE (69),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (108),
.OUT_PKT_ORI_BURST_SIZE_H (110),
.OUT_ST_DATA_W (111),
.ST_CHANNEL_W (23),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_src1_valid), // sink.valid
.in_channel (cmd_demux_src1_channel), // .channel
.in_startofpacket (cmd_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_src1_endofpacket), // .endofpacket
.in_ready (cmd_demux_src1_ready), // .ready
.in_data (cmd_demux_src1_data), // .data
.out_endofpacket (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_data), // .data
.out_channel (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (abus_slave_0_avalon_master_to_onchip_memory2_1_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (63),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (70),
.IN_PKT_TRANS_COMPRESSED_READ (64),
.IN_PKT_TRANS_WRITE (66),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (107),
.IN_PKT_RESPONSE_STATUS_L (106),
.IN_PKT_TRANS_EXCLUSIVE (69),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (108),
.IN_PKT_ORI_BURST_SIZE_H (110),
.IN_ST_DATA_W (111),
.OUT_PKT_ADDR_H (45),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (57),
.OUT_PKT_BYTE_CNT_L (52),
.OUT_PKT_TRANS_COMPRESSED_READ (46),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (89),
.OUT_PKT_RESPONSE_STATUS_L (88),
.OUT_PKT_TRANS_EXCLUSIVE (51),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (90),
.OUT_PKT_ORI_BURST_SIZE_H (92),
.OUT_ST_DATA_W (93),
.ST_CHANNEL_W (23),
.OPTIMIZE_FOR_RSP (0),
.RESPONSE_PATH (0),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (cmd_demux_001_src0_valid), // sink.valid
.in_channel (cmd_demux_001_src0_channel), // .channel
.in_startofpacket (cmd_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src0_endofpacket), // .endofpacket
.in_ready (cmd_demux_001_src0_ready), // .ready
.in_data (cmd_demux_001_src0_data), // .data
.out_endofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_endofpacket), // src.endofpacket
.out_data (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_data), // .data
.out_channel (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_channel), // .channel
.out_valid (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_valid), // .valid
.out_ready (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_ready), // .ready
.out_startofpacket (nios2_gen2_0_data_master_to_external_sdram_controller_s1_cmd_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (45),
.IN_PKT_ADDR_L (18),
.IN_PKT_DATA_H (15),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (17),
.IN_PKT_BYTEEN_L (16),
.IN_PKT_BYTE_CNT_H (57),
.IN_PKT_BYTE_CNT_L (52),
.IN_PKT_TRANS_COMPRESSED_READ (46),
.IN_PKT_TRANS_WRITE (48),
.IN_PKT_BURSTWRAP_H (60),
.IN_PKT_BURSTWRAP_L (58),
.IN_PKT_BURST_SIZE_H (63),
.IN_PKT_BURST_SIZE_L (61),
.IN_PKT_RESPONSE_STATUS_H (89),
.IN_PKT_RESPONSE_STATUS_L (88),
.IN_PKT_TRANS_EXCLUSIVE (51),
.IN_PKT_BURST_TYPE_H (65),
.IN_PKT_BURST_TYPE_L (64),
.IN_PKT_ORI_BURST_SIZE_L (90),
.IN_PKT_ORI_BURST_SIZE_H (92),
.IN_ST_DATA_W (93),
.OUT_PKT_ADDR_H (63),
.OUT_PKT_ADDR_L (36),
.OUT_PKT_DATA_H (31),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (35),
.OUT_PKT_BYTEEN_L (32),
.OUT_PKT_BYTE_CNT_H (75),
.OUT_PKT_BYTE_CNT_L (70),
.OUT_PKT_TRANS_COMPRESSED_READ (64),
.OUT_PKT_BURST_SIZE_H (81),
.OUT_PKT_BURST_SIZE_L (79),
.OUT_PKT_RESPONSE_STATUS_H (107),
.OUT_PKT_RESPONSE_STATUS_L (106),
.OUT_PKT_TRANS_EXCLUSIVE (69),
.OUT_PKT_BURST_TYPE_H (83),
.OUT_PKT_BURST_TYPE_L (82),
.OUT_PKT_ORI_BURST_SIZE_L (108),
.OUT_PKT_ORI_BURST_SIZE_H (110),
.OUT_ST_DATA_W (111),
.ST_CHANNEL_W (23),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_src1_valid), // sink.valid
.in_channel (rsp_demux_src1_channel), // .channel
.in_startofpacket (rsp_demux_src1_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_src1_endofpacket), // .endofpacket
.in_ready (rsp_demux_src1_ready), // .ready
.in_data (rsp_demux_src1_data), // .data
.out_endofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_data), // .data
.out_channel (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_channel), // .channel
.out_valid (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_valid), // .valid
.out_ready (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (external_sdram_controller_s1_to_nios2_gen2_0_data_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_merlin_width_adapter #(
.IN_PKT_ADDR_H (63),
.IN_PKT_ADDR_L (36),
.IN_PKT_DATA_H (31),
.IN_PKT_DATA_L (0),
.IN_PKT_BYTEEN_H (35),
.IN_PKT_BYTEEN_L (32),
.IN_PKT_BYTE_CNT_H (75),
.IN_PKT_BYTE_CNT_L (70),
.IN_PKT_TRANS_COMPRESSED_READ (64),
.IN_PKT_TRANS_WRITE (66),
.IN_PKT_BURSTWRAP_H (78),
.IN_PKT_BURSTWRAP_L (76),
.IN_PKT_BURST_SIZE_H (81),
.IN_PKT_BURST_SIZE_L (79),
.IN_PKT_RESPONSE_STATUS_H (107),
.IN_PKT_RESPONSE_STATUS_L (106),
.IN_PKT_TRANS_EXCLUSIVE (69),
.IN_PKT_BURST_TYPE_H (83),
.IN_PKT_BURST_TYPE_L (82),
.IN_PKT_ORI_BURST_SIZE_L (108),
.IN_PKT_ORI_BURST_SIZE_H (110),
.IN_ST_DATA_W (111),
.OUT_PKT_ADDR_H (45),
.OUT_PKT_ADDR_L (18),
.OUT_PKT_DATA_H (15),
.OUT_PKT_DATA_L (0),
.OUT_PKT_BYTEEN_H (17),
.OUT_PKT_BYTEEN_L (16),
.OUT_PKT_BYTE_CNT_H (57),
.OUT_PKT_BYTE_CNT_L (52),
.OUT_PKT_TRANS_COMPRESSED_READ (46),
.OUT_PKT_BURST_SIZE_H (63),
.OUT_PKT_BURST_SIZE_L (61),
.OUT_PKT_RESPONSE_STATUS_H (89),
.OUT_PKT_RESPONSE_STATUS_L (88),
.OUT_PKT_TRANS_EXCLUSIVE (51),
.OUT_PKT_BURST_TYPE_H (65),
.OUT_PKT_BURST_TYPE_L (64),
.OUT_PKT_ORI_BURST_SIZE_L (90),
.OUT_PKT_ORI_BURST_SIZE_H (92),
.OUT_ST_DATA_W (93),
.ST_CHANNEL_W (23),
.OPTIMIZE_FOR_RSP (1),
.RESPONSE_PATH (1),
.CONSTANT_BURST_SIZE (1),
.PACKING (1),
.ENABLE_ADDRESS_ALIGNMENT (0)
) onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter (
.clk (altpll_0_c0_clk), // clk.clk
.reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // clk_reset.reset
.in_valid (rsp_demux_001_src0_valid), // sink.valid
.in_channel (rsp_demux_001_src0_channel), // .channel
.in_startofpacket (rsp_demux_001_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_001_src0_endofpacket), // .endofpacket
.in_ready (rsp_demux_001_src0_ready), // .ready
.in_data (rsp_demux_001_src0_data), // .data
.out_endofpacket (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_endofpacket), // src.endofpacket
.out_data (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_data), // .data
.out_channel (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_channel), // .channel
.out_valid (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_valid), // .valid
.out_ready (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_ready), // .ready
.out_startofpacket (onchip_memory2_1_s1_to_abus_slave_0_avalon_master_rsp_width_adapter_src_startofpacket), // .startofpacket
.in_command_size_data (3'b000) // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (111),
.BITS_PER_SYMBOL (111),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (23),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser (
.in_clk (altpll_0_c0_clk), // in_clk.clk
.in_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (clk_0_clk_clk), // out_clk.clk
.out_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (cmd_demux_001_src8_ready), // in.ready
.in_valid (cmd_demux_001_src8_valid), // .valid
.in_startofpacket (cmd_demux_001_src8_startofpacket), // .startofpacket
.in_endofpacket (cmd_demux_001_src8_endofpacket), // .endofpacket
.in_channel (cmd_demux_001_src8_channel), // .channel
.in_data (cmd_demux_001_src8_data), // .data
.out_ready (crosser_out_ready), // out.ready
.out_valid (crosser_out_valid), // .valid
.out_startofpacket (crosser_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_out_endofpacket), // .endofpacket
.out_channel (crosser_out_channel), // .channel
.out_data (crosser_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
altera_avalon_st_handshake_clock_crosser #(
.DATA_WIDTH (111),
.BITS_PER_SYMBOL (111),
.USE_PACKETS (1),
.USE_CHANNEL (1),
.CHANNEL_WIDTH (23),
.USE_ERROR (0),
.ERROR_WIDTH (1),
.VALID_SYNC_DEPTH (2),
.READY_SYNC_DEPTH (2),
.USE_OUTPUT_PIPELINE (0)
) crosser_001 (
.in_clk (clk_0_clk_clk), // in_clk.clk
.in_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // in_clk_reset.reset
.out_clk (altpll_0_c0_clk), // out_clk.clk
.out_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // out_clk_reset.reset
.in_ready (rsp_demux_008_src0_ready), // in.ready
.in_valid (rsp_demux_008_src0_valid), // .valid
.in_startofpacket (rsp_demux_008_src0_startofpacket), // .startofpacket
.in_endofpacket (rsp_demux_008_src0_endofpacket), // .endofpacket
.in_channel (rsp_demux_008_src0_channel), // .channel
.in_data (rsp_demux_008_src0_data), // .data
.out_ready (crosser_001_out_ready), // out.ready
.out_valid (crosser_001_out_valid), // .valid
.out_startofpacket (crosser_001_out_startofpacket), // .startofpacket
.out_endofpacket (crosser_001_out_endofpacket), // .endofpacket
.out_channel (crosser_001_out_channel), // .channel
.out_data (crosser_001_out_data), // .data
.in_empty (1'b0), // (terminated)
.in_error (1'b0), // (terminated)
.out_empty (), // (terminated)
.out_error () // (terminated)
);
wasca_mm_interconnect_0_avalon_st_adapter #(
.inBitsPerSymbol (18),
.inUsePackets (0),
.inDataWidth (18),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (18),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (external_sdram_controller_s1_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (external_sdram_controller_s1_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (external_sdram_controller_s1_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_001 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_001_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_001_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_001_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_001_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_002 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_slave_0_avalon_nios_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_slave_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_slave_0_avalon_nios_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_002_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_002_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_002_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_002_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_003 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (abus_demux_0_avalon_nios_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (abus_demux_0_avalon_nios_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (abus_demux_0_avalon_nios_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_003_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_003_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_003_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_003_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_004 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (performance_counter_0_control_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (performance_counter_0_control_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (performance_counter_0_control_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_004_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_004_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_004_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_004_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_005 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_flash_0_csr_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_flash_0_csr_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_flash_0_csr_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_005_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_005_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_005_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_005_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_006 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_flash_0_data_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_flash_0_data_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_flash_0_data_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_006_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_006_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_006_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_006_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_007 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (nios2_gen2_0_debug_mem_slave_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_007_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_007_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_007_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_007_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_008 (
.in_clk_0_clk (clk_0_clk_clk), // in_clk_0.clk
.in_rst_0_reset (altpll_0_inclk_interface_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (altpll_0_pll_slave_agent_rdata_fifo_out_data), // in_0.data
.in_0_valid (altpll_0_pll_slave_agent_rdata_fifo_out_valid), // .valid
.in_0_ready (altpll_0_pll_slave_agent_rdata_fifo_out_ready), // .ready
.out_0_data (avalon_st_adapter_008_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_008_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_008_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_008_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_009 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (onchip_memory2_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (onchip_memory2_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (onchip_memory2_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_009_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_009_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_009_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_009_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_010 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (switches_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (switches_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (switches_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_010_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_010_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_010_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_010_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_011 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (leds_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (leds_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (leds_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_011_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_011_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_011_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_011_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_012 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (uart_0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (uart_0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (uart_0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_012_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_012_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_012_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_012_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_013 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex0_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex0_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex0_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_013_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_013_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_013_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_013_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_014 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex1_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex1_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex1_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_014_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_014_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_014_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_014_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_015 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex2_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex2_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex2_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_015_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_015_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_015_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_015_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_016 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex3_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex3_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex3_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_016_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_016_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_016_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_016_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_017 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex4_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex4_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex4_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_017_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_017_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_017_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_017_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_018 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hex5_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hex5_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hex5_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_018_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_018_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_018_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_018_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_019 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (hexdot_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (hexdot_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (hexdot_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_019_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_019_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_019_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_019_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_020 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (spi_sync_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (spi_sync_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (spi_sync_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_020_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_020_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_020_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_020_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_021 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (extra_leds_s1_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (extra_leds_s1_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (extra_leds_s1_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_021_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_021_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_021_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_021_out_0_error) // .error
);
wasca_mm_interconnect_0_avalon_st_adapter_001 #(
.inBitsPerSymbol (34),
.inUsePackets (0),
.inDataWidth (34),
.inChannelWidth (0),
.inErrorWidth (0),
.inUseEmptyPort (0),
.inUseValid (1),
.inUseReady (1),
.inReadyLatency (0),
.outDataWidth (34),
.outChannelWidth (0),
.outErrorWidth (1),
.outUseEmptyPort (0),
.outUseValid (1),
.outUseReady (1),
.outReadyLatency (0)
) avalon_st_adapter_022 (
.in_clk_0_clk (altpll_0_c0_clk), // in_clk_0.clk
.in_rst_0_reset (abus_slave_0_reset_reset_bridge_in_reset_reset), // in_rst_0.reset
.in_0_data (spi_stm32_spi_control_port_agent_rdata_fifo_src_data), // in_0.data
.in_0_valid (spi_stm32_spi_control_port_agent_rdata_fifo_src_valid), // .valid
.in_0_ready (spi_stm32_spi_control_port_agent_rdata_fifo_src_ready), // .ready
.out_0_data (avalon_st_adapter_022_out_0_data), // out_0.data
.out_0_valid (avalon_st_adapter_022_out_0_valid), // .valid
.out_0_ready (avalon_st_adapter_022_out_0_ready), // .ready
.out_0_error (avalon_st_adapter_022_out_0_error) // .error
);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__INV_BEHAVIORAL_PP_V
`define SKY130_FD_SC_HS__INV_BEHAVIORAL_PP_V
/**
* inv: Inverter.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__inv (
VPWR,
VGND,
Y ,
A
);
// Module ports
input VPWR;
input VGND;
output Y ;
input A ;
// Local signals
wire not0_out_Y ;
wire u_vpwr_vgnd0_out_Y;
// Name Output Other arguments
not not0 (not0_out_Y , A );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_Y, not0_out_Y, VPWR, VGND);
buf buf0 (Y , u_vpwr_vgnd0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__INV_BEHAVIORAL_PP_V |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2008 by Wilson Snyder.
`include "verilated.v"
module t;
// Note $sscanf already tested elsewhere
reg [3:0] n;
reg [63:0] q;
reg [16*8:1] wide;
reg [8:1] char;
reg [48*8:1] str;
reg [48*8:1] str2;
real r;
initial begin
n = 4'b1100;
q = 64'h1234_5678_abcd_0123;
wide = "hello-there12345";
$sformat(str, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str=%0s",str); `endif
if (str !== "n=1100 q= 1311768467750060323 w=hello-there12345") $stop;
q = {q[62:0],1'b1};
$swrite(str2, "n=%b q=%d w=%s", n, q, wide);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "n=1100 q= 2623536935500120647 w=hello-there12345") $stop;
$swrite(str2, "e=%e", r);
$swrite(str2, "e=%f", r);
$swrite(str2, "e=%g", r);
r = 0.01;
$swrite(str2, "e=%e f=%f g=%g", r, r, r);
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
if (str2 !== "e=1.000000e-02 f=0.010000 g=0.01") $stop;
$swrite(str2, "mod=%m");
`ifdef TEST_VERBOSE $display("str2=%0s",str2); `endif
`ifdef verilator
if (str2 !== "mod=top.v") $stop;
`else
if (str2 !== "mod=top.t") $stop;
`endif
$sformat(char,"%s","c");
if (char != "c") $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2017.3 (win64) Build 2018833 Wed Oct 4 19:58:22 MDT 2017
// Date : Fri Nov 17 14:53:08 2017
// Host : egk-pc running 64-bit major release (build 9200)
// Command : write_verilog -force -mode funcsim -rename_top DemoInterconnect_auto_pc_0 -prefix
// DemoInterconnect_auto_pc_0_ DemoInterconnect_auto_pc_0_sim_netlist.v
// Design : DemoInterconnect_auto_pc_0
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a15tcpg236-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* CHECK_LICENSE_TYPE = "DemoInterconnect_auto_pc_0,axi_protocol_converter_v2_1_14_axi_protocol_converter,{}" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* X_CORE_INFO = "axi_protocol_converter_v2_1_14_axi_protocol_converter,Vivado 2017.3" *)
(* NotValidForBitStream *)
module DemoInterconnect_auto_pc_0
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awvalid,
s_axi_awready,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_rvalid,
s_axi_rready,
m_axi_awaddr,
m_axi_awprot,
m_axi_awvalid,
m_axi_awready,
m_axi_wdata,
m_axi_wstrb,
m_axi_wvalid,
m_axi_wready,
m_axi_bresp,
m_axi_bvalid,
m_axi_bready,
m_axi_araddr,
m_axi_arprot,
m_axi_arvalid,
m_axi_arready,
m_axi_rdata,
m_axi_rresp,
m_axi_rvalid,
m_axi_rready);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 CLK CLK" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME CLK, FREQ_HZ 72000000, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, ASSOCIATED_BUSIF S_AXI:M_AXI, ASSOCIATED_RESET ARESETN" *) input aclk;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 RST RST" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME RST, POLARITY ACTIVE_LOW, TYPE INTERCONNECT" *) input aresetn;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWID" *) input [0:0]s_axi_awid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWADDR" *) input [31:0]s_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLEN" *) input [7:0]s_axi_awlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWSIZE" *) input [2:0]s_axi_awsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWBURST" *) input [1:0]s_axi_awburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWLOCK" *) input [0:0]s_axi_awlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWCACHE" *) input [3:0]s_axi_awcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWPROT" *) input [2:0]s_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREGION" *) input [3:0]s_axi_awregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWQOS" *) input [3:0]s_axi_awqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWVALID" *) input s_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI AWREADY" *) output s_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WDATA" *) input [31:0]s_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WSTRB" *) input [3:0]s_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WLAST" *) input s_axi_wlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WVALID" *) input s_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI WREADY" *) output s_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BID" *) output [0:0]s_axi_bid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BRESP" *) output [1:0]s_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BVALID" *) output s_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI BREADY" *) input s_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARID" *) input [0:0]s_axi_arid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARADDR" *) input [31:0]s_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLEN" *) input [7:0]s_axi_arlen;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARSIZE" *) input [2:0]s_axi_arsize;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARBURST" *) input [1:0]s_axi_arburst;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARLOCK" *) input [0:0]s_axi_arlock;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARCACHE" *) input [3:0]s_axi_arcache;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARPROT" *) input [2:0]s_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREGION" *) input [3:0]s_axi_arregion;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARQOS" *) input [3:0]s_axi_arqos;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARVALID" *) input s_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI ARREADY" *) output s_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RID" *) output [0:0]s_axi_rid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RDATA" *) output [31:0]s_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RRESP" *) output [1:0]s_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RLAST" *) output s_axi_rlast;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RVALID" *) output s_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 S_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME S_AXI, DATA_WIDTH 32, PROTOCOL AXI4, FREQ_HZ 72000000, ID_WIDTH 1, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 1, HAS_LOCK 1, HAS_PROT 1, HAS_CACHE 1, HAS_QOS 1, HAS_REGION 1, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 256, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) input s_axi_rready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWADDR" *) output [31:0]m_axi_awaddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWPROT" *) output [2:0]m_axi_awprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWVALID" *) output m_axi_awvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI AWREADY" *) input m_axi_awready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WDATA" *) output [31:0]m_axi_wdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WSTRB" *) output [3:0]m_axi_wstrb;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WVALID" *) output m_axi_wvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI WREADY" *) input m_axi_wready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BRESP" *) input [1:0]m_axi_bresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BVALID" *) input m_axi_bvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI BREADY" *) output m_axi_bready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARADDR" *) output [31:0]m_axi_araddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARPROT" *) output [2:0]m_axi_arprot;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARVALID" *) output m_axi_arvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI ARREADY" *) input m_axi_arready;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RDATA" *) input [31:0]m_axi_rdata;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RRESP" *) input [1:0]m_axi_rresp;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RVALID" *) input m_axi_rvalid;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 M_AXI RREADY" *) (* X_INTERFACE_PARAMETER = "XIL_INTERFACENAME M_AXI, DATA_WIDTH 32, PROTOCOL AXI4LITE, FREQ_HZ 72000000, ID_WIDTH 0, ADDR_WIDTH 32, AWUSER_WIDTH 0, ARUSER_WIDTH 0, WUSER_WIDTH 0, RUSER_WIDTH 0, BUSER_WIDTH 0, READ_WRITE_MODE READ_WRITE, HAS_BURST 0, HAS_LOCK 0, HAS_PROT 1, HAS_CACHE 0, HAS_QOS 0, HAS_REGION 0, HAS_WSTRB 1, HAS_BRESP 1, HAS_RRESP 1, SUPPORTS_NARROW_BURST 0, NUM_READ_OUTSTANDING 2, NUM_WRITE_OUTSTANDING 2, MAX_BURST_LENGTH 1, PHASE 0.0, CLK_DOMAIN /clk_wiz_0_clk_out1, NUM_READ_THREADS 1, NUM_WRITE_THREADS 1, RUSER_BITS_PER_BYTE 0, WUSER_BITS_PER_BYTE 0" *) output m_axi_rready;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire [31:0]m_axi_wdata;
wire m_axi_wready;
wire [3:0]m_axi_wstrb;
wire m_axi_wvalid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [3:0]s_axi_arcache;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [0:0]s_axi_arlock;
wire [2:0]s_axi_arprot;
wire [3:0]s_axi_arqos;
wire s_axi_arready;
wire [3:0]s_axi_arregion;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [3:0]s_axi_awcache;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [0:0]s_axi_awlock;
wire [2:0]s_axi_awprot;
wire [3:0]s_axi_awqos;
wire s_axi_awready;
wire [3:0]s_axi_awregion;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire s_axi_wlast;
wire s_axi_wready;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
wire NLW_inst_m_axi_wlast_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_arburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_arlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_arlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_arregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_arsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_aruser_UNCONNECTED;
wire [1:0]NLW_inst_m_axi_awburst_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awcache_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awid_UNCONNECTED;
wire [7:0]NLW_inst_m_axi_awlen_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awlock_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awqos_UNCONNECTED;
wire [3:0]NLW_inst_m_axi_awregion_UNCONNECTED;
wire [2:0]NLW_inst_m_axi_awsize_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_awuser_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wid_UNCONNECTED;
wire [0:0]NLW_inst_m_axi_wuser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_buser_UNCONNECTED;
wire [0:0]NLW_inst_s_axi_ruser_UNCONNECTED;
(* C_AXI_ADDR_WIDTH = "32" *)
(* C_AXI_ARUSER_WIDTH = "1" *)
(* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *)
(* C_AXI_DATA_WIDTH = "32" *)
(* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *)
(* C_AXI_SUPPORTS_READ = "1" *)
(* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *)
(* C_AXI_WUSER_WIDTH = "1" *)
(* C_FAMILY = "artix7" *)
(* C_IGNORE_ID = "0" *)
(* C_M_AXI_PROTOCOL = "2" *)
(* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
(* P_AXI3 = "1" *)
(* P_AXI4 = "0" *)
(* P_AXILITE = "2" *)
(* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *)
(* P_DECERR = "2'b11" *)
(* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *)
(* P_SLVERR = "2'b10" *)
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter inst
(.aclk(aclk),
.aresetn(aresetn),
.m_axi_araddr(m_axi_araddr),
.m_axi_arburst(NLW_inst_m_axi_arburst_UNCONNECTED[1:0]),
.m_axi_arcache(NLW_inst_m_axi_arcache_UNCONNECTED[3:0]),
.m_axi_arid(NLW_inst_m_axi_arid_UNCONNECTED[0]),
.m_axi_arlen(NLW_inst_m_axi_arlen_UNCONNECTED[7:0]),
.m_axi_arlock(NLW_inst_m_axi_arlock_UNCONNECTED[0]),
.m_axi_arprot(m_axi_arprot),
.m_axi_arqos(NLW_inst_m_axi_arqos_UNCONNECTED[3:0]),
.m_axi_arready(m_axi_arready),
.m_axi_arregion(NLW_inst_m_axi_arregion_UNCONNECTED[3:0]),
.m_axi_arsize(NLW_inst_m_axi_arsize_UNCONNECTED[2:0]),
.m_axi_aruser(NLW_inst_m_axi_aruser_UNCONNECTED[0]),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awburst(NLW_inst_m_axi_awburst_UNCONNECTED[1:0]),
.m_axi_awcache(NLW_inst_m_axi_awcache_UNCONNECTED[3:0]),
.m_axi_awid(NLW_inst_m_axi_awid_UNCONNECTED[0]),
.m_axi_awlen(NLW_inst_m_axi_awlen_UNCONNECTED[7:0]),
.m_axi_awlock(NLW_inst_m_axi_awlock_UNCONNECTED[0]),
.m_axi_awprot(m_axi_awprot),
.m_axi_awqos(NLW_inst_m_axi_awqos_UNCONNECTED[3:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awregion(NLW_inst_m_axi_awregion_UNCONNECTED[3:0]),
.m_axi_awsize(NLW_inst_m_axi_awsize_UNCONNECTED[2:0]),
.m_axi_awuser(NLW_inst_m_axi_awuser_UNCONNECTED[0]),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bid(1'b0),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rdata(m_axi_rdata),
.m_axi_rid(1'b0),
.m_axi_rlast(1'b1),
.m_axi_rready(m_axi_rready),
.m_axi_rresp(m_axi_rresp),
.m_axi_ruser(1'b0),
.m_axi_rvalid(m_axi_rvalid),
.m_axi_wdata(m_axi_wdata),
.m_axi_wid(NLW_inst_m_axi_wid_UNCONNECTED[0]),
.m_axi_wlast(NLW_inst_m_axi_wlast_UNCONNECTED),
.m_axi_wready(m_axi_wready),
.m_axi_wstrb(m_axi_wstrb),
.m_axi_wuser(NLW_inst_m_axi_wuser_UNCONNECTED[0]),
.m_axi_wvalid(m_axi_wvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arcache(s_axi_arcache),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arlock(s_axi_arlock),
.s_axi_arprot(s_axi_arprot),
.s_axi_arqos(s_axi_arqos),
.s_axi_arready(s_axi_arready),
.s_axi_arregion(s_axi_arregion),
.s_axi_arsize(s_axi_arsize),
.s_axi_aruser(1'b0),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awcache(s_axi_awcache),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awlock(s_axi_awlock),
.s_axi_awprot(s_axi_awprot),
.s_axi_awqos(s_axi_awqos),
.s_axi_awready(s_axi_awready),
.s_axi_awregion(s_axi_awregion),
.s_axi_awsize(s_axi_awsize),
.s_axi_awuser(1'b0),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_buser(NLW_inst_s_axi_buser_UNCONNECTED[0]),
.s_axi_bvalid(s_axi_bvalid),
.s_axi_rdata(s_axi_rdata),
.s_axi_rid(s_axi_rid),
.s_axi_rlast(s_axi_rlast),
.s_axi_rready(s_axi_rready),
.s_axi_rresp(s_axi_rresp),
.s_axi_ruser(NLW_inst_s_axi_ruser_UNCONNECTED[0]),
.s_axi_rvalid(s_axi_rvalid),
.s_axi_wdata(s_axi_wdata),
.s_axi_wid(1'b0),
.s_axi_wlast(s_axi_wlast),
.s_axi_wready(s_axi_wready),
.s_axi_wstrb(s_axi_wstrb),
.s_axi_wuser(1'b0),
.s_axi_wvalid(s_axi_wvalid));
endmodule
(* C_AXI_ADDR_WIDTH = "32" *) (* C_AXI_ARUSER_WIDTH = "1" *) (* C_AXI_AWUSER_WIDTH = "1" *)
(* C_AXI_BUSER_WIDTH = "1" *) (* C_AXI_DATA_WIDTH = "32" *) (* C_AXI_ID_WIDTH = "1" *)
(* C_AXI_RUSER_WIDTH = "1" *) (* C_AXI_SUPPORTS_READ = "1" *) (* C_AXI_SUPPORTS_USER_SIGNALS = "0" *)
(* C_AXI_SUPPORTS_WRITE = "1" *) (* C_AXI_WUSER_WIDTH = "1" *) (* C_FAMILY = "artix7" *)
(* C_IGNORE_ID = "0" *) (* C_M_AXI_PROTOCOL = "2" *) (* C_S_AXI_PROTOCOL = "0" *)
(* C_TRANSLATION_MODE = "2" *) (* DowngradeIPIdentifiedWarnings = "yes" *) (* P_AXI3 = "1" *)
(* P_AXI4 = "0" *) (* P_AXILITE = "2" *) (* P_AXILITE_SIZE = "3'b010" *)
(* P_CONVERSION = "2" *) (* P_DECERR = "2'b11" *) (* P_INCR = "2'b01" *)
(* P_PROTECTION = "1" *) (* P_SLVERR = "2'b10" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_axi_protocol_converter
(aclk,
aresetn,
s_axi_awid,
s_axi_awaddr,
s_axi_awlen,
s_axi_awsize,
s_axi_awburst,
s_axi_awlock,
s_axi_awcache,
s_axi_awprot,
s_axi_awregion,
s_axi_awqos,
s_axi_awuser,
s_axi_awvalid,
s_axi_awready,
s_axi_wid,
s_axi_wdata,
s_axi_wstrb,
s_axi_wlast,
s_axi_wuser,
s_axi_wvalid,
s_axi_wready,
s_axi_bid,
s_axi_bresp,
s_axi_buser,
s_axi_bvalid,
s_axi_bready,
s_axi_arid,
s_axi_araddr,
s_axi_arlen,
s_axi_arsize,
s_axi_arburst,
s_axi_arlock,
s_axi_arcache,
s_axi_arprot,
s_axi_arregion,
s_axi_arqos,
s_axi_aruser,
s_axi_arvalid,
s_axi_arready,
s_axi_rid,
s_axi_rdata,
s_axi_rresp,
s_axi_rlast,
s_axi_ruser,
s_axi_rvalid,
s_axi_rready,
m_axi_awid,
m_axi_awaddr,
m_axi_awlen,
m_axi_awsize,
m_axi_awburst,
m_axi_awlock,
m_axi_awcache,
m_axi_awprot,
m_axi_awregion,
m_axi_awqos,
m_axi_awuser,
m_axi_awvalid,
m_axi_awready,
m_axi_wid,
m_axi_wdata,
m_axi_wstrb,
m_axi_wlast,
m_axi_wuser,
m_axi_wvalid,
m_axi_wready,
m_axi_bid,
m_axi_bresp,
m_axi_buser,
m_axi_bvalid,
m_axi_bready,
m_axi_arid,
m_axi_araddr,
m_axi_arlen,
m_axi_arsize,
m_axi_arburst,
m_axi_arlock,
m_axi_arcache,
m_axi_arprot,
m_axi_arregion,
m_axi_arqos,
m_axi_aruser,
m_axi_arvalid,
m_axi_arready,
m_axi_rid,
m_axi_rdata,
m_axi_rresp,
m_axi_rlast,
m_axi_ruser,
m_axi_rvalid,
m_axi_rready);
input aclk;
input aresetn;
input [0:0]s_axi_awid;
input [31:0]s_axi_awaddr;
input [7:0]s_axi_awlen;
input [2:0]s_axi_awsize;
input [1:0]s_axi_awburst;
input [0:0]s_axi_awlock;
input [3:0]s_axi_awcache;
input [2:0]s_axi_awprot;
input [3:0]s_axi_awregion;
input [3:0]s_axi_awqos;
input [0:0]s_axi_awuser;
input s_axi_awvalid;
output s_axi_awready;
input [0:0]s_axi_wid;
input [31:0]s_axi_wdata;
input [3:0]s_axi_wstrb;
input s_axi_wlast;
input [0:0]s_axi_wuser;
input s_axi_wvalid;
output s_axi_wready;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [0:0]s_axi_buser;
output s_axi_bvalid;
input s_axi_bready;
input [0:0]s_axi_arid;
input [31:0]s_axi_araddr;
input [7:0]s_axi_arlen;
input [2:0]s_axi_arsize;
input [1:0]s_axi_arburst;
input [0:0]s_axi_arlock;
input [3:0]s_axi_arcache;
input [2:0]s_axi_arprot;
input [3:0]s_axi_arregion;
input [3:0]s_axi_arqos;
input [0:0]s_axi_aruser;
input s_axi_arvalid;
output s_axi_arready;
output [0:0]s_axi_rid;
output [31:0]s_axi_rdata;
output [1:0]s_axi_rresp;
output s_axi_rlast;
output [0:0]s_axi_ruser;
output s_axi_rvalid;
input s_axi_rready;
output [0:0]m_axi_awid;
output [31:0]m_axi_awaddr;
output [7:0]m_axi_awlen;
output [2:0]m_axi_awsize;
output [1:0]m_axi_awburst;
output [0:0]m_axi_awlock;
output [3:0]m_axi_awcache;
output [2:0]m_axi_awprot;
output [3:0]m_axi_awregion;
output [3:0]m_axi_awqos;
output [0:0]m_axi_awuser;
output m_axi_awvalid;
input m_axi_awready;
output [0:0]m_axi_wid;
output [31:0]m_axi_wdata;
output [3:0]m_axi_wstrb;
output m_axi_wlast;
output [0:0]m_axi_wuser;
output m_axi_wvalid;
input m_axi_wready;
input [0:0]m_axi_bid;
input [1:0]m_axi_bresp;
input [0:0]m_axi_buser;
input m_axi_bvalid;
output m_axi_bready;
output [0:0]m_axi_arid;
output [31:0]m_axi_araddr;
output [7:0]m_axi_arlen;
output [2:0]m_axi_arsize;
output [1:0]m_axi_arburst;
output [0:0]m_axi_arlock;
output [3:0]m_axi_arcache;
output [2:0]m_axi_arprot;
output [3:0]m_axi_arregion;
output [3:0]m_axi_arqos;
output [0:0]m_axi_aruser;
output m_axi_arvalid;
input m_axi_arready;
input [0:0]m_axi_rid;
input [31:0]m_axi_rdata;
input [1:0]m_axi_rresp;
input m_axi_rlast;
input [0:0]m_axi_ruser;
input m_axi_rvalid;
output m_axi_rready;
wire \<const0> ;
wire \<const1> ;
wire aclk;
wire aresetn;
wire [31:0]m_axi_araddr;
wire [2:0]m_axi_arprot;
wire m_axi_arready;
wire m_axi_arvalid;
wire [31:0]m_axi_awaddr;
wire [2:0]m_axi_awprot;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire [31:0]m_axi_rdata;
wire m_axi_rready;
wire [1:0]m_axi_rresp;
wire m_axi_rvalid;
wire m_axi_wready;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [2:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [2:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [31:0]s_axi_rdata;
wire [0:0]s_axi_rid;
wire s_axi_rlast;
wire s_axi_rready;
wire [1:0]s_axi_rresp;
wire s_axi_rvalid;
wire [31:0]s_axi_wdata;
wire [3:0]s_axi_wstrb;
wire s_axi_wvalid;
assign m_axi_arburst[1] = \<const0> ;
assign m_axi_arburst[0] = \<const1> ;
assign m_axi_arcache[3] = \<const0> ;
assign m_axi_arcache[2] = \<const0> ;
assign m_axi_arcache[1] = \<const0> ;
assign m_axi_arcache[0] = \<const0> ;
assign m_axi_arid[0] = \<const0> ;
assign m_axi_arlen[7] = \<const0> ;
assign m_axi_arlen[6] = \<const0> ;
assign m_axi_arlen[5] = \<const0> ;
assign m_axi_arlen[4] = \<const0> ;
assign m_axi_arlen[3] = \<const0> ;
assign m_axi_arlen[2] = \<const0> ;
assign m_axi_arlen[1] = \<const0> ;
assign m_axi_arlen[0] = \<const0> ;
assign m_axi_arlock[0] = \<const0> ;
assign m_axi_arqos[3] = \<const0> ;
assign m_axi_arqos[2] = \<const0> ;
assign m_axi_arqos[1] = \<const0> ;
assign m_axi_arqos[0] = \<const0> ;
assign m_axi_arregion[3] = \<const0> ;
assign m_axi_arregion[2] = \<const0> ;
assign m_axi_arregion[1] = \<const0> ;
assign m_axi_arregion[0] = \<const0> ;
assign m_axi_arsize[2] = \<const0> ;
assign m_axi_arsize[1] = \<const1> ;
assign m_axi_arsize[0] = \<const0> ;
assign m_axi_aruser[0] = \<const0> ;
assign m_axi_awburst[1] = \<const0> ;
assign m_axi_awburst[0] = \<const1> ;
assign m_axi_awcache[3] = \<const0> ;
assign m_axi_awcache[2] = \<const0> ;
assign m_axi_awcache[1] = \<const0> ;
assign m_axi_awcache[0] = \<const0> ;
assign m_axi_awid[0] = \<const0> ;
assign m_axi_awlen[7] = \<const0> ;
assign m_axi_awlen[6] = \<const0> ;
assign m_axi_awlen[5] = \<const0> ;
assign m_axi_awlen[4] = \<const0> ;
assign m_axi_awlen[3] = \<const0> ;
assign m_axi_awlen[2] = \<const0> ;
assign m_axi_awlen[1] = \<const0> ;
assign m_axi_awlen[0] = \<const0> ;
assign m_axi_awlock[0] = \<const0> ;
assign m_axi_awqos[3] = \<const0> ;
assign m_axi_awqos[2] = \<const0> ;
assign m_axi_awqos[1] = \<const0> ;
assign m_axi_awqos[0] = \<const0> ;
assign m_axi_awregion[3] = \<const0> ;
assign m_axi_awregion[2] = \<const0> ;
assign m_axi_awregion[1] = \<const0> ;
assign m_axi_awregion[0] = \<const0> ;
assign m_axi_awsize[2] = \<const0> ;
assign m_axi_awsize[1] = \<const1> ;
assign m_axi_awsize[0] = \<const0> ;
assign m_axi_awuser[0] = \<const0> ;
assign m_axi_wdata[31:0] = s_axi_wdata;
assign m_axi_wid[0] = \<const0> ;
assign m_axi_wlast = \<const1> ;
assign m_axi_wstrb[3:0] = s_axi_wstrb;
assign m_axi_wuser[0] = \<const0> ;
assign m_axi_wvalid = s_axi_wvalid;
assign s_axi_buser[0] = \<const0> ;
assign s_axi_ruser[0] = \<const0> ;
assign s_axi_wready = m_axi_wready;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s \gen_axilite.gen_b2s_conv.axilite_b2s
(.Q({m_axi_awprot,m_axi_awaddr[31:12]}),
.aclk(aclk),
.aresetn(aresetn),
.in({m_axi_rresp,m_axi_rdata}),
.m_axi_araddr(m_axi_araddr[11:0]),
.\m_axi_arprot[2] ({m_axi_arprot,m_axi_araddr[31:12]}),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.m_axi_awaddr(m_axi_awaddr[11:0]),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize[1:0]),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize[1:0]),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[0] ({s_axi_rid,s_axi_rlast,s_axi_rresp,s_axi_rdata}),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s
(s_axi_rvalid,
s_axi_awready,
Q,
s_axi_arready,
\m_axi_arprot[2] ,
s_axi_bvalid,
s_axi_bid,
s_axi_bresp,
\s_axi_rid[0] ,
m_axi_awvalid,
m_axi_bready,
m_axi_arvalid,
m_axi_rready,
m_axi_awaddr,
m_axi_araddr,
m_axi_awready,
m_axi_arready,
s_axi_rready,
aclk,
in,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
m_axi_bresp,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
s_axi_bready,
s_axi_awvalid,
m_axi_bvalid,
m_axi_rvalid,
s_axi_arvalid,
aresetn);
output s_axi_rvalid;
output s_axi_awready;
output [22:0]Q;
output s_axi_arready;
output [22:0]\m_axi_arprot[2] ;
output s_axi_bvalid;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [35:0]\s_axi_rid[0] ;
output m_axi_awvalid;
output m_axi_bready;
output m_axi_arvalid;
output m_axi_rready;
output [11:0]m_axi_awaddr;
output [11:0]m_axi_araddr;
input m_axi_awready;
input m_axi_arready;
input s_axi_rready;
input aclk;
input [33:0]in;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [1:0]m_axi_bresp;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input s_axi_bready;
input s_axi_awvalid;
input m_axi_bvalid;
input m_axi_rvalid;
input s_axi_arvalid;
input aresetn;
wire [22:0]Q;
wire \RD.ar_channel_0_n_1 ;
wire \RD.ar_channel_0_n_2 ;
wire \RD.ar_channel_0_n_22 ;
wire \RD.ar_channel_0_n_23 ;
wire \RD.ar_channel_0_n_24 ;
wire \RD.ar_channel_0_n_25 ;
wire \RD.ar_channel_0_n_3 ;
wire \RD.ar_channel_0_n_4 ;
wire \RD.r_channel_0_n_0 ;
wire \RD.r_channel_0_n_2 ;
wire SI_REG_n_120;
wire SI_REG_n_121;
wire SI_REG_n_122;
wire SI_REG_n_123;
wire SI_REG_n_124;
wire SI_REG_n_125;
wire SI_REG_n_126;
wire SI_REG_n_127;
wire SI_REG_n_130;
wire SI_REG_n_131;
wire SI_REG_n_132;
wire SI_REG_n_133;
wire SI_REG_n_134;
wire SI_REG_n_137;
wire SI_REG_n_138;
wire SI_REG_n_139;
wire SI_REG_n_140;
wire SI_REG_n_141;
wire SI_REG_n_142;
wire SI_REG_n_143;
wire SI_REG_n_144;
wire SI_REG_n_145;
wire SI_REG_n_146;
wire SI_REG_n_147;
wire SI_REG_n_148;
wire SI_REG_n_149;
wire SI_REG_n_150;
wire SI_REG_n_151;
wire SI_REG_n_152;
wire SI_REG_n_153;
wire SI_REG_n_154;
wire SI_REG_n_155;
wire SI_REG_n_156;
wire SI_REG_n_157;
wire SI_REG_n_158;
wire SI_REG_n_159;
wire SI_REG_n_160;
wire SI_REG_n_21;
wire SI_REG_n_22;
wire SI_REG_n_23;
wire SI_REG_n_24;
wire SI_REG_n_30;
wire SI_REG_n_68;
wire SI_REG_n_69;
wire SI_REG_n_70;
wire SI_REG_n_71;
wire SI_REG_n_73;
wire SI_REG_n_74;
wire SI_REG_n_75;
wire SI_REG_n_76;
wire SI_REG_n_82;
wire \WR.aw_channel_0_n_29 ;
wire \WR.aw_channel_0_n_30 ;
wire \WR.aw_channel_0_n_31 ;
wire \WR.aw_channel_0_n_32 ;
wire \WR.aw_channel_0_n_9 ;
wire \WR.b_channel_0_n_1 ;
wire \WR.b_channel_0_n_2 ;
wire aclk;
wire areset_d1;
wire areset_d1_i_1_n_0;
wire aresetn;
wire [1:0]\aw_cmd_fsm_0/state ;
wire [11:0]axaddr_incr;
wire b_awid;
wire [7:0]b_awlen;
wire b_push;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ;
wire [2:1]\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ;
wire \gen_simple_ar.ar_pipe/p_1_in ;
wire \gen_simple_aw.aw_pipe/p_1_in ;
wire [33:0]in;
wire [11:0]m_axi_araddr;
wire [22:0]\m_axi_arprot[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire m_axi_rready;
wire m_axi_rvalid;
wire r_rlast;
wire s_arid;
wire s_arid_r;
wire s_awid;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [35:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [11:0]si_rs_araddr;
wire [1:1]si_rs_arburst;
wire [3:0]si_rs_arlen;
wire [1:0]si_rs_arsize;
wire si_rs_arvalid;
wire [11:0]si_rs_awaddr;
wire [1:1]si_rs_awburst;
wire [3:0]si_rs_awlen;
wire [1:0]si_rs_awsize;
wire si_rs_awvalid;
wire si_rs_bid;
wire si_rs_bready;
wire [1:0]si_rs_bresp;
wire si_rs_bvalid;
wire [31:0]si_rs_rdata;
wire si_rs_rid;
wire si_rs_rlast;
wire si_rs_rready;
wire [1:0]si_rs_rresp;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel \RD.ar_channel_0
(.D({SI_REG_n_153,SI_REG_n_154,SI_REG_n_155,SI_REG_n_156,SI_REG_n_157,SI_REG_n_158,SI_REG_n_159}),
.E(\gen_simple_ar.ar_pipe/p_1_in ),
.O({SI_REG_n_124,SI_REG_n_125,SI_REG_n_126,SI_REG_n_127}),
.Q({s_arid,SI_REG_n_73,SI_REG_n_74,SI_REG_n_75,SI_REG_n_76,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,si_rs_araddr}),
.S({\RD.ar_channel_0_n_22 ,\RD.ar_channel_0_n_23 ,\RD.ar_channel_0_n_24 ,\RD.ar_channel_0_n_25 }),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axlen_cnt_reg[0] (\RD.ar_channel_0_n_4 ),
.\cnt_read_reg[2] (\RD.r_channel_0_n_0 ),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\RD.ar_channel_0_n_3 ),
.\m_payload_i_reg[35] (SI_REG_n_137),
.\m_payload_i_reg[35]_0 (SI_REG_n_139),
.\m_payload_i_reg[3] (SI_REG_n_160),
.\m_payload_i_reg[3]_0 ({SI_REG_n_68,SI_REG_n_69,SI_REG_n_70,SI_REG_n_71}),
.\m_payload_i_reg[46] (\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
.\m_payload_i_reg[47] (SI_REG_n_140),
.\m_payload_i_reg[47]_0 (SI_REG_n_138),
.\m_payload_i_reg[48] (SI_REG_n_141),
.\m_payload_i_reg[6] (SI_REG_n_152),
.\m_payload_i_reg[7] ({SI_REG_n_120,SI_REG_n_121,SI_REG_n_122,SI_REG_n_123}),
.r_push_r_reg(\RD.ar_channel_0_n_2 ),
.r_rlast(r_rlast),
.s_arid_r(s_arid_r),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_boundary_axaddr_r_reg[11] (\RD.ar_channel_0_n_1 ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel \RD.r_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out({si_rs_rresp,si_rs_rdata}),
.r_rlast(r_rlast),
.s_arid_r(s_arid_r),
.s_ready_i_reg(\RD.r_channel_0_n_2 ),
.s_ready_i_reg_0(SI_REG_n_142),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[35] ({si_rs_rid,si_rs_rlast}),
.\state_reg[1]_rep (\RD.r_channel_0_n_0 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_2 ));
DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice SI_REG
(.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.O({SI_REG_n_124,SI_REG_n_125,SI_REG_n_126,SI_REG_n_127}),
.Q({s_awid,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,SI_REG_n_24,si_rs_awlen,si_rs_awburst,SI_REG_n_30,si_rs_awsize,Q,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_29 ,\WR.aw_channel_0_n_30 ,\WR.aw_channel_0_n_31 ,\WR.aw_channel_0_n_32 }),
.aclk(aclk),
.aresetn(aresetn),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[3] ({SI_REG_n_68,SI_REG_n_69,SI_REG_n_70,SI_REG_n_71}),
.\axaddr_incr_reg[7] ({SI_REG_n_120,SI_REG_n_121,SI_REG_n_122,SI_REG_n_123}),
.\axaddr_offset_r_reg[0] (SI_REG_n_151),
.\axaddr_offset_r_reg[0]_0 (SI_REG_n_160),
.\axaddr_offset_r_reg[1] (SI_REG_n_130),
.\axaddr_offset_r_reg[1]_0 (SI_REG_n_137),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset ),
.\axaddr_offset_r_reg[2]_0 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ),
.\axaddr_offset_r_reg[2]_1 (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r ),
.\axaddr_offset_r_reg[3] (SI_REG_n_143),
.\axaddr_offset_r_reg[3]_0 (SI_REG_n_152),
.\axlen_cnt_reg[3] (SI_REG_n_132),
.\axlen_cnt_reg[3]_0 (SI_REG_n_140),
.b_push(b_push),
.\cnt_read_reg[1] (SI_REG_n_142),
.\cnt_read_reg[4] ({si_rs_rresp,si_rs_rdata}),
.\cnt_read_reg[4]_rep__2 (\RD.r_channel_0_n_2 ),
.\m_payload_i_reg[3] ({\RD.ar_channel_0_n_22 ,\RD.ar_channel_0_n_23 ,\RD.ar_channel_0_n_24 ,\RD.ar_channel_0_n_25 }),
.m_valid_i_reg(\gen_simple_ar.ar_pipe/p_1_in ),
.next_pending_r_reg(SI_REG_n_133),
.next_pending_r_reg_0(SI_REG_n_134),
.next_pending_r_reg_1(SI_REG_n_138),
.next_pending_r_reg_2(SI_REG_n_141),
.out(si_rs_bid),
.r_push_r_reg({si_rs_rid,si_rs_rlast}),
.\s_arid_r_reg[0] ({s_arid,SI_REG_n_73,SI_REG_n_74,SI_REG_n_75,SI_REG_n_76,si_rs_arlen,si_rs_arburst,SI_REG_n_82,si_rs_arsize,\m_axi_arprot[2] ,si_rs_araddr}),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\s_bresp_acc_reg[1] (si_rs_bresp),
.si_rs_arvalid(si_rs_arvalid),
.si_rs_awvalid(si_rs_awvalid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.si_rs_rready(si_rs_rready),
.\state_reg[0]_rep (\RD.ar_channel_0_n_4 ),
.\state_reg[1] (\WR.aw_channel_0_n_9 ),
.\state_reg[1]_0 (\aw_cmd_fsm_0/state ),
.\state_reg[1]_rep (\RD.ar_channel_0_n_1 ),
.\state_reg[1]_rep_0 (\RD.ar_channel_0_n_3 ),
.\wrap_boundary_axaddr_r_reg[6] ({SI_REG_n_144,SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149,SI_REG_n_150}),
.\wrap_boundary_axaddr_r_reg[6]_0 ({SI_REG_n_153,SI_REG_n_154,SI_REG_n_155,SI_REG_n_156,SI_REG_n_157,SI_REG_n_158,SI_REG_n_159}),
.\wrap_second_len_r_reg[3] (SI_REG_n_131),
.\wrap_second_len_r_reg[3]_0 (SI_REG_n_139));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel \WR.aw_channel_0
(.D(\cmd_translator_0/wrap_cmd_0/axaddr_offset_0 ),
.E(\gen_simple_aw.aw_pipe/p_1_in ),
.Q({s_awid,SI_REG_n_21,SI_REG_n_22,SI_REG_n_23,SI_REG_n_24,si_rs_awlen,si_rs_awburst,SI_REG_n_30,si_rs_awsize,si_rs_awaddr}),
.S({\WR.aw_channel_0_n_29 ,\WR.aw_channel_0_n_30 ,\WR.aw_channel_0_n_31 ,\WR.aw_channel_0_n_32 }),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[2] (\cmd_translator_0/wrap_cmd_0/axaddr_offset_r_1 ),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_awaddr(m_axi_awaddr),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[35] (SI_REG_n_130),
.\m_payload_i_reg[35]_0 (SI_REG_n_131),
.\m_payload_i_reg[3] (SI_REG_n_151),
.\m_payload_i_reg[46] (SI_REG_n_134),
.\m_payload_i_reg[47] (SI_REG_n_132),
.\m_payload_i_reg[48] (SI_REG_n_133),
.\m_payload_i_reg[6] (SI_REG_n_143),
.\m_payload_i_reg[6]_0 ({SI_REG_n_144,SI_REG_n_145,SI_REG_n_146,SI_REG_n_147,SI_REG_n_148,SI_REG_n_149,SI_REG_n_150}),
.si_rs_awvalid(si_rs_awvalid),
.\state_reg[0] (\aw_cmd_fsm_0/state ),
.\wrap_boundary_axaddr_r_reg[11] (\WR.aw_channel_0_n_9 ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel \WR.b_channel_0
(.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\WR.b_channel_0_n_1 ),
.\cnt_read_reg[1]_rep (\WR.b_channel_0_n_2 ),
.in({b_awid,b_awlen}),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.out(si_rs_bid),
.si_rs_bready(si_rs_bready),
.si_rs_bvalid(si_rs_bvalid),
.\skid_buffer_reg[1] (si_rs_bresp));
LUT1 #(
.INIT(2'h1))
areset_d1_i_1
(.I0(aresetn),
.O(areset_d1_i_1_n_0));
FDRE #(
.INIT(1'b0))
areset_d1_reg
(.C(aclk),
.CE(1'b1),
.D(areset_d1_i_1_n_0),
.Q(areset_d1),
.R(1'b0));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_ar_channel
(s_arid_r,
\wrap_boundary_axaddr_r_reg[11] ,
r_push_r_reg,
\m_payload_i_reg[0] ,
\axlen_cnt_reg[0] ,
\axaddr_offset_r_reg[2] ,
m_axi_arvalid,
r_rlast,
E,
m_axi_araddr,
S,
aclk,
Q,
\m_payload_i_reg[47] ,
si_rs_arvalid,
m_axi_arready,
\cnt_read_reg[2] ,
\m_payload_i_reg[46] ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[6] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3]_0 ,
D);
output s_arid_r;
output \wrap_boundary_axaddr_r_reg[11] ;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \axlen_cnt_reg[0] ;
output [1:0]\axaddr_offset_r_reg[2] ;
output m_axi_arvalid;
output r_rlast;
output [0:0]E;
output [11:0]m_axi_araddr;
output [3:0]S;
input aclk;
input [24:0]Q;
input \m_payload_i_reg[47] ;
input si_rs_arvalid;
input m_axi_arready;
input \cnt_read_reg[2] ;
input [1:0]\m_payload_i_reg[46] ;
input \m_payload_i_reg[35] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[6] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3]_0 ;
input [6:0]D;
wire [6:0]D;
wire [0:0]E;
wire [3:0]O;
wire [24:0]Q;
wire [3:0]S;
wire aclk;
wire ar_cmd_fsm_0_n_0;
wire ar_cmd_fsm_0_n_11;
wire ar_cmd_fsm_0_n_12;
wire ar_cmd_fsm_0_n_13;
wire ar_cmd_fsm_0_n_14;
wire ar_cmd_fsm_0_n_21;
wire ar_cmd_fsm_0_n_22;
wire ar_cmd_fsm_0_n_23;
wire ar_cmd_fsm_0_n_25;
wire ar_cmd_fsm_0_n_6;
wire ar_cmd_fsm_0_n_7;
wire ar_cmd_fsm_0_n_8;
wire ar_cmd_fsm_0_n_9;
wire areset_d1;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire \axlen_cnt_reg[0] ;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_10;
wire cmd_translator_0_n_11;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_3;
wire cmd_translator_0_n_4;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_7;
wire cmd_translator_0_n_8;
wire \cnt_read_reg[2] ;
wire \incr_cmd_0/sel_first ;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire [1:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire r_push_r_reg;
wire r_rlast;
wire s_arid_r;
wire sel_first_i;
wire si_rs_arvalid;
wire [1:0]state;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [3:0]\wrap_cmd_0/axaddr_offset ;
wire [3:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm ar_cmd_fsm_0
(.D({ar_cmd_fsm_0_n_6,ar_cmd_fsm_0_n_7,ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(state),
.aclk(aclk),
.areset_d1(areset_d1),
.\axaddr_incr_reg[0] (ar_cmd_fsm_0_n_25),
.axaddr_offset({\wrap_cmd_0/axaddr_offset [3],\wrap_cmd_0/axaddr_offset [0]}),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_wrap_reg[11] (ar_cmd_fsm_0_n_21),
.\axlen_cnt_reg[0] (\axlen_cnt_reg[0] ),
.\axlen_cnt_reg[3] (cmd_translator_0_n_7),
.\axlen_cnt_reg[4] (cmd_translator_0_n_11),
.\axlen_cnt_reg[5] (ar_cmd_fsm_0_n_0),
.\axlen_cnt_reg[6] ({cmd_translator_0_n_3,cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6}),
.\axlen_cnt_reg[7] (cmd_translator_0_n_8),
.\cnt_read_reg[2] (\cnt_read_reg[2] ),
.m_axi_arready(m_axi_arready),
.m_axi_arvalid(m_axi_arvalid),
.\m_payload_i_reg[0] (\m_payload_i_reg[0] ),
.\m_payload_i_reg[0]_0 (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (\m_payload_i_reg[46] [1]),
.\m_payload_i_reg[50] ({Q[22:21],Q[19],Q[17:16]}),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.r_push_r_reg(r_push_r_reg),
.s_axburst_eq1_reg(cmd_translator_0_n_10),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(ar_cmd_fsm_0_n_22),
.sel_first_reg_0(ar_cmd_fsm_0_n_23),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(cmd_translator_0_n_0),
.si_rs_arvalid(si_rs_arvalid),
.\wrap_cnt_r_reg[0] (ar_cmd_fsm_0_n_14),
.\wrap_cnt_r_reg[3] ({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13}),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1 cmd_translator_0
(.D({ar_cmd_fsm_0_n_6,ar_cmd_fsm_0_n_7,ar_cmd_fsm_0_n_8,ar_cmd_fsm_0_n_9}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.O(O),
.Q({cmd_translator_0_n_3,cmd_translator_0_n_4,cmd_translator_0_n_5,cmd_translator_0_n_6}),
.S(S),
.aclk(aclk),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\axaddr_offset_r_reg[2] ,\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_offset_r_reg[3]_0 (ar_cmd_fsm_0_n_14),
.\axaddr_offset_r_reg[3]_1 ({\wrap_cmd_0/axaddr_offset [3],\m_payload_i_reg[46] ,\wrap_cmd_0/axaddr_offset [0]}),
.\axlen_cnt_reg[5] (cmd_translator_0_n_11),
.\axlen_cnt_reg[7] (cmd_translator_0_n_7),
.m_axi_araddr(m_axi_araddr),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3]_0 ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[51] ({Q[23],Q[20:0]}),
.\m_payload_i_reg[6] (D),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(ar_cmd_fsm_0_n_21),
.next_pending_r_reg(cmd_translator_0_n_8),
.r_rlast(r_rlast),
.sel_first(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_0),
.sel_first_reg_1(cmd_translator_0_n_2),
.sel_first_reg_2(ar_cmd_fsm_0_n_23),
.sel_first_reg_3(ar_cmd_fsm_0_n_22),
.sel_first_reg_4(ar_cmd_fsm_0_n_25),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[0] (ar_cmd_fsm_0_n_0),
.\state_reg[0]_rep (cmd_translator_0_n_10),
.\state_reg[1] (state),
.\state_reg[1]_rep (r_push_r_reg),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_1 ({ar_cmd_fsm_0_n_11,ar_cmd_fsm_0_n_12,ar_cmd_fsm_0_n_13}));
FDRE \s_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(s_arid_r),
.R(1'b0));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_aw_channel
(in,
\wrap_boundary_axaddr_r_reg[11] ,
\state_reg[0] ,
\axaddr_offset_r_reg[2] ,
E,
b_push,
m_axi_awvalid,
m_axi_awaddr,
S,
aclk,
Q,
\m_payload_i_reg[47] ,
\cnt_read_reg[1]_rep ,
\cnt_read_reg[0]_rep ,
m_axi_awready,
si_rs_awvalid,
D,
\m_payload_i_reg[35] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[48] ,
areset_d1,
\m_payload_i_reg[46] ,
\m_payload_i_reg[6] ,
axaddr_incr,
\m_payload_i_reg[6]_0 );
output [8:0]in;
output \wrap_boundary_axaddr_r_reg[11] ;
output [1:0]\state_reg[0] ;
output [1:0]\axaddr_offset_r_reg[2] ;
output [0:0]E;
output b_push;
output m_axi_awvalid;
output [11:0]m_axi_awaddr;
output [3:0]S;
input aclk;
input [24:0]Q;
input \m_payload_i_reg[47] ;
input \cnt_read_reg[1]_rep ;
input \cnt_read_reg[0]_rep ;
input m_axi_awready;
input si_rs_awvalid;
input [1:0]D;
input \m_payload_i_reg[35] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input \m_payload_i_reg[48] ;
input areset_d1;
input \m_payload_i_reg[46] ;
input \m_payload_i_reg[6] ;
input [11:0]axaddr_incr;
input [6:0]\m_payload_i_reg[6]_0 ;
wire [1:0]D;
wire [0:0]E;
wire [24:0]Q;
wire [3:0]S;
wire aclk;
wire areset_d1;
wire aw_cmd_fsm_0_n_13;
wire aw_cmd_fsm_0_n_14;
wire aw_cmd_fsm_0_n_18;
wire aw_cmd_fsm_0_n_20;
wire aw_cmd_fsm_0_n_21;
wire aw_cmd_fsm_0_n_22;
wire aw_cmd_fsm_0_n_5;
wire [11:0]axaddr_incr;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire b_push;
wire cmd_translator_0_n_0;
wire cmd_translator_0_n_1;
wire cmd_translator_0_n_2;
wire cmd_translator_0_n_5;
wire cmd_translator_0_n_6;
wire cmd_translator_0_n_7;
wire cmd_translator_0_n_8;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep ;
wire [8:0]in;
wire \incr_cmd_0/sel_first ;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire m_axi_awready;
wire m_axi_awvalid;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire \m_payload_i_reg[46] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire [6:0]\m_payload_i_reg[6]_0 ;
wire next;
wire sel_first;
wire sel_first_i;
wire si_rs_awvalid;
wire [1:0]\state_reg[0] ;
wire \wrap_boundary_axaddr_r_reg[11] ;
wire [3:0]\wrap_cmd_0/axaddr_offset ;
wire [3:0]\wrap_cmd_0/axaddr_offset_r ;
wire [3:0]\wrap_cmd_0/wrap_second_len ;
wire [3:0]\wrap_cmd_0/wrap_second_len_r ;
wire [3:0]wrap_cnt;
wire wrap_next_pending;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm aw_cmd_fsm_0
(.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(\state_reg[0] ),
.aclk(aclk),
.areset_d1(areset_d1),
.axaddr_offset({\wrap_cmd_0/axaddr_offset [3],\wrap_cmd_0/axaddr_offset [0]}),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_wrap_reg[0] (aw_cmd_fsm_0_n_20),
.\axlen_cnt_reg[0] (aw_cmd_fsm_0_n_13),
.\axlen_cnt_reg[0]_0 (cmd_translator_0_n_5),
.\axlen_cnt_reg[2] (cmd_translator_0_n_8),
.\axlen_cnt_reg[3] (cmd_translator_0_n_6),
.b_push(b_push),
.\cnt_read_reg[0]_rep (\cnt_read_reg[0]_rep ),
.\cnt_read_reg[1]_rep (\cnt_read_reg[1]_rep ),
.incr_next_pending(incr_next_pending),
.m_axi_awready(m_axi_awready),
.m_axi_awvalid(m_axi_awvalid),
.\m_payload_i_reg[0] (E),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[35]_0 (\m_payload_i_reg[35]_0 ),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[46] (D[1]),
.\m_payload_i_reg[46]_0 (\m_payload_i_reg[46] ),
.\m_payload_i_reg[47] ({Q[19],Q[16:15]}),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.s_axburst_eq0_reg(aw_cmd_fsm_0_n_14),
.s_axburst_eq1_reg(aw_cmd_fsm_0_n_18),
.s_axburst_eq1_reg_0(cmd_translator_0_n_7),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg(aw_cmd_fsm_0_n_21),
.sel_first_reg_0(aw_cmd_fsm_0_n_22),
.sel_first_reg_1(cmd_translator_0_n_2),
.si_rs_awvalid(si_rs_awvalid),
.\wrap_cnt_r_reg[0] (aw_cmd_fsm_0_n_5),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len_r ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator cmd_translator_0
(.D({wrap_cnt[3:2],wrap_cnt[0]}),
.E(\wrap_boundary_axaddr_r_reg[11] ),
.Q(Q[23:0]),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[3] ({\wrap_cmd_0/axaddr_offset_r [3],\axaddr_offset_r_reg[2] ,\wrap_cmd_0/axaddr_offset_r [0]}),
.\axaddr_offset_r_reg[3]_0 (aw_cmd_fsm_0_n_5),
.\axaddr_offset_r_reg[3]_1 ({\wrap_cmd_0/axaddr_offset [3],D,\wrap_cmd_0/axaddr_offset [0]}),
.\axlen_cnt_reg[3] (cmd_translator_0_n_5),
.\axlen_cnt_reg[3]_0 (cmd_translator_0_n_6),
.incr_next_pending(incr_next_pending),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[39] (aw_cmd_fsm_0_n_14),
.\m_payload_i_reg[39]_0 (aw_cmd_fsm_0_n_18),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6]_0 ),
.next(next),
.next_pending_r_reg(cmd_translator_0_n_0),
.next_pending_r_reg_0(cmd_translator_0_n_1),
.next_pending_r_reg_1(cmd_translator_0_n_8),
.sel_first(sel_first),
.sel_first_0(\incr_cmd_0/sel_first ),
.sel_first_i(sel_first_i),
.sel_first_reg_0(cmd_translator_0_n_2),
.sel_first_reg_1(aw_cmd_fsm_0_n_22),
.sel_first_reg_2(aw_cmd_fsm_0_n_21),
.\state_reg[0] (aw_cmd_fsm_0_n_20),
.\state_reg[1] (cmd_translator_0_n_7),
.\state_reg[1]_0 (aw_cmd_fsm_0_n_13),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3] (\wrap_cmd_0/wrap_second_len_r ),
.\wrap_second_len_r_reg[3]_0 (\wrap_cmd_0/wrap_second_len ));
FDRE \s_awid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[24]),
.Q(in[8]),
.R(1'b0));
FDRE \s_awlen_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(Q[16]),
.Q(in[0]),
.R(1'b0));
FDRE \s_awlen_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(Q[17]),
.Q(in[1]),
.R(1'b0));
FDRE \s_awlen_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(Q[18]),
.Q(in[2]),
.R(1'b0));
FDRE \s_awlen_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(Q[19]),
.Q(in[3]),
.R(1'b0));
FDRE \s_awlen_r_reg[4]
(.C(aclk),
.CE(1'b1),
.D(Q[20]),
.Q(in[4]),
.R(1'b0));
FDRE \s_awlen_r_reg[5]
(.C(aclk),
.CE(1'b1),
.D(Q[21]),
.Q(in[5]),
.R(1'b0));
FDRE \s_awlen_r_reg[6]
(.C(aclk),
.CE(1'b1),
.D(Q[22]),
.Q(in[6]),
.R(1'b0));
FDRE \s_awlen_r_reg[7]
(.C(aclk),
.CE(1'b1),
.D(Q[23]),
.Q(in[7]),
.R(1'b0));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_b_channel
(si_rs_bvalid,
\cnt_read_reg[0]_rep ,
\cnt_read_reg[1]_rep ,
m_axi_bready,
out,
\skid_buffer_reg[1] ,
areset_d1,
aclk,
b_push,
si_rs_bready,
m_axi_bresp,
m_axi_bvalid,
in);
output si_rs_bvalid;
output \cnt_read_reg[0]_rep ;
output \cnt_read_reg[1]_rep ;
output m_axi_bready;
output [0:0]out;
output [1:0]\skid_buffer_reg[1] ;
input areset_d1;
input aclk;
input b_push;
input si_rs_bready;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
input [8:0]in;
wire aclk;
wire areset_d1;
wire b_push;
wire bid_fifo_0_n_2;
wire bid_fifo_0_n_5;
wire \bresp_cnt[7]_i_3_n_0 ;
wire [7:0]bresp_cnt_reg__0;
wire bresp_push;
wire [1:0]cnt_read;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep ;
wire [8:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire [0:0]out;
wire [7:0]p_0_in;
wire s_bresp_acc;
wire s_bresp_acc0;
wire \s_bresp_acc[0]_i_1_n_0 ;
wire \s_bresp_acc[1]_i_1_n_0 ;
wire \s_bresp_acc_reg_n_0_[0] ;
wire \s_bresp_acc_reg_n_0_[1] ;
wire shandshake;
wire shandshake_r;
wire si_rs_bready;
wire si_rs_bvalid;
wire [1:0]\skid_buffer_reg[1] ;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo bid_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.SR(s_bresp_acc0),
.aclk(aclk),
.areset_d1(areset_d1),
.b_push(b_push),
.\bresp_cnt_reg[7] (bresp_cnt_reg__0),
.bresp_push(bresp_push),
.bvalid_i_reg(bid_fifo_0_n_2),
.bvalid_i_reg_0(si_rs_bvalid),
.\cnt_read_reg[0]_rep_0 (\cnt_read_reg[0]_rep ),
.\cnt_read_reg[1]_rep_0 (\cnt_read_reg[1]_rep ),
.in(in),
.mhandshake_r(mhandshake_r),
.out(out),
.shandshake_r(shandshake_r),
.si_rs_bready(si_rs_bready));
LUT1 #(
.INIT(2'h1))
\bresp_cnt[0]_i_1
(.I0(bresp_cnt_reg__0[0]),
.O(p_0_in[0]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[1]_i_1
(.I0(bresp_cnt_reg__0[1]),
.I1(bresp_cnt_reg__0[0]),
.O(p_0_in[1]));
(* SOFT_HLUTNM = "soft_lutpair107" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[2]_i_1
(.I0(bresp_cnt_reg__0[2]),
.I1(bresp_cnt_reg__0[0]),
.I2(bresp_cnt_reg__0[1]),
.O(p_0_in[2]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT4 #(
.INIT(16'h6AAA))
\bresp_cnt[3]_i_1
(.I0(bresp_cnt_reg__0[3]),
.I1(bresp_cnt_reg__0[1]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[2]),
.O(p_0_in[3]));
(* SOFT_HLUTNM = "soft_lutpair105" *)
LUT5 #(
.INIT(32'h6AAAAAAA))
\bresp_cnt[4]_i_1
(.I0(bresp_cnt_reg__0[4]),
.I1(bresp_cnt_reg__0[2]),
.I2(bresp_cnt_reg__0[0]),
.I3(bresp_cnt_reg__0[1]),
.I4(bresp_cnt_reg__0[3]),
.O(p_0_in[4]));
LUT6 #(
.INIT(64'h6AAAAAAAAAAAAAAA))
\bresp_cnt[5]_i_1
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(p_0_in[5]));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT2 #(
.INIT(4'h6))
\bresp_cnt[6]_i_1
(.I0(bresp_cnt_reg__0[6]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.O(p_0_in[6]));
(* SOFT_HLUTNM = "soft_lutpair106" *)
LUT3 #(
.INIT(8'h6A))
\bresp_cnt[7]_i_2
(.I0(bresp_cnt_reg__0[7]),
.I1(\bresp_cnt[7]_i_3_n_0 ),
.I2(bresp_cnt_reg__0[6]),
.O(p_0_in[7]));
LUT6 #(
.INIT(64'h8000000000000000))
\bresp_cnt[7]_i_3
(.I0(bresp_cnt_reg__0[5]),
.I1(bresp_cnt_reg__0[3]),
.I2(bresp_cnt_reg__0[1]),
.I3(bresp_cnt_reg__0[0]),
.I4(bresp_cnt_reg__0[2]),
.I5(bresp_cnt_reg__0[4]),
.O(\bresp_cnt[7]_i_3_n_0 ));
FDRE \bresp_cnt_reg[0]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[0]),
.Q(bresp_cnt_reg__0[0]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[1]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[1]),
.Q(bresp_cnt_reg__0[1]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[2]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[2]),
.Q(bresp_cnt_reg__0[2]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[3]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[3]),
.Q(bresp_cnt_reg__0[3]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[4]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[4]),
.Q(bresp_cnt_reg__0[4]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[5]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[5]),
.Q(bresp_cnt_reg__0[5]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[6]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[6]),
.Q(bresp_cnt_reg__0[6]),
.R(s_bresp_acc0));
FDRE \bresp_cnt_reg[7]
(.C(aclk),
.CE(mhandshake_r),
.D(p_0_in[7]),
.Q(bresp_cnt_reg__0[7]),
.R(s_bresp_acc0));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0 bresp_fifo_0
(.D(bid_fifo_0_n_5),
.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.bresp_push(bresp_push),
.in({\s_bresp_acc_reg_n_0_[1] ,\s_bresp_acc_reg_n_0_[0] }),
.m_axi_bready(m_axi_bready),
.m_axi_bresp(m_axi_bresp),
.m_axi_bvalid(m_axi_bvalid),
.mhandshake(mhandshake),
.mhandshake_r(mhandshake_r),
.s_bresp_acc(s_bresp_acc),
.shandshake_r(shandshake_r),
.\skid_buffer_reg[1] (\skid_buffer_reg[1] ));
FDRE #(
.INIT(1'b0))
bvalid_i_reg
(.C(aclk),
.CE(1'b1),
.D(bid_fifo_0_n_2),
.Q(si_rs_bvalid),
.R(1'b0));
FDRE #(
.INIT(1'b0))
mhandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(mhandshake),
.Q(mhandshake_r),
.R(areset_d1));
LUT5 #(
.INIT(32'h000000E2))
\s_bresp_acc[0]_i_1
(.I0(\s_bresp_acc_reg_n_0_[0] ),
.I1(s_bresp_acc),
.I2(m_axi_bresp[0]),
.I3(bresp_push),
.I4(areset_d1),
.O(\s_bresp_acc[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'h000000E2))
\s_bresp_acc[1]_i_1
(.I0(\s_bresp_acc_reg_n_0_[1] ),
.I1(s_bresp_acc),
.I2(m_axi_bresp[1]),
.I3(bresp_push),
.I4(areset_d1),
.O(\s_bresp_acc[1]_i_1_n_0 ));
FDRE \s_bresp_acc_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[0]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[0] ),
.R(1'b0));
FDRE \s_bresp_acc_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\s_bresp_acc[1]_i_1_n_0 ),
.Q(\s_bresp_acc_reg_n_0_[1] ),
.R(1'b0));
LUT2 #(
.INIT(4'h8))
shandshake_r_i_1
(.I0(si_rs_bvalid),
.I1(si_rs_bready),
.O(shandshake));
FDRE #(
.INIT(1'b0))
shandshake_r_reg
(.C(aclk),
.CE(1'b1),
.D(shandshake),
.Q(shandshake_r),
.R(areset_d1));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator
(next_pending_r_reg,
next_pending_r_reg_0,
sel_first_reg_0,
sel_first_0,
sel_first,
\axlen_cnt_reg[3] ,
\axlen_cnt_reg[3]_0 ,
\state_reg[1] ,
next_pending_r_reg_1,
m_axi_awaddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
incr_next_pending,
aclk,
wrap_next_pending,
sel_first_i,
\m_payload_i_reg[39] ,
\m_payload_i_reg[39]_0 ,
sel_first_reg_1,
sel_first_reg_2,
E,
Q,
\m_payload_i_reg[47] ,
next,
axaddr_incr,
D,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\state_reg[0] ,
\state_reg[1]_0 ,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[6] );
output next_pending_r_reg;
output next_pending_r_reg_0;
output sel_first_reg_0;
output sel_first_0;
output sel_first;
output [0:0]\axlen_cnt_reg[3] ;
output \axlen_cnt_reg[3]_0 ;
output \state_reg[1] ;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input wrap_next_pending;
input sel_first_i;
input \m_payload_i_reg[39] ;
input \m_payload_i_reg[39]_0 ;
input sel_first_reg_1;
input sel_first_reg_2;
input [0:0]E;
input [23:0]Q;
input \m_payload_i_reg[47] ;
input next;
input [11:0]axaddr_incr;
input [2:0]D;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1]_0 ;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [6:0]\m_payload_i_reg[6] ;
wire [2:0]D;
wire [0:0]E;
wire [23:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire [0:0]\axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_4;
wire incr_cmd_0_n_5;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[39] ;
wire \m_payload_i_reg[39]_0 ;
wire \m_payload_i_reg[47] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [0:0]\state_reg[0] ;
wire \state_reg[1] ;
wire [0:0]\state_reg[1]_0 ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd incr_cmd_0
(.E(E),
.Q(\axlen_cnt_reg[3] ),
.S(S),
.aclk(aclk),
.axaddr_incr(axaddr_incr),
.\axaddr_incr_reg[0]_0 (sel_first_0),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14,incr_cmd_0_n_15}),
.\axlen_cnt_reg[3]_0 (\axlen_cnt_reg[3]_0 ),
.incr_next_pending(incr_next_pending),
.\m_axi_awaddr[10] (incr_cmd_0_n_16),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[51] ({Q[23:20],Q[18:17],Q[14:12],Q[3:0]}),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_1),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1]_0 ));
LUT3 #(
.INIT(8'hB8))
\memory_reg[3][0]_srl4_i_2
(.I0(s_axburst_eq1),
.I1(Q[15]),
.I2(s_axburst_eq0),
.O(\state_reg[1] ));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39] ),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i_reg[39]_0 ),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd wrap_cmd_0
(.D(D),
.E(E),
.Q({Q[19:15],Q[13:0]}),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_4,incr_cmd_0_n_5,incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14,incr_cmd_0_n_15}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.m_axi_awaddr(m_axi_awaddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.next(next),
.next_pending_r_reg_0(next_pending_r_reg_0),
.next_pending_r_reg_1(next_pending_r_reg_1),
.sel_first_reg_0(sel_first),
.sel_first_reg_1(sel_first_reg_2),
.sel_first_reg_2(incr_cmd_0_n_16),
.\state_reg[0] (\state_reg[0] ),
.wrap_next_pending(wrap_next_pending),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_cmd_translator" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_cmd_translator_1
(sel_first_reg_0,
sel_first,
sel_first_reg_1,
Q,
\axlen_cnt_reg[7] ,
next_pending_r_reg,
r_rlast,
\state_reg[0]_rep ,
\axlen_cnt_reg[5] ,
m_axi_araddr,
\wrap_second_len_r_reg[3] ,
\axaddr_offset_r_reg[3] ,
S,
aclk,
sel_first_i,
sel_first_reg_2,
sel_first_reg_3,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\state_reg[1] ,
si_rs_arvalid,
\state_reg[1]_rep ,
\m_payload_i_reg[47]_0 ,
\m_payload_i_reg[48] ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
\axaddr_offset_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
m_valid_i_reg,
D,
\axaddr_offset_r_reg[3]_1 ,
\wrap_second_len_r_reg[3]_0 ,
\wrap_second_len_r_reg[3]_1 ,
\m_payload_i_reg[6] ,
sel_first_reg_4,
m_axi_arready);
output sel_first_reg_0;
output sel_first;
output sel_first_reg_1;
output [3:0]Q;
output \axlen_cnt_reg[7] ;
output next_pending_r_reg;
output r_rlast;
output \state_reg[0]_rep ;
output \axlen_cnt_reg[5] ;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3] ;
output [3:0]\axaddr_offset_r_reg[3] ;
output [3:0]S;
input aclk;
input sel_first_i;
input sel_first_reg_2;
input sel_first_reg_3;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [21:0]\m_payload_i_reg[51] ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input \state_reg[1]_rep ;
input \m_payload_i_reg[47]_0 ;
input \m_payload_i_reg[48] ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input \axaddr_offset_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [3:0]\axaddr_offset_r_reg[3]_1 ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input [2:0]\wrap_second_len_r_reg[3]_1 ;
input [6:0]\m_payload_i_reg[6] ;
input [0:0]sel_first_reg_4;
input m_axi_arready;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire [3:0]\axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire [3:0]\axaddr_offset_r_reg[3]_1 ;
wire \axlen_cnt_reg[5] ;
wire \axlen_cnt_reg[7] ;
wire incr_cmd_0_n_10;
wire incr_cmd_0_n_11;
wire incr_cmd_0_n_12;
wire incr_cmd_0_n_13;
wire incr_cmd_0_n_14;
wire incr_cmd_0_n_15;
wire incr_cmd_0_n_16;
wire incr_cmd_0_n_17;
wire incr_cmd_0_n_21;
wire incr_cmd_0_n_6;
wire incr_cmd_0_n_7;
wire incr_cmd_0_n_8;
wire incr_cmd_0_n_9;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire m_axi_arready;
wire \m_payload_i_reg[35] ;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire [21:0]\m_payload_i_reg[51] ;
wire [6:0]\m_payload_i_reg[6] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire r_rlast;
wire s_axburst_eq0;
wire s_axburst_eq1;
wire sel_first;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire sel_first_reg_3;
wire [0:0]sel_first_reg_4;
wire si_rs_arvalid;
wire \state_reg[0] ;
wire \state_reg[0]_rep ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire wrap_cmd_0_n_1;
wire wrap_cmd_0_n_2;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [2:0]\wrap_second_len_r_reg[3]_1 ;
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2 incr_cmd_0
(.D(D),
.E(E),
.O(O),
.Q(Q),
.S(S),
.aclk(aclk),
.\axaddr_incr_reg[0]_0 (sel_first),
.\axaddr_incr_reg[11]_0 ({incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14,incr_cmd_0_n_15,incr_cmd_0_n_16,incr_cmd_0_n_17}),
.\axlen_cnt_reg[5]_0 (\axlen_cnt_reg[5] ),
.\axlen_cnt_reg[7]_0 (\axlen_cnt_reg[7] ),
.incr_next_pending(incr_next_pending),
.\m_axi_araddr[10] (incr_cmd_0_n_21),
.m_axi_arready(m_axi_arready),
.\m_payload_i_reg[3] (\m_payload_i_reg[3] ),
.\m_payload_i_reg[47] (\m_payload_i_reg[47] ),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[48] (\m_payload_i_reg[48] ),
.\m_payload_i_reg[51] ({\m_payload_i_reg[51] [21:20],\m_payload_i_reg[51] [18],\m_payload_i_reg[51] [14:12],\m_payload_i_reg[51] [3:0]}),
.\m_payload_i_reg[7] (\m_payload_i_reg[7] ),
.m_valid_i_reg(m_valid_i_reg),
.next_pending_r_reg_0(next_pending_r_reg),
.sel_first_reg_0(sel_first_reg_2),
.sel_first_reg_1(sel_first_reg_4),
.\state_reg[0] (\state_reg[0] ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h1D))
r_rlast_r_i_1
(.I0(s_axburst_eq0),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq1),
.O(r_rlast));
FDRE s_axburst_eq0_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_1),
.Q(s_axburst_eq0),
.R(1'b0));
FDRE s_axburst_eq1_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_cmd_0_n_2),
.Q(s_axburst_eq1),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_i),
.Q(sel_first_reg_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hB8))
\state[1]_i_3
(.I0(s_axburst_eq1),
.I1(\m_payload_i_reg[51] [15]),
.I2(s_axburst_eq0),
.O(\state_reg[0]_rep ));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3 wrap_cmd_0
(.E(E),
.aclk(aclk),
.\axaddr_incr_reg[11] ({incr_cmd_0_n_6,incr_cmd_0_n_7,incr_cmd_0_n_8,incr_cmd_0_n_9,incr_cmd_0_n_10,incr_cmd_0_n_11,incr_cmd_0_n_12,incr_cmd_0_n_13,incr_cmd_0_n_14,incr_cmd_0_n_15,incr_cmd_0_n_16,incr_cmd_0_n_17}),
.\axaddr_offset_r_reg[3]_0 (\axaddr_offset_r_reg[3] ),
.\axaddr_offset_r_reg[3]_1 (\axaddr_offset_r_reg[3]_0 ),
.\axaddr_offset_r_reg[3]_2 (\axaddr_offset_r_reg[3]_1 ),
.incr_next_pending(incr_next_pending),
.m_axi_araddr(m_axi_araddr),
.\m_payload_i_reg[35] (\m_payload_i_reg[35] ),
.\m_payload_i_reg[47] ({\m_payload_i_reg[51] [19:15],\m_payload_i_reg[51] [13:0]}),
.\m_payload_i_reg[47]_0 (\m_payload_i_reg[47]_0 ),
.\m_payload_i_reg[6] (\m_payload_i_reg[6] ),
.m_valid_i_reg(m_valid_i_reg),
.s_axburst_eq0_reg(wrap_cmd_0_n_1),
.s_axburst_eq1_reg(wrap_cmd_0_n_2),
.sel_first_i(sel_first_i),
.sel_first_reg_0(sel_first_reg_1),
.sel_first_reg_1(sel_first_reg_3),
.sel_first_reg_2(incr_cmd_0_n_21),
.si_rs_arvalid(si_rs_arvalid),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\wrap_second_len_r_reg[3]_0 (\wrap_second_len_r_reg[3] ),
.\wrap_second_len_r_reg[3]_1 (\wrap_second_len_r_reg[3]_0 ),
.\wrap_second_len_r_reg[3]_2 (\wrap_second_len_r_reg[3]_1 ));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd
(next_pending_r_reg_0,
\axaddr_incr_reg[0]_0 ,
Q,
\axlen_cnt_reg[3]_0 ,
\axaddr_incr_reg[11]_0 ,
\m_axi_awaddr[10] ,
S,
incr_next_pending,
aclk,
sel_first_reg_0,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
next,
axaddr_incr,
\state_reg[0] ,
\state_reg[1] );
output next_pending_r_reg_0;
output \axaddr_incr_reg[0]_0 ;
output [0:0]Q;
output \axlen_cnt_reg[3]_0 ;
output [11:0]\axaddr_incr_reg[11]_0 ;
output \m_axi_awaddr[10] ;
output [3:0]S;
input incr_next_pending;
input aclk;
input sel_first_reg_0;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [12:0]\m_payload_i_reg[51] ;
input next;
input [11:0]axaddr_incr;
input [0:0]\state_reg[0] ;
input [0:0]\state_reg[1] ;
wire [0:0]E;
wire [0:0]Q;
wire [3:0]S;
wire aclk;
wire [11:0]axaddr_incr;
wire \axaddr_incr[11]_i_1_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [11:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4_n_1 ;
wire \axaddr_incr_reg[11]_i_4_n_2 ;
wire \axaddr_incr_reg[11]_i_4_n_3 ;
wire \axaddr_incr_reg[11]_i_4_n_4 ;
wire \axaddr_incr_reg[11]_i_4_n_5 ;
wire \axaddr_incr_reg[11]_i_4_n_6 ;
wire \axaddr_incr_reg[11]_i_4_n_7 ;
wire \axaddr_incr_reg[3]_i_3_n_0 ;
wire \axaddr_incr_reg[3]_i_3_n_1 ;
wire \axaddr_incr_reg[3]_i_3_n_2 ;
wire \axaddr_incr_reg[3]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_3_n_4 ;
wire \axaddr_incr_reg[3]_i_3_n_5 ;
wire \axaddr_incr_reg[3]_i_3_n_6 ;
wire \axaddr_incr_reg[3]_i_3_n_7 ;
wire \axaddr_incr_reg[7]_i_3_n_0 ;
wire \axaddr_incr_reg[7]_i_3_n_1 ;
wire \axaddr_incr_reg[7]_i_3_n_2 ;
wire \axaddr_incr_reg[7]_i_3_n_3 ;
wire \axaddr_incr_reg[7]_i_3_n_4 ;
wire \axaddr_incr_reg[7]_i_3_n_5 ;
wire \axaddr_incr_reg[7]_i_3_n_6 ;
wire \axaddr_incr_reg[7]_i_3_n_7 ;
wire \axlen_cnt[1]_i_1__0_n_0 ;
wire \axlen_cnt[2]_i_1__0_n_0 ;
wire \axlen_cnt[3]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_1_n_0 ;
wire \axlen_cnt[4]_i_2_n_0 ;
wire \axlen_cnt[5]_i_1_n_0 ;
wire \axlen_cnt[5]_i_2_n_0 ;
wire \axlen_cnt[6]_i_1_n_0 ;
wire \axlen_cnt[7]_i_2_n_0 ;
wire \axlen_cnt[7]_i_3_n_0 ;
wire \axlen_cnt_reg[3]_0 ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[5] ;
wire \axlen_cnt_reg_n_0_[6] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_awaddr[10] ;
wire \m_payload_i_reg[47] ;
wire [12:0]\m_payload_i_reg[51] ;
wire next;
wire next_pending_r_i_5_n_0;
wire next_pending_r_reg_0;
wire [11:0]p_1_in;
wire sel_first_reg_0;
wire [0:0]\state_reg[0] ;
wire [0:0]\state_reg[1] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1
(.I0(axaddr_incr[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_7 ),
.O(p_1_in[0]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1
(.I0(axaddr_incr[10]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_5 ),
.O(p_1_in[10]));
LUT2 #(
.INIT(4'hE))
\axaddr_incr[11]_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(next),
.O(\axaddr_incr[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2
(.I0(axaddr_incr[11]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_4 ),
.O(p_1_in[11]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1
(.I0(axaddr_incr[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_6 ),
.O(p_1_in[1]));
(* SOFT_HLUTNM = "soft_lutpair96" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1
(.I0(axaddr_incr[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_5 ),
.O(p_1_in[2]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1
(.I0(axaddr_incr[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3_n_4 ),
.O(p_1_in[3]));
LUT4 #(
.INIT(16'h0102))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(next),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg[11]_0 [3]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg[11]_0 [2]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_14_n_0 ));
LUT4 #(
.INIT(16'h6AAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(next),
.O(S[3]));
LUT4 #(
.INIT(16'h262A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(next),
.O(S[2]));
LUT4 #(
.INIT(16'h060A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.I3(next),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1
(.I0(axaddr_incr[4]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_7 ),
.O(p_1_in[4]));
(* SOFT_HLUTNM = "soft_lutpair97" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1
(.I0(axaddr_incr[5]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_6 ),
.O(p_1_in[5]));
(* SOFT_HLUTNM = "soft_lutpair100" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1
(.I0(axaddr_incr[6]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_5 ),
.O(p_1_in[6]));
(* SOFT_HLUTNM = "soft_lutpair99" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1
(.I0(axaddr_incr[7]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3_n_4 ),
.O(p_1_in[7]));
(* SOFT_HLUTNM = "soft_lutpair98" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1
(.I0(axaddr_incr[8]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_7 ),
.O(p_1_in[8]));
(* SOFT_HLUTNM = "soft_lutpair95" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1
(.I0(axaddr_incr[9]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4_n_6 ),
.O(p_1_in[9]));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[0]),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[10]),
.Q(\axaddr_incr_reg[11]_0 [10]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[11]),
.Q(\axaddr_incr_reg[11]_0 [11]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4
(.CI(\axaddr_incr_reg[7]_i_3_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4_n_1 ,\axaddr_incr_reg[11]_i_4_n_2 ,\axaddr_incr_reg[11]_i_4_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4_n_4 ,\axaddr_incr_reg[11]_i_4_n_5 ,\axaddr_incr_reg[11]_i_4_n_6 ,\axaddr_incr_reg[11]_i_4_n_7 }),
.S(\axaddr_incr_reg[11]_0 [11:8]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[1]),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[2]),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[3]),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3_n_0 ,\axaddr_incr_reg[3]_i_3_n_1 ,\axaddr_incr_reg[3]_i_3_n_2 ,\axaddr_incr_reg[3]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(\axaddr_incr_reg[11]_0 [3:0]),
.O({\axaddr_incr_reg[3]_i_3_n_4 ,\axaddr_incr_reg[3]_i_3_n_5 ,\axaddr_incr_reg[3]_i_3_n_6 ,\axaddr_incr_reg[3]_i_3_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[4]),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[5]),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[6]),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[7]),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3
(.CI(\axaddr_incr_reg[3]_i_3_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3_n_0 ,\axaddr_incr_reg[7]_i_3_n_1 ,\axaddr_incr_reg[7]_i_3_n_2 ,\axaddr_incr_reg[7]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3_n_4 ,\axaddr_incr_reg[7]_i_3_n_5 ,\axaddr_incr_reg[7]_i_3_n_6 ,\axaddr_incr_reg[7]_i_3_n_7 }),
.S(\axaddr_incr_reg[11]_0 [7:4]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[8]),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(\axaddr_incr[11]_i_1_n_0 ),
.D(p_1_in[9]),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[3]_0 ),
.O(\axlen_cnt[1]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__0
(.I0(E),
.I1(\m_payload_i_reg[51] [8]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg[3]_0 ),
.O(\axlen_cnt[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg[3]_0 ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'h8FF88888))
\axlen_cnt[4]_i_1
(.I0(E),
.I1(\m_payload_i_reg[51] [9]),
.I2(\axlen_cnt_reg_n_0_[4] ),
.I3(\axlen_cnt[4]_i_2_n_0 ),
.I4(\axlen_cnt_reg[3]_0 ),
.O(\axlen_cnt[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT4 #(
.INIT(16'h0001))
\axlen_cnt[4]_i_2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(Q),
.I3(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt[4]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF606060))
\axlen_cnt[5]_i_1
(.I0(\axlen_cnt_reg_n_0_[5] ),
.I1(\axlen_cnt[5]_i_2_n_0 ),
.I2(\axlen_cnt_reg[3]_0 ),
.I3(E),
.I4(\m_payload_i_reg[51] [10]),
.O(\axlen_cnt[5]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair94" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[5]_i_2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(Q),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[4] ),
.O(\axlen_cnt[5]_i_2_n_0 ));
LUT5 #(
.INIT(32'hFF606060))
\axlen_cnt[6]_i_1
(.I0(\axlen_cnt_reg_n_0_[6] ),
.I1(\axlen_cnt[7]_i_3_n_0 ),
.I2(\axlen_cnt_reg[3]_0 ),
.I3(E),
.I4(\m_payload_i_reg[51] [11]),
.O(\axlen_cnt[6]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF9A009A009A00))
\axlen_cnt[7]_i_2
(.I0(\axlen_cnt_reg_n_0_[7] ),
.I1(\axlen_cnt_reg_n_0_[6] ),
.I2(\axlen_cnt[7]_i_3_n_0 ),
.I3(\axlen_cnt_reg[3]_0 ),
.I4(E),
.I5(\m_payload_i_reg[51] [12]),
.O(\axlen_cnt[7]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\axlen_cnt[7]_i_3
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(Q),
.I4(\axlen_cnt_reg_n_0_[3] ),
.I5(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt[7]_i_3_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\state_reg[1] ),
.Q(Q),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[4]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[5]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[5] ),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[6]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[6] ),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[7]_i_2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\m_axi_awaddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[51] [6]),
.O(\m_axi_awaddr[10] ));
LUT5 #(
.INIT(32'h55555554))
next_pending_r_i_3__1
(.I0(E),
.I1(next_pending_r_i_5_n_0),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[4] ),
.I4(\axlen_cnt_reg_n_0_[5] ),
.O(\axlen_cnt_reg[3]_0 ));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_5
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[6] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.O(next_pending_r_i_5_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_incr_cmd" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_incr_cmd_2
(incr_next_pending,
\axaddr_incr_reg[0]_0 ,
Q,
\axaddr_incr_reg[11]_0 ,
\axlen_cnt_reg[7]_0 ,
next_pending_r_reg_0,
\axlen_cnt_reg[5]_0 ,
\m_axi_araddr[10] ,
S,
aclk,
sel_first_reg_0,
\state_reg[0] ,
\m_payload_i_reg[47] ,
E,
\m_payload_i_reg[51] ,
\m_payload_i_reg[48] ,
\m_payload_i_reg[47]_0 ,
\state_reg[1]_rep ,
O,
\m_payload_i_reg[7] ,
\m_payload_i_reg[3] ,
m_valid_i_reg,
D,
sel_first_reg_1,
\state_reg[1] ,
m_axi_arready);
output incr_next_pending;
output \axaddr_incr_reg[0]_0 ;
output [3:0]Q;
output [11:0]\axaddr_incr_reg[11]_0 ;
output \axlen_cnt_reg[7]_0 ;
output next_pending_r_reg_0;
output \axlen_cnt_reg[5]_0 ;
output \m_axi_araddr[10] ;
output [3:0]S;
input aclk;
input sel_first_reg_0;
input \state_reg[0] ;
input \m_payload_i_reg[47] ;
input [0:0]E;
input [9:0]\m_payload_i_reg[51] ;
input \m_payload_i_reg[48] ;
input \m_payload_i_reg[47]_0 ;
input \state_reg[1]_rep ;
input [3:0]O;
input [3:0]\m_payload_i_reg[7] ;
input [3:0]\m_payload_i_reg[3] ;
input [0:0]m_valid_i_reg;
input [3:0]D;
input [0:0]sel_first_reg_1;
input [1:0]\state_reg[1] ;
input m_axi_arready;
wire [3:0]D;
wire [0:0]E;
wire [3:0]O;
wire [3:0]Q;
wire [3:0]S;
wire aclk;
wire \axaddr_incr[0]_i_1__0_n_0 ;
wire \axaddr_incr[10]_i_1__0_n_0 ;
wire \axaddr_incr[11]_i_2__0_n_0 ;
wire \axaddr_incr[1]_i_1__0_n_0 ;
wire \axaddr_incr[2]_i_1__0_n_0 ;
wire \axaddr_incr[3]_i_11_n_0 ;
wire \axaddr_incr[3]_i_12_n_0 ;
wire \axaddr_incr[3]_i_13_n_0 ;
wire \axaddr_incr[3]_i_14_n_0 ;
wire \axaddr_incr[3]_i_1__0_n_0 ;
wire \axaddr_incr[4]_i_1__0_n_0 ;
wire \axaddr_incr[5]_i_1__0_n_0 ;
wire \axaddr_incr[6]_i_1__0_n_0 ;
wire \axaddr_incr[7]_i_1__0_n_0 ;
wire \axaddr_incr[8]_i_1__0_n_0 ;
wire \axaddr_incr[9]_i_1__0_n_0 ;
wire \axaddr_incr_reg[0]_0 ;
wire [11:0]\axaddr_incr_reg[11]_0 ;
wire \axaddr_incr_reg[11]_i_4__0_n_1 ;
wire \axaddr_incr_reg[11]_i_4__0_n_2 ;
wire \axaddr_incr_reg[11]_i_4__0_n_3 ;
wire \axaddr_incr_reg[11]_i_4__0_n_4 ;
wire \axaddr_incr_reg[11]_i_4__0_n_5 ;
wire \axaddr_incr_reg[11]_i_4__0_n_6 ;
wire \axaddr_incr_reg[11]_i_4__0_n_7 ;
wire \axaddr_incr_reg[3]_i_3__0_n_0 ;
wire \axaddr_incr_reg[3]_i_3__0_n_1 ;
wire \axaddr_incr_reg[3]_i_3__0_n_2 ;
wire \axaddr_incr_reg[3]_i_3__0_n_3 ;
wire \axaddr_incr_reg[3]_i_3__0_n_4 ;
wire \axaddr_incr_reg[3]_i_3__0_n_5 ;
wire \axaddr_incr_reg[3]_i_3__0_n_6 ;
wire \axaddr_incr_reg[3]_i_3__0_n_7 ;
wire \axaddr_incr_reg[7]_i_3__0_n_0 ;
wire \axaddr_incr_reg[7]_i_3__0_n_1 ;
wire \axaddr_incr_reg[7]_i_3__0_n_2 ;
wire \axaddr_incr_reg[7]_i_3__0_n_3 ;
wire \axaddr_incr_reg[7]_i_3__0_n_4 ;
wire \axaddr_incr_reg[7]_i_3__0_n_5 ;
wire \axaddr_incr_reg[7]_i_3__0_n_6 ;
wire \axaddr_incr_reg[7]_i_3__0_n_7 ;
wire \axlen_cnt[2]_i_1__1_n_0 ;
wire \axlen_cnt[3]_i_1__1_n_0 ;
wire \axlen_cnt[4]_i_1__0_n_0 ;
wire \axlen_cnt[4]_i_2__0_n_0 ;
wire \axlen_cnt[7]_i_2__0_n_0 ;
wire \axlen_cnt_reg[5]_0 ;
wire \axlen_cnt_reg[7]_0 ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire \axlen_cnt_reg_n_0_[4] ;
wire \axlen_cnt_reg_n_0_[7] ;
wire incr_next_pending;
wire \m_axi_araddr[10] ;
wire m_axi_arready;
wire [3:0]\m_payload_i_reg[3] ;
wire \m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire \m_payload_i_reg[48] ;
wire [9:0]\m_payload_i_reg[51] ;
wire [3:0]\m_payload_i_reg[7] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_5__0_n_0;
wire next_pending_r_reg_0;
wire next_pending_r_reg_n_0;
wire sel_first_reg_0;
wire [0:0]sel_first_reg_1;
wire \state_reg[0] ;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[0]_i_1__0
(.I0(\m_payload_i_reg[3] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_7 ),
.O(\axaddr_incr[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[10]_i_1__0
(.I0(O[2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_5 ),
.O(\axaddr_incr[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[11]_i_2__0
(.I0(O[3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_4 ),
.O(\axaddr_incr[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[1]_i_1__0
(.I0(\m_payload_i_reg[3] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_6 ),
.O(\axaddr_incr[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[2]_i_1__0
(.I0(\m_payload_i_reg[3] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_5 ),
.O(\axaddr_incr[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'h0201020202020202))
\axaddr_incr[3]_i_10
(.I0(\m_payload_i_reg[51] [0]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[0]));
LUT3 #(
.INIT(8'h6A))
\axaddr_incr[3]_i_11
(.I0(\axaddr_incr_reg[11]_0 [3]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_11_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_12
(.I0(\axaddr_incr_reg[11]_0 [2]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_12_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_incr[3]_i_13
(.I0(\axaddr_incr_reg[11]_0 [1]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.O(\axaddr_incr[3]_i_13_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_incr[3]_i_14
(.I0(\axaddr_incr_reg[11]_0 [0]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.O(\axaddr_incr[3]_i_14_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[3]_i_1__0
(.I0(\m_payload_i_reg[3] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[3]_i_3__0_n_4 ),
.O(\axaddr_incr[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA6AAAAAAAAAAAAA))
\axaddr_incr[3]_i_7
(.I0(\m_payload_i_reg[51] [3]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[3]));
LUT6 #(
.INIT(64'h2A262A2A2A2A2A2A))
\axaddr_incr[3]_i_8
(.I0(\m_payload_i_reg[51] [2]),
.I1(\m_payload_i_reg[51] [5]),
.I2(\m_payload_i_reg[51] [4]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[2]));
LUT6 #(
.INIT(64'h0A060A0A0A0A0A0A))
\axaddr_incr[3]_i_9
(.I0(\m_payload_i_reg[51] [1]),
.I1(\m_payload_i_reg[51] [4]),
.I2(\m_payload_i_reg[51] [5]),
.I3(\state_reg[1] [1]),
.I4(\state_reg[1] [0]),
.I5(m_axi_arready),
.O(S[1]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[4]_i_1__0
(.I0(\m_payload_i_reg[7] [0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_7 ),
.O(\axaddr_incr[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[5]_i_1__0
(.I0(\m_payload_i_reg[7] [1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_6 ),
.O(\axaddr_incr[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[6]_i_1__0
(.I0(\m_payload_i_reg[7] [2]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_5 ),
.O(\axaddr_incr[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[7]_i_1__0
(.I0(\m_payload_i_reg[7] [3]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[7]_i_3__0_n_4 ),
.O(\axaddr_incr[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[8]_i_1__0
(.I0(O[0]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_7 ),
.O(\axaddr_incr[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_incr[9]_i_1__0
(.I0(O[1]),
.I1(\axaddr_incr_reg[0]_0 ),
.I2(\axaddr_incr_reg[11]_i_4__0_n_6 ),
.O(\axaddr_incr[9]_i_1__0_n_0 ));
FDRE \axaddr_incr_reg[0]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[0]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [0]),
.R(1'b0));
FDRE \axaddr_incr_reg[10]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[10]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [10]),
.R(1'b0));
FDRE \axaddr_incr_reg[11]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[11]_i_2__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [11]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[11]_i_4__0
(.CI(\axaddr_incr_reg[7]_i_3__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_4__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_4__0_n_1 ,\axaddr_incr_reg[11]_i_4__0_n_2 ,\axaddr_incr_reg[11]_i_4__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[11]_i_4__0_n_4 ,\axaddr_incr_reg[11]_i_4__0_n_5 ,\axaddr_incr_reg[11]_i_4__0_n_6 ,\axaddr_incr_reg[11]_i_4__0_n_7 }),
.S(\axaddr_incr_reg[11]_0 [11:8]));
FDRE \axaddr_incr_reg[1]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[1]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [1]),
.R(1'b0));
FDRE \axaddr_incr_reg[2]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[2]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [2]),
.R(1'b0));
FDRE \axaddr_incr_reg[3]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[3]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [3]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[3]_i_3__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_3__0_n_0 ,\axaddr_incr_reg[3]_i_3__0_n_1 ,\axaddr_incr_reg[3]_i_3__0_n_2 ,\axaddr_incr_reg[3]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI(\axaddr_incr_reg[11]_0 [3:0]),
.O({\axaddr_incr_reg[3]_i_3__0_n_4 ,\axaddr_incr_reg[3]_i_3__0_n_5 ,\axaddr_incr_reg[3]_i_3__0_n_6 ,\axaddr_incr_reg[3]_i_3__0_n_7 }),
.S({\axaddr_incr[3]_i_11_n_0 ,\axaddr_incr[3]_i_12_n_0 ,\axaddr_incr[3]_i_13_n_0 ,\axaddr_incr[3]_i_14_n_0 }));
FDRE \axaddr_incr_reg[4]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[4]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [4]),
.R(1'b0));
FDRE \axaddr_incr_reg[5]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[5]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [5]),
.R(1'b0));
FDRE \axaddr_incr_reg[6]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[6]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [6]),
.R(1'b0));
FDRE \axaddr_incr_reg[7]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[7]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [7]),
.R(1'b0));
CARRY4 \axaddr_incr_reg[7]_i_3__0
(.CI(\axaddr_incr_reg[3]_i_3__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_3__0_n_0 ,\axaddr_incr_reg[7]_i_3__0_n_1 ,\axaddr_incr_reg[7]_i_3__0_n_2 ,\axaddr_incr_reg[7]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_incr_reg[7]_i_3__0_n_4 ,\axaddr_incr_reg[7]_i_3__0_n_5 ,\axaddr_incr_reg[7]_i_3__0_n_6 ,\axaddr_incr_reg[7]_i_3__0_n_7 }),
.S(\axaddr_incr_reg[11]_0 [7:4]));
FDRE \axaddr_incr_reg[8]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[8]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [8]),
.R(1'b0));
FDRE \axaddr_incr_reg[9]
(.C(aclk),
.CE(sel_first_reg_1),
.D(\axaddr_incr[9]_i_1__0_n_0 ),
.Q(\axaddr_incr_reg[11]_0 [9]),
.R(1'b0));
LUT6 #(
.INIT(64'hF8F8F88F88888888))
\axlen_cnt[2]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[51] [7]),
.I2(\axlen_cnt_reg_n_0_[2] ),
.I3(Q[0]),
.I4(Q[1]),
.I5(\state_reg[0] ),
.O(\axlen_cnt[2]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hAAA90000FFFFFFFF))
\axlen_cnt[3]_i_1__1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\state_reg[0] ),
.I5(\m_payload_i_reg[47] ),
.O(\axlen_cnt[3]_i_1__1_n_0 ));
LUT5 #(
.INIT(32'hFF909090))
\axlen_cnt[4]_i_1__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(\axlen_cnt[4]_i_2__0_n_0 ),
.I2(\state_reg[0] ),
.I3(E),
.I4(\m_payload_i_reg[51] [8]),
.O(\axlen_cnt[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'hFFFE))
\axlen_cnt[4]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.O(\axlen_cnt[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT5 #(
.INIT(32'h00000001))
\axlen_cnt[5]_i_2__0
(.I0(\axlen_cnt_reg_n_0_[4] ),
.I1(Q[0]),
.I2(Q[1]),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(\axlen_cnt_reg_n_0_[3] ),
.O(\axlen_cnt_reg[5]_0 ));
LUT6 #(
.INIT(64'hF88888F8F888F888))
\axlen_cnt[7]_i_2__0
(.I0(E),
.I1(\m_payload_i_reg[51] [9]),
.I2(\state_reg[0] ),
.I3(\axlen_cnt_reg_n_0_[7] ),
.I4(Q[3]),
.I5(\axlen_cnt_reg[7]_0 ),
.O(\axlen_cnt[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h0000000000000001))
\axlen_cnt[7]_i_4
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(Q[1]),
.I3(Q[0]),
.I4(\axlen_cnt_reg_n_0_[4] ),
.I5(Q[2]),
.O(\axlen_cnt_reg[7]_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
FDRE \axlen_cnt_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[4]_i_1__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[4] ),
.R(1'b0));
FDRE \axlen_cnt_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \axlen_cnt_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(D[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \axlen_cnt_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[7]_i_2__0_n_0 ),
.Q(\axlen_cnt_reg_n_0_[7] ),
.R(1'b0));
LUT2 #(
.INIT(4'hB))
\m_axi_araddr[11]_INST_0_i_1
(.I0(\axaddr_incr_reg[0]_0 ),
.I1(\m_payload_i_reg[51] [6]),
.O(\m_axi_araddr[10] ));
LUT6 #(
.INIT(64'hDDDDCCFCFFDDFFFC))
next_pending_r_i_1__2
(.I0(\m_payload_i_reg[48] ),
.I1(\m_payload_i_reg[47]_0 ),
.I2(next_pending_r_reg_n_0),
.I3(\state_reg[1]_rep ),
.I4(E),
.I5(next_pending_r_reg_0),
.O(incr_next_pending));
LUT4 #(
.INIT(16'h0002))
next_pending_r_i_4__0
(.I0(next_pending_r_i_5__0_n_0),
.I1(\axlen_cnt_reg_n_0_[7] ),
.I2(Q[3]),
.I3(\axlen_cnt_reg_n_0_[4] ),
.O(next_pending_r_reg_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_5__0
(.I0(Q[1]),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(Q[2]),
.O(next_pending_r_i_5__0_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(incr_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_0),
.Q(\axaddr_incr_reg[0]_0 ),
.R(1'b0));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_r_channel
(\state_reg[1]_rep ,
m_axi_rready,
s_ready_i_reg,
out,
\skid_buffer_reg[35] ,
\state_reg[1]_rep_0 ,
aclk,
r_rlast,
s_arid_r,
s_ready_i_reg_0,
si_rs_rready,
m_axi_rvalid,
in,
areset_d1);
output \state_reg[1]_rep ;
output m_axi_rready;
output s_ready_i_reg;
output [33:0]out;
output [1:0]\skid_buffer_reg[35] ;
input \state_reg[1]_rep_0 ;
input aclk;
input r_rlast;
input s_arid_r;
input s_ready_i_reg_0;
input si_rs_rready;
input m_axi_rvalid;
input [33:0]in;
input areset_d1;
wire aclk;
wire areset_d1;
wire [4:3]cnt_read;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire r_push_r;
wire r_rlast;
wire rd_data_fifo_0_n_2;
wire rd_data_fifo_0_n_3;
wire s_arid_r;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire [1:0]\skid_buffer_reg[35] ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [1:0]trans_in;
wire transaction_fifo_0_n_3;
FDRE \r_arid_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(s_arid_r),
.Q(trans_in[1]),
.R(1'b0));
FDRE r_push_r_reg
(.C(aclk),
.CE(1'b1),
.D(\state_reg[1]_rep_0 ),
.Q(r_push_r),
.R(1'b0));
FDRE r_rlast_r_reg
(.C(aclk),
.CE(1'b1),
.D(r_rlast),
.Q(trans_in[0]),
.R(1'b0));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1 rd_data_fifo_0
(.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[2]_0 (transaction_fifo_0_n_3),
.\cnt_read_reg[4]_0 (rd_data_fifo_0_n_3),
.in(in),
.m_axi_rready(m_axi_rready),
.m_axi_rvalid(m_axi_rvalid),
.out(out),
.r_push_r(r_push_r),
.s_ready_i_reg(s_ready_i_reg),
.s_ready_i_reg_0(s_ready_i_reg_0),
.si_rs_rready(si_rs_rready),
.\state_reg[1]_rep (rd_data_fifo_0_n_2));
DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2 transaction_fifo_0
(.Q(cnt_read),
.aclk(aclk),
.areset_d1(areset_d1),
.\cnt_read_reg[0]_rep__2 (rd_data_fifo_0_n_2),
.\cnt_read_reg[4]_rep__2 (s_ready_i_reg),
.in(trans_in),
.r_push_r(r_push_r),
.s_ready_i_reg(transaction_fifo_0_n_3),
.s_ready_i_reg_0(s_ready_i_reg_0),
.s_ready_i_reg_1(rd_data_fifo_0_n_3),
.si_rs_rready(si_rs_rready),
.\skid_buffer_reg[35] (\skid_buffer_reg[35] ),
.\state_reg[1]_rep (\state_reg[1]_rep ));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_rd_cmd_fsm
(\axlen_cnt_reg[5] ,
Q,
r_push_r_reg,
\m_payload_i_reg[0] ,
\axlen_cnt_reg[0] ,
D,
E,
\wrap_cnt_r_reg[3] ,
\wrap_cnt_r_reg[0] ,
axaddr_offset,
\wrap_second_len_r_reg[3] ,
\axaddr_wrap_reg[11] ,
sel_first_reg,
sel_first_reg_0,
sel_first_i,
\axaddr_incr_reg[0] ,
m_axi_arvalid,
\m_payload_i_reg[0]_0 ,
si_rs_arvalid,
\axlen_cnt_reg[7] ,
m_axi_arready,
s_axburst_eq1_reg,
\cnt_read_reg[2] ,
\axlen_cnt_reg[6] ,
\axlen_cnt_reg[4] ,
\m_payload_i_reg[50] ,
\axlen_cnt_reg[3] ,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[46] ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
sel_first_reg_1,
areset_d1,
sel_first,
sel_first_reg_2,
\m_payload_i_reg[6] ,
aclk);
output \axlen_cnt_reg[5] ;
output [1:0]Q;
output r_push_r_reg;
output \m_payload_i_reg[0] ;
output \axlen_cnt_reg[0] ;
output [3:0]D;
output [0:0]E;
output [2:0]\wrap_cnt_r_reg[3] ;
output \wrap_cnt_r_reg[0] ;
output [1:0]axaddr_offset;
output [3:0]\wrap_second_len_r_reg[3] ;
output [0:0]\axaddr_wrap_reg[11] ;
output sel_first_reg;
output sel_first_reg_0;
output sel_first_i;
output [0:0]\axaddr_incr_reg[0] ;
output m_axi_arvalid;
output [0:0]\m_payload_i_reg[0]_0 ;
input si_rs_arvalid;
input \axlen_cnt_reg[7] ;
input m_axi_arready;
input s_axburst_eq1_reg;
input \cnt_read_reg[2] ;
input [3:0]\axlen_cnt_reg[6] ;
input \axlen_cnt_reg[4] ;
input [4:0]\m_payload_i_reg[50] ;
input \axlen_cnt_reg[3] ;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\m_payload_i_reg[46] ;
input [1:0]\axaddr_offset_r_reg[3] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input sel_first_reg_1;
input areset_d1;
input sel_first;
input sel_first_reg_2;
input \m_payload_i_reg[6] ;
input aclk;
wire [3:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [0:0]\axaddr_incr_reg[0] ;
wire [1:0]axaddr_offset;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_wrap_reg[11] ;
wire \axlen_cnt_reg[0] ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[4] ;
wire \axlen_cnt_reg[5] ;
wire [3:0]\axlen_cnt_reg[6] ;
wire \axlen_cnt_reg[7] ;
wire \cnt_read_reg[2] ;
wire m_axi_arready;
wire m_axi_arvalid;
wire \m_payload_i_reg[0] ;
wire [0:0]\m_payload_i_reg[0]_0 ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [0:0]\m_payload_i_reg[46] ;
wire [4:0]\m_payload_i_reg[50] ;
wire \m_payload_i_reg[6] ;
wire [1:0]next_state;
wire r_push_r_reg;
wire s_axburst_eq1_reg;
wire sel_first;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire \wrap_cnt_r[3]_i_2__0_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire [2:0]\wrap_cnt_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT4 #(
.INIT(16'hAAEA))
\axaddr_incr[11]_i_1__0
(.I0(sel_first),
.I1(m_axi_arready),
.I2(\axlen_cnt_reg[0] ),
.I3(\m_payload_i_reg[0] ),
.O(\axaddr_incr_reg[0] ));
LUT6 #(
.INIT(64'hAAAAAAAAAAC0AAAA))
\axaddr_offset_r[0]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[3] ),
.I2(\m_payload_i_reg[50] [0]),
.I3(Q[0]),
.I4(si_rs_arvalid),
.I5(Q[1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1__0
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\m_payload_i_reg[50] [2]),
.I2(\axlen_cnt_reg[0] ),
.I3(si_rs_arvalid),
.I4(\m_payload_i_reg[0] ),
.I5(\m_payload_i_reg[6] ),
.O(axaddr_offset[1]));
LUT5 #(
.INIT(32'h20FF2020))
\axlen_cnt[0]_i_1__2
(.I0(si_rs_arvalid),
.I1(\axlen_cnt_reg[0] ),
.I2(\m_payload_i_reg[50] [0]),
.I3(\axlen_cnt_reg[6] [0]),
.I4(\axlen_cnt_reg[5] ),
.O(D[0]));
LUT5 #(
.INIT(32'hF88F8888))
\axlen_cnt[1]_i_1__1
(.I0(E),
.I1(\m_payload_i_reg[50] [1]),
.I2(\axlen_cnt_reg[6] [1]),
.I3(\axlen_cnt_reg[6] [0]),
.I4(\axlen_cnt_reg[5] ),
.O(D[1]));
LUT5 #(
.INIT(32'hFF282828))
\axlen_cnt[5]_i_1__0
(.I0(\axlen_cnt_reg[5] ),
.I1(\axlen_cnt_reg[6] [2]),
.I2(\axlen_cnt_reg[4] ),
.I3(E),
.I4(\m_payload_i_reg[50] [3]),
.O(D[2]));
LUT5 #(
.INIT(32'hFF282828))
\axlen_cnt[6]_i_1__0
(.I0(\axlen_cnt_reg[5] ),
.I1(\axlen_cnt_reg[6] [3]),
.I2(\axlen_cnt_reg[3] ),
.I3(E),
.I4(\m_payload_i_reg[50] [4]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00CA))
\axlen_cnt[7]_i_1__0
(.I0(si_rs_arvalid),
.I1(m_axi_arready),
.I2(Q[0]),
.I3(Q[1]),
.O(\axaddr_wrap_reg[11] ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h00FB))
\axlen_cnt[7]_i_3__0
(.I0(Q[0]),
.I1(si_rs_arvalid),
.I2(Q[1]),
.I3(\axlen_cnt_reg[7] ),
.O(\axlen_cnt_reg[5] ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT2 #(
.INIT(4'h2))
m_axi_arvalid_INST_0
(.I0(\axlen_cnt_reg[0] ),
.I1(\m_payload_i_reg[0] ),
.O(m_axi_arvalid));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hD5))
\m_payload_i[31]_i_1__0
(.I0(si_rs_arvalid),
.I1(\m_payload_i_reg[0] ),
.I2(\axlen_cnt_reg[0] ),
.O(\m_payload_i_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h40))
r_push_r_i_1
(.I0(\m_payload_i_reg[0] ),
.I1(\axlen_cnt_reg[0] ),
.I2(m_axi_arready),
.O(r_push_r_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__2
(.I0(m_axi_arready),
.I1(sel_first_reg_1),
.I2(Q[1]),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFFC4C4CFCC))
sel_first_i_1__3
(.I0(m_axi_arready),
.I1(sel_first),
.I2(\m_payload_i_reg[0] ),
.I3(si_rs_arvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFCFFFFFFCCCECCCE))
sel_first_i_1__4
(.I0(si_rs_arvalid),
.I1(areset_d1),
.I2(\m_payload_i_reg[0] ),
.I3(\axlen_cnt_reg[0] ),
.I4(m_axi_arready),
.I5(sel_first_reg_2),
.O(sel_first_i));
LUT6 #(
.INIT(64'h003030303E3E3E3E))
\state[0]_i_1__0
(.I0(si_rs_arvalid),
.I1(Q[1]),
.I2(Q[0]),
.I3(m_axi_arready),
.I4(s_axburst_eq1_reg),
.I5(\cnt_read_reg[2] ),
.O(next_state[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h00AAB000))
\state[1]_i_1
(.I0(\cnt_read_reg[2] ),
.I1(s_axburst_eq1_reg),
.I2(m_axi_arready),
.I3(\axlen_cnt_reg[0] ),
.I4(\m_payload_i_reg[0] ),
.O(next_state[1]));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(Q[0]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[0]" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[0]),
.Q(\axlen_cnt_reg[0] ),
.R(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(Q[1]),
.R(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "state_reg[1]" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(next_state[1]),
.Q(\m_payload_i_reg[0] ),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1__0
(.I0(\m_payload_i_reg[0] ),
.I1(si_rs_arvalid),
.I2(\axlen_cnt_reg[0] ),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_cnt_r_reg[3] [0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(axaddr_offset[0]),
.I5(\wrap_second_len_r_reg[3] [1]),
.O(\wrap_cnt_r_reg[3] [1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1__0
(.I0(\wrap_second_len_r_reg[3] [3]),
.I1(\wrap_second_len_r_reg[3] [1]),
.I2(\wrap_cnt_r[3]_i_2__0_n_0 ),
.I3(\wrap_second_len_r_reg[3] [2]),
.O(\wrap_cnt_r_reg[3] [2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(axaddr_offset[1]),
.O(\wrap_cnt_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_arvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2__0
(.I0(axaddr_offset[0]),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[46] ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'h0FE0FFFF0FE00000))
\wrap_second_len_r[1]_i_1__0
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hCC2CFFFFCC2C0000))
\wrap_second_len_r[2]_i_1__0
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hFFFFF4FF44444444))
\wrap_second_len_r[3]_i_1__0
(.I0(E),
.I1(\wrap_second_len_r_reg[3]_0 [3]),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_second_len_r_reg[3] [3]));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo
(\cnt_read_reg[0]_rep_0 ,
\cnt_read_reg[1]_rep_0 ,
bvalid_i_reg,
SR,
bresp_push,
D,
out,
b_push,
shandshake_r,
areset_d1,
si_rs_bready,
bvalid_i_reg_0,
Q,
mhandshake_r,
\bresp_cnt_reg[7] ,
in,
aclk);
output \cnt_read_reg[0]_rep_0 ;
output \cnt_read_reg[1]_rep_0 ;
output bvalid_i_reg;
output [0:0]SR;
output bresp_push;
output [0:0]D;
output [0:0]out;
input b_push;
input shandshake_r;
input areset_d1;
input si_rs_bready;
input bvalid_i_reg_0;
input [1:0]Q;
input mhandshake_r;
input [7:0]\bresp_cnt_reg[7] ;
input [8:0]in;
input aclk;
wire [0:0]D;
wire [1:0]Q;
wire [0:0]SR;
wire aclk;
wire areset_d1;
wire b_push;
wire [7:0]\bresp_cnt_reg[7] ;
wire bresp_push;
wire bvalid_i_i_2_n_0;
wire bvalid_i_reg;
wire bvalid_i_reg_0;
wire [1:0]cnt_read;
wire \cnt_read[0]_i_1__2_n_0 ;
wire \cnt_read[1]_i_1_n_0 ;
wire \cnt_read_reg[0]_rep_0 ;
wire \cnt_read_reg[1]_rep_0 ;
wire [8:0]in;
wire \memory_reg[3][0]_srl4_i_2__0_n_0 ;
wire \memory_reg[3][0]_srl4_i_3_n_0 ;
wire \memory_reg[3][0]_srl4_i_4_n_0 ;
wire \memory_reg[3][0]_srl4_i_5_n_0 ;
wire \memory_reg[3][0]_srl4_i_6_n_0 ;
wire \memory_reg[3][0]_srl4_i_7_n_0 ;
wire \memory_reg[3][0]_srl4_i_8_n_0 ;
wire \memory_reg[3][0]_srl4_n_0 ;
wire \memory_reg[3][1]_srl4_n_0 ;
wire \memory_reg[3][2]_srl4_n_0 ;
wire \memory_reg[3][3]_srl4_n_0 ;
wire \memory_reg[3][4]_srl4_n_0 ;
wire \memory_reg[3][5]_srl4_n_0 ;
wire \memory_reg[3][6]_srl4_n_0 ;
wire \memory_reg[3][7]_srl4_n_0 ;
wire mhandshake_r;
wire [0:0]out;
wire shandshake_r;
wire si_rs_bready;
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT2 #(
.INIT(4'hE))
\bresp_cnt[7]_i_1
(.I0(areset_d1),
.I1(bresp_push),
.O(SR));
(* SOFT_HLUTNM = "soft_lutpair103" *)
LUT4 #(
.INIT(16'h0444))
bvalid_i_i_1
(.I0(areset_d1),
.I1(bvalid_i_i_2_n_0),
.I2(si_rs_bready),
.I3(bvalid_i_reg_0),
.O(bvalid_i_reg));
LUT6 #(
.INIT(64'hFFFFFFFF00070707))
bvalid_i_i_2
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(\cnt_read_reg[1]_rep_0 ),
.I2(shandshake_r),
.I3(Q[1]),
.I4(Q[0]),
.I5(bvalid_i_reg_0),
.O(bvalid_i_i_2_n_0));
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1
(.I0(bresp_push),
.I1(shandshake_r),
.I2(Q[0]),
.O(D));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__2
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(b_push),
.I2(shandshake_r),
.O(\cnt_read[0]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair102" *)
LUT4 #(
.INIT(16'hE718))
\cnt_read[1]_i_1
(.I0(\cnt_read_reg[0]_rep_0 ),
.I1(b_push),
.I2(shandshake_r),
.I3(\cnt_read_reg[1]_rep_0 ),
.O(\cnt_read[1]_i_1_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__2_n_0 ),
.Q(\cnt_read_reg[0]_rep_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1_n_0 ),
.Q(\cnt_read_reg[1]_rep_0 ),
.S(areset_d1));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[0]),
.Q(\memory_reg[3][0]_srl4_n_0 ));
LUT6 #(
.INIT(64'h0000000000004044))
\memory_reg[3][0]_srl4_i_1__0
(.I0(\memory_reg[3][0]_srl4_i_2__0_n_0 ),
.I1(mhandshake_r),
.I2(\memory_reg[3][7]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [7]),
.I4(\memory_reg[3][0]_srl4_i_3_n_0 ),
.I5(\memory_reg[3][0]_srl4_i_4_n_0 ),
.O(bresp_push));
LUT5 #(
.INIT(32'hFFFF22F2))
\memory_reg[3][0]_srl4_i_2__0
(.I0(\memory_reg[3][0]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [0]),
.I2(\bresp_cnt_reg[7] [3]),
.I3(\memory_reg[3][3]_srl4_n_0 ),
.I4(\memory_reg[3][0]_srl4_i_5_n_0 ),
.O(\memory_reg[3][0]_srl4_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hEFEEFFFFEFEEEFEE))
\memory_reg[3][0]_srl4_i_3
(.I0(\memory_reg[3][0]_srl4_i_6_n_0 ),
.I1(\memory_reg[3][0]_srl4_i_7_n_0 ),
.I2(\memory_reg[3][2]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [2]),
.I4(\bresp_cnt_reg[7] [5]),
.I5(\memory_reg[3][5]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_3_n_0 ));
LUT5 #(
.INIT(32'hFFFF22F2))
\memory_reg[3][0]_srl4_i_4
(.I0(\bresp_cnt_reg[7] [5]),
.I1(\memory_reg[3][5]_srl4_n_0 ),
.I2(\memory_reg[3][1]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [1]),
.I4(\memory_reg[3][0]_srl4_i_8_n_0 ),
.O(\memory_reg[3][0]_srl4_i_4_n_0 ));
LUT4 #(
.INIT(16'h4F44))
\memory_reg[3][0]_srl4_i_5
(.I0(\bresp_cnt_reg[7] [6]),
.I1(\memory_reg[3][6]_srl4_n_0 ),
.I2(\memory_reg[3][1]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [1]),
.O(\memory_reg[3][0]_srl4_i_5_n_0 ));
LUT6 #(
.INIT(64'h22F2FFFFFFFF22F2))
\memory_reg[3][0]_srl4_i_6
(.I0(\memory_reg[3][2]_srl4_n_0 ),
.I1(\bresp_cnt_reg[7] [2]),
.I2(\bresp_cnt_reg[7] [6]),
.I3(\memory_reg[3][6]_srl4_n_0 ),
.I4(\bresp_cnt_reg[7] [4]),
.I5(\memory_reg[3][4]_srl4_n_0 ),
.O(\memory_reg[3][0]_srl4_i_6_n_0 ));
LUT4 #(
.INIT(16'h4F44))
\memory_reg[3][0]_srl4_i_7
(.I0(\bresp_cnt_reg[7] [7]),
.I1(\memory_reg[3][7]_srl4_n_0 ),
.I2(\memory_reg[3][0]_srl4_n_0 ),
.I3(\bresp_cnt_reg[7] [0]),
.O(\memory_reg[3][0]_srl4_i_7_n_0 ));
LUT4 #(
.INIT(16'hF444))
\memory_reg[3][0]_srl4_i_8
(.I0(\bresp_cnt_reg[7] [3]),
.I1(\memory_reg[3][3]_srl4_n_0 ),
.I2(\cnt_read_reg[1]_rep_0 ),
.I3(\cnt_read_reg[0]_rep_0 ),
.O(\memory_reg[3][0]_srl4_i_8_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[1]),
.Q(\memory_reg[3][1]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][2]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[2]),
.Q(\memory_reg[3][2]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][3]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[3]),
.Q(\memory_reg[3][3]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][4]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[4]),
.Q(\memory_reg[3][4]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][5]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[5]),
.Q(\memory_reg[3][5]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][6]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[6]),
.Q(\memory_reg[3][6]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][7]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[7]),
.Q(\memory_reg[3][7]_srl4_n_0 ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][8]_srl4
(.A0(cnt_read[0]),
.A1(cnt_read[1]),
.A2(1'b0),
.A3(1'b0),
.CE(b_push),
.CLK(aclk),
.D(in[8]),
.Q(out));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized0
(s_bresp_acc,
mhandshake,
Q,
m_axi_bready,
\skid_buffer_reg[1] ,
in,
m_axi_bresp,
m_axi_bvalid,
mhandshake_r,
shandshake_r,
bresp_push,
aclk,
areset_d1,
D);
output s_bresp_acc;
output mhandshake;
output [1:0]Q;
output m_axi_bready;
output [1:0]\skid_buffer_reg[1] ;
input [1:0]in;
input [1:0]m_axi_bresp;
input m_axi_bvalid;
input mhandshake_r;
input shandshake_r;
input bresp_push;
input aclk;
input areset_d1;
input [0:0]D;
wire [0:0]D;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire bresp_push;
wire \cnt_read[1]_i_1__0_n_0 ;
wire [1:0]in;
wire m_axi_bready;
wire [1:0]m_axi_bresp;
wire m_axi_bvalid;
wire mhandshake;
wire mhandshake_r;
wire s_bresp_acc;
wire shandshake_r;
wire [1:0]\skid_buffer_reg[1] ;
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__0
(.I0(Q[1]),
.I1(Q[0]),
.I2(shandshake_r),
.I3(bresp_push),
.O(\cnt_read[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair104" *)
LUT3 #(
.INIT(8'h08))
m_axi_bready_INST_0
(.I0(Q[1]),
.I1(Q[0]),
.I2(mhandshake_r),
.O(m_axi_bready));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][0]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[1] [0]));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 " *)
SRL16E #(
.INIT(16'h0000))
\memory_reg[3][1]_srl4
(.A0(Q[0]),
.A1(Q[1]),
.A2(1'b0),
.A3(1'b0),
.CE(bresp_push),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[1] [1]));
LUT4 #(
.INIT(16'h2000))
mhandshake_r_i_1
(.I0(m_axi_bvalid),
.I1(mhandshake_r),
.I2(Q[0]),
.I3(Q[1]),
.O(mhandshake));
LUT5 #(
.INIT(32'h2020A220))
\s_bresp_acc[1]_i_2
(.I0(mhandshake),
.I1(in[1]),
.I2(m_axi_bresp[1]),
.I3(m_axi_bresp[0]),
.I4(in[0]),
.O(s_bresp_acc));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized1
(m_axi_rready,
s_ready_i_reg,
\state_reg[1]_rep ,
\cnt_read_reg[4]_0 ,
out,
s_ready_i_reg_0,
si_rs_rready,
m_axi_rvalid,
r_push_r,
Q,
\cnt_read_reg[2]_0 ,
in,
aclk,
areset_d1);
output m_axi_rready;
output s_ready_i_reg;
output \state_reg[1]_rep ;
output \cnt_read_reg[4]_0 ;
output [33:0]out;
input s_ready_i_reg_0;
input si_rs_rready;
input m_axi_rvalid;
input r_push_r;
input [1:0]Q;
input \cnt_read_reg[2]_0 ;
input [33:0]in;
input aclk;
input areset_d1;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [4:0]cnt_read;
wire \cnt_read[0]_i_1__0_n_0 ;
wire \cnt_read[1]_i_1__2_n_0 ;
wire \cnt_read[2]_i_1_n_0 ;
wire \cnt_read[3]_i_1__0_n_0 ;
wire \cnt_read[4]_i_1_n_0 ;
wire \cnt_read[4]_i_2_n_0 ;
wire \cnt_read[4]_i_3_n_0 ;
wire \cnt_read[4]_i_4_n_0 ;
wire \cnt_read[4]_i_5_n_0 ;
wire \cnt_read_reg[0]_rep__0_n_0 ;
wire \cnt_read_reg[0]_rep__1_n_0 ;
wire \cnt_read_reg[0]_rep__2_n_0 ;
wire \cnt_read_reg[0]_rep_n_0 ;
wire \cnt_read_reg[1]_rep__0_n_0 ;
wire \cnt_read_reg[1]_rep__1_n_0 ;
wire \cnt_read_reg[1]_rep__2_n_0 ;
wire \cnt_read_reg[1]_rep_n_0 ;
wire \cnt_read_reg[2]_0 ;
wire \cnt_read_reg[2]_rep__0_n_0 ;
wire \cnt_read_reg[2]_rep__1_n_0 ;
wire \cnt_read_reg[2]_rep__2_n_0 ;
wire \cnt_read_reg[2]_rep_n_0 ;
wire \cnt_read_reg[3]_rep__0_n_0 ;
wire \cnt_read_reg[3]_rep__1_n_0 ;
wire \cnt_read_reg[3]_rep__2_n_0 ;
wire \cnt_read_reg[3]_rep_n_0 ;
wire \cnt_read_reg[4]_0 ;
wire \cnt_read_reg[4]_rep__0_n_0 ;
wire \cnt_read_reg[4]_rep__1_n_0 ;
wire \cnt_read_reg[4]_rep__2_n_0 ;
wire \cnt_read_reg[4]_rep_n_0 ;
wire [33:0]in;
wire m_axi_rready;
wire m_axi_rvalid;
wire [33:0]out;
wire r_push_r;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire si_rs_rready;
wire \state_reg[1]_rep ;
wire wr_en0;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ;
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__0
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(s_ready_i_reg_0),
.I2(wr_en0),
.O(\cnt_read[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT4 #(
.INIT(16'hA69A))
\cnt_read[1]_i_1__2
(.I0(\cnt_read_reg[1]_rep__2_n_0 ),
.I1(wr_en0),
.I2(s_ready_i_reg_0),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[1]_i_1__2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT5 #(
.INIT(32'hAA6AA9AA))
\cnt_read[2]_i_1
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(wr_en0),
.I3(s_ready_i_reg_0),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(\cnt_read[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hAAAAAAA96AAAAAAA))
\cnt_read[3]_i_1__0
(.I0(\cnt_read_reg[3]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[0]_rep__2_n_0 ),
.I4(wr_en0),
.I5(s_ready_i_reg_0),
.O(\cnt_read[3]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hAA55AAA6A6AAA6AA))
\cnt_read[4]_i_1
(.I0(\cnt_read_reg[4]_rep__2_n_0 ),
.I1(\cnt_read[4]_i_2_n_0 ),
.I2(\cnt_read[4]_i_3_n_0 ),
.I3(\cnt_read[4]_i_4_n_0 ),
.I4(\cnt_read[4]_i_5_n_0 ),
.I5(\cnt_read_reg[3]_rep__2_n_0 ),
.O(\cnt_read[4]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_2
(.I0(\cnt_read_reg[2]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.O(\cnt_read[4]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT4 #(
.INIT(16'hFFFB))
\cnt_read[4]_i_3
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(si_rs_rready),
.I2(s_ready_i_reg),
.I3(wr_en0),
.O(\cnt_read[4]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h4F))
\cnt_read[4]_i_4
(.I0(s_ready_i_reg),
.I1(si_rs_rready),
.I2(wr_en0),
.O(\cnt_read[4]_i_4_n_0 ));
LUT3 #(
.INIT(8'h04))
\cnt_read[4]_i_4__0
(.I0(s_ready_i_reg),
.I1(si_rs_rready),
.I2(r_push_r),
.O(\cnt_read_reg[4]_0 ));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h80))
\cnt_read[4]_i_5
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[1]_rep__2_n_0 ),
.I2(\cnt_read_reg[2]_rep__2_n_0 ),
.O(\cnt_read[4]_i_5_n_0 ));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[0]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__0_n_0 ),
.Q(\cnt_read_reg[0]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[1]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__2_n_0 ),
.Q(\cnt_read_reg[1]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[2]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1_n_0 ),
.Q(\cnt_read_reg[2]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(cnt_read[3]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[3]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1__0_n_0 ),
.Q(\cnt_read_reg[3]_rep__2_n_0 ),
.S(areset_d1));
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(cnt_read[4]),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__0
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__0_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__1
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__1_n_0 ),
.S(areset_d1));
(* IS_FANOUT_CONSTRAINED = "1" *)
(* KEEP = "yes" *)
(* ORIG_CELL_NAME = "cnt_read_reg[4]" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]_rep__2
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1_n_0 ),
.Q(\cnt_read_reg[4]_rep__2_n_0 ),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'hF77F777F))
m_axi_rready_INST_0
(.I0(\cnt_read_reg[3]_rep__2_n_0 ),
.I1(\cnt_read_reg[4]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[2]_rep__2_n_0 ),
.I4(\cnt_read_reg[0]_rep__2_n_0 ),
.O(m_axi_rready));
LUT6 #(
.INIT(64'hFF80808080808080))
m_valid_i_i_2
(.I0(\cnt_read_reg[4]_rep__2_n_0 ),
.I1(\cnt_read_reg[3]_rep__2_n_0 ),
.I2(\cnt_read[4]_i_5_n_0 ),
.I3(Q[1]),
.I4(Q[0]),
.I5(\cnt_read_reg[2]_0 ),
.O(s_ready_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[0]),
.Q(out[0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hAA2A2AAA2A2A2AAA))
\memory_reg[31][0]_srl32_i_1
(.I0(m_axi_rvalid),
.I1(\cnt_read_reg[3]_rep__2_n_0 ),
.I2(\cnt_read_reg[4]_rep__2_n_0 ),
.I3(\cnt_read_reg[1]_rep__2_n_0 ),
.I4(\cnt_read_reg[2]_rep__2_n_0 ),
.I5(\cnt_read_reg[0]_rep__2_n_0 ),
.O(wr_en0));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][10]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[10]),
.Q(out[10]),
.Q31(\NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][11]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[11]),
.Q(out[11]),
.Q31(\NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][12]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[12]),
.Q(out[12]),
.Q31(\NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][13]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[13]),
.Q(out[13]),
.Q31(\NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][14]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[14]),
.Q(out[14]),
.Q31(\NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][15]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[15]),
.Q(out[15]),
.Q31(\NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][16]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[16]),
.Q(out[16]),
.Q31(\NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][17]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[17]),
.Q(out[17]),
.Q31(\NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][18]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[18]),
.Q(out[18]),
.Q31(\NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][19]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[19]),
.Q(out[19]),
.Q31(\NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[1]),
.Q(out[1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][20]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[20]),
.Q(out[20]),
.Q31(\NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][21]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[21]),
.Q(out[21]),
.Q31(\NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][22]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[22]),
.Q(out[22]),
.Q31(\NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][23]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[23]),
.Q(out[23]),
.Q31(\NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][24]_srl32
(.A({\cnt_read_reg[4]_rep_n_0 ,\cnt_read_reg[3]_rep_n_0 ,\cnt_read_reg[2]_rep_n_0 ,\cnt_read_reg[1]_rep_n_0 ,\cnt_read_reg[0]_rep_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[24]),
.Q(out[24]),
.Q31(\NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][25]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[25]),
.Q(out[25]),
.Q31(\NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][26]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[26]),
.Q(out[26]),
.Q31(\NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][27]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[27]),
.Q(out[27]),
.Q31(\NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][28]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[28]),
.Q(out[28]),
.Q31(\NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][29]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[29]),
.Q(out[29]),
.Q31(\NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][2]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[2]),
.Q(out[2]),
.Q31(\NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][30]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[30]),
.Q(out[30]),
.Q31(\NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][31]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[31]),
.Q(out[31]),
.Q31(\NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][32]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[32]),
.Q(out[32]),
.Q31(\NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][33]_srl32
(.A(cnt_read),
.CE(wr_en0),
.CLK(aclk),
.D(in[33]),
.Q(out[33]),
.Q31(\NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][3]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[3]),
.Q(out[3]),
.Q31(\NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][4]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[4]),
.Q(out[4]),
.Q31(\NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][5]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[5]),
.Q(out[5]),
.Q31(\NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][6]_srl32
(.A({\cnt_read_reg[4]_rep__1_n_0 ,\cnt_read_reg[3]_rep__1_n_0 ,\cnt_read_reg[2]_rep__1_n_0 ,\cnt_read_reg[1]_rep__1_n_0 ,\cnt_read_reg[0]_rep__1_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[6]),
.Q(out[6]),
.Q31(\NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][7]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[7]),
.Q(out[7]),
.Q31(\NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][8]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[8]),
.Q(out[8]),
.Q31(\NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][9]_srl32
(.A({\cnt_read_reg[4]_rep__0_n_0 ,\cnt_read_reg[3]_rep__0_n_0 ,\cnt_read_reg[2]_rep__0_n_0 ,\cnt_read_reg[1]_rep__0_n_0 ,\cnt_read_reg[0]_rep__0_n_0 }),
.CE(wr_en0),
.CLK(aclk),
.D(in[9]),
.Q(out[9]),
.Q31(\NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED ));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT5 #(
.INIT(32'h7C000000))
\state[1]_i_4
(.I0(\cnt_read_reg[0]_rep__2_n_0 ),
.I1(\cnt_read_reg[2]_rep__2_n_0 ),
.I2(\cnt_read_reg[1]_rep__2_n_0 ),
.I3(\cnt_read_reg[4]_rep__2_n_0 ),
.I4(\cnt_read_reg[3]_rep__2_n_0 ),
.O(\state_reg[1]_rep ));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_simple_fifo" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_simple_fifo__parameterized2
(\state_reg[1]_rep ,
Q,
s_ready_i_reg,
\skid_buffer_reg[35] ,
\cnt_read_reg[0]_rep__2 ,
r_push_r,
s_ready_i_reg_0,
s_ready_i_reg_1,
\cnt_read_reg[4]_rep__2 ,
si_rs_rready,
in,
aclk,
areset_d1);
output \state_reg[1]_rep ;
output [1:0]Q;
output s_ready_i_reg;
output [1:0]\skid_buffer_reg[35] ;
input \cnt_read_reg[0]_rep__2 ;
input r_push_r;
input s_ready_i_reg_0;
input s_ready_i_reg_1;
input \cnt_read_reg[4]_rep__2 ;
input si_rs_rready;
input [1:0]in;
input aclk;
input areset_d1;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [2:0]cnt_read;
wire \cnt_read[0]_i_1__1_n_0 ;
wire \cnt_read[1]_i_1__1_n_0 ;
wire \cnt_read[2]_i_1__0_n_0 ;
wire \cnt_read[3]_i_1_n_0 ;
wire \cnt_read[4]_i_1__0_n_0 ;
wire \cnt_read[4]_i_2__0_n_0 ;
wire \cnt_read[4]_i_3__0_n_0 ;
wire \cnt_read_reg[0]_rep__2 ;
wire \cnt_read_reg[4]_rep__2 ;
wire [1:0]in;
wire r_push_r;
wire s_ready_i_reg;
wire s_ready_i_reg_0;
wire s_ready_i_reg_1;
wire si_rs_rready;
wire [1:0]\skid_buffer_reg[35] ;
wire \state_reg[1]_rep ;
wire \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ;
wire \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h96))
\cnt_read[0]_i_1__1
(.I0(r_push_r),
.I1(s_ready_i_reg_0),
.I2(cnt_read[0]),
.O(\cnt_read[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT4 #(
.INIT(16'hDB24))
\cnt_read[1]_i_1__1
(.I0(cnt_read[0]),
.I1(s_ready_i_reg_0),
.I2(r_push_r),
.I3(cnt_read[1]),
.O(\cnt_read[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT5 #(
.INIT(32'hA6AAAA9A))
\cnt_read[2]_i_1__0
(.I0(cnt_read[2]),
.I1(r_push_r),
.I2(s_ready_i_reg_0),
.I3(cnt_read[0]),
.I4(cnt_read[1]),
.O(\cnt_read[2]_i_1__0_n_0 ));
LUT6 #(
.INIT(64'hBFFFFFFD40000002))
\cnt_read[3]_i_1
(.I0(s_ready_i_reg_0),
.I1(r_push_r),
.I2(cnt_read[1]),
.I3(cnt_read[0]),
.I4(cnt_read[2]),
.I5(Q[0]),
.O(\cnt_read[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'h9AA69AAA9AAA9AAA))
\cnt_read[4]_i_1__0
(.I0(Q[1]),
.I1(\cnt_read[4]_i_2__0_n_0 ),
.I2(Q[0]),
.I3(cnt_read[2]),
.I4(\cnt_read[4]_i_3__0_n_0 ),
.I5(s_ready_i_reg_1),
.O(\cnt_read[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT5 #(
.INIT(32'h75FFFFFF))
\cnt_read[4]_i_2__0
(.I0(r_push_r),
.I1(\cnt_read_reg[4]_rep__2 ),
.I2(si_rs_rready),
.I3(cnt_read[1]),
.I4(cnt_read[0]),
.O(\cnt_read[4]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT2 #(
.INIT(4'h1))
\cnt_read[4]_i_3__0
(.I0(cnt_read[1]),
.I1(cnt_read[0]),
.O(\cnt_read[4]_i_3__0_n_0 ));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[0]_i_1__1_n_0 ),
.Q(cnt_read[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[1]_i_1__1_n_0 ),
.Q(cnt_read[1]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[2]_i_1__0_n_0 ),
.Q(cnt_read[2]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[3]_i_1_n_0 ),
.Q(Q[0]),
.S(areset_d1));
(* KEEP = "yes" *)
FDSE #(
.INIT(1'b1))
\cnt_read_reg[4]
(.C(aclk),
.CE(1'b1),
.D(\cnt_read[4]_i_1__0_n_0 ),
.Q(Q[1]),
.S(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'h80))
m_valid_i_i_3
(.I0(cnt_read[2]),
.I1(cnt_read[0]),
.I2(cnt_read[1]),
.O(s_ready_i_reg));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][0]_srl32
(.A({Q,cnt_read}),
.CE(r_push_r),
.CLK(aclk),
.D(in[0]),
.Q(\skid_buffer_reg[35] [0]),
.Q31(\NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED ));
(* srl_bus_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] " *)
(* srl_name = "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 " *)
SRLC32E #(
.INIT(32'h00000000))
\memory_reg[31][1]_srl32
(.A({Q,cnt_read}),
.CE(r_push_r),
.CLK(aclk),
.D(in[1]),
.Q(\skid_buffer_reg[35] [1]),
.Q31(\NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED ));
LUT6 #(
.INIT(64'hBFEEAAAAAAAAAAAA))
\state[1]_i_2
(.I0(\cnt_read_reg[0]_rep__2 ),
.I1(cnt_read[2]),
.I2(cnt_read[0]),
.I3(cnt_read[1]),
.I4(Q[0]),
.I5(Q[1]),
.O(\state_reg[1]_rep ));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wr_cmd_fsm
(Q,
D,
\wrap_cnt_r_reg[0] ,
axaddr_offset,
\wrap_second_len_r_reg[3] ,
E,
\axlen_cnt_reg[0] ,
s_axburst_eq0_reg,
wrap_next_pending,
sel_first_i,
incr_next_pending,
s_axburst_eq1_reg,
next,
\axaddr_wrap_reg[0] ,
sel_first_reg,
sel_first_reg_0,
\m_payload_i_reg[0] ,
b_push,
m_axi_awvalid,
s_axburst_eq1_reg_0,
\cnt_read_reg[1]_rep ,
\cnt_read_reg[0]_rep ,
m_axi_awready,
si_rs_awvalid,
\wrap_second_len_r_reg[3]_0 ,
\m_payload_i_reg[35] ,
\m_payload_i_reg[46] ,
\axaddr_offset_r_reg[3] ,
\m_payload_i_reg[35]_0 ,
\m_payload_i_reg[3] ,
\m_payload_i_reg[47] ,
\axlen_cnt_reg[0]_0 ,
\axlen_cnt_reg[3] ,
\m_payload_i_reg[48] ,
next_pending_r_reg,
sel_first,
areset_d1,
sel_first_0,
sel_first_reg_1,
\m_payload_i_reg[46]_0 ,
\axlen_cnt_reg[2] ,
next_pending_r_reg_0,
\m_payload_i_reg[6] ,
aclk);
output [1:0]Q;
output [2:0]D;
output \wrap_cnt_r_reg[0] ;
output [1:0]axaddr_offset;
output [3:0]\wrap_second_len_r_reg[3] ;
output [0:0]E;
output [0:0]\axlen_cnt_reg[0] ;
output s_axburst_eq0_reg;
output wrap_next_pending;
output sel_first_i;
output incr_next_pending;
output s_axburst_eq1_reg;
output next;
output [0:0]\axaddr_wrap_reg[0] ;
output sel_first_reg;
output sel_first_reg_0;
output [0:0]\m_payload_i_reg[0] ;
output b_push;
output m_axi_awvalid;
input s_axburst_eq1_reg_0;
input \cnt_read_reg[1]_rep ;
input \cnt_read_reg[0]_rep ;
input m_axi_awready;
input si_rs_awvalid;
input [3:0]\wrap_second_len_r_reg[3]_0 ;
input \m_payload_i_reg[35] ;
input [0:0]\m_payload_i_reg[46] ;
input [1:0]\axaddr_offset_r_reg[3] ;
input \m_payload_i_reg[35]_0 ;
input \m_payload_i_reg[3] ;
input [2:0]\m_payload_i_reg[47] ;
input [0:0]\axlen_cnt_reg[0]_0 ;
input \axlen_cnt_reg[3] ;
input \m_payload_i_reg[48] ;
input next_pending_r_reg;
input sel_first;
input areset_d1;
input sel_first_0;
input sel_first_reg_1;
input \m_payload_i_reg[46]_0 ;
input \axlen_cnt_reg[2] ;
input next_pending_r_reg_0;
input \m_payload_i_reg[6] ;
input aclk;
wire [2:0]D;
wire [0:0]E;
wire [1:0]Q;
wire aclk;
wire areset_d1;
wire [1:0]axaddr_offset;
wire [1:0]\axaddr_offset_r_reg[3] ;
wire [0:0]\axaddr_wrap_reg[0] ;
wire [0:0]\axlen_cnt_reg[0] ;
wire [0:0]\axlen_cnt_reg[0]_0 ;
wire \axlen_cnt_reg[2] ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire \cnt_read_reg[0]_rep ;
wire \cnt_read_reg[1]_rep ;
wire incr_next_pending;
wire m_axi_awready;
wire m_axi_awvalid;
wire [0:0]\m_payload_i_reg[0] ;
wire \m_payload_i_reg[35] ;
wire \m_payload_i_reg[35]_0 ;
wire \m_payload_i_reg[3] ;
wire [0:0]\m_payload_i_reg[46] ;
wire \m_payload_i_reg[46]_0 ;
wire [2:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[48] ;
wire \m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [0:0]next_state;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire s_axburst_eq1_reg_0;
wire sel_first;
wire sel_first_0;
wire sel_first_i;
wire sel_first_reg;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire si_rs_awvalid;
wire \state[0]_i_2_n_0 ;
wire \state[1]_i_1__0_n_0 ;
wire \wrap_cnt_r[3]_i_2_n_0 ;
wire \wrap_cnt_r_reg[0] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3] ;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
LUT6 #(
.INIT(64'hAAAAAAAAAAC0AAAA))
\axaddr_offset_r[0]_i_1
(.I0(\axaddr_offset_r_reg[3] [0]),
.I1(\m_payload_i_reg[3] ),
.I2(\m_payload_i_reg[47] [1]),
.I3(Q[0]),
.I4(si_rs_awvalid),
.I5(Q[1]),
.O(axaddr_offset[0]));
LUT6 #(
.INIT(64'hAAAAACAAAAAAA0AA))
\axaddr_offset_r[3]_i_1
(.I0(\axaddr_offset_r_reg[3] [1]),
.I1(\m_payload_i_reg[47] [2]),
.I2(Q[0]),
.I3(si_rs_awvalid),
.I4(Q[1]),
.I5(\m_payload_i_reg[6] ),
.O(axaddr_offset[1]));
LUT6 #(
.INIT(64'h0400FFFF04000400))
\axlen_cnt[0]_i_1__0
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(\m_payload_i_reg[47] [1]),
.I4(\axlen_cnt_reg[0]_0 ),
.I5(\axlen_cnt_reg[3] ),
.O(\axlen_cnt_reg[0] ));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT4 #(
.INIT(16'hFF04))
\axlen_cnt[7]_i_1
(.I0(Q[0]),
.I1(si_rs_awvalid),
.I2(Q[1]),
.I3(next),
.O(\axaddr_wrap_reg[0] ));
LUT2 #(
.INIT(4'h2))
m_axi_awvalid_INST_0
(.I0(Q[0]),
.I1(Q[1]),
.O(m_axi_awvalid));
LUT2 #(
.INIT(4'hB))
\m_payload_i[31]_i_1
(.I0(b_push),
.I1(si_rs_awvalid),
.O(\m_payload_i_reg[0] ));
LUT6 #(
.INIT(64'h88008888A800A8A8))
\memory_reg[3][0]_srl4_i_1
(.I0(Q[0]),
.I1(Q[1]),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep ),
.I4(\cnt_read_reg[1]_rep ),
.I5(s_axburst_eq1_reg_0),
.O(b_push));
LUT5 #(
.INIT(32'hB8BBB888))
next_pending_r_i_1
(.I0(\m_payload_i_reg[48] ),
.I1(E),
.I2(\axlen_cnt_reg[3] ),
.I3(next),
.I4(next_pending_r_reg),
.O(incr_next_pending));
LUT5 #(
.INIT(32'h8BBB8B88))
next_pending_r_i_1__0
(.I0(\m_payload_i_reg[46]_0 ),
.I1(E),
.I2(\axlen_cnt_reg[2] ),
.I3(next),
.I4(next_pending_r_reg_0),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hF3F35100FFFF0000))
next_pending_r_i_4
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep ),
.I2(\cnt_read_reg[0]_rep ),
.I3(m_axi_awready),
.I4(Q[1]),
.I5(Q[0]),
.O(next));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair92" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [0]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1
(.I0(next),
.I1(sel_first),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg));
LUT6 #(
.INIT(64'hFFFFFFFF44444F44))
sel_first_i_1__0
(.I0(next),
.I1(sel_first_0),
.I2(Q[1]),
.I3(si_rs_awvalid),
.I4(Q[0]),
.I5(areset_d1),
.O(sel_first_reg_0));
LUT6 #(
.INIT(64'hFF04FFFFFF04FF04))
sel_first_i_1__1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.I3(areset_d1),
.I4(next),
.I5(sel_first_reg_1),
.O(sel_first_i));
LUT6 #(
.INIT(64'h5D555D55FFFFDDDD))
\state[0]_i_1
(.I0(\state[0]_i_2_n_0 ),
.I1(Q[1]),
.I2(\cnt_read_reg[0]_rep ),
.I3(\cnt_read_reg[1]_rep ),
.I4(si_rs_awvalid),
.I5(Q[0]),
.O(next_state));
LUT6 #(
.INIT(64'hFBFBFBFBFBBBFBFB))
\state[0]_i_2
(.I0(Q[1]),
.I1(Q[0]),
.I2(m_axi_awready),
.I3(\cnt_read_reg[0]_rep ),
.I4(\cnt_read_reg[1]_rep ),
.I5(s_axburst_eq1_reg_0),
.O(\state[0]_i_2_n_0 ));
LUT6 #(
.INIT(64'h0C0CAE0000000000))
\state[1]_i_1__0
(.I0(s_axburst_eq1_reg_0),
.I1(\cnt_read_reg[1]_rep ),
.I2(\cnt_read_reg[0]_rep ),
.I3(m_axi_awready),
.I4(Q[1]),
.I5(Q[0]),
.O(\state[1]_i_1__0_n_0 ));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\state_reg[0]
(.C(aclk),
.CE(1'b1),
.D(next_state),
.Q(Q[0]),
.R(areset_d1));
(* KEEP = "yes" *)
FDRE #(
.INIT(1'b0))
\state_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\state[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(areset_d1));
(* SOFT_HLUTNM = "soft_lutpair93" *)
LUT3 #(
.INIT(8'h04))
\wrap_boundary_axaddr_r[11]_i_1
(.I0(Q[1]),
.I1(si_rs_awvalid),
.I2(Q[0]),
.O(E));
LUT6 #(
.INIT(64'hAA8A5575AA8A5545))
\wrap_cnt_r[0]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(D[0]));
LUT6 #(
.INIT(64'hAAA6AA56AAAAAAAA))
\wrap_cnt_r[2]_i_1
(.I0(\wrap_second_len_r_reg[3] [2]),
.I1(\wrap_second_len_r_reg[3]_0 [0]),
.I2(E),
.I3(\wrap_cnt_r_reg[0] ),
.I4(axaddr_offset[0]),
.I5(\wrap_second_len_r_reg[3] [1]),
.O(D[1]));
LUT4 #(
.INIT(16'hA6AA))
\wrap_cnt_r[3]_i_1
(.I0(\wrap_second_len_r_reg[3] [3]),
.I1(\wrap_second_len_r_reg[3] [1]),
.I2(\wrap_cnt_r[3]_i_2_n_0 ),
.I3(\wrap_second_len_r_reg[3] [2]),
.O(D[2]));
LUT6 #(
.INIT(64'hD1D1D1D1D1D1DFD1))
\wrap_cnt_r[3]_i_2
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(axaddr_offset[1]),
.O(\wrap_cnt_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAA8AAA8AAA8AAABA))
\wrap_second_len_r[0]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(Q[0]),
.I2(si_rs_awvalid),
.I3(Q[1]),
.I4(\wrap_cnt_r_reg[0] ),
.I5(axaddr_offset[0]),
.O(\wrap_second_len_r_reg[3] [0]));
LUT6 #(
.INIT(64'h0000000004000404))
\wrap_second_len_r[0]_i_2
(.I0(axaddr_offset[0]),
.I1(\m_payload_i_reg[35] ),
.I2(\m_payload_i_reg[46] ),
.I3(E),
.I4(\axaddr_offset_r_reg[3] [1]),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_cnt_r_reg[0] ));
LUT6 #(
.INIT(64'h0FE0FFFF0FE00000))
\wrap_second_len_r[1]_i_1
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_second_len_r_reg[3] [1]));
LUT6 #(
.INIT(64'hCC2CFFFFCC2C0000))
\wrap_second_len_r[2]_i_1
(.I0(axaddr_offset[1]),
.I1(\m_payload_i_reg[46] ),
.I2(\m_payload_i_reg[35] ),
.I3(axaddr_offset[0]),
.I4(E),
.I5(\wrap_second_len_r_reg[3]_0 [2]),
.O(\wrap_second_len_r_reg[3] [2]));
LUT6 #(
.INIT(64'hFFFFF4FF44444444))
\wrap_second_len_r[3]_i_1
(.I0(E),
.I1(\wrap_second_len_r_reg[3]_0 [3]),
.I2(axaddr_offset[0]),
.I3(\m_payload_i_reg[35] ),
.I4(\m_payload_i_reg[46] ),
.I5(\m_payload_i_reg[35]_0 ),
.O(\wrap_second_len_r_reg[3] [3]));
endmodule
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd
(next_pending_r_reg_0,
sel_first_reg_0,
next_pending_r_reg_1,
m_axi_awaddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
wrap_next_pending,
aclk,
sel_first_reg_1,
E,
Q,
next,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
\state_reg[0] ,
D,
\m_payload_i_reg[6] );
output next_pending_r_reg_0;
output sel_first_reg_0;
output next_pending_r_reg_1;
output [11:0]m_axi_awaddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input wrap_next_pending;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]Q;
input next;
input sel_first_reg_2;
input [11:0]\axaddr_incr_reg[11] ;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]\state_reg[0] ;
input [2:0]D;
input [6:0]\m_payload_i_reg[6] ;
wire [2:0]D;
wire [0:0]E;
wire [18:0]Q;
wire aclk;
wire [11:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire [11:0]axaddr_wrap;
wire [11:0]axaddr_wrap0;
wire \axaddr_wrap[0]_i_1_n_0 ;
wire \axaddr_wrap[10]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_1_n_0 ;
wire \axaddr_wrap[11]_i_2_n_0 ;
wire \axaddr_wrap[11]_i_4_n_0 ;
wire \axaddr_wrap[1]_i_1_n_0 ;
wire \axaddr_wrap[2]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_1_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1_n_0 ;
wire \axaddr_wrap[5]_i_1_n_0 ;
wire \axaddr_wrap[6]_i_1_n_0 ;
wire \axaddr_wrap[7]_i_1_n_0 ;
wire \axaddr_wrap[8]_i_1_n_0 ;
wire \axaddr_wrap[9]_i_1_n_0 ;
wire \axaddr_wrap_reg[11]_i_3_n_1 ;
wire \axaddr_wrap_reg[11]_i_3_n_2 ;
wire \axaddr_wrap_reg[11]_i_3_n_3 ;
wire \axaddr_wrap_reg[3]_i_2_n_0 ;
wire \axaddr_wrap_reg[3]_i_2_n_1 ;
wire \axaddr_wrap_reg[3]_i_2_n_2 ;
wire \axaddr_wrap_reg[3]_i_2_n_3 ;
wire \axaddr_wrap_reg[7]_i_2_n_0 ;
wire \axaddr_wrap_reg[7]_i_2_n_1 ;
wire \axaddr_wrap_reg[7]_i_2_n_2 ;
wire \axaddr_wrap_reg[7]_i_2_n_3 ;
wire \axlen_cnt[0]_i_1_n_0 ;
wire \axlen_cnt[1]_i_1_n_0 ;
wire \axlen_cnt[2]_i_1_n_0 ;
wire \axlen_cnt[3]_i_1_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire [11:0]m_axi_awaddr;
wire \m_payload_i_reg[35] ;
wire [6:0]\m_payload_i_reg[6] ;
wire next;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire [0:0]\state_reg[0] ;
wire [11:0]wrap_boundary_axaddr_r;
wire [1:1]wrap_cnt;
wire [3:0]wrap_cnt_r;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1
(.I0(wrap_boundary_axaddr_r[0]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[0]),
.I3(next),
.I4(Q[0]),
.O(\axaddr_wrap[0]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1
(.I0(wrap_boundary_axaddr_r[10]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[10]),
.I3(next),
.I4(Q[10]),
.O(\axaddr_wrap[10]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1
(.I0(wrap_boundary_axaddr_r[11]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[11]),
.I3(next),
.I4(Q[11]),
.O(\axaddr_wrap[11]_i_1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2
(.I0(\axaddr_wrap[11]_i_4_n_0 ),
.I1(wrap_cnt_r[3]),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4
(.I0(wrap_cnt_r[0]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(wrap_cnt_r[1]),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(wrap_cnt_r[2]),
.O(\axaddr_wrap[11]_i_4_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1
(.I0(wrap_boundary_axaddr_r[1]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[1]),
.I3(next),
.I4(Q[1]),
.O(\axaddr_wrap[1]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1
(.I0(wrap_boundary_axaddr_r[2]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[2]),
.I3(next),
.I4(Q[2]),
.O(\axaddr_wrap[2]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1
(.I0(wrap_boundary_axaddr_r[3]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[3]),
.I3(next),
.I4(Q[3]),
.O(\axaddr_wrap[3]_i_1_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(axaddr_wrap[3]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(axaddr_wrap[2]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(axaddr_wrap[1]),
.I1(Q[13]),
.I2(Q[12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(axaddr_wrap[0]),
.I1(Q[12]),
.I2(Q[13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1
(.I0(wrap_boundary_axaddr_r[4]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[4]),
.I3(next),
.I4(Q[4]),
.O(\axaddr_wrap[4]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1
(.I0(wrap_boundary_axaddr_r[5]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[5]),
.I3(next),
.I4(Q[5]),
.O(\axaddr_wrap[5]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1
(.I0(wrap_boundary_axaddr_r[6]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[6]),
.I3(next),
.I4(Q[6]),
.O(\axaddr_wrap[6]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1
(.I0(wrap_boundary_axaddr_r[7]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[7]),
.I3(next),
.I4(Q[7]),
.O(\axaddr_wrap[7]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1
(.I0(wrap_boundary_axaddr_r[8]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[8]),
.I3(next),
.I4(Q[8]),
.O(\axaddr_wrap[8]_i_1_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1
(.I0(wrap_boundary_axaddr_r[9]),
.I1(\axaddr_wrap[11]_i_2_n_0 ),
.I2(axaddr_wrap0[9]),
.I3(next),
.I4(Q[9]),
.O(\axaddr_wrap[9]_i_1_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[0]_i_1_n_0 ),
.Q(axaddr_wrap[0]),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[10]_i_1_n_0 ),
.Q(axaddr_wrap[10]),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[11]_i_1_n_0 ),
.Q(axaddr_wrap[11]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3
(.CI(\axaddr_wrap_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3_n_1 ,\axaddr_wrap_reg[11]_i_3_n_2 ,\axaddr_wrap_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[11:8]),
.S(axaddr_wrap[11:8]));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[1]_i_1_n_0 ),
.Q(axaddr_wrap[1]),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[2]_i_1_n_0 ),
.Q(axaddr_wrap[2]),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[3]_i_1_n_0 ),
.Q(axaddr_wrap[3]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2_n_0 ,\axaddr_wrap_reg[3]_i_2_n_1 ,\axaddr_wrap_reg[3]_i_2_n_2 ,\axaddr_wrap_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(axaddr_wrap[3:0]),
.O(axaddr_wrap0[3:0]),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[4]_i_1_n_0 ),
.Q(axaddr_wrap[4]),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[5]_i_1_n_0 ),
.Q(axaddr_wrap[5]),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[6]_i_1_n_0 ),
.Q(axaddr_wrap[6]),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[7]_i_1_n_0 ),
.Q(axaddr_wrap[7]),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2
(.CI(\axaddr_wrap_reg[3]_i_2_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2_n_0 ,\axaddr_wrap_reg[7]_i_2_n_1 ,\axaddr_wrap_reg[7]_i_2_n_2 ,\axaddr_wrap_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_wrap0[7:4]),
.S(axaddr_wrap[7:4]));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[8]_i_1_n_0 ),
.Q(axaddr_wrap[8]),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axaddr_wrap[9]_i_1_n_0 ),
.Q(axaddr_wrap[9]),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1
(.I0(Q[15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[1] ),
.I5(\axlen_cnt_reg_n_0_[2] ),
.O(\axlen_cnt[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(Q[16]),
.O(\axlen_cnt[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(Q[17]),
.O(\axlen_cnt[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(Q[18]),
.O(\axlen_cnt[3]_i_1_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[0]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[1]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[2]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(\state_reg[0] ),
.D(\axlen_cnt[3]_i_1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[0]),
.I2(Q[14]),
.I3(Q[0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_awaddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[10]),
.I2(Q[14]),
.I3(Q[10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_awaddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[11]),
.I2(Q[14]),
.I3(Q[11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [11]),
.O(m_axi_awaddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[1]),
.I2(Q[14]),
.I3(Q[1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_awaddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[2]),
.I2(Q[14]),
.I3(Q[2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_awaddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[3]),
.I2(Q[14]),
.I3(Q[3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_awaddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[4]),
.I2(Q[14]),
.I3(Q[4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_awaddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[5]),
.I2(Q[14]),
.I3(Q[5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_awaddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[6]),
.I2(Q[14]),
.I3(Q[6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_awaddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[7]),
.I2(Q[14]),
.I3(Q[7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_awaddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[8]),
.I2(Q[14]),
.I3(Q[8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_awaddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_awaddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(axaddr_wrap[9]),
.I2(Q[14]),
.I3(Q[9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_awaddr[9]));
(* SOFT_HLUTNM = "soft_lutpair101" *)
LUT3 #(
.INIT(8'h01))
next_pending_r_i_3
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[1] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(next_pending_r_reg_1));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_0),
.R(1'b0));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(wrap_boundary_axaddr_r[0]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(Q[10]),
.Q(wrap_boundary_axaddr_r[10]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(Q[11]),
.Q(wrap_boundary_axaddr_r[11]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(wrap_boundary_axaddr_r[1]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(wrap_boundary_axaddr_r[2]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(wrap_boundary_axaddr_r[3]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(wrap_boundary_axaddr_r[4]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(wrap_boundary_axaddr_r[5]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(wrap_boundary_axaddr_r[6]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(Q[7]),
.Q(wrap_boundary_axaddr_r[7]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(Q[8]),
.Q(wrap_boundary_axaddr_r[8]),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(Q[9]),
.Q(wrap_boundary_axaddr_r[9]),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(wrap_cnt));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(D[0]),
.Q(wrap_cnt_r[0]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(wrap_cnt),
.Q(wrap_cnt_r[1]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(D[1]),
.Q(wrap_cnt_r[2]),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(D[2]),
.Q(wrap_cnt_r[3]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_protocol_converter_v2_1_14_b2s_wrap_cmd" *)
module DemoInterconnect_auto_pc_0_axi_protocol_converter_v2_1_14_b2s_wrap_cmd_3
(sel_first_reg_0,
s_axburst_eq0_reg,
s_axburst_eq1_reg,
m_axi_araddr,
\wrap_second_len_r_reg[3]_0 ,
\axaddr_offset_r_reg[3]_0 ,
aclk,
sel_first_reg_1,
E,
\m_payload_i_reg[47] ,
\state_reg[1] ,
si_rs_arvalid,
sel_first_i,
incr_next_pending,
\state_reg[1]_rep ,
\m_payload_i_reg[47]_0 ,
sel_first_reg_2,
\axaddr_incr_reg[11] ,
\axaddr_offset_r_reg[3]_1 ,
\m_payload_i_reg[35] ,
\axaddr_offset_r_reg[3]_2 ,
\wrap_second_len_r_reg[3]_1 ,
m_valid_i_reg,
\wrap_second_len_r_reg[3]_2 ,
\m_payload_i_reg[6] );
output sel_first_reg_0;
output s_axburst_eq0_reg;
output s_axburst_eq1_reg;
output [11:0]m_axi_araddr;
output [3:0]\wrap_second_len_r_reg[3]_0 ;
output [3:0]\axaddr_offset_r_reg[3]_0 ;
input aclk;
input sel_first_reg_1;
input [0:0]E;
input [18:0]\m_payload_i_reg[47] ;
input [1:0]\state_reg[1] ;
input si_rs_arvalid;
input sel_first_i;
input incr_next_pending;
input \state_reg[1]_rep ;
input \m_payload_i_reg[47]_0 ;
input sel_first_reg_2;
input [11:0]\axaddr_incr_reg[11] ;
input \axaddr_offset_r_reg[3]_1 ;
input \m_payload_i_reg[35] ;
input [3:0]\axaddr_offset_r_reg[3]_2 ;
input [3:0]\wrap_second_len_r_reg[3]_1 ;
input [0:0]m_valid_i_reg;
input [2:0]\wrap_second_len_r_reg[3]_2 ;
input [6:0]\m_payload_i_reg[6] ;
wire [0:0]E;
wire aclk;
wire [11:0]\axaddr_incr_reg[11] ;
wire [3:0]\axaddr_offset_r_reg[3]_0 ;
wire \axaddr_offset_r_reg[3]_1 ;
wire [3:0]\axaddr_offset_r_reg[3]_2 ;
wire \axaddr_wrap[0]_i_1__0_n_0 ;
wire \axaddr_wrap[10]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_1__0_n_0 ;
wire \axaddr_wrap[11]_i_2__0_n_0 ;
wire \axaddr_wrap[11]_i_4__0_n_0 ;
wire \axaddr_wrap[1]_i_1__0_n_0 ;
wire \axaddr_wrap[2]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_1__0_n_0 ;
wire \axaddr_wrap[3]_i_3_n_0 ;
wire \axaddr_wrap[3]_i_4_n_0 ;
wire \axaddr_wrap[3]_i_5_n_0 ;
wire \axaddr_wrap[3]_i_6_n_0 ;
wire \axaddr_wrap[4]_i_1__0_n_0 ;
wire \axaddr_wrap[5]_i_1__0_n_0 ;
wire \axaddr_wrap[6]_i_1__0_n_0 ;
wire \axaddr_wrap[7]_i_1__0_n_0 ;
wire \axaddr_wrap[8]_i_1__0_n_0 ;
wire \axaddr_wrap[9]_i_1__0_n_0 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_1 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_2 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_3 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_4 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_5 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_6 ;
wire \axaddr_wrap_reg[11]_i_3__0_n_7 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[3]_i_2__0_n_7 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_0 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_1 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_2 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_3 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_4 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_5 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_6 ;
wire \axaddr_wrap_reg[7]_i_2__0_n_7 ;
wire \axaddr_wrap_reg_n_0_[0] ;
wire \axaddr_wrap_reg_n_0_[10] ;
wire \axaddr_wrap_reg_n_0_[11] ;
wire \axaddr_wrap_reg_n_0_[1] ;
wire \axaddr_wrap_reg_n_0_[2] ;
wire \axaddr_wrap_reg_n_0_[3] ;
wire \axaddr_wrap_reg_n_0_[4] ;
wire \axaddr_wrap_reg_n_0_[5] ;
wire \axaddr_wrap_reg_n_0_[6] ;
wire \axaddr_wrap_reg_n_0_[7] ;
wire \axaddr_wrap_reg_n_0_[8] ;
wire \axaddr_wrap_reg_n_0_[9] ;
wire \axlen_cnt[0]_i_1__1_n_0 ;
wire \axlen_cnt[1]_i_1__2_n_0 ;
wire \axlen_cnt[2]_i_1__2_n_0 ;
wire \axlen_cnt[3]_i_1__2_n_0 ;
wire \axlen_cnt_reg_n_0_[0] ;
wire \axlen_cnt_reg_n_0_[1] ;
wire \axlen_cnt_reg_n_0_[2] ;
wire \axlen_cnt_reg_n_0_[3] ;
wire incr_next_pending;
wire [11:0]m_axi_araddr;
wire \m_payload_i_reg[35] ;
wire [18:0]\m_payload_i_reg[47] ;
wire \m_payload_i_reg[47]_0 ;
wire [6:0]\m_payload_i_reg[6] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_i_2__2_n_0;
wire next_pending_r_reg_n_0;
wire s_axburst_eq0_reg;
wire s_axburst_eq1_reg;
wire sel_first_i;
wire sel_first_reg_0;
wire sel_first_reg_1;
wire sel_first_reg_2;
wire si_rs_arvalid;
wire [1:0]\state_reg[1] ;
wire \state_reg[1]_rep ;
wire \wrap_boundary_axaddr_r_reg_n_0_[0] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[10] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[11] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[1] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[2] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[3] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[4] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[5] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[6] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[7] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[8] ;
wire \wrap_boundary_axaddr_r_reg_n_0_[9] ;
wire \wrap_cnt_r[1]_i_1__0_n_0 ;
wire \wrap_cnt_r_reg_n_0_[0] ;
wire \wrap_cnt_r_reg_n_0_[1] ;
wire \wrap_cnt_r_reg_n_0_[2] ;
wire \wrap_cnt_r_reg_n_0_[3] ;
wire wrap_next_pending;
wire [3:0]\wrap_second_len_r_reg[3]_0 ;
wire [3:0]\wrap_second_len_r_reg[3]_1 ;
wire [2:0]\wrap_second_len_r_reg[3]_2 ;
wire [3:3]\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE \axaddr_offset_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [0]),
.Q(\axaddr_offset_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [1]),
.Q(\axaddr_offset_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [2]),
.Q(\axaddr_offset_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \axaddr_offset_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\axaddr_offset_r_reg[3]_2 [3]),
.Q(\axaddr_offset_r_reg[3]_0 [3]),
.R(1'b0));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[0]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [0]),
.O(\axaddr_wrap[0]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[10]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [10]),
.O(\axaddr_wrap[10]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[11]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [11]),
.O(\axaddr_wrap[11]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h41))
\axaddr_wrap[11]_i_2__0
(.I0(\axaddr_wrap[11]_i_4__0_n_0 ),
.I1(\wrap_cnt_r_reg_n_0_[3] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.O(\axaddr_wrap[11]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h6FF6FFFFFFFF6FF6))
\axaddr_wrap[11]_i_4__0
(.I0(\wrap_cnt_r_reg_n_0_[0] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\wrap_cnt_r_reg_n_0_[1] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\wrap_cnt_r_reg_n_0_[2] ),
.O(\axaddr_wrap[11]_i_4__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[1]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [1]),
.O(\axaddr_wrap[1]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[2]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [2]),
.O(\axaddr_wrap[2]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[3]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[3]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [3]),
.O(\axaddr_wrap[3]_i_1__0_n_0 ));
LUT3 #(
.INIT(8'h6A))
\axaddr_wrap[3]_i_3
(.I0(\axaddr_wrap_reg_n_0_[3] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_3_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_4
(.I0(\axaddr_wrap_reg_n_0_[2] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_4_n_0 ));
LUT3 #(
.INIT(8'h9A))
\axaddr_wrap[3]_i_5
(.I0(\axaddr_wrap_reg_n_0_[1] ),
.I1(\m_payload_i_reg[47] [13]),
.I2(\m_payload_i_reg[47] [12]),
.O(\axaddr_wrap[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'hA9))
\axaddr_wrap[3]_i_6
(.I0(\axaddr_wrap_reg_n_0_[0] ),
.I1(\m_payload_i_reg[47] [12]),
.I2(\m_payload_i_reg[47] [13]),
.O(\axaddr_wrap[3]_i_6_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[4]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [4]),
.O(\axaddr_wrap[4]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[5]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [5]),
.O(\axaddr_wrap[5]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[6]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_5 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [6]),
.O(\axaddr_wrap[6]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[7]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[7]_i_2__0_n_4 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [7]),
.O(\axaddr_wrap[7]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[8]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_7 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [8]),
.O(\axaddr_wrap[8]_i_1__0_n_0 ));
LUT5 #(
.INIT(32'hB8FFB800))
\axaddr_wrap[9]_i_1__0
(.I0(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.I1(\axaddr_wrap[11]_i_2__0_n_0 ),
.I2(\axaddr_wrap_reg[11]_i_3__0_n_6 ),
.I3(\state_reg[1]_rep ),
.I4(\m_payload_i_reg[47] [9]),
.O(\axaddr_wrap[9]_i_1__0_n_0 ));
FDRE \axaddr_wrap_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[0]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[0] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[10]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[10]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[10] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[11]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[11]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[11] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[11]_i_3__0
(.CI(\axaddr_wrap_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_wrap_reg[11]_i_3__0_n_1 ,\axaddr_wrap_reg[11]_i_3__0_n_2 ,\axaddr_wrap_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[11]_i_3__0_n_4 ,\axaddr_wrap_reg[11]_i_3__0_n_5 ,\axaddr_wrap_reg[11]_i_3__0_n_6 ,\axaddr_wrap_reg[11]_i_3__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[11] ,\axaddr_wrap_reg_n_0_[10] ,\axaddr_wrap_reg_n_0_[9] ,\axaddr_wrap_reg_n_0_[8] }));
FDRE \axaddr_wrap_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[1]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[1] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[2]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[2] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[3]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[3] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_wrap_reg[3]_i_2__0_n_0 ,\axaddr_wrap_reg[3]_i_2__0_n_1 ,\axaddr_wrap_reg[3]_i_2__0_n_2 ,\axaddr_wrap_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({\axaddr_wrap_reg_n_0_[3] ,\axaddr_wrap_reg_n_0_[2] ,\axaddr_wrap_reg_n_0_[1] ,\axaddr_wrap_reg_n_0_[0] }),
.O({\axaddr_wrap_reg[3]_i_2__0_n_4 ,\axaddr_wrap_reg[3]_i_2__0_n_5 ,\axaddr_wrap_reg[3]_i_2__0_n_6 ,\axaddr_wrap_reg[3]_i_2__0_n_7 }),
.S({\axaddr_wrap[3]_i_3_n_0 ,\axaddr_wrap[3]_i_4_n_0 ,\axaddr_wrap[3]_i_5_n_0 ,\axaddr_wrap[3]_i_6_n_0 }));
FDRE \axaddr_wrap_reg[4]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[4]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[4] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[5]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[5]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[5] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[6]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[6]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[6] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[7]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[7]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[7] ),
.R(1'b0));
CARRY4 \axaddr_wrap_reg[7]_i_2__0
(.CI(\axaddr_wrap_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_wrap_reg[7]_i_2__0_n_0 ,\axaddr_wrap_reg[7]_i_2__0_n_1 ,\axaddr_wrap_reg[7]_i_2__0_n_2 ,\axaddr_wrap_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\axaddr_wrap_reg[7]_i_2__0_n_4 ,\axaddr_wrap_reg[7]_i_2__0_n_5 ,\axaddr_wrap_reg[7]_i_2__0_n_6 ,\axaddr_wrap_reg[7]_i_2__0_n_7 }),
.S({\axaddr_wrap_reg_n_0_[7] ,\axaddr_wrap_reg_n_0_[6] ,\axaddr_wrap_reg_n_0_[5] ,\axaddr_wrap_reg_n_0_[4] }));
FDRE \axaddr_wrap_reg[8]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[8]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[8] ),
.R(1'b0));
FDRE \axaddr_wrap_reg[9]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axaddr_wrap[9]_i_1__0_n_0 ),
.Q(\axaddr_wrap_reg_n_0_[9] ),
.R(1'b0));
LUT6 #(
.INIT(64'hA3A3A3A3A3A3A3A0))
\axlen_cnt[0]_i_1__1
(.I0(\m_payload_i_reg[47] [15]),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(E),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(\axlen_cnt[0]_i_1__1_n_0 ));
LUT6 #(
.INIT(64'hFFFF999800009998))
\axlen_cnt[1]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[1] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[3] ),
.I3(\axlen_cnt_reg_n_0_[2] ),
.I4(E),
.I5(\m_payload_i_reg[47] [16]),
.O(\axlen_cnt[1]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFA9A80000A9A8))
\axlen_cnt[2]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[2] ),
.I1(\axlen_cnt_reg_n_0_[0] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(E),
.I5(\m_payload_i_reg[47] [17]),
.O(\axlen_cnt[2]_i_1__2_n_0 ));
LUT6 #(
.INIT(64'hFFFFAAA80000AAA8))
\axlen_cnt[3]_i_1__2
(.I0(\axlen_cnt_reg_n_0_[3] ),
.I1(\axlen_cnt_reg_n_0_[2] ),
.I2(\axlen_cnt_reg_n_0_[1] ),
.I3(\axlen_cnt_reg_n_0_[0] ),
.I4(E),
.I5(\m_payload_i_reg[47] [18]),
.O(\axlen_cnt[3]_i_1__2_n_0 ));
FDRE \axlen_cnt_reg[0]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[0]_i_1__1_n_0 ),
.Q(\axlen_cnt_reg_n_0_[0] ),
.R(1'b0));
FDRE \axlen_cnt_reg[1]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[1]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[1] ),
.R(1'b0));
FDRE \axlen_cnt_reg[2]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[2]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[2] ),
.R(1'b0));
FDRE \axlen_cnt_reg[3]
(.C(aclk),
.CE(m_valid_i_reg),
.D(\axlen_cnt[3]_i_1__2_n_0 ),
.Q(\axlen_cnt_reg_n_0_[3] ),
.R(1'b0));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[0]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[0] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [0]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [0]),
.O(m_axi_araddr[0]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[10]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[10] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [10]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [10]),
.O(m_axi_araddr[10]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[11]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[11] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [11]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [11]),
.O(m_axi_araddr[11]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[1]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[1] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [1]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [1]),
.O(m_axi_araddr[1]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[2]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[2] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [2]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [2]),
.O(m_axi_araddr[2]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[3]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[3] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [3]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [3]),
.O(m_axi_araddr[3]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[4]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[4] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [4]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [4]),
.O(m_axi_araddr[4]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[5]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[5] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [5]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [5]),
.O(m_axi_araddr[5]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[6]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[6] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [6]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [6]),
.O(m_axi_araddr[6]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[7]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[7] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [7]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [7]),
.O(m_axi_araddr[7]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[8]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[8] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [8]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [8]),
.O(m_axi_araddr[8]));
LUT6 #(
.INIT(64'hEF40EF4FEF40E040))
\m_axi_araddr[9]_INST_0
(.I0(sel_first_reg_0),
.I1(\axaddr_wrap_reg_n_0_[9] ),
.I2(\m_payload_i_reg[47] [14]),
.I3(\m_payload_i_reg[47] [9]),
.I4(sel_first_reg_2),
.I5(\axaddr_incr_reg[11] [9]),
.O(m_axi_araddr[9]));
LUT5 #(
.INIT(32'hFFFFE0E2))
next_pending_r_i_1__1
(.I0(next_pending_r_reg_n_0),
.I1(\state_reg[1]_rep ),
.I2(next_pending_r_i_2__2_n_0),
.I3(E),
.I4(\m_payload_i_reg[47]_0 ),
.O(wrap_next_pending));
LUT6 #(
.INIT(64'hFBFBFBFBFBFBFB00))
next_pending_r_i_2__2
(.I0(\state_reg[1] [0]),
.I1(si_rs_arvalid),
.I2(\state_reg[1] [1]),
.I3(\axlen_cnt_reg_n_0_[3] ),
.I4(\axlen_cnt_reg_n_0_[2] ),
.I5(\axlen_cnt_reg_n_0_[1] ),
.O(next_pending_r_i_2__2_n_0));
FDRE next_pending_r_reg
(.C(aclk),
.CE(1'b1),
.D(wrap_next_pending),
.Q(next_pending_r_reg_n_0),
.R(1'b0));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hFB08))
s_axburst_eq0_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq0_reg));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT4 #(
.INIT(16'hABA8))
s_axburst_eq1_i_1__0
(.I0(wrap_next_pending),
.I1(\m_payload_i_reg[47] [14]),
.I2(sel_first_i),
.I3(incr_next_pending),
.O(s_axburst_eq1_reg));
FDRE sel_first_reg
(.C(aclk),
.CE(1'b1),
.D(sel_first_reg_1),
.Q(sel_first_reg_0),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[0]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [0]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[10]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [10]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[10] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[11]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [11]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[11] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[1]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [1]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[2]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [2]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[3]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [3]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[4]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [4]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[4] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[5]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [5]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[5] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[6]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[6] [6]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[6] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[7]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [7]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[7] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[8]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [8]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[8] ),
.R(1'b0));
FDRE \wrap_boundary_axaddr_r_reg[9]
(.C(aclk),
.CE(E),
.D(\m_payload_i_reg[47] [9]),
.Q(\wrap_boundary_axaddr_r_reg_n_0_[9] ),
.R(1'b0));
LUT5 #(
.INIT(32'h313D020E))
\wrap_cnt_r[1]_i_1__0
(.I0(\wrap_second_len_r_reg[3]_0 [0]),
.I1(E),
.I2(\axaddr_offset_r_reg[3]_1 ),
.I3(\m_payload_i_reg[35] ),
.I4(\wrap_second_len_r_reg[3]_0 [1]),
.O(\wrap_cnt_r[1]_i_1__0_n_0 ));
FDRE \wrap_cnt_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [0]),
.Q(\wrap_cnt_r_reg_n_0_[0] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_cnt_r[1]_i_1__0_n_0 ),
.Q(\wrap_cnt_r_reg_n_0_[1] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [1]),
.Q(\wrap_cnt_r_reg_n_0_[2] ),
.R(1'b0));
FDRE \wrap_cnt_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_2 [2]),
.Q(\wrap_cnt_r_reg_n_0_[3] ),
.R(1'b0));
FDRE \wrap_second_len_r_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [0]),
.Q(\wrap_second_len_r_reg[3]_0 [0]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [1]),
.Q(\wrap_second_len_r_reg[3]_0 [1]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [2]),
.Q(\wrap_second_len_r_reg[3]_0 [2]),
.R(1'b0));
FDRE \wrap_second_len_r_reg[3]
(.C(aclk),
.CE(1'b1),
.D(\wrap_second_len_r_reg[3]_1 [3]),
.Q(\wrap_second_len_r_reg[3]_0 [3]),
.R(1'b0));
endmodule
module DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axi_register_slice
(s_axi_awready,
s_axi_arready,
si_rs_awvalid,
s_axi_bvalid,
si_rs_bready,
si_rs_arvalid,
s_axi_rvalid,
si_rs_rready,
axaddr_incr,
Q,
\axaddr_incr_reg[3] ,
\s_arid_r_reg[0] ,
\axaddr_incr_reg[7] ,
O,
D,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[2] ,
\axaddr_offset_r_reg[1]_0 ,
next_pending_r_reg_1,
\wrap_second_len_r_reg[3]_0 ,
\axlen_cnt_reg[3]_0 ,
next_pending_r_reg_2,
\cnt_read_reg[1] ,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\axaddr_offset_r_reg[3]_0 ,
\wrap_boundary_axaddr_r_reg[6]_0 ,
\axaddr_offset_r_reg[0]_0 ,
s_axi_bid,
s_axi_bresp,
\s_axi_rid[0] ,
aclk,
aresetn,
s_axi_rready,
\cnt_read_reg[4]_rep__2 ,
S,
\m_payload_i_reg[3] ,
\state_reg[1] ,
\axaddr_offset_r_reg[2]_0 ,
\state_reg[1]_0 ,
s_axi_awvalid,
b_push,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[2]_1 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
out,
\s_bresp_acc_reg[1] ,
si_rs_bvalid,
s_axi_bready,
s_axi_arvalid,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
r_push_r_reg,
\cnt_read_reg[4] ,
E,
m_valid_i_reg);
output s_axi_awready;
output s_axi_arready;
output si_rs_awvalid;
output s_axi_bvalid;
output si_rs_bready;
output si_rs_arvalid;
output s_axi_rvalid;
output si_rs_rready;
output [11:0]axaddr_incr;
output [47:0]Q;
output [3:0]\axaddr_incr_reg[3] ;
output [47:0]\s_arid_r_reg[0] ;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]D;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output [1:0]\axaddr_offset_r_reg[2] ;
output \axaddr_offset_r_reg[1]_0 ;
output next_pending_r_reg_1;
output \wrap_second_len_r_reg[3]_0 ;
output \axlen_cnt_reg[3]_0 ;
output next_pending_r_reg_2;
output \cnt_read_reg[1] ;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \axaddr_offset_r_reg[3]_0 ;
output [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
output \axaddr_offset_r_reg[0]_0 ;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
output [35:0]\s_axi_rid[0] ;
input aclk;
input aresetn;
input s_axi_rready;
input \cnt_read_reg[4]_rep__2 ;
input [3:0]S;
input [3:0]\m_payload_i_reg[3] ;
input \state_reg[1] ;
input [1:0]\axaddr_offset_r_reg[2]_0 ;
input [1:0]\state_reg[1]_0 ;
input s_axi_awvalid;
input b_push;
input \state_reg[1]_rep ;
input [1:0]\axaddr_offset_r_reg[2]_1 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input [0:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input si_rs_bvalid;
input s_axi_bready;
input s_axi_arvalid;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [1:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
input [0:0]E;
input [0:0]m_valid_i_reg;
wire [1:0]D;
wire [0:0]E;
wire [3:0]O;
wire [47:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire [11:0]axaddr_incr;
wire [3:0]\axaddr_incr_reg[3] ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[0]_0 ;
wire \axaddr_offset_r_reg[1] ;
wire \axaddr_offset_r_reg[1]_0 ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire [1:0]\axaddr_offset_r_reg[2]_0 ;
wire [1:0]\axaddr_offset_r_reg[2]_1 ;
wire \axaddr_offset_r_reg[3] ;
wire \axaddr_offset_r_reg[3]_0 ;
wire \axlen_cnt_reg[3] ;
wire \axlen_cnt_reg[3]_0 ;
wire b_push;
wire \cnt_read_reg[1] ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__2 ;
wire \gen_simple_ar.ar_pipe_n_2 ;
wire \gen_simple_aw.aw_pipe_n_1 ;
wire \gen_simple_aw.aw_pipe_n_79 ;
wire [3:0]\m_payload_i_reg[3] ;
wire [0:0]m_valid_i_reg;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire next_pending_r_reg_1;
wire next_pending_r_reg_2;
wire [0:0]out;
wire [1:0]r_push_r_reg;
wire [47:0]\s_arid_r_reg[0] ;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [35:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire si_rs_arvalid;
wire si_rs_awvalid;
wire si_rs_bready;
wire si_rs_bvalid;
wire si_rs_rready;
wire \state_reg[0]_rep ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6]_0 ;
wire \wrap_second_len_r_reg[3] ;
wire \wrap_second_len_r_reg[3]_0 ;
DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice \gen_simple_ar.ar_pipe
(.O(O),
.Q(\s_arid_r_reg[0] ),
.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[0]_0 (\gen_simple_aw.aw_pipe_n_79 ),
.\axaddr_incr_reg[3] (\axaddr_incr_reg[3] ),
.\axaddr_incr_reg[7] (\axaddr_incr_reg[7] ),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0]_0 ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1]_0 ),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2] ),
.\axaddr_offset_r_reg[2]_0 (\axaddr_offset_r_reg[2]_1 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3]_0 ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3]_0 ),
.\m_payload_i_reg[3]_0 (\m_payload_i_reg[3] ),
.m_valid_i_reg_0(\gen_simple_ar.ar_pipe_n_2 ),
.m_valid_i_reg_1(m_valid_i_reg),
.next_pending_r_reg(next_pending_r_reg_1),
.next_pending_r_reg_0(next_pending_r_reg_2),
.s_axi_araddr(s_axi_araddr),
.s_axi_arburst(s_axi_arburst),
.s_axi_arid(s_axi_arid),
.s_axi_arlen(s_axi_arlen),
.s_axi_arprot(s_axi_arprot),
.s_axi_arready(s_axi_arready),
.s_axi_arsize(s_axi_arsize),
.s_axi_arvalid(s_axi_arvalid),
.s_ready_i_reg_0(si_rs_arvalid),
.\state_reg[0]_rep (\state_reg[0]_rep ),
.\state_reg[1]_rep (\state_reg[1]_rep ),
.\state_reg[1]_rep_0 (\state_reg[1]_rep_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6]_0 ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3]_0 ));
DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0 \gen_simple_aw.aw_pipe
(.D(D),
.E(E),
.Q(Q),
.S(S),
.aclk(aclk),
.aresetn(aresetn),
.\aresetn_d_reg[1]_inv (\gen_simple_aw.aw_pipe_n_79 ),
.\aresetn_d_reg[1]_inv_0 (\gen_simple_ar.ar_pipe_n_2 ),
.axaddr_incr(axaddr_incr),
.\axaddr_offset_r_reg[0] (\axaddr_offset_r_reg[0] ),
.\axaddr_offset_r_reg[1] (\axaddr_offset_r_reg[1] ),
.\axaddr_offset_r_reg[2] (\axaddr_offset_r_reg[2]_0 ),
.\axaddr_offset_r_reg[3] (\axaddr_offset_r_reg[3] ),
.\axlen_cnt_reg[3] (\axlen_cnt_reg[3] ),
.b_push(b_push),
.m_valid_i_reg_0(si_rs_awvalid),
.next_pending_r_reg(next_pending_r_reg),
.next_pending_r_reg_0(next_pending_r_reg_0),
.s_axi_awaddr(s_axi_awaddr),
.s_axi_awburst(s_axi_awburst),
.s_axi_awid(s_axi_awid),
.s_axi_awlen(s_axi_awlen),
.s_axi_awprot(s_axi_awprot),
.s_axi_awready(s_axi_awready),
.s_axi_awsize(s_axi_awsize),
.s_axi_awvalid(s_axi_awvalid),
.s_ready_i_reg_0(\gen_simple_aw.aw_pipe_n_1 ),
.\state_reg[1] (\state_reg[1] ),
.\state_reg[1]_0 (\state_reg[1]_0 ),
.\wrap_boundary_axaddr_r_reg[6] (\wrap_boundary_axaddr_r_reg[6] ),
.\wrap_second_len_r_reg[3] (\wrap_second_len_r_reg[3] ));
DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1 \gen_simple_b.b_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.m_valid_i_reg_0(si_rs_bready),
.out(out),
.s_axi_bid(s_axi_bid),
.s_axi_bready(s_axi_bready),
.s_axi_bresp(s_axi_bresp),
.s_axi_bvalid(s_axi_bvalid),
.\s_bresp_acc_reg[1] (\s_bresp_acc_reg[1] ),
.si_rs_bvalid(si_rs_bvalid));
DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2 \gen_simple_r.r_pipe
(.aclk(aclk),
.\aresetn_d_reg[0] (\gen_simple_aw.aw_pipe_n_1 ),
.\aresetn_d_reg[1]_inv (\gen_simple_ar.ar_pipe_n_2 ),
.\cnt_read_reg[1] (\cnt_read_reg[1] ),
.\cnt_read_reg[4] (\cnt_read_reg[4] ),
.\cnt_read_reg[4]_rep__2 (\cnt_read_reg[4]_rep__2 ),
.r_push_r_reg(r_push_r_reg),
.\s_axi_rid[0] (\s_axi_rid[0] ),
.s_axi_rready(s_axi_rready),
.s_axi_rvalid(s_axi_rvalid),
.\skid_buffer_reg[0]_0 (si_rs_rready));
endmodule
module DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice
(s_axi_arready,
s_ready_i_reg_0,
m_valid_i_reg_0,
\axaddr_incr_reg[3] ,
Q,
\axaddr_incr_reg[7] ,
O,
\axaddr_offset_r_reg[2] ,
\axaddr_offset_r_reg[1] ,
next_pending_r_reg,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\aresetn_d_reg[0] ,
aclk,
\aresetn_d_reg[0]_0 ,
\m_payload_i_reg[3]_0 ,
\state_reg[1]_rep ,
\axaddr_offset_r_reg[2]_0 ,
\state_reg[0]_rep ,
\state_reg[1]_rep_0 ,
s_axi_arvalid,
s_axi_arid,
s_axi_arlen,
s_axi_arburst,
s_axi_arsize,
s_axi_arprot,
s_axi_araddr,
m_valid_i_reg_1);
output s_axi_arready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [3:0]\axaddr_incr_reg[3] ;
output [47:0]Q;
output [3:0]\axaddr_incr_reg[7] ;
output [3:0]O;
output [1:0]\axaddr_offset_r_reg[2] ;
output \axaddr_offset_r_reg[1] ;
output next_pending_r_reg;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
input \aresetn_d_reg[0] ;
input aclk;
input \aresetn_d_reg[0]_0 ;
input [3:0]\m_payload_i_reg[3]_0 ;
input \state_reg[1]_rep ;
input [1:0]\axaddr_offset_r_reg[2]_0 ;
input \state_reg[0]_rep ;
input \state_reg[1]_rep_0 ;
input s_axi_arvalid;
input [0:0]s_axi_arid;
input [7:0]s_axi_arlen;
input [1:0]s_axi_arburst;
input [1:0]s_axi_arsize;
input [2:0]s_axi_arprot;
input [31:0]s_axi_araddr;
input [0:0]m_valid_i_reg_1;
wire [3:0]O;
wire [47:0]Q;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[0]_0 ;
wire \axaddr_incr[3]_i_4__0_n_0 ;
wire \axaddr_incr[3]_i_5__0_n_0 ;
wire \axaddr_incr[3]_i_6__0_n_0 ;
wire \axaddr_incr_reg[11]_i_3__0_n_1 ;
wire \axaddr_incr_reg[11]_i_3__0_n_2 ;
wire \axaddr_incr_reg[11]_i_3__0_n_3 ;
wire [3:0]\axaddr_incr_reg[3] ;
wire \axaddr_incr_reg[3]_i_2__0_n_0 ;
wire \axaddr_incr_reg[3]_i_2__0_n_1 ;
wire \axaddr_incr_reg[3]_i_2__0_n_2 ;
wire \axaddr_incr_reg[3]_i_2__0_n_3 ;
wire [3:0]\axaddr_incr_reg[7] ;
wire \axaddr_incr_reg[7]_i_2__0_n_0 ;
wire \axaddr_incr_reg[7]_i_2__0_n_1 ;
wire \axaddr_incr_reg[7]_i_2__0_n_2 ;
wire \axaddr_incr_reg[7]_i_2__0_n_3 ;
wire \axaddr_offset_r[1]_i_3__0_n_0 ;
wire \axaddr_offset_r[2]_i_2__0_n_0 ;
wire \axaddr_offset_r[2]_i_3__0_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire [1:0]\axaddr_offset_r_reg[2]_0 ;
wire \axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire \m_payload_i[0]_i_1__0_n_0 ;
wire \m_payload_i[10]_i_1__0_n_0 ;
wire \m_payload_i[11]_i_1__0_n_0 ;
wire \m_payload_i[12]_i_1__0_n_0 ;
wire \m_payload_i[13]_i_1__0_n_0 ;
wire \m_payload_i[14]_i_1__0_n_0 ;
wire \m_payload_i[15]_i_1__0_n_0 ;
wire \m_payload_i[16]_i_1__0_n_0 ;
wire \m_payload_i[17]_i_1__0_n_0 ;
wire \m_payload_i[18]_i_1__0_n_0 ;
wire \m_payload_i[19]_i_1__0_n_0 ;
wire \m_payload_i[1]_i_1__0_n_0 ;
wire \m_payload_i[20]_i_1__0_n_0 ;
wire \m_payload_i[21]_i_1__0_n_0 ;
wire \m_payload_i[22]_i_1__0_n_0 ;
wire \m_payload_i[23]_i_1__0_n_0 ;
wire \m_payload_i[24]_i_1__0_n_0 ;
wire \m_payload_i[25]_i_1__0_n_0 ;
wire \m_payload_i[26]_i_1__0_n_0 ;
wire \m_payload_i[27]_i_1__0_n_0 ;
wire \m_payload_i[28]_i_1__0_n_0 ;
wire \m_payload_i[29]_i_1__0_n_0 ;
wire \m_payload_i[2]_i_1__0_n_0 ;
wire \m_payload_i[30]_i_1__0_n_0 ;
wire \m_payload_i[31]_i_2__0_n_0 ;
wire \m_payload_i[32]_i_1__0_n_0 ;
wire \m_payload_i[33]_i_1__0_n_0 ;
wire \m_payload_i[34]_i_1__0_n_0 ;
wire \m_payload_i[35]_i_1__1_n_0 ;
wire \m_payload_i[36]_i_1__0_n_0 ;
wire \m_payload_i[38]_i_1__0_n_0 ;
wire \m_payload_i[39]_i_1__0_n_0 ;
wire \m_payload_i[3]_i_1__0_n_0 ;
wire \m_payload_i[44]_i_1__0_n_0 ;
wire \m_payload_i[45]_i_1__0_n_0 ;
wire \m_payload_i[46]_i_1__0_n_0 ;
wire \m_payload_i[47]_i_1__0_n_0 ;
wire \m_payload_i[48]_i_1__0_n_0 ;
wire \m_payload_i[49]_i_1__0_n_0 ;
wire \m_payload_i[4]_i_1__0_n_0 ;
wire \m_payload_i[50]_i_1__0_n_0 ;
wire \m_payload_i[51]_i_1__0_n_0 ;
wire \m_payload_i[53]_i_1__0_n_0 ;
wire \m_payload_i[5]_i_1__0_n_0 ;
wire \m_payload_i[6]_i_1__0_n_0 ;
wire \m_payload_i[7]_i_1__0_n_0 ;
wire \m_payload_i[8]_i_1__0_n_0 ;
wire \m_payload_i[9]_i_1__0_n_0 ;
wire [3:0]\m_payload_i_reg[3]_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]m_valid_i_reg_1;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_araddr;
wire [1:0]s_axi_arburst;
wire [0:0]s_axi_arid;
wire [7:0]s_axi_arlen;
wire [2:0]s_axi_arprot;
wire s_axi_arready;
wire [1:0]s_axi_arsize;
wire s_axi_arvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[0]_rep ;
wire \state_reg[1]_rep ;
wire \state_reg[1]_rep_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2__0_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED ;
FDRE #(
.INIT(1'b1))
\aresetn_d_reg[1]_inv
(.C(aclk),
.CE(1'b1),
.D(\aresetn_d_reg[0]_0 ),
.Q(m_valid_i_reg_0),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5__0
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5__0_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6__0
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6__0_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3__0
(.CI(\axaddr_incr_reg[7]_i_2__0_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3__0_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3__0_n_1 ,\axaddr_incr_reg[11]_i_3__0_n_2 ,\axaddr_incr_reg[11]_i_3__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(O),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2__0
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2__0_n_0 ,\axaddr_incr_reg[3]_i_2__0_n_1 ,\axaddr_incr_reg[3]_i_2__0_n_2 ,\axaddr_incr_reg[3]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4__0_n_0 ,\axaddr_incr[3]_i_5__0_n_0 ,\axaddr_incr[3]_i_6__0_n_0 }),
.O(\axaddr_incr_reg[3] ),
.S(\m_payload_i_reg[3]_0 ));
CARRY4 \axaddr_incr_reg[7]_i_2__0
(.CI(\axaddr_incr_reg[3]_i_2__0_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2__0_n_0 ,\axaddr_incr_reg[7]_i_2__0_n_1 ,\axaddr_incr_reg[7]_i_2__0_n_2 ,\axaddr_incr_reg[7]_i_2__0_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(\axaddr_incr_reg[7] ),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2__0
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1__0
(.I0(\axaddr_offset_r_reg[1] ),
.O(\axaddr_offset_r_reg[2] [0]));
LUT6 #(
.INIT(64'h4F7F00004F7FFFFF))
\axaddr_offset_r[1]_i_2__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[1]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[2]_0 [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3__0
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hC808FFFFC8080000))
\axaddr_offset_r[2]_i_1__0
(.I0(\axaddr_offset_r[2]_i_2__0_n_0 ),
.I1(Q[41]),
.I2(Q[35]),
.I3(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I4(\state_reg[1]_rep ),
.I5(\axaddr_offset_r_reg[2]_0 [1]),
.O(\axaddr_offset_r_reg[2] [1]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2__0
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_2__0_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2__0
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2__0
(.I0(Q[42]),
.I1(\state_reg[0]_rep ),
.I2(s_ready_i_reg_0),
.I3(\state_reg[1]_rep_0 ),
.O(\axlen_cnt_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__0
(.I0(s_axi_araddr[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__0
(.I0(s_axi_araddr[10]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__0
(.I0(s_axi_araddr[11]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__0
(.I0(s_axi_araddr[12]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__0
(.I0(s_axi_araddr[13]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__0
(.I0(s_axi_araddr[14]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__0
(.I0(s_axi_araddr[15]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__0
(.I0(s_axi_araddr[16]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__0
(.I0(s_axi_araddr[17]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__0
(.I0(s_axi_araddr[18]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__0
(.I0(s_axi_araddr[19]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__0
(.I0(s_axi_araddr[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__0
(.I0(s_axi_araddr[20]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__0
(.I0(s_axi_araddr[21]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__0
(.I0(s_axi_araddr[22]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__0
(.I0(s_axi_araddr[23]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__0
(.I0(s_axi_araddr[24]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__0
(.I0(s_axi_araddr[25]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__0
(.I0(s_axi_araddr[26]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__0
(.I0(s_axi_araddr[27]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__0
(.I0(s_axi_araddr[28]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__0
(.I0(s_axi_araddr[29]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__0
(.I0(s_axi_araddr[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__0
(.I0(s_axi_araddr[30]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2__0
(.I0(s_axi_araddr[31]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__0
(.I0(s_axi_arprot[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__0
(.I0(s_axi_arprot[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__0
(.I0(s_axi_arprot[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__1
(.I0(s_axi_arsize[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1__0
(.I0(s_axi_arsize[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(\m_payload_i[36]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1__0
(.I0(s_axi_arburst[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(\m_payload_i[38]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1__0
(.I0(s_axi_arburst[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(\m_payload_i[39]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__0
(.I0(s_axi_araddr[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1__0
(.I0(s_axi_arlen[0]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(\m_payload_i[44]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1__0
(.I0(s_axi_arlen[1]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(\m_payload_i[45]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1__0
(.I0(s_axi_arlen[2]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(\m_payload_i[46]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1__0
(.I0(s_axi_arlen[3]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(\m_payload_i[47]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1__0
(.I0(s_axi_arlen[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(\m_payload_i[48]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1__0
(.I0(s_axi_arlen[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(\m_payload_i[49]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__0
(.I0(s_axi_araddr[4]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1__0
(.I0(s_axi_arlen[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(\m_payload_i[50]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1__0
(.I0(s_axi_arlen[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(\m_payload_i[51]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1__0
(.I0(s_axi_arid),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(\m_payload_i[53]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__0
(.I0(s_axi_araddr[5]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__0
(.I0(s_axi_araddr[6]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__0
(.I0(s_axi_araddr[7]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__0
(.I0(s_axi_araddr[8]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__0
(.I0(s_axi_araddr[9]),
.I1(s_axi_arready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__0_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[0]_i_1__0_n_0 ),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[10]_i_1__0_n_0 ),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[11]_i_1__0_n_0 ),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[12]_i_1__0_n_0 ),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[13]_i_1__0_n_0 ),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[14]_i_1__0_n_0 ),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[15]_i_1__0_n_0 ),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[16]_i_1__0_n_0 ),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[17]_i_1__0_n_0 ),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[18]_i_1__0_n_0 ),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[19]_i_1__0_n_0 ),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[1]_i_1__0_n_0 ),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[20]_i_1__0_n_0 ),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[21]_i_1__0_n_0 ),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[22]_i_1__0_n_0 ),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[23]_i_1__0_n_0 ),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[24]_i_1__0_n_0 ),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[25]_i_1__0_n_0 ),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[26]_i_1__0_n_0 ),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[27]_i_1__0_n_0 ),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[28]_i_1__0_n_0 ),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[29]_i_1__0_n_0 ),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[2]_i_1__0_n_0 ),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[30]_i_1__0_n_0 ),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[31]_i_2__0_n_0 ),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[32]_i_1__0_n_0 ),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[33]_i_1__0_n_0 ),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[34]_i_1__0_n_0 ),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[35]_i_1__1_n_0 ),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[36]_i_1__0_n_0 ),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[38]_i_1__0_n_0 ),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[39]_i_1__0_n_0 ),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[3]_i_1__0_n_0 ),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[44]_i_1__0_n_0 ),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[45]_i_1__0_n_0 ),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[46]_i_1__0_n_0 ),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[47]_i_1__0_n_0 ),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[48]_i_1__0_n_0 ),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[49]_i_1__0_n_0 ),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[4]_i_1__0_n_0 ),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[50]_i_1__0_n_0 ),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[51]_i_1__0_n_0 ),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[53]_i_1__0_n_0 ),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[5]_i_1__0_n_0 ),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[6]_i_1__0_n_0 ),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[7]_i_1__0_n_0 ),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[8]_i_1__0_n_0 ),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(m_valid_i_reg_1),
.D(\m_payload_i[9]_i_1__0_n_0 ),
.Q(Q[9]),
.R(1'b0));
LUT5 #(
.INIT(32'hBFFFBBBB))
m_valid_i_i_1__1
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_ready_i_reg_0),
.R(m_valid_i_reg_0));
LUT4 #(
.INIT(16'h0001))
next_pending_r_i_2__1
(.I0(Q[43]),
.I1(Q[45]),
.I2(Q[44]),
.I3(Q[46]),
.O(next_pending_r_reg_0));
LUT5 #(
.INIT(32'hAAAAAAA8))
next_pending_r_i_3__0
(.I0(\state_reg[1]_rep ),
.I1(Q[42]),
.I2(Q[40]),
.I3(Q[39]),
.I4(Q[41]),
.O(next_pending_r_reg));
LUT5 #(
.INIT(32'hF444FFFF))
s_ready_i_i_1__0
(.I0(s_axi_arvalid),
.I1(s_axi_arready),
.I2(\state_reg[0]_rep ),
.I3(\state_reg[1]_rep_0 ),
.I4(s_ready_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_arready),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_arid),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_arready),
.D(s_axi_araddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1__0
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1__0
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888028AAAAA028A))
\wrap_boundary_axaddr_r[2]_i_1__0
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[41]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1__0
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2__0
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'h002A222A882AAA2A))
\wrap_boundary_axaddr_r[4]_i_1__0
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1__0
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1__0
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2__0
(.I0(\axaddr_offset_r[2]_i_3__0_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice_0
(s_axi_awready,
s_ready_i_reg_0,
m_valid_i_reg_0,
axaddr_incr,
Q,
D,
\axaddr_offset_r_reg[1] ,
\wrap_second_len_r_reg[3] ,
\axlen_cnt_reg[3] ,
next_pending_r_reg,
next_pending_r_reg_0,
\axaddr_offset_r_reg[3] ,
\wrap_boundary_axaddr_r_reg[6] ,
\axaddr_offset_r_reg[0] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[1]_inv_0 ,
aresetn,
S,
\state_reg[1] ,
\axaddr_offset_r_reg[2] ,
\state_reg[1]_0 ,
s_axi_awvalid,
b_push,
s_axi_awid,
s_axi_awlen,
s_axi_awburst,
s_axi_awsize,
s_axi_awprot,
s_axi_awaddr,
E);
output s_axi_awready;
output s_ready_i_reg_0;
output m_valid_i_reg_0;
output [11:0]axaddr_incr;
output [47:0]Q;
output [1:0]D;
output \axaddr_offset_r_reg[1] ;
output \wrap_second_len_r_reg[3] ;
output \axlen_cnt_reg[3] ;
output next_pending_r_reg;
output next_pending_r_reg_0;
output \axaddr_offset_r_reg[3] ;
output [6:0]\wrap_boundary_axaddr_r_reg[6] ;
output \axaddr_offset_r_reg[0] ;
output \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[1]_inv_0 ;
input aresetn;
input [3:0]S;
input \state_reg[1] ;
input [1:0]\axaddr_offset_r_reg[2] ;
input [1:0]\state_reg[1]_0 ;
input s_axi_awvalid;
input b_push;
input [0:0]s_axi_awid;
input [7:0]s_axi_awlen;
input [1:0]s_axi_awburst;
input [1:0]s_axi_awsize;
input [2:0]s_axi_awprot;
input [31:0]s_axi_awaddr;
input [0:0]E;
wire [1:0]D;
wire [0:0]E;
wire [47:0]Q;
wire [3:0]S;
wire aclk;
wire aresetn;
wire \aresetn_d_reg[1]_inv ;
wire \aresetn_d_reg[1]_inv_0 ;
wire \aresetn_d_reg_n_0_[0] ;
wire [11:0]axaddr_incr;
wire \axaddr_incr[3]_i_4_n_0 ;
wire \axaddr_incr[3]_i_5_n_0 ;
wire \axaddr_incr[3]_i_6_n_0 ;
wire \axaddr_incr_reg[11]_i_3_n_1 ;
wire \axaddr_incr_reg[11]_i_3_n_2 ;
wire \axaddr_incr_reg[11]_i_3_n_3 ;
wire \axaddr_incr_reg[3]_i_2_n_0 ;
wire \axaddr_incr_reg[3]_i_2_n_1 ;
wire \axaddr_incr_reg[3]_i_2_n_2 ;
wire \axaddr_incr_reg[3]_i_2_n_3 ;
wire \axaddr_incr_reg[7]_i_2_n_0 ;
wire \axaddr_incr_reg[7]_i_2_n_1 ;
wire \axaddr_incr_reg[7]_i_2_n_2 ;
wire \axaddr_incr_reg[7]_i_2_n_3 ;
wire \axaddr_offset_r[1]_i_3_n_0 ;
wire \axaddr_offset_r[2]_i_2_n_0 ;
wire \axaddr_offset_r[2]_i_3_n_0 ;
wire \axaddr_offset_r_reg[0] ;
wire \axaddr_offset_r_reg[1] ;
wire [1:0]\axaddr_offset_r_reg[2] ;
wire \axaddr_offset_r_reg[3] ;
wire \axlen_cnt_reg[3] ;
wire b_push;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire next_pending_r_reg;
wire next_pending_r_reg_0;
wire [31:0]s_axi_awaddr;
wire [1:0]s_axi_awburst;
wire [0:0]s_axi_awid;
wire [7:0]s_axi_awlen;
wire [2:0]s_axi_awprot;
wire s_axi_awready;
wire [1:0]s_axi_awsize;
wire s_axi_awvalid;
wire s_ready_i0;
wire s_ready_i_reg_0;
wire [53:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[36] ;
wire \skid_buffer_reg_n_0_[38] ;
wire \skid_buffer_reg_n_0_[39] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[44] ;
wire \skid_buffer_reg_n_0_[45] ;
wire \skid_buffer_reg_n_0_[46] ;
wire \skid_buffer_reg_n_0_[47] ;
wire \skid_buffer_reg_n_0_[48] ;
wire \skid_buffer_reg_n_0_[49] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[50] ;
wire \skid_buffer_reg_n_0_[51] ;
wire \skid_buffer_reg_n_0_[53] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
wire \state_reg[1] ;
wire [1:0]\state_reg[1]_0 ;
wire \wrap_boundary_axaddr_r[3]_i_2_n_0 ;
wire [6:0]\wrap_boundary_axaddr_r_reg[6] ;
wire \wrap_second_len_r_reg[3] ;
wire [3:3]\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED ;
LUT2 #(
.INIT(4'h7))
\aresetn_d[1]_inv_i_1
(.I0(\aresetn_d_reg_n_0_[0] ),
.I1(aresetn),
.O(\aresetn_d_reg[1]_inv ));
FDRE #(
.INIT(1'b0))
\aresetn_d_reg[0]
(.C(aclk),
.CE(1'b1),
.D(aresetn),
.Q(\aresetn_d_reg_n_0_[0] ),
.R(1'b0));
LUT3 #(
.INIT(8'h2A))
\axaddr_incr[3]_i_4
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_4_n_0 ));
LUT2 #(
.INIT(4'h2))
\axaddr_incr[3]_i_5
(.I0(Q[1]),
.I1(Q[36]),
.O(\axaddr_incr[3]_i_5_n_0 ));
LUT3 #(
.INIT(8'h02))
\axaddr_incr[3]_i_6
(.I0(Q[0]),
.I1(Q[35]),
.I2(Q[36]),
.O(\axaddr_incr[3]_i_6_n_0 ));
CARRY4 \axaddr_incr_reg[11]_i_3
(.CI(\axaddr_incr_reg[7]_i_2_n_0 ),
.CO({\NLW_axaddr_incr_reg[11]_i_3_CO_UNCONNECTED [3],\axaddr_incr_reg[11]_i_3_n_1 ,\axaddr_incr_reg[11]_i_3_n_2 ,\axaddr_incr_reg[11]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[11:8]),
.S(Q[11:8]));
CARRY4 \axaddr_incr_reg[3]_i_2
(.CI(1'b0),
.CO({\axaddr_incr_reg[3]_i_2_n_0 ,\axaddr_incr_reg[3]_i_2_n_1 ,\axaddr_incr_reg[3]_i_2_n_2 ,\axaddr_incr_reg[3]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({Q[3],\axaddr_incr[3]_i_4_n_0 ,\axaddr_incr[3]_i_5_n_0 ,\axaddr_incr[3]_i_6_n_0 }),
.O(axaddr_incr[3:0]),
.S(S));
CARRY4 \axaddr_incr_reg[7]_i_2
(.CI(\axaddr_incr_reg[3]_i_2_n_0 ),
.CO({\axaddr_incr_reg[7]_i_2_n_0 ,\axaddr_incr_reg[7]_i_2_n_1 ,\axaddr_incr_reg[7]_i_2_n_2 ,\axaddr_incr_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(axaddr_incr[7:4]),
.S(Q[7:4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[0]_i_2
(.I0(Q[3]),
.I1(Q[1]),
.I2(Q[35]),
.I3(Q[2]),
.I4(Q[36]),
.I5(Q[0]),
.O(\axaddr_offset_r_reg[0] ));
LUT1 #(
.INIT(2'h1))
\axaddr_offset_r[1]_i_1
(.I0(\axaddr_offset_r_reg[1] ),
.O(D[0]));
LUT6 #(
.INIT(64'h4F7F00004F7FFFFF))
\axaddr_offset_r[1]_i_2
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[35]),
.I2(Q[40]),
.I3(\axaddr_offset_r[1]_i_3_n_0 ),
.I4(\state_reg[1] ),
.I5(\axaddr_offset_r_reg[2] [0]),
.O(\axaddr_offset_r_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[1]_i_3
(.I0(Q[3]),
.I1(Q[36]),
.I2(Q[1]),
.O(\axaddr_offset_r[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'hC808FFFFC8080000))
\axaddr_offset_r[2]_i_1
(.I0(\axaddr_offset_r[2]_i_2_n_0 ),
.I1(Q[41]),
.I2(Q[35]),
.I3(\axaddr_offset_r[2]_i_3_n_0 ),
.I4(\state_reg[1] ),
.I5(\axaddr_offset_r_reg[2] [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_2
(.I0(Q[4]),
.I1(Q[36]),
.I2(Q[2]),
.O(\axaddr_offset_r[2]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\axaddr_offset_r[2]_i_3
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[3]),
.O(\axaddr_offset_r[2]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\axaddr_offset_r[3]_i_2
(.I0(Q[6]),
.I1(Q[4]),
.I2(Q[35]),
.I3(Q[5]),
.I4(Q[36]),
.I5(Q[3]),
.O(\axaddr_offset_r_reg[3] ));
LUT4 #(
.INIT(16'hFFDF))
\axlen_cnt[3]_i_2
(.I0(Q[42]),
.I1(\state_reg[1]_0 [0]),
.I2(m_valid_i_reg_0),
.I3(\state_reg[1]_0 [1]),
.O(\axlen_cnt_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1
(.I0(s_axi_awaddr[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1
(.I0(s_axi_awaddr[10]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(skid_buffer[10]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1
(.I0(s_axi_awaddr[11]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(skid_buffer[11]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1
(.I0(s_axi_awaddr[12]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(skid_buffer[12]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1
(.I0(s_axi_awaddr[13]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(skid_buffer[13]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1
(.I0(s_axi_awaddr[14]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(skid_buffer[14]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1
(.I0(s_axi_awaddr[15]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(skid_buffer[15]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1
(.I0(s_axi_awaddr[16]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(skid_buffer[16]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1
(.I0(s_axi_awaddr[17]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(skid_buffer[17]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1
(.I0(s_axi_awaddr[18]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(skid_buffer[18]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1
(.I0(s_axi_awaddr[19]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(skid_buffer[19]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1
(.I0(s_axi_awaddr[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1
(.I0(s_axi_awaddr[20]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(skid_buffer[20]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1
(.I0(s_axi_awaddr[21]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(skid_buffer[21]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1
(.I0(s_axi_awaddr[22]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(skid_buffer[22]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1
(.I0(s_axi_awaddr[23]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(skid_buffer[23]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1
(.I0(s_axi_awaddr[24]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(skid_buffer[24]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1
(.I0(s_axi_awaddr[25]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(skid_buffer[25]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1
(.I0(s_axi_awaddr[26]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(skid_buffer[26]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1
(.I0(s_axi_awaddr[27]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(skid_buffer[27]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1
(.I0(s_axi_awaddr[28]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(skid_buffer[28]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1
(.I0(s_axi_awaddr[29]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(skid_buffer[29]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1
(.I0(s_axi_awaddr[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1
(.I0(s_axi_awaddr[30]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(skid_buffer[30]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_2
(.I0(s_axi_awaddr[31]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(skid_buffer[31]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1
(.I0(s_axi_awprot[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(skid_buffer[32]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1
(.I0(s_axi_awprot[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(skid_buffer[33]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1
(.I0(s_axi_awprot[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(skid_buffer[34]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_1__0
(.I0(s_axi_awsize[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(skid_buffer[35]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[36]_i_1
(.I0(s_axi_awsize[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[36] ),
.O(skid_buffer[36]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[38]_i_1
(.I0(s_axi_awburst[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[38] ),
.O(skid_buffer[38]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[39]_i_1
(.I0(s_axi_awburst[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[39] ),
.O(skid_buffer[39]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1
(.I0(s_axi_awaddr[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(skid_buffer[3]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[44]_i_1
(.I0(s_axi_awlen[0]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[44] ),
.O(skid_buffer[44]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[45]_i_1
(.I0(s_axi_awlen[1]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[45] ),
.O(skid_buffer[45]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[46]_i_1
(.I0(s_axi_awlen[2]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[46] ),
.O(skid_buffer[46]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[47]_i_1
(.I0(s_axi_awlen[3]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[47] ),
.O(skid_buffer[47]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[48]_i_1
(.I0(s_axi_awlen[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[48] ),
.O(skid_buffer[48]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[49]_i_1
(.I0(s_axi_awlen[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[49] ),
.O(skid_buffer[49]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1
(.I0(s_axi_awaddr[4]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(skid_buffer[4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[50]_i_1
(.I0(s_axi_awlen[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[50] ),
.O(skid_buffer[50]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[51]_i_1
(.I0(s_axi_awlen[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[51] ),
.O(skid_buffer[51]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[53]_i_1
(.I0(s_axi_awid),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[53] ),
.O(skid_buffer[53]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1
(.I0(s_axi_awaddr[5]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(skid_buffer[5]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1
(.I0(s_axi_awaddr[6]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(skid_buffer[6]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1
(.I0(s_axi_awaddr[7]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(skid_buffer[7]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1
(.I0(s_axi_awaddr[8]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(skid_buffer[8]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1
(.I0(s_axi_awaddr[9]),
.I1(s_axi_awready),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(skid_buffer[9]));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(E),
.D(skid_buffer[0]),
.Q(Q[0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(E),
.D(skid_buffer[10]),
.Q(Q[10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(E),
.D(skid_buffer[11]),
.Q(Q[11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(E),
.D(skid_buffer[12]),
.Q(Q[12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(E),
.D(skid_buffer[13]),
.Q(Q[13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(E),
.D(skid_buffer[14]),
.Q(Q[14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(E),
.D(skid_buffer[15]),
.Q(Q[15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(E),
.D(skid_buffer[16]),
.Q(Q[16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(E),
.D(skid_buffer[17]),
.Q(Q[17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(E),
.D(skid_buffer[18]),
.Q(Q[18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(E),
.D(skid_buffer[19]),
.Q(Q[19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(E),
.D(skid_buffer[1]),
.Q(Q[1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(E),
.D(skid_buffer[20]),
.Q(Q[20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(E),
.D(skid_buffer[21]),
.Q(Q[21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(E),
.D(skid_buffer[22]),
.Q(Q[22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(E),
.D(skid_buffer[23]),
.Q(Q[23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(E),
.D(skid_buffer[24]),
.Q(Q[24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(E),
.D(skid_buffer[25]),
.Q(Q[25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(E),
.D(skid_buffer[26]),
.Q(Q[26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(E),
.D(skid_buffer[27]),
.Q(Q[27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(E),
.D(skid_buffer[28]),
.Q(Q[28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(E),
.D(skid_buffer[29]),
.Q(Q[29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(E),
.D(skid_buffer[2]),
.Q(Q[2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(E),
.D(skid_buffer[30]),
.Q(Q[30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(E),
.D(skid_buffer[31]),
.Q(Q[31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(E),
.D(skid_buffer[32]),
.Q(Q[32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(E),
.D(skid_buffer[33]),
.Q(Q[33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(E),
.D(skid_buffer[34]),
.Q(Q[34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(E),
.D(skid_buffer[35]),
.Q(Q[35]),
.R(1'b0));
FDRE \m_payload_i_reg[36]
(.C(aclk),
.CE(E),
.D(skid_buffer[36]),
.Q(Q[36]),
.R(1'b0));
FDRE \m_payload_i_reg[38]
(.C(aclk),
.CE(E),
.D(skid_buffer[38]),
.Q(Q[37]),
.R(1'b0));
FDRE \m_payload_i_reg[39]
(.C(aclk),
.CE(E),
.D(skid_buffer[39]),
.Q(Q[38]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(E),
.D(skid_buffer[3]),
.Q(Q[3]),
.R(1'b0));
FDRE \m_payload_i_reg[44]
(.C(aclk),
.CE(E),
.D(skid_buffer[44]),
.Q(Q[39]),
.R(1'b0));
FDRE \m_payload_i_reg[45]
(.C(aclk),
.CE(E),
.D(skid_buffer[45]),
.Q(Q[40]),
.R(1'b0));
FDRE \m_payload_i_reg[46]
(.C(aclk),
.CE(E),
.D(skid_buffer[46]),
.Q(Q[41]),
.R(1'b0));
FDRE \m_payload_i_reg[47]
(.C(aclk),
.CE(E),
.D(skid_buffer[47]),
.Q(Q[42]),
.R(1'b0));
FDRE \m_payload_i_reg[48]
(.C(aclk),
.CE(E),
.D(skid_buffer[48]),
.Q(Q[43]),
.R(1'b0));
FDRE \m_payload_i_reg[49]
(.C(aclk),
.CE(E),
.D(skid_buffer[49]),
.Q(Q[44]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(E),
.D(skid_buffer[4]),
.Q(Q[4]),
.R(1'b0));
FDRE \m_payload_i_reg[50]
(.C(aclk),
.CE(E),
.D(skid_buffer[50]),
.Q(Q[45]),
.R(1'b0));
FDRE \m_payload_i_reg[51]
(.C(aclk),
.CE(E),
.D(skid_buffer[51]),
.Q(Q[46]),
.R(1'b0));
FDRE \m_payload_i_reg[53]
(.C(aclk),
.CE(E),
.D(skid_buffer[53]),
.Q(Q[47]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(E),
.D(skid_buffer[5]),
.Q(Q[5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(E),
.D(skid_buffer[6]),
.Q(Q[6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(E),
.D(skid_buffer[7]),
.Q(Q[7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(E),
.D(skid_buffer[8]),
.Q(Q[8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(E),
.D(skid_buffer[9]),
.Q(Q[9]),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1
(.I0(b_push),
.I1(m_valid_i_reg_0),
.I2(s_axi_awvalid),
.I3(s_axi_awready),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[1]_inv_0 ));
LUT5 #(
.INIT(32'hFFFFFFFE))
next_pending_r_i_2
(.I0(next_pending_r_reg_0),
.I1(Q[43]),
.I2(Q[44]),
.I3(Q[46]),
.I4(Q[45]),
.O(next_pending_r_reg));
LUT4 #(
.INIT(16'hFFFE))
next_pending_r_i_2__0
(.I0(Q[41]),
.I1(Q[39]),
.I2(Q[40]),
.I3(Q[42]),
.O(next_pending_r_reg_0));
LUT1 #(
.INIT(2'h1))
s_ready_i_i_1__1
(.I0(\aresetn_d_reg_n_0_[0] ),
.O(s_ready_i_reg_0));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_2
(.I0(s_axi_awvalid),
.I1(s_axi_awready),
.I2(b_push),
.I3(m_valid_i_reg_0),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(s_axi_awready),
.R(s_ready_i_reg_0));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[0]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[1]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awprot[2]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[0]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[36]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awsize[1]),
.Q(\skid_buffer_reg_n_0_[36] ),
.R(1'b0));
FDRE \skid_buffer_reg[38]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[0]),
.Q(\skid_buffer_reg_n_0_[38] ),
.R(1'b0));
FDRE \skid_buffer_reg[39]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awburst[1]),
.Q(\skid_buffer_reg_n_0_[39] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[44]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[0]),
.Q(\skid_buffer_reg_n_0_[44] ),
.R(1'b0));
FDRE \skid_buffer_reg[45]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[1]),
.Q(\skid_buffer_reg_n_0_[45] ),
.R(1'b0));
FDRE \skid_buffer_reg[46]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[2]),
.Q(\skid_buffer_reg_n_0_[46] ),
.R(1'b0));
FDRE \skid_buffer_reg[47]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[3]),
.Q(\skid_buffer_reg_n_0_[47] ),
.R(1'b0));
FDRE \skid_buffer_reg[48]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[4]),
.Q(\skid_buffer_reg_n_0_[48] ),
.R(1'b0));
FDRE \skid_buffer_reg[49]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[5]),
.Q(\skid_buffer_reg_n_0_[49] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[50]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[6]),
.Q(\skid_buffer_reg_n_0_[50] ),
.R(1'b0));
FDRE \skid_buffer_reg[51]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awlen[7]),
.Q(\skid_buffer_reg_n_0_[51] ),
.R(1'b0));
FDRE \skid_buffer_reg[53]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awid),
.Q(\skid_buffer_reg_n_0_[53] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(s_axi_awready),
.D(s_axi_awaddr[9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
LUT4 #(
.INIT(16'hAA8A))
\wrap_boundary_axaddr_r[0]_i_1
(.I0(Q[0]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [0]));
LUT5 #(
.INIT(32'h8A888AAA))
\wrap_boundary_axaddr_r[1]_i_1
(.I0(Q[1]),
.I1(Q[36]),
.I2(Q[39]),
.I3(Q[35]),
.I4(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [1]));
LUT6 #(
.INIT(64'h8888028AAAAA028A))
\wrap_boundary_axaddr_r[2]_i_1
(.I0(Q[2]),
.I1(Q[35]),
.I2(Q[41]),
.I3(Q[40]),
.I4(Q[36]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [2]));
LUT6 #(
.INIT(64'h020202A2A2A202A2))
\wrap_boundary_axaddr_r[3]_i_1
(.I0(Q[3]),
.I1(\wrap_boundary_axaddr_r[3]_i_2_n_0 ),
.I2(Q[36]),
.I3(Q[40]),
.I4(Q[35]),
.I5(Q[39]),
.O(\wrap_boundary_axaddr_r_reg[6] [3]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\wrap_boundary_axaddr_r[3]_i_2
(.I0(Q[41]),
.I1(Q[35]),
.I2(Q[42]),
.O(\wrap_boundary_axaddr_r[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h002A222A882AAA2A))
\wrap_boundary_axaddr_r[4]_i_1
(.I0(Q[4]),
.I1(Q[35]),
.I2(Q[42]),
.I3(Q[36]),
.I4(Q[41]),
.I5(Q[40]),
.O(\wrap_boundary_axaddr_r_reg[6] [4]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT5 #(
.INIT(32'h2A222AAA))
\wrap_boundary_axaddr_r[5]_i_1
(.I0(Q[5]),
.I1(Q[36]),
.I2(Q[41]),
.I3(Q[35]),
.I4(Q[42]),
.O(\wrap_boundary_axaddr_r_reg[6] [5]));
LUT4 #(
.INIT(16'h2AAA))
\wrap_boundary_axaddr_r[6]_i_1
(.I0(Q[6]),
.I1(Q[36]),
.I2(Q[42]),
.I3(Q[35]),
.O(\wrap_boundary_axaddr_r_reg[6] [6]));
LUT6 #(
.INIT(64'h00000000EEE222E2))
\wrap_second_len_r[3]_i_2
(.I0(\axaddr_offset_r[2]_i_3_n_0 ),
.I1(Q[35]),
.I2(Q[4]),
.I3(Q[36]),
.I4(Q[6]),
.I5(\axlen_cnt_reg[3] ),
.O(\wrap_second_len_r_reg[3] ));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized1
(s_axi_bvalid,
m_valid_i_reg_0,
s_axi_bid,
s_axi_bresp,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
out,
\s_bresp_acc_reg[1] ,
si_rs_bvalid,
s_axi_bready);
output s_axi_bvalid;
output m_valid_i_reg_0;
output [0:0]s_axi_bid;
output [1:0]s_axi_bresp;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input [0:0]out;
input [1:0]\s_bresp_acc_reg[1] ;
input si_rs_bvalid;
input s_axi_bready;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \m_payload_i[0]_i_1_n_0 ;
wire \m_payload_i[1]_i_1_n_0 ;
wire \m_payload_i[2]_i_1_n_0 ;
wire m_valid_i0;
wire m_valid_i_reg_0;
wire [0:0]out;
wire [0:0]s_axi_bid;
wire s_axi_bready;
wire [1:0]s_axi_bresp;
wire s_axi_bvalid;
wire [1:0]\s_bresp_acc_reg[1] ;
wire s_ready_i0;
wire si_rs_bvalid;
wire [2:0]skid_buffer;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[2] ;
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[0]_i_1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[0] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bresp[0]),
.O(\m_payload_i[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[1]_i_1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[1] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bresp[1]),
.O(\m_payload_i[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'hB8FFB8B8B800B8B8))
\m_payload_i[2]_i_1
(.I0(out),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[2] ),
.I3(s_axi_bready),
.I4(s_axi_bvalid),
.I5(s_axi_bid),
.O(\m_payload_i[2]_i_1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[0]_i_1_n_0 ),
.Q(s_axi_bresp[0]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[1]_i_1_n_0 ),
.Q(s_axi_bresp[1]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(1'b1),
.D(\m_payload_i[2]_i_1_n_0 ),
.Q(s_axi_bid),
.R(1'b0));
LUT4 #(
.INIT(16'hF4FF))
m_valid_i_i_1__0
(.I0(s_axi_bready),
.I1(s_axi_bvalid),
.I2(si_rs_bvalid),
.I3(m_valid_i_reg_0),
.O(m_valid_i0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i0),
.Q(s_axi_bvalid),
.R(\aresetn_d_reg[1]_inv ));
LUT4 #(
.INIT(16'hF4FF))
s_ready_i_i_1
(.I0(si_rs_bvalid),
.I1(m_valid_i_reg_0),
.I2(s_axi_bready),
.I3(s_axi_bvalid),
.O(s_ready_i0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i0),
.Q(m_valid_i_reg_0),
.R(\aresetn_d_reg[0] ));
LUT3 #(
.INIT(8'hB8))
\skid_buffer[0]_i_1
(.I0(\s_bresp_acc_reg[1] [0]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(skid_buffer[0]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\skid_buffer[1]_i_1
(.I0(\s_bresp_acc_reg[1] [1]),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(skid_buffer[1]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\skid_buffer[2]_i_1
(.I0(out),
.I1(m_valid_i_reg_0),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(skid_buffer[2]));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(1'b1),
.D(skid_buffer[2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
endmodule
(* ORIG_REF_NAME = "axi_register_slice_v2_1_14_axic_register_slice" *)
module DemoInterconnect_auto_pc_0_axi_register_slice_v2_1_14_axic_register_slice__parameterized2
(s_axi_rvalid,
\skid_buffer_reg[0]_0 ,
\cnt_read_reg[1] ,
\s_axi_rid[0] ,
\aresetn_d_reg[1]_inv ,
aclk,
\aresetn_d_reg[0] ,
s_axi_rready,
\cnt_read_reg[4]_rep__2 ,
r_push_r_reg,
\cnt_read_reg[4] );
output s_axi_rvalid;
output \skid_buffer_reg[0]_0 ;
output \cnt_read_reg[1] ;
output [35:0]\s_axi_rid[0] ;
input \aresetn_d_reg[1]_inv ;
input aclk;
input \aresetn_d_reg[0] ;
input s_axi_rready;
input \cnt_read_reg[4]_rep__2 ;
input [1:0]r_push_r_reg;
input [33:0]\cnt_read_reg[4] ;
wire aclk;
wire \aresetn_d_reg[0] ;
wire \aresetn_d_reg[1]_inv ;
wire \cnt_read_reg[1] ;
wire [33:0]\cnt_read_reg[4] ;
wire \cnt_read_reg[4]_rep__2 ;
wire \m_payload_i[0]_i_1__1_n_0 ;
wire \m_payload_i[10]_i_1__1_n_0 ;
wire \m_payload_i[11]_i_1__1_n_0 ;
wire \m_payload_i[12]_i_1__1_n_0 ;
wire \m_payload_i[13]_i_1__1_n_0 ;
wire \m_payload_i[14]_i_1__1_n_0 ;
wire \m_payload_i[15]_i_1__1_n_0 ;
wire \m_payload_i[16]_i_1__1_n_0 ;
wire \m_payload_i[17]_i_1__1_n_0 ;
wire \m_payload_i[18]_i_1__1_n_0 ;
wire \m_payload_i[19]_i_1__1_n_0 ;
wire \m_payload_i[1]_i_1__1_n_0 ;
wire \m_payload_i[20]_i_1__1_n_0 ;
wire \m_payload_i[21]_i_1__1_n_0 ;
wire \m_payload_i[22]_i_1__1_n_0 ;
wire \m_payload_i[23]_i_1__1_n_0 ;
wire \m_payload_i[24]_i_1__1_n_0 ;
wire \m_payload_i[25]_i_1__1_n_0 ;
wire \m_payload_i[26]_i_1__1_n_0 ;
wire \m_payload_i[27]_i_1__1_n_0 ;
wire \m_payload_i[28]_i_1__1_n_0 ;
wire \m_payload_i[29]_i_1__1_n_0 ;
wire \m_payload_i[2]_i_1__1_n_0 ;
wire \m_payload_i[30]_i_1__1_n_0 ;
wire \m_payload_i[31]_i_1__1_n_0 ;
wire \m_payload_i[32]_i_1__1_n_0 ;
wire \m_payload_i[33]_i_1__1_n_0 ;
wire \m_payload_i[34]_i_1__1_n_0 ;
wire \m_payload_i[35]_i_2_n_0 ;
wire \m_payload_i[3]_i_1__1_n_0 ;
wire \m_payload_i[4]_i_1__1_n_0 ;
wire \m_payload_i[5]_i_1__1_n_0 ;
wire \m_payload_i[6]_i_1__1_n_0 ;
wire \m_payload_i[7]_i_1__1_n_0 ;
wire \m_payload_i[8]_i_1__1_n_0 ;
wire \m_payload_i[9]_i_1__1_n_0 ;
wire m_valid_i_i_1__2_n_0;
wire p_1_in;
wire [1:0]r_push_r_reg;
wire [35:0]\s_axi_rid[0] ;
wire s_axi_rready;
wire s_axi_rvalid;
wire s_ready_i_i_1__2_n_0;
wire \skid_buffer_reg[0]_0 ;
wire \skid_buffer_reg_n_0_[0] ;
wire \skid_buffer_reg_n_0_[10] ;
wire \skid_buffer_reg_n_0_[11] ;
wire \skid_buffer_reg_n_0_[12] ;
wire \skid_buffer_reg_n_0_[13] ;
wire \skid_buffer_reg_n_0_[14] ;
wire \skid_buffer_reg_n_0_[15] ;
wire \skid_buffer_reg_n_0_[16] ;
wire \skid_buffer_reg_n_0_[17] ;
wire \skid_buffer_reg_n_0_[18] ;
wire \skid_buffer_reg_n_0_[19] ;
wire \skid_buffer_reg_n_0_[1] ;
wire \skid_buffer_reg_n_0_[20] ;
wire \skid_buffer_reg_n_0_[21] ;
wire \skid_buffer_reg_n_0_[22] ;
wire \skid_buffer_reg_n_0_[23] ;
wire \skid_buffer_reg_n_0_[24] ;
wire \skid_buffer_reg_n_0_[25] ;
wire \skid_buffer_reg_n_0_[26] ;
wire \skid_buffer_reg_n_0_[27] ;
wire \skid_buffer_reg_n_0_[28] ;
wire \skid_buffer_reg_n_0_[29] ;
wire \skid_buffer_reg_n_0_[2] ;
wire \skid_buffer_reg_n_0_[30] ;
wire \skid_buffer_reg_n_0_[31] ;
wire \skid_buffer_reg_n_0_[32] ;
wire \skid_buffer_reg_n_0_[33] ;
wire \skid_buffer_reg_n_0_[34] ;
wire \skid_buffer_reg_n_0_[35] ;
wire \skid_buffer_reg_n_0_[3] ;
wire \skid_buffer_reg_n_0_[4] ;
wire \skid_buffer_reg_n_0_[5] ;
wire \skid_buffer_reg_n_0_[6] ;
wire \skid_buffer_reg_n_0_[7] ;
wire \skid_buffer_reg_n_0_[8] ;
wire \skid_buffer_reg_n_0_[9] ;
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT2 #(
.INIT(4'h2))
\cnt_read[3]_i_2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__2 ),
.O(\cnt_read_reg[1] ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[0]_i_1__1
(.I0(\cnt_read_reg[4] [0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[0] ),
.O(\m_payload_i[0]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[10]_i_1__1
(.I0(\cnt_read_reg[4] [10]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[10] ),
.O(\m_payload_i[10]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair86" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[11]_i_1__1
(.I0(\cnt_read_reg[4] [11]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[11] ),
.O(\m_payload_i[11]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[12]_i_1__1
(.I0(\cnt_read_reg[4] [12]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[12] ),
.O(\m_payload_i[12]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair85" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[13]_i_1__1
(.I0(\cnt_read_reg[4] [13]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[13] ),
.O(\m_payload_i[13]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[14]_i_1__1
(.I0(\cnt_read_reg[4] [14]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[14] ),
.O(\m_payload_i[14]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair84" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[15]_i_1__1
(.I0(\cnt_read_reg[4] [15]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[15] ),
.O(\m_payload_i[15]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[16]_i_1__1
(.I0(\cnt_read_reg[4] [16]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[16] ),
.O(\m_payload_i[16]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[17]_i_1__1
(.I0(\cnt_read_reg[4] [17]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[17] ),
.O(\m_payload_i[17]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[18]_i_1__1
(.I0(\cnt_read_reg[4] [18]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[18] ),
.O(\m_payload_i[18]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[19]_i_1__1
(.I0(\cnt_read_reg[4] [19]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[19] ),
.O(\m_payload_i[19]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair91" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[1]_i_1__1
(.I0(\cnt_read_reg[4] [1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[1] ),
.O(\m_payload_i[1]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[20]_i_1__1
(.I0(\cnt_read_reg[4] [20]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[20] ),
.O(\m_payload_i[20]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[21]_i_1__1
(.I0(\cnt_read_reg[4] [21]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[21] ),
.O(\m_payload_i[21]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[22]_i_1__1
(.I0(\cnt_read_reg[4] [22]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[22] ),
.O(\m_payload_i[22]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[23]_i_1__1
(.I0(\cnt_read_reg[4] [23]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[23] ),
.O(\m_payload_i[23]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[24]_i_1__1
(.I0(\cnt_read_reg[4] [24]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[24] ),
.O(\m_payload_i[24]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[25]_i_1__1
(.I0(\cnt_read_reg[4] [25]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[25] ),
.O(\m_payload_i[25]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[26]_i_1__1
(.I0(\cnt_read_reg[4] [26]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[26] ),
.O(\m_payload_i[26]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[27]_i_1__1
(.I0(\cnt_read_reg[4] [27]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[27] ),
.O(\m_payload_i[27]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[28]_i_1__1
(.I0(\cnt_read_reg[4] [28]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[28] ),
.O(\m_payload_i[28]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[29]_i_1__1
(.I0(\cnt_read_reg[4] [29]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[29] ),
.O(\m_payload_i[29]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[2]_i_1__1
(.I0(\cnt_read_reg[4] [2]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[2] ),
.O(\m_payload_i[2]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[30]_i_1__1
(.I0(\cnt_read_reg[4] [30]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[30] ),
.O(\m_payload_i[30]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[31]_i_1__1
(.I0(\cnt_read_reg[4] [31]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[31] ),
.O(\m_payload_i[31]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[32]_i_1__1
(.I0(\cnt_read_reg[4] [32]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[32] ),
.O(\m_payload_i[32]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[33]_i_1__1
(.I0(\cnt_read_reg[4] [33]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[33] ),
.O(\m_payload_i[33]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[34]_i_1__1
(.I0(r_push_r_reg[0]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[34] ),
.O(\m_payload_i[34]_i_1__1_n_0 ));
LUT2 #(
.INIT(4'hB))
\m_payload_i[35]_i_1
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.O(p_1_in));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[35]_i_2
(.I0(r_push_r_reg[1]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[35] ),
.O(\m_payload_i[35]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair90" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[3]_i_1__1
(.I0(\cnt_read_reg[4] [3]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[3] ),
.O(\m_payload_i[3]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[4]_i_1__1
(.I0(\cnt_read_reg[4] [4]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[4] ),
.O(\m_payload_i[4]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair89" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[5]_i_1__1
(.I0(\cnt_read_reg[4] [5]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[5] ),
.O(\m_payload_i[5]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[6]_i_1__1
(.I0(\cnt_read_reg[4] [6]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[6] ),
.O(\m_payload_i[6]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair88" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[7]_i_1__1
(.I0(\cnt_read_reg[4] [7]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[7] ),
.O(\m_payload_i[7]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[8]_i_1__1
(.I0(\cnt_read_reg[4] [8]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[8] ),
.O(\m_payload_i[8]_i_1__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair87" *)
LUT3 #(
.INIT(8'hB8))
\m_payload_i[9]_i_1__1
(.I0(\cnt_read_reg[4] [9]),
.I1(\skid_buffer_reg[0]_0 ),
.I2(\skid_buffer_reg_n_0_[9] ),
.O(\m_payload_i[9]_i_1__1_n_0 ));
FDRE \m_payload_i_reg[0]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[0]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [0]),
.R(1'b0));
FDRE \m_payload_i_reg[10]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[10]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [10]),
.R(1'b0));
FDRE \m_payload_i_reg[11]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[11]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [11]),
.R(1'b0));
FDRE \m_payload_i_reg[12]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[12]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [12]),
.R(1'b0));
FDRE \m_payload_i_reg[13]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[13]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [13]),
.R(1'b0));
FDRE \m_payload_i_reg[14]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[14]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [14]),
.R(1'b0));
FDRE \m_payload_i_reg[15]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[15]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [15]),
.R(1'b0));
FDRE \m_payload_i_reg[16]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[16]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [16]),
.R(1'b0));
FDRE \m_payload_i_reg[17]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[17]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [17]),
.R(1'b0));
FDRE \m_payload_i_reg[18]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[18]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [18]),
.R(1'b0));
FDRE \m_payload_i_reg[19]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[19]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [19]),
.R(1'b0));
FDRE \m_payload_i_reg[1]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[1]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [1]),
.R(1'b0));
FDRE \m_payload_i_reg[20]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[20]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [20]),
.R(1'b0));
FDRE \m_payload_i_reg[21]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[21]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [21]),
.R(1'b0));
FDRE \m_payload_i_reg[22]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[22]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [22]),
.R(1'b0));
FDRE \m_payload_i_reg[23]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[23]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [23]),
.R(1'b0));
FDRE \m_payload_i_reg[24]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[24]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [24]),
.R(1'b0));
FDRE \m_payload_i_reg[25]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[25]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [25]),
.R(1'b0));
FDRE \m_payload_i_reg[26]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[26]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [26]),
.R(1'b0));
FDRE \m_payload_i_reg[27]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[27]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [27]),
.R(1'b0));
FDRE \m_payload_i_reg[28]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[28]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [28]),
.R(1'b0));
FDRE \m_payload_i_reg[29]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[29]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [29]),
.R(1'b0));
FDRE \m_payload_i_reg[2]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[2]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [2]),
.R(1'b0));
FDRE \m_payload_i_reg[30]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[30]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [30]),
.R(1'b0));
FDRE \m_payload_i_reg[31]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[31]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [31]),
.R(1'b0));
FDRE \m_payload_i_reg[32]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[32]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [32]),
.R(1'b0));
FDRE \m_payload_i_reg[33]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[33]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [33]),
.R(1'b0));
FDRE \m_payload_i_reg[34]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[34]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [34]),
.R(1'b0));
FDRE \m_payload_i_reg[35]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[35]_i_2_n_0 ),
.Q(\s_axi_rid[0] [35]),
.R(1'b0));
FDRE \m_payload_i_reg[3]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[3]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [3]),
.R(1'b0));
FDRE \m_payload_i_reg[4]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[4]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [4]),
.R(1'b0));
FDRE \m_payload_i_reg[5]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[5]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [5]),
.R(1'b0));
FDRE \m_payload_i_reg[6]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[6]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [6]),
.R(1'b0));
FDRE \m_payload_i_reg[7]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[7]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [7]),
.R(1'b0));
FDRE \m_payload_i_reg[8]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[8]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [8]),
.R(1'b0));
FDRE \m_payload_i_reg[9]
(.C(aclk),
.CE(p_1_in),
.D(\m_payload_i[9]_i_1__1_n_0 ),
.Q(\s_axi_rid[0] [9]),
.R(1'b0));
LUT4 #(
.INIT(16'h4FFF))
m_valid_i_i_1__2
(.I0(s_axi_rready),
.I1(s_axi_rvalid),
.I2(\skid_buffer_reg[0]_0 ),
.I3(\cnt_read_reg[4]_rep__2 ),
.O(m_valid_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
m_valid_i_reg
(.C(aclk),
.CE(1'b1),
.D(m_valid_i_i_1__2_n_0),
.Q(s_axi_rvalid),
.R(\aresetn_d_reg[1]_inv ));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT4 #(
.INIT(16'hF8FF))
s_ready_i_i_1__2
(.I0(\skid_buffer_reg[0]_0 ),
.I1(\cnt_read_reg[4]_rep__2 ),
.I2(s_axi_rready),
.I3(s_axi_rvalid),
.O(s_ready_i_i_1__2_n_0));
FDRE #(
.INIT(1'b0))
s_ready_i_reg
(.C(aclk),
.CE(1'b1),
.D(s_ready_i_i_1__2_n_0),
.Q(\skid_buffer_reg[0]_0 ),
.R(\aresetn_d_reg[0] ));
FDRE \skid_buffer_reg[0]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [0]),
.Q(\skid_buffer_reg_n_0_[0] ),
.R(1'b0));
FDRE \skid_buffer_reg[10]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [10]),
.Q(\skid_buffer_reg_n_0_[10] ),
.R(1'b0));
FDRE \skid_buffer_reg[11]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [11]),
.Q(\skid_buffer_reg_n_0_[11] ),
.R(1'b0));
FDRE \skid_buffer_reg[12]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [12]),
.Q(\skid_buffer_reg_n_0_[12] ),
.R(1'b0));
FDRE \skid_buffer_reg[13]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [13]),
.Q(\skid_buffer_reg_n_0_[13] ),
.R(1'b0));
FDRE \skid_buffer_reg[14]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [14]),
.Q(\skid_buffer_reg_n_0_[14] ),
.R(1'b0));
FDRE \skid_buffer_reg[15]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [15]),
.Q(\skid_buffer_reg_n_0_[15] ),
.R(1'b0));
FDRE \skid_buffer_reg[16]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [16]),
.Q(\skid_buffer_reg_n_0_[16] ),
.R(1'b0));
FDRE \skid_buffer_reg[17]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [17]),
.Q(\skid_buffer_reg_n_0_[17] ),
.R(1'b0));
FDRE \skid_buffer_reg[18]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [18]),
.Q(\skid_buffer_reg_n_0_[18] ),
.R(1'b0));
FDRE \skid_buffer_reg[19]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [19]),
.Q(\skid_buffer_reg_n_0_[19] ),
.R(1'b0));
FDRE \skid_buffer_reg[1]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [1]),
.Q(\skid_buffer_reg_n_0_[1] ),
.R(1'b0));
FDRE \skid_buffer_reg[20]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [20]),
.Q(\skid_buffer_reg_n_0_[20] ),
.R(1'b0));
FDRE \skid_buffer_reg[21]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [21]),
.Q(\skid_buffer_reg_n_0_[21] ),
.R(1'b0));
FDRE \skid_buffer_reg[22]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [22]),
.Q(\skid_buffer_reg_n_0_[22] ),
.R(1'b0));
FDRE \skid_buffer_reg[23]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [23]),
.Q(\skid_buffer_reg_n_0_[23] ),
.R(1'b0));
FDRE \skid_buffer_reg[24]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [24]),
.Q(\skid_buffer_reg_n_0_[24] ),
.R(1'b0));
FDRE \skid_buffer_reg[25]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [25]),
.Q(\skid_buffer_reg_n_0_[25] ),
.R(1'b0));
FDRE \skid_buffer_reg[26]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [26]),
.Q(\skid_buffer_reg_n_0_[26] ),
.R(1'b0));
FDRE \skid_buffer_reg[27]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [27]),
.Q(\skid_buffer_reg_n_0_[27] ),
.R(1'b0));
FDRE \skid_buffer_reg[28]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [28]),
.Q(\skid_buffer_reg_n_0_[28] ),
.R(1'b0));
FDRE \skid_buffer_reg[29]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [29]),
.Q(\skid_buffer_reg_n_0_[29] ),
.R(1'b0));
FDRE \skid_buffer_reg[2]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [2]),
.Q(\skid_buffer_reg_n_0_[2] ),
.R(1'b0));
FDRE \skid_buffer_reg[30]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [30]),
.Q(\skid_buffer_reg_n_0_[30] ),
.R(1'b0));
FDRE \skid_buffer_reg[31]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [31]),
.Q(\skid_buffer_reg_n_0_[31] ),
.R(1'b0));
FDRE \skid_buffer_reg[32]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [32]),
.Q(\skid_buffer_reg_n_0_[32] ),
.R(1'b0));
FDRE \skid_buffer_reg[33]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [33]),
.Q(\skid_buffer_reg_n_0_[33] ),
.R(1'b0));
FDRE \skid_buffer_reg[34]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[0]),
.Q(\skid_buffer_reg_n_0_[34] ),
.R(1'b0));
FDRE \skid_buffer_reg[35]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(r_push_r_reg[1]),
.Q(\skid_buffer_reg_n_0_[35] ),
.R(1'b0));
FDRE \skid_buffer_reg[3]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [3]),
.Q(\skid_buffer_reg_n_0_[3] ),
.R(1'b0));
FDRE \skid_buffer_reg[4]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [4]),
.Q(\skid_buffer_reg_n_0_[4] ),
.R(1'b0));
FDRE \skid_buffer_reg[5]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [5]),
.Q(\skid_buffer_reg_n_0_[5] ),
.R(1'b0));
FDRE \skid_buffer_reg[6]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [6]),
.Q(\skid_buffer_reg_n_0_[6] ),
.R(1'b0));
FDRE \skid_buffer_reg[7]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [7]),
.Q(\skid_buffer_reg_n_0_[7] ),
.R(1'b0));
FDRE \skid_buffer_reg[8]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [8]),
.Q(\skid_buffer_reg_n_0_[8] ),
.R(1'b0));
FDRE \skid_buffer_reg[9]
(.C(aclk),
.CE(\skid_buffer_reg[0]_0 ),
.D(\cnt_read_reg[4] [9]),
.Q(\skid_buffer_reg_n_0_[9] ),
.R(1'b0));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (strong1, weak0) GSR = GSR_int;
assign (strong1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
module uart(
// Outputs
output wire uart_busy, // High means UART is transmitting
output reg uart_tx, // UART transmit wire
// Inputs
input uart_wr_i, // Raise to transmit byte
input [7:0]uart_dat_i, // 8-bit data
input sys_clk_i, // System clock, 68 MHz
input sys_rst_i // System reset
);
reg [3:0] bitcount;
reg [8:0] shifter;
assign uart_busy = |bitcount[3:1];
assign sending = |bitcount;
// sys_clk_i is 50MHz. We want a 115200Hz clock
reg [28:0] d;
wire [28:0] dInc = d[28] ? (115200) : (115200 - 50000000);
wire [28:0] dNxt = d + dInc;
always @(posedge sys_clk_i)
begin
d = dNxt;
end
wire ser_clk = ~d[28]; // this is the 115200 Hz clock
always @(posedge sys_clk_i)
begin
if (sys_rst_i) begin
uart_tx <= 1;
bitcount <= 0;
shifter <= 0;
end else begin
// just got a new byte
if (uart_wr_i & ~uart_busy) begin
shifter <= { uart_dat_i[7:0], 1'h0 };
bitcount <= (1 + 8 + 2);
end
if (sending & ser_clk) begin
{ shifter, uart_tx } <= { 1'h1, shifter };
bitcount <= bitcount - 1;
end
end
end
endmodule |
//Legal Notice: (C)2017 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module soc_design_timer_0 (
// inputs:
address,
chipselect,
clk,
reset_n,
write_n,
writedata,
// outputs:
irq,
readdata
)
;
output irq;
output [ 15: 0] readdata;
input [ 2: 0] address;
input chipselect;
input clk;
input reset_n;
input write_n;
input [ 15: 0] writedata;
wire clk_en;
wire control_interrupt_enable;
reg control_register;
wire control_wr_strobe;
reg counter_is_running;
wire counter_is_zero;
wire [ 16: 0] counter_load_value;
reg delayed_unxcounter_is_zeroxx0;
wire do_start_counter;
wire do_stop_counter;
reg force_reload;
reg [ 16: 0] internal_counter;
wire irq;
wire period_h_wr_strobe;
wire period_l_wr_strobe;
wire [ 15: 0] read_mux_out;
reg [ 15: 0] readdata;
wire status_wr_strobe;
wire timeout_event;
reg timeout_occurred;
assign clk_en = 1;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
internal_counter <= 17'h1869F;
else if (counter_is_running || force_reload)
if (counter_is_zero || force_reload)
internal_counter <= counter_load_value;
else
internal_counter <= internal_counter - 1;
end
assign counter_is_zero = internal_counter == 0;
assign counter_load_value = 17'h1869F;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
force_reload <= 0;
else if (clk_en)
force_reload <= period_h_wr_strobe || period_l_wr_strobe;
end
assign do_start_counter = 1;
assign do_stop_counter = 0;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
counter_is_running <= 1'b0;
else if (clk_en)
if (do_start_counter)
counter_is_running <= -1;
else if (do_stop_counter)
counter_is_running <= 0;
end
//delayed_unxcounter_is_zeroxx0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
delayed_unxcounter_is_zeroxx0 <= 0;
else if (clk_en)
delayed_unxcounter_is_zeroxx0 <= counter_is_zero;
end
assign timeout_event = (counter_is_zero) & ~(delayed_unxcounter_is_zeroxx0);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
timeout_occurred <= 0;
else if (clk_en)
if (status_wr_strobe)
timeout_occurred <= 0;
else if (timeout_event)
timeout_occurred <= -1;
end
assign irq = timeout_occurred && control_interrupt_enable;
//s1, which is an e_avalon_slave
assign read_mux_out = ({16 {(address == 1)}} & control_register) |
({16 {(address == 0)}} & {counter_is_running,
timeout_occurred});
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
readdata <= 0;
else if (clk_en)
readdata <= read_mux_out;
end
assign period_l_wr_strobe = chipselect && ~write_n && (address == 2);
assign period_h_wr_strobe = chipselect && ~write_n && (address == 3);
assign control_wr_strobe = chipselect && ~write_n && (address == 1);
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
control_register <= 0;
else if (control_wr_strobe)
control_register <= writedata[0];
end
assign control_interrupt_enable = control_register;
assign status_wr_strobe = chipselect && ~write_n && (address == 0);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized OR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_carry_latch_or #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire I,
output wire O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign O = CIN | I;
end else begin : USE_FPGA
OR2L or2l_inst1
(
.O(O),
.DI(CIN),
.SRI(I)
);
end
endgenerate
endmodule
|
// EE 471 Lab 1, Beck Pang, Spring 2015
// Main function for calling different counter onto the board
// @require: only call one counter a time
module DE1_SoCRegTest (CLOCK_50, LEDR, SW, KEY);
input CLOCK_50; // connect to system 50 MHz clock
output reg [9:0] LEDR;
input [9:0] SW;
input [3:0] KEY;
wire clk;
reg [6:0] hold;
reg regWR;
wire [1:0] slowClk;
wire clkControl, rst, enterLow, enterHigh;
reg [4:0] readAdd0, readAdd1, writeAdd;
reg [31:0] writeData;
//reg [
wire [31:0] readOutput0, readOutput1;
//reg [15:0] data;
//assign data[6:0] <= SW[6:0]
assign clkControl = SW[8];
assign enterLow = SW[7];
assign enterHigh = SW[6];
assign rst = SW[9];
clkSlower counter(slowClk, CLOCK_50, rst);
registerFile regs(clk, readAdd0, readAdd1, writeAdd, regWR, writeData, readOutput0, readOutput1);
always @(posedge clk) begin
if(rst) begin
hold <= 0;
regWR <= 1;
LEDR <= 0;
end else if(enterLow) begin
regWR <= 0;
writeData <= 32'hFFFF0000 + hold[3:0];
writeAdd <= hold[3:0];
end else if(enterHigh) begin
regWR <= 0;
writeData <= 32'h0000FFF0 + hold[3:0];
writeAdd <= 5'b10000 + hold[3:0];
end else begin
regWR <= 1;
readAdd0 <= hold[3:0];
readAdd1 <= 16 + hold[3:0];
LEDR[7:0] <= KEY[0] ? readOutput1[7:0] : readOutput0[7:0];
end
hold <= hold + 1'b1;
end
assign clk = clkControl ? slowClk[0] : slowClk[1];
endmodule |
`timescale 1ns/10ps
/**
* `timescale time_unit base / precision base
*
* -Specifies the time units and precision for delays:
* -time_unit is the amount of time a delay of 1 represents.
* The time unit must be 1 10 or 100
* -base is the time base for each unit, ranging from seconds
* to femtoseconds, and must be: s ms us ns ps or fs
* -precision and base represent how many decimal points of
* precision to use relative to the time units.
*/
/**
* This is written by Zhiyang Ong
* for EE577b Homework 4, Question 2
*/
/**
* Testbench for behavioral model for Finite State Machine model of the
* PISO convertor
*/
// Import the modules that will be tested for in this testbench
`include "piso.v"
// IMPORTANT: To run this, try: ncverilog -f piso.f +gui
module tb_piso();
/**
* Declare signal types for testbench to drive and monitor
* signals during the simulation of the PISO convertor
*
* The reg data type holds a value until a new value is driven
* onto it in an "initial" or "always" block. It can only be
* assigned a value in an "always" or "initial" block, and is
* used to apply stimulus to the inputs of the DUT.
*
* The wire type is a passive data type that holds a value driven
* onto it by a port, assign statement or reg type. Wires cannot be
* assigned values inside "always" and "initial" blocks. They can
* be used to hold the values of the DUT's outputs
*/
// Declare "wire" signals: outputs from the DUT
// serial_out & out_valid output signals
wire s_out,valid_op;
// ============================================================
// Declare "reg" signals: inputs to the DUT
// load, clk, & reset_b
reg load_en,clock,reset_low;
reg [7:0] data_input;
// ============================================================
// Counter for loop to enumerate all the values of r
//integer count;
// ============================================================
/**
* Each sequential control block, such as the initial or always
* block, will execute concurrently in every module at the start
* of the simulation
*/
always begin
// Clock frequency is arbitrarily chosen; Period=10ns
#5 clock = 0;
#5 clock = 1;
end
// ============================================================
/**
* Instantiate an instance of ee577bHw1q5model1() so that
* inputs can be passed to the Device Under Test (DUT)
* Given instance name is "xor1model"
*/
PISO pisoc (
// instance_name(signal name),
// Signal name can be the same as the instance name
s_out,valid_op,data_input,load_en,reset_low,clock);
// ============================================================
/**
* Initial block start executing sequentially @ t=0
* If and when a delay is encountered, the execution of this block
* pauses or waits until the delay time has passed, before resuming
* execution
*
* Each intial or always block executes concurrently; that is,
* multiple "always" or "initial" blocks will execute simultaneously
*
* E.g.
* always
* begin
* #10 clk_50 = ~clk_50; // Invert clock signal every 10 ns
* // Clock signal has a period of 20 ns or 50 MHz
* end
*/
initial
begin
// "$time" indicates the current time in the simulation
$display($time, " << Starting the simulation >>");
// @ t=0; reset the sequence detector
reset_low=1'd0;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd13;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd6;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd5;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd7;
#40 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd3;
#30 // Reset the data again
reset_low=1'd0;
load_en=1'd1;
data_input=8'd2;
#20
reset_low=1'd1;
load_en=1'd1;
data_input=8'd15;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd9;
#70 // Ignored input data
reset_low=1'd1;
load_en=1'd1;
data_input=8'd14;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd12;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd10;
#90
reset_low=1'd1;
load_en=1'd0;
data_input=8'd236;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd174;
#90
reset_low=1'd1;
load_en=1'd1;
data_input=8'd214;
#120
// end simulation
#30
$display($time, " << Finishing the simulation >>");
$finish;
end
endmodule
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (win64) Build 1577090 Thu Jun 2 16:32:40 MDT 2016
// Date : Mon Sep 12 13:26:35 2016
// Host : RDS1 running 64-bit major release (build 9200)
// Command : write_verilog -mode timesim -nolib -sdf_anno true -force -file
// C:/Users/jsequeira/Documents/Floating-Point-Unit-master/FPU_Add_subt_Mult/project_1/project_1.sim/sim_1/synth/timing/Testbench_FPU_Add_Subt_time_synth.v
// Design : FPU_Add_Subtract_Function
// Purpose : This verilog netlist is a timing simulation representation of the design and should not be modified or
// synthesized. Please ensure that this netlist is used with the corresponding SDF file.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
`define XIL_TIMING
module Add_Subt
(add_overflow_flag,
D,
\Q_reg[18] ,
\Q_reg[16] ,
\Q_reg[17] ,
\Q_reg[15] ,
Q,
\Q_reg[4] ,
S,
\Q_reg[7] ,
\Q_reg[11] ,
\Q_reg[15]_0 ,
\Q_reg[19] ,
\Q_reg[23] ,
\Q_reg[0] ,
E,
O,
CLK,
AR,
FSM_barrel_shifter_B_S,
\Q_reg[2] ,
\Q_reg[1] ,
\Q_reg[0]_0 ,
FSM_selector_C,
FSM_barrel_shifter_L_R,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
FSM_selector_B,
\Q_reg[0]_3 ,
\Q_reg[22] ,
\Q_reg[31] ,
\Q_reg[31]_0 ,
intAS,
\Q_reg[31]_1 ,
\Q_reg[25] ,
FSM_selector_D,
\Q_reg[22]_0 );
output add_overflow_flag;
output [20:0]D;
output \Q_reg[18] ;
output \Q_reg[16] ;
output \Q_reg[17] ;
output \Q_reg[15] ;
output [1:0]Q;
output [4:0]\Q_reg[4] ;
output [3:0]S;
output [3:0]\Q_reg[7] ;
output [3:0]\Q_reg[11] ;
output [3:0]\Q_reg[15]_0 ;
output [3:0]\Q_reg[19] ;
output [3:0]\Q_reg[23] ;
output [1:0]\Q_reg[0] ;
input [0:0]E;
input [2:0]O;
input CLK;
input [0:0]AR;
input FSM_barrel_shifter_B_S;
input \Q_reg[2] ;
input \Q_reg[1] ;
input \Q_reg[0]_0 ;
input FSM_selector_C;
input FSM_barrel_shifter_L_R;
input \Q_reg[0]_1 ;
input [0:0]\Q_reg[0]_2 ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_3 ;
input [22:0]\Q_reg[22] ;
input [23:0]\Q_reg[31] ;
input [0:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]\Q_reg[31]_1 ;
input [25:0]\Q_reg[25] ;
input FSM_selector_D;
input [22:0]\Q_reg[22]_0 ;
wire [0:0]AR;
wire CLK;
wire [20:0]D;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire [2:0]O;
wire [1:0]Q;
wire [1:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire [3:0]\Q_reg[11] ;
wire \Q_reg[15] ;
wire [3:0]\Q_reg[15]_0 ;
wire \Q_reg[16] ;
wire \Q_reg[17] ;
wire \Q_reg[18] ;
wire [3:0]\Q_reg[19] ;
wire \Q_reg[1] ;
wire [22:0]\Q_reg[22] ;
wire [22:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[23] ;
wire [25:0]\Q_reg[25] ;
wire \Q_reg[2] ;
wire [23:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [0:0]\Q_reg[31]_1 ;
wire [4:0]\Q_reg[4] ;
wire [3:0]\Q_reg[7] ;
wire [3:0]S;
wire add_overflow_flag;
wire intAS;
RegisterAdd__parameterized8 Add_Subt_Result
(.AR(AR),
.CLK(CLK),
.D(D),
.E(E),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_selector_B(FSM_selector_B),
.FSM_selector_C(FSM_selector_C),
.Q(Q),
.\Q_reg[0]_0 (\Q_reg[0]_0 ),
.\Q_reg[0]_1 (\Q_reg[0]_1 ),
.\Q_reg[0]_2 (\Q_reg[0]_2 ),
.\Q_reg[0]_3 (\Q_reg[0]_3 ),
.\Q_reg[15]_0 (\Q_reg[15] ),
.\Q_reg[16]_0 (\Q_reg[16] ),
.\Q_reg[17]_0 (\Q_reg[17] ),
.\Q_reg[18]_0 (\Q_reg[18] ),
.\Q_reg[1]_0 (\Q_reg[1] ),
.\Q_reg[22]_0 (\Q_reg[22] ),
.\Q_reg[2]_0 (\Q_reg[2] ),
.\Q_reg[31] ({O[1:0],\Q_reg[31] }),
.\Q_reg[4]_0 (\Q_reg[4] ));
RegisterAdd_6 Add_overflow_Result
(.AR(AR),
.CLK(CLK),
.E(E),
.O(O[2]),
.add_overflow_flag(add_overflow_flag));
add_sub_carry_out__parameterized0 Sgf_AS
(.FSM_selector_D(FSM_selector_D),
.\Q_reg[0] (\Q_reg[0] ),
.\Q_reg[11] (\Q_reg[11] ),
.\Q_reg[15] (\Q_reg[15]_0 ),
.\Q_reg[19] (\Q_reg[19] ),
.\Q_reg[22] (\Q_reg[22]_0 ),
.\Q_reg[23] (\Q_reg[23] ),
.\Q_reg[25] (\Q_reg[25] ),
.\Q_reg[31] (\Q_reg[31]_0 ),
.\Q_reg[31]_0 (\Q_reg[31]_1 ),
.\Q_reg[7] (\Q_reg[7] ),
.S(S),
.intAS(intAS));
endmodule
module Barrel_Shifter
(\Q_reg[16] ,
Q,
\Q_reg[25] ,
\Q_reg[17] ,
\Q_reg[24] ,
\Q_reg[18] ,
\Q_reg[23] ,
\Q_reg[19] ,
\Q_reg[22] ,
\Q_reg[20] ,
\Q_reg[21] ,
round_flag,
\Q_reg[0] ,
D,
FSM_barrel_shifter_L_R,
\Q_reg[16]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[4] ,
\Q_reg[3] ,
\Q_reg[17]_0 ,
r_mode_IBUF,
sign_final_result,
E,
CLK,
AR,
\Q_reg[2] ,
\FSM_sequential_state_reg_reg[3] );
output \Q_reg[16] ;
output [15:0]Q;
output \Q_reg[25] ;
output \Q_reg[17] ;
output \Q_reg[24] ;
output \Q_reg[18] ;
output \Q_reg[23] ;
output \Q_reg[19] ;
output \Q_reg[22] ;
output \Q_reg[20] ;
output \Q_reg[21] ;
output round_flag;
output [25:0]\Q_reg[0] ;
input [15:0]D;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4] ;
input \Q_reg[3] ;
input \Q_reg[17]_0 ;
input [1:0]r_mode_IBUF;
input sign_final_result;
input [0:0]E;
input CLK;
input [0:0]AR;
input [25:0]\Q_reg[2] ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]AR;
wire CLK;
wire [15:0]D;
wire [25:16]Data_Reg;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire [25:0]\Q_reg[0] ;
wire \Q_reg[16] ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17] ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire \Q_reg[25] ;
wire [25:0]\Q_reg[2] ;
wire \Q_reg[3] ;
wire \Q_reg[4] ;
wire [1:0]r_mode_IBUF;
wire round_flag;
wire sign_final_result;
Mux_Array Mux_Array
(.CLK(CLK),
.D(Data_Reg),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q),
.\Q_reg[16] (\Q_reg[16] ),
.\Q_reg[16]_0 (\Q_reg[16]_0 ),
.\Q_reg[17] (\Q_reg[17] ),
.\Q_reg[17]_0 (\Q_reg[17]_0 ),
.\Q_reg[18] (\Q_reg[18] ),
.\Q_reg[19] (\Q_reg[19] ),
.\Q_reg[20] (\Q_reg[20] ),
.\Q_reg[21] (\Q_reg[21] ),
.\Q_reg[22] (\Q_reg[22] ),
.\Q_reg[23] (\Q_reg[23] ),
.\Q_reg[24] (\Q_reg[24] ),
.\Q_reg[25] (\Q_reg[25] ),
.\Q_reg[2] (\Q_reg[2] ),
.\Q_reg[3] (\Q_reg[3] ),
.\Q_reg[4] (\Q_reg[4] ));
RegisterAdd__parameterized7 Output_Reg
(.AR(AR),
.CLK(CLK),
.D({Data_Reg,D}),
.E(E),
.\Q_reg[0]_0 (\Q_reg[0] ),
.r_mode_IBUF(r_mode_IBUF),
.round_flag(round_flag),
.sign_final_result(sign_final_result));
endmodule
module Comparator
(CO,
\Q_reg[0] ,
zero_flag,
DI,
S,
\Q_reg[15] ,
\Q_reg[15]_0 ,
\Q_reg[23] ,
\Q_reg[23]_0 ,
\Q_reg[30] ,
\Q_reg[30]_0 ,
\Q_reg[10] ,
\Q_reg[22] ,
\Q_reg[30]_1 ,
Q,
\Q_reg[0]_0 ,
\Q_reg[31] );
output [0:0]CO;
output [0:0]\Q_reg[0] ;
output zero_flag;
input [3:0]DI;
input [3:0]S;
input [3:0]\Q_reg[15] ;
input [3:0]\Q_reg[15]_0 ;
input [3:0]\Q_reg[23] ;
input [3:0]\Q_reg[23]_0 ;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[30]_0 ;
input [3:0]\Q_reg[10] ;
input [3:0]\Q_reg[22] ;
input [2:0]\Q_reg[30]_1 ;
input [0:0]Q;
input \Q_reg[0]_0 ;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [3:0]DI;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire [3:0]\Q_reg[10] ;
wire [3:0]\Q_reg[15] ;
wire [3:0]\Q_reg[15]_0 ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[23] ;
wire [3:0]\Q_reg[23]_0 ;
wire [3:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [2:0]\Q_reg[30]_1 ;
wire [0:0]\Q_reg[31] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire zero_flag;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
LUT4 #(
.INIT(16'h8228))
\FSM_sequential_state_reg[2]_i_3
(.I0(\Q_reg[0] ),
.I1(Q),
.I2(\Q_reg[0]_0 ),
.I3(\Q_reg[31] ),
.O(zero_flag));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[10] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[22] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[0] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_1 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[15] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[15]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[23] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[23]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[30] ),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30]_0 ));
endmodule
module Exp_Operation
(overflow_flag_OBUF,
underflow_flag_OBUF,
D,
Q,
Data_A,
\Q_reg[0] ,
S,
\Q_reg[3] ,
E,
CLK,
AR,
\Q_reg[0]_0 ,
sign_final_result,
\Q_reg[24] ,
\Q_reg[0]_1 ,
\Q_reg[30] ,
O,
\Q_reg[1] ,
\Q_reg[30]_0 ,
\Q_reg[1]_0 ,
FSM_exp_operation_A_S,
DI,
\Q_reg[26] ,
FSM_selector_B,
\Q_reg[0]_2 );
output overflow_flag_OBUF;
output underflow_flag_OBUF;
output [31:0]D;
output [4:0]Q;
output [0:0]Data_A;
output \Q_reg[0] ;
output [3:0]S;
output [3:0]\Q_reg[3] ;
input [0:0]E;
input CLK;
input [0:0]AR;
input \Q_reg[0]_0 ;
input sign_final_result;
input [22:0]\Q_reg[24] ;
input \Q_reg[0]_1 ;
input [7:0]\Q_reg[30] ;
input [0:0]O;
input [7:0]\Q_reg[1] ;
input [3:0]\Q_reg[30]_0 ;
input \Q_reg[1]_0 ;
input FSM_exp_operation_A_S;
input [0:0]DI;
input [2:0]\Q_reg[26] ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_2 ;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]DI;
wire [0:0]Data_A;
wire [0:0]E;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [0:0]O;
wire [4:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [7:0]\Q_reg[1] ;
wire \Q_reg[1]_0 ;
wire [22:0]\Q_reg[24] ;
wire [2:0]\Q_reg[26] ;
wire [7:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[3] ;
wire [3:0]S;
wire exp_result_n_10;
wire exp_result_n_8;
wire exp_result_n_9;
wire overflow_flag_OBUF;
wire sign_final_result;
wire underflow_flag_OBUF;
RegisterAdd_4 Overflow
(.AR(AR),
.CLK(CLK),
.D(D[22:0]),
.E(E),
.O(O),
.\Q_reg[0]_0 (underflow_flag_OBUF),
.\Q_reg[1] (\Q_reg[1] ),
.\Q_reg[22] (overflow_flag_OBUF),
.\Q_reg[24] (\Q_reg[24] ));
RegisterAdd_5 Underflow
(.AR(AR),
.CLK(CLK),
.D(D[31]),
.O(O),
.\Q_reg[0]_0 (\Q_reg[0] ),
.\Q_reg[0]_1 (\Q_reg[0]_0 ),
.\Q_reg[0]_2 (overflow_flag_OBUF),
.\Q_reg[1] ({\Q_reg[1] [7],\Q_reg[1] [4],\Q_reg[1] [2:0]}),
.\Q_reg[31] (underflow_flag_OBUF),
.sign_final_result(sign_final_result));
add_sub_carry_out exp_add_subt
(.DI(DI),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.Q({exp_result_n_8,exp_result_n_9,exp_result_n_10,Q[4:1]}),
.\Q_reg[0] (\Q_reg[0]_1 ),
.\Q_reg[0]_0 (\Q_reg[0]_2 ),
.\Q_reg[1] (\Q_reg[1]_0 ),
.\Q_reg[26] (\Q_reg[26] ),
.\Q_reg[30] (\Q_reg[30]_0 ),
.\Q_reg[30]_0 (\Q_reg[30] [7:1]),
.\Q_reg[3] (\Q_reg[3] ),
.S(S));
RegisterAdd__parameterized5 exp_result
(.AR(AR),
.CLK(CLK),
.D(D[30:23]),
.Data_A(Data_A),
.E(E),
.Q({exp_result_n_8,exp_result_n_9,exp_result_n_10,Q}),
.\Q_reg[0]_0 (overflow_flag_OBUF),
.\Q_reg[0]_1 (underflow_flag_OBUF),
.\Q_reg[0]_2 (\Q_reg[0]_1 ),
.\Q_reg[1]_0 (\Q_reg[1] ),
.\Q_reg[23] (\Q_reg[30] [0]));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_Add_Subtract_Function
(clk,
rst,
beg_FSM,
ack_FSM,
Data_X,
Data_Y,
add_subt,
r_mode,
overflow_flag,
underflow_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_FSM;
input ack_FSM;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
input [1:0]r_mode;
output overflow_flag;
output underflow_flag;
output ready;
output [31:0]final_result_ieee;
wire Add_Subt_Sgf_module_n_22;
wire Add_Subt_Sgf_module_n_23;
wire Add_Subt_Sgf_module_n_24;
wire Add_Subt_Sgf_module_n_25;
wire Add_Subt_Sgf_module_n_26;
wire Add_Subt_Sgf_module_n_27;
wire Add_Subt_Sgf_module_n_33;
wire Add_Subt_Sgf_module_n_34;
wire Add_Subt_Sgf_module_n_35;
wire Add_Subt_Sgf_module_n_36;
wire Add_Subt_Sgf_module_n_37;
wire Add_Subt_Sgf_module_n_38;
wire Add_Subt_Sgf_module_n_39;
wire Add_Subt_Sgf_module_n_40;
wire Add_Subt_Sgf_module_n_41;
wire Add_Subt_Sgf_module_n_42;
wire Add_Subt_Sgf_module_n_43;
wire Add_Subt_Sgf_module_n_44;
wire Add_Subt_Sgf_module_n_45;
wire Add_Subt_Sgf_module_n_46;
wire Add_Subt_Sgf_module_n_47;
wire Add_Subt_Sgf_module_n_48;
wire Add_Subt_Sgf_module_n_49;
wire Add_Subt_Sgf_module_n_50;
wire Add_Subt_Sgf_module_n_51;
wire Add_Subt_Sgf_module_n_52;
wire Add_Subt_Sgf_module_n_53;
wire Add_Subt_Sgf_module_n_54;
wire Add_Subt_Sgf_module_n_55;
wire Add_Subt_Sgf_module_n_56;
wire Add_Subt_Sgf_module_n_57;
wire Add_Subt_Sgf_module_n_58;
wire Barrel_Shifter_module_n_0;
wire Barrel_Shifter_module_n_17;
wire Barrel_Shifter_module_n_18;
wire Barrel_Shifter_module_n_19;
wire Barrel_Shifter_module_n_20;
wire Barrel_Shifter_module_n_21;
wire Barrel_Shifter_module_n_22;
wire Barrel_Shifter_module_n_23;
wire Barrel_Shifter_module_n_24;
wire Barrel_Shifter_module_n_25;
wire Barrel_Shifter_module_n_27;
wire Barrel_Shifter_module_n_28;
wire Barrel_Shifter_module_n_29;
wire Barrel_Shifter_module_n_30;
wire Barrel_Shifter_module_n_31;
wire Barrel_Shifter_module_n_32;
wire Barrel_Shifter_module_n_33;
wire Barrel_Shifter_module_n_34;
wire Barrel_Shifter_module_n_35;
wire Barrel_Shifter_module_n_36;
wire Barrel_Shifter_module_n_37;
wire Barrel_Shifter_module_n_38;
wire Barrel_Shifter_module_n_39;
wire Barrel_Shifter_module_n_40;
wire Barrel_Shifter_module_n_41;
wire Barrel_Shifter_module_n_42;
wire Barrel_Shifter_module_n_43;
wire Barrel_Shifter_module_n_44;
wire Barrel_Shifter_module_n_45;
wire Barrel_Shifter_module_n_46;
wire Barrel_Shifter_module_n_47;
wire Barrel_Shifter_module_n_48;
wire Barrel_Shifter_module_n_49;
wire Barrel_Shifter_module_n_50;
wire [4:0]Codec_to_Reg;
wire [0:0]Data_A;
wire [15:0]Data_Reg;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire Exp_Operation_Module_n_10;
wire Exp_Operation_Module_n_11;
wire Exp_Operation_Module_n_12;
wire Exp_Operation_Module_n_13;
wire Exp_Operation_Module_n_14;
wire Exp_Operation_Module_n_15;
wire Exp_Operation_Module_n_16;
wire Exp_Operation_Module_n_17;
wire Exp_Operation_Module_n_18;
wire Exp_Operation_Module_n_19;
wire Exp_Operation_Module_n_20;
wire Exp_Operation_Module_n_21;
wire Exp_Operation_Module_n_22;
wire Exp_Operation_Module_n_23;
wire Exp_Operation_Module_n_24;
wire Exp_Operation_Module_n_25;
wire Exp_Operation_Module_n_26;
wire Exp_Operation_Module_n_27;
wire Exp_Operation_Module_n_28;
wire Exp_Operation_Module_n_29;
wire Exp_Operation_Module_n_3;
wire Exp_Operation_Module_n_30;
wire Exp_Operation_Module_n_31;
wire Exp_Operation_Module_n_32;
wire Exp_Operation_Module_n_33;
wire Exp_Operation_Module_n_4;
wire Exp_Operation_Module_n_40;
wire Exp_Operation_Module_n_41;
wire Exp_Operation_Module_n_42;
wire Exp_Operation_Module_n_43;
wire Exp_Operation_Module_n_44;
wire Exp_Operation_Module_n_45;
wire Exp_Operation_Module_n_46;
wire Exp_Operation_Module_n_47;
wire Exp_Operation_Module_n_48;
wire Exp_Operation_Module_n_5;
wire Exp_Operation_Module_n_6;
wire Exp_Operation_Module_n_7;
wire Exp_Operation_Module_n_8;
wire Exp_Operation_Module_n_9;
wire FSM_Add_Subt_Sgf_load;
wire FSM_LZA_load;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_barrel_shifter_load;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_diff;
wire FSM_op_start_in_load_a;
wire FSM_op_start_in_load_b;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire FSM_selector_D;
wire FS_Module_n_10;
wire FS_Module_n_11;
wire FS_Module_n_12;
wire FS_Module_n_13;
wire FS_Module_n_2;
wire FS_Module_n_23;
wire FS_Module_n_24;
wire FS_Module_n_25;
wire FS_Module_n_5;
wire FS_Module_n_6;
wire FS_Module_n_7;
wire FS_Module_n_8;
wire FS_Module_n_9;
wire [4:0]LZA_output;
wire [25:0]\Mux_Array/Data_array[3]_0 ;
wire [25:10]\Mux_Array/Data_array[4]_1 ;
wire Oper_Start_in_module_n_10;
wire Oper_Start_in_module_n_11;
wire Oper_Start_in_module_n_12;
wire Oper_Start_in_module_n_13;
wire Oper_Start_in_module_n_14;
wire Oper_Start_in_module_n_15;
wire Oper_Start_in_module_n_16;
wire Oper_Start_in_module_n_17;
wire Oper_Start_in_module_n_18;
wire Oper_Start_in_module_n_19;
wire Oper_Start_in_module_n_20;
wire Oper_Start_in_module_n_21;
wire Oper_Start_in_module_n_22;
wire Oper_Start_in_module_n_23;
wire Oper_Start_in_module_n_24;
wire Oper_Start_in_module_n_25;
wire Oper_Start_in_module_n_26;
wire Oper_Start_in_module_n_27;
wire Oper_Start_in_module_n_28;
wire Oper_Start_in_module_n_29;
wire Oper_Start_in_module_n_3;
wire Oper_Start_in_module_n_33;
wire Oper_Start_in_module_n_34;
wire Oper_Start_in_module_n_35;
wire Oper_Start_in_module_n_36;
wire Oper_Start_in_module_n_37;
wire Oper_Start_in_module_n_38;
wire Oper_Start_in_module_n_39;
wire Oper_Start_in_module_n_4;
wire Oper_Start_in_module_n_40;
wire Oper_Start_in_module_n_41;
wire Oper_Start_in_module_n_42;
wire Oper_Start_in_module_n_43;
wire Oper_Start_in_module_n_44;
wire Oper_Start_in_module_n_45;
wire Oper_Start_in_module_n_46;
wire Oper_Start_in_module_n_47;
wire Oper_Start_in_module_n_48;
wire Oper_Start_in_module_n_49;
wire Oper_Start_in_module_n_5;
wire Oper_Start_in_module_n_50;
wire Oper_Start_in_module_n_51;
wire Oper_Start_in_module_n_52;
wire Oper_Start_in_module_n_53;
wire Oper_Start_in_module_n_54;
wire Oper_Start_in_module_n_55;
wire Oper_Start_in_module_n_56;
wire Oper_Start_in_module_n_57;
wire Oper_Start_in_module_n_58;
wire Oper_Start_in_module_n_59;
wire Oper_Start_in_module_n_6;
wire Oper_Start_in_module_n_60;
wire Oper_Start_in_module_n_61;
wire Oper_Start_in_module_n_62;
wire Oper_Start_in_module_n_63;
wire Oper_Start_in_module_n_64;
wire Oper_Start_in_module_n_65;
wire Oper_Start_in_module_n_66;
wire Oper_Start_in_module_n_67;
wire Oper_Start_in_module_n_68;
wire Oper_Start_in_module_n_69;
wire Oper_Start_in_module_n_7;
wire Oper_Start_in_module_n_70;
wire Oper_Start_in_module_n_71;
wire Oper_Start_in_module_n_72;
wire Oper_Start_in_module_n_73;
wire Oper_Start_in_module_n_74;
wire Oper_Start_in_module_n_75;
wire Oper_Start_in_module_n_76;
wire Oper_Start_in_module_n_77;
wire Oper_Start_in_module_n_78;
wire Oper_Start_in_module_n_79;
wire Oper_Start_in_module_n_8;
wire Oper_Start_in_module_n_80;
wire Oper_Start_in_module_n_81;
wire Oper_Start_in_module_n_82;
wire Oper_Start_in_module_n_83;
wire Oper_Start_in_module_n_84;
wire Oper_Start_in_module_n_85;
wire Oper_Start_in_module_n_86;
wire Oper_Start_in_module_n_87;
wire Oper_Start_in_module_n_88;
wire Oper_Start_in_module_n_89;
wire Oper_Start_in_module_n_9;
wire Oper_Start_in_module_n_90;
wire Oper_Start_in_module_n_91;
wire Oper_Start_in_module_n_92;
wire Oper_Start_in_module_n_93;
wire Oper_Start_in_module_n_94;
wire Oper_Start_in_module_n_95;
wire Sel_A_n_0;
wire Sel_B_n_0;
wire Sel_B_n_1;
wire Sel_B_n_10;
wire Sel_B_n_11;
wire Sel_B_n_12;
wire Sel_B_n_16;
wire Sel_B_n_17;
wire Sel_B_n_2;
wire Sel_B_n_3;
wire Sel_B_n_34;
wire Sel_B_n_35;
wire Sel_B_n_36;
wire Sel_B_n_37;
wire Sel_B_n_4;
wire Sel_B_n_40;
wire Sel_B_n_41;
wire Sel_B_n_5;
wire Sel_B_n_6;
wire Sel_B_n_7;
wire Sel_B_n_8;
wire Sel_B_n_9;
wire Sel_D_n_1;
wire [1:0]Sgf_normalized_result;
wire Sign_S_mux;
wire ack_FSM;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire add_subt;
wire add_subt_IBUF;
wire beg_FSM;
wire beg_FSM_IBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire eqXY;
wire [4:0]exp_oper_result;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire intAS;
wire [31:31]intDX;
wire [31:31]intDY;
wire overflow_flag;
wire overflow_flag_OBUF;
wire [1:0]r_mode;
wire [1:0]r_mode_IBUF;
wire ready;
wire ready_OBUF;
wire round_flag;
wire rst;
wire rst_IBUF;
wire rst_int;
wire sign_final_result;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
initial begin
$sdf_annotate("Testbench_FPU_Add_Subt_time_synth.sdf",,,,"tool_control");
end
Add_Subt Add_Subt_Sgf_module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D(\Mux_Array/Data_array[3]_0 [20:0]),
.E(FSM_Add_Subt_Sgf_load),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_selector_B(FSM_selector_B),
.FSM_selector_C(FSM_selector_C),
.FSM_selector_D(FSM_selector_D),
.O({Oper_Start_in_module_n_27,Oper_Start_in_module_n_28,Oper_Start_in_module_n_29}),
.Q({Add_Subt_Sgf_module_n_26,Add_Subt_Sgf_module_n_27}),
.\Q_reg[0] ({Add_Subt_Sgf_module_n_57,Add_Subt_Sgf_module_n_58}),
.\Q_reg[0]_0 (FS_Module_n_2),
.\Q_reg[0]_1 (Sel_B_n_40),
.\Q_reg[0]_2 (LZA_output[0]),
.\Q_reg[0]_3 (exp_oper_result[0]),
.\Q_reg[11] ({Add_Subt_Sgf_module_n_41,Add_Subt_Sgf_module_n_42,Add_Subt_Sgf_module_n_43,Add_Subt_Sgf_module_n_44}),
.\Q_reg[15] (Add_Subt_Sgf_module_n_25),
.\Q_reg[15]_0 ({Add_Subt_Sgf_module_n_45,Add_Subt_Sgf_module_n_46,Add_Subt_Sgf_module_n_47,Add_Subt_Sgf_module_n_48}),
.\Q_reg[16] (Add_Subt_Sgf_module_n_23),
.\Q_reg[17] (Add_Subt_Sgf_module_n_24),
.\Q_reg[18] (Add_Subt_Sgf_module_n_22),
.\Q_reg[19] ({Add_Subt_Sgf_module_n_49,Add_Subt_Sgf_module_n_50,Add_Subt_Sgf_module_n_51,Add_Subt_Sgf_module_n_52}),
.\Q_reg[1] (Sel_B_n_17),
.\Q_reg[22] ({Oper_Start_in_module_n_73,Oper_Start_in_module_n_74,Oper_Start_in_module_n_75,Oper_Start_in_module_n_76,Oper_Start_in_module_n_77,Oper_Start_in_module_n_78,Oper_Start_in_module_n_79,Oper_Start_in_module_n_80,Oper_Start_in_module_n_81,Oper_Start_in_module_n_82,Oper_Start_in_module_n_83,Oper_Start_in_module_n_84,Oper_Start_in_module_n_85,Oper_Start_in_module_n_86,Oper_Start_in_module_n_87,Oper_Start_in_module_n_88,Oper_Start_in_module_n_89,Oper_Start_in_module_n_90,Oper_Start_in_module_n_91,Oper_Start_in_module_n_92,Oper_Start_in_module_n_93,Oper_Start_in_module_n_94,Oper_Start_in_module_n_95}),
.\Q_reg[22]_0 ({Oper_Start_in_module_n_42,Oper_Start_in_module_n_43,Oper_Start_in_module_n_44,Oper_Start_in_module_n_45,Oper_Start_in_module_n_46,Oper_Start_in_module_n_47,Oper_Start_in_module_n_48,Oper_Start_in_module_n_49,Oper_Start_in_module_n_50,Oper_Start_in_module_n_51,Oper_Start_in_module_n_52,Oper_Start_in_module_n_53,Oper_Start_in_module_n_54,Oper_Start_in_module_n_55,Oper_Start_in_module_n_56,Oper_Start_in_module_n_57,Oper_Start_in_module_n_58,Oper_Start_in_module_n_59,Oper_Start_in_module_n_60,Oper_Start_in_module_n_61,Oper_Start_in_module_n_62,Oper_Start_in_module_n_63,Oper_Start_in_module_n_64}),
.\Q_reg[23] ({Add_Subt_Sgf_module_n_53,Add_Subt_Sgf_module_n_54,Add_Subt_Sgf_module_n_55,Add_Subt_Sgf_module_n_56}),
.\Q_reg[25] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result}),
.\Q_reg[2] (Sel_B_n_16),
.\Q_reg[31] ({Oper_Start_in_module_n_3,Oper_Start_in_module_n_4,Oper_Start_in_module_n_5,Oper_Start_in_module_n_6,Oper_Start_in_module_n_7,Oper_Start_in_module_n_8,Oper_Start_in_module_n_9,Oper_Start_in_module_n_10,Oper_Start_in_module_n_11,Oper_Start_in_module_n_12,Oper_Start_in_module_n_13,Oper_Start_in_module_n_14,Oper_Start_in_module_n_15,Oper_Start_in_module_n_16,Oper_Start_in_module_n_17,Oper_Start_in_module_n_18,Oper_Start_in_module_n_19,Oper_Start_in_module_n_20,Oper_Start_in_module_n_21,Oper_Start_in_module_n_22,Oper_Start_in_module_n_23,Oper_Start_in_module_n_24,Oper_Start_in_module_n_25,Oper_Start_in_module_n_26}),
.\Q_reg[31]_0 (intDY),
.\Q_reg[31]_1 (intDX),
.\Q_reg[4] (Codec_to_Reg),
.\Q_reg[7] ({Add_Subt_Sgf_module_n_37,Add_Subt_Sgf_module_n_38,Add_Subt_Sgf_module_n_39,Add_Subt_Sgf_module_n_40}),
.S({Add_Subt_Sgf_module_n_33,Add_Subt_Sgf_module_n_34,Add_Subt_Sgf_module_n_35,Add_Subt_Sgf_module_n_36}),
.add_overflow_flag(add_overflow_flag),
.intAS(intAS));
Barrel_Shifter Barrel_Shifter_module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D(Data_Reg),
.E(FSM_barrel_shifter_load),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_24),
.Q(\Mux_Array/Data_array[4]_1 ),
.\Q_reg[0] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result}),
.\Q_reg[16] (Barrel_Shifter_module_n_0),
.\Q_reg[16]_0 (Sel_B_n_34),
.\Q_reg[17] (Barrel_Shifter_module_n_18),
.\Q_reg[17]_0 (Sel_B_n_37),
.\Q_reg[18] (Barrel_Shifter_module_n_20),
.\Q_reg[19] (Barrel_Shifter_module_n_22),
.\Q_reg[20] (Barrel_Shifter_module_n_24),
.\Q_reg[21] (Barrel_Shifter_module_n_25),
.\Q_reg[22] (Barrel_Shifter_module_n_23),
.\Q_reg[23] (Barrel_Shifter_module_n_21),
.\Q_reg[24] (Barrel_Shifter_module_n_19),
.\Q_reg[25] (Barrel_Shifter_module_n_17),
.\Q_reg[2] (\Mux_Array/Data_array[3]_0 ),
.\Q_reg[3] (Sel_B_n_36),
.\Q_reg[4] (Sel_B_n_35),
.r_mode_IBUF(r_mode_IBUF),
.round_flag(round_flag),
.sign_final_result(sign_final_result));
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
Exp_Operation Exp_Operation_Module
(.AR(FS_Module_n_25),
.CLK(clk_IBUF_BUFG),
.D({Sign_S_mux,Exp_Operation_Module_n_3,Exp_Operation_Module_n_4,Exp_Operation_Module_n_5,Exp_Operation_Module_n_6,Exp_Operation_Module_n_7,Exp_Operation_Module_n_8,Exp_Operation_Module_n_9,Exp_Operation_Module_n_10,Exp_Operation_Module_n_11,Exp_Operation_Module_n_12,Exp_Operation_Module_n_13,Exp_Operation_Module_n_14,Exp_Operation_Module_n_15,Exp_Operation_Module_n_16,Exp_Operation_Module_n_17,Exp_Operation_Module_n_18,Exp_Operation_Module_n_19,Exp_Operation_Module_n_20,Exp_Operation_Module_n_21,Exp_Operation_Module_n_22,Exp_Operation_Module_n_23,Exp_Operation_Module_n_24,Exp_Operation_Module_n_25,Exp_Operation_Module_n_26,Exp_Operation_Module_n_27,Exp_Operation_Module_n_28,Exp_Operation_Module_n_29,Exp_Operation_Module_n_30,Exp_Operation_Module_n_31,Exp_Operation_Module_n_32,Exp_Operation_Module_n_33}),
.DI(Sel_B_n_11),
.Data_A(Data_A),
.E(FSM_exp_operation_load_diff),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.O(Sel_B_n_12),
.Q(exp_oper_result),
.\Q_reg[0] (Exp_Operation_Module_n_40),
.\Q_reg[0]_0 (FS_Module_n_13),
.\Q_reg[0]_1 (Sel_A_n_0),
.\Q_reg[0]_2 (LZA_output[0]),
.\Q_reg[1] ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[1]_0 (Sel_B_n_41),
.\Q_reg[24] ({Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50}),
.\Q_reg[26] ({Sel_B_n_8,Sel_B_n_9,Sel_B_n_10}),
.\Q_reg[30] ({Oper_Start_in_module_n_34,Oper_Start_in_module_n_35,Oper_Start_in_module_n_36,Oper_Start_in_module_n_37,Oper_Start_in_module_n_38,Oper_Start_in_module_n_39,Oper_Start_in_module_n_40,Oper_Start_in_module_n_41}),
.\Q_reg[30]_0 ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_72}),
.\Q_reg[3] ({Exp_Operation_Module_n_45,Exp_Operation_Module_n_46,Exp_Operation_Module_n_47,Exp_Operation_Module_n_48}),
.S({Exp_Operation_Module_n_41,Exp_Operation_Module_n_42,Exp_Operation_Module_n_43,Exp_Operation_Module_n_44}),
.overflow_flag_OBUF(overflow_flag_OBUF),
.sign_final_result(sign_final_result),
.underflow_flag_OBUF(underflow_flag_OBUF));
FSM_Add_Subtract FS_Module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.CO(eqXY),
.E(FS_Module_n_12),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_C(FSM_selector_C),
.FSM_selector_D(FSM_selector_D),
.Q({Add_Subt_Sgf_module_n_26,Add_Subt_Sgf_module_n_27}),
.\Q_reg[0] (FS_Module_n_5),
.\Q_reg[0]_0 (FS_Module_n_10),
.\Q_reg[0]_1 (FS_Module_n_11),
.\Q_reg[0]_10 (Add_Subt_Sgf_module_n_24),
.\Q_reg[0]_11 (Sel_B_n_40),
.\Q_reg[0]_12 (Sel_A_n_0),
.\Q_reg[0]_13 (Exp_Operation_Module_n_40),
.\Q_reg[0]_2 (FS_Module_n_13),
.\Q_reg[0]_3 (FSM_exp_operation_load_diff),
.\Q_reg[0]_4 (FSM_Add_Subt_Sgf_load),
.\Q_reg[0]_5 (FSM_op_start_in_load_a),
.\Q_reg[0]_6 (FSM_op_start_in_load_b),
.\Q_reg[0]_7 (FSM_barrel_shifter_load),
.\Q_reg[0]_8 (FSM_LZA_load),
.\Q_reg[0]_9 (Add_Subt_Sgf_module_n_25),
.\Q_reg[1] (Sel_B_n_17),
.\Q_reg[1]_0 ({Sel_B_n_1,Sel_B_n_2,Sel_B_n_4}),
.\Q_reg[21] (FS_Module_n_2),
.\Q_reg[23] ({\Mux_Array/Data_array[3]_0 [23],\Mux_Array/Data_array[3]_0 [21]}),
.\Q_reg[2] (Sel_B_n_16),
.\Q_reg[31] ({FS_Module_n_24,FS_Module_n_25}),
.\Q_reg[31]_0 (Oper_Start_in_module_n_33),
.S(FS_Module_n_23),
.ack_FSM_IBUF(ack_FSM_IBUF),
.add_overflow_flag(add_overflow_flag),
.beg_FSM_IBUF(beg_FSM_IBUF),
.in1(rst_IBUF),
.out({FS_Module_n_6,FS_Module_n_7,FS_Module_n_8,FS_Module_n_9}),
.ready_OBUF(ready_OBUF),
.round_flag(round_flag),
.underflow_flag_OBUF(underflow_flag_OBUF),
.zero_flag(zero_flag));
LZD Leading_Zero_Detector_Module
(.CLK(clk_IBUF_BUFG),
.D(Codec_to_Reg),
.E(FSM_LZA_load),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.Q(LZA_output));
Oper_Start_In Oper_Start_in_module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.CO(eqXY),
.D(Data_Y_IBUF),
.\Data_X[31] (Data_X_IBUF),
.E(FSM_op_start_in_load_a),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (Oper_Start_in_module_n_33),
.\FSM_sequential_state_reg_reg[3]_0 (FSM_op_start_in_load_b),
.\FSM_sequential_state_reg_reg[3]_1 ({FS_Module_n_24,FS_Module_n_25}),
.O({Oper_Start_in_module_n_27,Oper_Start_in_module_n_28,Oper_Start_in_module_n_29}),
.Q(intDY),
.\Q_reg[0] (intDX),
.\Q_reg[0]_0 (Sel_D_n_1),
.\Q_reg[23] ({Oper_Start_in_module_n_3,Oper_Start_in_module_n_4,Oper_Start_in_module_n_5,Oper_Start_in_module_n_6,Oper_Start_in_module_n_7,Oper_Start_in_module_n_8,Oper_Start_in_module_n_9,Oper_Start_in_module_n_10,Oper_Start_in_module_n_11,Oper_Start_in_module_n_12,Oper_Start_in_module_n_13,Oper_Start_in_module_n_14,Oper_Start_in_module_n_15,Oper_Start_in_module_n_16,Oper_Start_in_module_n_17,Oper_Start_in_module_n_18,Oper_Start_in_module_n_19,Oper_Start_in_module_n_20,Oper_Start_in_module_n_21,Oper_Start_in_module_n_22,Oper_Start_in_module_n_23,Oper_Start_in_module_n_24,Oper_Start_in_module_n_25,Oper_Start_in_module_n_26}),
.\Q_reg[25] ({Barrel_Shifter_module_n_27,Barrel_Shifter_module_n_28,Barrel_Shifter_module_n_29,Barrel_Shifter_module_n_30,Barrel_Shifter_module_n_31,Barrel_Shifter_module_n_32,Barrel_Shifter_module_n_33,Barrel_Shifter_module_n_34,Barrel_Shifter_module_n_35,Barrel_Shifter_module_n_36,Barrel_Shifter_module_n_37,Barrel_Shifter_module_n_38,Barrel_Shifter_module_n_39,Barrel_Shifter_module_n_40,Barrel_Shifter_module_n_41,Barrel_Shifter_module_n_42,Barrel_Shifter_module_n_43,Barrel_Shifter_module_n_44,Barrel_Shifter_module_n_45,Barrel_Shifter_module_n_46,Barrel_Shifter_module_n_47,Barrel_Shifter_module_n_48,Barrel_Shifter_module_n_49,Barrel_Shifter_module_n_50,Sgf_normalized_result[1]}),
.\Q_reg[31] ({Add_Subt_Sgf_module_n_37,Add_Subt_Sgf_module_n_38,Add_Subt_Sgf_module_n_39,Add_Subt_Sgf_module_n_40}),
.\Q_reg[31]_0 ({Add_Subt_Sgf_module_n_41,Add_Subt_Sgf_module_n_42,Add_Subt_Sgf_module_n_43,Add_Subt_Sgf_module_n_44}),
.\Q_reg[31]_1 ({Add_Subt_Sgf_module_n_45,Add_Subt_Sgf_module_n_46,Add_Subt_Sgf_module_n_47,Add_Subt_Sgf_module_n_48}),
.\Q_reg[31]_2 ({Add_Subt_Sgf_module_n_49,Add_Subt_Sgf_module_n_50,Add_Subt_Sgf_module_n_51,Add_Subt_Sgf_module_n_52}),
.\Q_reg[31]_3 ({Add_Subt_Sgf_module_n_53,Add_Subt_Sgf_module_n_54,Add_Subt_Sgf_module_n_55,Add_Subt_Sgf_module_n_56}),
.\Q_reg[31]_4 ({Add_Subt_Sgf_module_n_57,Add_Subt_Sgf_module_n_58}),
.\Q_reg[7] ({Oper_Start_in_module_n_34,Oper_Start_in_module_n_35,Oper_Start_in_module_n_36,Oper_Start_in_module_n_37,Oper_Start_in_module_n_38,Oper_Start_in_module_n_39,Oper_Start_in_module_n_40,Oper_Start_in_module_n_41,Oper_Start_in_module_n_42,Oper_Start_in_module_n_43,Oper_Start_in_module_n_44,Oper_Start_in_module_n_45,Oper_Start_in_module_n_46,Oper_Start_in_module_n_47,Oper_Start_in_module_n_48,Oper_Start_in_module_n_49,Oper_Start_in_module_n_50,Oper_Start_in_module_n_51,Oper_Start_in_module_n_52,Oper_Start_in_module_n_53,Oper_Start_in_module_n_54,Oper_Start_in_module_n_55,Oper_Start_in_module_n_56,Oper_Start_in_module_n_57,Oper_Start_in_module_n_58,Oper_Start_in_module_n_59,Oper_Start_in_module_n_60,Oper_Start_in_module_n_61,Oper_Start_in_module_n_62,Oper_Start_in_module_n_63,Oper_Start_in_module_n_64}),
.\Q_reg[7]_0 ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_68,Oper_Start_in_module_n_69,Oper_Start_in_module_n_70,Oper_Start_in_module_n_71,Oper_Start_in_module_n_72,Oper_Start_in_module_n_73,Oper_Start_in_module_n_74,Oper_Start_in_module_n_75,Oper_Start_in_module_n_76,Oper_Start_in_module_n_77,Oper_Start_in_module_n_78,Oper_Start_in_module_n_79,Oper_Start_in_module_n_80,Oper_Start_in_module_n_81,Oper_Start_in_module_n_82,Oper_Start_in_module_n_83,Oper_Start_in_module_n_84,Oper_Start_in_module_n_85,Oper_Start_in_module_n_86,Oper_Start_in_module_n_87,Oper_Start_in_module_n_88,Oper_Start_in_module_n_89,Oper_Start_in_module_n_90,Oper_Start_in_module_n_91,Oper_Start_in_module_n_92,Oper_Start_in_module_n_93,Oper_Start_in_module_n_94,Oper_Start_in_module_n_95}),
.S({Add_Subt_Sgf_module_n_33,Add_Subt_Sgf_module_n_34,Add_Subt_Sgf_module_n_35,Add_Subt_Sgf_module_n_36}),
.add_subt_IBUF(add_subt_IBUF),
.intAS(intAS),
.sign_final_result(sign_final_result),
.zero_flag(zero_flag));
RegisterAdd Sel_A
(.CLK(clk_IBUF_BUFG),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_11),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.\Q_reg[0]_0 (Sel_A_n_0));
RegisterAdd__parameterized0 Sel_B
(.CLK(clk_IBUF_BUFG),
.D(Data_Reg),
.DI(Sel_B_n_11),
.Data_A(Data_A),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.FSM_exp_operation_A_S(FSM_exp_operation_A_S),
.FSM_selector_B(FSM_selector_B),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.O(Sel_B_n_12),
.Q(\Mux_Array/Data_array[4]_1 ),
.\Q_reg[0]_0 (Sel_B_n_35),
.\Q_reg[0]_1 (Sel_B_n_36),
.\Q_reg[0]_2 (FS_Module_n_23),
.\Q_reg[0]_3 (FS_Module_n_2),
.\Q_reg[0]_4 (Add_Subt_Sgf_module_n_22),
.\Q_reg[0]_5 (Add_Subt_Sgf_module_n_23),
.\Q_reg[16] (Barrel_Shifter_module_n_17),
.\Q_reg[17] (Barrel_Shifter_module_n_19),
.\Q_reg[18] (Barrel_Shifter_module_n_21),
.\Q_reg[19] (Barrel_Shifter_module_n_23),
.\Q_reg[20] (Barrel_Shifter_module_n_25),
.\Q_reg[21] (Sel_B_n_40),
.\Q_reg[21]_0 (Barrel_Shifter_module_n_24),
.\Q_reg[22] (Barrel_Shifter_module_n_22),
.\Q_reg[23] (Barrel_Shifter_module_n_20),
.\Q_reg[24] (Barrel_Shifter_module_n_18),
.\Q_reg[25] ({\Mux_Array/Data_array[3]_0 [25:24],\Mux_Array/Data_array[3]_0 [22]}),
.\Q_reg[25]_0 (Sel_B_n_16),
.\Q_reg[25]_1 (Sel_B_n_17),
.\Q_reg[25]_2 (Barrel_Shifter_module_n_0),
.\Q_reg[26] ({Exp_Operation_Module_n_45,Exp_Operation_Module_n_46,Exp_Operation_Module_n_47,Exp_Operation_Module_n_48}),
.\Q_reg[30] ({Oper_Start_in_module_n_65,Oper_Start_in_module_n_66,Oper_Start_in_module_n_67,Oper_Start_in_module_n_68,Oper_Start_in_module_n_69,Oper_Start_in_module_n_70,Oper_Start_in_module_n_71}),
.\Q_reg[3] ({Sel_B_n_8,Sel_B_n_9,Sel_B_n_10}),
.\Q_reg[4] (LZA_output),
.\Q_reg[4]_0 (exp_oper_result),
.\Q_reg[7] ({Sel_B_n_0,Sel_B_n_1,Sel_B_n_2,Sel_B_n_3,Sel_B_n_4,Sel_B_n_5,Sel_B_n_6,Sel_B_n_7}),
.\Q_reg[7]_0 (Sel_B_n_41),
.\Q_reg[8] (Sel_B_n_37),
.\Q_reg[9] (Sel_B_n_34),
.S({Exp_Operation_Module_n_41,Exp_Operation_Module_n_42,Exp_Operation_Module_n_43,Exp_Operation_Module_n_44}),
.add_overflow_flag(add_overflow_flag),
.out({FS_Module_n_6,FS_Module_n_7,FS_Module_n_8,FS_Module_n_9}));
RegisterAdd_0 Sel_C
(.CLK(clk_IBUF_BUFG),
.FSM_selector_C(FSM_selector_C),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_5),
.\FSM_sequential_state_reg_reg[3]_0 (FS_Module_n_25));
RegisterAdd_1 Sel_D
(.CLK(clk_IBUF_BUFG),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[0] (FS_Module_n_10),
.\FSM_sequential_state_reg_reg[3] (FS_Module_n_25),
.\Q_reg[0]_0 (Sgf_normalized_result[0]),
.\Q_reg[3] (Sel_D_n_1));
IBUF ack_FSM_IBUF_inst
(.I(ack_FSM),
.O(ack_FSM_IBUF));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_FSM_IBUF_inst
(.I(beg_FSM),
.O(beg_FSM_IBUF));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
Tenth_Phase final_result_ieee_Module
(.AR(rst_int),
.CLK(clk_IBUF_BUFG),
.D({Sign_S_mux,Exp_Operation_Module_n_3,Exp_Operation_Module_n_4,Exp_Operation_Module_n_5,Exp_Operation_Module_n_6,Exp_Operation_Module_n_7,Exp_Operation_Module_n_8,Exp_Operation_Module_n_9,Exp_Operation_Module_n_10,Exp_Operation_Module_n_11,Exp_Operation_Module_n_12,Exp_Operation_Module_n_13,Exp_Operation_Module_n_14,Exp_Operation_Module_n_15,Exp_Operation_Module_n_16,Exp_Operation_Module_n_17,Exp_Operation_Module_n_18,Exp_Operation_Module_n_19,Exp_Operation_Module_n_20,Exp_Operation_Module_n_21,Exp_Operation_Module_n_22,Exp_Operation_Module_n_23,Exp_Operation_Module_n_24,Exp_Operation_Module_n_25,Exp_Operation_Module_n_26,Exp_Operation_Module_n_27,Exp_Operation_Module_n_28,Exp_Operation_Module_n_29,Exp_Operation_Module_n_30,Exp_Operation_Module_n_31,Exp_Operation_Module_n_32,Exp_Operation_Module_n_33}),
.E(FS_Module_n_12),
.Q(final_result_ieee_OBUF));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
IBUF \r_mode_IBUF[0]_inst
(.I(r_mode[0]),
.O(r_mode_IBUF[0]));
IBUF \r_mode_IBUF[1]_inst
(.I(r_mode[1]),
.O(r_mode_IBUF[1]));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
endmodule
module FSM_Add_Subtract
(\Q_reg[23] ,
\Q_reg[21] ,
FSM_barrel_shifter_B_S,
FSM_barrel_shifter_L_R,
\Q_reg[0] ,
out,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
E,
\Q_reg[0]_2 ,
FSM_exp_operation_A_S,
ready_OBUF,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
\Q_reg[0]_6 ,
AR,
\Q_reg[0]_7 ,
\Q_reg[0]_8 ,
S,
\Q_reg[31] ,
\Q_reg[2] ,
\Q_reg[0]_9 ,
\Q_reg[1] ,
\Q_reg[0]_10 ,
\Q_reg[0]_11 ,
Q,
FSM_selector_C,
round_flag,
FSM_selector_D,
\Q_reg[0]_12 ,
\Q_reg[1]_0 ,
\Q_reg[0]_13 ,
underflow_flag_OBUF,
CLK,
in1,
add_overflow_flag,
zero_flag,
beg_FSM_IBUF,
ack_FSM_IBUF,
CO,
\Q_reg[31]_0 );
output [1:0]\Q_reg[23] ;
output \Q_reg[21] ;
output FSM_barrel_shifter_B_S;
output FSM_barrel_shifter_L_R;
output \Q_reg[0] ;
output [3:0]out;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
output [0:0]E;
output \Q_reg[0]_2 ;
output FSM_exp_operation_A_S;
output ready_OBUF;
output [0:0]\Q_reg[0]_3 ;
output [0:0]\Q_reg[0]_4 ;
output [0:0]\Q_reg[0]_5 ;
output [0:0]\Q_reg[0]_6 ;
output [0:0]AR;
output [0:0]\Q_reg[0]_7 ;
output [0:0]\Q_reg[0]_8 ;
output [0:0]S;
output [1:0]\Q_reg[31] ;
input \Q_reg[2] ;
input \Q_reg[0]_9 ;
input \Q_reg[1] ;
input \Q_reg[0]_10 ;
input \Q_reg[0]_11 ;
input [1:0]Q;
input FSM_selector_C;
input round_flag;
input FSM_selector_D;
input \Q_reg[0]_12 ;
input [2:0]\Q_reg[1]_0 ;
input \Q_reg[0]_13 ;
input underflow_flag_OBUF;
input CLK;
input in1;
input add_overflow_flag;
input zero_flag;
input beg_FSM_IBUF;
input ack_FSM_IBUF;
input [0:0]CO;
input \Q_reg[31]_0 ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_exp_operation_A_S;
wire FSM_exp_operation_load_OU;
wire FSM_selector_C;
wire FSM_selector_D;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_1_n_0 ;
wire \FSM_sequential_state_reg[3]_i_2_n_0 ;
wire \FSM_sequential_state_reg[3]_i_3_n_0 ;
wire [1:0]Q;
wire \Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_10 ;
wire \Q_reg[0]_11 ;
wire \Q_reg[0]_12 ;
wire \Q_reg[0]_13 ;
wire \Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire [0:0]\Q_reg[0]_4 ;
wire [0:0]\Q_reg[0]_5 ;
wire [0:0]\Q_reg[0]_6 ;
wire [0:0]\Q_reg[0]_7 ;
wire [0:0]\Q_reg[0]_8 ;
wire \Q_reg[0]_9 ;
wire \Q_reg[1] ;
wire [2:0]\Q_reg[1]_0 ;
wire \Q_reg[21] ;
wire [1:0]\Q_reg[23] ;
wire \Q_reg[2] ;
wire [1:0]\Q_reg[31] ;
wire \Q_reg[31]_0 ;
wire [0:0]S;
wire ack_FSM_IBUF;
wire add_overflow_flag;
wire beg_FSM_IBUF;
wire in1;
(* RTL_KEEP = "yes" *) wire [3:0]out;
wire ready_OBUF;
wire round_flag;
wire underflow_flag_OBUF;
wire zero_flag;
LUT6 #(
.INIT(64'h0055005557115755))
\FSM_sequential_state_reg[0]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(FSM_selector_C),
.I3(out[2]),
.I4(zero_flag),
.I5(out[3]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'h0000FBFB3C3F0000))
\FSM_sequential_state_reg[1]_i_1
(.I0(FSM_selector_C),
.I1(out[2]),
.I2(out[3]),
.I3(zero_flag),
.I4(out[1]),
.I5(out[0]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT6 #(
.INIT(64'h3CC03CC02FF02CF0))
\FSM_sequential_state_reg[2]_i_1
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(zero_flag),
.I5(out[3]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
LUT6 #(
.INIT(64'h7777FFFFFFDDFEFE))
\FSM_sequential_state_reg[3]_i_1
(.I0(out[3]),
.I1(out[0]),
.I2(beg_FSM_IBUF),
.I3(ack_FSM_IBUF),
.I4(out[2]),
.I5(out[1]),
.O(\FSM_sequential_state_reg[3]_i_1_n_0 ));
LUT6 #(
.INIT(64'hFFFFA2F000F0A2F0))
\FSM_sequential_state_reg[3]_i_2
(.I0(out[0]),
.I1(FSM_selector_C),
.I2(out[3]),
.I3(out[2]),
.I4(out[1]),
.I5(\FSM_sequential_state_reg[3]_i_3_n_0 ),
.O(\FSM_sequential_state_reg[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'h4050405041514050))
\FSM_sequential_state_reg[3]_i_3
(.I0(out[3]),
.I1(out[0]),
.I2(out[2]),
.I3(round_flag),
.I4(CO),
.I5(\Q_reg[31]_0 ),
.O(\FSM_sequential_state_reg[3]_i_3_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(out[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(out[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(out[2]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg[3]_i_1_n_0 ),
.CLR(in1),
.D(\FSM_sequential_state_reg[3]_i_2_n_0 ),
.Q(out[3]));
LUT4 #(
.INIT(16'h2800))
\Q[0]_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.O(\Q_reg[0]_4 ));
LUT4 #(
.INIT(16'h0001))
\Q[0]_i_1__0
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(AR));
LUT6 #(
.INIT(64'hFFFFFFFF00002000))
\Q[0]_i_1__10
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(out[3]),
.I5(FSM_selector_D),
.O(\Q_reg[0]_0 ));
LUT6 #(
.INIT(64'hFFFFFFFF00002000))
\Q[0]_i_1__11
(.I0(round_flag),
.I1(out[0]),
.I2(out[2]),
.I3(out[1]),
.I4(out[3]),
.I5(\Q_reg[0]_12 ),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'h0001FFFF00010000))
\Q[0]_i_1__12
(.I0(\Q_reg[1]_0 [0]),
.I1(\Q_reg[1]_0 [2]),
.I2(\Q_reg[1]_0 [1]),
.I3(\Q_reg[0]_13 ),
.I4(FSM_exp_operation_load_OU),
.I5(underflow_flag_OBUF),
.O(\Q_reg[0]_2 ));
LUT5 #(
.INIT(32'hFFFF0800))
\Q[0]_i_1__9
(.I0(out[3]),
.I1(out[0]),
.I2(out[1]),
.I3(out[2]),
.I4(FSM_selector_C),
.O(\Q_reg[0] ));
LUT5 #(
.INIT(32'h00300200))
\Q[0]_i_3
(.I0(FSM_selector_C),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.I4(out[0]),
.O(FSM_exp_operation_load_OU));
LUT6 #(
.INIT(64'h0FFFFF5FFFFFF7FF))
\Q[0]_i_4
(.I0(add_overflow_flag),
.I1(FSM_selector_C),
.I2(out[0]),
.I3(out[2]),
.I4(out[1]),
.I5(out[3]),
.O(S));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1
(.I0(\Q_reg[21] ),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[2] ),
.I3(\Q_reg[0]_9 ),
.I4(\Q_reg[1] ),
.I5(\Q_reg[0]_10 ),
.O(\Q_reg[23] [0]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[23]_i_1__0
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[2] ),
.I2(\Q_reg[0]_10 ),
.I3(\Q_reg[1] ),
.I4(\Q_reg[21] ),
.O(\Q_reg[23] [1]));
LUT4 #(
.INIT(16'h0420))
\Q[25]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.O(\Q_reg[0]_7 ));
LUT6 #(
.INIT(64'hB888B888BBBB88BB))
\Q[25]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_11 ),
.I2(Q[0]),
.I3(FSM_selector_C),
.I4(Q[1]),
.I5(FSM_barrel_shifter_L_R),
.O(\Q_reg[21] ));
LUT5 #(
.INIT(32'h00001000))
\Q[25]_i_4
(.I0(out[1]),
.I1(out[3]),
.I2(out[2]),
.I3(FSM_selector_C),
.I4(add_overflow_flag),
.O(FSM_barrel_shifter_L_R));
LUT6 #(
.INIT(64'h00080C000008C000))
\Q[25]_i_7
(.I0(FSM_selector_C),
.I1(add_overflow_flag),
.I2(out[1]),
.I3(out[3]),
.I4(out[2]),
.I5(out[0]),
.O(FSM_barrel_shifter_B_S));
LUT4 #(
.INIT(16'h0010))
\Q[30]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[1]),
.I3(out[0]),
.O(\Q_reg[0]_6 ));
LUT4 #(
.INIT(16'h0010))
\Q[31]_i_1
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[0]_5 ));
LUT4 #(
.INIT(16'h4000))
\Q[31]_i_1__0
(.I0(out[2]),
.I1(out[3]),
.I2(out[0]),
.I3(out[1]),
.O(E));
LUT4 #(
.INIT(16'h0001))
\Q[31]_i_2
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[31] [1]));
LUT6 #(
.INIT(64'h0FFFFF5FFFFFF7FF))
\Q[3]_i_6
(.I0(add_overflow_flag),
.I1(FSM_selector_C),
.I2(out[0]),
.I3(out[2]),
.I4(out[1]),
.I5(out[3]),
.O(FSM_exp_operation_A_S));
LUT4 #(
.INIT(16'h2000))
\Q[4]_i_1
(.I0(out[2]),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.O(\Q_reg[0]_8 ));
LUT4 #(
.INIT(16'h0224))
\Q[7]_i_1
(.I0(out[0]),
.I1(out[2]),
.I2(out[3]),
.I3(out[1]),
.O(\Q_reg[0]_3 ));
LUT4 #(
.INIT(16'h0001))
\Q[7]_i_2
(.I0(out[3]),
.I1(out[2]),
.I2(out[0]),
.I3(out[1]),
.O(\Q_reg[31] [0]));
LUT4 #(
.INIT(16'h1000))
ready_OBUF_inst_i_1
(.I0(out[0]),
.I1(out[1]),
.I2(out[3]),
.I3(out[2]),
.O(ready_OBUF));
endmodule
module LZD
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [4:0]Q;
input [0:0]E;
input [4:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [4:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [4:0]Q;
RegisterAdd__parameterized9 Output_Reg
(.CLK(CLK),
.D(D),
.E(E),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q));
endmodule
module Mux_Array
(D,
\Q_reg[16] ,
Q,
\Q_reg[25] ,
\Q_reg[17] ,
\Q_reg[24] ,
\Q_reg[18] ,
\Q_reg[23] ,
\Q_reg[19] ,
\Q_reg[22] ,
\Q_reg[20] ,
\Q_reg[21] ,
FSM_barrel_shifter_L_R,
\Q_reg[16]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[4] ,
\Q_reg[3] ,
\Q_reg[17]_0 ,
\Q_reg[2] ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [9:0]D;
output \Q_reg[16] ;
output [15:0]Q;
output \Q_reg[25] ;
output \Q_reg[17] ;
output \Q_reg[24] ;
output \Q_reg[18] ;
output \Q_reg[23] ;
output \Q_reg[19] ;
output \Q_reg[22] ;
output \Q_reg[20] ;
output \Q_reg[21] ;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4] ;
input \Q_reg[3] ;
input \Q_reg[17]_0 ;
input [25:0]\Q_reg[2] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [9:0]D;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire \Q_reg[16] ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17] ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire \Q_reg[25] ;
wire [25:0]\Q_reg[2] ;
wire \Q_reg[3] ;
wire \Q_reg[4] ;
RegisterAdd__parameterized6 Mid_Reg
(.CLK(CLK),
.D(D),
.FSM_barrel_shifter_B_S(FSM_barrel_shifter_B_S),
.FSM_barrel_shifter_L_R(FSM_barrel_shifter_L_R),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.Q(Q),
.\Q_reg[16]_0 (\Q_reg[16] ),
.\Q_reg[16]_1 (\Q_reg[16]_0 ),
.\Q_reg[17]_0 (\Q_reg[17] ),
.\Q_reg[17]_1 (\Q_reg[17]_0 ),
.\Q_reg[18]_0 (\Q_reg[18] ),
.\Q_reg[19]_0 (\Q_reg[19] ),
.\Q_reg[20]_0 (\Q_reg[20] ),
.\Q_reg[21]_0 (\Q_reg[21] ),
.\Q_reg[22]_0 (\Q_reg[22] ),
.\Q_reg[23]_0 (\Q_reg[23] ),
.\Q_reg[24]_0 (\Q_reg[24] ),
.\Q_reg[25]_0 (\Q_reg[25] ),
.\Q_reg[2]_0 (\Q_reg[2] ),
.\Q_reg[3]_0 (\Q_reg[3] ),
.\Q_reg[4]_0 (\Q_reg[4] ));
endmodule
module Oper_Start_In
(intAS,
sign_final_result,
CO,
\Q_reg[23] ,
O,
zero_flag,
Q,
\Q_reg[0] ,
\FSM_sequential_state_reg_reg[3] ,
\Q_reg[7] ,
\Q_reg[7]_0 ,
E,
add_subt_IBUF,
CLK,
AR,
\FSM_sequential_state_reg_reg[3]_0 ,
\FSM_sequential_state_reg_reg[3]_1 ,
\Q_reg[0]_0 ,
S,
\Q_reg[31] ,
\Q_reg[31]_0 ,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
FSM_selector_D,
\Q_reg[25] ,
D,
\Data_X[31] );
output intAS;
output sign_final_result;
output [0:0]CO;
output [23:0]\Q_reg[23] ;
output [2:0]O;
output zero_flag;
output [0:0]Q;
output [0:0]\Q_reg[0] ;
output \FSM_sequential_state_reg_reg[3] ;
output [30:0]\Q_reg[7] ;
output [30:0]\Q_reg[7]_0 ;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
input [1:0]\FSM_sequential_state_reg_reg[3]_1 ;
input \Q_reg[0]_0 ;
input [3:0]S;
input [3:0]\Q_reg[31] ;
input [3:0]\Q_reg[31]_0 ;
input [3:0]\Q_reg[31]_1 ;
input [3:0]\Q_reg[31]_2 ;
input [3:0]\Q_reg[31]_3 ;
input [1:0]\Q_reg[31]_4 ;
input FSM_selector_D;
input [24:0]\Q_reg[25] ;
input [31:0]D;
input [31:0]\Data_X[31] ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [31:0]D;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [1:0]\FSM_sequential_state_reg_reg[3]_1 ;
wire [2:0]O;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire \Q_reg[0]_0 ;
wire [23:0]\Q_reg[23] ;
wire [24:0]\Q_reg[25] ;
wire [3:0]\Q_reg[31] ;
wire [3:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[31]_1 ;
wire [3:0]\Q_reg[31]_2 ;
wire [3:0]\Q_reg[31]_3 ;
wire [1:0]\Q_reg[31]_4 ;
wire [30:0]\Q_reg[7] ;
wire [30:0]\Q_reg[7]_0 ;
wire [3:0]S;
wire XRegister_n_10;
wire XRegister_n_100;
wire XRegister_n_101;
wire XRegister_n_102;
wire XRegister_n_103;
wire XRegister_n_104;
wire XRegister_n_105;
wire XRegister_n_106;
wire XRegister_n_107;
wire XRegister_n_108;
wire XRegister_n_109;
wire XRegister_n_11;
wire XRegister_n_110;
wire XRegister_n_111;
wire XRegister_n_112;
wire XRegister_n_113;
wire XRegister_n_114;
wire XRegister_n_115;
wire XRegister_n_116;
wire XRegister_n_117;
wire XRegister_n_118;
wire XRegister_n_119;
wire XRegister_n_12;
wire XRegister_n_120;
wire XRegister_n_121;
wire XRegister_n_122;
wire XRegister_n_123;
wire XRegister_n_124;
wire XRegister_n_125;
wire XRegister_n_126;
wire XRegister_n_127;
wire XRegister_n_128;
wire XRegister_n_129;
wire XRegister_n_13;
wire XRegister_n_130;
wire XRegister_n_131;
wire XRegister_n_132;
wire XRegister_n_133;
wire XRegister_n_134;
wire XRegister_n_135;
wire XRegister_n_136;
wire XRegister_n_137;
wire XRegister_n_138;
wire XRegister_n_139;
wire XRegister_n_14;
wire XRegister_n_140;
wire XRegister_n_141;
wire XRegister_n_142;
wire XRegister_n_143;
wire XRegister_n_144;
wire XRegister_n_145;
wire XRegister_n_15;
wire XRegister_n_16;
wire XRegister_n_17;
wire XRegister_n_18;
wire XRegister_n_19;
wire XRegister_n_2;
wire XRegister_n_20;
wire XRegister_n_21;
wire XRegister_n_22;
wire XRegister_n_23;
wire XRegister_n_24;
wire XRegister_n_25;
wire XRegister_n_26;
wire XRegister_n_27;
wire XRegister_n_28;
wire XRegister_n_29;
wire XRegister_n_3;
wire XRegister_n_30;
wire XRegister_n_31;
wire XRegister_n_32;
wire XRegister_n_33;
wire XRegister_n_34;
wire XRegister_n_35;
wire XRegister_n_36;
wire XRegister_n_37;
wire XRegister_n_38;
wire XRegister_n_39;
wire XRegister_n_4;
wire XRegister_n_40;
wire XRegister_n_41;
wire XRegister_n_42;
wire XRegister_n_43;
wire XRegister_n_44;
wire XRegister_n_45;
wire XRegister_n_46;
wire XRegister_n_47;
wire XRegister_n_48;
wire XRegister_n_49;
wire XRegister_n_5;
wire XRegister_n_50;
wire XRegister_n_51;
wire XRegister_n_52;
wire XRegister_n_53;
wire XRegister_n_54;
wire XRegister_n_55;
wire XRegister_n_56;
wire XRegister_n_57;
wire XRegister_n_58;
wire XRegister_n_59;
wire XRegister_n_6;
wire XRegister_n_60;
wire XRegister_n_61;
wire XRegister_n_62;
wire XRegister_n_63;
wire XRegister_n_64;
wire XRegister_n_65;
wire XRegister_n_66;
wire XRegister_n_67;
wire XRegister_n_68;
wire XRegister_n_69;
wire XRegister_n_7;
wire XRegister_n_70;
wire XRegister_n_71;
wire XRegister_n_72;
wire XRegister_n_73;
wire XRegister_n_74;
wire XRegister_n_75;
wire XRegister_n_76;
wire XRegister_n_77;
wire XRegister_n_78;
wire XRegister_n_79;
wire XRegister_n_8;
wire XRegister_n_80;
wire XRegister_n_81;
wire XRegister_n_82;
wire XRegister_n_83;
wire XRegister_n_84;
wire XRegister_n_85;
wire XRegister_n_86;
wire XRegister_n_87;
wire XRegister_n_88;
wire XRegister_n_89;
wire XRegister_n_9;
wire XRegister_n_90;
wire XRegister_n_91;
wire XRegister_n_92;
wire XRegister_n_93;
wire XRegister_n_94;
wire XRegister_n_95;
wire XRegister_n_96;
wire XRegister_n_97;
wire XRegister_n_98;
wire XRegister_n_99;
wire YRegister_n_28;
wire YRegister_n_29;
wire YRegister_n_30;
wire YRegister_n_31;
wire YRegister_n_32;
wire YRegister_n_33;
wire YRegister_n_34;
wire YRegister_n_35;
wire YRegister_n_36;
wire YRegister_n_37;
wire YRegister_n_38;
wire YRegister_n_39;
wire YRegister_n_40;
wire YRegister_n_41;
wire YRegister_n_42;
wire YRegister_n_43;
wire YRegister_n_44;
wire YRegister_n_45;
wire YRegister_n_46;
wire YRegister_n_47;
wire YRegister_n_48;
wire YRegister_n_49;
wire YRegister_n_50;
wire YRegister_n_51;
wire YRegister_n_52;
wire YRegister_n_53;
wire YRegister_n_54;
wire YRegister_n_55;
wire YRegister_n_56;
wire YRegister_n_57;
wire YRegister_n_58;
wire YRegister_n_59;
wire YRegister_n_60;
wire YRegister_n_61;
wire YRegister_n_62;
wire YRegister_n_63;
wire YRegister_n_64;
wire YRegister_n_65;
wire YRegister_n_66;
wire YRegister_n_67;
wire YRegister_n_68;
wire YRegister_n_69;
wire YRegister_n_70;
wire YRegister_n_71;
wire YRegister_n_72;
wire YRegister_n_73;
wire YRegister_n_74;
wire YRegister_n_75;
wire add_subt_IBUF;
wire gtXY;
wire intAS;
wire sign_final_result;
wire sign_result;
wire zero_flag;
RegisterAdd_2 ASRegister
(.AR(AR),
.CLK(CLK),
.E(E),
.\Q_reg[0]_0 (intAS),
.add_subt_IBUF(add_subt_IBUF));
RegisterAdd__parameterized3 MRegister
(.CLK(CLK),
.D({XRegister_n_59,XRegister_n_60,XRegister_n_61,XRegister_n_62,XRegister_n_63,XRegister_n_64,XRegister_n_65,XRegister_n_66,XRegister_n_67,XRegister_n_68,XRegister_n_69,XRegister_n_70,XRegister_n_71,XRegister_n_72,XRegister_n_73,XRegister_n_74,XRegister_n_75,XRegister_n_76,XRegister_n_77,XRegister_n_78,XRegister_n_79,XRegister_n_80,XRegister_n_81,XRegister_n_82,XRegister_n_83,XRegister_n_84,XRegister_n_85,XRegister_n_86,XRegister_n_87,XRegister_n_88,XRegister_n_89}),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 ),
.\Q_reg[7]_0 (\Q_reg[7] ));
Comparator Magnitude_Comparator
(.CO(gtXY),
.DI({XRegister_n_37,XRegister_n_38,XRegister_n_39,XRegister_n_40}),
.Q(Q),
.\Q_reg[0] (CO),
.\Q_reg[0]_0 (intAS),
.\Q_reg[10] ({XRegister_n_33,XRegister_n_34,XRegister_n_35,XRegister_n_36}),
.\Q_reg[15] ({XRegister_n_41,XRegister_n_42,XRegister_n_43,XRegister_n_44}),
.\Q_reg[15]_0 ({YRegister_n_63,YRegister_n_64,YRegister_n_65,YRegister_n_66}),
.\Q_reg[22] ({XRegister_n_45,XRegister_n_46,XRegister_n_47,XRegister_n_48}),
.\Q_reg[23] ({XRegister_n_49,XRegister_n_50,XRegister_n_51,XRegister_n_52}),
.\Q_reg[23]_0 ({YRegister_n_67,YRegister_n_68,YRegister_n_69,YRegister_n_70}),
.\Q_reg[30] ({XRegister_n_55,XRegister_n_56,XRegister_n_57,XRegister_n_58}),
.\Q_reg[30]_0 ({YRegister_n_71,YRegister_n_72,YRegister_n_73,YRegister_n_74}),
.\Q_reg[30]_1 ({YRegister_n_75,XRegister_n_53,XRegister_n_54}),
.\Q_reg[31] (\Q_reg[0] ),
.S({YRegister_n_59,YRegister_n_60,YRegister_n_61,YRegister_n_62}),
.zero_flag(zero_flag));
RegisterAdd_3 SignRegister
(.CLK(CLK),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [0]),
.sign_final_result(sign_final_result),
.sign_result(sign_result));
RegisterAdd__parameterized1 XRegister
(.CLK(CLK),
.CO(CO),
.D({XRegister_n_59,XRegister_n_60,XRegister_n_61,XRegister_n_62,XRegister_n_63,XRegister_n_64,XRegister_n_65,XRegister_n_66,XRegister_n_67,XRegister_n_68,XRegister_n_69,XRegister_n_70,XRegister_n_71,XRegister_n_72,XRegister_n_73,XRegister_n_74,XRegister_n_75,XRegister_n_76,XRegister_n_77,XRegister_n_78,XRegister_n_79,XRegister_n_80,XRegister_n_81,XRegister_n_82,XRegister_n_83,XRegister_n_84,XRegister_n_85,XRegister_n_86,XRegister_n_87,XRegister_n_88,XRegister_n_89}),
.DI({XRegister_n_37,XRegister_n_38,XRegister_n_39,XRegister_n_40}),
.\Data_X[31] (\Data_X[31] ),
.E(E),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3] ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [1]),
.Q({\Q_reg[0] ,XRegister_n_2,XRegister_n_3,XRegister_n_4,XRegister_n_5,XRegister_n_6,XRegister_n_7,XRegister_n_8,XRegister_n_9,XRegister_n_10,XRegister_n_11,XRegister_n_12,XRegister_n_13,XRegister_n_14,XRegister_n_15,XRegister_n_16,XRegister_n_17,XRegister_n_18,XRegister_n_19,XRegister_n_20,XRegister_n_21,XRegister_n_22,XRegister_n_23,XRegister_n_24,XRegister_n_25,XRegister_n_26,XRegister_n_27,XRegister_n_28,XRegister_n_29,XRegister_n_30,XRegister_n_31,XRegister_n_32}),
.\Q_reg[0]_0 ({XRegister_n_33,XRegister_n_34,XRegister_n_35,XRegister_n_36}),
.\Q_reg[0]_1 ({XRegister_n_41,XRegister_n_42,XRegister_n_43,XRegister_n_44}),
.\Q_reg[0]_2 ({XRegister_n_45,XRegister_n_46,XRegister_n_47,XRegister_n_48}),
.\Q_reg[0]_3 ({XRegister_n_49,XRegister_n_50,XRegister_n_51,XRegister_n_52}),
.\Q_reg[0]_4 ({XRegister_n_53,XRegister_n_54}),
.\Q_reg[0]_5 ({XRegister_n_55,XRegister_n_56,XRegister_n_57,XRegister_n_58}),
.\Q_reg[0]_6 ({XRegister_n_144,XRegister_n_145}),
.\Q_reg[0]_7 (intAS),
.\Q_reg[11]_0 ({XRegister_n_128,XRegister_n_129,XRegister_n_130,XRegister_n_131}),
.\Q_reg[15]_0 ({XRegister_n_132,XRegister_n_133,XRegister_n_134,XRegister_n_135}),
.\Q_reg[19]_0 ({XRegister_n_136,XRegister_n_137,XRegister_n_138,XRegister_n_139}),
.\Q_reg[23]_0 ({XRegister_n_140,XRegister_n_141,XRegister_n_142,XRegister_n_143}),
.\Q_reg[25]_0 (\Q_reg[25] ),
.\Q_reg[30]_0 ({XRegister_n_90,XRegister_n_91,XRegister_n_92,XRegister_n_93,XRegister_n_94,XRegister_n_95,XRegister_n_96,XRegister_n_97,XRegister_n_98,XRegister_n_99,XRegister_n_100,XRegister_n_101,XRegister_n_102,XRegister_n_103,XRegister_n_104,XRegister_n_105,XRegister_n_106,XRegister_n_107,XRegister_n_108,XRegister_n_109,XRegister_n_110,XRegister_n_111,XRegister_n_112,XRegister_n_113,XRegister_n_114,XRegister_n_115,XRegister_n_116,XRegister_n_117,XRegister_n_118,XRegister_n_119,XRegister_n_120}),
.\Q_reg[30]_1 (gtXY),
.\Q_reg[31]_0 ({Q,YRegister_n_28,YRegister_n_29,YRegister_n_30,YRegister_n_31,YRegister_n_32,YRegister_n_33,YRegister_n_34,YRegister_n_35,YRegister_n_36,YRegister_n_37,YRegister_n_38,YRegister_n_39,YRegister_n_40,YRegister_n_41,YRegister_n_42,YRegister_n_43,YRegister_n_44,YRegister_n_45,YRegister_n_46,YRegister_n_47,YRegister_n_48,YRegister_n_49,YRegister_n_50,YRegister_n_51,YRegister_n_52,YRegister_n_53,YRegister_n_54,YRegister_n_55,YRegister_n_56,YRegister_n_57,YRegister_n_58}),
.\Q_reg[3]_0 ({XRegister_n_121,XRegister_n_122,XRegister_n_123}),
.\Q_reg[7]_0 ({XRegister_n_124,XRegister_n_125,XRegister_n_126,XRegister_n_127}),
.sign_result(sign_result));
RegisterAdd__parameterized2 YRegister
(.CLK(CLK),
.D(D),
.E(E),
.FSM_selector_D(FSM_selector_D),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_1 [1]),
.O(O),
.Q({Q,YRegister_n_28,YRegister_n_29,YRegister_n_30,YRegister_n_31,YRegister_n_32,YRegister_n_33,YRegister_n_34,YRegister_n_35,YRegister_n_36,YRegister_n_37,YRegister_n_38,YRegister_n_39,YRegister_n_40,YRegister_n_41,YRegister_n_42,YRegister_n_43,YRegister_n_44,YRegister_n_45,YRegister_n_46,YRegister_n_47,YRegister_n_48,YRegister_n_49,YRegister_n_50,YRegister_n_51,YRegister_n_52,YRegister_n_53,YRegister_n_54,YRegister_n_55,YRegister_n_56,YRegister_n_57,YRegister_n_58}),
.\Q_reg[0]_0 ({YRegister_n_59,YRegister_n_60,YRegister_n_61,YRegister_n_62}),
.\Q_reg[0]_1 ({YRegister_n_63,YRegister_n_64,YRegister_n_65,YRegister_n_66}),
.\Q_reg[0]_2 ({YRegister_n_67,YRegister_n_68,YRegister_n_69,YRegister_n_70}),
.\Q_reg[0]_3 ({YRegister_n_71,YRegister_n_72,YRegister_n_73,YRegister_n_74}),
.\Q_reg[0]_4 (YRegister_n_75),
.\Q_reg[0]_5 (\Q_reg[0]_0 ),
.\Q_reg[0]_6 (intAS),
.\Q_reg[23]_0 (\Q_reg[23] ),
.\Q_reg[31]_0 ({XRegister_n_121,XRegister_n_122,XRegister_n_123}),
.\Q_reg[31]_1 ({XRegister_n_124,XRegister_n_125,XRegister_n_126,XRegister_n_127}),
.\Q_reg[31]_10 (\Q_reg[31]_3 ),
.\Q_reg[31]_11 ({XRegister_n_144,XRegister_n_145}),
.\Q_reg[31]_12 (\Q_reg[31]_4 ),
.\Q_reg[31]_13 ({\Q_reg[0] ,XRegister_n_2,XRegister_n_3,XRegister_n_4,XRegister_n_5,XRegister_n_6,XRegister_n_7,XRegister_n_8,XRegister_n_9,XRegister_n_10,XRegister_n_11,XRegister_n_12,XRegister_n_13,XRegister_n_14,XRegister_n_15,XRegister_n_16,XRegister_n_17,XRegister_n_18,XRegister_n_19,XRegister_n_20,XRegister_n_21,XRegister_n_22,XRegister_n_23,XRegister_n_24,XRegister_n_25,XRegister_n_26,XRegister_n_27,XRegister_n_28,XRegister_n_29,XRegister_n_30,XRegister_n_31,XRegister_n_32}),
.\Q_reg[31]_2 (\Q_reg[31] ),
.\Q_reg[31]_3 ({XRegister_n_128,XRegister_n_129,XRegister_n_130,XRegister_n_131}),
.\Q_reg[31]_4 (\Q_reg[31]_0 ),
.\Q_reg[31]_5 ({XRegister_n_132,XRegister_n_133,XRegister_n_134,XRegister_n_135}),
.\Q_reg[31]_6 (\Q_reg[31]_1 ),
.\Q_reg[31]_7 ({XRegister_n_136,XRegister_n_137,XRegister_n_138,XRegister_n_139}),
.\Q_reg[31]_8 (\Q_reg[31]_2 ),
.\Q_reg[31]_9 ({XRegister_n_140,XRegister_n_141,XRegister_n_142,XRegister_n_143}),
.S(S));
RegisterAdd__parameterized4 mRegister
(.CLK(CLK),
.D({XRegister_n_90,XRegister_n_91,XRegister_n_92,XRegister_n_93,XRegister_n_94,XRegister_n_95,XRegister_n_96,XRegister_n_97,XRegister_n_98,XRegister_n_99,XRegister_n_100,XRegister_n_101,XRegister_n_102,XRegister_n_103,XRegister_n_104,XRegister_n_105,XRegister_n_106,XRegister_n_107,XRegister_n_108,XRegister_n_109,XRegister_n_110,XRegister_n_111,XRegister_n_112,XRegister_n_113,XRegister_n_114,XRegister_n_115,XRegister_n_116,XRegister_n_117,XRegister_n_118,XRegister_n_119,XRegister_n_120}),
.\FSM_sequential_state_reg_reg[3] (\FSM_sequential_state_reg_reg[3]_0 ),
.\FSM_sequential_state_reg_reg[3]_0 (\FSM_sequential_state_reg_reg[3]_1 [0]),
.\Q_reg[7]_0 (\Q_reg[7]_0 ));
endmodule
module RegisterAdd
(\Q_reg[0]_0 ,
\FSM_sequential_state_reg_reg[0] ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output \Q_reg[0]_0 ;
input \FSM_sequential_state_reg_reg[0] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire \FSM_sequential_state_reg_reg[0] ;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire \Q_reg[0]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(\Q_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_0
(FSM_selector_C,
\FSM_sequential_state_reg_reg[3] ,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output FSM_selector_C;
input \FSM_sequential_state_reg_reg[3] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire FSM_selector_C;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\FSM_sequential_state_reg_reg[3] ),
.Q(FSM_selector_C));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(FSM_selector_D,
\Q_reg[3] ,
\FSM_sequential_state_reg_reg[0] ,
CLK,
\FSM_sequential_state_reg_reg[3] ,
\Q_reg[0]_0 );
output FSM_selector_D;
output \Q_reg[3] ;
input \FSM_sequential_state_reg_reg[0] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [0:0]\Q_reg[0]_0 ;
wire CLK;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[0] ;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[3] ;
LUT2 #(
.INIT(4'h8))
\Q[3]_i_2__0
(.I0(FSM_selector_D),
.I1(\Q_reg[0]_0 ),
.O(\Q_reg[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\FSM_sequential_state_reg_reg[0] ),
.Q(FSM_selector_D));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_2
(\Q_reg[0]_0 ,
E,
add_subt_IBUF,
CLK,
AR);
output \Q_reg[0]_0 ;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire \Q_reg[0]_0 ;
wire add_subt_IBUF;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(add_subt_IBUF),
.Q(\Q_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_3
(sign_final_result,
\FSM_sequential_state_reg_reg[3] ,
sign_result,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output sign_final_result;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input sign_result;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire sign_final_result;
wire sign_result;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(sign_result),
.Q(sign_final_result));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_4
(\Q_reg[22] ,
D,
E,
CLK,
AR,
\Q_reg[24] ,
\Q_reg[0]_0 ,
O,
\Q_reg[1] );
output \Q_reg[22] ;
output [22:0]D;
input [0:0]E;
input CLK;
input [0:0]AR;
input [22:0]\Q_reg[24] ;
input \Q_reg[0]_0 ;
input [0:0]O;
input [7:0]\Q_reg[1] ;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [0:0]E;
wire [0:0]O;
wire \Q[0]_i_1__8_n_0 ;
wire \Q[0]_i_3__1_n_0 ;
wire \Q_reg[0]_0 ;
wire [7:0]\Q_reg[1] ;
wire \Q_reg[22] ;
wire [22:0]\Q_reg[24] ;
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h02))
\Q[0]_i_1__5
(.I0(\Q_reg[24] [0]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'hBAAAAAAAAAAAAAAA))
\Q[0]_i_1__8
(.I0(O),
.I1(\Q[0]_i_3__1_n_0 ),
.I2(\Q_reg[1] [6]),
.I3(\Q_reg[1] [4]),
.I4(\Q_reg[1] [7]),
.I5(\Q_reg[1] [5]),
.O(\Q[0]_i_1__8_n_0 ));
LUT4 #(
.INIT(16'h7FFF))
\Q[0]_i_3__1
(.I0(\Q_reg[1] [1]),
.I1(\Q_reg[1] [3]),
.I2(\Q_reg[1] [2]),
.I3(\Q_reg[1] [0]),
.O(\Q[0]_i_3__1_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__1
(.I0(\Q_reg[24] [10]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__1
(.I0(\Q_reg[24] [11]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h02))
\Q[12]_i_1__1
(.I0(\Q_reg[24] [12]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'h02))
\Q[13]_i_1__1
(.I0(\Q_reg[24] [13]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__1
(.I0(\Q_reg[24] [14]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__1
(.I0(\Q_reg[24] [15]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h02))
\Q[16]_i_1__1
(.I0(\Q_reg[24] [16]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'h02))
\Q[17]_i_1__1
(.I0(\Q_reg[24] [17]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h02))
\Q[18]_i_1__1
(.I0(\Q_reg[24] [18]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'h02))
\Q[19]_i_1__1
(.I0(\Q_reg[24] [19]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'h02))
\Q[1]_i_1__2
(.I0(\Q_reg[24] [1]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h02))
\Q[20]_i_1__1
(.I0(\Q_reg[24] [20]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'h02))
\Q[21]_i_1__1
(.I0(\Q_reg[24] [21]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[21]));
LUT3 #(
.INIT(8'h02))
\Q[22]_i_1__1
(.I0(\Q_reg[24] [22]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[22]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h02))
\Q[2]_i_1__2
(.I0(\Q_reg[24] [2]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'h02))
\Q[3]_i_1__2
(.I0(\Q_reg[24] [3]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h02))
\Q[4]_i_1__2
(.I0(\Q_reg[24] [4]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'h02))
\Q[5]_i_1__1
(.I0(\Q_reg[24] [5]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__1
(.I0(\Q_reg[24] [6]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__2
(.I0(\Q_reg[24] [7]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h02))
\Q[8]_i_1__1
(.I0(\Q_reg[24] [8]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'h02))
\Q[9]_i_1__1
(.I0(\Q_reg[24] [9]),
.I1(\Q_reg[22] ),
.I2(\Q_reg[0]_0 ),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q[0]_i_1__8_n_0 ),
.Q(\Q_reg[22] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_5
(\Q_reg[31] ,
D,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
CLK,
AR,
sign_final_result,
\Q_reg[0]_2 ,
O,
\Q_reg[1] );
output \Q_reg[31] ;
output [0:0]D;
output \Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
input CLK;
input [0:0]AR;
input sign_final_result;
input \Q_reg[0]_2 ;
input [0:0]O;
input [4:0]\Q_reg[1] ;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]O;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [4:0]\Q_reg[1] ;
wire \Q_reg[31] ;
wire sign_final_result;
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFFE))
\Q[0]_i_2__1
(.I0(O),
.I1(\Q_reg[1] [1]),
.I2(\Q_reg[1] [3]),
.I3(\Q_reg[1] [4]),
.I4(\Q_reg[1] [0]),
.I5(\Q_reg[1] [2]),
.O(\Q_reg[0]_0 ));
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_2__0
(.I0(sign_final_result),
.I1(\Q_reg[31] ),
.I2(\Q_reg[0]_2 ),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\Q_reg[0]_1 ),
.Q(\Q_reg[31] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_6
(add_overflow_flag,
E,
O,
CLK,
AR);
output add_overflow_flag;
input [0:0]E;
input [0:0]O;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire [0:0]O;
wire add_overflow_flag;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(O),
.Q(add_overflow_flag));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(\Q_reg[7] ,
\Q_reg[3] ,
DI,
O,
\Q_reg[25] ,
\Q_reg[25]_0 ,
\Q_reg[25]_1 ,
D,
\Q_reg[9] ,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[8] ,
FSM_selector_B,
\Q_reg[21] ,
\Q_reg[7]_0 ,
Data_A,
FSM_exp_operation_A_S,
\Q_reg[26] ,
S,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
FSM_barrel_shifter_B_S,
\Q_reg[0]_4 ,
FSM_barrel_shifter_L_R,
\Q_reg[25]_2 ,
Q,
\Q_reg[16] ,
\Q_reg[24] ,
\Q_reg[17] ,
\Q_reg[23] ,
\Q_reg[18] ,
\Q_reg[22] ,
\Q_reg[19] ,
\Q_reg[21]_0 ,
\Q_reg[20] ,
\Q_reg[0]_5 ,
\Q_reg[4] ,
\Q_reg[4]_0 ,
\Q_reg[30] ,
add_overflow_flag,
out,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [7:0]\Q_reg[7] ;
output [2:0]\Q_reg[3] ;
output [0:0]DI;
output [0:0]O;
output [2:0]\Q_reg[25] ;
output \Q_reg[25]_0 ;
output \Q_reg[25]_1 ;
output [15:0]D;
output \Q_reg[9] ;
output \Q_reg[0]_0 ;
output \Q_reg[0]_1 ;
output \Q_reg[8] ;
output [1:0]FSM_selector_B;
output \Q_reg[21] ;
output \Q_reg[7]_0 ;
input [0:0]Data_A;
input FSM_exp_operation_A_S;
input [3:0]\Q_reg[26] ;
input [3:0]S;
input [0:0]\Q_reg[0]_2 ;
input \Q_reg[0]_3 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[0]_4 ;
input FSM_barrel_shifter_L_R;
input \Q_reg[25]_2 ;
input [15:0]Q;
input \Q_reg[16] ;
input \Q_reg[24] ;
input \Q_reg[17] ;
input \Q_reg[23] ;
input \Q_reg[18] ;
input \Q_reg[22] ;
input \Q_reg[19] ;
input \Q_reg[21]_0 ;
input \Q_reg[20] ;
input \Q_reg[0]_5 ;
input [4:0]\Q_reg[4] ;
input [4:0]\Q_reg[4]_0 ;
input [6:0]\Q_reg[30] ;
input add_overflow_flag;
input [3:0]out;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [15:0]D;
wire [0:0]DI;
wire [0:0]Data_A;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]O;
wire [15:0]Q;
wire \Q[0]_i_1_n_0 ;
wire \Q[13]_i_2_n_0 ;
wire \Q[13]_i_3_n_0 ;
wire \Q[14]_i_2_n_0 ;
wire \Q[14]_i_3_n_0 ;
wire \Q[15]_i_2_n_0 ;
wire \Q[15]_i_3_n_0 ;
wire \Q[1]_i_1__0_n_0 ;
wire \Q[7]_i_3__0_n_0 ;
wire \Q[7]_i_4_n_0 ;
wire \Q[7]_i_5_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire \Q_reg[0]_3 ;
wire \Q_reg[0]_4 ;
wire \Q_reg[0]_5 ;
wire \Q_reg[16] ;
wire \Q_reg[17] ;
wire \Q_reg[18] ;
wire \Q_reg[19] ;
wire \Q_reg[20] ;
wire \Q_reg[21] ;
wire \Q_reg[21]_0 ;
wire \Q_reg[22] ;
wire \Q_reg[23] ;
wire \Q_reg[24] ;
wire [2:0]\Q_reg[25] ;
wire \Q_reg[25]_0 ;
wire \Q_reg[25]_1 ;
wire \Q_reg[25]_2 ;
wire [3:0]\Q_reg[26] ;
wire [6:0]\Q_reg[30] ;
wire [2:0]\Q_reg[3] ;
wire \Q_reg[3]_i_1__0_n_0 ;
wire \Q_reg[3]_i_1__0_n_1 ;
wire \Q_reg[3]_i_1__0_n_2 ;
wire \Q_reg[3]_i_1__0_n_3 ;
wire [4:0]\Q_reg[4] ;
wire [4:0]\Q_reg[4]_0 ;
wire [7:0]\Q_reg[7] ;
wire \Q_reg[7]_0 ;
wire \Q_reg[7]_i_2_n_0 ;
wire \Q_reg[7]_i_2_n_1 ;
wire \Q_reg[7]_i_2_n_2 ;
wire \Q_reg[7]_i_2_n_3 ;
wire \Q_reg[8] ;
wire \Q_reg[9] ;
wire [3:0]S;
wire add_overflow_flag;
wire [3:0]out;
wire [3:0]\NLW_Q_reg[0]_i_2__0_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[0]_i_2__0_O_UNCONNECTED ;
LUT6 #(
.INIT(64'hDFFFFFDF10000010))
\Q[0]_i_1
(.I0(add_overflow_flag),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.I4(out[2]),
.I5(FSM_selector_B[0]),
.O(\Q[0]_i_1_n_0 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[0]_i_1__1
(.I0(\Q_reg[0]_0 ),
.I1(Q[15]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[16] ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1
(.I0(\Q[15]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[15]_i_2_n_0 ),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1
(.I0(\Q[14]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[14]_i_2_n_0 ),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1
(.I0(\Q[13]_i_3_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[13]_i_2_n_0 ),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1
(.I0(\Q[13]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[13]_i_3_n_0 ),
.O(D[13]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[13]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[2]),
.I3(\Q_reg[0]_1 ),
.I4(Q[10]),
.O(\Q[13]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[13]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[3]),
.I3(\Q_reg[0]_1 ),
.I4(Q[11]),
.O(\Q[13]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1
(.I0(\Q[14]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[14]_i_3_n_0 ),
.O(D[14]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[14]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[1]),
.I3(\Q_reg[0]_1 ),
.I4(Q[9]),
.O(\Q[14]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[14]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[4]),
.I3(\Q_reg[0]_1 ),
.I4(Q[12]),
.O(\Q[14]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1
(.I0(\Q[15]_i_2_n_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q[15]_i_3_n_0 ),
.O(D[15]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[15]_i_2
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[0]),
.I3(\Q_reg[0]_1 ),
.I4(Q[8]),
.O(\Q[15]_i_2_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[15]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[5]),
.I3(\Q_reg[0]_1 ),
.I4(Q[13]),
.O(\Q[15]_i_3_n_0 ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[6]),
.I3(\Q_reg[0]_1 ),
.I4(Q[14]),
.O(\Q_reg[9] ));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_3
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[0]_0 ),
.I2(Q[7]),
.I3(\Q_reg[0]_1 ),
.I4(Q[15]),
.O(\Q_reg[8] ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[1]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[14]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[17] ),
.O(D[1]));
LUT6 #(
.INIT(64'hEFFFFFFF20000030))
\Q[1]_i_1__0
(.I0(add_overflow_flag),
.I1(out[0]),
.I2(out[3]),
.I3(out[1]),
.I4(out[2]),
.I5(FSM_selector_B[1]),
.O(\Q[1]_i_1__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT5 #(
.INIT(32'hB8BBB888))
\Q[22]_i_1__0
(.I0(FSM_barrel_shifter_B_S),
.I1(\Q_reg[25]_0 ),
.I2(\Q_reg[0]_5 ),
.I3(\Q_reg[25]_1 ),
.I4(\Q_reg[0]_4 ),
.O(\Q_reg[25] [0]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT4 #(
.INIT(16'hEF40))
\Q[24]_i_1
(.I0(\Q_reg[25]_0 ),
.I1(\Q_reg[0]_4 ),
.I2(\Q_reg[25]_1 ),
.I3(FSM_barrel_shifter_B_S),
.O(\Q_reg[25] [1]));
LUT4 #(
.INIT(16'hEF40))
\Q[25]_i_1__0
(.I0(\Q_reg[25]_0 ),
.I1(\Q_reg[0]_3 ),
.I2(\Q_reg[25]_1 ),
.I3(FSM_barrel_shifter_B_S),
.O(\Q_reg[25] [2]));
LUT4 #(
.INIT(16'h2320))
\Q[25]_i_2__0
(.I0(\Q_reg[4] [2]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [2]),
.O(\Q_reg[25]_0 ));
LUT4 #(
.INIT(16'hDCDF))
\Q[25]_i_4__0
(.I0(\Q_reg[4] [1]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [1]),
.O(\Q_reg[25]_1 ));
LUT4 #(
.INIT(16'h2320))
\Q[25]_i_5
(.I0(\Q_reg[4] [4]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [4]),
.O(\Q_reg[0]_0 ));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT4 #(
.INIT(16'h22FC))
\Q[25]_i_5__0
(.I0(\Q_reg[4] [0]),
.I1(FSM_selector_B[1]),
.I2(\Q_reg[4]_0 [0]),
.I3(FSM_selector_B[0]),
.O(\Q_reg[21] ));
LUT4 #(
.INIT(16'hDCDF))
\Q[25]_i_6
(.I0(\Q_reg[4] [3]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[4]_0 [3]),
.O(\Q_reg[0]_1 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[2]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[13]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[18] ),
.O(D[2]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[3]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[12]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[19] ),
.O(D[3]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_3__0
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [2]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [3]),
.O(\Q_reg[3] [2]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [1]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [2]),
.O(\Q_reg[3] [1]));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[3]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [0]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [1]),
.O(\Q_reg[3] [0]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[4]_i_1__0
(.I0(\Q_reg[0]_0 ),
.I1(Q[11]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[20] ),
.O(D[4]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[5]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[10]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[21]_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[6]_i_1
(.I0(\Q_reg[0]_0 ),
.I1(Q[9]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[22] ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT2 #(
.INIT(4'hE))
\Q[7]_i_11
(.I0(FSM_selector_B[1]),
.I1(FSM_selector_B[0]),
.O(\Q_reg[7]_0 ));
LUT6 #(
.INIT(64'hEF40FFFFEF400000))
\Q[7]_i_1__0
(.I0(\Q_reg[0]_0 ),
.I1(Q[8]),
.I2(\Q_reg[0]_1 ),
.I3(FSM_barrel_shifter_B_S),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q_reg[23] ),
.O(D[7]));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_3__0
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [6]),
.O(\Q[7]_i_3__0_n_0 ));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_4
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [5]),
.O(\Q[7]_i_4_n_0 ));
LUT4 #(
.INIT(16'hA9AA))
\Q[7]_i_5
(.I0(FSM_exp_operation_A_S),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[30] [4]),
.O(\Q[7]_i_5_n_0 ));
LUT5 #(
.INIT(32'hAA56AAA6))
\Q[7]_i_6
(.I0(FSM_exp_operation_A_S),
.I1(\Q_reg[30] [3]),
.I2(FSM_selector_B[0]),
.I3(FSM_selector_B[1]),
.I4(\Q_reg[4] [4]),
.O(DI));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1
(.I0(\Q_reg[8] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[24] ),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1
(.I0(\Q_reg[9] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[25]_2 ),
.O(D[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q[0]_i_1_n_0 ),
.Q(FSM_selector_B[0]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[0]_i_2__0
(.CI(\Q_reg[7]_i_2_n_0 ),
.CO(\NLW_Q_reg[0]_i_2__0_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[0]_i_2__0_O_UNCONNECTED [3:1],O}),
.S({1'b0,1'b0,1'b0,\Q_reg[0]_2 }));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q[1]_i_1__0_n_0 ),
.Q(FSM_selector_B[1]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[3]_i_1__0
(.CI(1'b0),
.CO({\Q_reg[3]_i_1__0_n_0 ,\Q_reg[3]_i_1__0_n_1 ,\Q_reg[3]_i_1__0_n_2 ,\Q_reg[3]_i_1__0_n_3 }),
.CYINIT(Data_A),
.DI({\Q_reg[3] ,FSM_exp_operation_A_S}),
.O(\Q_reg[7] [3:0]),
.S(\Q_reg[26] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[7]_i_2
(.CI(\Q_reg[3]_i_1__0_n_0 ),
.CO({\Q_reg[7]_i_2_n_0 ,\Q_reg[7]_i_2_n_1 ,\Q_reg[7]_i_2_n_2 ,\Q_reg[7]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({\Q[7]_i_3__0_n_0 ,\Q[7]_i_4_n_0 ,\Q[7]_i_5_n_0 ,DI}),
.O(\Q_reg[7] [7:4]),
.S(S));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(sign_result,
Q,
\Q_reg[0]_0 ,
DI,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
D,
\Q_reg[30]_0 ,
\Q_reg[3]_0 ,
\Q_reg[7]_0 ,
\Q_reg[11]_0 ,
\Q_reg[15]_0 ,
\Q_reg[19]_0 ,
\Q_reg[23]_0 ,
\Q_reg[0]_6 ,
\FSM_sequential_state_reg_reg[3] ,
CO,
\Q_reg[31]_0 ,
\Q_reg[0]_7 ,
\Q_reg[30]_1 ,
FSM_selector_D,
\Q_reg[25]_0 ,
E,
\Data_X[31] ,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output sign_result;
output [31:0]Q;
output [3:0]\Q_reg[0]_0 ;
output [3:0]DI;
output [3:0]\Q_reg[0]_1 ;
output [3:0]\Q_reg[0]_2 ;
output [3:0]\Q_reg[0]_3 ;
output [1:0]\Q_reg[0]_4 ;
output [3:0]\Q_reg[0]_5 ;
output [30:0]D;
output [30:0]\Q_reg[30]_0 ;
output [2:0]\Q_reg[3]_0 ;
output [3:0]\Q_reg[7]_0 ;
output [3:0]\Q_reg[11]_0 ;
output [3:0]\Q_reg[15]_0 ;
output [3:0]\Q_reg[19]_0 ;
output [3:0]\Q_reg[23]_0 ;
output [1:0]\Q_reg[0]_6 ;
output \FSM_sequential_state_reg_reg[3] ;
input [0:0]CO;
input [31:0]\Q_reg[31]_0 ;
input \Q_reg[0]_7 ;
input [0:0]\Q_reg[30]_1 ;
input FSM_selector_D;
input [24:0]\Q_reg[25]_0 ;
input [0:0]E;
input [31:0]\Data_X[31] ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [0:0]CO;
wire [30:0]D;
wire [3:0]DI;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire FSM_selector_D;
wire \FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [31:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [3:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[0]_3 ;
wire [1:0]\Q_reg[0]_4 ;
wire [3:0]\Q_reg[0]_5 ;
wire [1:0]\Q_reg[0]_6 ;
wire \Q_reg[0]_7 ;
wire [3:0]\Q_reg[11]_0 ;
wire [3:0]\Q_reg[15]_0 ;
wire [3:0]\Q_reg[19]_0 ;
wire [3:0]\Q_reg[23]_0 ;
wire [24:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[30]_1 ;
wire [31:0]\Q_reg[31]_0 ;
wire [2:0]\Q_reg[3]_0 ;
wire [3:0]\Q_reg[7]_0 ;
wire sign_result;
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'h69))
\FSM_sequential_state_reg[3]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.O(\FSM_sequential_state_reg_reg[3] ));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT5 #(
.INIT(32'hCCCC0DD0))
\Q[0]_i_1__3
(.I0(CO),
.I1(Q[31]),
.I2(\Q_reg[31]_0 [31]),
.I3(\Q_reg[0]_7 ),
.I4(\Q_reg[30]_1 ),
.O(sign_result));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1__6
(.I0(Q[0]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hB8))
\Q[0]_i_1__7
(.I0(\Q_reg[31]_0 [0]),
.I1(\Q_reg[30]_1 ),
.I2(Q[0]),
.O(\Q_reg[30]_0 [0]));
LUT5 #(
.INIT(32'h00690096))
\Q[0]_i_3__2
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [24]),
.O(\Q_reg[0]_6 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[0]_i_4__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [23]),
.O(\Q_reg[0]_6 [0]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__2
(.I0(Q[10]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [10]),
.O(D[10]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__3
(.I0(\Q_reg[31]_0 [10]),
.I1(\Q_reg[30]_1 ),
.I2(Q[10]),
.O(\Q_reg[30]_0 [10]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__2
(.I0(Q[11]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [11]),
.O(D[11]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__3
(.I0(\Q_reg[31]_0 [11]),
.I1(\Q_reg[30]_1 ),
.I2(Q[11]),
.O(\Q_reg[30]_0 [11]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_2__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [10]),
.O(\Q_reg[11]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [9]),
.O(\Q_reg[11]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [8]),
.O(\Q_reg[11]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[11]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[11]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1__2
(.I0(Q[12]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [12]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_1__3
(.I0(\Q_reg[31]_0 [12]),
.I1(\Q_reg[30]_1 ),
.I2(Q[12]),
.O(\Q_reg[30]_0 [12]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1__2
(.I0(Q[13]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [13]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hB8))
\Q[13]_i_1__3
(.I0(\Q_reg[31]_0 [13]),
.I1(\Q_reg[30]_1 ),
.I2(Q[13]),
.O(\Q_reg[30]_0 [13]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__2
(.I0(Q[14]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [14]),
.O(D[14]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__3
(.I0(\Q_reg[31]_0 [14]),
.I1(\Q_reg[30]_1 ),
.I2(Q[14]),
.O(\Q_reg[30]_0 [14]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__2
(.I0(Q[15]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [15]),
.O(D[15]));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__3
(.I0(\Q_reg[31]_0 [15]),
.I1(\Q_reg[30]_1 ),
.I2(Q[15]),
.O(\Q_reg[30]_0 [15]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [14]),
.O(\Q_reg[15]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [13]),
.O(\Q_reg[15]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [12]),
.O(\Q_reg[15]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[15]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [11]),
.O(\Q_reg[15]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1__2
(.I0(Q[16]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [16]),
.O(D[16]));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1__3
(.I0(\Q_reg[31]_0 [16]),
.I1(\Q_reg[30]_1 ),
.I2(Q[16]),
.O(\Q_reg[30]_0 [16]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1__2
(.I0(Q[17]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [17]),
.O(D[17]));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1__3
(.I0(\Q_reg[31]_0 [17]),
.I1(\Q_reg[30]_1 ),
.I2(Q[17]),
.O(\Q_reg[30]_0 [17]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__2
(.I0(Q[18]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [18]),
.O(D[18]));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__3
(.I0(\Q_reg[31]_0 [18]),
.I1(\Q_reg[30]_1 ),
.I2(Q[18]),
.O(\Q_reg[30]_0 [18]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__2
(.I0(Q[19]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [19]),
.O(D[19]));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__3
(.I0(\Q_reg[31]_0 [19]),
.I1(\Q_reg[30]_1 ),
.I2(Q[19]),
.O(\Q_reg[30]_0 [19]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [18]),
.O(\Q_reg[19]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [17]),
.O(\Q_reg[19]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [16]),
.O(\Q_reg[19]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[19]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [15]),
.O(\Q_reg[19]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__3
(.I0(Q[1]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__4
(.I0(\Q_reg[31]_0 [1]),
.I1(\Q_reg[30]_1 ),
.I2(Q[1]),
.O(\Q_reg[30]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__2
(.I0(Q[20]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [20]),
.O(D[20]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__3
(.I0(\Q_reg[31]_0 [20]),
.I1(\Q_reg[30]_1 ),
.I2(Q[20]),
.O(\Q_reg[30]_0 [20]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__2
(.I0(Q[21]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [21]),
.O(D[21]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__3
(.I0(\Q_reg[31]_0 [21]),
.I1(\Q_reg[30]_1 ),
.I2(Q[21]),
.O(\Q_reg[30]_0 [21]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__2
(.I0(Q[22]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [22]),
.O(D[22]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__3
(.I0(\Q_reg[31]_0 [22]),
.I1(\Q_reg[30]_1 ),
.I2(Q[22]),
.O(\Q_reg[30]_0 [22]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__2
(.I0(Q[23]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [23]),
.O(D[23]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__3
(.I0(\Q_reg[31]_0 [23]),
.I1(\Q_reg[30]_1 ),
.I2(Q[23]),
.O(\Q_reg[30]_0 [23]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [22]),
.O(\Q_reg[23]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_3__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [21]),
.O(\Q_reg[23]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_4
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [20]),
.O(\Q_reg[23]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[23]_i_5
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [19]),
.O(\Q_reg[23]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__2
(.I0(Q[24]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [24]),
.O(D[24]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__3
(.I0(\Q_reg[31]_0 [24]),
.I1(\Q_reg[30]_1 ),
.I2(Q[24]),
.O(\Q_reg[30]_0 [24]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\Q[25]_i_1__2
(.I0(Q[25]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [25]),
.O(D[25]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hB8))
\Q[25]_i_1__3
(.I0(\Q_reg[31]_0 [25]),
.I1(\Q_reg[30]_1 ),
.I2(Q[25]),
.O(\Q_reg[30]_0 [25]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\Q[26]_i_1__0
(.I0(Q[26]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [26]),
.O(D[26]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hB8))
\Q[26]_i_1__1
(.I0(\Q_reg[31]_0 [26]),
.I1(\Q_reg[30]_1 ),
.I2(Q[26]),
.O(\Q_reg[30]_0 [26]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\Q[27]_i_1__0
(.I0(Q[27]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [27]),
.O(D[27]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hB8))
\Q[27]_i_1__1
(.I0(\Q_reg[31]_0 [27]),
.I1(\Q_reg[30]_1 ),
.I2(Q[27]),
.O(\Q_reg[30]_0 [27]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\Q[28]_i_1__0
(.I0(Q[28]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [28]),
.O(D[28]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hB8))
\Q[28]_i_1__1
(.I0(\Q_reg[31]_0 [28]),
.I1(\Q_reg[30]_1 ),
.I2(Q[28]),
.O(\Q_reg[30]_0 [28]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\Q[29]_i_1__0
(.I0(Q[29]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [29]),
.O(D[29]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hB8))
\Q[29]_i_1__1
(.I0(\Q_reg[31]_0 [29]),
.I1(\Q_reg[30]_1 ),
.I2(Q[29]),
.O(\Q_reg[30]_0 [29]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__3
(.I0(Q[2]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [2]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__4
(.I0(\Q_reg[31]_0 [2]),
.I1(\Q_reg[30]_1 ),
.I2(Q[2]),
.O(\Q_reg[30]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\Q[30]_i_1__1
(.I0(\Q_reg[31]_0 [30]),
.I1(\Q_reg[30]_1 ),
.I2(Q[30]),
.O(\Q_reg[30]_0 [30]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hB8))
\Q[30]_i_2
(.I0(Q[30]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [30]),
.O(D[30]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__3
(.I0(Q[3]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [3]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__4
(.I0(\Q_reg[31]_0 [3]),
.I1(\Q_reg[30]_1 ),
.I2(Q[3]),
.O(\Q_reg[30]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[3]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [2]),
.O(\Q_reg[3]_0 [2]));
LUT5 #(
.INIT(32'hFFFF6996))
\Q[3]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(\Q_reg[25]_0 [1]),
.I4(FSM_selector_D),
.O(\Q_reg[3]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[3]_i_5__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [0]),
.O(\Q_reg[3]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__3
(.I0(Q[4]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [4]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__4
(.I0(\Q_reg[31]_0 [4]),
.I1(\Q_reg[30]_1 ),
.I2(Q[4]),
.O(\Q_reg[30]_0 [4]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__2
(.I0(Q[5]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [5]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__3
(.I0(\Q_reg[31]_0 [5]),
.I1(\Q_reg[30]_1 ),
.I2(Q[5]),
.O(\Q_reg[30]_0 [5]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__2
(.I0(Q[6]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [6]),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__3
(.I0(\Q_reg[31]_0 [6]),
.I1(\Q_reg[30]_1 ),
.I2(Q[6]),
.O(\Q_reg[30]_0 [6]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__3
(.I0(Q[7]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [7]),
.O(D[7]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__4
(.I0(\Q_reg[31]_0 [7]),
.I1(\Q_reg[30]_1 ),
.I2(Q[7]),
.O(\Q_reg[30]_0 [7]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_2__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[7]_0 [3]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_3__1
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [5]),
.O(\Q_reg[7]_0 [2]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_4__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [4]),
.O(\Q_reg[7]_0 [1]));
LUT5 #(
.INIT(32'h00690096))
\Q[7]_i_5__0
(.I0(Q[31]),
.I1(\Q_reg[0]_7 ),
.I2(\Q_reg[31]_0 [31]),
.I3(FSM_selector_D),
.I4(\Q_reg[25]_0 [3]),
.O(\Q_reg[7]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1__2
(.I0(Q[8]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hB8))
\Q[8]_i_1__3
(.I0(\Q_reg[31]_0 [8]),
.I1(\Q_reg[30]_1 ),
.I2(Q[8]),
.O(\Q_reg[30]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1__2
(.I0(Q[9]),
.I1(\Q_reg[30]_1 ),
.I2(\Q_reg[31]_0 [9]),
.O(D[9]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hB8))
\Q[9]_i_1__3
(.I0(\Q_reg[31]_0 [9]),
.I1(\Q_reg[30]_1 ),
.I2(Q[9]),
.O(\Q_reg[30]_0 [9]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(\Data_X[31] [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.I4(\Q_reg[31]_0 [21]),
.I5(Q[21]),
.O(\Q_reg[0]_2 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.I4(\Q_reg[31]_0 [20]),
.I5(Q[20]),
.O(\Q_reg[0]_2 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.I4(\Q_reg[31]_0 [15]),
.I5(Q[15]),
.O(\Q_reg[0]_2 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.I4(\Q_reg[31]_0 [14]),
.I5(Q[14]),
.O(\Q_reg[0]_2 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.I4(\Q_reg[31]_0 [27]),
.I5(Q[27]),
.O(\Q_reg[0]_4 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.I4(\Q_reg[31]_0 [26]),
.I5(Q[26]),
.O(\Q_reg[0]_4 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.I4(\Q_reg[31]_0 [9]),
.I5(Q[9]),
.O(\Q_reg[0]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.I4(\Q_reg[31]_0 [8]),
.I5(Q[8]),
.O(\Q_reg[0]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.I4(\Q_reg[31]_0 [3]),
.I5(Q[3]),
.O(\Q_reg[0]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.I4(\Q_reg[31]_0 [2]),
.I5(Q[2]),
.O(\Q_reg[0]_0 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_1
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(Q[14]),
.I3(\Q_reg[31]_0 [14]),
.O(\Q_reg[0]_1 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_2
(.I0(Q[13]),
.I1(\Q_reg[31]_0 [13]),
.I2(Q[12]),
.I3(\Q_reg[31]_0 [12]),
.O(\Q_reg[0]_1 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_3
(.I0(Q[11]),
.I1(\Q_reg[31]_0 [11]),
.I2(Q[10]),
.I3(\Q_reg[31]_0 [10]),
.O(\Q_reg[0]_1 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__0_i_4
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(Q[8]),
.I3(\Q_reg[31]_0 [8]),
.O(\Q_reg[0]_1 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_1
(.I0(Q[23]),
.I1(\Q_reg[31]_0 [23]),
.I2(Q[22]),
.I3(\Q_reg[31]_0 [22]),
.O(\Q_reg[0]_3 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_2
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(Q[20]),
.I3(\Q_reg[31]_0 [20]),
.O(\Q_reg[0]_3 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_3
(.I0(Q[19]),
.I1(\Q_reg[31]_0 [19]),
.I2(Q[18]),
.I3(\Q_reg[31]_0 [18]),
.O(\Q_reg[0]_3 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__1_i_4
(.I0(Q[17]),
.I1(\Q_reg[31]_0 [17]),
.I2(Q[16]),
.I3(\Q_reg[31]_0 [16]),
.O(\Q_reg[0]_3 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(\Q_reg[0]_5 [3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_2
(.I0(Q[29]),
.I1(\Q_reg[31]_0 [29]),
.I2(Q[28]),
.I3(\Q_reg[31]_0 [28]),
.O(\Q_reg[0]_5 [2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_3
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(Q[26]),
.I3(\Q_reg[31]_0 [26]),
.O(\Q_reg[0]_5 [1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry__2_i_4
(.I0(Q[25]),
.I1(\Q_reg[31]_0 [25]),
.I2(Q[24]),
.I3(\Q_reg[31]_0 [24]),
.O(\Q_reg[0]_5 [0]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_1
(.I0(Q[7]),
.I1(\Q_reg[31]_0 [7]),
.I2(Q[6]),
.I3(\Q_reg[31]_0 [6]),
.O(DI[3]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_2
(.I0(Q[5]),
.I1(\Q_reg[31]_0 [5]),
.I2(Q[4]),
.I3(\Q_reg[31]_0 [4]),
.O(DI[2]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(Q[2]),
.I3(\Q_reg[31]_0 [2]),
.O(DI[1]));
LUT4 #(
.INIT(16'h22B2))
gtXY_o_carry_i_4
(.I0(Q[1]),
.I1(\Q_reg[31]_0 [1]),
.I2(Q[0]),
.I3(\Q_reg[31]_0 [0]),
.O(DI[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(\Q_reg[23]_0 ,
O,
Q,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[0]_3 ,
\Q_reg[0]_4 ,
\Q_reg[0]_5 ,
\Q_reg[31]_0 ,
S,
\Q_reg[31]_1 ,
\Q_reg[31]_2 ,
\Q_reg[31]_3 ,
\Q_reg[31]_4 ,
\Q_reg[31]_5 ,
\Q_reg[31]_6 ,
\Q_reg[31]_7 ,
\Q_reg[31]_8 ,
\Q_reg[31]_9 ,
\Q_reg[31]_10 ,
\Q_reg[31]_11 ,
\Q_reg[31]_12 ,
FSM_selector_D,
\Q_reg[0]_6 ,
\Q_reg[31]_13 ,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [23:0]\Q_reg[23]_0 ;
output [2:0]O;
output [31:0]Q;
output [3:0]\Q_reg[0]_0 ;
output [3:0]\Q_reg[0]_1 ;
output [3:0]\Q_reg[0]_2 ;
output [3:0]\Q_reg[0]_3 ;
output [0:0]\Q_reg[0]_4 ;
input \Q_reg[0]_5 ;
input [2:0]\Q_reg[31]_0 ;
input [3:0]S;
input [3:0]\Q_reg[31]_1 ;
input [3:0]\Q_reg[31]_2 ;
input [3:0]\Q_reg[31]_3 ;
input [3:0]\Q_reg[31]_4 ;
input [3:0]\Q_reg[31]_5 ;
input [3:0]\Q_reg[31]_6 ;
input [3:0]\Q_reg[31]_7 ;
input [3:0]\Q_reg[31]_8 ;
input [3:0]\Q_reg[31]_9 ;
input [3:0]\Q_reg[31]_10 ;
input [1:0]\Q_reg[31]_11 ;
input [1:0]\Q_reg[31]_12 ;
input FSM_selector_D;
input \Q_reg[0]_6 ;
input [31:0]\Q_reg[31]_13 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire FSM_selector_D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [2:0]O;
wire [31:0]Q;
wire \Q[3]_i_6__0_n_0 ;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [3:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[0]_3 ;
wire [0:0]\Q_reg[0]_4 ;
wire \Q_reg[0]_5 ;
wire \Q_reg[0]_6 ;
wire \Q_reg[0]_i_2_n_2 ;
wire \Q_reg[0]_i_2_n_3 ;
wire \Q_reg[11]_i_1_n_0 ;
wire \Q_reg[11]_i_1_n_1 ;
wire \Q_reg[11]_i_1_n_2 ;
wire \Q_reg[11]_i_1_n_3 ;
wire \Q_reg[15]_i_1_n_0 ;
wire \Q_reg[15]_i_1_n_1 ;
wire \Q_reg[15]_i_1_n_2 ;
wire \Q_reg[15]_i_1_n_3 ;
wire \Q_reg[19]_i_1_n_0 ;
wire \Q_reg[19]_i_1_n_1 ;
wire \Q_reg[19]_i_1_n_2 ;
wire \Q_reg[19]_i_1_n_3 ;
wire [23:0]\Q_reg[23]_0 ;
wire \Q_reg[23]_i_1_n_0 ;
wire \Q_reg[23]_i_1_n_1 ;
wire \Q_reg[23]_i_1_n_2 ;
wire \Q_reg[23]_i_1_n_3 ;
wire [2:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[31]_1 ;
wire [3:0]\Q_reg[31]_10 ;
wire [1:0]\Q_reg[31]_11 ;
wire [1:0]\Q_reg[31]_12 ;
wire [31:0]\Q_reg[31]_13 ;
wire [3:0]\Q_reg[31]_2 ;
wire [3:0]\Q_reg[31]_3 ;
wire [3:0]\Q_reg[31]_4 ;
wire [3:0]\Q_reg[31]_5 ;
wire [3:0]\Q_reg[31]_6 ;
wire [3:0]\Q_reg[31]_7 ;
wire [3:0]\Q_reg[31]_8 ;
wire [3:0]\Q_reg[31]_9 ;
wire \Q_reg[3]_i_1_n_0 ;
wire \Q_reg[3]_i_1_n_1 ;
wire \Q_reg[3]_i_1_n_2 ;
wire \Q_reg[3]_i_1_n_3 ;
wire \Q_reg[7]_i_1_n_0 ;
wire \Q_reg[7]_i_1_n_1 ;
wire \Q_reg[7]_i_1_n_2 ;
wire \Q_reg[7]_i_1_n_3 ;
wire [3:0]S;
wire S_A_S_op;
wire [3:2]\NLW_Q_reg[0]_i_2_CO_UNCONNECTED ;
wire [3:3]\NLW_Q_reg[0]_i_2_O_UNCONNECTED ;
LUT4 #(
.INIT(16'h4114))
\Q[0]_i_5
(.I0(FSM_selector_D),
.I1(Q[31]),
.I2(\Q_reg[0]_6 ),
.I3(\Q_reg[31]_13 [31]),
.O(S_A_S_op));
LUT4 #(
.INIT(16'h4114))
\Q[3]_i_6__0
(.I0(FSM_selector_D),
.I1(Q[31]),
.I2(\Q_reg[0]_6 ),
.I3(\Q_reg[31]_13 [31]),
.O(\Q[3]_i_6__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[0]),
.Q(Q[0]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[0]_i_2
(.CI(\Q_reg[23]_i_1_n_0 ),
.CO({\NLW_Q_reg[0]_i_2_CO_UNCONNECTED [3:2],\Q_reg[0]_i_2_n_2 ,\Q_reg[0]_i_2_n_3 }),
.CYINIT(1'b0),
.DI({1'b0,1'b0,\Q_reg[31]_11 }),
.O({\NLW_Q_reg[0]_i_2_O_UNCONNECTED [3],O}),
.S({1'b0,S_A_S_op,\Q_reg[31]_12 }));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[11]),
.Q(Q[11]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[11]_i_1
(.CI(\Q_reg[7]_i_1_n_0 ),
.CO({\Q_reg[11]_i_1_n_0 ,\Q_reg[11]_i_1_n_1 ,\Q_reg[11]_i_1_n_2 ,\Q_reg[11]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_3 ),
.O(\Q_reg[23]_0 [11:8]),
.S(\Q_reg[31]_4 ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[15]),
.Q(Q[15]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[15]_i_1
(.CI(\Q_reg[11]_i_1_n_0 ),
.CO({\Q_reg[15]_i_1_n_0 ,\Q_reg[15]_i_1_n_1 ,\Q_reg[15]_i_1_n_2 ,\Q_reg[15]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_5 ),
.O(\Q_reg[23]_0 [15:12]),
.S(\Q_reg[31]_6 ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[19]),
.Q(Q[19]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[19]_i_1
(.CI(\Q_reg[15]_i_1_n_0 ),
.CO({\Q_reg[19]_i_1_n_0 ,\Q_reg[19]_i_1_n_1 ,\Q_reg[19]_i_1_n_2 ,\Q_reg[19]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_7 ),
.O(\Q_reg[23]_0 [19:16]),
.S(\Q_reg[31]_8 ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[23]),
.Q(Q[23]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[23]_i_1
(.CI(\Q_reg[19]_i_1_n_0 ),
.CO({\Q_reg[23]_i_1_n_0 ,\Q_reg[23]_i_1_n_1 ,\Q_reg[23]_i_1_n_2 ,\Q_reg[23]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_9 ),
.O(\Q_reg[23]_0 [23:20]),
.S(\Q_reg[31]_10 ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[3]),
.Q(Q[3]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[3]_i_1
(.CI(1'b0),
.CO({\Q_reg[3]_i_1_n_0 ,\Q_reg[3]_i_1_n_1 ,\Q_reg[3]_i_1_n_2 ,\Q_reg[3]_i_1_n_3 }),
.CYINIT(\Q_reg[0]_5 ),
.DI({\Q_reg[31]_0 ,\Q[3]_i_6__0_n_0 }),
.O(\Q_reg[23]_0 [3:0]),
.S(S));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[7]),
.Q(Q[7]));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 \Q_reg[7]_i_1
(.CI(\Q_reg[3]_i_1_n_0 ),
.CO({\Q_reg[7]_i_1_n_0 ,\Q_reg[7]_i_1_n_1 ,\Q_reg[7]_i_1_n_2 ,\Q_reg[7]_i_1_n_3 }),
.CYINIT(1'b0),
.DI(\Q_reg[31]_1 ),
.O(\Q_reg[23]_0 [7:4]),
.S(\Q_reg[31]_2 ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_13 [30]),
.O(\Q_reg[0]_4 ));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[15]),
.I1(\Q_reg[31]_13 [15]),
.I2(Q[14]),
.I3(\Q_reg[31]_13 [14]),
.O(\Q_reg[0]_1 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[13]),
.I1(\Q_reg[31]_13 [13]),
.I2(Q[12]),
.I3(\Q_reg[31]_13 [12]),
.O(\Q_reg[0]_1 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[11]),
.I1(\Q_reg[31]_13 [11]),
.I2(Q[10]),
.I3(\Q_reg[31]_13 [10]),
.O(\Q_reg[0]_1 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[9]),
.I1(\Q_reg[31]_13 [9]),
.I2(Q[8]),
.I3(\Q_reg[31]_13 [8]),
.O(\Q_reg[0]_1 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[23]),
.I1(\Q_reg[31]_13 [23]),
.I2(Q[22]),
.I3(\Q_reg[31]_13 [22]),
.O(\Q_reg[0]_2 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[21]),
.I1(\Q_reg[31]_13 [21]),
.I2(Q[20]),
.I3(\Q_reg[31]_13 [20]),
.O(\Q_reg[0]_2 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[19]),
.I1(\Q_reg[31]_13 [19]),
.I2(Q[18]),
.I3(\Q_reg[31]_13 [18]),
.O(\Q_reg[0]_2 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[17]),
.I1(\Q_reg[31]_13 [17]),
.I2(Q[16]),
.I3(\Q_reg[31]_13 [16]),
.O(\Q_reg[0]_2 [0]));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[31]_13 [30]),
.O(\Q_reg[0]_3 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[29]),
.I1(\Q_reg[31]_13 [29]),
.I2(Q[28]),
.I3(\Q_reg[31]_13 [28]),
.O(\Q_reg[0]_3 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[27]),
.I1(\Q_reg[31]_13 [27]),
.I2(Q[26]),
.I3(\Q_reg[31]_13 [26]),
.O(\Q_reg[0]_3 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[25]),
.I1(\Q_reg[31]_13 [25]),
.I2(Q[24]),
.I3(\Q_reg[31]_13 [24]),
.O(\Q_reg[0]_3 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[7]),
.I1(\Q_reg[31]_13 [7]),
.I2(Q[6]),
.I3(\Q_reg[31]_13 [6]),
.O(\Q_reg[0]_0 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[5]),
.I1(\Q_reg[31]_13 [5]),
.I2(Q[4]),
.I3(\Q_reg[31]_13 [4]),
.O(\Q_reg[0]_0 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[3]),
.I1(\Q_reg[31]_13 [3]),
.I2(Q[2]),
.I3(\Q_reg[31]_13 [2]),
.O(\Q_reg[0]_0 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[1]),
.I1(\Q_reg[31]_13 [1]),
.I2(Q[0]),
.I3(\Q_reg[31]_13 [0]),
.O(\Q_reg[0]_0 [0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(\Q_reg[7]_0 ,
\FSM_sequential_state_reg_reg[3] ,
D,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output [30:0]\Q_reg[7]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [30:0]D;
input CLK;
input [1:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [30:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [1:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [30:0]\Q_reg[7]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[0]),
.Q(\Q_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[10]),
.Q(\Q_reg[7]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[11]),
.Q(\Q_reg[7]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[12]),
.Q(\Q_reg[7]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[13]),
.Q(\Q_reg[7]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[14]),
.Q(\Q_reg[7]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[15]),
.Q(\Q_reg[7]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[16]),
.Q(\Q_reg[7]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[17]),
.Q(\Q_reg[7]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[18]),
.Q(\Q_reg[7]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[19]),
.Q(\Q_reg[7]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[1]),
.Q(\Q_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[20]),
.Q(\Q_reg[7]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[21]),
.Q(\Q_reg[7]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[22]),
.Q(\Q_reg[7]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[23]),
.Q(\Q_reg[7]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[24]),
.Q(\Q_reg[7]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[25]),
.Q(\Q_reg[7]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[26]),
.Q(\Q_reg[7]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[27]),
.Q(\Q_reg[7]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[28]),
.Q(\Q_reg[7]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[29]),
.Q(\Q_reg[7]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[2]),
.Q(\Q_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[30]),
.Q(\Q_reg[7]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[3]),
.Q(\Q_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[4]),
.Q(\Q_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[5]),
.Q(\Q_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[6]),
.Q(\Q_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [0]),
.D(D[7]),
.Q(\Q_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[8]),
.Q(\Q_reg[7]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 [1]),
.D(D[9]),
.Q(\Q_reg[7]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(\Q_reg[7]_0 ,
\FSM_sequential_state_reg_reg[3] ,
D,
CLK,
\FSM_sequential_state_reg_reg[3]_0 );
output [30:0]\Q_reg[7]_0 ;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
input [30:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire CLK;
wire [30:0]D;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [0:0]\FSM_sequential_state_reg_reg[3]_0 ;
wire [30:0]\Q_reg[7]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[0]),
.Q(\Q_reg[7]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[10]),
.Q(\Q_reg[7]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[11]),
.Q(\Q_reg[7]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[12]),
.Q(\Q_reg[7]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[13]),
.Q(\Q_reg[7]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[14]),
.Q(\Q_reg[7]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[15]),
.Q(\Q_reg[7]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[16]),
.Q(\Q_reg[7]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[17]),
.Q(\Q_reg[7]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[18]),
.Q(\Q_reg[7]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[19]),
.Q(\Q_reg[7]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[1]),
.Q(\Q_reg[7]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[20]),
.Q(\Q_reg[7]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[21]),
.Q(\Q_reg[7]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[22]),
.Q(\Q_reg[7]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[23]),
.Q(\Q_reg[7]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[24]),
.Q(\Q_reg[7]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[25]),
.Q(\Q_reg[7]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[26]),
.Q(\Q_reg[7]_0 [26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[27]),
.Q(\Q_reg[7]_0 [27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[28]),
.Q(\Q_reg[7]_0 [28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[29]),
.Q(\Q_reg[7]_0 [29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[2]),
.Q(\Q_reg[7]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[30]),
.Q(\Q_reg[7]_0 [30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[3]),
.Q(\Q_reg[7]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[4]),
.Q(\Q_reg[7]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[5]),
.Q(\Q_reg[7]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[6]),
.Q(\Q_reg[7]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[7]),
.Q(\Q_reg[7]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[8]),
.Q(\Q_reg[7]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[3] ),
.CLR(\FSM_sequential_state_reg_reg[3]_0 ),
.D(D[9]),
.Q(\Q_reg[7]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(D,
Q,
Data_A,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
\Q_reg[23] ,
E,
\Q_reg[1]_0 ,
CLK,
AR);
output [7:0]D;
output [7:0]Q;
output [0:0]Data_A;
input \Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
input \Q_reg[0]_2 ;
input [0:0]\Q_reg[23] ;
input [0:0]E;
input [7:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]D;
wire [0:0]Data_A;
wire [0:0]E;
wire [7:0]Q;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire \Q_reg[0]_2 ;
wire [7:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[23] ;
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__1
(.I0(Q[0]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__1
(.I0(Q[1]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__1
(.I0(Q[2]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1
(.I0(Q[3]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1
(.I0(Q[4]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1
(.I0(Q[5]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1
(.I0(Q[6]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[6]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1__0
(.I0(Q[7]),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[0]_1 ),
.O(D[7]));
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_2__1
(.I0(Q[0]),
.I1(\Q_reg[0]_2 ),
.I2(\Q_reg[23] ),
.O(Data_A));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(D,
\Q_reg[16]_0 ,
Q,
\Q_reg[25]_0 ,
\Q_reg[17]_0 ,
\Q_reg[24]_0 ,
\Q_reg[18]_0 ,
\Q_reg[23]_0 ,
\Q_reg[19]_0 ,
\Q_reg[22]_0 ,
\Q_reg[20]_0 ,
\Q_reg[21]_0 ,
FSM_barrel_shifter_L_R,
\Q_reg[16]_1 ,
FSM_barrel_shifter_B_S,
\Q_reg[4]_0 ,
\Q_reg[3]_0 ,
\Q_reg[17]_1 ,
\Q_reg[2]_0 ,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [9:0]D;
output \Q_reg[16]_0 ;
output [15:0]Q;
output \Q_reg[25]_0 ;
output \Q_reg[17]_0 ;
output \Q_reg[24]_0 ;
output \Q_reg[18]_0 ;
output \Q_reg[23]_0 ;
output \Q_reg[19]_0 ;
output \Q_reg[22]_0 ;
output \Q_reg[20]_0 ;
output \Q_reg[21]_0 ;
input FSM_barrel_shifter_L_R;
input \Q_reg[16]_1 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[4]_0 ;
input \Q_reg[3]_0 ;
input \Q_reg[17]_1 ;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [9:0]D;
wire [9:0]\Data_array[4]_0 ;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [15:0]Q;
wire \Q_reg[16]_0 ;
wire \Q_reg[16]_1 ;
wire \Q_reg[17]_0 ;
wire \Q_reg[17]_1 ;
wire \Q_reg[18]_0 ;
wire \Q_reg[19]_0 ;
wire \Q_reg[20]_0 ;
wire \Q_reg[21]_0 ;
wire \Q_reg[22]_0 ;
wire \Q_reg[23]_0 ;
wire \Q_reg[24]_0 ;
wire \Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire \Q_reg[3]_0 ;
wire \Q_reg[4]_0 ;
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\Q[16]_i_1
(.I0(\Q_reg[16]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[16]_1 ),
.O(D[0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_2
(.I0(Q[15]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [9]),
.I4(\Q_reg[3]_0 ),
.I5(Q[7]),
.O(\Q_reg[16]_0 ));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hB8))
\Q[17]_i_1
(.I0(\Q_reg[17]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[17]_1 ),
.O(D[1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_2
(.I0(Q[14]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [8]),
.I4(\Q_reg[3]_0 ),
.I5(Q[6]),
.O(\Q_reg[17]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[18]_i_1
(.I0(\Q_reg[18]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[8]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_2
(.I0(Q[13]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [7]),
.I4(\Q_reg[3]_0 ),
.I5(Q[5]),
.O(\Q_reg[18]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[19]_i_1
(.I0(\Q_reg[19]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[9]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_2
(.I0(Q[12]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [6]),
.I4(\Q_reg[3]_0 ),
.I5(Q[4]),
.O(\Q_reg[19]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[20]_i_1__0
(.I0(\Q_reg[20]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[10]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_2
(.I0(Q[11]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [5]),
.I4(\Q_reg[3]_0 ),
.I5(Q[3]),
.O(\Q_reg[20]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[21]_i_1__0
(.I0(\Q_reg[21]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[11]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_2
(.I0(Q[10]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [4]),
.I4(\Q_reg[3]_0 ),
.I5(Q[2]),
.O(\Q_reg[21]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[22]_i_1
(.I0(\Q_reg[22]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[12]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_2
(.I0(Q[9]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [3]),
.I4(\Q_reg[3]_0 ),
.I5(Q[1]),
.O(\Q_reg[22]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[23]_i_1
(.I0(\Q_reg[23]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[13]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_2
(.I0(Q[8]),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [2]),
.I4(\Q_reg[3]_0 ),
.I5(Q[0]),
.O(\Q_reg[23]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[24]_i_1__0
(.I0(\Q_reg[24]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[14]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[8]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[24]_i_2__0
(.I0(Q[7]),
.I1(Q[15]),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [1]),
.I4(\Q_reg[3]_0 ),
.I5(\Data_array[4]_0 [9]),
.O(\Q_reg[24]_0 ));
LUT6 #(
.INIT(64'hBBB8BBBB8B888888))
\Q[25]_i_2
(.I0(\Q_reg[25]_0 ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg[4]_0 ),
.I3(Q[15]),
.I4(\Q_reg[3]_0 ),
.I5(FSM_barrel_shifter_B_S),
.O(D[9]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(Q[6]),
.I1(Q[14]),
.I2(\Q_reg[4]_0 ),
.I3(\Data_array[4]_0 [0]),
.I4(\Q_reg[3]_0 ),
.I5(\Data_array[4]_0 [8]),
.O(\Q_reg[25]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array[4]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [10]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [11]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [12]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [13]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [14]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [15]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [16]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [17]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [18]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [19]),
.Q(Q[9]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array[4]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [20]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [21]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [22]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [23]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [24]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [25]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array[4]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array[4]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array[4]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array[4]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array[4]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array[4]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array[4]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(1'b1),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array[4]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(round_flag,
\Q_reg[0]_0 ,
r_mode_IBUF,
sign_final_result,
E,
D,
CLK,
AR);
output round_flag;
output [25:0]\Q_reg[0]_0 ;
input [1:0]r_mode_IBUF;
input sign_final_result;
input [0:0]E;
input [25:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [25:0]D;
wire [0:0]E;
wire [25:0]\Q_reg[0]_0 ;
wire [1:0]r_mode_IBUF;
wire round_flag;
wire sign_final_result;
LUT5 #(
.INIT(32'h0E0000E0))
\FSM_sequential_state_reg[2]_i_2
(.I0(\Q_reg[0]_0 [1]),
.I1(\Q_reg[0]_0 [0]),
.I2(r_mode_IBUF[1]),
.I3(sign_final_result),
.I4(r_mode_IBUF[0]),
.O(round_flag));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[0]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg[0]_0 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg[0]_0 [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg[0]_0 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg[0]_0 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg[0]_0 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg[0]_0 [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg[0]_0 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg[0]_0 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg[0]_0 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg[0]_0 [19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg[0]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg[0]_0 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg[0]_0 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg[0]_0 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[0]_0 [23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[0]_0 [24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg[0]_0 [25]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[0]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[0]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[0]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[0]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[0]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg[0]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg[0]_0 [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg[0]_0 [9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(D,
\Q_reg[18]_0 ,
\Q_reg[16]_0 ,
\Q_reg[17]_0 ,
\Q_reg[15]_0 ,
Q,
\Q_reg[4]_0 ,
FSM_barrel_shifter_B_S,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
\Q_reg[0]_0 ,
FSM_selector_C,
FSM_barrel_shifter_L_R,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
FSM_selector_B,
\Q_reg[0]_3 ,
\Q_reg[22]_0 ,
E,
\Q_reg[31] ,
CLK,
AR);
output [20:0]D;
output \Q_reg[18]_0 ;
output \Q_reg[16]_0 ;
output \Q_reg[17]_0 ;
output \Q_reg[15]_0 ;
output [1:0]Q;
output [4:0]\Q_reg[4]_0 ;
input FSM_barrel_shifter_B_S;
input \Q_reg[2]_0 ;
input \Q_reg[1]_0 ;
input \Q_reg[0]_0 ;
input FSM_selector_C;
input FSM_barrel_shifter_L_R;
input \Q_reg[0]_1 ;
input [0:0]\Q_reg[0]_2 ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_3 ;
input [22:0]\Q_reg[22]_0 ;
input [0:0]E;
input [25:0]\Q_reg[31] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [20:0]D;
wire [0:0]E;
wire FSM_barrel_shifter_B_S;
wire FSM_barrel_shifter_L_R;
wire [1:0]FSM_selector_B;
wire FSM_selector_C;
wire [1:0]Q;
wire \Q[0]_i_2__0_n_0 ;
wire \Q[0]_i_2_n_0 ;
wire \Q[0]_i_3__0_n_0 ;
wire \Q[0]_i_4__0_n_0 ;
wire \Q[0]_i_5__0_n_0 ;
wire \Q[0]_i_6_n_0 ;
wire \Q[0]_i_7_n_0 ;
wire \Q[0]_i_8_n_0 ;
wire \Q[0]_i_9_n_0 ;
wire \Q[10]_i_2_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[11]_i_2_n_0 ;
wire \Q[11]_i_3_n_0 ;
wire \Q[11]_i_4_n_0 ;
wire \Q[12]_i_2_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[13]_i_2__0_n_0 ;
wire \Q[13]_i_3__0_n_0 ;
wire \Q[14]_i_2__0_n_0 ;
wire \Q[14]_i_3__0_n_0 ;
wire \Q[15]_i_2__0_n_0 ;
wire \Q[15]_i_3__0_n_0 ;
wire \Q[16]_i_2__0_n_0 ;
wire \Q[16]_i_3__0_n_0 ;
wire \Q[17]_i_2__0_n_0 ;
wire \Q[17]_i_3__0_n_0 ;
wire \Q[18]_i_2__0_n_0 ;
wire \Q[18]_i_3_n_0 ;
wire \Q[19]_i_2__0_n_0 ;
wire \Q[19]_i_3_n_0 ;
wire \Q[1]_i_2__0_n_0 ;
wire \Q[1]_i_2_n_0 ;
wire \Q[1]_i_3__0_n_0 ;
wire \Q[1]_i_3_n_0 ;
wire \Q[1]_i_4_n_0 ;
wire \Q[1]_i_5_n_0 ;
wire \Q[1]_i_6_n_0 ;
wire \Q[1]_i_7_n_0 ;
wire \Q[20]_i_2__0_n_0 ;
wire \Q[20]_i_3_n_0 ;
wire \Q[21]_i_3_n_0 ;
wire \Q[22]_i_3_n_0 ;
wire \Q[23]_i_3_n_0 ;
wire \Q[24]_i_3_n_0 ;
wire \Q[2]_i_2__0_n_0 ;
wire \Q[2]_i_2_n_0 ;
wire \Q[2]_i_3__0_n_0 ;
wire \Q[2]_i_3_n_0 ;
wire \Q[2]_i_4_n_0 ;
wire \Q[3]_i_2_n_0 ;
wire \Q[3]_i_3_n_0 ;
wire \Q[4]_i_2_n_0 ;
wire \Q[4]_i_3__0_n_0 ;
wire \Q[4]_i_3_n_0 ;
wire \Q[4]_i_4_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[4]_i_8_n_0 ;
wire \Q[5]_i_2_n_0 ;
wire \Q[5]_i_3_n_0 ;
wire \Q[6]_i_2_n_0 ;
wire \Q[6]_i_3_n_0 ;
wire \Q[7]_i_2__0_n_0 ;
wire \Q[7]_i_3_n_0 ;
wire \Q[8]_i_2_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[9]_i_2_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[0]_2 ;
wire [0:0]\Q_reg[0]_3 ;
wire \Q_reg[15]_0 ;
wire \Q_reg[16]_0 ;
wire \Q_reg[17]_0 ;
wire \Q_reg[18]_0 ;
wire \Q_reg[1]_0 ;
wire [22:0]\Q_reg[22]_0 ;
wire \Q_reg[2]_0 ;
wire [25:0]\Q_reg[31] ;
wire [4:0]\Q_reg[4]_0 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[0]_i_1__2
(.I0(\Q[4]_i_2_n_0 ),
.I1(\Q[6]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[0]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[2]_i_2_n_0 ),
.O(D[0]));
LUT6 #(
.INIT(64'h00000000FFFF00AE))
\Q[0]_i_1__4
(.I0(\Q[0]_i_2__0_n_0 ),
.I1(\Q[0]_i_3__0_n_0 ),
.I2(\Q[0]_i_4__0_n_0 ),
.I3(\Q[0]_i_5__0_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(Q[1]),
.O(\Q_reg[4]_0 [0]));
LUT6 #(
.INIT(64'hB8BBB8BBBB888888))
\Q[0]_i_2
(.I0(\Q[1]_i_3_n_0 ),
.I1(\Q_reg[0]_1 ),
.I2(Q[1]),
.I3(FSM_selector_C),
.I4(Q[0]),
.I5(FSM_barrel_shifter_L_R),
.O(\Q[0]_i_2_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\Q[0]_i_2__0
(.I0(\Q[0]_i_6_n_0 ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[0]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFF44F4))
\Q[0]_i_3__0
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q[0]_i_7_n_0 ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg_n_0_[8] ),
.I5(\Q_reg_n_0_[12] ),
.O(\Q[0]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT4 #(
.INIT(16'hFEFF))
\Q[0]_i_4__0
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q[0]_i_8_n_0 ),
.O(\Q[0]_i_4__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT5 #(
.INIT(32'hBABBBABA))
\Q[0]_i_5__0
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg_n_0_[19] ),
.O(\Q[0]_i_5__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h00F2))
\Q[0]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[17] ),
.O(\Q[0]_i_6_n_0 ));
LUT6 #(
.INIT(64'hCCCCCCCCEFEFEFEE))
\Q[0]_i_7
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg_n_0_[6] ),
.I2(\Q_reg_n_0_[3] ),
.I3(\Q[0]_i_9_n_0 ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[5] ),
.O(\Q[0]_i_7_n_0 ));
LUT4 #(
.INIT(16'hFF0B))
\Q[0]_i_8
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[9] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[0]_i_8_n_0 ));
LUT2 #(
.INIT(4'h2))
\Q[0]_i_9
(.I0(Q[0]),
.I1(\Q_reg_n_0_[1] ),
.O(\Q[0]_i_9_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1__0
(.I0(\Q[14]_i_2__0_n_0 ),
.I1(\Q[16]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[10]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[12]_i_2_n_0 ),
.O(D[10]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[10]_i_2
(.I0(\Q[11]_i_4_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[10]_i_3_n_0 ),
.O(\Q[10]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_3
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg[22]_0 [13]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[10] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [8]),
.O(\Q[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1__0
(.I0(\Q[15]_i_2__0_n_0 ),
.I1(\Q[17]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[11]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[13]_i_2__0_n_0 ),
.O(D[11]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[11]_i_2
(.I0(\Q[11]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[11]_i_4_n_0 ),
.O(\Q[11]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_3
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg[22]_0 [11]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[12] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [10]),
.O(\Q[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_4
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg[22]_0 [12]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[11] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [9]),
.O(\Q[11]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1__0
(.I0(\Q[16]_i_2__0_n_0 ),
.I1(\Q[18]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[12]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[14]_i_2__0_n_0 ),
.O(D[12]));
LUT6 #(
.INIT(64'hEFEADFD545408A80))
\Q[12]_i_2
(.I0(\Q_reg[0]_1 ),
.I1(\Q_reg_n_0_[13] ),
.I2(FSM_selector_C),
.I3(\Q_reg[22]_0 [11]),
.I4(FSM_barrel_shifter_L_R),
.I5(\Q[12]_i_3_n_0 ),
.O(\Q[12]_i_2_n_0 ));
LUT3 #(
.INIT(8'hB8))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[12] ),
.I1(FSM_selector_C),
.I2(\Q_reg[22]_0 [10]),
.O(\Q[12]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1__0
(.I0(\Q[17]_i_2__0_n_0 ),
.I1(\Q[19]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[13]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[15]_i_2__0_n_0 ),
.O(D[13]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[13]_i_2__0
(.I0(\Q[14]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[13]_i_3__0_n_0 ),
.O(\Q[13]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3__0
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg[22]_0 [10]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[13] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [11]),
.O(\Q[13]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1__0
(.I0(\Q[18]_i_2__0_n_0 ),
.I1(\Q[20]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[14]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[16]_i_2__0_n_0 ),
.O(D[14]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[14]_i_2__0
(.I0(\Q[15]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[14]_i_3__0_n_0 ),
.O(\Q[14]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_3__0
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg[22]_0 [9]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[14] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [12]),
.O(\Q[14]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1__0
(.I0(\Q[19]_i_2__0_n_0 ),
.I1(\Q_reg[15]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[15]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[17]_i_2__0_n_0 ),
.O(D[15]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[15]_i_2__0
(.I0(\Q[16]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[15]_i_3__0_n_0 ),
.O(\Q[15]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_3__0
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg[22]_0 [8]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[15] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [13]),
.O(\Q[15]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1__0
(.I0(\Q[20]_i_2__0_n_0 ),
.I1(\Q_reg[16]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[16]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[18]_i_2__0_n_0 ),
.O(D[16]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[16]_i_2__0
(.I0(\Q[17]_i_3__0_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[16]_i_3__0_n_0 ),
.O(\Q[16]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3__0
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg[22]_0 [7]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[16] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [14]),
.O(\Q[16]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1__0
(.I0(\Q_reg[15]_0 ),
.I1(\Q_reg[17]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[17]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[19]_i_2__0_n_0 ),
.O(D[17]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[17]_i_2__0
(.I0(\Q[18]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[17]_i_3__0_n_0 ),
.O(\Q[17]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3__0
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg[22]_0 [6]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[17] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [15]),
.O(\Q[17]_i_3__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1__0
(.I0(\Q_reg[16]_0 ),
.I1(\Q_reg[18]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[18]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[20]_i_2__0_n_0 ),
.O(D[18]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[18]_i_2__0
(.I0(\Q[19]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[18]_i_3_n_0 ),
.O(\Q[18]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_3
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg[22]_0 [5]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[18] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [16]),
.O(\Q[18]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1__0
(.I0(\Q_reg[17]_0 ),
.I1(\Q_reg[0]_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[19]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q_reg[15]_0 ),
.O(D[19]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[19]_i_2__0
(.I0(\Q[20]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[19]_i_3_n_0 ),
.O(\Q[19]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_3
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg[22]_0 [4]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[19] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [17]),
.O(\Q[19]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1__0
(.I0(\Q[5]_i_2_n_0 ),
.I1(\Q[7]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[1]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[3]_i_2_n_0 ),
.O(D[1]));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_1__1
(.I0(Q[1]),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q[1]_i_2__0_n_0 ),
.I3(\Q[1]_i_3__0_n_0 ),
.I4(\Q_reg_n_0_[22] ),
.I5(\Q_reg_n_0_[23] ),
.O(\Q_reg[4]_0 [1]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[1]_i_2
(.I0(\Q[2]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[1]_i_3_n_0 ),
.O(\Q[1]_i_2_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_2__0
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[21] ),
.O(\Q[1]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hAFC0A0C0))
\Q[1]_i_3
(.I0(\Q_reg_n_0_[24] ),
.I1(\Q_reg[22]_0 [22]),
.I2(FSM_barrel_shifter_L_R),
.I3(FSM_selector_C),
.I4(\Q_reg_n_0_[1] ),
.O(\Q[1]_i_3_n_0 ));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_3__0
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg_n_0_[18] ),
.I2(\Q[1]_i_4_n_0 ),
.I3(\Q[1]_i_5_n_0 ),
.I4(\Q_reg_n_0_[16] ),
.I5(\Q_reg_n_0_[17] ),
.O(\Q[1]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_4
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[15] ),
.O(\Q[1]_i_4_n_0 ));
LUT6 #(
.INIT(64'h1111111111110010))
\Q[1]_i_5
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q[1]_i_6_n_0 ),
.I3(\Q[1]_i_7_n_0 ),
.I4(\Q_reg_n_0_[10] ),
.I5(\Q_reg_n_0_[11] ),
.O(\Q[1]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT2 #(
.INIT(4'h1))
\Q[1]_i_6
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[1]_i_6_n_0 ));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[1]_i_7
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[7] ),
.I2(\Q_reg_n_0_[4] ),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg_n_0_[2] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[1]_i_7_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1
(.I0(\Q_reg[18]_0 ),
.I1(FSM_barrel_shifter_B_S),
.I2(\Q_reg[2]_0 ),
.I3(\Q[20]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q_reg[16]_0 ),
.O(D[20]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[20]_i_2__0
(.I0(\Q[21]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[20]_i_3_n_0 ),
.O(\Q[20]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_3
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg[22]_0 [3]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[20] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [18]),
.O(\Q[20]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[21]_i_2__0
(.I0(\Q[22]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[21]_i_3_n_0 ),
.O(\Q_reg[15]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_3
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg[22]_0 [2]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[21] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [19]),
.O(\Q[21]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[22]_i_2__0
(.I0(\Q[23]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[22]_i_3_n_0 ),
.O(\Q_reg[16]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_3
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg[22]_0 [1]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[22] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [20]),
.O(\Q[22]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[23]_i_2__0
(.I0(\Q[24]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[23]_i_3_n_0 ),
.O(\Q_reg[17]_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_3
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg[22]_0 [0]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[23] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [21]),
.O(\Q[23]_i_3_n_0 ));
LUT6 #(
.INIT(64'h88F3FFFF88F30000))
\Q[24]_i_2
(.I0(Q[0]),
.I1(FSM_selector_C),
.I2(Q[1]),
.I3(FSM_barrel_shifter_L_R),
.I4(\Q_reg[0]_1 ),
.I5(\Q[24]_i_3_n_0 ),
.O(\Q_reg[18]_0 ));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'hB833B800))
\Q[24]_i_3
(.I0(\Q_reg_n_0_[1] ),
.I1(FSM_barrel_shifter_L_R),
.I2(\Q_reg_n_0_[24] ),
.I3(FSM_selector_C),
.I4(\Q_reg[22]_0 [22]),
.O(\Q[24]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1__0
(.I0(\Q[6]_i_2_n_0 ),
.I1(\Q[8]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[2]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[4]_i_2_n_0 ),
.O(D[2]));
LUT6 #(
.INIT(64'h0001000000010001))
\Q[2]_i_1__1
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[23] ),
.I2(\Q_reg_n_0_[24] ),
.I3(Q[1]),
.I4(\Q[2]_i_2__0_n_0 ),
.I5(\Q[2]_i_3__0_n_0 ),
.O(\Q_reg[4]_0 [2]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[2]_i_2
(.I0(\Q[3]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[2]_i_3_n_0 ),
.O(\Q[2]_i_2_n_0 ));
LUT6 #(
.INIT(64'h00808888AAAAAAAA))
\Q[2]_i_2__0
(.I0(\Q[4]_i_7_n_0 ),
.I1(\Q[4]_i_4_n_0 ),
.I2(Q[0]),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[4]_i_3__0_n_0 ),
.I5(\Q[2]_i_4_n_0 ),
.O(\Q[2]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_3
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg[22]_0 [21]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[2] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [0]),
.O(\Q[2]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT4 #(
.INIT(16'h0001))
\Q[2]_i_3__0
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[2]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT4 #(
.INIT(16'h0001))
\Q[2]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[12] ),
.O(\Q[2]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1__0
(.I0(\Q[7]_i_2__0_n_0 ),
.I1(\Q[9]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[3]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[5]_i_2_n_0 ),
.O(D[3]));
LUT5 #(
.INIT(32'h8000AAAA))
\Q[3]_i_1__1
(.I0(\Q[4]_i_6_n_0 ),
.I1(\Q[4]_i_4_n_0 ),
.I2(\Q[4]_i_3__0_n_0 ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q[4]_i_5_n_0 ),
.O(\Q_reg[4]_0 [3]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[3]_i_2
(.I0(\Q[4]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[3]_i_3_n_0 ),
.O(\Q[3]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_3
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg[22]_0 [20]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[3] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [1]),
.O(\Q[3]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1__1
(.I0(\Q[8]_i_2_n_0 ),
.I1(\Q[10]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[4]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[6]_i_2_n_0 ),
.O(D[4]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[4]_i_2
(.I0(\Q[5]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[4]_i_3_n_0 ),
.O(\Q[4]_i_2_n_0 ));
LUT6 #(
.INIT(64'hFDFF000000000000))
\Q[4]_i_2__0
(.I0(\Q[4]_i_3__0_n_0 ),
.I1(\Q_reg_n_0_[1] ),
.I2(Q[0]),
.I3(\Q[4]_i_4_n_0 ),
.I4(\Q[4]_i_5_n_0 ),
.I5(\Q[4]_i_6_n_0 ),
.O(\Q_reg[4]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_3
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg[22]_0 [19]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[4] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [2]),
.O(\Q[4]_i_3_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_3__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[4] ),
.O(\Q[4]_i_3__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_4
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[7] ),
.O(\Q[4]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT5 #(
.INIT(32'h00010000))
\Q[4]_i_5
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[4]_i_7_n_0 ),
.O(\Q[4]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT5 #(
.INIT(32'h00010000))
\Q[4]_i_6
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg_n_0_[19] ),
.I2(\Q_reg_n_0_[20] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q[4]_i_8_n_0 ),
.O(\Q[4]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_7
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg_n_0_[16] ),
.I2(\Q_reg_n_0_[15] ),
.I3(\Q_reg_n_0_[14] ),
.O(\Q[4]_i_7_n_0 ));
LUT4 #(
.INIT(16'h0001))
\Q[4]_i_8
(.I0(Q[1]),
.I1(\Q_reg_n_0_[24] ),
.I2(\Q_reg_n_0_[23] ),
.I3(\Q_reg_n_0_[22] ),
.O(\Q[4]_i_8_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1__0
(.I0(\Q[9]_i_2_n_0 ),
.I1(\Q[11]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[5]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[7]_i_2__0_n_0 ),
.O(D[5]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[5]_i_2
(.I0(\Q[6]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[5]_i_3_n_0 ),
.O(\Q[5]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_3
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg[22]_0 [18]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[5] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [3]),
.O(\Q[5]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1__0
(.I0(\Q[10]_i_2_n_0 ),
.I1(\Q[12]_i_2_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[6]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[8]_i_2_n_0 ),
.O(D[6]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[6]_i_2
(.I0(\Q[7]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[6]_i_3_n_0 ),
.O(\Q[6]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_3
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg[22]_0 [17]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[6] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [4]),
.O(\Q[6]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1__1
(.I0(\Q[11]_i_2_n_0 ),
.I1(\Q[13]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[7]_i_2__0_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[9]_i_2_n_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[7]_i_2__0
(.I0(\Q[8]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[7]_i_3_n_0 ),
.O(\Q[7]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_3
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg[22]_0 [16]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[7] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [5]),
.O(\Q[7]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1__0
(.I0(\Q[12]_i_2_n_0 ),
.I1(\Q[14]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[8]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[10]_i_2_n_0 ),
.O(D[8]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[8]_i_2
(.I0(\Q[9]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[8]_i_3_n_0 ),
.O(\Q[8]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg[22]_0 [15]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[8] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [6]),
.O(\Q[8]_i_3_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1__0
(.I0(\Q[13]_i_2__0_n_0 ),
.I1(\Q[15]_i_2__0_n_0 ),
.I2(\Q_reg[2]_0 ),
.I3(\Q[9]_i_2_n_0 ),
.I4(\Q_reg[1]_0 ),
.I5(\Q[11]_i_2_n_0 ),
.O(D[9]));
LUT6 #(
.INIT(64'hFBFBAAAF0808AAA0))
\Q[9]_i_2
(.I0(\Q[10]_i_3_n_0 ),
.I1(\Q_reg[0]_2 ),
.I2(FSM_selector_B[1]),
.I3(\Q_reg[0]_3 ),
.I4(FSM_selector_B[0]),
.I5(\Q[9]_i_3_n_0 ),
.O(\Q[9]_i_2_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_3
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg[22]_0 [14]),
.I2(FSM_barrel_shifter_L_R),
.I3(\Q_reg_n_0_[9] ),
.I4(FSM_selector_C),
.I5(\Q_reg[22]_0 [7]),
.O(\Q[9]_i_3_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [25]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[31] [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(Q,
E,
D,
CLK,
\FSM_sequential_state_reg_reg[3] );
output [4:0]Q;
input [0:0]E;
input [4:0]D;
input CLK;
input [0:0]\FSM_sequential_state_reg_reg[3] ;
wire CLK;
wire [4:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[3] ;
wire [4:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(\FSM_sequential_state_reg_reg[3] ),
.D(D[4]),
.Q(Q[4]));
endmodule
module Tenth_Phase
(Q,
E,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
RegisterAdd__parameterized10 Final_Result_IEEE
(.AR(AR),
.CLK(CLK),
.D(D),
.E(E),
.Q(Q));
endmodule
module add_sub_carry_out
(S,
\Q_reg[3] ,
\Q_reg[30] ,
\Q_reg[1] ,
FSM_exp_operation_A_S,
\Q_reg[30]_0 ,
\Q_reg[0] ,
Q,
DI,
\Q_reg[26] ,
FSM_selector_B,
\Q_reg[0]_0 );
output [3:0]S;
output [3:0]\Q_reg[3] ;
input [3:0]\Q_reg[30] ;
input \Q_reg[1] ;
input FSM_exp_operation_A_S;
input [6:0]\Q_reg[30]_0 ;
input \Q_reg[0] ;
input [6:0]Q;
input [0:0]DI;
input [2:0]\Q_reg[26] ;
input [1:0]FSM_selector_B;
input [0:0]\Q_reg[0]_0 ;
wire [0:0]DI;
wire FSM_exp_operation_A_S;
wire [1:0]FSM_selector_B;
wire [6:0]Q;
wire \Q_reg[0] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[1] ;
wire [2:0]\Q_reg[26] ;
wire [3:0]\Q_reg[30] ;
wire [6:0]\Q_reg[30]_0 ;
wire [3:0]\Q_reg[3] ;
wire [3:0]S;
LUT4 #(
.INIT(16'h3E0E))
\Q[3]_i_10
(.I0(\Q_reg[30] [0]),
.I1(FSM_selector_B[1]),
.I2(FSM_selector_B[0]),
.I3(\Q_reg[0]_0 ),
.O(\Q_reg[3] [0]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_7
(.I0(\Q_reg[26] [2]),
.I1(\Q_reg[30]_0 [2]),
.I2(\Q_reg[0] ),
.I3(Q[2]),
.O(\Q_reg[3] [3]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_8
(.I0(\Q_reg[26] [1]),
.I1(\Q_reg[30]_0 [1]),
.I2(\Q_reg[0] ),
.I3(Q[1]),
.O(\Q_reg[3] [2]));
LUT4 #(
.INIT(16'h56A6))
\Q[3]_i_9
(.I0(\Q_reg[26] [0]),
.I1(\Q_reg[30]_0 [0]),
.I2(\Q_reg[0] ),
.I3(Q[0]),
.O(\Q_reg[3] [1]));
LUT4 #(
.INIT(16'h56A6))
\Q[7]_i_10
(.I0(DI),
.I1(\Q_reg[30]_0 [3]),
.I2(\Q_reg[0] ),
.I3(Q[3]),
.O(S[0]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_7
(.I0(\Q_reg[30] [3]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [6]),
.I4(\Q_reg[0] ),
.I5(Q[6]),
.O(S[3]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_8
(.I0(\Q_reg[30] [2]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [5]),
.I4(\Q_reg[0] ),
.I5(Q[5]),
.O(S[2]));
LUT6 #(
.INIT(64'h2D2D2DD2D2D22DD2))
\Q[7]_i_9
(.I0(\Q_reg[30] [1]),
.I1(\Q_reg[1] ),
.I2(FSM_exp_operation_A_S),
.I3(\Q_reg[30]_0 [4]),
.I4(\Q_reg[0] ),
.I5(Q[4]),
.O(S[1]));
endmodule
(* ORIG_REF_NAME = "add_sub_carry_out" *)
module add_sub_carry_out__parameterized0
(S,
\Q_reg[7] ,
\Q_reg[11] ,
\Q_reg[15] ,
\Q_reg[19] ,
\Q_reg[23] ,
\Q_reg[0] ,
\Q_reg[31] ,
intAS,
\Q_reg[31]_0 ,
\Q_reg[25] ,
FSM_selector_D,
\Q_reg[22] );
output [3:0]S;
output [3:0]\Q_reg[7] ;
output [3:0]\Q_reg[11] ;
output [3:0]\Q_reg[15] ;
output [3:0]\Q_reg[19] ;
output [3:0]\Q_reg[23] ;
output [1:0]\Q_reg[0] ;
input [0:0]\Q_reg[31] ;
input intAS;
input [0:0]\Q_reg[31]_0 ;
input [25:0]\Q_reg[25] ;
input FSM_selector_D;
input [22:0]\Q_reg[22] ;
wire FSM_selector_D;
wire [1:0]\Q_reg[0] ;
wire [3:0]\Q_reg[11] ;
wire [3:0]\Q_reg[15] ;
wire [3:0]\Q_reg[19] ;
wire [22:0]\Q_reg[22] ;
wire [3:0]\Q_reg[23] ;
wire [25:0]\Q_reg[25] ;
wire [0:0]\Q_reg[31] ;
wire [0:0]\Q_reg[31]_0 ;
wire [3:0]\Q_reg[7] ;
wire [3:0]S;
wire intAS;
LUT5 #(
.INIT(32'hFF960069))
\Q[0]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(FSM_selector_D),
.I4(\Q_reg[25] [25]),
.O(\Q_reg[0] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[0]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [22]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [24]),
.O(\Q_reg[0] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [9]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [11]),
.O(\Q_reg[11] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [8]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [10]),
.O(\Q_reg[11] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [7]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [9]),
.O(\Q_reg[11] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[11]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [6]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [8]),
.O(\Q_reg[11] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [13]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [15]),
.O(\Q_reg[15] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [12]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [14]),
.O(\Q_reg[15] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [11]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [13]),
.O(\Q_reg[15] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[15]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [10]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [12]),
.O(\Q_reg[15] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [17]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [19]),
.O(\Q_reg[19] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [16]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [18]),
.O(\Q_reg[19] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [15]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [17]),
.O(\Q_reg[19] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[19]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [14]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [16]),
.O(\Q_reg[19] [0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [21]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [23]),
.O(\Q_reg[23] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [20]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [22]),
.O(\Q_reg[23] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [19]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [21]),
.O(\Q_reg[23] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[23]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [18]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [20]),
.O(\Q_reg[23] [0]));
LUT2 #(
.INIT(4'h2))
\Q[3]_i_10
(.I0(\Q_reg[25] [0]),
.I1(FSM_selector_D),
.O(S[0]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[3]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [1]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [3]),
.O(S[3]));
LUT6 #(
.INIT(64'h00009669FFFF6996))
\Q[3]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [0]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [2]),
.O(S[2]));
LUT5 #(
.INIT(32'hFF006996))
\Q[3]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[25] [1]),
.I4(FSM_selector_D),
.O(S[1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_6
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [5]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [7]),
.O(\Q_reg[7] [3]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_7
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [4]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [6]),
.O(\Q_reg[7] [2]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_8
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [3]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [5]),
.O(\Q_reg[7] [1]));
LUT6 #(
.INIT(64'hFFFF966900006996))
\Q[7]_i_9
(.I0(\Q_reg[31] ),
.I1(intAS),
.I2(\Q_reg[31]_0 ),
.I3(\Q_reg[22] [2]),
.I4(FSM_selector_D),
.I5(\Q_reg[25] [4]),
.O(\Q_reg[7] [0]));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Write Response Channel for ATC
//
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// b_atc
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
module processing_system7_v5_5_b_atc #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6, spartan6 or later.
parameter integer C_AXI_ID_WIDTH = 4,
// Width of all ID signals on SI and MI side of checker.
// Range: >= 1.
parameter integer C_AXI_BUSER_WIDTH = 1,
// Width of AWUSER signals.
// Range: >= 1.
parameter integer C_FIFO_DEPTH_LOG = 4
)
(
// Global Signals
input wire ARESET,
input wire ACLK,
// Command Interface
input wire cmd_b_push,
input wire cmd_b_error,
input wire [C_AXI_ID_WIDTH-1:0] cmd_b_id,
output wire cmd_b_ready,
output wire [C_FIFO_DEPTH_LOG-1:0] cmd_b_addr,
output reg cmd_b_full,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID,
output reg [2-1:0] S_AXI_BRESP,
output wire [C_AXI_BUSER_WIDTH-1:0] S_AXI_BUSER,
output wire S_AXI_BVALID,
input wire S_AXI_BREADY,
// Master Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] M_AXI_BID,
input wire [2-1:0] M_AXI_BRESP,
input wire [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER,
input wire M_AXI_BVALID,
output wire M_AXI_BREADY,
// Trigger detection
output reg ERROR_TRIGGER,
output reg [C_AXI_ID_WIDTH-1:0] ERROR_TRANSACTION_ID
);
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Constants for packing levels.
localparam [2-1:0] C_RESP_OKAY = 2'b00;
localparam [2-1:0] C_RESP_EXOKAY = 2'b01;
localparam [2-1:0] C_RESP_SLVERROR = 2'b10;
localparam [2-1:0] C_RESP_DECERR = 2'b11;
// Command FIFO settings
localparam C_FIFO_WIDTH = C_AXI_ID_WIDTH + 1;
localparam C_FIFO_DEPTH = 2 ** C_FIFO_DEPTH_LOG;
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
integer index;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
// Command Queue.
reg [C_FIFO_DEPTH_LOG-1:0] addr_ptr;
reg [C_FIFO_WIDTH-1:0] data_srl[C_FIFO_DEPTH-1:0];
reg cmd_b_valid;
wire cmd_b_ready_i;
wire inject_error;
wire [C_AXI_ID_WIDTH-1:0] current_id;
// Search command.
wire found_match;
wire use_match;
wire matching_id;
// Manage valid command.
wire write_valid_cmd;
reg [C_FIFO_DEPTH-2:0] valid_cmd;
reg [C_FIFO_DEPTH-2:0] updated_valid_cmd;
reg [C_FIFO_DEPTH-2:0] next_valid_cmd;
reg [C_FIFO_DEPTH_LOG-1:0] search_addr_ptr;
reg [C_FIFO_DEPTH_LOG-1:0] collapsed_addr_ptr;
// Pipelined data
reg [C_AXI_ID_WIDTH-1:0] M_AXI_BID_I;
reg [2-1:0] M_AXI_BRESP_I;
reg [C_AXI_BUSER_WIDTH-1:0] M_AXI_BUSER_I;
reg M_AXI_BVALID_I;
wire M_AXI_BREADY_I;
/////////////////////////////////////////////////////////////////////////////
// Command Queue:
//
// Keep track of depth of Queue to generate full flag.
//
// Also generate valid to mark pressence of commands in Queue.
//
// Maintain Queue and extract data from currently searched entry.
//
/////////////////////////////////////////////////////////////////////////////
// SRL FIFO Pointer.
always @ (posedge ACLK) begin
if (ARESET) begin
addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
// Pushing data increase length/addr.
addr_ptr <= addr_ptr + 1;
end else if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
addr_ptr <= collapsed_addr_ptr;
end
end
end
// FIFO Flags.
always @ (posedge ACLK) begin
if (ARESET) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= 1'b0;
end else begin
if ( cmd_b_push & ~cmd_b_ready_i ) begin
cmd_b_full <= ( addr_ptr == C_FIFO_DEPTH-3 );
cmd_b_valid <= 1'b1;
end else if ( ~cmd_b_push & cmd_b_ready_i ) begin
cmd_b_full <= 1'b0;
cmd_b_valid <= ( collapsed_addr_ptr != C_FIFO_DEPTH-1 );
end
end
end
// Infere SRL for storage.
always @ (posedge ACLK) begin
if ( cmd_b_push ) begin
for (index = 0; index < C_FIFO_DEPTH-1 ; index = index + 1) begin
data_srl[index+1] <= data_srl[index];
end
data_srl[0] <= {cmd_b_error, cmd_b_id};
end
end
// Get current transaction info.
assign {inject_error, current_id} = data_srl[search_addr_ptr];
// Assign outputs.
assign cmd_b_addr = collapsed_addr_ptr;
/////////////////////////////////////////////////////////////////////////////
// Search Command Queue:
//
// Search for matching valid command in queue.
//
// A command is found when an valid entry with correct ID is found. The queue
// is search from the oldest entry, i.e. from a high value.
// When new commands are pushed the search address has to be updated to always
// start the search from the oldest available.
//
/////////////////////////////////////////////////////////////////////////////
// Handle search addr.
always @ (posedge ACLK) begin
if (ARESET) begin
search_addr_ptr <= {C_FIFO_DEPTH_LOG{1'b1}};
end else begin
if ( cmd_b_ready_i ) begin
// Collapse addr when data is popped.
search_addr_ptr <= collapsed_addr_ptr;
end else if ( M_AXI_BVALID_I & cmd_b_valid & ~found_match & ~cmd_b_push ) begin
// Skip non valid command.
search_addr_ptr <= search_addr_ptr - 1;
end else if ( cmd_b_push ) begin
search_addr_ptr <= search_addr_ptr + 1;
end
end
end
// Check if searched command is valid and match ID (for existing response on MI side).
assign matching_id = ( M_AXI_BID_I == current_id );
assign found_match = valid_cmd[search_addr_ptr] & matching_id & M_AXI_BVALID_I;
assign use_match = found_match & S_AXI_BREADY;
/////////////////////////////////////////////////////////////////////////////
// Track Used Commands:
//
// Actions that affect Valid Command:
// * When a new command is pushed
// => Shift valid vector one step
// * When a command is used
// => Clear corresponding valid bit
//
/////////////////////////////////////////////////////////////////////////////
// Valid command status is updated when a command is used or a new one is pushed.
assign write_valid_cmd = cmd_b_push | cmd_b_ready_i;
// Update the used command valid bit.
always @ *
begin
updated_valid_cmd = valid_cmd;
updated_valid_cmd[search_addr_ptr] = ~use_match;
end
// Shift valid vector when command is pushed.
always @ *
begin
if ( cmd_b_push ) begin
next_valid_cmd = {updated_valid_cmd[C_FIFO_DEPTH-3:0], 1'b1};
end else begin
next_valid_cmd = updated_valid_cmd;
end
end
// Valid signals for next cycle.
always @ (posedge ACLK) begin
if (ARESET) begin
valid_cmd <= {C_FIFO_WIDTH{1'b0}};
end else if ( write_valid_cmd ) begin
valid_cmd <= next_valid_cmd;
end
end
// Detect oldest available command in Queue.
always @ *
begin
// Default to empty.
collapsed_addr_ptr = {C_FIFO_DEPTH_LOG{1'b1}};
for (index = 0; index < C_FIFO_DEPTH-2 ; index = index + 1) begin
if ( next_valid_cmd[index] ) begin
collapsed_addr_ptr = index;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Pipe incoming data:
//
// The B channel is piped to improve timing and avoid impact in search
// mechanism due to late arriving signals.
//
/////////////////////////////////////////////////////////////////////////////
// Clock data.
always @ (posedge ACLK) begin
if (ARESET) begin
M_AXI_BID_I <= {C_AXI_ID_WIDTH{1'b0}};
M_AXI_BRESP_I <= 2'b00;
M_AXI_BUSER_I <= {C_AXI_BUSER_WIDTH{1'b0}};
M_AXI_BVALID_I <= 1'b0;
end else begin
if ( M_AXI_BREADY_I | ~M_AXI_BVALID_I ) begin
M_AXI_BVALID_I <= 1'b0;
end
if (M_AXI_BVALID & ( M_AXI_BREADY_I | ~M_AXI_BVALID_I) ) begin
M_AXI_BID_I <= M_AXI_BID;
M_AXI_BRESP_I <= M_AXI_BRESP;
M_AXI_BUSER_I <= M_AXI_BUSER;
M_AXI_BVALID_I <= 1'b1;
end
end
end
// Generate ready to get new transaction.
assign M_AXI_BREADY = M_AXI_BREADY_I | ~M_AXI_BVALID_I;
/////////////////////////////////////////////////////////////////////////////
// Inject Error:
//
// BRESP is modified according to command information.
//
/////////////////////////////////////////////////////////////////////////////
// Inject error in response.
always @ *
begin
if ( inject_error ) begin
S_AXI_BRESP = C_RESP_SLVERROR;
end else begin
S_AXI_BRESP = M_AXI_BRESP_I;
end
end
// Handle interrupt generation.
always @ (posedge ACLK) begin
if (ARESET) begin
ERROR_TRIGGER <= 1'b0;
ERROR_TRANSACTION_ID <= {C_AXI_ID_WIDTH{1'b0}};
end else begin
if ( inject_error & cmd_b_ready_i ) begin
ERROR_TRIGGER <= 1'b1;
ERROR_TRANSACTION_ID <= M_AXI_BID_I;
end else begin
ERROR_TRIGGER <= 1'b0;
end
end
end
/////////////////////////////////////////////////////////////////////////////
// Transaction Throttling:
//
// Response is passed forward when a matching entry has been found in queue.
// Both ready and valid are set when the command is completed.
//
/////////////////////////////////////////////////////////////////////////////
// Propagate masked valid.
assign S_AXI_BVALID = M_AXI_BVALID_I & cmd_b_valid & found_match;
// Return ready with push back.
assign M_AXI_BREADY_I = cmd_b_valid & use_match;
// Command has been handled.
assign cmd_b_ready_i = M_AXI_BVALID_I & cmd_b_valid & use_match;
assign cmd_b_ready = cmd_b_ready_i;
/////////////////////////////////////////////////////////////////////////////
// Write Response Propagation:
//
// All information is simply forwarded on from MI- to SI-Side untouched.
//
/////////////////////////////////////////////////////////////////////////////
// 1:1 mapping.
assign S_AXI_BID = M_AXI_BID_I;
assign S_AXI_BUSER = M_AXI_BUSER_I;
endmodule
|
/*
* Copyright (c) 2001 Stephan Boettcher <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
// $Id: dotinid.v,v 1.1 2001/06/26 00:32:18 sib4 Exp $
// $Log: dotinid.v,v $
// Revision 1.1 2001/06/26 00:32:18 sib4
// Two new tests for identifier parsing/elaboration
//
//
// IVL parser/elaboration test for escaped names with .
module a;
wire \a.b ;
m \c.d (\a.b );
initial
begin
\c.d . \y.z <= 1'b1;
#1;
if (\a.b === 1'b1)
$display("PASSED");
else
$display("FAILED");
end
endmodule
module m(x);
output x;
reg \y.z ;
assign x = \y.z ;
endmodule
|
//-----------------------------------------------------------------------------
// Copyright 2017 Damien Pretet ThotIP
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
//-----------------------------------------------------------------------------
`timescale 1 ns / 1 ps
`default_nettype none
module wptr_full
#(
parameter ADDRSIZE = 4
)(
input wire wclk,
input wire wrst_n,
input wire winc,
input wire [ADDRSIZE :0] wq2_rptr,
output reg wfull,
output reg awfull,
output wire [ADDRSIZE-1:0] waddr,
output reg [ADDRSIZE :0] wptr
);
reg [ADDRSIZE:0] wbin;
wire [ADDRSIZE:0] wgraynext, wbinnext, wgraynextp1;
wire awfull_val, wfull_val;
// GRAYSTYLE2 pointer
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n)
{wbin, wptr} <= 0;
else
{wbin, wptr} <= {wbinnext, wgraynext};
end
// Memory write-address pointer (okay to use binary to address memory)
assign waddr = wbin[ADDRSIZE-1:0];
assign wbinnext = wbin + (winc & ~wfull);
assign wgraynext = (wbinnext >> 1) ^ wbinnext;
assign wgraynextp1 = ((wbinnext + 1'b1) >> 1) ^ (wbinnext + 1'b1);
//------------------------------------------------------------------
// Simplified version of the three necessary full-tests:
// assign wfull_val=((wgnext[ADDRSIZE] !=wq2_rptr[ADDRSIZE] ) &&
// (wgnext[ADDRSIZE-1] !=wq2_rptr[ADDRSIZE-1]) &&
// (wgnext[ADDRSIZE-2:0]==wq2_rptr[ADDRSIZE-2:0]));
//------------------------------------------------------------------
assign wfull_val = (wgraynext == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
assign awfull_val = (wgraynextp1 == {~wq2_rptr[ADDRSIZE:ADDRSIZE-1],wq2_rptr[ADDRSIZE-2:0]});
always @(posedge wclk or negedge wrst_n) begin
if (!wrst_n) begin
awfull <= 1'b0;
wfull <= 1'b0;
end
else begin
awfull <= awfull_val;
wfull <= wfull_val;
end
end
endmodule
`resetall
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// This module implements exponent extraction and returns the adjusted exponent as integer.
// Adjusted means that we remove the bias implicit in the FP numbers. That is exp=127 that represents exponent of 0
// is returned as 0.
module acl_fp_extract_exp( clock, resetn, enable, valid_in, valid_out, stall_in, stall_out, dataa, result);
parameter WIDTH = 32;
parameter HIGH_CAPACITY = 1;
input clock, resetn;
input enable, valid_in, stall_in;
output valid_out, stall_out;
input [WIDTH-1:0] dataa;
output [31:0] result;
// Simply extract the mantissa and at the most shift it to the right by one position.
reg c1_valid;
wire c1_stall;
wire c1_enable = (HIGH_CAPACITY == 1) ? (~c1_valid | ~c1_stall) : enable;
assign stall_out = c1_valid & c1_stall;
reg [31:0] c1_exponent;
always@(posedge clock or negedge resetn)
begin
if (~resetn)
begin
c1_valid <= 1'b0;
c1_exponent <= 32'dx;
end
else if (c1_enable)
begin
c1_valid <= valid_in;
if (WIDTH==32)
begin
if ((~(|dataa[WIDTH-2:WIDTH-9])) || (&dataa[WIDTH-2:WIDTH-9]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-9]} - 9'd127;
end
end
else
begin
if ((~(|dataa[WIDTH-2:WIDTH-12])) || (&dataa[WIDTH-2:WIDTH-12]))
begin
c1_exponent <= 32'h7fffffff;
end
else
begin
c1_exponent <= {1'b0, dataa[WIDTH-2:WIDTH-12]} - 12'd1023;
end
end
end
end
assign c1_stall = stall_in;
assign valid_out = c1_valid;
assign result = c1_exponent;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module pcie_hcmd_sq_arb # (
parameter C_PCIE_DATA_WIDTH = 128,
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input pcie_user_clk,
input pcie_user_rst_n,
input [8:0] sq_rst_n,
input [8:0] sq_valid,
input [7:0] admin_sq_size,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] admin_sq_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [7:0] admin_sq_tail_ptr,
input [7:0] io_sq1_tail_ptr,
input [7:0] io_sq2_tail_ptr,
input [7:0] io_sq3_tail_ptr,
input [7:0] io_sq4_tail_ptr,
input [7:0] io_sq5_tail_ptr,
input [7:0] io_sq6_tail_ptr,
input [7:0] io_sq7_tail_ptr,
input [7:0] io_sq8_tail_ptr,
output arb_sq_rdy,
output [3:0] sq_qid,
output [C_PCIE_ADDR_WIDTH-1:2] hcmd_pcie_addr,
input sq_hcmd_ack
);
localparam S_ARB_HCMD = 5'b00001;
localparam S_LOAD_HEAD_PTR = 5'b00010;
localparam S_CALC_ADDR = 5'b00100;
localparam S_GNT_HCMD = 5'b01000;
localparam S_UPDATE_HEAD_PTR = 5'b10000;
reg [4:0] cur_state;
reg [4:0] next_state;
reg [7:0] r_admin_sq_head_ptr;
reg [7:0] r_io_sq1_head_ptr;
reg [7:0] r_io_sq2_head_ptr;
reg [7:0] r_io_sq3_head_ptr;
reg [7:0] r_io_sq4_head_ptr;
reg [7:0] r_io_sq5_head_ptr;
reg [7:0] r_io_sq6_head_ptr;
reg [7:0] r_io_sq7_head_ptr;
reg [7:0] r_io_sq8_head_ptr;
reg r_arb_sq_rdy;
reg [3:0] r_sq_qid;
reg [7:0] r_sq_head_ptr;
reg [C_PCIE_ADDR_WIDTH-1:2] r_hcmd_pcie_addr;
wire [8:0] w_sq_entry_valid;
wire w_sq_entry_valid_ok;
reg [8:0] r_sq_entry_valid;
wire [8:0] w_sq_valid_mask;
reg [8:0] r_sq_update_entry;
wire [8:0] w_sq_rst_n;
assign arb_sq_rdy = r_arb_sq_rdy;
assign sq_qid = r_sq_qid;
assign hcmd_pcie_addr = r_hcmd_pcie_addr;
assign w_sq_entry_valid[0] = (r_admin_sq_head_ptr != admin_sq_tail_ptr) & sq_valid[0];
assign w_sq_entry_valid[1] = (r_io_sq1_head_ptr != io_sq1_tail_ptr) & sq_valid[1];
assign w_sq_entry_valid[2] = (r_io_sq2_head_ptr != io_sq2_tail_ptr) & sq_valid[2];
assign w_sq_entry_valid[3] = (r_io_sq3_head_ptr != io_sq3_tail_ptr) & sq_valid[3];
assign w_sq_entry_valid[4] = (r_io_sq4_head_ptr != io_sq4_tail_ptr) & sq_valid[4];
assign w_sq_entry_valid[5] = (r_io_sq5_head_ptr != io_sq5_tail_ptr) & sq_valid[5];
assign w_sq_entry_valid[6] = (r_io_sq6_head_ptr != io_sq6_tail_ptr) & sq_valid[6];
assign w_sq_entry_valid[7] = (r_io_sq7_head_ptr != io_sq7_tail_ptr) & sq_valid[7];
assign w_sq_entry_valid[8] = (r_io_sq8_head_ptr != io_sq8_tail_ptr) & sq_valid[8];
assign w_sq_valid_mask = {r_sq_entry_valid[7:0], r_sq_entry_valid[8]};
assign w_sq_entry_valid_ok = ((w_sq_entry_valid[8:1] & w_sq_valid_mask[8:1]) != 0) | w_sq_entry_valid[0];
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0)
cur_state <= S_ARB_HCMD;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid_ok == 1)
next_state <= S_LOAD_HEAD_PTR;
else
next_state <= S_ARB_HCMD;
end
S_LOAD_HEAD_PTR: begin
next_state <= S_CALC_ADDR;
end
S_CALC_ADDR: begin
next_state <= S_GNT_HCMD;
end
S_GNT_HCMD: begin
if(sq_hcmd_ack == 1)
next_state <= S_UPDATE_HEAD_PTR;
else
next_state <= S_GNT_HCMD;
end
S_UPDATE_HEAD_PTR: begin
next_state <= S_ARB_HCMD;
end
default: begin
next_state <= S_ARB_HCMD;
end
endcase
end
always @ (posedge pcie_user_clk or negedge pcie_user_rst_n)
begin
if(pcie_user_rst_n == 0) begin
r_sq_entry_valid <= 1;
end
else begin
case(cur_state)
S_ARB_HCMD: begin
if(w_sq_entry_valid[0] == 1)
r_sq_entry_valid <= 1;
else
r_sq_entry_valid <= w_sq_valid_mask;
end
S_LOAD_HEAD_PTR: begin
end
S_CALC_ADDR: begin
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
end
always @ (posedge pcie_user_clk)
begin
case(cur_state)
S_ARB_HCMD: begin
end
S_LOAD_HEAD_PTR: begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: begin
r_hcmd_pcie_addr <= admin_sq_bs_addr;
r_sq_head_ptr <= r_admin_sq_head_ptr;
end
9'b000000010: begin
r_hcmd_pcie_addr <= io_sq1_bs_addr;
r_sq_head_ptr <= r_io_sq1_head_ptr;
end
9'b000000100: begin
r_hcmd_pcie_addr <= io_sq2_bs_addr;
r_sq_head_ptr <= r_io_sq2_head_ptr;
end
9'b000001000: begin
r_hcmd_pcie_addr <= io_sq3_bs_addr;
r_sq_head_ptr <= r_io_sq3_head_ptr;
end
9'b000010000: begin
r_hcmd_pcie_addr <= io_sq4_bs_addr;
r_sq_head_ptr <= r_io_sq4_head_ptr;
end
9'b000100000: begin
r_hcmd_pcie_addr <= io_sq5_bs_addr;
r_sq_head_ptr <= r_io_sq5_head_ptr;
end
9'b001000000: begin
r_hcmd_pcie_addr <= io_sq6_bs_addr;
r_sq_head_ptr <= r_io_sq6_head_ptr;
end
9'b010000000: begin
r_hcmd_pcie_addr <= io_sq7_bs_addr;
r_sq_head_ptr <= r_io_sq7_head_ptr;
end
9'b100000000: begin
r_hcmd_pcie_addr <= io_sq8_bs_addr;
r_sq_head_ptr <= r_io_sq8_head_ptr;
end
endcase
end
S_CALC_ADDR: begin
r_hcmd_pcie_addr <= r_hcmd_pcie_addr + {r_sq_head_ptr, 4'b0};
r_sq_head_ptr <= r_sq_head_ptr + 1;
end
S_GNT_HCMD: begin
end
S_UPDATE_HEAD_PTR: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_ARB_HCMD: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_LOAD_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_CALC_ADDR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
S_GNT_HCMD: begin
r_arb_sq_rdy <= 1;
r_sq_update_entry <= 0;
end
S_UPDATE_HEAD_PTR: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= r_sq_entry_valid;
end
default: begin
r_arb_sq_rdy <= 0;
r_sq_update_entry <= 0;
end
endcase
end
always @ (*)
begin
case(r_sq_entry_valid) // synthesis parallel_case full_case
9'b000000001: r_sq_qid <= 4'h0;
9'b000000010: r_sq_qid <= 4'h1;
9'b000000100: r_sq_qid <= 4'h2;
9'b000001000: r_sq_qid <= 4'h3;
9'b000010000: r_sq_qid <= 4'h4;
9'b000100000: r_sq_qid <= 4'h5;
9'b001000000: r_sq_qid <= 4'h6;
9'b010000000: r_sq_qid <= 4'h7;
9'b100000000: r_sq_qid <= 4'h8;
endcase
end
assign w_sq_rst_n[0] = pcie_user_rst_n & sq_rst_n[0];
assign w_sq_rst_n[1] = pcie_user_rst_n & sq_rst_n[1];
assign w_sq_rst_n[2] = pcie_user_rst_n & sq_rst_n[2];
assign w_sq_rst_n[3] = pcie_user_rst_n & sq_rst_n[3];
assign w_sq_rst_n[4] = pcie_user_rst_n & sq_rst_n[4];
assign w_sq_rst_n[5] = pcie_user_rst_n & sq_rst_n[5];
assign w_sq_rst_n[6] = pcie_user_rst_n & sq_rst_n[6];
assign w_sq_rst_n[7] = pcie_user_rst_n & sq_rst_n[7];
assign w_sq_rst_n[8] = pcie_user_rst_n & sq_rst_n[8];
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[0])
begin
if(w_sq_rst_n[0] == 0) begin
r_admin_sq_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[0] == 1) begin
if(r_admin_sq_head_ptr == admin_sq_size) begin
r_admin_sq_head_ptr <= 0;
end
else begin
r_admin_sq_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[1])
begin
if(w_sq_rst_n[1] == 0) begin
r_io_sq1_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[1] == 1) begin
if(r_io_sq1_head_ptr == io_sq1_size) begin
r_io_sq1_head_ptr <= 0;
end
else begin
r_io_sq1_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[2])
begin
if(w_sq_rst_n[2] == 0) begin
r_io_sq2_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[2] == 1) begin
if(r_io_sq2_head_ptr == io_sq2_size) begin
r_io_sq2_head_ptr <= 0;
end
else begin
r_io_sq2_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[3])
begin
if(w_sq_rst_n[3] == 0) begin
r_io_sq3_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[3] == 1) begin
if(r_io_sq3_head_ptr == io_sq3_size) begin
r_io_sq3_head_ptr <= 0;
end
else begin
r_io_sq3_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[4])
begin
if(w_sq_rst_n[4] == 0) begin
r_io_sq4_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[4] == 1) begin
if(r_io_sq4_head_ptr == io_sq4_size) begin
r_io_sq4_head_ptr <= 0;
end
else begin
r_io_sq4_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[5])
begin
if(w_sq_rst_n[5] == 0) begin
r_io_sq5_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[5] == 1) begin
if(r_io_sq5_head_ptr == io_sq5_size) begin
r_io_sq5_head_ptr <= 0;
end
else begin
r_io_sq5_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[6])
begin
if(w_sq_rst_n[6] == 0) begin
r_io_sq6_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[6] == 1) begin
if(r_io_sq6_head_ptr == io_sq6_size) begin
r_io_sq6_head_ptr <= 0;
end
else begin
r_io_sq6_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[7])
begin
if(w_sq_rst_n[7] == 0) begin
r_io_sq7_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[7] == 1) begin
if(r_io_sq7_head_ptr == io_sq7_size) begin
r_io_sq7_head_ptr <= 0;
end
else begin
r_io_sq7_head_ptr <= r_sq_head_ptr;
end
end
end
end
always @ (posedge pcie_user_clk or negedge w_sq_rst_n[8])
begin
if(w_sq_rst_n[8] == 0) begin
r_io_sq8_head_ptr <= 0;
end
else begin
if(r_sq_update_entry[8] == 1) begin
if(r_io_sq8_head_ptr == io_sq8_size) begin
r_io_sq8_head_ptr <= 0;
end
else begin
r_io_sq8_head_ptr <= r_sq_head_ptr;
end
end
end
end
endmodule
|
// SEG7_Display.v
// This file was auto-generated as part of a SOPC Builder generate operation.
// If you edit it your changes will probably be lost.
`timescale 1 ps / 1 ps
module SEG7_Display (
input wire iCLK, // clk.clk
input wire iWR, // avalon_slave.write
input wire [31:0] iDIG, // .writedata
output wire [6:0] oSEG0, // conduit_end.export
output wire [6:0] oSEG1, // .export
output wire [6:0] oSEG2, // .export
output wire [6:0] oSEG3, // .export
output wire [6:0] oSEG4, // .export
output wire [6:0] oSEG5, // .export
output wire [6:0] oSEG6, // .export
output wire [6:0] oSEG7, // .export
input wire iRST_N // reset_n.reset_n
);
SEG7_LUT_8 seg7_display (
.iCLK (iCLK), // clk.clk
.iWR (iWR), // avalon_slave.write
.iDIG (iDIG), // .writedata
.oSEG0 (oSEG0), // conduit_end.export
.oSEG1 (oSEG1), // .export
.oSEG2 (oSEG2), // .export
.oSEG3 (oSEG3), // .export
.oSEG4 (oSEG4), // .export
.oSEG5 (oSEG5), // .export
.oSEG6 (oSEG6), // .export
.oSEG7 (oSEG7), // .export
.iRST_N (iRST_N) // reset_n.reset_n
);
endmodule
|
`include "assert.vh"
`include "cpu.vh"
module cpu_tb();
reg clk = 0;
//
// ROM
//
localparam MEM_ADDR = 6;
localparam MEM_EXTRA = 4;
localparam STACK_DEPTH = 7;
reg [ MEM_ADDR :0] mem_addr;
reg [ MEM_EXTRA-1:0] mem_extra;
reg [ MEM_ADDR :0] rom_lower_bound = 0;
reg [ MEM_ADDR :0] rom_upper_bound = ~0;
wire [2**MEM_EXTRA*8-1:0] mem_data;
wire mem_error;
genrom #(
.ROMFILE("call1.hex"),
.AW(MEM_ADDR),
.DW(8),
.EXTRA(MEM_EXTRA)
)
ROM (
.clk(clk),
.addr(mem_addr),
.extra(mem_extra),
.lower_bound(rom_lower_bound),
.upper_bound(rom_upper_bound),
.data(mem_data),
.error(mem_error)
);
//
// CPU
//
parameter HAS_FPU = 1;
parameter USE_64B = 1;
reg reset = 1;
reg [ MEM_ADDR:0] pc = 33;
reg [STACK_DEPTH:0] index = 0;
wire [ 63:0] result;
wire [ 1:0] result_type;
wire result_empty;
wire [ 3:0] trap;
cpu #(
.HAS_FPU(HAS_FPU),
.USE_64B(USE_64B),
.MEM_DEPTH(MEM_ADDR),
.STACK_DEPTH(STACK_DEPTH)
)
dut
(
.clk(clk),
.reset(reset),
.pc(pc),
.index(index),
.result(result),
.result_type(result_type),
.result_empty(result_empty),
.trap(trap),
.mem_addr(mem_addr),
.mem_extra(mem_extra),
.mem_data(mem_data),
.mem_error(mem_error)
);
always #1 clk = ~clk;
initial begin
$dumpfile("call1_tb.vcd");
$dumpvars(0, cpu_tb);
#1
reset <= 0;
if(USE_64B) begin
#29
`assert(result, 42);
`assert(result_type, `i64);
`assert(result_empty, 0);
end
else begin
#17
`assert(trap, `NO_64B);
end
$finish;
end
endmodule
|
(***********************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA-Rocquencourt & LRI-CNRS-Orsay *)
(* \VV/ *************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(***********************************************************************)
(* $Id$ *)
(**************************************************************)
(* FSetDecide.v *)
(* *)
(* Author: Aaron Bohannon *)
(**************************************************************)
(** This file implements a decision procedure for a certain
class of propositions involving finite sets. *)
Require Import Decidable DecidableTypeEx FSetFacts.
(** First, a version for Weak Sets *)
Module WDecide (E : DecidableType)(Import M : WSfun E).
Module F := FSetFacts.WFacts E M.
(** * Overview
This functor defines the tactic [fsetdec], which will
solve any valid goal of the form
<<
forall s1 ... sn,
forall x1 ... xm,
P1 -> ... -> Pk -> P
>>
where [P]'s are defined by the grammar:
<<
P ::=
| Q
| Empty F
| Subset F F'
| Equal F F'
Q ::=
| E.eq X X'
| In X F
| Q /\ Q'
| Q \/ Q'
| Q -> Q'
| Q <-> Q'
| ~ Q
| True
| False
F ::=
| S
| empty
| singleton X
| add X F
| remove X F
| union F F'
| inter F F'
| diff F F'
X ::= x1 | ... | xm
S ::= s1 | ... | sn
>>
The tactic will also work on some goals that vary slightly from
the above form:
- The variables and hypotheses may be mixed in any order and may
have already been introduced into the context. Moreover,
there may be additional, unrelated hypotheses mixed in (these
will be ignored).
- A conjunction of hypotheses will be handled as easily as
separate hypotheses, i.e., [P1 /\ P2 -> P] can be solved iff
[P1 -> P2 -> P] can be solved.
- [fsetdec] should solve any goal if the FSet-related hypotheses
are contradictory.
- [fsetdec] will first perform any necessary zeta and beta
reductions and will invoke [subst] to eliminate any Coq
equalities between finite sets or their elements.
- If [E.eq] is convertible with Coq's equality, it will not
matter which one is used in the hypotheses or conclusion.
- The tactic can solve goals where the finite sets or set
elements are expressed by Coq terms that are more complicated
than variables. However, non-local definitions are not
expanded, and Coq equalities between non-variable terms are
not used. For example, this goal will be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2)
>>
This one will not be solved:
<<
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2)
>>
*)
(** * Facts and Tactics for Propositional Logic
These lemmas and tactics are in a module so that they do
not affect the namespace if you import the enclosing
module [Decide]. *)
Module FSetLogicalFacts.
Require Export Decidable.
Require Export Setoid.
(** ** Lemmas and Tactics About Decidable Propositions *)
(** ** Propositional Equivalences Involving Negation
These are all written with the unfolded form of
negation, since I am not sure if setoid rewriting will
always perform conversion. *)
(** ** Tactics for Negations *)
Tactic Notation "fold" "any" "not" :=
repeat (
match goal with
| H: context [?P -> False] |- _ =>
fold (~ P) in H
| |- context [?P -> False] =>
fold (~ P)
end).
(** [push not using db] will pushes all negations to the
leaves of propositions in the goal, using the lemmas in
[db] to assist in checking the decidability of the
propositions involved. If [using db] is omitted, then
[core] will be used. Additional versions are provided
to manipulate the hypotheses or the hypotheses and goal
together.
XXX: This tactic and the similar subsequent ones should
have been defined using [autorewrite]. However, dealing
with multiples rewrite sites and side-conditions is
done more cleverly with the following explicit
analysis of goals. *)
Ltac or_not_l_iff P Q tac :=
(rewrite (or_not_l_iff_1 P Q) by tac) ||
(rewrite (or_not_l_iff_2 P Q) by tac).
Ltac or_not_r_iff P Q tac :=
(rewrite (or_not_r_iff_1 P Q) by tac) ||
(rewrite (or_not_r_iff_2 P Q) by tac).
Ltac or_not_l_iff_in P Q H tac :=
(rewrite (or_not_l_iff_1 P Q) in H by tac) ||
(rewrite (or_not_l_iff_2 P Q) in H by tac).
Ltac or_not_r_iff_in P Q H tac :=
(rewrite (or_not_r_iff_1 P Q) in H by tac) ||
(rewrite (or_not_r_iff_2 P Q) in H by tac).
Tactic Notation "push" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [?P \/ ?Q -> False] => rewrite (not_or_iff P Q)
| |- context [?P /\ ?Q -> False] => rewrite (not_and_iff P Q)
| |- context [(?P -> ?Q) -> False] => rewrite (not_imp_iff P Q) by dec
end);
fold any not.
Tactic Notation "push" "not" :=
push not using core.
Tactic Notation
"push" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [?P \/ ?Q -> False] |- _ => rewrite (not_or_iff P Q) in H
| H: context [?P /\ ?Q -> False] |- _ => rewrite (not_and_iff P Q) in H
| H: context [(?P -> ?Q) -> False] |- _ =>
rewrite (not_imp_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "push" "not" "in" "*" "|-" :=
push not in * |- using core.
Tactic Notation "push" "not" "in" "*" "using" ident(db) :=
push not using db; push not in * |- using db.
Tactic Notation "push" "not" "in" "*" :=
push not in * using core.
(** A simple test case to see how this works. *)
Lemma test_push : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ ((R -> P) \/ (Q -> R))) ->
(~ (P /\ R)) ->
(~ (P -> R)) ->
True.
Proof.
intros. push not in *.
(* note that ~(R->P) remains (since R isnt decidable) *)
tauto.
Qed.
(** [pull not using db] will pull as many negations as
possible toward the top of the propositions in the goal,
using the lemmas in [db] to assist in checking the
decidability of the propositions involved. If [using
db] is omitted, then [core] will be used. Additional
versions are provided to manipulate the hypotheses or
the hypotheses and goal together. *)
Tactic Notation "pull" "not" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff;
repeat (
match goal with
| |- context [True -> False] => rewrite not_true_iff
| |- context [False -> False] => rewrite not_false_iff
| |- context [(?P -> False) -> False] => rewrite (not_not_iff P) by dec
| |- context [(?P -> False) -> (?Q -> False)] =>
rewrite (contrapositive P Q) by dec
| |- context [(?P -> False) \/ ?Q] => or_not_l_iff P Q dec
| |- context [?P \/ (?Q -> False)] => or_not_r_iff P Q dec
| |- context [(?P -> False) -> ?Q] => rewrite (imp_not_l P Q) by dec
| |- context [(?P -> False) /\ (?Q -> False)] =>
rewrite <- (not_or_iff P Q)
| |- context [?P -> ?Q -> False] => rewrite <- (not_and_iff P Q)
| |- context [?P /\ (?Q -> False)] => rewrite <- (not_imp_iff P Q) by dec
| |- context [(?Q -> False) /\ ?P] =>
rewrite <- (not_imp_rev_iff P Q) by dec
end);
fold any not.
Tactic Notation "pull" "not" :=
pull not using core.
Tactic Notation
"pull" "not" "in" "*" "|-" "using" ident(db) :=
let dec := solve_decidable using db in
unfold not, iff in * |-;
repeat (
match goal with
| H: context [True -> False] |- _ => rewrite not_true_iff in H
| H: context [False -> False] |- _ => rewrite not_false_iff in H
| H: context [(?P -> False) -> False] |- _ =>
rewrite (not_not_iff P) in H by dec
| H: context [(?P -> False) -> (?Q -> False)] |- _ =>
rewrite (contrapositive P Q) in H by dec
| H: context [(?P -> False) \/ ?Q] |- _ => or_not_l_iff_in P Q H dec
| H: context [?P \/ (?Q -> False)] |- _ => or_not_r_iff_in P Q H dec
| H: context [(?P -> False) -> ?Q] |- _ =>
rewrite (imp_not_l P Q) in H by dec
| H: context [(?P -> False) /\ (?Q -> False)] |- _ =>
rewrite <- (not_or_iff P Q) in H
| H: context [?P -> ?Q -> False] |- _ =>
rewrite <- (not_and_iff P Q) in H
| H: context [?P /\ (?Q -> False)] |- _ =>
rewrite <- (not_imp_iff P Q) in H by dec
| H: context [(?Q -> False) /\ ?P] |- _ =>
rewrite <- (not_imp_rev_iff P Q) in H by dec
end);
fold any not.
Tactic Notation "pull" "not" "in" "*" "|-" :=
pull not in * |- using core.
Tactic Notation "pull" "not" "in" "*" "using" ident(db) :=
pull not using db; pull not in * |- using db.
Tactic Notation "pull" "not" "in" "*" :=
pull not in * using core.
(** A simple test case to see how this works. *)
Lemma test_pull : forall P Q R : Prop,
decidable P ->
decidable Q ->
(~ True) ->
(~ False) ->
(~ ~ P) ->
(~ (P /\ Q) -> ~ R) ->
((P /\ Q) \/ ~ R) ->
(~ (P /\ Q) \/ R) ->
(R \/ ~ (P /\ Q)) ->
(~ R \/ (P /\ Q)) ->
(~ P -> R) ->
(~ (R -> P) /\ ~ (Q -> R)) ->
(~ P \/ ~ R) ->
(P /\ ~ R) ->
(~ R /\ P) ->
True.
Proof.
intros. pull not in *. tauto.
Qed.
End FSetLogicalFacts.
Import FSetLogicalFacts.
(** * Auxiliary Tactics
Again, these lemmas and tactics are in a module so that
they do not affect the namespace if you import the
enclosing module [Decide]. *)
Module FSetDecideAuxiliary.
(** ** Generic Tactics
We begin by defining a few generic, useful tactics. *)
(** [if t then t1 else t2] executes [t] and, if it does not
fail, then [t1] will be applied to all subgoals
produced. If [t] fails, then [t2] is executed. *)
Tactic Notation
"if" tactic(t)
"then" tactic(t1)
"else" tactic(t2) :=
first [ t; first [ t1 | fail 2 ] | t2 ].
(** [prop P holds by t] succeeds (but does not modify the
goal or context) if the proposition [P] can be proved by
[t] in the current context. Otherwise, the tactic
fails. *)
Tactic Notation "prop" constr(P) "holds" "by" tactic(t) :=
let H := fresh in
assert P as H by t;
clear H.
(** This tactic acts just like [assert ... by ...] but will
fail if the context already contains the proposition. *)
Tactic Notation "assert" "new" constr(e) "by" tactic(t) :=
match goal with
| H: e |- _ => fail 1
| _ => assert e by t
end.
(** [subst++] is similar to [subst] except that
- it never fails (as [subst] does on recursive
equations),
- it substitutes locally defined variable for their
definitions,
- it performs beta reductions everywhere, which may
arise after substituting a locally defined function
for its definition.
*)
Tactic Notation "subst" "++" :=
repeat (
match goal with
| x : _ |- _ => subst x
end);
cbv zeta beta in *.
(** [decompose records] calls [decompose record H] on every
relevant hypothesis [H]. *)
Tactic Notation "decompose" "records" :=
repeat (
match goal with
| H: _ |- _ => progress (decompose record H); clear H
end).
(** ** Discarding Irrelevant Hypotheses
We will want to clear the context of any
non-FSet-related hypotheses in order to increase the
speed of the tactic. To do this, we will need to be
able to decide which are relevant. We do this by making
a simple inductive definition classifying the
propositions of interest. *)
Inductive FSet_elt_Prop : Prop -> Prop :=
| eq_Prop : forall (S : Set) (x y : S),
FSet_elt_Prop (x = y)
| eq_elt_prop : forall x y,
FSet_elt_Prop (E.eq x y)
| In_elt_prop : forall x s,
FSet_elt_Prop (In x s)
| True_elt_prop :
FSet_elt_Prop True
| False_elt_prop :
FSet_elt_Prop False
| conj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P /\ Q)
| disj_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P \/ Q)
| impl_elt_prop : forall P Q,
FSet_elt_Prop P ->
FSet_elt_Prop Q ->
FSet_elt_Prop (P -> Q)
| not_elt_prop : forall P,
FSet_elt_Prop P ->
FSet_elt_Prop (~ P).
Inductive FSet_Prop : Prop -> Prop :=
| elt_FSet_Prop : forall P,
FSet_elt_Prop P ->
FSet_Prop P
| Empty_FSet_Prop : forall s,
FSet_Prop (Empty s)
| Subset_FSet_Prop : forall s1 s2,
FSet_Prop (Subset s1 s2)
| Equal_FSet_Prop : forall s1 s2,
FSet_Prop (Equal s1 s2).
(** Here is the tactic that will throw away hypotheses that
are not useful (for the intended scope of the [fsetdec]
tactic). *)
Hint Constructors FSet_elt_Prop FSet_Prop : FSet_Prop.
Ltac discard_nonFSet :=
decompose records;
repeat (
match goal with
| H : ?P |- _ =>
if prop (FSet_Prop P) holds by
(auto 100 with FSet_Prop)
then fail
else clear H
end).
(** ** Turning Set Operators into Propositional Connectives
The lemmas from [FSetFacts] will be used to break down
set operations into propositional formulas built over
the predicates [In] and [E.eq] applied only to
variables. We are going to use them with [autorewrite].
*)
Hint Rewrite
F.empty_iff F.singleton_iff F.add_iff F.remove_iff
F.union_iff F.inter_iff F.diff_iff
: set_simpl.
(** ** Decidability of FSet Propositions *)
(** [In] is decidable. *)
Lemma dec_In : forall x s,
decidable (In x s).
Proof.
red; intros; generalize (F.mem_iff s x); case (mem x s); intuition.
Qed.
(** [E.eq] is decidable. *)
Lemma dec_eq : forall (x y : E.t),
decidable (E.eq x y).
Proof.
red; intros x y; destruct (E.eq_dec x y); auto.
Qed.
(** The hint database [FSet_decidability] will be given to
the [push_neg] tactic from the module [Negation]. *)
Hint Resolve dec_In dec_eq : FSet_decidability.
(** ** Normalizing Propositions About Equality
We have to deal with the fact that [E.eq] may be
convertible with Coq's equality. Thus, we will find the
following tactics useful to replace one form with the
other everywhere. *)
(** The next tactic, [Logic_eq_to_E_eq], mentions the term
[E.t]; thus, we must ensure that [E.t] is used in favor
of any other convertible but syntactically distinct
term. *)
Ltac change_to_E_t :=
repeat (
match goal with
| H : ?T |- _ =>
progress (change T with E.t in H);
repeat (
match goal with
| J : _ |- _ => progress (change T with E.t in J)
| |- _ => progress (change T with E.t)
end )
end).
(** These two tactics take us from Coq's built-in equality
to [E.eq] (and vice versa) when possible. *)
Ltac Logic_eq_to_E_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change (@Logic.eq E.t) with E.eq in H)
| |- _ =>
progress (change (@Logic.eq E.t) with E.eq)
end).
Ltac E_eq_to_Logic_eq :=
repeat (
match goal with
| H: _ |- _ =>
progress (change E.eq with (@Logic.eq E.t) in H)
| |- _ =>
progress (change E.eq with (@Logic.eq E.t))
end).
(** This tactic works like the built-in tactic [subst], but
at the level of set element equality (which may not be
the convertible with Coq's equality). *)
Ltac substFSet :=
repeat (
match goal with
| H: E.eq ?x ?y |- _ => rewrite H in *; clear H
end).
(** ** Considering Decidability of Base Propositions
This tactic adds assertions about the decidability of
[E.eq] and [In] to the context. This is necessary for
the completeness of the [fsetdec] tactic. However, in
order to minimize the cost of proof search, we should be
careful to not add more than we need. Once negations
have been pushed to the leaves of the propositions, we
only need to worry about decidability for those base
propositions that appear in a negated form. *)
Ltac assert_decidability :=
(** We actually don't want these rules to fire if the
syntactic context in the patterns below is trivially
empty, but we'll just do some clean-up at the
afterward. *)
repeat (
match goal with
| H: context [~ E.eq ?x ?y] |- _ =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| H: context [~ In ?x ?s] |- _ =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
| |- context [~ E.eq ?x ?y] =>
assert new (E.eq x y \/ ~ E.eq x y) by (apply dec_eq)
| |- context [~ In ?x ?s] =>
assert new (In x s \/ ~ In x s) by (apply dec_In)
end);
(** Now we eliminate the useless facts we added (because
they would likely be very harmful to performance). *)
repeat (
match goal with
| _: ~ ?P, H : ?P \/ ~ ?P |- _ => clear H
end).
(** ** Handling [Empty], [Subset], and [Equal]
This tactic instantiates universally quantified
hypotheses (which arise from the unfolding of [Empty],
[Subset], and [Equal]) for each of the set element
expressions that is involved in some membership or
equality fact. Then it throws away those hypotheses,
which should no longer be needed. *)
Ltac inst_FSet_hypotheses :=
repeat (
match goal with
| H : forall a : E.t, _,
_ : context [ In ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ In ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq ?x _ ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq ?x _ ] =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _,
_ : context [ E.eq _ ?x ] |- _ =>
let P := type of (H x) in
assert new P by (exact (H x))
| H : forall a : E.t, _
|- context [ E.eq _ ?x ] =>
let P := type of (H x) in
assert new P by (exact (H x))
end);
repeat (
match goal with
| H : forall a : E.t, _ |- _ =>
clear H
end).
(** ** The Core [fsetdec] Auxiliary Tactics *)
(** Here is the crux of the proof search. Recursion through
[intuition]! (This will terminate if I correctly
understand the behavior of [intuition].) *)
Ltac fsetdec_rec :=
try (match goal with
| H: E.eq ?x ?x -> False |- _ => destruct H
end);
(reflexivity ||
contradiction ||
(progress substFSet; intuition fsetdec_rec)).
(** If we add [unfold Empty, Subset, Equal in *; intros;] to
the beginning of this tactic, it will satisfy the same
specification as the [fsetdec] tactic; however, it will
be much slower than necessary without the pre-processing
done by the wrapper tactic [fsetdec]. *)
Ltac fsetdec_body :=
inst_FSet_hypotheses;
autorewrite with set_simpl in *;
push not in * using FSet_decidability;
substFSet;
assert_decidability;
auto using E.eq_refl;
(intuition fsetdec_rec) ||
fail 1
"because the goal is beyond the scope of this tactic".
End FSetDecideAuxiliary.
Import FSetDecideAuxiliary.
(** * The [fsetdec] Tactic
Here is the top-level tactic (the only one intended for
clients of this library). It's specification is given at
the top of the file. *)
Ltac fsetdec :=
(** We first unfold any occurrences of [iff]. *)
unfold iff in *;
(** We fold occurrences of [not] because it is better for
[intros] to leave us with a goal of [~ P] than a goal of
[False]. *)
fold any not; intros;
(** Now we decompose conjunctions, which will allow the
[discard_nonFSet] and [assert_decidability] tactics to
do a much better job. *)
decompose records;
discard_nonFSet;
(** We unfold these defined propositions on finite sets. If
our goal was one of them, then have one more item to
introduce now. *)
unfold Empty, Subset, Equal in *; intros;
(** We now want to get rid of all uses of [=] in favor of
[E.eq]. However, the best way to eliminate a [=] is in
the context is with [subst], so we will try that first.
In fact, we may as well convert uses of [E.eq] into [=]
when possible before we do [subst] so that we can even
more mileage out of it. Then we will convert all
remaining uses of [=] back to [E.eq] when possible. We
use [change_to_E_t] to ensure that we have a canonical
name for set elements, so that [Logic_eq_to_E_eq] will
work properly. *)
change_to_E_t; E_eq_to_Logic_eq; subst++; Logic_eq_to_E_eq;
(** The next optimization is to swap a negated goal with a
negated hypothesis when possible. Any swap will improve
performance by eliminating the total number of
negations, but we will get the maximum benefit if we
swap the goal with a hypotheses mentioning the same set
element, so we try that first. If we reach the fourth
branch below, we attempt any swap. However, to maintain
completeness of this tactic, we can only perform such a
swap with a decidable proposition; hence, we first test
whether the hypothesis is an [FSet_elt_Prop], noting
that any [FSet_elt_Prop] is decidable. *)
pull not using FSet_decidability;
unfold not in *;
match goal with
| H: (In ?x ?r) -> False |- (In ?x ?s) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?x ?y) -> False =>
contradict H; fsetdec_body
| H: (In ?x ?r) -> False |- (E.eq ?y ?x) -> False =>
contradict H; fsetdec_body
| H: ?P -> False |- ?Q -> False =>
if prop (FSet_elt_Prop P) holds by
(auto 100 with FSet_Prop)
then (contradict H; fsetdec_body)
else fsetdec_body
| |- _ =>
fsetdec_body
end.
(** * Examples *)
Module FSetDecideTestCases.
Lemma test_eq_trans_1 : forall x y z s,
E.eq x y ->
~ ~ E.eq z y ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_trans_2 : forall x y z r s,
In x (singleton y) ->
~ In z r ->
~ ~ In z (add y r) ->
In x s ->
In z s.
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_1 : forall w x y z s,
E.eq x w ->
~ ~ E.eq x y ->
~ E.eq y z ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_eq_neq_trans_2 : forall w x y z r1 r2 s,
In x (singleton w) ->
~ In x r1 ->
In x (add y r1) ->
In y r2 ->
In y (remove z r2) ->
In w s ->
In w (remove z s).
Proof. fsetdec. Qed.
Lemma test_In_singleton : forall x,
In x (singleton x).
Proof. fsetdec. Qed.
Lemma test_Subset_add_remove : forall x s,
s [<=] (add x (remove x s)).
Proof. fsetdec. Qed.
Lemma test_eq_disjunction : forall w x y z,
In w (add x (add y (singleton z))) ->
E.eq w x \/ E.eq w y \/ E.eq w z.
Proof. fsetdec. Qed.
Lemma test_not_In_disj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ (In x s1 \/ In x s4 \/ E.eq y x).
Proof. fsetdec. Qed.
Lemma test_not_In_conj : forall x y s1 s2 s3 s4,
~ In x (union s1 (union s2 (union s3 (add y s4)))) ->
~ In x s1 /\ ~ In x s4 /\ ~ E.eq y x.
Proof. fsetdec. Qed.
Lemma test_iff_conj : forall a x s s',
(In a s' <-> E.eq x a \/ In a s) ->
(In a s' <-> In a (add x s)).
Proof. fsetdec. Qed.
Lemma test_set_ops_1 : forall x q r s,
(singleton x) [<=] s ->
Empty (union q r) ->
Empty (inter (diff s q) (diff s r)) ->
~ In x s.
Proof. fsetdec. Qed.
Lemma eq_chain_test : forall x1 x2 x3 x4 s1 s2 s3 s4,
Empty s1 ->
In x2 (add x1 s1) ->
In x3 s2 ->
~ In x3 (remove x2 s2) ->
~ In x4 s3 ->
In x4 (add x3 s3) ->
In x1 s4 ->
Subset (add x4 s4) s4.
Proof. fsetdec. Qed.
Lemma test_too_complex : forall x y z r s,
E.eq x y ->
(In x (singleton y) -> r [<=] s) ->
In z r ->
In z s.
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until s; intros Heq H Hr; lapply H; fsetdec.
Qed.
Lemma function_test_1 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g (g x2)) ->
In x1 s1 ->
In (g (g x2)) (f s2).
Proof. fsetdec. Qed.
Lemma function_test_2 :
forall (f : t -> t),
forall (g : elt -> elt),
forall (s1 s2 : t),
forall (x1 x2 : elt),
Equal s1 (f s2) ->
E.eq x1 (g x2) ->
In x1 s1 ->
g x2 = g (g x2) ->
In (g (g x2)) (f s2).
Proof.
(** [fsetdec] is not intended to solve this directly. *)
intros until 3. intros g_eq. rewrite <- g_eq. fsetdec.
Qed.
End FSetDecideTestCases.
End WDecide.
Require Import FSetInterface.
(** Now comes a special version dedicated to full sets. For this
one, only one argument [(M:S)] is necessary. *)
Module Decide (M : S).
Module D:=OT_as_DT M.E.
Module WD := WDecide D M.
Ltac fsetdec := WD.fsetdec.
End Decide. |
//-----------------------------------------------------------------------------
// Copyright (C) 2014 iZsh <izsh at fail0verflow.com>
//
// This code is licensed to you under the terms of the GNU GPL, version 2 or,
// at your option, any later version. See the LICENSE.txt file for the text of
// the license.
//-----------------------------------------------------------------------------
// testbench for lf_edge_detect
`include "lf_edge_detect.v"
`define FIN "tb_tmp/data.filtered.gold"
`define FOUT_MIN "tb_tmp/data.min"
`define FOUT_MAX "tb_tmp/data.max"
`define FOUT_STATE "tb_tmp/data.state"
`define FOUT_TOGGLE "tb_tmp/data.toggle"
`define FOUT_HIGH "tb_tmp/data.high"
`define FOUT_HIGHZ "tb_tmp/data.highz"
`define FOUT_LOWZ "tb_tmp/data.lowz"
`define FOUT_LOW "tb_tmp/data.low"
module lf_edge_detect_tb;
integer fin, fout_state, fout_toggle;
integer fout_high, fout_highz, fout_lowz, fout_low, fout_min, fout_max;
integer r;
reg clk = 0;
reg [7:0] adc_d;
wire adc_clk;
wire data_rdy;
wire edge_state;
wire edge_toggle;
wire [7:0] high_threshold;
wire [7:0] highz_threshold;
wire [7:0] lowz_threshold;
wire [7:0] low_threshold;
wire [7:0] max;
wire [7:0] min;
initial
begin
clk = 0;
fin = $fopen(`FIN, "r");
if (!fin) begin
$display("ERROR: can't open the data file");
$finish;
end
fout_min = $fopen(`FOUT_MIN, "w+");
fout_max = $fopen(`FOUT_MAX, "w+");
fout_state = $fopen(`FOUT_STATE, "w+");
fout_toggle = $fopen(`FOUT_TOGGLE, "w+");
fout_high = $fopen(`FOUT_HIGH, "w+");
fout_highz = $fopen(`FOUT_HIGHZ, "w+");
fout_lowz = $fopen(`FOUT_LOWZ, "w+");
fout_low = $fopen(`FOUT_LOW, "w+");
if (!$feof(fin))
adc_d = $fgetc(fin); // read the first value
end
always
# 1 clk = !clk;
// input
initial
begin
while (!$feof(fin)) begin
@(negedge clk) adc_d <= $fgetc(fin);
end
if ($feof(fin))
begin
# 3 $fclose(fin);
$fclose(fout_state);
$fclose(fout_toggle);
$fclose(fout_high);
$fclose(fout_highz);
$fclose(fout_lowz);
$fclose(fout_low);
$fclose(fout_min);
$fclose(fout_max);
$finish;
end
end
initial
begin
// $monitor("%d\t S: %b, E: %b", $time, edge_state, edge_toggle);
end
// output
always @(negedge clk)
if ($time > 2) begin
r = $fputc(min, fout_min);
r = $fputc(max, fout_max);
r = $fputc(edge_state, fout_state);
r = $fputc(edge_toggle, fout_toggle);
r = $fputc(high_threshold, fout_high);
r = $fputc(highz_threshold, fout_highz);
r = $fputc(lowz_threshold, fout_lowz);
r = $fputc(low_threshold, fout_low);
end
// module to test
lf_edge_detect detect(clk, adc_d, 8'd127,
max, min,
high_threshold, highz_threshold,
lowz_threshold, low_threshold,
edge_state, edge_toggle);
endmodule |
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: Sora_RCB
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description: Sora RCB top level wrapper.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// PCIe endpoint_blk_plus Logicore version 1.9 is used.
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "Sora_config.v" // set verilog include directories in ise synthesize property
`include "PCIe_setting.v"
//-------------------------------------------------------
// Sora_RCB top Module
//-------------------------------------------------------
`define RCB
module Sora_RCB
#(
parameter DDR_SIM = 0
)
(
//-------------------------------------------------------
// 1. PCI Express Fabric Interface
//-------------------------------------------------------
// Tx
output wire [(`PCI_EXP_LINK_WIDTH - 1):0] pci_exp_txp,
output wire [(`PCI_EXP_LINK_WIDTH - 1):0] pci_exp_txn,
// Rx
input wire [(`PCI_EXP_LINK_WIDTH - 1):0] pci_exp_rxp,
input wire [(`PCI_EXP_LINK_WIDTH - 1):0] pci_exp_rxn,
//-------------------------------------------------------
// 4. System (SYS) Interface
//-------------------------------------------------------
input wire pcie_sys_clk_p,
input wire pcie_sys_clk_n,
input wire sys_reset_n,
//-------------------------------------------------------
// 6. DDR2 Interface
//-------------------------------------------------------
input wire SYS_CLK_P,
input wire SYS_CLK_N,
input wire CLK200_P,
input wire CLK200_N,
inout wire [63:0] DDR2_DQ,
output wire [12:0] DDR2_A,
output wire [1:0] DDR2_BA,
output wire DDR2_RAS_N,
output wire DDR2_CAS_N,
output wire DDR2_WE_N,
output wire DDR2_RESET_N,
output wire DDR2_CS_N,
output wire DDR2_ODT,
output wire DDR2_CKE,
output wire [7:0] DDR2_DM,
inout wire [7:0] DDR2_DQS,
inout wire [7:0] DDR2_DQS_N,
output wire [1:0] DDR2_CK,
output wire [1:0] DDR2_CK_N,
//-------------------------------------------------------
// 7. Radio Interface
//-------------------------------------------------------
`ifdef WARPRadio
input RF_DAC_SPI_SDO,
output RF_DAC_SPI_SDI,
output RF_DAC_SPI_CLK,
output RF_DAC_SPI_CSB,
output RF_DAC_RESET,
input RF_DAC_PLLLOCK,
output [15:0] RF_DAC_I_DATA,
output [15:0] RF_DAC_Q_DATA,
output RF_RSSI_SLEEP,
input RF_RSSI_OTR,
output RF_RSSI_HIZ,
output RF_RSSI_CLK,
output RF_RSSI_CLAMP,
input [9:0] RF_RSSI_DATA,
output RF_RADIO_TXEN,
output RF_RADIO_RXEN,
output RF_RADIO_SHDN_N,
output RF_RADIO_RXHP,
input RF_RADIO_LD,
output RF_RADIO_SPI_SDI,
output RF_RADIO_SPI_CSB,
output RF_RADIO_SPI_CLK,
output [6:0] RF_RADIO_GAIN,
output RF_ADC_PWDNA,
output RF_ADC_PWDNB,
input RF_ADC_OTRA,
input RF_ADC_OTRB,
output RF_ADC_DFS,
output RF_ADC_DCS,
input [13:0] RF_ADC_DATA_A,
input [13:0] RF_ADC_DATA_B,
output [2:0] RF_LED,
output RF_CLK_N,
output RF_CLK_P,
// input [3:0] RF_DIPSW,
output [1:0] RF_ANTSW,
output RF_5PA_EN_N,
output RF_24PA_EN_N,
`endif
`ifdef SORA_FRL
output Sora_FRL_CLK_O_p,
output Sora_FRL_CLK_O_n,
input Sora_FRL_CLK_I_p,
input Sora_FRL_CLK_I_n,
output Sora_FRL_MSG_OUT_p,
output Sora_FRL_MSG_OUT_n,
input Sora_FRL_MSG_IN_p,
input Sora_FRL_MSG_IN_n,
input [3:0] Sora_FRL_DATA_IN_p,
input [3:0] Sora_FRL_DATA_IN_n,
output [3:0] Sora_FRL_DATA_OUT_p,
output [3:0] Sora_FRL_DATA_OUT_n,
input Sora_FRL_STATUS_IN_p,
input Sora_FRL_STATUS_IN_n,
output Sora_FRL_STATUS_OUT_p,
output Sora_FRL_STATUS_OUT_n,
`endif
`ifdef SORA_FRL_2nd
output Sora_FRL_2nd_CLK_O_p,
output Sora_FRL_2nd_CLK_O_n,
input Sora_FRL_2nd_CLK_I_p,
input Sora_FRL_2nd_CLK_I_n,
output Sora_FRL_2nd_MSG_OUT_p,
output Sora_FRL_2nd_MSG_OUT_n,
input Sora_FRL_2nd_MSG_IN_p,
input Sora_FRL_2nd_MSG_IN_n,
input [3:0] Sora_FRL_2nd_DATA_IN_p,
input [3:0] Sora_FRL_2nd_DATA_IN_n,
output [3:0] Sora_FRL_2nd_DATA_OUT_p,
output [3:0] Sora_FRL_2nd_DATA_OUT_n,
input Sora_FRL_2nd_STATUS_IN_p,
input Sora_FRL_2nd_STATUS_IN_n,
output Sora_FRL_2nd_STATUS_OUT_p,
output Sora_FRL_2nd_STATUS_OUT_n,
`endif
//-------------------------------------------------------
// 7. Debug Interface
//-------------------------------------------------------
//// Jiansong, 2009-12-10, send RXEnable signal to LED
// output wire RXEnable_n,
`ifdef SORA_FRL
output wire LED_link_up_and_phy_init_initialization_done_n,
output wire Sora_FRL_done_n,
`else
output wire LED_link_up_n,
output wire phy_init_initialization_done_n,
// output wire Radio_LO_Lock_n,
`endif
/// Jiansong: LED for clock
// output wire LED_clock,
output wire Radio_TX_n,
`ifdef RCB
// output wire LED_clock_1,
output wire Radio_RX_blink,
`endif
`ifdef RCB
output wire nPLOAD_1,
output wire nPLOAD_2 );
`else
output wire PLOAD_1,
output wire PLOAD_2 );
`endif
//-------------------------------------------------------
// Local Wires
//-------------------------------------------------------
wire sys_clk_c;
wire sys_reset_n_c;
wire trn_clk_c;
wire clk_0_from_mem_ctrl_dcm;
//XST treats the PCIe Block Plus as a black-box and will insert
//a BUFG on the user clock (trn_clk_c) unless buffer_type is none
//synthesis attribute buffer_type of trn_clk_c is "none"
//synthesis attribute max_fanout of trn_clk_c is "100000"
wire trn_reset_n_c;
wire trn_lnk_up_n_c;
wire cfg_trn_pending_n_c;
wire [(`PCI_EXP_CFG_DSN_WIDTH - 1):0] cfg_dsn_n_c;
wire trn_tsof_n_c;
wire trn_teof_n_c;
wire trn_tsrc_rdy_n_c;
wire trn_tdst_rdy_n_c;
wire trn_tsrc_dsc_n_c;
wire trn_terrfwd_n_c;
wire trn_tdst_dsc_n_c;
wire [(`PCI_EXP_TRN_DATA_WIDTH - 1):0] trn_td_c;
wire [(`PCI_EXP_TRN_REM_WIDTH - 1):0] trn_trem_n_c;
wire [(`PCI_EXP_TRN_BUF_AV_WIDTH - 1):0] trn_tbuf_av_c;
wire trn_rsof_n_c;
wire trn_reof_n_c;
wire trn_rsrc_rdy_n_c;
wire trn_rsrc_dsc_n_c;
wire trn_rdst_rdy_n_c;
wire trn_rerrfwd_n_c;
wire trn_rnp_ok_n_c;
wire [(`PCI_EXP_TRN_DATA_WIDTH - 1):0] trn_rd_c;
wire [(`PCI_EXP_TRN_REM_WIDTH - 1):0] trn_rrem_n_c;
wire [(`PCI_EXP_TRN_BAR_HIT_WIDTH - 1):0] trn_rbar_hit_n_c;
wire [(`PCI_EXP_TRN_FC_HDR_WIDTH - 1):0] trn_rfc_nph_av_c;
wire [(`PCI_EXP_TRN_FC_DATA_WIDTH - 1):0] trn_rfc_npd_av_c;
wire [(`PCI_EXP_TRN_FC_HDR_WIDTH - 1):0] trn_rfc_ph_av_c;
wire [(`PCI_EXP_TRN_FC_DATA_WIDTH - 1):0] trn_rfc_pd_av_c;
wire [(`PCI_EXP_TRN_FC_HDR_WIDTH - 1):0] trn_rfc_cplh_av_c;
wire [(`PCI_EXP_TRN_FC_DATA_WIDTH - 1):0] trn_rfc_cpld_av_c;
wire trn_rcpl_streaming_n_c;
wire [(`PCI_EXP_CFG_DATA_WIDTH - 1):0] cfg_do_c;
wire [(`PCI_EXP_CFG_DATA_WIDTH - 1):0] cfg_di_c;
wire [(`PCI_EXP_CFG_ADDR_WIDTH - 1):0] cfg_dwaddr_c;
wire [(`PCI_EXP_CFG_DATA_WIDTH/8 - 1):0] cfg_byte_en_n_c;
wire [(`PCI_EXP_CFG_CPLHDR_WIDTH - 1):0] cfg_err_tlp_cpl_header_c;
wire cfg_wr_en_n_c;
wire cfg_rd_en_n_c;
wire cfg_rd_wr_done_n_c;
wire cfg_err_cor_n_c;
wire cfg_err_ur_n_c;
wire cfg_err_ecrc_n_c;
wire cfg_err_cpl_timeout_n_c;
wire cfg_err_cpl_timeout;
wire cfg_err_cpl_abort_n_c;
wire cfg_err_cpl_unexpect_n_c;
wire cfg_err_posted_n_c;
wire cfg_err_cpl_rdy_n_c;
wire cfg_interrupt_n_c;
wire cfg_interrupt_rdy_n_c;
wire cfg_interrupt_assert_n_c;
wire [7 : 0] cfg_interrupt_di_c;
wire [7 : 0] cfg_interrupt_do_c;
wire [2 : 0] cfg_interrupt_mmenable_c;
wire cfg_interrupt_msienable_c;
wire cfg_turnoff_ok_n_c;
wire cfg_to_turnoff_n;
wire cfg_pm_wake_n_c;
wire [(`PCI_EXP_LNK_STATE_WIDTH - 1):0] cfg_pcie_link_state_n_c;
wire [(`PCI_EXP_CFG_BUSNUM_WIDTH - 1):0] cfg_bus_number_c;
wire [(`PCI_EXP_CFG_DEVNUM_WIDTH - 1):0] cfg_device_number_c;
wire [(`PCI_EXP_CFG_FUNNUM_WIDTH - 1):0] cfg_function_number_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_status_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_command_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_dstatus_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_dcommand_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_lstatus_c;
wire [(`PCI_EXP_CFG_CAP_WIDTH - 1):0] cfg_lcommand_c;
wire RST_i;
wire [127:0] WRITE_MEM_DATA;
wire [127:0] READ_MEM_DATA;
wire MEM_SEL;
wire WRITE_DATA_FULL;
wire ADDR_ALMOST_FULL;
//added the delay for functional simulation to account for FIFO
//delay in functional model
wire [30:0] #1 MEM_ADDR;
wire [2:0] MEM_CMD;
wire #1 DATA_WREN;
wire #1 ADDR_WREN;
wire [127:0] ingress_data;
wire [1:0] ingress_fifo_ctrl;
wire [1:0] ingress_fifo_status;
wire [2:0] ingress_xfer_size;
wire [27:6] ingress_start_addr;
wire ingress_data_req;
wire ingress_data_ack;
wire [12:0] pcie_id;
reg trn_reset_c;
reg [12:0] pcie_id_reg;
reg [2:0] max_pay_size_reg;
reg [2:0] max_read_req_reg;
wire pause_read_requests;
/// Jiansong: wires added by Jiansong
wire hostreset;
reg sys_reset;
// RX FIFO
wire [63:0] RX_FIFO_data_out;
wire RX_FIFO_RDEN;
wire RX_FIFO_pempty;
wire RXEnable;
wire RX_FIFO_full;
// the 2nd RX FIFO
`ifdef SORA_FRL_2nd
wire [63:0] RX_FIFO_2nd_data_out;
wire RX_FIFO_2nd_RDEN;
wire RX_FIFO_2nd_pempty;
wire RX_FIFO_2nd_full;
`endif
// Radio Module
//// wire [31:0] Radio_RX_data;
//// wire [15:0] Radio_RX_loop_data;
`ifdef WARPRadio
wire [15:0] Radio_RX_data_I;
wire [15:0] Radio_RX_data_Q;
`endif
`ifdef SORA_FRL
wire [31:0] Sora_FRL_RX_data;
wire Sora_FRL_RX_clk;
wire Sora_FRL_RX_wren;
`endif
// the 2nd Sora FRL
`ifdef SORA_FRL_2nd
wire [31:0] Sora_FRL_2nd_RX_data;
wire Sora_FRL_2nd_RX_clk;
wire Sora_FRL_2nd_RX_wren;
`endif
wire RX_FIFO_wren;
wire RX_FIFO_wrclk;
wire [15:0] Radio_TX_data;
wire [1:0] Radio_TX_FIFO_ctrl;
wire [2:0] Radio_TX_FIFO_status;
wire Radio_TX_done;
wire Radio_TX_start;
wire TX_FIFO_rdclk;
// clock wires
// wire clk200;
// wire clk80;
wire clk133;
`ifdef WARPRadio
wire sample_clock_select; // 0: 44MHz, 1: 40MHz
wire clk_sample;
wire clk44;
wire clk40;
wire clk11;
`endif
wire sys_clk_ibufg;
wire sys_clk_bufg;
/// Jiansong: TX related wires
wire TX_DDR_data_req;
wire TX_DDR_data_ack;
wire [27:6] TX_DDR_start_addr;
wire [2:0] TX_DDR_xfer_size;
/// Jiansong: error signals
wire egress_overflow_one;
wire [31:0] egress_rd_data_count;
wire [31:0] egress_wr_data_count;
/// Jiansong: pipeline registers for ddr
reg [127:0] WRITE_MEM_DATA_r;
reg [30:0] MEM_ADDR_r;
reg [2:0] MEM_CMD_r;
reg DATA_WREN_r;
reg ADDR_WREN_r;
`ifdef SORA_RADIO_REGISTERS
wire [1:0] Sora_RadioControl;
wire [31:0] Sora_LEDControl;
wire [31:0] Sora_AntennaSelection;
wire [31:0] Sora_SampleClock;
wire Sora_SampleClockSet;
wire [31:0] Sora_CoarseFreq;
wire [31:0] Sora_FinegradeFreq;
wire [31:0] Sora_FreqCompensation;
wire Sora_CenterFreqSet;
wire Sora_RadioLOLock;
wire [31:0] Sora_FilterBandwidth;
wire Sora_FilterBandwidthSet;
wire [31:0] Sora_TXVGA1;
wire [31:0] Sora_TXVGA2;
wire [31:0] Sora_TXPA1;
wire [31:0] Sora_TXPA2;
wire [31:0] Sora_RXLNA;
wire [31:0] Sora_RXPA;
wire [31:0] Sora_RXVGA1;
wire [31:0] Sora_RXVGA2;
`endif
`ifdef RADIO_CHANNEL_REGISTERS
wire [31:0] RChannel_Cmd_Data;
wire [6:0] RChannel_Cmd_Addr;
wire RChannel_Cmd_RdWr;
wire RChannel_Cmd_wren;
wire [31:0] RChannel_Reg_Read_Value;
wire RChannel_ReadDone;
wire RChannel_Cmd_FIFO_rden;
wire [39:0] RChannel_Cmd_FIFO_data;
wire RChannel_Cmd_FIFO_empty;
`endif
/// host register to WARP radio interface
`ifdef WARPRadio
wire [7:0] host_SPI_DAC_instruct;
wire [7:0] host_SPI_DAC_wdata;
wire host_SPI_DAC_start;
wire host_SPI_DAC_done;
wire [7:0] host_SPI_DAC_rdata;
wire [3:0] host_SPI_Radio_Addr;
wire [13:0] host_SPI_Radio_Data;
wire host_SPI_Radio_start;
wire host_SPI_Radio_done;
wire host_Radio_SHDN;
wire host_Radio_Reset;
wire host_Radio_RXHP;
wire host_Radio_LD;
wire [5:0] host_Radio_TXGAIN;
wire [6:0] host_Radio_RXGAIN;
wire host_DAC_RESET;
wire host_DAC_PLLLOCK;
wire host_RSSI_SLEEP;
wire host_RSSI_OTR;
wire host_RSSI_HIZ;
wire host_RSSI_CLAMP;
wire [9:0] host_RSSI_Data;
wire host_ADC_PWDNA;
wire host_ADC_PWDNB;
wire host_ADC_OTRA;
wire host_ADC_OTRB;
wire host_ADC_DFS;
wire host_ADC_DCS;
wire [2:0] host_Radio_LED;
wire [1:0] host_Radio_ANTSelect;
wire [3:0] host_Radio_DIPSW;
`endif
`ifdef SORA_FRL
wire RX_RST;
wire IDLE_RESET;
`endif
/// Jiansong: debug wires
wire [31:0] Debug18DDR1;
wire [31:0] Debug19DDR2;
wire [31:0] Debug23RX4;
wire [4:0] locked_debug;
// Jiansong: wires for output signals
// wire LED_clock_1_i;
// wire LED_clock_i;
// wire RF_CLK_N_i;
// wire RF_CLK_P_i;
reg Sora_RX_wren_LED;
`ifdef SORA_FRL
wire Sora_FRL_linkup;
`endif
assign pcie_id[12:0] = {cfg_bus_number_c[7:0],
cfg_device_number_c[4:0]};
always@(posedge trn_clk_c)begin
max_pay_size_reg[2:0] <= cfg_dcommand_c[7:5];
max_read_req_reg[2:0] <= cfg_dcommand_c[14:12];
pcie_id_reg[12:0] <= pcie_id[12:0];
end
`ifdef RCB
/// Jiansong: added
assign nPLOAD_2 = 1'b0;
assign nPLOAD_1 = 1'b0; //Always assert PLOAD_1 to the clock syntheziser
//chip so that a parallel load of the dip switch
//is forced
//The Dip switch should be preset to create the
//correct freq. for the DDR2 design
`else
/// Jiansong: added
assign PLOAD_2 = 1'b1;
assign PLOAD_1 = 1'b1; //Always assert PLOAD_1 to the clock syntheziser
//chip so that a parallel load of the dip switch
//is forced
//The Dip switch should be preset to create the
//correct freq. for the DDR2 design
`endif
//-------------------------------------------------------
// System Reset Input Pad Instance
//-------------------------------------------------------
// 100 MHz clock
IBUFDS refclk_ibuf (.O(sys_clk_c), .I(pcie_sys_clk_p), .IB(pcie_sys_clk_n));
IBUF sys_reset_n_ibuf (.O(sys_reset_n_c), .I(sys_reset_n));
//// Jiansong, 2009-12-10, send RXEnable signal to LED
// OBUF RXEnable_n_OBUF (.O(RXEnable_n), .I(~RXEnable));
`ifdef SORA_FRL
OBUF Sora_FRL_done_n_OBUF (.O(Sora_FRL_done_n), .I(~Sora_FRL_linkup));
OBUF LED_link_up_and_phy_init_initialization_done_n_OBUF (.O(LED_link_up_and_phy_init_initialization_done_n),
.I( (~phy_init_initialization_done) | trn_lnk_up_n_c ) );
`else
OBUF LED_link_up_n_OBUF(.O(LED_link_up_n), .I(trn_lnk_up_n_c));
OBUF DDR2_phy_init_n_OBUF(.O(phy_init_initialization_done_n),
.I(~phy_init_initialization_done));
// OBUF Radio_LO_Lock_n_OBUF (.O(Radio_LO_Lock_n), .I(~host_Radio_LD));
`endif
// output buffer to drive board circuits
// OBUF LED_clock_1_OBUF(.O(LED_clock_1), .I(~LED_clock_1_i));
OBUF Radio_TX_n_OBUF(.O(Radio_TX_n), .I(~Radio_TX_start));
//`ifdef SORA_FRL
OBUF Radio_RX_blink_OBUF(.O(Radio_RX_blink), .I(~Sora_RX_wren_LED));
//`else // SORA_FRL
// OBUF LED_clock_OBUF(.O(LED_clock), .I(~LED_clock_i));
//`endif // SORA_FRL
// OBUF RF_CLK_N_OBUF(.O(RF_CLK_N), .I(RF_CLK_N_i));
// OBUF RF_CLK_P_OBUF(.O(RF_CLK_P), .I(RF_CLK_P_i));
assign cfg_err_cpl_timeout_n_c = ~cfg_err_cpl_timeout;
always@(posedge trn_clk_c)
trn_reset_c <= ~trn_reset_n_c;
always@(posedge sys_clk_bufg)
sys_reset <= ~sys_reset_n_c;
/// Jiansong
//-------------------------------------------------------
// Clock module
//-------------------------------------------------------
`ifdef WARPRadio
Clock_module clock_module_inst(
// clock module only accepts hardware reset
.rst(trn_reset_c),
// .clk200(clk200),
.clk200(sys_clk_bufg),
// .clk80(clk80), /// Jiansong: 80MHz clock for radio module
.clk133(clk133),
.clk44(clk44),
.clk40(clk40),
.clk11(clk11),
.locked_debug(locked_debug),
.unlocked_err() /// whether the clocks are locked
);
// sample clock selection
BUFGMUX_CTRL BUFGMUX_CTRL_inst (
.O (clk_sample), // Clock MUX output
.I0 (clk44), // Clock0 input
.I1 (clk40), // Clock1 input
.S (sample_clock_select) // Clock select input
);
// End of BUFGMUX_CTRL_inst instantiation
`endif
`ifdef SORA_FRL
Clock_module_FRL clock_module_FRL_inst(
// clock module only accepts hardware reset
.rst(trn_reset_c),
// .clk200(clk200),
.clk200(sys_clk_bufg),
.clk133(clk133),
.locked_debug(locked_debug),
.unlocked_err() /// whether the clocks are locked
);
`endif
IBUFGDS_LVPECL_25 u_ibufg_sys_clk
(
.I (SYS_CLK_P),
.IB (SYS_CLK_N),
.O (sys_clk_ibufg)
);
BUFG u_bufg_sys_clk
(
.O (sys_clk_bufg),
.I (sys_clk_ibufg)
);
/// Jiansong
//-------------------------------------------------------
// Frequency dividing module for clock output to LED
//-------------------------------------------------------
//`ifdef SORA_FRL
reg [27:0] LED_Counter;
`ifdef SORA_FRL
always@(posedge Sora_FRL_RX_clk) begin
`else
always@(posedge RX_FIFO_wrclk) begin
`endif
if (trn_reset_c | hostreset) begin
LED_Counter <= 28'h000_0000;
Sora_RX_wren_LED <= 1'b0;
end else begin
`ifdef SORA_FRL
if (Sora_FRL_RX_wren) LED_Counter <= LED_Counter + 28'h000_0001;
`else
if (RX_FIFO_wren) LED_Counter <= LED_Counter + 28'h000_0001;
`endif
if (LED_Counter == 28'h14FB180) begin // 22,000,000
LED_Counter <= 28'h000_0000;
Sora_RX_wren_LED <= ~Sora_RX_wren_LED;
end
end
end
//-------------------------------------------------------
// Endpoint Implementation Application
//-------------------------------------------------------
pcie_dma_wrapper pcie_dma_wrapper_inst (
.clk(trn_clk_c),
.hard_rst(sys_reset),
.rst(trn_reset_c),
// .rst(trn_reset_c | hostreset),
// hot reset to whole system, two cycles
.hostreset(hostreset),
/// Jiansong: interface to RX data fifo
.RX_FIFO_data(RX_FIFO_data_out),
.RX_FIFO_RDEN(RX_FIFO_RDEN),
.RX_FIFO_pempty(RX_FIFO_pempty),
.RXEnable_o(RXEnable),
// interface to 2nd RX data fifo
`ifdef SORA_FRL_2nd
.RX_FIFO_2nd_data(RX_FIFO_2nd_data_out),
.RX_FIFO_2nd_RDEN(RX_FIFO_2nd_RDEN),
.RX_FIFO_2nd_pempty(RX_FIFO_2nd_pempty),
// .RXEnable_o(RXEnable),
`endif
/// Jiansong: interface to radio module
.Radio_TX_done(Radio_TX_done),
.Radio_TX_start(Radio_TX_start),
//interface to dma_ddr2_if
.ingress_xfer_size(ingress_xfer_size),
.ingress_start_addr(ingress_start_addr),
.ingress_data_req(ingress_data_req),
.ingress_data_ack(ingress_data_ack),
.ingress_fifo_status(ingress_fifo_status),
.ingress_fifo_ctrl(ingress_fifo_ctrl),
.ingress_data(ingress_data),
.pause_read_requests(pause_read_requests),
/// Jiansong: TX related inputs/outputs
.TX_DDR_data_req(TX_DDR_data_req),
.TX_DDR_data_ack(TX_DDR_data_ack),
.TX_DDR_start_addr(TX_DDR_start_addr),
.TX_DDR_xfer_size(TX_DDR_xfer_size),
//Misc signals to PCIE Block Plus
.pcie_max_pay_size(max_pay_size_reg[2:0]),
.pcie_max_read_req(max_read_req_reg[2:0]),
.pcie_id(pcie_id_reg[12:0]),
.comp_timeout(cfg_err_cpl_timeout),
// Tx Local-Link PCIE Block Plus
.trn_td( trn_td_c ), // O [63/31:0]
.trn_trem_n( trn_trem_n_c ), // O [7:0]
.trn_tsof_n( trn_tsof_n_c ), // O
.trn_teof_n( trn_teof_n_c ), // O
.trn_tsrc_rdy_n( trn_tsrc_rdy_n_c ), // O
.trn_tsrc_dsc_n( trn_tsrc_dsc_n_c ), // O
.trn_tdst_rdy_n( trn_tdst_rdy_n_c ), // I
.trn_tdst_dsc_n( trn_tdst_dsc_n_c ), // I
.trn_terrfwd_n( trn_terrfwd_n_c ), // O
.trn_tbuf_av( trn_tbuf_av_c[2:0] ), // I [4/3:0]
// Rx Local-Link PCIE Block Plus
.trn_rd( trn_rd_c ), // I [63/31:0]
.trn_rrem_n( trn_rrem_n_c ), // I [7:0]
.trn_rsof_n( trn_rsof_n_c ), // I
.trn_reof_n( trn_reof_n_c ), // I
.trn_rsrc_rdy_n( trn_rsrc_rdy_n_c ), // I
.trn_rsrc_dsc_n( trn_rsrc_dsc_n_c ), // I
.trn_rdst_rdy_n( trn_rdst_rdy_n_c ), // O
.trn_rerrfwd_n( trn_rerrfwd_n_c ), // I
.trn_rnp_ok_n( trn_rnp_ok_n_c ), // O
.trn_rbar_hit_n( trn_rbar_hit_n_c ), // I [6:0]
.trn_rfc_npd_av( trn_rfc_npd_av_c ), // I [11:0]
.trn_rfc_nph_av( trn_rfc_nph_av_c ), // I [7:0]
.trn_rfc_pd_av( trn_rfc_pd_av_c ), // I [11:0]
.trn_rfc_ph_av( trn_rfc_ph_av_c ), // I [7:0]
.trn_rfc_cpld_av( trn_rfc_cpld_av_c ), // I [11:0]
.trn_rfc_cplh_av( trn_rfc_cplh_av_c ), // I [7:0]
.trn_rcpl_streaming_n( trn_rcpl_streaming_n_c ), //O
/// Jiansong: error signals
.egress_overflow_one(egress_overflow_one),
.RX_FIFO_full(RX_FIFO_full),
`ifdef SORA_FRL_2nd
.RX_FIFO_2nd_full(RX_FIFO_2nd_full),
`endif
.egress_rd_data_count(egress_rd_data_count),
.egress_wr_data_count(egress_wr_data_count),
//Interface to memory controller
.phy_init_done(phy_init_initialization_done),
// Jiansong: HW status register input
.trn_lnk_up_n_c(trn_lnk_up_n_c),
// radio related inputs/outputs
`ifdef WARP_RADIO_REGISTERS
.RadioAntSelect (host_Radio_ANTSelect),
.RadioDIPSW (host_Radio_DIPSW),
.RadioLEDControl (host_Radio_LED),
.RadioMaximSHDN (host_Radio_SHDN),
.RadioMaximReset (host_Radio_Reset),
.RadioMaximRXHP (host_Radio_RXHP),
.RadioTXGainSetting (host_Radio_TXGAIN),
.RadioRXGainSetting (host_Radio_RXGAIN),
.RadioLD (host_Radio_LD),
.RadioADCControl ({host_ADC_DFS,host_ADC_DCS,host_ADC_PWDNB,host_ADC_PWDNA}),
.RadioADCStatus ({host_ADC_OTRB,host_ADC_OTRA}),
.RadioDACControl (host_DAC_RESET),
.RadioDACStatus (host_DAC_PLLLOCK),
.RadioMaximSPIStart (host_SPI_Radio_start),
.RadioMaximSPIDone (host_SPI_Radio_done),
.RadioDACSPIStart (host_SPI_DAC_start),
.RadioDACSPIDone (host_SPI_DAC_done),
.RadioMaximSPIAddr (host_SPI_Radio_Addr),
.RadioMaximSPIData (host_SPI_Radio_Data),
.RadioDACSPIData (host_SPI_DAC_wdata),
.RadioDACSPIInstuct (host_SPI_DAC_instruct),
.RadioDACSPIDataOut (host_SPI_DAC_rdata),
.RadioRSSIADCControl({host_RSSI_HIZ,host_RSSI_SLEEP,host_RSSI_CLAMP}),
.RadioRSSIData (host_RSSI_Data),
.RadioRSSIOTR (host_RSSI_OTR),
`endif
`ifdef SORA_RADIO_REGISTERS
.RadioControl (Sora_RadioControl),
.RadioStatus_in (Sora_RadioStatus_in),
.RadioID_in (Sora_RadioID_in),
.LEDControl (Sora_LEDControl),
.AntennaSelection (Sora_AntennaSelection),
.SampleClock (Sora_SampleClock),
.SampleClockSet (Sora_SampleClockSet),
.CoarseFreq (Sora_CoarseFreq),
.FinegradeFreq (Sora_FinegradeFreq),
.FreqCompensation (Sora_FreqCompensation),
.CenterFreqSet (Sora_CenterFreqSet),
.RadioLOLock (Sora_RadioLOLock),
.FilterBandwidth (Sora_FilterBandwidth),
.FilterBandwidthSet(Sora_FilterBandwidthSet),
.TXVGA1 (Sora_TXVGA1),
.TXVGA2 (Sora_TXVGA2),
.TXPA1 (Sora_TXPA1),
.TXPA2 (Sora_TXPA2),
.RXLNA (Sora_RXLNA),
.RXPA (Sora_RXPA),
.RXVGA1 (Sora_RXVGA1),
.RXVGA2 (Sora_RXVGA2),
`endif
`ifdef RADIO_CHANNEL_REGISTERS
.Radio_Cmd_Data (RChannel_Cmd_Data[31:0]),
.Radio_Cmd_Addr (RChannel_Cmd_Addr[6:0]),
.Radio_Cmd_RdWr (RChannel_Cmd_RdWr),
.Radio_Cmd_wren (RChannel_Cmd_wren),
.Channel_Reg_Read_Value (RChannel_Reg_Read_Value[31:0]),
.Channel_ReadDone_in (RChannel_ReadDone),
`endif
//Debug interface
.PCIeLinkStatus(cfg_lstatus_c),
.PCIeLinkControl(cfg_lcommand_c),
.Debug18DDR1(Debug18DDR1),
.Debug19DDR2(Debug19DDR2),
.Debug23RX4(Debug23RX4),
.locked_debug(locked_debug)
);
//-------------------------------------------------------
// RX FIFO
//-------------------------------------------------------
`ifdef WARPRadio
/// Jiansong: Data FIFO on RX path, input from radio module and
/// output to posted packet generator
//This is an 4KB FIFO constructed of BRAM
//Converts the datapath from 32-bit to 64-bit
RX_data_fifo RX_data_fifo_WARP_inst(
//// .din (Radio_RX_data),
//// .din (Radio_RX_loop_data),
.din ({Radio_RX_data_Q,Radio_RX_data_I}),
.rd_clk (trn_clk_c),
.rd_en (RX_FIFO_RDEN),
.rst (trn_reset_c | hostreset), /// Jiansong: both hardware and host reset
//// .wr_clk (clk80),
.wr_clk (RX_FIFO_wrclk),
//// .wr_en (~RX_FIFO_full & RXEnable),
.wr_en (RX_FIFO_wren & RXEnable),
// .wr_en (RX_FIFO_wren), // Jiansong: disable RX control for loopback
.dout (RX_FIFO_data_out),
.empty (), /// Jiansong: programing full is used
.full (RX_FIFO_full),
.prog_empty (RX_FIFO_pempty)
);
`endif
`ifdef SORA_FRL
/// Jiansong: Data FIFO on RX path, input from Sora FRL and
/// output to posted packet generator
//This is an 4KB FIFO constructed of BRAM
//Converts the datapath from 32-bit to 64-bit
RX_data_fifo RX_data_fifo_SORA_FRL_inst(
.din (Sora_FRL_RX_data[31:0]),
.rd_clk (trn_clk_c),
.rd_en (RX_FIFO_RDEN),
.rst (trn_reset_c | hostreset), /// Jiansong: both hardware and host reset
.wr_clk (Sora_FRL_RX_clk),
.wr_en (Sora_FRL_RX_wren & RXEnable), // Jiansong: disable RX control for loopback
.dout (RX_FIFO_data_out),
.empty (), /// Jiansong: programing full is used
.full (RX_FIFO_full),
.prog_empty (RX_FIFO_pempty)
);
`endif
`ifdef SORA_FRL_2nd
/// Jiansong: Data FIFO on RX path, input from the 2nd Sora FRL and
/// output to posted packet generator
//This is an 4KB FIFO constructed of BRAM
//Converts the datapath from 32-bit to 64-bit
RX_data_fifo RX_data_fifo_SORA_FRL_2nd_inst(
.din (Sora_FRL_2nd_RX_data[31:0]),
.rd_clk (trn_clk_c),
.rd_en (RX_FIFO_2nd_RDEN),
.rst (trn_reset_c | hostreset), /// Jiansong: both hardware and host reset
.wr_clk (Sora_FRL_2nd_RX_clk),
.wr_en (Sora_FRL_2nd_RX_wren & RXEnable), // Jiansong: disable RX control for loopback
.dout (RX_FIFO_2nd_data_out),
.empty (), /// Jiansong: programing full is used
.full (RX_FIFO_2nd_full),
.prog_empty (RX_FIFO_2nd_pempty)
);
`endif
//-------------------------------------------------------
// Radio module
//-------------------------------------------------------
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++ WARP Radio in GPIO Mode +++++++++++++++++++++
// Jiansong: this module interprets Sora Radio registers into control signals for WARP radio. This module is used when WARP radio is
// directly connected to Sora RCB via GPIOs, and the radio control interface between driver and Sora RCB is "Sora Radio
// registers". This design is for backward compatibility. Because at the very beginning, the radio control interface between
// driver and Sora RCB was "WARP specific radio registers"
//`ifdef SORA_RADIO_REGISTERS
`ifdef SORA_RADIO_REGISTERS_TO_WARP
//`ifdef WARPRadio
Sora_Radio_Interpretation_for_WARP Sora_Radio_Interpretation_for_WARP_inst(
.rst(trn_reset_c | hostreset), // both hardware and host reset
.clk(clk_sample),
// interface to PCIe module (host registers)
.Sora_RadioControl (Sora_RadioControl),
.Sora_RadioStatus_in (Sora_RadioStatus_in),
.Sora_RadioID_in (Sora_RadioID_in),
.Sora_LEDControl (Sora_LEDControl),
.Sora_AntennaSelection (Sora_AntennaSelection),
.Sora_SampleClock (Sora_SampleClock),
.Sora_SampleClockSet (Sora_SampleClockSet),
.Sora_CoarseFreq (Sora_CoarseFreq),
.Sora_FinegradeFreq (Sora_FinegradeFreq),
.Sora_FreqCompensation (Sora_FreqCompensation),
.Sora_CenterFreqSet (Sora_CenterFreqSet),
.Sora_RadioLOLock (Sora_RadioLOLock),
.Sora_FilterBandwidth (Sora_FilterBandwidth),
.Sora_FilterBandwidthSet(Sora_FilterBandwidthSet),
.Sora_TXVGA1 (Sora_TXVGA1),
.Sora_TXVGA2 (Sora_TXVGA2),
.Sora_TXPA1 (Sora_TXPA1),
.Sora_TXPA2 (Sora_TXPA2),
.Sora_RXLNA (Sora_RXLNA),
.Sora_RXPA (Sora_RXPA),
.Sora_RXVGA1 (Sora_RXVGA1),
.Sora_RXVGA2 (Sora_RXVGA2),
// interface to WARP radio module
.host_SPI_DAC_instruct (host_SPI_DAC_instruct),
.host_SPI_DAC_wdata (host_SPI_DAC_wdata),
.host_SPI_DAC_start (host_SPI_DAC_start),
.host_SPI_DAC_done (host_SPI_DAC_done),
.host_SPI_DAC_rdata (host_SPI_DAC_rdata),
.host_SPI_Radio_Addr (host_SPI_Radio_Addr),
.host_SPI_Radio_Data (host_SPI_Radio_Data),
.host_SPI_Radio_start (host_SPI_Radio_start),
.host_SPI_Radio_done (host_SPI_Radio_done),
.host_Radio_SHDN (host_Radio_SHDN),
.host_Radio_Reset (host_Radio_Reset),
.host_Radio_RXHP (host_Radio_RXHP),
.host_Radio_LD (host_Radio_LD),
.host_Radio_TXGAIN (host_Radio_TXGAIN),
.host_Radio_RXGAIN (host_Radio_RXGAIN),
.host_DAC_RESET (host_DAC_RESET),
.host_DAC_PLLLOCK (host_DAC_PLLLOCK),
.host_RSSI_SLEEP (host_RSSI_SLEEP),
.host_RSSI_OTR (host_RSSI_OTR),
.host_RSSI_HIZ (host_RSSI_HIZ),
.host_RSSI_CLAMP (host_RSSI_CLAMP),
.host_RSSI_Data (host_RSSI_Data),
.host_ADC_PWDNA (host_ADC_PWDNA),
.host_ADC_PWDNB (host_ADC_PWDNB),
.host_ADC_OTRA (host_ADC_OTRA),
.host_ADC_OTRB (host_ADC_OTRB),
.host_ADC_DFS (host_ADC_DFS),
.host_ADC_DCS (host_ADC_DCS),
.host_Radio_LED (host_Radio_LED),
.host_Radio_ANTSelect (host_Radio_ANTSelect),
.host_Radio_DIPSW (host_Radio_DIPSW)
);
//`endif
`endif
// Jiansong: The basic function is the same as Sora_Radio_Interpretation_for_WARP. The difference is the interface. Radio Register
// Table is implemented in this module and no longer mapped into RCB Register Table. The interface becomes basic function for
// writing radio registers and reading radio registers
//`ifdef RADIO_CHANNEL_REGISTERS
`ifdef RADIO_CHANNEL_REGISTERS_TO_WARP
// This FIFO acts as buffer for radio control commands from DMA module to radio module
Radio_Register_set_FIFO Radio_Register_set_FIFO_inst(
.din ({RChannel_Cmd_RdWr, RChannel_Cmd_Addr, RChannel_Cmd_Data}),
.rd_clk (clk_sample),
.rd_en (RChannel_Cmd_FIFO_rden),
.rst (trn_reset_c | hostreset),
.wr_clk (trn_clk_c),
.wr_en (RChannel_Cmd_wren),
.dout (RChannel_Cmd_FIFO_data),
.empty (RChannel_Cmd_FIFO_empty),
.full (),
.sbiterr (),
.dbiterr ()
);
Channel_Radio_Interpretation_for_WARP Channel_Radio_Interpretation_for_WARP_inst(
.rst(trn_reset_c | hostreset), // both hardware and host reset
.clk(clk_sample),
.sample_clock_select (sample_clock_select),
// interface to PCIe module (host registers)
.RChannel_Cmd_FIFO_rden (RChannel_Cmd_FIFO_rden),
.RChannel_Cmd_FIFO_data (RChannel_Cmd_FIFO_data[39:0]),
.RChannel_Cmd_FIFO_empty (RChannel_Cmd_FIFO_empty),
.RChannel_Reg_Read_Value (RChannel_Reg_Read_Value),
.RChannel_Reg_Read_Done (RChannel_ReadDone),
// interface to WARP radio module
.host_SPI_DAC_instruct (host_SPI_DAC_instruct),
.host_SPI_DAC_wdata (host_SPI_DAC_wdata),
.host_SPI_DAC_start (host_SPI_DAC_start),
.host_SPI_DAC_done (host_SPI_DAC_done),
.host_SPI_DAC_rdata (host_SPI_DAC_rdata),
.host_SPI_Radio_Addr (host_SPI_Radio_Addr),
.host_SPI_Radio_Data (host_SPI_Radio_Data),
.host_SPI_Radio_start (host_SPI_Radio_start),
.host_SPI_Radio_done (host_SPI_Radio_done),
.host_Radio_SHDN (host_Radio_SHDN),
.host_Radio_Reset (host_Radio_Reset),
.host_Radio_RXHP (host_Radio_RXHP),
.host_Radio_LD (host_Radio_LD),
.host_Radio_TXGAIN (host_Radio_TXGAIN),
.host_Radio_RXGAIN (host_Radio_RXGAIN),
.host_DAC_RESET (host_DAC_RESET),
.host_DAC_PLLLOCK (host_DAC_PLLLOCK),
.host_RSSI_SLEEP (host_RSSI_SLEEP),
.host_RSSI_OTR (host_RSSI_OTR),
.host_RSSI_HIZ (host_RSSI_HIZ),
.host_RSSI_CLAMP (host_RSSI_CLAMP),
.host_RSSI_Data (host_RSSI_Data),
.host_ADC_PWDNA (host_ADC_PWDNA),
.host_ADC_PWDNB (host_ADC_PWDNB),
.host_ADC_OTRA (host_ADC_OTRA),
.host_ADC_OTRB (host_ADC_OTRB),
.host_ADC_DFS (host_ADC_DFS),
.host_ADC_DCS (host_ADC_DCS),
.host_Radio_LED (host_Radio_LED),
.host_Radio_ANTSelect (host_Radio_ANTSelect),
.host_Radio_DIPSW (host_Radio_DIPSW)
);
`endif
// Jiansong: WARP radio module. If WARP radio is directly connected to Sora RCB via GPIOs, this module should be used. Otherwise
// if (whatever) radio module is connected to Sora RCB via LVDS, this module should not be used.
`ifdef WARPRadio
WARP_Radio_module WARP_radio_module_inst(
.rst(trn_reset_c | hostreset), // both hardware and host reset
.data_clk(clk_sample),
.spi_clk(clk11),
// Control from internal logic
.RXEnable(RXEnable),
.TXStart(Radio_TX_start),
// Status to internal logic
.RadioTXDone(Radio_TX_done),
.egress_rd_data_count(egress_rd_data_count),
// interfaces to internal FIFOs
.TX_FIFO_rdclk(TX_FIFO_rdclk),
.TX_FIFO_DataI(Radio_TX_data[7:0]),
.TX_FIFO_DataQ(Radio_TX_data[15:8]),
.TX_FIFO_Control(Radio_TX_FIFO_ctrl),
.TX_FIFO_Status(Radio_TX_FIFO_status),
.RX_FIFO_wrclk(RX_FIFO_wrclk),
.RX_FIFO_Control(RX_FIFO_wren),
.RX_FIFO_Status(RX_FIFO_full),
.RX_FIFO_DataI(Radio_RX_data_I),
.RX_FIFO_DataQ(Radio_RX_data_Q),
// interfaces to internal logic/host registers
.host_SPI_DAC_instruct (host_SPI_DAC_instruct),
.host_SPI_DAC_wdata (host_SPI_DAC_wdata),
.host_SPI_DAC_start (host_SPI_DAC_start),
.host_SPI_DAC_done (host_SPI_DAC_done),
.host_SPI_DAC_rdata (host_SPI_DAC_rdata),
.host_SPI_Radio_Addr (host_SPI_Radio_Addr),
.host_SPI_Radio_Data (host_SPI_Radio_Data),
.host_SPI_Radio_start (host_SPI_Radio_start),
.host_SPI_Radio_done (host_SPI_Radio_done),
.host_Radio_SHDN (host_Radio_SHDN),
.host_Radio_Reset (host_Radio_Reset),
.host_Radio_RXHP (host_Radio_RXHP),
.host_Radio_LD (host_Radio_LD),
.host_Radio_TXGAIN (host_Radio_TXGAIN),
.host_Radio_RXGAIN (host_Radio_RXGAIN),
.host_DAC_RESET (host_DAC_RESET),
.host_DAC_PLLLOCK (host_DAC_PLLLOCK),
.host_RSSI_SLEEP (host_RSSI_SLEEP),
.host_RSSI_OTR (host_RSSI_OTR),
.host_RSSI_HIZ (host_RSSI_HIZ),
.host_RSSI_CLAMP (host_RSSI_CLAMP),
.host_RSSI_Data (host_RSSI_Data),
.host_ADC_PWDNA (host_ADC_PWDNA),
.host_ADC_PWDNB (host_ADC_PWDNB),
.host_ADC_OTRA (host_ADC_OTRA),
.host_ADC_OTRB (host_ADC_OTRB),
.host_ADC_DFS (host_ADC_DFS),
.host_ADC_DCS (host_ADC_DCS),
.host_Radio_LED (host_Radio_LED),
.host_Radio_ANTSelect (host_Radio_ANTSelect),
.host_Radio_DIPSW (host_Radio_DIPSW),
// interfaces to pads/WARP Radio board
.RF_DAC_SPI_SDO (RF_DAC_SPI_SDO),
.RF_DAC_SPI_SDI (RF_DAC_SPI_SDI),
.RF_DAC_SPI_CLK (RF_DAC_SPI_CLK),
.RF_DAC_SPI_CSB (RF_DAC_SPI_CSB),
.RF_DAC_RESET (RF_DAC_RESET),
.RF_DAC_PLLLOCK (RF_DAC_PLLLOCK),
.RF_DAC_I_DATA (RF_DAC_I_DATA),
.RF_DAC_Q_DATA (RF_DAC_Q_DATA),
.RF_RSSI_SLEEP (RF_RSSI_SLEEP),
.RF_RSSI_OTR (RF_RSSI_OTR),
.RF_RSSI_HIZ (RF_RSSI_HIZ),
.RF_RSSI_CLK (RF_RSSI_CLK),
.RF_RSSI_CLAMP (RF_RSSI_CLAMP),
.RF_RSSI_DATA (RF_RSSI_DATA),
.RF_RADIO_TXEN (RF_RADIO_TXEN),
.RF_RADIO_RXEN (RF_RADIO_RXEN),
.RF_RADIO_SHDN_N (RF_RADIO_SHDN_N),
.RF_RADIO_RXHP (RF_RADIO_RXHP),
.RF_RADIO_LD (RF_RADIO_LD),
.RF_RADIO_SPI_SDI (RF_RADIO_SPI_SDI),
.RF_RADIO_SPI_CSB (RF_RADIO_SPI_CSB),
.RF_RADIO_SPI_CLK (RF_RADIO_SPI_CLK),
.RF_RADIO_GAIN (RF_RADIO_GAIN),
.RF_ADC_PWDNA (RF_ADC_PWDNA),
.RF_ADC_PWDNB (RF_ADC_PWDNB),
.RF_ADC_OTRA (RF_ADC_OTRA),
.RF_ADC_OTRB (RF_ADC_OTRB),
.RF_ADC_DFS (RF_ADC_DFS),
.RF_ADC_DCS (RF_ADC_DCS),
.RF_ADC_DATA_A (RF_ADC_DATA_A),
.RF_ADC_DATA_B (RF_ADC_DATA_B),
.RF_LED (RF_LED),
.RF_CLK_N (RF_CLK_N),
.RF_CLK_P (RF_CLK_P),
.RF_ANTSW (RF_ANTSW),
.RF_5PA_EN_N (RF_5PA_EN_N),
.RF_24PA_EN_N (RF_24PA_EN_N),
// debug output
.Debug23RX4(Debug23RX4)
);
`endif
//+++++++++++++++ WARP Radio in Parallel Mode +++++++++++++++++++++
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//`ifndef sora_simulation // we use parallel mode in simulation
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++ Sora Fast Radio Link +++++++++++++++++++++
`ifdef SORA_FRL
Sora_FRL_RCB Sora_FRL_RCB_inst(
// signals to FPGA pins
.CLK_O_p (Sora_FRL_CLK_O_p),
.CLK_O_n (Sora_FRL_CLK_O_n),
.CLK_I_p (Sora_FRL_CLK_I_p),
.CLK_I_n (Sora_FRL_CLK_I_n),
.MSG_OUT_p (Sora_FRL_MSG_OUT_p),
.MSG_OUT_n (Sora_FRL_MSG_OUT_n),
.MSG_IN_p (Sora_FRL_MSG_IN_p),
.MSG_IN_n (Sora_FRL_MSG_IN_n),
.DATA_IN_p (Sora_FRL_DATA_IN_p),
.DATA_IN_n (Sora_FRL_DATA_IN_n),
.DATA_OUT_p (Sora_FRL_DATA_OUT_p),
.DATA_OUT_n (Sora_FRL_DATA_OUT_n),
.STATUS_IN_p (Sora_FRL_STATUS_IN_p),
.STATUS_IN_n (Sora_FRL_STATUS_IN_n),
.STATUS_OUT_p (Sora_FRL_STATUS_OUT_p),
.STATUS_OUT_n (Sora_FRL_STATUS_OUT_n),
// signals to internal modules
.RST_internal (trn_reset_c | hostreset),
.SEND_EN (~Radio_TX_FIFO_status[0]),
.DATA_INT_IN_3 (Radio_TX_data[7:0]),
.DATA_INT_IN_2 (8'h00),
.DATA_INT_IN_1 (Radio_TX_data[15:8]),
.DATA_INT_IN_0 (8'h00),
.CLKRD_INT_DATA_IN (TX_FIFO_rdclk),
.RDEN_DATA_INT_IN (Radio_TX_FIFO_ctrl[0]),
.DATA_INT_OUT (Sora_FRL_RX_data[31:0]),
.CLKWR_INT_DATA_OUT (Sora_FRL_RX_clk),
.WREN_DATA_INT_OUT (Sora_FRL_RX_wren),
.DATA_ALMOSTEMPTY (),
.SEND_EN_MSG (1'b1),
.MSG_INT_IN ({RChannel_Cmd_RdWr,RChannel_Cmd_Addr[6:0],RChannel_Cmd_Data[31:0]}),
.CLKWR_INT_MSG_IN (trn_clk_c),
.WREN_MSG_INT_IN (RChannel_Cmd_wren),
// modified by Jiansong, 2010-5-27, we do not use FIFO to buf MSG_INT_OUT
.MSG_INT_OUT_Data (RChannel_Reg_Read_Value[31:0]),
.MSG_INT_OUT_Addr (),
.MSG_Valid (RChannel_ReadDone),
.STATUS_INT_OUT_CORRECT(),
.STATUS_INT_OUT_WRONG(),
.TxInit (Radio_TX_start),
.TxDone (Radio_TX_done),
.Radio_status_error (),
.Sora_FRL_linkup (Sora_FRL_linkup),
.LED ()
);
`endif
`ifdef SORA_FRL_2nd
Sora_FRL_RCB Sora_FRL_RCB_2nd_inst(
// signals to FPGA pins
.CLK_O_p (Sora_FRL_2nd_CLK_O_p),
.CLK_O_n (Sora_FRL_2nd_CLK_O_n),
.CLK_I_p (Sora_FRL_2nd_CLK_I_p),
.CLK_I_n (Sora_FRL_2nd_CLK_I_n),
.MSG_OUT_p (Sora_FRL_2nd_MSG_OUT_p),
.MSG_OUT_n (Sora_FRL_2nd_MSG_OUT_n),
.MSG_IN_p (Sora_FRL_2nd_MSG_IN_p),
.MSG_IN_n (Sora_FRL_2nd_MSG_IN_n),
.DATA_IN_p (Sora_FRL_2nd_DATA_IN_p),
.DATA_IN_n (Sora_FRL_2nd_DATA_IN_n),
.DATA_OUT_p (Sora_FRL_2nd_DATA_OUT_p),
.DATA_OUT_n (Sora_FRL_2nd_DATA_OUT_n),
.STATUS_IN_p (Sora_FRL_2nd_STATUS_IN_p),
.STATUS_IN_n (Sora_FRL_2nd_STATUS_IN_n),
.STATUS_OUT_p (Sora_FRL_2nd_STATUS_OUT_p),
.STATUS_OUT_n (Sora_FRL_2nd_STATUS_OUT_n),
// signals to internal modules
.RST (trn_reset_c | RX_RST | IDLE_RESET), //xt
.SEND_EN (~Radio_TX_FIFO_status[0]),
.DATA_INT_IN_3 (Radio_TX_data[7:0]),
.DATA_INT_IN_2 (8'h00),
.DATA_INT_IN_1 (Radio_TX_data[15:8]),
.DATA_INT_IN_0 (8'h00),
.CLKRD_INT_DATA_IN (TX_FIFO_rdclk),
.RDEN_DATA_INT_IN (Radio_TX_FIFO_ctrl[0]),
.DATA_INT_OUT (Sora_FRL_2nd_RX_data[31:0]),
.CLKWR_INT_DATA_OUT (Sora_FRL_2nd_RX_clk),
.WREN_DATA_INT_OUT (Sora_FRL_2nd_RX_wren),
.DATA_ALMOSTEMPTY (),
.SEND_EN_MSG (1'b1),
.MSG_INT_IN ({RChannel_Cmd_RdWr,RChannel_Cmd_Addr[6:0],RChannel_Cmd_Data[31:0]}),
.CLKWR_INT_MSG_IN (trn_clk_c),
.WREN_MSG_INT_IN (RChannel_Cmd_wren),
.MSG_INT_OUT (),
.CLKRD_INT_MSG_OUT (1'b0),
.RDEN_MSG_INT_OUT (1'b0),
.STATUS_INT_OUT_CORRECT(),
.STATUS_INT_OUT_WRONG(),
.TxInit (Radio_TX_start),
.TxDone (Radio_TX_done),
.RX_RST (RX_RST), //xt
.IDLE_RESET (IDLE_RESET), //xt
.LED ()
);
`endif
//`endif
//+++++++++++++++ Sora Fast Radio Link +++++++++++++++++++++
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//-------------------------------------------------------
// Block Plus Core for PCI Express Instance
//-------------------------------------------------------
`ifdef sora_simulation
endpoint_blk_plus_v1_8 ep ( /// Jiansong: used for simulation
`else
// endpoint_blk_plus_v1_9 ep ( /// Jiansong: used for synthesize
endpoint_blk_plus_v1_14 ep ( /// Jiansong: used for synthesize
`endif
//
// PCI Express Fabric Interface
//
.pci_exp_txp( pci_exp_txp ), // O [7/3/0:0]
.pci_exp_txn( pci_exp_txn ), // O [7/3/0:0]
.pci_exp_rxp( pci_exp_rxp ), // O [7/3/0:0]
.pci_exp_rxn( pci_exp_rxn ), // O [7/3/0:0]
//
// Transaction ( TRN ) Interface
//
.trn_clk( trn_clk_c ), // O
.trn_reset_n( trn_reset_n_c ), // O
.trn_lnk_up_n( trn_lnk_up_n_c ), // O
// Tx Local-Link
.trn_td( trn_td_c ), // I [63/31:0]
.trn_trem_n( trn_trem_n_c ), // I [7:0]
.trn_tsof_n( trn_tsof_n_c ), // I
.trn_teof_n( trn_teof_n_c ), // I
.trn_tsrc_rdy_n( trn_tsrc_rdy_n_c ), // I
.trn_tsrc_dsc_n( trn_tsrc_dsc_n_c ), // I
.trn_tdst_rdy_n( trn_tdst_rdy_n_c ), // O
.trn_tdst_dsc_n( trn_tdst_dsc_n_c ), // O
.trn_terrfwd_n( trn_terrfwd_n_c ), // I
.trn_tbuf_av( trn_tbuf_av_c ), // O [4/3:0]
// Rx Local-Link
.trn_rd( trn_rd_c ), // O [63/31:0]
.trn_rrem_n( trn_rrem_n_c ), // O [7:0]
.trn_rsof_n( trn_rsof_n_c ), // O
.trn_reof_n( trn_reof_n_c ), // O
.trn_rsrc_rdy_n( trn_rsrc_rdy_n_c ), // O
.trn_rsrc_dsc_n( trn_rsrc_dsc_n_c ), // O
.trn_rdst_rdy_n( trn_rdst_rdy_n_c ), // I
.trn_rerrfwd_n( trn_rerrfwd_n_c ), // O
.trn_rnp_ok_n( trn_rnp_ok_n_c ), // I
.trn_rbar_hit_n( trn_rbar_hit_n_c ), // O [6:0]
.trn_rfc_nph_av( trn_rfc_nph_av_c ), // O [11:0]
.trn_rfc_npd_av( trn_rfc_npd_av_c ), // O [7:0]
.trn_rfc_ph_av( trn_rfc_ph_av_c ), // O [11:0]
.trn_rfc_pd_av( trn_rfc_pd_av_c ), // O [7:0]
.trn_rcpl_streaming_n( trn_rcpl_streaming_n_c ), // I
//
// Host ( CFG ) Interface
//
.cfg_do( cfg_do_c ), // O [31:0]
.cfg_rd_wr_done_n( cfg_rd_wr_done_n_c ), // O
.cfg_di( 32'h00000000), // I [31:0]
.cfg_byte_en_n( 4'b1111), // I [3:0]
.cfg_dwaddr( 10'b0000000000), // I [9:0]
.cfg_wr_en_n( 1'b1), // I
.cfg_rd_en_n( 1'b1), // I
.cfg_err_cor_n( 1'b1), // I
.cfg_err_ur_n( 1'b1), // I
.cfg_err_ecrc_n( 1'b1), // I
// Jiansong, 2010-3-16, disable error report
// .cfg_err_cpl_timeout_n(cfg_err_cpl_timeout_n_c), // I
.cfg_err_cpl_timeout_n(1'b1), // I
.cfg_err_cpl_abort_n( 1'b1), // I
.cfg_err_cpl_unexpect_n( 1'b1), // I
.cfg_err_posted_n( 1'b1), // I
.cfg_err_tlp_cpl_header( 48'h000000000000), // I [47:0]
.cfg_err_cpl_rdy_n(cfg_err_cpl_rdy_n_c), // O
.cfg_err_locked_n(1'b1), // I
.cfg_interrupt_n( 1'b1), // I
.cfg_interrupt_rdy_n( cfg_interrupt_rdy_n_c ), // O
.cfg_interrupt_assert_n(1'b1), // I
.cfg_interrupt_di(8'b00000000), // I [7:0]
.cfg_interrupt_do(cfg_interrupt_do_c), // O [7:0]
.cfg_interrupt_mmenable(cfg_interrupt_mmenable_c), // O [2:0]
.cfg_interrupt_msienable(cfg_interrupt_msienable_c), // O
.cfg_pm_wake_n( 1'b1), // I
.cfg_pcie_link_state_n( cfg_pcie_link_state_n_c ), // O [2:0]
.cfg_to_turnoff_n( cfg_to_turnoff_n_c ), // O
.cfg_trn_pending_n( 1'b1), // I
.cfg_dsn( 64'h0000000000000000), // I [63:0]
.cfg_bus_number( cfg_bus_number_c ), // O [7:0]
.cfg_device_number( cfg_device_number_c ), // O [4:0]
.cfg_function_number( cfg_function_number_c ), // O [2:0]
.cfg_status( cfg_status_c ), // O [15:0]
.cfg_command( cfg_command_c ), // O [15:0]
.cfg_dstatus( cfg_dstatus_c ), // O [15:0]
.cfg_dcommand( cfg_dcommand_c ), // O [15:0]
.cfg_lstatus( cfg_lstatus_c ), // O [15:0]
.cfg_lcommand( cfg_lcommand_c ), // O [15:0]
// System ( SYS ) Interface
.sys_clk( sys_clk_c ), // I
.sys_reset_n( sys_reset_n_c), // I
.refclkout(),
// The following is used for simulation only. Setting
// the following core input to 1 will result in a fast
// train simulation to happen. This bit should not be set
// during synthesis or the core may not operate properly.
`ifdef SIMULATION
.fast_train_simulation_only(1'b1)
`else
.fast_train_simulation_only(1'b0)
`endif
);
dma_ddr2_if dma_ddr2_if_inst(
.radio_clk (TX_FIFO_rdclk),
.dma_clk (trn_clk_c),
.ddr_clk (clk_0_from_mem_ctrl_dcm),
.reset (SYS_RST_FROM_MEM_CTRL | trn_reset_c | hostreset),
//DMA SIGNALS
//egress
.egress_data (Radio_TX_data),
.egress_fifo_ctrl (Radio_TX_FIFO_ctrl),
.egress_fifo_status (Radio_TX_FIFO_status),
.egress_xfer_size (TX_DDR_xfer_size),
.egress_start_addr (TX_DDR_start_addr),
.egress_data_req (TX_DDR_data_req),
.egress_data_ack (TX_DDR_data_ack),
//ingress
.ingress_data (ingress_data),
.ingress_fifo_ctrl (ingress_fifo_ctrl), //bit 1 = reserved
//bit 0 = write_en
.ingress_fifo_status (ingress_fifo_status), //bit 1 = full
//bit 0 = almostfull
.ingress_xfer_size (ingress_xfer_size),
.ingress_start_addr (ingress_start_addr),
.ingress_data_req (ingress_data_req),
.ingress_data_ack (ingress_data_ack),
//END OF DMA SIGNALS
/// Jiansong: error or debug signals
.egress_overflow_one (egress_overflow_one),
.egress_wr_data_count(egress_wr_data_count),
//MEMORY CNTRLR SIGNALS
.m_wrdata (WRITE_MEM_DATA),
.m_rddata (READ_MEM_DATA),
.m_addr (MEM_ADDR[30:0]),
.m_cmd (MEM_CMD[2:0]),
.m_data_wen (DATA_WREN),
.m_addr_wen (ADDR_WREN),
.m_data_valid (READ_MEM_VALID),
.m_wdf_afull (WRITE_DATA_FULL),
.m_af_afull (ADDR_ALMOST_FULL),
//END OF MEMORY CNTRLR SIGNALS
.pause_read_requests (pause_read_requests),
.Debug18DDR1(Debug18DDR1),
.Debug19DDR2(Debug19DDR2)
);
//Instantiate DDR2 memory controller
//This reference design uses a 64bit DDR design
mem_interface_top #(
.BANK_WIDTH(2),
.CLK_WIDTH(2),
.DM_WIDTH(8),
.DQ_WIDTH(64),
.DQS_WIDTH(8),
.ROW_WIDTH(13),
.CAS_LAT(4),
.REG_ENABLE(0),
.SIM_ONLY(DDR_SIM)
)
ddr2_cntrl_inst(
.ddr2_dq (DDR2_DQ), //inout [63:0]
.ddr2_a (DDR2_A), //output [13:0]
.ddr2_ba (DDR2_BA), //output [1:0]
.ddr2_ras_n (DDR2_RAS_N), //output
.ddr2_cas_n (DDR2_CAS_N), //output
.ddr2_we_n (DDR2_WE_N), //output
.ddr2_reset_n (DDR2_RESET_N), //output
.ddr2_cs_n (DDR2_CS_N), //output [0:0]
.ddr2_odt (DDR2_ODT), //output [0:0]
.ddr2_cke (DDR2_CKE), //output [0:0]
.ddr2_dm (DDR2_DM), //output [8:0]
.sys_clk (clk133),
.clk200_p (CLK200_P), //input
.clk200_n (CLK200_N), //input
/// Jiansong: 200MHz output
.clk200_o (),
.sys_rst_n (sys_reset_n_c), // DCM need multi-cycle reset
.rst0_tb (SYS_RST_FROM_MEM_CTRL), //output
.clk0_tb (clk_0_from_mem_ctrl_dcm), //output
.phy_init_done (phy_init_initialization_done), //output
.app_wdf_afull (WRITE_DATA_FULL), //output
.app_af_afull (ADDR_ALMOST_FULL), //output
.rd_data_valid (READ_MEM_VALID), //output
.app_wdf_wren (DATA_WREN), //input
.app_af_wren (ADDR_WREN), //input
.app_af_addr (MEM_ADDR[30:0]), //input [30:0]
.app_af_cmd (MEM_CMD[2:0]),
.rd_data_fifo_out (READ_MEM_DATA),
.app_wdf_data (WRITE_MEM_DATA),
.app_wdf_mask_data(16'b0), //input [15:0]
.ddr2_dqs (DDR2_DQS), //inout [7:0]
.ddr2_dqs_n (DDR2_DQS_N), //inout [7:0]
.ddr2_ck (DDR2_CK), //output [1:0]
.ddr2_ck_n (DDR2_CK_N) //output [1:0]
);
endmodule
|
//------------------------------------------------------------------------------
// (c) Copyright 2013-2015 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//------------------------------------------------------------------------------
// ***************************
// * DO NOT MODIFY THIS FILE *
// ***************************
`timescale 1ps/1ps
module gtwizard_ultrascale_v1_7_1_gthe4_cpll_cal_freq_counter # (
parameter REVISION = 1
)(
output reg [17:0] freq_cnt_o = 18'd0,
output reg done_o,
input wire rst_i,
input wire [15:0] test_term_cnt_i,
input wire ref_clk_i,
input wire test_clk_i
);
//****************************************************************************
// Local Parameters
//****************************************************************************
localparam RESET_STATE = 0;
localparam MEASURE_STATE = 1;
localparam HOLD_STATE = 2;
localparam UPDATE_STATE = 3;
localparam DONE_STATE = 4;
//****************************************************************************
// Local Signals
//****************************************************************************
reg [17:0] testclk_cnt = 18'h00000;
reg [15:0] refclk_cnt = 16'h0000;
reg [3:0] testclk_div4 = 4'h1;
wire testclk_rst;
wire testclk_en;
reg [5:0] hold_clk = 6'd0;
reg [4:0] state = 5'd1;
(* ASYNC_REG = "TRUE" *) reg tstclk_rst_dly1, tstclk_rst_dly2;
(* ASYNC_REG = "TRUE" *) reg testclk_en_dly1, testclk_en_dly2;
//
// need to get testclk_rst into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
tstclk_rst_dly1 <= testclk_rst;
tstclk_rst_dly2 <= tstclk_rst_dly1;
end
//
// need to get testclk_en into TESTCLK_I domain
//
always @(posedge test_clk_i)
begin
testclk_en_dly1 <= testclk_en;
testclk_en_dly2 <= testclk_en_dly1;
end
always @(posedge test_clk_i)
begin
if (tstclk_rst_dly2 == 1'b1)
begin
testclk_div4 <= 4'h1;
end
else
begin
testclk_div4 <= {testclk_div4[2:0], testclk_div4[3]};
end
end
wire testclk_rst_sync;
gtwizard_ultrascale_v1_7_1_reset_synchronizer reset_synchronizer_testclk_rst_inst (
.clk_in (test_clk_i),
.rst_in (testclk_rst),
.rst_out (testclk_rst_sync)
);
always @(posedge test_clk_i or posedge testclk_rst_sync)
begin
if (testclk_rst_sync == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end
/* always @(posedge test_clk_i or posedge testclk_rst)
begin
if (testclk_rst == 1'b1)
begin
testclk_cnt <= 0;
end
else if (testclk_en_dly2 == 1'b1 && testclk_div4 == 4'h8)
begin
testclk_cnt <= testclk_cnt + 1;
end
end */
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i)
done_o <= 1'b0;
else
done_o <= state[DONE_STATE];
end
always @(posedge ref_clk_i or posedge rst_i)
begin
if (rst_i) begin
state <= 0;
state[RESET_STATE] <= 1'b1;
end
else begin
state <= 0;
case (1'b1) // synthesis parallel_case full_case
state[RESET_STATE]:
begin
if (hold_clk == 6'h3F)
state[MEASURE_STATE] <= 1'b1;
else
state[RESET_STATE] <= 1'b1;
end
state[MEASURE_STATE]:
begin
if (refclk_cnt == test_term_cnt_i)
state[HOLD_STATE] <= 1'b1;
else
state[MEASURE_STATE] <= 1'b1;
end
state[HOLD_STATE]:
begin
if (hold_clk == 6'hF)
state[UPDATE_STATE] <= 1'b1;
else
state[HOLD_STATE] <= 1'b1;
end
state[UPDATE_STATE]:
begin
freq_cnt_o <= testclk_cnt;
state[DONE_STATE] <= 1'b1;
end
state[DONE_STATE]:
begin
state[DONE_STATE] <= 1'b1;
end
endcase
end
end
assign testclk_rst = state[RESET_STATE];
assign testclk_en = state[MEASURE_STATE];
always @(posedge ref_clk_i)
begin
if (state[RESET_STATE] == 1'b1 || state[HOLD_STATE] == 1'b1)
hold_clk <= hold_clk + 1;
else
hold_clk <= 0;
end
always @(posedge ref_clk_i)
begin
if (state[MEASURE_STATE] == 1'b1)
refclk_cnt <= refclk_cnt + 1;
else
refclk_cnt <= 0;
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2005 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t_case_huge_sub3 (/*AUTOARG*/
// Outputs
outr,
// Inputs
clk, index
);
input clk;
input [9:0] index;
output [3:0] outr;
// =============================
/*AUTOREG*/
// Beginning of automatic regs (for this module's undeclared outputs)
reg [3:0] outr;
// End of automatics
// =============================
// Created from perl
//for $i (0..255) { $r=rand(4); printf "\t8'h%02x: begin outr <= outr^index[8:5]^4'h%01x; end\n", $i,
//rand(256); };
// Reset cheating
initial outr = 4'b0;
always @(posedge clk) begin
case (index[7:0])
8'h00: begin outr <= 4'h0; end
8'h01: begin /*No Change*/ end
8'h02: begin outr <= outr^index[8:5]^4'ha; end
8'h03: begin outr <= outr^index[8:5]^4'h4; end
8'h04: begin outr <= outr^index[8:5]^4'hd; end
8'h05: begin outr <= outr^index[8:5]^4'h1; end
8'h06: begin outr <= outr^index[8:5]^4'hf; end
8'h07: begin outr <= outr^index[8:5]^4'he; end
8'h08: begin outr <= outr^index[8:5]^4'h0; end
8'h09: begin outr <= outr^index[8:5]^4'h4; end
8'h0a: begin outr <= outr^index[8:5]^4'h5; end
8'h0b: begin outr <= outr^index[8:5]^4'ha; end
8'h0c: begin outr <= outr^index[8:5]^4'h2; end
8'h0d: begin outr <= outr^index[8:5]^4'hf; end
8'h0e: begin outr <= outr^index[8:5]^4'h5; end
8'h0f: begin outr <= outr^index[8:5]^4'h0; end
8'h10: begin outr <= outr^index[8:5]^4'h3; end
8'h11: begin outr <= outr^index[8:5]^4'hb; end
8'h12: begin outr <= outr^index[8:5]^4'h0; end
8'h13: begin outr <= outr^index[8:5]^4'hf; end
8'h14: begin outr <= outr^index[8:5]^4'h3; end
8'h15: begin outr <= outr^index[8:5]^4'h5; end
8'h16: begin outr <= outr^index[8:5]^4'h7; end
8'h17: begin outr <= outr^index[8:5]^4'h2; end
8'h18: begin outr <= outr^index[8:5]^4'h3; end
8'h19: begin outr <= outr^index[8:5]^4'hb; end
8'h1a: begin outr <= outr^index[8:5]^4'h5; end
8'h1b: begin outr <= outr^index[8:5]^4'h4; end
8'h1c: begin outr <= outr^index[8:5]^4'h2; end
8'h1d: begin outr <= outr^index[8:5]^4'hf; end
8'h1e: begin outr <= outr^index[8:5]^4'h0; end
8'h1f: begin outr <= outr^index[8:5]^4'h4; end
8'h20: begin outr <= outr^index[8:5]^4'h6; end
8'h21: begin outr <= outr^index[8:5]^4'ha; end
8'h22: begin outr <= outr^index[8:5]^4'h6; end
8'h23: begin outr <= outr^index[8:5]^4'hb; end
8'h24: begin outr <= outr^index[8:5]^4'ha; end
8'h25: begin outr <= outr^index[8:5]^4'he; end
8'h26: begin outr <= outr^index[8:5]^4'h7; end
8'h27: begin outr <= outr^index[8:5]^4'ha; end
8'h28: begin outr <= outr^index[8:5]^4'h3; end
8'h29: begin outr <= outr^index[8:5]^4'h8; end
8'h2a: begin outr <= outr^index[8:5]^4'h1; end
8'h2b: begin outr <= outr^index[8:5]^4'h8; end
8'h2c: begin outr <= outr^index[8:5]^4'h4; end
8'h2d: begin outr <= outr^index[8:5]^4'h4; end
8'h2e: begin outr <= outr^index[8:5]^4'he; end
8'h2f: begin outr <= outr^index[8:5]^4'h8; end
8'h30: begin outr <= outr^index[8:5]^4'ha; end
8'h31: begin outr <= outr^index[8:5]^4'h7; end
8'h32: begin outr <= outr^index[8:5]^4'h0; end
8'h33: begin outr <= outr^index[8:5]^4'h3; end
8'h34: begin outr <= outr^index[8:5]^4'h1; end
8'h35: begin outr <= outr^index[8:5]^4'h3; end
8'h36: begin outr <= outr^index[8:5]^4'h4; end
8'h37: begin outr <= outr^index[8:5]^4'h6; end
8'h38: begin outr <= outr^index[8:5]^4'h4; end
8'h39: begin outr <= outr^index[8:5]^4'hb; end
8'h3a: begin outr <= outr^index[8:5]^4'h7; end
8'h3b: begin outr <= outr^index[8:5]^4'h1; end
8'h3c: begin outr <= outr^index[8:5]^4'h2; end
8'h3d: begin outr <= outr^index[8:5]^4'h0; end
8'h3e: begin outr <= outr^index[8:5]^4'h2; end
8'h3f: begin outr <= outr^index[8:5]^4'ha; end
8'h40: begin outr <= outr^index[8:5]^4'h7; end
8'h41: begin outr <= outr^index[8:5]^4'h5; end
8'h42: begin outr <= outr^index[8:5]^4'h5; end
8'h43: begin outr <= outr^index[8:5]^4'h4; end
8'h44: begin outr <= outr^index[8:5]^4'h8; end
8'h45: begin outr <= outr^index[8:5]^4'h5; end
8'h46: begin outr <= outr^index[8:5]^4'hf; end
8'h47: begin outr <= outr^index[8:5]^4'h6; end
8'h48: begin outr <= outr^index[8:5]^4'h7; end
8'h49: begin outr <= outr^index[8:5]^4'h4; end
8'h4a: begin outr <= outr^index[8:5]^4'ha; end
8'h4b: begin outr <= outr^index[8:5]^4'hd; end
8'h4c: begin outr <= outr^index[8:5]^4'hb; end
8'h4d: begin outr <= outr^index[8:5]^4'hf; end
8'h4e: begin outr <= outr^index[8:5]^4'hd; end
8'h4f: begin outr <= outr^index[8:5]^4'h7; end
8'h50: begin outr <= outr^index[8:5]^4'h9; end
8'h51: begin outr <= outr^index[8:5]^4'ha; end
8'h52: begin outr <= outr^index[8:5]^4'hf; end
8'h53: begin outr <= outr^index[8:5]^4'h3; end
8'h54: begin outr <= outr^index[8:5]^4'h1; end
8'h55: begin outr <= outr^index[8:5]^4'h0; end
8'h56: begin outr <= outr^index[8:5]^4'h2; end
8'h57: begin outr <= outr^index[8:5]^4'h9; end
8'h58: begin outr <= outr^index[8:5]^4'h2; end
8'h59: begin outr <= outr^index[8:5]^4'h4; end
8'h5a: begin outr <= outr^index[8:5]^4'hc; end
8'h5b: begin outr <= outr^index[8:5]^4'hd; end
8'h5c: begin outr <= outr^index[8:5]^4'h3; end
8'h5d: begin outr <= outr^index[8:5]^4'hb; end
8'h5e: begin outr <= outr^index[8:5]^4'hd; end
8'h5f: begin outr <= outr^index[8:5]^4'h7; end
8'h60: begin outr <= outr^index[8:5]^4'h7; end
8'h61: begin outr <= outr^index[8:5]^4'h3; end
8'h62: begin outr <= outr^index[8:5]^4'h3; end
8'h63: begin outr <= outr^index[8:5]^4'hb; end
8'h64: begin outr <= outr^index[8:5]^4'h9; end
8'h65: begin outr <= outr^index[8:5]^4'h4; end
8'h66: begin outr <= outr^index[8:5]^4'h3; end
8'h67: begin outr <= outr^index[8:5]^4'h6; end
8'h68: begin outr <= outr^index[8:5]^4'h7; end
8'h69: begin outr <= outr^index[8:5]^4'h7; end
8'h6a: begin outr <= outr^index[8:5]^4'hf; end
8'h6b: begin outr <= outr^index[8:5]^4'h6; end
8'h6c: begin outr <= outr^index[8:5]^4'h8; end
8'h6d: begin outr <= outr^index[8:5]^4'he; end
8'h6e: begin outr <= outr^index[8:5]^4'h4; end
8'h6f: begin outr <= outr^index[8:5]^4'h6; end
8'h70: begin outr <= outr^index[8:5]^4'hc; end
8'h71: begin outr <= outr^index[8:5]^4'h9; end
8'h72: begin outr <= outr^index[8:5]^4'h5; end
8'h73: begin outr <= outr^index[8:5]^4'ha; end
8'h74: begin outr <= outr^index[8:5]^4'h7; end
8'h75: begin outr <= outr^index[8:5]^4'h0; end
8'h76: begin outr <= outr^index[8:5]^4'h1; end
8'h77: begin outr <= outr^index[8:5]^4'he; end
8'h78: begin outr <= outr^index[8:5]^4'ha; end
8'h79: begin outr <= outr^index[8:5]^4'h7; end
8'h7a: begin outr <= outr^index[8:5]^4'hf; end
8'h7b: begin outr <= outr^index[8:5]^4'he; end
8'h7c: begin outr <= outr^index[8:5]^4'h6; end
8'h7d: begin outr <= outr^index[8:5]^4'hc; end
8'h7e: begin outr <= outr^index[8:5]^4'hc; end
8'h7f: begin outr <= outr^index[8:5]^4'h0; end
8'h80: begin outr <= outr^index[8:5]^4'h0; end
8'h81: begin outr <= outr^index[8:5]^4'hd; end
8'h82: begin outr <= outr^index[8:5]^4'hb; end
8'h83: begin outr <= outr^index[8:5]^4'hc; end
8'h84: begin outr <= outr^index[8:5]^4'h2; end
8'h85: begin outr <= outr^index[8:5]^4'h8; end
8'h86: begin outr <= outr^index[8:5]^4'h3; end
8'h87: begin outr <= outr^index[8:5]^4'ha; end
8'h88: begin outr <= outr^index[8:5]^4'he; end
8'h89: begin outr <= outr^index[8:5]^4'h9; end
8'h8a: begin outr <= outr^index[8:5]^4'h1; end
8'h8b: begin outr <= outr^index[8:5]^4'h1; end
8'h8c: begin outr <= outr^index[8:5]^4'hc; end
8'h8d: begin outr <= outr^index[8:5]^4'h2; end
8'h8e: begin outr <= outr^index[8:5]^4'h2; end
8'h8f: begin outr <= outr^index[8:5]^4'hd; end
8'h90: begin outr <= outr^index[8:5]^4'h0; end
8'h91: begin outr <= outr^index[8:5]^4'h6; end
8'h92: begin outr <= outr^index[8:5]^4'h7; end
8'h93: begin outr <= outr^index[8:5]^4'hc; end
8'h94: begin outr <= outr^index[8:5]^4'hb; end
8'h95: begin outr <= outr^index[8:5]^4'h3; end
8'h96: begin outr <= outr^index[8:5]^4'h0; end
8'h97: begin outr <= outr^index[8:5]^4'hc; end
8'h98: begin outr <= outr^index[8:5]^4'hc; end
8'h99: begin outr <= outr^index[8:5]^4'hb; end
8'h9a: begin outr <= outr^index[8:5]^4'h6; end
8'h9b: begin outr <= outr^index[8:5]^4'h5; end
8'h9c: begin outr <= outr^index[8:5]^4'h5; end
8'h9d: begin outr <= outr^index[8:5]^4'h4; end
8'h9e: begin outr <= outr^index[8:5]^4'h7; end
8'h9f: begin outr <= outr^index[8:5]^4'he; end
8'ha0: begin outr <= outr^index[8:5]^4'hc; end
8'ha1: begin outr <= outr^index[8:5]^4'hc; end
8'ha2: begin outr <= outr^index[8:5]^4'h0; end
8'ha3: begin outr <= outr^index[8:5]^4'h1; end
8'ha4: begin outr <= outr^index[8:5]^4'hd; end
8'ha5: begin outr <= outr^index[8:5]^4'h3; end
8'ha6: begin outr <= outr^index[8:5]^4'hc; end
8'ha7: begin outr <= outr^index[8:5]^4'h2; end
8'ha8: begin outr <= outr^index[8:5]^4'h3; end
8'ha9: begin outr <= outr^index[8:5]^4'hd; end
8'haa: begin outr <= outr^index[8:5]^4'h5; end
8'hab: begin outr <= outr^index[8:5]^4'hb; end
8'hac: begin outr <= outr^index[8:5]^4'he; end
8'had: begin outr <= outr^index[8:5]^4'h0; end
8'hae: begin outr <= outr^index[8:5]^4'hf; end
8'haf: begin outr <= outr^index[8:5]^4'h9; end
8'hb0: begin outr <= outr^index[8:5]^4'hf; end
8'hb1: begin outr <= outr^index[8:5]^4'h7; end
8'hb2: begin outr <= outr^index[8:5]^4'h9; end
8'hb3: begin outr <= outr^index[8:5]^4'hf; end
8'hb4: begin outr <= outr^index[8:5]^4'he; end
8'hb5: begin outr <= outr^index[8:5]^4'h3; end
8'hb6: begin outr <= outr^index[8:5]^4'he; end
8'hb7: begin outr <= outr^index[8:5]^4'h8; end
8'hb8: begin outr <= outr^index[8:5]^4'hf; end
8'hb9: begin outr <= outr^index[8:5]^4'hd; end
8'hba: begin outr <= outr^index[8:5]^4'h3; end
8'hbb: begin outr <= outr^index[8:5]^4'h5; end
8'hbc: begin outr <= outr^index[8:5]^4'hd; end
8'hbd: begin outr <= outr^index[8:5]^4'ha; end
8'hbe: begin outr <= outr^index[8:5]^4'h7; end
8'hbf: begin outr <= outr^index[8:5]^4'he; end
8'hc0: begin outr <= outr^index[8:5]^4'h2; end
8'hc1: begin outr <= outr^index[8:5]^4'he; end
8'hc2: begin outr <= outr^index[8:5]^4'h9; end
8'hc3: begin outr <= outr^index[8:5]^4'hb; end
8'hc4: begin outr <= outr^index[8:5]^4'h0; end
8'hc5: begin outr <= outr^index[8:5]^4'h5; end
8'hc6: begin outr <= outr^index[8:5]^4'h9; end
8'hc7: begin outr <= outr^index[8:5]^4'h6; end
8'hc8: begin outr <= outr^index[8:5]^4'ha; end
8'hc9: begin outr <= outr^index[8:5]^4'hf; end
8'hca: begin outr <= outr^index[8:5]^4'h3; end
8'hcb: begin outr <= outr^index[8:5]^4'hb; end
8'hcc: begin outr <= outr^index[8:5]^4'he; end
8'hcd: begin outr <= outr^index[8:5]^4'h2; end
8'hce: begin outr <= outr^index[8:5]^4'h5; end
8'hcf: begin outr <= outr^index[8:5]^4'hf; end
8'hd0: begin outr <= outr^index[8:5]^4'h2; end
8'hd1: begin outr <= outr^index[8:5]^4'h9; end
8'hd2: begin outr <= outr^index[8:5]^4'hb; end
8'hd3: begin outr <= outr^index[8:5]^4'h8; end
8'hd4: begin outr <= outr^index[8:5]^4'h0; end
8'hd5: begin outr <= outr^index[8:5]^4'h2; end
8'hd6: begin outr <= outr^index[8:5]^4'hb; end
8'hd7: begin outr <= outr^index[8:5]^4'h2; end
8'hd8: begin outr <= outr^index[8:5]^4'ha; end
8'hd9: begin outr <= outr^index[8:5]^4'hf; end
8'hda: begin outr <= outr^index[8:5]^4'h8; end
8'hdb: begin outr <= outr^index[8:5]^4'h4; end
8'hdc: begin outr <= outr^index[8:5]^4'he; end
8'hdd: begin outr <= outr^index[8:5]^4'h6; end
8'hde: begin outr <= outr^index[8:5]^4'h9; end
8'hdf: begin outr <= outr^index[8:5]^4'h9; end
8'he0: begin outr <= outr^index[8:5]^4'h7; end
8'he1: begin outr <= outr^index[8:5]^4'h0; end
8'he2: begin outr <= outr^index[8:5]^4'h9; end
8'he3: begin outr <= outr^index[8:5]^4'h3; end
8'he4: begin outr <= outr^index[8:5]^4'h2; end
8'he5: begin outr <= outr^index[8:5]^4'h4; end
8'he6: begin outr <= outr^index[8:5]^4'h5; end
8'he7: begin outr <= outr^index[8:5]^4'h5; end
8'he8: begin outr <= outr^index[8:5]^4'hf; end
8'he9: begin outr <= outr^index[8:5]^4'ha; end
8'hea: begin outr <= outr^index[8:5]^4'hc; end
8'heb: begin outr <= outr^index[8:5]^4'hd; end
8'hec: begin outr <= outr^index[8:5]^4'h1; end
8'hed: begin outr <= outr^index[8:5]^4'h5; end
8'hee: begin outr <= outr^index[8:5]^4'h9; end
8'hef: begin outr <= outr^index[8:5]^4'h0; end
8'hf0: begin outr <= outr^index[8:5]^4'hd; end
8'hf1: begin outr <= outr^index[8:5]^4'hf; end
8'hf2: begin outr <= outr^index[8:5]^4'h4; end
8'hf3: begin outr <= outr^index[8:5]^4'ha; end
8'hf4: begin outr <= outr^index[8:5]^4'h8; end
8'hf5: begin outr <= outr^index[8:5]^4'he; end
8'hf6: begin outr <= outr^index[8:5]^4'he; end
8'hf7: begin outr <= outr^index[8:5]^4'h1; end
8'hf8: begin outr <= outr^index[8:5]^4'h6; end
8'hf9: begin outr <= outr^index[8:5]^4'h0; end
8'hfa: begin outr <= outr^index[8:5]^4'h5; end
8'hfb: begin outr <= outr^index[8:5]^4'h1; end
8'hfc: begin outr <= outr^index[8:5]^4'h8; end
8'hfd: begin outr <= outr^index[8:5]^4'h6; end
8'hfe: begin outr <= outr^index[8:5]^4'h1; end
default: begin outr <= outr^index[8:5]^4'h6; end
endcase
end
endmodule
|
/* ltcminer_icarus.v copyright kramble 2013
* Based on https://github.com/teknohog/Open-Source-FPGA-Bitcoin-Miner/tree/master/projects/Xilinx_cluster_cgminer
* Hub code for a cluster of miners using async links
* by teknohog
*/
`include "../source/sha-256-functions.v"
`include "../source/sha256_transform.v"
module ltcminer_icarus (osc_clk, RxD, TxD, led, extminer_rxd, extminer_txd, dip, TMP_SCL, TMP_SDA, TMP_ALERT);
function integer clog2; // Courtesy of razorfishsl, replaces $clog2()
input integer value;
begin
value = value-1;
for (clog2=0; value>0; clog2=clog2+1)
value = value>>1;
end
endfunction
// NB SPEED_MHZ resolution is 5MHz steps to keep pll divide ratio sensible. Change the divider in xilinx_pll.v if you
// want other steps (1MHz is not sensible as it requires divide 100 which is not in the allowed range 1..32 for DCM_SP)
// New dyn_pll has 1MHz resolution and can be changed by sending a specific getwork packet (uses top bytes of target)
`define USE_DYN_PLL // Enable new dyn_pll
`ifdef SPEED_MHZ
parameter SPEED_MHZ = `SPEED_MHZ;
`else
parameter SPEED_MHZ = 25; // Default to slow, use dynamic config to ramp up in realtime
`endif
`ifdef SPEED_LIMIT
parameter SPEED_LIMIT = `SPEED_LIMIT; // Fastest speed accepted by dyn_pll config
`else
parameter SPEED_LIMIT = 100; // Deliberately conservative, increase at own risk
`endif
`ifdef SPEED_MIN
parameter SPEED_MIN = `SPEED_MIN; // Slowest speed accepted by dyn_pll config (CARE can lock up if too low)
`else
parameter SPEED_MIN = 10;
`endif
`ifdef SERIAL_CLK
parameter comm_clk_frequency = `SERIAL_CLK;
`else
parameter comm_clk_frequency = 12_500_000; // 100MHz divide 8
`endif
`ifdef BAUD_RATE
parameter BAUD_RATE = `BAUD_RATE;
`else
parameter BAUD_RATE = 115_200;
`endif
// kramble - nonce distribution is crude using top 4 bits of nonce so max LOCAL_MINERS = 8
// teknohog's was more sophisticated, but requires modification of hashcore.v
// Miners on the same FPGA with this hub
`ifdef LOCAL_MINERS
parameter LOCAL_MINERS = `LOCAL_MINERS;
`else
parameter LOCAL_MINERS = 2; // One to four cores (configures ADDRBITS automatically)
`endif
`ifdef ADDRBITS
parameter ADDRBITS = `ADDRBITS; // Override for simulation or a quick ISE build (eg one 10 bit core)
`else
parameter ADDRBITS = 12 - clog2(LOCAL_MINERS); // Automatically selects largest RAM that will fit LX150
`endif
// kramble - nonce distribution only works for a single external port
`ifdef EXT_PORTS
parameter EXT_PORTS = `EXT_PORTS;
`else
parameter EXT_PORTS = 1;
`endif
localparam SLAVES = LOCAL_MINERS + EXT_PORTS;
input osc_clk;
wire hash_clk, uart_clk, pbkdf_clk;
`ifdef USE_DYN_PLL
wire first_dcm_locked, dcm_progclk, dcm_progdata, dcm_progen, dcm_reset, dcm_progdone, dcm_locked;
wire [2:1] dcm_status;
`endif
`ifndef SIM
`ifdef USE_DYN_PLL
dyn_pll # (.SPEED_MHZ(SPEED_MHZ)) dyn_pll_blk
(osc_clk,
pbkdf_clk,
hash_clk,
uart_clk,
first_dcm_locked,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_progdone,
dcm_locked,
dcm_status);
`else
main_pll # (.SPEED_MHZ(SPEED_MHZ)) pll_blk (.CLKIN_IN(osc_clk), .CLKFX_OUT(hash_clk), .CLKDV_OUT(uart_clk));
assign pbkdf_clk = uart_clk;
`endif
`else
assign hash_clk = osc_clk;
assign uart_clk = osc_clk;
assign pbkdf_clk = osc_clk;
`ifdef USE_DYN_PLL
assign first_dcm_locked = 1'b1;
assign dcm_progdone = 1'b1;
assign dcm_locked = 1'b1;
assign dcm_status = 0;
`endif
`endif
`ifdef USE_DYN_PLL
reg [7:0] dyn_pll_speed = SPEED_MHZ;
reg dyn_pll_start = 0;
parameter OSC_MHZ = 100; // Clock oscillator (used for divider ratio)
dyn_pll_ctrl # (.SPEED_MHZ(SPEED_MHZ), .SPEED_LIMIT(SPEED_LIMIT), .SPEED_MIN(SPEED_MIN), .OSC_MHZ(OSC_MHZ)) dyn_pll_ctrl_blk
(uart_clk, // NB uses uart_clk as its just osc/8 and should always be valid
first_dcm_locked, // ... but we check it anyway
dyn_pll_speed,
dyn_pll_start,
dcm_progclk,
dcm_progdata,
dcm_progen,
dcm_reset,
dcm_locked,
dcm_status);
`endif
input TMP_SCL, TMP_SDA, TMP_ALERT; // Unused but set to PULLUP so as to avoid turning on the HOT LED
// TODO implement I2C protocol to talk to temperature sensor chip (TMP101?)
// and drive FAN speed control output.
input [3:0]dip;
wire reset, nonce_chip;
assign reset = dip[0]; // Not used
assign nonce_chip = dip[1]; // Distinguishes between the two Icarus FPGA's
// Work distribution is simply copying to all miners, so no logic
// needed there, simply copy the RxD.
input RxD;
output TxD;
// Results from the input buffers (in serial_hub.v) of each slave
wire [SLAVES*32-1:0] slave_nonces;
wire [SLAVES*32-1:0] slave_debug_sr;
wire [SLAVES-1:0] new_nonces;
// Using the same transmission code as individual miners from serial.v
wire serial_send;
wire serial_busy;
wire [31:0] golden_nonce;
serial_transmit #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) sertx (.clk(uart_clk), .TxD(TxD), .send(serial_send), .busy(serial_busy), .word(golden_nonce));
hub_core #(.SLAVES(SLAVES)) hc (.uart_clk(uart_clk), .new_nonces(new_nonces), .golden_nonce(golden_nonce), .serial_send(serial_send), .serial_busy(serial_busy), .slave_nonces(slave_nonces));
// Common workdata input for local miners
wire [255:0] data1, data2;
wire [127:0] data3;
wire [31:0] target;
reg [31:0] targetreg = 32'h000007ff; // Start at sane value (overwritten by serial_receive)
wire rx_done; // Signals hashcore to reset the nonce
// NB in my implementation, it loads the nonce from data3 which should be fine as
// this should be zero, but also supports testing using non-zero nonces.
// Synchronise across clock domains from uart_clk to hash_clk
// This probably looks amateurish (mea maxima culpa, novice verilogger at work), but should be OK
reg rx_done_toggle = 1'b0; // uart_clk domain
always @ (posedge uart_clk)
rx_done_toggle <= rx_done_toggle ^ rx_done;
reg rx_done_toggle_d1 = 1'b0; // hash_clk domain
reg rx_done_toggle_d2 = 1'b0;
reg rx_done_toggle_d3 = 1'b0;
wire loadnonce;
assign loadnonce = rx_done_toggle_d3 ^ rx_done_toggle_d2;
always @ (posedge pbkdf_clk)
begin
rx_done_toggle_d1 <= rx_done_toggle;
rx_done_toggle_d2 <= rx_done_toggle_d1;
rx_done_toggle_d3 <= rx_done_toggle_d2;
if (loadnonce)
targetreg <= target;
end
// End of clock domain sync
wire [31:0] mod_target;
`ifdef USE_DYN_PLL
// Top byte of target is clock multiplier, 2nd byte is validation (one's complement of clock multiplier)
// These bytes are always zero in normal getwork, so we now hard code in mod_target and use them to set clock speed.
// NB The pll controller is in uart_clk domain so use serial_receive signals directly
// wire [7:0]invtarg; // Just checking the syntax in simulator, DELETE
// assign invtarg = ~target[24:16];
always @ (posedge uart_clk)
begin
dyn_pll_start <= 0;
// A sanity check to reduce the risk of speed being set to garbage
// Top byte of target is speed, second byte MUST be its inverse, and neither must be zero (which also rules out all ones)
if (rx_done && target[31:24] != dyn_pll_speed && target[31:24] != 0 && target[23:16] != 0 && target[31:24] == ~target[23:16])
// if (rx_done && target[31:24] != dyn_pll_speed && target[31:24] != 0) // Simpler version for DEBUG, does no verification
begin
dyn_pll_speed <= target[31:24];
dyn_pll_start <= 1;
end
end
assign mod_target = { 16'd0, targetreg[15:0] }; // Ignore top two bytes
`else
// Its better to always hard-wire the 16 MSB to zero ... if comms noise sets these bits it completely de-syncs,
// generating a continuous stream of golden_nonces overwhelming the python driver which can't then reset the target.
// assign mod_target = targetreg; // Original 32 bit target
assign mod_target = { 16'd0, targetreg[15:0] }; // Ignore top two bytes
`endif
serial_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) serrx (.clk(uart_clk), .RxD(RxD), .data1(data1),
.data2(data2), .data3(data3), .target(target), .rx_done(rx_done));
parameter SBITS = 8; // Shift data path width
// Local miners now directly connected
generate
genvar i;
for (i = 0; i < LOCAL_MINERS; i = i + 1)
// begin: for_local_miners ... too verbose, so...
begin: miners
wire [31:0] nonce_out; // Not used
wire [2:0] nonce_core = i;
wire gn_match;
wire salsa_busy, salsa_result, salsa_reset, salsa_start, salsa_shift;
wire [SBITS-1:0] salsa_din;
wire [SBITS-1:0] salsa_dout;
wire [3:0] dummy; // So we can ignore top 4 bits of slave_debug_sr
// Currently one pbkdfengine per salsaengine - TODO share the pbkdfengine for several salsaengines
pbkdfengine #(.SBITS(SBITS)) P
(.hash_clk(hash_clk), .pbkdf_clk(pbkdf_clk), .data1(data1), .data2(data2), .data3(data3), .target(mod_target),
.nonce_msb({nonce_chip, nonce_core}), .nonce_out(nonce_out), .golden_nonce_out(slave_nonces[i*32+31:i*32]),
.golden_nonce_match(gn_match), .loadnonce(loadnonce),
.salsa_din(salsa_din), .salsa_dout(salsa_dout), .salsa_busy(salsa_busy), .salsa_result(salsa_result),
.salsa_reset(salsa_reset), .salsa_start(salsa_start), .salsa_shift(salsa_shift));
salsaengine #(.ADDRBITS(ADDRBITS), .SBITS(SBITS)) S
(.hash_clk(hash_clk), .reset(salsa_reset), .din(salsa_din), .dout(salsa_dout),
.shift(salsa_shift), .start(salsa_start), .busy(salsa_busy), .result(salsa_result) );
// Synchronise across clock domains from pbkdf_clk to uart_clk for: assign new_nonces[i] = gn_match;
reg gn_match_toggle = 1'b0; // hash_clk domain
always @ (posedge pbkdf_clk)
gn_match_toggle <= gn_match_toggle ^ gn_match;
reg gn_match_toggle_d1 = 1'b0; // uart_clk domain
reg gn_match_toggle_d2 = 1'b0;
reg gn_match_toggle_d3 = 1'b0;
assign new_nonces[i] = gn_match_toggle_d3 ^ gn_match_toggle_d2;
always @ (posedge uart_clk)
begin
gn_match_toggle_d1 <= gn_match_toggle;
gn_match_toggle_d2 <= gn_match_toggle_d1;
gn_match_toggle_d3 <= gn_match_toggle_d2;
end
// End of clock domain sync
end // for
endgenerate
// External miner ports, results appended to the same
// slave_nonces/new_nonces as local ones
output [EXT_PORTS-1:0] extminer_txd;
input [EXT_PORTS-1:0] extminer_rxd;
// wire [EXT_PORTS-1:0] extminer_rxd_debug = 1'b1; // DISABLE INPUT
assign extminer_txd = {EXT_PORTS{RxD}};
generate
genvar j;
for (j = LOCAL_MINERS; j < SLAVES; j = j + 1)
// begin: for_ports ... too verbose, so ...
begin: ports
slave_receive #(.comm_clk_frequency(comm_clk_frequency), .baud_rate(BAUD_RATE)) slrx (.clk(uart_clk), .RxD(extminer_rxd[j-LOCAL_MINERS]), .nonce(slave_nonces[j*32+31:j*32]), .new_nonce(new_nonces[j]));
end
endgenerate
output [3:0] led;
assign led[1] = ~RxD;
// assign led[2] = ~TxD;
// assign led[3] = ~ (TMP_SCL | TMP_SDA | TMP_ALERT); // IDLE LED - held low (the TMP pins are PULLUP, this is a fudge to
// avoid warning about unused inputs)
assign led[3] = ~first_dcm_locked | ~dcm_locked | dcm_status[2] | ~(TMP_SCL | TMP_SDA | TMP_ALERT); // IDLE LED now dcm status
`define FLASHCLOCK // Gives some feedback as the the actual clock speed
`ifdef FLASHCLOCK
reg [26:0] hash_count = 0;
reg [3:0] sync_hash_count = 0;
always @ (posedge uart_clk)
if (rx_done)
sync_hash_count[0] <= ~sync_hash_count[0];
always @ (posedge hash_clk)
begin
sync_hash_count[3:1] <= sync_hash_count[2:0];
hash_count <= hash_count + 1'b1;
if (sync_hash_count[3] != sync_hash_count[2])
hash_count <= 0;
end
assign led[2] = hash_count[26];
`else
assign led[2] = ~TxD;
`endif
// Light up only from locally found nonces, not ext_port results
pwm_fade pf (.clk(uart_clk), .trigger(|new_nonces[LOCAL_MINERS-1:0]), .drive(led[0]));
endmodule
|
module test;
logic reset_li, clk, yumi_li;
logic [1:0] req_li, gnt_lo;
bsg_arb_round_robin
#(.width_p(1)) barr2
(.reset_i()
,.clk_i(clk)
,.reqs_i(1'b1)
,.grants_o()
,.yumi_i()
);
bsg_arb_round_robin
#(.width_p(2)) barr
(.reset_i(reset_li)
,.clk_i(clk)
,.reqs_i(req_li)
,.grants_o(gnt_lo)
,.yumi_i(yumi_li)
);
initial begin
$monitor("reset = %b, clk=%b, req_li=%b, gnt_lo=%b, yumi_li=%b, thermo_code=%b",reset_li,clk,req_li,gnt_lo,yumi_li,barr.fi2.thermocode_r);
#10 reset_li = 1;
#10 yumi_li = 0;
#10 req_li = 2'b00;
#10 clk = 1;
#10 reset_li = 0;
#10 clk = 0;
#10 req_li = 2'b01;
#10 clk = 1;
#10 yumi_li = 1;
#10 clk = 1;
#10 yumi_li = 0;
#10 clk = 0;
#10 req_li = 2'b01;
#10 yumi_li = 1;
#10 clk = 1;
#10 clk = 0;
#10 req_li = 2'b10;
#10 yumi_li = 1;
#10 clk = 1;
#10 clk = 0;
#10 req_li = 2'b11;
#10 yumi_li = 1;
#10 clk = 1;
#10 clk = 0;
#10 req_li = 2'b11;
#10 yumi_li = 1;
#10 clk = 1;
#10 clk = 0;
#10 req_li = 2'b11;
#10 yumi_li = 1;
#10 clk = 1;
#10 clk = 0;
#10 req_li = 2'b00;
#10 yumi_li = 0;
#10 clk = 1;
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__NAND4_2_V
`define SKY130_FD_SC_HS__NAND4_2_V
/**
* nand4: 4-input NAND.
*
* Verilog wrapper for nand4 with size of 2 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hs__nand4.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4_2 (
Y ,
A ,
B ,
C ,
D ,
VPWR,
VGND
);
output Y ;
input A ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hs__nand4_2 (
Y,
A,
B,
C,
D
);
output Y;
input A;
input B;
input C;
input D;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
sky130_fd_sc_hs__nand4 base (
.Y(Y),
.A(A),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HS__NAND4_2_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
typedef enum { EN_ZERO,
EN_ONE
} En_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
// Insure that we can declare a type with a function declaration
function enum integer {
EF_TRUE = 1,
EF_FALSE = 0 }
f_enum_inv ( input a);
f_enum_inv = a ? EF_FALSE : EF_TRUE;
endfunction
initial begin
if (f_enum_inv(1) != 0) $stop;
if (f_enum_inv(0) != 1) $stop;
end
En_t a, z;
sub sub (/*AUTOINST*/
// Outputs
.z (z),
// Inputs
.a (a));
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
a <= EN_ZERO;
end
if (cyc==2) begin
a <= EN_ONE;
if (z != EN_ONE) $stop;
end
if (cyc==3) begin
if (z != EN_ZERO) $stop;
end
if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module sub (input En_t a, output En_t z);
always @* z = (a==EN_ONE) ? EN_ZERO : EN_ONE;
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2003 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [39:0] con1,con2, con3;
reg [31:0] w32;
reg [31:0] v32 [2];
// surefire lint_off UDDSCN
reg [200:0] conw3, conw4;
// surefire lint_on UDDSCN
reg [16*8-1:0] con__ascii;
reg [31:0] win;
// Test casting is proper on narrow->wide->narrow conversions
// verilator lint_off WIDTH
wire [49:0] wider = ({18'h0, win} | (1'b1<<32)) - 50'h111;
wire [31:0] wider2 = ({win} | (1'b1<<32)) - 50'd111;
// verilator lint_on WIDTH
wire [31:0] narrow = wider[31:0];
wire [31:0] narrow2 = wider2[31:0];
// surefire lint_off ASWEMB
// surefire lint_off ASWCMB
// surefire lint_off CWECBB
// surefire lint_off CWECSB
// surefire lint_off STMINI
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
if (cyc==1) begin
$write("[%0t] t_const: Running\n", $time);
con1 = 4_0'h1000_0010; // Odd but legal _ in width
con2 = 40'h10_0000_0010;
con3 = con1 + 40'h10_1100_0101;
if (con1[31:0]!== 32'h1000_0010 || con1[39:32]!==0) $stop;
$display("%x %x %x\n", con2, con2[31:0], con2[39:32]);
if (con2[31:0]!== 32'h10 || con2[39:32]!==8'h10) $stop;
if (con3[31:0]!==32'h2100_0111 || con3[39:32]!==8'h10) $stop;
// verilator lint_off WIDTH
con1 = 10'h10 + 40'h80_1100_0131;
// verilator lint_on WIDTH
con2 = 40'h80_0000_0000 + 40'h13_7543_0107;
if (con1[31:0]!== 32'h1100_0141 || con1[39:32]!==8'h80) $stop;
if (con2[31:0]!== 32'h7543_0107 || con2[39:32]!==8'h93) $stop;
// verilator lint_off WIDTH
conw3 = 94'h000a_5010_4020_3030_2040_1050;
// verilator lint_on WIDTH
if (conw3[31:00]!== 32'h2040_1050 ||
conw3[63:32]!== 32'h4020_3030 ||
conw3[95:64]!== 32'h000a_5010 ||
conw3[128:96]!==33'h0) $stop;
$display("%x... %x\n", conw3[15:0], ~| conw3[15:0]);
if ((~| conw3[15:0]) !== 1'h0) $stop;
if ((~& conw3[15:0]) !== 1'h1) $stop;
// verilator lint_off WIDTH
conw4 = 112'h7010_602a_5030_4040_3050_2060_1070;
// verilator lint_on WIDTH
if (conw4[31:00]!== 32'h2060_1070 ||
conw4[63:32]!== 32'h4040_3050 ||
conw4[95:64]!== 32'h602a_5030 ||
conw4[127:96]!==32'h7010) $stop;
// conw4 = 144'h7000_7000_7010_602a_5030_4040_3050_2060_1070;
w32 = 12;
win <= 12;
if ((32'hffff0000 >> w32) != 32'h 000ffff0) $stop;
con__ascii = "abcdefghijklmnop";
if ( con__ascii !== {"abcd","efgh","ijkl","mnop"}) $stop;
con__ascii = "abcdefghijklm";
if ( con__ascii !== {24'h0,"a","bcde","fghi","jklm"}) $stop;
if ( 3'dx !== 3'hx) $stop;
// Wide decimal
if ( 94'd12345678901234567890123456789 != 94'h27e41b3246bec9b16e398115) $stop;
if (-94'sd123456789012345678901234567 != 94'h3f99e1020ea70d57d360b479) $stop;
// Increments
w32 = 12; w32++; if (w32 != 13) $stop;
w32 = 12; ++w32; if (w32 != 13) $stop;
w32 = 12; w32--; if (w32 != 11) $stop;
w32 = 12; --w32; if (w32 != 11) $stop;
w32 = 12; w32 += 2; if (w32 != 14) $stop;
w32 = 12; w32 -= 2; if (w32 != 10) $stop;
w32 = 12; w32 *= 2; if (w32 != 24) $stop;
w32 = 12; w32 /= 2; if (w32 != 6) $stop;
w32 = 12; w32 &= 6; if (w32 != 4) $stop;
w32 = 12; w32 |= 15; if (w32 != 15) $stop;
w32 = 12; w32 ^= 15; if (w32 != 3) $stop;
w32 = 12; w32 >>= 1; if (w32 != 6) $stop;
w32 = 12; w32 >>>= 1; if (w32 != 6) $stop;
w32 = 12; w32 <<= 1; if (w32 != 24) $stop;
w32 = 12; w32 %= 5; if (w32 != 2) $stop;
// Increments
v32[1] = 12; v32[1]++; if (v32[1] != 13) $stop;
v32[1] = 12; ++v32[1]; if (v32[1] != 13) $stop;
v32[1] = 12; v32[1]--; if (v32[1] != 11) $stop;
v32[1] = 12; --v32[1]; if (v32[1] != 11) $stop;
v32[1] = 12; v32[1] += 2; if (v32[1] != 14) $stop;
v32[1] = 12; v32[1] -= 2; if (v32[1] != 10) $stop;
v32[1] = 12; v32[1] *= 2; if (v32[1] != 24) $stop;
v32[1] = 12; v32[1] /= 2; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] &= 6; if (v32[1] != 4) $stop;
v32[1] = 12; v32[1] |= 15; if (v32[1] != 15) $stop;
v32[1] = 12; v32[1] ^= 15; if (v32[1] != 3) $stop;
v32[1] = 12; v32[1] >>= 1; if (v32[1] != 6) $stop;
v32[1] = 12; v32[1] <<= 1; if (v32[1] != 24) $stop;
end
if (cyc==2) begin
win <= 32'h123123;
if (narrow !== 32'hfffffefb) $stop;
if (narrow2 !== 32'hffffff9d) $stop;
end
if (cyc==3) begin
if (narrow !== 32'h00123012) $stop;
if (narrow2 !== 32'h001230b4) $stop;
end
if (cyc==10) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_int_mult32s_s5 (
enable,
clock,
dataa,
datab,
result);
parameter INPUT1_WIDTH = 32;
parameter INPUT2_WIDTH = 32;
localparam INPUT1_WIDTH_WITH_SIGN = INPUT1_WIDTH < 32 ? INPUT1_WIDTH + 1 : INPUT1_WIDTH;
localparam INPUT2_WIDTH_WITH_SIGN = INPUT2_WIDTH < 32 ? INPUT2_WIDTH + 1 : INPUT2_WIDTH;
input enable;
input clock;
input [INPUT1_WIDTH_WITH_SIGN - 1 : 0] dataa;
input [INPUT2_WIDTH_WITH_SIGN - 1 : 0] datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) output reg [31:0] result;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT1_WIDTH_WITH_SIGN - 1 : 0] reg_dataa2;
(* altera_attribute = "-name auto_shift_register_recognition OFF" *) reg [INPUT2_WIDTH_WITH_SIGN - 1 : 0] reg_datab2;
generate
if(INPUT1_WIDTH>=19 && INPUT1_WIDTH<=27 && INPUT2_WIDTH>=19 && INPUT2_WIDTH<=27)
begin
// Use a special WYSIWYG for the 27x27 multiplier mode
always@(posedge clock)
begin
if (enable)
begin
reg_dataa <= dataa;
reg_datab <= datab;
end
end
wire [53:0] mul_result;
wire [26:0] inp_a;
wire [26:0] inp_b;
assign inp_a = reg_dataa;
assign inp_b = reg_datab;
sv_mult27 the_multiplier(clock,enable,inp_a,inp_b,mul_result);
always@(*)
begin
result <= mul_result;
end
end
else
begin
// Default LPM_MULT inference
always@(posedge clock)
begin
if (enable)
begin
result <= reg_dataa2 * reg_datab2;
reg_dataa <= dataa;
reg_datab <= datab;
reg_dataa2 <= reg_dataa;
reg_datab2 <= reg_datab;
end
end
end
endgenerate
endmodule
|
// megafunction wizard: %FIFO%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: dcfifo
// ============================================================
// File Name: asyn_256_134.v
// Megafunction Name(s):
// dcfifo
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 15.0.0 Build 145 04/22/2015 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2015 Altera Corporation. All rights reserved.
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, the Altera Quartus II License Agreement,
//the Altera MegaCore Function License Agreement, or other
//applicable license agreement, including, without limitation,
//that your use is for the sole purpose of programming logic
//devices manufactured by Altera and sold by Altera or its
//authorized distributors. Please refer to the applicable
//agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module asyn_256_134 (
aclr,
data,
rdclk,
rdreq,
wrclk,
wrreq,
q,
wrusedw);
input aclr;
input [133:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
output [133:0] q;
output [7:0] wrusedw;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 aclr;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [133:0] sub_wire0;
wire [7:0] sub_wire1;
wire [133:0] q = sub_wire0[133:0];
wire [7:0] wrusedw = sub_wire1[7:0];
dcfifo dcfifo_component (
.aclr (aclr),
.data (data),
.rdclk (rdclk),
.rdreq (rdreq),
.wrclk (wrclk),
.wrreq (wrreq),
.q (sub_wire0),
.wrusedw (sub_wire1),
.rdempty (),
.rdfull (),
.rdusedw (),
.wrempty (),
.wrfull ());
defparam
dcfifo_component.intended_device_family = "Stratix V",
dcfifo_component.lpm_numwords = 256,
dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
dcfifo_component.lpm_width = 134,
dcfifo_component.lpm_widthu = 8,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.rdsync_delaypipe = 5,
dcfifo_component.read_aclr_synch = "OFF",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON",
dcfifo_component.write_aclr_synch = "OFF",
dcfifo_component.wrsync_delaypipe = 5;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
// Retrieval info: PRIVATE: Depth NUMERIC "256"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
// Retrieval info: PRIVATE: Width NUMERIC "134"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
// Retrieval info: PRIVATE: output_width NUMERIC "134"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
// Retrieval info: PRIVATE: wsFull NUMERIC "0"
// Retrieval info: PRIVATE: wsUsedW NUMERIC "1"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Stratix V"
// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "134"
// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: CONSTANT: READ_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF"
// Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND "aclr"
// Retrieval info: USED_PORT: data 0 0 134 0 INPUT NODEFVAL "data[133..0]"
// Retrieval info: USED_PORT: q 0 0 134 0 OUTPUT NODEFVAL "q[133..0]"
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL "rdclk"
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL "wrclk"
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL "wrusedw[7..0]"
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: CONNECT: @data 0 0 134 0 data 0 0 134 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: q 0 0 134 0 @q 0 0 134 0
// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL asyn_256_134_bb.v FALSE
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
`define SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
/**
* lpflow_clkbufkapwr: Clock tree buffer on keep-alive power rail.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__lpflow_clkbufkapwr (
//# {{data|Data Signals}}
input A,
output X
);
// Voltage supply signals
supply1 KAPWR;
supply1 VPWR ;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__LPFLOW_CLKBUFKAPWR_SYMBOL_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
`define zednkw 200
module BreadAddrDP (zfghtn, cjtmau, vipmpg, knquim, kqxkkr);
input zfghtn;
input [4:0] cjtmau;
input vipmpg;
input [7:0] knquim;
input [7:0] kqxkkr;
reg covfok;
reg [15:0] xwieqw;
reg [2:0] ofnjjt;
reg [37:0] hdsejo[0:1];
reg wxxzgd, tceppr, ratebp, fjizkr, iwwrnq;
reg vrqrih, ryyjxy;
reg fgzsox;
wire xdjikl = ~wxxzgd & ~tceppr & ~ratebp & fjizkr;
wire iytyol = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & ~xwieqw[10];
wire dywooz = ~wxxzgd & ~tceppr & ratebp & ~fjizkr & xwieqw[10];
wire qnpfus = ~wxxzgd & ~tceppr & ratebp & fjizkr;
wire fqlkrg = ~wxxzgd & tceppr & ~ratebp & ~fjizkr;
wire ktsveg = hdsejo[0][6] | (hdsejo[0][37:34] == 4'h1);
wire smxixw = vrqrih | (ryyjxy & ktsveg);
wire [7:0] grvsrs, kyxrft, uxhkka;
wire [7:0] eianuv = 8'h01 << ofnjjt;
wire [7:0] jvpnxn = {8{qnpfus}} & eianuv;
wire [7:0] zlnzlj = {8{fqlkrg}} & eianuv;
wire [7:0] nahzat = {8{iytyol}} & eianuv;
genvar i;
generate
for (i=0;i<8;i=i+1)
begin : dnlpyw
DecCountReg4 bzpytc (zfghtn, fgzsox, zlnzlj[i],
knquim[3:0], covfok, grvsrs[i]);
DecCountReg4 oghukp (zfghtn, fgzsox, zlnzlj[i],
knquim[7:4], covfok, kyxrft[i]);
DecCountReg4 ttvjoo (zfghtn, fgzsox, nahzat[i],
kqxkkr[3:0], covfok, uxhkka[i]);
end
endgenerate
endmodule
module DecCountReg4 (clk, fgzsox, fckiyr, uezcjy, covfok, juvlsh);
input clk, fgzsox, fckiyr, covfok;
input [3:0] uezcjy;
output juvlsh;
task Xinit;
begin
`ifdef TEST_HARNESS
khgawe = 1'b0;
`endif
end
endtask
function X;
input vrdejo;
begin
`ifdef TEST_HARNESS
if ((vrdejo & ~vrdejo) !== 1'h0) khgawe = 1'b1;
`endif
X = vrdejo;
end
endfunction
task Xcheck;
input vzpwwy;
begin
end
endtask
reg [3:0] udbvtl;
assign juvlsh = |udbvtl;
wire [3:0] mppedc = {4{fgzsox}} & (fckiyr ? uezcjy : (udbvtl - 4'h1));
wire qqibou = ((juvlsh | fckiyr) & covfok) | ~fgzsox;
always @(posedge clk)
begin
Xinit;
if (X(qqibou))
udbvtl <= #`zednkw mppedc;
Xcheck(fgzsox);
end
endmodule
|
// DESCRIPTION: Verilator: Test of gated clock detection
//
// The code as shown generates a result by a delayed assignment from PC. The
// creation of the result is from a clock gated from the clock that sets
// PC. Howevever since they are essentially the same clock, the result should
// be delayed by one cycle.
//
// Standard Verilator treats them as different clocks, so the result stays in
// step with the PC. An event drive simulator always allows the clock to win.
//
// The problem is caused by the extra loop added by Verilator to the
// evaluation of all internally generated clocks (effectively removed by
// marking the clock enable).
//
// This test is added to facilitate experiments with solutions.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett <[email protected]>.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg gated_clk_en = 1'b0 ;
reg [1:0] pc = 2'b0;
reg [1:0] res = 2'b0;
wire gated_clk = gated_clk_en & clk;
always @(posedge clk) begin
pc <= pc + 1;
gated_clk_en <= 1'b1;
end
always @(posedge gated_clk) begin
res <= pc;
end
always @(posedge clk) begin
if (pc == 2'b11) begin
// Correct behaviour is that res should be lagging pc in the count
// by one cycle
if (res == 2'b10) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
endmodule
|
//////////////////////////////////////////////////////////////////
// //
// RAM-based register Bank for Amber Core //
// //
// This file is part of the Amber project //
// http://www.opencores.org/project,amber //
// //
// Description //
// Contains 37 32-bit registers, 16 of which are visible //
// ina any one operating mode. //
// The block is designed using syncronous RAM primitive, //
// and fits well into an FPGA design //
// //
// Author(s): //
// - Dmitry Tarnyagin, [email protected] //
// //
//////////////////////////////////////////////////////////////////
// //
// Copyright (C) 2010 Authors and OPENCORES.ORG //
// //
// This source file may be used and distributed without //
// restriction provided that this copyright statement is not //
// removed from the file and that any derivative work contains //
// the original copyright notice and the associated disclaimer. //
// //
// This source file is free software; you can redistribute it //
// and/or modify it under the terms of the GNU Lesser General //
// Public License as published by the Free Software Foundation; //
// either version 2.1 of the License, or (at your option) any //
// later version. //
// //
// This source is distributed in the hope that it will be //
// useful, but WITHOUT ANY WARRANTY; without even the implied //
// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR //
// PURPOSE. See the GNU Lesser General Public License for more //
// details. //
// //
// You should have received a copy of the GNU Lesser General //
// Public License along with this source; if not, download it //
// from http://www.opencores.org/lgpl.shtml //
// //
//////////////////////////////////////////////////////////////////
module a23_ram_register_bank (
input i_clk,
input i_fetch_stall,
input [1:0] i_mode_exec, // registered cpu mode from execution stage
input [1:0] i_mode_exec_nxt, // 1 periods delayed from i_mode_idec
// Used for register reads
input [1:0] i_mode_rds_exec, // Use raw version in this implementation,
// includes i_user_mode_regs_store
input i_user_mode_regs_load,
input [3:0] i_rm_sel,
input [3:0] i_rds_sel,
input [3:0] i_rn_sel,
input i_pc_wen,
input [3:0] i_reg_bank_wsel,
input [23:0] i_pc, // program counter [25:2]
input [31:0] i_reg,
input [3:0] i_status_bits_flags,
input i_status_bits_irq_mask,
input i_status_bits_firq_mask,
output [31:0] o_rm,
output [31:0] o_rs,
output [31:0] o_rd,
output [31:0] o_rn,
output [31:0] o_pc
);
`include "a23_localparams.v"
`include "a23_functions.v"
wire [1:0] mode_idec;
wire [1:0] mode_exec;
wire [1:0] mode_rds;
wire [4:0] rm_addr;
wire [4:0] rds_addr;
wire [4:0] rn_addr;
wire [4:0] wr_addr;
// Register pool in embedded ram memory
reg [31:0] reg_ram_n[31:0];
reg [31:0] reg_ram_m[31:0];
reg [31:0] reg_ram_ds[31:0];
wire [31:0] rds_out;
wire [31:0] rm_out;
wire [31:0] rn_out;
// Synchronous ram input buffering
reg [4:0] rm_addr_reg;
reg [4:0] rds_addr_reg;
reg [4:0] rn_addr_reg;
// User Mode Registers
reg [23:0] r15 = 24'hc0_ffee;
wire [31:0] r15_out_rm;
wire [31:0] r15_out_rm_nxt;
wire [31:0] r15_out_rn;
// r15 selectors
reg rn_15 = 1'b0;
reg rm_15 = 1'b0;
reg rds_15 = 1'b0;
// Write Enables from execute stage
assign mode_idec = i_mode_exec_nxt & ~{2{i_user_mode_regs_load}};
assign wr_addr = reg_addr(mode_idec, i_reg_bank_wsel);
// Read Enables from stage 1 (fetch)
assign mode_exec = i_mode_exec_nxt;
assign rm_addr = reg_addr(mode_exec, i_rm_sel);
assign rn_addr = reg_addr(mode_exec, i_rn_sel);
// Rds
assign mode_rds = i_mode_rds_exec;
assign rds_addr = reg_addr(mode_rds, i_rds_sel);
// ========================================================
// r15 Register Read based on Mode
// ========================================================
assign r15_out_rm = { i_status_bits_flags,
i_status_bits_irq_mask,
i_status_bits_firq_mask,
r15,
i_mode_exec};
assign r15_out_rm_nxt = { i_status_bits_flags,
i_status_bits_irq_mask,
i_status_bits_firq_mask,
i_pc,
i_mode_exec};
assign r15_out_rn = {6'd0, r15, 2'd0};
// ========================================================
// Program Counter out
// ========================================================
assign o_pc = r15_out_rn;
// ========================================================
// Rm Selector
// ========================================================
assign rm_out = reg_ram_m[rm_addr_reg];
assign o_rm = rm_15 ? r15_out_rm :
rm_out;
// ========================================================
// Rds Selector
// ========================================================
assign rds_out = reg_ram_ds[rds_addr_reg];
assign o_rs = rds_15 ? r15_out_rn :
rds_out;
// ========================================================
// Rd Selector
// ========================================================
assign o_rd = rds_15 ? r15_out_rm_nxt :
rds_out;
// ========================================================
// Rn Selector
// ========================================================
assign rn_out = reg_ram_n[rn_addr_reg];
assign o_rn = rn_15 ? r15_out_rn :
rn_out;
// ========================================================
// Register Update
// ========================================================
always @ ( posedge i_clk )
if (!i_fetch_stall)
begin
// Register write.
// Actually the code is synthesed as a syncronous ram
// with an additional pass-through multiplexor for
// read-when-write handling.
reg_ram_n[wr_addr] <= i_reg;
reg_ram_m[wr_addr] <= i_reg;
reg_ram_ds[wr_addr] <= i_reg;
r15 <= i_pc_wen ? i_pc : r15;
// The latching is actually implemented in a hard block.
rn_addr_reg <= rn_addr;
rm_addr_reg <= rm_addr;
rds_addr_reg <= rds_addr;
rn_15 <= i_rn_sel == 4'hF;
rm_15 <= i_rm_sel == 4'hF;
rds_15 <= i_rds_sel == 4'hF;
end
// ========================================================
// Register mapping:
// ========================================================
// 0xxxx : r0 - r14
// 10xxx : r8_firq - r14_firq
// 110xx : r13_irq - r14_irq
// 111xx : r13_svc - r14_svc
function [4:0] reg_addr;
input [1:0] mode;
input [3:0] sel;
begin
casez ({mode, sel}) // synthesis full_case parallel_case
6'b??0???: reg_addr = {1'b0, sel}; // r0 - r7
6'b1?1100: reg_addr = {1'b0, sel}; // irq and svc r12
6'b001???: reg_addr = {1'b0, sel}; // user r8 - r14
6'b011???: reg_addr = {2'b10, sel[2:0]}; // fiq r8-r14
6'b1?10??: reg_addr = {1'b0, sel}; // irq and svc r8-r11
6'b101101: reg_addr = {3'b110, sel[1:0]}; // irq r13
6'b101110: reg_addr = {3'b110, sel[1:0]}; // irq r14
6'b101111: reg_addr = {3'b110, sel[1:0]}; // irq r15, just to make the case full
6'b111101: reg_addr = {3'b111, sel[1:0]}; // svc r13
6'b111110: reg_addr = {3'b111, sel[1:0]}; // svc r14
6'b111111: reg_addr = {3'b111, sel[1:0]}; // svc r15, just to make the case full
endcase
end
endfunction
// synthesis translate_off
// To be used as probes...
wire [31:0] r0;
wire [31:0] r1;
wire [31:0] r2;
wire [31:0] r3;
wire [31:0] r4;
wire [31:0] r5;
wire [31:0] r6;
wire [31:0] r7;
wire [31:0] r8;
wire [31:0] r9;
wire [31:0] r10;
wire [31:0] r11;
wire [31:0] r12;
wire [31:0] r13;
wire [31:0] r14;
wire [31:0] r13_svc;
wire [31:0] r14_svc;
wire [31:0] r13_irq;
wire [31:0] r14_irq;
wire [31:0] r8_firq;
wire [31:0] r9_firq;
wire [31:0] r10_firq;
wire [31:0] r11_firq;
wire [31:0] r12_firq;
wire [31:0] r13_firq;
wire [31:0] r14_firq;
wire [31:0] r0_out;
wire [31:0] r1_out;
wire [31:0] r2_out;
wire [31:0] r3_out;
wire [31:0] r4_out;
wire [31:0] r5_out;
wire [31:0] r6_out;
wire [31:0] r7_out;
wire [31:0] r8_out;
wire [31:0] r9_out;
wire [31:0] r10_out;
wire [31:0] r11_out;
wire [31:0] r12_out;
wire [31:0] r13_out;
wire [31:0] r14_out;
assign r0 = reg_ram_m[ 0];
assign r1 = reg_ram_m[ 1];
assign r2 = reg_ram_m[ 2];
assign r3 = reg_ram_m[ 3];
assign r4 = reg_ram_m[ 4];
assign r5 = reg_ram_m[ 5];
assign r6 = reg_ram_m[ 6];
assign r7 = reg_ram_m[ 7];
assign r8 = reg_ram_m[ 8];
assign r9 = reg_ram_m[ 9];
assign r10 = reg_ram_m[10];
assign r11 = reg_ram_m[11];
assign r12 = reg_ram_m[12];
assign r13 = reg_ram_m[13];
assign r14 = reg_ram_m[14];
assign r13_svc = reg_ram_m[29];
assign r14_svc = reg_ram_m[30];
assign r13_irq = reg_ram_m[25];
assign r14_irq = reg_ram_m[26];
assign r8_firq = reg_ram_m[16];
assign r9_firq = reg_ram_m[17];
assign r10_firq = reg_ram_m[18];
assign r11_firq = reg_ram_m[19];
assign r12_firq = reg_ram_m[20];
assign r13_firq = reg_ram_m[21];
assign r14_firq = reg_ram_m[22];
assign r0_out = reg_ram_m[reg_addr(mode_exec, 0)];
assign r1_out = reg_ram_m[reg_addr(mode_exec, 1)];
assign r2_out = reg_ram_m[reg_addr(mode_exec, 2)];
assign r3_out = reg_ram_m[reg_addr(mode_exec, 3)];
assign r4_out = reg_ram_m[reg_addr(mode_exec, 4)];
assign r5_out = reg_ram_m[reg_addr(mode_exec, 5)];
assign r6_out = reg_ram_m[reg_addr(mode_exec, 6)];
assign r7_out = reg_ram_m[reg_addr(mode_exec, 7)];
assign r8_out = reg_ram_m[reg_addr(mode_exec, 8)];
assign r9_out = reg_ram_m[reg_addr(mode_exec, 9)];
assign r10_out = reg_ram_m[reg_addr(mode_exec, 10)];
assign r11_out = reg_ram_m[reg_addr(mode_exec, 11)];
assign r12_out = reg_ram_m[reg_addr(mode_exec, 12)];
assign r13_out = reg_ram_m[reg_addr(mode_exec, 13)];
assign r14_out = reg_ram_m[reg_addr(mode_exec, 14)];
// synthesis translate_on
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sctag_sig_rptr.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
module sctag_sig_rptr(/*AUTOARG*/
// Outputs
fast_sig_buf,
// Inputs
fast_sig
);
output [39:0] fast_sig_buf;
input [39:0] fast_sig;
assign fast_sig_buf = fast_sig ;
endmodule
|
// -- (c) Copyright 2008 - 2012 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: N-deep SRL pipeline element with generic single-channel AXI interfaces.
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
// Structure:
// axic_srl_fifo
// ndeep_srl
// nto1_mux
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_data_fifo_v2_1_axic_srl_fifo #
(
parameter C_FAMILY = "none", // FPGA Family
parameter integer C_FIFO_WIDTH = 1, // Width of S_MESG/M_MESG.
parameter integer C_MAX_CTRL_FANOUT = 33, // Maximum number of mesg bits
// the control logic can be used
// on before the control logic
// needs to be replicated.
parameter integer C_FIFO_DEPTH_LOG = 2, // Depth of FIFO is 2**C_FIFO_DEPTH_LOG.
// The minimum size fifo generated is 4-deep.
parameter C_USE_FULL = 1 // Prevent overwrite by throttling S_READY.
)
(
input wire ACLK, // Clock
input wire ARESET, // Reset
input wire [C_FIFO_WIDTH-1:0] S_MESG, // Input data
input wire S_VALID, // Input data valid
output wire S_READY, // Input data ready
output wire [C_FIFO_WIDTH-1:0] M_MESG, // Output data
output wire M_VALID, // Output data valid
input wire M_READY // Output data ready
);
localparam P_FIFO_DEPTH_LOG = (C_FIFO_DEPTH_LOG>1) ? C_FIFO_DEPTH_LOG : 2;
localparam P_EMPTY = {P_FIFO_DEPTH_LOG{1'b1}};
localparam P_ALMOSTEMPTY = {P_FIFO_DEPTH_LOG{1'b0}};
localparam P_ALMOSTFULL_TEMP = {P_EMPTY, 1'b0};
localparam P_ALMOSTFULL = P_ALMOSTFULL_TEMP[0+:P_FIFO_DEPTH_LOG];
localparam P_NUM_REPS = (((C_FIFO_WIDTH+1)%C_MAX_CTRL_FANOUT) == 0) ?
(C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT :
((C_FIFO_WIDTH+1)/C_MAX_CTRL_FANOUT)+1;
(* syn_keep = "1" *) reg [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr;
(* syn_keep = "1" *) wire [P_NUM_REPS*P_FIFO_DEPTH_LOG-1:0] fifoaddr_i;
genvar i;
genvar j;
reg M_VALID_i;
reg S_READY_i;
wire push; // FIFO push
wire pop; // FIFO pop
reg areset_d1; // Reset delay register
wire [C_FIFO_WIDTH-1:0] m_axi_mesg_i; // Intermediate SRL data
assign M_VALID = M_VALID_i;
assign S_READY = C_USE_FULL ? S_READY_i : 1'b1;
assign M_MESG = m_axi_mesg_i;
assign push = S_VALID & (C_USE_FULL ? S_READY_i : 1'b1);
assign pop = M_VALID_i & M_READY;
always @(posedge ACLK) begin
areset_d1 <= ARESET;
end
generate
//---------------------------------------------------------------------------
// Create count of number of elements in FIFOs
//---------------------------------------------------------------------------
for (i=0;i<P_NUM_REPS;i=i+1) begin : gen_rep
assign fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] =
push ? fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] + 1 :
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] - 1;
always @(posedge ACLK) begin
if (ARESET)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
{P_FIFO_DEPTH_LOG{1'b1}};
else if (push ^ pop)
fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i] <=
fifoaddr_i[P_FIFO_DEPTH_LOG*(i+1)-1:P_FIFO_DEPTH_LOG*i];
end
end
//---------------------------------------------------------------------------
// When FIFO is empty, reset master valid bit. When not empty set valid bit.
// When FIFO is full, reset slave ready bit. When not full set ready bit.
//---------------------------------------------------------------------------
always @(posedge ACLK) begin
if (ARESET) begin
M_VALID_i <= 1'b0;
end else if ((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTEMPTY) && pop && ~push) begin
M_VALID_i <= 1'b0;
end else if (push) begin
M_VALID_i <= 1'b1;
end
end
always @(posedge ACLK) begin
if (ARESET) begin
S_READY_i <= 1'b0;
end else if (areset_d1) begin
S_READY_i <= 1'b1;
end else if (C_USE_FULL &&
((fifoaddr[P_FIFO_DEPTH_LOG*P_NUM_REPS-1:P_FIFO_DEPTH_LOG*(P_NUM_REPS-1)] ==
P_ALMOSTFULL) && push && ~pop)) begin
S_READY_i <= 1'b0;
end else if (C_USE_FULL && pop) begin
S_READY_i <= 1'b1;
end
end
//---------------------------------------------------------------------------
// Instantiate SRLs
//---------------------------------------------------------------------------
for (i=0;i<(C_FIFO_WIDTH/C_MAX_CTRL_FANOUT)+((C_FIFO_WIDTH%C_MAX_CTRL_FANOUT)>0);i=i+1) begin : gen_srls
for (j=0;((j<C_MAX_CTRL_FANOUT)&&(i*C_MAX_CTRL_FANOUT+j<C_FIFO_WIDTH));j=j+1) begin : gen_rep
axi_data_fifo_v2_1_ndeep_srl #
(
.C_FAMILY (C_FAMILY),
.C_A_WIDTH (P_FIFO_DEPTH_LOG)
)
srl_nx1
(
.CLK (ACLK),
.A (fifoaddr[P_FIFO_DEPTH_LOG*(i+1)-1:
P_FIFO_DEPTH_LOG*(i)]),
.CE (push),
.D (S_MESG[i*C_MAX_CTRL_FANOUT+j]),
.Q (m_axi_mesg_i[i*C_MAX_CTRL_FANOUT+j])
);
end
end
endgenerate
endmodule
`default_nettype wire
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.3 (win64) Build 1682563 Mon Oct 10 19:07:27 MDT 2016
// Date : Mon Sep 18 12:05:38 2017
// Host : PC4719 running 64-bit Service Pack 1 (build 7601)
// Command : write_verilog -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
// decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ila_0_stub.v
// Design : ila_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7k160tffg676-2
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* X_CORE_INFO = "ila,Vivado 2016.3" *)
module decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix(clk, probe0, probe1, probe2, probe3, probe4, probe5,
probe6, probe7)
/* synthesis syn_black_box black_box_pad_pin="clk,probe0[63:0],probe1[63:0],probe2[31:0],probe3[31:0],probe4[0:0],probe5[0:0],probe6[0:0],probe7[0:0]" */;
input clk;
input [63:0]probe0;
input [63:0]probe1;
input [31:0]probe2;
input [31:0]probe3;
input [0:0]probe4;
input [0:0]probe5;
input [0:0]probe6;
input [0:0]probe7;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21ba (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21BA_PP_BLACKBOX_V
|
/*
Copyright (c) 2019 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_ptp_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
parameter LOGIC_PTP_PERIOD_NS = 4'h6;
parameter LOGIC_PTP_PERIOD_FNS = 16'h6666;
parameter PTP_PERIOD_NS = 4'h6;
parameter PTP_PERIOD_FNS = 16'h6666;
parameter PTP_USE_SAMPLE_CLOCK = 0;
parameter TX_PTP_TS_ENABLE = 1;
parameter RX_PTP_TS_ENABLE = 1;
parameter TX_PTP_TS_FIFO_DEPTH = 64;
parameter RX_PTP_TS_FIFO_DEPTH = 64;
parameter PTP_TS_WIDTH = 96;
parameter TX_PTP_TAG_ENABLE = 1;
parameter PTP_TAG_WIDTH = 16;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg ptp_sample_clk = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg [PTP_TAG_WIDTH-1:0] s_axis_tx_ptp_ts_tag = 0;
reg s_axis_tx_ptp_ts_valid = 0;
reg m_axis_tx_ptp_ts_ready = 0;
reg rx_axis_tready = 0;
reg m_axis_rx_ptp_ts_ready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [PTP_TS_WIDTH-1:0] ptp_ts_96 = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire s_axis_tx_ptp_ts_ready;
wire [PTP_TS_WIDTH-1:0] m_axis_tx_ptp_ts_96;
wire [PTP_TAG_WIDTH-1:0] m_axis_tx_ptp_ts_tag;
wire m_axis_tx_ptp_ts_valid;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [PTP_TS_WIDTH-1:0] m_axis_rx_ptp_ts_96;
wire m_axis_rx_ptp_ts_valid;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
ptp_sample_clk,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
s_axis_tx_ptp_ts_tag,
s_axis_tx_ptp_ts_valid,
m_axis_tx_ptp_ts_ready,
rx_axis_tready,
m_axis_rx_ptp_ts_ready,
xgmii_rxd,
xgmii_rxc,
ptp_ts_96,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
s_axis_tx_ptp_ts_ready,
m_axis_tx_ptp_ts_96,
m_axis_tx_ptp_ts_tag,
m_axis_tx_ptp_ts_valid,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
m_axis_rx_ptp_ts_96,
m_axis_rx_ptp_ts_valid,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_ptp_64.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_ptp_64);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL),
.LOGIC_PTP_PERIOD_NS(LOGIC_PTP_PERIOD_NS),
.LOGIC_PTP_PERIOD_FNS(LOGIC_PTP_PERIOD_FNS),
.PTP_PERIOD_NS(PTP_PERIOD_NS),
.PTP_PERIOD_FNS(PTP_PERIOD_FNS),
.PTP_USE_SAMPLE_CLOCK(PTP_USE_SAMPLE_CLOCK),
.TX_PTP_TS_ENABLE(TX_PTP_TS_ENABLE),
.RX_PTP_TS_ENABLE(RX_PTP_TS_ENABLE),
.TX_PTP_TS_FIFO_DEPTH(TX_PTP_TS_FIFO_DEPTH),
.RX_PTP_TS_FIFO_DEPTH(RX_PTP_TS_FIFO_DEPTH),
.PTP_TS_WIDTH(PTP_TS_WIDTH),
.TX_PTP_TAG_ENABLE(TX_PTP_TAG_ENABLE),
.PTP_TAG_WIDTH(PTP_TAG_WIDTH)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.ptp_sample_clk(ptp_sample_clk),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.s_axis_tx_ptp_ts_tag(s_axis_tx_ptp_ts_tag),
.s_axis_tx_ptp_ts_valid(s_axis_tx_ptp_ts_valid),
.s_axis_tx_ptp_ts_ready(s_axis_tx_ptp_ts_ready),
.m_axis_tx_ptp_ts_96(m_axis_tx_ptp_ts_96),
.m_axis_tx_ptp_ts_tag(m_axis_tx_ptp_ts_tag),
.m_axis_tx_ptp_ts_valid(m_axis_tx_ptp_ts_valid),
.m_axis_tx_ptp_ts_ready(m_axis_tx_ptp_ts_ready),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.m_axis_rx_ptp_ts_96(m_axis_rx_ptp_ts_96),
.m_axis_rx_ptp_ts_valid(m_axis_rx_ptp_ts_valid),
.m_axis_rx_ptp_ts_ready(m_axis_rx_ptp_ts_ready),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ptp_ts_96(ptp_ts_96),
.ifg_delay(ifg_delay)
);
endmodule
|
Subsets and Splits
No saved queries yet
Save your SQL queries to embed, download, and access them later. Queries will appear here once saved.