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/*
* Copyright 2013, Homer Hsing <[email protected]>
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/*
* in byte_num out
* 0x11223344 0 0x01000000
* 0x11223344 1 0x11010000
* 0x11223344 2 0x11220100
* 0x11223344 3 0x11223301
*/
module padder1(in, byte_num, out);
input [31:0] in;
input [1:0] byte_num;
output reg [31:0] out;
always @ (*)
case (byte_num)
0: out = 32'h1000000;
1: out = {in[31:24], 24'h010000};
2: out = {in[31:16], 16'h0100};
3: out = {in[31:8], 8'h01};
endcase
endmodule
|
// test cases found using vloghammer
// https://github.com/YosysHQ/VlogHammer
module test01(a, y);
input [7:0] a;
output [3:0] y;
assign y = ~a >> 4;
endmodule
module test02(a, y);
input signed [3:0] a;
output signed [4:0] y;
assign y = (~a) >> 1;
endmodule
module test03(a, b, y);
input [2:0] a;
input signed [1:0] b;
output y;
assign y = ~(a >>> 1) == b;
endmodule
module test04(a, y);
input a;
output [1:0] y;
assign y = ~(a - 1'b0);
endmodule
// .. this test triggers a bug in Xilinx ISIM.
// module test05(a, y);
// input a;
// output y;
// assign y = 12345 >> {a, 32'd0};
// endmodule
// .. this test triggers a bug in Icarus Verilog.
// module test06(a, b, c, y);
// input signed [3:0] a;
// input signed [1:0] b;
// input signed [1:0] c;
// output [5:0] y;
// assign y = (a >> b) >>> c;
// endmodule
module test07(a, b, y);
input signed [1:0] a;
input signed [2:0] b;
output y;
assign y = 2'b11 != a+b;
endmodule
module test08(a, b, y);
input [1:0] a;
input [1:0] b;
output y;
assign y = a == ($signed(b) >>> 1);
endmodule
module test09(a, b, c, y);
input a;
input signed [1:0] b;
input signed [2:0] c;
output [3:0] y;
assign y = a ? b : c;
endmodule
module test10(a, b, c, y);
input a;
input signed [1:0] b;
input signed [2:0] c;
output y;
assign y = ^(a ? b : c);
endmodule
// module test11(a, b, y);
// input signed [3:0] a;
// input signed [3:0] b;
// output signed [5:0] y;
// assign y = -(5'd27);
// endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V
`define SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V
/**
* a21o: 2-input AND into first input of 2-input OR.
*
* X = ((A1 & A2) | B1)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_hdll__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_hdll__a21o (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , A1, A2 );
or or0 (or0_out_X , and0_out, B1 );
sky130_fd_sc_hdll__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__A21O_FUNCTIONAL_PP_V |
// Icarus has a number of places where it can calculate %.
module top;
parameter out0 = 64'shF333333333333392 % 3'sd3;
reg passed;
wire signed [63:0] in;
wire signed [2:0] const_w0;
reg signed [63:0] out1;
wire signed [63:0] out2;
reg signed [63:0] out3;
assign in = 64'hF333333333333392;
assign const_w0 = 3'sd3;
always @* begin
out1 = (in % const_w0);
end
assign out2 = (in % const_w0);
initial begin
passed = 1'b1;
#1;
$display("Testing %0d %% %0d.", in, const_w0);
// Check the parameter result.
if (out0 !== -2) begin
$display("Failed: constant %%, expected -2, got %0d.", out0);
passed = 1'b0;
end
// Check the always result.
if (out1 !== -2) begin
$display("Failed: procedural %%, expected -2, got %0d.", out1);
passed = 1'b0;
end
// Check the CA result.
if (out2 !== -2) begin
$display("Failed: CA %%, expected -2, got %0d.", out2);
passed = 1'b0;
end
// Check a compile time constant result.
out3 = 64'shF333333333333392 % 3'sd3;
if (out3 !== -2) begin
$display("Failed: CA %%, expected -2, got %0d.", out3);
passed = 1'b0;
end
if (passed) $display("PASSED");
$finish;
end
endmodule
|
module main;
reg [2:0] Q;
reg clk, clr, up, down;
reg flag;
(*ivl_synthesis_off *)
initial begin
clk = 0;
up = 0;
down = 0;
clr = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 0) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
up = 1;
clr = 0;
#1 clk = 1;
#1 clk = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b010) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
up = 0;
down = 1;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
if (flag !== 0) begin
$display("FAILED");
$finish;
end
down = 0;
#1 clk = 1;
#1 clk = 0;
if (Q !== 3'b001) begin
$display("FAILED");
$finish;
end
if (flag !== 1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
$finish;
end
/*
* This statement models a snythesizable UP/DOWN counter. The up
* and down cases are enabled by up and down signals. If both
* signals are absent, the synthesizer should take the implicit
* case that Q <= Q;
*/
(* ivl_synthesis_on *)
always @(posedge clk, posedge clr)
if (clr) begin
Q <= 0;
flag <= 0;
end else begin
if (up)
Q <= Q + 1;
else if (down)
Q <= Q - 1;
else
flag <= 1;
end
endmodule // main
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: sparc_exu_ecl_eccctl.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
////////////////////////////////////////////////////////////////////////
/*
// Module Name: sparc_exu_ecl_eccctl
// Description: Implements the control logic for ecc checking.
// This includes picking which error to fix (only one fixed per instruction),
// enabling the checks, and signalling the errors.
*/
module sparc_exu_ecl_eccctl (/*AUTOARG*/
// Outputs
ue_trap_m, ecl_ecc_sel_rs1_m_l, ecl_ecc_sel_rs2_m_l,
ecl_ecc_sel_rs3_m_l, ecl_ecc_log_rs1_m, ecl_ecc_log_rs2_m,
ecl_ecc_log_rs3_m, ecl_byp_sel_ecc_m, ecl_ecc_rs1_use_rf_e,
ecl_ecc_rs2_use_rf_e, ecl_ecc_rs3_use_rf_e, eccctl_wb_rd_m,
exu_ifu_ecc_ce_m, exu_ifu_ecc_ue_m, exu_ifu_err_reg_m,
ecl_byp_ecc_mask_m_l, exu_ifu_inj_ack, exu_ifu_err_synd_7_m,
// Inputs
clk, se, rst_tri_en, ecc_ecl_rs1_ce, ecc_ecl_rs1_ue,
ecc_ecl_rs2_ce, ecc_ecl_rs2_ue, ecc_ecl_rs3_ce, ecc_ecl_rs3_ue,
ecl_byp_rcc_mux2_sel_rf, ecl_byp_rs2_mux2_sel_rf,
ecl_byp_rs3_mux2_sel_rf, rs1_vld_e, rs2_vld_e, rs3_vld_e,
ifu_exu_rs1_m, ifu_exu_rs2_m, ifu_exu_rs3_m, rml_ecl_cwp_d,
ifu_exu_ecc_mask, ifu_exu_inj_irferr, ifu_exu_disable_ce_e,
wb_eccctl_spec_wen_next, ifu_exu_nceen_e, ifu_exu_inst_vld_e,
rml_ecl_gl_e, cancel_rs3_ecc_e
) ;
input clk;
input se;
input rst_tri_en;
input ecc_ecl_rs1_ce;
input ecc_ecl_rs1_ue;
input ecc_ecl_rs2_ce;
input ecc_ecl_rs2_ue;
input ecc_ecl_rs3_ce;
input ecc_ecl_rs3_ue;
input ecl_byp_rcc_mux2_sel_rf;
input ecl_byp_rs2_mux2_sel_rf;
input ecl_byp_rs3_mux2_sel_rf;
input rs1_vld_e;
input rs2_vld_e;
input rs3_vld_e;
input [4:0] ifu_exu_rs1_m;
input [4:0] ifu_exu_rs2_m;
input [4:0] ifu_exu_rs3_m;
input [2:0] rml_ecl_cwp_d;
input [7:0] ifu_exu_ecc_mask;
input ifu_exu_inj_irferr;
input ifu_exu_disable_ce_e;
input wb_eccctl_spec_wen_next;
input ifu_exu_nceen_e;
input ifu_exu_inst_vld_e;
input [1:0] rml_ecl_gl_e;
input cancel_rs3_ecc_e;
output ue_trap_m;
output ecl_ecc_sel_rs1_m_l;
output ecl_ecc_sel_rs2_m_l;
output ecl_ecc_sel_rs3_m_l;
output ecl_ecc_log_rs1_m;
output ecl_ecc_log_rs2_m;
output ecl_ecc_log_rs3_m;
output ecl_byp_sel_ecc_m;
output ecl_ecc_rs1_use_rf_e;
output ecl_ecc_rs2_use_rf_e;
output ecl_ecc_rs3_use_rf_e;
output [4:0] eccctl_wb_rd_m;
output exu_ifu_ecc_ce_m;
output exu_ifu_ecc_ue_m;
output [7:0] exu_ifu_err_reg_m;
output [7:0] ecl_byp_ecc_mask_m_l;
output exu_ifu_inj_ack;
output exu_ifu_err_synd_7_m;
wire sel_rs1_e;
wire sel_rs2_e;
wire sel_rs3_e;
wire sel_rs1_m;
wire sel_rs2_m;
wire sel_rs3_m;
wire safe_sel_rs1_m;
wire safe_sel_rs2_m;
wire safe_sel_rs3_m;
wire [2:0] cwp_e;
wire [2:0] cwp_m;
wire [1:0] gl_m;
wire inj_irferr_m;
wire inj_irferr_w;
wire detect_ce_e;
wire detect_ue_e;
wire flag_ecc_ce_e;
wire flag_ecc_ue_e;
wire [4:0] log_rs_m;
wire rs1_ce_m;
wire rs1_ue_m;
wire rs2_ce_m;
wire rs2_ue_m;
wire rs3_ue_m;
wire rs1_sel_rf_e;
wire rs2_sel_rf_e;
wire rs3_sel_rf_e;
wire vld_rs3_ce_e;
wire vld_rs3_ue_e;
// Store whether rf value was used for ecc checking
assign ecl_ecc_rs1_use_rf_e = rs1_sel_rf_e & rs1_vld_e & ifu_exu_inst_vld_e;
assign ecl_ecc_rs2_use_rf_e = rs2_sel_rf_e & rs2_vld_e & ifu_exu_inst_vld_e;
assign ecl_ecc_rs3_use_rf_e = rs3_sel_rf_e & rs3_vld_e & ifu_exu_inst_vld_e;
dff_s rs1_rf_dff(.din(ecl_byp_rcc_mux2_sel_rf), .clk(clk),
.q(rs1_sel_rf_e), .se(se), .si(), .so());
dff_s rs2_rf_dff(.din(ecl_byp_rs2_mux2_sel_rf), .clk(clk),
.q(rs2_sel_rf_e), .se(se), .si(), .so());
dff_s rs3_rf_dff(.din(ecl_byp_rs3_mux2_sel_rf), .clk(clk),
.q(rs3_sel_rf_e), .se(se), .si(), .so());
assign vld_rs3_ce_e = ecc_ecl_rs3_ce & ~cancel_rs3_ecc_e;
assign vld_rs3_ue_e = ecc_ecl_rs3_ue & ~cancel_rs3_ecc_e;
assign detect_ce_e = (ecc_ecl_rs1_ce | ecc_ecl_rs2_ce | vld_rs3_ce_e);
assign detect_ue_e = (ecc_ecl_rs1_ue | ecc_ecl_rs2_ue | vld_rs3_ue_e);
// Generate trap signals
assign flag_ecc_ue_e = (detect_ue_e |
detect_ce_e & ifu_exu_disable_ce_e); // convert ce to ue
assign flag_ecc_ce_e = detect_ce_e & ~ifu_exu_disable_ce_e;
// Pass along signal to fix errors
dff_s byp_sel_ecc_e2m(.din(flag_ecc_ce_e), .clk(clk), .q(ecl_byp_sel_ecc_m),
.se(se), .si(), .so());
dff_s ecc_ue_e2m(.din(flag_ecc_ue_e), .clk(clk), .q(exu_ifu_ecc_ue_m),
.se(se), .si(), .so());
dff_s nceen_e2m(.din(ifu_exu_nceen_e), .clk(clk), .q(nceen_m), .se(se), .si(), .so());
assign ue_trap_m = exu_ifu_ecc_ue_m & nceen_m;
// only report ce (and replay) if no ue
assign exu_ifu_ecc_ce_m = ecl_byp_sel_ecc_m & ~exu_ifu_ecc_ue_m;
// if globals then report %gl. otherwise log %cwp
assign exu_ifu_err_reg_m[7:5] = (~log_rs_m[4] & ~log_rs_m[3])? {1'b0,gl_m[1:0]}: cwp_m[2:0];
assign exu_ifu_err_reg_m[4:0] = log_rs_m[4:0];
// Control for mux to ecc decoder (just ce)
assign sel_rs1_e = ecc_ecl_rs1_ce;
assign sel_rs2_e = ~ecc_ecl_rs1_ce & ecc_ecl_rs2_ce;
assign sel_rs3_e = ~(ecc_ecl_rs1_ce | ecc_ecl_rs2_ce);
dff_s ecc_sel_rs1_dff(.din(sel_rs1_e), .clk(clk), .q(sel_rs1_m),
.se(se), .si(), .so());
dff_s ecc_sel_rs2_dff(.din(sel_rs2_e), .clk(clk), .q(sel_rs2_m),
.se(se), .si(), .so());
dff_s ecc_sel_rs3_dff(.din(sel_rs3_e), .clk(clk), .q(sel_rs3_m),
.se(se), .si(), .so());
// Make selects one hot
assign safe_sel_rs1_m = sel_rs1_m | rst_tri_en;
assign safe_sel_rs2_m = sel_rs2_m & ~rst_tri_en;
assign safe_sel_rs3_m = sel_rs3_m & ~rst_tri_en;
assign ecl_ecc_sel_rs1_m_l = ~safe_sel_rs1_m;
assign ecl_ecc_sel_rs2_m_l = ~safe_sel_rs2_m;
assign ecl_ecc_sel_rs3_m_l = ~safe_sel_rs3_m;
// Mux to generate the rd for fixed value
mux3ds #(5) ecc_rd_mux(.dout(eccctl_wb_rd_m[4:0]),
.in0(ifu_exu_rs1_m[4:0]),
.in1(ifu_exu_rs2_m[4:0]),
.in2(ifu_exu_rs3_m[4:0]),
.sel0(safe_sel_rs1_m),
.sel1(safe_sel_rs2_m),
.sel2(safe_sel_rs3_m));
// Control for muxes for logging errors
assign ecl_ecc_log_rs1_m = rs1_ue_m | (rs1_ce_m & ~rs2_ue_m & ~rs3_ue_m);
assign ecl_ecc_log_rs2_m = (rs2_ue_m & ~rs1_ue_m) | (rs2_ce_m & ~rs1_ue_m & ~rs1_ce_m & ~rs3_ue_m);
assign ecl_ecc_log_rs3_m = ~(ecl_ecc_log_rs1_m | ecl_ecc_log_rs2_m);
// Mux to generate the rs for error_logging
mux3ds #(5) ecc_rdlog_mux(.dout(log_rs_m[4:0]),
.in0(ifu_exu_rs1_m[4:0]),
.in1(ifu_exu_rs2_m[4:0]),
.in2(ifu_exu_rs3_m[4:0]),
.sel0(ecl_ecc_log_rs1_m),
.sel1(ecl_ecc_log_rs2_m),
.sel2(ecl_ecc_log_rs3_m));
dff_s #(3) cwp_d2e(.din(rml_ecl_cwp_d[2:0]), .clk(clk), .q(cwp_e[2:0]),
.se(se), .si(), .so());
dff_s #(3) cwp_e2m(.din(cwp_e[2:0]), .clk(clk), .q(cwp_m[2:0]),
.se(se), .si(), .so());
dff_s #(2) gl_e2m(.din(rml_ecl_gl_e[1:0]), .clk(clk), .q(gl_m[1:0]),
.se(se), .si(), .so());
// Syndrome needs to know if it was really a ce or ue
mux3ds ecc_synd7_mux(.dout(exu_ifu_err_synd_7_m),
.in0(rs1_ce_m),
.in1(rs2_ce_m),
.in2(~rs3_ue_m),
.sel0(ecl_ecc_log_rs1_m),
.sel1(ecl_ecc_log_rs2_m),
.sel2(ecl_ecc_log_rs3_m));
// signals for injecting errors
// inject error if it is enabled and a write will probably happen
// (don't bother to check kill_w
assign inj_irferr_m = wb_eccctl_spec_wen_next & ifu_exu_inj_irferr;
assign ecl_byp_ecc_mask_m_l = ~(ifu_exu_ecc_mask[7:0] & {8{inj_irferr_m}});
dff_s inj_irferr_m2w(.din(inj_irferr_m), .clk(clk), .q(inj_irferr_w),
.se(se), .si(), .so());
assign exu_ifu_inj_ack = inj_irferr_w;
// Pipeline Flops
dff_s rs1_ue_e2m(.din(ecc_ecl_rs1_ue), .clk(clk), .q(rs1_ue_m), .se(se), .si(), .so());
dff_s rs1_ce_e2m(.din(ecc_ecl_rs1_ce), .clk(clk), .q(rs1_ce_m), .se(se), .si(), .so());
dff_s rs2_ue_e2m(.din(ecc_ecl_rs2_ue), .clk(clk), .q(rs2_ue_m), .se(se), .si(), .so());
dff_s rs2_ce_e2m(.din(ecc_ecl_rs2_ce), .clk(clk), .q(rs2_ce_m), .se(se), .si(), .so());
dff_s rs3_ue_e2m(.din(vld_rs3_ue_e), .clk(clk), .q(rs3_ue_m), .se(se), .si(), .so());
endmodule // sparc_exu_ecl_eccctl
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
module ERROR_OUTPUT_LOGIC #(
parameter [7:0] DATA_WIDTH = 1,
parameter [7:0] ADDR_WIDTH = 6
) (
input rst,
input clk,
input loop_complete,
input error_detected,
input [7:0] error_state,
input [ADDR_WIDTH-1:0] error_address,
input [DATA_WIDTH-1:0] expected_data,
input [DATA_WIDTH-1:0] actual_data,
// Output to UART
input tx_data_accepted,
output reg tx_data_ready,
output reg [7:0] tx_data
);
reg reg_error_detected;
reg [7:0] reg_error_state;
reg [ADDR_WIDTH-1:0] reg_error_address;
reg [DATA_WIDTH-1:0] reg_expected_data;
reg [DATA_WIDTH-1:0] reg_actual_data;
reg [7:0] error_count;
reg [7:0] output_shift;
wire [7:0] next_output_shift = output_shift + 8;
wire count_shift_done = next_output_shift >= 8'd16;
wire address_shift_done = next_output_shift >= ADDR_WIDTH;
wire data_shift_done = next_output_shift >= DATA_WIDTH;
reg loop_ready;
reg [7:0] latched_error_count;
reg [7:0] errors;
reg [10:0] state;
reg [15:0] loop_count;
reg [15:0] latched_loop_count;
localparam START = (1 << 0),
ERROR_COUNT_HEADER = (1 << 1),
ERROR_COUNT_COUNT = (1 << 2),
CR = (1 << 3),
LF = (1 << 4),
ERROR_HEADER = (1 << 5),
ERROR_STATE = (1 << 6),
ERROR_ADDRESS = (1 << 7),
ERROR_EXPECTED_DATA = (1 << 8),
ERROR_ACTUAL_DATA = (1 << 9),
LOOP_COUNT = (1 << 10);
initial begin
tx_data_ready <= 1'b0;
tx_data <= 8'b0;
state <= START;
reg_error_detected <= 1'b0;
end
always @(posedge clk) begin
if(rst) begin
state <= START;
error_count <= 0;
reg_error_detected <= 0;
tx_data_ready <= 0;
tx_data <= 8'b0;
loop_count <= 0;
loop_ready <= 0;
end else begin
if(error_detected) begin
if(error_count < 255) begin
error_count <= error_count + 1;
end
if(!reg_error_detected) begin
reg_error_detected <= 1;
reg_error_state <= error_state;
reg_error_address <= error_address;
reg_expected_data <= expected_data;
reg_actual_data <= actual_data;
end
end
if(tx_data_accepted) begin
tx_data_ready <= 0;
end
if(loop_complete) begin
loop_count <= loop_count + 1;
if(!loop_ready) begin
loop_ready <= 1;
latched_error_count <= error_count;
latched_loop_count <= loop_count;
error_count <= 0;
end
end
case(state)
START: begin
if(reg_error_detected) begin
state <= ERROR_HEADER;
end else if(loop_ready) begin
state <= ERROR_COUNT_HEADER;
end
end
ERROR_COUNT_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "L";
tx_data_ready <= 1;
state <= ERROR_COUNT_COUNT;
end
end
ERROR_COUNT_COUNT: begin
if(!tx_data_ready) begin
tx_data <= latched_error_count;
tx_data_ready <= 1;
output_shift <= 0;
state <= LOOP_COUNT;
end
end
LOOP_COUNT: begin
if(!tx_data_ready) begin
tx_data <= (latched_loop_count >> output_shift);
tx_data_ready <= 1;
if(count_shift_done) begin
output_shift <= 0;
loop_ready <= 0;
state <= CR;
end else begin
output_shift <= next_output_shift;
end
end
end
CR: begin
if(!tx_data_ready) begin
tx_data <= 8'h0D; // "\r"
tx_data_ready <= 1;
state <= LF;
end
end
LF: begin
if(!tx_data_ready) begin
tx_data <= 8'h0A; // "\n"
tx_data_ready <= 1;
state <= START;
end
end
ERROR_HEADER: begin
if(!tx_data_ready) begin
tx_data <= "E";
tx_data_ready <= 1;
state <= ERROR_STATE;
end
end
ERROR_STATE: begin
if(!tx_data_ready) begin
tx_data <= reg_error_state;
tx_data_ready <= 1;
output_shift <= 0;
state <= ERROR_ADDRESS;
end
end
ERROR_ADDRESS: begin
if(!tx_data_ready) begin
tx_data <= (reg_error_address >> output_shift);
tx_data_ready <= 1;
if(address_shift_done) begin
output_shift <= 0;
state <= ERROR_EXPECTED_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_EXPECTED_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_expected_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
output_shift <= 0;
state <= ERROR_ACTUAL_DATA;
end else begin
output_shift <= next_output_shift;
end
end
end
ERROR_ACTUAL_DATA: begin
if(!tx_data_ready) begin
tx_data <= (reg_actual_data >> output_shift);
tx_data_ready <= 1;
if(data_shift_done) begin
state <= CR;
reg_error_detected <= 0;
end else begin
output_shift <= output_shift + 8;
end
end
end
default: begin
state <= START;
end
endcase
end
end
endmodule
|
/*
Copyright (c) 2015-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for eth_mac_10g_fifo
*/
module test_eth_mac_10g_fifo_64;
// Parameters
parameter DATA_WIDTH = 64;
parameter CTRL_WIDTH = (DATA_WIDTH/8);
parameter AXIS_DATA_WIDTH = DATA_WIDTH;
parameter AXIS_KEEP_ENABLE = (AXIS_DATA_WIDTH>8);
parameter AXIS_KEEP_WIDTH = (AXIS_DATA_WIDTH/8);
parameter ENABLE_PADDING = 1;
parameter ENABLE_DIC = 1;
parameter MIN_FRAME_LENGTH = 64;
parameter TX_FIFO_DEPTH = 4096;
parameter TX_FIFO_PIPELINE_OUTPUT = 2;
parameter TX_FRAME_FIFO = 1;
parameter TX_DROP_BAD_FRAME = TX_FRAME_FIFO;
parameter TX_DROP_WHEN_FULL = 0;
parameter RX_FIFO_DEPTH = 4096;
parameter RX_FIFO_PIPELINE_OUTPUT = 2;
parameter RX_FRAME_FIFO = 1;
parameter RX_DROP_BAD_FRAME = RX_FRAME_FIFO;
parameter RX_DROP_WHEN_FULL = RX_FRAME_FIFO;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg rx_clk = 0;
reg rx_rst = 0;
reg tx_clk = 0;
reg tx_rst = 0;
reg logic_clk = 0;
reg logic_rst = 0;
reg [AXIS_DATA_WIDTH-1:0] tx_axis_tdata = 0;
reg [AXIS_KEEP_WIDTH-1:0] tx_axis_tkeep = 0;
reg tx_axis_tvalid = 0;
reg tx_axis_tlast = 0;
reg tx_axis_tuser = 0;
reg rx_axis_tready = 0;
reg [DATA_WIDTH-1:0] xgmii_rxd = 0;
reg [CTRL_WIDTH-1:0] xgmii_rxc = 0;
reg [7:0] ifg_delay = 0;
// Outputs
wire tx_axis_tready;
wire [AXIS_DATA_WIDTH-1:0] rx_axis_tdata;
wire [AXIS_KEEP_WIDTH-1:0] rx_axis_tkeep;
wire rx_axis_tvalid;
wire rx_axis_tlast;
wire rx_axis_tuser;
wire [DATA_WIDTH-1:0] xgmii_txd;
wire [CTRL_WIDTH-1:0] xgmii_txc;
wire tx_error_underflow;
wire tx_fifo_overflow;
wire tx_fifo_bad_frame;
wire tx_fifo_good_frame;
wire rx_error_bad_frame;
wire rx_error_bad_fcs;
wire rx_fifo_overflow;
wire rx_fifo_bad_frame;
wire rx_fifo_good_frame;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
rx_clk,
rx_rst,
tx_clk,
tx_rst,
logic_clk,
logic_rst,
tx_axis_tdata,
tx_axis_tkeep,
tx_axis_tvalid,
tx_axis_tlast,
tx_axis_tuser,
rx_axis_tready,
xgmii_rxd,
xgmii_rxc,
ifg_delay
);
$to_myhdl(
tx_axis_tready,
rx_axis_tdata,
rx_axis_tkeep,
rx_axis_tvalid,
rx_axis_tlast,
rx_axis_tuser,
xgmii_txd,
xgmii_txc,
tx_error_underflow,
tx_fifo_overflow,
tx_fifo_bad_frame,
tx_fifo_good_frame,
rx_error_bad_frame,
rx_error_bad_fcs,
rx_fifo_overflow,
rx_fifo_bad_frame,
rx_fifo_good_frame
);
// dump file
$dumpfile("test_eth_mac_10g_fifo_64.lxt");
$dumpvars(0, test_eth_mac_10g_fifo_64);
end
eth_mac_10g_fifo #(
.DATA_WIDTH(DATA_WIDTH),
.CTRL_WIDTH(CTRL_WIDTH),
.AXIS_DATA_WIDTH(AXIS_DATA_WIDTH),
.AXIS_KEEP_ENABLE(AXIS_KEEP_ENABLE),
.AXIS_KEEP_WIDTH(AXIS_KEEP_WIDTH),
.ENABLE_PADDING(ENABLE_PADDING),
.ENABLE_DIC(ENABLE_DIC),
.MIN_FRAME_LENGTH(MIN_FRAME_LENGTH),
.TX_FIFO_DEPTH(TX_FIFO_DEPTH),
.TX_FIFO_PIPELINE_OUTPUT(TX_FIFO_PIPELINE_OUTPUT),
.TX_FRAME_FIFO(TX_FRAME_FIFO),
.TX_DROP_BAD_FRAME(TX_DROP_BAD_FRAME),
.TX_DROP_WHEN_FULL(TX_DROP_WHEN_FULL),
.RX_FIFO_DEPTH(RX_FIFO_DEPTH),
.RX_FIFO_PIPELINE_OUTPUT(RX_FIFO_PIPELINE_OUTPUT),
.RX_FRAME_FIFO(RX_FRAME_FIFO),
.RX_DROP_BAD_FRAME(RX_DROP_BAD_FRAME),
.RX_DROP_WHEN_FULL(RX_DROP_WHEN_FULL)
)
UUT (
.rx_clk(rx_clk),
.rx_rst(rx_rst),
.tx_clk(tx_clk),
.tx_rst(tx_rst),
.logic_clk(logic_clk),
.logic_rst(logic_rst),
.tx_axis_tdata(tx_axis_tdata),
.tx_axis_tkeep(tx_axis_tkeep),
.tx_axis_tvalid(tx_axis_tvalid),
.tx_axis_tready(tx_axis_tready),
.tx_axis_tlast(tx_axis_tlast),
.tx_axis_tuser(tx_axis_tuser),
.rx_axis_tdata(rx_axis_tdata),
.rx_axis_tkeep(rx_axis_tkeep),
.rx_axis_tvalid(rx_axis_tvalid),
.rx_axis_tready(rx_axis_tready),
.rx_axis_tlast(rx_axis_tlast),
.rx_axis_tuser(rx_axis_tuser),
.xgmii_rxd(xgmii_rxd),
.xgmii_rxc(xgmii_rxc),
.xgmii_txd(xgmii_txd),
.xgmii_txc(xgmii_txc),
.tx_error_underflow(tx_error_underflow),
.tx_fifo_overflow(tx_fifo_overflow),
.tx_fifo_bad_frame(tx_fifo_bad_frame),
.tx_fifo_good_frame(tx_fifo_good_frame),
.rx_error_bad_frame(rx_error_bad_frame),
.rx_error_bad_fcs(rx_error_bad_fcs),
.rx_fifo_overflow(rx_fifo_overflow),
.rx_fifo_bad_frame(rx_fifo_bad_frame),
.rx_fifo_good_frame(rx_fifo_good_frame),
.ifg_delay(ifg_delay)
);
endmodule
|
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_generic_ddio(
datain,
halfratebypass,
dataout,
clk_hr,
clk_fr
);
parameter WIDTH = 1;
localparam DATA_IN_WIDTH = 4 * WIDTH;
localparam DATA_OUT_WIDTH = WIDTH;
input [DATA_IN_WIDTH-1:0] datain;
input halfratebypass;
input [WIDTH-1:0] clk_hr;
input [WIDTH-1:0] clk_fr;
output [DATA_OUT_WIDTH-1:0] dataout;
generate
genvar pin;
for (pin = 0; pin < WIDTH; pin = pin + 1)
begin:acblock
wire fr_data_hi;
wire fr_data_lo;
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_hi (
.datainhi(datain[pin * 4]),
.datainlo(datain[pin * 4 + 2]),
.dataout(fr_data_hi),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.half_rate_mode("true"),
.use_new_clocking_model("true"),
.async_mode("none")
) hr_to_fr_lo (
.datainhi(datain[pin * 4 + 1]),
.datainlo(datain[pin * 4 + 3]),
.dataout(fr_data_lo),
.clkhi (clk_hr[pin]),
.clklo (clk_hr[pin]),
.hrbypass(halfratebypass),
.muxsel (clk_hr[pin])
);
cyclonev_ddio_out
#(
.async_mode("none"),
.half_rate_mode("false"),
.sync_mode("none"),
.use_new_clocking_model("true")
) ddio_out (
.datainhi(fr_data_hi),
.datainlo(fr_data_lo),
.dataout(dataout[pin]),
.clkhi (clk_fr[pin]),
.clklo (clk_fr[pin]),
.muxsel (clk_fr[pin])
);
end
endgenerate
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_arb_hp2_3.v
*
* Date : 2012-11
*
* Description : Module that arbitrates between RD/WR requests from 2 ports.
* Used for modelling the Top_Interconnect switch.
*****************************************************************************/
module processing_system7_bfm_v2_0_arb_hp2_3(
sw_clk,
rstn,
w_qos_hp2,
r_qos_hp2,
w_qos_hp3,
r_qos_hp3,
wr_ack_ddr_hp2,
wr_data_hp2,
wr_addr_hp2,
wr_bytes_hp2,
wr_dv_ddr_hp2,
rd_req_ddr_hp2,
rd_addr_hp2,
rd_bytes_hp2,
rd_data_ddr_hp2,
rd_dv_ddr_hp2,
wr_ack_ddr_hp3,
wr_data_hp3,
wr_addr_hp3,
wr_bytes_hp3,
wr_dv_ddr_hp3,
rd_req_ddr_hp3,
rd_addr_hp3,
rd_bytes_hp3,
rd_data_ddr_hp3,
rd_dv_ddr_hp3,
ddr_wr_ack,
ddr_wr_dv,
ddr_rd_req,
ddr_rd_dv,
ddr_rd_qos,
ddr_wr_qos,
ddr_wr_addr,
ddr_wr_data,
ddr_wr_bytes,
ddr_rd_addr,
ddr_rd_data,
ddr_rd_bytes
);
`include "processing_system7_bfm_v2_0_local_params.v"
input sw_clk;
input rstn;
input [axi_qos_width-1:0] w_qos_hp2;
input [axi_qos_width-1:0] r_qos_hp2;
input [axi_qos_width-1:0] w_qos_hp3;
input [axi_qos_width-1:0] r_qos_hp3;
input [axi_qos_width-1:0] ddr_rd_qos;
input [axi_qos_width-1:0] ddr_wr_qos;
output wr_ack_ddr_hp2;
input [max_burst_bits-1:0] wr_data_hp2;
input [addr_width-1:0] wr_addr_hp2;
input [max_burst_bytes_width:0] wr_bytes_hp2;
output wr_dv_ddr_hp2;
input rd_req_ddr_hp2;
input [addr_width-1:0] rd_addr_hp2;
input [max_burst_bytes_width:0] rd_bytes_hp2;
output [max_burst_bits-1:0] rd_data_ddr_hp2;
output rd_dv_ddr_hp2;
output wr_ack_ddr_hp3;
input [max_burst_bits-1:0] wr_data_hp3;
input [addr_width-1:0] wr_addr_hp3;
input [max_burst_bytes_width:0] wr_bytes_hp3;
output wr_dv_ddr_hp3;
input rd_req_ddr_hp3;
input [addr_width-1:0] rd_addr_hp3;
input [max_burst_bytes_width:0] rd_bytes_hp3;
output [max_burst_bits-1:0] rd_data_ddr_hp3;
output rd_dv_ddr_hp3;
input ddr_wr_ack;
output ddr_wr_dv;
output [addr_width-1:0]ddr_wr_addr;
output [max_burst_bits-1:0]ddr_wr_data;
output [max_burst_bytes_width:0]ddr_wr_bytes;
input ddr_rd_dv;
input [max_burst_bits-1:0] ddr_rd_data;
output ddr_rd_req;
output [addr_width-1:0] ddr_rd_addr;
output [max_burst_bytes_width:0] ddr_rd_bytes;
processing_system7_bfm_v2_0_arb_wr ddr_hp_wr(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(w_qos_hp2),
.qos2(w_qos_hp3),
.prt_dv1(wr_dv_ddr_hp2),
.prt_dv2(wr_dv_ddr_hp3),
.prt_data1(wr_data_hp2),
.prt_data2(wr_data_hp3),
.prt_addr1(wr_addr_hp2),
.prt_addr2(wr_addr_hp3),
.prt_bytes1(wr_bytes_hp2),
.prt_bytes2(wr_bytes_hp3),
.prt_ack1(wr_ack_ddr_hp2),
.prt_ack2(wr_ack_ddr_hp3),
.prt_req(ddr_wr_dv),
.prt_qos(ddr_wr_qos),
.prt_data(ddr_wr_data),
.prt_addr(ddr_wr_addr),
.prt_bytes(ddr_wr_bytes),
.prt_ack(ddr_wr_ack)
);
processing_system7_bfm_v2_0_arb_rd ddr_hp_rd(
.rstn(rstn),
.sw_clk(sw_clk),
.qos1(r_qos_hp2),
.qos2(r_qos_hp3),
.prt_req1(rd_req_ddr_hp2),
.prt_req2(rd_req_ddr_hp3),
.prt_data1(rd_data_ddr_hp2),
.prt_data2(rd_data_ddr_hp3),
.prt_addr1(rd_addr_hp2),
.prt_addr2(rd_addr_hp3),
.prt_bytes1(rd_bytes_hp2),
.prt_bytes2(rd_bytes_hp3),
.prt_dv1(rd_dv_ddr_hp2),
.prt_dv2(rd_dv_ddr_hp3),
.prt_req(ddr_rd_req),
.prt_qos(ddr_rd_qos),
.prt_data(ddr_rd_data),
.prt_addr(ddr_rd_addr),
.prt_bytes(ddr_rd_bytes),
.prt_dv(ddr_rd_dv)
);
endmodule
|
/******************************************************************************
-- (c) Copyright 2006 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
*****************************************************************************
*
* Filename: blk_mem_gen_v8_3_5.v
*
* Description:
* This file is the Verilog behvarial model for the
* Block Memory Generator Core.
*
*****************************************************************************
* Author: Xilinx
*
* History: Jan 11, 2006 Initial revision
* Jun 11, 2007 Added independent register stages for
* Port A and Port B (IP1_Jm/v2.5)
* Aug 28, 2007 Added mux pipeline stages feature (IP2_Jm/v2.6)
* Mar 13, 2008 Behavioral model optimizations
* April 07, 2009 : Added support for Spartan-6 and Virtex-6
* features, including the following:
* (i) error injection, detection and/or correction
* (ii) reset priority
* (iii) special reset behavior
*
*****************************************************************************/
`timescale 1ps/1ps
module STATE_LOGIC_v8_3 (O, I0, I1, I2, I3, I4, I5);
parameter INIT = 64'h0000000000000000;
input I0, I1, I2, I3, I4, I5;
output O;
reg O;
reg tmp;
always @( I5 or I4 or I3 or I2 or I1 or I0 ) begin
tmp = I0 ^ I1 ^ I2 ^ I3 ^ I4 ^ I5;
if ( tmp == 0 || tmp == 1)
O = INIT[{I5, I4, I3, I2, I1, I0}];
end
endmodule
module beh_vlog_muxf7_v8_3 (O, I0, I1, S);
output O;
reg O;
input I0, I1, S;
always @(I0 or I1 or S)
if (S)
O = I1;
else
O = I0;
endmodule
module beh_vlog_ff_clr_v8_3 (Q, C, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q<= 1'b0;
else
Q<= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_pre_v8_3 (Q, C, D, PRE);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, D, PRE;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (PRE)
Q <= 1'b1;
else
Q <= #FLOP_DELAY D;
endmodule
module beh_vlog_ff_ce_clr_v8_3 (Q, C, CE, CLR, D);
parameter INIT = 0;
localparam FLOP_DELAY = 100;
output Q;
input C, CE, CLR, D;
reg Q;
initial Q= 1'b0;
always @(posedge C )
if (CLR)
Q <= 1'b0;
else if (CE)
Q <= #FLOP_DELAY D;
endmodule
module write_netlist_v8_3
#(
parameter C_AXI_TYPE = 0
)
(
S_ACLK, S_ARESETN, S_AXI_AWVALID, S_AXI_WVALID, S_AXI_BREADY,
w_last_c, bready_timeout_c, aw_ready_r, S_AXI_WREADY, S_AXI_BVALID,
S_AXI_WR_EN, addr_en_c, incr_addr_c, bvalid_c
);
input S_ACLK;
input S_ARESETN;
input S_AXI_AWVALID;
input S_AXI_WVALID;
input S_AXI_BREADY;
input w_last_c;
input bready_timeout_c;
output aw_ready_r;
output S_AXI_WREADY;
output S_AXI_BVALID;
output S_AXI_WR_EN;
output addr_en_c;
output incr_addr_c;
output bvalid_c;
//-------------------------------------------------------------------------
//AXI LITE
//-------------------------------------------------------------------------
generate if (C_AXI_TYPE == 0 ) begin : gbeh_axi_lite_sm
wire w_ready_r_7;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSignal_bvalid_c;
wire NlwRenamedSignal_incr_addr_c;
wire present_state_FSM_FFd3_13;
wire present_state_FSM_FFd2_14;
wire present_state_FSM_FFd1_15;
wire present_state_FSM_FFd4_16;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd4_In1_21;
wire [0:0] Mmux_aw_ready_c ;
begin
assign
S_AXI_WREADY = w_ready_r_7,
S_AXI_BVALID = NlwRenamedSignal_incr_addr_c,
S_AXI_WR_EN = NlwRenamedSignal_bvalid_c,
incr_addr_c = NlwRenamedSignal_incr_addr_c,
bvalid_c = NlwRenamedSignal_bvalid_c;
assign NlwRenamedSignal_incr_addr_c = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_7)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4 (
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_16)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_13)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_15)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000055554440))
present_state_FSM_FFd3_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088880800))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_AWVALID),
.I1 ( S_AXI_WVALID),
.I2 ( bready_timeout_c),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAA2000))
Mmux_addr_en_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_WVALID),
.I4 ( present_state_FSM_FFd4_16),
.I5 (1'b0),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF5F07570F5F05500))
Mmux_w_ready_c_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd3_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( present_state_FSM_FFd1_15),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1 (
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( present_state_FSM_FFd3_13),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSignal_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h2F0F27072F0F2200))
present_state_FSM_FFd4_In1 (
.I0 ( S_AXI_WVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_13),
.I4 ( present_state_FSM_FFd4_16),
.I5 ( present_state_FSM_FFd2_14),
.O ( present_state_FSM_FFd4_In1_21)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
present_state_FSM_FFd4_In2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_In1_21),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h7535753575305500))
Mmux_aw_ready_c_0_1 (
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_WVALID),
.I3 ( present_state_FSM_FFd4_16),
.I4 ( present_state_FSM_FFd3_13),
.I5 ( present_state_FSM_FFd2_14),
.O ( Mmux_aw_ready_c[0])
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000F8))
Mmux_aw_ready_c_0_2 (
.I0 ( present_state_FSM_FFd1_15),
.I1 ( S_AXI_BREADY),
.I2 ( Mmux_aw_ready_c[0]),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( aw_ready_c)
);
end
end
endgenerate
//---------------------------------------------------------------------
// AXI FULL
//---------------------------------------------------------------------
generate if (C_AXI_TYPE == 1 ) begin : gbeh_axi_full_sm
wire w_ready_r_8;
wire w_ready_c;
wire aw_ready_c;
wire NlwRenamedSig_OI_bvalid_c;
wire present_state_FSM_FFd1_16;
wire present_state_FSM_FFd4_17;
wire present_state_FSM_FFd3_18;
wire present_state_FSM_FFd2_19;
wire present_state_FSM_FFd4_In;
wire present_state_FSM_FFd3_In;
wire present_state_FSM_FFd2_In;
wire present_state_FSM_FFd1_In;
wire present_state_FSM_FFd2_In1_24;
wire present_state_FSM_FFd4_In1_25;
wire N2;
wire N4;
begin
assign
S_AXI_WREADY = w_ready_r_8,
bvalid_c = NlwRenamedSig_OI_bvalid_c,
S_AXI_BVALID = 1'b0;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
aw_ready_r_2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( aw_ready_c),
.Q ( aw_ready_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
w_ready_r
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( w_ready_c),
.Q ( w_ready_r_8)
);
beh_vlog_ff_pre_v8_3 #(
.INIT (1'b1))
present_state_FSM_FFd4
(
.C ( S_ACLK),
.D ( present_state_FSM_FFd4_In),
.PRE ( S_ARESETN),
.Q ( present_state_FSM_FFd4_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd3
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd3_In),
.Q ( present_state_FSM_FFd3_18)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_19)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1
(
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd1_In),
.Q ( present_state_FSM_FFd1_16)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000005540))
present_state_FSM_FFd3_In1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd4_17),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd3_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hBF3FBB33AF0FAA00))
Mmux_aw_ready_c_0_2
(
.I0 ( S_AXI_BREADY),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd1_16),
.I4 ( present_state_FSM_FFd4_17),
.I5 ( NlwRenamedSig_OI_bvalid_c),
.O ( aw_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hAAAAAAAA20000000))
Mmux_addr_en_c_0_1
(
.I0 ( S_AXI_AWVALID),
.I1 ( bready_timeout_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( S_AXI_WVALID),
.I4 ( w_last_c),
.I5 ( present_state_FSM_FFd4_17),
.O ( addr_en_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000A8))
Mmux_S_AXI_WR_EN_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( present_state_FSM_FFd2_19),
.I2 ( present_state_FSM_FFd3_18),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( S_AXI_WR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000002220))
Mmux_incr_addr_c_0_1
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( incr_addr_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000008880))
Mmux_aw_ready_c_0_11
(
.I0 ( S_AXI_WVALID),
.I1 ( w_last_c),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( NlwRenamedSig_OI_bvalid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000D5C0))
present_state_FSM_FFd2_In1
(
.I0 ( w_last_c),
.I1 ( S_AXI_AWVALID),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( present_state_FSM_FFd3_18),
.I4 (1'b0),
.I5 (1'b0),
.O ( present_state_FSM_FFd2_In1_24)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFFFFAAAA08AAAAAA))
present_state_FSM_FFd2_In2
(
.I0 ( present_state_FSM_FFd2_19),
.I1 ( S_AXI_AWVALID),
.I2 ( bready_timeout_c),
.I3 ( w_last_c),
.I4 ( S_AXI_WVALID),
.I5 ( present_state_FSM_FFd2_In1_24),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00C0004000C00000))
present_state_FSM_FFd4_In1
(
.I0 ( S_AXI_AWVALID),
.I1 ( w_last_c),
.I2 ( S_AXI_WVALID),
.I3 ( bready_timeout_c),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( present_state_FSM_FFd4_In1_25)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88F8))
present_state_FSM_FFd4_In2
(
.I0 ( present_state_FSM_FFd1_16),
.I1 ( S_AXI_BREADY),
.I2 ( present_state_FSM_FFd4_17),
.I3 ( S_AXI_AWVALID),
.I4 ( present_state_FSM_FFd4_In1_25),
.I5 (1'b0),
.O ( present_state_FSM_FFd4_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_w_ready_c_0_SW0
(
.I0 ( w_last_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFABAFABAFAAAF000))
Mmux_w_ready_c_0_Q
(
.I0 ( N2),
.I1 ( bready_timeout_c),
.I2 ( S_AXI_AWVALID),
.I3 ( present_state_FSM_FFd4_17),
.I4 ( present_state_FSM_FFd3_18),
.I5 ( present_state_FSM_FFd2_19),
.O ( w_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_aw_ready_c_0_11_SW0
(
.I0 ( bready_timeout_c),
.I1 ( S_AXI_WVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h88808880FFFF8880))
present_state_FSM_FFd1_In1
(
.I0 ( w_last_c),
.I1 ( N4),
.I2 ( present_state_FSM_FFd2_19),
.I3 ( present_state_FSM_FFd3_18),
.I4 ( present_state_FSM_FFd1_16),
.I5 ( S_AXI_BREADY),
.O ( present_state_FSM_FFd1_In)
);
end
end
endgenerate
endmodule
module read_netlist_v8_3 #(
parameter C_AXI_TYPE = 1,
parameter C_ADDRB_WIDTH = 12
) ( S_AXI_R_LAST_INT, S_ACLK, S_ARESETN, S_AXI_ARVALID,
S_AXI_RREADY,S_AXI_INCR_ADDR,S_AXI_ADDR_EN,
S_AXI_SINGLE_TRANS,S_AXI_MUX_SEL, S_AXI_R_LAST, S_AXI_ARREADY,
S_AXI_RLAST, S_AXI_RVALID, S_AXI_RD_EN, S_AXI_ARLEN);
input S_AXI_R_LAST_INT;
input S_ACLK;
input S_ARESETN;
input S_AXI_ARVALID;
input S_AXI_RREADY;
output S_AXI_INCR_ADDR;
output S_AXI_ADDR_EN;
output S_AXI_SINGLE_TRANS;
output S_AXI_MUX_SEL;
output S_AXI_R_LAST;
output S_AXI_ARREADY;
output S_AXI_RLAST;
output S_AXI_RVALID;
output S_AXI_RD_EN;
input [7:0] S_AXI_ARLEN;
wire present_state_FSM_FFd1_13 ;
wire present_state_FSM_FFd2_14 ;
wire gaxi_full_sm_outstanding_read_r_15 ;
wire gaxi_full_sm_ar_ready_r_16 ;
wire gaxi_full_sm_r_last_r_17 ;
wire NlwRenamedSig_OI_gaxi_full_sm_r_valid_r ;
wire gaxi_full_sm_r_valid_c ;
wire S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o ;
wire gaxi_full_sm_ar_ready_c ;
wire gaxi_full_sm_outstanding_read_c ;
wire NlwRenamedSig_OI_S_AXI_R_LAST ;
wire S_AXI_ARLEN_7_GND_8_o_equal_1_o ;
wire present_state_FSM_FFd2_In ;
wire present_state_FSM_FFd1_In ;
wire Mmux_S_AXI_R_LAST13 ;
wire N01 ;
wire N2 ;
wire Mmux_gaxi_full_sm_ar_ready_c11 ;
wire N4 ;
wire N8 ;
wire N9 ;
wire N10 ;
wire N11 ;
wire N12 ;
wire N13 ;
assign
S_AXI_R_LAST = NlwRenamedSig_OI_S_AXI_R_LAST,
S_AXI_ARREADY = gaxi_full_sm_ar_ready_r_16,
S_AXI_RLAST = gaxi_full_sm_r_last_r_17,
S_AXI_RVALID = NlwRenamedSig_OI_gaxi_full_sm_r_valid_r;
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_outstanding_read_r (
.C (S_ACLK),
.CLR(S_ARESETN),
.D(gaxi_full_sm_outstanding_read_c),
.Q(gaxi_full_sm_outstanding_read_r_15)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_r_valid_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (gaxi_full_sm_r_valid_c),
.Q (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
gaxi_full_sm_ar_ready_r (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (gaxi_full_sm_ar_ready_c),
.Q (gaxi_full_sm_ar_ready_r_16)
);
beh_vlog_ff_ce_clr_v8_3 #(
.INIT(1'b0))
gaxi_full_sm_r_last_r (
.C (S_ACLK),
.CE (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.CLR (S_ARESETN),
.D (NlwRenamedSig_OI_S_AXI_R_LAST),
.Q (gaxi_full_sm_r_last_r_17)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd2 (
.C ( S_ACLK),
.CLR ( S_ARESETN),
.D ( present_state_FSM_FFd2_In),
.Q ( present_state_FSM_FFd2_14)
);
beh_vlog_ff_clr_v8_3 #(
.INIT (1'b0))
present_state_FSM_FFd1 (
.C (S_ACLK),
.CLR (S_ARESETN),
.D (present_state_FSM_FFd1_In),
.Q (present_state_FSM_FFd1_13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000000000000B))
S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o1 (
.I0 ( S_AXI_RREADY),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000008))
Mmux_S_AXI_SINGLE_TRANS11 (
.I0 (S_AXI_ARVALID),
.I1 (S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_SINGLE_TRANS)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000004))
Mmux_S_AXI_ADDR_EN11 (
.I0 (present_state_FSM_FFd1_13),
.I1 (S_AXI_ARVALID),
.I2 (1'b0),
.I3 (1'b0),
.I4 (1'b0),
.I5 (1'b0),
.O (S_AXI_ADDR_EN)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hECEE2022EEEE2022))
present_state_FSM_FFd2_In1 (
.I0 ( S_AXI_ARVALID),
.I1 ( present_state_FSM_FFd1_13),
.I2 ( S_AXI_RREADY),
.I3 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.O ( present_state_FSM_FFd2_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000044440444))
Mmux_S_AXI_R_LAST131 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_RREADY),
.I5 (1'b0),
.O ( Mmux_S_AXI_R_LAST13)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h4000FFFF40004000))
Mmux_S_AXI_INCR_ADDR11 (
.I0 ( S_AXI_R_LAST_INT),
.I1 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( Mmux_S_AXI_R_LAST13),
.O ( S_AXI_INCR_ADDR)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000FE))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_SW0 (
.I0 ( S_AXI_ARLEN[2]),
.I1 ( S_AXI_ARLEN[1]),
.I2 ( S_AXI_ARLEN[0]),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N01)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000001))
S_AXI_ARLEN_7_GND_8_o_equal_1_o_7_Q (
.I0 ( S_AXI_ARLEN[7]),
.I1 ( S_AXI_ARLEN[6]),
.I2 ( S_AXI_ARLEN[5]),
.I3 ( S_AXI_ARLEN[4]),
.I4 ( S_AXI_ARLEN[3]),
.I5 ( N01),
.O ( S_AXI_ARLEN_7_GND_8_o_equal_1_o)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000000007))
Mmux_gaxi_full_sm_outstanding_read_c1_SW0 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I2 ( 1'b0),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N2)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0020000002200200))
Mmux_gaxi_full_sm_outstanding_read_c1 (
.I0 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd1_13),
.I3 ( present_state_FSM_FFd2_14),
.I4 ( gaxi_full_sm_outstanding_read_r_15),
.I5 ( N2),
.O ( gaxi_full_sm_outstanding_read_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000000004555))
Mmux_gaxi_full_sm_ar_ready_c12 (
.I0 ( S_AXI_ARVALID),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( Mmux_gaxi_full_sm_ar_ready_c11)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000000000EF))
Mmux_S_AXI_R_LAST11_SW0 (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I3 ( 1'b0),
.I4 ( 1'b0),
.I5 ( 1'b0),
.O ( N4)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hFCAAFC0A00AA000A))
Mmux_S_AXI_R_LAST11 (
.I0 ( S_AXI_ARVALID),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( present_state_FSM_FFd1_13),
.I4 ( N4),
.I5 ( S_AXI_RREADY_gaxi_full_sm_r_valid_r_OR_9_o),
.O ( gaxi_full_sm_r_valid_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000AAAAAA08))
S_AXI_MUX_SEL1 (
.I0 (present_state_FSM_FFd1_13),
.I1 (NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 (S_AXI_RREADY),
.I3 (present_state_FSM_FFd2_14),
.I4 (gaxi_full_sm_outstanding_read_r_15),
.I5 (1'b0),
.O (S_AXI_MUX_SEL)
);
STATE_LOGIC_v8_3 #(
.INIT (64'hF3F3F755A2A2A200))
Mmux_S_AXI_RD_EN11 (
.I0 ( present_state_FSM_FFd1_13),
.I1 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I2 ( S_AXI_RREADY),
.I3 ( gaxi_full_sm_outstanding_read_r_15),
.I4 ( present_state_FSM_FFd2_14),
.I5 ( S_AXI_ARVALID),
.O ( S_AXI_RD_EN)
);
beh_vlog_muxf7_v8_3 present_state_FSM_FFd1_In3 (
.I0 ( N8),
.I1 ( N9),
.S ( present_state_FSM_FFd1_13),
.O ( present_state_FSM_FFd1_In)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000005410F4F0))
present_state_FSM_FFd1_In3_F (
.I0 ( S_AXI_RREADY),
.I1 ( present_state_FSM_FFd2_14),
.I2 ( S_AXI_ARVALID),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I5 ( 1'b0),
.O ( N8)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000072FF7272))
present_state_FSM_FFd1_In3_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N9)
);
beh_vlog_muxf7_v8_3 Mmux_gaxi_full_sm_ar_ready_c14 (
.I0 ( N10),
.I1 ( N11),
.S ( present_state_FSM_FFd1_13),
.O ( gaxi_full_sm_ar_ready_c)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000FFFF88A8))
Mmux_gaxi_full_sm_ar_ready_c14_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_RREADY),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I4 ( Mmux_gaxi_full_sm_ar_ready_c11),
.I5 ( 1'b0),
.O ( N10)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h000000008D008D8D))
Mmux_gaxi_full_sm_ar_ready_c14_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( S_AXI_R_LAST_INT),
.I2 ( gaxi_full_sm_outstanding_read_r_15),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N11)
);
beh_vlog_muxf7_v8_3 Mmux_S_AXI_R_LAST1 (
.I0 ( N12),
.I1 ( N13),
.S ( present_state_FSM_FFd1_13),
.O ( NlwRenamedSig_OI_S_AXI_R_LAST)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h0000000088088888))
Mmux_S_AXI_R_LAST1_F (
.I0 ( S_AXI_ARLEN_7_GND_8_o_equal_1_o),
.I1 ( S_AXI_ARVALID),
.I2 ( present_state_FSM_FFd2_14),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N12)
);
STATE_LOGIC_v8_3 #(
.INIT (64'h00000000E400E4E4))
Mmux_S_AXI_R_LAST1_G (
.I0 ( present_state_FSM_FFd2_14),
.I1 ( gaxi_full_sm_outstanding_read_r_15),
.I2 ( S_AXI_R_LAST_INT),
.I3 ( S_AXI_RREADY),
.I4 ( NlwRenamedSig_OI_gaxi_full_sm_r_valid_r),
.I5 ( 1'b0),
.O ( N13)
);
endmodule
module blk_mem_axi_write_wrapper_beh_v8_3
# (
// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0, // 0: Native Interface; 1: AXI Interface
parameter C_AXI_TYPE = 0, // 0: AXI Lite; 1: AXI Full;
parameter C_AXI_SLAVE_TYPE = 0, // 0: MEMORY SLAVE; 1: PERIPHERAL SLAVE;
parameter C_MEMORY_TYPE = 0, // 0: SP-RAM, 1: SDP-RAM; 2: TDP-RAM; 3: DP-ROM;
parameter C_WRITE_DEPTH_A = 0,
parameter C_AXI_AWADDR_WIDTH = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_WDATA_WIDTH = 32,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
// AXI OUTSTANDING WRITES
parameter C_AXI_OS_WR = 2
)
(
// AXI Global Signals
input S_ACLK,
input S_ARESETN,
// AXI Full/Lite Slave Write Channel (write side)
input [C_AXI_ID_WIDTH-1:0] S_AXI_AWID,
input [C_AXI_AWADDR_WIDTH-1:0] S_AXI_AWADDR,
input [8-1:0] S_AXI_AWLEN,
input [2:0] S_AXI_AWSIZE,
input [1:0] S_AXI_AWBURST,
input S_AXI_AWVALID,
output S_AXI_AWREADY,
input S_AXI_WVALID,
output S_AXI_WREADY,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_BID = 0,
output S_AXI_BVALID,
input S_AXI_BREADY,
// Signals for BMG interface
output [C_ADDRA_WIDTH-1:0] S_AXI_AWADDR_OUT,
output S_AXI_WR_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_AXI_WDATA_WIDTH == 8)?0:
((C_AXI_WDATA_WIDTH==16)?1:
((C_AXI_WDATA_WIDTH==32)?2:
((C_AXI_WDATA_WIDTH==64)?3:
((C_AXI_WDATA_WIDTH==128)?4:
((C_AXI_WDATA_WIDTH==256)?5:0))))));
wire bvalid_c ;
reg bready_timeout_c = 0;
wire [1:0] bvalid_rd_cnt_c;
reg bvalid_r = 0;
reg [2:0] bvalid_count_r = 0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_AWADDR_WIDTH:C_ADDRA_WIDTH)-1:0] awaddr_reg = 0;
reg [1:0] bvalid_wr_cnt_r = 0;
reg [1:0] bvalid_rd_cnt_r = 0;
wire w_last_c ;
wire addr_en_c ;
wire incr_addr_c ;
wire aw_ready_r ;
wire dec_alen_c ;
reg bvalid_d1_c = 0;
reg [7:0] awlen_cntr_r = 0;
reg [7:0] awlen_int = 0;
reg [1:0] awburst_int = 0;
integer total_bytes = 0;
integer wrap_boundary = 0;
integer wrap_base_addr = 0;
integer num_of_bytes_c = 0;
integer num_of_bytes_r = 0;
// Array to store BIDs
reg [C_AXI_ID_WIDTH-1:0] axi_bid_array[3:0] ;
wire S_AXI_BVALID_axi_wr_fsm;
//-------------------------------------
//AXI WRITE FSM COMPONENT INSTANTIATION
//-------------------------------------
write_netlist_v8_3 #(.C_AXI_TYPE(C_AXI_TYPE)) axi_wr_fsm
(
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
.S_AXI_AWVALID(S_AXI_AWVALID),
.aw_ready_r(aw_ready_r),
.S_AXI_WVALID(S_AXI_WVALID),
.S_AXI_WREADY(S_AXI_WREADY),
.S_AXI_BREADY(S_AXI_BREADY),
.S_AXI_WR_EN(S_AXI_WR_EN),
.w_last_c(w_last_c),
.bready_timeout_c(bready_timeout_c),
.addr_en_c(addr_en_c),
.incr_addr_c(incr_addr_c),
.bvalid_c(bvalid_c),
.S_AXI_BVALID (S_AXI_BVALID_axi_wr_fsm)
);
//Wrap Address boundary calculation
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWSIZE:0);
total_bytes = (num_of_bytes_r)*(awlen_int+1);
wrap_base_addr = ((awaddr_reg)/((total_bytes==0)?1:total_bytes))*(total_bytes);
wrap_boundary = wrap_base_addr+total_bytes;
end
//-------------------------------------------------------------------------
// BMG address generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awaddr_reg <= 0;
num_of_bytes_r <= 0;
awburst_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awaddr_reg <= #FLOP_DELAY S_AXI_AWADDR ;
num_of_bytes_r <= num_of_bytes_c;
awburst_int <= ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_AWBURST:2'b01);
end else if (incr_addr_c == 1'b1) begin
if (awburst_int == 2'b10) begin
if(awaddr_reg == (wrap_boundary-num_of_bytes_r)) begin
awaddr_reg <= wrap_base_addr;
end else begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end else if (awburst_int == 2'b01 || awburst_int == 2'b11) begin
awaddr_reg <= awaddr_reg + num_of_bytes_r;
end
end
end
end
assign S_AXI_AWADDR_OUT = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
awaddr_reg[C_AXI_AWADDR_WIDTH-1:C_RANGE]:awaddr_reg);
//-------------------------------------------------------------------------
// AXI wlast generation
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
awlen_cntr_r <= 0;
awlen_int <= 0;
end else begin
if (addr_en_c == 1'b1) begin
awlen_int <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
awlen_cntr_r <= #FLOP_DELAY (C_AXI_TYPE == 0?0:S_AXI_AWLEN) ;
end else if (dec_alen_c == 1'b1) begin
awlen_cntr_r <= #FLOP_DELAY awlen_cntr_r - 1 ;
end
end
end
assign w_last_c = (awlen_cntr_r == 0 && S_AXI_WVALID == 1'b1)?1'b1:1'b0;
assign dec_alen_c = (incr_addr_c | w_last_c);
//-------------------------------------------------------------------------
// Generation of bvalid counter for outstanding transactions
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_count_r <= 0;
end else begin
// bvalid_count_r generation
if (bvalid_c == 1'b1 && bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r ;
end else if (bvalid_c == 1'b1) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r + 1 ;
end else if (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1 && bvalid_count_r != 0) begin
bvalid_count_r <= #FLOP_DELAY bvalid_count_r - 1 ;
end
end
end
//-------------------------------------------------------------------------
// Generation of bvalid when BID is used
//-------------------------------------------------------------------------
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
bvalid_d1_c <= 0;
end else begin
// Delay the generation o bvalid_r for generation for BID
bvalid_d1_c <= bvalid_c;
//external bvalid signal generation
if (bvalid_d1_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of bvalid when BID is not used
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 0) begin:gaxi_bvalid_noid_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_r <= 0;
end else begin
//external bvalid signal generation
if (bvalid_c == 1'b1) begin
bvalid_r <= #FLOP_DELAY 1'b1 ;
end else if (bvalid_count_r <= 1 && S_AXI_BREADY == 1'b1) begin
bvalid_r <= #FLOP_DELAY 0 ;
end
end
end
end
endgenerate
//-------------------------------------------------------------------------
// Generation of Bready timeout
//-------------------------------------------------------------------------
always @(bvalid_count_r) begin
// bready_timeout_c generation
if(bvalid_count_r == C_AXI_OS_WR-1) begin
bready_timeout_c <= 1'b1;
end else begin
bready_timeout_c <= 1'b0;
end
end
//-------------------------------------------------------------------------
// Generation of BID
//-------------------------------------------------------------------------
generate if(C_HAS_AXI_ID == 1) begin:gaxi_bid_gen
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
bvalid_wr_cnt_r <= 0;
bvalid_rd_cnt_r <= 0;
end else begin
// STORE AWID IN AN ARRAY
if(bvalid_c == 1'b1) begin
bvalid_wr_cnt_r <= bvalid_wr_cnt_r + 1;
end
// generate BID FROM AWID ARRAY
bvalid_rd_cnt_r <= #FLOP_DELAY bvalid_rd_cnt_c ;
S_AXI_BID <= axi_bid_array[bvalid_rd_cnt_c];
end
end
assign bvalid_rd_cnt_c = (bvalid_r == 1'b1 && S_AXI_BREADY == 1'b1)?bvalid_rd_cnt_r+1:bvalid_rd_cnt_r;
//-------------------------------------------------------------------------
// Storing AWID for generation of BID
//-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if(S_ARESETN == 1'b1) begin
axi_bid_array[0] = 0;
axi_bid_array[1] = 0;
axi_bid_array[2] = 0;
axi_bid_array[3] = 0;
end else if(aw_ready_r == 1'b1 && S_AXI_AWVALID == 1'b1) begin
axi_bid_array[bvalid_wr_cnt_r] <= S_AXI_AWID;
end
end
end
endgenerate
assign S_AXI_BVALID = bvalid_r;
assign S_AXI_AWREADY = aw_ready_r;
endmodule
module blk_mem_axi_read_wrapper_beh_v8_3
# (
//// AXI Interface related parameters start here
parameter C_INTERFACE_TYPE = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_MEMORY_TYPE = 0,
parameter C_WRITE_WIDTH_A = 4,
parameter C_WRITE_DEPTH_A = 32,
parameter C_ADDRA_WIDTH = 12,
parameter C_AXI_PIPELINE_STAGES = 0,
parameter C_AXI_ARADDR_WIDTH = 12,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_ADDRB_WIDTH = 12
)
(
//// AXI Global Signals
input S_ACLK,
input S_ARESETN,
//// AXI Full/Lite Slave Read (Read side)
input [C_AXI_ARADDR_WIDTH-1:0] S_AXI_ARADDR,
input [7:0] S_AXI_ARLEN,
input [2:0] S_AXI_ARSIZE,
input [1:0] S_AXI_ARBURST,
input S_AXI_ARVALID,
output S_AXI_ARREADY,
output S_AXI_RLAST,
output S_AXI_RVALID,
input S_AXI_RREADY,
input [C_AXI_ID_WIDTH-1:0] S_AXI_ARID,
output reg [C_AXI_ID_WIDTH-1:0] S_AXI_RID = 0,
//// AXI Full/Lite Read Address Signals to BRAM
output [C_ADDRB_WIDTH-1:0] S_AXI_ARADDR_OUT,
output S_AXI_RD_EN
);
localparam FLOP_DELAY = 100; // 100 ps
localparam C_RANGE = ((C_WRITE_WIDTH_A == 8)?0:
((C_WRITE_WIDTH_A==16)?1:
((C_WRITE_WIDTH_A==32)?2:
((C_WRITE_WIDTH_A==64)?3:
((C_WRITE_WIDTH_A==128)?4:
((C_WRITE_WIDTH_A==256)?5:0))))));
reg [C_AXI_ID_WIDTH-1:0] ar_id_r=0;
wire addr_en_c;
wire rd_en_c;
wire incr_addr_c;
wire single_trans_c;
wire dec_alen_c;
wire mux_sel_c;
wire r_last_c;
wire r_last_int_c;
wire [C_ADDRB_WIDTH-1 : 0] araddr_out;
reg [7:0] arlen_int_r=0;
reg [7:0] arlen_cntr=8'h01;
reg [1:0] arburst_int_c=0;
reg [1:0] arburst_int_r=0;
reg [((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?
C_AXI_ARADDR_WIDTH:C_ADDRA_WIDTH)-1:0] araddr_reg =0;
integer num_of_bytes_c = 0;
integer total_bytes = 0;
integer num_of_bytes_r = 0;
integer wrap_base_addr_r = 0;
integer wrap_boundary_r = 0;
reg [7:0] arlen_int_c=0;
integer total_bytes_c = 0;
integer wrap_base_addr_c = 0;
integer wrap_boundary_c = 0;
assign dec_alen_c = incr_addr_c | r_last_int_c;
read_netlist_v8_3
#(.C_AXI_TYPE (1),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_read_fsm (
.S_AXI_INCR_ADDR(incr_addr_c),
.S_AXI_ADDR_EN(addr_en_c),
.S_AXI_SINGLE_TRANS(single_trans_c),
.S_AXI_MUX_SEL(mux_sel_c),
.S_AXI_R_LAST(r_last_c),
.S_AXI_R_LAST_INT(r_last_int_c),
//// AXI Global Signals
.S_ACLK(S_ACLK),
.S_ARESETN(S_ARESETN),
//// AXI Full/Lite Slave Read (Read side)
.S_AXI_ARLEN(S_AXI_ARLEN),
.S_AXI_ARVALID(S_AXI_ARVALID),
.S_AXI_ARREADY(S_AXI_ARREADY),
.S_AXI_RLAST(S_AXI_RLAST),
.S_AXI_RVALID(S_AXI_RVALID),
.S_AXI_RREADY(S_AXI_RREADY),
//// AXI Full/Lite Read Address Signals to BRAM
.S_AXI_RD_EN(rd_en_c)
);
always@(*) begin
num_of_bytes_c = 2**((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARSIZE:0);
total_bytes = (num_of_bytes_r)*(arlen_int_r+1);
wrap_base_addr_r = ((araddr_reg)/(total_bytes==0?1:total_bytes))*(total_bytes);
wrap_boundary_r = wrap_base_addr_r+total_bytes;
//////// combinatorial from interface
arlen_int_c = (C_AXI_TYPE == 0?0:S_AXI_ARLEN);
total_bytes_c = (num_of_bytes_c)*(arlen_int_c+1);
wrap_base_addr_c = ((S_AXI_ARADDR)/(total_bytes_c==0?1:total_bytes_c))*(total_bytes_c);
wrap_boundary_c = wrap_base_addr_c+total_bytes_c;
arburst_int_c = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARBURST:1);
end
////-------------------------------------------------------------------------
//// BMG address generation
////-------------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
araddr_reg <= 0;
arburst_int_r <= 0;
num_of_bytes_r <= 0;
end else begin
if (incr_addr_c == 1'b1 && addr_en_c == 1'b1 && single_trans_c == 1'b0) begin
arburst_int_r <= arburst_int_c;
num_of_bytes_r <= num_of_bytes_c;
if (arburst_int_c == 2'b10) begin
if(S_AXI_ARADDR == (wrap_boundary_c-num_of_bytes_c)) begin
araddr_reg <= wrap_base_addr_c;
end else begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (arburst_int_c == 2'b01 || arburst_int_c == 2'b11) begin
araddr_reg <= S_AXI_ARADDR + num_of_bytes_c;
end
end else if (addr_en_c == 1'b1) begin
araddr_reg <= S_AXI_ARADDR;
num_of_bytes_r <= num_of_bytes_c;
arburst_int_r <= arburst_int_c;
end else if (incr_addr_c == 1'b1) begin
if (arburst_int_r == 2'b10) begin
if(araddr_reg == (wrap_boundary_r-num_of_bytes_r)) begin
araddr_reg <= wrap_base_addr_r;
end else begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end else if (arburst_int_r == 2'b01 || arburst_int_r == 2'b11) begin
araddr_reg <= araddr_reg + num_of_bytes_r;
end
end
end
end
assign araddr_out = ((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?araddr_reg[C_AXI_ARADDR_WIDTH-1:C_RANGE]:araddr_reg);
////-----------------------------------------------------------------------
//// Counter to generate r_last_int_c from registered ARLEN - AXI FULL FSM
////-----------------------------------------------------------------------
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
arlen_cntr <= 8'h01;
arlen_int_r <= 0;
end else begin
if (addr_en_c == 1'b1 && dec_alen_c == 1'b1 && single_trans_c == 1'b0) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= S_AXI_ARLEN - 1'b1;
end else if (addr_en_c == 1'b1) begin
arlen_int_r <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
arlen_cntr <= (C_AXI_TYPE == 0?0:S_AXI_ARLEN) ;
end else if (dec_alen_c == 1'b1) begin
arlen_cntr <= arlen_cntr - 1'b1 ;
end
else begin
arlen_cntr <= arlen_cntr;
end
end
end
assign r_last_int_c = (arlen_cntr == 0 && S_AXI_RREADY == 1'b1)?1'b1:1'b0;
////------------------------------------------------------------------------
//// AXI FULL FSM
//// Mux Selection of ARADDR
//// ARADDR is driven out from the read fsm based on the mux_sel_c
//// Based on mux_sel either ARADDR is given out or the latched ARADDR is
//// given out to BRAM
////------------------------------------------------------------------------
assign S_AXI_ARADDR_OUT = (mux_sel_c == 1'b0)?((C_AXI_TYPE == 1 && C_AXI_SLAVE_TYPE == 0)?S_AXI_ARADDR[C_AXI_ARADDR_WIDTH-1:C_RANGE]:S_AXI_ARADDR):araddr_out;
////------------------------------------------------------------------------
//// Assign output signals - AXI FULL FSM
////------------------------------------------------------------------------
assign S_AXI_RD_EN = rd_en_c;
generate if (C_HAS_AXI_ID == 1) begin:gaxi_bvalid_id_r
always @(posedge S_ACLK or S_ARESETN) begin
if (S_ARESETN == 1'b1) begin
S_AXI_RID <= 0;
ar_id_r <= 0;
end else begin
if (addr_en_c == 1'b1 && rd_en_c == 1'b1) begin
S_AXI_RID <= S_AXI_ARID;
ar_id_r <= S_AXI_ARID;
end else if (addr_en_c == 1'b1 && rd_en_c == 1'b0) begin
ar_id_r <= S_AXI_ARID;
end else if (rd_en_c == 1'b1) begin
S_AXI_RID <= ar_id_r;
end
end
end
end
endgenerate
endmodule
module blk_mem_axi_regs_fwd_v8_3
#(parameter C_DATA_WIDTH = 8
)(
input ACLK,
input ARESET,
input S_VALID,
output S_READY,
input [C_DATA_WIDTH-1:0] S_PAYLOAD_DATA,
output M_VALID,
input M_READY,
output reg [C_DATA_WIDTH-1:0] M_PAYLOAD_DATA
);
reg [C_DATA_WIDTH-1:0] STORAGE_DATA;
wire S_READY_I;
reg M_VALID_I;
reg [1:0] ARESET_D;
//assign local signal to its output signal
assign S_READY = S_READY_I;
assign M_VALID = M_VALID_I;
always @(posedge ACLK) begin
ARESET_D <= {ARESET_D[0], ARESET};
end
//Save payload data whenever we have a transaction on the slave side
always @(posedge ACLK or ARESET) begin
if (ARESET == 1'b1) begin
STORAGE_DATA <= 0;
end else begin
if(S_VALID == 1'b1 && S_READY_I == 1'b1 ) begin
STORAGE_DATA <= S_PAYLOAD_DATA;
end
end
end
always @(posedge ACLK) begin
M_PAYLOAD_DATA = STORAGE_DATA;
end
//M_Valid set to high when we have a completed transfer on slave side
//Is removed on a M_READY except if we have a new transfer on the slave side
always @(posedge ACLK or ARESET_D) begin
if (ARESET_D != 2'b00) begin
M_VALID_I <= 1'b0;
end else begin
if (S_VALID == 1'b1) begin
//Always set M_VALID_I when slave side is valid
M_VALID_I <= 1'b1;
end else if (M_READY == 1'b1 ) begin
//Clear (or keep) when no slave side is valid but master side is ready
M_VALID_I <= 1'b0;
end
end
end
//Slave Ready is either when Master side drives M_READY or we have space in our storage data
assign S_READY_I = (M_READY || (!M_VALID_I)) && !(|(ARESET_D));
endmodule
//*****************************************************************************
// Output Register Stage module
//
// This module builds the output register stages of the memory. This module is
// instantiated in the main memory module (blk_mem_gen_v8_3_5) which is
// declared/implemented further down in this file.
//*****************************************************************************
module blk_mem_gen_v8_3_5_output_stage
#(parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RST = 0,
parameter C_RSTRAM = 0,
parameter C_RST_PRIORITY = "CE",
parameter C_INIT_VAL = "0",
parameter C_HAS_EN = 0,
parameter C_HAS_REGCE = 0,
parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_MEM_OUTPUT_REGS = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter NUM_STAGES = 1,
parameter C_EN_ECC_PIPE = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input RST,
input EN,
input REGCE,
input [C_DATA_WIDTH-1:0] DIN_I,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN_I,
input DBITERR_IN_I,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN_I,
input ECCPIPECE,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RST : Determines the presence of the RST port
// C_RSTRAM : Determines if special reset behavior is used
// C_RST_PRIORITY : Determines the priority between CE and SR
// C_INIT_VAL : Initialization value
// C_HAS_EN : Determines the presence of the EN port
// C_HAS_REGCE : Determines the presence of the REGCE port
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// NUM_STAGES : Determines the number of output stages
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// RST : Reset input to reset memory outputs to a user-defined
// reset state
// EN : Enable all read and write operations
// REGCE : Register Clock Enable to control each pipeline output
// register stages
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
// Fix for CR-509792
localparam REG_STAGES = (NUM_STAGES < 2) ? 1 : NUM_STAGES-1;
// Declare the pipeline registers
// (includes mem output reg, mux pipeline stages, and mux output reg)
reg [C_DATA_WIDTH*REG_STAGES-1:0] out_regs;
reg [C_ADDRB_WIDTH*REG_STAGES-1:0] rdaddrecc_regs;
reg [REG_STAGES-1:0] sbiterr_regs;
reg [REG_STAGES-1:0] dbiterr_regs;
reg [C_DATA_WIDTH*8-1:0] init_str = C_INIT_VAL;
reg [C_DATA_WIDTH-1:0] init_val ;
//*********************************************
// Wire off optional inputs based on parameters
//*********************************************
wire en_i;
wire regce_i;
wire rst_i;
// Internal signals
reg [C_DATA_WIDTH-1:0] DIN;
reg [C_ADDRB_WIDTH-1:0] RDADDRECC_IN;
reg SBITERR_IN;
reg DBITERR_IN;
// Internal enable for output registers is tied to user EN or '1' depending
// on parameters
assign en_i = (C_HAS_EN==0 || EN);
// Internal register enable for output registers is tied to user REGCE, EN or
// '1' depending on parameters
// For V4 ECC, REGCE is always 1
// Virtex-4 ECC Not Yet Supported
assign regce_i = ((C_HAS_REGCE==1) && REGCE) ||
((C_HAS_REGCE==0) && (C_HAS_EN==0 || EN));
//Internal SRR is tied to user RST or '0' depending on parameters
assign rst_i = (C_HAS_RST==1) && RST;
//****************************************************
// Power on: load up the output registers and latches
//****************************************************
initial begin
if (!($sscanf(init_str, "%h", init_val))) begin
init_val = 0;
end
DOUT = init_val;
RDADDRECC = 0;
SBITERR = 1'b0;
DBITERR = 1'b0;
DIN = {(C_DATA_WIDTH){1'b0}};
RDADDRECC_IN = 0;
SBITERR_IN = 0;
DBITERR_IN = 0;
// This will be one wider than need, but 0 is an error
out_regs = {(REG_STAGES+1){init_val}};
rdaddrecc_regs = 0;
sbiterr_regs = {(REG_STAGES+1){1'b0}};
dbiterr_regs = {(REG_STAGES+1){1'b0}};
end
//***********************************************
// NUM_STAGES = 0 (No output registers. RAM only)
//***********************************************
generate if (NUM_STAGES == 0) begin : zero_stages
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 0) begin : no_ecc_pipe_reg
always @* begin
DIN = DIN_I;
SBITERR_IN = SBITERR_IN_I;
DBITERR_IN = DBITERR_IN_I;
RDADDRECC_IN = RDADDRECC_IN_I;
end
end
endgenerate
generate if (C_EN_ECC_PIPE == 1) begin : with_ecc_pipe_reg
always @(posedge CLK) begin
if(ECCPIPECE == 1) begin
DIN <= #FLOP_DELAY DIN_I;
SBITERR_IN <= #FLOP_DELAY SBITERR_IN_I;
DBITERR_IN <= #FLOP_DELAY DBITERR_IN_I;
RDADDRECC_IN <= #FLOP_DELAY RDADDRECC_IN_I;
end
end
end
endgenerate
//***********************************************
// NUM_STAGES = 1
// (Mem Output Reg only or Mux Output Reg only)
//***********************************************
// Possible valid combinations:
// Note: C_HAS_MUX_OUTPUT_REGS_*=0 when (C_RSTRAM_*=1)
// +-----------------------------------------+
// | C_RSTRAM_* | Reset Behavior |
// +----------------+------------------------+
// | 0 | Normal Behavior |
// +----------------+------------------------+
// | 1 | Special Behavior |
// +----------------+------------------------+
//
// Normal = REGCE gates reset, as in the case of all families except S3ADSP.
// Special = EN gates reset, as in the case of S3ADSP.
generate if (NUM_STAGES == 1 &&
(C_RSTRAM == 0 || (C_RSTRAM == 1 && (C_XDEVICEFAMILY != "spartan3adsp" && C_XDEVICEFAMILY != "aspartan3adsp" )) ||
C_HAS_MEM_OUTPUT_REGS == 0 || C_HAS_RST == 0))
begin : one_stages_norm
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY DIN;
RDADDRECC <= #FLOP_DELAY RDADDRECC_IN;
SBITERR <= #FLOP_DELAY SBITERR_IN;
DBITERR <= #FLOP_DELAY DBITERR_IN;
end //Output signal assignments
end //end Priority conditions
end //end RST Type conditions
end //end one_stages_norm generate statement
endgenerate
// Special Reset Behavior for S3ADSP
generate if (NUM_STAGES == 1 && C_RSTRAM == 1 && (C_XDEVICEFAMILY =="spartan3adsp" || C_XDEVICEFAMILY =="aspartan3adsp"))
begin : one_stage_splbhv
always @(posedge CLK) begin
if (en_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
end else if (regce_i && !rst_i) begin
DOUT <= #FLOP_DELAY DIN;
end //Output signal assignments
end //end CLK
end //end one_stage_splbhv generate statement
endgenerate
//************************************************************
// NUM_STAGES > 1
// Mem Output Reg + Mux Output Reg
// or
// Mem Output Reg + Mux Pipeline Stages (>0) + Mux Output Reg
// or
// Mux Pipeline Stages (>0) + Mux Output Reg
//*************************************************************
generate if (NUM_STAGES > 1) begin : multi_stage
//Asynchronous Reset
always @(posedge CLK) begin
if (C_RST_PRIORITY == "CE") begin //REGCE has priority
if (regce_i && rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end else begin //RST has priority
if (rst_i) begin
DOUT <= #FLOP_DELAY init_val;
RDADDRECC <= #FLOP_DELAY 0;
SBITERR <= #FLOP_DELAY 1'b0;
DBITERR <= #FLOP_DELAY 1'b0;
end else if (regce_i) begin
DOUT <= #FLOP_DELAY
out_regs[C_DATA_WIDTH*(NUM_STAGES-2)+:C_DATA_WIDTH];
RDADDRECC <= #FLOP_DELAY rdaddrecc_regs[C_ADDRB_WIDTH*(NUM_STAGES-2)+:C_ADDRB_WIDTH];
SBITERR <= #FLOP_DELAY sbiterr_regs[NUM_STAGES-2];
DBITERR <= #FLOP_DELAY dbiterr_regs[NUM_STAGES-2];
end //Output signal assignments
end //end Priority conditions
// Shift the data through the output stages
if (en_i) begin
out_regs <= #FLOP_DELAY (out_regs << C_DATA_WIDTH) | DIN;
rdaddrecc_regs <= #FLOP_DELAY (rdaddrecc_regs << C_ADDRB_WIDTH) | RDADDRECC_IN;
sbiterr_regs <= #FLOP_DELAY (sbiterr_regs << 1) | SBITERR_IN;
dbiterr_regs <= #FLOP_DELAY (dbiterr_regs << 1) | DBITERR_IN;
end
end //end CLK
end //end multi_stage generate statement
endgenerate
endmodule
module blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(parameter C_DATA_WIDTH = 32,
parameter C_ADDRB_WIDTH = 10,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_USE_SOFTECC = 0,
parameter FLOP_DELAY = 100
)
(
input CLK,
input [C_DATA_WIDTH-1:0] DIN,
output reg [C_DATA_WIDTH-1:0] DOUT,
input SBITERR_IN,
input DBITERR_IN,
output reg SBITERR,
output reg DBITERR,
input [C_ADDRB_WIDTH-1:0] RDADDRECC_IN,
output reg [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_DATA_WIDTH : Memory write/read width
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_SOFTECC_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// FLOP_DELAY : Constant delay for register assignments
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLK : Clock to synchronize all read and write operations
// DIN : Data input to the Output stage.
// DOUT : Final Data output
// SBITERR_IN : SBITERR input signal to the Output stage.
// SBITERR : Final SBITERR Output signal.
// DBITERR_IN : DBITERR input signal to the Output stage.
// DBITERR : Final DBITERR Output signal.
// RDADDRECC_IN : RDADDRECC input signal to the Output stage.
// RDADDRECC : Final RDADDRECC Output signal.
//////////////////////////////////////////////////////////////////////////
reg [C_DATA_WIDTH-1:0] dout_i = 0;
reg sbiterr_i = 0;
reg dbiterr_i = 0;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_i = 0;
//***********************************************
// NO OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==0) begin : no_output_stage
always @* begin
DOUT = DIN;
RDADDRECC = RDADDRECC_IN;
SBITERR = SBITERR_IN;
DBITERR = DBITERR_IN;
end
end
endgenerate
//***********************************************
// WITH OUTPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_OUTPUT_REGS_B==1) begin : has_output_stage
always @(posedge CLK) begin
dout_i <= #FLOP_DELAY DIN;
rdaddrecc_i <= #FLOP_DELAY RDADDRECC_IN;
sbiterr_i <= #FLOP_DELAY SBITERR_IN;
dbiterr_i <= #FLOP_DELAY DBITERR_IN;
end
always @* begin
DOUT = dout_i;
RDADDRECC = rdaddrecc_i;
SBITERR = sbiterr_i;
DBITERR = dbiterr_i;
end //end always
end //end in_or_out_stage generate statement
endgenerate
endmodule
//*****************************************************************************
// Main Memory module
//
// This module is the top-level behavioral model and this implements the RAM
//*****************************************************************************
module blk_mem_gen_v8_3_5_mem_module
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter FLOP_DELAY = 100,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input CLKA,
input RSTA,
input ENA,
input REGCEA,
input [C_WEA_WIDTH-1:0] WEA,
input [C_ADDRA_WIDTH-1:0] ADDRA,
input [C_WRITE_WIDTH_A-1:0] DINA,
output [C_READ_WIDTH_A-1:0] DOUTA,
input CLKB,
input RSTB,
input ENB,
input REGCEB,
input [C_WEB_WIDTH-1:0] WEB,
input [C_ADDRB_WIDTH-1:0] ADDRB,
input [C_WRITE_WIDTH_B-1:0] DINB,
output [C_READ_WIDTH_B-1:0] DOUTB,
input INJECTSBITERR,
input INJECTDBITERR,
input ECCPIPECE,
input SLEEP,
output SBITERR,
output DBITERR,
output [C_ADDRB_WIDTH-1:0] RDADDRECC
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
// Note: C_CORENAME parameter is hard-coded to "blk_mem_gen_v8_3_5" and it is
// only used by this module to print warning messages. It is neither passed
// down from blk_mem_gen_v8_3_5_xst.v nor present in the instantiation template
// coregen generates
//***************************************************************************
// constants for the core behavior
//***************************************************************************
// file handles for logging
//--------------------------------------------------
localparam ADDRFILE = 32'h8000_0001; //stdout for addr out of range
localparam COLLFILE = 32'h8000_0001; //stdout for coll detection
localparam ERRFILE = 32'h8000_0001; //stdout for file I/O errors
// other constants
//--------------------------------------------------
localparam COLL_DELAY = 100; // 100 ps
// locally derived parameters to determine memory shape
//-----------------------------------------------------
localparam CHKBIT_WIDTH = (C_WRITE_WIDTH_A>57 ? 8 : (C_WRITE_WIDTH_A>26 ? 7 : (C_WRITE_WIDTH_A>11 ? 6 : (C_WRITE_WIDTH_A>4 ? 5 : (C_WRITE_WIDTH_A<5 ? 4 :0)))));
localparam MIN_WIDTH_A = (C_WRITE_WIDTH_A < C_READ_WIDTH_A) ?
C_WRITE_WIDTH_A : C_READ_WIDTH_A;
localparam MIN_WIDTH_B = (C_WRITE_WIDTH_B < C_READ_WIDTH_B) ?
C_WRITE_WIDTH_B : C_READ_WIDTH_B;
localparam MIN_WIDTH = (MIN_WIDTH_A < MIN_WIDTH_B) ?
MIN_WIDTH_A : MIN_WIDTH_B;
localparam MAX_DEPTH_A = (C_WRITE_DEPTH_A > C_READ_DEPTH_A) ?
C_WRITE_DEPTH_A : C_READ_DEPTH_A;
localparam MAX_DEPTH_B = (C_WRITE_DEPTH_B > C_READ_DEPTH_B) ?
C_WRITE_DEPTH_B : C_READ_DEPTH_B;
localparam MAX_DEPTH = (MAX_DEPTH_A > MAX_DEPTH_B) ?
MAX_DEPTH_A : MAX_DEPTH_B;
// locally derived parameters to assist memory access
//----------------------------------------------------
// Calculate the width ratios of each port with respect to the narrowest
// port
localparam WRITE_WIDTH_RATIO_A = C_WRITE_WIDTH_A/MIN_WIDTH;
localparam READ_WIDTH_RATIO_A = C_READ_WIDTH_A/MIN_WIDTH;
localparam WRITE_WIDTH_RATIO_B = C_WRITE_WIDTH_B/MIN_WIDTH;
localparam READ_WIDTH_RATIO_B = C_READ_WIDTH_B/MIN_WIDTH;
// To modify the LSBs of the 'wider' data to the actual
// address value
//----------------------------------------------------
localparam WRITE_ADDR_A_DIV = C_WRITE_WIDTH_A/MIN_WIDTH_A;
localparam READ_ADDR_A_DIV = C_READ_WIDTH_A/MIN_WIDTH_A;
localparam WRITE_ADDR_B_DIV = C_WRITE_WIDTH_B/MIN_WIDTH_B;
localparam READ_ADDR_B_DIV = C_READ_WIDTH_B/MIN_WIDTH_B;
// If byte writes aren't being used, make sure BYTE_SIZE is not
// wider than the memory elements to avoid compilation warnings
localparam BYTE_SIZE = (C_BYTE_SIZE < MIN_WIDTH) ? C_BYTE_SIZE : MIN_WIDTH;
// The memory
reg [MIN_WIDTH-1:0] memory [0:MAX_DEPTH-1];
reg [MIN_WIDTH-1:0] temp_mem_array [0:MAX_DEPTH-1];
reg [C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:0] doublebit_error = 3;
// ECC error arrays
reg sbiterr_arr [0:MAX_DEPTH-1];
reg dbiterr_arr [0:MAX_DEPTH-1];
reg softecc_sbiterr_arr [0:MAX_DEPTH-1];
reg softecc_dbiterr_arr [0:MAX_DEPTH-1];
// Memory output 'latches'
reg [C_READ_WIDTH_A-1:0] memory_out_a;
reg [C_READ_WIDTH_B-1:0] memory_out_b;
// ECC error inputs and outputs from output_stage module:
reg sbiterr_in;
wire sbiterr_sdp;
reg dbiterr_in;
wire dbiterr_sdp;
wire [C_READ_WIDTH_B-1:0] dout_i;
wire dbiterr_i;
wire sbiterr_i;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_i;
reg [C_ADDRB_WIDTH-1:0] rdaddrecc_in;
wire [C_ADDRB_WIDTH-1:0] rdaddrecc_sdp;
// Reset values
reg [C_READ_WIDTH_A-1:0] inita_val;
reg [C_READ_WIDTH_B-1:0] initb_val;
// Collision detect
reg is_collision;
reg is_collision_a, is_collision_delay_a;
reg is_collision_b, is_collision_delay_b;
// Temporary variables for initialization
//---------------------------------------
integer status;
integer initfile;
integer meminitfile;
// data input buffer
reg [C_WRITE_WIDTH_A-1:0] mif_data;
reg [C_WRITE_WIDTH_A-1:0] mem_data;
// string values in hex
reg [C_READ_WIDTH_A*8-1:0] inita_str = C_INITA_VAL;
reg [C_READ_WIDTH_B*8-1:0] initb_str = C_INITB_VAL;
reg [C_WRITE_WIDTH_A*8-1:0] default_data_str = C_DEFAULT_DATA;
// initialization filename
reg [1023*8-1:0] init_file_str = C_INIT_FILE_NAME;
reg [1023*8-1:0] mem_init_file_str = C_INIT_FILE;
//Constants used to calculate the effective address widths for each of the
//four ports.
integer cnt = 1;
integer write_addr_a_width, read_addr_a_width;
integer write_addr_b_width, read_addr_b_width;
localparam C_FAMILY_LOCALPARAM = (C_FAMILY=="zynquplus"?"virtex7":(C_FAMILY=="kintexuplus"?"virtex7":(C_FAMILY=="virtexuplus"?"virtex7":(C_FAMILY=="virtexu"?"virtex7":(C_FAMILY=="kintexu" ? "virtex7":(C_FAMILY=="virtex7" ? "virtex7" : (C_FAMILY=="virtex7l" ? "virtex7" : (C_FAMILY=="qvirtex7" ? "virtex7" : (C_FAMILY=="qvirtex7l" ? "virtex7" : (C_FAMILY=="kintex7" ? "virtex7" : (C_FAMILY=="kintex7l" ? "virtex7" : (C_FAMILY=="qkintex7" ? "virtex7" : (C_FAMILY=="qkintex7l" ? "virtex7" : (C_FAMILY=="artix7" ? "virtex7" : (C_FAMILY=="artix7l" ? "virtex7" : (C_FAMILY=="qartix7" ? "virtex7" : (C_FAMILY=="qartix7l" ? "virtex7" : (C_FAMILY=="aartix7" ? "virtex7" : (C_FAMILY=="zynq" ? "virtex7" : (C_FAMILY=="azynq" ? "virtex7" : (C_FAMILY=="qzynq" ? "virtex7" : C_FAMILY)))))))))))))))))))));
// Internal configuration parameters
//---------------------------------------------
localparam SINGLE_PORT = (C_MEM_TYPE==0 || C_MEM_TYPE==3);
localparam IS_ROM = (C_MEM_TYPE==3 || C_MEM_TYPE==4);
localparam HAS_A_WRITE = (!IS_ROM);
localparam HAS_B_WRITE = (C_MEM_TYPE==2);
localparam HAS_A_READ = (C_MEM_TYPE!=1);
localparam HAS_B_READ = (!SINGLE_PORT);
localparam HAS_B_PORT = (HAS_B_READ || HAS_B_WRITE);
// Calculate the mux pipeline register stages for Port A and Port B
//------------------------------------------------------------------
localparam MUX_PIPELINE_STAGES_A = (C_HAS_MUX_OUTPUT_REGS_A) ?
C_MUX_PIPELINE_STAGES : 0;
localparam MUX_PIPELINE_STAGES_B = (C_HAS_MUX_OUTPUT_REGS_B) ?
C_MUX_PIPELINE_STAGES : 0;
// Calculate total number of register stages in the core
// -----------------------------------------------------
localparam NUM_OUTPUT_STAGES_A = (C_HAS_MEM_OUTPUT_REGS_A+MUX_PIPELINE_STAGES_A+C_HAS_MUX_OUTPUT_REGS_A);
localparam NUM_OUTPUT_STAGES_B = (C_HAS_MEM_OUTPUT_REGS_B+MUX_PIPELINE_STAGES_B+C_HAS_MUX_OUTPUT_REGS_B);
wire ena_i;
wire enb_i;
wire reseta_i;
wire resetb_i;
wire [C_WEA_WIDTH-1:0] wea_i;
wire [C_WEB_WIDTH-1:0] web_i;
wire rea_i;
wire reb_i;
wire rsta_outp_stage;
wire rstb_outp_stage;
// ECC SBITERR/DBITERR Outputs
// The ECC Behavior is modeled by the behavioral models only for Virtex-6.
// For Virtex-5, these outputs will be tied to 0.
assign SBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?sbiterr_sdp:0;
assign DBITERR = ((C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?dbiterr_sdp:0;
assign RDADDRECC = (((C_FAMILY_LOCALPARAM == "virtex7") && C_MEM_TYPE == 1 && C_USE_ECC == 1) || C_USE_SOFTECC == 1)?rdaddrecc_sdp:0;
// This effectively wires off optional inputs
assign ena_i = (C_HAS_ENA==0) || ENA;
assign enb_i = ((C_HAS_ENB==0) || ENB) && HAS_B_PORT;
// To match RTL : In RTL, write enable of the primitive is tied to all 1's and
// the enable of the primitive is ANDing of wea(0) and ena. so eventually, the
// write operation depends on both enable and write enable. So, the below code
// which is actually doing the write operation only on enable ignoring the wea
// is removed to be in consistent with RTL.
// To Fix CR855535 (The fix to this CR is reverted to match RTL)
//assign wea_i = (HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 1 && ENA == 1) ? 'b1 :(HAS_A_WRITE == 1 && C_MEM_TYPE == 1 &&C_USE_ECC == 1 && C_HAS_ENA == 0) ? WEA : (HAS_A_WRITE && ena_i && C_USE_ECC == 0) ? WEA : 'b0;
assign wea_i = (HAS_A_WRITE && ena_i) ? WEA : 'b0;
assign web_i = (HAS_B_WRITE && enb_i) ? WEB : 'b0;
assign rea_i = (HAS_A_READ) ? ena_i : 'b0;
assign reb_i = (HAS_B_READ) ? enb_i : 'b0;
// These signals reset the memory latches
assign reseta_i =
((C_HAS_RSTA==1 && RSTA && NUM_OUTPUT_STAGES_A==0) ||
(C_HAS_RSTA==1 && RSTA && C_RSTRAM_A==1));
assign resetb_i =
((C_HAS_RSTB==1 && RSTB && NUM_OUTPUT_STAGES_B==0) ||
(C_HAS_RSTB==1 && RSTB && C_RSTRAM_B==1));
// Tasks to access the memory
//---------------------------
//**************
// write_a
//**************
task write_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg [C_WEA_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_A-1:0] data,
input inj_sbiterr,
input inj_dbiterr);
reg [C_WRITE_WIDTH_A-1:0] current_contents;
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_A_DIV);
if (address >= C_WRITE_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEA) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_A + i];
end
end
// Apply incoming bytes
if (C_WEA_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEA_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Insert double bit errors:
if (C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
// Modified for Implementing CR_859399
current_contents[0] = !(current_contents[30]);
current_contents[1] = !(current_contents[62]);
/*current_contents[0] = !(current_contents[0]);
current_contents[1] = !(current_contents[1]);*/
end
end
// Insert softecc double bit errors:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1:2] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-3:0];
doublebit_error[0] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-1];
doublebit_error[1] = doublebit_error[C_WRITE_WIDTH_A+CHKBIT_WIDTH-2];
current_contents = current_contents ^ doublebit_error[C_WRITE_WIDTH_A-1:0];
end
end
// Write data to memory
if (WRITE_WIDTH_RATIO_A == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_A] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_A; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_A + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
// Store the address at which error is injected:
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
sbiterr_arr[addr] = 1;
end else begin
sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
dbiterr_arr[addr] = 1;
end else begin
dbiterr_arr[addr] = 0;
end
end
// Store the address at which softecc error is injected:
if (C_USE_SOFTECC == 1) begin
if ((C_HAS_INJECTERR == 1 && inj_sbiterr == 1'b1) ||
(C_HAS_INJECTERR == 3 && inj_sbiterr == 1'b1 && inj_dbiterr != 1'b1))
begin
softecc_sbiterr_arr[addr] = 1;
end else begin
softecc_sbiterr_arr[addr] = 0;
end
if ((C_HAS_INJECTERR == 2 || C_HAS_INJECTERR == 3) && inj_dbiterr == 1'b1) begin
softecc_dbiterr_arr[addr] = 1;
end else begin
softecc_dbiterr_arr[addr] = 0;
end
end
end
end
endtask
//**************
// write_b
//**************
task write_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg [C_WEB_WIDTH-1:0] byte_en,
input reg [C_WRITE_WIDTH_B-1:0] data);
reg [C_WRITE_WIDTH_B-1:0] current_contents;
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
// Shift the address by the ratio
address = (addr/WRITE_ADDR_B_DIV);
if (address >= C_WRITE_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Write",
C_CORENAME, addr);
end
// valid address
end else begin
// Combine w/ byte writes
if (C_USE_BYTE_WEB) begin
// Get the current memory contents
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
current_contents = memory[address];
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
current_contents[MIN_WIDTH*i+:MIN_WIDTH]
= memory[address*WRITE_WIDTH_RATIO_B + i];
end
end
// Apply incoming bytes
if (C_WEB_WIDTH == 1) begin
// Workaround for IUS 5.5 part-select issue
if (byte_en[0]) begin
current_contents = data;
end
end else begin
for (i = 0; i < C_WEB_WIDTH; i = i + 1) begin
if (byte_en[i]) begin
current_contents[BYTE_SIZE*i+:BYTE_SIZE]
= data[BYTE_SIZE*i+:BYTE_SIZE];
end
end
end
// No byte-writes, overwrite the whole word
end else begin
current_contents = data;
end
// Write data to memory
if (WRITE_WIDTH_RATIO_B == 1) begin
// Workaround for IUS 5.5 part-select issue
memory[address*WRITE_WIDTH_RATIO_B] = current_contents;
end else begin
for (i = 0; i < WRITE_WIDTH_RATIO_B; i = i + 1) begin
memory[address*WRITE_WIDTH_RATIO_B + i]
= current_contents[MIN_WIDTH*i+:MIN_WIDTH];
end
end
end
end
endtask
//**************
// read_a
//**************
task read_a
(input reg [C_ADDRA_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRA_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_a <= #FLOP_DELAY inita_val;
end else begin
// Shift the address by the ratio
address = (addr/READ_ADDR_A_DIV);
if (address >= C_READ_DEPTH_A) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for A Read",
C_CORENAME, addr);
end
memory_out_a <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_A==1) begin
memory_out_a <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_A; i = i + 1) begin
memory_out_a[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_A + i];
end
end //end READ_WIDTH_RATIO_A==1 loop
end //end valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// read_b
//**************
task read_b
(input reg [C_ADDRB_WIDTH-1:0] addr,
input reg reset);
reg [C_ADDRB_WIDTH-1:0] address;
integer i;
begin
if (reset) begin
memory_out_b <= #FLOP_DELAY initb_val;
sbiterr_in <= #FLOP_DELAY 1'b0;
dbiterr_in <= #FLOP_DELAY 1'b0;
rdaddrecc_in <= #FLOP_DELAY 0;
end else begin
// Shift the address
address = (addr/READ_ADDR_B_DIV);
if (address >= C_READ_DEPTH_B) begin
if (!C_DISABLE_WARN_BHV_RANGE) begin
$fdisplay(ADDRFILE,
"%0s WARNING: Address %0h is outside range for B Read",
C_CORENAME, addr);
end
memory_out_b <= #FLOP_DELAY 'bX;
sbiterr_in <= #FLOP_DELAY 1'bX;
dbiterr_in <= #FLOP_DELAY 1'bX;
rdaddrecc_in <= #FLOP_DELAY 'bX;
// valid address
end else begin
if (READ_WIDTH_RATIO_B==1) begin
memory_out_b <= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B];
end else begin
// Increment through the 'partial' words in the memory
for (i = 0; i < READ_WIDTH_RATIO_B; i = i + 1) begin
memory_out_b[MIN_WIDTH*i+:MIN_WIDTH]
<= #FLOP_DELAY memory[address*READ_WIDTH_RATIO_B + i];
end
end
if ((C_FAMILY_LOCALPARAM == "virtex7") && C_USE_ECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else if (C_USE_SOFTECC == 1) begin
rdaddrecc_in <= #FLOP_DELAY addr;
if (softecc_sbiterr_arr[addr] == 1) begin
sbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
sbiterr_in <= #FLOP_DELAY 1'b0;
end
if (softecc_dbiterr_arr[addr] == 1) begin
dbiterr_in <= #FLOP_DELAY 1'b1;
end else begin
dbiterr_in <= #FLOP_DELAY 1'b0;
end
end else begin
rdaddrecc_in <= #FLOP_DELAY 0;
dbiterr_in <= #FLOP_DELAY 1'b0;
sbiterr_in <= #FLOP_DELAY 1'b0;
end //end SOFTECC Loop
end //end Valid address loop
end //end reset-data assignment loops
end
endtask
//**************
// reset_a
//**************
task reset_a (input reg reset);
begin
if (reset) memory_out_a <= #FLOP_DELAY inita_val;
end
endtask
//**************
// reset_b
//**************
task reset_b (input reg reset);
begin
if (reset) memory_out_b <= #FLOP_DELAY initb_val;
end
endtask
//**************
// init_memory
//**************
task init_memory;
integer i, j, addr_step;
integer status;
reg [C_WRITE_WIDTH_A-1:0] default_data;
begin
default_data = 0;
//Display output message indicating that the behavioral model is being
//initialized
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE) $display(" Block Memory Generator module loading initial data...");
// Convert the default to hex
if (C_USE_DEFAULT_DATA) begin
if (default_data_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_DEFAULT_DATA is empty!", C_CORENAME);
$finish;
end else begin
status = $sscanf(default_data_str, "%h", default_data);
if (status == 0) begin
$fdisplay(ERRFILE, {"%0s ERROR: Unsuccessful hexadecimal read",
"from C_DEFAULT_DATA: %0s"},
C_CORENAME, C_DEFAULT_DATA);
$finish;
end
end
end
// Step by WRITE_ADDR_A_DIV through the memory via the
// Port A write interface to hit every location once
addr_step = WRITE_ADDR_A_DIV;
// 'write' to every location with default (or 0)
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, default_data, 1'b0, 1'b0);
end
// Get specialized data from the MIF file
if (C_LOAD_INIT_FILE) begin
if (init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE_NAME is empty!",
C_CORENAME);
$finish;
end else begin
initfile = $fopen(init_file_str, "r");
if (initfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE_NAME: %0s!"},
C_CORENAME, init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
for (i = 0; i < C_WRITE_DEPTH_A*addr_step; i = i + addr_step) begin
status = $fscanf(initfile, "%b", mif_data);
if (status > 0) begin
write_a(i, {C_WEA_WIDTH{1'b1}}, mif_data, 1'b0, 1'b0);
end
end
$fclose(initfile);
end //initfile
end //init_file_str
end //C_LOAD_INIT_FILE
if (C_USE_BRAM_BLOCK) begin
// Get specialized data from the MIF file
if (C_INIT_FILE != "NONE") begin
if (mem_init_file_str == "") begin
$fdisplay(ERRFILE, "%0s ERROR: C_INIT_FILE is empty!",
C_CORENAME);
$finish;
end else begin
meminitfile = $fopen(mem_init_file_str, "r");
if (meminitfile == 0) begin
$fdisplay(ERRFILE, {"%0s, ERROR: Problem opening",
"C_INIT_FILE: %0s!"},
C_CORENAME, mem_init_file_str);
$finish;
end else begin
// loop through the mif file, loading in the data
$readmemh(mem_init_file_str, memory );
for (j = 0; j < MAX_DEPTH-1 ; j = j + 1) begin
end
$fclose(meminitfile);
end //meminitfile
end //mem_init_file_str
end //C_INIT_FILE
end //C_USE_BRAM_BLOCK
//Display output message indicating that the behavioral model is done
//initializing
if (C_USE_DEFAULT_DATA || C_LOAD_INIT_FILE)
$display(" Block Memory Generator data initialization complete.");
end
endtask
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//*******************
// collision_check
//*******************
function integer collision_check (input reg [C_ADDRA_WIDTH-1:0] addr_a,
input integer iswrite_a,
input reg [C_ADDRB_WIDTH-1:0] addr_b,
input integer iswrite_b);
reg c_aw_bw, c_aw_br, c_ar_bw;
integer scaled_addra_to_waddrb_width;
integer scaled_addrb_to_waddrb_width;
integer scaled_addra_to_waddra_width;
integer scaled_addrb_to_waddra_width;
integer scaled_addra_to_raddrb_width;
integer scaled_addrb_to_raddrb_width;
integer scaled_addra_to_raddra_width;
integer scaled_addrb_to_raddra_width;
begin
c_aw_bw = 0;
c_aw_br = 0;
c_ar_bw = 0;
//If write_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_b_width. Once both are scaled to
//write_addr_b_width, compare.
scaled_addra_to_waddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_b_width));
scaled_addrb_to_waddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_b_width));
//If write_addr_a_width is smaller, scale both addresses to that width for
//comparing write_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to write_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to write_addr_a_width. Once both are scaled to
//write_addr_a_width, compare.
scaled_addra_to_waddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-write_addr_a_width));
scaled_addrb_to_waddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-write_addr_a_width));
//If read_addr_b_width is smaller, scale both addresses to that width for
//comparing write_addr_a and read_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_b_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_b_width. Once both are scaled to
//read_addr_b_width, compare.
scaled_addra_to_raddrb_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_b_width));
scaled_addrb_to_raddrb_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_b_width));
//If read_addr_a_width is smaller, scale both addresses to that width for
//comparing read_addr_a and write_addr_b; addr_a starts as C_ADDRA_WIDTH,
//scale it down to read_addr_a_width. addr_b starts as C_ADDRB_WIDTH,
//scale it down to read_addr_a_width. Once both are scaled to
//read_addr_a_width, compare.
scaled_addra_to_raddra_width = ((addr_a)/
2**(C_ADDRA_WIDTH-read_addr_a_width));
scaled_addrb_to_raddra_width = ((addr_b)/
2**(C_ADDRB_WIDTH-read_addr_a_width));
//Look for a write-write collision. In order for a write-write
//collision to exist, both ports must have a write transaction.
if (iswrite_a && iswrite_b) begin
if (write_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_bw = 1;
end else begin
c_aw_bw = 0;
end
end //width
end //iswrite_a and iswrite_b
//If the B port is reading (which means it is enabled - so could be
//a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
//to asymmetric write/read ports.
if (iswrite_a) begin
if (write_addr_a_width > read_addr_b_width) begin
if (scaled_addra_to_raddrb_width == scaled_addrb_to_raddrb_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end else begin
if (scaled_addrb_to_waddra_width == scaled_addra_to_waddra_width) begin
c_aw_br = 1;
end else begin
c_aw_br = 0;
end
end //width
end //iswrite_a
//If the A port is reading (which means it is enabled - so could be
// a TX_WRITE or TX_READ), then check for a write-read collision).
//This could happen whether or not a write-write collision exists due
// to asymmetric write/read ports.
if (iswrite_b) begin
if (read_addr_a_width > write_addr_b_width) begin
if (scaled_addra_to_waddrb_width == scaled_addrb_to_waddrb_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end else begin
if (scaled_addrb_to_raddra_width == scaled_addra_to_raddra_width) begin
c_ar_bw = 1;
end else begin
c_ar_bw = 0;
end
end //width
end //iswrite_b
collision_check = c_aw_bw | c_aw_br | c_ar_bw;
end
endfunction
//*******************************
// power on values
//*******************************
initial begin
// Load up the memory
init_memory;
// Load up the output registers and latches
if ($sscanf(inita_str, "%h", inita_val)) begin
memory_out_a = inita_val;
end else begin
memory_out_a = 0;
end
if ($sscanf(initb_str, "%h", initb_val)) begin
memory_out_b = initb_val;
end else begin
memory_out_b = 0;
end
sbiterr_in = 1'b0;
dbiterr_in = 1'b0;
rdaddrecc_in = 0;
// Determine the effective address widths for each of the 4 ports
write_addr_a_width = C_ADDRA_WIDTH - log2roundup(WRITE_ADDR_A_DIV);
read_addr_a_width = C_ADDRA_WIDTH - log2roundup(READ_ADDR_A_DIV);
write_addr_b_width = C_ADDRB_WIDTH - log2roundup(WRITE_ADDR_B_DIV);
read_addr_b_width = C_ADDRB_WIDTH - log2roundup(READ_ADDR_B_DIV);
$display("Block Memory Generator module %m is using a behavioral model for simulation which will not precisely model memory collision behavior.");
end
//***************************************************************************
// These are the main blocks which schedule read and write operations
// Note that the reset priority feature at the latch stage is only supported
// for Spartan-6. For other families, the default priority at the latch stage
// is "CE"
//***************************************************************************
// Synchronous clocks: schedule port operations with respect to
// both write operating modes
generate
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_wf_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_rf_wf
always @(posedge CLKA) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "WRITE_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_wf_rf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else
if(C_COMMON_CLK && (C_WRITE_MODE_A == "READ_FIRST") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_rf_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="WRITE_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_wf_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="READ_FIRST") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_rf_nc
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"WRITE_FIRST")) begin : com_clk_sched_nc_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"READ_FIRST")) begin : com_clk_sched_nc_rf
always @(posedge CLKA) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if(C_COMMON_CLK && (C_WRITE_MODE_A =="NO_CHANGE") && (C_WRITE_MODE_B ==
"NO_CHANGE")) begin : com_clk_sched_nc_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
else if(C_COMMON_CLK) begin: com_clk_sched_default
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
endgenerate
// Asynchronous clocks: port operation is independent
generate
if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "WRITE_FIRST")) begin : async_clk_sched_clka_wf
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "READ_FIRST")) begin : async_clk_sched_clka_rf
always @(posedge CLKA) begin
//Read A
if (rea_i) read_a(ADDRA, reseta_i);
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
end
end
else if((!C_COMMON_CLK) && (C_WRITE_MODE_A == "NO_CHANGE")) begin : async_clk_sched_clka_nc
always @(posedge CLKA) begin
//Write A
if (wea_i) write_a(ADDRA, wea_i, DINA, INJECTSBITERR, INJECTDBITERR);
//Read A
if (rea_i && (!wea_i || reseta_i)) read_a(ADDRA, reseta_i);
end
end
endgenerate
generate
if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "WRITE_FIRST")) begin: async_clk_sched_clkb_wf
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "READ_FIRST")) begin: async_clk_sched_clkb_rf
always @(posedge CLKB) begin
//Read B
if (reb_i) read_b(ADDRB, resetb_i);
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
end
end
else if ((!C_COMMON_CLK) && (C_WRITE_MODE_B == "NO_CHANGE")) begin: async_clk_sched_clkb_nc
always @(posedge CLKB) begin
//Write B
if (web_i) write_b(ADDRB, web_i, DINB);
//Read B
if (reb_i && (!web_i || resetb_i)) read_b(ADDRB, resetb_i);
end
end
endgenerate
//***************************************************************
// Instantiate the variable depth output register stage module
//***************************************************************
// Port A
assign rsta_outp_stage = RSTA & (~SLEEP);
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTA),
.C_RSTRAM (C_RSTRAM_A),
.C_RST_PRIORITY (C_RST_PRIORITY_A),
.C_INIT_VAL (C_INITA_VAL),
.C_HAS_EN (C_HAS_ENA),
.C_HAS_REGCE (C_HAS_REGCEA),
.C_DATA_WIDTH (C_READ_WIDTH_A),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_A),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_A),
.C_EN_ECC_PIPE (0),
.FLOP_DELAY (FLOP_DELAY))
reg_a
(.CLK (CLKA),
.RST (rsta_outp_stage),//(RSTA),
.EN (ENA),
.REGCE (REGCEA),
.DIN_I (memory_out_a),
.DOUT (DOUTA),
.SBITERR_IN_I (1'b0),
.DBITERR_IN_I (1'b0),
.SBITERR (),
.DBITERR (),
.RDADDRECC_IN_I ({C_ADDRB_WIDTH{1'b0}}),
.ECCPIPECE (1'b0),
.RDADDRECC ()
);
assign rstb_outp_stage = RSTB & (~SLEEP);
// Port B
blk_mem_gen_v8_3_5_output_stage
#(.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_RST_TYPE ("SYNC"),
.C_HAS_RST (C_HAS_RSTB),
.C_RSTRAM (C_RSTRAM_B),
.C_RST_PRIORITY (C_RST_PRIORITY_B),
.C_INIT_VAL (C_INITB_VAL),
.C_HAS_EN (C_HAS_ENB),
.C_HAS_REGCE (C_HAS_REGCEB),
.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.NUM_STAGES (NUM_OUTPUT_STAGES_B),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.FLOP_DELAY (FLOP_DELAY))
reg_b
(.CLK (CLKB),
.RST (rstb_outp_stage),//(RSTB),
.EN (ENB),
.REGCE (REGCEB),
.DIN_I (memory_out_b),
.DOUT (dout_i),
.SBITERR_IN_I (sbiterr_in),
.DBITERR_IN_I (dbiterr_in),
.SBITERR (sbiterr_i),
.DBITERR (dbiterr_i),
.RDADDRECC_IN_I (rdaddrecc_in),
.ECCPIPECE (ECCPIPECE),
.RDADDRECC (rdaddrecc_i)
);
//***************************************************************
// Instantiate the Input and Output register stages
//***************************************************************
blk_mem_gen_v8_3_5_softecc_output_reg_stage
#(.C_DATA_WIDTH (C_READ_WIDTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_USE_SOFTECC (C_USE_SOFTECC),
.FLOP_DELAY (FLOP_DELAY))
has_softecc_output_reg_stage
(.CLK (CLKB),
.DIN (dout_i),
.DOUT (DOUTB),
.SBITERR_IN (sbiterr_i),
.DBITERR_IN (dbiterr_i),
.SBITERR (sbiterr_sdp),
.DBITERR (dbiterr_sdp),
.RDADDRECC_IN (rdaddrecc_i),
.RDADDRECC (rdaddrecc_sdp)
);
//****************************************************
// Synchronous collision checks
//****************************************************
// CR 780544 : To make verilog model's collison warnings in consistant with
// vhdl model, the non-blocking assignments are replaced with blocking
// assignments.
generate if (!C_DISABLE_WARN_BHV_COLL && C_COMMON_CLK) begin : sync_coll
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision = 0;
end
end else begin
is_collision = 0;
end
// If the write port is in READ_FIRST mode, there is no collision
if (C_WRITE_MODE_A=="READ_FIRST" && wea_i && !web_i) begin
is_collision = 0;
end
if (C_WRITE_MODE_B=="READ_FIRST" && web_i && !wea_i) begin
is_collision = 0;
end
// Only flag if one of the accesses is a write
if (is_collision && (wea_i || web_i)) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B %0s address: %0h\n",
wea_i ? "write" : "read", ADDRA,
web_i ? "write" : "read", ADDRB);
end
end
//****************************************************
// Asynchronous collision checks
//****************************************************
end else if (!C_DISABLE_WARN_BHV_COLL && !C_COMMON_CLK) begin : async_coll
// Delay A and B addresses in order to mimic setup/hold times
wire [C_ADDRA_WIDTH-1:0] #COLL_DELAY addra_delay = ADDRA;
wire [0:0] #COLL_DELAY wea_delay = wea_i;
wire #COLL_DELAY ena_delay = ena_i;
wire [C_ADDRB_WIDTH-1:0] #COLL_DELAY addrb_delay = ADDRB;
wire [0:0] #COLL_DELAY web_delay = web_i;
wire #COLL_DELAY enb_delay = enb_i;
// Do the checks w/rt A
always @(posedge CLKA) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_a = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_a = 0;
end
end else begin
is_collision_a = 0;
end
if (ena_i && enb_delay) begin
if(wea_i || web_delay) begin
is_collision_delay_a = collision_check(ADDRA, wea_i, addrb_delay,
web_delay);
end else begin
is_collision_delay_a = 0;
end
end else begin
is_collision_delay_a = 0;
end
// Only flag if B access is a write
if (is_collision_a && web_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, ADDRB);
end else if (is_collision_delay_a && web_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A %0s address: %0h, B write address: %0h\n",
wea_i ? "write" : "read", ADDRA, addrb_delay);
end
end
// Do the checks w/rt B
always @(posedge CLKB) begin
// Possible collision if both are enabled and the addresses match
if (ena_i && enb_i) begin
if (wea_i || web_i) begin
is_collision_b = collision_check(ADDRA, wea_i, ADDRB, web_i);
end else begin
is_collision_b = 0;
end
end else begin
is_collision_b = 0;
end
if (ena_delay && enb_i) begin
if (wea_delay || web_i) begin
is_collision_delay_b = collision_check(addra_delay, wea_delay, ADDRB,
web_i);
end else begin
is_collision_delay_b = 0;
end
end else begin
is_collision_delay_b = 0;
end
// Only flag if A access is a write
if (is_collision_b && wea_i) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
ADDRA, web_i ? "write" : "read", ADDRB);
end else if (is_collision_delay_b && wea_delay) begin
$fwrite(COLLFILE, "%0s collision detected at time: %0d, ",
C_CORENAME, $time);
$fwrite(COLLFILE, "A write address: %0h, B %s address: %0h\n",
addra_delay, web_i ? "write" : "read", ADDRB);
end
end
end
endgenerate
endmodule
//*****************************************************************************
// Top module wraps Input register and Memory module
//
// This module is the top-level behavioral model and this implements the memory
// module and the input registers
//*****************************************************************************
module blk_mem_gen_v8_3_5
#(parameter C_CORENAME = "blk_mem_gen_v8_3_5",
parameter C_FAMILY = "virtex7",
parameter C_XDEVICEFAMILY = "virtex7",
parameter C_ELABORATION_DIR = "",
parameter C_INTERFACE_TYPE = 0,
parameter C_USE_BRAM_BLOCK = 0,
parameter C_CTRL_ECC_ALGO = "NONE",
parameter C_ENABLE_32BIT_ADDRESS = 0,
parameter C_AXI_TYPE = 0,
parameter C_AXI_SLAVE_TYPE = 0,
parameter C_HAS_AXI_ID = 0,
parameter C_AXI_ID_WIDTH = 4,
parameter C_MEM_TYPE = 2,
parameter C_BYTE_SIZE = 9,
parameter C_ALGORITHM = 1,
parameter C_PRIM_TYPE = 3,
parameter C_LOAD_INIT_FILE = 0,
parameter C_INIT_FILE_NAME = "",
parameter C_INIT_FILE = "",
parameter C_USE_DEFAULT_DATA = 0,
parameter C_DEFAULT_DATA = "0",
//parameter C_RST_TYPE = "SYNC",
parameter C_HAS_RSTA = 0,
parameter C_RST_PRIORITY_A = "CE",
parameter C_RSTRAM_A = 0,
parameter C_INITA_VAL = "0",
parameter C_HAS_ENA = 1,
parameter C_HAS_REGCEA = 0,
parameter C_USE_BYTE_WEA = 0,
parameter C_WEA_WIDTH = 1,
parameter C_WRITE_MODE_A = "WRITE_FIRST",
parameter C_WRITE_WIDTH_A = 32,
parameter C_READ_WIDTH_A = 32,
parameter C_WRITE_DEPTH_A = 64,
parameter C_READ_DEPTH_A = 64,
parameter C_ADDRA_WIDTH = 5,
parameter C_HAS_RSTB = 0,
parameter C_RST_PRIORITY_B = "CE",
parameter C_RSTRAM_B = 0,
parameter C_INITB_VAL = "",
parameter C_HAS_ENB = 1,
parameter C_HAS_REGCEB = 0,
parameter C_USE_BYTE_WEB = 0,
parameter C_WEB_WIDTH = 1,
parameter C_WRITE_MODE_B = "WRITE_FIRST",
parameter C_WRITE_WIDTH_B = 32,
parameter C_READ_WIDTH_B = 32,
parameter C_WRITE_DEPTH_B = 64,
parameter C_READ_DEPTH_B = 64,
parameter C_ADDRB_WIDTH = 5,
parameter C_HAS_MEM_OUTPUT_REGS_A = 0,
parameter C_HAS_MEM_OUTPUT_REGS_B = 0,
parameter C_HAS_MUX_OUTPUT_REGS_A = 0,
parameter C_HAS_MUX_OUTPUT_REGS_B = 0,
parameter C_HAS_SOFTECC_INPUT_REGS_A = 0,
parameter C_HAS_SOFTECC_OUTPUT_REGS_B= 0,
parameter C_MUX_PIPELINE_STAGES = 0,
parameter C_USE_SOFTECC = 0,
parameter C_USE_ECC = 0,
parameter C_EN_ECC_PIPE = 0,
parameter C_HAS_INJECTERR = 0,
parameter C_SIM_COLLISION_CHECK = "NONE",
parameter C_COMMON_CLK = 1,
parameter C_DISABLE_WARN_BHV_COLL = 0,
parameter C_EN_SLEEP_PIN = 0,
parameter C_USE_URAM = 0,
parameter C_EN_RDADDRA_CHG = 0,
parameter C_EN_RDADDRB_CHG = 0,
parameter C_EN_DEEPSLEEP_PIN = 0,
parameter C_EN_SHUTDOWN_PIN = 0,
parameter C_EN_SAFETY_CKT = 0,
parameter C_COUNT_36K_BRAM = "",
parameter C_COUNT_18K_BRAM = "",
parameter C_EST_POWER_SUMMARY = "",
parameter C_DISABLE_WARN_BHV_RANGE = 0
)
(input clka,
input rsta,
input ena,
input regcea,
input [C_WEA_WIDTH-1:0] wea,
input [C_ADDRA_WIDTH-1:0] addra,
input [C_WRITE_WIDTH_A-1:0] dina,
output [C_READ_WIDTH_A-1:0] douta,
input clkb,
input rstb,
input enb,
input regceb,
input [C_WEB_WIDTH-1:0] web,
input [C_ADDRB_WIDTH-1:0] addrb,
input [C_WRITE_WIDTH_B-1:0] dinb,
output [C_READ_WIDTH_B-1:0] doutb,
input injectsbiterr,
input injectdbiterr,
output sbiterr,
output dbiterr,
output [C_ADDRB_WIDTH-1:0] rdaddrecc,
input eccpipece,
input sleep,
input deepsleep,
input shutdown,
output rsta_busy,
output rstb_busy,
//AXI BMG Input and Output Port Declarations
//AXI Global Signals
input s_aclk,
input s_aresetn,
//AXI Full/lite slave write (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input [31:0] s_axi_awaddr,
input [7:0] s_axi_awlen,
input [2:0] s_axi_awsize,
input [1:0] s_axi_awburst,
input s_axi_awvalid,
output s_axi_awready,
input [C_WRITE_WIDTH_A-1:0] s_axi_wdata,
input [C_WEA_WIDTH-1:0] s_axi_wstrb,
input s_axi_wlast,
input s_axi_wvalid,
output s_axi_wready,
output [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output [1:0] s_axi_bresp,
output s_axi_bvalid,
input s_axi_bready,
//AXI Full/lite slave read (write side)
input [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input [31:0] s_axi_araddr,
input [7:0] s_axi_arlen,
input [2:0] s_axi_arsize,
input [1:0] s_axi_arburst,
input s_axi_arvalid,
output s_axi_arready,
output [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output [C_WRITE_WIDTH_B-1:0] s_axi_rdata,
output [1:0] s_axi_rresp,
output s_axi_rlast,
output s_axi_rvalid,
input s_axi_rready,
//AXI Full/lite sideband signals
input s_axi_injectsbiterr,
input s_axi_injectdbiterr,
output s_axi_sbiterr,
output s_axi_dbiterr,
output [C_ADDRB_WIDTH-1:0] s_axi_rdaddrecc
);
//******************************
// Port and Generic Definitions
//******************************
//////////////////////////////////////////////////////////////////////////
// Generic Definitions
//////////////////////////////////////////////////////////////////////////
// C_CORENAME : Instance name of the Block Memory Generator core
// C_FAMILY,C_XDEVICEFAMILY: Designates architecture targeted. The following
// options are available - "spartan3", "spartan6",
// "virtex4", "virtex5", "virtex6" and "virtex6l".
// C_MEM_TYPE : Designates memory type.
// It can be
// 0 - Single Port Memory
// 1 - Simple Dual Port Memory
// 2 - True Dual Port Memory
// 3 - Single Port Read Only Memory
// 4 - Dual Port Read Only Memory
// C_BYTE_SIZE : Size of a byte (8 or 9 bits)
// C_ALGORITHM : Designates the algorithm method used
// for constructing the memory.
// It can be Fixed_Primitives, Minimum_Area or
// Low_Power
// C_PRIM_TYPE : Designates the user selected primitive used to
// construct the memory.
//
// C_LOAD_INIT_FILE : Designates the use of an initialization file to
// initialize memory contents.
// C_INIT_FILE_NAME : Memory initialization file name.
// C_USE_DEFAULT_DATA : Designates whether to fill remaining
// initialization space with default data
// C_DEFAULT_DATA : Default value of all memory locations
// not initialized by the memory
// initialization file.
// C_RST_TYPE : Type of reset - Synchronous or Asynchronous
// C_HAS_RSTA : Determines the presence of the RSTA port
// C_RST_PRIORITY_A : Determines the priority between CE and SR for
// Port A.
// C_RSTRAM_A : Determines if special reset behavior is used for
// Port A
// C_INITA_VAL : The initialization value for Port A
// C_HAS_ENA : Determines the presence of the ENA port
// C_HAS_REGCEA : Determines the presence of the REGCEA port
// C_USE_BYTE_WEA : Determines if the Byte Write is used or not.
// C_WEA_WIDTH : The width of the WEA port
// C_WRITE_MODE_A : Configurable write mode for Port A. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_A : Memory write width for Port A.
// C_READ_WIDTH_A : Memory read width for Port A.
// C_WRITE_DEPTH_A : Memory write depth for Port A.
// C_READ_DEPTH_A : Memory read depth for Port A.
// C_ADDRA_WIDTH : Width of the ADDRA input port
// C_HAS_RSTB : Determines the presence of the RSTB port
// C_RST_PRIORITY_B : Determines the priority between CE and SR for
// Port B.
// C_RSTRAM_B : Determines if special reset behavior is used for
// Port B
// C_INITB_VAL : The initialization value for Port B
// C_HAS_ENB : Determines the presence of the ENB port
// C_HAS_REGCEB : Determines the presence of the REGCEB port
// C_USE_BYTE_WEB : Determines if the Byte Write is used or not.
// C_WEB_WIDTH : The width of the WEB port
// C_WRITE_MODE_B : Configurable write mode for Port B. It can be
// WRITE_FIRST, READ_FIRST or NO_CHANGE.
// C_WRITE_WIDTH_B : Memory write width for Port B.
// C_READ_WIDTH_B : Memory read width for Port B.
// C_WRITE_DEPTH_B : Memory write depth for Port B.
// C_READ_DEPTH_B : Memory read depth for Port B.
// C_ADDRB_WIDTH : Width of the ADDRB input port
// C_HAS_MEM_OUTPUT_REGS_A : Designates the use of a register at the output
// of the RAM primitive for Port A.
// C_HAS_MEM_OUTPUT_REGS_B : Designates the use of a register at the output
// of the RAM primitive for Port B.
// C_HAS_MUX_OUTPUT_REGS_A : Designates the use of a register at the output
// of the MUX for Port A.
// C_HAS_MUX_OUTPUT_REGS_B : Designates the use of a register at the output
// of the MUX for Port B.
// C_HAS_SOFTECC_INPUT_REGS_A :
// C_HAS_SOFTECC_OUTPUT_REGS_B :
// C_MUX_PIPELINE_STAGES : Designates the number of pipeline stages in
// between the muxes.
// C_USE_SOFTECC : Determines if the Soft ECC feature is used or
// not. Only applicable Spartan-6
// C_USE_ECC : Determines if the ECC feature is used or
// not. Only applicable for V5 and V6
// C_HAS_INJECTERR : Determines if the error injection pins
// are present or not. If the ECC feature
// is not used, this value is defaulted to
// 0, else the following are the allowed
// values:
// 0 : No INJECTSBITERR or INJECTDBITERR pins
// 1 : Only INJECTSBITERR pin exists
// 2 : Only INJECTDBITERR pin exists
// 3 : Both INJECTSBITERR and INJECTDBITERR pins exist
// C_SIM_COLLISION_CHECK : Controls the disabling of Unisim model collision
// warnings. It can be "ALL", "NONE",
// "Warnings_Only" or "Generate_X_Only".
// C_COMMON_CLK : Determins if the core has a single CLK input.
// C_DISABLE_WARN_BHV_COLL : Controls the Behavioral Model Collision warnings
// C_DISABLE_WARN_BHV_RANGE: Controls the Behavioral Model Out of Range
// warnings
//////////////////////////////////////////////////////////////////////////
// Port Definitions
//////////////////////////////////////////////////////////////////////////
// CLKA : Clock to synchronize all read and write operations of Port A.
// RSTA : Reset input to reset memory outputs to a user-defined
// reset state for Port A.
// ENA : Enable all read and write operations of Port A.
// REGCEA : Register Clock Enable to control each pipeline output
// register stages for Port A.
// WEA : Write Enable to enable all write operations of Port A.
// ADDRA : Address of Port A.
// DINA : Data input of Port A.
// DOUTA : Data output of Port A.
// CLKB : Clock to synchronize all read and write operations of Port B.
// RSTB : Reset input to reset memory outputs to a user-defined
// reset state for Port B.
// ENB : Enable all read and write operations of Port B.
// REGCEB : Register Clock Enable to control each pipeline output
// register stages for Port B.
// WEB : Write Enable to enable all write operations of Port B.
// ADDRB : Address of Port B.
// DINB : Data input of Port B.
// DOUTB : Data output of Port B.
// INJECTSBITERR : Single Bit ECC Error Injection Pin.
// INJECTDBITERR : Double Bit ECC Error Injection Pin.
// SBITERR : Output signal indicating that a Single Bit ECC Error has been
// detected and corrected.
// DBITERR : Output signal indicating that a Double Bit ECC Error has been
// detected.
// RDADDRECC : Read Address Output signal indicating address at which an
// ECC error has occurred.
//////////////////////////////////////////////////////////////////////////
wire SBITERR;
wire DBITERR;
wire S_AXI_AWREADY;
wire S_AXI_WREADY;
wire S_AXI_BVALID;
wire S_AXI_ARREADY;
wire S_AXI_RLAST;
wire S_AXI_RVALID;
wire S_AXI_SBITERR;
wire S_AXI_DBITERR;
wire [C_WEA_WIDTH-1:0] WEA = wea;
wire [C_ADDRA_WIDTH-1:0] ADDRA = addra;
wire [C_WRITE_WIDTH_A-1:0] DINA = dina;
wire [C_READ_WIDTH_A-1:0] DOUTA;
wire [C_WEB_WIDTH-1:0] WEB = web;
wire [C_ADDRB_WIDTH-1:0] ADDRB = addrb;
wire [C_WRITE_WIDTH_B-1:0] DINB = dinb;
wire [C_READ_WIDTH_B-1:0] DOUTB;
wire [C_ADDRB_WIDTH-1:0] RDADDRECC;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_AWID = s_axi_awid;
wire [31:0] S_AXI_AWADDR = s_axi_awaddr;
wire [7:0] S_AXI_AWLEN = s_axi_awlen;
wire [2:0] S_AXI_AWSIZE = s_axi_awsize;
wire [1:0] S_AXI_AWBURST = s_axi_awburst;
wire [C_WRITE_WIDTH_A-1:0] S_AXI_WDATA = s_axi_wdata;
wire [C_WEA_WIDTH-1:0] S_AXI_WSTRB = s_axi_wstrb;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_BID;
wire [1:0] S_AXI_BRESP;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_ARID = s_axi_arid;
wire [31:0] S_AXI_ARADDR = s_axi_araddr;
wire [7:0] S_AXI_ARLEN = s_axi_arlen;
wire [2:0] S_AXI_ARSIZE = s_axi_arsize;
wire [1:0] S_AXI_ARBURST = s_axi_arburst;
wire [C_AXI_ID_WIDTH-1:0] S_AXI_RID;
wire [C_WRITE_WIDTH_B-1:0] S_AXI_RDATA;
wire [1:0] S_AXI_RRESP;
wire [C_ADDRB_WIDTH-1:0] S_AXI_RDADDRECC;
// Added to fix the simulation warning #CR731605
wire [C_WEB_WIDTH-1:0] WEB_parameterized = 0;
wire ECCPIPECE;
wire SLEEP;
reg RSTA_BUSY = 0;
reg RSTB_BUSY = 0;
// Declaration of internal signals to avoid warnings #927399
wire CLKA;
wire RSTA;
wire ENA;
wire REGCEA;
wire CLKB;
wire RSTB;
wire ENB;
wire REGCEB;
wire INJECTSBITERR;
wire INJECTDBITERR;
wire S_ACLK;
wire S_ARESETN;
wire S_AXI_AWVALID;
wire S_AXI_WLAST;
wire S_AXI_WVALID;
wire S_AXI_BREADY;
wire S_AXI_ARVALID;
wire S_AXI_RREADY;
wire S_AXI_INJECTSBITERR;
wire S_AXI_INJECTDBITERR;
assign CLKA = clka;
assign RSTA = rsta;
assign ENA = ena;
assign REGCEA = regcea;
assign CLKB = clkb;
assign RSTB = rstb;
assign ENB = enb;
assign REGCEB = regceb;
assign INJECTSBITERR = injectsbiterr;
assign INJECTDBITERR = injectdbiterr;
assign ECCPIPECE = eccpipece;
assign SLEEP = sleep;
assign sbiterr = SBITERR;
assign dbiterr = DBITERR;
assign S_ACLK = s_aclk;
assign S_ARESETN = s_aresetn;
assign S_AXI_AWVALID = s_axi_awvalid;
assign s_axi_awready = S_AXI_AWREADY;
assign S_AXI_WLAST = s_axi_wlast;
assign S_AXI_WVALID = s_axi_wvalid;
assign s_axi_wready = S_AXI_WREADY;
assign s_axi_bvalid = S_AXI_BVALID;
assign S_AXI_BREADY = s_axi_bready;
assign S_AXI_ARVALID = s_axi_arvalid;
assign s_axi_arready = S_AXI_ARREADY;
assign s_axi_rlast = S_AXI_RLAST;
assign s_axi_rvalid = S_AXI_RVALID;
assign S_AXI_RREADY = s_axi_rready;
assign S_AXI_INJECTSBITERR = s_axi_injectsbiterr;
assign S_AXI_INJECTDBITERR = s_axi_injectdbiterr;
assign s_axi_sbiterr = S_AXI_SBITERR;
assign s_axi_dbiterr = S_AXI_DBITERR;
assign rsta_busy = RSTA_BUSY;
assign rstb_busy = RSTB_BUSY;
assign doutb = DOUTB;
assign douta = DOUTA;
assign rdaddrecc = RDADDRECC;
assign s_axi_bid = S_AXI_BID;
assign s_axi_bresp = S_AXI_BRESP;
assign s_axi_rid = S_AXI_RID;
assign s_axi_rdata = S_AXI_RDATA;
assign s_axi_rresp = S_AXI_RRESP;
assign s_axi_rdaddrecc = S_AXI_RDADDRECC;
localparam FLOP_DELAY = 100; // 100 ps
reg injectsbiterr_in;
reg injectdbiterr_in;
reg rsta_in;
reg ena_in;
reg regcea_in;
reg [C_WEA_WIDTH-1:0] wea_in;
reg [C_ADDRA_WIDTH-1:0] addra_in;
reg [C_WRITE_WIDTH_A-1:0] dina_in;
wire [C_ADDRA_WIDTH-1:0] s_axi_awaddr_out_c;
wire [C_ADDRB_WIDTH-1:0] s_axi_araddr_out_c;
wire s_axi_wr_en_c;
wire s_axi_rd_en_c;
wire s_aresetn_a_c;
wire [7:0] s_axi_arlen_c ;
wire [C_AXI_ID_WIDTH-1 : 0] s_axi_rid_c;
wire [C_WRITE_WIDTH_B-1 : 0] s_axi_rdata_c;
wire [1:0] s_axi_rresp_c;
wire s_axi_rlast_c;
wire s_axi_rvalid_c;
wire s_axi_rready_c;
wire regceb_c;
localparam C_AXI_PAYLOAD = (C_HAS_MUX_OUTPUT_REGS_B == 1)?C_WRITE_WIDTH_B+C_AXI_ID_WIDTH+3:C_AXI_ID_WIDTH+3;
wire [C_AXI_PAYLOAD-1 : 0] s_axi_payload_c;
wire [C_AXI_PAYLOAD-1 : 0] m_axi_payload_c;
// Safety logic related signals
reg [4:0] RSTA_SHFT_REG = 0;
reg POR_A = 0;
reg [4:0] RSTB_SHFT_REG = 0;
reg POR_B = 0;
reg ENA_dly = 0;
reg ENA_dly_D = 0;
reg ENB_dly = 0;
reg ENB_dly_D = 0;
wire RSTA_I_SAFE;
wire RSTB_I_SAFE;
wire ENA_I_SAFE;
wire ENB_I_SAFE;
reg ram_rstram_a_busy = 0;
reg ram_rstreg_a_busy = 0;
reg ram_rstram_b_busy = 0;
reg ram_rstreg_b_busy = 0;
reg ENA_dly_reg = 0;
reg ENB_dly_reg = 0;
reg ENA_dly_reg_D = 0;
reg ENB_dly_reg_D = 0;
//**************
// log2roundup
//**************
function integer log2roundup (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
if (data_value > 1) begin
for(cnt=1 ; cnt < data_value ; cnt = cnt * 2) begin
width = width + 1;
end //loop
end //if
log2roundup = width;
end //log2roundup
endfunction
//**************
// log2int
//**************
function integer log2int (input integer data_value);
integer width;
integer cnt;
begin
width = 0;
cnt= data_value;
for(cnt=data_value ; cnt >1 ; cnt = cnt / 2) begin
width = width + 1;
end //loop
log2int = width;
end //log2int
endfunction
//**************************************************************************
// FUNCTION : divroundup
// Returns the ceiling value of the division
// Data_value - the quantity to be divided, dividend
// Divisor - the value to divide the data_value by
//**************************************************************************
function integer divroundup (input integer data_value,input integer divisor);
integer div;
begin
div = data_value/divisor;
if ((data_value % divisor) != 0) begin
div = div+1;
end //if
divroundup = div;
end //if
endfunction
localparam AXI_FULL_MEMORY_SLAVE = ((C_AXI_SLAVE_TYPE == 0 && C_AXI_TYPE == 1)?1:0);
localparam C_AXI_ADDR_WIDTH_MSB = C_ADDRA_WIDTH+log2roundup(C_WRITE_WIDTH_A/8);
localparam C_AXI_ADDR_WIDTH = C_AXI_ADDR_WIDTH_MSB;
//Data Width Number of LSB address bits to be discarded
//1 to 16 1
//17 to 32 2
//33 to 64 3
//65 to 128 4
//129 to 256 5
//257 to 512 6
//513 to 1024 7
// The following two constants determine this.
localparam LOWER_BOUND_VAL = (log2roundup(divroundup(C_WRITE_WIDTH_A,8) == 0))?0:(log2roundup(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_AXI_ADDR_WIDTH_LSB = ((AXI_FULL_MEMORY_SLAVE == 1)?0:LOWER_BOUND_VAL);
localparam C_AXI_OS_WR = 2;
//***********************************************
// INPUT REGISTERS.
//***********************************************
generate if (C_HAS_SOFTECC_INPUT_REGS_A==0) begin : no_softecc_input_reg_stage
always @* begin
injectsbiterr_in = INJECTSBITERR;
injectdbiterr_in = INJECTDBITERR;
rsta_in = RSTA;
ena_in = ENA;
regcea_in = REGCEA;
wea_in = WEA;
addra_in = ADDRA;
dina_in = DINA;
end //end always
end //end no_softecc_input_reg_stage
endgenerate
generate if (C_HAS_SOFTECC_INPUT_REGS_A==1) begin : has_softecc_input_reg_stage
always @(posedge CLKA) begin
injectsbiterr_in <= #FLOP_DELAY INJECTSBITERR;
injectdbiterr_in <= #FLOP_DELAY INJECTDBITERR;
rsta_in <= #FLOP_DELAY RSTA;
ena_in <= #FLOP_DELAY ENA;
regcea_in <= #FLOP_DELAY REGCEA;
wea_in <= #FLOP_DELAY WEA;
addra_in <= #FLOP_DELAY ADDRA;
dina_in <= #FLOP_DELAY DINA;
end //end always
end //end input_reg_stages generate statement
endgenerate
//**************************************************************************
// NO SAFETY LOGIC
//**************************************************************************
generate
if (C_EN_SAFETY_CKT == 0) begin : NO_SAFETY_CKT_GEN
assign ENA_I_SAFE = ena_in;
assign ENB_I_SAFE = ENB;
assign RSTA_I_SAFE = rsta_in;
assign RSTB_I_SAFE = RSTB;
end
endgenerate
//***************************************************************************
// SAFETY LOGIC
// Power-ON Reset Generation
//***************************************************************************
generate
if (C_EN_SAFETY_CKT == 1) begin
always @(posedge clka) RSTA_SHFT_REG <= #FLOP_DELAY {RSTA_SHFT_REG[3:0],1'b1} ;
always @(posedge clka) POR_A <= #FLOP_DELAY RSTA_SHFT_REG[4] ^ RSTA_SHFT_REG[0];
always @(posedge clkb) RSTB_SHFT_REG <= #FLOP_DELAY {RSTB_SHFT_REG[3:0],1'b1} ;
always @(posedge clkb) POR_B <= #FLOP_DELAY RSTB_SHFT_REG[4] ^ RSTB_SHFT_REG[0];
assign RSTA_I_SAFE = rsta_in | POR_A;
assign RSTB_I_SAFE = (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) ? 1'b0 : (RSTB | POR_B);
end
endgenerate
//-----------------------------------------------------------------------------
// -- RSTA/B_BUSY Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && (C_EN_SAFETY_CKT == 1)) begin : RSTA_BUSY_NO_REG
always @(*) ram_rstram_a_busy = RSTA_I_SAFE | ENA_dly | ENA_dly_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstram_a_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0 && C_EN_SAFETY_CKT == 1) begin : RSTA_BUSY_WITH_REG
always @(*) ram_rstreg_a_busy = RSTA_I_SAFE | ENA_dly_reg | ENA_dly_reg_D;
always @(posedge clka) RSTA_BUSY <= #FLOP_DELAY ram_rstreg_a_busy;
end
endgenerate
generate
if ( (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) && C_EN_SAFETY_CKT == 1) begin : SPRAM_RST_BUSY
always @(*) RSTB_BUSY = 1'b0;
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && (C_MEM_TYPE != 0 && C_MEM_TYPE != 3) && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_NO_REG
always @(*) ram_rstram_b_busy = RSTB_I_SAFE | ENB_dly | ENB_dly_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstram_b_busy;
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : RSTB_BUSY_WITH_REG
always @(*) ram_rstreg_b_busy = RSTB_I_SAFE | ENB_dly_reg | ENB_dly_reg_D;
always @(posedge clkb) RSTB_BUSY <= #FLOP_DELAY ram_rstreg_b_busy;
end
endgenerate
//-----------------------------------------------------------------------------
// -- ENA/ENB Generation
//-----------------------------------------------------------------------------
generate
if ((C_HAS_MEM_OUTPUT_REGS_A==0 || (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==1)) && C_EN_SAFETY_CKT == 1) begin : ENA_NO_REG
always @(posedge clka) begin
ENA_dly <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_D <= #FLOP_DELAY ENA_dly;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_D | ena_in);
end
endgenerate
generate
if ( (C_HAS_MEM_OUTPUT_REGS_A==1 && C_RSTRAM_A==0) && C_EN_SAFETY_CKT == 1) begin : ENA_WITH_REG
always @(posedge clka) begin
ENA_dly_reg <= #FLOP_DELAY RSTA_I_SAFE;
ENA_dly_reg_D <= #FLOP_DELAY ENA_dly_reg;
end
assign ENA_I_SAFE = (C_HAS_ENA == 0)? 1'b1 : (ENA_dly_reg_D | ena_in);
end
endgenerate
generate
if (C_MEM_TYPE == 0 || C_MEM_TYPE == 3) begin : SPRAM_ENB
assign ENB_I_SAFE = 1'b0;
end
endgenerate
generate
if ((C_HAS_MEM_OUTPUT_REGS_B==0 || (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==1)) && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1) begin : ENB_NO_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_D <= #FLOP_DELAY ENB_dly;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_D | ENB);
end
endgenerate
generate
if (C_HAS_MEM_OUTPUT_REGS_B==1 && C_RSTRAM_B==0 && C_MEM_TYPE != 0 && C_MEM_TYPE != 3 && C_EN_SAFETY_CKT == 1)begin : ENB_WITH_REG
always @(posedge clkb) begin : PROC_ENB_GEN
ENB_dly_reg <= #FLOP_DELAY RSTB_I_SAFE;
ENB_dly_reg_D <= #FLOP_DELAY ENB_dly_reg;
end
assign ENB_I_SAFE = (C_HAS_ENB == 0)? 1'b1 : (ENB_dly_reg_D | ENB);
end
endgenerate
generate if ((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 0)) begin : native_mem_module
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_ALGORITHM (C_ALGORITHM),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
generate if((C_INTERFACE_TYPE == 0) && (C_ENABLE_32BIT_ADDRESS == 1)) begin : native_mem_mapped_module
localparam C_ADDRA_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_A);
localparam C_ADDRB_WIDTH_ACTUAL = log2roundup(C_WRITE_DEPTH_B);
localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_A/8);
localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2int(C_WRITE_WIDTH_B/8);
// localparam C_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_A/8);
// localparam C_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_ACTUAL+log2roundup(C_WRITE_WIDTH_B/8);
localparam C_MEM_MAP_ADDRA_WIDTH_MSB = C_ADDRA_WIDTH_MSB;
localparam C_MEM_MAP_ADDRB_WIDTH_MSB = C_ADDRB_WIDTH_MSB;
// Data Width Number of LSB address bits to be discarded
// 1 to 16 1
// 17 to 32 2
// 33 to 64 3
// 65 to 128 4
// 129 to 256 5
// 257 to 512 6
// 513 to 1024 7
// The following two constants determine this.
localparam MEM_MAP_LOWER_BOUND_VAL_A = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam MEM_MAP_LOWER_BOUND_VAL_B = (log2int(divroundup(C_WRITE_WIDTH_A,8)==0)) ? 0:(log2int(divroundup(C_WRITE_WIDTH_A,8)));
localparam C_MEM_MAP_ADDRA_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_A;
localparam C_MEM_MAP_ADDRB_WIDTH_LSB = MEM_MAP_LOWER_BOUND_VAL_B;
wire [C_ADDRB_WIDTH_ACTUAL-1 :0] rdaddrecc_i;
wire [C_ADDRB_WIDTH-1:C_MEM_MAP_ADDRB_WIDTH_MSB] msb_zero_i;
wire [C_MEM_MAP_ADDRB_WIDTH_LSB-1:0] lsb_zero_i;
assign msb_zero_i = 0;
assign lsb_zero_i = 0;
assign RDADDRECC = {msb_zero_i,rdaddrecc_i,lsb_zero_i};
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (C_HAS_ENA),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (C_USE_BYTE_WEA),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH_ACTUAL),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (C_HAS_ENB),
.C_HAS_REGCEB (C_HAS_REGCEB),
.C_USE_BYTE_WEB (C_USE_BYTE_WEB),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH_ACTUAL),
.C_HAS_MEM_OUTPUT_REGS_A (C_HAS_MEM_OUTPUT_REGS_A),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (C_HAS_MUX_OUTPUT_REGS_A),
.C_HAS_MUX_OUTPUT_REGS_B (C_HAS_MUX_OUTPUT_REGS_B),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (C_EN_ECC_PIPE),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (CLKA),
.RSTA (RSTA_I_SAFE),//(rsta_in),
.ENA (ENA_I_SAFE),//(ena_in),
.REGCEA (regcea_in),
.WEA (wea_in),
.ADDRA (addra_in[C_MEM_MAP_ADDRA_WIDTH_MSB-1:C_MEM_MAP_ADDRA_WIDTH_LSB]),
.DINA (dina_in),
.DOUTA (DOUTA),
.CLKB (CLKB),
.RSTB (RSTB_I_SAFE),//(RSTB),
.ENB (ENB_I_SAFE),//(ENB),
.REGCEB (REGCEB),
.WEB (WEB),
.ADDRB (ADDRB[C_MEM_MAP_ADDRB_WIDTH_MSB-1:C_MEM_MAP_ADDRB_WIDTH_LSB]),
.DINB (DINB),
.DOUTB (DOUTB),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.ECCPIPECE (ECCPIPECE),
.SLEEP (SLEEP),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.RDADDRECC (rdaddrecc_i)
);
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0 && C_HAS_MUX_OUTPUT_REGS_B == 0 ) begin : no_regs
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RLAST = s_axi_rlast_c;
assign S_AXI_RVALID = s_axi_rvalid_c;
assign S_AXI_RID = s_axi_rid_c;
assign S_AXI_RRESP = s_axi_rresp_c;
assign s_axi_rready_c = S_AXI_RREADY;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regceb
assign regceb_c = s_axi_rvalid_c && s_axi_rready_c;
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 0) begin : no_regceb
assign regceb_c = REGCEB;
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1) begin : only_core_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rdata_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RDATA = m_axi_payload_c[C_AXI_PAYLOAD-C_AXI_ID_WIDTH-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH-C_WRITE_WIDTH_B];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MEM_OUTPUT_REGS_B == 1) begin : only_emb_op_regs
assign s_axi_payload_c = {s_axi_rid_c,s_axi_rresp_c,s_axi_rlast_c};
assign S_AXI_RDATA = s_axi_rdata_c;
assign S_AXI_RID = m_axi_payload_c[C_AXI_PAYLOAD-1 : C_AXI_PAYLOAD-C_AXI_ID_WIDTH];
assign S_AXI_RRESP = m_axi_payload_c[2:1];
assign S_AXI_RLAST = m_axi_payload_c[0];
end
endgenerate
generate if (C_HAS_MUX_OUTPUT_REGS_B == 1 || C_HAS_MEM_OUTPUT_REGS_B == 1) begin : has_regs_fwd
blk_mem_axi_regs_fwd_v8_3
#(.C_DATA_WIDTH (C_AXI_PAYLOAD))
axi_regs_inst (
.ACLK (S_ACLK),
.ARESET (s_aresetn_a_c),
.S_VALID (s_axi_rvalid_c),
.S_READY (s_axi_rready_c),
.S_PAYLOAD_DATA (s_axi_payload_c),
.M_VALID (S_AXI_RVALID),
.M_READY (S_AXI_RREADY),
.M_PAYLOAD_DATA (m_axi_payload_c)
);
end
endgenerate
generate if (C_INTERFACE_TYPE == 1) begin : axi_mem_module
assign s_aresetn_a_c = !S_ARESETN;
assign S_AXI_BRESP = 2'b00;
assign s_axi_rresp_c = 2'b00;
assign s_axi_arlen_c = (C_AXI_TYPE == 1)?S_AXI_ARLEN:8'h0;
blk_mem_axi_write_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_AXI_AWADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_WDATA_WIDTH (C_WRITE_WIDTH_A),
.C_AXI_OS_WR (C_AXI_OS_WR))
axi_wr_fsm (
// AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
// AXI Full/Lite Slave Write interface
.S_AXI_AWADDR (S_AXI_AWADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_AWLEN (S_AXI_AWLEN),
.S_AXI_AWID (S_AXI_AWID),
.S_AXI_AWSIZE (S_AXI_AWSIZE),
.S_AXI_AWBURST (S_AXI_AWBURST),
.S_AXI_AWVALID (S_AXI_AWVALID),
.S_AXI_AWREADY (S_AXI_AWREADY),
.S_AXI_WVALID (S_AXI_WVALID),
.S_AXI_WREADY (S_AXI_WREADY),
.S_AXI_BVALID (S_AXI_BVALID),
.S_AXI_BREADY (S_AXI_BREADY),
.S_AXI_BID (S_AXI_BID),
// Signals for BRAM interfac(
.S_AXI_AWADDR_OUT (s_axi_awaddr_out_c),
.S_AXI_WR_EN (s_axi_wr_en_c)
);
blk_mem_axi_read_wrapper_beh_v8_3
#(.C_INTERFACE_TYPE (C_INTERFACE_TYPE),
.C_AXI_TYPE (C_AXI_TYPE),
.C_AXI_SLAVE_TYPE (C_AXI_SLAVE_TYPE),
.C_MEMORY_TYPE (C_MEM_TYPE),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_AXI_PIPELINE_STAGES (1),
.C_AXI_ARADDR_WIDTH ((AXI_FULL_MEMORY_SLAVE == 1)?C_AXI_ADDR_WIDTH:C_AXI_ADDR_WIDTH-C_AXI_ADDR_WIDTH_LSB),
.C_HAS_AXI_ID (C_HAS_AXI_ID),
.C_AXI_ID_WIDTH (C_AXI_ID_WIDTH),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH))
axi_rd_sm(
//AXI Global Signals
.S_ACLK (S_ACLK),
.S_ARESETN (s_aresetn_a_c),
//AXI Full/Lite Read Side
.S_AXI_ARADDR (S_AXI_ARADDR[C_AXI_ADDR_WIDTH_MSB-1:C_AXI_ADDR_WIDTH_LSB]),
.S_AXI_ARLEN (s_axi_arlen_c),
.S_AXI_ARSIZE (S_AXI_ARSIZE),
.S_AXI_ARBURST (S_AXI_ARBURST),
.S_AXI_ARVALID (S_AXI_ARVALID),
.S_AXI_ARREADY (S_AXI_ARREADY),
.S_AXI_RLAST (s_axi_rlast_c),
.S_AXI_RVALID (s_axi_rvalid_c),
.S_AXI_RREADY (s_axi_rready_c),
.S_AXI_ARID (S_AXI_ARID),
.S_AXI_RID (s_axi_rid_c),
//AXI Full/Lite Read FSM Outputs
.S_AXI_ARADDR_OUT (s_axi_araddr_out_c),
.S_AXI_RD_EN (s_axi_rd_en_c)
);
blk_mem_gen_v8_3_5_mem_module
#(.C_CORENAME (C_CORENAME),
.C_FAMILY (C_FAMILY),
.C_XDEVICEFAMILY (C_XDEVICEFAMILY),
.C_MEM_TYPE (C_MEM_TYPE),
.C_BYTE_SIZE (C_BYTE_SIZE),
.C_USE_BRAM_BLOCK (C_USE_BRAM_BLOCK),
.C_ALGORITHM (C_ALGORITHM),
.C_PRIM_TYPE (C_PRIM_TYPE),
.C_LOAD_INIT_FILE (C_LOAD_INIT_FILE),
.C_INIT_FILE_NAME (C_INIT_FILE_NAME),
.C_INIT_FILE (C_INIT_FILE),
.C_USE_DEFAULT_DATA (C_USE_DEFAULT_DATA),
.C_DEFAULT_DATA (C_DEFAULT_DATA),
.C_RST_TYPE ("SYNC"),
.C_HAS_RSTA (C_HAS_RSTA),
.C_RST_PRIORITY_A (C_RST_PRIORITY_A),
.C_RSTRAM_A (C_RSTRAM_A),
.C_INITA_VAL (C_INITA_VAL),
.C_HAS_ENA (1),
.C_HAS_REGCEA (C_HAS_REGCEA),
.C_USE_BYTE_WEA (1),
.C_WEA_WIDTH (C_WEA_WIDTH),
.C_WRITE_MODE_A (C_WRITE_MODE_A),
.C_WRITE_WIDTH_A (C_WRITE_WIDTH_A),
.C_READ_WIDTH_A (C_READ_WIDTH_A),
.C_WRITE_DEPTH_A (C_WRITE_DEPTH_A),
.C_READ_DEPTH_A (C_READ_DEPTH_A),
.C_ADDRA_WIDTH (C_ADDRA_WIDTH),
.C_HAS_RSTB (C_HAS_RSTB),
.C_RST_PRIORITY_B (C_RST_PRIORITY_B),
.C_RSTRAM_B (C_RSTRAM_B),
.C_INITB_VAL (C_INITB_VAL),
.C_HAS_ENB (1),
.C_HAS_REGCEB (C_HAS_MEM_OUTPUT_REGS_B),
.C_USE_BYTE_WEB (1),
.C_WEB_WIDTH (C_WEB_WIDTH),
.C_WRITE_MODE_B (C_WRITE_MODE_B),
.C_WRITE_WIDTH_B (C_WRITE_WIDTH_B),
.C_READ_WIDTH_B (C_READ_WIDTH_B),
.C_WRITE_DEPTH_B (C_WRITE_DEPTH_B),
.C_READ_DEPTH_B (C_READ_DEPTH_B),
.C_ADDRB_WIDTH (C_ADDRB_WIDTH),
.C_HAS_MEM_OUTPUT_REGS_A (0),
.C_HAS_MEM_OUTPUT_REGS_B (C_HAS_MEM_OUTPUT_REGS_B),
.C_HAS_MUX_OUTPUT_REGS_A (0),
.C_HAS_MUX_OUTPUT_REGS_B (0),
.C_HAS_SOFTECC_INPUT_REGS_A (C_HAS_SOFTECC_INPUT_REGS_A),
.C_HAS_SOFTECC_OUTPUT_REGS_B (C_HAS_SOFTECC_OUTPUT_REGS_B),
.C_MUX_PIPELINE_STAGES (C_MUX_PIPELINE_STAGES),
.C_USE_SOFTECC (C_USE_SOFTECC),
.C_USE_ECC (C_USE_ECC),
.C_HAS_INJECTERR (C_HAS_INJECTERR),
.C_SIM_COLLISION_CHECK (C_SIM_COLLISION_CHECK),
.C_COMMON_CLK (C_COMMON_CLK),
.FLOP_DELAY (FLOP_DELAY),
.C_DISABLE_WARN_BHV_COLL (C_DISABLE_WARN_BHV_COLL),
.C_EN_ECC_PIPE (0),
.C_DISABLE_WARN_BHV_RANGE (C_DISABLE_WARN_BHV_RANGE))
blk_mem_gen_v8_3_5_inst
(.CLKA (S_ACLK),
.RSTA (s_aresetn_a_c),
.ENA (s_axi_wr_en_c),
.REGCEA (regcea_in),
.WEA (S_AXI_WSTRB),
.ADDRA (s_axi_awaddr_out_c),
.DINA (S_AXI_WDATA),
.DOUTA (DOUTA),
.CLKB (S_ACLK),
.RSTB (s_aresetn_a_c),
.ENB (s_axi_rd_en_c),
.REGCEB (regceb_c),
.WEB (WEB_parameterized),
.ADDRB (s_axi_araddr_out_c),
.DINB (DINB),
.DOUTB (s_axi_rdata_c),
.INJECTSBITERR (injectsbiterr_in),
.INJECTDBITERR (injectdbiterr_in),
.SBITERR (SBITERR),
.DBITERR (DBITERR),
.ECCPIPECE (1'b0),
.SLEEP (1'b0),
.RDADDRECC (RDADDRECC)
);
end
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: ddr_phy_v2_3_phy_ocd_cntlr.v
// /___/ /\ Date Last Modified: $Date: 2011/02/25 02:07:40 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose: Steps through the major sections of the output clock
// delay algorithm. Enabling various subblocks at the right time.
//
// Steps through each byte of the interface.
//
// Implements both the simple and complex data pattern.
//
// for each byte in interface
// begin
// Limit
// Scan - which includes DQS centering
// Precharge
// end
// set _wrlvl and _done equal to one
//
//Reference:
//Revision History:
//*****************************************************************************
`timescale 1ps/1ps
module mig_7series_v2_3_ddr_phy_ocd_cntlr #
(parameter TCQ = 100,
parameter DQS_CNT_WIDTH = 3,
parameter DQS_WIDTH = 8)
(/*AUTOARG*/
// Outputs
wrlvl_final, complex_wrlvl_final, oclk_init_delay_done,
ocd_prech_req, lim_start, complex_oclkdelay_calib_done,
oclkdelay_calib_done, phy_rddata_en_1, phy_rddata_en_2,
phy_rddata_en_3, ocd_cntlr2stg2_dec, oclkdelay_calib_cnt,
reset_scan,
// Inputs
clk, rst, prech_done, oclkdelay_calib_start,
complex_oclkdelay_calib_start, lim_done, phy_rddata_en,
po_counter_read_val, po_rdy, scan_done
);
localparam ONE = 1;
input clk;
input rst;
output wrlvl_final, complex_wrlvl_final;
reg wrlvl_final_ns, wrlvl_final_r, complex_wrlvl_final_ns, complex_wrlvl_final_r;
always @(posedge clk) wrlvl_final_r <= #TCQ wrlvl_final_ns;
always @(posedge clk) complex_wrlvl_final_r <= #TCQ complex_wrlvl_final_ns;
assign wrlvl_final = wrlvl_final_r;
assign complex_wrlvl_final = complex_wrlvl_final_r;
// Completed initial delay increment
output oclk_init_delay_done; // may not need this... maybe for fast cal mode.
assign oclk_init_delay_done = 1'b1;
// Precharge done status from ddr_phy_init
input prech_done;
reg ocd_prech_req_ns, ocd_prech_req_r;
always @(posedge clk) ocd_prech_req_r <= #TCQ ocd_prech_req_ns;
output ocd_prech_req;
assign ocd_prech_req = ocd_prech_req_r;
input oclkdelay_calib_start, complex_oclkdelay_calib_start;
input lim_done;
reg lim_start_ns, lim_start_r;
always @(posedge clk) lim_start_r <= #TCQ lim_start_ns;
output lim_start;
assign lim_start = lim_start_r;
reg complex_oclkdelay_calib_done_ns, complex_oclkdelay_calib_done_r;
always @(posedge clk) complex_oclkdelay_calib_done_r <= #TCQ complex_oclkdelay_calib_done_ns;
output complex_oclkdelay_calib_done;
assign complex_oclkdelay_calib_done = complex_oclkdelay_calib_done_r;
reg oclkdelay_calib_done_ns, oclkdelay_calib_done_r;
always @(posedge clk) oclkdelay_calib_done_r <= #TCQ oclkdelay_calib_done_ns;
output oclkdelay_calib_done;
assign oclkdelay_calib_done = oclkdelay_calib_done_r;
input phy_rddata_en;
reg prde_r1, prde_r2;
always @(posedge clk) prde_r1 <= #TCQ phy_rddata_en;
always @(posedge clk) prde_r2 <= #TCQ prde_r1;
wire prde = complex_oclkdelay_calib_start ? prde_r2 : phy_rddata_en;
reg phy_rddata_en_r1, phy_rddata_en_r2, phy_rddata_en_r3;
always @(posedge clk) phy_rddata_en_r1 <= #TCQ prde;
always @(posedge clk) phy_rddata_en_r2 <= #TCQ phy_rddata_en_r1;
always @(posedge clk) phy_rddata_en_r3 <= #TCQ phy_rddata_en_r2;
output phy_rddata_en_1, phy_rddata_en_2, phy_rddata_en_3;
assign phy_rddata_en_1 = phy_rddata_en_r1;
assign phy_rddata_en_2 = phy_rddata_en_r2;
assign phy_rddata_en_3 = phy_rddata_en_r3;
input [8:0] po_counter_read_val;
reg ocd_cntlr2stg2_dec_r;
output ocd_cntlr2stg2_dec;
assign ocd_cntlr2stg2_dec = ocd_cntlr2stg2_dec_r;
input po_rdy;
reg [3:0] po_rd_wait_ns, po_rd_wait_r;
always @(posedge clk) po_rd_wait_r <= #TCQ po_rd_wait_ns;
reg [DQS_CNT_WIDTH-1:0] byte_ns, byte_r;
always @(posedge clk) byte_r <= #TCQ byte_ns;
output [DQS_CNT_WIDTH:0] oclkdelay_calib_cnt;
assign oclkdelay_calib_cnt = {1'b0, byte_r};
reg reset_scan_ns, reset_scan_r;
always @(posedge clk) reset_scan_r <= #TCQ reset_scan_ns;
output reset_scan;
assign reset_scan = reset_scan_r;
input scan_done;
reg [2:0] sm_ns, sm_r;
always @(posedge clk) sm_r <= #TCQ sm_ns;
// Primary state machine.
always @(*) begin
// Default next state assignments.
byte_ns = byte_r;
complex_wrlvl_final_ns = complex_wrlvl_final_r;
lim_start_ns = lim_start_r;
oclkdelay_calib_done_ns = oclkdelay_calib_done_r;
complex_oclkdelay_calib_done_ns = complex_oclkdelay_calib_done_r;
ocd_cntlr2stg2_dec_r = 1'b0;
po_rd_wait_ns = po_rd_wait_r;
if (|po_rd_wait_r) po_rd_wait_ns = po_rd_wait_r - 4'b1;
reset_scan_ns = reset_scan_r;
wrlvl_final_ns = wrlvl_final_r;
sm_ns = sm_r;
ocd_prech_req_ns= 1'b0;
if (rst == 1'b1) begin
// RESET next states
complex_oclkdelay_calib_done_ns = 1'b0;
complex_wrlvl_final_ns = 1'b0;
sm_ns = /*AK("READY")*/3'd0;
lim_start_ns = 1'b0;
oclkdelay_calib_done_ns = 1'b0;
reset_scan_ns = 1'b1;
wrlvl_final_ns = 1'b0;
end else
// State based actions and next states.
case (sm_r)
/*AL("READY")*/3'd0: begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
if (oclkdelay_calib_start && ~oclkdelay_calib_done_r ||
complex_oclkdelay_calib_start && ~complex_oclkdelay_calib_done_r)
begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("LIMIT_START")*/3'd1:
sm_ns = /*AK("LIMIT_WAIT")*/3'd2;
/*AL("LIMIT_WAIT")*/3'd2:begin
if (lim_done) begin
lim_start_ns = 1'b0;
sm_ns = /*AK("SCAN")*/3'd3;
reset_scan_ns = 1'b0;
end
end
/*AL("SCAN")*/3'd3:begin
if (scan_done) begin
reset_scan_ns = 1'b1;
sm_ns = /*AK("COMPUTE")*/3'd4;
end
end
/*AL("COMPUTE")*/3'd4:begin
sm_ns = /*AK("PRECHARGE")*/3'd5;
ocd_prech_req_ns = 1'b1;
end
/*AL("PRECHARGE")*/3'd5:begin
if (prech_done) sm_ns = /*AK("DONE")*/3'd6;
end
/*AL("DONE")*/3'd6:begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
byte_ns = {DQS_CNT_WIDTH{1'b0}};
po_rd_wait_ns = 4'd8;
sm_ns = /*AK("STG2_2_ZERO")*/3'd7;
end else begin
sm_ns = /*AK("LIMIT_START")*/3'd1;
lim_start_ns = 1'b1;
end
end
/*AL("STG2_2_ZERO")*/3'd7:
if (~|po_rd_wait_r && po_rdy)
if (|po_counter_read_val[5:0]) ocd_cntlr2stg2_dec_r = 1'b1;
else begin
if ({1'b0, byte_r} == DQS_WIDTH[DQS_CNT_WIDTH:0] - ONE[DQS_WIDTH:0]) begin
sm_ns = /*AK("READY")*/3'd0;
oclkdelay_calib_done_ns= 1'b1;
wrlvl_final_ns = 1'b1;
if (complex_oclkdelay_calib_start) begin
complex_oclkdelay_calib_done_ns = 1'b1;
complex_wrlvl_final_ns = 1'b1;
end
end else begin
byte_ns = byte_r + ONE[DQS_CNT_WIDTH-1:0];
po_rd_wait_ns = 4'd8;
end
end // else: !if(|po_counter_read_val[5:0])
endcase // case (sm_r)
end // always @ begin
endmodule // mig_7series_v2_3_ddr_phy_ocd_cntlr
// Local Variables:
// verilog-autolabel-prefix: "3'd"
// End:
|
//////////////////////////////////////////////////////////////////////
//// ////
//// Generic Single-Port Synchronous RAM ////
//// ////
//// This file is part of memory library available from ////
//// http://www.opencores.org/cvsweb.shtml/generic_memories/ ////
//// ////
//// Description ////
//// This block is a wrapper with common single-port ////
//// synchronous memory interface for different ////
//// types of ASIC and FPGA RAMs. Beside universal memory ////
//// interface it also provides behavioral model of generic ////
//// single-port synchronous RAM. ////
//// It should be used in all OPENCORES designs that want to be ////
//// portable accross different target technologies and ////
//// independent of target memory. ////
//// ////
//// Supported ASIC RAMs are: ////
//// - Artisan Single-Port Sync RAM ////
//// - Avant! Two-Port Sync RAM (*) ////
//// - Virage Single-Port Sync RAM ////
//// - Virtual Silicon Single-Port Sync RAM ////
//// ////
//// Supported FPGA RAMs are: ////
//// - Xilinx Virtex RAMB4_S16 ////
//// - Altera LPM ////
//// ////
//// To Do: ////
//// - xilinx rams need external tri-state logic ////
//// - fix avant! two-port ram ////
//// - add additional RAMs ////
//// ////
//// Author(s): ////
//// - Damjan Lampret, [email protected] ////
//// ////
//////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2000 Authors and OPENCORES.ORG ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer. ////
//// ////
//// This source file is free software; you can redistribute it ////
//// and/or modify it under the terms of the GNU Lesser General ////
//// Public License as published by the Free Software Foundation; ////
//// either version 2.1 of the License, or (at your option) any ////
//// later version. ////
//// ////
//// This source is distributed in the hope that it will be ////
//// useful, but WITHOUT ANY WARRANTY; without even the implied ////
//// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ////
//// PURPOSE. See the GNU Lesser General Public License for more ////
//// details. ////
//// ////
//// You should have received a copy of the GNU Lesser General ////
//// Public License along with this source; if not, download it ////
//// from http://www.opencores.org/lgpl.shtml ////
//// ////
//////////////////////////////////////////////////////////////////////
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "or1200_defines.v"
module or1200_spram_512x20(
`ifdef OR1200_BIST
// RAM BIST
mbist_si_i, mbist_so_o, mbist_ctrl_i,
`endif
// Generic synchronous single-port RAM interface
clk, rst, ce, we, oe, addr, di, doq
);
//
// Default address and data buses width
//
parameter aw = 9;
parameter dw = 20;
`ifdef OR1200_BIST
//
// RAM BIST
//
input mbist_si_i;
input [`OR1200_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;
output mbist_so_o;
`endif
//
// Generic synchronous single-port RAM interface
//
input clk; // Clock
input rst; // Reset
input ce; // Chip enable input
input we; // Write enable input
input oe; // Output enable input
input [aw-1:0] addr; // address bus inputs
input [dw-1:0] di; // input data bus
output [dw-1:0] doq; // output data bus
//
// Internal wires and registers
//
wire [3:0] unconnected;
`ifdef OR1200_ARTISAN_SSP
`else
`ifdef OR1200_VIRTUALSILICON_SSP
`else
`ifdef OR1200_BIST
assign mbist_so_o = mbist_si_i;
`endif
`endif
`endif
`ifdef OR1200_ARTISAN_SSP
//
// Instantiation of ASIC memory:
//
// Artisan Synchronous Single-Port RAM (ra1sh)
//
`ifdef UNUSED
art_hssp_512x20 #(dw, 1<<aw, aw) artisan_ssp(
`else
`ifdef OR1200_BIST
art_hssp_512x20_bist artisan_ssp(
`else
art_hssp_512x20 artisan_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CLK(clk),
.CEN(~ce),
.WEN(~we),
.A(addr),
.D(di),
.OEN(~oe),
.Q(doq)
);
`else
`ifdef OR1200_AVANT_ATP
//
// Instantiation of ASIC memory:
//
// Avant! Asynchronous Two-Port RAM
//
avant_atp avant_atp(
.web(~we),
.reb(),
.oeb(~oe),
.rcsb(),
.wcsb(),
.ra(addr),
.wa(addr),
.di(di),
.doq(doq)
);
`else
`ifdef OR1200_VIRAGE_SSP
//
// Instantiation of ASIC memory:
//
// Virage Synchronous 1-port R/W RAM
//
virage_ssp virage_ssp(
.clk(clk),
.adr(addr),
.d(di),
.we(we),
.oe(oe),
.me(ce),
.q(doq)
);
`else
`ifdef OR1200_VIRTUALSILICON_SSP
//
// Instantiation of ASIC memory:
//
// Virtual Silicon Single-Port Synchronous SRAM
//
`ifdef UNUSED
vs_hdsp_512x20 #(1<<aw, aw-1, dw-1) vs_ssp(
`else
`ifdef OR1200_BIST
vs_hdsp_512x20_bist vs_ssp(
`else
vs_hdsp_512x20 vs_ssp(
`endif
`endif
`ifdef OR1200_BIST
// RAM BIST
.mbist_si_i(mbist_si_i),
.mbist_so_o(mbist_so_o),
.mbist_ctrl_i(mbist_ctrl_i),
`endif
.CK(clk),
.ADR(addr),
.DI(di),
.WEN(~we),
.CEN(~ce),
.OEN(~oe),
.DOUT(doq)
);
`else
`ifdef OR1200_XILINX_RAMB4
//
// Instantiation of FPGA memory:
//
// Virtex/Spartan2
//
//
// Block 0
//
RAMB4_S8 ramb4_s8_0(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[7:0]),
.EN(ce),
.WE(we),
.DO(doq[7:0])
);
//
// Block 1
//
RAMB4_S8 ramb4_s8_1(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI(di[15:8]),
.EN(ce),
.WE(we),
.DO(doq[15:8])
);
//
// Block 2
//
RAMB4_S8 ramb4_s8_2(
.CLK(clk),
.RST(rst),
.ADDR(addr),
.DI({4'b0000, di[19:16]}),
.EN(ce),
.WE(we),
.DO({unconnected, doq[19:16]})
);
`else
`ifdef OR1200_ALTERA_LPM
//
// Instantiation of FPGA memory:
//
// Altera LPM
//
// Added By Jamil Khatib
//
wire wr;
assign wr = ce & we;
initial $display("Using Altera LPM.");
lpm_ram_dq lpm_ram_dq_component (
.address(addr),
.inclock(clk),
.outclock(clk),
.data(di),
.we(wr),
.q(doq)
);
defparam lpm_ram_dq_component.lpm_width = dw,
lpm_ram_dq_component.lpm_widthad = aw,
lpm_ram_dq_component.lpm_indata = "REGISTERED",
lpm_ram_dq_component.lpm_address_control = "REGISTERED",
lpm_ram_dq_component.lpm_outdata = "UNREGISTERED",
lpm_ram_dq_component.lpm_hint = "USE_EAB=ON";
// examplar attribute lpm_ram_dq_component NOOPT TRUE
`else
//
// Generic single-port synchronous RAM model
//
//
// Generic RAM's registers and wires
//
reg [dw-1:0] mem [(1<<aw)-1:0]; // RAM content
reg [aw-1:0] addr_reg; // RAM address register
//
// Data output drivers
//
assign doq = (oe) ? mem[addr_reg] : {dw{1'b0}};
//
// RAM address register
//
always @(posedge clk or posedge rst)
if (rst)
addr_reg <= #1 {aw{1'b0}};
else if (ce)
addr_reg <= #1 addr;
//
// RAM write
//
always @(posedge clk)
if (ce && we)
mem[addr] <= #1 di;
`endif // !OR1200_ALTERA_LPM
`endif // !OR1200_XILINX_RAMB4_S16
`endif // !OR1200_VIRTUALSILICON_SSP
`endif // !OR1200_VIRAGE_SSP
`endif // !OR1200_AVANT_ATP
`endif // !OR1200_ARTISAN_SSP
endmodule
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: rx_trn_data_fsm
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Receive TRN Data FSM. This module interfaces to the Block Plus RX
// TRN. It presents the 64-bit data from completer and and forwards that
// data with a data_valid signal. This block also decodes packet header info
// and forwards it to the rx_trn_monitor block.
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rx_trn_data_fsm(
input wire clk,
input wire rst,
// Rx Local-Link
input wire [63:0] trn_rd,
input wire [7:0] trn_rrem_n,
input wire trn_rsof_n,
input wire trn_reof_n,
input wire trn_rsrc_rdy_n,
input wire trn_rsrc_dsc_n,
output reg trn_rdst_rdy_n,
input wire trn_rerrfwd_n,
output wire trn_rnp_ok_n,
input wire [6:0] trn_rbar_hit_n,
input wire [11:0] trn_rfc_npd_av,
input wire [7:0] trn_rfc_nph_av,
input wire [11:0] trn_rfc_pd_av,
input wire [7:0] trn_rfc_ph_av,
input wire [11:0] trn_rfc_cpld_av,
input wire [7:0] trn_rfc_cplh_av,
output wire trn_rcpl_streaming_n,
//DATA FIFO SIGNALS
output reg [63:0] data_out,
output wire [7:0] data_out_be,
output reg data_valid,
input wire data_fifo_status,
//END DATA FIFO SIGNALS
//HEADER FIELD SIGNALS
//The following are registered from the header fields of the current packet
//See the PCIe Base Specification for definitions of these headers
output reg fourdw_n_threedw, //fourdw = 1'b1; 3dw = 1'b0;
output reg payload,
output reg [2:0] tc, //traffic class
output reg td, //digest
output reg ep, //poisoned bit
output reg [1:0] attr, //attribute field
output reg [9:0] dw_length, //DWORD Length
//the following fields are dependent on the type of TLP being received
//regs with MEM prefix are valid for memory TLPS and regs with CMP prefix
//are valid for completion TLPS
output reg [15:0] MEM_req_id, //requester ID for memory TLPs
output reg [7:0] MEM_tag, //tag for non-posted memory read request
output reg [15:0] CMP_comp_id, //completer id for completion TLPs
output reg [2:0]CMP_compl_stat, //status for completion TLPs
output reg CMP_bcm, //byte count modified field for completions TLPs
output reg [11:0] CMP_byte_count, //remaining byte count for completion TLPs
output reg [63:0] MEM_addr, //address field for memory TLPs
output reg [15:0] CMP_req_id, //requester if for completions TLPs
output reg [7:0] CMP_tag, //tag field for completion TLPs
output reg [6:0] CMP_lower_addr, //lower address field for completion TLPs
//decode of the format field
output wire MRd, //Mem read
output wire MWr, //Mem write
output wire CplD, //Completion w/ data
output wire Msg, //Message TLP
output wire UR, //Unsupported request TLP i.e. IO, CPL,etc..
output reg [6:0] bar_hit, //valid when a BAR is hit
output reg header_fields_valid//valid signal to qualify the above header fields
//END HEADER FIELD SIGNALS
);
//state machine states
localparam IDLE = 3'b000;
localparam NOT_READY = 3'b001;
localparam SOF = 3'b010;
localparam HEAD2 = 3'b011;
localparam BODY = 3'b100;
localparam EOF = 3'b101;
//additional pipelines regs for RX TRN interface
reg [63:0] trn_rd_d1;
reg [7:0] trn_rrem_d1_n;
reg trn_rsof_d1_n;
reg trn_reof_d1_n;
reg trn_rsrc_rdy_d1_n;
reg trn_rsrc_dsc_d1_n;
reg trn_rerrfwd_d1_n;
reg [6:0] trn_rbar_hit_d1_n;
reg [11:0] trn_rfc_npd_av_d1;
reg [7:0] trn_rfc_nph_av_d1;
reg [11:0] trn_rfc_pd_av_d1;
reg [7:0] trn_rfc_ph_av_d1;
reg [11:0] trn_rfc_cpld_av_d1;
reg [7:0] trn_rfc_cplh_av_d1;
//second pipeline
reg [63:0] trn_rd_d2;
reg [7:0] trn_rrem_d2_n;
reg trn_rsof_d2_n;
reg trn_reof_d2_n;
reg trn_rsrc_rdy_d2_n;
reg trn_rsrc_dsc_d2_n;
reg trn_rerrfwd_d2_n;
reg [6:0] trn_rbar_hit_d2_n;
reg [11:0] trn_rfc_npd_av_d2;
reg [7:0] trn_rfc_nph_av_d2;
reg [11:0] trn_rfc_pd_av_d2;
reg [7:0] trn_rfc_ph_av_d2;
reg [11:0] trn_rfc_cpld_av_d2;
reg [7:0] trn_rfc_cplh_av_d2;
reg [4:0] rx_packet_type;
reg [2:0] trn_state;
wire [63:0] data_out_mux;
wire [7:0] data_out_be_mux;
reg data_valid_early;
reg rst_reg;
always@(posedge clk) rst_reg <= rst;
// TIE constant signals here
assign trn_rnp_ok_n = 1'b0;
assign trn_rcpl_streaming_n = 1'b0; //use completion streaming mode
//all the outputs of the endpoint should be pipelined
//to help meet required timing of an 8 lane design
always @ (posedge clk)
begin
trn_rd_d1[63:0] <= trn_rd[63:0] ;
trn_rrem_d1_n[7:0] <= trn_rrem_n[7:0] ;
trn_rsof_d1_n <= trn_rsof_n ;
trn_reof_d1_n <= trn_reof_n ;
trn_rsrc_rdy_d1_n <= trn_rsrc_rdy_n ;
trn_rsrc_dsc_d1_n <= trn_rsrc_dsc_n ;
trn_rerrfwd_d1_n <= trn_rerrfwd_n ;
trn_rbar_hit_d1_n[6:0] <= trn_rbar_hit_n[6:0] ;
trn_rfc_npd_av_d1[11:0] <= trn_rfc_npd_av[11:0] ;
trn_rfc_nph_av_d1[7:0] <= trn_rfc_nph_av[7:0] ;
trn_rfc_pd_av_d1[11:0] <= trn_rfc_pd_av[11:0] ;
trn_rfc_ph_av_d1[7:0] <= trn_rfc_ph_av[7:0] ;
trn_rfc_cpld_av_d1[11:0] <= trn_rfc_cpld_av[11:0];
trn_rfc_cplh_av_d1[7:0] <= trn_rfc_cplh_av[7:0] ;
trn_rd_d2[63:0] <= trn_rd_d1[63:0] ;
trn_rrem_d2_n[7:0] <= trn_rrem_d1_n[7:0] ;
trn_rsof_d2_n <= trn_rsof_d1_n ;
trn_reof_d2_n <= trn_reof_d1_n ;
trn_rsrc_rdy_d2_n <= trn_rsrc_rdy_d1_n ;
trn_rsrc_dsc_d2_n <= trn_rsrc_dsc_d1_n ;
trn_rerrfwd_d2_n <= trn_rerrfwd_d1_n ;
trn_rbar_hit_d2_n[6:0] <= trn_rbar_hit_d1_n[6:0] ;
trn_rfc_npd_av_d2[11:0] <= trn_rfc_npd_av_d1[11:0] ;
trn_rfc_nph_av_d2[7:0] <= trn_rfc_nph_av_d1[7:0] ;
trn_rfc_pd_av_d2[11:0] <= trn_rfc_pd_av_d1[11:0] ;
trn_rfc_ph_av_d2[7:0] <= trn_rfc_ph_av_d1[7:0] ;
trn_rfc_cpld_av_d2[11:0] <= trn_rfc_cpld_av_d1[11:0];
trn_rfc_cplh_av_d2[7:0] <= trn_rfc_cplh_av_d1[7:0] ;
end
assign rx_sof_d1 = ~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n;
// Assign packet type information about the current RX Packet
// rx_packet_type is decoded in always block directly below these assigns
assign MRd = rx_packet_type[4];
assign MWr = rx_packet_type[3];
assign CplD = rx_packet_type[2];
assign Msg = rx_packet_type[1];
assign UR = rx_packet_type[0];
//register the packet header fields and decode the packet type
//both memory and completion TLP header fields are registered for each
//received packet, however, only the fields for the incoming type will be
//valid
always@(posedge clk )
begin
if(rst_reg)begin
rx_packet_type[4:0] <= 5'b00000;
fourdw_n_threedw <= 0;
payload <= 0;
tc[2:0] <= 0; //traffic class
td <= 0; //digest
ep <= 0; //poisoned bit
attr[1:0] <= 0;
dw_length[9:0] <= 0;
MEM_req_id[15:0] <= 0;
MEM_tag[7:0] <= 0;
CMP_comp_id[15:0] <= 0;
CMP_compl_stat[2:0] <= 0;
CMP_bcm <= 0;
CMP_byte_count[11:0] <= 0;
end else begin
if(rx_sof_d1)begin
//these fields same for all TLPs
fourdw_n_threedw <= trn_rd_d1[61];
payload <= trn_rd_d1[62];
tc[2:0] <= trn_rd_d1[54:52]; //traffic class
td <= trn_rd_d1[47]; //digest
ep <= trn_rd_d1[46]; //poisoned bit
attr[1:0] <= trn_rd_d1[45:44];
dw_length[9:0] <= trn_rd_d1[41:32];
//also latch bar_hit
bar_hit[6:0] <= ~trn_rbar_hit_d1_n[6:0];
//these following fields dependent on packet type
//i.e. memory packet fields are only valid for mem packet types
//and completer packet fields are only valid for completer packet type;
//memory packet fields
MEM_req_id[15:0] <= trn_rd_d1[31:16];
MEM_tag[7:0] <= trn_rd_d1[15:8];
//first and last byte enables not needed because plus core delivers
//completer packet fields
CMP_comp_id[15:0] <= trn_rd_d1[31:16];
CMP_compl_stat[2:0] <= trn_rd_d1[15:13];
CMP_bcm <= trn_rd_d1[12];
CMP_byte_count[11:0] <= trn_rd_d1[11:0];
//add message fields here if needed
//decode the packet type and register in rx_packet_type
casex({trn_rd_d1[62],trn_rd_d1[60:56]})
6'b000000: begin //mem read
rx_packet_type[4:0] <= 5'b10000;
end
6'b100000: begin //mem write
rx_packet_type[4:0] <= 5'b01000;
end
6'b101010: begin //completer with data
rx_packet_type[4:0] <= 5'b00100;
end
6'bx10xxx: begin //message
rx_packet_type[4:0] <= 5'b00010;
end
default: begin //all other packet types are unsupported for this design
rx_packet_type[4:0] <= 5'b00001;
end
endcase
end
end
end
// Now do the same for the second header of the current packet
always@(posedge clk )begin
if(rst_reg)begin
MEM_addr[63:0] <= 0;
CMP_req_id[15:0] <= 0;
CMP_tag[7:0] <= 0;
CMP_lower_addr[6:0] <= 0;
end else begin
if(trn_state == SOF & ~trn_rsrc_rdy_d1_n)begin //packet is in process of
//reading out second header
if(fourdw_n_threedw)
MEM_addr[63:0] <= trn_rd_d1[63:0];
else
MEM_addr[63:0] <= {32'h00000000,trn_rd_d1[63:32]};
CMP_req_id[15:0] <= trn_rd_d1[63:48];
CMP_tag[7:0] <= trn_rd_d1[47:40];
CMP_lower_addr[6:0] <= trn_rd_d1[48:32];
end
end
end
// generate a valid signal for the headers field
always@(posedge clk)begin
if(rst_reg)
header_fields_valid <= 0;
else
header_fields_valid <= ~trn_rsrc_rdy_d2_n & trn_rsof_d1_n;
end
//This state machine keeps track of what state the RX TRN interface
//is currently in
always @ (posedge clk )
begin
if(rst_reg)
begin
trn_state <= IDLE;
trn_rdst_rdy_n <= 1'b0;
end
else
begin
case(trn_state)
IDLE: begin
trn_rdst_rdy_n <= 1'b0;
if(rx_sof_d1)
trn_state <= SOF;
else
trn_state <= IDLE;
end
/// Jiansong: notice, completion streaming here
NOT_READY: begin // This state is a placeholder only - it is currently not
// entered from any other state
// This state could be used for throttling the PCIe
// Endpoint Block Plus RX TRN interface, however, this
// should not be done when using completion streaming
// mode as this reference design does
trn_rdst_rdy_n <= 1'b1;
trn_state <= IDLE;
end
SOF: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= HEAD2;
else
trn_state <= SOF;
end
HEAD2: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else if(trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= BODY;
else
trn_state <= HEAD2;
end
BODY: begin
if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= BODY;
end
EOF: begin
if(~trn_rsof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= SOF;
else if(trn_rsof_d1_n & trn_rsrc_rdy_d1_n)
trn_state <= IDLE;
else if(~trn_reof_d1_n & ~trn_rsrc_rdy_d1_n)
trn_state <= EOF;
else
trn_state <= IDLE;
end
default: begin
trn_state <= IDLE;
end
endcase
end
end
//data shifter logic
//need to shift the data depending if we receive a four DWORD or three DWORD
//TLP type - Note that completion packets will always be 3DW TLPs
assign data_out_mux[63:0] = (fourdw_n_threedw)
? trn_rd_d2[63:0]
: {trn_rd_d2[31:0],trn_rd_d1[63:32]};
/// Jiansong: notice, why? 64bit data? likely should be modified
//swap the byte ordering to little endian
//e.g. data_out = B7,B6,B5,B4,B3,B2,B1,B0
always@(posedge clk)
data_out[63:0] <= {data_out_mux[7:0],data_out_mux[15:8],
data_out_mux[23:16],data_out_mux[31:24],
data_out_mux[39:32],data_out_mux[47:40],
data_out_mux[55:48],data_out_mux[63:56]};
//Data byte enable logic:
//Need to add byte enable logic for incoming memory transactions if desired
//to allow memory transaction granularity smaller than DWORD.
//
//This design always requests data on 128 byte boundaries so for
//completion TLPs the byte enables would always be asserted
//
//Note that the endpoint block plus uses negative logic, however,
//I decided to use positive logic for the user application.
assign data_out_be = 8'hff;
//data_valid generation logic
//Generally, data_valid should be asserted the same amount of cycles
//that trn_rsrc_rdy_n is asserted (minus the cycles that sof and
//eof are asserted).
//There are two exceptions to this:
// - 3DW TLPs with odd number of DW without Digest
// In this case an extra cycle is required
// - eof is used to generate this extra cycle
// - 4DW TLPs with even number of DW with Digest
// In this case an extra cycle needs to be removed
// - the last cycle is removed
// Jiansong: fix Mrd data to fifo bug
always@(*)begin
case({fourdw_n_threedw, dw_length[0], td})
3'b010: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& ~trn_reof_d2_n
& payload;
3'b101: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_reof_d1_n
& payload;
default: data_valid_early = ~trn_rsrc_rdy_d2_n
& trn_rsof_d2_n
& trn_reof_d2_n
& payload;
endcase
end
//delay by one clock to match data_out (and presumably data_out_be)
always@(posedge clk)
if(rst_reg)
data_valid <= 1'b0;
else
data_valid <= data_valid_early;
endmodule
|
/******************************************************************************
* License Agreement *
* *
* Copyright (c) 1991-2012 Altera Corporation, San Jose, California, USA. *
* All rights reserved. *
* *
* Any megafunction design, and related net list (encrypted or decrypted), *
* support information, device programming or simulation file, and any other *
* associated documentation or information provided by Altera or a partner *
* under Altera's Megafunction Partnership Program may be used only to *
* program PLD devices (but not masked PLD devices) from Altera. Any other *
* use of such megafunction design, net list, support information, device *
* programming or simulation file, or any other related documentation or *
* information is prohibited for any other purpose, including, but not *
* limited to modification, reverse engineering, de-compiling, or use with *
* any other silicon devices, unless such use is explicitly licensed under *
* a separate agreement with Altera or a megafunction partner. Title to *
* the intellectual property, including patents, copyrights, trademarks, *
* trade secrets, or maskworks, embodied in any such megafunction design, *
* net list, support information, device programming or simulation file, or *
* any other related documentation or information provided by Altera or a *
* megafunction partner, remains with Altera, the megafunction partner, or *
* their respective licensors. No other licenses, including any licenses *
* needed under any third party's intellectual property, are provided herein.*
* Copying or modifying any file, or portion thereof, to which this notice *
* is attached violates this copyright. *
* *
* THIS FILE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL *
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
* FROM, OUT OF OR IN CONNECTION WITH THIS FILE OR THE USE OR OTHER DEALINGS *
* IN THIS FILE. *
* *
* This agreement shall be governed in all respects by the laws of the State *
* of California and by the laws of the United States of America. *
* *
******************************************************************************/
/******************************************************************************
* *
* This module is a rom for auto initializing the on board ADV7180 video chip.*
* *
******************************************************************************/
module altera_up_av_config_auto_init_ob_adv7180 (
// Inputs
rom_address,
// Bidirectionals
// Outputs
rom_data
);
/*****************************************************************************
* Parameter Declarations *
*****************************************************************************/
parameter INPUT_CTRL = 16'h0000;
parameter VIDEO_SELECTION = 16'h01C8;
parameter OUTPUT_CTRL = 16'h030C;
parameter EXT_OUTPUT_CTRL = 16'h0445;
parameter AUTODETECT = 16'h077F;
parameter BRIGHTNESS = 16'h0A00;
parameter HUE = 16'h0B00;
parameter DEFAULT_VALUE_Y = 16'h0C36;
parameter DEFAULT_VALUE_C = 16'h0D7C;
parameter POWER_MGMT = 16'h0F00;
parameter ANALOG_CLAMP_CTRL = 16'h1412;
parameter DIGITAL_CLAMP_CTRL = 16'h1500;
parameter SHAPING_FILTER_CTRL_1 = 16'h1701;
parameter SHAPING_FILTER_CTRL_2 = 16'h1893;
parameter COMB_FILTER_CTRL_2 = 16'h19F1;
parameter PIXEL_DELAY_CTRL = 16'h2758;
parameter MISC_GAIN_CTRL = 16'h2BE1;
parameter AGC_MODE_CTRL = 16'h2CAE;
parameter CHROMA_GAIN_CTRL_1 = 16'h2DF4;
parameter CHROMA_GAIN_CTRL_2 = 16'h2E00;
parameter LUMA_GAIN_CTRL_1 = 16'h2FF0;
parameter LUMA_GAIN_CTRL_2 = 16'h3000;
parameter VSYNC_FIELD_CTRL_1 = 16'h3112;
parameter VSYNC_FIELD_CTRL_2 = 16'h3241;
parameter VSYNC_FIELD_CTRL_3 = 16'h3384;
parameter HSYNC_FIELD_CTRL_1 = 16'h3400;
parameter HSYNC_FIELD_CTRL_2 = 16'h3502;
parameter HSYNC_FIELD_CTRL_3 = 16'h3600;
parameter POLARITY = 16'h3701;
parameter NTSC_COMB_CTRL = 16'h3880;
parameter PAL_COMB_CTRL = 16'h39C0;
parameter ADC_CTRL = 16'h3A10;
parameter MANUAL_WINDOW_CTRL = 16'h3DB2;
parameter RESAMPLE_CONTROL = 16'h4101;
parameter CRC = 16'hB21C;
parameter ADC_SWITCH_1 = 16'hC300;
parameter ADC_SWITCH_2 = 16'hC400;
parameter LETTERBOX_CTRL_1 = 16'hDCAC;
parameter LETTERBOX_CTRL_2 = 16'hDD4C;
parameter NTSC_V_BIT_BEGIN = 16'hE525;
parameter NTSC_V_BIT_END = 16'hE604;
parameter NTSC_F_BIT_TOGGLE = 16'hE763;
parameter PAL_V_BIT_BEGIN = 16'hE865;
parameter PAL_V_BIT_END = 16'hE914;
parameter PAL_F_BIT_TOGGLE = 16'hEA63;
parameter VBLANK_CTRL_1 = 16'hEB55;
parameter VBLANK_CTRL_2 = 16'hEC55;
/*****************************************************************************
* Port Declarations *
*****************************************************************************/
// Inputs
input [ 5: 0] rom_address;
// Bidirectionals
// Outputs
output [26: 0] rom_data;
/*****************************************************************************
* Constant Declarations *
*****************************************************************************/
// States
/*****************************************************************************
* Internal Wires and Registers Declarations *
*****************************************************************************/
// Internal Wires
reg [23: 0] data;
// Internal Registers
// State Machine Registers
/*****************************************************************************
* Finite State Machine(s) *
*****************************************************************************/
/*****************************************************************************
* Sequential Logic *
*****************************************************************************/
// Output Registers
// Internal Registers
/*****************************************************************************
* Combinational Logic *
*****************************************************************************/
// Output Assignments
assign rom_data = {data[23:16], 1'b0,
data[15: 8], 1'b0,
data[ 7: 0], 1'b0};
// Internal Assignments
always @(*)
begin
case (rom_address)
// Video Config Data
10 : data <= {8'h40, INPUT_CTRL};
11 : data <= {8'h40, VIDEO_SELECTION};
12 : data <= {8'h40, OUTPUT_CTRL};
13 : data <= {8'h40, EXT_OUTPUT_CTRL};
14 : data <= {8'h40, AUTODETECT};
15 : data <= {8'h40, BRIGHTNESS};
16 : data <= {8'h40, HUE};
17 : data <= {8'h40, DEFAULT_VALUE_Y};
18 : data <= {8'h40, DEFAULT_VALUE_C};
19 : data <= {8'h40, POWER_MGMT};
20 : data <= {8'h40, ANALOG_CLAMP_CTRL};
21 : data <= {8'h40, DIGITAL_CLAMP_CTRL};
22 : data <= {8'h40, SHAPING_FILTER_CTRL_1};
23 : data <= {8'h40, SHAPING_FILTER_CTRL_2};
24 : data <= {8'h40, COMB_FILTER_CTRL_2};
25 : data <= {8'h40, PIXEL_DELAY_CTRL};
26 : data <= {8'h40, MISC_GAIN_CTRL};
27 : data <= {8'h40, AGC_MODE_CTRL};
28 : data <= {8'h40, CHROMA_GAIN_CTRL_1};
29 : data <= {8'h40, CHROMA_GAIN_CTRL_2};
30 : data <= {8'h40, LUMA_GAIN_CTRL_1};
31 : data <= {8'h40, LUMA_GAIN_CTRL_2};
32 : data <= {8'h40, VSYNC_FIELD_CTRL_1};
33 : data <= {8'h40, VSYNC_FIELD_CTRL_2};
34 : data <= {8'h40, VSYNC_FIELD_CTRL_3};
35 : data <= {8'h40, HSYNC_FIELD_CTRL_1};
36 : data <= {8'h40, HSYNC_FIELD_CTRL_2};
37 : data <= {8'h40, HSYNC_FIELD_CTRL_3};
38 : data <= {8'h40, POLARITY};
39 : data <= {8'h40, NTSC_COMB_CTRL};
40 : data <= {8'h40, PAL_COMB_CTRL};
41 : data <= {8'h40, ADC_CTRL};
42 : data <= {8'h40, MANUAL_WINDOW_CTRL};
43 : data <= {8'h40, RESAMPLE_CONTROL};
44 : data <= {8'h40, CRC};
45 : data <= {8'h40, ADC_SWITCH_1};
46 : data <= {8'h40, ADC_SWITCH_2};
47 : data <= {8'h40, LETTERBOX_CTRL_1};
48 : data <= {8'h40, LETTERBOX_CTRL_2};
49 : data <= {8'h40, NTSC_V_BIT_BEGIN};
50 : data <= {8'h40, NTSC_V_BIT_END};
51 : data <= {8'h40, NTSC_F_BIT_TOGGLE};
52 : data <= {8'h40, PAL_V_BIT_BEGIN};
53 : data <= {8'h40, PAL_V_BIT_END};
54 : data <= {8'h40, PAL_F_BIT_TOGGLE};
55 : data <= {8'h40, VBLANK_CTRL_1};
56 : data <= {8'h40, VBLANK_CTRL_2};
default : data <= {8'h00, 16'h0000};
endcase
end
/*****************************************************************************
* Internal Modules *
*****************************************************************************/
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2014 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
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// (including loss of data, profits, goodwill, or any type of
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// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ddr_mc_phy_wrapper.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Oct 10 2010
// \___\/\___\
//
//Device : 7 Series
//Design Name : DDR3 SDRAM
//Purpose : Wrapper file that encompasses the MC_PHY module
// instantiation and handles the vector remapping between
// the MC_PHY ports and the user's DDR3 ports. Vector
// remapping affects DDR3 control, address, and DQ/DQS/DM.
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1 ps / 1 ps
module mig_7series_v2_3_ddr_mc_phy_wrapper #
(
parameter TCQ = 100, // Register delay (simulation only)
parameter tCK = 2500, // ps
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter DATA_IO_PRIM_TYPE = "DEFAULT", // # = "HP_LP", "HR_LP", "DEFAULT"
parameter DATA_IO_IDLE_PWRDWN = "ON", // "ON" or "OFF"
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter nCK_PER_CLK = 4, // Memory:Logic clock ratio
parameter nCS_PER_RANK = 1, // # of unique CS outputs per rank
parameter BANK_WIDTH = 3, // # of bank address
parameter CKE_WIDTH = 1, // # of clock enable outputs
parameter CS_WIDTH = 1, // # of chip select
parameter CK_WIDTH = 1, // # of CK
parameter CWL = 5, // CAS Write latency
parameter DDR2_DQSN_ENABLE = "YES", // Enable differential DQS for DDR2
parameter DM_WIDTH = 8, // # of data mask
parameter DQ_WIDTH = 16, // # of data bits
parameter DQS_CNT_WIDTH = 3, // ceil(log2(DQS_WIDTH))
parameter DQS_WIDTH = 8, // # of strobe pairs
parameter DRAM_TYPE = "DDR3", // DRAM type (DDR2, DDR3)
parameter RANKS = 4, // # of ranks
parameter ODT_WIDTH = 1, // # of ODT outputs
parameter POC_USE_METASTABLE_SAMP = "FALSE",
parameter REG_CTRL = "OFF", // "ON" for registered DIMM
parameter ROW_WIDTH = 16, // # of row/column address
parameter USE_CS_PORT = 1, // Support chip select output
parameter USE_DM_PORT = 1, // Support data mask output
parameter USE_ODT_PORT = 1, // Support ODT output
parameter IBUF_LPWR_MODE = "OFF", // input buffer low power option
parameter LP_DDR_CK_WIDTH = 2,
// Hard PHY parameters
parameter PHYCTL_CMD_FIFO = "FALSE",
parameter DATA_CTL_B0 = 4'hc,
parameter DATA_CTL_B1 = 4'hf,
parameter DATA_CTL_B2 = 4'hf,
parameter DATA_CTL_B3 = 4'hf,
parameter DATA_CTL_B4 = 4'hf,
parameter BYTE_LANES_B0 = 4'b1111,
parameter BYTE_LANES_B1 = 4'b0000,
parameter BYTE_LANES_B2 = 4'b0000,
parameter BYTE_LANES_B3 = 4'b0000,
parameter BYTE_LANES_B4 = 4'b0000,
parameter PHY_0_BITLANES = 48'h0000_0000_0000,
parameter PHY_1_BITLANES = 48'h0000_0000_0000,
parameter PHY_2_BITLANES = 48'h0000_0000_0000,
// Parameters calculated outside of this block
parameter HIGHEST_BANK = 3, // Highest I/O bank index
parameter HIGHEST_LANE = 12, // Highest byte lane index
// ** Pin mapping parameters
// Parameters for mapping between hard PHY and physical DDR3 signals
// There are 2 classes of parameters:
// - DQS_BYTE_MAP, CK_BYTE_MAP, CKE_ODT_BYTE_MAP: These consist of
// 8-bit elements. Each element indicates the bank and byte lane
// location of that particular signal. The bit lane in this case
// doesn't need to be specified, either because there's only one
// pin pair in each byte lane that the DQS or CK pair can be
// located at, or in the case of CKE_ODT_BYTE_MAP, only the byte
// lane needs to be specified in order to determine which byte
// lane generates the RCLK (Note that CKE, and ODT must be located
// in the same bank, thus only one element in CKE_ODT_BYTE_MAP)
// [7:4] = bank # (0-4)
// [3:0] = byte lane # (0-3)
// - All other MAP parameters: These consist of 12-bit elements. Each
// element indicates the bank, byte lane, and bit lane location of
// that particular signal:
// [11:8] = bank # (0-4)
// [7:4] = byte lane # (0-3)
// [3:0] = bit lane # (0-11)
// Note that not all elements in all parameters will be used - it
// depends on the actual widths of the DDR3 buses. The parameters are
// structured to support a maximum of:
// - DQS groups: 18
// - data mask bits: 18
// In addition, the default parameter size of some of the parameters will
// support a certain number of bits, however, this can be expanded at
// compile time by expanding the width of the vector passed into this
// parameter
// - chip selects: 10
// - bank bits: 3
// - address bits: 16
parameter CK_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
parameter ADDR_MAP
= 192'h000_000_000_000_000_000_000_000_000_000_000_000_000_000_000_000,
parameter BANK_MAP = 36'h000_000_000,
parameter CAS_MAP = 12'h000,
parameter CKE_ODT_BYTE_MAP = 8'h00,
parameter CKE_MAP = 96'h000_000_000_000_000_000_000_000,
parameter ODT_MAP = 96'h000_000_000_000_000_000_000_000,
parameter CKE_ODT_AUX = "FALSE",
parameter CS_MAP = 120'h000_000_000_000_000_000_000_000_000_000,
parameter PARITY_MAP = 12'h000,
parameter RAS_MAP = 12'h000,
parameter WE_MAP = 12'h000,
parameter DQS_BYTE_MAP
= 144'h00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00_00,
// DATAx_MAP parameter is used for byte lane X in the design
parameter DATA0_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA1_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA2_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA3_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA4_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA5_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA6_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA7_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA8_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA9_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA10_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA11_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA12_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA13_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA14_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA15_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA16_MAP = 96'h000_000_000_000_000_000_000_000,
parameter DATA17_MAP = 96'h000_000_000_000_000_000_000_000,
// MASK0_MAP used for bytes [8:0], MASK1_MAP for bytes [17:9]
parameter MASK0_MAP = 108'h000_000_000_000_000_000_000_000_000,
parameter MASK1_MAP = 108'h000_000_000_000_000_000_000_000_000,
// Simulation options
parameter SIM_CAL_OPTION = "NONE",
// The PHY_CONTROL primitive in the bank where PLL exists is declared
// as the Master PHY_CONTROL.
parameter MASTER_PHY_CTL = 1,
parameter DRAM_WIDTH = 8
)
(
input rst,
input iddr_rst,
input clk,
input freq_refclk,
input mem_refclk,
input pll_lock,
input sync_pulse,
input mmcm_ps_clk,
input idelayctrl_refclk,
input phy_cmd_wr_en,
input phy_data_wr_en,
input [31:0] phy_ctl_wd,
input phy_ctl_wr,
input phy_if_empty_def,
input phy_if_reset,
input [5:0] data_offset_1,
input [5:0] data_offset_2,
input [3:0] aux_in_1,
input [3:0] aux_in_2,
output [4:0] idelaye2_init_val,
output [5:0] oclkdelay_init_val,
output if_empty,
output phy_ctl_full,
output phy_cmd_full,
output phy_data_full,
output phy_pre_data_a_full,
output [(CK_WIDTH * LP_DDR_CK_WIDTH)-1:0] ddr_clk,
output phy_mc_go,
input phy_write_calib,
input phy_read_calib,
input calib_in_common,
input [5:0] calib_sel,
input [DQS_CNT_WIDTH:0] byte_sel_cnt,
input [DRAM_WIDTH-1:0] fine_delay_incdec_pb,
input fine_delay_sel,
input [HIGHEST_BANK-1:0] calib_zero_inputs,
input [HIGHEST_BANK-1:0] calib_zero_ctrl,
input [2:0] po_fine_enable,
input [2:0] po_coarse_enable,
input [2:0] po_fine_inc,
input [2:0] po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [2:0] po_sel_fine_oclk_delay,
input [8:0] po_counter_load_val,
output [8:0] po_counter_read_val,
output [5:0] pi_counter_read_val,
input [HIGHEST_BANK-1:0] pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input [5:0] pi_counter_load_val,
input idelay_ce,
input idelay_inc,
input idelay_ld,
input idle,
output pi_phase_locked,
output pi_phase_locked_all,
output pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_out_of_range,
// From/to calibration logic/soft PHY
input phy_init_data_sel,
input [nCK_PER_CLK*ROW_WIDTH-1:0] mux_address,
input [nCK_PER_CLK*BANK_WIDTH-1:0] mux_bank,
input [nCK_PER_CLK-1:0] mux_cas_n,
input [CS_WIDTH*nCS_PER_RANK*nCK_PER_CLK-1:0] mux_cs_n,
input [nCK_PER_CLK-1:0] mux_ras_n,
input [1:0] mux_odt,
input [nCK_PER_CLK-1:0] mux_cke,
input [nCK_PER_CLK-1:0] mux_we_n,
input [nCK_PER_CLK-1:0] parity_in,
input [2*nCK_PER_CLK*DQ_WIDTH-1:0] mux_wrdata,
input [2*nCK_PER_CLK*(DQ_WIDTH/8)-1:0] mux_wrdata_mask,
input mux_reset_n,
output [2*nCK_PER_CLK*DQ_WIDTH-1:0] rd_data,
// Memory I/F
output [ROW_WIDTH-1:0] ddr_addr,
output [BANK_WIDTH-1:0] ddr_ba,
output ddr_cas_n,
output [CKE_WIDTH-1:0] ddr_cke,
output [CS_WIDTH*nCS_PER_RANK-1:0] ddr_cs_n,
output [DM_WIDTH-1:0] ddr_dm,
output [ODT_WIDTH-1:0] ddr_odt,
output ddr_parity,
output ddr_ras_n,
output ddr_we_n,
output ddr_reset_n,
inout [DQ_WIDTH-1:0] ddr_dq,
inout [DQS_WIDTH-1:0] ddr_dqs,
inout [DQS_WIDTH-1:0] ddr_dqs_n,
//output iodelay_ctrl_rdy,
output pd_out
,input dbg_pi_counter_read_en
,output ref_dll_lock
,input rst_phaser_ref
,output [11:0] dbg_pi_phase_locked_phy4lanes
,output [11:0] dbg_pi_dqs_found_lanes_phy4lanes
);
function [71:0] generate_bytelanes_ddr_ck;
input [143:0] ck_byte_map;
integer v ;
begin
generate_bytelanes_ddr_ck = 'b0 ;
for (v = 0; v < CK_WIDTH; v = v + 1) begin
if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 2)
generate_bytelanes_ddr_ck[48+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else if ((CK_BYTE_MAP[((v*8)+4)+:4]) == 1)
generate_bytelanes_ddr_ck[24+(4*v)+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
else
generate_bytelanes_ddr_ck[4*v+1*(CK_BYTE_MAP[(v*8)+:4])] = 1'b1;
end
end
endfunction
function [(2*CK_WIDTH*8)-1:0] generate_ddr_ck_map;
input [143:0] ck_byte_map;
integer g;
begin
generate_ddr_ck_map = 'b0 ;
for(g = 0 ; g < CK_WIDTH ; g= g + 1) begin
generate_ddr_ck_map[(g*2*8)+:8] = (ck_byte_map[(g*8)+:4] == 4'd0) ? "A" :
(ck_byte_map[(g*8)+:4] == 4'd1) ? "B" :
(ck_byte_map[(g*8)+:4] == 4'd2) ? "C" : "D" ;
generate_ddr_ck_map[(((g*2)+1)*8)+:8] = (ck_byte_map[((g*8)+4)+:4] == 4'd0) ? "0" :
(ck_byte_map[((g*8)+4)+:4] == 4'd1) ? "1" : "2" ; //each STRING charater takes 0 location
end
end
endfunction
// Enable low power mode for input buffer
localparam IBUF_LOW_PWR
= (IBUF_LPWR_MODE == "OFF") ? "FALSE" :
((IBUF_LPWR_MODE == "ON") ? "TRUE" : "ILLEGAL");
// Ratio of data to strobe
localparam DQ_PER_DQS = DQ_WIDTH / DQS_WIDTH;
// number of data phases per internal clock
localparam PHASE_PER_CLK = 2*nCK_PER_CLK;
// used to determine routing to OUT_FIFO for control/address for 2:1
// vs. 4:1 memory:internal clock ratio modes
localparam PHASE_DIV = 4 / nCK_PER_CLK;
localparam CLK_PERIOD = tCK * nCK_PER_CLK;
// Create an aggregate parameters for data mapping to reduce # of generate
// statements required in remapping code. Need to account for the case
// when the DQ:DQS ratio is not 8:1 - in this case, each DATAx_MAP
// parameter will have fewer than 8 elements used
localparam FULL_DATA_MAP = {DATA17_MAP[12*DQ_PER_DQS-1:0],
DATA16_MAP[12*DQ_PER_DQS-1:0],
DATA15_MAP[12*DQ_PER_DQS-1:0],
DATA14_MAP[12*DQ_PER_DQS-1:0],
DATA13_MAP[12*DQ_PER_DQS-1:0],
DATA12_MAP[12*DQ_PER_DQS-1:0],
DATA11_MAP[12*DQ_PER_DQS-1:0],
DATA10_MAP[12*DQ_PER_DQS-1:0],
DATA9_MAP[12*DQ_PER_DQS-1:0],
DATA8_MAP[12*DQ_PER_DQS-1:0],
DATA7_MAP[12*DQ_PER_DQS-1:0],
DATA6_MAP[12*DQ_PER_DQS-1:0],
DATA5_MAP[12*DQ_PER_DQS-1:0],
DATA4_MAP[12*DQ_PER_DQS-1:0],
DATA3_MAP[12*DQ_PER_DQS-1:0],
DATA2_MAP[12*DQ_PER_DQS-1:0],
DATA1_MAP[12*DQ_PER_DQS-1:0],
DATA0_MAP[12*DQ_PER_DQS-1:0]};
// Same deal, but for data mask mapping
localparam FULL_MASK_MAP = {MASK1_MAP, MASK0_MAP};
localparam TMP_BYTELANES_DDR_CK = generate_bytelanes_ddr_ck(CK_BYTE_MAP) ;
localparam TMP_GENERATE_DDR_CK_MAP = generate_ddr_ck_map(CK_BYTE_MAP) ;
// Temporary parameters to determine which bank is outputting the CK/CK#
// Eventually there will be support for multiple CK/CK# output
//localparam TMP_DDR_CLK_SELECT_BANK = (CK_BYTE_MAP[7:4]);
//// Temporary method to force MC_PHY to generate ODDR associated with
//// CK/CK# output only for a single byte lane in the design. All banks
//// that won't be generating the CK/CK# will have "UNUSED" as their
//// PHY_GENERATE_DDR_CK parameter
//localparam TMP_PHY_0_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 0) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_1_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 1) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
//localparam TMP_PHY_2_GENERATE_DDR_CK
// = (TMP_DDR_CLK_SELECT_BANK != 2) ? "UNUSED" :
// ((CK_BYTE_MAP[1:0] == 2'b00) ? "A" :
// ((CK_BYTE_MAP[1:0] == 2'b01) ? "B" :
// ((CK_BYTE_MAP[1:0] == 2'b10) ? "C" : "D")));
// Function to generate MC_PHY parameters PHY_BITLANES_OUTONLYx
// which indicates which bit lanes in data byte lanes are
// output-only bitlanes (e.g. used specifically for data mask outputs)
function [143:0] calc_phy_bitlanes_outonly;
input [215:0] data_mask_in;
integer z;
begin
calc_phy_bitlanes_outonly = 'b0;
// Only enable BITLANES parameters for data masks if, well, if
// the data masks are actually enabled
if (USE_DM_PORT == 1)
for (z = 0; z < DM_WIDTH; z = z + 1)
calc_phy_bitlanes_outonly[48*data_mask_in[(12*z+8)+:3] +
12*data_mask_in[(12*z+4)+:2] +
data_mask_in[12*z+:4]] = 1'b1;
end
endfunction
localparam PHY_BITLANES_OUTONLY = calc_phy_bitlanes_outonly(FULL_MASK_MAP);
localparam PHY_0_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[47:0];
localparam PHY_1_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[95:48];
localparam PHY_2_BITLANES_OUTONLY = PHY_BITLANES_OUTONLY[143:96];
// Determine which bank and byte lane generates the RCLK used to clock
// out the auxilliary (ODT, CKE) outputs
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_ON
= (CKE_ODT_BYTE_MAP[7:4] == 4'h0) ? 0 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h1) ? 1 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h2) ? 2 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h3) ? 3 :
((CKE_ODT_BYTE_MAP[7:4] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_ON
= (CKE_ODT_BYTE_MAP[3:0] == 4'h0) ? "A" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h1) ? "B" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h2) ? "C" :
((CKE_ODT_BYTE_MAP[3:0] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK_AUX_OFF
= (CKE_MAP[11:8] == 4'h0) ? 0 :
((CKE_MAP[11:8] == 4'h1) ? 1 :
((CKE_MAP[11:8] == 4'h2) ? 2 :
((CKE_MAP[11:8] == 4'h3) ? 3 :
((CKE_MAP[11:8] == 4'h4) ? 4 : -1))));
localparam CKE_ODT_RCLK_SELECT_LANE_AUX_OFF
= (CKE_MAP[7:4] == 4'h0) ? "A" :
((CKE_MAP[7:4] == 4'h1) ? "B" :
((CKE_MAP[7:4] == 4'h2) ? "C" :
((CKE_MAP[7:4] == 4'h3) ? "D" : "ILLEGAL")));
localparam CKE_ODT_RCLK_SELECT_BANK = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_BANK_AUX_ON : CKE_ODT_RCLK_SELECT_BANK_AUX_OFF ;
localparam CKE_ODT_RCLK_SELECT_LANE = (CKE_ODT_AUX == "TRUE") ? CKE_ODT_RCLK_SELECT_LANE_AUX_ON : CKE_ODT_RCLK_SELECT_LANE_AUX_OFF ;
//***************************************************************************
// OCLKDELAYED tap setting calculation:
// Parameters for calculating amount of phase shifting output clock to
// achieve 90 degree offset between DQS and DQ on writes
//***************************************************************************
//90 deg equivalent to 0.25 for MEM_RefClk <= 300 MHz
// and 1.25 for Mem_RefClk > 300 MHz
localparam PO_OCLKDELAY_INV = (((SIM_CAL_OPTION == "NONE") && (tCK > 2500)) || (tCK >= 3333)) ? "FALSE" : "TRUE";
//DIV1: MemRefClk >= 400 MHz, DIV2: 200 <= MemRefClk < 400,
//DIV4: MemRefClk < 200 MHz
localparam PHY_0_A_PI_FREQ_REF_DIV = tCK > 5000 ? "DIV4" :
tCK > 2500 ? "DIV2": "NONE";
localparam FREQ_REF_DIV = (PHY_0_A_PI_FREQ_REF_DIV == "DIV4" ? 4 :
PHY_0_A_PI_FREQ_REF_DIV == "DIV2" ? 2 : 1);
// Intrinsic delay between OCLK and OCLK_DELAYED Phaser Output
localparam real INT_DELAY = 0.4392/FREQ_REF_DIV + 100.0/tCK;
// Whether OCLK_DELAY output comes inverted or not
localparam real HALF_CYCLE_DELAY = 0.5*(PO_OCLKDELAY_INV == "TRUE" ? 1 : 0);
// Phaser-Out Stage3 Tap delay for 90 deg shift.
// Maximum tap delay is FreqRefClk period distributed over 64 taps
// localparam real TAP_DELAY = MC_OCLK_DELAY/64/FREQ_REF_DIV;
localparam real MC_OCLK_DELAY = ((PO_OCLKDELAY_INV == "TRUE" ? 1.25 : 0.25) -
(INT_DELAY + HALF_CYCLE_DELAY))
* 63 * FREQ_REF_DIV;
//localparam integer PHY_0_A_PO_OCLK_DELAY = MC_OCLK_DELAY;
localparam integer PHY_0_A_PO_OCLK_DELAY_HW
= (tCK > 2273) ? 34 :
(tCK > 2000) ? 33 :
(tCK > 1724) ? 32 :
(tCK > 1515) ? 31 :
(tCK > 1315) ? 30 :
(tCK > 1136) ? 29 :
(tCK > 1021) ? 28 : 27;
// Note that simulation requires a different value than in H/W because of the
// difference in the way delays are modeled
localparam integer PHY_0_A_PO_OCLK_DELAY = (SIM_CAL_OPTION == "NONE") ?
((tCK > 2500) ? 8 :
(DRAM_TYPE == "DDR3") ? PHY_0_A_PO_OCLK_DELAY_HW : 30) :
MC_OCLK_DELAY;
// Initial DQ IDELAY value
localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = (SIM_CAL_OPTION != "FAST_CAL") ? 0 :
(tCK < 1000) ? 0 :
(tCK < 1330) ? 0 :
(tCK < 2300) ? 0 :
(tCK < 2500) ? 2 : 0;
//localparam PHY_0_A_IDELAYE2_IDELAY_VALUE = 0;
// Aux_out parameters RD_CMD_OFFSET = CL+2? and WR_CMD_OFFSET = CWL+3?
localparam PHY_0_RD_CMD_OFFSET_0 = 10;
localparam PHY_0_RD_CMD_OFFSET_1 = 10;
localparam PHY_0_RD_CMD_OFFSET_2 = 10;
localparam PHY_0_RD_CMD_OFFSET_3 = 10;
// 4:1 and 2:1 have WR_CMD_OFFSET values for ODT timing
localparam PHY_0_WR_CMD_OFFSET_0 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_1 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_2 = (nCK_PER_CLK == 4) ? 8 : 4;
localparam PHY_0_WR_CMD_OFFSET_3 = (nCK_PER_CLK == 4) ? 8 : 4;
// 4:1 and 2:1 have different values
localparam PHY_0_WR_DURATION_0 = 7;
localparam PHY_0_WR_DURATION_1 = 7;
localparam PHY_0_WR_DURATION_2 = 7;
localparam PHY_0_WR_DURATION_3 = 7;
// Aux_out parameters for toggle mode (CKE)
localparam CWL_M = (REG_CTRL == "ON") ? CWL + 1 : CWL;
localparam PHY_0_CMD_OFFSET = (nCK_PER_CLK == 4) ? (CWL_M % 2) ? 8 : 9 :
(CWL < 7) ?
4 + ((CWL_M % 2) ? 0 : 1) :
5 + ((CWL_M % 2) ? 0 : 1);
// temporary parameter to enable/disable PHY PC counters. In both 4:1 and
// 2:1 cases, this should be disabled. For now, enable for 4:1 mode to
// avoid making too many changes at once.
localparam PHY_COUNT_EN = (nCK_PER_CLK == 4) ? "TRUE" : "FALSE";
wire [((HIGHEST_LANE+3)/4)*4-1:0] aux_out;
wire [HIGHEST_LANE-1:0] mem_dqs_in;
wire [HIGHEST_LANE-1:0] mem_dqs_out;
wire [HIGHEST_LANE-1:0] mem_dqs_ts;
wire [HIGHEST_LANE*10-1:0] mem_dq_in;
wire [HIGHEST_LANE*12-1:0] mem_dq_out;
wire [HIGHEST_LANE*12-1:0] mem_dq_ts;
wire [DQ_WIDTH-1:0] in_dq;
wire [DQS_WIDTH-1:0] in_dqs;
wire [ROW_WIDTH-1:0] out_addr;
wire [BANK_WIDTH-1:0] out_ba;
wire out_cas_n;
wire [CS_WIDTH*nCS_PER_RANK-1:0] out_cs_n;
wire [DM_WIDTH-1:0] out_dm;
wire [ODT_WIDTH -1:0] out_odt;
wire [CKE_WIDTH -1 :0] out_cke ;
wire [DQ_WIDTH-1:0] out_dq;
wire [DQS_WIDTH-1:0] out_dqs;
wire out_parity;
wire out_ras_n;
wire out_we_n;
wire [HIGHEST_LANE*80-1:0] phy_din;
wire [HIGHEST_LANE*80-1:0] phy_dout;
wire phy_rd_en;
wire [DM_WIDTH-1:0] ts_dm;
wire [DQ_WIDTH-1:0] ts_dq;
wire [DQS_WIDTH-1:0] ts_dqs;
wire [DQS_WIDTH-1:0] in_dqs_lpbk_to_iddr;
wire [DQS_WIDTH-1:0] pd_out_pre;
//wire metaQ;
reg [31:0] phy_ctl_wd_i1;
reg [31:0] phy_ctl_wd_i2;
reg phy_ctl_wr_i1;
reg phy_ctl_wr_i2;
reg [5:0] data_offset_1_i1;
reg [5:0] data_offset_1_i2;
reg [5:0] data_offset_2_i1;
reg [5:0] data_offset_2_i2;
wire [31:0] phy_ctl_wd_temp;
wire phy_ctl_wr_temp;
wire [5:0] data_offset_1_temp;
wire [5:0] data_offset_2_temp;
wire [5:0] data_offset_1_of;
wire [5:0] data_offset_2_of;
wire [31:0] phy_ctl_wd_of;
wire phy_ctl_wr_of /* synthesis syn_maxfan = 1 */;
wire [3:0] phy_ctl_full_temp;
wire data_io_idle_pwrdwn;
reg [29:0] fine_delay_mod; //3 bit per DQ
reg fine_delay_sel_r; //timing adj with fine_delay_incdec_pb
(* use_dsp48 = "no" *) wire [DQS_CNT_WIDTH:0] byte_sel_cnt_w1;
// Always read from input data FIFOs when not empty
assign phy_rd_en = !if_empty;
// IDELAYE2 initial value
assign idelaye2_init_val = PHY_0_A_IDELAYE2_IDELAY_VALUE;
assign oclkdelay_init_val = PHY_0_A_PO_OCLK_DELAY;
// Idle powerdown when there are no pending reads in the MC
assign data_io_idle_pwrdwn = DATA_IO_IDLE_PWRDWN == "ON" ? idle : 1'b0;
//***************************************************************************
// Auxiliary output steering
//***************************************************************************
// For a 4 rank I/F the aux_out[3:0] from the addr/ctl bank will be
// mapped to ddr_odt and the aux_out[7:4] from one of the data banks
// will map to ddr_cke. For I/Fs less than 4 the aux_out[3:0] from the
// addr/ctl bank would bank would map to both ddr_odt and ddr_cke.
generate
if(CKE_ODT_AUX == "TRUE")begin:cke_thru_auxpins
if (CKE_WIDTH == 1) begin : gen_cke
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_cke_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke)
);
end else begin: gen_2rank_cke
OBUF u_cke0_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK]),
.O (ddr_cke[0])
);
OBUF u_cke1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_cke[1])
);
end
end
endgenerate
generate
if(CKE_ODT_AUX == "TRUE")begin:odt_thru_auxpins
if (USE_ODT_PORT == 1) begin : gen_use_odt
// Explicitly instantiate OBUF to ensure that these are present
// in the netlist. Typically this is not required since NGDBUILD
// at the top-level knows to infer an I/O/IOBUF and therefore a
// top-level LOC constraint can be attached to that pin. This does
// not work when a hierarchical flow is used and the LOC is applied
// at the individual core-level UCF
OBUF u_odt_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+1]),
.O (ddr_odt[0])
);
if (ODT_WIDTH == 2 && RANKS == 1) begin: gen_2port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 2 && RANKS == 2) begin: gen_2rank_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[1])
);
end else if (ODT_WIDTH == 3 && RANKS == 1) begin: gen_3port_odt
OBUF u_odt1_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+2]),
.O (ddr_odt[1])
);
OBUF u_odt2_obuf
(
.I (aux_out[4*CKE_ODT_RCLK_SELECT_BANK+3]),
.O (ddr_odt[2])
);
end
end else begin
assign ddr_odt = 'b0;
end
end
endgenerate
//***************************************************************************
// Read data bit steering
//***************************************************************************
// Transpose elements of rd_data_map to form final read data output:
// phy_din elements are grouped according to "physical bit" - e.g.
// for nCK_PER_CLK = 4, there are 8 data phases transfered per physical
// bit per clock cycle:
// = {dq0_fall3, dq0_rise3, dq0_fall2, dq0_rise2,
// dq0_fall1, dq0_rise1, dq0_fall0, dq0_rise0}
// whereas rd_data is are grouped according to "phase" - e.g.
// = {dq7_rise0, dq6_rise0, dq5_rise0, dq4_rise0,
// dq3_rise0, dq2_rise0, dq1_rise0, dq0_rise0}
// therefore rd_data is formed by transposing phy_din - e.g.
// for nCK_PER_CLK = 4, and DQ_WIDTH = 16, and assuming MC_PHY
// bit_lane[0] maps to DQ[0], and bit_lane[1] maps to DQ[1], then
// the assignments for bits of rd_data corresponding to DQ[1:0]
// would be:
// {rd_data[112], rd_data[96], rd_data[80], rd_data[64],
// rd_data[48], rd_data[32], rd_data[16], rd_data[0]} = phy_din[7:0]
// {rd_data[113], rd_data[97], rd_data[81], rd_data[65],
// rd_data[49], rd_data[33], rd_data[17], rd_data[1]} = phy_din[15:8]
generate
genvar i, j;
for (i = 0; i < DQ_WIDTH; i = i + 1) begin: gen_loop_rd_data_1
for (j = 0; j < PHASE_PER_CLK; j = j + 1) begin: gen_loop_rd_data_2
assign rd_data[DQ_WIDTH*j + i]
= phy_din[(320*FULL_DATA_MAP[(12*i+8)+:3]+
80*FULL_DATA_MAP[(12*i+4)+:2] +
8*FULL_DATA_MAP[12*i+:4]) + j];
end
end
endgenerate
//generage idelay_inc per bits
reg [11:0] cal_tmp;
reg [95:0] byte_sel_data_map;
assign byte_sel_cnt_w1 = byte_sel_cnt;
always @ (posedge clk) begin
byte_sel_data_map <= #TCQ FULL_DATA_MAP[12*DQ_PER_DQS*byte_sel_cnt_w1+:96];
end
always @ (posedge clk) begin
fine_delay_mod[((byte_sel_data_map[3:0])*3)+:3] <= #TCQ {fine_delay_incdec_pb[0],2'b00};
fine_delay_mod[((byte_sel_data_map[12+3:12])*3)+:3] <= #TCQ {fine_delay_incdec_pb[1],2'b00};
fine_delay_mod[((byte_sel_data_map[24+3:24])*3)+:3] <= #TCQ {fine_delay_incdec_pb[2],2'b00};
fine_delay_mod[((byte_sel_data_map[36+3:36])*3)+:3] <= #TCQ {fine_delay_incdec_pb[3],2'b00};
fine_delay_mod[((byte_sel_data_map[48+3:48])*3)+:3] <= #TCQ {fine_delay_incdec_pb[4],2'b00};
fine_delay_mod[((byte_sel_data_map[60+3:60])*3)+:3] <= #TCQ {fine_delay_incdec_pb[5],2'b00};
fine_delay_mod[((byte_sel_data_map[72+3:72])*3)+:3] <= #TCQ {fine_delay_incdec_pb[6],2'b00};
fine_delay_mod[((byte_sel_data_map[84+3:84])*3)+:3] <= #TCQ {fine_delay_incdec_pb[7],2'b00};
fine_delay_sel_r <= #TCQ fine_delay_sel;
end
//***************************************************************************
// Control/address
//***************************************************************************
assign out_cas_n
= mem_dq_out[48*CAS_MAP[10:8] + 12*CAS_MAP[5:4] + CAS_MAP[3:0]];
generate
// if signal placed on bit lanes [0-9]
if (CAS_MAP[3:0] < 4'hA) begin: gen_cas_lt10
// Determine routing based on clock ratio mode. If running in 4:1
// mode, then all four bits from logic are used. If 2:1 mode, only
// 2-bits are provided by logic, and each bit is repeated 2x to form
// 4-bit input to IN_FIFO, e.g.
// 4:1 mode: phy_dout[] = {in[3], in[2], in[1], in[0]}
// 2:1 mode: phy_dout[] = {in[1], in[1], in[0], in[0]}
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*CAS_MAP[3:0])+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end else begin: gen_cas_ge10
// If signal is placed in bit lane [10] or [11], route to upper
// nibble of phy_dout lane [5] or [6] respectively (in this case
// phy_dout lane [5, 6] are multiplexed to take input for two
// different SDR signals - this is how bits[10,11] need to be
// provided to the OUT_FIFO
assign phy_dout[(320*CAS_MAP[10:8] + 80*CAS_MAP[5:4] +
8*(CAS_MAP[3:0]-5) + 4)+:4]
= {mux_cas_n[3/PHASE_DIV], mux_cas_n[2/PHASE_DIV],
mux_cas_n[1/PHASE_DIV], mux_cas_n[0]};
end
endgenerate
assign out_ras_n
= mem_dq_out[48*RAS_MAP[10:8] + 12*RAS_MAP[5:4] + RAS_MAP[3:0]];
generate
if (RAS_MAP[3:0] < 4'hA) begin: gen_ras_lt10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*RAS_MAP[3:0])+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end else begin: gen_ras_ge10
assign phy_dout[(320*RAS_MAP[10:8] + 80*RAS_MAP[5:4] +
8*(RAS_MAP[3:0]-5) + 4)+:4]
= {mux_ras_n[3/PHASE_DIV], mux_ras_n[2/PHASE_DIV],
mux_ras_n[1/PHASE_DIV], mux_ras_n[0]};
end
endgenerate
assign out_we_n
= mem_dq_out[48*WE_MAP[10:8] + 12*WE_MAP[5:4] + WE_MAP[3:0]];
generate
if (WE_MAP[3:0] < 4'hA) begin: gen_we_lt10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*WE_MAP[3:0])+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end else begin: gen_we_ge10
assign phy_dout[(320*WE_MAP[10:8] + 80*WE_MAP[5:4] +
8*(WE_MAP[3:0]-5) + 4)+:4]
= {mux_we_n[3/PHASE_DIV], mux_we_n[2/PHASE_DIV],
mux_we_n[1/PHASE_DIV], mux_we_n[0]};
end
endgenerate
generate
if (REG_CTRL == "ON") begin: gen_parity_out
// Generate addr/ctrl parity output only for DDR3 and DDR2 registered DIMMs
assign out_parity
= mem_dq_out[48*PARITY_MAP[10:8] + 12*PARITY_MAP[5:4] +
PARITY_MAP[3:0]];
if (PARITY_MAP[3:0] < 4'hA) begin: gen_lt10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*PARITY_MAP[3:0])+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end else begin: gen_ge10
assign phy_dout[(320*PARITY_MAP[10:8] + 80*PARITY_MAP[5:4] +
8*(PARITY_MAP[3:0]-5) + 4)+:4]
= {parity_in[3/PHASE_DIV], parity_in[2/PHASE_DIV],
parity_in[1/PHASE_DIV], parity_in[0]};
end
end
endgenerate
//*****************************************************************
generate
genvar m, n,x;
//*****************************************************************
// Control/address (multi-bit) buses
//*****************************************************************
// Row/Column address
for (m = 0; m < ROW_WIDTH; m = m + 1) begin: gen_addr_out
assign out_addr[m]
= mem_dq_out[48*ADDR_MAP[(12*m+8)+:3] +
12*ADDR_MAP[(12*m+4)+:2] +
ADDR_MAP[12*m+:4]];
if (ADDR_MAP[12*m+:4] < 4'hA) begin: gen_lt10
// For multi-bit buses, we also have to deal with transposition
// when going from the logic-side control bus to phy_dout
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*ADDR_MAP[12*m+:4] + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ADDR_MAP[(12*m+8)+:3] +
80*ADDR_MAP[(12*m+4)+:2] +
8*(ADDR_MAP[12*m+:4]-5) + 4 + n]
= mux_address[ROW_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Bank address
for (m = 0; m < BANK_WIDTH; m = m + 1) begin: gen_ba_out
assign out_ba[m]
= mem_dq_out[48*BANK_MAP[(12*m+8)+:3] +
12*BANK_MAP[(12*m+4)+:2] +
BANK_MAP[12*m+:4]];
if (BANK_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*BANK_MAP[12*m+:4] + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*BANK_MAP[(12*m+8)+:3] +
80*BANK_MAP[(12*m+4)+:2] +
8*(BANK_MAP[12*m+:4]-5) + 4 + n]
= mux_bank[BANK_WIDTH*(n/PHASE_DIV) + m];
end
end
end
// Chip select
if (USE_CS_PORT == 1) begin: gen_cs_n_out
for (m = 0; m < CS_WIDTH*nCS_PER_RANK; m = m + 1) begin: gen_cs_out
assign out_cs_n[m]
= mem_dq_out[48*CS_MAP[(12*m+8)+:3] +
12*CS_MAP[(12*m+4)+:2] +
CS_MAP[12*m+:4]];
if (CS_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*CS_MAP[12*m+:4] + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CS_MAP[(12*m+8)+:3] +
80*CS_MAP[(12*m+4)+:2] +
8*(CS_MAP[12*m+:4]-5) + 4 + n]
= mux_cs_n[CS_WIDTH*nCS_PER_RANK*(n/PHASE_DIV) + m];
end
end
end
end
if(CKE_ODT_AUX == "FALSE") begin
// ODT_ports
wire [ODT_WIDTH*nCK_PER_CLK -1 :0] mux_odt_remap ;
if(RANKS == 1) begin
for(x =0 ; x < nCK_PER_CLK ; x = x+1) begin
assign mux_odt_remap[(x*ODT_WIDTH)+:ODT_WIDTH] = {ODT_WIDTH{mux_odt[0]}} ;
end
end else begin
for(x =0 ; x < 2*nCK_PER_CLK ; x = x+2) begin
assign mux_odt_remap[(x*ODT_WIDTH/RANKS)+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[0]}} ;
assign mux_odt_remap[((x*ODT_WIDTH/RANKS)+(ODT_WIDTH/RANKS))+:ODT_WIDTH/RANKS] = {ODT_WIDTH/RANKS{mux_odt[1]}} ;
end
end
if (USE_ODT_PORT == 1) begin: gen_odt_out
for (m = 0; m < ODT_WIDTH; m = m + 1) begin: gen_odt_out_1
assign out_odt[m]
= mem_dq_out[48*ODT_MAP[(12*m+8)+:3] +
12*ODT_MAP[(12*m+4)+:2] +
ODT_MAP[12*m+:4]];
if (ODT_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*ODT_MAP[12*m+:4] + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*ODT_MAP[(12*m+8)+:3] +
80*ODT_MAP[(12*m+4)+:2] +
8*(ODT_MAP[12*m+:4]-5) + 4 + n]
= mux_odt_remap[ODT_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
wire [CKE_WIDTH*nCK_PER_CLK -1:0] mux_cke_remap ;
for(x = 0 ; x < nCK_PER_CLK ; x = x +1) begin
assign mux_cke_remap[(x*CKE_WIDTH)+:CKE_WIDTH] = {CKE_WIDTH{mux_cke[x]}} ;
end
for (m = 0; m < CKE_WIDTH; m = m + 1) begin: gen_cke_out
assign out_cke[m]
= mem_dq_out[48*CKE_MAP[(12*m+8)+:3] +
12*CKE_MAP[(12*m+4)+:2] +
CKE_MAP[12*m+:4]];
if (CKE_MAP[12*m+:4] < 4'hA) begin: gen_lt10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*CKE_MAP[12*m+:4] + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end else begin: gen_ge10
for (n = 0; n < 4; n = n + 1) begin: loop_xpose
assign phy_dout[320*CKE_MAP[(12*m+8)+:3] +
80*CKE_MAP[(12*m+4)+:2] +
8*(CKE_MAP[12*m+:4]-5) + 4 + n]
= mux_cke_remap[CKE_WIDTH*(n/PHASE_DIV) + m];
end
end
end
end
//*****************************************************************
// Data mask
//*****************************************************************
if (USE_DM_PORT == 1) begin: gen_dm_out
for (m = 0; m < DM_WIDTH; m = m + 1) begin: gen_dm_out
assign out_dm[m]
= mem_dq_out[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
assign ts_dm[m]
= mem_dq_ts[48*FULL_MASK_MAP[(12*m+8)+:3] +
12*FULL_MASK_MAP[(12*m+4)+:2] +
FULL_MASK_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_MASK_MAP[(12*m+8)+:3] +
80*FULL_MASK_MAP[(12*m+4)+:2] +
8*FULL_MASK_MAP[12*m+:4] + n]
= mux_wrdata_mask[DM_WIDTH*n + m];
end
end
end
//*****************************************************************
// Input and output DQ
//*****************************************************************
for (m = 0; m < DQ_WIDTH; m = m + 1) begin: gen_dq_inout
// to MC_PHY
assign mem_dq_in[40*FULL_DATA_MAP[(12*m+8)+:3] +
10*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]]
= in_dq[m];
// to I/O buffers
assign out_dq[m]
= mem_dq_out[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
assign ts_dq[m]
= mem_dq_ts[48*FULL_DATA_MAP[(12*m+8)+:3] +
12*FULL_DATA_MAP[(12*m+4)+:2] +
FULL_DATA_MAP[12*m+:4]];
for (n = 0; n < PHASE_PER_CLK; n = n + 1) begin: loop_xpose
assign phy_dout[320*FULL_DATA_MAP[(12*m+8)+:3] +
80*FULL_DATA_MAP[(12*m+4)+:2] +
8*FULL_DATA_MAP[12*m+:4] + n]
= mux_wrdata[DQ_WIDTH*n + m];
end
end
//*****************************************************************
// Input and output DQS
//*****************************************************************
for (m = 0; m < DQS_WIDTH; m = m + 1) begin: gen_dqs_inout
// to MC_PHY
assign mem_dqs_in[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]]
= in_dqs[m];
// to I/O buffers
assign out_dqs[m]
= mem_dqs_out[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
assign ts_dqs[m]
= mem_dqs_ts[4*DQS_BYTE_MAP[(8*m+4)+:3] + DQS_BYTE_MAP[(8*m)+:2]];
end
endgenerate
assign pd_out = pd_out_pre[byte_sel_cnt_w1];
//***************************************************************************
// Memory I/F output and I/O buffer instantiation
//***************************************************************************
// Note on instantiation - generally at the minimum, it's not required to
// instantiate the output buffers - they can be inferred by the synthesis
// tool, and there aren't any attributes that need to be associated with
// them. Consider as a future option to take out the OBUF instantiations
OBUF u_cas_n_obuf
(
.I (out_cas_n),
.O (ddr_cas_n)
);
OBUF u_ras_n_obuf
(
.I (out_ras_n),
.O (ddr_ras_n)
);
OBUF u_we_n_obuf
(
.I (out_we_n),
.O (ddr_we_n)
);
generate
genvar p;
for (p = 0; p < ROW_WIDTH; p = p + 1) begin: gen_addr_obuf
OBUF u_addr_obuf
(
.I (out_addr[p]),
.O (ddr_addr[p])
);
end
for (p = 0; p < BANK_WIDTH; p = p + 1) begin: gen_bank_obuf
OBUF u_bank_obuf
(
.I (out_ba[p]),
.O (ddr_ba[p])
);
end
if (USE_CS_PORT == 1) begin: gen_cs_n_obuf
for (p = 0; p < CS_WIDTH*nCS_PER_RANK; p = p + 1) begin: gen_cs_obuf
OBUF u_cs_n_obuf
(
.I (out_cs_n[p]),
.O (ddr_cs_n[p])
);
end
end
if(CKE_ODT_AUX == "FALSE")begin:cke_odt_thru_outfifo
if (USE_ODT_PORT== 1) begin: gen_odt_obuf
for (p = 0; p < ODT_WIDTH; p = p + 1) begin: gen_odt_obuf
OBUF u_cs_n_obuf
(
.I (out_odt[p]),
.O (ddr_odt[p])
);
end
end
for (p = 0; p < CKE_WIDTH; p = p + 1) begin: gen_cke_obuf
OBUF u_cs_n_obuf
(
.I (out_cke[p]),
.O (ddr_cke[p])
);
end
end
if (REG_CTRL == "ON") begin: gen_parity_obuf
// Generate addr/ctrl parity output only for DDR3 registered DIMMs
OBUF u_parity_obuf
(
.I (out_parity),
.O (ddr_parity)
);
end else begin: gen_parity_tieoff
assign ddr_parity = 1'b0;
end
if ((DRAM_TYPE == "DDR3") || (REG_CTRL == "ON")) begin: gen_reset_obuf
// Generate reset output only for DDR3 and DDR2 RDIMMs
OBUF u_reset_obuf
(
.I (mux_reset_n),
.O (ddr_reset_n)
);
end else begin: gen_reset_tieoff
assign ddr_reset_n = 1'b1;
end
if (USE_DM_PORT == 1) begin: gen_dm_obuf
for (p = 0; p < DM_WIDTH; p = p + 1) begin: loop_dm
OBUFT u_dm_obuf
(
.I (out_dm[p]),
.T (ts_dm[p]),
.O (ddr_dm[p])
);
end
end else begin: gen_dm_tieoff
assign ddr_dm = 'b0;
end
if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dq_iobuf_HP
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dq_iobuf_HR
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end else begin: gen_dq_iobuf_default
for (p = 0; p < DQ_WIDTH; p = p + 1) begin: gen_dq_iobuf
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dq
(
.I (out_dq[p]),
.T (ts_dq[p]),
.O (in_dq[p]),
.IO (ddr_dq[p])
);
end
end
//if (DATA_IO_PRIM_TYPE == "HP_LP") begin: gen_dqs_iobuf_HP
if ((BANK_TYPE == "HP_IO") || (BANK_TYPE == "HPL_IO")) begin: gen_dqs_iobuf_HP
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin : gen_ddr2_or_low_dqs_diff
IOBUFDS_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_DCIEN #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.DCITERMDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
//end else if (DATA_IO_PRIM_TYPE == "HR_LP") begin: gen_dqs_iobuf_HR
end else if ((BANK_TYPE == "HR_IO") || (BANK_TYPE == "HRL_IO")) begin: gen_dqs_iobuf_HR
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else if ((DRAM_TYPE == "DDR2") ||
(tCK > 2500)) begin: gen_ddr2_or_low_dqs_diff
IOBUFDS_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS_DIFF_OUT_INTERMDISABLE #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE"),
.SIM_DEVICE ("7SERIES"),
.USE_IBUFDISABLE ("FALSE")
)
u_iobuf_dqs
(
.INTERMDISABLE (data_io_idle_pwrdwn),
//.IBUFDISABLE (data_io_idle_pwrdwn),
.I (out_dqs[p]),
.TM (ts_dqs[p]),
.TS (ts_dqs[p]),
.OB (in_dqs_lpbk_to_iddr[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
mig_7series_v2_3_poc_pd #
(
.TCQ (TCQ),
.POC_USE_METASTABLE_SAMP (POC_USE_METASTABLE_SAMP)
)
u_iddr_edge_det
(
.clk (clk),
.iddr_rst (iddr_rst),
.kclk (in_dqs_lpbk_to_iddr[p]),
.mmcm_ps_clk (mmcm_ps_clk),
.pd_out (pd_out_pre[p])
);
end
end
end else begin: gen_dqs_iobuf_default
for (p = 0; p < DQS_WIDTH; p = p + 1) begin: gen_dqs_iobuf
if ((DRAM_TYPE == "DDR2") &&
(DDR2_DQSN_ENABLE != "YES")) begin: gen_ddr2_dqs_se
IOBUF #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR)
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p])
);
assign ddr_dqs_n[p] = 1'b0;
assign pd_out_pre[p] = 1'b0;
end else begin: gen_dqs_diff
IOBUFDS #
(
.IBUF_LOW_PWR (IBUF_LOW_PWR),
.DQS_BIAS ("TRUE")
)
u_iobuf_dqs
(
.I (out_dqs[p]),
.T (ts_dqs[p]),
.O (in_dqs[p]),
.IO (ddr_dqs[p]),
.IOB (ddr_dqs_n[p])
);
assign pd_out_pre[p] = 1'b0;
end
end
end
endgenerate
always @(posedge clk) begin
phy_ctl_wd_i1 <= #TCQ phy_ctl_wd;
phy_ctl_wr_i1 <= #TCQ phy_ctl_wr;
phy_ctl_wd_i2 <= #TCQ phy_ctl_wd_i1;
phy_ctl_wr_i2 <= #TCQ phy_ctl_wr_i1;
data_offset_1_i1 <= #TCQ data_offset_1;
data_offset_1_i2 <= #TCQ data_offset_1_i1;
data_offset_2_i1 <= #TCQ data_offset_2;
data_offset_2_i2 <= #TCQ data_offset_2_i1;
end
// 2 cycles of command delay needed for 4;1 mode. 2:1 mode does not need it.
// 2:1 mode the command goes through pre fifo
assign phy_ctl_wd_temp = (nCK_PER_CLK == 4) ? phy_ctl_wd_i2 : phy_ctl_wd_of;
assign phy_ctl_wr_temp = (nCK_PER_CLK == 4) ? phy_ctl_wr_i2 : phy_ctl_wr_of;
assign data_offset_1_temp = (nCK_PER_CLK == 4) ? data_offset_1_i2 : data_offset_1_of;
assign data_offset_2_temp = (nCK_PER_CLK == 4) ? data_offset_2_i2 : data_offset_2_of;
generate
begin
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (32)
)
phy_ctl_pre_fifo_0
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[1]),
.wr_en_in (phy_ctl_wr),
.d_in (phy_ctl_wd),
.wr_en_out (phy_ctl_wr_of),
.d_out (phy_ctl_wd_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_1
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[2]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_1),
.wr_en_out (),
.d_out (data_offset_1_of)
);
mig_7series_v2_3_ddr_of_pre_fifo #
(
.TCQ (25),
.DEPTH (8),
.WIDTH (6)
)
phy_ctl_pre_fifo_2
(
.clk (clk),
.rst (rst),
.full_in (phy_ctl_full_temp[3]),
.wr_en_in (phy_ctl_wr),
.d_in (data_offset_2),
.wr_en_out (),
.d_out (data_offset_2_of)
);
end
endgenerate
//***************************************************************************
// Hard PHY instantiation
//***************************************************************************
assign phy_ctl_full = phy_ctl_full_temp[0];
mig_7series_v2_3_ddr_mc_phy #
(
.BYTE_LANES_B0 (BYTE_LANES_B0),
.BYTE_LANES_B1 (BYTE_LANES_B1),
.BYTE_LANES_B2 (BYTE_LANES_B2),
.BYTE_LANES_B3 (BYTE_LANES_B3),
.BYTE_LANES_B4 (BYTE_LANES_B4),
.DATA_CTL_B0 (DATA_CTL_B0),
.DATA_CTL_B1 (DATA_CTL_B1),
.DATA_CTL_B2 (DATA_CTL_B2),
.DATA_CTL_B3 (DATA_CTL_B3),
.DATA_CTL_B4 (DATA_CTL_B4),
.PHY_0_BITLANES (PHY_0_BITLANES),
.PHY_1_BITLANES (PHY_1_BITLANES),
.PHY_2_BITLANES (PHY_2_BITLANES),
.PHY_0_BITLANES_OUTONLY (PHY_0_BITLANES_OUTONLY),
.PHY_1_BITLANES_OUTONLY (PHY_1_BITLANES_OUTONLY),
.PHY_2_BITLANES_OUTONLY (PHY_2_BITLANES_OUTONLY),
.RCLK_SELECT_BANK (CKE_ODT_RCLK_SELECT_BANK),
.RCLK_SELECT_LANE (CKE_ODT_RCLK_SELECT_LANE),
//.CKE_ODT_AUX (CKE_ODT_AUX),
.GENERATE_DDR_CK_MAP (TMP_GENERATE_DDR_CK_MAP),
.BYTELANES_DDR_CK (TMP_BYTELANES_DDR_CK),
.NUM_DDR_CK (CK_WIDTH),
.LP_DDR_CK_WIDTH (LP_DDR_CK_WIDTH),
.PO_CTL_COARSE_BYPASS ("FALSE"),
.PHYCTL_CMD_FIFO ("FALSE"),
.PHY_CLK_RATIO (nCK_PER_CLK),
.MASTER_PHY_CTL (MASTER_PHY_CTL),
.PHY_FOUR_WINDOW_CLOCKS (63),
.PHY_EVENTS_DELAY (18),
.PHY_COUNT_EN ("FALSE"), //PHY_COUNT_EN
.PHY_SYNC_MODE ("FALSE"),
.SYNTHESIS ((SIM_CAL_OPTION == "NONE") ? "TRUE" : "FALSE"),
.PHY_DISABLE_SEQ_MATCH ("TRUE"), //"TRUE"
.PHY_0_GENERATE_IDELAYCTRL ("FALSE"),
.PHY_0_A_PI_FREQ_REF_DIV (PHY_0_A_PI_FREQ_REF_DIV),
.PHY_0_CMD_OFFSET (PHY_0_CMD_OFFSET), //for CKE
.PHY_0_RD_CMD_OFFSET_0 (PHY_0_RD_CMD_OFFSET_0),
.PHY_0_RD_CMD_OFFSET_1 (PHY_0_RD_CMD_OFFSET_1),
.PHY_0_RD_CMD_OFFSET_2 (PHY_0_RD_CMD_OFFSET_2),
.PHY_0_RD_CMD_OFFSET_3 (PHY_0_RD_CMD_OFFSET_3),
.PHY_0_RD_DURATION_0 (6),
.PHY_0_RD_DURATION_1 (6),
.PHY_0_RD_DURATION_2 (6),
.PHY_0_RD_DURATION_3 (6),
.PHY_0_WR_CMD_OFFSET_0 (PHY_0_WR_CMD_OFFSET_0),
.PHY_0_WR_CMD_OFFSET_1 (PHY_0_WR_CMD_OFFSET_1),
.PHY_0_WR_CMD_OFFSET_2 (PHY_0_WR_CMD_OFFSET_2),
.PHY_0_WR_CMD_OFFSET_3 (PHY_0_WR_CMD_OFFSET_3),
.PHY_0_WR_DURATION_0 (PHY_0_WR_DURATION_0),
.PHY_0_WR_DURATION_1 (PHY_0_WR_DURATION_1),
.PHY_0_WR_DURATION_2 (PHY_0_WR_DURATION_2),
.PHY_0_WR_DURATION_3 (PHY_0_WR_DURATION_3),
.PHY_0_AO_TOGGLE ((RANKS == 1) ? 1 : 5),
.PHY_0_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_0_A_PO_OCLKDELAY_INV (PO_OCLKDELAY_INV),
.PHY_0_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_0_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_1_GENERATE_DDR_CK (TMP_PHY_1_GENERATE_DDR_CK),
//.PHY_1_NUM_DDR_CK (1),
.PHY_1_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_1_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_1_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_GENERATE_IDELAYCTRL ("FALSE"),
//.PHY_2_GENERATE_DDR_CK (TMP_PHY_2_GENERATE_DDR_CK),
//.PHY_2_NUM_DDR_CK (1),
.PHY_2_A_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_B_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_C_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_D_PO_OCLK_DELAY (PHY_0_A_PO_OCLK_DELAY),
.PHY_2_A_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_B_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_C_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.PHY_2_D_IDELAYE2_IDELAY_VALUE (PHY_0_A_IDELAYE2_IDELAY_VALUE),
.TCK (tCK),
.PHY_0_IODELAY_GRP (IODELAY_GRP),
.PHY_1_IODELAY_GRP (IODELAY_GRP),
.PHY_2_IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.CKE_ODT_AUX (CKE_ODT_AUX)
)
u_ddr_mc_phy
(
.rst (rst),
// Don't use MC_PHY to generate DDR_RESET_N output. Instead
// generate this output outside of MC_PHY (and synchronous to CLK)
.ddr_rst_in_n (1'b1),
.phy_clk (clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
// Remove later - always same connection as phy_clk port
.mem_refclk_div4 (clk),
.pll_lock (pll_lock),
.auxout_clk (),
.sync_pulse (sync_pulse),
// IDELAYCTRL instantiated outside of mc_phy module
.idelayctrl_refclk (),
.phy_dout (phy_dout),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phy_ctl_wd (phy_ctl_wd_temp),
.phy_ctl_wr (phy_ctl_wr_temp),
.if_empty_def (phy_if_empty_def),
.if_rst (phy_if_reset),
.phyGo ('b1),
.aux_in_1 (aux_in_1),
.aux_in_2 (aux_in_2),
// No support yet for different data offsets for different I/O banks
// (possible use in supporting wider range of skew among bytes)
.data_offset_1 (data_offset_1_temp),
.data_offset_2 (data_offset_2_temp),
.cke_in (),
.if_a_empty (),
.if_empty (if_empty),
.if_empty_or (),
.if_empty_and (),
.of_ctl_a_full (),
// .of_data_a_full (phy_data_full),
.of_ctl_full (phy_cmd_full),
.of_data_full (),
.pre_data_a_full (phy_pre_data_a_full),
.idelay_ld (idelay_ld),
.idelay_ce (idelay_ce),
.idelay_inc (idelay_inc),
.input_sink (),
.phy_din (phy_din),
.phy_ctl_a_full (),
.phy_ctl_full (phy_ctl_full_temp),
.mem_dq_out (mem_dq_out),
.mem_dq_ts (mem_dq_ts),
.mem_dq_in (mem_dq_in),
.mem_dqs_out (mem_dqs_out),
.mem_dqs_ts (mem_dqs_ts),
.mem_dqs_in (mem_dqs_in),
.aux_out (aux_out),
.phy_ctl_ready (),
.rst_out (),
.ddr_clk (ddr_clk),
//.rclk (),
.mcGo (phy_mc_go),
.phy_write_calib (phy_write_calib),
.phy_read_calib (phy_read_calib),
.calib_sel (calib_sel),
.calib_in_common (calib_in_common),
.calib_zero_inputs (calib_zero_inputs),
.calib_zero_ctrl (calib_zero_ctrl),
.calib_zero_lanes ('b0),
.po_fine_enable (po_fine_enable),
.po_coarse_enable (po_coarse_enable),
.po_fine_inc (po_fine_inc),
.po_coarse_inc (po_coarse_inc),
.po_counter_load_en (po_counter_load_en),
.po_sel_fine_oclk_delay (po_sel_fine_oclk_delay),
.po_counter_load_val (po_counter_load_val),
.po_counter_read_en (po_counter_read_en),
.po_coarse_overflow (),
.po_fine_overflow (),
.po_counter_read_val (po_counter_read_val),
.pi_rst_dqs_find (pi_rst_dqs_find),
.pi_fine_enable (pi_fine_enable),
.pi_fine_inc (pi_fine_inc),
.pi_counter_load_en (pi_counter_load_en),
.pi_counter_read_en (dbg_pi_counter_read_en),
.pi_counter_load_val (pi_counter_load_val),
.pi_fine_overflow (),
.pi_counter_read_val (pi_counter_read_val),
.pi_phase_locked (pi_phase_locked),
.pi_phase_locked_all (pi_phase_locked_all),
.pi_dqs_found (),
.pi_dqs_found_any (pi_dqs_found),
.pi_dqs_found_all (pi_dqs_found_all),
.pi_dqs_found_lanes (dbg_pi_dqs_found_lanes_phy4lanes),
// Currently not being used. May be used in future if periodic
// reads become a requirement. This output could be used to signal
// a catastrophic failure in read capture and the need for
// re-calibration.
.pi_dqs_out_of_range (pi_dqs_out_of_range)
,.ref_dll_lock (ref_dll_lock)
,.pi_phase_locked_lanes (dbg_pi_phase_locked_phy4lanes)
,.fine_delay (fine_delay_mod)
,.fine_delay_sel (fine_delay_sel_r)
// ,.rst_phaser_ref (rst_phaser_ref)
);
endmodule
|
//
// Copyright (c) 1999 Steven Wilson ([email protected])
//
// This source code is free software; you can redistribute it
// and/or modify it in source code form under the terms of the GNU
// General Public License as published by the Free Software
// Foundation; either version 2 of the License, or (at your option)
// any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
//
// SDW - Validate always repeat (expression) statement ;
module main ;
reg [3:0] value1,value2,value3;
initial
begin
value1 = 0; // Time 0 assignemnt
value2 = 0;
#6 ;
if(value1 != 4'h1)
begin
$display("FAILED - 3.1.7B always forever (1) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h2)
begin
$display("FAILED - 3.1.7B always forever (2) ");
value2 = 1;
end
#5 ;
if(value1 != 4'h3)
begin
$display("FAILED - 3.1.7B always forever (3) ");
value2 = 1;
end
if(value2 == 0)
$display("PASSED");
$finish;
end
always repeat(3) begin
#5 ;
value1 = value1 + 1;
end
endmodule
|
// ========== Copyright Header Begin ==========================================
//
// OpenSPARC T1 Processor File: softint_mon.v
// Copyright (c) 2006 Sun Microsystems, Inc. All Rights Reserved.
// DO NOT ALTER OR REMOVE COPYRIGHT NOTICES.
//
// The above named program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public
// License version 2 as published by the Free Software Foundation.
//
// The above named program is distributed in the hope that it will be
// useful, but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
// General Public License for more details.
//
// You should have received a copy of the GNU General Public
// License along with this work; if not, write to the Free Software
// Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301, USA.
//
// ========== Copyright Header End ============================================
///////////////////////////////////////////////////////////////////////
// softint_mon.v
//
// Description:
// This file contains monitors required for the SOFTINT register part
// TLU (Trap Logic Unit) verification.
//
///////////////////////////////////////////////////////////////////////
`include "cross_module.h"
module softint_mon(/*AUTOARG*/
rtl_softint0,
rtl_softint1,
rtl_softint2,
rtl_softint3,
rtl_wsr_data_w,
rtl_sftint_en_l_g,
rtl_sftint_b0_en,
rtl_tickcmp_int,
rtl_sftint_b16_en,
rtl_stickcmp_int,
rtl_sftint_b15_en,
rtl_pib_picl_wrap,
rtl_pib_pich_wrap,
rtl_wr_sftint_l_g,
rtl_set_sftint_l_g,
rtl_clr_sftint_l_g,
rtl_clk,
rtl_reset,
core_id
);
input [16:0] rtl_softint0;
input [16:0] rtl_softint1;
input [16:0] rtl_softint2;
input [16:0] rtl_softint3;
input [16:0] rtl_wsr_data_w;
input [3:0] rtl_sftint_en_l_g;
input [3:0] rtl_sftint_b0_en;
input [3:0] rtl_tickcmp_int;
input [3:0] rtl_sftint_b16_en;
input [3:0] rtl_stickcmp_int;
input [3:0] rtl_sftint_b15_en;
input [3:0] rtl_pib_picl_wrap;
input [3:0] rtl_pib_pich_wrap;
input rtl_wr_sftint_l_g;
input rtl_set_sftint_l_g;
input rtl_clr_sftint_l_g;
input rtl_clk;
input rtl_reset;
input [2:0] core_id;
/*
wire [16:0] rtl_softint0 = `TOP_DESIGN.sparc0.tlu.tdp.sftint0;
wire [16:0] rtl_softint1 = `TOP_DESIGN.sparc0.tlu.tdp.sftint1;
wire [16:0] rtl_softint2 = `TOP_DESIGN.sparc0.tlu.tdp.sftint2;
wire [16:0] rtl_softint3 = `TOP_DESIGN.sparc0.tlu.tdp.sftint3;
wire [16:0] rtl_wsr_data_w = `TOP_DESIGN.sparc0.tlu.tdp.wsr_data_w;
wire [3:0] rtl_sftint_en_l_g = `TOP_DESIGN.sparc0.tlu.tdp.tlu_sftint_en_l_g;
wire [3:0] rtl_sftint_b0_en = `TOP_DESIGN.sparc0.tlu.tdp.sftint_b0_en;
wire [3:0] rtl_tickcmp_int = `TOP_DESIGN.sparc0.tlu.tdp.tickcmp_int;
wire [3:0] rtl_sftint_b16_en = `TOP_DESIGN.sparc0.tlu.tdp.sftint_b16_en;
wire [3:0] rtl_stickcmp_int = `TOP_DESIGN.sparc0.tlu.tdp.stickcmp_int;
wire [3:0] rtl_sftint_b15_en = `TOP_DESIGN.sparc0.tlu.tdp.sftint_b15_en;
wire [3:0] rtl_pib_picl_wrap = `TOP_DESIGN.sparc0.tlu.tdp.pib_picl_wrap;
wire [3:0] rtl_pib_pich_wrap = `TOP_DESIGN.sparc0.tlu.tdp.pib_pich_wrap;
wire rtl_wr_sftint_l_g = `TOP_DESIGN.sparc0.tlu.tdp.tlu_wr_sftint_l_g;
wire rtl_set_sftint_l_g = `TOP_DESIGN.sparc0.tlu.tdp.tlu_set_sftint_l_g;
wire rtl_clr_sftint_l_g = `TOP_DESIGN.sparc0.tlu.tdp.tlu_clr_sftint_l_g;
wire rtl_clk = `TOP_DESIGN.sparc0.tlu.tdp.rclk;
wire rtl_reset = `TOP_DESIGN.sparc0.tlu.tdp.tlu_rst;
*/
wire rst_l = ~rtl_reset;
reg [16:0] local_softint0;
reg [16:0] local_softint1;
reg [16:0] local_softint2;
reg [16:0] local_softint3;
reg enable;
//============
// initialize
initial begin
enable = 1'b1;
if ($test$plusargs("turn_off_softint_check")) enable = 1'b0;
//else if ($test$plusargs("turn_on_softint_monitor")) enable = 1'b1;
if (enable) $display("Info: ***** Enabling the SOFTINT-Register Checker *****");
else $display("Info: ***** Disabling the SOFTINT-Register Checker *****");
//local_softint0[16:0] <= {17{1'b0}};
//local_softint1[16:0] <= {17{1'b0}};
//local_softint2[16:0] <= {17{1'b0}};
//local_softint3[16:0] <= {17{1'b0}};
end
//=========================
// SOFTINT0 register update
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or negedge rtl_sftint_en_l_g[0] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint0[14:1] <= {14{1'b0}};
end
else if (~rtl_sftint_en_l_g[0]) begin
if (~rtl_wr_sftint_l_g) local_softint0[14:1] <= rtl_wsr_data_w[14:1];
else if (~rtl_set_sftint_l_g) local_softint0[14:1] <= (local_softint0[14:1] | rtl_wsr_data_w[14:1]);
else if (~rtl_clr_sftint_l_g) local_softint0[14:1] <= (local_softint0[14:1] & ~rtl_wsr_data_w[14:1]);
else local_softint0[14:1] <= local_softint0[14:1];
end
else begin
local_softint0[14:1] <= local_softint0[14:1];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b0_en[0] or posedge rtl_tickcmp_int[0] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint0[0] <= 1'b0;
end
else if (rtl_sftint_b0_en[0]) begin
if (rtl_tickcmp_int[0]) local_softint0[0] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint0[0] <= rtl_wsr_data_w[0];
else if (~rtl_set_sftint_l_g) local_softint0[0] <= (local_softint0[0] | rtl_wsr_data_w[0]);
else if (~rtl_clr_sftint_l_g) local_softint0[0] <= (local_softint0[0] & ~rtl_wsr_data_w[0]);
else local_softint0[0] <= local_softint0[0];
end
else begin
local_softint0[0] <= local_softint0[0];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b16_en[0] or posedge rtl_stickcmp_int[0] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint0[16] <= 1'b0;
end
else if (rtl_sftint_b16_en[0]) begin
if (rtl_stickcmp_int[0]) local_softint0[16] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint0[16] <= rtl_wsr_data_w[16];
else if (~rtl_set_sftint_l_g) local_softint0[16] <= (local_softint0[16] | rtl_wsr_data_w[16]);
else if (~rtl_clr_sftint_l_g) local_softint0[16] <= (local_softint0[16] & ~rtl_wsr_data_w[16]);
else local_softint0[16] <= local_softint0[16];
end
else begin
local_softint0[16] <= local_softint0[16];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b15_en[0] or posedge rtl_pib_picl_wrap[0] or posedge rtl_pib_pich_wrap[0] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint0[15] <= 1'b0;
end
else if (rtl_sftint_b15_en[0]) begin
if (rtl_pib_picl_wrap[0] | rtl_pib_pich_wrap[0]) local_softint0[15] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint0[15] <= rtl_wsr_data_w[15];
else if (~rtl_set_sftint_l_g) local_softint0[15] <= (local_softint0[15] | rtl_wsr_data_w[15]);
else if (~rtl_clr_sftint_l_g) local_softint0[15] <= (local_softint0[15] & ~rtl_wsr_data_w[15]);
else local_softint0[15] <= local_softint0[15];
end
else begin
local_softint0[15] <= local_softint0[15];
end
end // always
always @(rtl_softint0) begin
if (rtl_softint0 != local_softint0) begin
if (enable & rst_l) begin
$display("*ERROR*: %0d: softint_mon: Thread0 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint0[16:0], local_softint0[16:0]);
$display("*Info*: softint_mon: Use -sim_run_args=+turn_off_softint_monitor to disable the softint_mon");
`MONITOR_PATH.fail("softint_mon: Thread0 SOFTINT register mismatch");
end
else begin
$display("*WARNING*: %0d: softint_mon: Thread0 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint0[16:0], local_softint0[16:0]);
end
end
else begin
$display("*Info*: %0d: softint_mon: Thread0 SOFTINT register MATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint0[16:0], local_softint0[16:0]);
end
end
//=========================
// SOFTINT1 register update
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or negedge rtl_sftint_en_l_g[1] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint1[14:1] <= {14{1'b0}};
end
else if (~rtl_sftint_en_l_g[1]) begin
if (~rtl_wr_sftint_l_g) local_softint1[14:1] <= rtl_wsr_data_w[14:1];
else if (~rtl_set_sftint_l_g) local_softint1[14:1] <= (local_softint1[14:1] | rtl_wsr_data_w[14:1]);
else if (~rtl_clr_sftint_l_g) local_softint1[14:1] <= (local_softint1[14:1] & ~rtl_wsr_data_w[14:1]);
else local_softint1[14:1] <= local_softint1[14:1];
end
else begin
local_softint1[14:1] <= local_softint1[14:1];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b0_en[1] or posedge rtl_tickcmp_int[1] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint1[0] <= 1'b0;
end
else if (rtl_sftint_b0_en[1]) begin
if (rtl_tickcmp_int[1]) local_softint1[0] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint1[0] <= rtl_wsr_data_w[0];
else if (~rtl_set_sftint_l_g) local_softint1[0] <= (local_softint1[0] | rtl_wsr_data_w[0]);
else if (~rtl_clr_sftint_l_g) local_softint1[0] <= (local_softint1[0] & ~rtl_wsr_data_w[0]);
else local_softint1[0] <= local_softint1[0];
end
else begin
local_softint1[0] <= local_softint1[0];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b16_en[1] or posedge rtl_stickcmp_int[1] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint1[16] <= 1'b0;
end
else if (rtl_sftint_b16_en[1]) begin
if (rtl_stickcmp_int[1]) local_softint1[16] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint1[16] <= rtl_wsr_data_w[16];
else if (~rtl_set_sftint_l_g) local_softint1[16] <= (local_softint1[16] | rtl_wsr_data_w[16]);
else if (~rtl_clr_sftint_l_g) local_softint1[16] <= (local_softint1[16] & ~rtl_wsr_data_w[16]);
else local_softint1[16] <= local_softint1[16];
end
else begin
local_softint1[16] <= local_softint1[16];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b15_en[1] or posedge rtl_pib_picl_wrap[1] or posedge rtl_pib_pich_wrap[1] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint1[15] <= 1'b0;
end
else if (rtl_sftint_b15_en[1]) begin
if (rtl_pib_picl_wrap[1] | rtl_pib_pich_wrap[1]) local_softint1[15] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint1[15] <= rtl_wsr_data_w[15];
else if (~rtl_set_sftint_l_g) local_softint1[15] <= (local_softint1[15] | rtl_wsr_data_w[15]);
else if (~rtl_clr_sftint_l_g) local_softint1[15] <= (local_softint1[15] & ~rtl_wsr_data_w[15]);
else local_softint1[15] <= local_softint1[15];
end
else begin
local_softint1[15] <= local_softint1[15];
end
end // always
always @(rtl_softint1) begin
if (rtl_softint1 != local_softint1) begin
if (enable & rst_l) begin
$display("*ERROR*: %0d: softint_mon: Thread1 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint1[16:0], local_softint1[16:0]);
$display("*Info*: softint_mon: Use -sim_run_args=+turn_off_softint_monitor to disable the softint_mon");
`MONITOR_PATH.fail("softint_mon: Thread1 SOFTINT register mismatch");
end
else begin
$display("*WARNING*: %0d: softint_mon: Thread1 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint1[16:0], local_softint1[16:0]);
end
end
else begin
$display("*Info*: %0d: softint_mon: Thread1 SOFTINT register MATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint1[16:0], local_softint1[16:0]);
end
end
//=========================
// SOFTINT2 register update
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or negedge rtl_sftint_en_l_g[2] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint2[14:1] <= {14{1'b0}};
end
else if (~rtl_sftint_en_l_g[2]) begin
if (~rtl_wr_sftint_l_g) local_softint2[14:1] <= rtl_wsr_data_w[14:1];
else if (~rtl_set_sftint_l_g) local_softint2[14:1] <= (local_softint2[14:1] | rtl_wsr_data_w[14:1]);
else if (~rtl_clr_sftint_l_g) local_softint2[14:1] <= (local_softint2[14:1] & ~rtl_wsr_data_w[14:1]);
else local_softint2[14:1] <= local_softint2[14:1];
end
else begin
local_softint2[14:1] <= local_softint2[14:1];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b0_en[2] or posedge rtl_tickcmp_int[2] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint2[0] <= 1'b0;
end
else if (rtl_sftint_b0_en[2]) begin
if (rtl_tickcmp_int[2]) local_softint2[0] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint2[0] <= rtl_wsr_data_w[0];
else if (~rtl_set_sftint_l_g) local_softint2[0] <= (local_softint2[0] | rtl_wsr_data_w[0]);
else if (~rtl_clr_sftint_l_g) local_softint2[0] <= (local_softint2[0] & ~rtl_wsr_data_w[0]);
else local_softint2[0] <= local_softint2[0];
end
else begin
local_softint2[0] <= local_softint2[0];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b16_en[2] or posedge rtl_stickcmp_int[2] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint2[16] <= 1'b0;
end
else if (rtl_sftint_b16_en[2]) begin
if (rtl_stickcmp_int[2]) local_softint2[16] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint2[16] <= rtl_wsr_data_w[16];
else if (~rtl_set_sftint_l_g) local_softint2[16] <= (local_softint2[16] | rtl_wsr_data_w[16]);
else if (~rtl_clr_sftint_l_g) local_softint2[16] <= (local_softint2[16] & ~rtl_wsr_data_w[16]);
else local_softint2[16] <= local_softint2[16];
end
else begin
local_softint2[16] <= local_softint2[16];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b15_en[2] or posedge rtl_pib_picl_wrap[2] or posedge rtl_pib_pich_wrap[2] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint2[15] <= 1'b0;
end
else if (rtl_sftint_b15_en[2]) begin
if (rtl_pib_picl_wrap[2] | rtl_pib_pich_wrap[2]) local_softint2[15] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint2[15] <= rtl_wsr_data_w[15];
else if (~rtl_set_sftint_l_g) local_softint2[15] <= (local_softint2[15] | rtl_wsr_data_w[15]);
else if (~rtl_clr_sftint_l_g) local_softint2[15] <= (local_softint2[15] & ~rtl_wsr_data_w[15]);
else local_softint2[15] <= local_softint2[15];
end
else begin
local_softint2[15] <= local_softint2[15];
end
end // always
always @(rtl_softint2) begin
if (rtl_softint2 != local_softint2) begin
if (enable & rst_l) begin
$display("*ERROR*: %0d: softint_mon: Thread2 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint2[16:0], local_softint2[16:0]);
$display("*Info*: softint_mon: Use -sim_run_args=+turn_off_softint_monitor to disable the softint_mon");
`MONITOR_PATH.fail("softint_mon: Thread2 SOFTINT register mismatch");
end
else begin
$display("*WARNING*: %0d: softint_mon: Thread2 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint2[16:0], local_softint2[16:0]);
end
end
else begin
$display("*Info*: %0d: softint_mon: Thread2 SOFTINT register MATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint2[16:0], local_softint2[16:0]);
end
end
//=========================
// SOFTINT3 register update
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or negedge rtl_sftint_en_l_g[3] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint3[14:1] <= {14{1'b0}};
end
else if (~rtl_sftint_en_l_g[3]) begin
if (~rtl_wr_sftint_l_g) local_softint3[14:1] <= rtl_wsr_data_w[14:1];
else if (~rtl_set_sftint_l_g) local_softint3[14:1] <= (local_softint3[14:1] | rtl_wsr_data_w[14:1]);
else if (~rtl_clr_sftint_l_g) local_softint3[14:1] <= (local_softint3[14:1] & ~rtl_wsr_data_w[14:1]);
else local_softint3[14:1] <= local_softint3[14:1];
end
else begin
local_softint3[14:1] <= local_softint3[14:1];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b0_en[3] or posedge rtl_tickcmp_int[3] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint3[0] <= 1'b0;
end
else if (rtl_sftint_b0_en[3]) begin
if (rtl_tickcmp_int[3]) local_softint3[0] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint3[0] <= rtl_wsr_data_w[0];
else if (~rtl_set_sftint_l_g) local_softint3[0] <= (local_softint3[0] | rtl_wsr_data_w[0]);
else if (~rtl_clr_sftint_l_g) local_softint3[0] <= (local_softint3[0] & ~rtl_wsr_data_w[0]);
else local_softint3[0] <= local_softint3[0];
end
else begin
local_softint3[0] <= local_softint3[0];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b16_en[3] or posedge rtl_stickcmp_int[3] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint3[16] <= 1'b0;
end
else if (rtl_sftint_b16_en[3]) begin
if (rtl_stickcmp_int[3]) local_softint3[16] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint3[16] <= rtl_wsr_data_w[16];
else if (~rtl_set_sftint_l_g) local_softint3[16] <= (local_softint3[16] | rtl_wsr_data_w[16]);
else if (~rtl_clr_sftint_l_g) local_softint3[16] <= (local_softint3[16] & ~rtl_wsr_data_w[16]);
else local_softint3[16] <= local_softint3[16];
end
else begin
local_softint3[16] <= local_softint3[16];
end
end // always
always @(posedge rtl_clk or rtl_reset) begin
/*
always @(rtl_reset or posedge rtl_sftint_b15_en[3] or posedge rtl_pib_picl_wrap[3] or posedge rtl_pib_pich_wrap[3] or negedge rtl_wr_sftint_l_g or negedge rtl_set_sftint_l_g or negedge rtl_clr_sftint_l_g) begin
#1
*/
if (rtl_reset) begin
local_softint3[15] <= 1'b0;
end
else if (rtl_sftint_b15_en[3]) begin
if (rtl_pib_picl_wrap[3] | rtl_pib_pich_wrap[3]) local_softint3[15] <= 1'b1;
else if (~rtl_wr_sftint_l_g) local_softint3[15] <= rtl_wsr_data_w[15];
else if (~rtl_set_sftint_l_g) local_softint3[15] <= (local_softint3[15] | rtl_wsr_data_w[15]);
else if (~rtl_clr_sftint_l_g) local_softint3[15] <= (local_softint3[15] & ~rtl_wsr_data_w[15]);
else local_softint3[15] <= local_softint3[15];
end
else begin
local_softint3[15] <= local_softint3[15];
end
end // always
always @(rtl_softint3) begin
if (rtl_softint3 != local_softint3) begin
if (enable & rst_l) begin
$display("*ERROR*: %0d: softint_mon: Thread3 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint3[16:0], local_softint3[16:0]);
$display("*Info*: softint_mon: Use -sim_run_args=+turn_off_softint_monitor to disable the softint_mon");
`MONITOR_PATH.fail("softint_mon: Thread3 SOFTINT register mismatch");
end
else begin
$display("*WARNING*: %0d: softint_mon: Thread3 SOFTINT register MISMATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint3[16:0], local_softint3[16:0]);
end
end
else begin
$display("*Info*: %0d: softint_mon: Thread3 SOFTINT register MATCH: RTL(17'h%x) Vs Expected(17'h%x)", $time, rtl_softint3[16:0], local_softint3[16:0]);
end
end
endmodule
////////////////////////// //T H E E N D //////////////////////////
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer: Muhammad Ijaz
//
// Create Date: 05/05/2017 10:24:09 PM
// Design Name:
// Module Name: MULTIPLEXER_4_TO_1
// Project Name: RISC-V
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module MULTIPLEXER_4_TO_1 #(
parameter BUS_WIDTH = 32
) (
input [BUS_WIDTH - 1 : 0] IN1 ,
input [BUS_WIDTH - 1 : 0] IN2 ,
input [BUS_WIDTH - 1 : 0] IN3 ,
input [BUS_WIDTH - 1 : 0] IN4 ,
input [1 : 0] SELECT ,
output [BUS_WIDTH - 1 : 0] OUT
);
reg [BUS_WIDTH - 1 : 0] out_reg;
always@(*)
begin
case(SELECT)
2'b00:
begin
out_reg = IN1;
end
2'b01:
begin
out_reg = IN2;
end
2'b10:
begin
out_reg = IN3;
end
2'b11:
begin
out_reg = IN4;
end
endcase
end
assign OUT = out_reg;
endmodule
|
// clock polarity (CPOL) = 1 and clock phase (CPHA) = 1
// http://en.wikipedia.org/wiki/Serial_Peripheral_Interface_Bus
// http://www.byteparadigm.com/kb/article/AA-00255/22/Introduction-to-SPI-and-IC-protocols.html
// http://read.pudn.com/downloads132/doc/561635/123.doc
module SPI_3WIRE(
clk,
reset_n,
//
CMD_START,
CMD_DONE,
REG_ADDR,
REG_RW,
REG_RX_NUM,
FIFO_CLEAR,
FIFO_WRITE,
FIFO_WRITEDATA,
FIFO_READ_ACK,
FIFO_READDATA,
//
SPI_CS_n,
SPI_SCLK,
SPI_SDIO
);
parameter DIVIDER = 10;
parameter CPOL = 1;
input clk;
input reset_n;
input CMD_START;
output CMD_DONE;
input [5:0] REG_ADDR;
input REG_RW; // 1: read, 0:write
input [3:0] REG_RX_NUM; // 16 max, no = value+1
input FIFO_CLEAR;
input [7:0] FIFO_WRITE;
input [7:0] FIFO_WRITEDATA;
input [7:0] FIFO_READ_ACK;
output [7:0] FIFO_READDATA;
output SPI_CS_n;
output SPI_SCLK;
inout SPI_SDIO;
///////////////////////////////////
// generate spi clock
reg spi_clk;
reg [7:0] clk_cnt;
always @ (posedge clk or negedge reset_n)
begin
if (~reset_n)
begin
clk_cnt <= 0;
spi_clk <= 1;
end
else
begin
if (clk_cnt > DIVIDER)
begin
spi_clk <= ~spi_clk;
clk_cnt <= 0;
end
else
clk_cnt <= clk_cnt + 1;
end
end
///////////////////////////////
// tx fifo
reg fifo_tx_rdreq;
wire [7:0] fifo_tx_q;
wire fifo_tx_empty;
wire [7:0] fifo_tx_wrusedw;
gsensor_fifo gsensor_fifo_tx(
.aclr(FIFO_CLEAR),
.data(FIFO_WRITEDATA),
.rdclk(spi_clk),
.rdreq(fifo_tx_rdreq),
.wrclk(clk),
.wrreq(FIFO_WRITE),
.q(fifo_tx_q),
.rdempty(fifo_tx_empty),
.rdusedw(),
.wrfull(),
.wrusedw(fifo_tx_wrusedw)
);
///////////////////////////////
// rx fifo
reg [7:0] fifo_rx_data;
reg fifo_rx_wrreq;
gsensor_fifo gsensor_fifo_rx(
.aclr(FIFO_CLEAR),
.data(fifo_rx_data),
.rdclk(clk),
.rdreq(FIFO_READ_ACK),
.wrclk(spi_clk),
.wrreq(fifo_rx_wrreq),
.q(FIFO_READDATA),
.rdempty(),
.rdusedw(),
.wrfull(),
.wrusedw()
);
///////////////////////////////
// detect START edge
reg pre_CMD_START;
always @ (posedge spi_clk or negedge reset_n)
begin
if (~reset_n)
pre_CMD_START <= 1'b1;
else
pre_CMD_START <= CMD_START;
end
//////////////////////////////////
// state
`define ST_IDLE 3'd0
`define ST_START 3'd1
`define ST_RW_MB_ADDR 3'd2
`define ST_DATA 3'd3
`define ST_END 3'd4
`define ST_DONE 3'd5
reg [2:0] state;
reg [2:0] state_at_falling;
reg reg_write;
reg [5:0] rw_reg_byte_num;
reg [5:0] byte_cnt;
reg [2:0] bit_index;
always @ (posedge spi_clk or negedge reset_n)
begin
if (~reset_n)
state <= `ST_IDLE;
else if (~pre_CMD_START & CMD_START)
begin
state <= `ST_START;
reg_write <= ~REG_RW;
rw_reg_byte_num <= (REG_RW)?(REG_RX_NUM + 1):(fifo_tx_wrusedw);
end
else
begin
case (state)
`ST_START:
begin
bit_index <= 7;
state <= `ST_RW_MB_ADDR;
end
`ST_RW_MB_ADDR:
begin
if (bit_index == 0)
begin
state <= `ST_DATA;
byte_cnt <= rw_reg_byte_num-1;
end
//
bit_index <= bit_index - 1;
end
`ST_DATA:
begin
if (bit_index == 0)
begin
if (byte_cnt == 0)
state <= `ST_END;
else
byte_cnt <= byte_cnt - 1;
end
//
bit_index <= bit_index - 1;
end
`ST_END:
begin
state <= `ST_DONE;
end
`ST_DONE:
begin
state <= `ST_DONE;
end
default:
state <= `ST_IDLE;
endcase
end
end
//=========================
// get tx_byte from fifo
reg [7:0] tx_byte;
wire read_fifo_first;
wire read_fifo_other;
wire mb_flag;
assign read_fifo_first = ((state == `ST_RW_MB_ADDR) && (bit_index == 0) && reg_write)?1'b1:1'b0;
//assign read_fifo_1 = ((state == `ST_DATA) && (bit_index == 0) && reg_write)?1'b1:1'b0;
assign read_fifo_other = ((state == `ST_DATA) && (bit_index == 0) && reg_write && (byte_cnt != 0))?1'b1:1'b0;
assign mb_flag = (rw_reg_byte_num == 1)?1'b0:1'b1;
always @ (posedge spi_clk or negedge reset_n)
begin
if (~reset_n)
fifo_tx_rdreq <= 1'b0;
else if (state == `ST_START)
begin
// tx_byte <= {~reg_write, (reg_write)?((fifo_tx_wrusedw==1)?1'b0:1'b1):((REG_RX_NUM==0)?1'b0:1'b1), REG_ADDR};
tx_byte <= {~reg_write, mb_flag, REG_ADDR};
fifo_tx_rdreq <= 1'b0;
end
else if (read_fifo_first | read_fifo_other)
begin
tx_byte <= fifo_tx_q;
fifo_tx_rdreq <= 1'b1;
end
else
fifo_tx_rdreq <= 1'b0;
end
////////////////////////////////
// serial tx data at falling edge
reg tx_bit;
always @ (negedge spi_clk)
begin
tx_bit <= tx_byte[bit_index];
end
////////////////////////////////
// capture serail rx data at rising edge
reg [7:0] rx_byte;
always @ (posedge spi_clk or negedge reset_n)
begin
if (~reset_n)
fifo_rx_wrreq <= 1'b0;
else if (~data_out)
begin
if (bit_index == 0)
begin
fifo_rx_data <= {rx_byte[7:1], SPI_SDIO};
rx_byte <= 0;
fifo_rx_wrreq <= 1'b1;
end
else
begin
rx_byte[bit_index] <= SPI_SDIO;
fifo_rx_wrreq <= 1'b0;
end
end
else
fifo_rx_wrreq <= 1'b0;
end
////////////////////////////////
// phase at falling edge
always @ (negedge spi_clk or negedge reset_n)
begin
if (~reset_n)
state_at_falling <= `ST_IDLE;
else
state_at_falling <= state;
end
////////////////////////////////
// combiniation
wire data_out;
assign data_out = ((state_at_falling == `ST_RW_MB_ADDR) || (state_at_falling == `ST_DATA && reg_write))?1'b1:1'b0;
assign SPI_CS_n = (state_at_falling == `ST_IDLE || state_at_falling == `ST_DONE)?1'b1:1'b0;
assign SPI_SCLK = (~SPI_CS_n && (state != `ST_START) && (state != `ST_END))?spi_clk:1'b1;
assign SPI_SDIO = (~SPI_CS_n & data_out)?(tx_bit?1'b1:1'b0):1'bz;
assign CMD_DONE = (state == `ST_DONE)?1'b1:1'b0;
///////////////////////////////
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V
/**
* or4b: 4-input OR, first input inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__or4b (
X ,
A ,
B ,
C ,
D_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A ;
input B ;
input C ;
input D_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire not0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
not not0 (not0_out , D_N );
or or0 (or0_out_X , not0_out, C, B, A );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__OR4B_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
`define SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
/**
* muxb4to1: Buffered 4-input multiplexer.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__muxb4to1 (
//# {{data|Data Signals}}
input [3:0] D,
output Z,
//# {{control|Control Signals}}
input [3:0] S
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUXB4TO1_SYMBOL_V
|
// DESCRIPTION: Verilator: Test of gated clock detection
//
// The code as shown generates a result by a delayed assignment from PC. The
// creation of the result is from a clock gated from the clock that sets
// PC. Howevever since they are essentially the same clock, the result should
// be delayed by one cycle.
//
// Standard Verilator treats them as different clocks, so the result stays in
// step with the PC. An event drive simulator always allows the clock to win.
//
// The problem is caused by the extra loop added by Verilator to the
// evaluation of all internally generated clocks (effectively removed by
// marking the clock enable).
//
// This test is added to facilitate experiments with solutions.
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2013 by Jeremy Bennett <[email protected]>.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg gated_clk_en = 1'b0 ;
reg [1:0] pc = 2'b0;
reg [1:0] res = 2'b0;
wire gated_clk = gated_clk_en & clk;
always @(posedge clk) begin
pc <= pc + 1;
gated_clk_en <= 1'b1;
end
always @(posedge gated_clk) begin
res <= pc;
end
always @(posedge clk) begin
if (pc == 2'b11) begin
// Correct behaviour is that res should be lagging pc in the count
// by one cycle
if (res == 2'b10) begin
$write("*-* All Finished *-*\n");
$finish;
end
else begin
$stop;
end
end
end
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized AND with generic_baseblocks_v2_1_0_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_0_carry_and #
(
parameter C_FAMILY = "virtex6"
// FPGA Family. Current version: virtex6 or spartan6.
)
(
input wire CIN,
input wire S,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" ) begin : USE_RTL
assign COUT = CIN & S;
end else begin : USE_FPGA
MUXCY and_inst
(
.O (COUT),
.CI (CIN),
.DI (1'b0),
.S (S)
);
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__CLKBUF_4_V
`define SKY130_FD_SC_HDLL__CLKBUF_4_V
/**
* clkbuf: Clock tree buffer.
*
* Verilog wrapper for clkbuf with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__clkbuf.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_4 (
X ,
A ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__clkbuf_4 (
X,
A
);
output X;
input A;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__clkbuf base (
.X(X),
.A(A)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__CLKBUF_4_V
|
/* ****************************************************************************
This Source Code Form is subject to the terms of the
Open Hardware Description License, v. 1.0. If a copy
of the OHDL was not distributed with this file, You
can obtain one at http://juliusbaxter.net/ohdl/ohdl.txt
Description: Load, store unit for espresso pipeline
All combinatorial outputs to pipeline
Dbus interface request signal out synchronous
32-bit specific due to sign extension of results
Copyright (C) 2012 Authors
Author(s): Julius Baxter <[email protected]>
***************************************************************************** */
`include "mor1kx-defines.v"
module mor1kx_lsu_espresso
(/*AUTOARG*/
// Outputs
lsu_result_o, lsu_valid_o, lsu_except_dbus_o, lsu_except_align_o,
dbus_adr_o, dbus_req_o, dbus_dat_o, dbus_bsel_o, dbus_we_o,
dbus_burst_o,
// Inputs
clk, rst, padv_fetch_i, lsu_adr_i, rfb_i, op_lsu_load_i,
op_lsu_store_i, lsu_length_i, lsu_zext_i, exception_taken_i,
du_restart_i, stepping_i, next_fetch_done_i, dbus_err_i,
dbus_ack_i, dbus_dat_i
);
parameter OPTION_OPERAND_WIDTH = 32;
parameter OPTION_REGISTERED_IO = "NO";
input clk, rst;
input padv_fetch_i;
// calculated address from ALU
input [OPTION_OPERAND_WIDTH-1:0] lsu_adr_i;
// register file B in (store operand)
input [OPTION_OPERAND_WIDTH-1:0] rfb_i;
// from decode stage regs, indicate if load or store
input op_lsu_load_i;
input op_lsu_store_i;
input [1:0] lsu_length_i;
input lsu_zext_i;
input exception_taken_i;
input du_restart_i;
input stepping_i;
input next_fetch_done_i;
output [OPTION_OPERAND_WIDTH-1:0] lsu_result_o;
output lsu_valid_o;
// exception output
output lsu_except_dbus_o;
output lsu_except_align_o;
// interface to data bus
output [OPTION_OPERAND_WIDTH-1:0] dbus_adr_o;
output dbus_req_o;
output [OPTION_OPERAND_WIDTH-1:0] dbus_dat_o;
output [3:0] dbus_bsel_o;
output dbus_we_o;
output dbus_burst_o;
input dbus_err_i;
input dbus_ack_i;
input [OPTION_OPERAND_WIDTH-1:0] dbus_dat_i;
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_aligned; // comb.
reg [OPTION_OPERAND_WIDTH-1:0] dbus_dat_extended; // comb.
reg [OPTION_OPERAND_WIDTH-1:0] dbus_adr_r;
reg [3:0] dbus_bsel;
reg dbus_err_r;
reg access_done;
reg [OPTION_OPERAND_WIDTH-1:0] lsu_result_r;
reg op_lsu;
wire align_err_word;
wire align_err_short;
wire align_err;
wire except_align;
reg except_align_r;
reg except_dbus;
reg execute_go;
assign dbus_dat_o = (lsu_length_i == 2'b00) ? // byte access
{rfb_i[7:0],rfb_i[7:0],rfb_i[7:0],rfb_i[7:0]} :
(lsu_length_i == 2'b01) ? // halfword access
{rfb_i[15:0],rfb_i[15:0]} :
rfb_i; // word access
assign align_err_word = |dbus_adr_o[1:0];
assign align_err_short = dbus_adr_o[0];
assign lsu_valid_o = dbus_ack_i | dbus_err_r| access_done;
assign lsu_except_dbus_o = dbus_err_r | except_dbus;
assign align_err = (lsu_length_i == 2'b10) & align_err_word |
(lsu_length_i == 2'b01) & align_err_short;
assign lsu_except_align_o = except_align_r;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
execute_go <= 0;
else
execute_go <= padv_fetch_i | (stepping_i & next_fetch_done_i);
always @(posedge clk `OR_ASYNC_RST)
if (rst)
access_done <= 0;
else if (padv_fetch_i | du_restart_i)
access_done <= 0;
else if (dbus_ack_i | dbus_err_r | lsu_except_align_o)
access_done <= 1;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_align_r <= 0;
else if (exception_taken_i)
except_align_r <= 0;
else
except_align_r <= except_align;
always @(posedge clk `OR_ASYNC_RST)
if (rst)
except_dbus <= 0;
else if (exception_taken_i)
except_dbus <= 0;
else if (dbus_err_r)
except_dbus <= 1;
// Need to register address due to behavior of RF when source register is
// same as destination register - value changes after one cycle to the
// forwarding register's value, which is incorrect.
// So we save it on first cycle.
// TODO - perhaps detect in RF when this is case, and make it keep the
// output steady to avoid an extra address registering stage here.
always @(posedge clk `OR_ASYNC_RST)
if (rst)
dbus_adr_r <= 0;
else if (execute_go & (op_lsu_load_i | op_lsu_store_i))
dbus_adr_r <= lsu_adr_i;
// Big endian bus mapping
always @(*)
case (lsu_length_i)
2'b00: // byte access
case(dbus_adr_o[1:0])
2'b00:
dbus_bsel = 4'b1000;
2'b01:
dbus_bsel = 4'b0100;
2'b10:
dbus_bsel = 4'b0010;
2'b11:
dbus_bsel = 4'b0001;
endcase
2'b01: // halfword access
case(dbus_adr_o[1])
1'b0:
dbus_bsel = 4'b1100;
1'b1:
dbus_bsel = 4'b0011;
endcase
2'b10,
2'b11:
dbus_bsel = 4'b1111;
endcase
assign dbus_bsel_o = dbus_bsel;
assign dbus_we_o = op_lsu_store_i;
// Select part of read word
// Can use registered address here, as it'll take at least one cycle for
// the data to come back, and by that time dbus_adr_r has the address
always @*
case(dbus_adr_r[1:0])
2'b00:
dbus_dat_aligned = dbus_dat_i;
2'b01:
dbus_dat_aligned = {dbus_dat_i[23:0],8'd0};
2'b10:
dbus_dat_aligned = {dbus_dat_i[15:0],16'd0};
2'b11:
dbus_dat_aligned = {dbus_dat_i[7:0],24'd0};
endcase // case (dbus_adr_r[1:0])
// Do appropriate extension
always @(*)
case({lsu_zext_i, lsu_length_i})
3'b100: // lbz
dbus_dat_extended = {24'd0,dbus_dat_aligned[31:24]};
3'b101: // lhz
dbus_dat_extended = {16'd0,dbus_dat_aligned[31:16]};
3'b000: // lbs
dbus_dat_extended = {{24{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:24]};
3'b001: // lhs
dbus_dat_extended = {{16{dbus_dat_aligned[31]}},
dbus_dat_aligned[31:16]};
default:
dbus_dat_extended = dbus_dat_aligned;
endcase
// Register result incase writeback doesn't occur for a few cycles
// TODO - remove this - we should write straight into the RF!
always @(posedge clk)
if (dbus_ack_i & op_lsu_load_i)
lsu_result_r <= dbus_dat_extended;
assign dbus_burst_o = 0;
// Break up paths of signals which are usually pretty long
generate
if (OPTION_REGISTERED_IO!="NO")
begin : registered_io
assign dbus_adr_o = dbus_adr_r;
always @(posedge clk)
begin
dbus_err_r <= dbus_err_i;
op_lsu <= op_lsu_load_i | op_lsu_store_i;
end
// Make sure padv_i isn't high because we'll be registering the
// fact that this cycle is an LSU op while it is
assign dbus_req_o = !execute_go & op_lsu &
!(except_align | except_align_r) &
!access_done;
assign except_align = op_lsu & (op_lsu_load_i | op_lsu_store_i) &
align_err & !execute_go;
end
else
begin : nonregistered_io
assign dbus_adr_o = execute_go ? lsu_adr_i : dbus_adr_r;
always @*
begin
dbus_err_r = dbus_err_i;
op_lsu = op_lsu_load_i | op_lsu_store_i;
end
assign dbus_req_o = op_lsu & !except_align & !access_done;
assign except_align = op_lsu & align_err;
end
endgenerate
assign lsu_result_o = access_done ? lsu_result_r : dbus_dat_extended;
endmodule // mor1kx_lsu
|
// test_mis.v - Testbench for mis.bvrl
// 01-22-01 E. Brombaugh
/*
* Copyright (c) 2001 Eric Brombaugh <[email protected]>
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* The mis'' module was generated by the synopsis module compiler
* and is typical of the modules it generates. The testbench was hand
* coded. This file was merged into a single file using the Verilog
* preprocessor.
*/
`timescale 1ns / 10 ps
module mis( y, a, b );
input [3:0] a;
input [3:0] b;
output [12:0] y;
wire dpa_zero, dpa_one;
wire [5:0] const__1_24_;
wire [7:0] C0;
wire [6:0] const__2_33_;
wire [7:0] C1;
wire [12:0] y_1_;
assign dpa_zero= 1024'h0;
assign dpa_one= 1024'h1;
assign const__1_24_=- 1024'h18;
assign const__2_33_=- 1024'h21;
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:5 input signed [3:0] a, b; */
/* mis.mcl:10 C0 = -24; */
assign C0= ((const__1_24_[4:0]-(const__1_24_[5]<<5)));
/* mis.mcl:11 C1 = -33; */
assign C1= ((const__2_33_[5:0]-(const__2_33_[6]<<6)));
/* mis.mcl:13 y = C0*a + C1*b; */
assign y_1_= ((C0[6:0]-(C0[7]<<7))*(a[2:0]-(a[3]<<3))+
(C1[6:0]-(C1[7]<<7))*(b[2:0]-(b[3]<<3)));
/* mis.mcl:6 output signed [12:0] y; */
assign y = y_1_[12:0];
/* mis.mcl:4 module mis (y, a, b); */
/* mis.mcl:13 y = C0*a + C1*b; */
/*User Defined Aliases */
endmodule
module test_mis;
reg [10:0] count;
reg clk;
reg [3:0] a, b;
wire [12:0] y;
mis u1(y, a, b);
initial
begin
count = 0;
clk = 0;
a = 0;
b = 0;
end
always
#10 clk = ~clk;
always @(posedge clk)
begin
a = count[3:0];
b = count[7:4];
#10
$display("%h %h %h", a, b, y);
count = count + 1;
if(count == 0)
$finish(0);
end
endmodule
|
// ----------------------------------------------------------------------
// Copyright (c) 2016, The Regents of the University of California All
// rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met:
//
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
//
// * Redistributions in binary form must reproduce the above
// copyright notice, this list of conditions and the following
// disclaimer in the documentation and/or other materials provided
// with the distribution.
//
// * Neither the name of The Regents of the University of California
// nor the names of its contributors may be used to endorse or
// promote products derived from this software without specific
// prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL REGENTS OF THE
// UNIVERSITY OF CALIFORNIA BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
// OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
// TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
// USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH
// DAMAGE.
// ----------------------------------------------------------------------
//----------------------------------------------------------------------------
// Filename: tx_port_writer.v
// Version: 1.00.a
// Verilog Standard: Verilog-2001
// Description: Handles receiving new transaction events and data, and
// making requests to tx engine.
// for the RIFFA channel.
// Author: Matt Jacobsen
// History: @mattj: Version 2.0
//-----------------------------------------------------------------------------
`define S_TXPORTWR_MAIN_IDLE 8'b0000_0001
`define S_TXPORTWR_MAIN_CHECK 8'b0000_0010
`define S_TXPORTWR_MAIN_SIG_NEW 8'b0000_0100
`define S_TXPORTWR_MAIN_NEW_ACK 8'b0000_1000
`define S_TXPORTWR_MAIN_WRITE 8'b0001_0000
`define S_TXPORTWR_MAIN_DONE 8'b0010_0000
`define S_TXPORTWR_MAIN_SIG_DONE 8'b0100_0000
`define S_TXPORTWR_MAIN_RESET 8'b1000_0000
`define S_TXPORTWR_TX_IDLE 8'b0000_0001
`define S_TXPORTWR_TX_BUF 8'b0000_0010
`define S_TXPORTWR_TX_ADJ_0 8'b0000_0100
`define S_TXPORTWR_TX_ADJ_1 8'b0000_1000
`define S_TXPORTWR_TX_ADJ_2 8'b0001_0000
`define S_TXPORTWR_TX_CHECK_DATA 8'b0010_0000
`define S_TXPORTWR_TX_WRITE 8'b0100_0000
`define S_TXPORTWR_TX_WRITE_REM 8'b1000_0000
`timescale 1ns/1ns
module tx_port_writer (
input CLK,
input RST,
input [2:0] CONFIG_MAX_PAYLOAD_SIZE, // Maximum write payload: 000=128B, 001=256B, 010=512B, 011=1024B
output TXN, // Write transaction notification
input TXN_ACK, // Write transaction acknowledged
output [31:0] TXN_LEN, // Write transaction length
output [31:0] TXN_OFF_LAST, // Write transaction offset/last
output [31:0] TXN_DONE_LEN, // Write transaction actual transfer length
output TXN_DONE, // Write transaction done
output TXN_ERR, // Write transaction encountered an error
input TXN_DONE_ACK, // Write transaction actual transfer length read
input NEW_TXN, // Transaction parameters are valid
output NEW_TXN_ACK, // Transaction parameter read, continue
input NEW_TXN_LAST, // Channel last write
input [31:0] NEW_TXN_LEN, // Channel write length (in 32 bit words)
input [30:0] NEW_TXN_OFF, // Channel write offset
input [31:0] NEW_TXN_WORDS_RECVD, // Count of data words received in transaction
input NEW_TXN_DONE, // Transaction is closed
input [63:0] SG_ELEM_ADDR, // Scatter gather element address
input [31:0] SG_ELEM_LEN, // Scatter gather element length (in words)
input SG_ELEM_RDY, // Scatter gather element ready
input SG_ELEM_EMPTY, // Scatter gather elements empty
output SG_ELEM_REN, // Scatter gather element read enable
output SG_RST, // Scatter gather data reset
input SG_ERR, // Scatter gather read encountered an error
output TX_REQ, // Outgoing write request
input TX_REQ_ACK, // Outgoing write request acknowledged
output [63:0] TX_ADDR, // Outgoing write high address
output [9:0] TX_LEN, // Outgoing write length (in 32 bit words)
output TX_LAST, // Outgoing write is last request for transaction
input TX_SENT // Outgoing write complete
);
`include "functions.vh"
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rMainState=`S_TXPORTWR_MAIN_IDLE, _rMainState=`S_TXPORTWR_MAIN_IDLE;
reg [31:0] rOffLast=0, _rOffLast=0;
reg rWordsEQ0=0, _rWordsEQ0=0;
reg rStarted=0, _rStarted=0;
reg [31:0] rDoneLen=0, _rDoneLen=0;
reg rSgErr=0, _rSgErr=0;
reg rTxErrd=0, _rTxErrd=0;
reg rTxnAck=0, _rTxnAck=0;
(* syn_encoding = "user" *)
(* fsm_encoding = "user" *)
reg [7:0] rTxState=`S_TXPORTWR_TX_IDLE, _rTxState=`S_TXPORTWR_TX_IDLE;
reg [31:0] rSentWords=0, _rSentWords=0;
reg [31:0] rWords=0, _rWords=0;
reg [31:0] rBufWords=0, _rBufWords=0;
reg [31:0] rBufWordsInit=0, _rBufWordsInit=0;
reg rLargeBuf=0, _rLargeBuf=0;
reg [63:0] rAddr=64'd0, _rAddr=64'd0;
reg [2:0] rCarry=0, _rCarry=0;
reg rValsPropagated=0, _rValsPropagated=0;
reg [5:0] rValsProp=0, _rValsProp=0;
reg rCopyBufWords=0, _rCopyBufWords=0;
reg rUseInit=0, _rUseInit=0;
reg [10:0] rPageRem=0, _rPageRem=0;
reg rPageSpill=0, _rPageSpill=0;
reg rPageSpillInit=0, _rPageSpillInit=0;
reg [10:0] rPreLen=0, _rPreLen=0;
reg [2:0] rMaxPayloadSize=0, _rMaxPayloadSize=0;
reg [2:0] rMaxPayloadShift=0, _rMaxPayloadShift=0;
reg [9:0] rMaxPayload=0, _rMaxPayload=0;
reg rPayloadSpill=0, _rPayloadSpill=0;
reg rMaxLen=1, _rMaxLen=1;
reg [9:0] rLen=0, _rLen=0;
reg [31:0] rSendingWords=0, _rSendingWords=0;
reg rAvail=0, _rAvail=0;
reg [1:0] rTxnDone=0, _rTxnDone=0;
reg [9:0] rLastLen=0, _rLastLen=0;
reg rLastLenEQ0=0, _rLastLenEQ0=0;
reg rLenEQWords=0, _rLenEQWords=0;
reg rLenEQBufWords=0, _rLenEQBufWords=0;
reg rNotRequesting=1, _rNotRequesting=1;
reg [63:0] rReqAddr=64'd0, _rReqAddr=64'd0;
reg [9:0] rReqLen=0, _rReqLen=0;
reg rReqLast=0, _rReqLast=0;
reg rTxReqAck=0, _rTxReqAck=0;
reg rDone=0, _rDone=0;
reg [9:0] rAckCount=0, _rAckCount=0;
reg rTxSent=0, _rTxSent=0;
reg rLastDoneRead=1, _rLastDoneRead=1;
reg rTxnDoneAck=0, _rTxnDoneAck=0;
reg rReqPartialDone=0, _rReqPartialDone=0;
reg rPartialDone=0, _rPartialDone=0;
assign NEW_TXN_ACK = rMainState[1]; // S_TXPORTWR_MAIN_CHECK
assign TXN = rMainState[2]; // S_TXPORTWR_MAIN_SIG_NEW
assign TXN_DONE = (rMainState[6] | rPartialDone); // S_TXPORTWR_MAIN_SIG_DONE
assign TXN_LEN = rWords;
assign TXN_OFF_LAST = rOffLast;
assign TXN_DONE_LEN = rDoneLen;
assign TXN_ERR = rTxErrd;
assign SG_ELEM_REN = rTxState[2]; // S_TXPORTWR_TX_ADJ_0
assign SG_RST = rMainState[3]; // S_TXPORTWR_MAIN_NEW_ACK
assign TX_REQ = !rNotRequesting;
assign TX_ADDR = rReqAddr;
assign TX_LEN = rReqLen;
assign TX_LAST = rReqLast;
// Buffer the input signals that come from outside the tx_port.
always @ (posedge CLK) begin
rTxnAck <= #1 (RST ? 1'd0 : _rTxnAck);
rTxnDoneAck <= #1 (RST ? 1'd0 : _rTxnDoneAck);
rSgErr <= #1 (RST ? 1'd0 : _rSgErr);
rTxReqAck <= #1 (RST ? 1'd0 : _rTxReqAck);
rTxSent <= #1 (RST ? 1'd0 : _rTxSent);
end
always @ (*) begin
_rTxnAck = TXN_ACK;
_rTxnDoneAck = TXN_DONE_ACK;
_rSgErr = SG_ERR;
_rTxReqAck = TX_REQ_ACK;
_rTxSent = TX_SENT;
end
// Wait for a NEW_TXN request. Then request transfers until all the data is sent
// or until the specified length is reached. Then signal TXN_DONE.
always @ (posedge CLK) begin
rMainState <= #1 (RST ? `S_TXPORTWR_MAIN_IDLE : _rMainState);
rOffLast <= #1 _rOffLast;
rWordsEQ0 <= #1 _rWordsEQ0;
rStarted <= #1 _rStarted;
rDoneLen <= #1 (RST ? 0 : _rDoneLen);
rTxErrd <= #1 (RST ? 1'd0 : _rTxErrd);
end
always @ (*) begin
_rMainState = rMainState;
_rOffLast = rOffLast;
_rWordsEQ0 = rWordsEQ0;
_rStarted = rStarted;
_rDoneLen = rDoneLen;
_rTxErrd = rTxErrd;
case (rMainState)
`S_TXPORTWR_MAIN_IDLE: begin // Wait for channel write request
_rStarted = 0;
_rWordsEQ0 = (NEW_TXN_LEN == 0);
_rOffLast = {NEW_TXN_OFF, NEW_TXN_LAST};
if (NEW_TXN)
_rMainState = `S_TXPORTWR_MAIN_CHECK;
end
`S_TXPORTWR_MAIN_CHECK: begin // Continue with transaction?
if (rOffLast[0] | !rWordsEQ0)
_rMainState = `S_TXPORTWR_MAIN_SIG_NEW;
else
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_SIG_NEW: begin // Signal new write
_rMainState = `S_TXPORTWR_MAIN_NEW_ACK;
end
`S_TXPORTWR_MAIN_NEW_ACK: begin // Wait for acknowledgement
if (rTxnAck) // ACK'd on PC read of TXN length
_rMainState = (rWordsEQ0 ? `S_TXPORTWR_MAIN_SIG_DONE : `S_TXPORTWR_MAIN_WRITE);
end
`S_TXPORTWR_MAIN_WRITE: begin // Start writing and wait for all writes to complete
_rStarted = (rStarted | rTxState[1]); // S_TXPORTWR_TX_BUF
_rTxErrd = (rTxErrd | rSgErr);
if (rTxState[0] & rStarted) // S_TXPORTWR_TX_IDLE
_rMainState = `S_TXPORTWR_MAIN_DONE;
end
`S_TXPORTWR_MAIN_DONE: begin // Wait for the last transaction to complete
if (rDone & rLastDoneRead) begin
_rDoneLen = rSentWords;
_rMainState = `S_TXPORTWR_MAIN_SIG_DONE;
end
end
`S_TXPORTWR_MAIN_SIG_DONE: begin // Signal the done port
_rTxErrd = 0;
_rMainState = `S_TXPORTWR_MAIN_RESET;
end
`S_TXPORTWR_MAIN_RESET: begin // Wait for the channel tx to drop
if (NEW_TXN_DONE)
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
default: begin
_rMainState = `S_TXPORTWR_MAIN_IDLE;
end
endcase
end
// Manage sending TX requests to the TX engine. Transfers will be limited
// by each scatter gather buffer's size, max payload size, and must not
// cross a (4KB) page boundary. The request is only made if there is sufficient
// data already written to the buffer.
wire [9:0] wLastLen = (NEW_TXN_WORDS_RECVD - rSentWords);
wire [9:0] wAddrLoInv = ~rAddr[11:2];
wire [10:0] wPageRem = (wAddrLoInv + 1'd1);
always @ (posedge CLK) begin
rTxState <= #1 (RST | rSgErr ? `S_TXPORTWR_TX_IDLE : _rTxState);
rSentWords <= #1 (rMainState[0] ? 0 : _rSentWords);
rWords <= #1 _rWords;
rBufWords <= #1 _rBufWords;
rBufWordsInit <= #1 _rBufWordsInit;
rAddr <= #1 _rAddr;
rCarry <= #1 _rCarry;
rValsPropagated <= #1 _rValsPropagated;
rValsProp <= #1 _rValsProp;
rLargeBuf <= #1 _rLargeBuf;
rPageRem <= #1 _rPageRem;
rPageSpill <= #1 _rPageSpill;
rPageSpillInit <= #1 _rPageSpillInit;
rCopyBufWords <= #1 _rCopyBufWords;
rUseInit <= #1 _rUseInit;
rPreLen <= #1 _rPreLen;
rMaxPayloadSize <= #1 _rMaxPayloadSize;
rMaxPayloadShift <= #1 _rMaxPayloadShift;
rMaxPayload <= #1 _rMaxPayload;
rPayloadSpill <= #1 _rPayloadSpill;
rMaxLen <= #1 (RST ? 1'd1 : _rMaxLen);
rLen <= #1 _rLen;
rSendingWords <= #1 _rSendingWords;
rAvail <= #1 _rAvail;
rTxnDone <= #1 _rTxnDone;
rLastLen <= #1 _rLastLen;
rLastLenEQ0 <= #1 _rLastLenEQ0;
rLenEQWords <= #1 _rLenEQWords;
rLenEQBufWords <= #1 _rLenEQBufWords;
end
always @ (*) begin
_rTxState = rTxState;
_rCopyBufWords = rCopyBufWords;
_rUseInit = rUseInit;
_rValsProp = ((rValsProp<<1) | rTxState[3]); // S_TXPORTWR_TX_ADJ_1
_rValsPropagated = (rValsProp == 6'd0);
_rLargeBuf = (SG_ELEM_LEN > rWords);
{_rCarry[0], _rAddr[15:0]} = (rTxState[1] ? SG_ELEM_ADDR[15:0] : (rAddr[15:0] + ({12{rTxState[6]}} & {rLen, 2'd0}))); // S_TXPORTWR_TX_WRITE
{_rCarry[1], _rAddr[31:16]} = (rTxState[1] ? SG_ELEM_ADDR[31:16] : (rAddr[31:16] + rCarry[0]));
{_rCarry[2], _rAddr[47:32]} = (rTxState[1] ? SG_ELEM_ADDR[47:32] : (rAddr[47:32] + rCarry[1]));
_rAddr[63:48] = (rTxState[1] ? SG_ELEM_ADDR[63:48] : (rAddr[63:48] + rCarry[2]));
_rSentWords = (rTxState[7] ? NEW_TXN_WORDS_RECVD : rSentWords) + ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rWords = (NEW_TXN_ACK ? NEW_TXN_LEN : (rWords - ({10{rTxState[6]}} & rLen))); // S_TXPORTWR_TX_WRITE
_rBufWordsInit = (rLargeBuf ? rWords : SG_ELEM_LEN);
_rBufWords = (rCopyBufWords ? rBufWordsInit : rBufWords) - ({10{rTxState[6]}} & rLen); // S_TXPORTWR_TX_WRITE
_rPageRem = wPageRem;
_rPageSpillInit = (rBufWordsInit > wPageRem);
_rPageSpill = (rBufWords > wPageRem);
_rPreLen = ((rPageSpillInit & rUseInit) | (rPageSpill & !rUseInit) ? rPageRem : rBufWords[10:0]);
_rMaxPayloadSize = CONFIG_MAX_PAYLOAD_SIZE;
_rMaxPayloadShift = (rMaxPayloadSize > 3'd4 ? 3'd4 : rMaxPayloadSize);
_rMaxPayload = (6'd32<<rMaxPayloadShift);
_rPayloadSpill = (rPreLen > rMaxPayload);
_rMaxLen = ((rMaxLen & !rValsProp[1]) | rTxState[6]); // S_TXPORTWR_TX_WRITE
_rLen = (rPayloadSpill | rMaxLen ? rMaxPayload : rPreLen[9:0]);
_rSendingWords = rSentWords + rLen;
_rAvail = (NEW_TXN_WORDS_RECVD >= rSendingWords);
_rTxnDone = ((rTxnDone<<1) | NEW_TXN_DONE);
_rLastLen = wLastLen;
_rLastLenEQ0 = (rLastLen == 10'd0);
_rLenEQWords = (rLen == rWords);
_rLenEQBufWords = (rLen == rBufWords);
case (rTxState)
`S_TXPORTWR_TX_IDLE: begin // Wait for channel write request
if (rMainState[4] & !rStarted) // S_TXPORTWR_MAIN_WRITE
_rTxState = `S_TXPORTWR_TX_BUF;
end
`S_TXPORTWR_TX_BUF: begin // Wait for buffer length and address
if (SG_ELEM_RDY)
_rTxState = `S_TXPORTWR_TX_ADJ_0;
end
`S_TXPORTWR_TX_ADJ_0: begin // Fix for large buffer
_rCopyBufWords = 1;
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_ADJ_1: begin // Check for page boundary crossing
_rCopyBufWords = 0;
_rUseInit = rCopyBufWords;
_rTxState = `S_TXPORTWR_TX_ADJ_2;
end
`S_TXPORTWR_TX_ADJ_2: begin // Wait for values to propagate
// Fix for page boundary crossing
// Check for max payload
// Fix for max payload
_rUseInit = 0;
if (rValsProp[2])
_rTxState = `S_TXPORTWR_TX_CHECK_DATA;
end
`S_TXPORTWR_TX_CHECK_DATA: begin // Wait for available data
if (rNotRequesting) begin
if (rAvail)
_rTxState = `S_TXPORTWR_TX_WRITE;
else if (rValsPropagated & rTxnDone[1])
_rTxState = (rLastLenEQ0 ? `S_TXPORTWR_TX_IDLE : `S_TXPORTWR_TX_WRITE_REM);
end
end
`S_TXPORTWR_TX_WRITE: begin // Send len and repeat or finish?
if (rLenEQWords)
_rTxState = `S_TXPORTWR_TX_IDLE;
else if (rLenEQBufWords)
_rTxState = `S_TXPORTWR_TX_BUF;
else
_rTxState = `S_TXPORTWR_TX_ADJ_1;
end
`S_TXPORTWR_TX_WRITE_REM: begin // Send remaining data and finish
_rTxState = `S_TXPORTWR_TX_IDLE;
end
default: begin
_rTxState = `S_TXPORTWR_TX_IDLE;
end
endcase
end
// Request TX transfers separately so that the TX FSM can continue calculating
// the next set of request parameters without having to wait for the TX_REQ_ACK.
always @ (posedge CLK) begin
rAckCount <= #1 (RST ? 10'd0 : _rAckCount);
rNotRequesting <= #1 (RST ? 1'd1 : _rNotRequesting);
rReqAddr <= #1 _rReqAddr;
rReqLen <= #1 _rReqLen;
rReqLast <= #1 _rReqLast;
rDone <= #1 _rDone;
rLastDoneRead <= #1 (RST ? 1'd1 : _rLastDoneRead);
end
always @ (*) begin
// Start signaling when the TX FSM is ready.
if (rTxState[6] | rTxState[7]) // S_TXPORTWR_TX_WRITE
_rNotRequesting = 0;
else
_rNotRequesting = (rNotRequesting | rTxReqAck);
// Pass off the rAddr & rLen when ready and wait for TX_REQ_ACK.
if (rTxState[6]) begin // S_TXPORTWR_TX_WRITE
_rReqAddr = rAddr;
_rReqLen = rLen;
_rReqLast = rLenEQWords;
end
else if (rTxState[7]) begin // S_TXPORTWR_TX_WRITE_REM
_rReqAddr = rAddr;
_rReqLen = rLastLen;
_rReqLast = 1;
end
else begin
_rReqAddr = rReqAddr;
_rReqLen = rReqLen;
_rReqLast = rReqLast;
end
// Track TX_REQ_ACK and TX_SENT to determine when the transaction is over.
_rDone = (rAckCount == 10'd0);
if (rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rAckCount = 0;
else
_rAckCount = rAckCount + rTxState[6] + rTxState[7] - rTxSent; // S_TXPORTWR_TX_WRITE, S_TXPORTWR_TX_WRITE_REM
// Track when the user reads the actual transfer amount.
_rLastDoneRead = (rMainState[6] ? 1'd0 : (rLastDoneRead | rTxnDoneAck)); // S_TXPORTWR_MAIN_SIG_DONE
end
// Facilitate sending a TXN_DONE when we receive a TXN_ACK after the transaction
// has begun sending. This will happen when the workstation detects that it has
// sent/used all its currently mapped scatter gather elements, but it's not enough
// to complete the transaction. The TXN_DONE will let the workstation know it can
// release the current scatter gather mappings and allocate new ones.
always @ (posedge CLK) begin
rPartialDone <= #1 _rPartialDone;
rReqPartialDone <= #1 (RST ? 1'd0 : _rReqPartialDone);
end
always @ (*) begin
// Signal TXN_DONE after we've recieved the (seemingly superfluous) TXN_ACK,
// we have no outstanding transfer requests, we're not currently requesting a
// transfer, and there are no more scatter gather elements.
_rPartialDone = (rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]); // S_TXPORTWR_TX_BUF
// Keep track of (seemingly superfluous) TXN_ACK requests.
if ((rReqPartialDone & rDone & rNotRequesting & SG_ELEM_EMPTY & rTxState[1]) | rMainState[0]) // S_TXPORTWR_MAIN_IDLE
_rReqPartialDone = 0;
else
_rReqPartialDone = (rReqPartialDone | (rTxnAck & !rMainState[3])); // !S_TXPORTWR_MAIN_NEW_ACK
end
/*
wire [35:0] wControl0;
chipscope_icon_1 cs_icon(
.CONTROL0(wControl0)
);
chipscope_ila_t8_512 a0(
.CLK(CLK),
.CONTROL(wControl0),
.TRIG0({rTxState[6] | rTxState[7] | rTxSent, rAckCount[6:0]}),
.DATA({280'd0,
NEW_TXN_WORDS_RECVD, // 32
rSendingWords, // 32
rAvail, // 1
rNotRequesting, // 1
NEW_TXN_LAST, // 1
NEW_TXN_LEN, // 32
NEW_TXN_OFF, // 31
NEW_TXN, // 1
rAckCount, // 10
rLastDoneRead, // 1
rWords, // 32
rBufWords, // 32
rLen, // 10
rTxState, // 8
rMainState}) // 8
);
*/
endmodule
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
module LiftControl(sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK
,Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis
,Stop3Dis,Stop4Dis,PosDis/*,choice*/,seg);//核心控制模块,The Top Level
output Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;//向上、向下与停靠的请求显示
output[3:0] PosDis;//楼层显示
output[6:0] seg;
//input choice;
input sw0,sw1,sw2,sw3,sw4,sw5,reset,k0,k1,k2,k3,CLK;//向上、向下与停靠的按键输入
wire clk,reset;
reg DoorFlag=1'b0,blink;
reg Up1Dis,Up2Dis,Up3Dis,Dn2Dis,Dn3Dis,Dn4Dis,Stop1Dis,Stop2Dis,Stop3Dis,Stop4Dis;
reg[1:0] UpDnFlag=2'b00;
reg[2:0] count;//门开后要持续4个时钟周期,用count
reg[3:0] pos,PosDis;
wire[6:0] seg;
//reg speedup=1'b0;
reg[3:0] UpReq,DownReq,StopReq;//分别用来合并向上请求的各信号，向下请求的各信号和停靠请求的各信号
reg[6:0] LiftState=7'b0000001,NextState=7'b0000001;//分别表示电梯的当前状态和下一状态
parameter WAIT=7'b0000001, UP=7'b0000010, DOWN=7'b0000100, UPSTOP=7'b0001000
, DOWNSTOP=7'b0010000, OPENDOOR=7'b0100000, CLOSEDOOR=7'b1000000;
parameter IDLE=4'b0000,FLOOR1=4'b0001, FLOOR2=4'b0010, FLOOR3=4'b0100, FLOOR4=4'b1000;
parameter TRUE=1'b1, FALSE=1'b0;
parameter OPEN=1'b1, CLOSED=1'b0;
parameter UPFLAG=2'b01,DNFLAG=2'b10,STATIC=2'b00;
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
LEDDisplay led(.pos(pos), .seg(seg));
/*
always @(posedge clk or posedge choice)
if(choice)
FrequenceDevide fd(.CLK(CLK),.reset(reset),.clk(clk));//降频模块
else
FrequenceDevide2 fd(.speedup(speedup),.CLK(CLK),.reset(reset),.clk(clk));//降频模块*/
always @(posedge sw0 or posedge reset or posedge DoorFlag)//一层上升请求
begin
if(reset)
Up1Dis<=1'b0;
if(sw0)
Up1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Up1Dis<=1'b0;
end
end
end
always @(posedge sw1 or posedge reset or posedge DoorFlag)//二层上升请求
begin
if(reset)
Up2Dis<=1'b0;
if(sw1)
Up2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Up2Dis<=1'b0;
end
end
end
always @(posedge sw2 or posedge reset or posedge DoorFlag)//三层上升请求
begin
if(reset)
Up3Dis<=1'b0;
if(sw2)
Up3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Up3Dis<=1'b0;
end
end
end
always @(posedge sw3 or posedge reset or posedge DoorFlag)//二层下降请求
begin
if(reset)
Dn2Dis<=1'b0;
if(sw3)
Dn2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Dn2Dis<=1'b0;
end
end
end
always @(posedge sw4 or posedge reset or posedge DoorFlag)//三层下降请求
begin
if(reset)
Dn3Dis<=1'b0;
if(sw4)
Dn3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Dn3Dis<=1'b0;
end
end
end
always @(posedge sw5 or posedge reset or posedge DoorFlag)//四层下降请求
begin
if(reset)
Dn4Dis<=1'b0;
if(sw5)
Dn4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Dn4Dis<=1'b0;
end
end
end
always @(posedge k0 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop1Dis<=1'b0;
if(k0)
Stop1Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0001)
begin
Stop1Dis<=1'b0;
end
end
end
always @(posedge k1 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop2Dis<=1'b0;
if(k1)
Stop2Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0010)
begin
Stop2Dis<=1'b0;
end
end
end
always @(posedge k2 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop3Dis<=1'b0;
if(k2)
Stop3Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b0100)
begin
Stop3Dis<=1'b0;
end
end
end
always @(posedge k3 or posedge reset or posedge DoorFlag)
begin
if(reset)
Stop4Dis<=1'b0;
if(k3)
Stop4Dis<=1'b1;
else if(DoorFlag)
begin
if(pos==4'b1000)
begin
Stop4Dis<=1'b0;
end
end
end
always @(pos or blink or reset or clk)
begin
if(reset)
PosDis=4'b0001;
else if(blink)//开门LED闪烁
PosDis=IDLE;
else
case(pos)
FLOOR1:
PosDis=FLOOR1;
FLOOR2:
PosDis=FLOOR2;
FLOOR3:
PosDis=FLOOR3;
FLOOR4:
PosDis=FLOOR4;
default:
PosDis=FLOOR1;
endcase
//若使用如下方法，电梯不能正常运行
//同时赋值时钟脉冲紊乱，故单独使用LEDDisplay模块处理楼层LED显示
/*case(pos)
FLOOR1:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
FLOOR2:
begin
PosDis<=FLOOR2;
seg<=7'b0100100;
end
FLOOR3:
begin
PosDis<=FLOOR3;
seg<=7'b0110000;
end
FLOOR4:
begin
PosDis<=FLOOR4;
seg<=7'b0011001;
end
default:
begin
PosDis<=FLOOR1;
seg<=7'b1111001;
end
endcase */
end
always @(Up1Dis or Up2Dis or Up3Dis )
UpReq={1'b0,Up3Dis,Up2Dis,Up1Dis};
always @(Dn2Dis or Dn3Dis or Dn4Dis)
DownReq={Dn4Dis, Dn3Dis, Dn2Dis,1'b0};
always @(Stop1Dis or Stop2Dis or Stop3Dis or Stop4Dis)
StopReq={Stop4Dis,Stop3Dis,Stop2Dis,Stop1Dis};
always @(posedge clk or posedge reset)
if(reset)
begin
LiftState<=WAIT;
end
else
begin
LiftState<=NextState;
end
always @(clk)
begin
if((DoorFlag==OPEN)&&(~clk))//门打开并且时钟信号处于低电平
blink<=1'b1;//开门LED闪烁信号
else
blink<=1'b0;
end
always @(LiftState or UpReq or DownReq or StopReq or pos or count or UpDnFlag or reset)
begin
if(reset)
NextState=WAIT;
else
case(LiftState)
WAIT:
begin
if(StopReq>0)//有停靠请求否
begin
if((StopReq&pos)>0)//停靠请求中有当前楼层停靠请求否
NextState=OPENDOOR;//有当前楼层请求，则下一状态转开门
else if(StopReq>pos)//有当前楼层之上的停靠请求否
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))//上下请求中有当前楼层请求否
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))//上下请求中有当前楼层之上的请求否
NextState=UP;
else if(UpReq||DownReq)//上下请求中有当前楼层之下的请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，继续处于WAIT模式
end
UP:
begin
if((StopReq&pos)||(UpReq&pos))//停靠或上升请求中有当前楼层的请求否
NextState=UPSTOP;//有，下一状态转为UPSTOP(停靠后要1s才开门,UPSTOP即为这1s的过渡期)
else if((StopReq>pos)||(UpReq>pos))//停靠或上升请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//下降请求中有当前楼层之上的请求否
NextState=UP;
else if((DownReq&pos)&&(pos<FLOOR4))
NextState=DOWNSTOP;
else if((DownReq&pos)&&(pos==FLOOR4))
NextState=DOWNSTOP;
else//下降请求中只有当前楼层之下的请求
NextState=DOWN;
end
else if(StopReq||UpReq)//只有当前楼层之上的停靠或上升请求否
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
DOWN:
begin
if((StopReq&pos)||(DownReq&pos))
NextState=DOWNSTOP;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)&&(pos>FLOOR1))
NextState=UPSTOP;
else if((UpReq&pos)&&(pos==FLOOR1))
NextState=UPSTOP;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
UPSTOP:
begin
NextState=OPENDOOR;
end
DOWNSTOP:
begin
NextState=OPENDOOR;
end
OPENDOOR:
begin
if(count<4)//开门不足4周期，则继续转移到开门状态
NextState=OPENDOOR;
else
NextState=CLOSEDOOR;
end
CLOSEDOOR:
begin
if(UpDnFlag==UPFLAG)//开门关门前电梯是处于上升状态
begin
if((StopReq&pos)||(UpReq&pos))//上升或停靠请求中有当前楼层的请求否，有可能关门的瞬间又有新的请求
NextState=OPENDOOR;
else if((StopReq>pos)||(UpReq>pos))//上升或停靠请求中有当前楼层之上的请求否
NextState=UP;
else if(DownReq>0)//有下降请求否
begin
if((DownReq>pos)&&((DownReq^pos)>pos))//有当前楼层之上的下降请求，则下一状态转移上升
NextState=UP;
else if((DownReq&pos)>0)//有当前楼层的下降请求信号，且更上层无下降请求
NextState=OPENDOOR;
else//只有低于当前层的下降请求
NextState=DOWN;
end
else if(StopReq||UpReq)//上升和停靠请求中只有当前层下的请求
NextState=DOWN;
else
NextState=WAIT;//无任何请求，转为WAIT模式
end
else if(UpDnFlag==DNFLAG)
begin
if((StopReq&pos)||(DownReq&pos))
NextState=OPENDOOR;
else if(((StopReq&FLOOR1)<pos&&(StopReq&FLOOR1))||((StopReq&FLOOR2)<pos&&(StopReq&FLOOR2))||((StopReq&FLOOR3)<pos&&(StopReq&FLOOR3))||((StopReq&FLOOR4)<pos&&(StopReq&FLOOR4)))
NextState=DOWN;
else if(((DownReq&FLOOR1)<pos&&(DownReq&FLOOR1))||((DownReq&FLOOR2)<pos&&(DownReq&FLOOR2))||((DownReq&FLOOR3)<pos&&(DownReq&FLOOR3))||((DownReq&FLOOR4)<pos&&(DownReq&FLOOR4)))
NextState=DOWN;
else if(UpReq>0)
begin
if(((UpReq&FLOOR1)<pos&&(UpReq&FLOOR1))||((UpReq&FLOOR2)<pos&&(UpReq&FLOOR2))||((UpReq&FLOOR3)<pos&&(UpReq&FLOOR3))||((UpReq&FLOOR4)<pos&&(UpReq&FLOOR4)))
NextState=DOWN;
else if((UpReq&pos)>0)
NextState=OPENDOOR;
else
NextState=UP;
end
else if(StopReq||DownReq)
NextState=UP;
else
NextState=WAIT;
end
else
begin
if(StopReq>0)
begin
if((StopReq&pos)>0)
NextState=OPENDOOR;
else if(StopReq>pos)
NextState=UP;
else
NextState=DOWN;
end
else if((UpReq&pos)||(DownReq&pos))
begin
NextState=OPENDOOR;
end
else if((UpReq>pos)||(DownReq>pos))
NextState=UP;
else if(UpReq||DownReq)
NextState=DOWN;
else
begin
NextState=WAIT;
end
end
end
default:
NextState=WAIT;
endcase
end
always @(posedge clk or posedge reset)
if(reset)
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
else
begin
case(NextState)
WAIT:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
UP:
begin
pos<=pos<<1;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWN:
begin
pos<=pos>>1;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
UPSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UPFLAG;
end
DOWNSTOP:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=DNFLAG;
end
OPENDOOR:
begin
pos<=pos;
DoorFlag<=OPEN;
UpDnFlag<=UpDnFlag;
end
CLOSEDOOR:
begin
pos<=pos;
DoorFlag<=CLOSED;
UpDnFlag<=UpDnFlag;
end
default:
begin
pos<=FLOOR1;
DoorFlag<=CLOSED;
UpDnFlag<=STATIC;
end
endcase
end
always @(posedge clk or posedge reset)
if(reset)
count<=0;
else if((NextState==OPENDOOR)&&(count<4))
count<=count+1;
else
count<=0;
endmodule |
// (C) 2001-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
`timescale 1 ps / 1 ps
module hps_sdram_p0_acv_hard_io_pads(
reset_n_addr_cmd_clk,
reset_n_afi_clk,
oct_ctl_rs_value,
oct_ctl_rt_value,
phy_ddio_address,
phy_ddio_bank,
phy_ddio_cs_n,
phy_ddio_cke,
phy_ddio_odt,
phy_ddio_we_n,
phy_ddio_ras_n,
phy_ddio_cas_n,
phy_ddio_ck,
phy_ddio_reset_n,
phy_mem_address,
phy_mem_bank,
phy_mem_cs_n,
phy_mem_cke,
phy_mem_odt,
phy_mem_we_n,
phy_mem_ras_n,
phy_mem_cas_n,
phy_mem_reset_n,
pll_afi_clk,
pll_afi_phy_clk,
pll_avl_phy_clk,
pll_avl_clk,
avl_clk,
pll_mem_clk,
pll_mem_phy_clk,
pll_write_clk,
pll_dqs_ena_clk,
pll_addr_cmd_clk,
phy_mem_dq,
phy_mem_dm,
phy_mem_ck,
phy_mem_ck_n,
mem_dqs,
mem_dqs_n,
dll_phy_delayctrl,
scc_clk,
scc_data,
scc_dqs_ena,
scc_dqs_io_ena,
scc_dq_ena,
scc_dm_ena,
scc_upd,
seq_read_latency_counter,
seq_read_increment_vfifo_fr,
seq_read_increment_vfifo_hr,
phy_ddio_dmdout,
phy_ddio_dqdout,
phy_ddio_dqs_oe,
phy_ddio_dqsdout,
phy_ddio_dqsb_oe,
phy_ddio_dqslogic_oct,
phy_ddio_dqslogic_fiforeset,
phy_ddio_dqslogic_aclr_pstamble,
phy_ddio_dqslogic_aclr_fifoctrl,
phy_ddio_dqslogic_incwrptr,
phy_ddio_dqslogic_readlatency,
ddio_phy_dqslogic_rdatavalid,
ddio_phy_dqdin,
phy_ddio_dqslogic_incrdataen,
phy_ddio_dqslogic_dqsena,
phy_ddio_dqoe,
capture_strobe_tracking
);
parameter DEVICE_FAMILY = "";
parameter FAST_SIM_MODEL = 0;
parameter OCT_SERIES_TERM_CONTROL_WIDTH = "";
parameter OCT_PARALLEL_TERM_CONTROL_WIDTH = "";
parameter MEM_ADDRESS_WIDTH = "";
parameter MEM_BANK_WIDTH = "";
parameter MEM_CHIP_SELECT_WIDTH = "";
parameter MEM_CLK_EN_WIDTH = "";
parameter MEM_CK_WIDTH = "";
parameter MEM_ODT_WIDTH = "";
parameter MEM_DQS_WIDTH = "";
parameter MEM_DM_WIDTH = "";
parameter MEM_CONTROL_WIDTH = "";
parameter MEM_DQ_WIDTH = "";
parameter MEM_READ_DQS_WIDTH = "";
parameter MEM_WRITE_DQS_WIDTH = "";
parameter DLL_DELAY_CTRL_WIDTH = "";
parameter ADC_PHASE_SETTING = "";
parameter ADC_INVERT_PHASE = "";
parameter IS_HHP_HPS = "";
localparam AFI_ADDRESS_WIDTH = 64;
localparam AFI_BANK_WIDTH = 12;
localparam AFI_CHIP_SELECT_WIDTH = 8;
localparam AFI_CLK_EN_WIDTH = 8;
localparam AFI_ODT_WIDTH = 8;
localparam AFI_DATA_MASK_WIDTH = 20;
localparam AFI_CONTROL_WIDTH = 4;
input reset_n_afi_clk;
input reset_n_addr_cmd_clk;
input [OCT_SERIES_TERM_CONTROL_WIDTH-1:0] oct_ctl_rs_value;
input [OCT_PARALLEL_TERM_CONTROL_WIDTH-1:0] oct_ctl_rt_value;
input [AFI_ADDRESS_WIDTH-1:0] phy_ddio_address;
input [AFI_BANK_WIDTH-1:0] phy_ddio_bank;
input [AFI_CHIP_SELECT_WIDTH-1:0] phy_ddio_cs_n;
input [AFI_CLK_EN_WIDTH-1:0] phy_ddio_cke;
input [AFI_ODT_WIDTH-1:0] phy_ddio_odt;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ras_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_cas_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_ck;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_we_n;
input [AFI_CONTROL_WIDTH-1:0] phy_ddio_reset_n;
output [MEM_ADDRESS_WIDTH-1:0] phy_mem_address;
output [MEM_BANK_WIDTH-1:0] phy_mem_bank;
output [MEM_CHIP_SELECT_WIDTH-1:0] phy_mem_cs_n;
output [MEM_CLK_EN_WIDTH-1:0] phy_mem_cke;
output [MEM_ODT_WIDTH-1:0] phy_mem_odt;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_we_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_ras_n;
output [MEM_CONTROL_WIDTH-1:0] phy_mem_cas_n;
output phy_mem_reset_n;
input pll_afi_clk;
input pll_afi_phy_clk;
input pll_avl_phy_clk;
input pll_avl_clk;
input avl_clk;
input pll_mem_clk;
input pll_mem_phy_clk;
input pll_write_clk;
input pll_dqs_ena_clk;
input pll_addr_cmd_clk;
inout [MEM_DQ_WIDTH-1:0] phy_mem_dq;
output [MEM_DM_WIDTH-1:0] phy_mem_dm;
output [MEM_CK_WIDTH-1:0] phy_mem_ck;
output [MEM_CK_WIDTH-1:0] phy_mem_ck_n;
inout [MEM_DQS_WIDTH-1:0] mem_dqs;
inout [MEM_DQS_WIDTH-1:0] mem_dqs_n;
input [DLL_DELAY_CTRL_WIDTH-1:0] dll_phy_delayctrl;
input scc_clk;
input scc_data;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_ena;
input [MEM_READ_DQS_WIDTH - 1:0] scc_dqs_io_ena;
input [MEM_DQ_WIDTH - 1:0] scc_dq_ena;
input [MEM_DM_WIDTH - 1:0] scc_dm_ena;
input [4:0] seq_read_latency_counter;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_fr;
input [MEM_READ_DQS_WIDTH-1:0] seq_read_increment_vfifo_hr;
input scc_upd;
output [MEM_READ_DQS_WIDTH - 1:0] capture_strobe_tracking;
input [24 : 0] phy_ddio_dmdout;
input [179 : 0] phy_ddio_dqdout;
input [9 : 0] phy_ddio_dqs_oe;
input [19 : 0] phy_ddio_dqsdout;
input [9 : 0] phy_ddio_dqsb_oe;
input [9 : 0] phy_ddio_dqslogic_oct;
input [4 : 0] phy_ddio_dqslogic_fiforeset;
input [4 : 0] phy_ddio_dqslogic_aclr_pstamble;
input [4 : 0] phy_ddio_dqslogic_aclr_fifoctrl;
input [9 : 0] phy_ddio_dqslogic_incwrptr;
input [24 : 0] phy_ddio_dqslogic_readlatency;
output [4 : 0] ddio_phy_dqslogic_rdatavalid;
output [179 : 0] ddio_phy_dqdin;
input [9 : 0] phy_ddio_dqslogic_incrdataen;
input [9 : 0] phy_ddio_dqslogic_dqsena;
input [89 : 0] phy_ddio_dqoe;
wire [MEM_DQ_WIDTH-1:0] mem_phy_dq;
wire [DLL_DELAY_CTRL_WIDTH-1:0] read_bidir_dll_phy_delayctrl;
wire [MEM_READ_DQS_WIDTH-1:0] bidir_read_dqs_bus_out;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_high;
wire [MEM_DQ_WIDTH-1:0] bidir_read_dq_input_data_out_low;
wire dqs_busout;
wire hr_clk = pll_avl_clk;
wire core_clk = pll_afi_clk;
wire reset_n_core_clk = reset_n_afi_clk;
hps_sdram_p0_acv_hard_addr_cmd_pads uaddr_cmd_pads(
/*
.config_data_in(config_data_in),
.config_clock_in(config_clock_in),
.config_io_ena(config_io_ena),
.config_update(config_update),
*/
.reset_n (reset_n_addr_cmd_clk),
.reset_n_afi_clk (reset_n_afi_clk),
.pll_afi_clk (pll_afi_phy_clk),
.pll_mem_clk (pll_mem_phy_clk),
.pll_hr_clk (hr_clk),
.pll_avl_phy_clk (pll_avl_phy_clk),
.pll_write_clk (pll_write_clk),
.dll_delayctrl_in (dll_phy_delayctrl),
.phy_ddio_address (phy_ddio_address),
.phy_ddio_bank (phy_ddio_bank),
.phy_ddio_cs_n (phy_ddio_cs_n),
.phy_ddio_cke (phy_ddio_cke),
.phy_ddio_odt (phy_ddio_odt),
.phy_ddio_we_n (phy_ddio_we_n),
.phy_ddio_ras_n (phy_ddio_ras_n),
.phy_ddio_cas_n (phy_ddio_cas_n),
.phy_ddio_ck (phy_ddio_ck),
.phy_ddio_reset_n (phy_ddio_reset_n),
.phy_mem_address (phy_mem_address),
.phy_mem_bank (phy_mem_bank),
.phy_mem_cs_n (phy_mem_cs_n),
.phy_mem_cke (phy_mem_cke),
.phy_mem_odt (phy_mem_odt),
.phy_mem_we_n (phy_mem_we_n),
.phy_mem_ras_n (phy_mem_ras_n),
.phy_mem_cas_n (phy_mem_cas_n),
.phy_mem_reset_n (phy_mem_reset_n),
.phy_mem_ck (phy_mem_ck),
.phy_mem_ck_n (phy_mem_ck_n)
);
defparam uaddr_cmd_pads.DEVICE_FAMILY = DEVICE_FAMILY;
defparam uaddr_cmd_pads.MEM_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH;
defparam uaddr_cmd_pads.MEM_BANK_WIDTH = MEM_BANK_WIDTH;
defparam uaddr_cmd_pads.MEM_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH;
defparam uaddr_cmd_pads.MEM_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH;
defparam uaddr_cmd_pads.MEM_CK_WIDTH = MEM_CK_WIDTH;
defparam uaddr_cmd_pads.MEM_ODT_WIDTH = MEM_ODT_WIDTH;
defparam uaddr_cmd_pads.MEM_CONTROL_WIDTH = MEM_CONTROL_WIDTH;
defparam uaddr_cmd_pads.AFI_ADDRESS_WIDTH = MEM_ADDRESS_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_BANK_WIDTH = MEM_BANK_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CHIP_SELECT_WIDTH = MEM_CHIP_SELECT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CLK_EN_WIDTH = MEM_CLK_EN_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_ODT_WIDTH = MEM_ODT_WIDTH * 4;
defparam uaddr_cmd_pads.AFI_CONTROL_WIDTH = MEM_CONTROL_WIDTH * 4;
defparam uaddr_cmd_pads.DLL_WIDTH = DLL_DELAY_CTRL_WIDTH;
defparam uaddr_cmd_pads.ADC_PHASE_SETTING = ADC_PHASE_SETTING;
defparam uaddr_cmd_pads.ADC_INVERT_PHASE = ADC_INVERT_PHASE;
defparam uaddr_cmd_pads.IS_HHP_HPS = IS_HHP_HPS;
localparam NUM_OF_DQDQS = MEM_WRITE_DQS_WIDTH;
localparam DQDQS_DATA_WIDTH = MEM_DQ_WIDTH / NUM_OF_DQDQS;
localparam NATIVE_GROUP_SIZE =
(DQDQS_DATA_WIDTH == 8) ? 9 : DQDQS_DATA_WIDTH;
localparam DQDQS_DM_WIDTH = MEM_DM_WIDTH / MEM_WRITE_DQS_WIDTH;
localparam NUM_OF_DQDQS_WITH_DM = MEM_WRITE_DQS_WIDTH;
generate
genvar i;
for (i=0; i<NUM_OF_DQDQS; i=i+1)
begin: dq_ddio
hps_sdram_p0_altdqdqs ubidir_dq_dqs (
.write_strobe_clock_in (pll_mem_phy_clk),
.reset_n_core_clock_in (reset_n_core_clk),
.core_clock_in (core_clk),
.fr_clock_in (pll_write_clk),
.hr_clock_in (pll_avl_phy_clk),
.parallelterminationcontrol_in(oct_ctl_rt_value),
.seriesterminationcontrol_in(oct_ctl_rs_value),
.strobe_ena_hr_clock_in (hr_clk),
.capture_strobe_tracking (capture_strobe_tracking[i]),
.read_write_data_io (phy_mem_dq[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.read_data_out (ddio_phy_dqdin[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.capture_strobe_out(dqs_busout),
.extra_write_data_in (phy_ddio_dmdout[(i + 1) * 4 - 1 : (i * 4)]),
.write_data_in (phy_ddio_dqdout[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*4-1) : (NATIVE_GROUP_SIZE*i*4)]),
.write_oe_in (phy_ddio_dqoe[((NATIVE_GROUP_SIZE*i+DQDQS_DATA_WIDTH)*2-1) : (NATIVE_GROUP_SIZE*i*2)]),
.strobe_io (mem_dqs[i]),
.strobe_n_io (mem_dqs_n[i]),
.output_strobe_ena(phy_ddio_dqs_oe[(i + 1) * 2 - 1 : (i * 2)]),
.write_strobe(phy_ddio_dqsdout[(i + 1) * 4 - 1 : (i * 4)]),
.oct_ena_in(phy_ddio_dqslogic_oct[(i + 1) * 2 - 1 : (i * 2)]),
.extra_write_data_out (phy_mem_dm[i]),
.config_data_in (scc_data),
.config_dqs_ena (scc_dqs_ena[i]),
.config_io_ena (scc_dq_ena[(DQDQS_DATA_WIDTH*(i+1)-1) : DQDQS_DATA_WIDTH*i]),
.config_dqs_io_ena (scc_dqs_io_ena[i]),
.config_update (scc_upd),
.config_clock_in (scc_clk),
.config_extra_io_ena (scc_dm_ena[i]),
.lfifo_rdata_en(phy_ddio_dqslogic_incrdataen[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rdata_en_full(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.lfifo_rd_latency(phy_ddio_dqslogic_readlatency[(i + 1) * 5 - 1 : (i * 5)]),
.lfifo_reset_n (phy_ddio_dqslogic_aclr_fifoctrl[i]),
.lfifo_rdata_valid(ddio_phy_dqslogic_rdatavalid[i]),
.vfifo_qvld(phy_ddio_dqslogic_dqsena[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_inc_wr_ptr(phy_ddio_dqslogic_incwrptr[(i + 1) * 2 - 1 : (i * 2)]),
.vfifo_reset_n (phy_ddio_dqslogic_aclr_pstamble[i]),
.dll_delayctrl_in (dll_phy_delayctrl),
.rfifo_reset_n(phy_ddio_dqslogic_fiforeset[i])
);
end
endgenerate
generate
genvar j;
for (j = NUM_OF_DQDQS; j < 5; j=j+1)
begin: to_vcc
assign ddio_phy_dqslogic_rdatavalid[j] = 1'b1;
end
endgenerate
endmodule
|
(******************************************************************************)
(** Imports **)
(* Disable notation conflict warnings *)
Set Warnings "-notation-overridden".
(* SSReflect *)
From Coq Require Import ssreflect ssrbool ssrfun.
From mathcomp Require Import ssrnat seq eqtype.
Set Bullet Behavior "Strict Subproofs".
(* Sortedness *)
Require Import Coq.Sorting.Sorted.
(* Basic Haskell libraries *)
Require Import GHC.Base Proofs.GHC.Base.
Require Import GHC.List Proofs.GHC.List.
Require Import GHC.Enum Proofs.GHC.Enum.
Require Import Data.Foldable Proofs.Data.Foldable.
Require Import Data.OldList Proofs.Data.OldList.
Require Import Data.Bits Proofs.Data.Bits.Popcount.
(* Quickcheck *)
Require Import Test.QuickCheck.Property.
(* IntSet library *)
Require Import Data.IntSet.Internal.
(* IntSet proofs *)
Require Import IntSetProperties.
Require Import DyadicIntervals.
Require Import IntSetProofs.
(* Bit manipulation *)
Require Import BitUtils.
(* Working with Haskell *)
Require Import OrdTactic.
Require Import HSUtil IntSetUtil SortedUtil.
(******************************************************************************)
(** Name dismabiguation -- copied from HSUtil **)
Notation list := Coq.Init.Datatypes.list.
Notation seq := Coq.Lists.List.seq.
Notation reflect := ssrbool.reflect.
(******************************************************************************)
(** Theorems **)
(** The quoted comments and the section headers are taken directly from
`intset-properties.hs`. **)
(********************************************************************
Valid IntMaps
********************************************************************)
Theorem thm_Valid : toProp prop_Valid.
Proof.
rewrite /prop_Valid /forValidUnitTree /forValid /=; apply valid_correct.
Qed.
(********************************************************************
Construction validity
********************************************************************)
Theorem thm_EmptyValid : toProp prop_EmptyValid.
Proof. done. Qed.
Theorem thm_SingletonValid : toProp prop_SingletonValid.
Proof.
rewrite /prop_SingletonValid /= => x POS_x.
by apply valid_correct, singleton_WF.
Qed.
Theorem thm_InsertIntoEmptyValid : toProp prop_InsertIntoEmptyValid.
Proof.
rewrite /prop_InsertIntoEmptyValid /= => x POS.
by apply valid_correct, insert_WF.
Qed.
(********************************************************************
Single, Member, Insert, Delete, Member, FromList
********************************************************************)
Theorem thm_Single : toProp prop_Single.
Proof. by rewrite /prop_Single /= => x POS_x; apply/Eq_eq. Qed.
Theorem thm_Member : toProp prop_Member.
Proof.
rewrite /prop_Member /= => xs POS_xs n POS_n.
rewrite !Foldable_all_ssreflect; apply/allP => /= k.
by rewrite fromList_member // Eq_refl.
Qed.
Theorem thm_NotMember : toProp prop_NotMember.
Proof.
rewrite /prop_NotMember /= => xs POS_xs n POS_n.
rewrite !Foldable_all_ssreflect; apply/allP => /= k.
by rewrite /notMember /notElem /= fromList_member // Eq_refl.
Qed.
(* SKIPPED: test_LookupSomething, prop_LookupLT, prop_LookupGT, prop_LookupLE, prop_LookupGE *)
Theorem thm_InsertDelete : toProp prop_InsertDelete.
Proof.
rewrite /prop_InsertDelete /= => x POS s WF_s.
move: (insert_WF x _ WF_s ) => WF_ins.
move: (delete_WF x _ WF_ins) => WF_res.
case x_nin_s: (~~ member x s) => //=; split=> /=; first by apply valid_correct.
apply/eqIntSetMemberP => // k.
rewrite delete_member // insert_member //.
rewrite Eq_inv andb_orr andbN orFb.
case: (EqExact_cases k x) => [[Beq Peq] | [Bneq Pneq]].
- by rewrite Peq; move: x_nin_s => /negbTE->; rewrite andbF.
- by rewrite Bneq andTb.
Qed.
(* Cheating: manually forgetting POS constraint *)
Theorem thm_MemberFromList : toProp prop_MemberFromList.
Proof.
rewrite /prop_MemberFromList /= => xs _.
set abs_xs := flat_map _ xs.
apply/andP; split.
all: rewrite Foldable_all_ssreflect; apply/allP => /= k; rewrite in_elem.
- rewrite fromList_member //.
- rewrite /notMember /notElem /= fromList_member //.
+ move=> k_abs; have k_pos: (0 <= k)%N. {
Nomega.
}
clear k_abs; subst abs_xs; elim: xs => [|x xs IH] //=.
rewrite elem_app negb_orb IH andbT.
by case: k k_pos {IH}; case: x.
Qed.
(********************************************************************
Union, Difference and Intersection
********************************************************************)
Theorem thm_UnionInsert : toProp prop_UnionInsert.
Proof.
rewrite /prop_UnionInsert /= => x POS_x s WF_s.
move: (singleton_WF x) => WF_sing.
move: (union_WF _ _ WF_s WF_sing) => WF_union.
move: (insert_WF x _ WF_s) => WF_ins.
split=> /=; first by apply valid_correct.
apply/eqIntSetMemberP => // k.
by rewrite union_member // singleton_member // insert_member // orbC.
Qed.
Theorem thm_UnionAssoc : toProp prop_UnionAssoc.
Proof.
rewrite /prop_UnionAssoc /= => s1 WF1 s2 WF2 s3 WF3.
move: (union_WF _ _ WF1 WF2) => WF12.
move: (union_WF _ _ WF2 WF3) => WF23.
move: (union_WF _ _ WF12 WF3) => WF123.
move: (union_WF _ _ WF1 WF23) => WF123'.
apply/eqIntSetMemberP => // k.
by rewrite !union_member // orbA.
Qed.
Theorem thm_UnionComm : toProp prop_UnionComm.
Proof.
Proof.
rewrite /prop_UnionComm /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
move: (union_WF _ _ WF2 WF1) => WF21.
apply/eqIntSetMemberP => // k.
by rewrite !union_member // orbC.
Qed.
Theorem thm_Diff : toProp prop_Diff.
Proof.
rewrite /prop_Diff /= => xs POS_xs ys POS_ys.
move: (fromList_WF xs) => WF_xs.
move: (fromList_WF ys) => WF_ys.
move: (difference_WF _ _ WF_xs WF_ys) => WF_diff.
split=> /=; first by apply valid_correct.
apply/Eq_eq/StronglySorted_Ord_eq_In.
- by apply toList_sorted.
- apply StronglySorted_NoDup_Ord; first apply sort_StronglySorted.
rewrite -sort_NoDup.
apply diff_preserves_NoDup, nub_NoDup.
- move=> a.
rewrite !(rwP (elemP _ _)).
rewrite sort_elem.
rewrite diff_NoDup_elem; last apply nub_NoDup.
rewrite !nub_elem.
rewrite toAscList_member // difference_member // !fromList_member //.
Qed.
Theorem thm_Int : toProp prop_Int.
Proof.
rewrite /prop_Int /= => xs _ ys _.
move: (fromList_WF xs) => WF_xs.
move: (fromList_WF ys) => WF_ys.
move: (intersection_WF _ _ WF_xs WF_ys) => WF_both.
split=> /=; first by apply valid_correct.
apply/Eq_eq; fold toList.
apply StronglySorted_Nlt_eq_In;
[by apply to_List_sorted | apply StronglySorted_sort_nub_Nlt | ].
move=> a.
by rewrite !(rwP (elemP _ _))
toList_member // intersection_member // !fromList_member //
sort_elem nub_elem intersect_elem.
Qed.
Theorem thm_disjoint : toProp prop_disjoint.
Proof.
rewrite /prop_disjoint /= => s1 WF1 s2 WF2.
move: (intersection_WF _ _ WF1 WF2) => WF12.
apply/Eq_eq/bool_eq_iff.
rewrite disjoint_member // null_member //.
split=> [is_disjoint | is_not_intersection] k.
- rewrite intersection_member //; apply negbTE.
apply is_disjoint.
- move: (is_not_intersection k).
rewrite intersection_member // => /negbT.
by rewrite negb_andb.
Qed.
(********************************************************************
Lists
********************************************************************)
(* SKIPPED: prop_Ordered *)
Theorem thm_List : toProp prop_List.
Proof.
rewrite /prop_List /=; rewrite -/toList => xs POS_xs.
Proof.
have WF_xs: WF (fromList xs) by apply fromList_WF.
apply/Eq_eq/StronglySorted_Ord_eq_In.
- apply StronglySorted_sort_nub.
- apply toList_sorted, fromList_WF=> //.
- move=> a.
by rewrite !(rwP (elemP _ _))
toList_member // fromList_member //
sort_elem nub_elem.
Qed.
Theorem thm_DescList : toProp prop_DescList.
Proof.
rewrite /prop_DescList /= => xs POS_xs.
replace (toDescList (fromList xs)) with (reverse (toAscList (fromList xs)))
by by rewrite !hs_coq_reverse_rev toDescList_spec //; apply fromList_WF.
apply/Eq_eq; f_equal; apply/Eq_eq.
by apply thm_List.
Qed.
Theorem thm_AscDescList : toProp prop_AscDescList.
Proof.
rewrite /prop_AscDescList /= => xs POS_xs.
rewrite /toAscList toDescList_spec; last by apply fromList_WF.
by rewrite hs_coq_reverse_rev rev_involutive Eq_refl.
Qed.
(* SKIPPED: prop_fromList *)
(********************************************************************
Bin invariants
********************************************************************)
(* "Check the invariant that the mask is a power of 2." *)
Theorem thm_MaskPow2 : toProp prop_MaskPow2.
Proof.
(* We do `...; [|done|done]` and the next rewrite both together instead of
`//=` to avoid ever trying to simplify `powersOf2`, which would both
generate [0..63] *and do the exponentiation*. *)
simpl; elim=> [p m l IHl r IHr | p m | ] WFs; [|done|done].
rewrite /prop_MaskPow2 -/prop_MaskPow2.
move: (WFs) => /WF_Bin_children [WFl WFr].
apply/and3P; split; [| apply IHl, WFl | apply IHr, WFr].
rewrite /powersOf2 flat_map_cons_f; change @GHC.Base.map with @Coq.Lists.List.map.
rewrite fromList_member.
rewrite (lock enumFromTo).
apply/elemP; rewrite in_map_iff.
move: (valid_maskPowerOfTwo _ WFs) => /= /and3P [/Eq_eq/bitcount_0_1_power [i ->] _ _].
exists i; split => //.
admit. (* Unprovable *)
Abort.
(* "Check that the prefix satisfies its invariant." *)
Theorem thm_Prefix : toProp prop_Prefix.
Proof.
elim => [p m | p bm | ] //.
rewrite /prop_Prefix -/prop_Prefix /toList (lock toAscList) /= => l IHl r IHr WFs;
move: (WFs) => /WF_Bin_children [WFl WFr].
move: (WFs) => [fs SEMs];
inversion SEMs as [|s' [ps ms] fs' DESCs]; subst s' fs';
inversion DESCs as [|l' rng_l fl r' rng_r fr p' m' rng_s' fs'
DESCl DESCr POSrng subrange_l subrange_r def_p def_m def_fs];
subst p' m' l' r' rng_s' fs' p m.
apply/and3P; split; try by (apply IHl || apply IHr).
rewrite !Foldable_all_ssreflect. apply/allP => x MEM_x.
rewrite match_nomatch.
rewrite nomatch_spec.
move: MEM_x.
rewrite -(lock toAscList) in_elem toAscList_member // (member_Sem SEMs) => MEM_x.
rewrite negb_involutive.
rewrite def_fs in MEM_x. apply orb_true_iff in MEM_x. destruct MEM_x.
eapply inRange_isSubrange_true; only 2: eapply (Desc_inside DESCl); only 1: isSubrange_true; assumption.
eapply inRange_isSubrange_true; only 2: eapply (Desc_inside DESCr); only 1: isSubrange_true; assumption.
assumption.
Qed.
(* "Check that the left elements don't have the mask bit set, and the right ones
do." *)
Theorem thm_LeftRight : toProp prop_LeftRight.
Proof.
rewrite /prop_LeftRight /= => -[p m l r | // | // ] WFs; move: (WFs) => /WF_Bin_children [WFl WFr].
move: (WFs) => /valid_maskRespected /=.
move => /andP [mask_l mask_r]. move: mask_r.
move => /andP [mask_r _]. move: mask_l mask_r.
rewrite !Foldable_and_all !Foldable_all_ssreflect !flat_map_cons_f /zero /elems /toList.
move=> /allP /= mask_l /allP /= mask_r.
apply/andP; split; apply/allP => /= b /mapP [] /= x x_in {b}->; apply/Eq_eq.
- by move: (mask_l _ x_in) => /N.eqb_spec ->.
- move: (mask_r _ x_in) => /N.eqb_spec.
case: (WF_Bin_mask_power_N WFs) => [i ?]; subst m.
rewrite -N.shiftl_1_l => NEQ_bits.
apply N.bits_inj_iff => ix.
rewrite N.shiftl_1_l N.land_spec N.pow2_bits_eqb.
rewrite -> N.shiftl_1_l in NEQ_bits.
case: (N.eqb_spec i ix) => [? | NEQ]; first subst.
+ rewrite andb_true_r.
rewrite <- N_land_pow2_testbit.
rewrite negb_true_iff.
rewrite N.eqb_neq.
rewrite N.land_comm.
assumption.
+ apply andb_false_r.
Qed.
(********************************************************************
IntSet operations are like Set operations
********************************************************************)
(* "Check that IntSet.isProperSubsetOf is the same as Set.isProperSubsetOf." *)
Theorem thm_isProperSubsetOf : toProp prop_isProperSubsetOf.
Proof.
Abort.
(* "In the above test, isProperSubsetOf almost always returns False (since a
random set is almost never a subset of another random set). So this second
test checks the True case." *)
Theorem thm_isProperSubsetOf2 : toProp prop_isProperSubsetOf2.
Proof.
rewrite /prop_isProperSubsetOf2 /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
apply/Eq_eq/bool_eq_iff.
rewrite isProperSubsetOf_member //; split; first by intuition.
move=> s1_diff; split=> // k k_in_s1.
by rewrite union_member // k_in_s1 orTb.
Qed.
Theorem thm_isSubsetOf : toProp prop_isSubsetOf.
Proof.
rewrite /prop_isSubsetOf /= => s1 WF1 s2 WF2.
Abort.
Theorem thm_isSubsetOf2 : toProp prop_isSubsetOf2.
Proof.
rewrite /prop_isSubsetOf2 /= => s1 WF1 s2 WF2.
move: (union_WF _ _ WF1 WF2) => WF12.
rewrite isSubsetOf_member // => k.
by rewrite union_member // => ->; rewrite orTb.
Qed.
Theorem thm_size : toProp prop_size.
Proof.
rewrite /prop_size /= => s WF_s.
rewrite size_spec //.
split=> /=.
- change @foldl' with @foldl; rewrite foldl_spec //.
apply/Eq_eq.
generalize (toList s). intro xs.
rewrite <- fold_left_length.
replace (0%N) with (N.of_nat 0) by reflexivity.
generalize 0.
induction xs.
* reflexivity.
* intros. rewrite IHxs. cbn - [N.of_nat].
f_equal.
rewrite Nat2N.inj_succ.
Nomega.
- apply Eq_refl.
Qed.
(* SKIPPED: prop_findMax, prop_findMin *)
Theorem thm_ord : toProp prop_ord.
Proof.
rewrite /prop_ord /= => s1 WF1 s2 WF2.
apply Eq_refl.
Qed.
(* SKIPPED: prop_readShow *)
Theorem thm_foldR : toProp prop_foldR.
Proof.
rewrite /prop_foldR /= => s WF_s.
by rewrite Eq_refl.
Qed.
Theorem thm_foldR' : toProp prop_foldR'.
Proof.
rewrite /prop_foldR' /= => s WF_s.
by rewrite Eq_refl.
Qed.
Theorem thm_foldL : toProp prop_foldL.
Proof.
rewrite /prop_foldL /= => s WF_s.
by rewrite foldl_spec // -hs_coq_foldl_base Eq_refl.
Qed.
Theorem thm_foldL' : toProp prop_foldL'.
Proof.
rewrite /prop_foldL' /=; change @foldl' with @foldl; apply thm_foldL.
Qed.
Theorem thm_map : toProp prop_map.
Proof.
rewrite /prop_map /map /= => s WF_s.
rewrite map_id.
apply/eqIntSetMemberP=> //; first by apply fromList_WF.
move=> k.
by rewrite fromList_member // toList_member // Eq_refl.
Qed.
(* SKIPPED: prop_maxView, prop_minView *)
Theorem thm_split : toProp prop_split.
Proof.
rewrite /prop_split /= => s WF_ss x POS_x.
rewrite split_filter //.
have WF_lt: WF (filter (fun y => y < x) s) by apply filter_WF.
have WF_gt: WF (filter (fun y => y > x) s) by apply filter_WF.
have WF_del: WF (delete x s) by apply delete_WF.
move: (union_WF _ _ WF_lt WF_gt) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat split=> /=; try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/eqIntSetMemberP => // k.
rewrite delete_member // union_member // !filter_member //.
rewrite -andb_orr andbC; f_equal.
apply Ord_lt_gt_antisym.
Qed.
Theorem thm_splitMember : toProp prop_splitMember.
Proof.
rewrite /prop_splitMember /= => s WF_ss x POS_x.
rewrite splitMember_filter //.
have WF_lt: WF (filter (fun y => y < x) s) by apply filter_WF.
have WF_gt: WF (filter (fun y => y > x) s) by apply filter_WF.
have WF_del: WF (delete x s) by apply delete_WF.
move: (union_WF _ _ WF_lt WF_gt) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat split=> //=; try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP [].
- by apply Eq_refl.
- apply/eqIntSetMemberP => // k.
rewrite delete_member // union_member // !filter_member //.
rewrite -andb_orr andbC; f_equal.
apply Ord_lt_gt_antisym.
Qed.
Theorem thm_splitRoot : toProp prop_splitRoot.
Proof.
rewrite /prop_splitRoot /= => -[p m l r | p m | ] WFs //=.
- move: (WFs) => /WF_Bin_children [WFl WFr].
have WFlr: WF (union l r) by apply union_WF.
have WFrl: WF (union r l) by apply union_WF.
have: (m > 0%N). {
move: (WFs) => [fs SEMs];
inversion SEMs as [|s' [ps ms] fs' DESCs];
subst s' fs';
inversion DESCs as [|l' rng_l fl r' rng_r fr p' m' rng_s' fs'
DESCl DESCr POSrng subrange_l subrange_r def_p def_m def_fs];
subst p' m' l' r' rng_s' fs' p m.
unfold ">", Ord_Char___ => /=.
apply/N.ltb_spec0.
apply N_pow_pos_nonneg => //.
}
move=> /(Ord_gt_not_lt _ _)/negbTE ->.
rewrite /unions !hs_coq_foldl'_list /= !(union_eq empty) /=.
apply/andP; split.
+ apply null_list_none => -[x y] /in_flat_map [kl [/elemP IN_kl /in_flat_map [kr [/elemP IN_kr IN_xy]]]].
move: IN_kl IN_kr; rewrite !toList_member // => IN_kl IN_kr.
move: (Bin_left_lt_right WFs _ IN_kl _ IN_kr) IN_xy.
by move=> /(Ord_lt_not_gt _ _)/negbTE ->.
+ by apply/eqIntSetMemberP => // k; rewrite Bin_member // union_member //.
- apply/andP; split; by [elim: (foldrBits _ _ _ _) | apply/Eq_eq].
Qed.
Theorem thm_partition : toProp prop_partition.
Proof.
rewrite /prop_partition /= => s WF_s _ _.
rewrite partition_filter //.
have WF_odd: WF (filter GHC.Real.odd s) by apply filter_WF.
have WF_even: WF (filter (fun k => ~~ GHC.Real.odd k) s) by apply filter_WF.
move: (union_WF _ _ WF_odd WF_even) => WF_union.
rewrite !Foldable_all_ssreflect.
repeat (split=> /=); try by apply valid_correct.
- apply/allP=> /= k.
by rewrite in_elem toList_member // filter_member // => /andP[].
- apply/allP=> /= k.
rewrite in_elem toList_member // filter_member // => /andP[].
by rewrite /GHC.Real.odd negb_involutive.
- apply/eqIntSetMemberP=> // k.
rewrite union_member // !filter_member //.
by case: (member k s)=> //=; rewrite orb_negb_r.
Qed.
Theorem thm_filter : toProp prop_filter.
Proof.
rewrite /prop_filter /= => s WF_s _ _.
have WF_odd: WF (filter GHC.Real.odd s) by apply filter_WF.
have WF_even: WF (filter GHC.Real.even s) by apply filter_WF.
have WF_even': WF (filter (fun k => ~~ GHC.Real.odd k) s) by apply filter_WF.
move: (union_WF _ _ WF_odd WF_even) => WF_union.
repeat (split=> /=); try by apply valid_correct.
rewrite partition_filter //.
apply/andP; split; first by apply Eq_refl.
apply/eqIntSetMemberP=> // k.
rewrite !filter_member //.
by rewrite /GHC.Real.odd negb_involutive.
Qed.
(* SKIPPED: prop_bitcount *)
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
`define SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
/**
* o21a: 2-input OR into first input of 2-input AND.
*
* X = ((A1 | A2) & B1)
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hd__o21a (
X ,
A1 ,
A2 ,
B1 ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HD__O21A_PP_BLACKBOX_V
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision$
// $Date$
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module RevertReg(CLK, Q_OUT, D_IN, EN);
parameter width = 1;
parameter init = { width {1'b0} } ;
input CLK;
input EN;
input [width - 1 : 0] D_IN;
output [width - 1 : 0] Q_OUT;
assign Q_OUT = init;
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__XOR2_BLACKBOX_V
`define SKY130_FD_SC_MS__XOR2_BLACKBOX_V
/**
* xor2: 2-input exclusive OR.
*
* X = A ^ B
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__xor2 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__XOR2_BLACKBOX_V
|
//----------------------------------------------------------------------------
// Copyright (C) 2009 , Olivier Girard
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions
// are met:
// * Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// * Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution.
// * Neither the name of the authors nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
// OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
// THE POSSIBILITY OF SUCH DAMAGE
//
//----------------------------------------------------------------------------
//
// *File Name: omsp_watchdog.v
//
// *Module Description:
// Watchdog Timer
//
// *Author(s):
// - Olivier Girard, [email protected]
//
//----------------------------------------------------------------------------
// $Rev$
// $LastChangedBy$
// $LastChangedDate$
//----------------------------------------------------------------------------
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_defines.v"
`endif
module omsp_watchdog (
// OUTPUTs
per_dout, // Peripheral data output
wdt_irq, // Watchdog-timer interrupt
wdt_reset, // Watchdog-timer reset
wdt_wkup, // Watchdog Wakeup
wdtifg, // Watchdog-timer interrupt flag
wdtnmies, // Watchdog-timer NMI edge selection
// INPUTs
aclk, // ACLK
aclk_en, // ACLK enable
dbg_freeze, // Freeze Watchdog counter
mclk, // Main system clock
per_addr, // Peripheral address
per_din, // Peripheral data input
per_en, // Peripheral enable (high active)
per_we, // Peripheral write enable (high active)
por, // Power-on reset
puc_rst, // Main system reset
scan_enable, // Scan enable (active during scan shifting)
scan_mode, // Scan mode
smclk, // SMCLK
smclk_en, // SMCLK enable
wdtie, // Watchdog timer interrupt enable
wdtifg_irq_clr, // Watchdog-timer interrupt flag irq accepted clear
wdtifg_sw_clr, // Watchdog-timer interrupt flag software clear
wdtifg_sw_set // Watchdog-timer interrupt flag software set
);
// OUTPUTs
//=========
output [15:0] per_dout; // Peripheral data output
output wdt_irq; // Watchdog-timer interrupt
output wdt_reset; // Watchdog-timer reset
output wdt_wkup; // Watchdog Wakeup
output wdtifg; // Watchdog-timer interrupt flag
output wdtnmies; // Watchdog-timer NMI edge selection
// INPUTs
//=========
input aclk; // ACLK
input aclk_en; // ACLK enable
input dbg_freeze; // Freeze Watchdog counter
input mclk; // Main system clock
input [13:0] per_addr; // Peripheral address
input [15:0] per_din; // Peripheral data input
input per_en; // Peripheral enable (high active)
input [1:0] per_we; // Peripheral write enable (high active)
input por; // Power-on reset
input puc_rst; // Main system reset
input scan_enable; // Scan enable (active during scan shifting)
input scan_mode; // Scan mode
input smclk; // SMCLK
input smclk_en; // SMCLK enable
input wdtie; // Watchdog timer interrupt enable
input wdtifg_irq_clr; // Clear Watchdog-timer interrupt flag
input wdtifg_sw_clr; // Watchdog-timer interrupt flag software clear
input wdtifg_sw_set; // Watchdog-timer interrupt flag software set
//=============================================================================
// 1) PARAMETER DECLARATION
//=============================================================================
// Register base address (must be aligned to decoder bit width)
parameter [14:0] BASE_ADDR = 15'h0120;
// Decoder bit width (defines how many bits are considered for address decoding)
parameter DEC_WD = 2;
// Register addresses offset
parameter [DEC_WD-1:0] WDTCTL = 'h0;
// Register one-hot decoder utilities
parameter DEC_SZ = (1 << DEC_WD);
parameter [DEC_SZ-1:0] BASE_REG = {{DEC_SZ-1{1'b0}}, 1'b1};
// Register one-hot decoder
parameter [DEC_SZ-1:0] WDTCTL_D = (BASE_REG << WDTCTL);
//============================================================================
// 2) REGISTER DECODER
//============================================================================
// Local register selection
wire reg_sel = per_en & (per_addr[13:DEC_WD-1]==BASE_ADDR[14:DEC_WD]);
// Register local address
wire [DEC_WD-1:0] reg_addr = {per_addr[DEC_WD-2:0], 1'b0};
// Register address decode
wire [DEC_SZ-1:0] reg_dec = (WDTCTL_D & {DEC_SZ{(reg_addr==WDTCTL)}});
// Read/Write probes
wire reg_write = |per_we & reg_sel;
wire reg_read = ~|per_we & reg_sel;
// Read/Write vectors
wire [DEC_SZ-1:0] reg_wr = reg_dec & {DEC_SZ{reg_write}};
wire [DEC_SZ-1:0] reg_rd = reg_dec & {DEC_SZ{reg_read}};
//============================================================================
// 3) REGISTERS
//============================================================================
// WDTCTL Register
//-----------------
// WDTNMI is not implemented and therefore masked
reg [7:0] wdtctl;
wire wdtctl_wr = reg_wr[WDTCTL];
`ifdef CLOCK_GATING
wire mclk_wdtctl;
omsp_clock_gate clock_gate_wdtctl (.gclk(mclk_wdtctl),
.clk (mclk), .enable(wdtctl_wr), .scan_enable(scan_enable));
`else
wire UNUSED_scan_enable = scan_enable;
wire mclk_wdtctl = mclk;
`endif
`ifdef NMI
parameter [7:0] WDTNMIES_MASK = 8'h40;
`else
parameter [7:0] WDTNMIES_MASK = 8'h00;
`endif
`ifdef ASIC_CLOCKING
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_MASK = 8'h04;
`else
parameter [7:0] WDTSSEL_MASK = 8'h00;
`endif
`else
parameter [7:0] WDTSSEL_MASK = 8'h04;
`endif
parameter [7:0] WDTCTL_MASK = (8'b1001_0011 | WDTSSEL_MASK | WDTNMIES_MASK);
always @ (posedge mclk_wdtctl or posedge puc_rst)
if (puc_rst) wdtctl <= 8'h00;
`ifdef CLOCK_GATING
else wdtctl <= per_din[7:0] & WDTCTL_MASK;
`else
else if (wdtctl_wr) wdtctl <= per_din[7:0] & WDTCTL_MASK;
`endif
wire wdtpw_error = wdtctl_wr & (per_din[15:8]!=8'h5a);
wire wdttmsel = wdtctl[4];
wire wdtnmies = wdtctl[6];
//============================================================================
// 4) DATA OUTPUT GENERATION
//============================================================================
`ifdef NMI
parameter [7:0] WDTNMI_RD_MASK = 8'h20;
`else
parameter [7:0] WDTNMI_RD_MASK = 8'h00;
`endif
`ifdef WATCHDOG_MUX
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
`else
`ifdef WATCHDOG_NOMUX_ACLK
parameter [7:0] WDTSSEL_RD_MASK = 8'h04;
`else
parameter [7:0] WDTSSEL_RD_MASK = 8'h00;
`endif
`endif
parameter [7:0] WDTCTL_RD_MASK = WDTNMI_RD_MASK | WDTSSEL_RD_MASK;
// Data output mux
wire [15:0] wdtctl_rd = {8'h69, wdtctl | WDTCTL_RD_MASK} & {16{reg_rd[WDTCTL]}};
wire [15:0] per_dout = wdtctl_rd;
//=============================================================================
// 5) WATCHDOG TIMER (ASIC IMPLEMENTATION)
//=============================================================================
`ifdef ASIC_CLOCKING
// Watchdog clock source selection
//---------------------------------
wire wdt_clk;
`ifdef WATCHDOG_MUX
omsp_clock_mux clock_mux_watchdog (
.clk_out (wdt_clk),
.clk_in0 (smclk),
.clk_in1 (aclk),
.reset (puc_rst),
.scan_mode (scan_mode),
.select_in (wdtctl[2])
);
`else
`ifdef WATCHDOG_NOMUX_ACLK
assign wdt_clk = aclk;
wire UNUSED_smclk = smclk;
`else
wire UNUSED_aclk = aclk;
assign wdt_clk = smclk;
`endif
`endif
// Reset synchronizer for the watchdog local clock domain
//--------------------------------------------------------
wire wdt_rst_noscan;
wire wdt_rst;
// Reset Synchronizer
omsp_sync_reset sync_reset_por (
.rst_s (wdt_rst_noscan),
.clk (wdt_clk),
.rst_a (puc_rst)
);
// Scan Reset Mux
omsp_scan_mux scan_mux_wdt_rst (
.scan_mode (scan_mode),
.data_in_scan (puc_rst),
.data_in_func (wdt_rst_noscan),
.data_out (wdt_rst)
);
// Watchog counter clear (synchronization)
//-----------------------------------------
// Toggle bit whenever the watchog needs to be cleared
reg wdtcnt_clr_toggle;
wire wdtcnt_clr_detect = (wdtctl_wr & per_din[3]);
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtcnt_clr_toggle <= 1'b0;
else if (wdtcnt_clr_detect) wdtcnt_clr_toggle <= ~wdtcnt_clr_toggle;
// Synchronization
wire wdtcnt_clr_sync;
omsp_sync_cell sync_cell_wdtcnt_clr (
.data_out (wdtcnt_clr_sync),
.data_in (wdtcnt_clr_toggle),
.clk (wdt_clk),
.rst (wdt_rst)
);
// Edge detection
reg wdtcnt_clr_sync_dly;
always @ (posedge wdt_clk or posedge wdt_rst)
if (wdt_rst) wdtcnt_clr_sync_dly <= 1'b0;
else wdtcnt_clr_sync_dly <= wdtcnt_clr_sync;
wire wdtqn_edge;
wire wdtcnt_clr = (wdtcnt_clr_sync ^ wdtcnt_clr_sync_dly) | wdtqn_edge;
// Watchog counter increment (synchronization)
//----------------------------------------------
wire wdtcnt_incr;
omsp_sync_cell sync_cell_wdtcnt_incr (
.data_out (wdtcnt_incr),
.data_in (~wdtctl[7] & ~dbg_freeze),
.clk (wdt_clk),
.rst (wdt_rst)
);
// Watchdog 16 bit counter
//--------------------------
reg [15:0] wdtcnt;
wire [15:0] wdtcnt_nxt = wdtcnt+16'h0001;
`ifdef CLOCK_GATING
wire wdtcnt_en = wdtcnt_clr | wdtcnt_incr;
wire wdt_clk_cnt;
omsp_clock_gate clock_gate_wdtcnt (.gclk(wdt_clk_cnt),
.clk (wdt_clk), .enable(wdtcnt_en), .scan_enable(scan_enable));
`else
wire wdt_clk_cnt = wdt_clk;
`endif
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdtcnt <= 16'h0000;
else if (wdtcnt_clr) wdtcnt <= 16'h0000;
`ifdef CLOCK_GATING
else wdtcnt <= wdtcnt_nxt;
`else
else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
`endif
// Local synchronizer for the wdtctl.WDTISx
// configuration (note that we can live with
// a full bus synchronizer as it won't hurt
// if we get a wrong WDTISx value for a
// single clock cycle)
//--------------------------------------------
reg [1:0] wdtisx_s;
reg [1:0] wdtisx_ss;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst)
begin
wdtisx_s <= 2'h0;
wdtisx_ss <= 2'h0;
end
else
begin
wdtisx_s <= wdtctl[1:0];
wdtisx_ss <= wdtisx_s;
end
// Interval selection mux
//--------------------------
reg wdtqn;
always @(wdtisx_ss or wdtcnt_nxt)
case(wdtisx_ss)
2'b00 : wdtqn = wdtcnt_nxt[15];
2'b01 : wdtqn = wdtcnt_nxt[13];
2'b10 : wdtqn = wdtcnt_nxt[9];
default: wdtqn = wdtcnt_nxt[6];
endcase
// Watchdog event detection
//-----------------------------
// Interval end detection
assign wdtqn_edge = (wdtqn & wdtcnt_incr);
// Toggle bit for the transmition to the MCLK domain
reg wdt_evt_toggle;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdt_evt_toggle <= 1'b0;
else if (wdtqn_edge) wdt_evt_toggle <= ~wdt_evt_toggle;
// Synchronize in the MCLK domain
wire wdt_evt_toggle_sync;
omsp_sync_cell sync_cell_wdt_evt (
.data_out (wdt_evt_toggle_sync),
.data_in (wdt_evt_toggle),
.clk (mclk),
.rst (puc_rst)
);
// Delay for edge detection of the toggle bit
reg wdt_evt_toggle_sync_dly;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdt_evt_toggle_sync_dly <= 1'b0;
else wdt_evt_toggle_sync_dly <= wdt_evt_toggle_sync;
wire wdtifg_evt = (wdt_evt_toggle_sync_dly ^ wdt_evt_toggle_sync) | wdtpw_error;
// Watchdog wakeup generation
//-------------------------------------------------------------
// Clear wakeup when the watchdog flag is cleared (glitch free)
reg wdtifg_clr_reg;
wire wdtifg_clr;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtifg_clr_reg <= 1'b1;
else wdtifg_clr_reg <= wdtifg_clr;
// Set wakeup when the watchdog event is detected (glitch free)
reg wdtqn_edge_reg;
always @ (posedge wdt_clk_cnt or posedge wdt_rst)
if (wdt_rst) wdtqn_edge_reg <= 1'b0;
else wdtqn_edge_reg <= wdtqn_edge;
// Watchdog wakeup cell
wire wdt_wkup_pre;
omsp_wakeup_cell wakeup_cell_wdog (
.wkup_out (wdt_wkup_pre), // Wakup signal (asynchronous)
.scan_clk (mclk), // Scan clock
.scan_mode (scan_mode), // Scan mode
.scan_rst (puc_rst), // Scan reset
.wkup_clear (wdtifg_clr_reg), // Glitch free wakeup event clear
.wkup_event (wdtqn_edge_reg) // Glitch free asynchronous wakeup event
);
// When not in HOLD, the watchdog can generate a wakeup when:
// - in interval mode (if interrupts are enabled)
// - in reset mode (always)
reg wdt_wkup_en;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdt_wkup_en <= 1'b0;
else wdt_wkup_en <= ~wdtctl[7] & (~wdttmsel | (wdttmsel & wdtie));
// Make wakeup when not enabled
wire wdt_wkup;
omsp_and_gate and_wdt_wkup (.y(wdt_wkup), .a(wdt_wkup_pre), .b(wdt_wkup_en));
// Watchdog interrupt flag
//------------------------------
reg wdtifg;
wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
assign wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1'b0;
else if (wdtifg_set) wdtifg <= 1'b1;
else if (wdtifg_clr) wdtifg <= 1'b0;
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
// LINT cleanup
wire UNUSED_smclk_en = smclk_en;
wire UNUSED_aclk_en = aclk_en;
//=============================================================================
// 6) WATCHDOG TIMER (FPGA IMPLEMENTATION)
//=============================================================================
`else
// Watchdog clock source selection
//---------------------------------
wire clk_src_en = wdtctl[2] ? aclk_en : smclk_en;
// Watchdog 16 bit counter
//--------------------------
reg [15:0] wdtcnt;
wire wdtifg_evt;
wire wdtcnt_clr = (wdtctl_wr & per_din[3]) | wdtifg_evt;
wire wdtcnt_incr = ~wdtctl[7] & clk_src_en & ~dbg_freeze;
wire [15:0] wdtcnt_nxt = wdtcnt+16'h0001;
always @ (posedge mclk or posedge puc_rst)
if (puc_rst) wdtcnt <= 16'h0000;
else if (wdtcnt_clr) wdtcnt <= 16'h0000;
else if (wdtcnt_incr) wdtcnt <= wdtcnt_nxt;
// Interval selection mux
//--------------------------
reg wdtqn;
always @(wdtctl or wdtcnt_nxt)
case(wdtctl[1:0])
2'b00 : wdtqn = wdtcnt_nxt[15];
2'b01 : wdtqn = wdtcnt_nxt[13];
2'b10 : wdtqn = wdtcnt_nxt[9];
default: wdtqn = wdtcnt_nxt[6];
endcase
// Watchdog event detection
//-----------------------------
assign wdtifg_evt = (wdtqn & wdtcnt_incr) | wdtpw_error;
// Watchdog interrupt flag
//------------------------------
reg wdtifg;
wire wdtifg_set = wdtifg_evt | wdtifg_sw_set;
wire wdtifg_clr = (wdtifg_irq_clr & wdttmsel) | wdtifg_sw_clr;
always @ (posedge mclk or posedge por)
if (por) wdtifg <= 1'b0;
else if (wdtifg_set) wdtifg <= 1'b1;
else if (wdtifg_clr) wdtifg <= 1'b0;
// Watchdog interrupt generation
//---------------------------------
wire wdt_irq = wdttmsel & wdtifg & wdtie;
wire wdt_wkup = 1'b0;
// Watchdog reset generation
//-----------------------------
reg wdt_reset;
always @ (posedge mclk or posedge por)
if (por) wdt_reset <= 1'b0;
else wdt_reset <= wdtpw_error | (wdtifg_set & ~wdttmsel);
// LINT cleanup
wire UNUSED_scan_mode = scan_mode;
wire UNUSED_smclk = smclk;
wire UNUSED_aclk = aclk;
`endif
wire [15:0] UNUSED_per_din = per_din;
endmodule // omsp_watchdog
`ifdef OMSP_NO_INCLUDE
`else
`include "openMSP430_undefines.v"
`endif
|
// DESCRIPTION: Verilator: Verilog Test module
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
reg [2*32-1:0] w2; initial w2 = {2 {32'h12345678}};
reg [9*32-1:0] w9; initial w9 = {9 {32'h12345678}};
reg [10*32-1:0] w10; initial w10 = {10{32'h12345678}};
reg [11*32-1:0] w11; initial w11 = {11{32'h12345678}};
reg [15*32-1:0] w15; initial w15 = {15{32'h12345678}};
reg [31*32-1:0] w31; initial w31 = {31{32'h12345678}};
reg [47*32-1:0] w47; initial w47 = {47{32'h12345678}};
reg [63*32-1:0] w63; initial w63 = {63{32'h12345678}};
// Aggregate outputs into a single result vector
wire [63:0] result = (w2[63:0]
^ w9[64:1]
^ w10[65:2]
^ w11[66:3]
^ w15[67:4]
^ w31[68:5]
^ w47[69:6]
^ w63[70:7]);
// What checksum will we end up with
`define EXPECTED_SUM 64'h184cb39122d8c6e3
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
w2 <= w2 >> 1;
w9 <= w9 >> 1;
w10 <= w10 >> 1;
w11 <= w11 >> 1;
w15 <= w15 >> 1;
w31 <= w31 >> 1;
w47 <= w47 >> 1;
w63 <= w63 >> 1;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
`define SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
/**
* o22ai: 2-input OR into both inputs of 2-input NAND.
*
* Y = !((A1 | A2) & (B1 | B2))
*
* Verilog stub (with power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_ms__o22ai (
//# {{data|Data Signals}}
input A1 ,
input A2 ,
input B1 ,
input B2 ,
output Y ,
//# {{power|Power}}
input VPB ,
input VPWR,
input VGND,
input VNB
);
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__O22AI_PP_SYMBOL_V
|
//Com2DocHDL
/*
:Project
FPGA-Imaging-Library
:Design
ThresholdLocal
:Function
Local thresholding by Threshold from filters.
It will give the first output after 1 cycle while the tow input both enable.
ref_enable must enable after in_enable !
:Module
Main module
:Version
1.0
:Modified
2015-05-22
Copyright (C) 2015 Tianyu Dai (dtysky) <[email protected]>
This library is free software; you can redistribute it and/or
modify it under the terms of the GNU Lesser General Public
License as published by the Free Software Foundation; either
version 2.1 of the License, or (at your option) any later version.
This library is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
Lesser General Public License for more details.
You should have received a copy of the GNU Lesser General Public
License along with this library; if not, write to the Free Software
Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
Homepage for this project:
http://fil.dtysky.moe
Sources for this project:
https://github.com/dtysky/FPGA-Imaging-Library
My e-mail:
[email protected]
My blog:
http://dtysky.moe
*/
`timescale 1ns / 1ps
module ThresholdLocal(
clk,
rst_n,
in_enable,
in_data,
ref_enable,
ref_data,
out_ready,
out_data);
/*
::description
This module's working mode.
::range
0 for Pipline, 1 for Req-ack
*/
parameter[0 : 0] work_mode = 0;
/*
::description
The width(and height) of input window, if input is not a window, set it to 1.
::range
1 - 15
*/
parameter[3 : 0] in_window_width = 1;
/*
::description
Color's bit width.
::range
1 - 12
*/
parameter[3 : 0] color_width = 8;
/*
::description
The possible max cycles from in_enable to ref_enable.
*/
parameter max_delay = 8;
/*
::description
Width bits of max delay.
::range
Depend on max delay
*/
parameter max_delay_bits = 4;
/*
::description
Clock.
*/
input clk;
/*
::description
Reset, active low.
*/
input rst_n;
/*
::description
Filter's rank, if half of full size of window, this module working as median filter, etc.
*/
input in_enable;
/*
::description
Input data, it must be synchronous with in_enable.
*/
input [color_width * in_window_width * in_window_width - 1 : 0] in_data;
/*
::description
Threshold enable.
*/
input ref_enable;
/*
::description
Threshold, used as threshold for thresholding, it must be synchronous with ref_enable.
*/
input[color_width - 1 : 0] ref_data;
/*
::description
Output data ready, in both two mode, it will be high while the out_data can be read.
*/
output out_ready;
/*
::description
Output data, it will be synchronous with out_ready.
*/
output out_data;
reg reg_out_ready;
reg reg_out_data;
reg[max_delay_bits - 1 : 0] con_out;
genvar i, j;
generate
if(work_mode == 0) begin
reg[color_width - 1 : 0] buffer[0 : max_delay - 1];
wire[max_delay - 1 : 0] res;
always @(posedge clk or negedge rst_n or negedge in_enable) begin
if(~rst_n || ~in_enable)
con_out <= 0;
else if(con_out == max_delay)
con_out <= con_out;
else if(~ref_enable)
con_out <= con_out + 1;
else
con_out <= con_out;
end
always @(posedge clk or negedge rst_n or negedge ref_enable) begin
if(~rst_n || ~ref_enable) begin
reg_out_ready <= 0;
reg_out_data <= 0;
end else begin
reg_out_ready <= 1;
reg_out_data <= res[con_out - 1];
end
end
for (i = 0; i < max_delay; i = i + 1) begin
if(i == 0) begin
always @(posedge clk)
buffer[i] <= in_data[((in_window_width * in_window_width >> 1) + 1) * color_width - 1 : (in_window_width * in_window_width >> 1) * color_width];
end else begin
always @(posedge clk)
buffer[i] <= buffer[i - 1];
end
assign res[i] = buffer[i] < ref_data ? 0 : 1;
end
end else begin
always @(posedge clk or negedge rst_n or negedge ref_enable) begin
if(~rst_n || ~ref_enable) begin
reg_out_ready <= 0;
reg_out_data <= 0;
end else begin
reg_out_ready <= 1;
reg_out_data <= in_data < ref_data ? 0 : 1;
end
end
end
assign out_ready = reg_out_ready;
assign out_data = reg_out_data;
endgenerate
endmodule |
(* begin hide *)
Require Export HoTT Ch02.
(* end hide *)
(** printing <~> %\ensuremath{\eqvsym}% **)
(** printing == %\ensuremath{\sim}% **)
(** printing ^-1 %\ensuremath{^{-1}}% **)
(** * Sets and logic *)
Notation Brck Q := (merely Q).
(** %\exerdone{3.1}{127}%
Prove that if $A \eqvsym B$ and $A$ is a set, then so is $B$.
*)
(** %\soln%
Suppose that $A \eqvsym B$ and that $A$ is a set. Since $A$ is a set, $x =_{A}
y$ is a mere proposition. And since $A \eqvsym B$, this means that $x =_{B} y$
is a mere proposition, hence that $B$ is a set.
Alternatively, we can unravel some definitions. By assumption we have $f : A
\eqvsym B$ and
%\[
g : \isset(A) \equiv \prd{x, y:A}\prd{p,q : x=y} (p = q)
\]%
Now suppose that $x, y : B$ and $p, q : x = y$. Then $f^{-1}(x),
f^{-1}(y) : A$ and $f^{-1}(p), f^{-1}(q) : f^{-1}(x) =
f^{-1}(y)$, so
%\[
f\!\left(g(f^{-1}(x), f^{-1}(y), f^{-1}(p), f^{-1}(q))\right)
:
f(f^{-1}(p)) = f(f^{-1}(q))
\]%
Since $f^{-1}$ is a quasi-inverse of $f$, we have the homotopy $\alpha :
\prd{a:A} (f(f^{-1}(a)) = a)$, thus
%\[
\alpha_{x}^{-1} \ct
f\!\left(g(f^{-1}(x), f^{-1}(y), f^{-1}(p), f^{-1}(q))\right)
\ct \alpha_{y}
:
p = q
\]%
So we've constructed an element of
%\[
\isset(B) : \prd{x, y : B} \prd{p, q : x = y} (p = q)
\]%
*)
Theorem ex3_1 (A B : Type) `{Univalence} : A <~> B -> IsHSet A -> IsHSet B.
Proof.
intros f g.
apply equiv_path_universe in f.
rewrite <- f.
apply g.
Defined.
Theorem ex3_1' (A B : Type) : A <~> B -> IsHSet A -> IsHSet B.
Proof.
intros f g x y.
apply hprop_allpath. intros p q.
assert (ap f^-1 p = ap f^-1 q). apply g.
apply ((ap (ap f^-1))^-1 X).
Defined.
(** %\exerdone{3.2}{127}%
Prove that if $A$ and $B$ are sets, then so is $A + B$.
*)
(** %\soln%
Suppose that $A$ and $B$ are sets. Then for all $a, a' : A$ and $b, b': B$, $a
= a'$ and $b = b'$ are contractible. Given the characterization of the path
space of $A+B$ in \S2.12, it must also be contractible. Hence $A + B$ is a
set.
More explicitly, suppose that $z, z' : A + B$ and $p, q : z = z'$. By
induction, there are four cases.
- $z \equiv \inl(a)$ and $z' \equiv \inl(a')$. Then $(z = z') \eqvsym (a = a')$, and since $A$ is a set, $a = a'$ is contractible, so $(z = z')$ is as well.
- $z \equiv \inl(a)$ and $z' \equiv \inr(b)$. Then $(z = z') \eqvsym \emptyt$, so $p$ is a contradiction.
- $z \equiv \inr(b)$ and $z' \equiv \inl(a)$. Then $(z = z') \eqvsym \emptyt$, so $p$ is a contradiction.
- $z \equiv \inr(b)$ and $z' \equiv \inr(b')$. Then $(z = z') \eqvsym (b = b')$, and since $B$ is a set, this type is contractible.
So $z = z'$ is contractible, making $A + B$ a set.
*)
Theorem ex3_2 (A B : Type) : IsHSet A -> IsHSet B -> IsHSet (A + B).
Proof.
intros f g.
intros z z'. apply hprop_allpath. intros p q.
assert ((path_sum z z')^-1 p = (path_sum z z')^-1 q).
pose proof ((path_sum z z')^-1 p).
destruct z as [a | b], z' as [a' | b'].
apply f. contradiction. contradiction. apply g.
apply ((ap (path_sum z z')^-1)^-1 X).
Defined.
(** %\exerdone{3.3}{127}%
Prove that if $A$ is a set and $B : A \to \UU$ is a type family such that
$B(x)$ is a set for all $x:A$, then $\sm{x:A}B(x)$ is a set.
*)
(** %\soln%
At this point the pattern in these proofs is relatively obvious: show
that the path space of the combined types is determined by the path
spaces of the base types, and then apply the fact that the base types
are sets. So here we suppose that $w w' : \sm{x:A} B(x)$, and that $p
q : (w = w')$. Now
%\[
(w = w') \eqvsym \sm{p : \fst(w) = \fst(w')} p_{*}(\snd(w)) = \snd(w')
\]%
by Theorem 2.7.2. Since $A$ is a set, $\fst(w) = \fst(w')$ is
contractible, so $(w = w') \eqvsym ((\refl{\fst(w)})_{*}(\snd(w)) =
\snd(w')) \equiv (\snd(w) = \snd(w'))$ by Lemma 3.11.9. And since $B$
is a set, this too is contractible, making $w = w'$ contractible and
$\sm{x:A} B(x)$ a set.
*)
Theorem ex3_3 (A : Type) (B : A -> Type) :
IsHSet A -> (forall x:A, IsHSet (B x)) -> IsHSet {x : A & B x}.
Proof.
intros f g.
intros w w'. apply hprop_allpath. intros p q.
assert ((path_sigma_uncurried B w w')^-1 p = (path_sigma_uncurried B w w')^-1 q).
apply path_sigma_uncurried. simpl.
assert (p..1 = q..1). apply f. exists X. apply (g w'.1).
apply ((ap (path_sigma_uncurried B w w')^-1)^-1 X).
Defined.
(** %\exerdone{3.4}{127}%
Show that $A$ is a mere proposition if and only if $A \to A$ is contractible.
*)
(** %\soln%
For the forward direction, suppose that $A$ is a mere proposition. Then by
Example 3.6.2, $A \to A$ is a mere proposition. We also have $\idfunc{A} : A
\to A$ when $A$ is inhabited and $! : A \to A$ when it's not, so $A \to A$ is
contractible.
For the other direction, suppose that $A \to A$ is contractible and that $x y :
A$. We have the functions $z \mapsto x$ and $z \mapsto y$, and since $A \to A$
is contractible these functions are equal. $\happly$ then gives $x = y$, so
$A$ is a mere proposition.
*)
Theorem ex3_4 `{Funext} (A : Type) : IsHProp A <-> Contr (A -> A).
Proof.
split; intro H'.
(* forward *)
exists idmap; intro f.
apply path_forall; intro x. apply H'.
(* backward *)
apply hprop_allpath; intros x y.
assert ((fun z:A => x) = (fun z:A => y)).
destruct H'. transitivity center.
apply (contr (fun _ => x))^. apply (contr (fun _ : A => y)).
apply (apD10 X x).
Defined.
(** %\exerdone{3.5}{127}%
Show that $\isprop(A) \eqvsym (A \to \iscontr(A))$.
*)
(** %\soln%
Lemma 3.3.3 gives us maps $\isprop(A) \to (A \to \iscontr(A))$ and $(A
\to \iscontr(A)) \to \isprop(A)$. Note that $\iscontr(A)$ is a mere
proposition, so $A \to \iscontr(A)$ is as well. $\isprop(A)$ is
always a mere proposition, so by Lemma 3.3.3 we have the equivalence.
*)
Module Ex5.
Theorem equiv_hprop_inhabited_contr `{Funext} (A : Type)
: IsHProp A <~> (A -> Contr A).
Proof.
apply equiv_iff_hprop.
apply contr_inhabited_hprop.
apply hprop_inhabited_contr.
Defined.
End Ex5.
(** %\exerdone{3.6}{127}%
Show that if $A$ is a mere proposition, then so is $A + (\lnot A)$.
*)
(** %\soln%
Suppose that $A$ is a mere proposition, and that $x, y : A + (\lnot A)$. By a
case analysis, we have
- $x = \inl(a)$ and $y = \inl(a')$. Then $(x = y) \eqvsym (a = a')$, and $A$ is a mere proposition, so this holds.
- $x = \inl(a)$ and $y = \inr(f)$. Then $f(a) : \emptyt$, a contradiction.
- $x = \inr(f)$ and $y = \inl(a)$. Then $f(a) : \emptyt$, a contradiction.
- $x = \inr(f)$ and $y = \inr(f')$. Then $(x = y) \eqvsym (f = f')$, and $\lnot A$ is a mere proposition, so this holds.
*)
Theorem ex3_6 `{Funext} {A} : IsHProp A -> IsHProp (A + ~A).
Proof.
intro H'.
assert (IsHProp (~A)) as H''.
apply hprop_allpath. intros f f'. apply path_forall; intro x. contradiction.
apply hprop_allpath. intros x y.
destruct x as [a | f], y as [a' | f'].
apply (ap inl). apply H'.
contradiction.
contradiction.
apply (ap inr). apply H''.
Defined.
(** %\exerdone{3.7}{127}%
More generally, show that if $A$ and $B$ are mere propositions and $\lnot (A
\times B)$, then $A + B$ is also a mere proposition.
*)
(** %\soln%
Suppose that $A$ and $B$ are mere propositions with $f : \lnot (A \times B)$,
and let $x, y : A + B$. Then we have cases:
- $x = \inl(a)$ and $y = \inl(a')$. Then $(x = y) \eqvsym (a = a')$, and $A$ is a mere proposition, so this holds.
- $x = \inl(a)$ and $y = \inr(b)$. Then $f(a, b) : \emptyt$, a contradiction.
- $x = \inr(b)$ and $y = \inl(a)$. Then $f(a, b) : \emptyt$, a contradiction.
- $x = \inr(b)$ and $y = \inr(b')$. Then $(x = y) \eqvsym (b = b')$, and $B$ is a mere proposition, so this holds.
*)
Theorem ex3_7 {A B} : IsHProp A -> IsHProp B -> ~(A * B) -> IsHProp (A+B).
Proof.
intros HA HB f.
apply hprop_allpath; intros x y.
destruct x as [a | b], y as [a' | b'].
apply (ap inl). apply HA.
assert Empty. apply (f (a, b')). contradiction.
assert Empty. apply (f (a', b)). contradiction.
apply (ap inr). apply HB.
Defined.
(** %\exerdone{3.8}{127}%
Assuming that some type $\isequiv(f)$ satisfies
%\begin{itemize}
\item[(i)] For each $f : A \to B$, there is a function $\qinv(f) \to \isequiv(f)$;
\item[(ii)] For each $f$ we have $\isequiv(f) \to \qinv(f)$;
\item[(iii)] For any two $e_{1}, e_{2} : \isequiv(f)$ we have $e_{1} = e_{2}$,
\end{itemize}%
show that the type $\brck{\qinv(f)}$ satisfies the same conditions and is
equivalent to $\isequiv(f)$.
*)
(** %\soln%
Suppose that $f : A \to B$. There is a function $\qinv(f) \to \brck{\qinv(f)}$
by definition. Since $\isequiv(f)$ is a mere proposition (by iii), the
recursion principle for $\brck{\qinv(f)}$ gives a map $\brck{\qinv(f)} \to
\isequiv(f)$, which we compose with the map from (ii) to give a map
$\brck{\qinv(f)} \to \qinv(f)$. Finally, $\brck{\qinv(f)}$ is a mere
proposition by construction. Since $\brck{\qinv(f)}$ and $\isequiv(f)$ are
both mere propositions and logically equivalent, $\brck{\qinv(f)} \eqvsym
\isequiv(f)$ by Lemma 3.3.3.
*)
Section Exercise3_8.
Variables (E Q : Type).
Hypothesis H1 : Q -> E.
Hypothesis H2 : E -> Q.
Hypothesis H3 : forall e e' : E, e = e'.
Definition ex3_8_i : Q -> (Brck Q) := tr.
Definition ex3_8_ii : (Brck Q) -> Q.
intro q. apply H2. apply (@Trunc_ind -1 Q).
intro q'. apply hprop_allpath. apply H3.
apply H1. apply q.
Defined.
Theorem ex3_8_iii : forall q q' : Brck Q, q = q'.
apply path_ishprop.
Defined.
Theorem ex3_8_iv : (Brck Q) <~> E.
apply @equiv_iff_hprop.
apply hprop_allpath. apply ex3_8_iii.
apply hprop_allpath. apply H3.
apply (H1 o ex3_8_ii).
apply (ex3_8_i o H2).
Defined.
End Exercise3_8.
(** %\exerdone{3.9}{127}%
Show that if $\LEM{}$ holds, then the type $\prop \defeq \sm{A:\UU}\isprop(A)$
is equivalent to $\bool$.
*)
(** %\soln%
Suppose that
%\[
f : \prd{A:\UU}\left(\isprop(A) \to (A + \lnot A)\right)
\]%
To construct a map $\prop \to \bool$, it suffices to consider an element of the
form $(A, g)$, where $g : \isprop(A)$. Then $f(g) : A + \lnot A$, so we have
two cases:
- $f(g) \equiv \inl(a)$, in which case we send it to $1_{\bool}$, or
- $f(g) \equiv \inr(a)$, in which case we send it to $0_{\bool}$.
To go the other way, note that $\LEM{}$ splits $\prop$ into two equivalence
classes (basically, the true and false propositions), and $\unit$ and $\emptyt$
are in different classes. Univalence quotients out these classes, leaving us
with two elements. We'll use $\unit$ and $\emptyt$ as representatives, so we
send $0_{\bool}$ to $\emptyt$ and $1_{\bool}$ to $\unit$.
Coq has some trouble with the universes here, so we have to specify that we want [(Unit : Type)] and [(Empty : Type)]; otherwise we get the [Type0] versions.
*)
Section Exercise3_9.
Hypothesis LEM : forall (A : Type), IsHProp A -> (A + ~A).
Definition ex3_9_f (P : {A:Type & IsHProp A}) : Bool :=
match (LEM P.1 P.2) with
| inl a => true
| inr a' => false
end.
Lemma hprop_Unit : IsHProp (Unit : Type).
apply hprop_inhabited_contr. intro u. apply contr_unit.
Defined.
Definition ex3_9_inv (b : Bool) : {A : Type & IsHProp A} :=
match b with
| true => @existT Type IsHProp (Unit : Type) hprop_Unit
| false => @existT Type IsHProp (Empty : Type) hprop_Empty
end.
Theorem ex3_9 `{Univalence} : {A : Type & IsHProp A} <~> Bool.
Proof.
refine (equiv_adjointify ex3_9_f ex3_9_inv _ _).
intro b. unfold ex3_9_f, ex3_9_inv.
destruct b.
simpl. destruct (LEM (Unit:Type) hprop_Unit).
reflexivity.
contradiction n. exact tt.
simpl. destruct (LEM (Empty:Type) hprop_Empty).
contradiction. reflexivity.
intro w. destruct w as [A p]. unfold ex3_9_f, ex3_9_inv.
simpl. destruct (LEM A p) as [x | x].
apply path_sigma_uncurried. simpl.
assert ((Unit:Type) = A).
assert (Contr A). apply contr_inhabited_hprop. apply p. apply x.
apply equiv_path_universe. apply equiv_inverse. apply equiv_contr_unit.
exists X. induction X. simpl.
assert (IsHProp (IsHProp (Unit:Type))).
typeclasses eauto. apply X.
apply path_sigma_uncurried. simpl.
assert ((Empty:Type) = A).
apply equiv_path_universe. apply equiv_iff_hprop.
intro z. contradiction.
intro a. contradiction.
exists X. induction X. simpl.
assert (IsHProp (IsHProp (Empty:Type))).
typeclasses eauto. apply X.
Defined.
End Exercise3_9.
(** %\exerdone{3.10}{127}%
Show that if $\UU_{i+1}$ satisfies $\LEM{}$, then the canonical inclusion
$\prop_{\UU_{i}} \to \prop_{\UU_{i+1}}$ is an equivalence.
*)
(** %\soln%
If $\LEM{i+1}$ holds, then $\LEM{i}$ holds as well. For suppose that
$A : \UU_{i}$ and $p : \isprop(A)$. Then we also have $A :
\UU_{i+1}$, so $\LEM{i+1}(A, p) : A + \lnot A$, establishing
$\LEM{i}$. By the previous exercise, then, $\prop_{\UU_{i}} \eqvsym
\bool \eqvsym \prop_{\UU_{i+1}}$.
Since Coq doesn't let the user access the [Type]${}_{i}$ hierarchy,
there's not much to do here. This is really more of a ``proof by
contemplation'' anyway.
*)
(** %\exerdone{3.11}{127}%
Show that it is not the case that for all $A : \UU$ we have $\brck{A} \to A$.
*)
(** %\soln%
We can essentially just copy Theorem 3.2.2. Suppose given a function $f :
\prd{A:\UU} \brck{A} \to A$, and recall the equivalence $e : \bool \eqvsym
\bool$ from Exercise 2.13 given by $e(1_{\bool}) \defeq 0_{\bool}$ and
$e(0_{\bool}) = 1_{\bool}$. Then $\ua(e) : \bool = \bool$, $f(\bool)
: \brck{\bool} \to \bool$, and
%\[
\mapdepfunc{f}(\ua(e)) :
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)} = f(\bool)
\]%
So for $u : \brck{\bool}$,
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)}(u) = f(\bool)(u)
\]%
and by 2.9.4, we have
%\[
\transfib{A \mapsto (\brck{A} \to A)}{\ua(e)}{f(\bool)}(u)
=
\transfib{A \mapsto A}{\ua(e)}{f(\bool)(\transfib{\lvert \blank
\rvert}{\ua(e)^{-1}}{u}})
\]%
But, any two $u, v : \brck{A}$ are equal, since $\brck{A}$ is contractible. So
$\transfib{\lvert\blank\rvert}{\ua(e)^{-1}}{u} = u$, and so
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
\transfib{A \mapsto A}{\ua(e)}{f(\bool)(u)}
= f(\bool)(u)
\]%
and the propositional computation rule for $\ua$ gives
%\[
\happly(\mapdepfunc{f}(\ua(e)), u) :
e(f(\bool)(u)) = f(\bool)(u)
\]%
But $e$ has no fixed points, so we have a contradiction.
*)
Lemma negb_no_fixpoint : forall b, ~ (negb b = b).
Proof.
intros b H. destruct b; simpl in H.
apply (false_ne_true H).
apply (true_ne_false H).
Defined.
Theorem ex3_11 `{Univalence} : ~ (forall A, Brck A -> A).
Proof.
intro f.
assert (forall b, negb (f Bool b) = f Bool b). intro b.
assert (transport (fun A => Brck A -> A) (path_universe negb) (f Bool) b
=
f Bool b).
apply (apD10 (apD f (path_universe negb)) b).
assert (transport (fun A => Brck A -> A) (path_universe negb) (f Bool) b
=
transport idmap (path_universe negb)
(f Bool (transport (fun A => Brck A)
(path_universe negb)^
b))).
refine (transport_arrow _ _ _).
rewrite X in X0.
assert (b = (transport (fun A : Type => Brck A) (path_universe negb) ^ b)).
apply path_ishprop. rewrite <- X1 in X0. symmetry in X0.
assert (transport idmap (path_universe negb) (f Bool b) = negb (f Bool b)).
apply transport_path_universe. rewrite X2 in X0. apply X0.
apply (@negb_no_fixpoint (f Bool (tr true))).
apply (X (tr true)).
Defined.
(** %\exerdone{3.12}{127}%
Show that if $\LEM{}$ holds, then for all $A : \UU$ we have $\bbrck{\brck{A}
\to A}$.
*)
(** %\soln%
Suppose that $\LEM{}$ holds, and that $A : \UU$. By $\LEM{}$, either $\brck{A}$
or $\lnot\brck{A}$. If the
former, then we can use the recursion principle for $\brck{A}$ to construct a
map to $\bbrck{\brck{A} \to A}$, then apply it to the element of $\brck{A}$.
So we need a map $A \to \bbrck{\brck{A} \to A}$, which is not hard to get:
%\[
\lam{a:A}\left\lvert\lam{a':\brck{A}}a\right\rvert : A \to \bbrck{\brck{A} \to A}
\]%
If the latter, then we have the canonical map out of the empty type $\brck{A}
\to A$, hence we have $\bbrck{\brck{A} \to A}$.
*)
Section Exercise3_12.
Hypothesis LEM : forall A, IsHProp A -> (A + ~A).
Theorem ex3_12 : forall A, Brck (Brck A -> A).
Proof.
intro A.
destruct (LEM (Brck A) _).
strip_truncations. apply tr. intro a. apply t.
apply tr. intro a. contradiction (n a).
Defined.
End Exercise3_12.
(** %\exerdone{3.13}{127}%
Show that the axiom
%\[
\LEM{}': \prd{A:\UU} (A + \lnot A)
\]%
implies that for $X : \UU$, $A : X \to \UU$, and $P : \prd{x:X} A(x) \to \UU$,
if $X$ is a set, $A(x)$ is a set for all $x:X$, and $P(x, a)$ is a mere
proposition for all $x:X$ and $a:A(x)$,
%\[
\left(\prd{x:X}\left\lVert\sm{a:A(x)}P(x, a)\right\rVert\right)
\to
\left\lVert \sm{g:\prd{x:X}A(x)}\prd{x:X}P(x, g(x))\right\rVert.
\]%
*)
(** %\soln%
By Lemma 3.8.2, it suffices to show that for any set $X$ and any $Y : X \to
\UU$ such that $Y(x)$ is a set, we have
%\[
\left(\prd{x:X}\brck{Y(x)}\right) \to \left\lVert\prd{x:X}Y(x)\right\rVert
\]%
Suppose that $f : \prd{x:X}\brck{Y(x)}$. By $\LEM{}'$, either $Y(x)$ is
inhabited or it's not. If it is, then $\LEM{}'(Y(x)) \equiv y : Y(x)$, and we
have
%\[
\left\lvert\lam{x:X}y\right\rvert : \left\lVert \prd{x:X} Y(x) \right\rVert
\]%
Suppose instead that $\lnot Y(x)$ and that $x:X$. Then $f(x) : \brck{Y(x)}$.
Since we're trying to derive a mere proposition, we can ignore this truncation
and suppose that $f(x) : Y(x)$, in which case we have a contradiction, and
we're done.
The reason we can ignore the truncation (and apply [strip_truncations] in Coq)
in hypotheses is given by the reasoning in the previous Exercise. If the
conclusion is a mere proposition, then the recursion principle for
$\brck{Y(x)}$ allows us to construct an arrow out of $\brck{Y(x)}$ if we have
one from $Y(x)$.
*)
Definition AC := forall X A P,
IsHSet X -> (forall x, IsHSet (A x)) -> (forall x a, IsHProp (P x a))
-> ((forall x:X, Brck {a:A x & P x a})
-> Brck {g : forall x, A x & forall x, P x (g x)}).
Definition AC_prod := forall (X : hSet) (Y : X -> Type),
(forall x, IsHSet (Y x)) ->
((forall x, Brck (Y x)) -> Brck (forall x, Y x)).
Lemma hprop_is_hset (A : Type) : IsHProp A -> IsHSet A.
Proof.
typeclasses eauto.
Defined.
Lemma AC_equiv_AC_prod `{Funext} : AC <~> AC_prod.
Proof.
apply equiv_iff_hprop; unfold AC, AC_prod.
(* forward *)
intros AC HX Y HY f.
transparent assert (He : (
Brck ({g : forall x, Y x & forall x, (fun x a => Unit) x (g x)})
<~>
Brck (forall x, Y x)
)).
apply equiv_iff_hprop.
intro w. strip_truncations. apply tr. apply w.1.
intro g. strip_truncations. apply tr. exists g. intro x. apply tt.
apply He. clear He. apply (AC _ Y (fun x a => Unit)). apply HX. apply HY.
intros. apply hprop_Unit. intros.
assert (y : Brck (Y x)) by apply f. strip_truncations.
apply tr. exists y. apply tt.
(* back *)
intros AC_prod X A P HX HA HP f.
transparent assert (He: (
Brck (forall x, {a : A x & P x a})
<~>
Brck {g : forall x, A x & forall x, P x (g x)}
)).
apply equiv_iff_hprop.
intros. strip_truncations. apply tr. exists (fun x => (X0 x).1).
intro x. apply (X0 x).2.
intros. strip_truncations. apply tr. intro x. apply (X0.1 x; X0.2 x).
apply He. clear He.
apply (AC_prod (BuildhSet X) (fun x => {a : A x & P x a})).
intros. apply ex3_3. apply (HA x). intro a.
apply hprop_is_hset. apply (HP x a).
intro x. apply (f x).
Defined.
Section Exercise3_13.
Hypothesis LEM' : forall A, A + ~A.
Theorem ex3_13 `{Funext} : AC.
Proof.
apply AC_equiv_AC_prod. intros X Y HX HY.
apply tr. intros.
destruct (LEM' (Y x)). apply y.
assert (Brck (Y x)) as y'. apply HY.
assert (~ Brck (Y x)) as nn. intro p. strip_truncations. contradiction.
contradiction nn.
Defined.
End Exercise3_13.
(** %\exerdone{3.14}{127}%
Show that assuming $\LEM{}$, the double negation $\lnot\lnot A$ has the same
universal property as the propositional truncation $\brck{A}$, and is therefore
equivalent to it.
*)
(** %\soln%
Suppose that $a : \lnot\lnot A$ and that we have some function $g : A \to B$,
where $B$ is a mere proposition, so $p : \isprop(B)$. We can construct a
function $\lnot \lnot A \to \lnot \lnot B$ by using contraposition twice,
producing $g'': \lnot \lnot A \to \lnot \lnot B$
%\[
g''(h) \defeq
\lam{f : \lnot B}h(\lam{a:A}f(g(a)))
\]%
$\LEM{}$ then allows us to use double negation elimination to produce a map
$\lnot \lnot B \to B$. Suppose that $f : \lnot \lnot B$. Then we have
$\LEM{}(B, p) : B + \lnot B$, and in the left case we can produce the witness,
and in the right case we use $f$ to derive a contradiction. Explicitly, we
have $\ell : \lnot \lnot B \to B$ given by
%\[
\ell(f) \defeq
\rec{B + \lnot\lnot B}(B, \idfunc{B}, f, \LEM{}(B, p))
\]%
The computation rule does not hold judgementally for $g'' \circ \ell$. I don't
see that it can, given the use of $\LEM{}$. Clearly it does hold
propositionally, if one takes $\lvert a \rvert' \defeq \lam{f}f(a)$ to be the
analogue of the constructor for $\brck{A}$; for any $a : A$, we have $g(a) :
B$, and the fact that $B$ is a mere proposition ensures that $(g'' \circ
\ell)(\lvert a \rvert') = g(a)$.
*)
Section Exercise3_14.
Hypothesis LEM : forall A, IsHProp A -> (A + ~A).
Definition Brck' (A : Type) := ~ ~ A.
Definition min1' {A : Type} (a : A) : Brck' A := fun f => f a.
Definition contrapositive {A B : Type} : (A -> B) -> (~ B -> ~ A).
intros. intro a. apply X0. apply X. apply a.
Defined.
Definition DNE {B : Type} `{IsHProp B} : ~ ~ B -> B.
intros. destruct (LEM B IsHProp0). apply b. contradiction X.
Defined.
Definition trunc_rect' {A B : Type} (g : A -> B) : IsHProp B -> Brck' A -> B.
intros HB a. apply DNE. apply (contrapositive (contrapositive g)). apply a.
Defined.
End Exercise3_14.
(** %\exerdone{3.15}{128}%
Show that if we assume propositional resizing, then the type
%\[
\prd{P:\prop}\left((A \to P) \to P\right)
\]%
has the same universal property as $\brck{A}$.
*)
(** %\soln%
Let $A:\UU_{i}$, so that for $\brck{A}'' \defeq \prd{P:\prop_{\UU_{i}}} ((A \to
P) \to P)$ we have $\brck{A}'' : \UU_{i+1}$. By propositional resizing,
however, we have a corresponding $\brck{A}'' : \UU_{i}$. To construct an arrow
$\brck{A}'' \to B$, suppose that $f : \brck{A}''$ and $g : A \to B$. Then
$f(B, g) : B$. So $\lam{f}\tilde{f}(B, g) : \brck{A}'' \to B$, where
$\tilde{f}$ is the image of $f$ under the inverse of the canonical inclusion
$\prop_{\UU_{i}} \to \prop_{\UU_{i+1}}$.
To show that the computation rule holds, let
%\[
\lvert a \rvert'' \defeq \lam{P}{f}f(a) : \prd{P:\prop}\left((A \to P) \to P
\right)
\]%
We need to show that $(\lam{f}\tilde{f}(B, g))(\lvert a \rvert'') \equiv g(a)$.
Assuming that propositional resizing gives a judgemental equality, we have
%\begin{align*}
(\lam{f}\tilde{f}(B, g))(\lvert a \rvert '')
&\equiv
(\lam{f}\tilde{f}(B, g))(\lam{P}{f}f(a))
\\&\equiv
(\lam{P}{f}f(a))(B, g)
\\&\equiv
g(a)
\end{align*}%
*)
Definition Brck'' (A : Type) := forall (P : hProp), ((A -> P) -> P).
Definition min1'' {A : Type} (a : A) := fun (P : hProp) (f : A -> P) => f a.
Definition trunc_rect'' {A B : Type} (g : A -> B) : IsHProp B -> Brck'' A -> B.
intros p f.
apply (f (BuildhProp B)). apply g.
Defined.
(** %\exerdone{3.16}{128}%
Assuming $\LEM{}$, show that double negation commutes with universal
quantification of mere propositions over sets. That is, show that if $X$ is a
set and each $Y(x)$ is a mere proposition, then $\LEM{}$ implies
%\[
\left(\prd{x:X}\lnot\lnot Y(x)\right)
\eqvsym
\left(\lnot\lnot\prd{x:X} Y(x)\right).
\]%
*)
(** %\soln%
Each side is a mere proposition, since one side is a dependent function into a
mere proposition and the other is a negation. So we just need to show that
each implies the other. From left to right we use the fact that $\LEM{}$
is equivalent to double negation to obtain $\prd{x:X}Y(x)$, and double negation
introduction is always allowed, giving the right side. For the other direction
we do the same.
*)
Section Exercise3_16.
Hypothesis LEM : forall A, IsHProp A -> (A + ~ A).
Theorem ex3_16 `{Funext} (X : hSet) (Y : X -> Type) :
(forall x, IsHProp (Y x)) ->
(forall x, ~ ~ Y x) <~> ~ ~ (forall x, Y x).
Proof.
intro HY. apply equiv_iff_hprop; intro H'.
intro f. apply f. intro x.
destruct (LEM (Y x)).
apply HY. apply y.
contradiction (H' x).
intro x.
destruct (LEM (Y x)).
apply HY. intro f. contradiction.
assert (~ (forall x, Y x)). intro f. contradiction (f x).
contradiction H'.
Qed.
End Exercise3_16.
(** %\exerdone{3.17}{128}%
Show that the rules for the propositional truncation given in %\S3.7% are
sufficient to imply the following induction principle: for any type family $B :
\brck{A} \to \UU$ such that each $B(x)$ is a mere proposition, if for every
$a:A$ we have $B(\lvert a \rvert)$, then for every $x : \brck{A}$ we have
$B(x)$.
*)
(** %\soln%
Suppose that $B : \brck{A} \to \UU$, $B(x)$ is a mere proposition for all $x :
\brck{A}$ and that $f : \prd{a:A} B(\lvert a \rvert)$. Suppose that $x
: \brck{A}$; we need to construct an element of $B(x)$. By the
induction principle for $\brck{A}$, it suffices to exhibit a map $A
\to B(x)$. So suppose that $a:A$, and we'll construct an element of
$B(x)$. Since $\brck{A}$ is contractible, we have $p : \lvert a
\rvert = x$, and $p_{*}(f(a)) : B(x)$.
*)
Theorem ex3_17 (A : Type) (B : Brck A -> Type) :
(forall x, IsHProp (B x)) -> (forall a, B (tr a)) -> (forall x, B x).
Proof.
intros HB f. intro x.
apply Trunc_ind. apply HB.
intro a. apply (f a).
Defined.
(** %\exerdone{3.18}{128}%
Show that the law of excluded middle
%\[
\LEM{} : \prd{A:\UU} \left( \isprop(A) \to (A + \lnot A)\right)
\]%
and the law of double negation
%\[
\DN : \prd{A:\UU} \left( \isprop(A) \to (\lnot\lnot A \to A)\right)
\]%
are logically equivalent.
*)
(** %\soln%
For the forward direction, suppose that $\LEM{}$ holds, that $A : \UU$,
that $H : \isprop(A)$, and that $f : \lnot\lnot A$. We then need to produce an
element of $A$. We have $z \defeq \LEM{}(A, H) : A + \lnot A$, so we can
consider cases:
- $z \equiv \inl(a)$, in which case we can produce $a$.
- $z \equiv \inr(x)$, in which case we have $f(x) : \emptyt$, a contradiction.
giving the forward direction.
Suppose instead that $\DN$ holds, and we have $A : \UU$ and $H : \isprop(A)$.
We need to provide an element of $A + \lnot A$. By Exercise 3.6, $A + \lnot A$
is a mere proposition, so by $\DN$, if we can give an element of $\lnot\lnot(A
+ \lnot A)$, then we'll get one of $A + \lnot A$. In Exercise 1.13 we
constructed such an element, so producing that gives one of $A + \lnot A$, and
we're done.
*)
Theorem ex3_18 `{Funext} :
(forall A, IsHProp A -> (A + ~A)) <-> (forall A, IsHProp A -> (~ ~A -> A)).
Proof.
split.
intros LEM A H' f. destruct (LEM A H'). apply a. contradiction.
intros DN A H'. apply (DN (A + ~A) (ex3_6 H')).
exact (fun g : ~ (A + ~ A) => g (inr (fun a:A => g (inl a)))).
Qed.
(** %\exerdone{3.19}{128}%
Suppose $P : \mathbb{N} \to \UU$ is a decidable family of mere propositions.
Prove that
%\[
\left\lVert \sm{n:\mathbb{N}} P(n) \right\rVert
\to
\sm{n:\mathbb{N}} P(n).
\]%
*)
(** %\soln%
Since $P : \mathbb{N} \to \UU$ is decidable, we have $f : \prd{n:\mathbb{N}}
(P(n) + \lnot P(n))$. So if $\bbrck{\sm{n:\mathbb{N}}
P(n)}$ is inhabited, then there is some smallest $n$ such that $P(n)$.
It would be nice if we could define a function to return the
smallest $n$ such that $P(n)$. But unbounded minimization isn't a
total function, so that won't obviously work. Following the
discussion of Corollary 3.9.2, what we can do instead is to define some
%\[
Q : \left(\sm{n:\mathbb{N}} P(n)\right) \to \UU
\]%
such that $\sm{w:\sm{n:\mathbb{N}} P(n)} Q(w)$ is a mere proposition. Then
we can project out an element of $\sm{n:\mathbb{N}} P(n)$.
$Q(w)$ will be the proposition that $w$ is the smallest member of
$\sm{n\mathbb{N}}P(n)$. Explicitly,
%\[
Q(w) \defeq
\prd{w' : \sm{n:\mathbb{N}}P(n)} \fst(w) \leq \fst(w')
\]%
Then we have
%\[
\sm{w : \sm{n : \mathbb{N}} P(n)} Q(w)
\equiv
\sm{w : \sm{n : \mathbb{N}} P(n)}
\prd{w' : \sm{n:\mathbb{N}}P(n)} \fst(w) \leq \fst(w')
\]%
which we must show to be a mere proposition. Suppose that $w$ and $w'$ are two
elements of this type. By $\snd(w)$ and $\snd(w')$, we have $\fst(\fst(w)) \leq
\fst(\fst(w'))$ and $\fst(\fst(w')) \leq \fst(\fst(w))$, so $\fst(\fst(w)) = \fst(\fst(w'))$. Since
$\mathbb{N}$ has decidable equality, $\fst(w) \leq \snd(w')$ is a mere
proposition for all $w$ and $w'$, meaning that $Q(w)$ is a mere proposition.
So $w = w'$, meaning that our type is contractible.
Now we can use the universal property of $\bbrck{\sm{n:\mathbb{N}}P(n)}$ to
construct an arrow into $\sm{w : \sm{n:\mathbb{N}} P(n)} Q(w)$ by way of a
function $\big(\sm{n:\mathbb{N}} P(n)\big) \to \sm{w : \sm{n:\mathbb{N}} P(n)}
Q(w)$. So suppose that we have some element $w : \sm{n:\mathbb{N}} P(n)$.
Using bounded minimization, we can obtain the smallest element of $\sm{n:
\mathbb{N}} P(n)$ that's less than or equal to $w$, and this will in fact be
the smallest element _tout court_. This means that it's a member of our
constructed type, so we've constructed a map
%\[
\left\lVert \sm{n:\mathbb{N}} P(n) \right\rVert
\to
\sm{w:\sm{n:\mathbb{N}}P(n)}Q(w)
\]%
and projecting out gives the function in the statement.
*)
Local Open Scope nat_scope.
Fixpoint nat_code (n m : nat) :=
match n, m with
| O, O => Unit
| S n', O => Empty
| O, S m' => Empty
| S n', S m' => nat_code n' m'
end.
Fixpoint nat_r (n : nat) : nat_code n n :=
match n with
| O => tt
| S n' => nat_r n'
end.
Definition nat_encode (n m : nat) (p : n = m) : (nat_code n m)
:= transport (nat_code n) p (nat_r n).
Definition nat_decode : forall (n m : nat), (nat_code n m) -> (n = m).
Proof.
induction n, m; intro H.
reflexivity. contradiction. contradiction.
apply (ap S). apply IHn. apply H.
Defined.
Theorem equiv_path_nat : forall n m, (nat_code n m) <~> (n = m).
Proof.
intros.
refine (equiv_adjointify (nat_decode n m) (nat_encode n m) _ _).
intro p. destruct p. simpl.
induction n. reflexivity. simpl.
apply (ap (ap S) IHn).
generalize dependent m.
induction n. induction m.
intro c. apply eta_unit.
intro c. contradiction.
induction m.
intro c. contradiction.
intro c. simpl. unfold nat_encode.
refine ((transport_compose _ S _ _)^ @ _).
simpl. apply IHn.
Defined.
Lemma Sn_neq_O : forall n, S n <> O.
Proof.
intros n H. apply nat_encode in H. contradiction.
Defined.
Lemma plus_eq_O (n m : nat) : n + m = O -> (n = O) /\ (m = O).
Proof.
destruct n.
intro H. split. reflexivity. apply H.
intro H. simpl in H. apply nat_encode in H. contradiction.
Defined.
Lemma le_trans : forall n m k, (n <= m) -> (m <= k) -> (n <= k).
Proof.
intros n m k Hnm Hmk.
destruct Hnm as [l p].
destruct Hmk as [l' p'].
exists (l + l').
refine ((plus_assoc _ _ _)^ @ _).
refine (_ @ p'). f_ap.
Defined.
Lemma le_Sn_le (n m : nat) : S n <= m -> n <= m.
Proof.
intro H. apply (le_trans n (S n) m). exists 1. apply (plus_1_r _)^. apply H.
Defined.
Lemma plus_cancelL : forall n m k, n + m = n + k -> m = k.
Proof.
intro n. induction n. trivial.
intros m k H.
apply S_inj in H. apply IHn. apply H.
Defined.
Lemma le_antisymmetric (n m : nat) : (n <= m) -> (m <= n) -> (n = m).
Proof.
intro H. destruct H as [k p].
intro H. destruct H as [k' p'].
transparent assert (q : (n + (k + k') = n + O)).
refine ((plus_assoc _ _ _)^ @ _).
refine ((ap (fun s => s + k') p) @ _).
refine (_ @ (plus_O_r _)).
apply p'.
apply plus_cancelL in q.
apply plus_eq_O in q.
refine ((plus_O_r _) @ _).
refine ((ap (plus n) (fst q))^ @ _).
apply p.
Defined.
Lemma decidable_paths_nat : DecidablePaths nat.
Proof.
intros n m.
generalize dependent m.
generalize dependent n.
induction n, m.
left. reflexivity.
right. intro H. apply nat_encode in H. contradiction.
right. intro H. apply nat_encode in H. contradiction.
destruct (IHn m).
left. apply (ap S p).
right. intro H. apply S_inj in H. apply n0. apply H.
Defined.
Lemma hset_nat : IsHSet nat.
Proof. apply hset_decpaths. apply decidable_paths_nat. Defined.
Lemma hprop_le (n m : nat) : IsHProp (n <= m).
Proof.
apply hprop_allpath. intros p q.
refine (path_sigma_hprop _ _ _).
destruct p as [k p], q as [k' p']. simpl.
apply (plus_cancelL n).
apply (p @ p'^).
Defined.
Lemma hprop_dependent `{Funext} (A : Type) (P : A -> Type) :
(forall a, IsHProp (P a)) -> IsHProp (forall a, P a).
Proof.
intro HP.
apply hprop_allpath. intros p p'. apply path_forall; intro a. apply HP.
Defined.
Definition n_le_n (n : nat) : n <= n := (O; (plus_O_r n)^).
Definition n_le_Sn (n : nat) : n <= S n := (S O; (plus_1_r n)^).
Lemma Spred (n : nat) : (n <> O) -> S (pred n) = n.
Proof.
induction n; intro H; [contradiction H|]; reflexivity.
Defined.
Lemma le_partitions (n : nat) : forall m, (m <= n) + (n <= m).
Proof.
induction n.
intro m. right. exists m. reflexivity.
intro m.
destruct (IHn m) as [IHnm | IHnm].
left. apply (le_trans _ n). apply IHnm. apply n_le_Sn.
destruct IHnm as [k p].
destruct (decidable_paths_nat n m).
left. exists 1. refine ((plus_1_r _)^ @ _). apply (ap S p0^).
right. exists (pred k). refine ((plus_n_Sm _ _) @ _). refine (_ @ p).
f_ap. apply Spred.
intro H. apply n0.
refine ((plus_O_r _) @ _). refine ((ap (plus n) H^) @ _). apply p.
Defined.
Lemma le_neq__lt (n m : nat) : (n <= m) -> (n <> m) -> (n < m).
Proof.
intros H1 H2. destruct H1 as [k p].
exists (pred k). refine (_ @ p). f_ap.
apply Spred. intro Hk. apply H2.
refine (_ @ p). refine ((plus_O_r _) @ _). f_ap.
apply Hk^.
Defined.
Lemma lt_partitions (n m : nat) : (n < m) + (n = m) + (m < n).
Proof.
destruct (decidable_paths_nat n m).
left. right. apply p.
destruct (le_partitions n m).
right. apply le_neq__lt. apply l. intro H. apply n0. apply H^.
left. left. apply le_neq__lt. apply l. apply n0.
Defined.
Lemma p_nnp : forall P, P -> ~ ~ P.
Proof. auto. Defined.
Lemma n_nlt_n (n : nat) : ~ (n < n).
Proof.
intros H. destruct H as [k p].
apply (nat_encode (S k) O).
apply (plus_cancelL n).
apply (p @ (plus_O_r _)).
Defined.
Lemma n_neq_Sn (n : nat) : n <> S n.
Proof.
induction n.
intro H. apply nat_encode in H. contradiction.
intro H. apply IHn. apply S_inj in H. apply H.
Defined.
Lemma n_lt_Sm__n_le_m (n m : nat) : (n < S m) -> (n <= m).
Proof.
intro H. destruct H as [k p]. exists k.
apply S_inj. refine (_ @ p).
apply plus_n_Sm.
Defined.
Lemma le_O (n : nat) : n <= O -> n = O.
Proof.
intro H. destruct H as [k p].
apply plus_eq_O in p. apply (fst p).
Defined.
Lemma lt_1 (n : nat) : n < 1 -> n = O.
Proof.
intro H.
apply le_O. apply n_lt_Sm__n_le_m. apply H.
Defined.
Lemma lt_le (n m : nat) : n < m -> n <= m.
Proof.
intro H. destruct H as [k p].
exists (S k). apply p.
Defined.
Lemma Sn_lt_Sm__n_lt_m (n m : nat) : S n < S m -> n < m.
Proof.
intro H. destruct H as [k p]. exists k.
simpl in p. apply S_inj in p. apply p.
Defined.
Lemma lt_neq (n m : nat) : n < m -> n <> m.
Proof.
generalize dependent m.
induction n.
intros m H HX.
destruct H as [k p]. simpl in p.
apply (nat_encode (S k) O).
apply (p @ HX^).
induction m.
intros H HX.
apply (nat_encode (S n) O). apply HX.
intros H Hx.
apply Sn_lt_Sm__n_lt_m in H.
apply IHn in H. apply H. apply S_inj. apply Hx.
Defined.
Lemma lt_trans (n m k : nat) : n < m -> m < k -> n < k.
Proof.
intros H1 H2.
destruct H1 as [l p], H2 as [l' p'].
exists (l + S l').
refine (_ @ p').
change (S (l + S l')) with (S l + S l').
refine ((plus_assoc _ _ _)^ @ _). f_ap.
Defined.
Lemma n_lt_Sn (n : nat) : n < S n.
Proof.
exists O. apply (plus_1_r _)^.
Defined.
Lemma bound_up (n m : nat) : (n <= m) -> (n <> m) -> (S n <= m).
Proof.
intros H1 H2.
apply le_neq__lt in H1.
destruct H1 as [k p]. exists k.
refine ((plus_n_Sm _ _) @ _). apply p. apply H2.
Defined.
Lemma le_lt__lt (n m k : nat) : n <= m -> m < k -> n < k.
Proof.
intros H1 H2.
destruct (decidable_paths_nat n m).
destruct H2 as [l q].
exists l. refine (_ @ q). f_ap.
apply (lt_trans _ m).
apply le_neq__lt. apply H1. apply n0. apply H2.
Defined.
Lemma lt_le__lt (n m k : nat) : n < m -> m <= k -> n < k.
Proof.
intros H1 H2.
destruct (decidable_paths_nat m k).
destruct H1 as [l q].
exists l. refine (_ @ p). apply q.
apply (lt_trans _ m).
apply H1. apply le_neq__lt. apply H2. apply n0.
Defined.
Lemma le_eq__le (n m k : nat) : (n <= m) -> (m = k) -> (n <= k).
Proof.
intros H1 H2.
destruct H1 as [l p].
exists l. apply (p @ H2).
Defined.
Lemma n_le_m__Sn_le_Sm (n m : nat) : n <= m -> (S n <= S m).
Proof.
intro H. destruct H as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma Sn_le_Sm__n_le_m (n m : nat) : S n <= S m -> n <= m.
Proof.
intro H. destruct H as [k p]. exists k.
simpl in p. apply S_inj in p. apply p.
Defined.
Lemma n_nlt_O (n : nat) : ~ (n < O).
Proof.
induction n. apply n_nlt_n.
intro H. destruct H as [k p]. apply nat_encode in p. contradiction.
Defined.
Lemma O_lt_n (n : nat) : (n <> O) -> (O < n).
Proof.
intro H.
exists (pred n).
apply Spred. apply H.
Defined.
Lemma n_lt_m__Sn_lt_Sm (n m : nat) : n < m -> S n < S m.
Proof.
intro H. destruct H as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma n_lt_m__n_le_Sm (n m : nat) : n < m -> n <= S m.
Proof.
intro H. destruct H as [k p].
exists (S (S k)). apply (ap S) in p. refine (_ @ p).
symmetry. apply plus_n_Sm.
Defined.
Lemma lt_bound_down (n m : nat) : n < S m -> (n <> m) -> n < m.
Proof.
intros H X. destruct H as [k p].
exists (pred k). refine ((plus_n_Sm _ _)^ @ _).
refine ((plus_n_Sm _ _) @ _). apply S_inj. refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. apply (ap S). apply Spred.
intro H. apply X. apply S_inj. refine (_ @ p).
refine (_ @ (plus_n_Sm _ _)). apply (ap S). refine ((plus_O_r _) @ _). f_ap.
apply H^.
Defined.
Lemma lt_bound_up (n m : nat) : n < m -> (S n <> m) -> S n < m.
Proof.
intros H X.
destruct H as [k p]. exists (pred k). refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. f_ap. apply Spred. intro H.
apply X. refine (_ @ p). refine ((plus_1_r _) @ _). f_ap. f_ap. apply H^.
Defined.
Lemma pred_n_eq_O : forall n, pred n = O -> (n = O) + (n = 1).
Proof.
induction n.
intros. left. reflexivity.
intros H. simpl in H. right. apply (ap S H).
Defined.
Lemma bound_down (n m : nat) : (n <= S m) -> (n <> S m) -> (n <= m).
Proof.
intros H1 H2.
apply le_neq__lt in H1.
destruct H1 as [k p]. exists k.
apply S_inj. refine ((plus_n_Sm _ _) @ _). apply p. apply H2.
Defined.
Lemma nle_lt (n m : nat) : ~ (n <= m) -> (m < n).
Proof.
generalize dependent m.
induction n.
intros m H. assert Empty. apply H. exists m. reflexivity. contradiction.
intros m H. destruct m.
exists n. reflexivity.
apply n_lt_m__Sn_lt_Sm. apply IHn. intro H'. apply H.
destruct H' as [k p]. exists k. simpl. apply (ap S). apply p.
Defined.
Lemma Sn_neq_n (n : nat) : S n <> n.
Proof.
intro H.
apply (nat_encode 1 0).
apply (plus_cancelL n).
refine ((plus_1_r _)^ @ _). refine (_ @ (plus_O_r _)).
apply H.
Defined.
Lemma lt_antisymmetric (n m : nat) : n < m -> ~ (m < n).
Proof.
intros H HX.
destruct H as [k p], HX as [k' p'].
transparent assert (H : (S k + S k' = O)).
apply (plus_cancelL n). refine (_ @ (plus_O_r _)).
refine (_ @ p'). refine ((plus_assoc _ _ _)^ @ _). f_ap.
apply nat_encode in H. contradiction.
Defined.
Lemma lt_eq__lt (n m k : nat) : (n < m) -> (m = k) -> (n < k).
Proof.
intros H1 H2.
destruct H1 as [l p].
exists l. refine (p @ _). apply H2.
Defined.
Lemma nlt_le (n m : nat) : ~ (n < m) -> (m <= n).
Proof.
generalize dependent m.
induction n.
intros m H. destruct (decidable_paths_nat m O). exists O. refine (_ @ p).
symmetry. apply plus_O_r.
assert Empty. apply H. apply O_lt_n. apply n. contradiction.
induction m.
intro H. exists (S n). reflexivity.
intro H. apply n_le_m__Sn_le_Sm. apply IHn.
intro H'. apply H. apply n_lt_m__Sn_lt_Sm. apply H'.
Defined.
Lemma n_lt_m__Sn_le_m (n m : nat) : (n < m) -> (S n <= m).
Proof.
intro H.
apply n_lt_m__Sn_lt_Sm in H.
apply n_lt_Sm__n_le_m in H.
apply H.
Defined.
Lemma n_le_m__n_lt_Sm (n m : nat) : n <= m -> n < S m.
Proof.
intro H.
destruct H as [k p].
exists k. refine ((plus_n_Sm _ _)^ @ _). f_ap.
Defined.
Section Exercise3_19.
Context {P : nat -> Type} {HP : forall n, IsHProp (P n)}
{DP : forall n, P n + ~ P n}.
Local Definition Q (w : {n : nat & P n}) : Type :=
forall w' : {n : nat & P n}, w.1 <= w'.1.
Lemma hprop_Q `{Funext} : forall w, IsHProp (Q w).
Proof.
intro w. unfold Q. apply hprop_dependent. intro w'. apply hprop_le.
Defined.
Lemma hprop_sigma_Q `{Funext} : IsHProp {w : {n : nat & P n} & Q w}.
Proof.
apply hprop_allpath. intros w w'.
refine (path_sigma_hprop _ _ _). apply hprop_Q.
apply path_sigma_hprop. apply le_antisymmetric.
apply (w.2 w'.1). apply (w'.2 w.1).
Defined.
Definition bmin (bound : nat) : nat.
Proof.
induction bound as [|z].
destruct (DP O). apply O. apply 1.
destruct (lt_partitions IHz (S z)) as [[Ho | Ho] | Ho].
apply IHz.
destruct (DP (S z)).
apply (S z).
apply (S (S z)).
apply (S (S z)).
Defined.
Lemma bmin_correct_O (n : nat) : P O -> bmin n = O.
Proof.
intro H.
induction n. simpl. destruct (DP O). reflexivity. apply n in H. contradiction.
simpl. rewrite IHn. reflexivity.
Defined.
Lemma bmin_correct_self_P (n : nat) : bmin n = n -> P n.
Proof.
induction n.
intros H. simpl in H.
destruct (DP O).
apply p.
apply nat_encode in H. contradiction.
intro H.
simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
rewrite H in Ho. apply n_nlt_n in Ho. contradiction.
destruct (DP (S n)). apply p.
transparent assert (X : Empty).
apply (n_neq_Sn (S n)). apply H^.
contradiction.
transparent assert (X : Empty).
apply (n_neq_Sn (S n)). apply H^.
contradiction.
Defined.
Lemma bmin_correct_bound (n : nat) : bmin n <= S n.
Proof.
induction n.
simpl.
destruct (DP O). exists 1. reflexivity.
exists O. apply plus_n_Sm.
simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
apply (le_trans _ (S n)). apply IHn. apply n_le_Sn.
destruct (DP (S n)).
apply n_le_Sn.
apply n_le_n.
apply n_le_n.
Defined.
Lemma bmin_correct_nPn (n : nat) : bmin n = S n -> ~ P n.
Proof.
induction n.
intros H HX.
apply (bmin_correct_O O) in HX.
apply (nat_encode 1 O). refine (H^ @ _). refine (_ @ HX). reflexivity.
intros H HX. simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
rewrite H in Ho. apply (n_nlt_n (S (S n))).
apply (lt_trans _ (S n)). apply Ho. apply n_lt_Sn.
destruct (DP (S n)).
apply (n_neq_Sn (S n)). apply H.
apply n0. apply HX.
clear H.
apply (n_nlt_n (bmin n)).
apply (le_lt__lt _ (S n)).
apply bmin_correct_bound.
apply Ho.
Defined.
Lemma bmin_correct_success (n : nat) : bmin n < S n -> P (bmin n).
Proof.
induction n.
intro H. apply lt_1 in H. apply bmin_correct_self_P in H.
apply ((bmin_correct_O _ H)^ # H).
simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
intro H. apply IHn. apply Ho.
destruct (DP (S n)).
intro H. apply p.
intro H. apply n_nlt_n in H. contradiction.
intro H. apply n_nlt_n in H. contradiction.
Defined.
Lemma bmin_correct_i (n : nat) : forall m, (m < n) -> (m < bmin n) -> ~ P m.
Proof.
induction n.
intros m H1 H2.
apply n_nlt_O in H1. contradiction.
induction m. intro H. clear H.
destruct (decidable_paths_nat n O).
(* Case: n = O *)
(* we just want the contrapositive of bmin_correct_O *)
intro H.
apply (contrapositive (bmin_correct_O (S n))).
intro H'. rewrite H' in H. apply n_nlt_n in H. contradiction.
(* Case: n <> O *)
intro H. apply IHn. apply O_lt_n. apply n0.
simpl in H.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
(* Case: bmin n < S n *)
apply H.
(* Case: bmin n = S n *)
rewrite Ho. apply O_lt_n. apply Sn_neq_O.
apply (lt_trans _ (S n)). apply O_lt_n. apply Sn_neq_O. apply Ho.
intros H1. apply Sn_lt_Sm__n_lt_m in H1. simpl.
destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
(* Case: bmin n < S n *)
intro H. apply IHn.
destruct (decidable_paths_nat (bmin n) n).
rewrite <- p. apply H.
apply lt_bound_down in Ho.
apply (lt_trans _ (bmin n)). apply H. apply Ho. apply n0. apply H.
(* Case: bmin n = S n *)
intro H.
destruct (decidable_paths_nat (S m) n).
apply bmin_correct_nPn. rewrite p. apply Ho.
apply lt_bound_up in H1. apply IHn. apply H1.
apply (lt_trans _ n). apply H1. rewrite Ho. apply n_lt_Sn.
apply n0.
(* Case: bmin n > S n *)
set (H := (bmin_correct_bound n)).
assert Empty. apply (n_nlt_n (S n)).
apply (lt_le__lt _ (bmin n)).
apply Ho. apply H. contradiction.
Defined.
Lemma bmin_correct_i' (n : nat) : forall m, (m <= n) -> (m < bmin n) -> ~ P m.
Proof.
intros m H.
destruct (decidable_paths_nat m n).
clear H.
intro H.
set (H' := (bmin_correct_nPn n)). rewrite p. apply H'. clear H'.
set (H' := (bmin_correct_bound n)). rewrite p in H.
apply le_antisymmetric. apply H'. destruct H as [k q].
exists k. refine ((plus_n_Sm _ _) @ _). apply q.
apply le_neq__lt in H. generalize H. apply bmin_correct_i. apply n0.
Defined.
Lemma bmin_correct_leb (n : nat) : P n -> (bmin n <= n).
Proof.
induction n.
intro H. apply (bmin_correct_O O) in H.
exists O. refine (_ @ H). symmetry. apply plus_O_r.
intro H.
simpl. destruct (lt_partitions (bmin n) (S n)) as [[Ho | Ho] | Ho].
destruct Ho as [k p]. exists (S k). apply p.
destruct (DP (S n)). exists O. symmetry. apply plus_O_r.
apply n0 in H. contradiction.
apply (le_trans _ (bmin n)).
apply n_lt_m__Sn_le_m. apply Ho.
apply (bmin_correct_bound n).
Defined.
Lemma bmin_correct_i_cp (n m : nat) : P m -> (bmin n <= m).
Proof.
intro H.
transparent assert (H' : (
forall n m : nat, (m < n /\ m < bmin n) -> ~ P m
)).
intros n' m' H'. apply (bmin_correct_i n'). apply (fst H'). apply (snd H').
transparent assert (H'' : (~ ~ P m)). apply p_nnp. apply H.
apply (contrapositive (H' n m)) in H''.
transparent assert (H''' : (sum (~ (m < n)) (~ (m < bmin n)))).
destruct (lt_partitions n m) as [[Ho | Ho] | Ho].
left. apply lt_antisymmetric. apply Ho.
left. intro H'''. apply (n_nlt_n n). apply (lt_eq__lt m n m) in H'''.
apply (n_nlt_n m) in H'''. contradiction.
apply Ho.
right. intro H'''.
apply H''. split. apply Ho. apply H'''.
destruct H'''; clear H'' H'.
apply nlt_le in n0.
apply nlt_le. intro H'.
set (H'' := (bmin_correct_bound n)).
transparent assert (Heq : (n = m)).
apply le_antisymmetric. apply n0. apply n_lt_Sm__n_le_m.
apply (lt_le__lt _ (bmin n) _). apply H'. apply H''.
transparent assert (Hle : (m <= n)).
exists O. refine (_ @ Heq^). symmetry. apply plus_O_r.
generalize H. change (P m -> Empty) with (~ P m).
apply (bmin_correct_i' n). apply Hle. apply H'.
apply nlt_le in n0. apply n0.
Defined.
Lemma bmin_correct (bound : nat) :
{n : nat & P n /\ n <= bound} -> forall n, P n -> bmin bound <= n.
Proof.
induction bound.
intros w n p.
destruct w as [w [a b]].
apply le_O in b.
exists n. transitivity (O + n). f_ap. apply bmin_correct_O. apply (b # a).
reflexivity.
intros w n p. simpl.
destruct (lt_partitions (bmin bound) (S bound)) as [[Ho | Ho] | Ho].
(* bmin bound < S bound *)
apply IHbound. exists (bmin bound). split.
apply bmin_correct_success. apply Ho.
destruct Ho as [k q]. exists k. apply S_inj. refine (_ @ q).
refine ((plus_n_Sm _ _) @ _). reflexivity.
apply p.
(* bmin bound = S bound *)
destruct w as [w [a b]].
destruct (decidable_paths_nat w (S bound)).
destruct (DP (S bound)).
apply nlt_le. intro H.
generalize p. change (P n -> Empty) with (~ P n).
apply (bmin_correct_i' bound).
apply n_lt_Sm__n_le_m. apply H. rewrite Ho. apply H.
rewrite <- p0 in n0. apply n0 in a. contradiction.
apply le_neq__lt in b.
apply n_lt_Sm__n_le_m in b.
transparent assert (Hlt : (w < bmin bound)).
apply (lt_eq__lt _ (S bound)).
apply n_le_m__n_lt_Sm. apply b. apply Ho^.
assert Empty. generalize a. change (P w -> Empty) with (~ P w).
apply (bmin_correct_i' bound). apply b. apply Hlt. contradiction. apply n0.
(* S bound < bmin bound *)
set (H := (bmin_correct_bound bound)).
apply (lt_le__lt _ _ (S bound)) in Ho.
apply n_nlt_n in Ho. contradiction.
apply H.
Defined.
Lemma ex3_19 `{Funext} : Brck {n : nat & P n} -> {n : nat & P n}.
Proof.
intro w.
apply (@pr1 _ Q).
set (H' := hprop_sigma_Q).
strip_truncations.
transparent assert (w' : {n : nat & P n}).
exists (bmin w.1).
apply bmin_correct_success.
apply n_le_m__n_lt_Sm. apply bmin_correct_leb. apply w.2.
exists w'.
unfold Q.
intro w''.
apply bmin_correct.
exists w.1. split. apply w.2. apply n_le_n. apply w''.2.
Defined.
End Exercise3_19.
Local Close Scope nat_scope.
(** %\exerdone{3.20}{128}%
Prove Lemma 3.11.9(ii): if $A$ is contractible with center $a$, then
$\sm{x:A}P(x)$ is equivalent to $P(a)$.
*)
(** %\soln%
Suppose that $A$ is contractible with center $a$. For the forward direction,
suppose that $w : \sm{x:A} P(x)$. Then $\fst(w) = a$, since $A$ is
contractible, so from $\snd(w) : P(\fst(w))$ and the indiscernibility
of identicals, we have $P(a)$. For the backward direction, suppose
that $p : P(a)$. Then we have $(a, p) : \sm{x:A} P(x)$.
To show that these are quasi-inverses, suppose that $p : P(a)$. Going backward
gives $(a, p) : \sm{x:A} P(x)$, and going forward we have
$(\contr_{a}^{-1})_{*}p$. Since $A$ is contractible, $\contr_{a} =
\refl{a}$, so this reduces to $p$, as needed.
For the other direction, suppose that $w : \sm{x:X} P(x)$. Going forward gives
$(\contr_{\fst(w)}^{-1})_{*}\snd(w) : P(a)$, and going back gives
%\[
(a, (\contr_{\fst(w)}^{-1})_{*}\snd(w)) : \sm{x:A} P(x)
\]%
By Theorem 2.7.2, it suffices to show that $a = \fst(w)$ and that
%\[
(\contr_{\fst(w)})_{*}(\contr_{\fst(w)}^{-1})_{*} \snd(w) = \snd(w)
\]%
The first of these is given by the fact that $A$ is contractible. The second
results from the functorality of transport.
*)
Module Ex20.
Theorem equiv_sigma_contr_base (A : Type) (P : A -> Type) (HA : Contr A) :
{x : A & P x} <~> P (center A).
Proof.
simple refine (equiv_adjointify _ _ _ _).
intro w. apply (transport _ (contr w.1)^). apply w.2.
intro p. apply (center A; p).
intro p. simpl.
assert (Contr (center A = center A)). apply contr_paths_contr.
assert (contr (center A) = idpath). apply path_ishprop.
rewrite X0. reflexivity.
intro w. apply path_sigma_uncurried.
simpl. exists (contr w.1).
apply transport_pV.
Defined.
End Ex20.
(** %\exerdone{3.21}{128}%
Prove that $\isprop(P) \eqvsym (P \eqvsym \brck{P})$.
*)
(** %\soln%
$\isprop(P)$ is a mere proposition by Lemma 3.3.5. $P \eqvsym \brck{P}$ is
also a mere proposition. An equivalence is determined by its underlying
function, and for all $f, g : P \to \brck{P}$, $f = g$ by function
extensionality and the fact that $\brck{P}$ is a mere proposition. Since each
of the two sides is a mere proposition, we just need to show that they imply
each other, by Lemma 3.3.3. Lemma 3.9.1 gives the forward direction. For the
backward direction, suppose that $e : P \eqvsym \brck{P}$, and let $x, y : P$.
Then $e(x) = e(y)$, since $\brck{P}$ is a proposition, and applying $e^{-1}$ to
each side gives $x = y$. Thus $P$ is a mere proposition.
*)
Theorem ex3_21 `{Funext} (P : Type) : IsHProp P <~> (P <~> Brck P).
Proof.
assert (IsHProp (P <~> Brck P)). apply hprop_allpath; intros e1 e2.
apply path_equiv. apply path_forall; intro p.
apply hprop_allpath. apply path_ishprop.
apply equiv_iff_hprop.
intro HP. apply equiv_iff_hprop. apply tr.
apply Trunc_ind. intro p. apply HP. apply idmap.
intro e. apply hprop_allpath; intros x y.
assert (e x = e y) as p. apply hprop_allpath. apply path_ishprop.
rewrite (eissect e x)^. rewrite (eissect e y)^.
apply (ap e^-1 p).
Defined.
(** %\exerdone{3.22}{128}%
As in classical set theory, the finite version of the axiom of choice is a
theorem. Prove that the axiom of choice holds when $X$ is a finite type
$\Fin(n)$.
*)
(** %\soln%
We want to show that for all $n$, $A : \Fin(n) \to \UU$, and
$P : \prd{m_{n} : \Fin(n)} A(m_{n}) \to \UU$, if $A$ is a family of sets and
$P$ a family of propositions, then
%\[
\left(
\prd{m_{n} : \Fin(n)} \left\lVert \sm{a:A(m_{n})} P(m_{n}, a)\right\rVert
\right)
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A(m_{n})} \prd{m_{n} : \Fin(n)}
P(m_{n}, g(m_{n}))
}
\]%
We proceed by induction on $n$. Note first that $\eqv{\Fin(0)}{\emptyt}$ and
that $\eqv{\Fin(n + 1)}{\Fin(n) + \unit}$, which follow quickly from the fact
that $\N$ is a set. In particular, we'll use the equivalence which sends
$n_{n+1}$ to $\star$ and $m_{n+1}$ to $m_{n}$ for $m < n$.
For the base case, $n \equiv 0$, everything is easily provided by ex falso
quodlibet.
For the induction step, we can define a new family of sets $A' : (\Fin(n) +
\unit) \to \UU$ as follows:
%\begin{align*}
A'(z) &= \begin{cases}
A(m_{n+1}) & \text{if $z \equiv m_{n}$} \\
A(n_{n+1}) & \text{if $z \equiv \star$}
\end{cases}
\end{align*}%
And if $e : \eqv{\Fin(n+1)}{\Fin(n) + \unit}$, then we clearly have
$h : \eqv{A(z)}{A'(e(z))}$ for all $z : \Fin(n+1)$. Similarly, we can define
%\begin{align*}
P'(z, a) &= \begin{cases}
P(m_{n+1}, h^{-1}(a)) & \text{if $z \equiv m_{n}$} \\
P(n_{n+1}, h^{-1}(a)) & \text{if $z \equiv \star$}
\end{cases}
\end{align*}%
For which we clearly have $g : \eqv{P(z, a)}{P'(e(z), h(a))}$ for all $z$ and
$a$. So, by the functorality of equivalence (Ex.%~%2.17), we have
%\[
\eqv{
\prd{m_{n+1} : \Fin(n + 1)} \brck{\sm{a : A(m_{n+1})} P(m_{n+1}, a)}
}{
\prd{z : \Fin(n) + \unit} \brck{\sm{a : A'(z)} P'(z, a)}
}
\]%
But, since the induction principle for the sum type is an equivalence, we also
have
%\[
\eqv{
\prd{z : \Fin(n) + \unit} \brck{\sm{a : A'(z)} P'(z, a)}
}{
\left(\prd{z : \Fin(n)} \brck{\sm{a : A'(\inl(z))} P'(\inl(z), a)}\right)
\times
\left(\prd{z : \unit} \brck{\sm{a : A'(\inr(z))} P'(\inr(z), a)}\right)
}
\]%
And to construct an arrow out of this, we just need to give an arrow out of
each one. Now, by the same equivalences, we can rewrite the conclusion as
%\[
\brck{
\sm{g : \prd{z : \Fin(n) + \unit} A'(z)}
\prd{z : \Fin(n) + \unit}
P'(z, g(z))
}
\]%
Using the universal property of $\Sigma$ types, we get
%\[
\brck{
\prd{z : \Fin(n) + \unit} \sm{a : A'(z)} P'(z, a)
}
\]%
and the functorality of the induction principle for the sum gives
%\[
\brck{
\left(\prd{z : \Fin(n)} \sm{a : A'(\inl(z))} P'(\inl(z), a)\right)
\times
\left(\prd{z : \unit} \sm{a : A'(\inr(z))} P'(\inr(z), a)\right)
}
\]%
Since this is only a finite product, we can take it outside of the truncation,
giving
%\[
\brck{
\prd{z : \Fin(n)} \sm{a : A'(\inl(z))} P'(\inl(z), a)
}
\times
\brck{
\prd{z : \unit} \sm{a : A'(\inr(z))} P'(\inr(z), a)
}
\]%
and using the universal property of $\Sigma$ types to go back once more, we
finally arrive at
%\[
\brck{
\sm{g : \prd{z : \Fin(n)} A'(\inl(z))}
\prd{z : \Fin(n)}
P'(\inl(z), g(z))
}
\times
\brck{
\prd{z : \unit}
\sm{a : A'(\inr(z))}
P'(\inr(z), a)
}
\]%
Since each of the domain and codomain are products, we can produce the required
map by giving one between the first items of each product and one between the
second. So first we need an arrow
%\[
\prd{m_{n} : \Fin(n)} \brck{\sm{a : A'(\inl(m_{n}))} P'(\inl(m_{n}), a)}
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A'(\inl(m_{n}))}
\prd{m_{n} : \Fin(n)}
P'(\inl(m_{n}), g(m_{n}))
}
\]%
but by definition of $A'$ and $P'$, this is just
%\[
\prd{m_{n} : \Fin(n)} \brck{\sm{a : A(m_{n})} P(m_{n}, a)}
\to
\brck{
\sm{g : \prd{m_{n} : \Fin(n)} A(m_{n})}
\prd{m_{n} : \Fin(n)}
P(m_{n}, g(m_{n}))
}
\]%
which is the induction hypothesis. For the second map, we need
%\[
\prd{z : \unit}\brck{\sm{a : A'(\inr(z))} P'(\inr(z), a)}
\to
\brck{\prd{z : \unit}\sm{a : A'(\inr(z))} P'(\inr(z), a)}
\]%
which by the computation rules for $A'$ and $P'$ is
%\[
\left(\unit \to \brck{\sm{a : A(n_{n+1})} P(n_{n+1}, a)}\right)
\to
\brck{\unit \to \sm{a : A(n_{n+1})} P(n_{n+1}, a)}
\]%
and this is easily constructed using the recursor for truncation.
*)
Definition cardO : Fin O -> Empty.
Proof.
intro w. destruct w as [n [k p]].
apply plus_eq_O in p. apply (nat_encode (S k) O). apply (snd p).
Defined.
Theorem isequiv_cardO : IsEquiv cardO.
Proof.
simple refine (isequiv_adjointify _ _ _ _).
apply Empty_rect.
(* Section *)
intro w. contradiction.
(* Retraction *)
intro w. destruct w as [n [k p]].
assert Empty.
apply (nat_encode (S k) O).
apply (@snd (n = O) _).
apply plus_eq_O.
apply p.
contradiction.
Defined.
Definition cardF {n : nat} : Fin (S n) -> Fin n + Unit.
Proof.
intro w.
destruct w as [m [k p]].
destruct (decidable_paths_nat m n).
right. apply tt.
left. exists m. exists (pred k).
apply S_inj. refine (_ @ p).
refine ((plus_n_Sm _ _) @ _). f_ap. f_ap. apply Spred.
intro H. apply n0. apply S_inj. refine (_ @ p).
refine ((plus_O_r _) @ _). refine ((plus_n_Sm _ _) @ _). f_ap. f_ap.
apply H^.
Defined.
Lemma plus_cancelR (n m k : nat) : plus m n = plus k n -> m = k.
Proof.
intro H.
apply (plus_cancelL n).
refine ((plus_comm _ _) @ _). refine (H @ _). apply (plus_comm _ _)^.
Defined.
Lemma hprop_lt (n m : nat) : IsHProp (lt n m).
Proof.
apply hprop_allpath. intros x y.
apply path_sigma_hprop.
destruct x as [x p], y as [y p'].
simpl. apply S_inj. apply (plus_cancelL n). apply (p @ p'^).
Defined.
Lemma path_Fin (n : nat) (w w' : Fin n) : (w.1 = w'.1) -> w = w'.
Proof.
intro p.
destruct w as [m w], w' as [m' w'].
simpl. apply path_sigma_uncurried. exists p.
set (H := hprop_lt m' n).
apply path_ishprop.
Defined.
Theorem isequiv_cardF : forall n, IsEquiv (@cardF n).
Proof.
intro n.
simple refine (isequiv_adjointify _ _ _ _).
(* inverse *)
intro H. destruct H as [w | t]. destruct w as [m [k p]].
exists m. exists (S k). refine ((plus_n_Sm _ _)^ @ _). apply (ap S). apply p.
exists n. exists O. apply (plus_1_r _)^.
(* Section *)
intro H. destruct H as [w | t].
(* w : Fin n *)
destruct w as [m [k p]]. unfold cardF. simpl.
destruct (decidable_paths_nat m n).
assert Empty. apply (nat_encode (S k) O). apply (plus_cancelL m).
refine (_ @ (plus_O_r _)). refine (_ @ p0^). apply p. contradiction.
apply (ap inl). apply path_Fin. reflexivity.
(* t : Unit *)
unfold cardF. simpl. destruct (decidable_paths_nat n n).
apply (ap inr). apply contr_unit. contradiction (n0 1).
(* Retraction *)
intro w. destruct w as [m [k p]]. unfold cardF. simpl.
destruct (decidable_paths_nat m n).
apply path_Fin. apply p0^.
apply path_Fin. reflexivity.
Defined.
Lemma eq_lt__lt (n m k : nat) : (n = m) -> (lt m k) -> (lt n k).
Proof.
intros p w.
destruct w as [l q].
exists l. refine (_ @ q). f_ap.
Defined.
Lemma pred_inj (n m : nat) : n <> O -> m <> O -> (pred n = pred m) -> n = m.
Proof.
intros Hn Hm H.
refine ((Spred n Hn)^ @ _). refine (_ @ (Spred m Hm)).
apply (ap S). apply H.
Defined.
Lemma pn_lt_n (n : nat) : n <> O -> (lt (pred n) n).
Proof.
intro H. exists O. refine ((plus_1_r _)^ @ _). apply Spred. apply H.
Defined.
Lemma brck_equiv (A B : Type) : (A <~> B) -> (Brck A <~> Brck B).
Proof.
intro e.
apply equiv_iff_hprop.
intro a'. strip_truncations. apply tr. apply e. apply a'.
intro b'. strip_truncations. apply tr. apply e^-1. apply b'.
Defined.
Theorem brck_functor_prod (A B : Type) : Brck (A * B) <~> Brck A * Brck B.
Proof.
apply equiv_iff_hprop.
intro x. split; strip_truncations; apply tr. apply (fst x). apply (snd x).
intro x. destruct x as [a b]. strip_truncations. apply tr. apply (a, b).
Defined.
(* The induction step of the proof *)
Section ISFAC.
Context {n : nat} {A : Fin (S n) -> Type} {P : forall m, A m -> Type}.
Local Definition A' := A o (@equiv_inv _ _ cardF (isequiv_cardF n)).
Local Definition P' : forall m, A' m -> Type.
Proof.
intros m a.
simple refine (P _ _).
apply (@equiv_inv _ _ cardF (isequiv_cardF n)).
apply m. apply a.
Defined.
Theorem domain_trans `{Funext} :
(forall m, Brck {a : A m & P m a})
<~>
(forall z, Brck {a : A ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z))
& P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) a})
*
(forall z : Unit, Brck {a : A (n; (O; (plus_1_r _)^)) &
P (n; (O; (plus_1_r _)^)) a}).
Proof.
equiv_via (forall z, Brck {a : A' z & P' z a}).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z.
apply brck_equiv.
simple refine (equiv_functor_sigma' _ _).
unfold A'. apply equiv_idmap.
intro a. unfold P'. simpl. apply equiv_idmap.
equiv_via (
(forall z, Brck {a : A' (inl z) & P' (inl z) a})
*
(forall z, Brck {a : A' (inr z) & P' (inr z) a})
).
apply equiv_inverse.
simple refine (equiv_sum_ind _).
apply equiv_functor_prod'; apply equiv_idmap.
Defined.
Theorem codomain_trans `{Funext} :
Brck {g : forall m, A m & forall m, P m (g m)}
<~>
Brck {g : forall z, (A o (@equiv_inv _ _ cardF (isequiv_cardF n)) o inl) z
& forall z,
P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) (g z)}
*
Brck (forall z : Unit, {a : A (n; (O; (plus_1_r _)^)) &
P (n; (O; (plus_1_r _)^)) a}).
Proof.
equiv_via (Brck {g : forall z, A' z & forall z, P' z (g z)}).
apply brck_equiv.
simple refine (equiv_functor_sigma' _ _).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z. apply equiv_idmap.
intro g. simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro z. apply equiv_idmap.
equiv_via (Brck (forall z, {a : A' z & P' z a})).
apply brck_equiv. refine (equiv_sigT_coind _ _).
equiv_via (Brck ((forall z, {a : A' (inl z) & P' (inl z) a})
*
(forall z, {a : A' (inr z) & P' (inr z) a}))).
apply brck_equiv.
apply equiv_inverse. refine (equiv_sum_ind _).
equiv_via (Brck (forall z : Fin n, {a : A' (inl z) & P' (inl z) a})
*
Brck (forall z : Unit, {a : A' (inr z) & P' (inr z) a})).
apply brck_functor_prod.
refine (equiv_functor_prod' _ _).
apply brck_equiv.
unfold A', P'.
apply equiv_inverse.
refine (equiv_sigT_coind _ _).
apply brck_equiv. apply equiv_idmap.
Defined.
End ISFAC.
Theorem finite_AC `{Funext} (n : nat) (A : Fin n -> Type)
(P : forall m, A m -> Type) :
(forall m, Brck {a : A m & P m a})
-> Brck {g : forall m, A m & forall m, P m (g m)}.
Proof.
induction n.
intro H'. apply tr.
exists (fun m : Fin 0 => Empty_rect (fun _ => A m) (cardO m)).
intro m. contradiction (cardO m).
intro f.
apply domain_trans in f.
destruct f as [fn f1].
apply codomain_trans.
split.
apply (IHn _ ((fun z a =>
P ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)) a))).
apply fn.
set (z := tt).
apply f1 in z. strip_truncations. apply tr. intro t. apply z.
Defined.
(**
There's also a shorter proof by way of Lemma 3.8.2. It suffices to show
for all $n : \N$ and $Y : \Fin(n) \to \UU$
%\[
\left(\prd{m_{n} : \Fin(n)} \brck{Y(m_{n})}\right)
\to
\brck{\prd{m_{n} : \Fin(n)} Y(x)}
\]%
Things proceed by induction, as before. For $n \equiv 0$ everything follows
from a contradiction. For the induction step, we can define a new family $Y' :
(\Fin(n) + \unit) \to \UU$ as before. Then
%\[
\prd{m_{n+1} : \Fin(n+1)} \brck{Y(m_{n+1})}
\eqvsym
\prd{z : \Fin(n) + \unit} \brck{Y'(z)}
\eqvsym
\left(\prd{z : \Fin(n)} \brck{Y'(\inl(z))}\right)
\times
\left(\prd{z : \unit} \brck{Y'(\inr(z))}\right)
\]%
and
%\begin{align*}
\brck{\prd{m_{n+1} : \Fin(n+1)} Y(m_{n+1})}
&\eqvsym
\brck{\prd{z : \Fin(n) + \unit} Y'(z)}
\\&\eqvsym
\brck{\left(\prd{z : \Fin(n)} Y'(\inl(z))\right)
\times
\left(\prd{z : \unit} Y'(\inr(z))\right)}
\\&\eqvsym
\brck{\prd{z : \Fin(n)} Y'(\inl(z))}
\times
\brck{\prd{z : \unit} Y'(\inr(z))}
\end{align*}%
As before, we pair the induction hypothesis with a trivially constructed map to
produce the required arrow.
*)
(* the induction step *)
Section ISFAC'.
Context {n : nat} {Y : Fin (S n) -> Type}.
Local Definition Y' := Y o (@equiv_inv _ _ cardF (isequiv_cardF n)).
Theorem domain_trans' `{Funext} :
(forall m, Brck (Y m))
<~>
(forall z, Brck (Y ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z))))
* (forall z : Unit, Brck (Y (n; (O; (plus_1_r _)^)))).
Proof.
equiv_via (forall z, Brck (Y' z)).
simple refine (equiv_functor_forall' _ _).
apply equiv_inverse. apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro b. apply equiv_idmap.
equiv_via ((forall z, Brck (Y' (inl z))) * (forall z, Brck (Y' (inr z)))).
apply equiv_inverse. refine (equiv_sum_ind _).
apply equiv_idmap.
Defined.
Theorem codomain_trans' `{Funext} :
Brck (forall z, Y ((@equiv_inv _ _ cardF (isequiv_cardF n)) (inl z)))
*
Brck (forall z : Unit, Y (n; (O; (plus_1_r _)^)))
<~>
Brck (forall m, Y m).
Proof.
equiv_via (Brck (forall z, Y' (inl z)) * Brck (forall z : Unit, Y' (inr z))).
apply equiv_idmap.
equiv_via (Brck ((forall z, Y' (inl z)) * (forall z, Y' (inr z)))).
apply equiv_inverse. apply brck_functor_prod.
equiv_via (Brck (forall z, Y' z)).
apply brck_equiv. refine (equiv_sum_ind _).
apply brck_equiv. simple refine (equiv_functor_forall' _ _).
apply (BuildEquiv _ _ cardF (isequiv_cardF n)).
intro b. unfold Y'. apply equiv_path.
f_ap. apply eissect.
Defined.
End ISFAC'.
Theorem finite_AC' `{Funext} (n : nat) (Y : Fin n -> Type) :
(forall m, Brck (Y m)) -> Brck (forall m, Y m).
Proof.
induction n.
intro H'. apply tr. intro m. contradiction (cardO m).
intro f.
apply domain_trans' in f. destruct f as [fn f1].
apply codomain_trans'. split.
apply IHn. apply fn.
set (z := tt). apply f1 in z. strip_truncations. apply tr. intro t. apply z.
Defined.
Theorem finite_AC_eqv_finite_AC' `{Funext} :
(forall (n : nat) (A : Fin n -> Type) P,
(forall m, Brck {a : A m & P m a})
->
Brck {g : forall m, A m & forall m, P m (g m)})
<~>
(forall (n : nat) (Y : Fin n -> Type),
(forall m, Brck (Y m)) -> Brck (forall m, Y m)).
Proof.
apply equiv_iff_hprop.
(* forward *)
intros finite_AC n Y f.
transparent assert (e : (
Brck {g : forall m, Y m & forall m, (fun z a => Unit) m (g m)}
<~>
Brck (forall m, Y m)
)).
equiv_via (Brck (forall m, {y : Y m & (fun z a => Unit) m y})).
apply brck_equiv. refine (equiv_sigT_coind _ _).
apply brck_equiv. simple refine (equiv_functor_forall' _ _). apply equiv_idmap.
intro b. apply equiv_sigma_contr. intro y. apply contr_unit.
apply e. clear e.
apply (finite_AC n Y (fun z a => Unit)).
intro m. assert (Brck (Y m)). apply (f m).
strip_truncations. apply tr. exists X. apply tt.
(* back *)
intros finite_AC' n A P f.
transparent assert (e : (
Brck (forall m, (fun x => {a : A x & P x a}) m)
<~>
Brck {g : forall m : Fin n, A m & forall m : Fin n, P m (g m)}
)).
apply brck_equiv.
apply equiv_inverse. refine (equiv_sigT_coind _ _).
apply e. clear e.
apply finite_AC'. apply f.
Defined.
Theorem finite_AC_alt `{Funext} (n : nat) (A : Fin n -> Type)
(P : forall m, A m -> Type) :
(forall m, Brck {a : A m & P m a})
-> Brck {g : forall m, A m & forall m, P m (g m)}.
Proof.
generalize dependent n.
apply finite_AC_eqv_finite_AC'.
apply finite_AC'.
Defined.
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V
`define SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import sub cells.
`include "../u_vpwr_vgnd/sky130_fd_sc_hs__u_vpwr_vgnd.v"
`celldefine
module sky130_fd_sc_hs__einvp (
A ,
TE ,
Z ,
VPWR,
VGND
);
// Module ports
input A ;
input TE ;
output Z ;
input VPWR;
input VGND;
// Local signals
wire u_vpwr_vgnd0_out_A ;
wire u_vpwr_vgnd1_out_TE;
// Name Output Other arguments
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd0 (u_vpwr_vgnd0_out_A , A, VPWR, VGND );
sky130_fd_sc_hs__u_vpwr_vgnd u_vpwr_vgnd1 (u_vpwr_vgnd1_out_TE, TE, VPWR, VGND );
notif1 notif10 (Z , u_vpwr_vgnd0_out_A, u_vpwr_vgnd1_out_TE);
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HS__EINVP_BEHAVIORAL_V |
module TOP (/*AUTOARG*/
// Outputs
SIG_NAMEB, SIG_NAMEA
)
/*AUTOOUTPUT*/
// Beginning of automatic outputs (from unused autoinst outputs)
output [223:0] SIG_NAMEA; // From A of A.v, ...
output [FOO*4-2:0] SIG_NAMEB; // From C of C.v
// End of automatics
/*AUTOINPUT*/
/*AUTOWIRE*/
A A(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[224*1-1:128*1]));
B B(/*AUTOINST*/
// Outputs
.SIG_NAMEA (SIG_NAMEA[127:0]));
C C(/*AUTOINST*/
// Outputs
.SIG_NAMEB (SIG_NAMEB[FOO*4-2*1:0]));
endmodule
module A(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [224*1-1:128*1] SIG_NAMEA;
//output [223:128] SIG_NAMEA;
endmodule
module B(/*AUTOARG*/
// Outputs
SIG_NAMEA
);
output [127:0] SIG_NAMEA;
endmodule
module C(/*AUTOARG*/
// Outputs
SIG_NAMEB
);
output [FOO*4-2*1:0] SIG_NAMEB;
endmodule
|
`include "REG.v"
`include "CMD.v"
`include "BloqueDATA.v"
`include "modules/DMA.v"
module SD_host (clk_host,
reset_host,
io_enable_cmd,
CMD_PIN_IN,
CMD_PIN_OUT,
clk_SD,
data_in_register,
data_out_register,
req_register,
ack_register,
addres_register,
rw_register,
DATA_PIN_IN,
DATA_PIN_OUT,
IO_enable_Phy_SD_CARD,
pad_enable_Phy_PAD,
pad_state_Phy_PAD,
cmd_reg_write,
cmd_reg_read,
Continue,
descriptor_table,
TRAN,
STOP);
//señales del host
input wire clk_host, reset_host;
input wire DATA_PIN_IN;
output wire DATA_PIN_OUT;
output wire IO_enable_Phy_SD_CARD;
//outputs para el estado del PAD
output wire pad_enable_Phy_PAD;
output wire pad_state_Phy_PAD;
//señales del CMD
input wire CMD_PIN_IN;
output wire io_enable_cmd, CMD_PIN_OUT;
//señales del register
input wire [31:0]data_in_register;
output wire [31:0] data_out_register;
input wire req_register;
input wire ack_register;
input wire [4:0]addres_register;
input wire rw_register;
// señales de DMA
input wire cmd_reg_write;
input wire cmd_reg_read;
input wire Continue;
input wire [6:0][85:0] descriptor_table;
input wire TRAN;
input wire STOP;
//señales compartidas del SD
input wire clk_SD;
//cables de conexion entre DMA y CMD
wire new_command;
//cables de conexion entre REG y CMD
wire [31:0]cmd_argument;
wire [5:0]cmd_index;
wire [127:0]response;
wire cmd_complete, cmd_index_error;
assign cmd_argument = bloque_registers.Argument;
assign cmd_index = bloque_registers.cmd_index;
assign bloque_registers.cmd_complete = cmd_complete;
assign bloque_registers.cmd_index_error = cmd_index_error;
//wires entre REGS y DATA
wire [15:0] timeout_Reg_Regs_DATA;
wire writeRead_Regs_DATA;
wire [3:0] blockCount_Regs_DATA;
wire multipleData_Regs_DATA;
wire timeout_enable_Regs_DATA;
//wires entre DMA y DATA
wire transfer_complete_DATA_DMA;
assign timeout_Reg_Regs_DATA = bloque_registers.Timeout_Reg;
assign writeRead_Regs_DATA = bloque_registers.writeRead;
assign blockCount_Regs_DATA = bloque_registers.block_count;
assign multipleData_Regs_DATA = bloque_registers.multipleData;
assign timeout_enable_Regs_DATA = bloque_registers.timeout_enable;
// wire entre DMA y FIFO
wire FIFO_EMPTY_DMA;
wire FIFO_FULL_DMA;
wire [63:0] system_address;
wire writing_mem; // 1 if dir = 0 and TFC = 0
wire reading_mem; //
wire reading_fifo;
wire writing_fifo;
wire [5:0] next_descriptor_index;
reg [5:0] descriptor_index;
always @(posedge clk_host) begin
descriptor_index <= next_descriptor_index;
end
DMA bloqueDMA(reset,
clk_host,
transfer_complete_DATA_DMA,
cmd_reg_write,
cmd_reg_read,
Continue,
TRAN,
STOP,
FIFO_EMPTY_DMA,
FIFO_FULL_DMA,
descriptor_table [0][85:22], // data_address
descriptor_table [0][20:5], // length
descriptor_index,
descriptor_table [0][4], //act1
descriptor_table [0][3], //act2
descriptor_table [0][2], // END
descriptor_table [0][1], // valid
descriptor_table [0][0], // dir
new_command, // To CMD block
system_address,
writing_mem, // 1 if dir = 0 and TFC = 0
reading_mem, //
reading_fifo,
writing_fifo,
next_descriptor_index);
CMD bloque_CMD(clk_host, reset_host, new_command, cmd_argument, cmd_index, cmd_complete, cmd_index_error, response, CMD_PIN_OUT, IO_enable_pin, CMD_PIN_IN, clk_SD);
REG bloque_registers(clk_host, rw_register, addres_register, data_in_register, data_out_register);
//Bloque de DATA
BloqueDATA Data_Control(
.CLK(clk_host),
.SD_CLK(clk_SD),
.RESET_L(reset_host),
.timeout_Reg_Regs_DATA(timeout_Reg_Regs_DATA),
.writeRead_Regs_DATA(writeRead_Regs_DATA),
.blockCount_Regs_DATA(blockCount_Regs_DATA),
.multipleData_Regs_DATA(multipleData_Regs_DATA),
.timeout_enable_Regs_DATA(timeout_enable_Regs_DATA),
//.FIFO_OK_FIFO_DATA(),
//.[31:0] dataFromFIFO_FIFO_Phy(),
//.New_DAT_DMA_DATA(),
//.DATA_PIN_IN(DATA_PIN_IN),
//.writeFIFO_enable_Phy_FIFO(),
//.readFIFO_enable_Phy_FIFO(),
//.[31:0] dataReadToFIFO_Phy_FIFO(),
.transfer_complete_DATA_DMA(transfer_complete_DATA_DMA),
.IO_enable_Phy_SD_CARD(IO_enable_Phy_SD_CARD),
.DATA_PIN_OUT(DATA_PIN_OUT),
.pad_state_Phy_PAD(pad_state_Phy_PAD),
.pad_enable_Phy_PAD(pad_enable_Phy_PAD)
);
endmodule // SD_host
|
module fifo_empty_block (/*AUTOARG*/
// Outputs
rd_fifo_empty, rd_addr, rd_gray_pointer,
// Inputs
reset, rd_clk, rd_wr_gray_pointer, rd_read
);
parameter AW = 2; // Number of bits to access all the entries
//##########
//# INPUTS
//##########
input reset;
input rd_clk;
input [AW:0] rd_wr_gray_pointer;//from other clock domain
input rd_read;
//###########
//# OUTPUTS
//###########
output rd_fifo_empty;
output [AW-1:0] rd_addr;
output [AW:0] rd_gray_pointer;
//#########
//# REGS
//#########
reg [AW:0] rd_gray_pointer;
reg [AW:0] rd_binary_pointer;
reg rd_fifo_empty;
//##########
//# WIRES
//##########
wire rd_fifo_empty_next;
wire [AW:0] rd_binary_next;
wire [AW:0] rd_gray_next;
//Counter States
always @(posedge rd_clk or posedge reset)
if(reset)
begin
rd_binary_pointer[AW:0] <= {(AW+1){1'b0}};
rd_gray_pointer[AW:0] <= {(AW+1){1'b0}};
end
else if(rd_read)
begin
rd_binary_pointer[AW:0] <= rd_binary_next[AW:0];
rd_gray_pointer[AW:0] <= rd_gray_next[AW:0];
end
//Read Address
assign rd_addr[AW-1:0] = rd_binary_pointer[AW-1:0];
//Updating binary pointer
assign rd_binary_next[AW:0] = rd_binary_pointer[AW:0] +
{{(AW){1'b0}},rd_read};
//Gray Pointer Conversion (for more reliable synchronization)!
assign rd_gray_next[AW:0] = {1'b0,rd_binary_next[AW:1]} ^
rd_binary_next[AW:0];
//# FIFO empty indication
assign rd_fifo_empty_next = (rd_gray_next[AW:0]==rd_wr_gray_pointer[AW:0]);
always @ (posedge rd_clk or posedge reset)
if(reset)
rd_fifo_empty <= 1'b1;
else
rd_fifo_empty <= rd_fifo_empty_next;
endmodule // fifo_empty_block
/*
Copyright (C) 2013 Adapteva, Inc.
Contributed by Andreas Olofsson, Roman Trogan <[email protected]>
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program (see the file COPYING). If not, see
<http://www.gnu.org/licenses/>.
*/
|
/**********************************************************************
date:2016/3/26
designer:ZhaiShaoMin
project:ring network multicore
module name:tb_arbiter_OUT_rep
module function: figure out what's wrong with it
***********************************************************************/
`timescale 1ns/1ps
module tb_arbiter_for_OUT_req();
//input
reg clk;
reg rst;
reg OUT_req_rdy;
reg v_ic_req;
reg v_dc_req;
reg v_mem_req;
reg [1:0] ic_req_ctrl;
reg [1:0] dc_req_ctrl;
reg [1:0] mem_req_ctrl;
//output
wire ack_OUT_req;
wire ack_ic_req;
wire ack_dc_req;
wire ack_mem_req;
wire [2:0] select; // select 1/3
arbiter_for_OUT_req uut(//input
.clk(clk),
.rst(rst),
.OUT_req_rdy(OUT_req_rdy),
.v_ic_req(v_ic_req),
.v_dc_req(v_dc_req),
.v_mem_req(v_mem_req),
.ic_req_ctrl(ic_req_ctrl),
.dc_req_ctrl(dc_req_ctrl),
.mem_req_ctrl(mem_req_ctrl),
//output
.ack_OUT_req(ack_OUT_req),
.ack_ic_req(ack_ic_req),
.ack_dc_req(ack_dc_req),
.ack_mem_req(ack_mem_req),
.select(select)
);
integer log_file;
//define task for compare expected outputs with actural outputs
task cmp_outputs;
input exp_ack_OUT_req;
input exp_ack_ic_req;
input exp_ack_dc_req;
input exp_ack_mem_req;
input [2:0] exp_select;
begin
$display("Time:%t\n",$time);
$fdisplay (log_file, "Time: %t\n", $time);
if (ack_OUT_req != exp_ack_OUT_req)
begin
$display("ERROR: Invalid ack_OUT_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
$fdisplay(log_file,"ERROR: Invalid ack_OUT_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_OUT_req,ack_OUT_req);
end
if (ack_ic_req != exp_ack_ic_req)
begin
$display("ERROR: Invalid ack_ic_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
$fdisplay(log_file,"ERROR: Invalid ack_ic_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_ic_req,ack_ic_req);
end
if (ack_dc_req != exp_ack_dc_req)
begin
$display("ERROR: Invalid ack_dc_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
$fdisplay(log_file,"ERROR: Invalid ack_dc_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_dc_req,ack_dc_req);
end
if (ack_mem_req != exp_ack_mem_req)
begin
$display("ERROR: Invalid ack_mem_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
$fdisplay(log_file,"ERROR: Invalid ack_mem_req\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_ack_mem_req,ack_mem_req);
end
if (select != exp_select)
begin
$display("ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
$fdisplay(log_file,"ERROR: Invalid select\n \t Expected: 0x%x \n \t Acutal: 0x%x", exp_select,select);
end
if((ack_OUT_req != exp_ack_OUT_req)&&
(ack_ic_req != exp_ack_ic_req)&&
(ack_dc_req != exp_ack_dc_req)&&
(ack_mem_req != exp_ack_mem_req)&&
(select != exp_select))
begin
$display("passed test!");
$fdisplay(log_file,"passed test!");
end
end
endtask
//initial inputs
initial begin
clk=1'b0;
rst=1'b1;
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b00;
mem_req_ctrl=2'b00;
log_file=$fopen("log_arbiter_for_OUT_req.txt");
end
`define clk_step #14;
always #7 clk=~clk;
//////////////////////////////////////////////////////////
///////////initial actural test : arbiter_for_OUT_req ////
initial begin
`clk_step
$display("TEST BEGIN.......");
$fdisplay(log_file,"TEST BEGIN.......");
rst=1'b0;
`clk_step
///////////////////////////////////////////////////////////////
//First case: v_ic_req ,v_dc_req and v_mem_req are all valid///
$display("First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$fdisplay(log_file,"First case: v_ic_req ,v_dc_req and v_mem_req are all valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b0;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("2nd try : ic should win! ");
$fdisplay(log_file,"2nd try : ic should win!");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("3rd try : ic should win! ");
$fdisplay(log_file,"3rd try : ic should win!");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("last try : ic should finish ! ");
$fdisplay(log_file,"last try : ic should finish !");
OUT_req_rdy=1'b1;
v_ic_req=1'b1;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b11;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
/* `clk_step
$display("last try :just test if ic has finish and mem win ! ");
$fdisplay(log_file,"last try : if ic has finish and mem win !");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
*/
/////////////////////////////////////////////////////////////////
///////2nd case :both mem and dc are valid! and mem will win!////
/////////////////////////////////////////////////////////////////
rst=1'b1;
#7;
rst=1'b0;
#7;
//clk_step
$display("2nd case: v_dc_req and v_mem_req are valid");
$fdisplay(log_file,"2nd case: v_dc_req and v_mem_req are valid");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b11;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/////////////////////////////////////////////////////////////////////////////
////3rd case: both mem and dc are valid but it's dc's turn to transfer msg///
`clk_step
$display("3rd case: both mem and dc are valid but it's dc's turn to transfer msg\n also test for last try error");
$fdisplay(log_file,"3rd case: both mem and dc are valid but it's dc's turn to transfer msg\n also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
// req fifo is not ready
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b1;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
///////////////////////////////////////////////////////////////
////4th case : only dc is valid! /////
`clk_step
$display("4th case : only dc is valid!\n also test for last try error");
$fdisplay(log_file,"4th case : only dc is valid!\n also test for last try error");
$display("First try");
$fdisplay(log_file,"First try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b00;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
//req fifo is not ready
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b10;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("last try");
$fdisplay(log_file,"last try");
OUT_req_rdy=1'b1;
v_ic_req=1'b0;
v_dc_req=1'b1;
v_mem_req=1'b0;
ic_req_ctrl=2'b00;
dc_req_ctrl=2'b11;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b1, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b010 //exp_select;
);
////////////////////////////////////////////////////////////
////5th case: only mem is valid !///////////////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b10;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b0;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b11;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b1, //exp_ack_mem_req;
3'b001 //exp_select;
);
/////////////////////////////////////////////////
////both mem and ic are valid ///////////////////
`clk_step
$display("1st try");
$fdisplay(log_file,"1st try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b01;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
/// req fifo is not ready!
`clk_step
$display("2nd try");
$fdisplay(log_file,"2nd try");
OUT_req_rdy=1'b0; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b10;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b0, //exp_ack_OUT_req;
1'b0, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b000 //exp_select;
);
`clk_step
$display("3rd try");
$fdisplay(log_file,"3rd try");
OUT_req_rdy=1'b1; //doesn't matter
v_ic_req=1'b1;
v_dc_req=1'b0;
v_mem_req=1'b1;
ic_req_ctrl=2'b11;
dc_req_ctrl=2'b01;
mem_req_ctrl=2'b01;
cmp_outputs(1'b1, //exp_ack_OUT_req;
1'b1, //exp_ack_ic_req;
1'b0, //exp_ack_dc_req;
1'b0, //exp_ack_mem_req;
3'b100 //exp_select;
);
`clk_step
$display("FINISH TEST!");
$fdisplay(log_file,"FINISH TEST!");
$stop;
end
endmodule
|
/*WARNING: ONLY SAME EDGE SUPPORTED FOR NOW*/
//D1,D2 sampled on rising edge of C
module ODDR (/*AUTOARG*/
// Outputs
Q,
// Inputs
C, CE, D1, D2, R, S
);
parameter DDR_CLK_EDGE=0; //clock recovery mode
parameter INIT=0; //Q init value
parameter SRTYPE=0;//"SYNC", "ASYNC"
input C; // Clock input
input CE; // Clock enable input
input D1; // Data input1
input D2; // Data input2
input R; // Reset (depends on SRTYPE)
input S; // Active high asynchronous pin
output Q; // Data Output that connects to the IOB pad
reg Q1,Q2;
reg Q2_reg;
//Generate different logic based on parameters
//Only doing same edge and async reset for now
always @ (posedge C or posedge R)
if (R)
Q1 <= 1'b0;
else
Q1 <= D1;
always @ (posedge C or posedge R)
if (R)
Q2 <= 1'b0;
else
Q2 <= D2;
always @ (negedge C or posedge R)
if (R)
Q2_reg <= 1'b0;
else
Q2_reg <= Q2;
assign Q = C ? Q1 : Q2_reg;
endmodule // ODDR
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
// Date : Sun May 21 18:13:28 2017
// Host : GILAMONSTER running 64-bit major release (build 9200)
// Command : write_verilog -force -mode synth_stub -rename_top system_ov7670_controller_0_0 -prefix
// system_ov7670_controller_0_0_ system_ov7670_controller_0_0_stub.v
// Design : system_ov7670_controller_0_0
// Purpose : Stub declaration of top-level module interface
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
// This empty module with port declaration file causes synthesis tools to infer a black box for IP.
// The synthesis directives are for Synopsys Synplify support to prevent IO buffer insertion.
// Please paste the declaration into a Verilog source file or add the file as an additional source.
(* x_core_info = "ov7670_controller,Vivado 2016.4" *)
module system_ov7670_controller_0_0(clk, resend, config_finished, sioc, siod, reset,
pwdn, xclk)
/* synthesis syn_black_box black_box_pad_pin="clk,resend,config_finished,sioc,siod,reset,pwdn,xclk" */;
input clk;
input resend;
output config_finished;
output sioc;
inout siod;
output reset;
output pwdn;
output xclk;
endmodule
|
//-----------------------------------------------------------------------------
// File : master.v
// Creation date : 15.05.2017
// Creation time : 11:13:06
// Description : A component containing two wishbone master interfaces and thus two wishbone master module instantiations. Its operation is governed by external start signal, and will send a done signal after both master modules have sent and received everything.
// Created by : TermosPullo
// Tool : Kactus2 3.4.109 32-bit
// Plugin : Verilog generator 2.0e
// This file was generated based on IP-XACT component tut.fi:peripheral.logic:wb_dual_master:1.0
// whose XML file is D:/kactus2Repos/ipxactexamplelib/tut.fi/peripheral.logic/wb_dual_master/1.0/wb_dual_master.1.0.xml
//-----------------------------------------------------------------------------
module master #(
parameter ADDR_WIDTH = 16, // The width of the address.
parameter MASTER_1_BASE_ADDRESS = 64, // The first referred address of master1.
parameter DATA_COUNT = 8, // How many values there are in the register array.
parameter DATA_WIDTH = 16, // The width of the both transferred and inputted data.
parameter MASTER_0_BASE_ADDRESS = 0, // The first referred address of master0.
parameter AUB = 8, // Addressable unit bits of the memory.
parameter VERILOG_SPECIFIC = 'hEE // A verilog specific parameter
) (
// Interface: master_0
input ack_i_0, // Slave asserts acknowledge.
input [DATA_WIDTH-1:0] dat_i_0, // Data from slave to master.
input err_i_0, // Indicates abnormal cycle termination.
output [ADDR_WIDTH-1:0] adr_o_0, // The address of the data.
output cyc_o_0, // Asserted by master for transfer.
output [DATA_WIDTH-1:0] dat_o_0, // Data from master to slave.
output stb_o_0, // Asserted by master for transfer.
output we_o_0, // Write = 1, Read = 0.
// Interface: master_1
input ack_i_1, // Slave asserts acknowledge.
input [DATA_WIDTH-1:0] dat_i_1, // Data from slave to master.
input err_i_1, // Indicates abnormal cycle termination.
output [ADDR_WIDTH-1:0] adr_o_1, // The address of the data.
output cyc_o_1, // Asserted by master for transfer.
output [DATA_WIDTH-1:0] dat_o_1, // Data from master to slave.
output stb_o_1, // Asserted by master for transfer.
output we_o_1, // Write = 1, Read = 0.
// Interface: wb_system
input clk_i, // The mandatory clock, as this is synchronous logic.
input rst_i, // The mandatory reset, as this is synchronous logic.
// These ports are not in any interface
input start, // Input used to signal that is is ok to start the masters.
output done // Output used to signal that the masters are done sending.
);
// WARNING: EVERYTHING ON AND ABOVE THIS LINE MAY BE OVERWRITTEN BY KACTUS2!!!
// Needs "done" from both masters.
wire done_0;
wire done_1;
assign done = done_0 & done_1;
wb_master #(
.DATA_COUNT (DATA_COUNT),
.BASE_ADDRESS (MASTER_0_BASE_ADDRESS),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
wb_master_0(
.clk_i(clk_i),
.rst_i(rst_i),
.cyc_o(cyc_o_0),
.stb_o(stb_o_0),
.ack_i(ack_i_0),
.we_o(we_o_0),
.dat_o(dat_o_0),
.dat_i(dat_i_0),
.adr_o(adr_o_0),
.err_i(err_i_0),
.start(start),
.done(done_0)
);
wb_master #(
.DATA_COUNT (DATA_COUNT),
.BASE_ADDRESS (MASTER_1_BASE_ADDRESS),
.DATA_WIDTH (DATA_WIDTH),
.ADDR_WIDTH (ADDR_WIDTH))
wb_master_1(
.clk_i(clk_i),
.rst_i(rst_i),
.cyc_o(cyc_o_1),
.stb_o(stb_o_1),
.ack_i(ack_i_1),
.we_o(we_o_1),
.dat_o(dat_o_1),
.dat_i(dat_i_1),
.adr_o(adr_o_1),
.err_i(err_i_1),
.start(start),
.done(done_1)
);
endmodule
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////////////////////////////////////////////////////////////////////////////////
// Original Author: Schuyler Eldridge
// Contact Point: Schuyler Eldridge ([email protected])
// div_pipelined.v
// Created: 4.3.2012
// Modified: 4.5.2012
//
// Testbench for div_pipelined.v
//
// Copyright (C) 2012 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module t_div_pipelined();
reg clk, start, reset_n;
reg [7:0] dividend, divisor;
wire data_valid, div_by_zero;
wire [7:0] quotient, quotient_correct;
parameter
BITS = 8;
div_pipelined
#(
.BITS(BITS)
)
div_pipelined
(
.clk(clk),
.reset_n(reset_n),
.dividend(dividend),
.divisor(divisor),
.quotient(quotient),
.div_by_zero(div_by_zero),
// .quotient_correct(quotient_correct),
.start(start),
.data_valid(data_valid)
);
initial begin
#10 reset_n = 0;
#50 reset_n = 1;
#1
clk = 0;
dividend = -1;
divisor = 127;
#1000 $finish;
end
// always
// #20 dividend = dividend + 1;
always begin
#10 divisor = divisor - 1; start = 1;
#10 start = 0;
end
always
#5 clk = ~clk;
endmodule
|
/*
* Copyright (c) 2000 Stephen Williams ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This program is designed to test non-constant bit selects in the
* concatenated l-value of procedural assignment.
*/
module main;
reg [3:0] vec;
reg a;
integer i;
initial begin
vec = 4'b0000;
a = 0;
if (vec !== 4'b0000) begin
$display("FAILED -- initialized vec to %b", vec);
$finish;
end
for (i = 0 ; i < 4 ; i = i + 1) begin
#1 { a, vec[i] } <= 2'b11;
end
#1 if (vec !== 4'b1111) begin
$display("FAILED == vec (%b) is not 1111", vec);
$finish;
end
if (a !== 1'b1) begin
$display("FAILED -- a (%b) is not 1", a);
$finish;
end
$display("PASSED");
end // initial begin
endmodule // main
|
/////////////////////////////////////////////////////////////////////////
//
// pLIB
// D-FLIP-FLOPS
/////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////
// p_I_FD FD error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD (Q,D,C,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
defparam FD_z.INIT=INIT;
FD FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD FD error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD (Q,D,C,E);
parameter INIT = 1'b0;
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FD_1 FD_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Dtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Q),.D(Dtemp),.C(C));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FD_1 FD_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FD_1 (Q,D,C,E);
output Q;
input D;
input C;
input E;
wire Qtemp;
// Xilinx FD instance
FD_1 FD_z (.Q(Qtemp),.D(D),.C(C));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC FDC error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC FDC error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDC_1 FDC_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Dtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDC_1 FDC_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDC_1 (Q,D,C,CLR,E);
output Q;
input D;
input C;
input E;
input CLR;
wire Qtemp;
// Xilinx FD instance
FDC_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE FDCE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCE_1 FDCE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCE_1 FDCE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCE_1 (Q,D,C,CLR,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP FDCP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP FDCP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCP_1 FDCP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCP_1 FDCP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCP_1 (Q,D,C,CLR,PRE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDCP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE FDCPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE FDCPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDCPE_1 FDCPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDCPE_1 FDCPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDCPE_1 (Q,D,C,CLR,PRE,CE,E);
output Q;
input D;
input C;
input E;
input CLR;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDCPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CLR(CLR),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE FDE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE FDE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDE_1 FDE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Dtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDE_1 FDE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDE_1 (Q,D,C,CE,E);
output Q;
input D;
input C;
input E;
input CE;
wire Qtemp;
// Xilinx FD instance
FDE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP FDP error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP FDP error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDP_1 FDP_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Dtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDP_1 FDP_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDP_1 (Q,D,C,PRE,E);
output Q;
input D;
input C;
input E;
input PRE;
wire Qtemp;
// Xilinx FD instance
FDP_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE FDPE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE FDPE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDPE_1 FDPE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Dtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDPE_1 FDPE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDPE_1 (Q,D,C,PRE,CE,E);
output Q;
input D;
input C;
input E;
input PRE;
input CE;
wire Qtemp;
// Xilinx FD instance
FDPE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.PRE(PRE),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR FDR error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR FDR error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR (Q,D,C,R,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
defparam FD_z.INIT=INIT;
// Xilinx FD instance
FDR FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDR_1 FDR_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Dtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDR_1 FDR_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDR_1 (Q,D,C,R,E);
output Q;
input D;
input C;
input E;
input R;
wire Qtemp;
// Xilinx FD instance
FDR_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE FDRE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE FDRE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE (Q,D,C,R,CE,E);
parameter INIT=1'b0;
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE #(.INIT(INIT)) FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRE_1 FDRE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRE_1 FDRE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRE_1 (Q,D,C,R,CE,E);
output Q;
input D;
input C;
input E;
input R;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS FDRS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRS_1 FDRS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Dtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRS_1 FDRS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRS_1 (Q,D,C,R,S,E);
output Q;
input D;
input C;
input E;
input R;
input S;
wire Qtemp;
// Xilinx FD instance
FDRS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE FDRS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE FDRSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDRSE_1 FDRSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDRSE_1 FDRSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDRSE_1 (Q,D,C,R,S,CE,E);
output Q;
input D;
input C;
input E;
input R;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDRSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.R(R),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS FDS error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS FDS error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDS_1 FDS_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Dtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDS_1 FDS_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDS_1 (Q,D,C,S,E);
output Q;
input D;
input C;
input E;
input S;
wire Qtemp;
// Xilinx FD instance
FDS_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE FDSE error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE FDSE error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_I_FDSE_1 FDSE_1 error at input
/////////////////////////////////////////////////////////////////////////
module p_I_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Dtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Q),.D(Dtemp),.C(C),.S(S),.CE(CE));
// Error injection
and (Dtemp,D,E);
endmodule
/////////////////////////////////////////////////////////////////////////
// p_O_FDSE_1 FDSE_1 error at output
/////////////////////////////////////////////////////////////////////////
module p_O_FDSE_1 (Q,D,C,S,CE,E);
output Q;
input D;
input C;
input E;
input S;
input CE;
wire Qtemp;
// Xilinx FD instance
FDSE_1 FD_z (.Q(Qtemp),.D(D),.C(C),.S(S),.CE(CE));
// Error injection
and (Q,Qtemp,E);
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V
`define SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V
/**
* dlrtp: Delay latch, inverted reset, non-inverted enable,
* single output.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dlatch_pr/sky130_fd_sc_hdll__udp_dlatch_pr.v"
`celldefine
module sky130_fd_sc_hdll__dlrtp (
Q ,
RESET_B,
D ,
GATE
);
// Module ports
output Q ;
input RESET_B;
input D ;
input GATE ;
// Local signals
wire RESET;
wire buf_Q;
// Delay Name Output Other arguments
not not0 (RESET , RESET_B );
sky130_fd_sc_hdll__udp_dlatch$PR `UNIT_DELAY dlatch0 (buf_Q , D, GATE, RESET );
buf buf0 (Q , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__DLRTP_FUNCTIONAL_V |
// file: clk_wiz_v3_6_tb.v
//
// (c) Copyright 2008 - 2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//----------------------------------------------------------------------------
// Clocking wizard demonstration testbench
//----------------------------------------------------------------------------
// This demonstration testbench instantiates the example design for the
// clocking wizard. Input clocks are toggled, which cause the clocking
// network to lock and the counters to increment.
//----------------------------------------------------------------------------
`timescale 1ps/1ps
`define wait_lock @(posedge dut.clknetwork.dcm_sp_inst.LOCKED)
module clk_wiz_v3_6_tb ();
// Clock to Q delay of 100ps
localparam TCQ = 100;
// timescale is 1ps/1ps
localparam ONE_NS = 1000;
localparam PHASE_ERR_MARGIN = 100; // 100ps
// how many cycles to run
localparam COUNT_PHASE = 1024;
// we'll be using the period in many locations
localparam time PER1 = 20.0*ONE_NS;
localparam time PER1_1 = PER1/2;
localparam time PER1_2 = PER1 - PER1/2;
// Declare the input clock signals
reg CLK_IN1 = 1;
// The high bit of the sampling counter
wire COUNT;
reg COUNTER_RESET = 0;
wire [1:1] CLK_OUT;
//Freq Check using the M & D values setting and actual Frequency generated
// Input clock generation
//------------------------------------
always begin
CLK_IN1 = #PER1_1 ~CLK_IN1;
CLK_IN1 = #PER1_2 ~CLK_IN1;
end
// Test sequence
reg [15*8-1:0] test_phase = "";
initial begin
// Set up any display statements using time to be readable
$timeformat(-12, 2, "ps", 10);
COUNTER_RESET = 0;
test_phase = "wait lock";
`wait_lock;
#(PER1*6);
COUNTER_RESET = 1;
#(PER1*20)
COUNTER_RESET = 0;
test_phase = "counting";
#(PER1*COUNT_PHASE);
$display("SIMULATION PASSED");
$display("SYSTEM_CLOCK_COUNTER : %0d\n",$time/PER1);
$finish;
end
// Instantiation of the example design containing the clock
// network and sampling counters
//---------------------------------------------------------
clk_wiz_v3_6_exdes
#(
.TCQ (TCQ)
) dut
(// Clock in ports
.CLK_IN1 (CLK_IN1),
// Reset for logic in example design
.COUNTER_RESET (COUNTER_RESET),
.CLK_OUT (CLK_OUT),
// High bits of the counters
.COUNT (COUNT));
// Freq Check
endmodule
|
module qsys_serial_device#(
parameter address_size=8)(
// Qsys bus interface
input rsi_MRST_reset,
input csi_MCLK_clk,
input [31:0] avs_ctrl_writedata,
output reg[31:0] avs_ctrl_readdata,
input [3:0] avs_ctrl_byteenable,
input [7:0] avs_ctrl_address,
input avs_ctrl_write,
input avs_ctrl_read,
input avs_ctrl_chipselect,
output reg avs_ctrl_waitrequest,
output reg avs_ctrl_readdatavalid,
// Qsys serial interface
output reg sdo,
input sdi,
output clk,
output reg sle,
input srdy
);
reg [64:0] data_buffer;
assign clk = csi_MCLK_clk;
parameter initial_state = 8'd0;
parameter bus_data_wait = initial_state+8'd1;
parameter bus_data_ready = bus_data_wait+8'd1;
parameter bus_transmit_start = bus_data_ready + 8'd1;
parameter bus_transmit_ready = bus_transmit_start + 8'd64;
parameter bus_transmit_finish = bus_transmit_ready + 8'd1;
parameter bus_ready_wait = bus_transmit_finish + 8'd1;
parameter bus_transmit_back = bus_ready_wait + 8'd1;
parameter bus_data_read = bus_transmit_back + 8'd1;
parameter bus_data_read_finish = bus_data_read + 8'd2;
reg [7:0] state;
reg [7:0] nextstate;
always@(posedge csi_MCLK_clk or posedge rsi_MRST_reset)
begin
if (rsi_MRST_reset)
state <= initial_state;
else
state <= nextstate;
end
always@(state or srdy or avs_ctrl_write or avs_ctrl_read)
begin
case(state)
initial_state: nextstate <= bus_data_wait;
bus_data_wait: begin
if(avs_ctrl_write == 1'b1 || avs_ctrl_read == 1'b1)
begin
if(avs_ctrl_chipselect == 1'b1)
nextstate <= bus_data_ready;
else
nextstate <= bus_data_wait;
end
else
nextstate <= bus_data_wait;
end
bus_data_ready: nextstate <= bus_transmit_start;
bus_transmit_start: nextstate <= state + 1;
bus_transmit_ready: nextstate <= bus_transmit_finish;
bus_transmit_finish: nextstate <= bus_ready_wait;
bus_ready_wait:
begin
if(srdy == 1'b1)
nextstate <= bus_transmit_back;
else
nextstate <= bus_ready_wait;
end
bus_transmit_back:
begin
if(srdy == 1'b0)
nextstate <= bus_data_read;
else
nextstate <= bus_transmit_back;
end
bus_data_read: nextstate <= state +1;
bus_data_read_finish: nextstate <= bus_data_wait;
default: nextstate <= state + 1;
endcase
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_wait)
begin
data_buffer[63:32] <= avs_ctrl_address;
if (avs_ctrl_write == 1'b1)
begin
data_buffer[64] <= 1'b1; //write
data_buffer[31:0] <= avs_ctrl_writedata;
end
else if (avs_ctrl_read == 1'b1)
begin
data_buffer[64] <= 1'b0; //read
data_buffer[31:0] <= 32'd0;
end
end
else if (state >= bus_transmit_start && state <= bus_transmit_ready)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
sdo <= data_buffer[64];
end
else if (state == bus_transmit_back)
begin
integer i;
for(i=0;i<64;i=i+1)
data_buffer[i+1] <= data_buffer[i];
data_buffer[0]<= sdi;
end
end
always@(posedge csi_MCLK_clk)
begin
if (state >= bus_data_ready && state < bus_transmit_ready)
sle <= 1;
else
sle <= 0;
end
always@(state)
begin
if (state >= bus_data_ready && state <= bus_data_read)
avs_ctrl_waitrequest = 1'b1;
else
avs_ctrl_waitrequest = 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read )
avs_ctrl_readdatavalid <= 1'b1;
else
avs_ctrl_readdatavalid <= 1'b0;
end
always@(posedge csi_MCLK_clk)
begin
if (state == bus_data_read)
begin
avs_ctrl_readdata <= data_buffer[31:0];
end
end
endmodule |
// Directive indicates that 1ns is the time period used when specifying delays
// (i.e., #10 means 10ns); 100ps is the smallest unit of time precision that
// will be simulated (100ps = .1ns; thus #.1 is meaningful, #.00001 is equivalent
// to #0)
`timescale 1ns / 100ps
module testbench ();
reg clk;
reg reset_;
wire [7:0] led;
// Create an instance of the circuit under test
knightrider knightrider_0 (
.clk(clk),
.reset_(reset_),
.led(led)
);
// Initialize the clock signal to zero; drive reset_ active (low) for the
// first 100ns of the simulation.
initial begin
clk <= 1'b0;
reset_ <= 1'b0;
#100; reset_ <= 1'b1;
end
// Stop the simulation after 1100ms; note that simulations can run indefinitely
// (with waveforms loaded incrementally in the viewer.) Press ctrl-c to break
// iverilog, then enter '$finish' to stop the simulation.
initial begin
#1100000000 $finish;
end
// Toggle the clock every 31.25ns (32 MHz frequency)
initial forever begin
#31.25; clk <= ~clk;
end
// Produce a waveform output of this simulation
initial begin
$dumpfile("waveform.vcd");
$dumpvars();
end
always@ (led)
$display("%t LEDs changed to %b", $time, led);
endmodule
|
`define ADDER_WIDTH 010
`define DUMMY_WIDTH 128
`define 2_LEVEL_ADDER
module adder_tree_top (
clk,
isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1,
sum,
);
input clk;
input [`ADDER_WIDTH+0-1:0] isum0_0_0_0, isum0_0_0_1, isum0_0_1_0, isum0_0_1_1, isum0_1_0_0, isum0_1_0_1, isum0_1_1_0, isum0_1_1_1;
output [`ADDER_WIDTH :0] sum;
reg [`ADDER_WIDTH :0] sum;
wire [`ADDER_WIDTH+3-1:0] sum0;
wire [`ADDER_WIDTH+2-1:0] sum0_0, sum0_1;
wire [`ADDER_WIDTH+1-1:0] sum0_0_0, sum0_0_1, sum0_1_0, sum0_1_1;
reg [`ADDER_WIDTH+0-1:0] sum0_0_0_0, sum0_0_0_1, sum0_0_1_0, sum0_0_1_1, sum0_1_0_0, sum0_1_0_1, sum0_1_1_0, sum0_1_1_1;
adder_tree_branch L1_0(sum0_0, sum0_1, sum0 );
defparam L1_0.EXTRA_BITS = 2;
adder_tree_branch L2_0(sum0_0_0, sum0_0_1, sum0_0 );
adder_tree_branch L2_1(sum0_1_0, sum0_1_1, sum0_1 );
defparam L2_0.EXTRA_BITS = 1;
defparam L2_1.EXTRA_BITS = 1;
adder_tree_branch L3_0(sum0_0_0_0, sum0_0_0_1, sum0_0_0);
adder_tree_branch L3_1(sum0_0_1_0, sum0_0_1_1, sum0_0_1);
adder_tree_branch L3_2(sum0_1_0_0, sum0_1_0_1, sum0_1_0);
adder_tree_branch L3_3(sum0_1_1_0, sum0_1_1_1, sum0_1_1);
defparam L3_0.EXTRA_BITS = 0;
defparam L3_1.EXTRA_BITS = 0;
defparam L3_2.EXTRA_BITS = 0;
defparam L3_3.EXTRA_BITS = 0;
always @(posedge clk) begin
sum0_0_0_0 <= isum0_0_0_0;
sum0_0_0_1 <= isum0_0_0_1;
sum0_0_1_0 <= isum0_0_1_0;
sum0_0_1_1 <= isum0_0_1_1;
sum0_1_0_0 <= isum0_1_0_0;
sum0_1_0_1 <= isum0_1_0_1;
sum0_1_1_0 <= isum0_1_1_0;
sum0_1_1_1 <= isum0_1_1_1;
`ifdef 3_LEVEL_ADDER
sum <= sum0;
`endif
`ifdef 2_LEVEL_ADDER
sum <= sum0_0;
`endif
end
endmodule
module adder_tree_branch(a,b,sum);
parameter EXTRA_BITS = 0;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] a;
input [`ADDER_WIDTH+EXTRA_BITS-1:0] b;
output [`ADDER_WIDTH+EXTRA_BITS:0] sum;
assign sum = a + b;
endmodule |
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V
/**
* and4bb: 4-input AND, first two inputs inverted.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__and4bb (
X ,
A_N ,
B_N ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A_N ;
input B_N ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
nor nor0 (nor0_out , A_N, B_N );
and and0 (and0_out_X , nor0_out, C, D );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, and0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__AND4BB_FUNCTIONAL_PP_V |
(** * Basics: Functional Programming in Coq *)
(*
[Admitted] is Coq's "escape hatch" that says accept this definition
without proof. We use it to mark the 'holes' in the development
that should be completed as part of your homework exercises. In
practice, [Admitted] is useful when you're incrementally developing
large proofs. *)
Definition admit {T: Type} : T. Admitted.
(* ###################################################################### *)
(** * Introduction *)
(** The functional programming style brings programming closer to
simple, everyday mathematics: If a procedure or method has no side
effects, then pretty much all you need to understand about it is
how it maps inputs to outputs -- that is, you can think of it as
just a concrete method for computing a mathematical function.
This is one sense of the word "functional" in "functional
programming." The direct connection between programs and simple
mathematical objects supports both formal proofs of correctness
and sound informal reasoning about program behavior.
The other sense in which functional programming is "functional" is
that it emphasizes the use of functions (or methods) as
_first-class_ values -- i.e., values that can be passed as
arguments to other functions, returned as results, stored in data
structures, etc. The recognition that functions can be treated as
data in this way enables a host of useful and powerful idioms.
Other common features of functional languages include _algebraic
data types_ and _pattern matching_, which make it easy to construct
and manipulate rich data structures, and sophisticated
_polymorphic type systems_ that support abstraction and code
reuse. Coq shares all of these features.
The first half of this chapter introduces the most essential
elements of Coq's functional programming language. The second
half introduces some basic _tactics_ that can be used to prove
simple properties of Coq programs.
*)
(* ###################################################################### *)
(** * Enumerated Types *)
(** One unusual aspect of Coq is that its set of built-in
features is _extremely_ small. For example, instead of providing
the usual palette of atomic data types (booleans, integers,
strings, etc.), Coq offers an extremely powerful mechanism for
defining new data types from scratch -- so powerful that all these
familiar types arise as instances.
Naturally, the Coq distribution comes with an extensive standard
library providing definitions of booleans, numbers, and many
common data structures like lists and hash tables. But there is
nothing magic or primitive about these library definitions: they
are ordinary user code. To illustrate this, we will explicitly
recapitulate all the definitions we need in this course, rather
than just getting them implicitly from the library.
To see how this mechanism works, let's start with a very simple
example. *)
(* ###################################################################### *)
(** ** Days of the Week *)
(** The following declaration tells Coq that we are defining
a new set of data values -- a _type_. *)
Inductive day : Type :=
| monday : day
| tuesday : day
| wednesday : day
| thursday : day
| friday : day
| saturday : day
| sunday : day.
(** The type is called [day], and its members are [monday],
[tuesday], etc. The second and following lines of the definition
can be read "[monday] is a [day], [tuesday] is a [day], etc."
Having defined [day], we can write functions that operate on
days. *)
Definition next_weekday (d:day) : day :=
match d with
| monday => tuesday
| tuesday => wednesday
| wednesday => thursday
| thursday => friday
| friday => monday
| saturday => monday
| sunday => monday
end.
(** One thing to note is that the argument and return types of
this function are explicitly declared. Like most functional
programming languages, Coq can often figure out these types for
itself when they are not given explicitly -- i.e., it performs
some _type inference_ -- but we'll always include them to make
reading easier. *)
(** Having defined a function, we should check that it works on
some examples. There are actually three different ways to do this
in Coq.
First, we can use the command [Eval compute] to evaluate a
compound expression involving [next_weekday]. *)
Eval compute in (next_weekday friday).
(* ==> monday : day *)
Eval compute in (next_weekday (next_weekday saturday)).
(* ==> tuesday : day *)
(** If you have a computer handy, this would be an excellent
moment to fire up the Coq interpreter under your favorite IDE --
either CoqIde or Proof General -- and try this for yourself. Load
this file ([Basics.v]) from the book's accompanying Coq sources,
find the above example, submit it to Coq, and observe the
result. *)
(** The keyword [compute] tells Coq precisely how to
evaluate the expression we give it. For the moment, [compute] is
the only one we'll need; later on we'll see some alternatives that
are sometimes useful. *)
(** Second, we can record what we _expect_ the result to be in
the form of a Coq example: *)
Example test_next_weekday:
(next_weekday (next_weekday saturday)) = tuesday.
(** This declaration does two things: it makes an
assertion (that the second weekday after [saturday] is [tuesday]),
and it gives the assertion a name that can be used to refer to it
later. *)
(** Having made the assertion, we can also ask Coq to verify it,
like this: *)
Proof. simpl. reflexivity. Qed.
(** The details are not important for now (we'll come back to
them in a bit), but essentially this can be read as "The assertion
we've just made can be proved by observing that both sides of the
equality evaluate to the same thing, after some simplification." *)
(** Third, we can ask Coq to _extract_, from our [Definition], a
program in some other, more conventional, programming
language (OCaml, Scheme, or Haskell) with a high-performance
compiler. This facility is very interesting, since it gives us a
way to construct _fully certified_ programs in mainstream
languages. Indeed, this is one of the main uses for which Coq was
developed. We'll come back to this topic in later chapters. More
information can also be found in the Coq'Art book by Bertot and
Casteran, as well as the Coq reference manual. *)
(* ###################################################################### *)
(** ** Booleans *)
(** In a similar way, we can define the standard type [bool] of
booleans, with members [true] and [false]. *)
Inductive bool : Type :=
| true : bool
| false : bool.
(** Although we are rolling our own booleans here for the sake
of building up everything from scratch, Coq does, of course,
provide a default implementation of the booleans in its standard
library, together with a multitude of useful functions and
lemmas. (Take a look at [Coq.Init.Datatypes] in the Coq library
documentation if you're interested.) Whenever possible, we'll
name our own definitions and theorems so that they exactly
coincide with the ones in the standard library. *)
(** Functions over booleans can be defined in the same way as
above: *)
Definition negb (b:bool) : bool :=
match b with
| true => false
| false => true
end.
Definition andb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => b2
| false => false
end.
Definition orb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => true
| false => b2
end.
(** The last two illustrate the syntax for multi-argument
function definitions. *)
(** The following four "unit tests" constitute a complete
specification -- a truth table -- for the [orb] function: *)
Example test_orb1: (orb true false) = true.
Proof. reflexivity. Qed.
Example test_orb2: (orb false false) = false.
Proof. reflexivity. Qed.
Example test_orb3: (orb false true) = true.
Proof. reflexivity. Qed.
Example test_orb4: (orb true true) = true.
Proof. reflexivity. Qed.
(** (Note that we've dropped the [simpl] in the proofs. It's not
actually needed because [reflexivity] automatically performs
simplification.) *)
(** _A note on notation_: In .v files, we use square brackets to
delimit fragments of Coq code within comments; this convention,
also used by the [coqdoc] documentation tool, keeps them visually
separate from the surrounding text. In the html version of the
files, these pieces of text appear in a [different font]. *)
(** The values [Admitted] and [admit] can be used to fill
a hole in an incomplete definition or proof. We'll use them in the
following exercises. In general, your job in the exercises is
to replace [admit] or [Admitted] with real definitions or proofs. *)
(** **** Exercise: 1 star (nandb) *)
(** Complete the definition of the following function, then make
sure that the [Example] assertions below can each be verified by
Coq. *)
(** This function should return [true] if either or both of
its inputs are [false]. *)
Definition nandb (b1:bool) (b2:bool) : bool :=
match b1 with
| true => negb b2
| false => true
end.
(** Remove "[Admitted.]" and fill in each proof with
"[Proof. reflexivity. Qed.]" *)
Example test_nandb1: (nandb true false) = true.
Proof. reflexivity. Qed.
Example test_nandb2: (nandb false false) = true.
Proof. reflexivity. Qed.
Example test_nandb3: (nandb false true) = true.
Proof. reflexivity. Qed.
Example test_nandb4: (nandb true true) = false.
Proof. reflexivity. Qed.
(** [] *)
(** **** Exercise: 1 star (andb3) *)
(** Do the same for the [andb3] function below. This function should
return [true] when all of its inputs are [true], and [false]
otherwise. *)
Definition andb3 (b1:bool) (b2:bool) (b3:bool) : bool :=
match b1 with
| true => andb b2 b3
| false => false
end.
Example test_andb31: (andb3 true true true) = true.
Proof. reflexivity. Qed.
Example test_andb32: (andb3 false true true) = false.
Proof. reflexivity. Qed.
Example test_andb33: (andb3 true false true) = false.
Proof. reflexivity. Qed.
Example test_andb34: (andb3 true true false) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** ** Function Types *)
(** The [Check] command causes Coq to print the type of an
expression. For example, the type of [negb true] is [bool]. *)
Check true.
(* ===> true : bool *)
Check (negb true).
(* ===> negb true : bool *)
(** Functions like [negb] itself are also data values, just like
[true] and [false]. Their types are called _function types_, and
they are written with arrows. *)
Check negb.
(* ===> negb : bool -> bool *)
(** The type of [negb], written [bool -> bool] and pronounced
"[bool] arrow [bool]," can be read, "Given an input of type
[bool], this function produces an output of type [bool]."
Similarly, the type of [andb], written [bool -> bool -> bool], can
be read, "Given two inputs, both of type [bool], this function
produces an output of type [bool]." *)
(* ###################################################################### *)
(** ** Numbers *)
(** _Technical digression_: Coq provides a fairly sophisticated
_module system_, to aid in organizing large developments. In this
course we won't need most of its features, but one is useful: If
we enclose a collection of declarations between [Module X] and
[End X] markers, then, in the remainder of the file after the
[End], these definitions will be referred to by names like [X.foo]
instead of just [foo]. Here, we use this feature to introduce the
definition of the type [nat] in an inner module so that it does
not shadow the one from the standard library. *)
Module Playground1.
(** The types we have defined so far are examples of "enumerated
types": their definitions explicitly enumerate a finite set of
elements. A more interesting way of defining a type is to give a
collection of "inductive rules" describing its elements. For
example, we can define the natural numbers as follows: *)
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
(** The clauses of this definition can be read:
- [O] is a natural number (note that this is the letter "[O]," not
the numeral "[0]").
- [S] is a "constructor" that takes a natural number and yields
another one -- that is, if [n] is a natural number, then [S n]
is too.
Let's look at this in a little more detail.
Every inductively defined set ([day], [nat], [bool], etc.) is
actually a set of _expressions_. The definition of [nat] says how
expressions in the set [nat] can be constructed:
- the expression [O] belongs to the set [nat];
- if [n] is an expression belonging to the set [nat], then [S n]
is also an expression belonging to the set [nat]; and
- expressions formed in these two ways are the only ones belonging
to the set [nat].
The same rules apply for our definitions of [day] and [bool]. The
annotations we used for their constructors are analogous to the
one for the [O] constructor, and indicate that each of those
constructors doesn't take any arguments. *)
(** These three conditions are the precise force of the
[Inductive] declaration. They imply that the expression [O], the
expression [S O], the expression [S (S O)], the expression
[S (S (S O))], and so on all belong to the set [nat], while other
expressions like [true], [andb true false], and [S (S false)] do
not.
We can write simple functions that pattern match on natural
numbers just as we did above -- for example, the predecessor
function: *)
Definition pred (n : nat) : nat :=
match n with
| O => O
| S n' => n'
end.
(** The second branch can be read: "if [n] has the form [S n']
for some [n'], then return [n']." *)
End Playground1.
Definition minustwo (n : nat) : nat :=
match n with
| O => O
| S O => O
| S (S n') => n'
end.
(** Because natural numbers are such a pervasive form of data,
Coq provides a tiny bit of built-in magic for parsing and printing
them: ordinary arabic numerals can be used as an alternative to
the "unary" notation defined by the constructors [S] and [O]. Coq
prints numbers in arabic form by default: *)
Check (S (S (S (S O)))).
Eval compute in (minustwo 4).
(** The constructor [S] has the type [nat -> nat], just like the
functions [minustwo] and [pred]: *)
Check S.
Check pred.
Check minustwo.
(** These are all things that can be applied to a number to yield a
number. However, there is a fundamental difference: functions
like [pred] and [minustwo] come with _computation rules_ -- e.g.,
the definition of [pred] says that [pred 2] can be simplified to
[1] -- while the definition of [S] has no such behavior attached.
Although it is like a function in the sense that it can be applied
to an argument, it does not _do_ anything at all! *)
(** For most function definitions over numbers, pure pattern
matching is not enough: we also need recursion. For example, to
check that a number [n] is even, we may need to recursively check
whether [n-2] is even. To write such functions, we use the
keyword [Fixpoint]. *)
Fixpoint evenb (n:nat) : bool :=
match n with
| O => true
| S O => false
| S (S n') => evenb n'
end.
(** We can define [oddb] by a similar [Fixpoint] declaration, but here
is a simpler definition that will be a bit easier to work with: *)
Definition oddb (n:nat) : bool := negb (evenb n).
Example test_oddb1: (oddb (S O)) = true.
Proof. reflexivity. Qed.
Example test_oddb2: (oddb (S (S (S (S O))))) = false.
Proof. reflexivity. Qed.
(** Naturally, we can also define multi-argument functions by
recursion. (Once again, we use a module to avoid polluting the
namespace.) *)
Module Playground2.
Fixpoint plus (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus n' m)
end.
(** Adding three to two now gives us five, as we'd expect. *)
Eval compute in (plus (S (S (S O))) (S (S O))).
(** The simplification that Coq performs to reach this conclusion can
be visualized as follows: *)
(* [plus (S (S (S O))) (S (S O))]
==> [S (plus (S (S O)) (S (S O)))] by the second clause of the [match]
==> [S (S (plus (S O) (S (S O))))] by the second clause of the [match]
==> [S (S (S (plus O (S (S O)))))] by the second clause of the [match]
==> [S (S (S (S (S O))))] by the first clause of the [match]
*)
(** As a notational convenience, if two or more arguments have
the same type, they can be written together. In the following
definition, [(n m : nat)] means just the same as if we had written
[(n : nat) (m : nat)]. *)
Fixpoint mult (n m : nat) : nat :=
match n with
| O => O
| S n' => plus m (mult n' m)
end.
Example test_mult1: (mult 3 3) = 9.
Proof. reflexivity. Qed.
(** You can match two expressions at once by putting a comma
between them: *)
Fixpoint minus (n m:nat) : nat :=
match n, m with
| O , _ => O
| S _ , O => n
| S n', S m' => minus n' m'
end.
(** The _ in the first line is a _wildcard pattern_. Writing _ in a
pattern is the same as writing some variable that doesn't get used
on the right-hand side. This avoids the need to invent a bogus
variable name. *)
End Playground2.
Fixpoint exp (base power : nat) : nat :=
match power with
| O => S O
| S p => mult base (exp base p)
end.
(** **** Exercise: 1 star (factorial) *)
(** Recall the standard factorial function:
<<
factorial(0) = 1
factorial(n) = n * factorial(n-1) (if n>0)
>>
Translate this into Coq. *)
Fixpoint factorial (n:nat) : nat :=
match n with
| O => 1
| S n' => mult n (factorial n')
end.
Example test_factorial1: (factorial 3) = 6.
Proof. reflexivity. Qed.
Example test_factorial2: (factorial 5) = (mult 10 12).
Proof. reflexivity. Qed.
(** [] *)
(** We can make numerical expressions a little easier to read and
write by introducing "notations" for addition, multiplication, and
subtraction. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x - y" := (minus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
Check ((0 + 1) + 1).
(** (The [level], [associativity], and [nat_scope] annotations
control how these notations are treated by Coq's parser. The
details are not important, but interested readers can refer to the
"More on Notation" subsection in the "Advanced Material" section at
the end of this chapter.) *)
(** Note that these do not change the definitions we've already
made: they are simply instructions to the Coq parser to accept [x
+ y] in place of [plus x y] and, conversely, to the Coq
pretty-printer to display [plus x y] as [x + y]. *)
(** When we say that Coq comes with nothing built-in, we really
mean it: even equality testing for numbers is a user-defined
operation! *)
(** The [beq_nat] function tests [nat]ural numbers for [eq]uality,
yielding a [b]oolean. Note the use of nested [match]es (we could
also have used a simultaneous match, as we did in [minus].) *)
Fixpoint beq_nat (n m : nat) : bool :=
match n with
| O => match m with
| O => true
| S m' => false
end
| S n' => match m with
| O => false
| S m' => beq_nat n' m'
end
end.
(** Similarly, the [ble_nat] function tests [nat]ural numbers for
[l]ess-or-[e]qual, yielding a [b]oolean. *)
Fixpoint ble_nat (n m : nat) : bool :=
match n with
| O => true
| S n' =>
match m with
| O => false
| S m' => ble_nat n' m'
end
end.
Example test_ble_nat1: (ble_nat 2 2) = true.
Proof. reflexivity. Qed.
Example test_ble_nat2: (ble_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_ble_nat3: (ble_nat 4 2) = false.
Proof. reflexivity. Qed.
(** **** Exercise: 2 stars (blt_nat) *)
(** The [blt_nat] function tests [nat]ural numbers for [l]ess-[t]han,
yielding a [b]oolean. Instead of making up a new [Fixpoint] for
this one, define it in terms of a previously defined function. *)
Definition blt_nat (n m : nat) : bool :=
andb (ble_nat n m) (negb (beq_nat n m)).
Example test_blt_nat1: (blt_nat 2 2) = false.
Proof. reflexivity. Qed.
Example test_blt_nat2: (blt_nat 2 4) = true.
Proof. reflexivity. Qed.
Example test_blt_nat3: (blt_nat 4 2) = false.
Proof. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Simplification *)
(** Now that we've defined a few datatypes and functions, let's
turn to the question of how to state and prove properties of their
behavior. Actually, in a sense, we've already started doing this:
each [Example] in the previous sections makes a precise claim
about the behavior of some function on some particular inputs.
The proofs of these claims were always the same: use [reflexivity]
to check that both sides of the [=] simplify to identical values.
(By the way, it will be useful later to know that
[reflexivity] actually does somewhat more simplification than [simpl]
does -- for example, it tries "unfolding" defined terms, replacing them with
their right-hand sides. The reason for this difference is that,
when reflexivity succeeds, the whole goal is finished and we don't
need to look at whatever expanded expressions [reflexivity] has
found; by contrast, [simpl] is used in situations where we may
have to read and understand the new goal, so we would not want it
blindly expanding definitions.)
The same sort of "proof by simplification" can be used to prove
more interesting properties as well. For example, the fact that
[0] is a "neutral element" for [+] on the left can be proved
just by observing that [0 + n] reduces to [n] no matter what
[n] is, a fact that can be read directly off the definition of [plus].*)
Theorem plus_O_n : forall n : nat, 0 + n = n.
Proof.
intros n. reflexivity. Qed.
(** (_Note_: You may notice that the above statement looks
different in the original source file and the final html output. In Coq
files, we write the [forall] universal quantifier using the
"_forall_" reserved identifier. This gets printed as an
upside-down "A", the familiar symbol used in logic.) *)
(** The form of this theorem and proof are almost exactly the
same as the examples above; there are just a few differences.
First, we've used the keyword [Theorem] instead of
[Example]. Indeed, the difference is purely a matter of
style; the keywords [Example] and [Theorem] (and a few others,
including [Lemma], [Fact], and [Remark]) mean exactly the same
thing to Coq.
Secondly, we've added the quantifier [forall n:nat], so that our
theorem talks about _all_ natural numbers [n]. In order to prove
theorems of this form, we need to to be able to reason by
_assuming_ the existence of an arbitrary natural number [n]. This
is achieved in the proof by [intros n], which moves the quantifier
from the goal to a "context" of current assumptions. In effect, we
start the proof by saying "OK, suppose [n] is some arbitrary number."
The keywords [intros], [simpl], and [reflexivity] are examples of
_tactics_. A tactic is a command that is used between [Proof] and
[Qed] to tell Coq how it should check the correctness of some
claim we are making. We will see several more tactics in the rest
of this lecture, and yet more in future lectures. *)
(** We could try to prove a similar theorem about [plus] *)
Theorem plus_n_O : forall n, n + 0 = n.
(** However, unlike the previous proof, [simpl] doesn't do anything in
this case *)
Proof.
simpl. (* Doesn't do anything! *)
Abort.
(** (Can you explain why this happens? Step through both proofs with
Coq and notice how the goal and context change.) *)
Theorem plus_1_l : forall n:nat, 1 + n = S n.
Proof.
intros n. reflexivity. Qed.
Theorem mult_0_l : forall n:nat, 0 * n = 0.
Proof.
intros n. reflexivity. Qed.
(** The [_l] suffix in the names of these theorems is
pronounced "on the left." *)
(* ###################################################################### *)
(** * Proof by Rewriting *)
(** Here is a slightly more interesting theorem: *)
Theorem plus_id_example : forall n m:nat,
n = m ->
n + n = m + m.
(** Instead of making a completely universal claim about all numbers
[n] and [m], this theorem talks about a more specialized property
that only holds when [n = m]. The arrow symbol is pronounced
"implies."
As before, we need to be able to reason by assuming the existence
of some numbers [n] and [m]. We also need to assume the hypothesis
[n = m]. The [intros] tactic will serve to move all three of these
from the goal into assumptions in the current context.
Since [n] and [m] are arbitrary numbers, we can't just use
simplification to prove this theorem. Instead, we prove it by
observing that, if we are assuming [n = m], then we can replace
[n] with [m] in the goal statement and obtain an equality with the
same expression on both sides. The tactic that tells Coq to
perform this replacement is called [rewrite]. *)
Proof.
intros n m. (* move both quantifiers into the context *)
intros H. (* move the hypothesis into the context *)
rewrite -> H. (* Rewrite the goal using the hypothesis *)
reflexivity. Qed.
(** The first line of the proof moves the universally quantified
variables [n] and [m] into the context. The second moves the
hypothesis [n = m] into the context and gives it the (arbitrary)
name [H]. The third tells Coq to rewrite the current goal ([n + n
= m + m]) by replacing the left side of the equality hypothesis
[H] with the right side.
(The arrow symbol in the [rewrite] has nothing to do with
implication: it tells Coq to apply the rewrite from left to right.
To rewrite from right to left, you can use [rewrite <-]. Try
making this change in the above proof and see what difference it
makes in Coq's behavior.) *)
(** **** Exercise: 1 star (plus_id_exercise) *)
(** Remove "[Admitted.]" and fill in the proof. *)
Theorem plus_id_exercise : forall n m o : nat,
n = m -> m = o -> n + m = m + o.
Proof.
intros. rewrite H. rewrite H0. reflexivity. Qed.
(** [] *)
(** As we've seen in earlier examples, the [Admitted] command
tells Coq that we want to skip trying to prove this theorem and
just accept it as a given. This can be useful for developing
longer proofs, since we can state subsidiary facts that we believe
will be useful for making some larger argument, use [Admitted] to
accept them on faith for the moment, and continue thinking about
the larger argument until we are sure it makes sense; then we can
go back and fill in the proofs we skipped. Be careful, though:
every time you say [Admitted] (or [admit]) you are leaving a door
open for total nonsense to enter Coq's nice, rigorous, formally
checked world! *)
(** We can also use the [rewrite] tactic with a previously proved
theorem instead of a hypothesis from the context. *)
Theorem mult_0_plus : forall n m : nat,
(0 + n) * m = n * m.
Proof.
intros n m.
rewrite -> plus_O_n.
reflexivity. Qed.
(** **** Exercise: 2 stars (mult_S_1) *)
Theorem mult_S_1 : forall n m : nat,
m = S n ->
m * (1 + n) = m * m.
Proof.
intros. simpl. symmetry. rewrite H. symmetry. reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * Proof by Case Analysis *)
(** Of course, not everything can be proved by simple
calculation: In general, unknown, hypothetical values (arbitrary
numbers, booleans, lists, etc.) can block the calculation.
For example, if we try to prove the following fact using the
[simpl] tactic as above, we get stuck. *)
Theorem plus_1_neq_0_firsttry : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n.
simpl. (* does nothing! *)
Abort.
(** The reason for this is that the definitions of both
[beq_nat] and [+] begin by performing a [match] on their first
argument. But here, the first argument to [+] is the unknown
number [n] and the argument to [beq_nat] is the compound
expression [n + 1]; neither can be simplified.
What we need is to be able to consider the possible forms of [n]
separately. If [n] is [O], then we can calculate the final result
of [beq_nat (n + 1) 0] and check that it is, indeed, [false].
And if [n = S n'] for some [n'], then, although we don't know
exactly what number [n + 1] yields, we can calculate that, at
least, it will begin with one [S], and this is enough to calculate
that, again, [beq_nat (n + 1) 0] will yield [false].
The tactic that tells Coq to consider, separately, the cases where
[n = O] and where [n = S n'] is called [destruct]. *)
Theorem plus_1_neq_0 : forall n : nat,
beq_nat (n + 1) 0 = false.
Proof.
intros n. destruct n as [p | n'].
reflexivity.
reflexivity. Qed.
(** The [destruct] generates _two_ subgoals, which we must then
prove, separately, in order to get Coq to accept the theorem as
proved. (No special command is needed for moving from one subgoal
to the other. When the first subgoal has been proved, it just
disappears and we are left with the other "in focus.") In this
proof, each of the subgoals is easily proved by a single use of
[reflexivity].
The annotation "[as [| n']]" is called an _intro pattern_. It
tells Coq what variable names to introduce in each subgoal. In
general, what goes between the square brackets is a _list_ of
lists of names, separated by [|]. Here, the first component is
empty, since the [O] constructor is nullary (it doesn't carry any
data). The second component gives a single name, [n'], since [S]
is a unary constructor.
The [destruct] tactic can be used with any inductively defined
datatype. For example, we use it here to prove that boolean
negation is involutive -- i.e., that negation is its own
inverse. *)
Theorem negb_involutive : forall b : bool,
negb (negb b) = b.
Proof.
intros b. destruct b.
reflexivity.
reflexivity. Qed.
(** Note that the [destruct] here has no [as] clause because
none of the subcases of the [destruct] need to bind any variables,
so there is no need to specify any names. (We could also have
written [as [|]], or [as []].) In fact, we can omit the [as]
clause from _any_ [destruct] and Coq will fill in variable names
automatically. Although this is convenient, it is arguably bad
style, since Coq often makes confusing choices of names when left
to its own devices. *)
(** **** Exercise: 1 star (zero_nbeq_plus_1) *)
Theorem zero_nbeq_plus_1 : forall n : nat,
beq_nat 0 (n + 1) = false.
Proof.
intros. destruct n as [|n']. simpl. reflexivity.
reflexivity. Qed.
(** [] *)
(* ###################################################################### *)
(** * More Exercises *)
(** **** Exercise: 2 stars (boolean_functions) *)
(** Use the tactics you have learned so far to prove the following
theorem about boolean functions. *)
Theorem identity_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite H . rewrite H. reflexivity. Qed.
(** Now state and prove a theorem [negation_fn_applied_twice] similar
to the previous one but where the second hypothesis says that the
function [f] has the property that [f x = negb x].*)
(* FILL IN HERE *)
Theorem negation_fn_applied_twice :
forall (f : bool -> bool),
(forall (x : bool), f x = negb x) ->
forall (b : bool), f (f b) = b.
Proof.
intros. rewrite H. rewrite H. destruct b. simpl. reflexivity.
reflexivity. Qed.
(** [] *)
(** **** Exercise: 2 stars (andb_eq_orb) *)
(** Prove the following theorem. (You may want to first prove a
subsidiary lemma or two. Alternatively, remember that you do
not have to introduce all hypotheses at the same time.) *)
Theorem andb_eq_orb :
forall (b c : bool),
(andb b c = orb b c) ->
b = c.
Proof.
intros b c. destruct b. simpl. intros. rewrite H. reflexivity.
simpl. intros. rewrite H. reflexivity. Qed.
(** [] *)
(** **** Exercise: 3 stars (binary) *)
(** Consider a different, more efficient representation of natural
numbers using a binary rather than unary system. That is, instead
of saying that each natural number is either zero or the successor
of a natural number, we can say that each binary number is either
- zero,
- twice a binary number, or
- one more than twice a binary number.
(a) First, write an inductive definition of the type [bin]
corresponding to this description of binary numbers.
(Hint: Recall that the definition of [nat] from class,
Inductive nat : Type :=
| O : nat
| S : nat -> nat.
says nothing about what [O] and [S] "mean." It just says "[O] is
in the set called [nat], and if [n] is in the set then so is [S
n]." The interpretation of [O] as zero and [S] as successor/plus
one comes from the way that we _use_ [nat] values, by writing
functions to do things with them, proving things about them, and
so on. Your definition of [bin] should be correspondingly simple;
it is the functions you will write next that will give it
mathematical meaning.)
(b) Next, write an increment function [incr] for binary numbers,
and a function [bin_to_nat] to convert binary numbers to unary numbers.
(c) Write five unit tests [test_bin_incr1], [test_bin_incr2], etc.
for your increment and binary-to-unary functions. Notice that
incrementing a binary number and then converting it to unary
should yield the same result as first converting it to unary and
then incrementing.
*)
Inductive bin : Type :=
| zero : bin
| twiceN : bin -> bin
| twiceNPlus1 : bin -> bin.
Fixpoint incr (b : bin) :=
match b with
| zero => twiceNPlus1 zero
| twiceN b' => twiceNPlus1 b'
| twiceNPlus1 b' => twiceN (incr b')
end.
Eval compute in incr (twiceNPlus1 (twiceNPlus1 zero)).
Fixpoint bin_to_nat (b : bin) : nat :=
match b with
| zero => O
| twiceN b' => 2 * (bin_to_nat b')
| twiceNPlus1 b' => 1 + (2 * (bin_to_nat b'))
end.
Example test_bin_incr1 : incr (twiceNPlus1 (twiceNPlus1 zero)) = twiceN (twiceN (twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr2 : incr (zero) = ((twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr3 : incr (twiceNPlus1 zero) = (twiceN (twiceNPlus1 zero)).
Proof. reflexivity. Qed.
Example test_bin_incr4 : bin_to_nat ( incr (twiceNPlus1 (twiceNPlus1 zero))) = 4.
Proof. reflexivity. Qed.
Example test_bin_incr5 : bin_to_nat ( incr (twiceN (twiceNPlus1 (twiceNPlus1 zero)))) = 7.
Proof. reflexivity. Qed.
(* FILL IN HERE *)
(** [] *)
(* ###################################################################### *)
(** * More on Notation (Advanced) *)
(** In general, sections marked Advanced are not needed to follow the
rest of the book, except possibly other Advanced sections. On a
first reading, you might want to skim these sections so that you
know what's there for future reference. *)
Notation "x + y" := (plus x y)
(at level 50, left associativity)
: nat_scope.
Notation "x * y" := (mult x y)
(at level 40, left associativity)
: nat_scope.
(** For each notation-symbol in Coq we can specify its _precedence level_
and its _associativity_. The precedence level n can be specified by the
keywords [at level n] and it is helpful to disambiguate
expressions containing different symbols. The associativity is helpful
to disambiguate expressions containing more occurrences of the same
symbol. For example, the parameters specified above for [+] and [*]
say that the expression [1+2*3*4] is a shorthand for the expression
[(1+((2*3)*4))]. Coq uses precedence levels from 0 to 100, and
_left_, _right_, or _no_ associativity.
Each notation-symbol in Coq is also active in a _notation scope_.
Coq tries to guess what scope you mean, so when you write [S(O*O)]
it guesses [nat_scope], but when you write the cartesian
product (tuple) type [bool*bool] it guesses [type_scope].
Occasionally you have to help it out with percent-notation by
writing [(x*y)%nat], and sometimes in Coq's feedback to you it
will use [%nat] to indicate what scope a notation is in.
Notation scopes also apply to numeral notation (3,4,5, etc.), so you
may sometimes see [0%nat] which means [O], or [0%Z] which means the
Integer zero.
*)
(** * [Fixpoint] and Structural Recursion (Advanced) *)
Fixpoint plus' (n : nat) (m : nat) : nat :=
match n with
| O => m
| S n' => S (plus' n' m)
end.
(** When Coq checks this definition, it notes that [plus'] is
"decreasing on 1st argument." What this means is that we are
performing a _structural recursion_ over the argument [n] -- i.e.,
that we make recursive calls only on strictly smaller values of
[n]. This implies that all calls to [plus'] will eventually
terminate. Coq demands that some argument of _every_ [Fixpoint]
definition is "decreasing".
This requirement is a fundamental feature of Coq's design: In
particular, it guarantees that every function that can be defined
in Coq will terminate on all inputs. However, because Coq's
"decreasing analysis" is not very sophisticated, it is sometimes
necessary to write functions in slightly unnatural ways. *)
(** **** Exercise: 2 stars, optional (decreasing) *)
(** To get a concrete sense of this, find a way to write a sensible
[Fixpoint] definition (of a simple function on numbers, say) that
_does_ terminate on all inputs, but that Coq will reject because
of this restriction. *)
(* FILL IN HERE *)
(** [] *)
(** $Date: 2014-12-31 15:31:47 -0500 (Wed, 31 Dec 2014) $ *)
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2003-2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg check;
initial check = 1'b0;
Genit g (.clk(clk), .check(check));
always @ (posedge clk) begin
//$write("[%0t] cyc==%0d %x %x\n",$time, cyc, check, out);
cyc <= cyc + 1;
if (cyc==0) begin
// Setup
check <= 1'b0;
end
else if (cyc==1) begin
check <= 1'b1;
end
else if (cyc==9) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
//`define WAVES
`ifdef WAVES
initial begin
$dumpfile("obj_dir/t_gen_intdot2/t_gen_intdot.vcd");
$dumpvars(12, t);
end
`endif
endmodule
module One;
wire one = 1'b1;
endmodule
module Genit (
input clk,
input check);
// ARRAY
One cellarray1[1:0] (); //cellarray[0..1][0..1]
always @ (posedge clk) if (cellarray1[0].one !== 1'b1) $stop;
always @ (posedge clk) if (cellarray1[1].one !== 1'b1) $stop;
// IF
generate
// genblk1 refers to the if's name, not the "generate" itself.
if (1'b1) // IMPLIED begin: genblk1
One ifcell1(); // genblk1.ifcell1
else
One ifcell1(); // genblk1.ifcell1
endgenerate
// On compliant simulators "Implicit name" not allowed here; IE we can't use "genblk1" etc
`ifdef verilator
always @ (posedge clk) if (genblk1.ifcell1.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
begin : namedif2
if (1'b1)
One ifcell2(); // namedif2.genblk1.ifcell2
end
endgenerate
`ifdef verilator
always @ (posedge clk) if (namedif2.genblk1.ifcell2.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
if (1'b1)
begin : namedif3
One ifcell3(); // namedif3.ifcell3
end
endgenerate
always @ (posedge clk) if (namedif3.ifcell3.one !== 1'b1) $stop;
// CASE
generate
case (1'b1)
1'b1 :
One casecell10(); // genblk3.casecell10
endcase
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk3.casecell10.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
generate
case (1'b1)
1'b1 : begin : namedcase11
One casecell11();
end
endcase
endgenerate
always @ (posedge clk) if (namedcase11.casecell11.one !== 1'b1) $stop;
genvar i;
genvar j;
// IF
generate
for (i = 0; i < 2; i = i + 1)
One cellfor20 (); // genblk4[0..1].cellfor20
endgenerate
`ifdef verilator
always @ (posedge clk) if (genblk4[0].cellfor20.one !== 1'b1) $stop;
always @ (posedge clk) if (genblk4[1].cellfor20.one !== 1'b1) $stop;
//`else // NOT SUPPORTED accoring to spec - generic block references
`endif
// COMBO
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor21
One cellfor21 (); // namedfor21[0..1].cellfor21
end
endgenerate
always @ (posedge clk) if (namedfor21[0].cellfor21.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor21[1].cellfor21.one !== 1'b1) $stop;
generate
for (i = 0; i < 2; i = i + 1)
begin : namedfor30
for (j = 0; j < 2; j = j + 1)
begin : forb30
if (j == 0)
begin : forif30
One cellfor30a (); // namedfor30[0..1].forb30[0].forif30.cellfor30a
end
else
`ifdef verilator
begin : forif30b
`else
begin : forif30 // forif30 seems to work on some simulators, not verilator yet
`endif
One cellfor30b (); // namedfor30[0..1].forb30[1].forif30.cellfor30b
end
end
end
endgenerate
always @ (posedge clk) if (namedfor30[0].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[0].forif30.cellfor30a.one !== 1'b1) $stop;
`ifdef verilator
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30b.cellfor30b.one !== 1'b1) $stop;
`else
always @ (posedge clk) if (namedfor30[0].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
always @ (posedge clk) if (namedfor30[1].forb30[1].forif30.cellfor30b.one !== 1'b1) $stop;
`endif
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
// CONFIG:
// NUM_COEFF = 17
// PIPLINED = 1
// WARNING: more than enough COEFFICIENTS in array (there are 26, and we only need 9)
module fir (
clk,
reset,
clk_ena,
i_valid,
i_in,
o_valid,
o_out
);
// Data Width
parameter dw = 18; //Data input/output bits
// Number of filter coefficients
parameter N = 17;
parameter N_UNIQ = 9; // ciel(N/2) assuming symmetric filter coefficients
//Number of extra valid cycles needed to align output (i.e. computation pipeline depth + input/output registers
localparam N_VALID_REGS = 23;
input clk;
input reset;
input clk_ena;
input i_valid;
input [dw-1:0] i_in; // signed
output o_valid;
output [dw-1:0] o_out; // signed
// Data Width dervied parameters
localparam dw_add_int = 18; //Internal adder precision bits
localparam dw_mult_int = 36; //Internal multiplier precision bits
localparam scale_factor = 17; //Multiplier normalization shift amount
// Number of extra registers in INPUT_PIPELINE_REG to prevent contention for CHAIN_END's chain adders
localparam N_INPUT_REGS = 17;
// Debug
// initial begin
// $display ("Data Width: %d", dw);
// $display ("Data Width Add Internal: %d", dw_add_int);
// $display ("Data Width Mult Internal: %d", dw_mult_int);
// $display ("Scale Factor: %d", scale_factor);
// end
reg [dw-1:0] COEFFICIENT_0;
reg [dw-1:0] COEFFICIENT_1;
reg [dw-1:0] COEFFICIENT_2;
reg [dw-1:0] COEFFICIENT_3;
reg [dw-1:0] COEFFICIENT_4;
reg [dw-1:0] COEFFICIENT_5;
reg [dw-1:0] COEFFICIENT_6;
reg [dw-1:0] COEFFICIENT_7;
reg [dw-1:0] COEFFICIENT_8;
always@(posedge clk) begin
COEFFICIENT_0 <= 18'd88;
COEFFICIENT_1 <= 18'd0;
COEFFICIENT_2 <= -18'd97;
COEFFICIENT_3 <= -18'd197;
COEFFICIENT_4 <= -18'd294;
COEFFICIENT_5 <= -18'd380;
COEFFICIENT_6 <= -18'd447;
COEFFICIENT_7 <= -18'd490;
COEFFICIENT_8 <= -18'd504;
end
////******************************************************
// *
// * Valid Delay Pipeline
// *
// *****************************************************
//Input valid signal is pipelined to become output valid signal
//Valid registers
reg [N_VALID_REGS-1:0] VALID_PIPELINE_REGS;
always@(posedge clk or posedge reset) begin
if(reset) begin
VALID_PIPELINE_REGS <= 0;
end else begin
if(clk_ena) begin
VALID_PIPELINE_REGS <= {VALID_PIPELINE_REGS[N_VALID_REGS-2:0], i_valid};
end else begin
VALID_PIPELINE_REGS <= VALID_PIPELINE_REGS;
end
end
end
////******************************************************
// *
// * Input Register Pipeline
// *
// *****************************************************
//Pipelined input values
//Input value registers
wire [dw-1:0] INPUT_PIPELINE_REG_0;
wire [dw-1:0] INPUT_PIPELINE_REG_1;
wire [dw-1:0] INPUT_PIPELINE_REG_2;
wire [dw-1:0] INPUT_PIPELINE_REG_3;
wire [dw-1:0] INPUT_PIPELINE_REG_4;
wire [dw-1:0] INPUT_PIPELINE_REG_5;
wire [dw-1:0] INPUT_PIPELINE_REG_6;
wire [dw-1:0] INPUT_PIPELINE_REG_7;
wire [dw-1:0] INPUT_PIPELINE_REG_8;
wire [dw-1:0] INPUT_PIPELINE_REG_9;
wire [dw-1:0] INPUT_PIPELINE_REG_10;
wire [dw-1:0] INPUT_PIPELINE_REG_11;
wire [dw-1:0] INPUT_PIPELINE_REG_12;
wire [dw-1:0] INPUT_PIPELINE_REG_13;
wire [dw-1:0] INPUT_PIPELINE_REG_14;
wire [dw-1:0] INPUT_PIPELINE_REG_15;
wire [dw-1:0] INPUT_PIPELINE_REG_16;
input_pipeline in_pipe(
.clk(clk), .clk_ena(clk_ena),
.in_stream(i_in),
.pipeline_reg_0(INPUT_PIPELINE_REG_0),
.pipeline_reg_1(INPUT_PIPELINE_REG_1),
.pipeline_reg_2(INPUT_PIPELINE_REG_2),
.pipeline_reg_3(INPUT_PIPELINE_REG_3),
.pipeline_reg_4(INPUT_PIPELINE_REG_4),
.pipeline_reg_5(INPUT_PIPELINE_REG_5),
.pipeline_reg_6(INPUT_PIPELINE_REG_6),
.pipeline_reg_7(INPUT_PIPELINE_REG_7),
.pipeline_reg_8(INPUT_PIPELINE_REG_8),
.pipeline_reg_9(INPUT_PIPELINE_REG_9),
.pipeline_reg_10(INPUT_PIPELINE_REG_10),
.pipeline_reg_11(INPUT_PIPELINE_REG_11),
.pipeline_reg_12(INPUT_PIPELINE_REG_12),
.pipeline_reg_13(INPUT_PIPELINE_REG_13),
.pipeline_reg_14(INPUT_PIPELINE_REG_14),
.pipeline_reg_15(INPUT_PIPELINE_REG_15),
.pipeline_reg_16(INPUT_PIPELINE_REG_16),
.reset(reset) );
defparam in_pipe.WIDTH = 18; // = dw
////******************************************************
// *
// * Computation Pipeline
// *
// *****************************************************
// ************************* LEVEL 0 ************************* \\
wire [dw-1:0] L0_output_wires_0;
wire [dw-1:0] L0_output_wires_1;
wire [dw-1:0] L0_output_wires_2;
wire [dw-1:0] L0_output_wires_3;
wire [dw-1:0] L0_output_wires_4;
wire [dw-1:0] L0_output_wires_5;
wire [dw-1:0] L0_output_wires_6;
wire [dw-1:0] L0_output_wires_7;
wire [dw-1:0] L0_output_wires_8;
adder_with_1_reg L0_adder_0and16(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_0),
.datab (INPUT_PIPELINE_REG_16),
.result(L0_output_wires_0)
);
adder_with_1_reg L0_adder_1and15(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_1),
.datab (INPUT_PIPELINE_REG_15),
.result(L0_output_wires_1)
);
adder_with_1_reg L0_adder_2and14(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_2),
.datab (INPUT_PIPELINE_REG_14),
.result(L0_output_wires_2)
);
adder_with_1_reg L0_adder_3and13(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_3),
.datab (INPUT_PIPELINE_REG_13),
.result(L0_output_wires_3)
);
adder_with_1_reg L0_adder_4and12(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_4),
.datab (INPUT_PIPELINE_REG_12),
.result(L0_output_wires_4)
);
adder_with_1_reg L0_adder_5and11(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_5),
.datab (INPUT_PIPELINE_REG_11),
.result(L0_output_wires_5)
);
adder_with_1_reg L0_adder_6and10(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_6),
.datab (INPUT_PIPELINE_REG_10),
.result(L0_output_wires_6)
);
adder_with_1_reg L0_adder_7and9(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_7),
.datab (INPUT_PIPELINE_REG_9),
.result(L0_output_wires_7)
);
// (8 main tree Adders)
// ********* Byes ******** \\
one_register L0_byereg_for_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (INPUT_PIPELINE_REG_8),
.result(L0_output_wires_8)
);
// (1 byes)
// ************************* LEVEL 1 ************************* \\
// **************** Multipliers **************** \\
wire [dw-1:0] L1_mult_wires_0;
wire [dw-1:0] L1_mult_wires_1;
wire [dw-1:0] L1_mult_wires_2;
wire [dw-1:0] L1_mult_wires_3;
wire [dw-1:0] L1_mult_wires_4;
wire [dw-1:0] L1_mult_wires_5;
wire [dw-1:0] L1_mult_wires_6;
wire [dw-1:0] L1_mult_wires_7;
wire [dw-1:0] L1_mult_wires_8;
multiplier_with_reg L1_mul_0(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_0),
.datab (COEFFICIENT_0),
.result(L1_mult_wires_0)
);
multiplier_with_reg L1_mul_1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_1),
.datab (COEFFICIENT_1),
.result(L1_mult_wires_1)
);
multiplier_with_reg L1_mul_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_2),
.datab (COEFFICIENT_2),
.result(L1_mult_wires_2)
);
multiplier_with_reg L1_mul_3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_3),
.datab (COEFFICIENT_3),
.result(L1_mult_wires_3)
);
multiplier_with_reg L1_mul_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_4),
.datab (COEFFICIENT_4),
.result(L1_mult_wires_4)
);
multiplier_with_reg L1_mul_5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_5),
.datab (COEFFICIENT_5),
.result(L1_mult_wires_5)
);
multiplier_with_reg L1_mul_6(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_6),
.datab (COEFFICIENT_6),
.result(L1_mult_wires_6)
);
multiplier_with_reg L1_mul_7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_7),
.datab (COEFFICIENT_7),
.result(L1_mult_wires_7)
);
multiplier_with_reg L1_mul_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L0_output_wires_8),
.datab (COEFFICIENT_8),
.result(L1_mult_wires_8)
);
// (9 Multipliers)
// **************** Adders **************** \\
wire [dw-1:0] L1_output_wires_0;
wire [dw-1:0] L1_output_wires_1;
wire [dw-1:0] L1_output_wires_2;
wire [dw-1:0] L1_output_wires_3;
wire [dw-1:0] L1_output_wires_4;
adder_with_1_reg L1_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_0),
.datab (L1_mult_wires_1),
.result(L1_output_wires_0)
);
adder_with_1_reg L1_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_2),
.datab (L1_mult_wires_3),
.result(L1_output_wires_1)
);
adder_with_1_reg L1_adder_4and5(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_4),
.datab (L1_mult_wires_5),
.result(L1_output_wires_2)
);
adder_with_1_reg L1_adder_6and7(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_6),
.datab (L1_mult_wires_7),
.result(L1_output_wires_3)
);
// (4 main tree Adders)
// ********* Byes ******** \\
one_register L1_byereg_for_8(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_mult_wires_8),
.result(L1_output_wires_4)
);
// (1 byes)
// ************************* LEVEL 2 ************************* \\
wire [dw-1:0] L2_output_wires_0;
wire [dw-1:0] L2_output_wires_1;
wire [dw-1:0] L2_output_wires_2;
adder_with_1_reg L2_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_0),
.datab (L1_output_wires_1),
.result(L2_output_wires_0)
);
adder_with_1_reg L2_adder_2and3(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_2),
.datab (L1_output_wires_3),
.result(L2_output_wires_1)
);
// (2 main tree Adders)
// ********* Byes ******** \\
one_register L2_byereg_for_4(
.clk(clk), .clk_ena(clk_ena),
.dataa (L1_output_wires_4),
.result(L2_output_wires_2)
);
// (1 byes)
// ************************* LEVEL 3 ************************* \\
wire [dw-1:0] L3_output_wires_0;
wire [dw-1:0] L3_output_wires_1;
adder_with_1_reg L3_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_0),
.datab (L2_output_wires_1),
.result(L3_output_wires_0)
);
// (1 main tree Adders)
// ********* Byes ******** \\
one_register L3_byereg_for_2(
.clk(clk), .clk_ena(clk_ena),
.dataa (L2_output_wires_2),
.result(L3_output_wires_1)
);
// (1 byes)
// ************************* LEVEL 4 ************************* \\
wire [dw-1:0] L4_output_wires_0;
adder_with_1_reg L4_adder_0and1(
.clk(clk), .clk_ena(clk_ena),
.dataa (L3_output_wires_0),
.datab (L3_output_wires_1),
.result(L4_output_wires_0)
);
// (1 main tree Adders)
////******************************************************
// *
// * Output Logic
// *
// *****************************************************
//Actual outputs
assign o_out = L4_output_wires_0;
assign o_valid = VALID_PIPELINE_REGS[N_VALID_REGS-1];
endmodule
module input_pipeline (
clk,
clk_ena,
in_stream,
pipeline_reg_0,
pipeline_reg_1,
pipeline_reg_2,
pipeline_reg_3,
pipeline_reg_4,
pipeline_reg_5,
pipeline_reg_6,
pipeline_reg_7,
pipeline_reg_8,
pipeline_reg_9,
pipeline_reg_10,
pipeline_reg_11,
pipeline_reg_12,
pipeline_reg_13,
pipeline_reg_14,
pipeline_reg_15,
pipeline_reg_16,
reset);
parameter WIDTH = 1;
//Input value registers
input clk;
input clk_ena;
input [WIDTH-1:0] in_stream;
output [WIDTH-1:0] pipeline_reg_0;
output [WIDTH-1:0] pipeline_reg_1;
output [WIDTH-1:0] pipeline_reg_2;
output [WIDTH-1:0] pipeline_reg_3;
output [WIDTH-1:0] pipeline_reg_4;
output [WIDTH-1:0] pipeline_reg_5;
output [WIDTH-1:0] pipeline_reg_6;
output [WIDTH-1:0] pipeline_reg_7;
output [WIDTH-1:0] pipeline_reg_8;
output [WIDTH-1:0] pipeline_reg_9;
output [WIDTH-1:0] pipeline_reg_10;
output [WIDTH-1:0] pipeline_reg_11;
output [WIDTH-1:0] pipeline_reg_12;
output [WIDTH-1:0] pipeline_reg_13;
output [WIDTH-1:0] pipeline_reg_14;
output [WIDTH-1:0] pipeline_reg_15;
output [WIDTH-1:0] pipeline_reg_16;
reg [WIDTH-1:0] pipeline_reg_0;
reg [WIDTH-1:0] pipeline_reg_1;
reg [WIDTH-1:0] pipeline_reg_2;
reg [WIDTH-1:0] pipeline_reg_3;
reg [WIDTH-1:0] pipeline_reg_4;
reg [WIDTH-1:0] pipeline_reg_5;
reg [WIDTH-1:0] pipeline_reg_6;
reg [WIDTH-1:0] pipeline_reg_7;
reg [WIDTH-1:0] pipeline_reg_8;
reg [WIDTH-1:0] pipeline_reg_9;
reg [WIDTH-1:0] pipeline_reg_10;
reg [WIDTH-1:0] pipeline_reg_11;
reg [WIDTH-1:0] pipeline_reg_12;
reg [WIDTH-1:0] pipeline_reg_13;
reg [WIDTH-1:0] pipeline_reg_14;
reg [WIDTH-1:0] pipeline_reg_15;
reg [WIDTH-1:0] pipeline_reg_16;
input reset;
always@(posedge clk or posedge reset) begin
if(reset) begin
pipeline_reg_0 <= 0;
pipeline_reg_1 <= 0;
pipeline_reg_2 <= 0;
pipeline_reg_3 <= 0;
pipeline_reg_4 <= 0;
pipeline_reg_5 <= 0;
pipeline_reg_6 <= 0;
pipeline_reg_7 <= 0;
pipeline_reg_8 <= 0;
pipeline_reg_9 <= 0;
pipeline_reg_10 <= 0;
pipeline_reg_11 <= 0;
pipeline_reg_12 <= 0;
pipeline_reg_13 <= 0;
pipeline_reg_14 <= 0;
pipeline_reg_15 <= 0;
pipeline_reg_16 <= 0;
end else begin
if(clk_ena) begin
pipeline_reg_0 <= in_stream;
pipeline_reg_1 <= pipeline_reg_0;
pipeline_reg_2 <= pipeline_reg_1;
pipeline_reg_3 <= pipeline_reg_2;
pipeline_reg_4 <= pipeline_reg_3;
pipeline_reg_5 <= pipeline_reg_4;
pipeline_reg_6 <= pipeline_reg_5;
pipeline_reg_7 <= pipeline_reg_6;
pipeline_reg_8 <= pipeline_reg_7;
pipeline_reg_9 <= pipeline_reg_8;
pipeline_reg_10 <= pipeline_reg_9;
pipeline_reg_11 <= pipeline_reg_10;
pipeline_reg_12 <= pipeline_reg_11;
pipeline_reg_13 <= pipeline_reg_12;
pipeline_reg_14 <= pipeline_reg_13;
pipeline_reg_15 <= pipeline_reg_14;
pipeline_reg_16 <= pipeline_reg_15;
end //else begin
//pipeline_reg_0 <= pipeline_reg_0;
//pipeline_reg_1 <= pipeline_reg_1;
//pipeline_reg_2 <= pipeline_reg_2;
//pipeline_reg_3 <= pipeline_reg_3;
//pipeline_reg_4 <= pipeline_reg_4;
//pipeline_reg_5 <= pipeline_reg_5;
//pipeline_reg_6 <= pipeline_reg_6;
//pipeline_reg_7 <= pipeline_reg_7;
//pipeline_reg_8 <= pipeline_reg_8;
//pipeline_reg_9 <= pipeline_reg_9;
//pipeline_reg_10 <= pipeline_reg_10;
//pipeline_reg_11 <= pipeline_reg_11;
//pipeline_reg_12 <= pipeline_reg_12;
//pipeline_reg_13 <= pipeline_reg_13;
//pipeline_reg_14 <= pipeline_reg_14;
//pipeline_reg_15 <= pipeline_reg_15;
//pipeline_reg_16 <= pipeline_reg_16;
//end
end
end
endmodule
module adder_with_1_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa + datab;
end
end
endmodule
module multiplier_with_reg (
clk,
clk_ena,
dataa,
datab,
result);
input clk;
input clk_ena;
input [17:0] dataa;
input [17:0] datab;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa * datab;
end
end
endmodule
module one_register (
clk,
clk_ena,
dataa,
result);
input clk;
input clk_ena;
input [17:0] dataa;
output [17:0] result;
reg [17:0] result;
always @(posedge clk) begin
if(clk_ena) begin
result <= dataa;
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2006 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc; initial cyc = 0;
reg [63:0] crc;
reg [63:0] sum;
reg out1;
sub sub (.in(crc[23:0]), .out1(out1));
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n", $time, cyc, crc, sum, out1);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63] ^ crc[2] ^ crc[0]};
sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
if (cyc==1) begin
// Setup
crc <= 64'h00000000_00000097;
sum <= 64'h0;
end
else if (cyc==90) begin
if (sum !== 64'h2e5cb972eb02b8a0) $stop;
end
else if (cyc==91) begin
end
else if (cyc==92) begin
end
else if (cyc==93) begin
end
else if (cyc==94) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module sub (/*AUTOARG*/
// Outputs
out1,
// Inputs
in
);
input [23:0] in;
output reg [0:0] out1; // Note this tests a vector of 1 bit, which is different from a non-arrayed signal
parameter [1023:0] RANDOM = 1024'b101011010100011011100111101001000000101000001111111111100110000110011011010110011101000100110000110101111101000111100100010111001001110001010101000111000100010000010011100001100011110110110000101100011111000110111110010110011000011111111010101110001101010010001111110111100000110111101100110101110001110110000010000110101110111001111001100001101110001011100111001001110101001010000110101010100101111000010000010110100101110100110000110110101000100011101111100011000110011001100010010011001101100100101110010100110101001110011111110010000111001111000010001101100101101110111110001000010110010011100101001011111110011010110111110000110010011110001110110011010011010110011011111001110100010110100011100001011000101111000010011111010111001110110011101110101011111001100011000101000001000100111110010100111011101010101011001101000100000101111110010011010011010001111010001110000110010100011110110011001010000011001010010110111101010010011111111010001000101100010100100010011001100110000111111000001000000001001111101110000100101;
always @* begin
casez (in[17:16])
2'b00: casez (in[2:0])
3'h0: out1[0] = in[0]^RANDOM[0];
3'h1: out1[0] = in[0]^RANDOM[1];
3'h2: out1[0] = in[0]^RANDOM[2];
3'h3: out1[0] = in[0]^RANDOM[3];
3'h4: out1[0] = in[0]^RANDOM[4];
3'h5: out1[0] = in[0]^RANDOM[5];
3'h6: out1[0] = in[0]^RANDOM[6];
3'h7: out1[0] = in[0]^RANDOM[7];
endcase
2'b01: casez (in[2:0])
3'h0: out1[0] = RANDOM[10];
3'h1: out1[0] = RANDOM[11];
3'h2: out1[0] = RANDOM[12];
3'h3: out1[0] = RANDOM[13];
3'h4: out1[0] = RANDOM[14];
3'h5: out1[0] = RANDOM[15];
3'h6: out1[0] = RANDOM[16];
3'h7: out1[0] = RANDOM[17];
endcase
2'b1?: casez (in[4])
1'b1: casez (in[2:0])
3'h0: out1[0] = RANDOM[20];
3'h1: out1[0] = RANDOM[21];
3'h2: out1[0] = RANDOM[22];
3'h3: out1[0] = RANDOM[23];
3'h4: out1[0] = RANDOM[24];
3'h5: out1[0] = RANDOM[25];
3'h6: out1[0] = RANDOM[26];
3'h7: out1[0] = RANDOM[27];
endcase
1'b0: casez (in[2:0])
3'h0: out1[0] = RANDOM[30];
3'h1: out1[0] = RANDOM[31];
3'h2: out1[0] = RANDOM[32];
3'h3: out1[0] = RANDOM[33];
3'h4: out1[0] = RANDOM[34];
3'h5: out1[0] = RANDOM[35];
3'h6: out1[0] = RANDOM[36];
3'h7: out1[0] = RANDOM[37];
endcase
endcase
endcase
end
endmodule
|
// -- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
// --
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_ctrl_ecc_top.v
//
// Description:
//
// Specifications:
//
// Structure:
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
module mig_7series_v4_0_axi_ctrl_addr_decode #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
// Width of AXI-4-Lite address bus
parameter integer C_ADDR_WIDTH = 32,
// Number of Registers
parameter integer C_NUM_REG = 5,
parameter integer C_NUM_REG_WIDTH = 3,
// Number of Registers
parameter C_REG_ADDR_ARRAY = 160'h0000_f00C_0000_f008_0000_f004_0000_f000_FFFF_FFFF,
parameter C_REG_RDWR_ARRAY = 5'b00101
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// AXI4-Lite Slave Interface
// Slave Interface System Signals
input wire [C_ADDR_WIDTH-1:0] axaddr ,
// Slave Interface Write Data Ports
output wire [C_NUM_REG_WIDTH-1:0] reg_decode_num
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
function [C_ADDR_WIDTH-1:0] calc_bit_mask (
input [C_NUM_REG*C_ADDR_WIDTH-1:0] addr_decode_array
);
begin : func_calc_bit_mask
integer i;
reg [C_ADDR_WIDTH-1:0] first_addr;
reg [C_ADDR_WIDTH-1:0] bit_mask;
calc_bit_mask = {C_ADDR_WIDTH{1'b0}};
first_addr = addr_decode_array[C_ADDR_WIDTH+:C_ADDR_WIDTH];
for (i = 2; i < C_NUM_REG; i = i + 1) begin
bit_mask = first_addr ^ addr_decode_array[C_ADDR_WIDTH*i +: C_ADDR_WIDTH];
calc_bit_mask = calc_bit_mask | bit_mask;
end
end
endfunction
function integer lsb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_lsb_mask_index
lsb_mask_index = 0;
while ((lsb_mask_index < C_ADDR_WIDTH-1) && ~mask[lsb_mask_index]) begin
lsb_mask_index = lsb_mask_index + 1;
end
end
endfunction
function integer msb_mask_index (
input [C_ADDR_WIDTH-1:0] mask
);
begin : my_msb_mask_index
msb_mask_index = C_ADDR_WIDTH-1;
while ((msb_mask_index > 0) && ~mask[msb_mask_index]) begin
msb_mask_index = msb_mask_index - 1;
end
end
endfunction
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam P_ADDR_BIT_MASK = calc_bit_mask(C_REG_ADDR_ARRAY);
localparam P_MASK_LSB = lsb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_MSB = msb_mask_index(P_ADDR_BIT_MASK);
localparam P_MASK_WIDTH = P_MASK_MSB - P_MASK_LSB + 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
integer i;
(* rom_extract = "no" *)
reg [C_NUM_REG_WIDTH-1:0] reg_decode_num_i;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
always @(*) begin
reg_decode_num_i = {C_NUM_REG_WIDTH{1'b0}};
for (i = 1; i < C_NUM_REG; i = i + 1) begin : decode_addr
if ((axaddr[P_MASK_MSB:P_MASK_LSB] == C_REG_ADDR_ARRAY[i*C_ADDR_WIDTH+P_MASK_LSB+:P_MASK_WIDTH])
&& C_REG_RDWR_ARRAY[i] ) begin
reg_decode_num_i = i[C_NUM_REG_WIDTH-1:0];
end
end
end
assign reg_decode_num = reg_decode_num_i;
endmodule
`default_nettype wire
|
module RegisterTestBench2;
parameter sim_time = 750*2; // Num of Cycles * 2
reg [31:0] In;
reg Clk,Reset;
reg[15:0] Load;
wire[31:0] Out[15:0];
generate
genvar i;
for (i=0; i<=15; i=i+1) begin : registers
Register test_reg(.IN(In),
.Clk(Clk),
.Reset(Reset),
.Load(Load[i]),
.OUT(Out[i]));
end
endgenerate
integer j=0;
initial fork
//Cycle 1 == Set
//Clk = 0
In=0;Reset=1;Clk = 0;
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#1 //Clk = 1
In=1;
#1 Reset=0;
#1 Load[0]=1; // always load on tick after for loop
//#2 Clk = 0 Cycle 2
#3 for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#4 Load[1]=1;
#5 In=2;
#5 //Clk =0 Cycle 3
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#6 Load[2]=1;
#6 In=3;
#7 //Clk =0 Cycle 4
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#8 Load[3]=1;
#8 In=4;
#9 //Clk =0 Cycle 5
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#10 Load[4]=1;
#10 In=5;
#11 //Clk = 0 Cycle 6
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#12 Load[5]=1;
#12 In=6;
#13 //Clk = 0 Cycle 7
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#14 Load[6]=1;
#14 In=7;
#15 //Clk = 0 Cycle 8
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#16 Load[7]=1;
#16 In=8;
#17 //Clk = 0 Cycle 9
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#18 Load[8]=1;
#18 In=9;
#19 //Clk = 0 Cycle 10
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#20 Load[9]=1;
#20 In=10;
#21 //Clk = 0 Cycle 11
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#22 Load[10]=1;
#22 In=11;
#23 //Clk = 0 Cycle 12
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#24 Load[11]=1;
#24 In=12;
#25 //Clk = 0 Cycle 13
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#26 Load[12]=1;
#26 In=13;
#27 //Clk = 0 Cycle 13
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#28 Load[13]=1;
#28 In=14;
#29 //Clk = 0 Cycle 14
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#30 Load[14]=1;
#30 In=15;
#31 //Clk = 0 Cycle 15
for(j=0;j<=15;j=j+1)
begin
Load[j]=0;
end
#32 Load[15]=1;
#32 In=16;
join
always
#1 Clk = ~Clk;
initial #sim_time $finish; //Especifica cuando termina la simulacion
initial begin
$dumpfile("RegisterTestBench2.vcd");
$dumpvars(0,RegisterTestBench2);
$display(" Test Results" ); // imprime header
$monitor("T = %3d,Clk = %3d,In = %3d,Reset = %3d,Load[0] = %3d,Load[1] = %3d,Load[2] = %3d,Load[3] = %3d,Load[4] = %3d,Load[5] = %3d,Load[6] = %3d,Load[7] = %3d,Load[8] = %3d,Load[9] = %3d,Load[10] = %3d,Load[11] = %3d,Load[12] = %3d,Load[13] = %3d,Load[14] = %3d,Load[15] = %3d,Out[0] = %3d,Out[1] = %3d,Out[2] = %3d,Out[3] = %3d,Out[4] = %3d,Out[5] = %3d,Out[6] = %3d,Out[7] = %3d,Out[8] = %3d,Out[9] = %3d,Out[10] = %3d,Out[11] = %3d,Out[12] = %3d,Out[13] = %3d,Out[14] = %3d,Out[15] = %3d",$time,Clk,In,Reset,Load[0],Load[1],Load[2],Load[3],Load[4],Load[5],Load[6],Load[7],Load[8],Load[9],Load[10],Load[11],Load[12],Load[13],Load[14],Load[15],Out[0],Out[1],Out[2],Out[3],Out[4],Out[5],Out[6],Out[7],Out[8],Out[9],Out[10],Out[11],Out[12],Out[13],Out[14],Out[15]); //imprime se~ales
end
endmodule
//iverilog Register.v RegisterTestBench2.v
//gtkwave RegisterTestBench2.vcd |
//-----------------------------------------------------------------------------
//
// (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Spartan-6 Integrated Block for PCI Express
// File : axi_basic_tx_pipeline.v
//----------------------------------------------------------------------------//
// File: axi_basic_tx_pipeline.v //
// //
// Description: //
// AXI to TRN TX pipeline. Converts transmitted data from AXI protocol to //
// TRN. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// axi_basic_tx //
// axi_basic_tx_pipeline //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module axi_basic_tx_pipeline #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter STRB_WIDTH = C_DATA_WIDTH / 8 // TKEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [STRB_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
output trn_tecrc_gen, // TX ECRC generate
input trn_lnk_up, // PCIe link up
// System
//-----------
input tready_thrtl, // TREADY from thrtl ctl
input user_clk, // user clock from block
input user_rst // user reset from block
);
// Input register stage
reg [C_DATA_WIDTH-1:0] reg_tdata;
reg reg_tvalid;
reg [STRB_WIDTH-1:0] reg_tkeep;
reg [3:0] reg_tuser;
reg reg_tlast;
reg reg_tready;
// Pipeline utility signals
reg trn_in_packet;
reg axi_in_packet;
reg flush_axi;
wire disable_trn;
reg reg_disable_trn;
wire axi_beat_live = s_axis_tx_tvalid && s_axis_tx_tready;
wire axi_end_packet = axi_beat_live && s_axis_tx_tlast;
//----------------------------------------------------------------------------//
// Convert TRN data format to AXI data format. AXI is DWORD swapped from TRN. //
// 128-bit: 64-bit: 32-bit: //
// TRN DW0 maps to AXI DW3 TRN DW0 maps to AXI DW1 TNR DW0 maps to AXI DW0 //
// TRN DW1 maps to AXI DW2 TRN DW1 maps to AXI DW0 //
// TRN DW2 maps to AXI DW1 //
// TRN DW3 maps to AXI DW0 //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : td_DW_swap_128
assign trn_td = {reg_tdata[31:0],
reg_tdata[63:32],
reg_tdata[95:64],
reg_tdata[127:96]};
end
else if(C_DATA_WIDTH == 64) begin : td_DW_swap_64
assign trn_td = {reg_tdata[31:0], reg_tdata[63:32]};
end
else begin : td_DW_swap_32
assign trn_td = reg_tdata;
end
endgenerate
//----------------------------------------------------------------------------//
// Create trn_tsof. If we're not currently in a packet and TVALID goes high, //
// assert TSOF. //
//----------------------------------------------------------------------------//
assign trn_tsof = reg_tvalid && !trn_in_packet;
//----------------------------------------------------------------------------//
// Create trn_in_packet. This signal tracks if the TRN interface is currently //
// in the middle of a packet, which is needed to generate trn_tsof //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
trn_in_packet <= #TCQ 1'b0;
end
else begin
if(trn_tsof && trn_tsrc_rdy && trn_tdst_rdy && !trn_teof) begin
trn_in_packet <= #TCQ 1'b1;
end
else if((trn_in_packet && trn_teof && trn_tsrc_rdy) || !trn_lnk_up) begin
trn_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create axi_in_packet. This signal tracks if the AXI interface is currently //
// in the middle of a packet, which is needed in case the link goes down. //
//----------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
axi_in_packet <= #TCQ 1'b0;
end
else begin
if(axi_beat_live && !s_axis_tx_tlast) begin
axi_in_packet <= #TCQ 1'b1;
end
else if(axi_beat_live) begin
axi_in_packet <= #TCQ 1'b0;
end
end
end
//----------------------------------------------------------------------------//
// Create disable_trn. This signal asserts when the link goes down and //
// triggers the deassertiong of trn_tsrc_rdy. The deassertion of disable_trn //
// depends on C_PM_PRIORITY, as described below. //
//----------------------------------------------------------------------------//
generate
// In the C_PM_PRIORITY pipeline, we disable the TRN interfacefrom the time
// the link goes down until the the AXI interface is ready to accept packets
// again (via assertion of TREADY). By waiting for TREADY, we allow the
// previous value buffer to fill, so we're ready for any throttling by the
// user or the block.
if(C_PM_PRIORITY == "TRUE") begin : pm_priority_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b1;
end
else begin
// When the link goes down, disable the TRN interface.
if(!trn_lnk_up)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// When the link comes back up and the AXI interface is ready, we can
// release the pipeline and return to normal operation.
else if(!flush_axi && s_axis_tx_tready) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
assign disable_trn = reg_disable_trn;
end
// In the throttle-controlled pipeline, we don't have a previous value buffer.
// The throttle control mechanism handles TREADY, so all we need to do is
// detect when the link goes down and disable the TRN interface until the link
// comes back up and the AXI interface is finished flushing any packets.
else begin : thrtl_ctl_trn_flush
always @(posedge user_clk) begin
if(user_rst) begin
reg_disable_trn <= #TCQ 1'b0;
end
else begin
// If the link is down and AXI is in packet, disable TRN and look for
// the end of the packet
if(axi_in_packet && !trn_lnk_up && !axi_end_packet)
begin
reg_disable_trn <= #TCQ 1'b1;
end
// AXI packet is ending, so we're done flushing
else if(axi_end_packet) begin
reg_disable_trn <= #TCQ 1'b0;
end
end
end
// Disable the TRN interface if link is down or we're still flushing the AXI
// interface.
assign disable_trn = reg_disable_trn || !trn_lnk_up;
end
endgenerate
//----------------------------------------------------------------------------//
// Convert STRB to RREM. Here, we are converting the encoding method for the //
// location of the EOF from AXI (TKEEP) to TRN flavor (rrem). //
//----------------------------------------------------------------------------//
generate
if(C_DATA_WIDTH == 128) begin : tkeep_to_trem_128
//---------------------------------------//
// Conversion table: //
// trem | tkeep //
// [1] [0] | [15:12] [11:8] [7:4] [3:0] //
// ------------------------------------- //
// 1 1 | D3 D2 D1 D0 //
// 1 0 | -- D2 D1 D0 //
// 0 1 | -- -- D1 D0 //
// 0 0 | -- -- -- D0 //
//---------------------------------------//
wire axi_DW_1 = reg_tkeep[7];
wire axi_DW_2 = reg_tkeep[11];
wire axi_DW_3 = reg_tkeep[15];
assign trn_trem[1] = axi_DW_2;
assign trn_trem[0] = axi_DW_3 || (axi_DW_1 && !axi_DW_2);
end
else if(C_DATA_WIDTH == 64) begin : tkeep_to_trem_64
assign trn_trem = reg_tkeep[7];
end
else begin : tkeep_to_trem_32
assign trn_trem = 1'b0;
end
endgenerate
//----------------------------------------------------------------------------//
// Create remaining TRN signals //
//----------------------------------------------------------------------------//
assign trn_teof = reg_tlast;
assign trn_tecrc_gen = reg_tuser[0];
assign trn_terrfwd = reg_tuser[1];
assign trn_tstr = reg_tuser[2];
assign trn_tsrc_dsc = reg_tuser[3];
//----------------------------------------------------------------------------//
// Pipeline stage //
//----------------------------------------------------------------------------//
// We need one of two approaches for the pipeline stage depending on the
// C_PM_PRIORITY parameter.
generate
reg reg_tsrc_rdy;
// If set to FALSE, that means the user wants to use the TX packet boundary
// throttling feature. Since all Block throttling will now be predicted, we
// can use a simple straight-through pipeline.
if(C_PM_PRIORITY == "FALSE") begin : throttle_ctl_pipeline
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {STRB_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tsrc_rdy <= #TCQ 1'b0;
end
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
// Hold trn_tsrc_rdy low when flushing a packet.
reg_tsrc_rdy <= #TCQ axi_beat_live && !disable_trn;
end
end
assign trn_tsrc_rdy = reg_tsrc_rdy;
// With TX packet boundary throttling, TREADY is pipelined in
// axi_basic_tx_thrtl_ctl and wired through here.
assign s_axis_tx_tready = tready_thrtl;
end
//**************************************************************************//
// If C_PM_PRIORITY is set to TRUE, that means the user prefers to have all PM
// functionality intact isntead of TX packet boundary throttling. Now the
// Block could back-pressure at any time, which creates the standard problem
// of potential data loss due to the handshaking latency. Here we need a
// previous value buffer, just like the RX data path.
else begin : pm_prioity_pipeline
reg [C_DATA_WIDTH-1:0] tdata_prev;
reg tvalid_prev;
reg [STRB_WIDTH-1:0] tkeep_prev;
reg tlast_prev;
reg [3:0] tuser_prev;
reg reg_tdst_rdy;
wire data_hold;
reg data_prev;
//------------------------------------------------------------------------//
// Previous value buffer //
// --------------------- //
// We are inserting a pipeline stage in between AXI and TRN, which causes //
// some issues with handshaking signals trn_tsrc_rdy/s_axis_tx_tready. //
// The added cycle of latency in the path causes the Block to fall behind //
// the AXI interface whenever it throttles. //
// //
// To avoid loss of data, we must keep the previous value of all //
// s_axis_tx_* signals in case the Block throttles. //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
tdata_prev <= #TCQ {C_DATA_WIDTH{1'b0}};
tvalid_prev <= #TCQ 1'b0;
tkeep_prev <= #TCQ {STRB_WIDTH{1'b0}};
tlast_prev <= #TCQ 1'b0;
tuser_prev <= #TCQ 4'h 0;
end
else begin
// prev buffer works by checking s_axis_tx_tready. When
// s_axis_tx_tready is asserted, a new value is present on the
// interface.
if(!s_axis_tx_tready) begin
tdata_prev <= #TCQ tdata_prev;
tvalid_prev <= #TCQ tvalid_prev;
tkeep_prev <= #TCQ tkeep_prev;
tlast_prev <= #TCQ tlast_prev;
tuser_prev <= #TCQ tuser_prev;
end
else begin
tdata_prev <= #TCQ s_axis_tx_tdata;
tvalid_prev <= #TCQ s_axis_tx_tvalid;
tkeep_prev <= #TCQ s_axis_tx_tkeep;
tlast_prev <= #TCQ s_axis_tx_tlast;
tuser_prev <= #TCQ s_axis_tx_tuser;
end
end
end
// Create special buffer which locks in the proper value of TDATA depending
// on whether the user is throttling or not. This buffer has three states:
//
// HOLD state: TDATA maintains its current value
// - the Block has throttled the PCIe block
// PREVIOUS state: the buffer provides the previous value on TDATA
// - the Block has finished throttling, and is a little
// behind the user
// CURRENT state: the buffer passes the current value on TDATA
// - the Block is caught up and ready to receive the
// latest data from the user
always @(posedge user_clk) begin
if(user_rst) begin
reg_tdata <= #TCQ {C_DATA_WIDTH{1'b0}};
reg_tvalid <= #TCQ 1'b0;
reg_tkeep <= #TCQ {STRB_WIDTH{1'b0}};
reg_tlast <= #TCQ 1'b0;
reg_tuser <= #TCQ 4'h0;
reg_tdst_rdy <= #TCQ 1'b0;
end
else begin
reg_tdst_rdy <= #TCQ trn_tdst_rdy;
if(!data_hold) begin
// PREVIOUS state
if(data_prev) begin
reg_tdata <= #TCQ tdata_prev;
reg_tvalid <= #TCQ tvalid_prev;
reg_tkeep <= #TCQ tkeep_prev;
reg_tlast <= #TCQ tlast_prev;
reg_tuser <= #TCQ tuser_prev;
end
// CURRENT state
else begin
reg_tdata <= #TCQ s_axis_tx_tdata;
reg_tvalid <= #TCQ s_axis_tx_tvalid;
reg_tkeep <= #TCQ s_axis_tx_tkeep;
reg_tlast <= #TCQ s_axis_tx_tlast;
reg_tuser <= #TCQ s_axis_tx_tuser;
end
end
// else HOLD state
end
end
// Logic to instruct pipeline to hold its value
assign data_hold = trn_tsrc_rdy && !trn_tdst_rdy;
// Logic to instruct pipeline to use previous bus values. Always use
// previous value after holding a value.
always @(posedge user_clk) begin
if(user_rst) begin
data_prev <= #TCQ 1'b0;
end
else begin
data_prev <= #TCQ data_hold;
end
end
//------------------------------------------------------------------------//
// Create trn_tsrc_rdy. If we're flushing the TRN hold trn_tsrc_rdy low. //
//------------------------------------------------------------------------//
assign trn_tsrc_rdy = reg_tvalid && !disable_trn;
//------------------------------------------------------------------------//
// Create TREADY //
//------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
reg_tready <= #TCQ 1'b0;
end
else begin
// If the link went down and we need to flush a packet in flight, hold
// TREADY high
if(flush_axi && !axi_end_packet) begin
reg_tready <= #TCQ 1'b1;
end
// If the link is up, TREADY is as follows:
// TREADY = 1 when trn_tsrc_rdy == 0
// - While idle, keep the pipeline primed and ready for the next
// packet
//
// TREADY = trn_tdst_rdy when trn_tsrc_rdy == 1
// - While in packet, throttle pipeline based on state of TRN
else if(trn_lnk_up) begin
reg_tready <= #TCQ trn_tdst_rdy || !trn_tsrc_rdy;
end
// If the link is down and we're not flushing a packet, hold TREADY low
// wait for link to come back up
else begin
reg_tready <= #TCQ 1'b0;
end
end
end
assign s_axis_tx_tready = reg_tready;
end
//--------------------------------------------------------------------------//
// Create flush_axi. This signal detects if the link goes down while the //
// AXI interface is in packet. In this situation, we need to flush the //
// packet through the AXI interface and discard it. //
//--------------------------------------------------------------------------//
always @(posedge user_clk) begin
if(user_rst) begin
flush_axi <= #TCQ 1'b0;
end
else begin
// If the AXI interface is in packet and the link goes down, purge it.
if(axi_in_packet && !trn_lnk_up && !axi_end_packet) begin
flush_axi <= #TCQ 1'b1;
end
// The packet is finished, so we're done flushing.
else if(axi_end_packet) begin
flush_axi <= #TCQ 1'b0;
end
end
end
endgenerate
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__OR2_1_V
`define SKY130_FD_SC_HDLL__OR2_1_V
/**
* or2: 2-input OR.
*
* Verilog wrapper for or2 with size of 1 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hdll__or2.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_1 (
X ,
A ,
B ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A ;
input B ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hdll__or2_1 (
X,
A,
B
);
output X;
input A;
input B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hdll__or2 base (
.X(X),
.A(A),
.B(B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__OR2_1_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [6:0] mem1d;
reg [6:0] mem2d [5:0];
reg [6:0] mem3d [4:0][5:0];
integer i,j,k;
// Four different test cases for out of bounds
// =
// <=
// Continuous assigns
// Output pin interconnect (also covers cont assigns)
// Each with both bit selects and array selects
initial begin
mem1d[0] = 1'b0;
i=7;
mem1d[i] = 1'b1;
if (mem1d[0] !== 1'b0) $stop;
//
for (i=0; i<8; i=i+1) begin
for (j=0; j<8; j=j+1) begin
for (k=0; k<8; k=k+1) begin
mem1d[k] = k[0];
mem2d[j][k] = j[0]+k[0];
mem3d[i][j][k] = i[0]+j[0]+k[0];
end
end
end
for (i=0; i<5; i=i+1) begin
for (j=0; j<6; j=j+1) begin
for (k=0; k<7; k=k+1) begin
if (mem1d[k] !== k[0]) $stop;
if (mem2d[j][k] !== j[0]+k[0]) $stop;
if (mem3d[i][j][k] !== i[0]+j[0]+k[0]) $stop;
end
end
end
end
integer wi;
wire [31:0] wd = cyc;
reg [31:0] reg2d[6:0];
always @ (posedge clk) reg2d[wi[2:0]] <= wd;
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d reg2d[%0d]=%0x wd=%0x\n",$time, cyc, wi[2:0], reg2d[wi[2:0]], wd);
`endif
cyc <= cyc + 1;
if (cyc<10) begin
wi <= 0;
end
else if (cyc==10) begin
wi <= 1;
end
else if (cyc==11) begin
if (reg2d[0] !== 10) $stop;
wi <= 6;
end
else if (cyc==12) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
wi <= 7; // Will be ignored
end
else if (cyc==13) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==14) begin
if (reg2d[0] !== 10) $stop;
if (reg2d[1] !== 11) $stop;
if (reg2d[6] !== 12) $stop;
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*+--------------------------------------------------------------------------
Copyright (c) 2015, Microsoft Corporation
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
* Redistributions of source code must retain the above copyright notice, this
list of conditions and the following disclaimer.
* Redistributions in binary form must reproduce the above copyright notice,
this list of conditions and the following disclaimer in the documentation
and/or other materials provided with the distribution.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
//////////////////////////////////////////////////////////////////////////////////
// Company: Microsoft Research Asia
// Engineer: Jiansong Zhang
//
// Create Date: 21:39:39 06/01/2009
// Design Name:
// Module Name: tx_engine
// Project Name: Sora
// Target Devices: Virtex5 LX50T
// Tool versions: ISE10.1.03
// Description:
// Purpose: Detects rising edge of input signal and outputs a single-shot
// signal upon detection
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
module rising_edge_detect(
input clk,
input rst,
input in,
output one_shot_out);
reg in_reg;
//register the input
always@(posedge clk)begin
if(rst)begin
in_reg <= 1'b0;
end else begin
in_reg <= in;
end
end
//detect the rising edge
assign one_shot_out = ~in_reg & in;
endmodule
|
//------------------------------------------------------------------------------
// This confidential and proprietary software may be used only as authorized by
// a licensing agreement from Altera Corporation.
//
// Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
// use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any
// output files any of the foregoing (including device programming or
// simulation files), and any associated documentation or information are
// expressly subject to the terms and conditions of the Altera Program
// License Subscription Agreement or other applicable license agreement,
// including, without limitation, that your use is for the sole purpose
// of programming logic devices manufactured by Altera and sold by Altera
// or its authorized distributors. Please refer to the applicable
// agreement for further details.
//
// The entire notice above must be reproduced on all authorized copies and any
// such reproduction must be pursuant to a licensing agreement from Altera.
//
// Title : Example top level testbench for ddr3_int DDR/2/3 SDRAM High Performance Controller
// Project : DDR/2/3 SDRAM High Performance Controller
//
// File : ddr3_int_example_top_tb.v
//
// Revision : V10.0
//
// Abstract:
// Automatically generated testbench for the example top level design to allow
// functional and timing simulation.
//
//------------------------------------------------------------------------------
//
// *************** This is a MegaWizard generated file ****************
//
// If you need to edit this file make sure the edits are not inside any 'MEGAWIZARD'
// text insertion areas.
// (between "<< START MEGAWIZARD INSERT" and "<< END MEGAWIZARD INSERT" comments)
//
// Any edits inside these delimiters will be overwritten by the megawizard if you
// re-run it.
//
// If you really need to make changes inside these delimiters then delete
// both 'START' and 'END' delimiters. This will stop the megawizard updating this
// section again.
//
//----------------------------------------------------------------------------------
// << START MEGAWIZARD INSERT PARAMETER_LIST
// Parameters:
//
// Device Family : arria ii gx
// local Interface Data Width : 128
// MEM_CHIPSELS : 1
// MEM_CS_PER_RANK : 1
// MEM_BANK_BITS : 3
// MEM_ROW_BITS : 14
// MEM_COL_BITS : 10
// LOCAL_DATA_BITS : 128
// NUM_CLOCK_PAIRS : 1
// CLOCK_TICK_IN_PS : 3333
// REGISTERED_DIMM : false
// TINIT_CLOCKS : 75008
// Data_Width_Ratio : 4
// << END MEGAWIZARD INSERT PARAMETER_LIST
//----------------------------------------------------------------------------------
// << MEGAWIZARD PARSE FILE DDR10.0
`timescale 1 ps/1 ps
// << START MEGAWIZARD INSERT MODULE
module ddr3_int_example_top_tb ();
// << END MEGAWIZARD INSERT MODULE
// << START MEGAWIZARD INSERT PARAMS
parameter gMEM_CHIPSELS = 1;
parameter gMEM_CS_PER_RANK = 1;
parameter gMEM_NUM_RANKS = 1 / 1;
parameter gMEM_BANK_BITS = 3;
parameter gMEM_ROW_BITS = 14;
parameter gMEM_COL_BITS = 10;
parameter gMEM_ADDR_BITS = 14;
parameter gMEM_DQ_PER_DQS = 8;
parameter DM_DQS_WIDTH = 4;
parameter gLOCAL_DATA_BITS = 128;
parameter gLOCAL_IF_DWIDTH_AFTER_ECC = 128;
parameter gNUM_CLOCK_PAIRS = 1;
parameter RTL_ROUNDTRIP_CLOCKS = 0.0;
parameter CLOCK_TICK_IN_PS = 3333;
parameter REGISTERED_DIMM = 1'b0;
parameter BOARD_DQS_DELAY = 0;
parameter BOARD_CLK_DELAY = 0;
parameter DWIDTH_RATIO = 4;
parameter TINIT_CLOCKS = 75008;
parameter REF_CLOCK_TICK_IN_PS = 40000;
// Parameters below are for generic memory model
parameter gMEM_TQHS_PS = 300;
parameter gMEM_TAC_PS = 400;
parameter gMEM_TDQSQ_PS = 125;
parameter gMEM_IF_TRCD_NS = 13.5;
parameter gMEM_IF_TWTR_CK = 4;
parameter gMEM_TDSS_CK = 0.2;
parameter gMEM_IF_TRFC_NS = 110.0;
parameter gMEM_IF_TRP_NS = 13.5;
parameter gMEM_IF_TRCD_PS = gMEM_IF_TRCD_NS * 1000.0;
parameter gMEM_IF_TWTR_PS = gMEM_IF_TWTR_CK * CLOCK_TICK_IN_PS;
parameter gMEM_IF_TRFC_PS = gMEM_IF_TRFC_NS * 1000.0;
parameter gMEM_IF_TRP_PS = gMEM_IF_TRP_NS * 1000.0;
parameter CLOCK_TICK_IN_NS = CLOCK_TICK_IN_PS / 1000.0;
parameter gMEM_TDQSQ_NS = gMEM_TDQSQ_PS / 1000.0;
parameter gMEM_TDSS_NS = gMEM_TDSS_CK * CLOCK_TICK_IN_NS;
// << END MEGAWIZARD INSERT PARAMS
// set to zero for Gatelevel
parameter RTL_DELAYS = 1;
parameter USE_GENERIC_MEMORY_MODEL = 1'b0;
// The round trip delay is now modeled inside the datapath (<your core name>_auk_ddr_dqs_group.v/vhd) for RTL simulation.
parameter D90_DEG_DELAY = 0; //RTL only
parameter GATE_BOARD_DQS_DELAY = BOARD_DQS_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
parameter GATE_BOARD_CLK_DELAY = BOARD_CLK_DELAY * (RTL_DELAYS ? 0 : 1); // Gate level timing only
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
parameter gMEM_CLK_PHASE_EN = "false";
parameter real gMEM_CLK_PHASE = 0;
parameter real MEM_CLK_RATIO = ((360.0-gMEM_CLK_PHASE)/360.0);
parameter MEM_CLK_DELAY = MEM_CLK_RATIO*CLOCK_TICK_IN_PS * ((gMEM_CLK_PHASE_EN=="true") ? 1 : 0);
wire clk_to_ram0, clk_to_ram1, clk_to_ram2;
wire cmd_bus_watcher_enabled;
reg clk;
reg clk_n;
reg reset_n;
wire mem_reset_n;
wire[gMEM_ADDR_BITS - 1:0] a;
wire[gMEM_BANK_BITS - 1:0] ba;
wire[gMEM_CHIPSELS - 1:0] cs_n;
wire[gMEM_NUM_RANKS - 1:0] cke;
wire[gMEM_NUM_RANKS - 1:0] odt; //DDR2 only
wire ras_n;
wire cas_n;
wire we_n;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs;
//wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dqs_n;
//wire stratix_dqs_ref_clk; // only used on stratix to provide external dll reference clock
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram;
wire[gNUM_CLOCK_PAIRS - 1:0] clk_to_sdram_n;
wire #(GATE_BOARD_CLK_DELAY * 1) clk_to_ram;
wire clk_to_ram_n;
wire[gMEM_ROW_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) a_delayed;
wire[gMEM_BANK_BITS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) ba_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cke_delayed;
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) odt_delayed; //DDR2 only
wire[gMEM_NUM_RANKS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 + 1) cs_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) ras_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) cas_n_delayed;
wire #(GATE_BOARD_CLK_DELAY * 1 + 1) we_n_delayed;
wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;
// DDR3 parity only
wire ac_parity;
wire mem_err_out_n;
assign mem_err_out_n = 1'b1;
// pulldown (dm);
assign (weak1, weak0) dm = 0;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO - 1:0] mem_dq = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs = 100'bz;
tri [gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] mem_dqs_n = 100'bz;
assign (weak1, weak0) mem_dq = 0;
assign (weak1, weak0) mem_dqs = 0;
assign (weak1, weak0) mem_dqs_n = 1;
wire [gMEM_BANK_BITS - 1:0] zero_one; //"01";
assign zero_one = 1;
wire test_complete;
wire [7:0] test_status;
// counter to count the number of sucessful read and write loops
integer test_complete_count;
wire pnf;
wire [gLOCAL_IF_DWIDTH_AFTER_ECC / 8 - 1:0] pnf_per_byte;
assign cmd_bus_watcher_enabled = 1'b0;
// Below 5 lines for SPR272543:
// Testbench workaround for tests with "dedicated memory clock phase shift" failing,
// because dqs delay isnt' being modelled in simulations
assign #(MEM_CLK_DELAY/4.0) clk_to_ram2 = clk_to_sdram[0];
assign #(MEM_CLK_DELAY/4.0) clk_to_ram1 = clk_to_ram2;
assign #(MEM_CLK_DELAY/4.0) clk_to_ram0 = clk_to_ram1;
assign #((MEM_CLK_DELAY/4.0)) clk_to_ram = clk_to_ram0;
assign clk_to_ram_n = ~clk_to_ram ; // mem model ignores clk_n ?
// ddr sdram interface
// << START MEGAWIZARD INSERT ENTITY
ddr3_int_example_top dut (
// << END MEGAWIZARD INSERT ENTITY
.clock_source(clk),
.global_reset_n(reset_n),
// << START MEGAWIZARD INSERT PORT_MAP
.mem_clk(clk_to_sdram),
.mem_clk_n(clk_to_sdram_n),
.mem_odt(odt),
.mem_dqsn(mem_dqs_n),
.mem_reset_n(mem_reset_n),
.mem_cke(cke),
.mem_cs_n(cs_n),
.mem_ras_n(ras_n),
.mem_cas_n(cas_n),
.mem_we_n(we_n),
.mem_ba(ba),
.mem_addr(a),
.mem_dq(mem_dq),
.mem_dqs(mem_dqs),
.mem_dm(dm),
// << END MEGAWIZARD INSERT PORT_MAP
.test_complete(test_complete),
.test_status(test_status),
.pnf_per_byte(pnf_per_byte),
.pnf(pnf)
);
// << START MEGAWIZARD INSERT MEMORY_ARRAY
// This will need updating to match the memory models you are using.
// Instantiate a generated DDR memory model to match the datawidth & chipselect requirements
ddr3_int_mem_model mem (
.mem_rst_n (mem_reset_n),
.mem_dq (mem_dq),
.mem_dqs (mem_dqs),
.mem_dqs_n (mem_dqs_n),
.mem_addr (a_delayed),
.mem_ba (ba_delayed),
.mem_clk (clk_to_ram),
.mem_clk_n (clk_to_ram_n),
.mem_cke (cke_delayed),
.mem_cs_n (cs_n_delayed),
.mem_ras_n (ras_n_delayed),
.mem_cas_n (cas_n_delayed),
.mem_we_n (we_n_delayed),
.mem_dm (dm_delayed),
.mem_odt (odt_delayed)
);
// << END MEGAWIZARD INSERT MEMORY_ARRAY
always
begin
clk <= 1'b0 ;
clk_n <= 1'b1 ;
while (1'b1)
begin
#((REF_CLOCK_TICK_IN_PS / 2) * 1);
clk <= ~clk ;
clk_n <= ~clk_n ;
end
end
initial
begin
reset_n <= 1'b0 ;
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
@(clk);
reset_n <= 1'b1 ;
end
// control and data lines = 3 inches
assign a_delayed = a[gMEM_ROW_BITS - 1:0] ;
assign ba_delayed = ba ;
assign cke_delayed = cke ;
assign odt_delayed = odt ;
assign cs_n_delayed = cs_n ;
assign ras_n_delayed = ras_n ;
assign cas_n_delayed = cas_n ;
assign we_n_delayed = we_n ;
assign dm_delayed = dm ;
// ---------------------------------------------------------------
initial
begin : endit
integer count;
reg ln;
count = 0;
// Stop simulation after test_complete or TINIT + 600000 clocks
while ((count < (TINIT_CLOCKS + 600000)) & (test_complete !== 1))
begin
count = count + 1;
@(negedge clk_to_sdram[0]);
end
if (test_complete === 1)
begin
if (pnf)
begin
$write($time);
$write(" --- SIMULATION PASSED --- ");
$stop;
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED --- ");
$stop;
end
end
else
begin
$write($time);
$write(" --- SIMULATION FAILED, DID NOT COMPLETE --- ");
$stop;
end
end
always @(clk_to_sdram[0] or reset_n)
begin
if (!reset_n)
begin
test_complete_count <= 0 ;
end
else if ((clk_to_sdram[0]))
begin
if (test_complete)
begin
test_complete_count <= test_complete_count + 1 ;
end
end
end
reg[2:0] cmd_bus;
//***********************************************************
// Watch the SDRAM command bus
always @(clk_to_ram)
begin
if (clk_to_ram)
begin
if (1'b1)
begin
cmd_bus = {ras_n_delayed, cas_n_delayed, we_n_delayed};
case (cmd_bus)
3'b000 :
begin
// LMR command
$write($time);
if (ba_delayed == zero_one)
begin
$write(" ELMR settings = ");
if (!(a_delayed[0]))
begin
$write("DLL enable");
end
end
else
begin
$write(" LMR settings = ");
case (a_delayed[1:0])
3'b00 : $write("BL = 8,");
3'b01 : $write("BL = On The Fly,");
3'b10 : $write("BL = 4,");
default : $write("BL = ??,");
endcase
case (a_delayed[6:4])
3'b001 : $write(" CL = 5.0,");
3'b010 : $write(" CL = 6.0,");
3'b011 : $write(" CL = 7.0,");
3'b100 : $write(" CL = 8.0,");
3'b101 : $write(" CL = 9.0,");
3'b110 : $write(" CL = 10.0,");
default : $write(" CL = ??,");
endcase
if ((a_delayed[8])) $write(" DLL reset");
end
$write("\n");
end
3'b001 :
begin
// ARF command
$write($time);
$write(" ARF\n");
end
3'b010 :
begin
// PCH command
$write($time);
$write(" PCH");
if ((a_delayed[10]))
begin
$write(" all banks \n");
end
else
begin
$write(" bank ");
$write("%H\n", ba_delayed);
end
end
3'b011 :
begin
// ACT command
$write($time);
$write(" ACT row address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b100 :
begin
// WR command
$write($time);
$write(" WR to col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b101 :
begin
// RD command
$write($time);
$write(" RD from col address ");
$write("%H", a_delayed);
$write(" bank ");
$write("%H\n", ba_delayed);
end
3'b110 :
begin
// BT command
$write($time);
$write(" BT ");
end
3'b111 :
begin
// NOP command
end
endcase
end
else
begin
end // if enabled
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HD__AND4B_4_V
`define SKY130_FD_SC_HD__AND4B_4_V
/**
* and4b: 4-input AND, first input inverted.
*
* Verilog wrapper for and4b with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_hd__and4b.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N ,
B ,
C ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A_N ;
input B ;
input C ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_hd__and4b_4 (
X ,
A_N,
B ,
C ,
D
);
output X ;
input A_N;
input B ;
input C ;
input D ;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_hd__and4b base (
.X(X),
.A_N(A_N),
.B(B),
.C(C),
.D(D)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_HD__AND4B_4_V
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
`define SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
/**
* mux2i: 2-input multiplexer, output inverted.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hdll__mux2i (
Y ,
A0 ,
A1 ,
S ,
VPWR,
VGND,
VPB ,
VNB
);
output Y ;
input A0 ;
input A1 ;
input S ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HDLL__MUX2I_PP_BLACKBOX_V
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
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// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : ecc_gen.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
`timescale 1ps/1ps
// Generate the ecc code. Note that the synthesizer should
// generate this as a static logic. Code in this block should
// never run during simulation phase, or directly impact timing.
//
// The code generated is a single correct, double detect code.
// It is the classic Hamming code. Instead, the code is
// optimized for minimal/balanced tree depth and size. See
// Hsiao IBM Technial Journal 1970.
//
// The code is returned as a single bit vector, h_rows. This was
// the only way to "subroutinize" this with the restrictions of
// disallowed include files and that matrices cannot be passed
// in ports.
//
// Factorial and the combos functions are defined. Combos
// simply computes the number of combinations from the set
// size and elements at a time.
//
// The function next_combo computes the next combination in
// lexicographical order given the "current" combination. Its
// output is undefined if given the last combination in the
// lexicographical order.
//
// next_combo is insensitive to the number of elements in the
// combinations.
//
// An H transpose matrix is generated because that's the easiest
// way to do it. The H transpose matrix is generated by taking
// the one at a time combinations, then the 3 at a time, then
// the 5 at a time. The number combinations used is equal to
// the width of the code (CODE_WIDTH). The boundaries between
// the 1, 3 and 5 groups are hardcoded in the for loop.
//
// At the same time the h_rows vector is generated from the
// H transpose matrix.
module mig_7series_v2_3_ecc_gen
#(
parameter CODE_WIDTH = 72,
parameter ECC_WIDTH = 8,
parameter DATA_WIDTH = 64
)
(
/*AUTOARG*/
// Outputs
h_rows
);
function integer factorial (input integer i);
integer index;
if (i == 1) factorial = 1;
else begin
factorial = 1;
for (index=2; index<=i; index=index+1)
factorial = factorial * index;
end
endfunction // factorial
function integer combos (input integer n, k);
combos = factorial(n)/(factorial(k)*factorial(n-k));
endfunction // combinations
// function next_combo
// Given a combination, return the next combo in lexicographical
// order. Scans from right to left. Assumes the first combination
// is k ones all of the way to the left.
//
// Upon entry, initialize seen0, trig1, and ones. "seen0" means
// that a zero has been observed while scanning from right to left.
// "trig1" means that a one have been observed _after_ seen0 is set.
// "ones" counts the number of ones observed while scanning the input.
//
// If trig1 is one, just copy the input bit to the output and increment
// to the next bit. Otherwise set the the output bit to zero, if the
// input is a one, increment ones. If the input bit is a one and seen0
// is true, dump out the accumulated ones. Set seen0 to the complement
// of the input bit. Note that seen0 is not used subsequent to trig1
// getting set.
function [ECC_WIDTH-1:0] next_combo (input [ECC_WIDTH-1:0] i);
integer index;
integer dump_index;
reg seen0;
reg trig1;
// integer ones;
reg [ECC_WIDTH-1:0] ones;
begin
seen0 = 1'b0;
trig1 = 1'b0;
ones = 0;
for (index=0; index<ECC_WIDTH; index=index+1)
begin
// The "== 1'bx" is so this will converge at time zero.
// XST assumes false, which should be OK.
if ((&i == 1'bx) || trig1) next_combo[index] = i[index];
else begin
next_combo[index] = 1'b0;
ones = ones + i[index];
if (i[index] && seen0) begin
trig1 = 1'b1;
for (dump_index=index-1; dump_index>=0;dump_index=dump_index-1)
if (dump_index>=index-ones) next_combo[dump_index] = 1'b1;
end
seen0 = ~i[index];
end // else: !if(trig1)
end
end // function
endfunction // next_combo
wire [ECC_WIDTH-1:0] ht_matrix [CODE_WIDTH-1:0];
output wire [CODE_WIDTH*ECC_WIDTH-1:0] h_rows;
localparam COMBOS_3 = combos(ECC_WIDTH, 3);
localparam COMBOS_5 = combos(ECC_WIDTH, 5);
genvar n;
genvar s;
generate
for (n=0; n<CODE_WIDTH; n=n+1) begin : ht
if (n == 0)
assign ht_matrix[n] = {{3{1'b1}}, {ECC_WIDTH-3{1'b0}}};
else if (n == COMBOS_3 && n < DATA_WIDTH)
assign ht_matrix[n] = {{5{1'b1}}, {ECC_WIDTH-5{1'b0}}};
else if ((n == COMBOS_3+COMBOS_5) && n < DATA_WIDTH)
assign ht_matrix[n] = {{7{1'b1}}, {ECC_WIDTH-7{1'b0}}};
else if (n == DATA_WIDTH)
assign ht_matrix[n] = {{1{1'b1}}, {ECC_WIDTH-1{1'b0}}};
else assign ht_matrix[n] = next_combo(ht_matrix[n-1]);
for (s=0; s<ECC_WIDTH; s=s+1) begin : h_row
assign h_rows[s*CODE_WIDTH+n] = ht_matrix[n][s];
end
end
endgenerate
endmodule // ecc_gen
|
// stereo volume control
// channel 1&2 --> left
// channel 0&3 --> right
module paula_audio_mixer (
input clk, //bus clock
input clk7_en,
input [7:0] sample0, //sample 0 input
input [7:0] sample1, //sample 1 input
input [7:0] sample2, //sample 2 input
input [7:0] sample3, //sample 3 input
input [6:0] vol0, //volume 0 input
input [6:0] vol1, //volume 1 input
input [6:0] vol2, //volume 2 input
input [6:0] vol3, //volume 3 input
output reg [14:0]ldatasum, //left DAC data
output reg [14:0]rdatasum //right DAC data
);
// volume control
wire [14-1:0] msample0, msample1, msample2, msample3;
// when volume MSB is set, volume is always maximum
paula_audio_volume sv0
(
.sample(sample0),
.volume({ (vol0[6] | vol0[5]),
(vol0[6] | vol0[4]),
(vol0[6] | vol0[3]),
(vol0[6] | vol0[2]),
(vol0[6] | vol0[1]),
(vol0[6] | vol0[0]) }),
.out(msample0)
);
paula_audio_volume sv1
(
.sample(sample1),
.volume({ (vol1[6] | vol1[5]),
(vol1[6] | vol1[4]),
(vol1[6] | vol1[3]),
(vol1[6] | vol1[2]),
(vol1[6] | vol1[1]),
(vol1[6] | vol1[0]) }),
.out(msample1)
);
paula_audio_volume sv2
(
.sample(sample2),
.volume({ (vol2[6] | vol2[5]),
(vol2[6] | vol2[4]),
(vol2[6] | vol2[3]),
(vol2[6] | vol2[2]),
(vol2[6] | vol2[1]),
(vol2[6] | vol2[0]) }),
.out(msample2)
);
paula_audio_volume sv3
(
.sample(sample3),
.volume({ (vol3[6] | vol3[5]),
(vol3[6] | vol3[4]),
(vol3[6] | vol3[3]),
(vol3[6] | vol3[2]),
(vol3[6] | vol3[1]),
(vol3[6] | vol3[0]) }),
.out(msample3)
);
// channel muxing
// !!! this is 28MHz clock !!!
always @ (posedge clk) begin
ldatasum <= #1 {msample1[13], msample1} + {msample2[13], msample2};
rdatasum <= #1 {msample0[13], msample0} + {msample3[13], msample3};
end
endmodule
|
/*
Copyright (c) 2014-2018 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`timescale 1ns / 1ps
/*
* Testbench for ip_eth_tx_64
*/
module test_ip_eth_tx_64;
// Inputs
reg clk = 0;
reg rst = 0;
reg [7:0] current_test = 0;
reg s_ip_hdr_valid = 0;
reg [47:0] s_eth_dest_mac = 0;
reg [47:0] s_eth_src_mac = 0;
reg [15:0] s_eth_type = 0;
reg [5:0] s_ip_dscp = 0;
reg [1:0] s_ip_ecn = 0;
reg [15:0] s_ip_length = 0;
reg [15:0] s_ip_identification = 0;
reg [2:0] s_ip_flags = 0;
reg [12:0] s_ip_fragment_offset = 0;
reg [7:0] s_ip_ttl = 0;
reg [7:0] s_ip_protocol = 0;
reg [31:0] s_ip_source_ip = 0;
reg [31:0] s_ip_dest_ip = 0;
reg [63:0] s_ip_payload_axis_tdata = 0;
reg [7:0] s_ip_payload_axis_tkeep = 0;
reg s_ip_payload_axis_tvalid = 0;
reg s_ip_payload_axis_tlast = 0;
reg s_ip_payload_axis_tuser = 0;
reg m_eth_hdr_ready = 0;
reg m_eth_payload_axis_tready = 0;
// Outputs
wire s_ip_hdr_ready;
wire s_ip_payload_axis_tready;
wire m_eth_hdr_valid;
wire [47:0] m_eth_dest_mac;
wire [47:0] m_eth_src_mac;
wire [15:0] m_eth_type;
wire [63:0] m_eth_payload_axis_tdata;
wire [7:0] m_eth_payload_axis_tkeep;
wire m_eth_payload_axis_tvalid;
wire m_eth_payload_axis_tlast;
wire m_eth_payload_axis_tuser;
wire busy;
wire error_payload_early_termination;
initial begin
// myhdl integration
$from_myhdl(
clk,
rst,
current_test,
s_ip_hdr_valid,
s_eth_dest_mac,
s_eth_src_mac,
s_eth_type,
s_ip_dscp,
s_ip_ecn,
s_ip_length,
s_ip_identification,
s_ip_flags,
s_ip_fragment_offset,
s_ip_ttl,
s_ip_protocol,
s_ip_source_ip,
s_ip_dest_ip,
s_ip_payload_axis_tdata,
s_ip_payload_axis_tkeep,
s_ip_payload_axis_tvalid,
s_ip_payload_axis_tlast,
s_ip_payload_axis_tuser,
m_eth_hdr_ready,
m_eth_payload_axis_tready
);
$to_myhdl(
s_ip_hdr_ready,
s_ip_payload_axis_tready,
m_eth_hdr_valid,
m_eth_dest_mac,
m_eth_src_mac,
m_eth_type,
m_eth_payload_axis_tdata,
m_eth_payload_axis_tkeep,
m_eth_payload_axis_tvalid,
m_eth_payload_axis_tlast,
m_eth_payload_axis_tuser,
busy,
error_payload_early_termination
);
// dump file
$dumpfile("test_ip_eth_tx_64.lxt");
$dumpvars(0, test_ip_eth_tx_64);
end
ip_eth_tx_64
UUT (
.clk(clk),
.rst(rst),
// IP frame input
.s_ip_hdr_valid(s_ip_hdr_valid),
.s_ip_hdr_ready(s_ip_hdr_ready),
.s_eth_dest_mac(s_eth_dest_mac),
.s_eth_src_mac(s_eth_src_mac),
.s_eth_type(s_eth_type),
.s_ip_dscp(s_ip_dscp),
.s_ip_ecn(s_ip_ecn),
.s_ip_length(s_ip_length),
.s_ip_identification(s_ip_identification),
.s_ip_flags(s_ip_flags),
.s_ip_fragment_offset(s_ip_fragment_offset),
.s_ip_ttl(s_ip_ttl),
.s_ip_protocol(s_ip_protocol),
.s_ip_source_ip(s_ip_source_ip),
.s_ip_dest_ip(s_ip_dest_ip),
.s_ip_payload_axis_tdata(s_ip_payload_axis_tdata),
.s_ip_payload_axis_tkeep(s_ip_payload_axis_tkeep),
.s_ip_payload_axis_tvalid(s_ip_payload_axis_tvalid),
.s_ip_payload_axis_tready(s_ip_payload_axis_tready),
.s_ip_payload_axis_tlast(s_ip_payload_axis_tlast),
.s_ip_payload_axis_tuser(s_ip_payload_axis_tuser),
// Ethernet frame output
.m_eth_hdr_valid(m_eth_hdr_valid),
.m_eth_hdr_ready(m_eth_hdr_ready),
.m_eth_dest_mac(m_eth_dest_mac),
.m_eth_src_mac(m_eth_src_mac),
.m_eth_type(m_eth_type),
.m_eth_payload_axis_tdata(m_eth_payload_axis_tdata),
.m_eth_payload_axis_tkeep(m_eth_payload_axis_tkeep),
.m_eth_payload_axis_tvalid(m_eth_payload_axis_tvalid),
.m_eth_payload_axis_tready(m_eth_payload_axis_tready),
.m_eth_payload_axis_tlast(m_eth_payload_axis_tlast),
.m_eth_payload_axis_tuser(m_eth_payload_axis_tuser),
// Status signals
.busy(busy),
.error_payload_early_termination(error_payload_early_termination)
);
endmodule
|
module ADC_CTRL (
iRST,
iCLK,
iCLK_n,
iGO,
oDIN,
oCS_n,
oSCLK,
iDOUT,
oADC_12_bit_channel_0,
oADC_12_bit_channel_1,
oADC_12_bit_channel_2,
oADC_12_bit_channel_3,
oADC_12_bit_channel_4,
oADC_12_bit_channel_5,
oADC_12_bit_channel_6,
oADC_12_bit_channel_7
);
input iRST;
input iCLK;
input iCLK_n;
input iGO;
output oDIN;
output oCS_n;
output oSCLK;
input iDOUT;
output reg [11:0] oADC_12_bit_channel_0;
output reg [11:0] oADC_12_bit_channel_1;
output reg [11:0] oADC_12_bit_channel_2;
output reg [11:0] oADC_12_bit_channel_3;
output reg [11:0] oADC_12_bit_channel_4;
output reg [11:0] oADC_12_bit_channel_5;
output reg [11:0] oADC_12_bit_channel_6;
output reg [11:0] oADC_12_bit_channel_7;
reg [2:0] channel;
reg data;
reg go_en;
reg sclk;
reg [3:0] cont;
reg [3:0] m_cont;
reg [11:0] adc_data;
reg [31:0] adc_counter;
assign oCS_n = ~go_en;
assign oSCLK = (go_en)? iCLK:1;
assign oDIN = data;
always@( iCLK )//posedge iGO or posedge iRST)
begin
if(iRST)
go_en <= 0;
else
begin
if(iGO)
go_en <= 1;
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
cont <= 0;
else
begin
if(iCLK)
cont <= cont + 1;
end
end
always@(posedge iCLK_n)
begin
if(iCLK_n)
m_cont <= cont;
end
always@(posedge iCLK_n or negedge go_en)
begin
if(!go_en)
data <= 0;
else
begin
if(iCLK_n)
begin
if (cont == 2)
data <= channel[2];
else if (cont == 3)
data <= channel[1];
else if (cont == 4)
data <= channel[0];
else
data <= 0;
end
end
end
always@(posedge iCLK or negedge go_en)
begin
if(!go_en)
begin
adc_data <= 0;
end
else
if(iCLK)
begin
if (m_cont == 4)
adc_data[11] <= iDOUT;
else if (m_cont == 5)
adc_data[10] <= iDOUT;
else if (m_cont == 6)
adc_data[9] <= iDOUT;
else if (m_cont == 7)
adc_data[8] <= iDOUT;
else if (m_cont == 8)
adc_data[7] <= iDOUT;
else if (m_cont == 9)
adc_data[6] <= iDOUT;
else if (m_cont == 10)
adc_data[5] <= iDOUT;
else if (m_cont == 11)
adc_data[4] <= iDOUT;
else if (m_cont == 12)
adc_data[3] <= iDOUT;
else if (m_cont == 13)
adc_data[2] <= iDOUT;
else if (m_cont == 14)
adc_data[1] <= iDOUT;
else if (m_cont == 15)
adc_data[0] <= iDOUT;
else if (m_cont == 1)
begin
if ( adc_counter < 32'd20 )
begin
adc_counter <= adc_counter + 1'b1;
end
else
begin
if (channel == 3'd0)
oADC_12_bit_channel_0 <= adc_data;
else if (channel == 3'd1)
oADC_12_bit_channel_1 <= adc_data;
else if (channel == 3'd2)
oADC_12_bit_channel_2 <= adc_data;
else if (channel == 3'd3)
oADC_12_bit_channel_3 <= adc_data;
else if (channel == 3'd4)
oADC_12_bit_channel_4 <= adc_data;
else if (channel == 3'd5)
oADC_12_bit_channel_5 <= adc_data;
else if (channel == 3'd6)
oADC_12_bit_channel_6 <= adc_data;
else if (channel == 3'd7)
oADC_12_bit_channel_7 <= adc_data;
adc_counter <= 32'd0;
channel <= channel + 1'b1;
end
end
end
end
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2019 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
`define stop $stop
`define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
`define checks(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='%s' exp='%s'\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0);
module t (/*AUTOARG*/);
initial begin
int q[int];
int qe[int]; // Empty
int qv[$]; // Value returns
int qi[$]; // Index returns
int i;
string v;
q = '{10:1, 11:2, 12:2, 13:4, 14:3};
v = $sformatf("%p", q); `checks(v, "'{'ha:'h1, 'hb:'h2, 'hc:'h2, 'hd:'h4, 'he:'h3} ");
// NOT tested: with ... selectors
//q.sort; // Not legal on assoc - see t_assoc_meth_bad
//q.rsort; // Not legal on assoc - see t_assoc_meth_bad
//q.reverse; // Not legal on assoc - see t_assoc_meth_bad
//q.shuffle; // Not legal on assoc - see t_assoc_meth_bad
v = $sformatf("%p", qe); `checks(v, "'{}");
qv = q.unique;
v = $sformatf("%p", qv); `checks(v, "'{'h1, 'h2, 'h4, 'h3} ");
qv = qe.unique;
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.unique_index; qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'ha, 'hb, 'hd, 'he} ");
qi = qe.unique_index;
v = $sformatf("%p", qi); `checks(v, "'{}");
// These require an with clause or are illegal
// TODO add a lint check that with clause is provided
qv = q.find with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2, 'h2} ");
qv = q.find_first with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find_last with (item == 2);
v = $sformatf("%p", qv); `checks(v, "'{'h2} ");
qv = q.find with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_first with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = q.find_last with (item == 20);
v = $sformatf("%p", qv); `checks(v, "'{}");
qi = q.find_index with (item == 2); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{'hb, 'hc} ");
qi = q.find_first_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hb} ");
qi = q.find_last_index with (item == 2);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find_index with (item == 20); qi.sort;
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_first_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_last_index with (item == 20);
v = $sformatf("%p", qi); `checks(v, "'{}");
qi = q.find_index with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'hc} ");
qi = q.find with (item.index == 12);
v = $sformatf("%p", qi); `checks(v, "'{'h2} ");
qv = q.min;
v = $sformatf("%p", qv); `checks(v, "'{'h1} ");
qv = q.max;
v = $sformatf("%p", qv); `checks(v, "'{'h4} ");
qv = qe.min;
v = $sformatf("%p", qv); `checks(v, "'{}");
qv = qe.max;
v = $sformatf("%p", qv); `checks(v, "'{}");
// Reduction methods
i = q.sum;
`checkh(i, 32'hc);
i = q.sum with (item + 1);
`checkh(i, 32'h11);
i = q.product;
`checkh(i, 32'h30);
i = q.product with (item + 1);
`checkh(i, 32'h168);
i = qe.sum;
`checkh(i, 32'h0);
i = qe.product;
`checkh(i, 32'h0);
q = '{10:32'b1100, 11:32'b1010};
i = q.and;
`checkh(i, 32'b1000);
i = q.and with (item + 1);
`checkh(i, 32'b1001);
i = q.or;
`checkh(i, 32'b1110);
i = q.or with (item + 1);
`checkh(i, 32'b1111);
i = q.xor;
`checkh(i, 32'b0110);
i = q.xor with (item + 1);
`checkh(i, 32'b0110);
i = qe.and;
`checkh(i, 32'b0);
i = qe.or;
`checkh(i, 32'b0);
i = qe.xor;
`checkh(i, 32'b0);
i = q.and();
`checkh(i, 32'b1000);
i = q.and() with (item + 1);
`checkh(i, 32'b1001);
i = q.or();
`checkh(i, 32'b1110);
i = q.or() with (item + 1);
`checkh(i, 32'b1111);
i = q.xor();
`checkh(i, 32'b0110);
i = q.xor() with (item + 1);
`checkh(i, 32'b0110);
i = qe.and();
`checkh(i, 32'b0);
i = qe.or();
`checkh(i, 32'b0);
i = qe.xor();
`checkh(i, 32'b0);
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_rst,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_status,
hdmi_tpm_oos,
hdmi_clk_ratio,
// vdma interface
vdma_clk,
vdma_rst,
vdma_ovf,
vdma_unf,
vdma_tpm_oos,
// bus interface
up_rstn,
up_clk,
up_sel,
up_wr,
up_addr,
up_wdata,
up_rdata,
up_ack);
// parameters
parameter PCORE_VERSION = 32'h00040062;
parameter PCORE_ID = 0;
// hdmi interface
input hdmi_clk;
output hdmi_rst;
output hdmi_full_range;
output hdmi_csc_bypass;
output [ 1:0] hdmi_srcsel;
output [23:0] hdmi_const_rgb;
output [15:0] hdmi_hl_active;
output [15:0] hdmi_hl_width;
output [15:0] hdmi_hs_width;
output [15:0] hdmi_he_max;
output [15:0] hdmi_he_min;
output [15:0] hdmi_vf_active;
output [15:0] hdmi_vf_width;
output [15:0] hdmi_vs_width;
output [15:0] hdmi_ve_max;
output [15:0] hdmi_ve_min;
input hdmi_status;
input hdmi_tpm_oos;
input [31:0] hdmi_clk_ratio;
// vdma interface
input vdma_clk;
output vdma_rst;
input vdma_ovf;
input vdma_unf;
input vdma_tpm_oos;
// bus interface
input up_rstn;
input up_clk;
input up_sel;
input up_wr;
input [13:0] up_addr;
input [31:0] up_wdata;
output [31:0] up_rdata;
output up_ack;
// internal registers
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_full_range = 'd0;
reg up_csc_bypass = 'd0;
reg [ 1:0] up_srcsel = 'd1;
reg [23:0] up_const_rgb = 'd0;
reg [15:0] up_hl_active = 'd0;
reg [15:0] up_hl_width = 'd0;
reg [15:0] up_hs_width = 'd0;
reg [15:0] up_he_max = 'd0;
reg [15:0] up_he_min = 'd0;
reg [15:0] up_vf_active = 'd0;
reg [15:0] up_vf_width = 'd0;
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_ve_max = 'd0;
reg [15:0] up_ve_min = 'd0;
reg up_ack = 'd0;
reg [31:0] up_rdata = 'd0;
reg up_xfer_toggle = 'd0;
reg hdmi_up_xfer_toggle_m1 = 'd0;
reg hdmi_up_xfer_toggle_m2 = 'd0;
reg hdmi_up_xfer_toggle_m3 = 'd0;
reg hdmi_full_range = 'd0;
reg hdmi_csc_bypass = 'd0;
reg [ 1:0] hdmi_srcsel = 'd1;
reg [23:0] hdmi_const_rgb = 'd0;
reg [15:0] hdmi_hl_active = 'd0;
reg [15:0] hdmi_hl_width = 'd0;
reg [15:0] hdmi_hs_width = 'd0;
reg [15:0] hdmi_he_max = 'd0;
reg [15:0] hdmi_he_min = 'd0;
reg [15:0] hdmi_vf_active = 'd0;
reg [15:0] hdmi_vf_width = 'd0;
reg [15:0] hdmi_vs_width = 'd0;
reg [15:0] hdmi_ve_max = 'd0;
reg [15:0] hdmi_ve_min = 'd0;
reg up_hdmi_status_m1 = 'd0;
reg up_hdmi_status = 'd0;
reg up_hdmi_tpm_oos_m1 = 'd0;
reg up_hdmi_tpm_oos_m2 = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_count_toggle_m1 = 'd0;
reg up_count_toggle_m2 = 'd0;
reg up_count_toggle_m3 = 'd0;
reg up_count_toggle = 'd0;
reg [15:0] up_count = 'd0;
reg [31:0] up_hdmi_clk_count = 'd0;
reg hdmi_clk_count_toggle_m1 = 'd0;
reg hdmi_clk_count_toggle_m2 = 'd0;
reg hdmi_clk_count_toggle_m3 = 'd0;
reg hdmi_clk_count_toggle = 'd0;
reg [31:0] hdmi_clk_count_hold = 'd0;
reg [32:0] hdmi_clk_count = 'd0;
reg [ 5:0] vdma_xfer_cnt = 'd0;
reg vdma_xfer_toggle = 'd0;
reg vdma_xfer_ovf = 'd0;
reg vdma_xfer_unf = 'd0;
reg vdma_acc_ovf = 'd0;
reg vdma_acc_unf = 'd0;
reg up_vdma_xfer_toggle_m1 = 'd0;
reg up_vdma_xfer_toggle_m2 = 'd0;
reg up_vdma_xfer_toggle_m3 = 'd0;
reg up_vdma_xfer_ovf = 'd0;
reg up_vdma_xfer_unf = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf = 'd0;
reg up_vdma_tpm_oos_m1 = 'd0;
reg up_vdma_tpm_oos_m2 = 'd0;
reg up_vdma_tpm_oos = 'd0;
// internal signals
wire up_sel_s;
wire up_wr_s;
wire up_preset_s;
wire hdmi_up_xfer_toggle_s;
wire up_count_toggle_s;
wire hdmi_clk_count_toggle_s;
wire up_vdma_xfer_toggle_s;
// decode block select
assign up_sel_s = (up_addr[13:12] == 2'd0) ? up_sel : 1'b0;
assign up_wr_s = up_sel_s & up_wr;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_scratch <= 'd0;
up_resetn <= 'd0;
up_full_range <= 'd0;
up_csc_bypass <= 'd0;
up_srcsel <= 'd1;
up_const_rgb <= 'd0;
up_hl_active <= 'd0;
up_hl_width <= 'd0;
up_hs_width <= 'd0;
up_he_max <= 'd0;
up_he_min <= 'd0;
up_vf_active <= 'd0;
up_vf_width <= 'd0;
up_vs_width <= 'd0;
up_ve_max <= 'd0;
up_ve_min <= 'd0;
end else begin
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h011)) begin
up_full_range <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h012)) begin
up_srcsel <= up_wdata[1:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h013)) begin
up_const_rgb <= up_wdata[23:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h100)) begin
up_hl_active <= up_wdata[31:16];
up_hl_width <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h101)) begin
up_hs_width <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h102)) begin
up_he_max <= up_wdata[31:16];
up_he_min <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h110)) begin
up_vf_active <= up_wdata[31:16];
up_vf_width <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h111)) begin
up_vs_width <= up_wdata[15:0];
end
if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h112)) begin
up_ve_max <= up_wdata[31:16];
up_ve_min <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_ack <= 'd0;
up_rdata <= 'd0;
end else begin
up_ack <= up_sel_s;
if (up_sel_s == 1'b1) begin
case (up_addr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= PCORE_ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'd0, up_resetn};
12'h011: up_rdata <= {30'd0, up_full_range, up_csc_bypass};
12'h012: up_rdata <= {30'd0, up_srcsel};
12'h013: up_rdata <= {8'd0, up_const_rgb};
12'h015: up_rdata <= up_hdmi_clk_count;
12'h016: up_rdata <= hdmi_clk_ratio;
12'h017: up_rdata <= {31'd0, up_hdmi_status};
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
12'h100: up_rdata <= {up_hl_active, up_hl_width};
12'h101: up_rdata <= {16'd0, up_hs_width};
12'h102: up_rdata <= {up_he_max, up_he_min};
12'h110: up_rdata <= {up_vf_active, up_vf_width};
12'h111: up_rdata <= {16'd0, up_vs_width};
12'h112: up_rdata <= {up_ve_max, up_ve_min};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// common xfer toggle (where no enable or start is available)
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_xfer_toggle <= 'd0;
end else begin
if (up_count[5:0] == 6'd0) begin
up_xfer_toggle <= ~up_xfer_toggle;
end
end
end
// HDMI CONTROL
FDPE #(.INIT(1'b1)) i_hdmi_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (hdmi_clk),
.Q (hdmi_rst));
// hdmi control transfer
assign hdmi_up_xfer_toggle_s = hdmi_up_xfer_toggle_m3 ^ hdmi_up_xfer_toggle_m2;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_up_xfer_toggle_m1 <= 'd0;
hdmi_up_xfer_toggle_m2 <= 'd0;
hdmi_up_xfer_toggle_m3 <= 'd0;
end else begin
hdmi_up_xfer_toggle_m1 <= up_xfer_toggle;
hdmi_up_xfer_toggle_m2 <= hdmi_up_xfer_toggle_m1;
hdmi_up_xfer_toggle_m3 <= hdmi_up_xfer_toggle_m2;
end
if (hdmi_up_xfer_toggle_s == 1'b1) begin
hdmi_full_range <= up_full_range;
hdmi_csc_bypass <= up_csc_bypass;
hdmi_srcsel <= up_srcsel;
hdmi_const_rgb <= up_const_rgb;
hdmi_hl_active <= up_hl_active;
hdmi_hl_width <= up_hl_width;
hdmi_hs_width <= up_hs_width;
hdmi_he_max <= up_he_max;
hdmi_he_min <= up_he_min;
hdmi_vf_active <= up_vf_active;
hdmi_vf_width <= up_vf_width;
hdmi_vs_width <= up_vs_width;
hdmi_ve_max <= up_ve_max;
hdmi_ve_min <= up_ve_min;
end
end
// hdmi status transfer
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_hdmi_status_m1 <= 'd0;
up_hdmi_status <= 'd0;
up_hdmi_tpm_oos_m1 <= 'd0;
up_hdmi_tpm_oos_m2 <= 'd0;
up_hdmi_tpm_oos <= 1'b0;
end else begin
up_hdmi_status_m1 <= hdmi_status;
up_hdmi_status <= up_hdmi_status_m1;
up_hdmi_tpm_oos_m1 <= hdmi_tpm_oos;
up_hdmi_tpm_oos_m2 <= up_hdmi_tpm_oos_m1;
if (up_hdmi_tpm_oos_m2 == 1'b1) begin
up_hdmi_tpm_oos <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h019)) begin
up_hdmi_tpm_oos <= up_hdmi_tpm_oos & ~up_wdata[1];
end
end
end
// processor base reference
assign up_count_toggle_s = up_count_toggle_m3 ^ up_count_toggle_m2;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_count_toggle_m1 <= 'd0;
up_count_toggle_m2 <= 'd0;
up_count_toggle_m3 <= 'd0;
up_count_toggle <= 'd0;
up_count <= 'd0;
up_hdmi_clk_count <= 'd0;
end else begin
up_count_toggle_m1 <= hdmi_clk_count_toggle;
up_count_toggle_m2 <= up_count_toggle_m1;
up_count_toggle_m3 <= up_count_toggle_m2;
if (up_count == 16'd0) begin
up_count_toggle <= ~up_count_toggle;
end
up_count <= up_count + 1'b1;
if (up_count_toggle_s == 1'b1) begin
up_hdmi_clk_count <= hdmi_clk_count_hold;
end
end
end
// measuring clock
assign hdmi_clk_count_toggle_s = hdmi_clk_count_toggle_m3 ^ hdmi_clk_count_toggle_m2;
always @(posedge hdmi_clk) begin
if (hdmi_rst == 1'b1) begin
hdmi_clk_count_toggle_m1 <= 'd0;
hdmi_clk_count_toggle_m2 <= 'd0;
hdmi_clk_count_toggle_m3 <= 'd0;
end else begin
hdmi_clk_count_toggle_m1 <= up_count_toggle;
hdmi_clk_count_toggle_m2 <= hdmi_clk_count_toggle_m1;
hdmi_clk_count_toggle_m3 <= hdmi_clk_count_toggle_m2;
end
if (hdmi_clk_count_toggle_s == 1'b1) begin
hdmi_clk_count_toggle <= ~hdmi_clk_count_toggle;
hdmi_clk_count_hold <= hdmi_clk_count[31:0];
end
if (hdmi_clk_count_toggle_s == 1'b1) begin
hdmi_clk_count <= 33'd1;
end else if (hdmi_clk_count[32] == 1'b0) begin
hdmi_clk_count <= hdmi_clk_count + 1'b1;
end else begin
hdmi_clk_count <= {33{1'b1}};
end
end
// VDMA CONTROL
FDPE #(.INIT(1'b1)) i_vdma_rst_reg (
.CE (1'b1),
.D (1'b0),
.PRE (up_preset_s),
.C (vdma_clk),
.Q (vdma_rst));
// vdma status transfer
always @(posedge vdma_clk) begin
vdma_xfer_cnt <= vdma_xfer_cnt + 1'b1;
if (vdma_xfer_cnt == 6'd0) begin
vdma_xfer_toggle <= ~vdma_xfer_toggle;
vdma_xfer_ovf <= vdma_acc_ovf;
vdma_xfer_unf <= vdma_acc_unf;
end
if (vdma_xfer_cnt == 6'd0) begin
vdma_acc_ovf <= vdma_ovf;
vdma_acc_unf <= vdma_unf;
end else begin
vdma_acc_ovf <= vdma_acc_ovf | vdma_ovf;
vdma_acc_unf <= vdma_acc_unf | vdma_unf;
end
end
assign up_vdma_xfer_toggle_s = up_vdma_xfer_toggle_m2 ^ up_vdma_xfer_toggle_m3;
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_vdma_xfer_toggle_m1 <= 'd0;
up_vdma_xfer_toggle_m2 <= 'd0;
up_vdma_xfer_toggle_m3 <= 'd0;
up_vdma_xfer_ovf <= 'd0;
up_vdma_xfer_unf <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf <= 'd0;
end else begin
up_vdma_xfer_toggle_m1 <= vdma_xfer_toggle;
up_vdma_xfer_toggle_m2 <= up_vdma_xfer_toggle_m1;
up_vdma_xfer_toggle_m3 <= up_vdma_xfer_toggle_m2;
if (up_vdma_xfer_toggle_s == 1'b1) begin
up_vdma_xfer_ovf <= vdma_xfer_ovf;
up_vdma_xfer_unf <= vdma_xfer_unf;
end
if (up_vdma_xfer_ovf == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h018)) begin
up_vdma_ovf <= up_vdma_ovf & ~up_wdata[1];
end
if (up_vdma_xfer_unf == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h018)) begin
up_vdma_unf <= up_vdma_unf & ~up_wdata[0];
end
end
end
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_vdma_tpm_oos_m1 <= 'd0;
up_vdma_tpm_oos_m2 <= 'd0;
up_vdma_tpm_oos <= 1'b0;
end else begin
up_vdma_tpm_oos_m1 <= vdma_tpm_oos;
up_vdma_tpm_oos_m2 <= up_vdma_tpm_oos_m1;
if (up_vdma_tpm_oos_m2 == 1'b1) begin
up_vdma_tpm_oos <= 1'b1;
end else if ((up_wr_s == 1'b1) && (up_addr[11:0] == 12'h019)) begin
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
end
end
end
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*****************************************************************************
* File : processing_system7_bfm_v2_0_5_gen_clock.v
*
* Date : 2012-11
*
* Description : Module that generates FCLK clocks and internal clock for Zynq BFM.
*
*****************************************************************************/
`timescale 1ns/1ps
module processing_system7_bfm_v2_0_5_gen_clock(
ps_clk,
sw_clk,
fclk_clk3,
fclk_clk2,
fclk_clk1,
fclk_clk0
);
input ps_clk;
output sw_clk;
output fclk_clk3;
output fclk_clk2;
output fclk_clk1;
output fclk_clk0;
parameter freq_clk3 = 50;
parameter freq_clk2 = 50;
parameter freq_clk1 = 50;
parameter freq_clk0 = 50;
reg clk0 = 1'b0;
reg clk1 = 1'b0;
reg clk2 = 1'b0;
reg clk3 = 1'b0;
reg sw_clk = 1'b0;
assign fclk_clk0 = clk0;
assign fclk_clk1 = clk1;
assign fclk_clk2 = clk2;
assign fclk_clk3 = clk3;
real clk3_p = (1000.00/freq_clk3)/2;
real clk2_p = (1000.00/freq_clk2)/2;
real clk1_p = (1000.00/freq_clk1)/2;
real clk0_p = (1000.00/freq_clk0)/2;
always #(clk3_p) clk3 = !clk3;
always #(clk2_p) clk2 = !clk2;
always #(clk1_p) clk1 = !clk1;
always #(clk0_p) clk0 = !clk0;
always #(0.5) sw_clk = !sw_clk;
endmodule
|
// -- (c) Copyright 2009 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
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// -- (including loss of data, profits, goodwill, or any type of
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// -- reasonably foreseeable or Xilinx had been advised of the
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// --
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// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// File name: si_transactor.v
//
// Description:
// This module manages multi-threaded transactions for one SI-slot.
// The module interface consists of a 1-slave to 1-master address channel, plus a
// (M+1)-master (from M MI-slots plus error handler) to 1-slave response channel.
// The module maintains transaction thread control registers that count the
// number of outstanding transations for each thread and the target MI-slot.
// On the address channel, the module decodes addresses to select among MI-slots
// accessible to the SI-slot where it is instantiated.
// It then qualifies whether each received transaction
// should be propagated as a request to the address channel arbiter.
// Transactions are blocked while there is any outstanding transaction to a
// different slave (MI-slot) for the requested ID thread (for deadlock avoidance).
// On the response channel, the module mulitplexes transfers from each of the
// MI-slots whenever a transfer targets the ID of an active thread,
// arbitrating between MI-slots if multiple threads respond concurrently.
//
//--------------------------------------------------------------------------
//
// Structure:
// si_transactor
// addr_decoder
// comparator_static
// mux_enc
// axic_srl_fifo
// arbiter_resp
//
//-----------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_crossbar_v2_1_si_transactor #
(
parameter C_FAMILY = "none",
parameter integer C_SI = 0, // SI-slot number of current instance.
parameter integer C_DIR = 0, // Direction: 0 = Write; 1 = Read.
parameter integer C_NUM_ADDR_RANGES = 1,
parameter integer C_NUM_M = 2,
parameter integer C_NUM_M_LOG = 1,
parameter integer C_ACCEPTANCE = 1, // Acceptance limit of this SI-slot.
parameter integer C_ACCEPTANCE_LOG = 0, // Width of acceptance counter for this SI-slot.
parameter integer C_ID_WIDTH = 1,
parameter integer C_THREAD_ID_WIDTH = 0,
parameter integer C_ADDR_WIDTH = 32,
parameter integer C_AMESG_WIDTH = 1, // Used for AW or AR channel payload, depending on instantiation.
parameter integer C_RMESG_WIDTH = 1, // Used for B or R channel payload, depending on instantiation.
parameter [C_ID_WIDTH-1:0] C_BASE_ID = {C_ID_WIDTH{1'b0}},
parameter [C_ID_WIDTH-1:0] C_HIGH_ID = {C_ID_WIDTH{1'b0}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_BASE_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b1}},
parameter [C_NUM_M*C_NUM_ADDR_RANGES*64-1:0] C_HIGH_ADDR = {C_NUM_M*C_NUM_ADDR_RANGES*64{1'b0}},
parameter integer C_SINGLE_THREAD = 0,
parameter [C_NUM_M-1:0] C_TARGET_QUAL = {C_NUM_M{1'b1}},
parameter [C_NUM_M*32-1:0] C_M_AXI_SECURE = {C_NUM_M{32'h00000000}},
parameter integer C_RANGE_CHECK = 0,
parameter integer C_ADDR_DECODE =0,
parameter [C_NUM_M*32-1:0] C_ERR_MODE = {C_NUM_M{32'h00000000}},
parameter integer C_DEBUG = 1
)
(
// Global Signals
input wire ACLK,
input wire ARESET,
// Slave Address Channel Interface Ports
input wire [C_ID_WIDTH-1:0] S_AID,
input wire [C_ADDR_WIDTH-1:0] S_AADDR,
input wire [8-1:0] S_ALEN,
input wire [3-1:0] S_ASIZE,
input wire [2-1:0] S_ABURST,
input wire [2-1:0] S_ALOCK,
input wire [3-1:0] S_APROT,
// input wire [4-1:0] S_AREGION,
input wire [C_AMESG_WIDTH-1:0] S_AMESG,
input wire S_AVALID,
output wire S_AREADY,
// Master Address Channel Interface Ports
output wire [C_ID_WIDTH-1:0] M_AID,
output wire [C_ADDR_WIDTH-1:0] M_AADDR,
output wire [8-1:0] M_ALEN,
output wire [3-1:0] M_ASIZE,
output wire [2-1:0] M_ALOCK,
output wire [3-1:0] M_APROT,
output wire [4-1:0] M_AREGION,
output wire [C_AMESG_WIDTH-1:0] M_AMESG,
output wire [(C_NUM_M+1)-1:0] M_ATARGET_HOT,
output wire [(C_NUM_M_LOG+1)-1:0] M_ATARGET_ENC,
output wire [7:0] M_AERROR,
output wire M_AVALID_QUAL,
output wire M_AVALID,
input wire M_AREADY,
// Slave Response Channel Interface Ports
output wire [C_ID_WIDTH-1:0] S_RID,
output wire [C_RMESG_WIDTH-1:0] S_RMESG,
output wire S_RLAST,
output wire S_RVALID,
input wire S_RREADY,
// Master Response Channel Interface Ports
input wire [(C_NUM_M+1)*C_ID_WIDTH-1:0] M_RID,
input wire [(C_NUM_M+1)*C_RMESG_WIDTH-1:0] M_RMESG,
input wire [(C_NUM_M+1)-1:0] M_RLAST,
input wire [(C_NUM_M+1)-1:0] M_RVALID,
output wire [(C_NUM_M+1)-1:0] M_RREADY,
input wire [(C_NUM_M+1)-1:0] M_RTARGET, // Does response ID from each MI-slot target this SI slot?
input wire [8-1:0] DEBUG_A_TRANS_SEQ
);
localparam integer P_WRITE = 0;
localparam integer P_READ = 1;
localparam integer P_RMUX_MESG_WIDTH = C_ID_WIDTH + C_RMESG_WIDTH + 1;
localparam [31:0] P_AXILITE_ERRMODE = 32'h00000001;
localparam integer P_NONSECURE_BIT = 1;
localparam integer P_NUM_M_LOG_M1 = C_NUM_M_LOG ? C_NUM_M_LOG : 1;
localparam [C_NUM_M-1:0] P_M_AXILITE = f_m_axilite(0); // Mask of AxiLite MI-slots
localparam [1:0] P_FIXED = 2'b00;
localparam integer P_NUM_M_DE_LOG = f_ceil_log2(C_NUM_M+1);
localparam integer P_THREAD_ID_WIDTH_M1 = (C_THREAD_ID_WIDTH > 0) ? C_THREAD_ID_WIDTH : 1;
localparam integer P_NUM_ID_VAL = 2**C_THREAD_ID_WIDTH;
localparam integer P_NUM_THREADS = (P_NUM_ID_VAL < C_ACCEPTANCE) ? P_NUM_ID_VAL : C_ACCEPTANCE;
localparam [C_NUM_M-1:0] P_M_SECURE_MASK = f_bit32to1_mi(C_M_AXI_SECURE); // Mask of secure MI-slots
// Ceiling of log2(x)
function integer f_ceil_log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
f_ceil_log2 = acc;
end
endfunction
// AxiLite protocol flag vector
function [C_NUM_M-1:0] f_m_axilite
(
input integer null_arg
);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_m_axilite[mi] = (C_ERR_MODE[mi*32+:32] == P_AXILITE_ERRMODE);
end
end
endfunction
// Convert Bit32 vector of range [0,1] to Bit1 vector on MI
function [C_NUM_M-1:0] f_bit32to1_mi
(input [C_NUM_M*32-1:0] vec32);
integer mi;
begin
for (mi=0; mi<C_NUM_M; mi=mi+1) begin
f_bit32to1_mi[mi] = vec32[mi*32];
end
end
endfunction
wire [C_NUM_M-1:0] target_mi_hot;
wire [P_NUM_M_LOG_M1-1:0] target_mi_enc;
wire [(C_NUM_M+1)-1:0] m_atarget_hot_i;
wire [(P_NUM_M_DE_LOG)-1:0] m_atarget_enc_i;
wire match;
wire [3:0] target_region;
wire [3:0] m_aregion_i;
wire m_avalid_i;
wire s_aready_i;
wire any_error;
wire s_rvalid_i;
wire [C_ID_WIDTH-1:0] s_rid_i;
wire s_rlast_i;
wire [P_RMUX_MESG_WIDTH-1:0] si_rmux_mesg;
wire [(C_NUM_M+1)*P_RMUX_MESG_WIDTH-1:0] mi_rmux_mesg;
wire [(C_NUM_M+1)-1:0] m_rvalid_qual;
wire [(C_NUM_M+1)-1:0] m_rready_arb;
wire [(C_NUM_M+1)-1:0] m_rready_i;
wire target_secure;
wire target_axilite;
wire m_avalid_qual_i;
wire [7:0] m_aerror_i;
genvar gen_mi;
genvar gen_thread;
generate
if (C_ADDR_DECODE) begin : gen_addr_decoder
axi_crossbar_v2_1_addr_decoder #
(
.C_FAMILY (C_FAMILY),
.C_NUM_TARGETS (C_NUM_M),
.C_NUM_TARGETS_LOG (P_NUM_M_LOG_M1),
.C_NUM_RANGES (C_NUM_ADDR_RANGES),
.C_ADDR_WIDTH (C_ADDR_WIDTH),
.C_TARGET_ENC (1),
.C_TARGET_HOT (1),
.C_REGION_ENC (1),
.C_BASE_ADDR (C_BASE_ADDR),
.C_HIGH_ADDR (C_HIGH_ADDR),
.C_TARGET_QUAL (C_TARGET_QUAL),
.C_RESOLUTION (2)
)
addr_decoder_inst
(
.ADDR (S_AADDR),
.TARGET_HOT (target_mi_hot),
.TARGET_ENC (target_mi_enc),
.MATCH (match),
.REGION (target_region)
);
end else begin : gen_no_addr_decoder
assign target_mi_hot = 1;
assign target_mi_enc = 0;
assign match = 1'b1;
assign target_region = 4'b0000;
end
endgenerate
assign target_secure = |(target_mi_hot & P_M_SECURE_MASK);
assign target_axilite = |(target_mi_hot & P_M_AXILITE);
assign any_error = C_RANGE_CHECK && (m_aerror_i != 0); // DECERR if error-detection enabled and any error condition.
assign m_aerror_i[0] = ~match; // Invalid target address
assign m_aerror_i[1] = target_secure && S_APROT[P_NONSECURE_BIT]; // TrustZone violation
assign m_aerror_i[2] = target_axilite && ((S_ALEN != 0) ||
(S_ASIZE[1:0] == 2'b11) || (S_ASIZE[2] == 1'b1)); // AxiLite access violation
assign m_aerror_i[7:3] = 5'b00000; // Reserved
assign M_ATARGET_HOT = m_atarget_hot_i;
assign m_atarget_hot_i = (any_error ? {1'b1, {C_NUM_M{1'b0}}} : {1'b0, target_mi_hot});
assign m_atarget_enc_i = (any_error ? C_NUM_M : target_mi_enc);
assign M_AVALID = m_avalid_i;
assign m_avalid_i = S_AVALID;
assign M_AVALID_QUAL = m_avalid_qual_i;
assign S_AREADY = s_aready_i;
assign s_aready_i = M_AREADY;
assign M_AERROR = m_aerror_i;
assign M_ATARGET_ENC = m_atarget_enc_i;
assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : 4'b0000;
// assign m_aregion_i = any_error ? 4'b0000 : (C_ADDR_DECODE != 0) ? target_region : S_AREGION;
assign M_AREGION = m_aregion_i;
assign M_AID = S_AID;
assign M_AADDR = S_AADDR;
assign M_ALEN = S_ALEN;
assign M_ASIZE = S_ASIZE;
assign M_ALOCK = S_ALOCK;
assign M_APROT = S_APROT;
assign M_AMESG = S_AMESG;
assign S_RVALID = s_rvalid_i;
assign M_RREADY = m_rready_i;
assign s_rid_i = si_rmux_mesg[0+:C_ID_WIDTH];
assign S_RMESG = si_rmux_mesg[C_ID_WIDTH+:C_RMESG_WIDTH];
assign s_rlast_i = si_rmux_mesg[C_ID_WIDTH+C_RMESG_WIDTH+:1];
assign S_RID = s_rid_i;
assign S_RLAST = s_rlast_i;
assign m_rvalid_qual = M_RVALID & M_RTARGET;
assign m_rready_i = m_rready_arb & M_RTARGET;
generate
for (gen_mi=0; gen_mi<(C_NUM_M+1); gen_mi=gen_mi+1) begin : gen_rmesg_mi
// Note: Concatenation of mesg signals is from MSB to LSB; assignments that chop mesg signals appear in opposite order.
assign mi_rmux_mesg[gen_mi*P_RMUX_MESG_WIDTH+:P_RMUX_MESG_WIDTH] = {
M_RLAST[gen_mi],
M_RMESG[gen_mi*C_RMESG_WIDTH+:C_RMESG_WIDTH],
M_RID[gen_mi*C_ID_WIDTH+:C_ID_WIDTH]
};
end // gen_rmesg_mi
if (C_ACCEPTANCE == 1) begin : gen_single_issue
wire cmd_push;
wire cmd_pop;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign m_avalid_qual_i = ~accept_cnt | cmd_pop; // Ready for arbitration if no outstanding transaction or transaction being completed
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 1'b0;
active_target_enc <= 0;
active_target_hot <= 0;
end else begin
if (cmd_push) begin
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
accept_cnt <= 1'b1;
end else if (cmd_pop) begin
accept_cnt <= 1'b0;
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_issue
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_issue
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_issue
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else if (C_SINGLE_THREAD || (P_NUM_ID_VAL==1)) begin : gen_single_thread
wire s_avalid_en;
wire cmd_push;
wire cmd_pop;
reg [C_ID_WIDTH-1:0] active_id;
reg [(C_NUM_M+1)-1:0] active_target_hot;
reg [P_NUM_M_DE_LOG-1:0] active_target_enc;
reg [4-1:0] active_region;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
reg [8-1:0] debug_r_beat_cnt_i;
wire [8-1:0] debug_r_trans_seq_i;
wire accept_limit ;
// Implement single-region-per-ID cyclic dependency avoidance method.
assign s_avalid_en = // This transaction is qualified to request arbitration if ...
(accept_cnt == 0) || // Either there are no outstanding transactions, or ...
(((P_NUM_ID_VAL==1) || (S_AID[P_THREAD_ID_WIDTH_M1-1:0] == active_id[P_THREAD_ID_WIDTH_M1-1:0])) && // the current transaction ID matches the previous, and ...
(active_target_enc == m_atarget_enc_i) && // all outstanding transactions are to the same target MI ...
(active_region == m_aregion_i)); // and to the same REGION.
assign cmd_push = M_AREADY;
assign cmd_pop = s_rvalid_i && S_RREADY && s_rlast_i; // Pop command queue if end of read burst
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~cmd_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = s_avalid_en & ~accept_limit;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
active_id <= 0;
active_target_enc <= 0;
active_target_hot <= 0;
active_region <= 0;
end else begin
if (cmd_push) begin
active_id <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target_enc <= m_atarget_enc_i;
active_target_hot <= m_atarget_hot_i;
active_region <= m_aregion_i;
if (~cmd_pop) begin
accept_cnt <= accept_cnt + 1;
end
end else begin
if (cmd_pop & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end
end // Clocked process
assign m_rready_arb = active_target_hot & {(C_NUM_M+1){S_RREADY}};
assign s_rvalid_i = |(active_target_hot & m_rvalid_qual);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_single_thread
(
.S (active_target_enc),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
if (C_DEBUG) begin : gen_debug_r_single_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i && S_RREADY) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i <= 0;
end else begin
debug_r_beat_cnt_i <= debug_r_beat_cnt_i + 1;
end
end
end else begin
debug_r_beat_cnt_i <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_single_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push),
.S_READY (),
.M_MESG (debug_r_trans_seq_i),
.M_VALID (),
.M_READY (cmd_pop)
);
end // gen_debug_r
end else begin : gen_multi_thread
wire [(P_NUM_M_DE_LOG)-1:0] resp_select;
reg [(C_ACCEPTANCE_LOG+1)-1:0] accept_cnt;
wire [P_NUM_THREADS-1:0] s_avalid_en;
wire [P_NUM_THREADS-1:0] thread_valid;
wire [P_NUM_THREADS-1:0] aid_match;
wire [P_NUM_THREADS-1:0] rid_match;
wire [P_NUM_THREADS-1:0] cmd_push;
wire [P_NUM_THREADS-1:0] cmd_pop;
wire [P_NUM_THREADS:0] accum_push;
reg [P_NUM_THREADS*C_ID_WIDTH-1:0] active_id;
reg [P_NUM_THREADS*8-1:0] active_target;
reg [P_NUM_THREADS*8-1:0] active_region;
reg [P_NUM_THREADS*8-1:0] active_cnt;
reg [P_NUM_THREADS*8-1:0] debug_r_beat_cnt_i;
wire [P_NUM_THREADS*8-1:0] debug_r_trans_seq_i;
wire any_aid_match;
wire any_rid_match;
wire accept_limit;
wire any_push;
wire any_pop;
axi_crossbar_v2_1_arbiter_resp # // Multi-thread response arbiter
(
.C_FAMILY (C_FAMILY),
.C_NUM_S (C_NUM_M+1),
.C_NUM_S_LOG (P_NUM_M_DE_LOG),
.C_GRANT_ENC (1),
.C_GRANT_HOT (0)
)
arbiter_resp_inst
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_VALID (m_rvalid_qual),
.S_READY (m_rready_arb),
.M_GRANT_HOT (),
.M_GRANT_ENC (resp_select),
.M_VALID (s_rvalid_i),
.M_READY (S_RREADY)
);
generic_baseblocks_v2_1_mux_enc #
(
.C_FAMILY (C_FAMILY),
.C_RATIO (C_NUM_M+1),
.C_SEL_WIDTH (P_NUM_M_DE_LOG),
.C_DATA_WIDTH (P_RMUX_MESG_WIDTH)
) mux_resp_multi_thread
(
.S (resp_select),
.A (mi_rmux_mesg),
.O (si_rmux_mesg),
.OE (1'b1)
);
assign any_push = M_AREADY;
assign any_pop = s_rvalid_i & S_RREADY & s_rlast_i;
assign accept_limit = (accept_cnt == C_ACCEPTANCE) & ~any_pop; // Allow next push if a transaction is currently being completed
assign m_avalid_qual_i = (&s_avalid_en) & ~accept_limit; // The current request is qualified for arbitration when it is qualified against all outstanding transaction threads.
assign any_aid_match = |aid_match;
assign any_rid_match = |rid_match;
assign accum_push[0] = 1'b0;
always @(posedge ACLK) begin
if (ARESET) begin
accept_cnt <= 0;
end else begin
if (any_push & ~any_pop) begin
accept_cnt <= accept_cnt + 1;
end else if (any_pop & ~any_push & (accept_cnt != 0)) begin
accept_cnt <= accept_cnt - 1;
end
end
end // Clocked process
for (gen_thread=0; gen_thread<P_NUM_THREADS; gen_thread=gen_thread+1) begin : gen_thread_loop
assign thread_valid[gen_thread] = (active_cnt[gen_thread*8 +: C_ACCEPTANCE_LOG+1] != 0);
assign aid_match[gen_thread] = // The currect thread is active for the requested transaction if
thread_valid[gen_thread] && // this thread slot is not vacant, and
((S_AID[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]); // the requested ID matches the active ID for this thread.
assign s_avalid_en[gen_thread] = // The current request is qualified against this thread slot if
(~aid_match[gen_thread]) || // This thread slot is not active for the requested ID, or
((m_atarget_enc_i == active_target[gen_thread*8+:P_NUM_M_DE_LOG]) && // this outstanding transaction was to the same target and
(m_aregion_i == active_region[gen_thread*8+:4])); // to the same region.
// cmd_push points to the position of either the active thread for the requested ID or the lowest vacant thread slot.
assign accum_push[gen_thread+1] = accum_push[gen_thread] | ~thread_valid[gen_thread];
assign cmd_push[gen_thread] = any_push & (aid_match[gen_thread] | ((~any_aid_match) & ~thread_valid[gen_thread] & ~accum_push[gen_thread]));
// cmd_pop points to the position of the active thread that matches the current RID.
assign rid_match[gen_thread] = thread_valid[gen_thread] & ((s_rid_i[P_THREAD_ID_WIDTH_M1-1:0]) == active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1]);
assign cmd_pop[gen_thread] = any_pop & rid_match[gen_thread];
always @(posedge ACLK) begin
if (ARESET) begin
active_id[gen_thread*C_ID_WIDTH+:C_ID_WIDTH] <= 0;
active_target[gen_thread*8+:8] <= 0;
active_region[gen_thread*8+:8] <= 0;
active_cnt[gen_thread*8+:8] <= 0;
end else begin
if (cmd_push[gen_thread]) begin
active_id[gen_thread*C_ID_WIDTH+:P_THREAD_ID_WIDTH_M1] <= S_AID[P_THREAD_ID_WIDTH_M1-1:0];
active_target[gen_thread*8+:P_NUM_M_DE_LOG] <= m_atarget_enc_i;
active_region[gen_thread*8+:4] <= m_aregion_i;
if (~cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] + 1;
end
end else if (cmd_pop[gen_thread]) begin
active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] <= active_cnt[gen_thread*8+:C_ACCEPTANCE_LOG+1] - 1;
end
end
end // Clocked process
if (C_DEBUG) begin : gen_debug_r_multi_thread
// DEBUG READ BEAT COUNTER (only meaningful for R-channel)
always @(posedge ACLK) begin
if (ARESET) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else if (C_DIR == P_READ) begin
if (s_rvalid_i & S_RREADY & rid_match[gen_thread]) begin
if (s_rlast_i) begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= debug_r_beat_cnt_i[gen_thread*8+:8] + 1;
end
end
end else begin
debug_r_beat_cnt_i[gen_thread*8+:8] <= 0;
end
end // Clocked process
// DEBUG R-CHANNEL TRANSACTION SEQUENCE FIFO
axi_data_fifo_v2_1_axic_srl_fifo #
(
.C_FAMILY (C_FAMILY),
.C_FIFO_WIDTH (8),
.C_FIFO_DEPTH_LOG (C_ACCEPTANCE_LOG+1),
.C_USE_FULL (0)
)
debug_r_seq_fifo_multi_thread
(
.ACLK (ACLK),
.ARESET (ARESET),
.S_MESG (DEBUG_A_TRANS_SEQ),
.S_VALID (cmd_push[gen_thread]),
.S_READY (),
.M_MESG (debug_r_trans_seq_i[gen_thread*8+:8]),
.M_VALID (),
.M_READY (cmd_pop[gen_thread])
);
end // gen_debug_r_multi_thread
end // Next gen_thread_loop
end // thread control
endgenerate
endmodule
`default_nettype wire
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__SDFSTP_4_V
`define SKY130_FD_SC_MS__SDFSTP_4_V
/**
* sdfstp: Scan delay flop, inverted set, non-inverted clock,
* single output.
*
* Verilog wrapper for sdfstp with size of 4 units.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__sdfstp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_ms__sdfstp_4 (
Q ,
CLK ,
D ,
SCD ,
SCE ,
SET_B
);
output Q ;
input CLK ;
input D ;
input SCD ;
input SCE ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_ms__sdfstp base (
.Q(Q),
.CLK(CLK),
.D(D),
.SCD(SCD),
.SCE(SCE),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_MS__SDFSTP_4_V
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2009 by Wilson Snyder.
typedef reg [2:0] threeansi_t;
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
typedef reg [2:0] three_t;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
// Take CRC data and apply to testblock inputs
wire [2:0] in = crc[2:0];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
threeansi_t outa; // From testa of TestAnsi.v
three_t outna; // From test of TestNonAnsi.v
// End of automatics
TestNonAnsi test (// Outputs
.out (outna),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
TestAnsi testa (// Outputs
.out (outa),
/*AUTOINST*/
// Inputs
.clk (clk),
.in (in));
// Aggregate outputs into a single result vector
wire [63:0] result = {57'h0, outna, 1'b0, outa};
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h018decfea0a8828a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module TestNonAnsi (/*AUTOARG*/
// Outputs
out,
// Inputs
clk, in
);
typedef reg [2:0] three_t;
input clk;
input three_t in;
output three_t out;
always @(posedge clk) begin
out <= ~in;
end
endmodule
module TestAnsi (
input clk,
input threeansi_t in,
output threeansi_t out
);
always @(posedge clk) begin
out <= ~in;
end
endmodule
// Local Variables:
// verilog-typedef-regexp: "_t$"
// End:
|
// DESCRIPTION: Verilator: Verilog Test module
//
// Copyright 2009 by Wilson Snyder. This program is free software; you can
// redistribute it and/or modify it under the terms of either the GNU
// Lesser General Public License Version 3 or the Perl Artistic License
// Version 2.0.
// SPDX-License-Identifier: LGPL-3.0-only OR Artistic-2.0
`ifdef VCS
`define NO_SHORTREAL
`endif
`ifdef NC
`define NO_SHORTREAL
`endif
`ifdef VERILATOR // Unsupported
`define NO_SHORTREAL
`endif
module t (/*AUTOARG*/);
// Note these are NOT pure.
import "DPI-C" function int dpii_clear ();
import "DPI-C" function int dpii_count (input int ctr);
import "DPI-C" function bit dpii_inc0 (input int ctr);
import "DPI-C" function bit dpii_inc1 (input int ctr);
import "DPI-C" function bit dpii_incx (input int ctr, input bit value);
integer i;
integer j;
bit b;
integer errors;
task check1(integer line, bit got, bit ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
task check(integer line, int got, int ex);
if (got != ex) begin
$display("%%Error: Line %0d: Bad result, got=%0d expect=%0d",line,got,ex);
errors++;
end
endtask
// Test loop
initial begin
// Spec says && || -> and ?: short circuit, no others do.
// Check both constant & non constants.
dpii_clear();
check1(`__LINE__, (1'b0 && dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 && dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) && dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) && dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) && dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) && dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 0);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 & dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 & dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) & dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) & dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) & dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) & dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 || dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 || dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) || dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) || dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) || dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) || dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 0);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 0);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 0);
//
dpii_clear();
check1(`__LINE__, (1'b0 | dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 | dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) | dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) | dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) | dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) | dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 -> dpii_inc0(0)), 1'b1);
check1(`__LINE__, (1'b1 -> dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) -> dpii_inc0(3)), 1'b1);
check1(`__LINE__, (dpii_inc1(4) -> dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) -> dpii_inc1(7)), 1'b1);
check1(`__LINE__, (!(dpii_inc1(8) -> dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 0);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 ? dpii_inc0(0) : dpii_inc0(1)), 1'b0);
check1(`__LINE__, (1'b1 ? dpii_inc0(2) : dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc0(4) ? dpii_inc0(5) : dpii_inc0(6)), 1'b0);
check1(`__LINE__, (dpii_inc1(7) ? dpii_inc0(8) : dpii_inc0(9)), 1'b0);
check (`__LINE__, dpii_count(0), 0);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 0);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 0);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 0);
//
dpii_clear();
check1(`__LINE__, (1'b0 * dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 * dpii_inc0(1)), 1'b0);
check1(`__LINE__, (dpii_inc0(2) * dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) * dpii_inc0(5)), 1'b0);
check1(`__LINE__, (dpii_inc0(6) * dpii_inc1(7)), 1'b0);
check1(`__LINE__, (!(dpii_inc1(8) * dpii_inc1(9))), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
dpii_clear();
check1(`__LINE__, (1'b0 + dpii_inc0(0)), 1'b0);
check1(`__LINE__, (1'b1 + dpii_inc0(1)), 1'b1);
check1(`__LINE__, (dpii_inc0(2) + dpii_inc0(3)), 1'b0);
check1(`__LINE__, (dpii_inc1(4) + dpii_inc0(5)), 1'b1);
check1(`__LINE__, (dpii_inc0(6) + dpii_inc1(7)), 1'b1);
check1(`__LINE__, (dpii_inc1(8) + dpii_inc1(9)), 1'b0);
check (`__LINE__, dpii_count(0), 1);
check (`__LINE__, dpii_count(1), 1);
check (`__LINE__, dpii_count(2), 1);
check (`__LINE__, dpii_count(3), 1);
check (`__LINE__, dpii_count(4), 1);
check (`__LINE__, dpii_count(5), 1);
check (`__LINE__, dpii_count(6), 1);
check (`__LINE__, dpii_count(7), 1);
check (`__LINE__, dpii_count(8), 1);
check (`__LINE__, dpii_count(9), 1);
//
// Something a lot more complicated
dpii_clear();
for (i=0; i<64; i++) begin
b = ( ((dpii_incx(0,i[0])
&& (dpii_incx(1,i[1])
|| dpii_incx(2,i[2])
| dpii_incx(3,i[3]))) // | not ||
|| dpii_incx(4,i[4]))
-> dpii_incx(5,i[5]));
end
check (`__LINE__, dpii_count(0), 64);
check (`__LINE__, dpii_count(1), 32);
check (`__LINE__, dpii_count(2), 16);
check (`__LINE__, dpii_count(3), 16);
check (`__LINE__, dpii_count(4), 36);
check (`__LINE__, dpii_count(5), 46);
if (|errors) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2017.4
// Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module hls_contrast_streeOg_DSP48_3(
input [9 - 1:0] in0,
input [23 - 1:0] in1,
input [31 - 1:0] in2,
output [32 - 1:0] dout);
wire signed [25 - 1:0] a;
wire signed [18 - 1:0] b;
wire signed [48 - 1:0] c;
wire signed [43 - 1:0] m;
wire signed [48 - 1:0] p;
assign a = $unsigned(in1);
assign b = $signed(in0);
assign c = $unsigned(in2);
assign m = a * b;
assign p = m + c;
assign dout = p;
endmodule
`timescale 1 ns / 1 ps
module hls_contrast_streeOg(
din0,
din1,
din2,
dout);
parameter ID = 32'd1;
parameter NUM_STAGE = 32'd1;
parameter din0_WIDTH = 32'd1;
parameter din1_WIDTH = 32'd1;
parameter din2_WIDTH = 32'd1;
parameter dout_WIDTH = 32'd1;
input[din0_WIDTH - 1:0] din0;
input[din1_WIDTH - 1:0] din1;
input[din2_WIDTH - 1:0] din2;
output[dout_WIDTH - 1:0] dout;
hls_contrast_streeOg_DSP48_3 hls_contrast_streeOg_DSP48_3_U(
.in0( din0 ),
.in1( din1 ),
.in2( din2 ),
.dout( dout ));
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2014 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
reg [63:0] sum;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [67:0] left; // From test of Test.v
wire [67:0] right; // From test of Test.v
// End of automatics
wire [6:0] amt = crc[6:0];
wire [67:0] in = {crc[3:0], crc[63:0]};
Test test (/*AUTOINST*/
// Outputs
.left (left[67:0]),
.right (right[67:0]),
// Inputs
.amt (amt[6:0]),
.in (in[67:0]));
wire [63:0] result = (left[63:0] ^ {60'h0, left[67:64]}
^ right[63:0] ^ {60'h0, right[67:64]});
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x result=%x amt=%x left=%x right=%x\n",
$time, cyc, crc, result, amt, left, right);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
if (cyc==0) begin
// Setup
crc <= 64'h5aef0c8d_d70a4497;
sum <= 64'h0;
end
else if (cyc<10) begin
sum <= 64'h0;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
if (crc !== 64'hc77bb9b3784ea091) $stop;
// What checksum will we end up with (above print should match)
`define EXPECTED_SUM 64'h0da01049b480c38a
if (sum !== `EXPECTED_SUM) $stop;
$write("*-* All Finished *-*\n");
$finish;
end
end
endmodule
module Test (/*AUTOARG*/
// Outputs
left, right,
// Inputs
amt, in
);
input [6:0] amt;
input [67:0] in;
// amt must be constant
output wire [67:0] left;
output wire [67:0] right;
assign right = { << 33 {in}};
assign left = { >> 33 {in}};
endmodule
|
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-26 23:25:59
// Last Modified : 2016-11-01 16:15:50
// Revision :
// Author : Jorge Esteban Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
//=========================================================================================
//==================================================================================================
// Filename : RKOA_OPCHANGE.v
// Created On : 2016-10-24 22:49:36
// Last Modified : 2016-10-26 23:25:21
// Revision :
// Author : Jorge Sequeira Rojas
// Company : Instituto Tecnologico de Costa Rica
// Email : [email protected]
//
// Description :
//
//
//==================================================================================================
`timescale 1ns / 1ps
`define STOP_SW1 3
`define STOP_SW2 4
module Simple_KOA_STAGE_1
//#(parameter SW = 24, parameter precision = 0)
#(parameter SW = 24)
(
input wire clk,
input wire rst,
input wire load_b_i,
input wire [SW-1:0] Data_A_i,
input wire [SW-1:0] Data_B_i,
output wire [2*SW-1:0] sgf_result_o
);
///////////////////////////////////////////////////////////
wire [1:0] zero1;
wire [3:0] zero2;
assign zero1 = 2'b00;
assign zero2 = 4'b0000;
///////////////////////////////////////////////////////////
wire [SW/2-1:0] rightside1;
wire [SW/2:0] rightside2;
//Modificacion: Leftside signals are added. They are created as zero fillings as preparation for the final adder.
wire [SW/2-3:0] leftside1;
wire [SW/2-4:0] leftside2;
reg [4*(SW/2)+2:0] Result;
reg [4*(SW/2)-1:0] sgf_r;
assign rightside1 = {(SW/2){1'b0}};
assign rightside2 = {(SW/2+1){1'b0}};
assign leftside1 = {(SW/2-4){1'b0}}; //Se le quitan dos bits con respecto al right side, esto porque al sumar, se agregan bits, esos hacen que sea diferente
assign leftside2 = {(SW/2-5){1'b0}};
localparam half = SW/2;
generate
case (SW%2)
0:begin : EVEN1
reg [SW/2:0] result_A_adder;
reg [SW/2:0] result_B_adder;
wire [SW-1:0] Q_left;
wire [SW-1:0] Q_right;
wire [SW+1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+1:0] S_B; //SW+2
mult #(.SW(SW/2)) left(
// .clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2)) right(
// .clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW((SW/2)+1)) middle (
// .clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : EVEN
result_A_adder <= (Data_A_i[((SW/2)-1):0] + Data_A_i[(SW-1) -: SW/2]);
result_B_adder <= (Data_B_i[((SW/2)-1):0] + Data_B_i[(SW-1) -: SW/2]);
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2):0] <= {leftside1,S_B,rightside1} + {Q_left,Q_right};
end
RegisterAdd #(.W(4*(SW/2))) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[4*(SW/2)-1:0]),
.Q({sgf_result_o})
);
end
1:begin : ODD1
reg [SW/2+1:0] result_A_adder;
reg [SW/2+1:0] result_B_adder;
wire [2*(SW/2)-1:0] Q_left;
wire [2*(SW/2+1)-1:0] Q_right;
wire [2*(SW/2+2)-1:0] Q_middle;
reg [2*(SW/2+2)-1:0] S_A;
reg [SW+4-1:0] S_B;
mult #(.SW(SW/2)) left(
.clk(clk),
.Data_A_i(Data_A_i[SW-1:SW-SW/2]),
.Data_B_i(Data_B_i[SW-1:SW-SW/2]),
.Data_S_o(Q_left)
);
mult #(.SW(SW/2+1)) right(
.clk(clk),
.Data_A_i(Data_A_i[SW-SW/2-1:0]),
.Data_B_i(Data_B_i[SW-SW/2-1:0]),
.Data_S_o(Q_right)
);
mult #(.SW(SW/2+2)) middle (
.clk(clk),
.Data_A_i(result_A_adder),
.Data_B_i(result_B_adder),
.Data_S_o(Q_middle)
);
always @* begin : ODD
result_A_adder <= (Data_A_i[SW-SW/2-1:0] + Data_A_i[SW-1:SW-SW/2]);
result_B_adder <= Data_B_i[SW-SW/2-1:0] + Data_B_i[SW-1:SW-SW/2];
S_B <= (Q_middle - Q_left - Q_right);
Result[4*(SW/2)+2:0]<= {leftside2,S_B,rightside2} + {Q_left,Q_right};
//sgf_result_o <= Result[2*SW-1:0];
end
RegisterAdd #(.W(4*(SW/2)+2)) finalreg ( //Data X input register
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Result[2*SW-1:0]),
.Q({sgf_result_o})
);
end
endcase
endgenerate
endmodule
|
(** * Smallstep: Small-step Operational Semantics *)
Require Export Imp.
(** The evaluators we have seen so far (e.g., the ones for
[aexp]s, [bexp]s, and commands) have been formulated in a
"big-step" style -- they specify how a given expression can be
evaluated to its final value (or a command plus a store to a final
store) "all in one big step."
This style is simple and natural for many purposes -- indeed,
Gilles Kahn, who popularized its use, called it _natural
semantics_. But there are some things it does not do well. In
particular, it does not give us a natural way of talking about
_concurrent_ programming languages, where the "semantics" of a
program -- i.e., the essence of how it behaves -- is not just
which input states get mapped to which output states, but also
includes the intermediate states that it passes through along the
way, since these states can also be observed by concurrently
executing code.
Another shortcoming of the big-step style is more technical, but
critical in some situations. To see the issue, suppose we wanted
to define a variant of Imp where variables could hold _either_
numbers _or_ lists of numbers (see the [HoareList] chapter for
details). In the syntax of this extended language, it will be
possible to write strange expressions like [2 + nil], and our
semantics for arithmetic expressions will then need to say
something about how such expressions behave. One
possibility (explored in the [HoareList] chapter) is to maintain
the convention that every arithmetic expressions evaluates to some
number by choosing some way of viewing a list as a number -- e.g.,
by specifying that a list should be interpreted as [0] when it
occurs in a context expecting a number. But this is really a bit
of a hack.
A much more natural approach is simply to say that the behavior of
an expression like [2+nil] is _undefined_ -- it doesn't evaluate
to any result at all. And we can easily do this: we just have to
formulate [aeval] and [beval] as [Inductive] propositions rather
than Fixpoints, so that we can make them partial functions instead
of total ones.
However, now we encounter a serious deficiency. In this language,
a command might _fail_ to map a given starting state to any ending
state for two quite different reasons: either because the
execution gets into an infinite loop or because, at some point,
the program tries to do an operation that makes no sense, such as
adding a number to a list, and none of the evaluation rules can be
applied.
These two outcomes -- nontermination vs. getting stuck in an
erroneous configuration -- are quite different. In particular, we
want to allow the first (permitting the possibility of infinite
loops is the price we pay for the convenience of programming with
general looping constructs like [while]) but prevent the
second (which is just wrong), for example by adding some form of
_typechecking_ to the language. Indeed, this will be a major
topic for the rest of the course. As a first step, we need a
different way of presenting the semantics that allows us to
distinguish nontermination from erroneous "stuck states."
So, for lots of reasons, we'd like to have a finer-grained way of
defining and reasoning about program behaviors. This is the topic
of the present chapter. We replace the "big-step" [eval] relation
with a "small-step" relation that specifies, for a given program,
how the "atomic steps" of computation are performed. *)
(* ########################################################### *)
(** * A Toy Language *)
(** To save space in the discussion, let's go back to an
incredibly simple language containing just constants and
addition. (We use single letters -- [C] and [P] -- for the
constructor names, for brevity.) At the end of the chapter, we'll
see how to apply the same techniques to the full Imp language. *)
Inductive tm : Type :=
| C : nat -> tm (* Constant *)
| P : tm -> tm -> tm. (* Plus *)
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P" ].
(** Here is a standard evaluator for this language, written in the
same (big-step) style as we've been using up to this point. *)
Fixpoint evalF (t : tm) : nat :=
match t with
| C n => n
| P a1 a2 => evalF a1 + evalF a2
end.
(** Now, here is the same evaluator, written in exactly the same
style, but formulated as an inductively defined relation. Again,
we use the notation [t || n] for "[t] evaluates to [n]." *)
(**
-------- (E_Const)
C n || n
t1 || n1
t2 || n2
---------------------- (E_Plus)
P t1 t2 || C (n1 + n2)
*)
Reserved Notation " t '||' n " (at level 50, left associativity).
Inductive eval : tm -> nat -> Prop :=
| E_Const : forall n,
C n || n
| E_Plus : forall t1 t2 n1 n2,
t1 || n1 ->
t2 || n2 ->
P t1 t2 || (n1 + n2)
where " t '||' n " := (eval t n).
Tactic Notation "eval_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "E_Const" | Case_aux c "E_Plus" ].
Module SimpleArith1.
(** Now, here is a small-step version. *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
t2 ==> t2'
--------------------------- (ST_Plus2)
P (C n1) t2 ==> P (C n1) t2'
*)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall n1 t2 t2',
t2 ==> t2' ->
P (C n1) t2 ==> P (C n1) t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** Things to notice:
- We are defining just a single reduction step, in which
one [P] node is replaced by its value.
- Each step finds the _leftmost_ [P] node that is ready to
go (both of its operands are constants) and rewrites it in
place. The first rule tells how to rewrite this [P] node
itself; the other two rules tell how to find it.
- A term that is just a constant cannot take a step. *)
(** Let's pause and check a couple of examples of reasoning with
the [step] relation... *)
(** If [t1] can take a step to [t1'], then [P t1 t2] steps
to [P t1' t2]: *)
Example test_step_1 :
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>
P
(C (0 + 3))
(P (C 2) (C 4)).
Proof.
apply ST_Plus1. apply ST_PlusConstConst. Qed.
(** **** Exercise: 1 star (test_step_2) *)
(** Right-hand sides of sums can take a step only when the
left-hand side is finished: if [t2] can take a step to [t2'],
then [P (C n) t2] steps to [P (C n)
t2']: *)
Example test_step_2 :
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>
P
(C 0)
(P
(C 2)
(C (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** * Relations *)
(** We will be using several different step relations, so it is
helpful to generalize a bit and state a few definitions and
theorems about relations in general. (The optional chapter
[Rel.v] develops some of these ideas in a bit more detail; it may
be useful if the treatment here is too dense.) *)
(** A (binary) _relation_ on a set [X] is a family of propositions
parameterized by two elements of [X] -- i.e., a proposition about
pairs of elements of [X]. *)
Definition relation (X: Type) := X->X->Prop.
(** Our main examples of such relations in this chapter will be
the single-step and multi-step reduction relations on terms, [==>]
and [==>*], but there are many other examples -- some that come to
mind are the "equals," "less than," "less than or equal to," and
"is the square of" relations on numbers, and the "prefix of"
relation on lists and strings. *)
(** One simple property of the [==>] relation is that, like the
evaluation relation for our language of Imp programs, it is
_deterministic_.
_Theorem_: For each [t], there is at most one [t'] such that [t]
steps to [t'] ([t ==> t'] is provable). Formally, this is the
same as saying that [==>] is deterministic. *)
(** _Proof sketch_: We show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal, by induction on a derivation of
[step x y1]. There are several cases to consider, depending on
the last rule used in this derivation and in the given derivation
of [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) _and_ one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] has both the form [P t1 t2] and
the form [C n]. [] *)
Definition deterministic {X: Type} (R: relation X) :=
forall x y1 y2 : X, R x y1 -> R x y2 -> y1 = y2.
Theorem step_deterministic:
deterministic step.
Proof.
unfold deterministic. intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2.
Case "ST_PlusConstConst". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". reflexivity.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2". inversion H2.
Case "ST_Plus1". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H0 in Hy1. inversion Hy1.
SCase "ST_Plus1".
rewrite <- (IHHy1 t1'0).
reflexivity. assumption.
SCase "ST_Plus2". rewrite <- H in Hy1. inversion Hy1.
Case "ST_Plus2". step_cases (inversion Hy2) SCase.
SCase "ST_PlusConstConst". rewrite <- H1 in Hy1. inversion Hy1.
SCase "ST_Plus1". inversion H2.
SCase "ST_Plus2".
rewrite <- (IHHy1 t2'0).
reflexivity. assumption.
Qed.
(** There is some annoying repetition in this proof.
Each use of [inversion Hy2] results in three subcases,
only one of which is relevant (the one which matches the
current case in the induction on [Hy1]). The other two
subcases need to be dismissed by finding the contradiction
among the hypotheses and doing inversion on it.
There is a tactic called [solve by inversion] defined in [SfLib.v]
that can be of use in such cases. It will solve the goal if it
can be solved by inverting some hypothesis; otherwise, it fails.
(There are variants [solve by inversion 2] and [solve by inversion 3]
that work if two or three consecutive inversions will solve the goal.)
The example below shows how a proof of the previous theorem can be
simplified using this tactic.
*)
Theorem step_deterministic_alt: deterministic step.
Proof.
intros x y1 y2 Hy1 Hy2.
generalize dependent y2.
step_cases (induction Hy1) Case; intros y2 Hy2;
inversion Hy2; subst; try (solve by inversion).
Case "ST_PlusConstConst". reflexivity.
Case "ST_Plus1".
apply IHHy1 in H2. rewrite H2. reflexivity.
Case "ST_Plus2".
apply IHHy1 in H2. rewrite H2. reflexivity.
Qed.
End SimpleArith1.
(* ########################################################### *)
(** ** Values *)
(** Let's take a moment to slightly generalize the way we state the
definition of single-step reduction. *)
(** It is useful to think of the [==>] relation as defining an
_abstract machine_:
- At any moment, the _state_ of the machine is a term.
- A _step_ of the machine is an atomic unit of computation --
here, a single "add" operation.
- The _halting states_ of the machine are ones where there is no
more computation to be done.
*)
(**
We can then execute a term [t] as follows:
- Take [t] as the starting state of the machine.
- Repeatedly use the [==>] relation to find a sequence of
machine states, starting with [t], where each state steps to
the next.
- When no more reduction is possible, "read out" the final state
of the machine as the result of execution. *)
(** Intuitively, it is clear that the final states of the
machine are always terms of the form [C n] for some [n].
We call such terms _values_. *)
Inductive value : tm -> Prop :=
v_const : forall n, value (C n).
(** Having introduced the idea of values, we can use it in the
definition of the [==>] relation to write [ST_Plus2] rule in a
slightly more elegant way: *)
(**
------------------------------- (ST_PlusConstConst)
P (C n1) (C n2) ==> C (n1 + n2)
t1 ==> t1'
-------------------- (ST_Plus1)
P t1 t2 ==> P t1' t2
value v1
t2 ==> t2'
-------------------- (ST_Plus2)
P v1 t2 ==> P v1 t2'
*)
(** Again, the variable names here carry important information:
by convention, [v1] ranges only over values, while [t1] and [t2]
range over arbitrary terms. (Given this convention, the explicit
[value] hypothesis is arguably redundant. We'll keep it for now,
to maintain a close correspondence between the informal and Coq
versions of the rules, but later on we'll drop it in informal
rules, for the sake of brevity.) *)
(** Here are the formal rules: *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2)
==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 -> (* <----- n.b. *)
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2" ].
(** **** Exercise: 3 stars (redo_determinism) *)
(** As a sanity check on this change, let's re-verify determinism
Proof sketch: We must show that if [x] steps to both [y1] and [y2]
then [y1] and [y2] are equal. Consider the final rules used in
the derivations of [step x y1] and [step x y2].
- If both are [ST_PlusConstConst], the result is immediate.
- It cannot happen that one is [ST_PlusConstConst] and the other
is [ST_Plus1] or [ST_Plus2], since this would imply that [x] has
the form [P t1 t2] where both [t1] and [t2] are
constants (by [ST_PlusConstConst]) AND one of [t1] or [t2] has
the form [P ...].
- Similarly, it cannot happen that one is [ST_Plus1] and the other
is [ST_Plus2], since this would imply that [x] has the form
[P t1 t2] where [t1] both has the form [P t1 t2] and
is a value (hence has the form [C n]).
- The cases when both derivations end with [ST_Plus1] or
[ST_Plus2] follow by the induction hypothesis. [] *)
(** Most of this proof is the same as the one above. But to get
maximum benefit from the exercise you should try to write it from
scratch and just use the earlier one if you get stuck. *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Strong Progress and Normal Forms *)
(** The definition of single-step reduction for our toy language is
fairly simple, but for a larger language it would be pretty easy
to forget one of the rules and create a situation where some term
cannot take a step even though it has not been completely reduced
to a value. The following theorem shows that we did not, in fact,
make such a mistake here. *)
(** _Theorem_ (_Strong Progress_): If [t] is a term, then either [t]
is a value, or there exists a term [t'] such that [t ==> t']. *)
(** _Proof_: By induction on [t].
- Suppose [t = C n]. Then [t] is a [value].
- Suppose [t = P t1 t2], where (by the IH) [t1] is either a
value or can step to some [t1'], and where [t2] is either a
value or can step to some [t2']. We must show [P t1 t2] is
either a value or steps to some [t'].
- If [t1] and [t2] are both values, then [t] can take a step, by
[ST_PlusConstConst].
- If [t1] is a value and [t2] can take a step, then so can [t],
by [ST_Plus2].
- If [t1] can take a step, then so can [t], by [ST_Plus1]. [] *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
tm_cases (induction t) Case.
Case "C". left. apply v_const.
Case "P". right. inversion IHt1.
SCase "l". inversion IHt2.
SSCase "l". inversion H. inversion H0.
exists (C (n + n0)).
apply ST_PlusConstConst.
SSCase "r". inversion H0 as [t' H1].
exists (P t1 t').
apply ST_Plus2. apply H. apply H1.
SCase "r". inversion H as [t' H0].
exists (P t' t2).
apply ST_Plus1. apply H0. Qed.
(** This important property is called _strong progress_, because
every term either is a value or can "make progress" by stepping to
some other term. (The qualifier "strong" distinguishes it from a
more refined version that we'll see in later chapters, called
simply "progress.") *)
(** The idea of "making progress" can be extended to tell us something
interesting about [value]s: in this language [value]s are exactly
the terms that _cannot_ make progress in this sense.
To state this observation formally, let's begin by giving a name
to terms that cannot make progress. We'll call them _normal
forms_. *)
Definition normal_form {X:Type} (R:relation X) (t:X) : Prop :=
~ exists t', R t t'.
(** This definition actually specifies what it is to be a normal form
for an _arbitrary_ relation [R] over an arbitrary set [X], not
just for the particular single-step reduction relation over terms
that we are interested in at the moment. We'll re-use the same
terminology for talking about other relations later in the
course. *)
(** We can use this terminology to generalize the observation we made
in the strong progress theorem: in this language, normal forms and
values are actually the same thing. *)
Lemma value_is_nf : forall v,
value v -> normal_form step v.
Proof.
unfold normal_form. intros v H. inversion H.
intros contra. inversion contra. inversion H1.
Qed.
Lemma nf_is_value : forall t,
normal_form step t -> value t.
Proof. (* a corollary of [strong_progress]... *)
unfold normal_form. intros t H.
assert (G : value t \/ exists t', t ==> t').
SCase "Proof of assertion". apply strong_progress.
inversion G.
SCase "l". apply H0.
SCase "r". apply ex_falso_quodlibet. apply H. assumption. Qed.
Corollary nf_same_as_value : forall t,
normal_form step t <-> value t.
Proof.
split. apply nf_is_value. apply value_is_nf. Qed.
(** Why is this interesting?
Because [value] is a syntactic concept -- it is defined by looking
at the form of a term -- while [normal_form] is a semantic one --
it is defined by looking at how the term steps. It is not obvious
that these concepts should coincide!
Indeed, we could easily have written the definitions so that they
would not coincide... *)
(* ##################################################### *)
(** We might, for example, mistakenly define [value] so that it
includes some terms that are not finished reducing. *)
Module Temp1.
(* Open an inner module so we can redefine value and step. *)
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_funny : forall t1 n2, (* <---- *)
value (P t1 (C n2)).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp1.
(* ##################################################### *)
(** Alternatively, we might mistakenly define [step] so that it
permits something designated as a value to reduce further. *)
Module Temp2.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_Funny : forall n, (* <---- *)
C n ==> P (C n) (C 0)
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
where " t '==>' t' " := (step t t').
(** **** Exercise: 2 stars, advanced (value_not_same_as_normal_form) *)
Lemma value_not_same_as_normal_form :
exists v, value v /\ ~ normal_form step v.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp2.
(* ########################################################### *)
(** Finally, we might define [value] and [step] so that there is some
term that is not a value but that cannot take a step in the [step]
relation. Such terms are said to be _stuck_. In this case this is
caused by a mistake in the semantics, but we will also see
situations where, even in a correct language definition, it makes
sense to allow some terms to be stuck. *)
Module Temp3.
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n).
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
where " t '==>' t' " := (step t t').
(** (Note that [ST_Plus2] is missing.) *)
(** **** Exercise: 3 stars, advanced (value_not_same_as_normal_form') *)
Lemma value_not_same_as_normal_form :
exists t, ~ value t /\ normal_form step t.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
End Temp3.
(* ########################################################### *)
(** *** Additional Exercises *)
Module Temp4.
(** Here is another very simple language whose terms, instead of being
just plus and numbers, are just the booleans true and false and a
conditional expression... *)
Inductive tm : Type :=
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Inductive value : tm -> Prop :=
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
(** **** Exercise: 1 star (smallstep_bools) *)
(** Which of the following propositions are provable? (This is just a
thought exercise, but for an extra challenge feel free to prove
your answers in Coq.) *)
Definition bool_step_prop1 :=
tfalse ==> tfalse.
(* FILL IN HERE *)
Definition bool_step_prop2 :=
tif
ttrue
(tif ttrue ttrue ttrue)
(tif tfalse tfalse tfalse)
==>
ttrue.
(* FILL IN HERE *)
Definition bool_step_prop3 :=
tif
(tif ttrue ttrue ttrue)
(tif ttrue ttrue ttrue)
tfalse
==>
tif
ttrue
(tif ttrue ttrue ttrue)
tfalse.
(* FILL IN HERE *)
(** [] *)
(** **** Exercise: 3 stars, optional (progress_bool) *)
(** Just as we proved a progress theorem for plus expressions, we can
do so for boolean expressions, as well. *)
Theorem strong_progress : forall t,
value t \/ (exists t', t ==> t').
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars, optional (step_deterministic) *)
Theorem step_deterministic :
deterministic step.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
Module Temp5.
(** **** Exercise: 2 stars (smallstep_bool_shortcut) *)
(** Suppose we want to add a "short circuit" to the step relation for
boolean expressions, so that it can recognize when the [then] and
[else] branches of a conditional are the same value (either
[ttrue] or [tfalse]) and reduce the whole conditional to this
value in a single step, even if the guard has not yet been reduced
to a value. For example, we would like this proposition to be
provable:
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
*)
(** Write an extra clause for the step relation that achieves this
effect and prove [bool_step_prop4]. *)
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
(* FILL IN HERE *)
where " t '==>' t' " := (step t t').
Definition bool_step_prop4 :=
tif
(tif ttrue ttrue ttrue)
tfalse
tfalse
==>
tfalse.
Example bool_step_prop4_holds :
bool_step_prop4.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional (properties_of_altered_step) *)
(** It can be shown that the determinism and strong progress theorems
for the step relation in the lecture notes also hold for the
definition of step given above. After we add the clause
[ST_ShortCircuit]...
- Is the [step] relation still deterministic? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- Does a strong progress theorem hold? Write yes or no and
briefly (1 sentence) explain your answer.
Optional: prove your answer correct in Coq.
*)
(* FILL IN HERE *)
(**
- In general, is there any way we could cause strong progress to
fail if we took away one or more constructors from the original
step relation? Write yes or no and briefly (1 sentence) explain
your answer.
(* FILL IN HERE *)
*)
(** [] *)
End Temp5.
End Temp4.
(* ########################################################### *)
(** * Multi-Step Reduction *)
(** Until now, we've been working with the _single-step reduction_
relation [==>], which formalizes the individual steps of an
_abstract machine_ for executing programs.
We can also use this machine to reduce programs to completion --
to find out what final result they yield. This can be formalized
as follows:
- First, we define a _multi-step reduction relation_ [==>*], which
relates terms [t] and [t'] if [t] can reach [t'] by any number
of single reduction steps (including zero steps!).
- Then we define a "result" of a term [t] as a normal form that
[t] can reach by multi-step reduction. *)
(* ########################################################### *)
(** Since we'll want to reuse the idea of multi-step reduction many
times in this and future chapters, let's take a little extra
trouble here and define it generically.
Given a relation [R], we define a relation [multi R], called the
_multi-step closure of [R]_ as follows: *)
Inductive multi {X:Type} (R: relation X) : relation X :=
| multi_refl : forall (x : X), multi R x x
| multi_step : forall (x y z : X),
R x y ->
multi R y z ->
multi R x z.
(** The effect of this definition is that [multi R] relates two
elements [x] and [y] if either
- [x = y], or else
- there is some sequence [z1], [z2], ..., [zn]
such that
R x z1
R z1 z2
...
R zn y.
Thus, if [R] describes a single-step of computation, [z1],
... [zn] is the sequence of intermediate steps of computation
between [x] and [y].
*)
Tactic Notation "multi_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "multi_refl" | Case_aux c "multi_step" ].
(** We write [==>*] for the [multi step] relation -- i.e., the
relation that relates two terms [t] and [t'] if we can get from
[t] to [t'] using the [step] relation zero or more times. *)
Notation " t '==>*' t' " := (multi step t t') (at level 40).
(** The relation [multi R] has several crucial properties.
First, it is obviously _reflexive_ (that is, [forall x, multi R x
x]). In the case of the [==>*] (i.e. [multi step]) relation, the
intuition is that a term can execute to itself by taking zero
steps of execution.
Second, it contains [R] -- that is, single-step executions are a
particular case of multi-step executions. (It is this fact that
justifies the word "closure" in the term "multi-step closure of
[R].") *)
Theorem multi_R : forall (X:Type) (R:relation X) (x y : X),
R x y -> (multi R) x y.
Proof.
intros X R x y H.
apply multi_step with y. apply H. apply multi_refl. Qed.
(** Third, [multi R] is _transitive_. *)
Theorem multi_trans :
forall (X:Type) (R: relation X) (x y z : X),
multi R x y ->
multi R y z ->
multi R x z.
Proof.
intros X R x y z G H.
multi_cases (induction G) Case.
Case "multi_refl". assumption.
Case "multi_step".
apply multi_step with y. assumption.
apply IHG. assumption. Qed.
(** That is, if [t1==>*t2] and [t2==>*t3], then [t1==>*t3]. *)
(* ########################################################### *)
(** ** Examples *)
Lemma test_multistep_1:
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
apply multi_step with
(P
(C (0 + 3))
(P (C 2) (C 4))).
apply ST_Plus1. apply ST_PlusConstConst.
apply multi_step with
(P
(C (0 + 3))
(C (2 + 4))).
apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
apply multi_R.
apply ST_PlusConstConst. Qed.
(** Here's an alternate proof that uses [eapply] to avoid explicitly
constructing all the intermediate terms. *)
Lemma test_multistep_1':
P
(P (C 0) (C 3))
(P (C 2) (C 4))
==>*
C ((0 + 3) + (2 + 4)).
Proof.
eapply multi_step. apply ST_Plus1. apply ST_PlusConstConst.
eapply multi_step. apply ST_Plus2. apply v_const.
apply ST_PlusConstConst.
eapply multi_step. apply ST_PlusConstConst.
apply multi_refl. Qed.
(** **** Exercise: 1 star, optional (test_multistep_2) *)
Lemma test_multistep_2:
C 3 ==>* C 3.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 1 star, optional (test_multistep_3) *)
Lemma test_multistep_3:
P (C 0) (C 3)
==>*
P (C 0) (C 3).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 2 stars (test_multistep_4) *)
Lemma test_multistep_4:
P
(C 0)
(P
(C 2)
(P (C 0) (C 3)))
==>*
P
(C 0)
(C (2 + (0 + 3))).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Normal Forms Again *)
(** If [t] reduces to [t'] in zero or more steps and [t'] is a
normal form, we say that "[t'] is a normal form of [t]." *)
Definition step_normal_form := normal_form step.
Definition normal_form_of (t t' : tm) :=
(t ==>* t' /\ step_normal_form t').
(** We have already seen that, for our language, single-step reduction is
deterministic -- i.e., a given term can take a single step in
at most one way. It follows from this that, if [t] can reach
a normal form, then this normal form is unique. In other words, we
can actually pronounce [normal_form t t'] as "[t'] is _the_
normal form of [t]." *)
(** **** Exercise: 3 stars, optional (normal_forms_unique) *)
Theorem normal_forms_unique:
deterministic normal_form_of.
Proof.
unfold deterministic. unfold normal_form_of. intros x y1 y2 P1 P2.
inversion P1 as [P11 P12]; clear P1. inversion P2 as [P21 P22]; clear P2.
generalize dependent y2.
(* We recommend using this initial setup as-is! *)
(* FILL IN HERE *) Admitted.
(** [] *)
(** Indeed, something stronger is true for this language (though not
for all languages): the reduction of _any_ term [t] will
eventually reach a normal form -- i.e., [normal_form_of] is a
_total_ function. Formally, we say the [step] relation is
_normalizing_. *)
Definition normalizing {X:Type} (R:relation X) :=
forall t, exists t',
(multi R) t t' /\ normal_form R t'.
(** To prove that [step] is normalizing, we need a couple of lemmas.
First, we observe that, if [t] reduces to [t'] in many steps, then
the same sequence of reduction steps within [t] is also possible
when [t] appears as the left-hand child of a [P] node, and
similarly when [t] appears as the right-hand child of a [P]
node whose left-hand child is a value. *)
Lemma multistep_congr_1 : forall t1 t1' t2,
t1 ==>* t1' ->
P t1 t2 ==>* P t1' t2.
Proof.
intros t1 t1' t2 H. multi_cases (induction H) Case.
Case "multi_refl". apply multi_refl.
Case "multi_step". apply multi_step with (P y t2).
apply ST_Plus1. apply H.
apply IHmulti. Qed.
(** **** Exercise: 2 stars (multistep_congr_2) *)
Lemma multistep_congr_2 : forall t1 t2 t2',
value t1 ->
t2 ==>* t2' ->
P t1 t2 ==>* P t1 t2'.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** _Theorem_: The [step] function is normalizing -- i.e., for every
[t] there exists some [t'] such that [t] steps to [t'] and [t'] is
a normal form.
_Proof sketch_: By induction on terms. There are two cases to
consider:
- [t = C n] for some [n]. Here [t] doesn't take a step,
and we have [t' = t]. We can derive the left-hand side by
reflexivity and the right-hand side by observing (a) that values
are normal forms (by [nf_same_as_value]) and (b) that [t] is a
value (by [v_const]).
- [t = P t1 t2] for some [t1] and [t2]. By the IH, [t1] and
[t2] have normal forms [t1'] and [t2']. Recall that normal
forms are values (by [nf_same_as_value]); we know that [t1' =
C n1] and [t2' = C n2], for some [n1] and [n2].
We can combine the [==>*] derivations for [t1] and [t2] to prove
that [P t1 t2] reduces in many steps to [C (n1 + n2)].
It is clear that our choice of [t' = C (n1 + n2)] is a
value, which is in turn a normal form. [] *)
Theorem step_normalizing :
normalizing step.
Proof.
unfold normalizing.
tm_cases (induction t) Case.
Case "C".
exists (C n).
split.
SCase "l". apply multi_refl.
SCase "r".
(* We can use [rewrite] with "iff" statements, not
just equalities: *)
rewrite nf_same_as_value. apply v_const.
Case "P".
inversion IHt1 as [t1' H1]; clear IHt1. inversion IHt2 as [t2' H2]; clear IHt2.
inversion H1 as [H11 H12]; clear H1. inversion H2 as [H21 H22]; clear H2.
rewrite nf_same_as_value in H12. rewrite nf_same_as_value in H22.
inversion H12 as [n1]. inversion H22 as [n2].
rewrite <- H in H11.
rewrite <- H0 in H21.
exists (C (n1 + n2)).
split.
SCase "l".
apply multi_trans with (P (C n1) t2).
apply multistep_congr_1. apply H11.
apply multi_trans with
(P (C n1) (C n2)).
apply multistep_congr_2. apply v_const. apply H21.
apply multi_R. apply ST_PlusConstConst.
SCase "r".
rewrite nf_same_as_value. apply v_const. Qed.
(* ########################################################### *)
(** ** Equivalence of Big-Step and Small-Step Reduction *)
(** Having defined the operational semantics of our tiny programming
language in two different styles, it makes sense to ask whether
these definitions actually define the same thing! They do, though
it takes a little work to show it. (The details are left as an
exercise). *)
(** **** Exercise: 3 stars (eval__multistep) *)
Theorem eval__multistep : forall t n,
t || n -> t ==>* C n.
(** The key idea behind the proof comes from the following picture:
P t1 t2 ==> (by ST_Plus1)
P t1' t2 ==> (by ST_Plus1)
P t1'' t2 ==> (by ST_Plus1)
...
P (C n1) t2 ==> (by ST_Plus2)
P (C n1) t2' ==> (by ST_Plus2)
P (C n1) t2'' ==> (by ST_Plus2)
...
P (C n1) (C n2) ==> (by ST_PlusConstConst)
C (n1 + n2)
That is, the multistep reduction of a term of the form [P t1 t2]
proceeds in three phases:
- First, we use [ST_Plus1] some number of times to reduce [t1]
to a normal form, which must (by [nf_same_as_value]) be a
term of the form [C n1] for some [n1].
- Next, we use [ST_Plus2] some number of times to reduce [t2]
to a normal form, which must again be a term of the form [C
n2] for some [n2].
- Finally, we use [ST_PlusConstConst] one time to reduce [P (C
n1) (C n2)] to [C (n1 + n2)]. *)
(** To formalize this intuition, you'll need to use the congruence
lemmas from above (you might want to review them now, so that
you'll be able to recognize when they are useful), plus some basic
properties of [==>*]: that it is reflexive, transitive, and
includes [==>]. *)
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, advanced (eval__multistep_inf) *)
(** Write a detailed informal version of the proof of [eval__multistep].
(* FILL IN HERE *)
[]
*)
(** For the other direction, we need one lemma, which establishes a
relation between single-step reduction and big-step evaluation. *)
(** **** Exercise: 3 stars (step__eval) *)
Lemma step__eval : forall t t' n,
t ==> t' ->
t' || n ->
t || n.
Proof.
intros t t' n Hs. generalize dependent n.
(* FILL IN HERE *) Admitted.
(** [] *)
(** The fact that small-step reduction implies big-step is now
straightforward to prove, once it is stated correctly.
The proof proceeds by induction on the multi-step reduction
sequence that is buried in the hypothesis [normal_form_of t t']. *)
(** Make sure you understand the statement before you start to
work on the proof. *)
(** **** Exercise: 3 stars (multistep__eval) *)
Theorem multistep__eval : forall t t',
normal_form_of t t' -> exists n, t' = C n /\ t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(* ########################################################### *)
(** ** Additional Exercises *)
(** **** Exercise: 3 stars, optional (interp_tm) *)
(** Remember that we also defined big-step evaluation of [tm]s as a
function [evalF]. Prove that it is equivalent to the existing
semantics.
Hint: we just proved that [eval] and [multistep] are
equivalent, so logically it doesn't matter which you choose.
One will be easier than the other, though! *)
Theorem evalF_eval : forall t n,
evalF t = n <-> t || n.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 4 stars (combined_properties) *)
(** We've considered the arithmetic and conditional expressions
separately. This exercise explores how the two interact. *)
Module Combined.
Inductive tm : Type :=
| C : nat -> tm
| P : tm -> tm -> tm
| ttrue : tm
| tfalse : tm
| tif : tm -> tm -> tm -> tm.
Tactic Notation "tm_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "C" | Case_aux c "P"
| Case_aux c "ttrue" | Case_aux c "tfalse" | Case_aux c "tif" ].
Inductive value : tm -> Prop :=
| v_const : forall n, value (C n)
| v_true : value ttrue
| v_false : value tfalse.
Reserved Notation " t '==>' t' " (at level 40).
Inductive step : tm -> tm -> Prop :=
| ST_PlusConstConst : forall n1 n2,
P (C n1) (C n2) ==> C (n1 + n2)
| ST_Plus1 : forall t1 t1' t2,
t1 ==> t1' ->
P t1 t2 ==> P t1' t2
| ST_Plus2 : forall v1 t2 t2',
value v1 ->
t2 ==> t2' ->
P v1 t2 ==> P v1 t2'
| ST_IfTrue : forall t1 t2,
tif ttrue t1 t2 ==> t1
| ST_IfFalse : forall t1 t2,
tif tfalse t1 t2 ==> t2
| ST_If : forall t1 t1' t2 t3,
t1 ==> t1' ->
tif t1 t2 t3 ==> tif t1' t2 t3
where " t '==>' t' " := (step t t').
Tactic Notation "step_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "ST_PlusConstConst"
| Case_aux c "ST_Plus1" | Case_aux c "ST_Plus2"
| Case_aux c "ST_IfTrue" | Case_aux c "ST_IfFalse" | Case_aux c "ST_If" ].
(** Earlier, we separately proved for both plus- and if-expressions...
- that the step relation was deterministic, and
- a strong progress lemma, stating that every term is either a
value or can take a step.
Prove or disprove these two properties for the combined language. *)
(* FILL IN HERE *)
(** [] *)
End Combined.
(* ########################################################### *)
(** * Small-Step Imp *)
(** For a more serious example, here is the small-step version of the
Imp operational semantics. *)
(** The small-step evaluation relations for arithmetic and boolean
expressions are straightforward extensions of the tiny language
we've been working up to now. To make them easier to read, we
introduce the symbolic notations [==>a] and [==>b], respectively,
for the arithmetic and boolean step relations. *)
Inductive aval : aexp -> Prop :=
av_num : forall n, aval (ANum n).
(** We are not actually going to bother to define boolean
values, since they aren't needed in the definition of [==>b]
below (why?), though they might be if our language were a bit
larger (why?). *)
Reserved Notation " t '/' st '==>a' t' " (at level 40, st at level 39).
Inductive astep : state -> aexp -> aexp -> Prop :=
| AS_Id : forall st i,
AId i / st ==>a ANum (st i)
| AS_Plus : forall st n1 n2,
APlus (ANum n1) (ANum n2) / st ==>a ANum (n1 + n2)
| AS_Plus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(APlus a1 a2) / st ==>a (APlus a1' a2)
| AS_Plus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(APlus v1 a2) / st ==>a (APlus v1 a2')
| AS_Minus : forall st n1 n2,
(AMinus (ANum n1) (ANum n2)) / st ==>a (ANum (minus n1 n2))
| AS_Minus1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMinus a1 a2) / st ==>a (AMinus a1' a2)
| AS_Minus2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMinus v1 a2) / st ==>a (AMinus v1 a2')
| AS_Mult : forall st n1 n2,
(AMult (ANum n1) (ANum n2)) / st ==>a (ANum (mult n1 n2))
| AS_Mult1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(AMult (a1) (a2)) / st ==>a (AMult (a1') (a2))
| AS_Mult2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(AMult v1 a2) / st ==>a (AMult v1 a2')
where " t '/' st '==>a' t' " := (astep st t t').
Reserved Notation " t '/' st '==>b' t' " (at level 40, st at level 39).
Inductive bstep : state -> bexp -> bexp -> Prop :=
| BS_Eq : forall st n1 n2,
(BEq (ANum n1) (ANum n2)) / st ==>b
(if (beq_nat n1 n2) then BTrue else BFalse)
| BS_Eq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BEq a1 a2) / st ==>b (BEq a1' a2)
| BS_Eq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BEq v1 a2) / st ==>b (BEq v1 a2')
| BS_LtEq : forall st n1 n2,
(BLe (ANum n1) (ANum n2)) / st ==>b
(if (ble_nat n1 n2) then BTrue else BFalse)
| BS_LtEq1 : forall st a1 a1' a2,
a1 / st ==>a a1' ->
(BLe a1 a2) / st ==>b (BLe a1' a2)
| BS_LtEq2 : forall st v1 a2 a2',
aval v1 ->
a2 / st ==>a a2' ->
(BLe v1 a2) / st ==>b (BLe v1 (a2'))
| BS_NotTrue : forall st,
(BNot BTrue) / st ==>b BFalse
| BS_NotFalse : forall st,
(BNot BFalse) / st ==>b BTrue
| BS_NotStep : forall st b1 b1',
b1 / st ==>b b1' ->
(BNot b1) / st ==>b (BNot b1')
| BS_AndTrueTrue : forall st,
(BAnd BTrue BTrue) / st ==>b BTrue
| BS_AndTrueFalse : forall st,
(BAnd BTrue BFalse) / st ==>b BFalse
| BS_AndFalse : forall st b2,
(BAnd BFalse b2) / st ==>b BFalse
| BS_AndTrueStep : forall st b2 b2',
b2 / st ==>b b2' ->
(BAnd BTrue b2) / st ==>b (BAnd BTrue b2')
| BS_AndStep : forall st b1 b1' b2,
b1 / st ==>b b1' ->
(BAnd b1 b2) / st ==>b (BAnd b1' b2)
where " t '/' st '==>b' t' " := (bstep st t t').
(** The semantics of commands is the interesting part. We need two
small tricks to make it work:
- We use [SKIP] as a "command value" -- i.e., a command that
has reached a normal form.
- An assignment command reduces to [SKIP] (and an updated
state).
- The sequencing command waits until its left-hand
subcommand has reduced to [SKIP], then throws it away so
that reduction can continue with the right-hand
subcommand.
- We reduce a [WHILE] command by transforming it into a
conditional followed by the same [WHILE]. *)
(** (There are other ways of achieving the effect of the latter
trick, but they all share the feature that the original [WHILE]
command needs to be saved somewhere while a single copy of the loop
body is being evaluated.) *)
Reserved Notation " t '/' st '==>' t' '/' st' "
(at level 40, st at level 39, t' at level 39).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
IFB BTrue THEN c1 ELSE c2 FI / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
IFB BFalse THEN c1 ELSE c2 FI / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b / st ==>b b' ->
IFB b THEN c1 ELSE c2 FI / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st
==> (IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
(* ########################################################### *)
(** * Concurrent Imp *)
(** Finally, to show the power of this definitional style, let's
enrich Imp with a new form of command that runs two subcommands in
parallel and terminates when both have terminated. To reflect the
unpredictability of scheduling, the actions of the subcommands may
be interleaved in any order, but they share the same memory and
can communicate by reading and writing the same variables. *)
Module CImp.
Inductive com : Type :=
| CSkip : com
| CAss : id -> aexp -> com
| CSeq : com -> com -> com
| CIf : bexp -> com -> com -> com
| CWhile : bexp -> com -> com
(* New: *)
| CPar : com -> com -> com.
Tactic Notation "com_cases" tactic(first) ident(c) :=
first;
[ Case_aux c "SKIP" | Case_aux c "::=" | Case_aux c ";"
| Case_aux c "IFB" | Case_aux c "WHILE" | Case_aux c "PAR" ].
Notation "'SKIP'" :=
CSkip.
Notation "x '::=' a" :=
(CAss x a) (at level 60).
Notation "c1 ;; c2" :=
(CSeq c1 c2) (at level 80, right associativity).
Notation "'WHILE' b 'DO' c 'END'" :=
(CWhile b c) (at level 80, right associativity).
Notation "'IFB' b 'THEN' c1 'ELSE' c2 'FI'" :=
(CIf b c1 c2) (at level 80, right associativity).
Notation "'PAR' c1 'WITH' c2 'END'" :=
(CPar c1 c2) (at level 80, right associativity).
Inductive cstep : (com * state) -> (com * state) -> Prop :=
(* Old part *)
| CS_AssStep : forall st i a a',
a / st ==>a a' ->
(i ::= a) / st ==> (i ::= a') / st
| CS_Ass : forall st i n,
(i ::= (ANum n)) / st ==> SKIP / (update st i n)
| CS_SeqStep : forall st c1 c1' st' c2,
c1 / st ==> c1' / st' ->
(c1 ;; c2) / st ==> (c1' ;; c2) / st'
| CS_SeqFinish : forall st c2,
(SKIP ;; c2) / st ==> c2 / st
| CS_IfTrue : forall st c1 c2,
(IFB BTrue THEN c1 ELSE c2 FI) / st ==> c1 / st
| CS_IfFalse : forall st c1 c2,
(IFB BFalse THEN c1 ELSE c2 FI) / st ==> c2 / st
| CS_IfStep : forall st b b' c1 c2,
b /st ==>b b' ->
(IFB b THEN c1 ELSE c2 FI) / st ==> (IFB b' THEN c1 ELSE c2 FI) / st
| CS_While : forall st b c1,
(WHILE b DO c1 END) / st ==>
(IFB b THEN (c1;; (WHILE b DO c1 END)) ELSE SKIP FI) / st
(* New part: *)
| CS_Par1 : forall st c1 c1' c2 st',
c1 / st ==> c1' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1' WITH c2 END) / st'
| CS_Par2 : forall st c1 c2 c2' st',
c2 / st ==> c2' / st' ->
(PAR c1 WITH c2 END) / st ==> (PAR c1 WITH c2' END) / st'
| CS_ParDone : forall st,
(PAR SKIP WITH SKIP END) / st ==> SKIP / st
where " t '/' st '==>' t' '/' st' " := (cstep (t,st) (t',st')).
Definition cmultistep := multi cstep.
Notation " t '/' st '==>*' t' '/' st' " :=
(multi cstep (t,st) (t',st'))
(at level 40, st at level 39, t' at level 39).
(** Among the many interesting properties of this language is the fact
that the following program can terminate with the variable [X] set
to any value... *)
Definition par_loop : com :=
PAR
Y ::= ANum 1
WITH
WHILE BEq (AId Y) (ANum 0) DO
X ::= APlus (AId X) (ANum 1)
END
END.
(** In particular, it can terminate with [X] set to [0]: *)
Example par_loop_example_0:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 0.
Proof.
eapply ex_intro. split.
unfold par_loop.
eapply multi_step. apply CS_Par1.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** It can also terminate with [X] set to [2]: *)
Example par_loop_example_2:
exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = 2.
Proof.
eapply ex_intro. split.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfTrue.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_AssStep. apply AS_Plus.
eapply multi_step. apply CS_Par2. apply CS_SeqStep.
apply CS_Ass.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_SeqFinish.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
eapply multi_refl.
reflexivity. Qed.
(** More generally... *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n__Sn : forall n st,
st X = n /\ st Y = 0 ->
par_loop / st ==>* par_loop / (update st X (S n)).
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** **** Exercise: 3 stars, optional *)
Lemma par_body_n : forall n st,
st X = 0 /\ st Y = 0 ->
exists st',
par_loop / st ==>* par_loop / st' /\ st' X = n /\ st' Y = 0.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** ... the above loop can exit with [X] having any value
whatsoever. *)
Theorem par_loop_any_X:
forall n, exists st',
par_loop / empty_state ==>* SKIP / st'
/\ st' X = n.
Proof.
intros n.
destruct (par_body_n n empty_state).
split; unfold update; reflexivity.
rename x into st.
inversion H as [H' [HX HY]]; clear H.
exists (update st Y 1). split.
eapply multi_trans with (par_loop,st). apply H'.
eapply multi_step. apply CS_Par1. apply CS_Ass.
eapply multi_step. apply CS_Par2. apply CS_While.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq1. apply AS_Id. rewrite update_eq.
eapply multi_step. apply CS_Par2. apply CS_IfStep.
apply BS_Eq. simpl.
eapply multi_step. apply CS_Par2. apply CS_IfFalse.
eapply multi_step. apply CS_ParDone.
apply multi_refl.
rewrite update_neq. assumption. intro X; inversion X.
Qed.
End CImp.
(* ########################################################### *)
(** * A Small-Step Stack Machine *)
(** Last example: a small-step semantics for the stack machine example
from Imp.v. *)
Definition stack := list nat.
Definition prog := list sinstr.
Inductive stack_step : state -> prog * stack -> prog * stack -> Prop :=
| SS_Push : forall st stk n p',
stack_step st (SPush n :: p', stk) (p', n :: stk)
| SS_Load : forall st stk i p',
stack_step st (SLoad i :: p', stk) (p', st i :: stk)
| SS_Plus : forall st stk n m p',
stack_step st (SPlus :: p', n::m::stk) (p', (m+n)::stk)
| SS_Minus : forall st stk n m p',
stack_step st (SMinus :: p', n::m::stk) (p', (m-n)::stk)
| SS_Mult : forall st stk n m p',
stack_step st (SMult :: p', n::m::stk) (p', (m*n)::stk).
Theorem stack_step_deterministic : forall st,
deterministic (stack_step st).
Proof.
unfold deterministic. intros st x y1 y2 H1 H2.
induction H1; inversion H2; reflexivity.
Qed.
Definition stack_multistep st := multi (stack_step st).
(** **** Exercise: 3 stars, advanced (compiler_is_correct) *)
(** Remember the definition of [compile] for [aexp] given in the
[Imp] chapter. We want now to prove [compile] correct with respect
to the stack machine.
State what it means for the compiler to be correct according to
the stack machine small step semantics and then prove it. *)
Definition compiler_is_correct_statement : Prop :=
(* FILL IN HERE *) admit.
Theorem compiler_is_correct : compiler_is_correct_statement.
Proof.
(* FILL IN HERE *) Admitted.
(** [] *)
(** $Date: 2014-12-31 15:16:58 -0500 (Wed, 31 Dec 2014) $ *)
|
`include "hglobal.v"
`default_nettype none
module pakout
#(parameter
PSZ=`NS_PACKET_SIZE,
FSZ=`NS_PACKOUT_FSZ,
ASZ=`NS_ADDRESS_SIZE,
DSZ=`NS_DATA_SIZE,
RSZ=`NS_REDUN_SIZE
)(
`NS_DECLARE_GLB_CHNL(gch),
`NS_DECLARE_PAKOUT_CHNL(snd0),
`NS_DECLARE_IN_CHNL(rcv0)
);
parameter RCV_REQ_CKS = `NS_REQ_CKS;
parameter SND_ACK_CKS = `NS_ACK_CKS;
`NS_DEBOUNCER_ACK(gch_clk, gch_reset, snd0)
`NS_DEBOUNCER_REQ(gch_clk, gch_reset, rcv0)
localparam TOT_PKS = ((`NS_FULL_MSG_SZ / PSZ) + 1);
localparam FIFO_IDX_WIDTH = ((($clog2(FSZ)-1) >= 0)?($clog2(FSZ)-1):(0));
localparam PACKETS_IDX_WIDTH = ((($clog2(TOT_PKS)-1) >= 0)?($clog2(TOT_PKS)-1):(0));
reg [0:0] rg_rdy = `NS_OFF;
// out0 regs
`NS_DECLARE_REG_PAKOUT(rgo0)
reg [0:0] rgo0_req = `NS_OFF;
// inp0 regs
reg [0:0] rgi0_ack = `NS_OFF;
// fifos
`NS_DECLARE_FIFO(bf0)
reg [0:0] added_hd = `NS_OFF;
always @(posedge gch_clk)
begin
if(gch_reset) begin
rg_rdy <= `NS_OFF;
end
if(! gch_reset && ! rg_rdy) begin
rg_rdy <= ! rg_rdy;
`NS_PACKOUT_INIT(rgo0)
rgo0_req <= `NS_OFF;
rgi0_ack <= `NS_OFF;
`NS_FIFO_INIT(bf0);
added_hd <= `NS_OFF;
end
if(! gch_reset && rg_rdy) begin
if(rcv0_ckd_req && (! rgi0_ack)) begin
`NS_FIFO_TRY_ADD_HEAD(bf0, rcv0, added_hd);
end
`NS_FIFO_ACK_ADDED_HEAD(bf0, rgi0_ack, added_hd)
if((! rcv0_ckd_req) && rgi0_ack) begin
rgi0_ack <= `NS_OFF;
end
`NS_PACKOUT_TRY_INC(rgo0, bf0, snd0_ckd_ack, rgo0_req)
end
end
assign gch_ready = rg_rdy && snd0_rdy && rcv0_rdy;
//out1
assign snd0_pakio = rgo0_pakio;
assign snd0_req_out = rgo0_req;
//inp0
assign rcv0_ack_out = rgi0_ack;
endmodule
|
// NOTE: This test program is WRONG, in that it ignores the fact
// that continuous assigns drive with their own strength and drop
// any strength that the r-value may have.
module strength();
wire sup1; assign (supply0, supply1) sup1 = 1'b1;
wire str1; assign (strong0, strong1) str1 = 1'b1;
wire pl1; assign (pull0, pull1) pl1 = 1'b1;
wire we1; assign (weak0, weak1) we1 = 1'b1;
wire sup0; assign (supply0, supply1) sup0 = 1'b0;
wire str0; assign (strong0, strong1) str0 = 1'b0;
wire pl0; assign (pull0, pull1) pl0 = 1'b0;
wire we0; assign (weak0, weak1) we0 = 1'b0;
wire sup1_sup0;
wire sup1_str0;
wire sup1_pl0;
wire sup1_we0;
assign sup1_sup0 = sup1;
assign sup1_sup0 = sup0;
assign sup1_str0 = sup1;
assign sup1_str0 = str0;
assign sup1_pl0 = sup1;
assign sup1_pl0 = pl0;
assign sup1_we0 = sup1;
assign sup1_we0 = we0;
initial begin
#1;
$display("sup1_sup0 resulted in: %b", sup1_sup0);
$display("sup1_str0 resulted in: %b", sup1_str0);
$display("sup1_pl0 resulted in: %b", sup1_pl0);
$display("sup1_we0 resulted in: %b", sup1_we0);
end
wire str1_sup0;
wire str1_str0;
wire str1_pl0;
wire str1_we0;
assign str1_sup0 = str1;
assign str1_sup0 = sup0;
assign str1_str0 = str1;
assign str1_str0 = str0;
assign str1_pl0 = str1;
assign str1_pl0 = pl0;
assign str1_we0 = str1;
assign str1_we0 = we0;
initial begin
#2;
$display("str1_sup0 resulted in: %b", str1_sup0);
$display("str1_str0 resulted in: %b", str1_str0);
$display("str1_pl0 resulted in: %b", str1_pl0);
$display("str1_we0 resulted in: %b", str1_we0);
end
wire pl1_sup0;
wire pl1_str0;
wire pl1_pl0;
wire pl1_we0;
assign pl1_sup0 = pl1;
assign pl1_sup0 = sup0;
assign pl1_str0 = pl1;
assign pl1_str0 = str0;
assign pl1_pl0 = pl1;
assign pl1_pl0 = pl0;
assign pl1_we0 = pl1;
assign pl1_we0 = we0;
initial begin
#3;
$display("pl1_sup0 resulted in: %b", pl1_sup0);
$display("pl1_str0 resulted in: %b", pl1_str0);
$display("pl1_pl0 resulted in: %b", pl1_pl0);
$display("pl1_we0 resulted in: %b", pl1_we0);
end
wire we1_sup0;
wire we1_str0;
wire we1_pl0;
wire we1_we0;
assign we1_sup0 = we1;
assign we1_sup0 = sup0;
assign we1_str0 = we1;
assign we1_str0 = str0;
assign we1_pl0 = we1;
assign we1_pl0 = pl0;
assign we1_we0 = we1;
assign we1_we0 = we0;
initial begin
#4;
$display("we1_sup0 resulted in: %b", we1_sup0);
$display("we1_str0 resulted in: %b", we1_str0);
$display("we1_pl0 resulted in: %b", we1_pl0);
$display("we1_we0 resulted in: %b", we1_we0);
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_rsqrt(clock, resetn,
i_datain, i_datain_valid, o_datain_stall,
o_dataout, o_dataout_valid, i_stall);
parameter DATA_WIDTH = 32;
parameter LATENCY = 11;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_datain;
input i_datain_valid;
output o_datain_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
reg [LATENCY-1:0] shift_reg_valid;
wire [DATA_WIDTH-1:0] datain;
wire is_fifo_in_valid;
wire is_stalled;
wire is_fifo_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_datain), .data_out(datain), .valid_in(i_datain_valid),
.valid_out( is_fifo_in_valid ), .stall_in(is_fifo_stalled), .stall_out(o_datain_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
always @(posedge clock or negedge resetn)
begin
if (~resetn)
begin
shift_reg_valid <= {LATENCY{1'b0}};
end
else
begin
if(~is_stalled)
shift_reg_valid <= { is_fifo_in_valid, shift_reg_valid[LATENCY-1:1] };
end
end
assign is_stalled = (shift_reg_valid[0] & i_stall);
assign is_fifo_stalled = (shift_reg_valid[0] & i_stall) | !(is_fifo_in_valid);
acl_fp_rsqrt_s5 rsqrt_unit(
.enable(~is_stalled), .clock(clock), .dataa(datain), .result(o_dataout));
assign o_dataout_valid = shift_reg_valid[0];
endmodule
|
//////////////////////////////////////////////////////////////////////////////
// This module is a wrapper for the soft IP NextGen controller and the MMR
// This file is only used for the ALTMEMPHY flow
//////////////////////////////////////////////////////////////////////////////
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
//
module ddr3_s4_amphy_alt_mem_ddrx_controller_top(
clk,
half_clk,
reset_n,
local_ready,
local_write,
local_read,
local_address,
local_byteenable,
local_writedata,
local_burstcount,
local_beginbursttransfer,
local_readdata,
local_readdatavalid,
afi_rst_n,
afi_cs_n,
afi_cke,
afi_odt,
afi_addr,
afi_ba,
afi_ras_n,
afi_cas_n,
afi_we_n,
afi_dqs_burst,
afi_wdata_valid,
afi_wdata,
afi_dm,
afi_wlat,
afi_rdata_en,
afi_rdata_en_full,
afi_rdata,
afi_rdata_valid,
afi_rlat,
afi_cal_success,
afi_cal_fail,
afi_cal_req,
afi_mem_clk_disable,
afi_cal_byte_lane_sel_n,
afi_ctl_refresh_done,
afi_seq_busy,
afi_ctl_long_idle,
local_init_done,
local_refresh_ack,
local_powerdn_ack,
local_self_rfsh_ack,
local_autopch_req,
local_refresh_req,
local_refresh_chip,
local_powerdn_req,
local_self_rfsh_req,
local_self_rfsh_chip,
local_multicast,
local_priority,
ecc_interrupt,
csr_read_req,
csr_write_req,
csr_burst_count,
csr_beginbursttransfer,
csr_addr,
csr_wdata,
csr_rdata,
csr_be,
csr_rdata_valid,
csr_waitrequest
);
//////////////////////////////////////////////////////////////////////////////
// << START MEGAWIZARD INSERT GENERICS
// Inserted Generics
localparam MEM_TYPE = "DDR3";
localparam LOCAL_SIZE_WIDTH = 3;
localparam LOCAL_ADDR_WIDTH = 24;
localparam LOCAL_DATA_WIDTH = 32;
localparam LOCAL_BE_WIDTH = 4;
localparam LOCAL_IF_TYPE = "AVALON";
localparam MEM_IF_CS_WIDTH = 1;
localparam MEM_IF_CKE_WIDTH = 1;
localparam MEM_IF_ODT_WIDTH = 1;
localparam MEM_IF_ADDR_WIDTH = 13;
localparam MEM_IF_ROW_WIDTH = 13;
localparam MEM_IF_COL_WIDTH = 10;
localparam MEM_IF_BA_WIDTH = 3;
localparam MEM_IF_DQS_WIDTH = 1;
localparam MEM_IF_DQ_WIDTH = 8;
localparam MEM_IF_DM_WIDTH = 1;
localparam MEM_IF_CLK_PAIR_COUNT = 1;
localparam MEM_IF_CS_PER_DIMM = 1;
localparam DWIDTH_RATIO = 4;
localparam CTL_LOOK_AHEAD_DEPTH = 4;
localparam CTL_CMD_QUEUE_DEPTH = 8;
localparam CTL_HRB_ENABLED = 0;
localparam CTL_ECC_ENABLED = 0;
localparam CTL_ECC_RMW_ENABLED = 0;
localparam CTL_ECC_CSR_ENABLED = 0;
localparam CTL_CSR_ENABLED = 0;
localparam CTL_ODT_ENABLED = 0;
localparam CSR_ADDR_WIDTH = 16;
localparam CSR_DATA_WIDTH = 32;
localparam CSR_BE_WIDTH = 4;
localparam CTL_OUTPUT_REGD = 0;
localparam MEM_CAS_WR_LAT = 7;
localparam MEM_ADD_LAT = 0;
localparam MEM_TCL = 9;
localparam MEM_TRRD = 2;
localparam MEM_TFAW = 10;
localparam MEM_TRFC = 34;
localparam MEM_TREFI = 2341;
localparam MEM_TRCD = 5;
localparam MEM_TRP = 5;
localparam MEM_TWR = 5;
localparam MEM_TWTR = 4;
localparam MEM_TRTP = 3;
localparam MEM_TRAS = 11;
localparam MEM_TRC = 15;
localparam ADDR_ORDER = 0;
localparam MEM_AUTO_PD_CYCLES = 0;
localparam MEM_IF_RD_TO_WR_TURNAROUND_OCT = 2;
localparam MEM_IF_WR_TO_RD_TURNAROUND_OCT = 0;
localparam CTL_ECC_MULTIPLES_16_24_40_72 = 1;
localparam CTL_USR_REFRESH = 0;
localparam CTL_REGDIMM_ENABLED = 0;
localparam MULTICAST_WR_EN = 0;
localparam LOW_LATENCY = 0;
localparam CTL_DYNAMIC_BANK_ALLOCATION = 0;
localparam CTL_DYNAMIC_BANK_NUM = 4;
localparam ENABLE_BURST_MERGE = 0;
localparam LOCAL_ID_WIDTH = 8;
localparam LOCAL_CS_WIDTH = 0;
localparam CTL_TBP_NUM = 4;
localparam WRBUFFER_ADDR_WIDTH = 6;
localparam RDBUFFER_ADDR_WIDTH = 6;
localparam MEM_IF_CHIP = 1;
localparam MEM_IF_BANKADDR_WIDTH = 3;
localparam MEM_IF_DWIDTH = 8;
localparam MAX_MEM_IF_CS_WIDTH = 30;
localparam MAX_MEM_IF_CHIP = 4;
localparam MAX_MEM_IF_BANKADDR_WIDTH = 3;
localparam MAX_MEM_IF_ROWADDR_WIDTH = 16;
localparam MAX_MEM_IF_COLADDR_WIDTH = 12;
localparam MAX_MEM_IF_ODT_WIDTH = 1;
localparam MAX_MEM_IF_DQS_WIDTH = 5;
localparam MAX_MEM_IF_DQ_WIDTH = 40;
localparam MAX_MEM_IF_MASK_WIDTH = 5;
localparam MAX_LOCAL_DATA_WIDTH = 80;
localparam CFG_TYPE = 'b010;
localparam CFG_INTERFACE_WIDTH = 8;
localparam CFG_BURST_LENGTH = 'b01000;
localparam CFG_DEVICE_WIDTH = 1;
localparam CFG_REORDER_DATA = 1;
localparam CFG_DATA_REORDERING_TYPE = "INTER_BANK";
localparam CFG_STARVE_LIMIT = 10;
localparam CFG_ADDR_ORDER = 'b00;
localparam CFG_TCCD = 2;
localparam CFG_SELF_RFSH_EXIT_CYCLES = 512;
localparam CFG_PDN_EXIT_CYCLES = 3;
localparam MEM_TMRD_CK = 6;
localparam CFG_GEN_SBE = 0;
localparam CFG_GEN_DBE = 0;
localparam CFG_ENABLE_INTR = 0;
localparam CFG_MASK_SBE_INTR = 0;
localparam CFG_MASK_DBE_INTR = 0;
localparam CFG_MASK_CORRDROP_INTR = 0;
localparam CFG_CLR_INTR = 0;
localparam CFG_WRITE_ODT_CHIP = 'h1;
localparam CFG_READ_ODT_CHIP = 'h0;
localparam CFG_PORT_WIDTH_WRITE_ODT_CHIP = 1;
localparam CFG_PORT_WIDTH_READ_ODT_CHIP = 1;
localparam CFG_ENABLE_NO_DM = 0;
// << END MEGAWIZARD INSERT GENERICS
//////////////////////////////////////////////////////////////////////////////
localparam CFG_LOCAL_SIZE_WIDTH = LOCAL_SIZE_WIDTH;
localparam CFG_LOCAL_ADDR_WIDTH = LOCAL_ADDR_WIDTH;
localparam CFG_LOCAL_DATA_WIDTH = LOCAL_DATA_WIDTH;
localparam CFG_LOCAL_BE_WIDTH = LOCAL_BE_WIDTH;
localparam CFG_LOCAL_ID_WIDTH = LOCAL_ID_WIDTH;
localparam CFG_LOCAL_IF_TYPE = LOCAL_IF_TYPE;
localparam CFG_MEM_IF_ADDR_WIDTH = MEM_IF_ADDR_WIDTH;
localparam CFG_MEM_IF_CLK_PAIR_COUNT = MEM_IF_CLK_PAIR_COUNT;
localparam CFG_DWIDTH_RATIO = DWIDTH_RATIO;
localparam CFG_ODT_ENABLED = CTL_ODT_ENABLED;
localparam CFG_CTL_TBP_NUM = CTL_TBP_NUM;
localparam CFG_WRBUFFER_ADDR_WIDTH = WRBUFFER_ADDR_WIDTH;
localparam CFG_RDBUFFER_ADDR_WIDTH = RDBUFFER_ADDR_WIDTH;
localparam CFG_MEM_IF_CS_WIDTH = MEM_IF_CS_WIDTH;
localparam CFG_MEM_IF_CHIP = MEM_IF_CHIP;
localparam CFG_MEM_IF_BA_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_MEM_IF_ROW_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_MEM_IF_COL_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_MEM_IF_CKE_WIDTH = MEM_IF_CKE_WIDTH;
localparam CFG_MEM_IF_ODT_WIDTH = MEM_IF_ODT_WIDTH;
localparam CFG_MEM_IF_DQS_WIDTH = MEM_IF_DQS_WIDTH;
localparam CFG_MEM_IF_DQ_WIDTH = MEM_IF_DWIDTH;
localparam CFG_MEM_IF_DM_WIDTH = MEM_IF_DM_WIDTH;
localparam CFG_COL_ADDR_WIDTH = MEM_IF_COL_WIDTH;
localparam CFG_ROW_ADDR_WIDTH = MEM_IF_ROW_WIDTH;
localparam CFG_BANK_ADDR_WIDTH = MEM_IF_BANKADDR_WIDTH;
localparam CFG_CS_ADDR_WIDTH = LOCAL_CS_WIDTH;
localparam CFG_CAS_WR_LAT = MEM_CAS_WR_LAT;
localparam CFG_ADD_LAT = MEM_ADD_LAT;
localparam CFG_TCL = MEM_TCL;
localparam CFG_TRRD = MEM_TRRD;
localparam CFG_TFAW = MEM_TFAW;
localparam CFG_TRFC = MEM_TRFC;
localparam CFG_TREFI = MEM_TREFI;
localparam CFG_TRCD = MEM_TRCD;
localparam CFG_TRP = MEM_TRP;
localparam CFG_TWR = MEM_TWR;
localparam CFG_TWTR = MEM_TWTR;
localparam CFG_TRTP = MEM_TRTP;
localparam CFG_TRAS = MEM_TRAS;
localparam CFG_TRC = MEM_TRC;
localparam CFG_AUTO_PD_CYCLES = MEM_AUTO_PD_CYCLES;
localparam CFG_TMRD = MEM_TMRD_CK;
localparam CFG_ENABLE_ECC = CTL_ECC_ENABLED;
localparam CFG_ENABLE_AUTO_CORR = CTL_ECC_RMW_ENABLED;
localparam CFG_ECC_MULTIPLES_16_24_40_72 = CTL_ECC_MULTIPLES_16_24_40_72;
localparam CFG_ENABLE_ECC_CODE_OVERWRITES = 1'b1;
localparam CFG_CAL_REQ = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_RDWR = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_BC = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_RD_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_BC = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 0;
localparam CFG_EXTRA_CTL_CLK_WR_TO_PCH = 0;
localparam CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 0;
localparam CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_VALID = 0;
localparam CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 0;
localparam CFG_EXTRA_CTL_CLK_ARF_PERIOD = 0;
localparam CFG_EXTRA_CTL_CLK_PDN_PERIOD = 0;
localparam CFG_ENABLE_DQS_TRACKING = 0;
localparam CFG_OUTPUT_REGD = CTL_OUTPUT_REGD;
localparam CFG_MASK_CORR_DROPPED_INTR = 0;
localparam CFG_USER_RFSH = CTL_USR_REFRESH;
localparam CFG_REGDIMM_ENABLE = CTL_REGDIMM_ENABLED;
localparam CFG_PORT_WIDTH_TYPE = 3;
localparam CFG_PORT_WIDTH_INTERFACE_WIDTH = 8;
localparam CFG_PORT_WIDTH_BURST_LENGTH = 5;
localparam CFG_PORT_WIDTH_DEVICE_WIDTH = 4;
localparam CFG_PORT_WIDTH_REORDER_DATA = 1;
localparam CFG_PORT_WIDTH_STARVE_LIMIT = 6;
localparam CFG_PORT_WIDTH_OUTPUT_REGD = 1;
localparam CFG_PORT_WIDTH_ADDR_ORDER = 2;
localparam CFG_PORT_WIDTH_COL_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5;
localparam CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CS_ADDR_WIDTH = 3;
localparam CFG_PORT_WIDTH_CAS_WR_LAT = 4;
localparam CFG_PORT_WIDTH_ADD_LAT = 3;
localparam CFG_PORT_WIDTH_TCL = 4;
localparam CFG_PORT_WIDTH_TRRD = 4;
localparam CFG_PORT_WIDTH_TFAW = 6;
localparam CFG_PORT_WIDTH_TRFC = 8;
localparam CFG_PORT_WIDTH_TREFI = 13;
localparam CFG_PORT_WIDTH_TRCD = 4;
localparam CFG_PORT_WIDTH_TRP = 4;
localparam CFG_PORT_WIDTH_TWR = 4;
localparam CFG_PORT_WIDTH_TWTR = 4;
localparam CFG_PORT_WIDTH_TRTP = 4;
localparam CFG_PORT_WIDTH_TRAS = 5;
localparam CFG_PORT_WIDTH_TRC = 6;
localparam CFG_PORT_WIDTH_TCCD = 4;
localparam CFG_PORT_WIDTH_TMRD = 3;
localparam CFG_PORT_WIDTH_SELF_RFSH_EXIT_CYCLES = 10;
localparam CFG_PORT_WIDTH_PDN_EXIT_CYCLES = 4;
localparam CFG_PORT_WIDTH_AUTO_PD_CYCLES = 16;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_RDWR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_RD_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_BC = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_TO_PCH = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_WR_AP_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PCH_ALL_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_VALID = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_ARF_PERIOD = 4;
localparam CFG_PORT_WIDTH_EXTRA_CTL_CLK_PDN_PERIOD = 4;
localparam CFG_PORT_WIDTH_ENABLE_ECC = 1;
localparam CFG_PORT_WIDTH_ENABLE_AUTO_CORR = 1;
localparam CFG_PORT_WIDTH_GEN_SBE = 1;
localparam CFG_PORT_WIDTH_GEN_DBE = 1;
localparam CFG_PORT_WIDTH_ENABLE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_SBE_INTR = 1;
localparam CFG_PORT_WIDTH_MASK_DBE_INTR = 1;
localparam CFG_PORT_WIDTH_CLR_INTR = 1;
localparam CFG_PORT_WIDTH_USER_RFSH = 1;
localparam CFG_PORT_WIDTH_SELF_RFSH = 1;
localparam CFG_PORT_WIDTH_REGDIMM_ENABLE = 1;
localparam CFG_WLAT_BUS_WIDTH = 5;
localparam CFG_RDATA_RETURN_MODE = (CFG_REORDER_DATA == 1) ? "INORDER" : "PASSTHROUGH";
localparam CFG_LPDDR2_ENABLED = (CFG_TYPE == `MMR_TYPE_LPDDR2) ? 1 : 0;
localparam CFG_ADDR_RATE_RATIO = (CFG_LPDDR2_ENABLED == 1) ? 2 : 1;
localparam CFG_AFI_IF_FR_ADDR_WIDTH = (CFG_ADDR_RATE_RATIO * CFG_MEM_IF_ADDR_WIDTH);
localparam STS_PORT_WIDTH_SBE_ERROR = 1;
localparam STS_PORT_WIDTH_DBE_ERROR = 1;
localparam STS_PORT_WIDTH_CORR_DROP_ERROR = 1;
localparam STS_PORT_WIDTH_SBE_COUNT = 8;
localparam STS_PORT_WIDTH_DBE_COUNT = 8;
localparam STS_PORT_WIDTH_CORR_DROP_COUNT = 8;
// We are supposed to use these parameters when the CSR is enabled
// but the MAX_ parameters are not defined
//localparam AFI_CS_WIDTH = (MAX_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CKE_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ODT_WIDTH = (MAX_CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_ADDR_WIDTH = (MAX_CFG_MEM_IF_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_BA_WIDTH = (MAX_CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
//localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * MAX_CFG_MEM_IF_CHIP);
localparam AFI_CS_WIDTH = (CFG_MEM_IF_CHIP * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CKE_WIDTH = (CFG_MEM_IF_CKE_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ODT_WIDTH = (CFG_MEM_IF_ODT_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_ADDR_WIDTH = (CFG_AFI_IF_FR_ADDR_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_BA_WIDTH = (CFG_MEM_IF_BA_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_CAL_BYTE_LANE_SEL_N_WIDTH = (CFG_MEM_IF_DQS_WIDTH * CFG_MEM_IF_CHIP);
localparam AFI_CMD_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_DQS_BURST_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_VALID_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_WDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_DM_WIDTH = (CFG_MEM_IF_DM_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_WLAT_WIDTH = CFG_WLAT_BUS_WIDTH;
localparam AFI_RDATA_EN_WIDTH = (CFG_MEM_IF_DQS_WIDTH * (CFG_DWIDTH_RATIO / 2));
localparam AFI_RDATA_WIDTH = (CFG_MEM_IF_DQ_WIDTH * CFG_DWIDTH_RATIO);
localparam AFI_RDATA_VALID_WIDTH = (CFG_DWIDTH_RATIO / 2);
localparam AFI_RLAT_WIDTH = 5;
localparam AFI_OTF_BITNUM = 12;
localparam AFI_AUTO_PRECHARGE_BITNUM = 10;
localparam AFI_MEM_CLK_DISABLE_WIDTH = CFG_MEM_IF_CLK_PAIR_COUNT;
//////////////////////////////////////////////////////////////////////////////
// BEGIN PORT SECTION
// Clk and reset signals
input clk;
input half_clk;
input reset_n;
// Avalon signals
output local_ready;
input local_write;
input local_read;
input [LOCAL_ADDR_WIDTH - 1 : 0] local_address;
input [LOCAL_BE_WIDTH - 1 : 0] local_byteenable;
input [LOCAL_DATA_WIDTH - 1 : 0] local_writedata;
input [LOCAL_SIZE_WIDTH - 1 : 0] local_burstcount;
input local_beginbursttransfer;
output [LOCAL_DATA_WIDTH - 1 : 0] local_readdata;
output local_readdatavalid;
// AFI signals
output [AFI_CMD_WIDTH - 1 : 0] afi_rst_n;
output [AFI_CS_WIDTH - 1 : 0] afi_cs_n;
output [AFI_CKE_WIDTH - 1 : 0] afi_cke;
output [AFI_ODT_WIDTH - 1 : 0] afi_odt;
output [AFI_ADDR_WIDTH - 1 : 0] afi_addr;
output [AFI_BA_WIDTH - 1 : 0] afi_ba;
output [AFI_CMD_WIDTH - 1 : 0] afi_ras_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_cas_n;
output [AFI_CMD_WIDTH - 1 : 0] afi_we_n;
output [AFI_DQS_BURST_WIDTH - 1 : 0] afi_dqs_burst;
output [AFI_WDATA_VALID_WIDTH - 1 : 0] afi_wdata_valid;
output [AFI_WDATA_WIDTH - 1 : 0] afi_wdata;
output [AFI_DM_WIDTH - 1 : 0] afi_dm;
input [AFI_WLAT_WIDTH - 1 : 0] afi_wlat;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en;
output [AFI_RDATA_EN_WIDTH - 1 : 0] afi_rdata_en_full;
input [AFI_RDATA_WIDTH - 1 : 0] afi_rdata;
input [AFI_RDATA_VALID_WIDTH - 1 : 0] afi_rdata_valid;
input [AFI_RLAT_WIDTH - 1 : 0] afi_rlat;
input afi_cal_success;
input afi_cal_fail;
output afi_cal_req;
output [AFI_MEM_CLK_DISABLE_WIDTH - 1 : 0] afi_mem_clk_disable;
output [AFI_CAL_BYTE_LANE_SEL_N_WIDTH - 1 : 0] afi_cal_byte_lane_sel_n;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_refresh_done;
input [CFG_MEM_IF_CHIP - 1 : 0] afi_seq_busy;
output [CFG_MEM_IF_CHIP - 1 : 0] afi_ctl_long_idle;
// Sideband signals
output local_init_done;
output local_refresh_ack;
output local_powerdn_ack;
output local_self_rfsh_ack;
input local_autopch_req;
input local_refresh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_refresh_chip;
input local_powerdn_req;
input local_self_rfsh_req;
input [CFG_MEM_IF_CHIP - 1 : 0] local_self_rfsh_chip;
input local_multicast;
input local_priority;
// Csr & ecc signals
output ecc_interrupt;
input csr_read_req;
input csr_write_req;
input [1 - 1 : 0] csr_burst_count;
input csr_beginbursttransfer;
input [CSR_ADDR_WIDTH - 1 : 0] csr_addr;
input [CSR_DATA_WIDTH - 1 : 0] csr_wdata;
output [CSR_DATA_WIDTH - 1 : 0] csr_rdata;
input [CSR_BE_WIDTH - 1 : 0] csr_be;
output csr_rdata_valid;
output csr_waitrequest;
// END PORT SECTION
//////////////////////////////////////////////////////////////////////////////
wire itf_cmd_ready;
wire itf_cmd_valid;
wire itf_cmd;
wire [LOCAL_ADDR_WIDTH - 1 : 0] itf_cmd_address;
wire [LOCAL_SIZE_WIDTH - 1 : 0] itf_cmd_burstlen;
wire itf_cmd_id;
wire itf_cmd_priority;
wire itf_cmd_autopercharge;
wire itf_cmd_multicast;
wire itf_wr_data_ready;
wire itf_wr_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_wr_data;
wire [LOCAL_BE_WIDTH - 1 : 0] itf_wr_data_byte_en;
wire itf_wr_data_begin;
wire itf_wr_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_wr_data_id;
wire itf_rd_data_ready;
wire itf_rd_data_valid;
wire [LOCAL_DATA_WIDTH - 1 : 0] itf_rd_data;
wire [2 - 1 : 0] itf_rd_data_error;
wire itf_rd_data_begin;
wire itf_rd_data_last;
wire [CFG_LOCAL_ID_WIDTH - 1 : 0] itf_rd_data_id;
// Converter
alt_mem_ddrx_mm_st_converter # (
.AVL_SIZE_WIDTH ( LOCAL_SIZE_WIDTH ),
.AVL_ADDR_WIDTH ( LOCAL_ADDR_WIDTH ),
.AVL_DATA_WIDTH ( LOCAL_DATA_WIDTH )
) mm_st_converter_inst (
.ctl_clk ( clk ),
.ctl_reset_n ( reset_n ),
.ctl_half_clk ( half_clk ),
.ctl_half_clk_reset_n ( reset_n ),
.avl_ready ( local_ready ),
.avl_read_req ( local_read ),
.avl_write_req ( local_write ),
.avl_size ( local_burstcount ),
.avl_burstbegin ( local_beginbursttransfer ),
.avl_addr ( local_address ),
.avl_rdata_valid ( local_readdatavalid ),
.local_rdata_error ( ),
.avl_rdata ( local_readdata ),
.avl_wdata ( local_writedata ),
.avl_be ( local_byteenable ),
.local_multicast ( local_multicast ),
.local_autopch_req ( local_autopch_req ),
.local_priority ( local_priority ),
.itf_cmd_ready ( itf_cmd_ready ),
.itf_cmd_valid ( itf_cmd_valid ),
.itf_cmd ( itf_cmd ),
.itf_cmd_address ( itf_cmd_address ),
.itf_cmd_burstlen ( itf_cmd_burstlen ),
.itf_cmd_id ( itf_cmd_id ),
.itf_cmd_priority ( itf_cmd_priority ),
.itf_cmd_autopercharge ( itf_cmd_autopercharge ),
.itf_cmd_multicast ( itf_cmd_multicast ),
.itf_wr_data_ready ( itf_wr_data_ready ),
.itf_wr_data_valid ( itf_wr_data_valid ),
.itf_wr_data ( itf_wr_data ),
.itf_wr_data_byte_en ( itf_wr_data_byte_en ),
.itf_wr_data_begin ( itf_wr_data_begin ),
.itf_wr_data_last ( itf_wr_data_last ),
.itf_wr_data_id ( itf_wr_data_id ),
.itf_rd_data_ready ( itf_rd_data_ready ),
.itf_rd_data_valid ( itf_rd_data_valid ),
.itf_rd_data ( itf_rd_data ),
.itf_rd_data_error ( itf_rd_data_error ),
.itf_rd_data_begin ( itf_rd_data_begin ),
.itf_rd_data_last ( itf_rd_data_last ),
.itf_rd_data_id ( itf_rd_data_id )
);
// Next Gen Controller
//////////////////////////////////////////////////////////////////////////////
alt_mem_ddrx_controller_st_top #(
.LOCAL_SIZE_WIDTH(LOCAL_SIZE_WIDTH),
.LOCAL_ADDR_WIDTH(LOCAL_ADDR_WIDTH),
.LOCAL_DATA_WIDTH(LOCAL_DATA_WIDTH),
.LOCAL_BE_WIDTH(LOCAL_BE_WIDTH),
.LOCAL_ID_WIDTH(LOCAL_ID_WIDTH),
.LOCAL_CS_WIDTH(LOCAL_CS_WIDTH),
.MEM_IF_ADDR_WIDTH(MEM_IF_ADDR_WIDTH),
.MEM_IF_CLK_PAIR_COUNT(MEM_IF_CLK_PAIR_COUNT),
.LOCAL_IF_TYPE(LOCAL_IF_TYPE),
.DWIDTH_RATIO(DWIDTH_RATIO),
.CTL_ODT_ENABLED(CTL_ODT_ENABLED),
.CTL_OUTPUT_REGD(CTL_OUTPUT_REGD),
.CTL_TBP_NUM(CTL_TBP_NUM),
.WRBUFFER_ADDR_WIDTH(WRBUFFER_ADDR_WIDTH),
.RDBUFFER_ADDR_WIDTH(RDBUFFER_ADDR_WIDTH),
.MEM_IF_CS_WIDTH(MEM_IF_CS_WIDTH),
.MEM_IF_CHIP(MEM_IF_CHIP),
.MEM_IF_BANKADDR_WIDTH(MEM_IF_BANKADDR_WIDTH),
.MEM_IF_ROW_WIDTH(MEM_IF_ROW_WIDTH),
.MEM_IF_COL_WIDTH(MEM_IF_COL_WIDTH),
.MEM_IF_ODT_WIDTH(MEM_IF_ODT_WIDTH),
.MEM_IF_DQS_WIDTH(MEM_IF_DQS_WIDTH),
.MEM_IF_DWIDTH(MEM_IF_DWIDTH),
.MEM_IF_DM_WIDTH(MEM_IF_DM_WIDTH),
.MAX_MEM_IF_CS_WIDTH(MAX_MEM_IF_CS_WIDTH),
.MAX_MEM_IF_CHIP(MAX_MEM_IF_CHIP),
.MAX_MEM_IF_BANKADDR_WIDTH(MAX_MEM_IF_BANKADDR_WIDTH),
.MAX_MEM_IF_ROWADDR_WIDTH(MAX_MEM_IF_ROWADDR_WIDTH),
.MAX_MEM_IF_COLADDR_WIDTH(MAX_MEM_IF_COLADDR_WIDTH),
.MAX_MEM_IF_ODT_WIDTH(MAX_MEM_IF_ODT_WIDTH),
.MAX_MEM_IF_DQS_WIDTH(MAX_MEM_IF_DQS_WIDTH),
.MAX_MEM_IF_DQ_WIDTH(MAX_MEM_IF_DQ_WIDTH),
.MAX_MEM_IF_MASK_WIDTH(MAX_MEM_IF_MASK_WIDTH),
.MAX_LOCAL_DATA_WIDTH(MAX_LOCAL_DATA_WIDTH),
.CFG_TYPE(CFG_TYPE),
.CFG_INTERFACE_WIDTH(CFG_INTERFACE_WIDTH),
.CFG_BURST_LENGTH(CFG_BURST_LENGTH),
.CFG_DEVICE_WIDTH(CFG_DEVICE_WIDTH),
.CFG_REORDER_DATA(CFG_REORDER_DATA),
.CFG_DATA_REORDERING_TYPE(CFG_DATA_REORDERING_TYPE),
.CFG_STARVE_LIMIT(CFG_STARVE_LIMIT),
.CFG_ADDR_ORDER(CFG_ADDR_ORDER),
.MEM_CAS_WR_LAT(MEM_CAS_WR_LAT),
.MEM_ADD_LAT(MEM_ADD_LAT),
.MEM_TCL(MEM_TCL),
.MEM_TRRD(MEM_TRRD),
.MEM_TFAW(MEM_TFAW),
.MEM_TRFC(MEM_TRFC),
.MEM_TREFI(MEM_TREFI),
.MEM_TRCD(MEM_TRCD),
.MEM_TRP(MEM_TRP),
.MEM_TWR(MEM_TWR),
.MEM_TWTR(MEM_TWTR),
.MEM_TRTP(MEM_TRTP),
.MEM_TRAS(MEM_TRAS),
.MEM_TRC(MEM_TRC),
.CFG_TCCD(CFG_TCCD),
.MEM_AUTO_PD_CYCLES(MEM_AUTO_PD_CYCLES),
.CFG_SELF_RFSH_EXIT_CYCLES(CFG_SELF_RFSH_EXIT_CYCLES),
.CFG_PDN_EXIT_CYCLES(CFG_PDN_EXIT_CYCLES),
.MEM_TMRD_CK(MEM_TMRD_CK),
.CTL_ECC_ENABLED(CTL_ECC_ENABLED),
.CTL_ECC_RMW_ENABLED(CTL_ECC_RMW_ENABLED),
.CTL_ECC_MULTIPLES_16_24_40_72(CTL_ECC_MULTIPLES_16_24_40_72),
.CFG_GEN_SBE(CFG_GEN_SBE),
.CFG_GEN_DBE(CFG_GEN_DBE),
.CFG_ENABLE_INTR(CFG_ENABLE_INTR),
.CFG_MASK_SBE_INTR(CFG_MASK_SBE_INTR),
.CFG_MASK_DBE_INTR(CFG_MASK_DBE_INTR),
.CFG_MASK_CORRDROP_INTR(CFG_MASK_CORRDROP_INTR),
.CFG_CLR_INTR(CFG_CLR_INTR),
.CTL_USR_REFRESH(CTL_USR_REFRESH),
.CTL_REGDIMM_ENABLED(CTL_REGDIMM_ENABLED),
.CFG_WRITE_ODT_CHIP(CFG_WRITE_ODT_CHIP),
.CFG_READ_ODT_CHIP(CFG_READ_ODT_CHIP),
.CFG_PORT_WIDTH_WRITE_ODT_CHIP(CFG_PORT_WIDTH_WRITE_ODT_CHIP),
.CFG_PORT_WIDTH_READ_ODT_CHIP(CFG_PORT_WIDTH_READ_ODT_CHIP),
.MEM_IF_CKE_WIDTH(MEM_IF_CKE_WIDTH),
.CTL_CSR_ENABLED(CTL_CSR_ENABLED),
.CFG_ENABLE_NO_DM(CFG_ENABLE_NO_DM),
.CSR_ADDR_WIDTH(CSR_ADDR_WIDTH),
.CSR_DATA_WIDTH(CSR_DATA_WIDTH),
.CSR_BE_WIDTH(CSR_BE_WIDTH),
.CFG_WLAT_BUS_WIDTH(AFI_WLAT_WIDTH),
.CFG_RLAT_BUS_WIDTH(AFI_RLAT_WIDTH),
.MEM_IF_RD_TO_WR_TURNAROUND_OCT(MEM_IF_RD_TO_WR_TURNAROUND_OCT),
.MEM_IF_WR_TO_RD_TURNAROUND_OCT(MEM_IF_WR_TO_RD_TURNAROUND_OCT)
) controller_inst (
.clk(clk),
.half_clk(half_clk),
.reset_n(reset_n),
.itf_cmd_ready(itf_cmd_ready),
.itf_cmd_valid(itf_cmd_valid),
.itf_cmd(itf_cmd),
.itf_cmd_address(itf_cmd_address),
.itf_cmd_burstlen(itf_cmd_burstlen),
.itf_cmd_id(itf_cmd_id),
.itf_cmd_priority(itf_cmd_priority),
.itf_cmd_autopercharge(itf_cmd_autopercharge),
.itf_cmd_multicast(itf_cmd_multicast),
.itf_wr_data_ready(itf_wr_data_ready),
.itf_wr_data_valid(itf_wr_data_valid),
.itf_wr_data(itf_wr_data),
.itf_wr_data_byte_en(itf_wr_data_byte_en),
.itf_wr_data_begin(itf_wr_data_begin),
.itf_wr_data_last(itf_wr_data_last),
.itf_wr_data_id(itf_wr_data_id),
.itf_rd_data_ready(itf_rd_data_ready),
.itf_rd_data_valid(itf_rd_data_valid),
.itf_rd_data(itf_rd_data),
.itf_rd_data_error(itf_rd_data_error),
.itf_rd_data_begin(itf_rd_data_begin),
.itf_rd_data_last(itf_rd_data_last),
.itf_rd_data_id(itf_rd_data_id),
.afi_rst_n(afi_rst_n),
.afi_cs_n(afi_cs_n),
.afi_cke(afi_cke),
.afi_odt(afi_odt),
.afi_addr(afi_addr),
.afi_ba(afi_ba),
.afi_ras_n(afi_ras_n),
.afi_cas_n(afi_cas_n),
.afi_we_n(afi_we_n),
.afi_dqs_burst(afi_dqs_burst),
.afi_wdata_valid(afi_wdata_valid),
.afi_wdata(afi_wdata),
.afi_dm(afi_dm),
.afi_wlat(afi_wlat),
.afi_rdata_en(afi_rdata_en),
.afi_rdata_en_full(afi_rdata_en_full),
.afi_rdata(afi_rdata),
.afi_rdata_valid(afi_rdata_valid),
.afi_rlat(afi_rlat),
.afi_cal_success(afi_cal_success),
.afi_cal_fail(afi_cal_fail),
.afi_cal_req(afi_cal_req),
.afi_mem_clk_disable(afi_mem_clk_disable),
.afi_cal_byte_lane_sel_n(afi_cal_byte_lane_sel_n),
.afi_ctl_refresh_done(afi_ctl_refresh_done),
.afi_seq_busy(afi_seq_busy),
.afi_ctl_long_idle(afi_ctl_long_idle),
.local_init_done(local_init_done),
.local_refresh_ack(local_refresh_ack),
.local_powerdn_ack(local_powerdn_ack),
.local_self_rfsh_ack(local_self_rfsh_ack),
.local_autopch_req(local_autopch_req),
.local_refresh_req(local_refresh_req),
.local_refresh_chip(local_refresh_chip),
.local_powerdn_req(local_powerdn_req),
.local_self_rfsh_req(local_self_rfsh_req),
.local_self_rfsh_chip(local_self_rfsh_chip),
.local_multicast(local_multicast),
.local_priority(local_priority),
.ecc_interrupt(ecc_interrupt),
.csr_read_req(csr_read_req),
.csr_write_req(csr_write_req),
.csr_burst_count(csr_burst_count),
.csr_beginbursttransfer(csr_beginbursttransfer),
.csr_addr(csr_addr),
.csr_wdata(csr_wdata),
.csr_rdata(csr_rdata),
.csr_be(csr_be),
.csr_rdata_valid(csr_rdata_valid),
.csr_waitrequest(csr_waitrequest)
);
endmodule
|
/*
Copyright (c) 2015-2020 Alex Forencich
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
*/
// Language: Verilog 2001
`resetall
`timescale 1ns / 1ps
`default_nettype none
/*
* si5324_i2c_init
*/
module si5324_i2c_init (
input wire clk,
input wire rst,
/*
* I2C master interface
*/
output wire [6:0] cmd_address,
output wire cmd_start,
output wire cmd_read,
output wire cmd_write,
output wire cmd_write_multiple,
output wire cmd_stop,
output wire cmd_valid,
input wire cmd_ready,
output wire [7:0] data_out,
output wire data_out_valid,
input wire data_out_ready,
output wire data_out_last,
/*
* Status
*/
output wire busy,
/*
* Configuration
*/
input wire start
);
/*
Generic module for I2C bus initialization. Good for use when multiple devices
on an I2C bus must be initialized on system start without intervention of a
general-purpose processor.
Copy this file and change init_data and INIT_DATA_LEN as needed.
This module can be used in two modes: simple device initalization, or multiple
device initialization. In multiple device mode, the same initialization sequence
can be performed on multiple different device addresses.
To use single device mode, only use the start write to address and write data commands.
The module will generate the I2C commands in sequential order. Terminate the list
with a 0 entry.
To use the multiple device mode, use the start data and start address block commands
to set up lists of initialization data and device addresses. The module enters
multiple device mode upon seeing a start data block command. The module stores the
offset of the start of the data block and then skips ahead until it reaches a start
address block command. The module will store the offset to the address block and
read the first address in the block. Then it will jump back to the data block
and execute it, substituting the stored address for each current address write
command. Upon reaching the start address block command, the module will read out the
next address and start again at the top of the data block. If the module encounters
a start data block command while looking for an address, then it will store a new data
offset and then look for a start address block command. Terminate the list with a 0
entry. Normal address commands will operate normally inside a data block.
Commands:
00 0000000 : stop
00 0000001 : exit multiple device mode
00 0000011 : start write to current address
00 0001000 : start address block
00 0001001 : start data block
00 1000001 : send I2C stop
01 aaaaaaa : start write to address
1 dddddddd : write 8-bit data
Examples
write 0x11223344 to register 0x0004 on device at 0x50
01 1010000 start write to 0x50
1 00000000 write address 0x0004
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
0 00000000 stop
write 0x11223344 to register 0x0004 on devices at 0x50, 0x51, 0x52, and 0x53
00 0001001 start data block
00 0000011 start write to current address
1 00000100
1 00010001 write data 0x11223344
1 00100010
1 00110011
1 01000100
00 0001000 start address block
01 1010000 address 0x50
01 1010000 address 0x51
01 1010000 address 0x52
01 1010000 address 0x53
00 0000000 stop
*/
// init_data ROM
localparam INIT_DATA_LEN = 37;
reg [8:0] init_data [INIT_DATA_LEN-1:0];
initial begin
// init Si5324 registers
init_data[0] = {2'b01, 7'h74}; // start write to 0x74 (I2C mux)
init_data[1] = {1'b1, 8'h10}; // select Si5324
init_data[2] = {2'b00, 7'b1000001}; // I2C stop
init_data[3] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[4] = {1'b1, 8'd0}; // register 0
init_data[5] = {1'b1, 8'h54}; // Reg 0: Free run, Clock off before ICAL, Bypass off (normal operation)
init_data[6] = {1'b1, 8'hE4}; // Reg 1: CKIN2 second priority, CKIN1 first priority
init_data[7] = {1'b1, 8'h12}; // Reg 2: BWSEL = 1
init_data[8] = {1'b1, 8'h15}; // Reg 3: CKIN1 selected, Digital Hold off, Output clocks disabled during ICAL
init_data[9] = {1'b1, 8'h92}; // Reg 4: Automatic Revertive, HIST_DEL = 0x12
init_data[10] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[11] = {1'b1, 8'd10}; // register 10
init_data[12] = {1'b1, 8'h08}; // Reg 10: CKOUT2 disabled, CKOUT1 enabled
init_data[13] = {1'b1, 8'h40}; // Reg 11: CKIN2 enabled, CKIN1 enabled
init_data[14] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[15] = {1'b1, 8'd25}; // register 25
init_data[16] = {1'b1, 8'hA0}; // Reg 25: N1_HS = 9
init_data[17] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[18] = {1'b1, 8'd31}; // register 31
init_data[19] = {1'b1, 8'h00}; // Regs 31,32,33: NC1_LS = 4
init_data[20] = {1'b1, 8'h00};
init_data[21] = {1'b1, 8'h03};
init_data[22] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[23] = {1'b1, 8'd40}; // register 40
init_data[24] = {1'b1, 8'hC2}; // Regs 40,41,42: N2_HS = 10, N2_LS = 150000
init_data[25] = {1'b1, 8'h49};
init_data[26] = {1'b1, 8'hEF};
init_data[27] = {1'b1, 8'h00}; // Regs 43,44,45: N31 = 30475
init_data[28] = {1'b1, 8'h77};
init_data[29] = {1'b1, 8'h0B};
init_data[30] = {1'b1, 8'h00}; // Regs 46,47,48: N32 = 30475
init_data[31] = {1'b1, 8'h77};
init_data[32] = {1'b1, 8'h0B};
init_data[33] = {2'b01, 7'h68}; // start write to 0x68 (Si5324)
init_data[34] = {1'b1, 8'd136}; // register 136
init_data[35] = {1'b1, 8'h40}; // Reg 136: ICAL = 1
init_data[36] = 9'd0; // stop
end
localparam [3:0]
STATE_IDLE = 3'd0,
STATE_RUN = 3'd1,
STATE_TABLE_1 = 3'd2,
STATE_TABLE_2 = 3'd3,
STATE_TABLE_3 = 3'd4;
reg [4:0] state_reg = STATE_IDLE, state_next;
parameter AW = $clog2(INIT_DATA_LEN);
reg [8:0] init_data_reg = 9'd0;
reg [AW-1:0] address_reg = {AW{1'b0}}, address_next;
reg [AW-1:0] address_ptr_reg = {AW{1'b0}}, address_ptr_next;
reg [AW-1:0] data_ptr_reg = {AW{1'b0}}, data_ptr_next;
reg [6:0] cur_address_reg = 7'd0, cur_address_next;
reg [6:0] cmd_address_reg = 7'd0, cmd_address_next;
reg cmd_start_reg = 1'b0, cmd_start_next;
reg cmd_write_reg = 1'b0, cmd_write_next;
reg cmd_stop_reg = 1'b0, cmd_stop_next;
reg cmd_valid_reg = 1'b0, cmd_valid_next;
reg [7:0] data_out_reg = 8'd0, data_out_next;
reg data_out_valid_reg = 1'b0, data_out_valid_next;
reg start_flag_reg = 1'b0, start_flag_next;
reg busy_reg = 1'b0;
assign cmd_address = cmd_address_reg;
assign cmd_start = cmd_start_reg;
assign cmd_read = 1'b0;
assign cmd_write = cmd_write_reg;
assign cmd_write_multiple = 1'b0;
assign cmd_stop = cmd_stop_reg;
assign cmd_valid = cmd_valid_reg;
assign data_out = data_out_reg;
assign data_out_valid = data_out_valid_reg;
assign data_out_last = 1'b1;
assign busy = busy_reg;
always @* begin
state_next = STATE_IDLE;
address_next = address_reg;
address_ptr_next = address_ptr_reg;
data_ptr_next = data_ptr_reg;
cur_address_next = cur_address_reg;
cmd_address_next = cmd_address_reg;
cmd_start_next = cmd_start_reg & ~(cmd_valid & cmd_ready);
cmd_write_next = cmd_write_reg & ~(cmd_valid & cmd_ready);
cmd_stop_next = cmd_stop_reg & ~(cmd_valid & cmd_ready);
cmd_valid_next = cmd_valid_reg & ~cmd_ready;
data_out_next = data_out_reg;
data_out_valid_next = data_out_valid_reg & ~data_out_ready;
start_flag_next = start_flag_reg;
if (cmd_valid | data_out_valid) begin
// wait for output registers to clear
state_next = state_reg;
end else begin
case (state_reg)
STATE_IDLE: begin
// wait for start signal
if (~start_flag_reg & start) begin
address_next = {AW{1'b0}};
start_flag_next = 1'b1;
state_next = STATE_RUN;
end else begin
state_next = STATE_IDLE;
end
end
STATE_RUN: begin
// process commands
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b001000001) begin
// send stop
cmd_write_next = 1'b0;
cmd_start_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_RUN;
end
end
STATE_TABLE_1: begin
// find address table start
if (init_data_reg == 9'b000001000) begin
// address table start
address_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end
end
STATE_TABLE_2: begin
// find next address
if (init_data_reg[8:7] == 2'b01) begin
// write address command
// store address and move to data table
cur_address_next = init_data_reg[6:0];
address_ptr_next = address_reg + 1;
address_next = data_ptr_reg;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_2;
end
end
STATE_TABLE_3: begin
// process data table with selected address
if (init_data_reg[8] == 1'b1) begin
// write data
cmd_write_next = 1'b1;
cmd_stop_next = 1'b0;
cmd_valid_next = 1'b1;
data_out_next = init_data_reg[7:0];
data_out_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg[8:7] == 2'b01) begin
// write address
cmd_address_next = init_data_reg[6:0];
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000000011) begin
// write current address
cmd_address_next = cur_address_reg;
cmd_start_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b001000001) begin
// send stop
cmd_write_next = 1'b0;
cmd_start_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end else if (init_data_reg == 9'b000001001) begin
// data table start
data_ptr_next = address_reg + 1;
address_next = address_reg + 1;
state_next = STATE_TABLE_1;
end else if (init_data_reg == 9'b000001000) begin
// address table start
address_next = address_ptr_reg;
state_next = STATE_TABLE_2;
end else if (init_data_reg == 9'd1) begin
// exit mode
address_next = address_reg + 1;
state_next = STATE_RUN;
end else if (init_data_reg == 9'd0) begin
// stop
cmd_start_next = 1'b0;
cmd_write_next = 1'b0;
cmd_stop_next = 1'b1;
cmd_valid_next = 1'b1;
state_next = STATE_IDLE;
end else begin
// invalid command, skip
address_next = address_reg + 1;
state_next = STATE_TABLE_3;
end
end
endcase
end
end
always @(posedge clk) begin
if (rst) begin
state_reg <= STATE_IDLE;
init_data_reg <= 9'd0;
address_reg <= {AW{1'b0}};
address_ptr_reg <= {AW{1'b0}};
data_ptr_reg <= {AW{1'b0}};
cur_address_reg <= 7'd0;
cmd_valid_reg <= 1'b0;
data_out_valid_reg <= 1'b0;
start_flag_reg <= 1'b0;
busy_reg <= 1'b0;
end else begin
state_reg <= state_next;
// read init_data ROM
init_data_reg <= init_data[address_next];
address_reg <= address_next;
address_ptr_reg <= address_ptr_next;
data_ptr_reg <= data_ptr_next;
cur_address_reg <= cur_address_next;
cmd_valid_reg <= cmd_valid_next;
data_out_valid_reg <= data_out_valid_next;
start_flag_reg <= start & start_flag_next;
busy_reg <= (state_reg != STATE_IDLE);
end
cmd_address_reg <= cmd_address_next;
cmd_start_reg <= cmd_start_next;
cmd_write_reg <= cmd_write_next;
cmd_stop_reg <= cmd_stop_next;
data_out_reg <= data_out_next;
end
endmodule
`resetall
|
module ArithAlu(
/* verilator lint_off UNUSED */
clk,
opMode,
srca,
srcb,
dst,
sri,
sro
);
input clk;
input[3:0] opMode;
input[63:0] srca;
input[63:0] srcb;
output[63:0] dst;
input[3:0] sri;
output[3:0] sro;
parameter[3:0] UOP_NONE = 4'h00;
parameter[3:0] UOP_ADD = 4'h01;
parameter[3:0] UOP_SUB = 4'h02;
parameter[3:0] UOP_MUL = 4'h03;
parameter[3:0] UOP_AND = 4'h04;
parameter[3:0] UOP_OR = 4'h05;
parameter[3:0] UOP_XOR = 4'h06;
parameter[3:0] UOP_SHL = 4'h07;
parameter[3:0] UOP_SHR = 4'h08;
parameter[3:0] UOP_SAR = 4'h09;
parameter[3:0] UOP_ADDC = 4'h0A;
parameter[3:0] UOP_CMPEQ = 4'h0B;
parameter[3:0] UOP_CMPGT = 4'h0C;
parameter[3:0] UOP_CMPGE = 4'h0D;
parameter[3:0] UOP_CMPHS = 4'h0E;
parameter[3:0] UOP_CMPHI = 4'h0F;
// reg[63:0] tSrcaQ;
// reg[63:0] tSrcbQ;
/* verilator lint_off UNOPTFLAT */
reg[63:0] tDstQ;
// reg[31:0] tDst;
reg[5:0] tShl;
reg[3:0] tSr;
assign dst=tDstQ;
assign sro=tSr;
always @ (opMode) begin
case(opMode)
UOP_ADD: begin
tDstQ = srca+srcb;
tSr=sri;
end
UOP_SUB: begin
tDstQ = srca-srcb;
tSr=sri;
end
UOP_MUL: begin
tDstQ = srca*srcb;
tSr=sri;
end
UOP_AND: begin
tDstQ = srca&srcb;
tSr=sri;
end
UOP_OR: begin
tDstQ = srca|srcb;
tSr=sri;
end
UOP_XOR: begin
tDstQ = srca^srcb;
tSr=sri;
end
UOP_SHL: begin
tShl = srcb[5:0];
tDstQ = srca<<tShl;
tSr=sri;
end
UOP_SHR: begin
tShl = srcb[5:0];
tDstQ = srca>>tShl;
tSr=sri;
end
UOP_SAR: begin
tShl = srcb[5:0];
tDstQ = srca>>>tShl;
tSr=sri;
end
UOP_ADDC: begin
if(sri[0])
tDstQ = srca+srcb+1;
else
tDstQ = srca+srcb;
tSr[3:2]=sri[3:2];
tSr[0]=tDstQ[31]^srca[31];
tSr[1]=tDstQ[63]^srca[63];
end
UOP_CMPEQ: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]==srcb[31:0]);
tSr[1]=(srca[63:0]==srcb[63:0]);
end
UOP_CMPGT: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
tSr[1]=(srca[63:0]>srcb[63:0]);
end
UOP_CMPGE: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
tSr[1]=(srca[63:0]>=srcb[63:0]);
end
UOP_CMPHS: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>srcb[31:0]);
tSr[1]=(srca[63:0]>srcb[63:0]);
end
UOP_CMPHI: begin
tDstQ = srca;
tSr[3:2]=sri[3:2];
tSr[0]=(srca[31:0]>=srcb[31:0]);
tSr[1]=(srca[63:0]>=srcb[63:0]);
end
default: begin
tDstQ = 64'h0000_0000_0000_0000;
tSr=sri;
end
endcase
// dst=tDstQ;
// sro=tSr;
end
endmodule
|
//*****************************************************************************
// (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : %version
// \ \ Application : MIG
// / / Filename : col_mach.v
// /___/ /\ Date Last Modified : $date$
// \ \ / \ Date Created : Tue Jun 30 2009
// \___\/\___\
//
//Device : 7-Series
//Design Name : DDR3 SDRAM
//Purpose :
//Reference :
//Revision History :
//*****************************************************************************
// The column machine manages the dq bus. Since there is a single DQ
// bus, and the column part of the DRAM is tightly coupled to this DQ
// bus, conceptually, the DQ bus and all of the column hardware in
// a multi rank DRAM array are managed as a single unit.
//
//
// The column machine does not "enforce" the column timing directly.
// It generates information and sends it to the bank machines. If the
// bank machines incorrectly make a request, the column machine will
// simply overwrite the existing request with the new request even
// if this would result in a timing or protocol violation.
//
// The column machine
// hosts the block that controls read and write data transfer
// to and from the dq bus.
//
// And if configured, there is provision for tracking the address
// of a command as it moves through the column pipeline. This
// address will be logged for detected ECC errors.
`timescale 1 ps / 1 ps
module mig_7series_v2_3_col_mach #
(
parameter TCQ = 100,
parameter BANK_WIDTH = 3,
parameter BURST_MODE = "8",
parameter COL_WIDTH = 12,
parameter CS_WIDTH = 4,
parameter DATA_BUF_ADDR_WIDTH = 8,
parameter DATA_BUF_OFFSET_WIDTH = 1,
parameter DELAY_WR_DATA_CNTRL = 0,
parameter DQS_WIDTH = 8,
parameter DRAM_TYPE = "DDR3",
parameter EARLY_WR_DATA_ADDR = "OFF",
parameter ECC = "OFF",
parameter MC_ERR_ADDR_WIDTH = 31,
parameter nCK_PER_CLK = 2,
parameter nPHY_WRLAT = 0,
parameter RANK_WIDTH = 2,
parameter ROW_WIDTH = 16
)
(/*AUTOARG*/
// Outputs
dq_busy_data, wr_data_offset, mc_wrdata_en, wr_data_en,
wr_data_addr, rd_rmw, ecc_err_addr, ecc_status_valid, wr_ecc_buf, rd_data_end,
rd_data_addr, rd_data_offset, rd_data_en, col_read_fifo_empty,
// Inputs
clk, rst, sent_col, col_size, col_wr_data_buf_addr,
phy_rddata_valid, col_periodic_rd, col_data_buf_addr, col_rmw,
col_rd_wr, col_ra, col_ba, col_row, col_a
);
input clk;
input rst;
input sent_col;
input col_rd_wr;
output reg dq_busy_data = 1'b0;
// The following generates a column command disable based mostly on the type
// of DRAM and the fabric to DRAM CK ratio.
generate
if ((nCK_PER_CLK == 1) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
begin : three_bumps
reg [1:0] granted_col_d_r;
wire [1:0] granted_col_d_ns = {sent_col, granted_col_d_r[1]};
always @(posedge clk) granted_col_d_r <= #TCQ granted_col_d_ns;
always @(/*AS*/granted_col_d_r or sent_col)
dq_busy_data = sent_col || |granted_col_d_r;
end
if (((nCK_PER_CLK == 2) && ((BURST_MODE == "8") || (DRAM_TYPE == "DDR3")))
|| ((nCK_PER_CLK == 1) && ((BURST_MODE == "4") || (DRAM_TYPE == "DDR2"))))
begin : one_bump
always @(/*AS*/sent_col) dq_busy_data = sent_col;
end
endgenerate
// This generates a data offset based on fabric clock to DRAM CK ratio and
// the size bit. Note that this is different that the dq_busy_data signal
// generated above.
reg [1:0] offset_r = 2'b0;
reg [1:0] offset_ns = 2'b0;
input col_size;
wire data_end;
generate
if(nCK_PER_CLK == 4) begin : data_valid_4_1
// For 4:1 mode all data is transfered in a single beat so the default
// values of 0 for offset_r/offset_ns suffice - just tie off data_end
assign data_end = 1'b1;
end
else begin
if(DATA_BUF_OFFSET_WIDTH == 2) begin : data_valid_1_1
always @(col_size or offset_r or rst or sent_col) begin
if (rst) offset_ns = 2'b0;
else begin
offset_ns = offset_r;
if (sent_col) offset_ns = 2'b1;
else if (|offset_r && (offset_r != {col_size, 1'b1}))
offset_ns = offset_r + 2'b1;
else offset_ns = 2'b0;
end
end
always @(posedge clk) offset_r <= #TCQ offset_ns;
assign data_end = col_size ? (offset_r == 2'b11) : offset_r[0];
end
else begin : data_valid_2_1
always @(col_size or rst or sent_col)
offset_ns[0] = rst ? 1'b0 : sent_col && col_size;
always @(posedge clk) offset_r[0] <= #TCQ offset_ns[0];
assign data_end = col_size ? offset_r[0] : 1'b1;
end
end
endgenerate
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r1 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg [DATA_BUF_OFFSET_WIDTH-1:0] offset_r2 = {DATA_BUF_OFFSET_WIDTH{1'b0}};
reg col_rd_wr_r1;
reg col_rd_wr_r2;
generate
if ((nPHY_WRLAT >= 1) || (DELAY_WR_DATA_CNTRL == 1)) begin : offset_pipe_0
always @(posedge clk) offset_r1 <=
#TCQ offset_r[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r1 <= #TCQ col_rd_wr;
end
if(nPHY_WRLAT == 2) begin : offset_pipe_1
always @(posedge clk) offset_r2 <=
#TCQ offset_r1[DATA_BUF_OFFSET_WIDTH-1:0];
always @(posedge clk) col_rd_wr_r2 <= #TCQ col_rd_wr_r1;
end
endgenerate
output wire [DATA_BUF_OFFSET_WIDTH-1:0] wr_data_offset;
assign wr_data_offset = (DELAY_WR_DATA_CNTRL == 1)
? offset_r1[DATA_BUF_OFFSET_WIDTH-1:0]
: (EARLY_WR_DATA_ADDR == "OFF")
? offset_r[DATA_BUF_OFFSET_WIDTH-1:0]
: offset_ns[DATA_BUF_OFFSET_WIDTH-1:0];
reg sent_col_r1;
reg sent_col_r2;
always @(posedge clk) sent_col_r1 <= #TCQ sent_col;
always @(posedge clk) sent_col_r2 <= #TCQ sent_col_r1;
wire wrdata_en = (nPHY_WRLAT == 0) ?
(sent_col || |offset_r) & ~col_rd_wr :
(nPHY_WRLAT == 1) ?
(sent_col_r1 || |offset_r1) & ~col_rd_wr_r1 :
//(nPHY_WRLAT >= 2) ?
(sent_col_r2 || |offset_r2) & ~col_rd_wr_r2;
output wire mc_wrdata_en;
assign mc_wrdata_en = wrdata_en;
output wire wr_data_en;
assign wr_data_en = (DELAY_WR_DATA_CNTRL == 1)
? ((sent_col_r1 || |offset_r1) && ~col_rd_wr_r1)
: ((sent_col || |offset_r) && ~col_rd_wr);
input [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr;
output wire [DATA_BUF_ADDR_WIDTH-1:0] wr_data_addr;
generate
if (DELAY_WR_DATA_CNTRL == 1) begin : delay_wr_data_cntrl_eq_1
reg [DATA_BUF_ADDR_WIDTH-1:0] col_wr_data_buf_addr_r;
always @(posedge clk) col_wr_data_buf_addr_r <=
#TCQ col_wr_data_buf_addr;
assign wr_data_addr = col_wr_data_buf_addr_r;
end
else begin : delay_wr_data_cntrl_ne_1
assign wr_data_addr = col_wr_data_buf_addr;
end
endgenerate
// CAS-RD to mc_rddata_en
wire read_data_valid = (sent_col || |offset_r) && col_rd_wr;
function integer clogb2 (input integer size); // ceiling logb2
begin
size = size - 1;
for (clogb2=1; size>1; clogb2=clogb2+1)
size = size >> 1;
end
endfunction // clogb2
// Implement FIFO that records reads as they are sent to the DRAM.
// When phy_rddata_valid is returned some unknown time later, the
// FIFO output is used to control how the data is interpreted.
input phy_rddata_valid;
output wire rd_rmw;
output reg [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr;
output reg ecc_status_valid;
output reg wr_ecc_buf;
output reg rd_data_end;
output reg [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr;
output reg [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset;
output reg rd_data_en /* synthesis syn_maxfan = 10 */;
output col_read_fifo_empty;
input col_periodic_rd;
input [DATA_BUF_ADDR_WIDTH-1:0] col_data_buf_addr;
input col_rmw;
input [RANK_WIDTH-1:0] col_ra;
input [BANK_WIDTH-1:0] col_ba;
input [ROW_WIDTH-1:0] col_row;
input [ROW_WIDTH-1:0] col_a;
// Real column address (skip A10/AP and A12/BC#). The maximum width is 12;
// the width will be tailored for the target DRAM downstream.
wire [11:0] col_a_full;
// Minimum row width is 12; take remaining 11 bits after omitting A10/AP
assign col_a_full[10:0] = {col_a[11], col_a[9:0]};
// Get the 12th bit when row address width accommodates it; omit A12/BC#
generate
if (ROW_WIDTH >= 14) begin : COL_A_FULL_11_1
assign col_a_full[11] = col_a[13];
end else begin : COL_A_FULL_11_0
assign col_a_full[11] = 0;
end
endgenerate
// Extract only the width of the target DRAM
wire [COL_WIDTH-1:0] col_a_extracted = col_a_full[COL_WIDTH-1:0];
localparam MC_ERR_LINE_WIDTH = MC_ERR_ADDR_WIDTH-DATA_BUF_OFFSET_WIDTH;
localparam FIFO_WIDTH = 1 /*data_end*/ +
1 /*periodic_rd*/ +
DATA_BUF_ADDR_WIDTH +
DATA_BUF_OFFSET_WIDTH +
((ECC == "OFF") ? 0 : 1+MC_ERR_LINE_WIDTH);
localparam FULL_RAM_CNT = (FIFO_WIDTH/6);
localparam REMAINDER = FIFO_WIDTH % 6;
localparam RAM_CNT = FULL_RAM_CNT + ((REMAINDER == 0 ) ? 0 : 1);
localparam RAM_WIDTH = (RAM_CNT*6);
generate
begin : read_fifo
wire [MC_ERR_LINE_WIDTH:0] ecc_line;
if (CS_WIDTH == 1)
assign ecc_line = {col_rmw, col_ba, col_row, col_a_extracted};
else
assign ecc_line = {col_rmw,
col_ra,
col_ba,
col_row,
col_a_extracted};
wire [FIFO_WIDTH-1:0] real_fifo_data;
if (ECC == "OFF")
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0]};
else
assign real_fifo_data = {data_end,
col_periodic_rd,
col_data_buf_addr,
offset_r[DATA_BUF_OFFSET_WIDTH-1:0],
ecc_line};
wire [RAM_WIDTH-1:0] fifo_in_data;
if (REMAINDER == 0)
assign fifo_in_data = real_fifo_data;
else
assign fifo_in_data = {{6-REMAINDER{1'b0}}, real_fifo_data};
wire [RAM_WIDTH-1:0] fifo_out_data_ns;
reg [4:0] head_r;
wire [4:0] head_ns = rst ? 5'b0 : read_data_valid
? (head_r + 5'b1)
: head_r;
always @(posedge clk) head_r <= #TCQ head_ns;
reg [4:0] tail_r;
wire [4:0] tail_ns = rst ? 5'b0 : phy_rddata_valid
? (tail_r + 5'b1)
: tail_r;
always @(posedge clk) tail_r <= #TCQ tail_ns;
assign col_read_fifo_empty = head_r == tail_r ? 1'b1 : 1'b0;
genvar i;
for (i=0; i<RAM_CNT; i=i+1) begin : fifo_ram
RAM32M
#(.INIT_A(64'h0000000000000000),
.INIT_B(64'h0000000000000000),
.INIT_C(64'h0000000000000000),
.INIT_D(64'h0000000000000000)
) RAM32M0 (
.DOA(fifo_out_data_ns[((i*6)+4)+:2]),
.DOB(fifo_out_data_ns[((i*6)+2)+:2]),
.DOC(fifo_out_data_ns[((i*6)+0)+:2]),
.DOD(),
.DIA(fifo_in_data[((i*6)+4)+:2]),
.DIB(fifo_in_data[((i*6)+2)+:2]),
.DIC(fifo_in_data[((i*6)+0)+:2]),
.DID(2'b0),
.ADDRA(tail_ns),
.ADDRB(tail_ns),
.ADDRC(tail_ns),
.ADDRD(head_r),
.WE(1'b1),
.WCLK(clk)
);
end // block: fifo_ram
reg [RAM_WIDTH-1:0] fifo_out_data_r;
always @(posedge clk) fifo_out_data_r <= #TCQ fifo_out_data_ns;
// When ECC is ON, most of the FIFO output is delayed
// by one state.
if (ECC == "OFF") begin
reg periodic_rd;
always @(/*AS*/phy_rddata_valid or fifo_out_data_r) begin
{rd_data_end,
periodic_rd,
rd_data_addr,
rd_data_offset} = fifo_out_data_r[FIFO_WIDTH-1:0];
ecc_err_addr = {MC_ERR_ADDR_WIDTH{1'b0}};
rd_data_en = phy_rddata_valid && ~periodic_rd;
ecc_status_valid = 1'b0;
wr_ecc_buf = 1'b0;
end
assign rd_rmw = 1'b0;
end
else begin
wire rd_data_end_ns;
wire periodic_rd;
wire [DATA_BUF_ADDR_WIDTH-1:0] rd_data_addr_ns;
wire [DATA_BUF_OFFSET_WIDTH-1:0] rd_data_offset_ns;
wire [MC_ERR_ADDR_WIDTH-1:0] ecc_err_addr_ns;
assign {rd_data_end_ns,
periodic_rd,
rd_data_addr_ns,
rd_data_offset_ns,
rd_rmw,
ecc_err_addr_ns[DATA_BUF_OFFSET_WIDTH+:MC_ERR_LINE_WIDTH]} =
{fifo_out_data_r[FIFO_WIDTH-1:0]};
assign ecc_err_addr_ns[0+:DATA_BUF_OFFSET_WIDTH] = rd_data_offset_ns;
always @(posedge clk) rd_data_end <= #TCQ rd_data_end_ns;
always @(posedge clk) rd_data_addr <= #TCQ rd_data_addr_ns;
always @(posedge clk) rd_data_offset <= #TCQ rd_data_offset_ns;
always @(posedge clk) ecc_err_addr <= #TCQ ecc_err_addr_ns;
wire rd_data_en_ns = phy_rddata_valid && ~(periodic_rd || rd_rmw);
always @(posedge clk) rd_data_en <= rd_data_en_ns;
wire ecc_status_valid_ns = phy_rddata_valid && ~periodic_rd;
always @(posedge clk) ecc_status_valid <= #TCQ ecc_status_valid_ns;
wire wr_ecc_buf_ns = phy_rddata_valid && ~periodic_rd && rd_rmw;
always @(posedge clk) wr_ecc_buf <= #TCQ wr_ecc_buf_ns;
end
end
endgenerate
endmodule
|
`define SMV
`include "routingBlock.v"
/*
* File: routingBlock_tb.v
* Test bench for routingblock.v
* Includes assertions for verification
*/
module main();
// Inputs to DUT
reg [8*32:0] inputState;
reg [2:0] inputSelect;
// Outputs of DUT
wire [31:0] result;
wire configInvalid;
routingBlock routingBlock_t(.inputState(inputState),
.inputSelect(inputSelect),
.out(result),
.configInvalid(configInvalid),
.NUM_INPUTS(8),
.NUM_INPUTS_LOG_2(3));
endmodule // main
/* ********* SMV Assertions *********
//SMV-Assertions
# Properties select_0, select_1, .., select_7, select_def:
# Assert when inputSelect = X, the Xth 32-bit block of inputState is returned.
# Note that this assumes INPUT_WIDTH = 32 in routingBlock.
# Note this only checks for 0 <= X < 8. If NUM_INPUTS is set to something higher than 8, more checks would need to be added.
\select_0 : assert G((\inputSelect = 0) -> (\result = \inputState [((32*1)-1)..(32*0)]));
\select_1 : assert G((\inputSelect = 1) -> (\result = \inputState [((32*2)-1)..(32*1)]));
\select_2 : assert G((\inputSelect = 2) -> (\result = \inputState [((32*3)-1)..(32*2)]));
\select_3 : assert G((\inputSelect = 3) -> (\result = \inputState [((32*4)-1)..(32*3)]));
\select_4 : assert G((\inputSelect = 4) -> (\result = \inputState [((32*5)-1)..(32*4)]));
\select_5 : assert G((\inputSelect = 5) -> (\result = \inputState [((32*6)-1)..(32*5)]));
\select_6 : assert G((\inputSelect = 6) -> (\result = \inputState [((32*7)-1)..(32*6)]));
\select_7 : assert G((\inputSelect = 7) -> (\result = \inputState [((32*8)-1)..(32*7)]));
\select_def : assert G((\inputSelect > 7) -> (\result = 0));
# Properties select_inv, select_val:
# Assert configInvalid is set iff inputSelect is outside the range [0,7]
# Note if NUM_INPUTS is changed, the checked range would need to be adjusted.
\select_inv : assert G(((\inputSelect < 0) || (\inputSelect > 7)) -> \configInvalid );
\select_val : assert G((\inputSelect < 8) -> ~\configInvalid );
//SMV-Assertions
*/ |
//-----------------------------------------------------------------------------
//-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
//--
//-- This file contains confidential and proprietary information
//-- of Xilinx, Inc. and is protected under U.S. and
//-- international copyright and other intellectual property
//-- laws.
//--
//-- DISCLAIMER
//-- This disclaimer is not a license and does not grant any
//-- rights to the materials distributed herewith. Except as
//-- otherwise provided in a valid license issued to you by
//-- Xilinx, and to the maximum extent permitted by applicable
//-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
//-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
//-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
//-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
//-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
//-- (2) Xilinx shall not be liable (whether in contract or tort,
//-- including negligence, or under any other theory of
//-- liability) for any loss or damage of any kind or nature
//-- related to, arising under or in connection with these
//-- materials, including for any direct, or any indirect,
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//-- reasonably foreseeable or Xilinx had been advised of the
//-- possibility of the same.
//--
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//-- regulations governing limitations on product liability.
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//-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
//-- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description: Up-Sizer
// Up-Sizer for generic SI- and MI-side data widths. This module instantiates
// Address, Write Data and Read Data Up-Sizer modules, each one taking care
// of the channel specific tasks.
// The Address Up-Sizer can handle both AR and AW channels.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
// axi_upsizer
// a_upsizer
// fifo
// fifo_gen
// fifo_coregen
// w_upsizer
// r_upsizer
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_dwidth_converter_v2_1_axi_upsizer #
(
parameter C_FAMILY = "virtex7",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_AXI_PROTOCOL = 0,
// Protocol of SI and MI (0=AXI4, 1=AXI3).
parameter integer C_S_AXI_ID_WIDTH = 1,
// Width of all ID signals on SI side of converter.
// Range: 1 - 32.
parameter integer C_SUPPORTS_ID = 0,
// Indicates whether SI-side ID needs to be stored and compared.
// 0 = No, SI is single-threaded, propagate all transactions.
// 1 = Yes, stall any transaction with ID different than outstanding transactions.
parameter integer C_AXI_ADDR_WIDTH = 32,
// Width of all ADDR signals on SI and MI.
// Range (AXI4, AXI3): 12 - 64.
parameter integer C_S_AXI_DATA_WIDTH = 32,
// Width of s_axi_wdata and s_axi_rdata.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_M_AXI_DATA_WIDTH = 64,
// Width of m_axi_wdata and m_axi_rdata.
// Assume always >= than C_S_AXI_DATA_WIDTH.
// Range: 32, 64, 128, 256, 512, 1024.
parameter integer C_AXI_SUPPORTS_WRITE = 1,
parameter integer C_AXI_SUPPORTS_READ = 1,
///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// parameter integer C_FIFO_MODE = 0,
parameter integer C_FIFO_MODE = 1,
// 0=None, 1=Packet_FIFO, 2=Clock_conversion_Packet_FIFO, 3=Simple_FIFO (FUTURE), 4=Clock_conversion_Simple_FIFO (FUTURE)
parameter integer C_S_AXI_ACLK_RATIO = 1, // Clock frequency ratio of SI w.r.t. MI.
// Range = [1..16].
parameter integer C_M_AXI_ACLK_RATIO = 2, // Clock frequency ratio of MI w.r.t. SI.
// Range = [2..16] if C_S_AXI_ACLK_RATIO = 1; else must be 1.
parameter integer C_AXI_IS_ACLK_ASYNC = 0, // Indicates whether S and M clocks are asynchronous.
// FUTURE FEATURE
// Range = [0, 1].
parameter integer C_PACKING_LEVEL = 1,
// 0 = Never pack (expander only); packing logic is omitted.
// 1 = Pack only when CACHE[1] (Modifiable) is high.
// 2 = Always pack, regardless of sub-size transaction or Modifiable bit.
// (Required when used as helper-core by mem-con. Same size AXI interfaces
// should only be used when always packing)
parameter integer C_SYNCHRONIZER_STAGE = 3
)
(
// Slave Interface
input wire s_axi_aresetn,
input wire s_axi_aclk,
// Slave Interface Write Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [8-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [2-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire s_axi_awvalid,
output wire s_axi_awready,
// Slave Interface Write Data Ports
input wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_S_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire s_axi_wvalid,
output wire s_axi_wready,
// Slave Interface Write Response Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire s_axi_bvalid,
input wire s_axi_bready,
// Slave Interface Read Address Ports
input wire [C_S_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [8-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [2-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire s_axi_arvalid,
output wire s_axi_arready,
// Slave Interface Read Data Ports
output wire [C_S_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_S_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire s_axi_rvalid,
input wire s_axi_rready,
// Master Interface
input wire m_axi_aresetn,
input wire m_axi_aclk,
// Master Interface Write Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [8-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [2-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire m_axi_awvalid,
input wire m_axi_awready,
// Master Interface Write Data Ports
output wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_M_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire m_axi_wvalid,
input wire m_axi_wready,
// Master Interface Write Response Ports
input wire [2-1:0] m_axi_bresp,
input wire m_axi_bvalid,
output wire m_axi_bready,
// Master Interface Read Address Port
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [8-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [2-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire m_axi_arvalid,
input wire m_axi_arready,
// Master Interface Read Data Ports
input wire [C_M_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire m_axi_rvalid,
output wire m_axi_rready
);
// Log2 of number of 32bit word on SI-side.
localparam integer C_S_AXI_BYTES_LOG = log2(C_S_AXI_DATA_WIDTH/8);
// Log2 of number of 32bit word on MI-side.
localparam integer C_M_AXI_BYTES_LOG = log2(C_M_AXI_DATA_WIDTH/8);
// Log2 of Up-Sizing ratio for data.
localparam integer C_RATIO = C_M_AXI_DATA_WIDTH / C_S_AXI_DATA_WIDTH;
localparam integer C_RATIO_LOG = log2(C_RATIO);
localparam P_BYPASS = 32'h0;
localparam P_LIGHTWT = 32'h7;
localparam P_FWD_REV = 32'h1;
localparam integer P_CONV_LIGHT_WT = 0;
localparam integer P_AXI4 = 0;
localparam integer C_FIFO_DEPTH_LOG = 5;
localparam P_SI_LT_MI = (C_S_AXI_ACLK_RATIO < C_M_AXI_ACLK_RATIO);
localparam integer P_ACLK_RATIO = P_SI_LT_MI ? (C_M_AXI_ACLK_RATIO / C_S_AXI_ACLK_RATIO) : (C_S_AXI_ACLK_RATIO / C_M_AXI_ACLK_RATIO);
localparam integer P_NO_FIFO = 0;
localparam integer P_PKTFIFO = 1;
localparam integer P_PKTFIFO_CLK = 2;
localparam integer P_DATAFIFO = 3;
localparam integer P_DATAFIFO_CLK = 4;
localparam P_CLK_CONV = ((C_FIFO_MODE == P_PKTFIFO_CLK) || (C_FIFO_MODE == P_DATAFIFO_CLK));
localparam integer C_M_AXI_AW_REGISTER = 0;
// Simple register AW output.
// Range: 0, 1
localparam integer C_M_AXI_W_REGISTER = 1; // Parameter not used; W reg always implemented.
localparam integer C_M_AXI_AR_REGISTER = 0;
// Simple register AR output.
// Range: 0, 1
localparam integer C_S_AXI_R_REGISTER = 0;
// Simple register R output (SI).
// Range: 0, 1
localparam integer C_M_AXI_R_REGISTER = 1;
// Register slice on R input (MI) side.
// 0 = Bypass (not recommended due to combinatorial M_RVALID -> M_RREADY path)
// 1 = Fully-registered (needed only when upsizer propagates bursts at 1:1 width ratio)
// 7 = Light-weight (safe when upsizer always packs at 1:n width ratio, as in interconnect)
localparam integer P_RID_QUEUE = ((C_SUPPORTS_ID != 0) && !((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK))) ? 1 : 0;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
// Log2.
function integer log2
(
input integer x
);
integer acc;
begin
acc=0;
while ((2**acc) < x)
acc = acc + 1;
log2 = acc;
end
endfunction
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire aclk;
wire m_aclk;
wire sample_cycle;
wire sample_cycle_early;
wire sm_aresetn;
wire s_aresetn_i;
wire [C_S_AXI_ID_WIDTH-1:0] sr_awid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_awaddr ;
wire [8-1:0] sr_awlen ;
wire [3-1:0] sr_awsize ;
wire [2-1:0] sr_awburst ;
wire [2-1:0] sr_awlock ;
wire [4-1:0] sr_awcache ;
wire [3-1:0] sr_awprot ;
wire [4-1:0] sr_awregion ;
wire [4-1:0] sr_awqos ;
wire sr_awvalid ;
wire sr_awready ;
wire [C_S_AXI_ID_WIDTH-1:0] sr_arid ;
wire [C_AXI_ADDR_WIDTH-1:0] sr_araddr ;
wire [8-1:0] sr_arlen ;
wire [3-1:0] sr_arsize ;
wire [2-1:0] sr_arburst ;
wire [2-1:0] sr_arlock ;
wire [4-1:0] sr_arcache ;
wire [3-1:0] sr_arprot ;
wire [4-1:0] sr_arregion ;
wire [4-1:0] sr_arqos ;
wire sr_arvalid ;
wire sr_arready ;
wire [C_S_AXI_DATA_WIDTH-1:0] sr_wdata ;
wire [(C_S_AXI_DATA_WIDTH/8)-1:0] sr_wstrb ;
wire sr_wlast ;
wire sr_wvalid ;
wire sr_wready ;
wire [C_M_AXI_DATA_WIDTH-1:0] mr_rdata ;
wire [2-1:0] mr_rresp ;
wire mr_rlast ;
wire mr_rvalid ;
wire mr_rready ;
wire m_axi_rready_i;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_i ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_awlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?8:4)-1:0] s_axi_arlen_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_awlock_ii ;
wire [((C_AXI_PROTOCOL==P_AXI4)?1:2)-1:0] s_axi_arlock_ii ;
wire [3:0] s_axi_awregion_ii;
wire [3:0] s_axi_arregion_ii;
assign s_axi_awlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen : s_axi_awlen[3:0];
assign s_axi_awlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlock[0] : s_axi_awlock;
assign s_axi_arlen_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen : s_axi_arlen[3:0];
assign s_axi_arlock_i = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlock[0] : s_axi_arlock;
assign sr_awlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awlen_ii: {4'b0, s_axi_awlen_ii};
assign sr_awlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_awlock_ii} : s_axi_awlock_ii;
assign sr_arlen = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arlen_ii: {4'b0, s_axi_arlen_ii};
assign sr_arlock = (C_AXI_PROTOCOL == P_AXI4) ? {1'b0, s_axi_arlock_ii} : s_axi_arlock_ii;
assign sr_awregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_awregion_ii : 4'b0;
assign sr_arregion = (C_AXI_PROTOCOL == P_AXI4) ? s_axi_arregion_ii : 4'b0;
assign aclk = s_axi_aclk;
assign sm_aresetn = s_axi_aresetn & m_axi_aresetn;
generate
if (P_CLK_CONV) begin : gen_clock_conv
if (C_AXI_IS_ACLK_ASYNC) begin : gen_async_conv
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end else begin : gen_sync_conv
wire fast_aclk;
wire slow_aclk;
reg s_aresetn_r;
if (P_SI_LT_MI) begin : gen_fastclk_mi
assign fast_aclk = m_axi_aclk;
assign slow_aclk = s_axi_aclk;
end else begin : gen_fastclk_si
assign fast_aclk = s_axi_aclk;
assign slow_aclk = m_axi_aclk;
end
assign m_aclk = m_axi_aclk;
assign s_aresetn_i = s_aresetn_r;
always @(negedge sm_aresetn, posedge fast_aclk) begin
if (~sm_aresetn) begin
s_aresetn_r <= 1'b0;
end else if (s_axi_aresetn & m_axi_aresetn & sample_cycle_early) begin
s_aresetn_r <= 1'b1;
end
end
// Sample cycle used to determine when to assert a signal on a fast clock
// to be flopped onto a slow clock.
axi_clock_converter_v2_1_axic_sample_cycle_ratio #(
.C_RATIO ( P_ACLK_RATIO )
)
axic_sample_cycle_inst (
.SLOW_ACLK ( slow_aclk ) ,
.FAST_ACLK ( fast_aclk ) ,
.SAMPLE_CYCLE_EARLY ( sample_cycle_early ) ,
.SAMPLE_CYCLE ( sample_cycle )
);
end
end else begin : gen_no_clk_conv
assign m_aclk = s_axi_aclk;
assign s_aresetn_i = s_axi_aresetn;
assign sample_cycle_early = 1'b1;
assign sample_cycle = 1'b1;
end // gen_clock_conv
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_AW (C_AXI_SUPPORTS_WRITE ? P_LIGHTWT : P_BYPASS),
.C_REG_CONFIG_AR (C_AXI_SUPPORTS_READ ? P_LIGHTWT : P_BYPASS)
)
si_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (aclk),
.s_axi_awid (s_axi_awid ),
.s_axi_awaddr (s_axi_awaddr ),
.s_axi_awlen (s_axi_awlen_i ),
.s_axi_awsize (s_axi_awsize ),
.s_axi_awburst (s_axi_awburst ),
.s_axi_awlock (s_axi_awlock_i ),
.s_axi_awcache (s_axi_awcache ),
.s_axi_awprot (s_axi_awprot ),
.s_axi_awregion (s_axi_awregion ),
.s_axi_awqos (s_axi_awqos ),
.s_axi_awuser (1'b0 ),
.s_axi_awvalid (s_axi_awvalid ),
.s_axi_awready (s_axi_awready ),
.s_axi_wid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.s_axi_wdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_S_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid (s_axi_arid ),
.s_axi_araddr (s_axi_araddr ),
.s_axi_arlen (s_axi_arlen_i ),
.s_axi_arsize (s_axi_arsize ),
.s_axi_arburst (s_axi_arburst ),
.s_axi_arlock (s_axi_arlock_i ),
.s_axi_arcache (s_axi_arcache ),
.s_axi_arprot (s_axi_arprot ),
.s_axi_arregion (s_axi_arregion ),
.s_axi_arqos (s_axi_arqos ),
.s_axi_aruser (1'b0 ),
.s_axi_arvalid (s_axi_arvalid ),
.s_axi_arready (s_axi_arready ),
.s_axi_rid ( ) ,
.s_axi_rdata ( ) ,
.s_axi_rresp ( ) ,
.s_axi_rlast ( ) ,
.s_axi_ruser ( ) ,
.s_axi_rvalid ( ) ,
.s_axi_rready ( 1'b0 ) ,
.m_axi_awid (sr_awid ),
.m_axi_awaddr (sr_awaddr ),
.m_axi_awlen (s_axi_awlen_ii),
.m_axi_awsize (sr_awsize ),
.m_axi_awburst (sr_awburst ),
.m_axi_awlock (s_axi_awlock_ii),
.m_axi_awcache (sr_awcache ),
.m_axi_awprot (sr_awprot ),
.m_axi_awregion (s_axi_awregion_ii ),
.m_axi_awqos (sr_awqos ),
.m_axi_awuser (),
.m_axi_awvalid (sr_awvalid ),
.m_axi_awready (sr_awready ),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( {C_S_AXI_ID_WIDTH{1'b0}} ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (sr_arid ),
.m_axi_araddr (sr_araddr ),
.m_axi_arlen (s_axi_arlen_ii),
.m_axi_arsize (sr_arsize ),
.m_axi_arburst (sr_arburst ),
.m_axi_arlock (s_axi_arlock_ii),
.m_axi_arcache (sr_arcache ),
.m_axi_arprot (sr_arprot ),
.m_axi_arregion (s_axi_arregion_ii ),
.m_axi_arqos (sr_arqos ),
.m_axi_aruser (),
.m_axi_arvalid (sr_arvalid ),
.m_axi_arready (sr_arready ),
.m_axi_rid ( {C_S_AXI_ID_WIDTH{1'b0}}),
.m_axi_rdata ( {C_S_AXI_DATA_WIDTH{1'b0}} ),
.m_axi_rresp ( 2'b00 ),
.m_axi_rlast ( 1'b0 ),
.m_axi_ruser ( 1'b0 ),
.m_axi_rvalid ( 1'b0 ),
.m_axi_rready ( )
);
/////////////////////////////////////////////////////////////////////////////
// Handle Write Channels (AW/W/B)
/////////////////////////////////////////////////////////////////////////////
if (C_AXI_SUPPORTS_WRITE == 1) begin : USE_WRITE
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr_i ;
wire [8-1:0] m_axi_awlen_i ;
wire [3-1:0] m_axi_awsize_i ;
wire [2-1:0] m_axi_awburst_i ;
wire [2-1:0] m_axi_awlock_i ;
wire [4-1:0] m_axi_awcache_i ;
wire [3-1:0] m_axi_awprot_i ;
wire [4-1:0] m_axi_awregion_i ;
wire [4-1:0] m_axi_awqos_i ;
wire m_axi_awvalid_i ;
wire m_axi_awready_i ;
wire s_axi_bvalid_i ;
wire [2-1:0] s_axi_bresp_i ;
wire [C_AXI_ADDR_WIDTH-1:0] wr_cmd_si_addr;
wire [8-1:0] wr_cmd_si_len;
wire [3-1:0] wr_cmd_si_size;
wire [2-1:0] wr_cmd_si_burst;
// Write Channel Signals for Commands Queue Interface.
wire wr_cmd_valid;
wire wr_cmd_fix;
wire wr_cmd_modified;
wire wr_cmd_complete_wrap;
wire wr_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] wr_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] wr_cmd_step;
wire [8-1:0] wr_cmd_length;
wire wr_cmd_ready;
wire wr_cmd_id_ready;
wire [C_S_AXI_ID_WIDTH-1:0] wr_cmd_id;
wire wpush;
wire wpop;
reg [C_FIFO_DEPTH_LOG-1:0] wcnt;
// Write Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AW_REGISTER),
.C_AXI_CHANNEL (0),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (C_SUPPORTS_ID),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) write_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
.cmd_id (wr_cmd_id),
.cmd_id_ready (wr_cmd_id_ready),
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_id (),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_awid),
.S_AXI_AADDR (sr_awaddr),
.S_AXI_ALEN (sr_awlen),
.S_AXI_ASIZE (sr_awsize),
.S_AXI_ABURST (sr_awburst),
.S_AXI_ALOCK (sr_awlock),
.S_AXI_ACACHE (sr_awcache),
.S_AXI_APROT (sr_awprot),
.S_AXI_AREGION (sr_awregion),
.S_AXI_AQOS (sr_awqos),
.S_AXI_AVALID (sr_awvalid),
.S_AXI_AREADY (sr_awready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_awaddr_i ),
.M_AXI_ALEN (m_axi_awlen_i ),
.M_AXI_ASIZE (m_axi_awsize_i ),
.M_AXI_ABURST (m_axi_awburst_i ),
.M_AXI_ALOCK (m_axi_awlock_i ),
.M_AXI_ACACHE (m_axi_awcache_i ),
.M_AXI_APROT (m_axi_awprot_i ),
.M_AXI_AREGION (m_axi_awregion_i ),
.M_AXI_AQOS (m_axi_awqos_i ),
.M_AXI_AVALID (m_axi_awvalid_i ),
.M_AXI_AREADY (m_axi_awready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_w_upsizer
// Packet FIFO Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_write_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (wr_cmd_si_addr ),
.cmd_si_len (wr_cmd_si_len ),
.cmd_si_size (wr_cmd_si_size ),
.cmd_si_burst (wr_cmd_si_burst),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_AWADDR (m_axi_awaddr_i ),
.S_AXI_AWLEN (m_axi_awlen_i ),
.S_AXI_AWSIZE (m_axi_awsize_i ),
.S_AXI_AWBURST (m_axi_awburst_i ),
.S_AXI_AWLOCK (m_axi_awlock_i ),
.S_AXI_AWCACHE (m_axi_awcache_i ),
.S_AXI_AWPROT (m_axi_awprot_i ),
.S_AXI_AWREGION (m_axi_awregion_i ),
.S_AXI_AWQOS (m_axi_awqos_i ),
.S_AXI_AWVALID (m_axi_awvalid_i ),
.S_AXI_AWREADY (m_axi_awready_i ),
// Master Interface Write Address Port
.M_AXI_AWADDR (m_axi_awaddr),
.M_AXI_AWLEN (m_axi_awlen),
.M_AXI_AWSIZE (m_axi_awsize),
.M_AXI_AWBURST (m_axi_awburst),
.M_AXI_AWLOCK (m_axi_awlock),
.M_AXI_AWCACHE (m_axi_awcache),
.M_AXI_AWPROT (m_axi_awprot),
.M_AXI_AWREGION (m_axi_awregion),
.M_AXI_AWQOS (m_axi_awqos),
.M_AXI_AWVALID (m_axi_awvalid),
.M_AXI_AWREADY (m_axi_awready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_w_upsizer
// Write Data channel.
axi_dwidth_converter_v2_1_w_upsizer #
(
.C_FAMILY ("rtl"),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) write_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (wr_cmd_valid),
.cmd_fix (wr_cmd_fix),
.cmd_modified (wr_cmd_modified),
.cmd_complete_wrap (wr_cmd_complete_wrap),
.cmd_packed_wrap (wr_cmd_packed_wrap),
.cmd_first_word (wr_cmd_first_word),
.cmd_next_word (wr_cmd_next_word),
.cmd_last_word (wr_cmd_last_word),
.cmd_offset (wr_cmd_offset),
.cmd_mask (wr_cmd_mask),
.cmd_step (wr_cmd_step),
.cmd_length (wr_cmd_length),
.cmd_ready (wr_cmd_ready),
// Slave Interface Write Data Ports
.S_AXI_WDATA (s_axi_wdata),
.S_AXI_WSTRB (s_axi_wstrb),
.S_AXI_WLAST (s_axi_wlast),
.S_AXI_WVALID (s_axi_wvalid),
.S_AXI_WREADY (s_axi_wready),
// Master Interface Write Data Ports
.M_AXI_WDATA (m_axi_wdata),
.M_AXI_WSTRB (m_axi_wstrb),
.M_AXI_WLAST (m_axi_wlast),
.M_AXI_WVALID (m_axi_wvalid),
.M_AXI_WREADY (m_axi_wready)
);
assign m_axi_awaddr = m_axi_awaddr_i ;
assign m_axi_awlen = m_axi_awlen_i ;
assign m_axi_awsize = m_axi_awsize_i ;
assign m_axi_awburst = m_axi_awburst_i ;
assign m_axi_awlock = m_axi_awlock_i ;
assign m_axi_awcache = m_axi_awcache_i ;
assign m_axi_awprot = m_axi_awprot_i ;
assign m_axi_awregion = m_axi_awregion_i ;
assign m_axi_awqos = m_axi_awqos_i ;
assign m_axi_awvalid = m_axi_awvalid_i ;
assign m_axi_awready_i = m_axi_awready ;
end // gen_w_upsizer
// Write Response channel.
assign wr_cmd_id_ready = s_axi_bvalid_i & s_axi_bready;
assign s_axi_bid = wr_cmd_id;
assign s_axi_bresp = s_axi_bresp_i;
assign s_axi_bvalid = s_axi_bvalid_i;
if (P_CLK_CONV) begin : gen_b_clk_conv
if (C_AXI_IS_ACLK_ASYNC == 0) begin : gen_b_sync_conv
axi_clock_converter_v2_1_axic_sync_clock_converter #(
.C_FAMILY ( C_FAMILY ) ,
.C_PAYLOAD_WIDTH ( 2 ) ,
.C_M_ACLK_RATIO ( P_SI_LT_MI ? 1 : P_ACLK_RATIO ) ,
.C_S_ACLK_RATIO ( P_SI_LT_MI ? P_ACLK_RATIO : 1 ) ,
.C_MODE(P_CONV_LIGHT_WT)
)
b_sync_clock_converter (
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early),
.S_ACLK ( m_axi_aclk ) ,
.S_ARESETN ( m_axi_aresetn ) ,
.S_PAYLOAD ( m_axi_bresp ) ,
.S_VALID ( m_axi_bvalid ) ,
.S_READY ( m_axi_bready ) ,
.M_ACLK ( s_axi_aclk ) ,
.M_ARESETN ( s_axi_aresetn ) ,
.M_PAYLOAD ( s_axi_bresp_i ) ,
.M_VALID ( s_axi_bvalid_i ) ,
.M_READY ( s_axi_bready )
);
end else begin : gen_b_async_conv
fifo_generator_v12_0 #(
.C_COMMON_CLOCK(0),
.C_SYNCHRONIZER_STAGE(C_SYNCHRONIZER_STAGE),
.C_INTERFACE_TYPE(2),
.C_AXI_TYPE(1),
.C_HAS_AXI_ID(1),
.C_AXI_LEN_WIDTH(8),
.C_AXI_LOCK_WIDTH(2),
.C_DIN_WIDTH_WACH(63),
.C_DIN_WIDTH_WDCH(38),
.C_DIN_WIDTH_WRCH(3),
.C_DIN_WIDTH_RACH(63),
.C_DIN_WIDTH_RDCH(36),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(18),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(18),
.C_ENABLE_RLOCS(0),
.C_FAMILY(C_FAMILY),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_INT_CLK(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_INIT_WR_PNTR_VAL(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(1),
.C_PRELOAD_REGS(0),
.C_PRIM_FIFO_TYPE("4kx4"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(2),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(3),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(1022),
.C_PROG_FULL_THRESH_NEGATE_VAL(1021),
.C_PROG_FULL_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(10),
.C_RD_DEPTH(1024),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(10),
.C_UNDERFLOW_LOW(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_RESPONSE_LATENCY(1),
.C_MSGON_VAL(1),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_HAS_AXI_WR_CHANNEL(1),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_MASTER_CE(0),
.C_ADD_NGC_CONSTRAINT(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_AXI_ID_WIDTH(1),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_DATA_WIDTH(32),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_RUSER(0),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_WUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_RUSER_WIDTH(1),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TKEEP(0),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TKEEP_WIDTH(4),
.C_WACH_TYPE(2),
.C_WDCH_TYPE(2),
.C_WRCH_TYPE(0),
.C_RACH_TYPE(0),
.C_RDCH_TYPE(0),
.C_AXIS_TYPE(0),
.C_IMPLEMENTATION_TYPE_WACH(12),
.C_IMPLEMENTATION_TYPE_WDCH(11),
.C_IMPLEMENTATION_TYPE_WRCH(12),
.C_IMPLEMENTATION_TYPE_RACH(12),
.C_IMPLEMENTATION_TYPE_RDCH(11),
.C_IMPLEMENTATION_TYPE_AXIS(11),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_AXIS(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_DIN_WIDTH_AXIS(1),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(32),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(5),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(31),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(29),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(13),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1021),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1021),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_AXIS(0)
) dw_fifogen_b_async (
.m_aclk(m_axi_aclk),
.s_aclk(s_axi_aclk),
.s_aresetn(sm_aresetn),
.s_axi_awid(1'b0),
.s_axi_awaddr(32'b0),
.s_axi_awlen(8'b0),
.s_axi_awsize(3'b0),
.s_axi_awburst(2'b0),
.s_axi_awlock(2'b0),
.s_axi_awcache(4'b0),
.s_axi_awprot(3'b0),
.s_axi_awqos(4'b0),
.s_axi_awregion(4'b0),
.s_axi_awuser(1'b0),
.s_axi_awvalid(1'b0),
.s_axi_awready(),
.s_axi_wid(1'b0),
.s_axi_wdata(32'b0),
.s_axi_wstrb(4'b0),
.s_axi_wlast(1'b0),
.s_axi_wuser(1'b0),
.s_axi_wvalid(1'b0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(s_axi_bresp_i),
.s_axi_buser(),
.s_axi_bvalid(s_axi_bvalid_i),
.s_axi_bready(s_axi_bready),
.m_axi_awid(),
.m_axi_awaddr(),
.m_axi_awlen(),
.m_axi_awsize(),
.m_axi_awburst(),
.m_axi_awlock(),
.m_axi_awcache(),
.m_axi_awprot(),
.m_axi_awqos(),
.m_axi_awregion(),
.m_axi_awuser(),
.m_axi_awvalid(),
.m_axi_awready(1'b0),
.m_axi_wid(),
.m_axi_wdata(),
.m_axi_wstrb(),
.m_axi_wlast(),
.m_axi_wuser(),
.m_axi_wvalid(),
.m_axi_wready(1'b0),
.m_axi_bid(1'b0),
.m_axi_bresp(m_axi_bresp),
.m_axi_buser(1'b0),
.m_axi_bvalid(m_axi_bvalid),
.m_axi_bready(m_axi_bready),
.s_axi_arid(1'b0),
.s_axi_araddr(32'b0),
.s_axi_arlen(8'b0),
.s_axi_arsize(3'b0),
.s_axi_arburst(2'b0),
.s_axi_arlock(2'b0),
.s_axi_arcache(4'b0),
.s_axi_arprot(3'b0),
.s_axi_arqos(4'b0),
.s_axi_arregion(4'b0),
.s_axi_aruser(1'b0),
.s_axi_arvalid(1'b0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_ruser(),
.s_axi_rvalid(),
.s_axi_rready(1'b0),
.m_axi_arid(),
.m_axi_araddr(),
.m_axi_arlen(),
.m_axi_arsize(),
.m_axi_arburst(),
.m_axi_arlock(),
.m_axi_arcache(),
.m_axi_arprot(),
.m_axi_arqos(),
.m_axi_arregion(),
.m_axi_aruser(),
.m_axi_arvalid(),
.m_axi_arready(1'b0),
.m_axi_rid(1'b0),
.m_axi_rdata(32'b0),
.m_axi_rresp(2'b0),
.m_axi_rlast(1'b0),
.m_axi_ruser(1'b0),
.m_axi_rvalid(1'b0),
.m_axi_rready(),
.m_aclk_en(1'b0),
.s_aclk_en(1'b0),
.backup(1'b0),
.backup_marker(1'b0),
.clk(1'b0),
.rst(1'b0),
.srst(1'b0),
.wr_clk(1'b0),
.wr_rst(1'b0),
.rd_clk(1'b0),
.rd_rst(1'b0),
.din(18'b0),
.wr_en(1'b0),
.rd_en(1'b0),
.prog_empty_thresh(10'b0),
.prog_empty_thresh_assert(10'b0),
.prog_empty_thresh_negate(10'b0),
.prog_full_thresh(10'b0),
.prog_full_thresh_assert(10'b0),
.prog_full_thresh_negate(10'b0),
.int_clk(1'b0),
.injectdbiterr(1'b0),
.injectsbiterr(1'b0),
.dout(),
.full(),
.almost_full(),
.wr_ack(),
.overflow(),
.empty(),
.almost_empty(),
.valid(),
.underflow(),
.data_count(),
.rd_data_count(),
.wr_data_count(),
.prog_full(),
.prog_empty(),
.sbiterr(),
.dbiterr(),
.s_axis_tvalid(1'b0),
.s_axis_tready(),
.s_axis_tdata(64'b0),
.s_axis_tstrb(4'b0),
.s_axis_tkeep(4'b0),
.s_axis_tlast(1'b0),
.s_axis_tid(8'b0),
.s_axis_tdest(4'b0),
.s_axis_tuser(4'b0),
.m_axis_tvalid(),
.m_axis_tready(1'b0),
.m_axis_tdata(),
.m_axis_tstrb(),
.m_axis_tkeep(),
.m_axis_tlast(),
.m_axis_tid(),
.m_axis_tdest(),
.m_axis_tuser(),
.axi_aw_injectsbiterr(1'b0),
.axi_aw_injectdbiterr(1'b0),
.axi_aw_prog_full_thresh(4'b0),
.axi_aw_prog_empty_thresh(4'b0),
.axi_aw_data_count(),
.axi_aw_wr_data_count(),
.axi_aw_rd_data_count(),
.axi_aw_sbiterr(),
.axi_aw_dbiterr(),
.axi_aw_overflow(),
.axi_aw_underflow(),
.axi_aw_prog_full(),
.axi_aw_prog_empty(),
.axi_w_injectsbiterr(1'b0),
.axi_w_injectdbiterr(1'b0),
.axi_w_prog_full_thresh(10'b0),
.axi_w_prog_empty_thresh(10'b0),
.axi_w_data_count(),
.axi_w_wr_data_count(),
.axi_w_rd_data_count(),
.axi_w_sbiterr(),
.axi_w_dbiterr(),
.axi_w_overflow(),
.axi_w_underflow(),
.axi_b_injectsbiterr(1'b0),
.axi_w_prog_full(),
.axi_w_prog_empty(),
.axi_b_injectdbiterr(1'b0),
.axi_b_prog_full_thresh(5'b0),
.axi_b_prog_empty_thresh(5'b0),
.axi_b_data_count(),
.axi_b_wr_data_count(),
.axi_b_rd_data_count(),
.axi_b_sbiterr(),
.axi_b_dbiterr(),
.axi_b_overflow(),
.axi_b_underflow(),
.axi_ar_injectsbiterr(1'b0),
.axi_b_prog_full(),
.axi_b_prog_empty(),
.axi_ar_injectdbiterr(1'b0),
.axi_ar_prog_full_thresh(4'b0),
.axi_ar_prog_empty_thresh(4'b0),
.axi_ar_data_count(),
.axi_ar_wr_data_count(),
.axi_ar_rd_data_count(),
.axi_ar_sbiterr(),
.axi_ar_dbiterr(),
.axi_ar_overflow(),
.axi_ar_underflow(),
.axi_ar_prog_full(),
.axi_ar_prog_empty(),
.axi_r_injectsbiterr(1'b0),
.axi_r_injectdbiterr(1'b0),
.axi_r_prog_full_thresh(10'b0),
.axi_r_prog_empty_thresh(10'b0),
.axi_r_data_count(),
.axi_r_wr_data_count(),
.axi_r_rd_data_count(),
.axi_r_sbiterr(),
.axi_r_dbiterr(),
.axi_r_overflow(),
.axi_r_underflow(),
.axis_injectsbiterr(1'b0),
.axi_r_prog_full(),
.axi_r_prog_empty(),
.axis_injectdbiterr(1'b0),
.axis_prog_full_thresh(10'b0),
.axis_prog_empty_thresh(10'b0),
.axis_data_count(),
.axis_wr_data_count(),
.axis_rd_data_count(),
.axis_sbiterr(),
.axis_dbiterr(),
.axis_overflow(),
.axis_underflow(),
.axis_prog_full(),
.axis_prog_empty(),
.wr_rst_busy(),
.rd_rst_busy(),
.sleep(1'b0)
);
end
end else begin : gen_b_passthru
assign m_axi_bready = s_axi_bready;
assign s_axi_bresp_i = m_axi_bresp;
assign s_axi_bvalid_i = m_axi_bvalid;
end // gen_b
end else begin : NO_WRITE
assign sr_awready = 1'b0;
assign s_axi_wready = 1'b0;
assign s_axi_bid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_bresp = 2'b0;
assign s_axi_bvalid = 1'b0;
assign m_axi_awaddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_awlen = 8'b0;
assign m_axi_awsize = 3'b0;
assign m_axi_awburst = 2'b0;
assign m_axi_awlock = 2'b0;
assign m_axi_awcache = 4'b0;
assign m_axi_awprot = 3'b0;
assign m_axi_awregion = 4'b0;
assign m_axi_awqos = 4'b0;
assign m_axi_awvalid = 1'b0;
assign m_axi_wdata = {C_M_AXI_DATA_WIDTH{1'b0}};
assign m_axi_wstrb = {C_M_AXI_DATA_WIDTH/8{1'b0}};
assign m_axi_wlast = 1'b0;
assign m_axi_wvalid = 1'b0;
assign m_axi_bready = 1'b0;
end
endgenerate
/////////////////////////////////////////////////////////////////////////////
// Handle Read Channels (AR/R)
/////////////////////////////////////////////////////////////////////////////
generate
if (C_AXI_SUPPORTS_READ == 1) begin : USE_READ
wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr_i ;
wire [8-1:0] m_axi_arlen_i ;
wire [3-1:0] m_axi_arsize_i ;
wire [2-1:0] m_axi_arburst_i ;
wire [2-1:0] m_axi_arlock_i ;
wire [4-1:0] m_axi_arcache_i ;
wire [3-1:0] m_axi_arprot_i ;
wire [4-1:0] m_axi_arregion_i ;
wire [4-1:0] m_axi_arqos_i ;
wire m_axi_arvalid_i ;
wire m_axi_arready_i ;
// Read Channel Signals for Commands Queue Interface.
wire rd_cmd_valid;
wire rd_cmd_fix;
wire rd_cmd_modified;
wire rd_cmd_complete_wrap;
wire rd_cmd_packed_wrap;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_first_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_next_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_last_word;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_offset;
wire [C_M_AXI_BYTES_LOG-1:0] rd_cmd_mask;
wire [C_S_AXI_BYTES_LOG:0] rd_cmd_step;
wire [8-1:0] rd_cmd_length;
wire rd_cmd_ready;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_id;
wire [C_AXI_ADDR_WIDTH-1:0] rd_cmd_si_addr;
wire [C_S_AXI_ID_WIDTH-1:0] rd_cmd_si_id;
wire [8-1:0] rd_cmd_si_len;
wire [3-1:0] rd_cmd_si_size;
wire [2-1:0] rd_cmd_si_burst;
// Read Address Channel.
axi_dwidth_converter_v2_1_a_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_PROTOCOL (C_AXI_PROTOCOL),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_SUPPORTS_ID (C_SUPPORTS_ID),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_M_AXI_REGISTER (C_M_AXI_AR_REGISTER),
.C_AXI_CHANNEL (1),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
// .C_FIFO_MODE (0),
.C_FIFO_MODE (C_FIFO_MODE),
.C_ID_QUEUE (P_RID_QUEUE),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG)
) read_addr_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
// Slave Interface Write Address Ports
.S_AXI_AID (sr_arid),
.S_AXI_AADDR (sr_araddr),
.S_AXI_ALEN (sr_arlen),
.S_AXI_ASIZE (sr_arsize),
.S_AXI_ABURST (sr_arburst),
.S_AXI_ALOCK (sr_arlock),
.S_AXI_ACACHE (sr_arcache),
.S_AXI_APROT (sr_arprot),
.S_AXI_AREGION (sr_arregion),
.S_AXI_AQOS (sr_arqos),
.S_AXI_AVALID (sr_arvalid),
.S_AXI_AREADY (sr_arready),
// Master Interface Write Address Port
.M_AXI_AADDR (m_axi_araddr_i ),
.M_AXI_ALEN (m_axi_arlen_i ),
.M_AXI_ASIZE (m_axi_arsize_i ),
.M_AXI_ABURST (m_axi_arburst_i ),
.M_AXI_ALOCK (m_axi_arlock_i ),
.M_AXI_ACACHE (m_axi_arcache_i ),
.M_AXI_APROT (m_axi_arprot_i ),
.M_AXI_AREGION (m_axi_arregion_i ),
.M_AXI_AQOS (m_axi_arqos_i ),
.M_AXI_AVALID (m_axi_arvalid_i ),
.M_AXI_AREADY (m_axi_arready_i )
);
if ((C_FIFO_MODE == P_PKTFIFO) || (C_FIFO_MODE == P_PKTFIFO_CLK)) begin : gen_pktfifo_r_upsizer
// Packet FIFO Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer_pktfifo #
(
.C_FAMILY (C_FAMILY),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG),
.C_CLK_CONV (P_CLK_CONV),
.C_S_AXI_ACLK_RATIO (C_S_AXI_ACLK_RATIO),
.C_M_AXI_ACLK_RATIO (C_M_AXI_ACLK_RATIO),
.C_AXI_IS_ACLK_ASYNC (C_AXI_IS_ACLK_ASYNC),
.C_SYNCHRONIZER_STAGE (C_SYNCHRONIZER_STAGE)
) pktfifo_read_data_inst
(
.S_AXI_ARESETN ( s_axi_aresetn ) ,
.S_AXI_ACLK ( s_axi_aclk ) ,
.M_AXI_ARESETN ( m_axi_aresetn ) ,
.M_AXI_ACLK ( m_axi_aclk ) ,
// Command Interface
.cmd_si_addr (rd_cmd_si_addr ),
.cmd_si_id (rd_cmd_si_id ),
.cmd_si_len (rd_cmd_si_len ),
.cmd_si_size (rd_cmd_si_size ),
.cmd_si_burst (rd_cmd_si_burst),
.cmd_ready (rd_cmd_ready),
// Slave Interface Write Address Ports
.S_AXI_ARADDR (m_axi_araddr_i ),
.S_AXI_ARLEN (m_axi_arlen_i ),
.S_AXI_ARSIZE (m_axi_arsize_i ),
.S_AXI_ARBURST (m_axi_arburst_i ),
.S_AXI_ARLOCK (m_axi_arlock_i ),
.S_AXI_ARCACHE (m_axi_arcache_i ),
.S_AXI_ARPROT (m_axi_arprot_i ),
.S_AXI_ARREGION (m_axi_arregion_i ),
.S_AXI_ARQOS (m_axi_arqos_i ),
.S_AXI_ARVALID (m_axi_arvalid_i ),
.S_AXI_ARREADY (m_axi_arready_i ),
// Master Interface Write Address Port
.M_AXI_ARADDR (m_axi_araddr),
.M_AXI_ARLEN (m_axi_arlen),
.M_AXI_ARSIZE (m_axi_arsize),
.M_AXI_ARBURST (m_axi_arburst),
.M_AXI_ARLOCK (m_axi_arlock),
.M_AXI_ARCACHE (m_axi_arcache),
.M_AXI_ARPROT (m_axi_arprot),
.M_AXI_ARREGION (m_axi_arregion),
.M_AXI_ARQOS (m_axi_arqos),
.M_AXI_ARVALID (m_axi_arvalid),
.M_AXI_ARREADY (m_axi_arready),
// Slave Interface Write Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Write Data Ports
.M_AXI_RDATA (m_axi_rdata),
.M_AXI_RRESP (m_axi_rresp),
.M_AXI_RLAST (m_axi_rlast),
.M_AXI_RVALID (m_axi_rvalid),
.M_AXI_RREADY (m_axi_rready),
.SAMPLE_CYCLE (sample_cycle),
.SAMPLE_CYCLE_EARLY (sample_cycle_early)
);
end else begin : gen_non_fifo_r_upsizer
// Read Data channel.
axi_dwidth_converter_v2_1_r_upsizer #
(
.C_FAMILY ("rtl"),
.C_AXI_ID_WIDTH (C_S_AXI_ID_WIDTH),
.C_S_AXI_DATA_WIDTH (C_S_AXI_DATA_WIDTH),
.C_M_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_S_AXI_REGISTER (C_S_AXI_R_REGISTER),
.C_PACKING_LEVEL (C_PACKING_LEVEL),
.C_S_AXI_BYTES_LOG (C_S_AXI_BYTES_LOG),
.C_M_AXI_BYTES_LOG (C_M_AXI_BYTES_LOG),
.C_RATIO (C_RATIO),
.C_RATIO_LOG (C_RATIO_LOG)
) read_data_inst
(
// Global Signals
.ARESET (~s_aresetn_i),
.ACLK (aclk),
// Command Interface
.cmd_valid (rd_cmd_valid),
.cmd_fix (rd_cmd_fix),
.cmd_modified (rd_cmd_modified),
.cmd_complete_wrap (rd_cmd_complete_wrap),
.cmd_packed_wrap (rd_cmd_packed_wrap),
.cmd_first_word (rd_cmd_first_word),
.cmd_next_word (rd_cmd_next_word),
.cmd_last_word (rd_cmd_last_word),
.cmd_offset (rd_cmd_offset),
.cmd_mask (rd_cmd_mask),
.cmd_step (rd_cmd_step),
.cmd_length (rd_cmd_length),
.cmd_ready (rd_cmd_ready),
.cmd_id (rd_cmd_id),
// Slave Interface Read Data Ports
.S_AXI_RID (s_axi_rid),
.S_AXI_RDATA (s_axi_rdata),
.S_AXI_RRESP (s_axi_rresp),
.S_AXI_RLAST (s_axi_rlast),
.S_AXI_RVALID (s_axi_rvalid),
.S_AXI_RREADY (s_axi_rready),
// Master Interface Read Data Ports
.M_AXI_RDATA (mr_rdata),
.M_AXI_RRESP (mr_rresp),
.M_AXI_RLAST (mr_rlast),
.M_AXI_RVALID (mr_rvalid),
.M_AXI_RREADY (mr_rready)
);
axi_register_slice_v2_1_axi_register_slice #
(
.C_FAMILY (C_FAMILY),
.C_AXI_PROTOCOL (0),
.C_AXI_ID_WIDTH (1),
.C_AXI_ADDR_WIDTH (C_AXI_ADDR_WIDTH),
.C_AXI_DATA_WIDTH (C_M_AXI_DATA_WIDTH),
.C_AXI_SUPPORTS_USER_SIGNALS (0),
.C_REG_CONFIG_R (C_M_AXI_R_REGISTER)
)
mi_register_slice_inst
(
.aresetn (s_aresetn_i),
.aclk (m_aclk),
.s_axi_awid ( 1'b0 ),
.s_axi_awaddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_awlen ( 8'b0 ),
.s_axi_awsize ( 3'b0 ),
.s_axi_awburst ( 2'b0 ),
.s_axi_awlock ( 1'b0 ),
.s_axi_awcache ( 4'b0 ),
.s_axi_awprot ( 3'b0 ),
.s_axi_awregion ( 4'b0 ),
.s_axi_awqos ( 4'b0 ),
.s_axi_awuser ( 1'b0 ),
.s_axi_awvalid ( 1'b0 ),
.s_axi_awready ( ),
.s_axi_wid ( 1'b0 ),
.s_axi_wdata ( {C_M_AXI_DATA_WIDTH{1'b0}} ),
.s_axi_wstrb ( {C_M_AXI_DATA_WIDTH/8{1'b0}} ),
.s_axi_wlast ( 1'b0 ),
.s_axi_wuser ( 1'b0 ),
.s_axi_wvalid ( 1'b0 ),
.s_axi_wready ( ),
.s_axi_bid ( ),
.s_axi_bresp ( ),
.s_axi_buser ( ),
.s_axi_bvalid ( ),
.s_axi_bready ( 1'b0 ),
.s_axi_arid ( 1'b0 ),
.s_axi_araddr ( {C_AXI_ADDR_WIDTH{1'b0}} ),
.s_axi_arlen ( 8'b0 ),
.s_axi_arsize ( 3'b0 ),
.s_axi_arburst ( 2'b0 ),
.s_axi_arlock ( 1'b0 ),
.s_axi_arcache ( 4'b0 ),
.s_axi_arprot ( 3'b0 ),
.s_axi_arregion ( 4'b0 ),
.s_axi_arqos ( 4'b0 ),
.s_axi_aruser ( 1'b0 ),
.s_axi_arvalid ( 1'b0 ),
.s_axi_arready ( ),
.s_axi_rid (),
.s_axi_rdata (mr_rdata ),
.s_axi_rresp (mr_rresp ),
.s_axi_rlast (mr_rlast ),
.s_axi_ruser (),
.s_axi_rvalid (mr_rvalid ),
.s_axi_rready (mr_rready ),
.m_axi_awid (),
.m_axi_awaddr (),
.m_axi_awlen (),
.m_axi_awsize (),
.m_axi_awburst (),
.m_axi_awlock (),
.m_axi_awcache (),
.m_axi_awprot (),
.m_axi_awregion (),
.m_axi_awqos (),
.m_axi_awuser (),
.m_axi_awvalid (),
.m_axi_awready (1'b0),
.m_axi_wid () ,
.m_axi_wdata (),
.m_axi_wstrb (),
.m_axi_wlast (),
.m_axi_wuser (),
.m_axi_wvalid (),
.m_axi_wready (1'b0),
.m_axi_bid ( 1'b0 ) ,
.m_axi_bresp ( 2'b0 ) ,
.m_axi_buser ( 1'b0 ) ,
.m_axi_bvalid ( 1'b0 ) ,
.m_axi_bready ( ) ,
.m_axi_arid (),
.m_axi_araddr (),
.m_axi_arlen (),
.m_axi_arsize (),
.m_axi_arburst (),
.m_axi_arlock (),
.m_axi_arcache (),
.m_axi_arprot (),
.m_axi_arregion (),
.m_axi_arqos (),
.m_axi_aruser (),
.m_axi_arvalid (),
.m_axi_arready (1'b0),
.m_axi_rid (1'b0 ),
.m_axi_rdata (m_axi_rdata ),
.m_axi_rresp (m_axi_rresp ),
.m_axi_rlast (m_axi_rlast ),
.m_axi_ruser (1'b0 ),
.m_axi_rvalid (m_axi_rvalid ),
.m_axi_rready (m_axi_rready_i )
);
assign m_axi_araddr = m_axi_araddr_i ;
assign m_axi_arlen = m_axi_arlen_i ;
assign m_axi_arsize = m_axi_arsize_i ;
assign m_axi_arburst = m_axi_arburst_i ;
assign m_axi_arlock = m_axi_arlock_i ;
assign m_axi_arcache = m_axi_arcache_i ;
assign m_axi_arprot = m_axi_arprot_i ;
assign m_axi_arregion = m_axi_arregion_i ;
assign m_axi_arqos = m_axi_arqos_i ;
assign m_axi_arvalid = m_axi_arvalid_i ;
assign m_axi_arready_i = m_axi_arready ;
assign m_axi_rready = m_axi_rready_i;
end // gen_r_upsizer
end else begin : NO_READ
assign sr_arready = 1'b0;
assign s_axi_rid = {C_S_AXI_ID_WIDTH{1'b0}};
assign s_axi_rdata = {C_S_AXI_DATA_WIDTH{1'b0}};
assign s_axi_rresp = 2'b0;
assign s_axi_rlast = 1'b0;
assign s_axi_rvalid = 1'b0;
assign m_axi_araddr = {C_AXI_ADDR_WIDTH{1'b0}};
assign m_axi_arlen = 8'b0;
assign m_axi_arsize = 3'b0;
assign m_axi_arburst = 2'b0;
assign m_axi_arlock = 2'b0;
assign m_axi_arcache = 4'b0;
assign m_axi_arprot = 3'b0;
assign m_axi_arregion = 4'b0;
assign m_axi_arqos = 4'b0;
assign m_axi_arvalid = 1'b0;
assign mr_rready = 1'b0;
end
endgenerate
endmodule
`default_nettype wire
|
/***********************************************************************
Single Port RAM that maps to a Xilinx/Lattice BRAM
This file is part FPGA Libre project http://fpgalibre.sf.net/
Description:
This is a program memory for the AVR. It maps to a Xilinx/Lattice
BRAM.
This version can be modified by the CPU (i. e. SPM instruction)
To Do:
-
Author:
- Salvador E. Tropea, salvador inti.gob.ar
------------------------------------------------------------------------------
Copyright (c) 2008-2017 Salvador E. Tropea <salvador inti.gob.ar>
Copyright (c) 2008-2017 Instituto Nacional de Tecnología Industrial
Distributed under the BSD license
------------------------------------------------------------------------------
Design unit: SinglePortPM(Xilinx) (Entity and architecture)
File name: pm_s_rw.in.v (template used)
Note: None
Limitations: None known
Errors: None known
Library: work
Dependencies: IEEE.std_logic_1164
Target FPGA: Spartan 3 (XC3S1500-4-FG456)
iCE40 (iCE40HX4K)
Language: Verilog
Wishbone: No
Synthesis tools: Xilinx Release 9.2.03i - xst J.39
iCEcube2.2016.02
Simulation tools: GHDL [Sokcho edition] (0.2x)
Text editor: SETEdit 0.5.x
***********************************************************************/
module lattuino_1_blPM_2
#(
parameter WORD_SIZE=16,// Word Size
parameter FALL_EDGE=0, // Ram clock falling edge
parameter ADDR_W=13 // Address Width
)
(
input clk_i,
input [ADDR_W-1:0] addr_i,
output [WORD_SIZE-1:0] data_o,
input we_i,
input [WORD_SIZE-1:0] data_i
);
localparam ROM_SIZE=2**ADDR_W;
reg [ADDR_W-1:0] addr_r;
reg [WORD_SIZE-1:0] rom[0:ROM_SIZE-1];
initial begin
$readmemh("../../../Work/lattuino_1_bl_2_v.dat",rom,696);
end
generate
if (!FALL_EDGE)
begin : use_rising_edge
always @(posedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_rising_edge
else
begin : use_falling_edge
always @(negedge clk_i)
begin : do_rom
addr_r <= addr_i;
if (we_i)
rom[addr_i] <= data_i;
end // do_rom
end // use_falling_edge
endgenerate
assign data_o=rom[addr_r];
endmodule // lattuino_1_blPM_2
|
/////////////////////////////
//LAB01 29/05 - Atividade 1//
/////////////////////////////
module Mod_Teste(
input CLOCK_27,
input CLOCK_50,
input [3:0] KEY,
input [17:0] SW,
output [6:0] HEX0,
output [6:0] HEX1,
output [6:0] HEX2,
output [6:0] HEX3,
output [6:0] HEX4,
output [6:0] HEX5,
output [6:0] HEX6,
output [6:0] HEX7,
output [8:0] LEDG,
output [17:0] LEDR,
output LCD_ON, // LCD Power ON/OFF
output LCD_BLON, // LCD Back Light ON/OFF
output LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read
output LCD_EN, // LCD Enable
output LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data
inout [7:0] LCD_DATA, // LCD Data bus 8 bits
//////////////////////// GPIO ////////////////////////////////
inout [35:0] GPIO_0, // GPIO Connection 0
inout [35:0] GPIO_1
);
assign GPIO_1 = 36'hzzzzzzzzz;
assign GPIO_0 = 36'hzzzzzzzzz;
// LCD
assign LCD_ON = 1'b1;
assign LCD_BLON = 1'b1;
LCD_TEST LCD0 (
// Host Side
.iCLK ( CLOCK_50 ),
.iRST_N ( KEY[0] ),
// Data to display
.d0(CONST_bus), // 4 dígitos canto superior esquerdo
.d1(), // 4 dígitos superior meio
.d2(CONST_bus), // 4 dígitos canto superior direito
.d3(ADDR_bus), // 4 dígitos canto inferior esquerdo
.d4(DATA_bus), // 4 dígitos inferior meio
.d5(D_bus_internal), // 4 dígitos canto inferior direito
// LCD Side
.LCD_DATA( LCD_DATA ),
.LCD_RW( LCD_RW ),
.LCD_EN( LCD_EN ),
.LCD_RS( LCD_RS )
);
parameter WORD_WIDTH = 16;
parameter DR_WIDTH = 3;
parameter OPCODE_WIDTH = 7;
parameter INSTR_WIDTH = WORD_WIDTH;
parameter CNTRL_WIDTH = 3*DR_WIDTH+11;
wire RST_key = KEY[0];
wire CLK_key = KEY[3];
//reg RST_key;
//reg CLK_key;
wire [WORD_WIDTH-1:0] ADDR_bus, DATA_bus, DATA_in_bus, CONST_bus, PC_out, INSTRM_out, D_bus_internal;
wire [CNTRL_WIDTH-1:0] CNTRL_bus;
wire [3:0] FLAG_bus;
assign DATA_in_bus = SW[17:3];
assign LEDR = VIEWER_MUX_OUT[19:2];
assign LEDG = VIEWER_MUX_OUT[1:0];
ControlUnit CU0(
.CNTRL_out(CNTRL_bus),
.CONST_out(CONST_bus),
.PC_out(PC_out),
.INSTRM_in(INSTRM_out),
.INSTR_in(ADDR_bus),
.FLAG_in(FLAG_bus),
.RST_in(RST_key),
.CLK_in(CLK_key)
);
defparam CU0.WORD_WIDTH = WORD_WIDTH;
defparam CU0.DR_WIDTH = DR_WIDTH;
InstructionMemory IM0(
.INSTR_in(PC_out),
.INSTR_out(INSTRM_out)
);
defparam IM0.WORD_WIDTH = WORD_WIDTH;
defparam IM0.DR_WIDTH = DR_WIDTH;
Datapath DP0(
.FLAG_out(FLAG_bus),
.A_bus(ADDR_bus),
.D_bus(DATA_bus),
.D_bus_internal(D_bus_internal),
.D_in(DATA_in_bus),
.CNTRL_in(CNTRL_bus),
.CONST_in(CONST_bus),
.CLK(CLK_key)
);
defparam DP0.WORD_WIDTH = WORD_WIDTH;
defparam DP0.DR_WIDTH = DR_WIDTH;
/*
DataMemory DM0(
.Data_out(DATA_in_bus),
.Addr_in(ADDR_bus),
.Data_in(DATA_bus),
.CNTRL_in(CNTRL_bus)
);
*/
wire [3:0] VIEWER_MUX_OUT0;
wire [3:0] VIEWER_MUX_OUT1;
wire [3:0] VIEWER_MUX_OUT2;
wire [3:0] VIEWER_MUX_OUT3;
wire [3:0] VIEWER_MUX_OUT4;
reg [CNTRL_WIDTH-1:0] VIEWER_MUX_OUT;
assign VIEWER_MUX_OUT4 = VIEWER_MUX_OUT[19:16];
assign VIEWER_MUX_OUT3 = VIEWER_MUX_OUT[15:12];
assign VIEWER_MUX_OUT2 = VIEWER_MUX_OUT[11:8];
assign VIEWER_MUX_OUT1 = VIEWER_MUX_OUT[7:4];
assign VIEWER_MUX_OUT0 = VIEWER_MUX_OUT[3:0];
Decoder_Binary2HexSevenSegments B2H7S0(
.out(HEX0),
.in(VIEWER_MUX_OUT0)
);
Decoder_Binary2HexSevenSegments B2H7S1(
.out(HEX1),
.in(VIEWER_MUX_OUT1)
);
Decoder_Binary2HexSevenSegments B2H7S2(
.out(HEX2),
.in(VIEWER_MUX_OUT2)
);
Decoder_Binary2HexSevenSegments B2H7S3(
.out(HEX3),
.in(VIEWER_MUX_OUT3)
);
Decoder_Binary2HexSevenSegments B2H7S4(
.out(HEX4),
.in(VIEWER_MUX_OUT4)
);
/*
initial begin
CLK_key <= 0;
RST_key <= 1;
repeat (50) begin
#(5) CLK_key <= !CLK_key;
end
end
initial begin
#100 $finish;
end
*/
always@(SW[2:0], DATA_in_bus, D_bus_internal, ADDR_bus, DATA_bus, CNTRL_bus, PC_out, INSTRM_out) begin
case(SW[2:0])
3'b000: VIEWER_MUX_OUT = DATA_in_bus;
3'b001: VIEWER_MUX_OUT = D_bus_internal;
3'b010: VIEWER_MUX_OUT = ADDR_bus;
3'b011: VIEWER_MUX_OUT = DATA_bus;
3'b100: VIEWER_MUX_OUT = CNTRL_bus;
3'b101: VIEWER_MUX_OUT = PC_out;
3'b110: VIEWER_MUX_OUT = INSTRM_out;
//3'b111: VIEWER_MUX_OUT = INSTRM_out;
default: VIEWER_MUX_OUT = D_bus_internal;
endcase
end
endmodule |
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010 by Wilson Snyder.
//
// --------------------------------------------------------
// Bug Description:
//
// Issue: The gated clock gclk_vld[0] toggles but dvld[0]
// input to the flop does not propagate to the output
// signal entry_vld[0] correctly. The value that propagates
// is the new value of dvld[0] not the one just before the
// posedge of gclk_vld[0].
// --------------------------------------------------------
// Define to see the bug with test failing with gated clock 'gclk_vld'
// Comment out the define to see the test passing with ungated clock 'clk'
`define GATED_CLK_TESTCASE 1
// A side effect of the problem is this warning, disabled by default
//verilator lint_on IMPERFECTSCH
// Test Bench
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc=0;
reg [63:0] crc;
// Take CRC data and apply to testblock inputs
wire [7:0] dvld = crc[7:0];
wire [7:0] ff_en_e1 = crc[15:8];
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] entry_vld; // From test of Test.v
wire [7:0] ff_en_vld; // From test of Test.v
// End of automatics
Test test (/*AUTOINST*/
// Outputs
.ff_en_vld (ff_en_vld[7:0]),
.entry_vld (entry_vld[7:0]),
// Inputs
.clk (clk),
.dvld (dvld[7:0]),
.ff_en_e1 (ff_en_e1[7:0]));
reg err_code;
reg ffq_clk_active;
reg [7:0] prv_dvld;
initial begin
err_code = 0;
ffq_clk_active = 0;
end
always @ (posedge clk) begin
prv_dvld = test.dvld;
end
always @ (negedge test.ff_entry_dvld_0.clk) begin
ffq_clk_active = 1;
if (test.entry_vld[0] !== prv_dvld[0]) err_code = 1;
end
// Test loop
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d crc=%x ",$time, cyc, crc);
$display(" en=%b fen=%b d=%b ev=%b",
test.flop_en_vld[0], test.ff_en_vld[0],
test.dvld[0], test.entry_vld[0]);
`endif
cyc <= cyc + 1;
crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
if (cyc<3) begin
crc <= 64'h5aef0c8d_d70a4497;
end
else if (cyc==99) begin
$write("[%0t] cyc==%0d crc=%x\n",$time, cyc, crc);
if (ffq_clk_active == 0) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with no Clock arriving at FFQs");
$display ("----");
$stop;
end
else if (err_code) begin
$display ("----");
$display ("%%Error: TESTCASE FAILED with invalid propagation of 'd' to 'q' of FFQs");
$display ("----");
$stop;
end
else begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
module llq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
/* verilator lint_off COMBDLY */
always @(clk or d)
if (clk == 1'b0)
qr <= d;
/* verilator lint_on COMBDLY */
assign q = qr;
endmodule
module ffq (clk, d, q);
parameter WIDTH = 32;
input clk;
input [WIDTH-1:0] d;
output [WIDTH-1:0] q;
reg [WIDTH-1:0] qr;
always @(posedge clk)
qr <= d;
assign q = qr;
endmodule
// DUT module
module Test (/*AUTOARG*/
// Outputs
ff_en_vld, entry_vld,
// Inputs
clk, dvld, ff_en_e1
);
input clk;
input [7:0] dvld;
input [7:0] ff_en_e1;
output [7:0] ff_en_vld;
output wire [7:0] entry_vld;
wire [7:0] gclk_vld;
wire [7:0] ff_en_vld /*verilator clock_enable*/;
reg [7:0] flop_en_vld;
always @(posedge clk) flop_en_vld <= ff_en_e1;
// clock gating
`ifdef GATED_CLK_TESTCASE
assign gclk_vld = {8{clk}} & ff_en_vld;
`else
assign gclk_vld = {8{clk}};
`endif
// latch for avoiding glitch on the clock gating control
llq #(8) dp_ff_en_vld (.clk(clk), .d(flop_en_vld), .q(ff_en_vld));
// flops that use the gated clock signal
ffq #(1) ff_entry_dvld_0 (.clk(gclk_vld[0]), .d(dvld[0]), .q(entry_vld[0]));
ffq #(1) ff_entry_dvld_1 (.clk(gclk_vld[1]), .d(dvld[1]), .q(entry_vld[1]));
ffq #(1) ff_entry_dvld_2 (.clk(gclk_vld[2]), .d(dvld[2]), .q(entry_vld[2]));
ffq #(1) ff_entry_dvld_3 (.clk(gclk_vld[3]), .d(dvld[3]), .q(entry_vld[3]));
ffq #(1) ff_entry_dvld_4 (.clk(gclk_vld[4]), .d(dvld[4]), .q(entry_vld[4]));
ffq #(1) ff_entry_dvld_5 (.clk(gclk_vld[5]), .d(dvld[5]), .q(entry_vld[5]));
ffq #(1) ff_entry_dvld_6 (.clk(gclk_vld[6]), .d(dvld[6]), .q(entry_vld[6]));
ffq #(1) ff_entry_dvld_7 (.clk(gclk_vld[7]), .d(dvld[7]), .q(entry_vld[7]));
endmodule
|
(************************************************************************)
(* * The Coq Proof Assistant / The Coq Development Team *)
(* v * INRIA, CNRS and contributors - Copyright 1999-2018 *)
(* <O___,, * (see CREDITS file for the list of authors) *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(* * (see LICENSE file for the text of the license) *)
(************************************************************************)
(** * An light axiomatization of integers (used in MSetAVL). *)
(** We define a signature for an integer datatype based on [Z].
The goal is to allow a switch after extraction to ocaml's
[big_int] or even [int] when finiteness isn't a problem
(typically : when mesuring the height of an AVL tree).
*)
Require Import BinInt.
Delimit Scope Int_scope with I.
Local Open Scope Int_scope.
(** * A specification of integers *)
Module Type Int.
Parameter t : Set.
Bind Scope Int_scope with t.
Parameter i2z : t -> Z.
Parameter _0 : t.
Parameter _1 : t.
Parameter _2 : t.
Parameter _3 : t.
Parameter add : t -> t -> t.
Parameter opp : t -> t.
Parameter sub : t -> t -> t.
Parameter mul : t -> t -> t.
Parameter max : t -> t -> t.
Notation "0" := _0 : Int_scope.
Notation "1" := _1 : Int_scope.
Notation "2" := _2 : Int_scope.
Notation "3" := _3 : Int_scope.
Infix "+" := add : Int_scope.
Infix "-" := sub : Int_scope.
Infix "*" := mul : Int_scope.
Notation "- x" := (opp x) : Int_scope.
(** For logical relations, we can rely on their counterparts in Z,
since they don't appear after extraction. Moreover, using tactics
like omega is easier this way. *)
Notation "x == y" := (i2z x = i2z y)
(at level 70, y at next level, no associativity) : Int_scope.
Notation "x <= y" := (i2z x <= i2z y)%Z : Int_scope.
Notation "x < y" := (i2z x < i2z y)%Z : Int_scope.
Notation "x >= y" := (i2z x >= i2z y)%Z : Int_scope.
Notation "x > y" := (i2z x > i2z y)%Z : Int_scope.
Notation "x <= y <= z" := (x <= y /\ y <= z) : Int_scope.
Notation "x <= y < z" := (x <= y /\ y < z) : Int_scope.
Notation "x < y < z" := (x < y /\ y < z) : Int_scope.
Notation "x < y <= z" := (x < y /\ y <= z) : Int_scope.
(** Informative comparisons. *)
Axiom eqb : t -> t -> bool.
Axiom ltb : t -> t -> bool.
Axiom leb : t -> t -> bool.
Infix "=?" := eqb.
Infix "<?" := ltb.
Infix "<=?" := leb.
(** For compatibility, some decidability fonctions (informative). *)
Axiom gt_le_dec : forall x y : t, {x > y} + {x <= y}.
Axiom ge_lt_dec : forall x y : t, {x >= y} + {x < y}.
Axiom eq_dec : forall x y : t, { x == y } + {~ x==y }.
(** Specifications *)
(** First, we ask [i2z] to be injective. Said otherwise, our ad-hoc equality
[==] and the generic [=] are in fact equivalent. We define [==]
nonetheless since the translation to [Z] for using automatic tactic
is easier. *)
Axiom i2z_eq : forall n p : t, n == p -> n = p.
(** Then, we express the specifications of the above parameters using their
Z counterparts. *)
Axiom i2z_0 : i2z _0 = 0%Z.
Axiom i2z_1 : i2z _1 = 1%Z.
Axiom i2z_2 : i2z _2 = 2%Z.
Axiom i2z_3 : i2z _3 = 3%Z.
Axiom i2z_add : forall n p, i2z (n + p) = (i2z n + i2z p)%Z.
Axiom i2z_opp : forall n, i2z (-n) = (-i2z n)%Z.
Axiom i2z_sub : forall n p, i2z (n - p) = (i2z n - i2z p)%Z.
Axiom i2z_mul : forall n p, i2z (n * p) = (i2z n * i2z p)%Z.
Axiom i2z_max : forall n p, i2z (max n p) = Z.max (i2z n) (i2z p).
Axiom i2z_eqb : forall n p, eqb n p = Z.eqb (i2z n) (i2z p).
Axiom i2z_ltb : forall n p, ltb n p = Z.ltb (i2z n) (i2z p).
Axiom i2z_leb : forall n p, leb n p = Z.leb (i2z n) (i2z p).
End Int.
(** * Facts and tactics using [Int] *)
Module MoreInt (Import I:Int).
Local Notation int := I.t.
Lemma eqb_eq n p : (n =? p) = true <-> n == p.
Proof.
now rewrite i2z_eqb, Z.eqb_eq.
Qed.
Lemma eqb_neq n p : (n =? p) = false <-> ~(n == p).
Proof.
rewrite <- eqb_eq. destruct (n =? p); intuition.
Qed.
Lemma ltb_lt n p : (n <? p) = true <-> n < p.
Proof.
now rewrite i2z_ltb, Z.ltb_lt.
Qed.
Lemma ltb_nlt n p : (n <? p) = false <-> ~(n < p).
Proof.
rewrite <- ltb_lt. destruct (n <? p); intuition.
Qed.
Lemma leb_le n p : (n <=? p) = true <-> n <= p.
Proof.
now rewrite i2z_leb, Z.leb_le.
Qed.
Lemma leb_nle n p : (n <=? p) = false <-> ~(n <= p).
Proof.
rewrite <- leb_le. destruct (n <=? p); intuition.
Qed.
(** A magic (but costly) tactic that goes from [int] back to the [Z]
friendly world ... *)
Hint Rewrite ->
i2z_0 i2z_1 i2z_2 i2z_3 i2z_add i2z_opp i2z_sub i2z_mul i2z_max
i2z_eqb i2z_ltb i2z_leb : i2z.
Ltac i2z := match goal with
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H);
try autorewrite with i2z; clear H; intro H; i2z
| |- ?a = ?b =>
apply (i2z_eq a b); try autorewrite with i2z; i2z
| H : _ |- _ => progress autorewrite with i2z in H; i2z
| _ => try autorewrite with i2z
end.
(** A reflexive version of the [i2z] tactic *)
(** this [i2z_refl] is actually weaker than [i2z]. For instance, if a
[i2z] is buried deep inside a subterm, [i2z_refl] may miss it.
See also the limitation about [Set] or [Type] part below.
Anyhow, [i2z_refl] is enough for applying [romega]. *)
Ltac i2z_gen := match goal with
| |- ?a = ?b => apply (i2z_eq a b); i2z_gen
| H : ?a = ?b |- _ =>
generalize (f_equal i2z H); clear H; i2z_gen
| H : eq (A:=Z) ?a ?b |- _ => revert H; i2z_gen
| H : Z.lt ?a ?b |- _ => revert H; i2z_gen
| H : Z.le ?a ?b |- _ => revert H; i2z_gen
| H : Z.gt ?a ?b |- _ => revert H; i2z_gen
| H : Z.ge ?a ?b |- _ => revert H; i2z_gen
| H : _ -> ?X |- _ =>
(* A [Set] or [Type] part cannot be dealt with easily
using the [ExprP] datatype. So we forget it, leaving
a goal that can be weaker than the original. *)
match type of X with
| Type => clear H; i2z_gen
| Prop => revert H; i2z_gen
end
| H : _ <-> _ |- _ => revert H; i2z_gen
| H : _ /\ _ |- _ => revert H; i2z_gen
| H : _ \/ _ |- _ => revert H; i2z_gen
| H : ~ _ |- _ => revert H; i2z_gen
| _ => idtac
end.
Inductive ExprI : Set :=
| EI0 : ExprI
| EI1 : ExprI
| EI2 : ExprI
| EI3 : ExprI
| EIadd : ExprI -> ExprI -> ExprI
| EIopp : ExprI -> ExprI
| EIsub : ExprI -> ExprI -> ExprI
| EImul : ExprI -> ExprI -> ExprI
| EImax : ExprI -> ExprI -> ExprI
| EIraw : int -> ExprI.
Inductive ExprZ : Set :=
| EZadd : ExprZ -> ExprZ -> ExprZ
| EZopp : ExprZ -> ExprZ
| EZsub : ExprZ -> ExprZ -> ExprZ
| EZmul : ExprZ -> ExprZ -> ExprZ
| EZmax : ExprZ -> ExprZ -> ExprZ
| EZofI : ExprI -> ExprZ
| EZraw : Z -> ExprZ.
Inductive ExprP : Type :=
| EPeq : ExprZ -> ExprZ -> ExprP
| EPlt : ExprZ -> ExprZ -> ExprP
| EPle : ExprZ -> ExprZ -> ExprP
| EPgt : ExprZ -> ExprZ -> ExprP
| EPge : ExprZ -> ExprZ -> ExprP
| EPimpl : ExprP -> ExprP -> ExprP
| EPequiv : ExprP -> ExprP -> ExprP
| EPand : ExprP -> ExprP -> ExprP
| EPor : ExprP -> ExprP -> ExprP
| EPneg : ExprP -> ExprP
| EPraw : Prop -> ExprP.
(** [int] to [ExprI] *)
Ltac i2ei trm :=
match constr:(trm) with
| 0 => constr:(EI0)
| 1 => constr:(EI1)
| 2 => constr:(EI2)
| 3 => constr:(EI3)
| ?x + ?y => let ex := i2ei x with ey := i2ei y in constr:(EIadd ex ey)
| ?x - ?y => let ex := i2ei x with ey := i2ei y in constr:(EIsub ex ey)
| ?x * ?y => let ex := i2ei x with ey := i2ei y in constr:(EImul ex ey)
| max ?x ?y => let ex := i2ei x with ey := i2ei y in constr:(EImax ex ey)
| - ?x => let ex := i2ei x in constr:(EIopp ex)
| ?x => constr:(EIraw x)
end
(** [Z] to [ExprZ] *)
with z2ez trm :=
match constr:(trm) with
| (?x + ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZadd ex ey)
| (?x - ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZsub ex ey)
| (?x * ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EZmul ex ey)
| (Z.max ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EZmax ex ey)
| (- ?x)%Z => let ex := z2ez x in constr:(EZopp ex)
| i2z ?x => let ex := i2ei x in constr:(EZofI ex)
| ?x => constr:(EZraw x)
end.
(** [Prop] to [ExprP] *)
Ltac p2ep trm :=
match constr:(trm) with
| (?x <-> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPequiv ex ey)
| (?x -> ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPimpl ex ey)
| (?x /\ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPand ex ey)
| (?x \/ ?y) => let ex := p2ep x with ey := p2ep y in constr:(EPor ex ey)
| (~ ?x) => let ex := p2ep x in constr:(EPneg ex)
| (eq (A:=Z) ?x ?y) => let ex := z2ez x with ey := z2ez y in constr:(EPeq ex ey)
| (?x < ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPlt ex ey)
| (?x <= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPle ex ey)
| (?x > ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPgt ex ey)
| (?x >= ?y)%Z => let ex := z2ez x with ey := z2ez y in constr:(EPge ex ey)
| ?x => constr:(EPraw x)
end.
(** [ExprI] to [int] *)
Fixpoint ei2i (e:ExprI) : int :=
match e with
| EI0 => 0
| EI1 => 1
| EI2 => 2
| EI3 => 3
| EIadd e1 e2 => (ei2i e1)+(ei2i e2)
| EIsub e1 e2 => (ei2i e1)-(ei2i e2)
| EImul e1 e2 => (ei2i e1)*(ei2i e2)
| EImax e1 e2 => max (ei2i e1) (ei2i e2)
| EIopp e => -(ei2i e)
| EIraw i => i
end.
(** [ExprZ] to [Z] *)
Fixpoint ez2z (e:ExprZ) : Z :=
match e with
| EZadd e1 e2 => ((ez2z e1)+(ez2z e2))%Z
| EZsub e1 e2 => ((ez2z e1)-(ez2z e2))%Z
| EZmul e1 e2 => ((ez2z e1)*(ez2z e2))%Z
| EZmax e1 e2 => Z.max (ez2z e1) (ez2z e2)
| EZopp e => (-(ez2z e))%Z
| EZofI e => i2z (ei2i e)
| EZraw z => z
end.
(** [ExprP] to [Prop] *)
Fixpoint ep2p (e:ExprP) : Prop :=
match e with
| EPeq e1 e2 => (ez2z e1) = (ez2z e2)
| EPlt e1 e2 => ((ez2z e1)<(ez2z e2))%Z
| EPle e1 e2 => ((ez2z e1)<=(ez2z e2))%Z
| EPgt e1 e2 => ((ez2z e1)>(ez2z e2))%Z
| EPge e1 e2 => ((ez2z e1)>=(ez2z e2))%Z
| EPimpl e1 e2 => (ep2p e1) -> (ep2p e2)
| EPequiv e1 e2 => (ep2p e1) <-> (ep2p e2)
| EPand e1 e2 => (ep2p e1) /\ (ep2p e2)
| EPor e1 e2 => (ep2p e1) \/ (ep2p e2)
| EPneg e => ~ (ep2p e)
| EPraw p => p
end.
(** [ExprI] (supposed under a [i2z]) to a simplified [ExprZ] *)
Fixpoint norm_ei (e:ExprI) : ExprZ :=
match e with
| EI0 => EZraw (0%Z)
| EI1 => EZraw (1%Z)
| EI2 => EZraw (2%Z)
| EI3 => EZraw (3%Z)
| EIadd e1 e2 => EZadd (norm_ei e1) (norm_ei e2)
| EIsub e1 e2 => EZsub (norm_ei e1) (norm_ei e2)
| EImul e1 e2 => EZmul (norm_ei e1) (norm_ei e2)
| EImax e1 e2 => EZmax (norm_ei e1) (norm_ei e2)
| EIopp e => EZopp (norm_ei e)
| EIraw i => EZofI (EIraw i)
end.
(** [ExprZ] to a simplified [ExprZ] *)
Fixpoint norm_ez (e:ExprZ) : ExprZ :=
match e with
| EZadd e1 e2 => EZadd (norm_ez e1) (norm_ez e2)
| EZsub e1 e2 => EZsub (norm_ez e1) (norm_ez e2)
| EZmul e1 e2 => EZmul (norm_ez e1) (norm_ez e2)
| EZmax e1 e2 => EZmax (norm_ez e1) (norm_ez e2)
| EZopp e => EZopp (norm_ez e)
| EZofI e => norm_ei e
| EZraw z => EZraw z
end.
(** [ExprP] to a simplified [ExprP] *)
Fixpoint norm_ep (e:ExprP) : ExprP :=
match e with
| EPeq e1 e2 => EPeq (norm_ez e1) (norm_ez e2)
| EPlt e1 e2 => EPlt (norm_ez e1) (norm_ez e2)
| EPle e1 e2 => EPle (norm_ez e1) (norm_ez e2)
| EPgt e1 e2 => EPgt (norm_ez e1) (norm_ez e2)
| EPge e1 e2 => EPge (norm_ez e1) (norm_ez e2)
| EPimpl e1 e2 => EPimpl (norm_ep e1) (norm_ep e2)
| EPequiv e1 e2 => EPequiv (norm_ep e1) (norm_ep e2)
| EPand e1 e2 => EPand (norm_ep e1) (norm_ep e2)
| EPor e1 e2 => EPor (norm_ep e1) (norm_ep e2)
| EPneg e => EPneg (norm_ep e)
| EPraw p => EPraw p
end.
Lemma norm_ei_correct (e:ExprI) : ez2z (norm_ei e) = i2z (ei2i e).
Proof.
induction e; simpl; i2z; auto; try congruence.
Qed.
Lemma norm_ez_correct (e:ExprZ) : ez2z (norm_ez e) = ez2z e.
Proof.
induction e; simpl; i2z; auto; try congruence; apply norm_ei_correct.
Qed.
Lemma norm_ep_correct (e:ExprP) : ep2p (norm_ep e) <-> ep2p e.
Proof.
induction e; simpl; rewrite ?norm_ez_correct; intuition.
Qed.
Lemma norm_ep_correct2 (e:ExprP) : ep2p (norm_ep e) -> ep2p e.
Proof.
intros; destruct (norm_ep_correct e); auto.
Qed.
Ltac i2z_refl :=
i2z_gen;
match goal with |- ?t =>
let e := p2ep t in
change (ep2p e); apply norm_ep_correct2; simpl
end.
(* i2z_refl can be replaced below by (simpl in *; i2z).
The reflexive version improves compilation of AVL files by about 15% *)
End MoreInt.
(** * An implementation of [Int] *)
(** It's always nice to know that our [Int] interface is realizable :-) *)
Module Z_as_Int <: Int.
Local Open Scope Z_scope.
Definition t := Z.
Definition _0 := 0.
Definition _1 := 1.
Definition _2 := 2.
Definition _3 := 3.
Definition add := Z.add.
Definition opp := Z.opp.
Definition sub := Z.sub.
Definition mul := Z.mul.
Definition max := Z.max.
Definition eqb := Z.eqb.
Definition ltb := Z.ltb.
Definition leb := Z.leb.
Definition eq_dec := Z.eq_dec.
Definition gt_le_dec i j : {i > j} + { i <= j }.
Proof.
generalize (Z.ltb_spec j i).
destruct (j <? i); [left|right]; inversion H; trivial.
now apply Z.lt_gt.
Defined.
Definition ge_lt_dec i j : {i >= j} + { i < j }.
Proof.
generalize (Z.ltb_spec i j).
destruct (i <? j); [right|left]; inversion H; trivial.
now apply Z.le_ge.
Defined.
Definition i2z : t -> Z := fun n => n.
Lemma i2z_eq n p : i2z n = i2z p -> n = p. Proof. trivial. Qed.
Lemma i2z_0 : i2z _0 = 0. Proof. reflexivity. Qed.
Lemma i2z_1 : i2z _1 = 1. Proof. reflexivity. Qed.
Lemma i2z_2 : i2z _2 = 2. Proof. reflexivity. Qed.
Lemma i2z_3 : i2z _3 = 3. Proof. reflexivity. Qed.
Lemma i2z_add n p : i2z (n + p) = i2z n + i2z p.
Proof. reflexivity. Qed.
Lemma i2z_opp n : i2z (- n) = - i2z n.
Proof. reflexivity. Qed.
Lemma i2z_sub n p : i2z (n - p) = i2z n - i2z p.
Proof. reflexivity. Qed.
Lemma i2z_mul n p : i2z (n * p) = i2z n * i2z p.
Proof. reflexivity. Qed.
Lemma i2z_max n p : i2z (max n p) = Z.max (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_eqb n p : eqb n p = Z.eqb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_leb n p : leb n p = Z.leb (i2z n) (i2z p).
Proof. reflexivity. Qed.
Lemma i2z_ltb n p : ltb n p = Z.ltb (i2z n) (i2z p).
Proof. reflexivity. Qed.
(** Compatibility notations for Coq v8.4 *)
Notation plus := add (only parsing).
Notation minus := sub (only parsing).
Notation mult := mul (only parsing).
End Z_as_Int.
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