text
stringlengths 992
1.04M
|
|---|
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axis to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axi2vector #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_awid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_awaddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_awlen,
input wire [3-1:0] s_axi_awsize,
input wire [2-1:0] s_axi_awburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_awlock,
input wire [4-1:0] s_axi_awcache,
input wire [3-1:0] s_axi_awprot,
input wire [4-1:0] s_axi_awregion,
input wire [4-1:0] s_axi_awqos,
input wire [C_AXI_AWUSER_WIDTH-1:0] s_axi_awuser,
// Slave Interface Write Data Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_wid,
input wire [C_AXI_DATA_WIDTH-1:0] s_axi_wdata,
input wire [C_AXI_DATA_WIDTH/8-1:0] s_axi_wstrb,
input wire s_axi_wlast,
input wire [C_AXI_WUSER_WIDTH-1:0] s_axi_wuser,
// Slave Interface Write Response Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_bid,
output wire [2-1:0] s_axi_bresp,
output wire [C_AXI_BUSER_WIDTH-1:0] s_axi_buser,
// Slave Interface Read Address Ports
input wire [C_AXI_ID_WIDTH-1:0] s_axi_arid,
input wire [C_AXI_ADDR_WIDTH-1:0] s_axi_araddr,
input wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] s_axi_arlen,
input wire [3-1:0] s_axi_arsize,
input wire [2-1:0] s_axi_arburst,
input wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] s_axi_arlock,
input wire [4-1:0] s_axi_arcache,
input wire [3-1:0] s_axi_arprot,
input wire [4-1:0] s_axi_arregion,
input wire [4-1:0] s_axi_arqos,
input wire [C_AXI_ARUSER_WIDTH-1:0] s_axi_aruser,
// Slave Interface Read Data Ports
output wire [C_AXI_ID_WIDTH-1:0] s_axi_rid,
output wire [C_AXI_DATA_WIDTH-1:0] s_axi_rdata,
output wire [2-1:0] s_axi_rresp,
output wire s_axi_rlast,
output wire [C_AXI_RUSER_WIDTH-1:0] s_axi_ruser,
// payloads
output wire [C_AWPAYLOAD_WIDTH-1:0] s_awpayload,
output wire [C_WPAYLOAD_WIDTH-1:0] s_wpayload,
input wire [C_BPAYLOAD_WIDTH-1:0] s_bpayload,
output wire [C_ARPAYLOAD_WIDTH-1:0] s_arpayload,
input wire [C_RPAYLOAD_WIDTH-1:0] s_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign s_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH] = s_axi_awaddr;
assign s_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH] = s_axi_awprot;
assign s_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH] = s_axi_wdata;
assign s_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH] = s_axi_wstrb;
assign s_axi_bresp = s_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH];
assign s_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH] = s_axi_araddr;
assign s_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH] = s_axi_arprot;
assign s_axi_rdata = s_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH];
assign s_axi_rresp = s_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH];
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign s_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] = s_axi_awsize;
assign s_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH] = s_axi_awburst;
assign s_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH] = s_axi_awcache;
assign s_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] = s_axi_awlen;
assign s_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] = s_axi_awlock;
assign s_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] = s_axi_awid;
assign s_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] = s_axi_awqos;
assign s_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] = s_axi_wlast;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign s_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] = s_axi_wid;
end
else begin : gen_no_axi3_wid_packing
end
assign s_axi_bid = s_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH];
assign s_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] = s_axi_arsize;
assign s_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH] = s_axi_arburst;
assign s_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH] = s_axi_arcache;
assign s_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] = s_axi_arlen;
assign s_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] = s_axi_arlock;
assign s_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] = s_axi_arid;
assign s_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] = s_axi_arqos;
assign s_axi_rlast = s_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH];
assign s_axi_rid = s_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH];
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign s_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH] = s_axi_awregion;
assign s_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH] = s_axi_arregion;
end
else begin : gen_no_region_signals
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign s_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH] = s_axi_awuser;
assign s_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] = s_axi_wuser;
assign s_axi_buser = s_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH];
assign s_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH] = s_axi_aruser;
assign s_axi_ruser = s_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH];
end
else begin : gen_no_user_signals
assign s_axi_buser = 'b0;
assign s_axi_ruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign s_axi_bid = 'b0;
assign s_axi_buser = 'b0;
assign s_axi_rlast = 1'b1;
assign s_axi_rid = 'b0;
assign s_axi_ruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012-2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
// Description: SRL based FIFO for AXIS/AXI Channels.
//--------------------------------------------------------------------------
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_axic_srl_fifo #(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter C_FAMILY = "virtex7",
parameter integer C_PAYLOAD_WIDTH = 1,
parameter integer C_FIFO_DEPTH = 16 // Range: 4-16.
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire aclk, // Clock
input wire aresetn, // Reset
input wire [C_PAYLOAD_WIDTH-1:0] s_payload, // Input data
input wire s_valid, // Input data valid
output reg s_ready, // Input data ready
output wire [C_PAYLOAD_WIDTH-1:0] m_payload, // Output data
output reg m_valid, // Output data valid
input wire m_ready // Output data ready
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
// ceiling logb2
function integer f_clogb2 (input integer size);
integer s;
begin
s = size;
s = s - 1;
for (f_clogb2=1; s>1; f_clogb2=f_clogb2+1)
s = s >> 1;
end
endfunction // clogb2
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer LP_LOG_FIFO_DEPTH = f_clogb2(C_FIFO_DEPTH);
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [LP_LOG_FIFO_DEPTH-1:0] fifo_index;
wire [4-1:0] fifo_addr;
wire push;
wire pop ;
reg areset_r1;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
always @(posedge aclk) begin
areset_r1 <= ~aresetn;
end
always @(posedge aclk) begin
if (~aresetn) begin
fifo_index <= {LP_LOG_FIFO_DEPTH{1'b1}};
end
else begin
fifo_index <= push & ~pop ? fifo_index + 1'b1 :
~push & pop ? fifo_index - 1'b1 :
fifo_index;
end
end
assign push = s_valid & s_ready;
always @(posedge aclk) begin
if (~aresetn) begin
s_ready <= 1'b0;
end
else begin
s_ready <= areset_r1 ? 1'b1 :
push & ~pop && (fifo_index == (C_FIFO_DEPTH - 2'd2)) ? 1'b0 :
~push & pop ? 1'b1 :
s_ready;
end
end
assign pop = m_valid & m_ready;
always @(posedge aclk) begin
if (~aresetn) begin
m_valid <= 1'b0;
end
else begin
m_valid <= ~push & pop && (fifo_index == {LP_LOG_FIFO_DEPTH{1'b0}}) ? 1'b0 :
push & ~pop ? 1'b1 :
m_valid;
end
end
generate
if (LP_LOG_FIFO_DEPTH < 4) begin : gen_pad_fifo_addr
assign fifo_addr[0+:LP_LOG_FIFO_DEPTH] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
assign fifo_addr[LP_LOG_FIFO_DEPTH+:(4-LP_LOG_FIFO_DEPTH)] = {4-LP_LOG_FIFO_DEPTH{1'b0}};
end
else begin : gen_fifo_addr
assign fifo_addr[LP_LOG_FIFO_DEPTH-1:0] = fifo_index[LP_LOG_FIFO_DEPTH-1:0];
end
endgenerate
generate
genvar i;
for (i = 0; i < C_PAYLOAD_WIDTH; i = i + 1) begin : gen_data_bit
SRL16E
u_srl_fifo(
.Q ( m_payload[i] ) ,
.A0 ( fifo_addr[0] ) ,
.A1 ( fifo_addr[1] ) ,
.A2 ( fifo_addr[2] ) ,
.A3 ( fifo_addr[3] ) ,
.CE ( push ) ,
.CLK ( aclk ) ,
.D ( s_payload[i] )
);
end
endgenerate
endmodule
`default_nettype wire
// (c) Copyright 2012 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// axi to vector
// A generic module to merge all axi signals into one signal called payload.
// This is strictly wires, so no clk, reset, aclken, valid/ready are required.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_infrastructure_v1_1_0_vector2axi #
(
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_AXI_PROTOCOL = 0,
parameter integer C_AXI_ID_WIDTH = 4,
parameter integer C_AXI_ADDR_WIDTH = 32,
parameter integer C_AXI_DATA_WIDTH = 32,
parameter integer C_AXI_SUPPORTS_USER_SIGNALS = 0,
parameter integer C_AXI_SUPPORTS_REGION_SIGNALS = 0,
parameter integer C_AXI_AWUSER_WIDTH = 1,
parameter integer C_AXI_WUSER_WIDTH = 1,
parameter integer C_AXI_BUSER_WIDTH = 1,
parameter integer C_AXI_ARUSER_WIDTH = 1,
parameter integer C_AXI_RUSER_WIDTH = 1,
parameter integer C_AWPAYLOAD_WIDTH = 61,
parameter integer C_WPAYLOAD_WIDTH = 73,
parameter integer C_BPAYLOAD_WIDTH = 6,
parameter integer C_ARPAYLOAD_WIDTH = 61,
parameter integer C_RPAYLOAD_WIDTH = 69
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
// Slave Interface Write Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_awid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_awaddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_awlen,
output wire [3-1:0] m_axi_awsize,
output wire [2-1:0] m_axi_awburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_awlock,
output wire [4-1:0] m_axi_awcache,
output wire [3-1:0] m_axi_awprot,
output wire [4-1:0] m_axi_awregion,
output wire [4-1:0] m_axi_awqos,
output wire [C_AXI_AWUSER_WIDTH-1:0] m_axi_awuser,
// Slave Interface Write Data Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_wid,
output wire [C_AXI_DATA_WIDTH-1:0] m_axi_wdata,
output wire [C_AXI_DATA_WIDTH/8-1:0] m_axi_wstrb,
output wire m_axi_wlast,
output wire [C_AXI_WUSER_WIDTH-1:0] m_axi_wuser,
// Slave Interface Write Response Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_bid,
input wire [2-1:0] m_axi_bresp,
input wire [C_AXI_BUSER_WIDTH-1:0] m_axi_buser,
// Slave Interface Read Address Ports
output wire [C_AXI_ID_WIDTH-1:0] m_axi_arid,
output wire [C_AXI_ADDR_WIDTH-1:0] m_axi_araddr,
output wire [((C_AXI_PROTOCOL == 1) ? 4 : 8)-1:0] m_axi_arlen,
output wire [3-1:0] m_axi_arsize,
output wire [2-1:0] m_axi_arburst,
output wire [((C_AXI_PROTOCOL == 1) ? 2 : 1)-1:0] m_axi_arlock,
output wire [4-1:0] m_axi_arcache,
output wire [3-1:0] m_axi_arprot,
output wire [4-1:0] m_axi_arregion,
output wire [4-1:0] m_axi_arqos,
output wire [C_AXI_ARUSER_WIDTH-1:0] m_axi_aruser,
// Slave Interface Read Data Ports
input wire [C_AXI_ID_WIDTH-1:0] m_axi_rid,
input wire [C_AXI_DATA_WIDTH-1:0] m_axi_rdata,
input wire [2-1:0] m_axi_rresp,
input wire m_axi_rlast,
input wire [C_AXI_RUSER_WIDTH-1:0] m_axi_ruser,
// payloads
input wire [C_AWPAYLOAD_WIDTH-1:0] m_awpayload,
input wire [C_WPAYLOAD_WIDTH-1:0] m_wpayload,
output wire [C_BPAYLOAD_WIDTH-1:0] m_bpayload,
input wire [C_ARPAYLOAD_WIDTH-1:0] m_arpayload,
output wire [C_RPAYLOAD_WIDTH-1:0] m_rpayload
);
////////////////////////////////////////////////////////////////////////////////
// Functions
////////////////////////////////////////////////////////////////////////////////
`include "axi_infrastructure_v1_1_0.vh"
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
////////////////////////////////////////////////////////////////////////////////
// AXI4, AXI4LITE, AXI3 packing
assign m_axi_awaddr = m_awpayload[G_AXI_AWADDR_INDEX+:G_AXI_AWADDR_WIDTH];
assign m_axi_awprot = m_awpayload[G_AXI_AWPROT_INDEX+:G_AXI_AWPROT_WIDTH];
assign m_axi_wdata = m_wpayload[G_AXI_WDATA_INDEX+:G_AXI_WDATA_WIDTH];
assign m_axi_wstrb = m_wpayload[G_AXI_WSTRB_INDEX+:G_AXI_WSTRB_WIDTH];
assign m_bpayload[G_AXI_BRESP_INDEX+:G_AXI_BRESP_WIDTH] = m_axi_bresp;
assign m_axi_araddr = m_arpayload[G_AXI_ARADDR_INDEX+:G_AXI_ARADDR_WIDTH];
assign m_axi_arprot = m_arpayload[G_AXI_ARPROT_INDEX+:G_AXI_ARPROT_WIDTH];
assign m_rpayload[G_AXI_RDATA_INDEX+:G_AXI_RDATA_WIDTH] = m_axi_rdata;
assign m_rpayload[G_AXI_RRESP_INDEX+:G_AXI_RRESP_WIDTH] = m_axi_rresp;
generate
if (C_AXI_PROTOCOL == 0 || C_AXI_PROTOCOL == 1) begin : gen_axi4_or_axi3_packing
assign m_axi_awsize = m_awpayload[G_AXI_AWSIZE_INDEX+:G_AXI_AWSIZE_WIDTH] ;
assign m_axi_awburst = m_awpayload[G_AXI_AWBURST_INDEX+:G_AXI_AWBURST_WIDTH];
assign m_axi_awcache = m_awpayload[G_AXI_AWCACHE_INDEX+:G_AXI_AWCACHE_WIDTH];
assign m_axi_awlen = m_awpayload[G_AXI_AWLEN_INDEX+:G_AXI_AWLEN_WIDTH] ;
assign m_axi_awlock = m_awpayload[G_AXI_AWLOCK_INDEX+:G_AXI_AWLOCK_WIDTH] ;
assign m_axi_awid = m_awpayload[G_AXI_AWID_INDEX+:G_AXI_AWID_WIDTH] ;
assign m_axi_awqos = m_awpayload[G_AXI_AWQOS_INDEX+:G_AXI_AWQOS_WIDTH] ;
assign m_axi_wlast = m_wpayload[G_AXI_WLAST_INDEX+:G_AXI_WLAST_WIDTH] ;
if (C_AXI_PROTOCOL == 1) begin : gen_axi3_wid_packing
assign m_axi_wid = m_wpayload[G_AXI_WID_INDEX+:G_AXI_WID_WIDTH] ;
end
else begin : gen_no_axi3_wid_packing
assign m_axi_wid = 1'b0;
end
assign m_bpayload[G_AXI_BID_INDEX+:G_AXI_BID_WIDTH] = m_axi_bid;
assign m_axi_arsize = m_arpayload[G_AXI_ARSIZE_INDEX+:G_AXI_ARSIZE_WIDTH] ;
assign m_axi_arburst = m_arpayload[G_AXI_ARBURST_INDEX+:G_AXI_ARBURST_WIDTH];
assign m_axi_arcache = m_arpayload[G_AXI_ARCACHE_INDEX+:G_AXI_ARCACHE_WIDTH];
assign m_axi_arlen = m_arpayload[G_AXI_ARLEN_INDEX+:G_AXI_ARLEN_WIDTH] ;
assign m_axi_arlock = m_arpayload[G_AXI_ARLOCK_INDEX+:G_AXI_ARLOCK_WIDTH] ;
assign m_axi_arid = m_arpayload[G_AXI_ARID_INDEX+:G_AXI_ARID_WIDTH] ;
assign m_axi_arqos = m_arpayload[G_AXI_ARQOS_INDEX+:G_AXI_ARQOS_WIDTH] ;
assign m_rpayload[G_AXI_RLAST_INDEX+:G_AXI_RLAST_WIDTH] = m_axi_rlast;
assign m_rpayload[G_AXI_RID_INDEX+:G_AXI_RID_WIDTH] = m_axi_rid ;
if (C_AXI_SUPPORTS_REGION_SIGNALS == 1 && G_AXI_AWREGION_WIDTH > 0) begin : gen_region_signals
assign m_axi_awregion = m_awpayload[G_AXI_AWREGION_INDEX+:G_AXI_AWREGION_WIDTH];
assign m_axi_arregion = m_arpayload[G_AXI_ARREGION_INDEX+:G_AXI_ARREGION_WIDTH];
end
else begin : gen_no_region_signals
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
end
if (C_AXI_SUPPORTS_USER_SIGNALS == 1 && C_AXI_PROTOCOL != 2) begin : gen_user_signals
assign m_axi_awuser = m_awpayload[G_AXI_AWUSER_INDEX+:G_AXI_AWUSER_WIDTH];
assign m_axi_wuser = m_wpayload[G_AXI_WUSER_INDEX+:G_AXI_WUSER_WIDTH] ;
assign m_bpayload[G_AXI_BUSER_INDEX+:G_AXI_BUSER_WIDTH] = m_axi_buser ;
assign m_axi_aruser = m_arpayload[G_AXI_ARUSER_INDEX+:G_AXI_ARUSER_WIDTH];
assign m_rpayload[G_AXI_RUSER_INDEX+:G_AXI_RUSER_WIDTH] = m_axi_ruser ;
end
else begin : gen_no_user_signals
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
end
else begin : gen_axi4lite_packing
assign m_axi_awsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_awburst = 'b0;
assign m_axi_awcache = 'b0;
assign m_axi_awlen = 'b0;
assign m_axi_awlock = 'b0;
assign m_axi_awid = 'b0;
assign m_axi_awqos = 'b0;
assign m_axi_wlast = 1'b1;
assign m_axi_wid = 'b0;
assign m_axi_arsize = (C_AXI_DATA_WIDTH == 32) ? 3'd2 : 3'd3;
assign m_axi_arburst = 'b0;
assign m_axi_arcache = 'b0;
assign m_axi_arlen = 'b0;
assign m_axi_arlock = 'b0;
assign m_axi_arid = 'b0;
assign m_axi_arqos = 'b0;
assign m_axi_awregion = 'b0;
assign m_axi_arregion = 'b0;
assign m_axi_awuser = 'b0;
assign m_axi_wuser = 'b0;
assign m_axi_aruser = 'b0;
end
endgenerate
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 2012.2
// \ \ Description :
// / /
// /__/ /\ Filename : MUXF9.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/unified/chen/g2ltw/g2ltw.pl
// Revision: 1.0
// 09/26/12 - 680234 - ncsim compile error
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module MUXF9
`ifdef XIL_TIMING //Simprim
#(
parameter LOC = "UNPLACED"
)
`endif
(
output O,
input I0,
input I1,
input S
);
reg O_out;
always @(I0 or I1 or S)
if (S)
O_out = I1;
else
O_out = I0;
assign O = O_out;
`ifdef XIL_TIMING
specify
(I0 => O) = (0:0:0, 0:0:0);
(I1 => O) = (0:0:0, 0:0:0);
(S => O) = (0:0:0, 0:0:0);
specparam PATHPULSE$ = 0;
endspecify
`endif
endmodule
`endcelldefine
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
`define SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
/**
* einvn: Tri-state inverter, negative enable.
*
* Verilog stub definition (black box with power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hvl__einvn (
Z ,
A ,
TE_B,
VPWR,
VGND,
VPB ,
VNB
);
output Z ;
input A ;
input TE_B;
input VPWR;
input VGND;
input VPB ;
input VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HVL__EINVN_PP_BLACKBOX_V
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: ENCLab:ip:Tiger4NSC:1.2.3
// IP Revision: 1
(* X_CORE_INFO = "FMCTop,Vivado 2014.4.1" *)
(* CHECK_LICENSE_TYPE = "OpenSSD2_Tiger4NSC_0_0,FMCTop,{}" *)
(* DowngradeIPIdentifiedWarnings = "yes" *)
module OpenSSD2_Tiger4NSC_0_0 (
iClock,
iReset,
C_AWVALID,
C_AWREADY,
C_AWADDR,
C_AWPROT,
C_WVALID,
C_WREADY,
C_WDATA,
C_WSTRB,
C_BVALID,
C_BREADY,
C_BRESP,
C_ARVALID,
C_ARREADY,
C_ARADDR,
C_ARPROT,
C_RVALID,
C_RREADY,
C_RDATA,
C_RRESP,
D_AWADDR,
D_AWLEN,
D_AWSIZE,
D_AWBURST,
D_AWCACHE,
D_AWPROT,
D_AWVALID,
D_AWREADY,
D_WDATA,
D_WSTRB,
D_WLAST,
D_WVALID,
D_WREADY,
D_BRESP,
D_BVALID,
D_BREADY,
D_ARADDR,
D_ARLEN,
D_ARSIZE,
D_ARBURST,
D_ARCACHE,
D_ARPROT,
D_ARVALID,
D_ARREADY,
D_RDATA,
D_RRESP,
D_RLAST,
D_RVALID,
D_RREADY,
oOpcode,
oTargetID,
oSourceID,
oAddress,
oLength,
oCMDValid,
iCMDReady,
oWriteData,
oWriteLast,
oWriteValid,
iWriteReady,
iReadData,
iReadLast,
iReadValid,
oReadReady,
iReadyBusy,
oROMClock,
oROMReset,
oROMAddr,
oROMRW,
oROMEnable,
oROMWData,
iROMRData,
iSharedKESReady,
oErrorDetectionEnd,
oDecodeNeeded,
oSyndromes,
iIntraSharedKESEnd,
iErroredChunk,
iCorrectionFail,
iErrorCount,
iELPCoefficients,
oCSAvailable,
O_DEBUG
);
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 signal_clock CLK" *)
input wire iClock;
(* X_INTERFACE_INFO = "xilinx.com:signal:reset:1.0 signal_reset RST" *)
input wire iReset;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWVALID" *)
input wire C_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWREADY" *)
output wire C_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWADDR" *)
input wire [31 : 0] C_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI AWPROT" *)
input wire [2 : 0] C_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WVALID" *)
input wire C_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WREADY" *)
output wire C_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WDATA" *)
input wire [31 : 0] C_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI WSTRB" *)
input wire [3 : 0] C_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BVALID" *)
output wire C_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BREADY" *)
input wire C_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI BRESP" *)
output wire [1 : 0] C_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARVALID" *)
input wire C_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARREADY" *)
output wire C_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARADDR" *)
input wire [31 : 0] C_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI ARPROT" *)
input wire [2 : 0] C_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RVALID" *)
output wire C_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RREADY" *)
input wire C_RREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RDATA" *)
output wire [31 : 0] C_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 C_AXI RRESP" *)
output wire [1 : 0] C_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWADDR" *)
output wire [31 : 0] D_AWADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWLEN" *)
output wire [7 : 0] D_AWLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWSIZE" *)
output wire [2 : 0] D_AWSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWBURST" *)
output wire [1 : 0] D_AWBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWCACHE" *)
output wire [3 : 0] D_AWCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWPROT" *)
output wire [2 : 0] D_AWPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWVALID" *)
output wire D_AWVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI AWREADY" *)
input wire D_AWREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WDATA" *)
output wire [31 : 0] D_WDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WSTRB" *)
output wire [3 : 0] D_WSTRB;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WLAST" *)
output wire D_WLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WVALID" *)
output wire D_WVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI WREADY" *)
input wire D_WREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BRESP" *)
input wire [1 : 0] D_BRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BVALID" *)
input wire D_BVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI BREADY" *)
output wire D_BREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARADDR" *)
output wire [31 : 0] D_ARADDR;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARLEN" *)
output wire [7 : 0] D_ARLEN;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARSIZE" *)
output wire [2 : 0] D_ARSIZE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARBURST" *)
output wire [1 : 0] D_ARBURST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARCACHE" *)
output wire [3 : 0] D_ARCACHE;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARPROT" *)
output wire [2 : 0] D_ARPROT;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARVALID" *)
output wire D_ARVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI ARREADY" *)
input wire D_ARREADY;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RDATA" *)
input wire [31 : 0] D_RDATA;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RRESP" *)
input wire [1 : 0] D_RRESP;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RLAST" *)
input wire D_RLAST;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RVALID" *)
input wire D_RVALID;
(* X_INTERFACE_INFO = "xilinx.com:interface:aximm:1.0 D_AXI RREADY" *)
output wire D_RREADY;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Opcode" *)
output wire [5 : 0] oOpcode;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface TargetID" *)
output wire [4 : 0] oTargetID;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface SourceID" *)
output wire [4 : 0] oSourceID;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Address" *)
output wire [31 : 0] oAddress;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface Length" *)
output wire [15 : 0] oLength;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface CMDValid" *)
output wire oCMDValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface CMDReady" *)
input wire iCMDReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteData" *)
output wire [31 : 0] oWriteData;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteLast" *)
output wire oWriteLast;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteValid" *)
output wire oWriteValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface WriteReady" *)
input wire iWriteReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadData" *)
input wire [31 : 0] iReadData;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadLast" *)
input wire iReadLast;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadValid" *)
input wire iReadValid;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadReady" *)
output wire oReadReady;
(* X_INTERFACE_INFO = "ENCLab:user:V2FMCDCLW:1.0 NFCInterface ReadyBusy" *)
input wire [7 : 0] iReadyBusy;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface CLK" *)
output wire oROMClock;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface RST" *)
output wire oROMReset;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface ADDR" *)
output wire [255 : 0] oROMAddr;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface WE" *)
output wire oROMRW;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface EN" *)
output wire oROMEnable;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface DIN" *)
output wire [63 : 0] oROMWData;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 uROMInterface DOUT" *)
input wire [63 : 0] iROMRData;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface SharedKESReady" *)
input wire iSharedKESReady;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErrorDetectionEnd" *)
output wire [1 : 0] oErrorDetectionEnd;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface DecodeNeeded" *)
output wire [1 : 0] oDecodeNeeded;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface Syndromes" *)
output wire [647 : 0] oSyndromes;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface IntraSharedKESEnd" *)
input wire iIntraSharedKESEnd;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErroredChunk" *)
input wire [1 : 0] iErroredChunk;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface CorrectionFail" *)
input wire [1 : 0] iCorrectionFail;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ErrorCount" *)
input wire [17 : 0] iErrorCount;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface ELPCoefficients" *)
input wire [359 : 0] iELPCoefficients;
(* X_INTERFACE_INFO = "ENCLab:user:SharedKESInterface:1.0 SharedKESInterface CSAvailable" *)
output wire oCSAvailable;
output wire [31 : 0] O_DEBUG;
FMCTop #(
.NumberOfWays(8),
.ProgWordWidth(64),
.UProgSize(256),
.BCHDecMulti(2),
.GaloisFieldDegree(12),
.MaxErrorCountBits(9),
.Syndromes(27),
.ELPCoefficients(15)
) inst (
.iClock(iClock),
.iReset(iReset),
.C_AWVALID(C_AWVALID),
.C_AWREADY(C_AWREADY),
.C_AWADDR(C_AWADDR),
.C_AWPROT(C_AWPROT),
.C_WVALID(C_WVALID),
.C_WREADY(C_WREADY),
.C_WDATA(C_WDATA),
.C_WSTRB(C_WSTRB),
.C_BVALID(C_BVALID),
.C_BREADY(C_BREADY),
.C_BRESP(C_BRESP),
.C_ARVALID(C_ARVALID),
.C_ARREADY(C_ARREADY),
.C_ARADDR(C_ARADDR),
.C_ARPROT(C_ARPROT),
.C_RVALID(C_RVALID),
.C_RREADY(C_RREADY),
.C_RDATA(C_RDATA),
.C_RRESP(C_RRESP),
.D_AWADDR(D_AWADDR),
.D_AWLEN(D_AWLEN),
.D_AWSIZE(D_AWSIZE),
.D_AWBURST(D_AWBURST),
.D_AWCACHE(D_AWCACHE),
.D_AWPROT(D_AWPROT),
.D_AWVALID(D_AWVALID),
.D_AWREADY(D_AWREADY),
.D_WDATA(D_WDATA),
.D_WSTRB(D_WSTRB),
.D_WLAST(D_WLAST),
.D_WVALID(D_WVALID),
.D_WREADY(D_WREADY),
.D_BRESP(D_BRESP),
.D_BVALID(D_BVALID),
.D_BREADY(D_BREADY),
.D_ARADDR(D_ARADDR),
.D_ARLEN(D_ARLEN),
.D_ARSIZE(D_ARSIZE),
.D_ARBURST(D_ARBURST),
.D_ARCACHE(D_ARCACHE),
.D_ARPROT(D_ARPROT),
.D_ARVALID(D_ARVALID),
.D_ARREADY(D_ARREADY),
.D_RDATA(D_RDATA),
.D_RRESP(D_RRESP),
.D_RLAST(D_RLAST),
.D_RVALID(D_RVALID),
.D_RREADY(D_RREADY),
.oOpcode(oOpcode),
.oTargetID(oTargetID),
.oSourceID(oSourceID),
.oAddress(oAddress),
.oLength(oLength),
.oCMDValid(oCMDValid),
.iCMDReady(iCMDReady),
.oWriteData(oWriteData),
.oWriteLast(oWriteLast),
.oWriteValid(oWriteValid),
.iWriteReady(iWriteReady),
.iReadData(iReadData),
.iReadLast(iReadLast),
.iReadValid(iReadValid),
.oReadReady(oReadReady),
.iReadyBusy(iReadyBusy),
.oROMClock(oROMClock),
.oROMReset(oROMReset),
.oROMAddr(oROMAddr),
.oROMRW(oROMRW),
.oROMEnable(oROMEnable),
.oROMWData(oROMWData),
.iROMRData(iROMRData),
.iSharedKESReady(iSharedKESReady),
.oErrorDetectionEnd(oErrorDetectionEnd),
.oDecodeNeeded(oDecodeNeeded),
.oSyndromes(oSyndromes),
.iIntraSharedKESEnd(iIntraSharedKESEnd),
.iErroredChunk(iErroredChunk),
.iCorrectionFail(iCorrectionFail),
.iErrorCount(iErrorCount),
.iELPCoefficients(iELPCoefficients),
.oCSAvailable(oCSAvailable),
.O_DEBUG(O_DEBUG)
);
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized Mux from 2:1 upto 16:1.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_mux #
(
parameter C_FAMILY = "rtl",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_SEL_WIDTH = 4,
// Data width for comparator.
parameter integer C_DATA_WIDTH = 2
// Data width for comparator.
)
(
input wire [C_SEL_WIDTH-1:0] S,
input wire [(2**C_SEL_WIDTH)*C_DATA_WIDTH-1:0] A,
output wire [C_DATA_WIDTH-1:0] O
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar bit_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Instantiate or use RTL code
/////////////////////////////////////////////////////////////////////////////
generate
if ( C_FAMILY == "rtl" || C_SEL_WIDTH < 3 ) begin : USE_RTL
assign O = A[(S)*C_DATA_WIDTH +: C_DATA_WIDTH];
end else begin : USE_FPGA
wire [C_DATA_WIDTH-1:0] C;
wire [C_DATA_WIDTH-1:0] D;
// Lower half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_c_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**(C_SEL_WIDTH-1))*C_DATA_WIDTH-1 : 0]),
.O (C)
);
// Upper half recursively.
generic_baseblocks_v2_1_mux #
(
.C_FAMILY (C_FAMILY),
.C_SEL_WIDTH (C_SEL_WIDTH-1),
.C_DATA_WIDTH (C_DATA_WIDTH)
) mux_d_inst
(
.S (S[C_SEL_WIDTH-2:0]),
.A (A[(2**C_SEL_WIDTH)*C_DATA_WIDTH-1 : (2**(C_SEL_WIDTH-1))*C_DATA_WIDTH]),
.O (D)
);
// Generate instantiated generic_baseblocks_v2_1_mux components as required.
for (bit_cnt = 0; bit_cnt < C_DATA_WIDTH ; bit_cnt = bit_cnt + 1) begin : NUM
if ( C_SEL_WIDTH == 4 ) begin : USE_F8
MUXF8 muxf8_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end else if ( C_SEL_WIDTH == 3 ) begin : USE_F7
MUXF7 muxf7_inst
(
.I0 (C[bit_cnt]),
.I1 (D[bit_cnt]),
.S (S[C_SEL_WIDTH-1]),
.O (O[bit_cnt])
);
end // C_SEL_WIDTH
end // end for bit_cnt
end
endgenerate
endmodule
|
/**
* This is written by Zhiyang Ong
* and Andrew Mattheisen
* for EE577b Troy WideWord Processor Project
*
*
* @reminder December 1, 2007
* Remember to remove wrbyteen and ctrl_ppp from the inputs to
* the ALU and its testbench
*/
// GOLD VERSION
/**
* Reference:
* Nestoras Tzartzanis, EE 577B Verilog Example, Jan 25, 1996
* http://www-scf.usc.edu/~ee577/tutorial/verilog/alu.v
*/
/**
* Note that all instructions are 32-bits, and that Big-Endian
* byte and bit labeling is used. Hence, a[0] is the most
* significant bit, and a[31] is the least significant bit.
*
* Use of casex and casez may affect functionality, and produce
* larger and slower designs that omit the full_case directive
*
* Reference:
* Don Mills and Clifford E. Cummings, "RTL Coding Styles That
* Yield Simulation and Synthesis Mismatches", SNUG 1999
*
* ALU is a combinational logic block without clock signals
*/
`include "control.h"
// Behavioral model for the ALU
module alu (reg_A,reg_B,ctrl_ppp,ctrl_ww,alu_op,result,wrbyteen);
// Output signals...
// Result from copmputing an arithmetic or logical operation
output [0:127] result;
/**
* Overflow fromn arithmetic operations are ignored; use
* saturating mode for arithmetic operations - cap the value
* at the maximum value.
*
* Also, an output signal to indicate that an overflow has
* occurred will not be provided
*/
// ===============================================================
// Input signals
// Input register A
input [0:127] reg_A;
// Input register B
input [0:127] reg_B;
// Clock signal
//input clock;
// Control signal bits - ppp
input [0:2] ctrl_ppp;
// Control signal bits - ww
input [0:1] ctrl_ww;
/**
* Control signal bits - determine which arithmetic or logic
* operation to perform
*/
input [0:4] alu_op;
/**
* Byte-write enable signals: one for each byte of the data
*
* Asserted high when each byte of the address word needs to be
* updated during the write operation
*/
input [15:0] wrbyteen;
/**
* May also include: branch_offset[n:0], is_branch
* Size of branch offset is specified in the Instruction Set
* Architecture
*
* The reset signal for the ALU is ignored
*/
// Defining constants: parameter [name_of_constant] = value;
parameter max_128_bits = 128'hffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'hfffffffffffffffffffffffffffffffff;
//parameter max_128_bits = 128'h00112233445566778899aabbccddeeff1;
//parameter max_128_bits = 128'h123415678901234567890123456789012;
// ===============================================================
// Declare "wire" signals:
//wire FSM_OUTPUT;
// ===============================================================
// Declare "reg" signals:
reg [0:127] result; // Output signals
// ===============================================================
always @(reg_A or reg_B or ctrl_ppp or ctrl_ww or alu_op or wrbyteen)
begin
/**
* Based on the assigned arithmetic or logic instruction,
* carry out the appropriate function on the operands
*/
case(alu_op)
/**
* In computer science, a logical shift is a shift operator
* that shifts all the bits of its operand. Unlike an
* arithmetic shift, a logical shift does not preserve
* a number's sign bit or distinguish a number's exponent
* from its mantissa; every bit in the operand is simply
* moved a given number of bit positions, and the vacant
* bit-positions are filled in, generally with zeros
* (compare with a circular shift).
*
* SRL,SLL,Srli,sra,srai...
*/
// ================================================
// ======================================================
// SLL instruction << mv to LSB << bit 127
`aluwsll:
begin
case(ctrl_ww)
`w8: // aluwsll AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]<<reg_B[5:7];
result[8:15]<=reg_A[8:15]<<reg_B[13:15];
result[16:23]<=reg_A[16:23]<<reg_B[21:23];
result[24:31]<=reg_A[24:31]<<reg_B[29:31];
result[32:39]<=reg_A[32:39]<<reg_B[37:39];
result[40:47]<=reg_A[40:47]<<reg_B[45:47];
result[48:55]<=reg_A[48:55]<<reg_B[53:55];
result[56:63]<=reg_A[56:63]<<reg_B[61:63];
result[64:71]<=reg_A[64:71]<<reg_B[69:71];
result[72:79]<=reg_A[72:79]<<reg_B[77:79];
result[80:87]<=reg_A[80:87]<<reg_B[85:87];
result[88:95]<=reg_A[88:95]<<reg_B[93:95];
result[96:103]<=reg_A[96:103]<<reg_B[101:103];
result[104:111]<=reg_A[104:111]<<reg_B[109:111];
result[112:119]<=reg_A[112:119]<<reg_B[117:119];
result[120:127]<=reg_A[120:127]<<reg_B[125:127];
end
`w16: // aluwsll AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]<<reg_B[12:15];
result[16:31]<=reg_A[16:31]<<reg_B[28:31];
result[32:47]<=reg_A[32:47]<<reg_B[44:47];
result[48:63]<=reg_A[48:63]<<reg_B[60:63];
result[64:79]<=reg_A[64:79]<<reg_B[76:79];
result[80:95]<=reg_A[80:95]<<reg_B[92:95];
result[96:111]<=reg_A[96:111]<<reg_B[108:111];
result[112:127]<=reg_A[112:127]<<reg_B[124:127];
end
`w32: // aluwsll AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]<<reg_B[27:31];
result[32:63]<=reg_A[32:63]<<reg_B[59:63];
result[64:95]<=reg_A[64:95]<<reg_B[91:95];
result[96:127]<=reg_A[96:127]<<reg_B[123:127];
end
default: // aluwsll AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
/*
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
* ======================================================
*/
// ======================================================
// SRL instruction >> mv to MSB >> bit 0
`aluwsrl:
begin
case(ctrl_ppp)
`aa: // aluwsrl AND `aa
begin
case(ctrl_ww)
`w8: // aluwsrl AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default: // aluwsrl AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsrl AND `uu
begin
case(ctrl_ww)
`w8: // aluwsrl AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
end
`w16: // aluwsrl AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
end
`w32: // aluwsrl AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsrl AND `dd
begin
case(ctrl_ww)
`w8: // aluwsrl AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsrl AND `ee
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
result[16:23]<=reg_A[16:23]>>reg_B[21:23];
result[32:39]<=reg_A[32:39]>>reg_B[37:39];
result[48:55]<=reg_A[48:55]>>reg_B[53:55];
result[64:71]<=reg_A[64:71]>>reg_B[69:71];
result[80:87]<=reg_A[80:87]>>reg_B[85:87];
result[96:103]<=reg_A[96:103]>>reg_B[101:103];
result[112:119]<=reg_A[112:119]>>reg_B[117:119];
end
`w16: // aluwsrl AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
result[32:47]<=reg_A[32:47]>>reg_B[44:47];
result[64:79]<=reg_A[64:79]>>reg_B[76:79];
result[96:111]<=reg_A[96:111]>>reg_B[108:111];
end
`w32: // aluwsrl AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
result[64:95]<=reg_A[64:95]>>reg_B[91:95];
end
default:
begin
// aluwsrl AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsrl AND `oo
begin
case(ctrl_ww)
`w8: // aluwsrl AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]>>reg_B[13:15];
result[24:31]<=reg_A[24:31]>>reg_B[29:31];
result[40:47]<=reg_A[40:47]>>reg_B[45:47];
result[56:63]<=reg_A[56:63]>>reg_B[61:63];
result[72:79]<=reg_A[72:79]>>reg_B[77:79];
result[88:95]<=reg_A[88:95]>>reg_B[93:95];
result[104:111]<=reg_A[104:111]>>reg_B[109:111];
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]>>reg_B[28:31];
result[48:63]<=reg_A[48:63]>>reg_B[60:63];
result[80:95]<=reg_A[80:95]>>reg_B[92:95];
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]>>reg_B[59:63];
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsrl AND `mm
begin
case(ctrl_ww)
`w8: // aluwsrl AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]>>reg_B[5:7];
end
`w16: // aluwsrl AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]>>reg_B[12:15];
end
`w32: // aluwsrl AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]>>reg_B[27:31];
end
default:
begin
// aluwsrl AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsrl AND `ll
begin
case(ctrl_ww)
`w8: // aluwsrl AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]>>reg_B[125:127];
end
`w16: // aluwsrl AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]>>reg_B[124:127];
end
`w32: // aluwsrl AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]>>reg_B[123:127];
end
default:
begin
// aluwsrl AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsrl AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ================================================
// ADD instruction
`aluwadd:
begin
case(ctrl_ppp)
`aa: // aluwadd AND `aa
begin
case(ctrl_ww)
`w8: // aluwadd AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default: // aluwadd AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwadd AND `uu
begin
case(ctrl_ww)
`w8: // aluwadd AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
end
`w16: // aluwadd AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
end
`w32: // aluwadd AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[32:63]<=reg_A[32:63]+reg_B[32:63];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwadd AND `dd
begin
case(ctrl_ww)
`w8: // aluwadd AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]+reg_B[64:95];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwadd AND `ee
begin
case(ctrl_ww)
`w8: // aluwadd AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
result[16:23]<=reg_A[16:23]+reg_B[16:23];
result[32:39]<=reg_A[32:39]+reg_B[32:39];
result[48:55]<=reg_A[48:55]+reg_B[48:55];
result[64:71]<=reg_A[64:71]+reg_B[64:71];
result[80:87]<=reg_A[80:87]+reg_B[80:87];
result[96:103]<=reg_A[96:103]+reg_B[96:103];
result[112:119]<=reg_A[112:119]+reg_B[112:119];
end
`w16: // aluwadd AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
result[32:47]<=reg_A[32:47]+reg_B[32:47];
result[64:79]<=reg_A[64:79]+reg_B[64:79];
result[96:111]<=reg_A[96:111]+reg_B[96:111];
end
`w32: // aluwadd AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
result[64:95]<=reg_A[64:95]+reg_B[64:95];
end
default:
begin
// aluwadd AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwadd AND `oo
begin
case(ctrl_ww)
`w8: // aluwadd AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]+reg_B[8:15];
result[24:31]<=reg_A[24:31]+reg_B[24:31];
result[40:47]<=reg_A[40:47]+reg_B[40:47];
result[56:63]<=reg_A[56:63]+reg_B[56:63];
result[72:79]<=reg_A[72:79]+reg_B[72:79];
result[88:95]<=reg_A[88:95]+reg_B[88:95];
result[104:111]<=reg_A[104:111]+reg_B[104:111];
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]+reg_B[16:31];
result[48:63]<=reg_A[48:63]+reg_B[48:63];
result[80:95]<=reg_A[80:95]+reg_B[80:95];
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]+reg_B[32:63];
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwadd AND `mm
begin
case(ctrl_ww)
`w8: // aluwadd AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]+reg_B[0:7];
end
`w16: // aluwadd AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]+reg_B[0:15];
end
`w32: // aluwadd AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]+reg_B[0:31];
end
default:
begin
// aluwadd AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwadd AND `ll
begin
case(ctrl_ww)
`w8: // aluwadd AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]+reg_B[120:127];
end
`w16: // aluwadd AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]+reg_B[112:127];
end
`w32: // aluwadd AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]+reg_B[96:127];
end
default:
begin
// aluwadd AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwadd AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// AND instruction
`aluwand:
begin
case(ctrl_ppp)
`aa: // aluwand AND `aa
begin
case(ctrl_ww)
`w8: // aluwand AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default: // aluwand AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwand AND `uu
begin
case(ctrl_ww)
`w8: // aluwand AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[8:15]<=reg_A[8:15]®_B[8:15];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[56:63]<=reg_A[56:63]®_B[56:63];
end
`w16: // aluwand AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[16:31]<=reg_A[16:31]®_B[16:31];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[48:63]<=reg_A[48:63]®_B[48:63];
end
`w32: // aluwand AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[32:63]<=reg_A[32:63]®_B[32:63];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwand AND `dd
begin
case(ctrl_ww)
`w8: // aluwand AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]®_B[64:71];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[112:119]<=reg_A[112:119]®_B[112:119];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]®_B[64:79];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[96:111]<=reg_A[96:111]®_B[96:111];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]®_B[64:95];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwand AND `ee
begin
case(ctrl_ww)
`w8: // aluwand AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
result[16:23]<=reg_A[16:23]®_B[16:23];
result[32:39]<=reg_A[32:39]®_B[32:39];
result[48:55]<=reg_A[48:55]®_B[48:55];
result[64:71]<=reg_A[64:71]®_B[64:71];
result[80:87]<=reg_A[80:87]®_B[80:87];
result[96:103]<=reg_A[96:103]®_B[96:103];
result[112:119]<=reg_A[112:119]®_B[112:119];
end
`w16: // aluwand AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
result[32:47]<=reg_A[32:47]®_B[32:47];
result[64:79]<=reg_A[64:79]®_B[64:79];
result[96:111]<=reg_A[96:111]®_B[96:111];
end
`w32: // aluwand AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
result[64:95]<=reg_A[64:95]®_B[64:95];
end
default:
begin
// aluwand AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwand AND `oo
begin
case(ctrl_ww)
`w8: // aluwand AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]®_B[8:15];
result[24:31]<=reg_A[24:31]®_B[24:31];
result[40:47]<=reg_A[40:47]®_B[40:47];
result[56:63]<=reg_A[56:63]®_B[56:63];
result[72:79]<=reg_A[72:79]®_B[72:79];
result[88:95]<=reg_A[88:95]®_B[88:95];
result[104:111]<=reg_A[104:111]®_B[104:111];
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]®_B[16:31];
result[48:63]<=reg_A[48:63]®_B[48:63];
result[80:95]<=reg_A[80:95]®_B[80:95];
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]®_B[32:63];
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwand AND `mm
begin
case(ctrl_ww)
`w8: // aluwand AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]®_B[0:7];
end
`w16: // aluwand AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]®_B[0:15];
end
`w32: // aluwand AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]®_B[0:31];
end
default:
begin
// aluwand AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwand AND `ll
begin
case(ctrl_ww)
`w8: // aluwand AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]®_B[120:127];
end
`w16: // aluwand AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]®_B[112:127];
end
`w32: // aluwand AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]®_B[96:127];
end
default:
begin
// aluwand AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwand AND Default
begin
result<=128'd0;
end
endcase
end
// ==============================================
// ================================================
// NOT instruction
`aluwnot:
begin
case(ctrl_ppp)
`aa: // aluwnot AND `aa
begin
case(ctrl_ww)
`w8: // aluwnot AND `aa AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `aa AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `aa AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default: // aluwnot AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwnot AND `uu
begin
case(ctrl_ww)
`w8: // aluwnot AND `uu AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[8:15]<=~reg_A[8:15];
result[16:23]<=~reg_A[16:23];
result[24:31]<=~reg_A[24:31];
result[32:39]<=~reg_A[32:39];
result[40:47]<=~reg_A[40:47];
result[48:55]<=~reg_A[48:55];
result[56:63]<=~reg_A[56:63];
end
`w16: // aluwnot AND `uu AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[16:31]<=~reg_A[16:31];
result[32:47]<=~reg_A[32:47];
result[48:63]<=~reg_A[48:63];
end
`w32: // aluwnot AND `uu AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[32:63]<=~reg_A[32:63];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwnot AND `dd
begin
case(ctrl_ww)
`w8: // aluwnot AND `dd AND `w8
begin
result[64:71]<=~reg_A[64:71];
result[72:79]<=~reg_A[72:79];
result[80:87]<=~reg_A[80:87];
result[88:95]<=~reg_A[88:95];
result[96:103]<=~reg_A[96:103];
result[104:111]<=~reg_A[104:111];
result[112:119]<=~reg_A[112:119];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `dd AND `w16
begin
result[64:79]<=~reg_A[64:79];
result[80:95]<=~reg_A[80:95];
result[96:111]<=~reg_A[96:111];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `dd AND `w32
begin
result[64:95]<=~reg_A[64:95];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwnot AND `ee
begin
case(ctrl_ww)
`w8: // aluwnot AND `ee AND `w8
begin
result[0:7]<=~reg_A[0:7];
result[16:23]<=~reg_A[16:23];
result[32:39]<=~reg_A[32:39];
result[48:55]<=~reg_A[48:55];
result[64:71]<=~reg_A[64:71];
result[80:87]<=~reg_A[80:87];
result[96:103]<=~reg_A[96:103];
result[112:119]<=~reg_A[112:119];
end
`w16: // aluwnot AND `ee AND `w16
begin
result[0:15]<=~reg_A[0:15];
result[32:47]<=~reg_A[32:47];
result[64:79]<=~reg_A[64:79];
result[96:111]<=~reg_A[96:111];
end
`w32: // aluwnot AND `ee AND `w32
begin
result[0:31]<=~reg_A[0:31];
result[64:95]<=~reg_A[64:95];
end
default:
begin
// aluwnot AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwnot AND `oo
begin
case(ctrl_ww)
`w8: // aluwnot AND `oo AND `w8
begin
result[8:15]<=~reg_A[8:15];
result[24:31]<=~reg_A[24:31];
result[40:47]<=~reg_A[40:47];
result[56:63]<=~reg_A[56:63];
result[72:79]<=~reg_A[72:79];
result[88:95]<=~reg_A[88:95];
result[104:111]<=~reg_A[104:111];
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `oo AND `w16
begin
result[16:31]<=~reg_A[16:31];
result[48:63]<=~reg_A[48:63];
result[80:95]<=~reg_A[80:95];
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `oo AND `w32
begin
result[32:63]<=~reg_A[32:63];
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwnot AND `mm
begin
case(ctrl_ww)
`w8: // aluwnot AND `mm AND `w8
begin
result[0:7]<=~reg_A[0:7];
end
`w16: // aluwnot AND `mm AND `w16
begin
result[0:15]<=~reg_A[0:15];
end
`w32: // aluwnot AND `mm AND `w32
begin
result[0:31]<=~reg_A[0:31];
end
default:
begin
// aluwnot AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwnot AND `ll
begin
case(ctrl_ww)
`w8: // aluwnot AND `ll AND `w8
begin
result[120:127]<=~reg_A[120:127];
end
`w16: // aluwnot AND `ll AND `w16
begin
result[112:127]<=~reg_A[112:127];
end
`w32: // aluwnot AND `ll AND `w32
begin
result[96:127]<=~reg_A[96:127];
end
default:
begin
// aluwnot AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwnot AND Default
begin
result<=128'd0;
end
endcase
end
// ================================================
// OR instruction
`aluwor:
begin
case(ctrl_ppp)
`aa: // aluwor AND `aa
begin
case(ctrl_ww)
`w8: // aluwor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default: // aluwor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwor AND `uu
begin
case(ctrl_ww)
`w8: // aluwor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
end
`w16: // aluwor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
end
`w32: // aluwor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[32:63]<=reg_A[32:63]|reg_B[32:63];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwor AND `dd
begin
case(ctrl_ww)
`w8: // aluwor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]|reg_B[64:95];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwor AND `ee
begin
case(ctrl_ww)
`w8: // aluwor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
result[16:23]<=reg_A[16:23]|reg_B[16:23];
result[32:39]<=reg_A[32:39]|reg_B[32:39];
result[48:55]<=reg_A[48:55]|reg_B[48:55];
result[64:71]<=reg_A[64:71]|reg_B[64:71];
result[80:87]<=reg_A[80:87]|reg_B[80:87];
result[96:103]<=reg_A[96:103]|reg_B[96:103];
result[112:119]<=reg_A[112:119]|reg_B[112:119];
end
`w16: // aluwor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
result[32:47]<=reg_A[32:47]|reg_B[32:47];
result[64:79]<=reg_A[64:79]|reg_B[64:79];
result[96:111]<=reg_A[96:111]|reg_B[96:111];
end
`w32: // aluwor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
result[64:95]<=reg_A[64:95]|reg_B[64:95];
end
default:
begin
// aluwor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwor AND `oo
begin
case(ctrl_ww)
`w8: // aluwor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]|reg_B[8:15];
result[24:31]<=reg_A[24:31]|reg_B[24:31];
result[40:47]<=reg_A[40:47]|reg_B[40:47];
result[56:63]<=reg_A[56:63]|reg_B[56:63];
result[72:79]<=reg_A[72:79]|reg_B[72:79];
result[88:95]<=reg_A[88:95]|reg_B[88:95];
result[104:111]<=reg_A[104:111]|reg_B[104:111];
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]|reg_B[16:31];
result[48:63]<=reg_A[48:63]|reg_B[48:63];
result[80:95]<=reg_A[80:95]|reg_B[80:95];
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]|reg_B[32:63];
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwor AND `mm
begin
case(ctrl_ww)
`w8: // aluwor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]|reg_B[0:7];
end
`w16: // aluwor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]|reg_B[0:15];
end
`w32: // aluwor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]|reg_B[0:31];
end
default:
begin
// aluwor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwor AND `ll
begin
case(ctrl_ww)
`w8: // aluwor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]|reg_B[120:127];
end
`w16: // aluwor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]|reg_B[112:127];
end
`w32: // aluwor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]|reg_B[96:127];
end
default:
begin
// aluwor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwor AND Default
begin
result<=128'd0;
end
endcase
end
// ========================================================
// XOR instruction
`aluwxor:
begin
case(ctrl_ppp)
`aa: // aluwxor AND `aa
begin
case(ctrl_ww)
`w8: // aluwxor AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default: // aluwxor AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwxor AND `uu
begin
case(ctrl_ww)
`w8: // aluwxor AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
end
`w16: // aluwxor AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
end
`w32: // aluwxor AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[32:63]<=reg_A[32:63]^reg_B[32:63];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwxor AND `dd
begin
case(ctrl_ww)
`w8: // aluwxor AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]^reg_B[64:95];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwxor AND `ee
begin
case(ctrl_ww)
`w8: // aluwxor AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
result[16:23]<=reg_A[16:23]^reg_B[16:23];
result[32:39]<=reg_A[32:39]^reg_B[32:39];
result[48:55]<=reg_A[48:55]^reg_B[48:55];
result[64:71]<=reg_A[64:71]^reg_B[64:71];
result[80:87]<=reg_A[80:87]^reg_B[80:87];
result[96:103]<=reg_A[96:103]^reg_B[96:103];
result[112:119]<=reg_A[112:119]^reg_B[112:119];
end
`w16: // aluwxor AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
result[32:47]<=reg_A[32:47]^reg_B[32:47];
result[64:79]<=reg_A[64:79]^reg_B[64:79];
result[96:111]<=reg_A[96:111]^reg_B[96:111];
end
`w32: // aluwxor AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
result[64:95]<=reg_A[64:95]^reg_B[64:95];
end
default:
begin
// aluwxor AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwxor AND `oo
begin
case(ctrl_ww)
`w8: // aluwxor AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]^reg_B[8:15];
result[24:31]<=reg_A[24:31]^reg_B[24:31];
result[40:47]<=reg_A[40:47]^reg_B[40:47];
result[56:63]<=reg_A[56:63]^reg_B[56:63];
result[72:79]<=reg_A[72:79]^reg_B[72:79];
result[88:95]<=reg_A[88:95]^reg_B[88:95];
result[104:111]<=reg_A[104:111]^reg_B[104:111];
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]^reg_B[16:31];
result[48:63]<=reg_A[48:63]^reg_B[48:63];
result[80:95]<=reg_A[80:95]^reg_B[80:95];
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]^reg_B[32:63];
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwxor AND `mm
begin
case(ctrl_ww)
`w8: // aluwxor AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]^reg_B[0:7];
end
`w16: // aluwxor AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]^reg_B[0:15];
end
`w32: // aluwxor AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]^reg_B[0:31];
end
default:
begin
// aluwxor AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwxor AND `ll
begin
case(ctrl_ww)
`w8: // aluwxor AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]^reg_B[120:127];
end
`w16: // aluwxor AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]^reg_B[112:127];
end
`w32: // aluwxor AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]^reg_B[96:127];
end
default:
begin
// aluwxor AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwxor AND Default
begin
result<=128'd0;
end
endcase
end
// ======================================================
// SUB instruction
`aluwsub:
begin
case(ctrl_ppp)
`aa: // aluwsub AND `aa
begin
case(ctrl_ww)
`w8: // aluwsub AND `aa AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `aa AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `aa AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default: // aluwsub AND `aa AND Default
begin
result<=128'd0;
end
endcase
end
`uu: // aluwsub AND `uu
begin
case(ctrl_ww)
`w8: // aluwsub AND `uu AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
end
`w16: // aluwsub AND `uu AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
end
`w32: // aluwsub AND `uu AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[32:63]<=reg_A[32:63]-reg_B[32:63];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`dd: // aluwsub AND `dd
begin
case(ctrl_ww)
`w8: // aluwsub AND `dd AND `w8
begin
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `dd AND `w16
begin
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `dd AND `w32
begin
result[64:95]<=reg_A[64:95]-reg_B[64:95];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `dd AND Default
result<=128'd0;
end
endcase
end
`ee: // aluwsub AND `ee
begin
case(ctrl_ww)
`w8: // aluwsub AND `ee AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
result[16:23]<=reg_A[16:23]-reg_B[16:23];
result[32:39]<=reg_A[32:39]-reg_B[32:39];
result[48:55]<=reg_A[48:55]-reg_B[48:55];
result[64:71]<=reg_A[64:71]-reg_B[64:71];
result[80:87]<=reg_A[80:87]-reg_B[80:87];
result[96:103]<=reg_A[96:103]-reg_B[96:103];
result[112:119]<=reg_A[112:119]-reg_B[112:119];
end
`w16: // aluwsub AND `ee AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
result[32:47]<=reg_A[32:47]-reg_B[32:47];
result[64:79]<=reg_A[64:79]-reg_B[64:79];
result[96:111]<=reg_A[96:111]-reg_B[96:111];
end
`w32: // aluwsub AND `ee AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
result[64:95]<=reg_A[64:95]-reg_B[64:95];
end
default:
begin
// aluwsub AND `ee AND Default
result<=128'd0;
end
endcase
end
`oo: // aluwsub AND `oo
begin
case(ctrl_ww)
`w8: // aluwsub AND `oo AND `w8
begin
result[8:15]<=reg_A[8:15]-reg_B[8:15];
result[24:31]<=reg_A[24:31]-reg_B[24:31];
result[40:47]<=reg_A[40:47]-reg_B[40:47];
result[56:63]<=reg_A[56:63]-reg_B[56:63];
result[72:79]<=reg_A[72:79]-reg_B[72:79];
result[88:95]<=reg_A[88:95]-reg_B[88:95];
result[104:111]<=reg_A[104:111]-reg_B[104:111];
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `oo AND `w16
begin
result[16:31]<=reg_A[16:31]-reg_B[16:31];
result[48:63]<=reg_A[48:63]-reg_B[48:63];
result[80:95]<=reg_A[80:95]-reg_B[80:95];
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `oo AND `w32
begin
result[32:63]<=reg_A[32:63]-reg_B[32:63];
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `oo AND Default
result<=128'd0;
end
endcase
end
`mm: // aluwsub AND `mm
begin
case(ctrl_ww)
`w8: // aluwsub AND `mm AND `w8
begin
result[0:7]<=reg_A[0:7]-reg_B[0:7];
end
`w16: // aluwsub AND `mm AND `w16
begin
result[0:15]<=reg_A[0:15]-reg_B[0:15];
end
`w32: // aluwsub AND `mm AND `w32
begin
result[0:31]<=reg_A[0:31]-reg_B[0:31];
end
default:
begin
// aluwsub AND `mm AND `w8
result<=128'd0;
end
endcase
end
`ll: // aluwsub AND `ll
begin
case(ctrl_ww)
`w8: // aluwsub AND `ll AND `w8
begin
result[120:127]<=reg_A[120:127]-reg_B[120:127];
end
`w16: // aluwsub AND `ll AND `w16
begin
result[112:127]<=reg_A[112:127]-reg_B[112:127];
end
`w32: // aluwsub AND `ll AND `w32
begin
result[96:127]<=reg_A[96:127]-reg_B[96:127];
end
default:
begin
// aluwsub AND `ll AND Default
result<=128'd0;
end
endcase
end
default: // aluwsub AND Default
begin
result<=128'd0;
end
endcase
end
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
//================================================================================
// ==============================================================
// PRM instruction
`aluwprm:
begin
case(reg_B[4:7]) //byte0
4'd0:
result[0:7]<=reg_A[0:7];
4'd1:
result[0:7]<=reg_A[8:15];
4'd2:
result[0:7]<=reg_A[16:23];
4'd3:
result[0:7]<=reg_A[24:31];
4'd4:
result[0:7]<=reg_A[32:39];
4'd5:
result[0:7]<=reg_A[40:47];
4'd6:
result[0:7]<=reg_A[48:55];
4'd7:
result[0:7]<=reg_A[56:63];
4'd8:
result[0:7]<=reg_A[64:71];
4'd9:
result[0:7]<=reg_A[72:79];
4'd10:
result[0:7]<=reg_A[80:87];
4'd11:
result[0:7]<=reg_A[88:95];
4'd12:
result[0:7]<=reg_A[96:103];
4'd13:
result[0:7]<=reg_A[104:111];
4'd14:
result[0:7]<=reg_A[112:119];
4'd15:
result[0:7]<=reg_A[120:127];
endcase
case(reg_B[12:15]) //byte1
4'd0:
result[8:15]<=reg_A[0:7];
4'd1:
result[8:15]<=reg_A[8:15];
4'd2:
result[8:15]<=reg_A[16:23];
4'd3:
result[8:15]<=reg_A[24:31];
4'd4:
result[8:15]<=reg_A[32:39];
4'd5:
result[8:15]<=reg_A[40:47];
4'd6:
result[8:15]<=reg_A[48:55];
4'd7:
result[8:15]<=reg_A[56:63];
4'd8:
result[8:15]<=reg_A[64:71];
4'd9:
result[8:15]<=reg_A[72:79];
4'd10:
result[8:15]<=reg_A[80:87];
4'd11:
result[8:15]<=reg_A[88:95];
4'd12:
result[8:15]<=reg_A[96:103];
4'd13:
result[8:15]<=reg_A[104:111];
4'd14:
result[8:15]<=reg_A[112:119];
4'd15:
result[8:15]<=reg_A[120:127];
endcase
case(reg_B[20:23]) //byte2
4'd0:
result[16:23]<=reg_A[0:7];
4'd1:
result[16:23]<=reg_A[8:15];
4'd2:
result[16:23]<=reg_A[16:23];
4'd3:
result[16:23]<=reg_A[24:31];
4'd4:
result[16:23]<=reg_A[32:39];
4'd5:
result[16:23]<=reg_A[40:47];
4'd6:
result[16:23]<=reg_A[48:55];
4'd7:
result[16:23]<=reg_A[56:63];
4'd8:
result[16:23]<=reg_A[64:71];
4'd9:
result[16:23]<=reg_A[72:79];
4'd10:
result[16:23]<=reg_A[80:87];
4'd11:
result[16:23]<=reg_A[88:95];
4'd12:
result[16:23]<=reg_A[96:103];
4'd13:
result[16:23]<=reg_A[104:111];
4'd14:
result[16:23]<=reg_A[112:119];
4'd15:
result[16:23]<=reg_A[120:127];
endcase
case(reg_B[28:31]) //byte3
4'd0:
result[24:31]<=reg_A[0:7];
4'd1:
result[24:31]<=reg_A[8:15];
4'd2:
result[24:31]<=reg_A[16:23];
4'd3:
result[24:31]<=reg_A[24:31];
4'd4:
result[24:31]<=reg_A[32:39];
4'd5:
result[24:31]<=reg_A[40:47];
4'd6:
result[24:31]<=reg_A[48:55];
4'd7:
result[24:31]<=reg_A[56:63];
4'd8:
result[24:31]<=reg_A[64:71];
4'd9:
result[24:31]<=reg_A[72:79];
4'd10:
result[24:31]<=reg_A[80:87];
4'd11:
result[24:31]<=reg_A[88:95];
4'd12:
result[24:31]<=reg_A[96:103];
4'd13:
result[24:31]<=reg_A[104:111];
4'd14:
result[24:31]<=reg_A[112:119];
4'd15:
result[24:31]<=reg_A[120:127];
endcase
case(reg_B[36:39]) //byte4
4'd0:
result[32:39]<=reg_A[0:7];
4'd1:
result[32:39]<=reg_A[8:15];
4'd2:
result[32:39]<=reg_A[16:23];
4'd3:
result[32:39]<=reg_A[24:31];
4'd4:
result[32:39]<=reg_A[32:39];
4'd5:
result[32:39]<=reg_A[40:47];
4'd6:
result[32:39]<=reg_A[48:55];
4'd7:
result[32:39]<=reg_A[56:63];
4'd8:
result[32:39]<=reg_A[64:71];
4'd9:
result[32:39]<=reg_A[72:79];
4'd10:
result[32:39]<=reg_A[80:87];
4'd11:
result[32:39]<=reg_A[88:95];
4'd12:
result[32:39]<=reg_A[96:103];
4'd13:
result[32:39]<=reg_A[104:111];
4'd14:
result[32:39]<=reg_A[112:119];
4'd15:
result[32:39]<=reg_A[120:127];
endcase
case(reg_B[44:47]) //byte5
4'd0:
result[40:47]<=reg_A[0:7];
4'd1:
result[40:47]<=reg_A[8:15];
4'd2:
result[40:47]<=reg_A[16:23];
4'd3:
result[40:47]<=reg_A[24:31];
4'd4:
result[40:47]<=reg_A[32:39];
4'd5:
result[40:47]<=reg_A[40:47];
4'd6:
result[40:47]<=reg_A[48:55];
4'd7:
result[40:47]<=reg_A[56:63];
4'd8:
result[40:47]<=reg_A[64:71];
4'd9:
result[40:47]<=reg_A[72:79];
4'd10:
result[40:47]<=reg_A[80:87];
4'd11:
result[40:47]<=reg_A[88:95];
4'd12:
result[40:47]<=reg_A[96:103];
4'd13:
result[40:47]<=reg_A[104:111];
4'd14:
result[40:47]<=reg_A[112:119];
4'd15:
result[40:47]<=reg_A[120:127];
endcase
case(reg_B[52:55]) //byte6
4'd0:
result[48:55]<=reg_A[0:7];
4'd1:
result[48:55]<=reg_A[8:15];
4'd2:
result[48:55]<=reg_A[16:23];
4'd3:
result[48:55]<=reg_A[24:31];
4'd4:
result[48:55]<=reg_A[32:39];
4'd5:
result[48:55]<=reg_A[40:47];
4'd6:
result[48:55]<=reg_A[48:55];
4'd7:
result[48:55]<=reg_A[56:63];
4'd8:
result[48:55]<=reg_A[64:71];
4'd9:
result[48:55]<=reg_A[72:79];
4'd10:
result[48:55]<=reg_A[80:87];
4'd11:
result[48:55]<=reg_A[88:95];
4'd12:
result[48:55]<=reg_A[96:103];
4'd13:
result[48:55]<=reg_A[104:111];
4'd14:
result[48:55]<=reg_A[112:119];
4'd15:
result[48:55]<=reg_A[120:127];
endcase
case(reg_B[60:63]) //byte7
4'd0:
result[56:63]<=reg_A[0:7];
4'd1:
result[56:63]<=reg_A[8:15];
4'd2:
result[56:63]<=reg_A[16:23];
4'd3:
result[56:63]<=reg_A[24:31];
4'd4:
result[56:63]<=reg_A[32:39];
4'd5:
result[56:63]<=reg_A[40:47];
4'd6:
result[56:63]<=reg_A[48:55];
4'd7:
result[56:63]<=reg_A[56:63];
4'd8:
result[56:63]<=reg_A[64:71];
4'd9:
result[56:63]<=reg_A[72:79];
4'd10:
result[56:63]<=reg_A[80:87];
4'd11:
result[56:63]<=reg_A[88:95];
4'd12:
result[56:63]<=reg_A[96:103];
4'd13:
result[56:63]<=reg_A[104:111];
4'd14:
result[56:63]<=reg_A[112:119];
4'd15:
result[56:63]<=reg_A[120:127];
endcase
case(reg_B[68:71]) //byte8
4'd0:
result[64:71]<=reg_A[0:7];
4'd1:
result[64:71]<=reg_A[8:15];
4'd2:
result[64:71]<=reg_A[16:23];
4'd3:
result[64:71]<=reg_A[24:31];
4'd4:
result[64:71]<=reg_A[32:39];
4'd5:
result[64:71]<=reg_A[40:47];
4'd6:
result[64:71]<=reg_A[48:55];
4'd7:
result[64:71]<=reg_A[56:63];
4'd8:
result[64:71]<=reg_A[64:71];
4'd9:
result[64:71]<=reg_A[72:79];
4'd10:
result[64:71]<=reg_A[80:87];
4'd11:
result[64:71]<=reg_A[88:95];
4'd12:
result[64:71]<=reg_A[96:103];
4'd13:
result[64:71]<=reg_A[104:111];
4'd14:
result[64:71]<=reg_A[112:119];
4'd15:
result[64:71]<=reg_A[120:127];
endcase
case(reg_B[76:79]) //byte9
4'd0:
result[72:79]<=reg_A[0:7];
4'd1:
result[72:79]<=reg_A[8:15];
4'd2:
result[72:79]<=reg_A[16:23];
4'd3:
result[72:79]<=reg_A[24:31];
4'd4:
result[72:79]<=reg_A[32:39];
4'd5:
result[72:79]<=reg_A[40:47];
4'd6:
result[72:79]<=reg_A[48:55];
4'd7:
result[72:79]<=reg_A[56:63];
4'd8:
result[72:79]<=reg_A[64:71];
4'd9:
result[72:79]<=reg_A[72:79];
4'd10:
result[72:79]<=reg_A[80:87];
4'd11:
result[72:79]<=reg_A[88:95];
4'd12:
result[72:79]<=reg_A[96:103];
4'd13:
result[72:79]<=reg_A[104:111];
4'd14:
result[72:79]<=reg_A[112:119];
4'd15:
result[72:79]<=reg_A[120:127];
endcase
case(reg_B[84:87]) //byte10
4'd0:
result[80:87]<=reg_A[0:7];
4'd1:
result[80:87]<=reg_A[8:15];
4'd2:
result[80:87]<=reg_A[16:23];
4'd3:
result[80:87]<=reg_A[24:31];
4'd4:
result[80:87]<=reg_A[32:39];
4'd5:
result[80:87]<=reg_A[40:47];
4'd6:
result[80:87]<=reg_A[48:55];
4'd7:
result[80:87]<=reg_A[56:63];
4'd8:
result[80:87]<=reg_A[64:71];
4'd9:
result[80:87]<=reg_A[72:79];
4'd10:
result[80:87]<=reg_A[80:87];
4'd11:
result[80:87]<=reg_A[88:95];
4'd12:
result[80:87]<=reg_A[96:103];
4'd13:
result[80:87]<=reg_A[104:111];
4'd14:
result[80:87]<=reg_A[112:119];
4'd15:
result[80:87]<=reg_A[120:127];
endcase
case(reg_B[92:95]) //byte11
4'd0:
result[88:95]<=reg_A[0:7];
4'd1:
result[88:95]<=reg_A[8:15];
4'd2:
result[88:95]<=reg_A[16:23];
4'd3:
result[88:95]<=reg_A[24:31];
4'd4:
result[88:95]<=reg_A[32:39];
4'd5:
result[88:95]<=reg_A[40:47];
4'd6:
result[88:95]<=reg_A[48:55];
4'd7:
result[88:95]<=reg_A[56:63];
4'd8:
result[88:95]<=reg_A[64:71];
4'd9:
result[88:95]<=reg_A[72:79];
4'd10:
result[88:95]<=reg_A[80:87];
4'd11:
result[88:95]<=reg_A[88:95];
4'd12:
result[88:95]<=reg_A[96:103];
4'd13:
result[88:95]<=reg_A[104:111];
4'd14:
result[88:95]<=reg_A[112:119];
4'd15:
result[88:95]<=reg_A[120:127];
endcase
case(reg_B[100:103]) //byte12
4'd0:
result[96:103]<=reg_A[0:7];
4'd1:
result[96:103]<=reg_A[8:15];
4'd2:
result[96:103]<=reg_A[16:23];
4'd3:
result[96:103]<=reg_A[24:31];
4'd4:
result[96:103]<=reg_A[32:39];
4'd5:
result[96:103]<=reg_A[40:47];
4'd6:
result[96:103]<=reg_A[48:55];
4'd7:
result[96:103]<=reg_A[56:63];
4'd8:
result[96:103]<=reg_A[64:71];
4'd9:
result[96:103]<=reg_A[72:79];
4'd10:
result[96:103]<=reg_A[80:87];
4'd11:
result[96:103]<=reg_A[88:95];
4'd12:
result[96:103]<=reg_A[96:103];
4'd13:
result[96:103]<=reg_A[104:111];
4'd14:
result[96:103]<=reg_A[112:119];
4'd15:
result[96:103]<=reg_A[120:127];
endcase
case(reg_B[108:111]) //byte13
4'd0:
result[104:111]<=reg_A[0:7];
4'd1:
result[104:111]<=reg_A[8:15];
4'd2:
result[104:111]<=reg_A[16:23];
4'd3:
result[104:111]<=reg_A[24:31];
4'd4:
result[104:111]<=reg_A[32:39];
4'd5:
result[104:111]<=reg_A[40:47];
4'd6:
result[104:111]<=reg_A[48:55];
4'd7:
result[104:111]<=reg_A[56:63];
4'd8:
result[104:111]<=reg_A[64:71];
4'd9:
result[104:111]<=reg_A[72:79];
4'd10:
result[104:111]<=reg_A[80:87];
4'd11:
result[104:111]<=reg_A[88:95];
4'd12:
result[104:111]<=reg_A[96:103];
4'd13:
result[104:111]<=reg_A[104:111];
4'd14:
result[104:111]<=reg_A[112:119];
4'd15:
result[104:111]<=reg_A[120:127];
endcase
case(reg_B[116:119]) //byte14
4'd0:
result[112:119]<=reg_A[112:119];
4'd1:
result[112:119]<=reg_A[8:15];
4'd2:
result[112:119]<=reg_A[16:23];
4'd3:
result[112:119]<=reg_A[24:31];
4'd4:
result[112:119]<=reg_A[32:39];
4'd5:
result[112:119]<=reg_A[40:47];
4'd6:
result[112:119]<=reg_A[48:55];
4'd7:
result[112:119]<=reg_A[56:63];
4'd8:
result[112:119]<=reg_A[64:71];
4'd9:
result[112:119]<=reg_A[72:79];
4'd10:
result[112:119]<=reg_A[80:87];
4'd11:
result[112:119]<=reg_A[88:95];
4'd12:
result[112:119]<=reg_A[96:103];
4'd13:
result[112:119]<=reg_A[104:111];
4'd14:
result[112:119]<=reg_A[112:119];
4'd15:
result[112:119]<=reg_A[120:127];
endcase
case(reg_B[124:127]) //byte15
4'd0:
result[120:127]<=reg_A[0:7];
4'd1:
result[120:127]<=reg_A[8:15];
4'd2:
result[120:127]<=reg_A[16:23];
4'd3:
result[120:127]<=reg_A[24:31];
4'd4:
result[120:127]<=reg_A[32:39];
4'd5:
result[120:127]<=reg_A[40:47];
4'd6:
result[120:127]<=reg_A[48:55];
4'd7:
result[120:127]<=reg_A[56:63];
4'd8:
result[120:127]<=reg_A[64:71];
4'd9:
result[120:127]<=reg_A[72:79];
4'd10:
result[120:127]<=reg_A[80:87];
4'd11:
result[120:127]<=reg_A[88:95];
4'd12:
result[120:127]<=reg_A[96:103];
4'd13:
result[120:127]<=reg_A[104:111];
4'd14:
result[120:127]<=reg_A[112:119];
4'd15:
result[120:127]<=reg_A[120:127];
endcase
end
/*
* ========================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*=========================================================
*========================================================
*=========================================================
*========================================================
*========================================================
*=======================================================
*========================================================
*=======================================================
*=======================================================
*/
// ==============================================================
// SLLI instruction
`aluwslli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={reg_A[1:7],{1'b0}};
result[8:15]<={reg_A[9:15],{1'b0}};
result[16:23]<={reg_A[17:23],{1'b0}};
result[24:31]<={reg_A[25:31],{1'b0}};
result[32:39]<={reg_A[33:39],{1'b0}};
result[40:47]<={reg_A[41:47],{1'b0}};
result[48:55]<={reg_A[49:55],{1'b0}};
result[56:63]<={reg_A[57:63],{1'b0}};
result[64:71]<={reg_A[65:71],{1'b0}};
result[72:79]<={reg_A[73:79],{1'b0}};
result[80:87]<={reg_A[81:87],{1'b0}};
result[88:95]<={reg_A[89:95],{1'b0}};
result[96:103]<={reg_A[97:103],{1'b0}};
result[104:111]<={reg_A[105:111],{1'b0}};
result[112:119]<={reg_A[113:119],{1'b0}};
result[120:127]<={reg_A[121:127],{1'b0}};
end
3'd2:
begin
result[0:7]<={reg_A[2:7],{2{1'b0}}};
result[8:15]<={reg_A[10:15],{2{1'b0}}};
result[16:23]<={reg_A[18:23],{2{1'b0}}};
result[24:31]<={reg_A[26:31],{2{1'b0}}};
result[32:39]<={reg_A[34:39],{2{1'b0}}};
result[40:47]<={reg_A[42:47],{2{1'b0}}};
result[48:55]<={reg_A[50:55],{2{1'b0}}};
result[56:63]<={reg_A[58:63],{2{1'b0}}};
result[64:71]<={reg_A[66:71],{2{1'b0}}};
result[72:79]<={reg_A[74:79],{2{1'b0}}};
result[80:87]<={reg_A[82:87],{2{1'b0}}};
result[88:95]<={reg_A[90:95],{2{1'b0}}};
result[96:103]<={reg_A[98:103],{2{1'b0}}};
result[104:111]<={reg_A[106:111],{2{1'b0}}};
result[112:119]<={reg_A[114:119],{2{1'b0}}};
result[120:127]<={reg_A[122:127],{2{1'b0}}};
end
3'd3:
begin
result[0:7]<={reg_A[3:7],{3{1'b0}}};
result[8:15]<={reg_A[11:15],{3{1'b0}}};
result[16:23]<={reg_A[19:23],{3{1'b0}}};
result[24:31]<={reg_A[27:31],{3{1'b0}}};
result[32:39]<={reg_A[35:39],{3{1'b0}}};
result[40:47]<={reg_A[43:47],{3{1'b0}}};
result[48:55]<={reg_A[51:55],{3{1'b0}}};
result[56:63]<={reg_A[59:63],{3{1'b0}}};
result[64:71]<={reg_A[67:71],{3{1'b0}}};
result[72:79]<={reg_A[75:79],{3{1'b0}}};
result[80:87]<={reg_A[83:87],{3{1'b0}}};
result[88:95]<={reg_A[91:95],{3{1'b0}}};
result[96:103]<={reg_A[99:103],{3{1'b0}}};
result[104:111]<={reg_A[107:111],{3{1'b0}}};
result[112:119]<={reg_A[115:119],{3{1'b0}}};
result[120:127]<={reg_A[123:127],{3{1'b0}}};
end
3'd4:
begin
result[0:7]<={reg_A[4:7],{4{1'b0}}};
result[8:15]<={reg_A[12:15],{4{1'b0}}};
result[16:23]<={reg_A[20:23],{4{1'b0}}};
result[24:31]<={reg_A[28:31],{4{1'b0}}};
result[32:39]<={reg_A[36:39],{4{1'b0}}};
result[40:47]<={reg_A[44:47],{4{1'b0}}};
result[48:55]<={reg_A[52:55],{4{1'b0}}};
result[56:63]<={reg_A[60:63],{4{1'b0}}};
result[64:71]<={reg_A[68:71],{4{1'b0}}};
result[72:79]<={reg_A[76:79],{4{1'b0}}};
result[80:87]<={reg_A[84:87],{4{1'b0}}};
result[88:95]<={reg_A[92:95],{4{1'b0}}};
result[96:103]<={reg_A[100:103],{4{1'b0}}};
result[104:111]<={reg_A[108:111],{4{1'b0}}};
result[112:119]<={reg_A[116:119],{4{1'b0}}};
result[120:127]<={reg_A[124:127],{4{1'b0}}};
end
3'd5:
begin
result[0:7]<={reg_A[5:7],{5{1'b0}}};
result[8:15]<={reg_A[13:15],{5{1'b0}}};
result[16:23]<={reg_A[21:23],{5{1'b0}}};
result[24:31]<={reg_A[29:31],{5{1'b0}}};
result[32:39]<={reg_A[37:39],{5{1'b0}}};
result[40:47]<={reg_A[45:47],{5{1'b0}}};
result[48:55]<={reg_A[53:55],{5{1'b0}}};
result[56:63]<={reg_A[61:63],{5{1'b0}}};
result[64:71]<={reg_A[69:71],{5{1'b0}}};
result[72:79]<={reg_A[77:79],{5{1'b0}}};
result[80:87]<={reg_A[85:87],{5{1'b0}}};
result[88:95]<={reg_A[93:95],{5{1'b0}}};
result[96:103]<={reg_A[101:103],{5{1'b0}}};
result[104:111]<={reg_A[109:111],{5{1'b0}}};
result[112:119]<={reg_A[117:119],{5{1'b0}}};
result[120:127]<={reg_A[125:127],{5{1'b0}}};
end
3'd6:
begin
result[0:7]<={reg_A[6:7],{6{1'b0}}};
result[8:15]<={reg_A[14:15],{6{1'b0}}};
result[16:23]<={reg_A[22:23],{6{1'b0}}};
result[24:31]<={reg_A[30:31],{6{1'b0}}};
result[32:39]<={reg_A[38:39],{6{1'b0}}};
result[40:47]<={reg_A[46:47],{6{1'b0}}};
result[48:55]<={reg_A[54:55],{6{1'b0}}};
result[56:63]<={reg_A[62:63],{6{1'b0}}};
result[64:71]<={reg_A[70:71],{6{1'b0}}};
result[72:79]<={reg_A[78:79],{6{1'b0}}};
result[80:87]<={reg_A[86:87],{6{1'b0}}};
result[88:95]<={reg_A[94:95],{6{1'b0}}};
result[96:103]<={reg_A[102:103],{6{1'b0}}};
result[104:111]<={reg_A[110:111],{6{1'b0}}};
result[112:119]<={reg_A[118:119],{6{1'b0}}};
result[120:127]<={reg_A[126:127],{6{1'b0}}};
end
3'd7:
begin
result[0:7]<={reg_A[7],{7{1'b0}}};
result[8:15]<={reg_A[15],{7{1'b0}}};
result[16:23]<={reg_A[23],{7{1'b0}}};
result[24:31]<={reg_A[31],{7{1'b0}}};
result[32:39]<={reg_A[39],{7{1'b0}}};
result[40:47]<={reg_A[47],{7{1'b0}}};
result[48:55]<={reg_A[55],{7{1'b0}}};
result[56:63]<={reg_A[63],{7{1'b0}}};
result[64:71]<={reg_A[71],{7{1'b0}}};
result[72:79]<={reg_A[79],{7{1'b0}}};
result[80:87]<={reg_A[87],{7{1'b0}}};
result[88:95]<={reg_A[95],{7{1'b0}}};
result[96:103]<={reg_A[103],{7{1'b0}}};
result[104:111]<={reg_A[111],{7{1'b0}}};
result[112:119]<={reg_A[119],{7{1'b0}}};
result[120:127]<={reg_A[127],{7{1'b0}}};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={reg_A[1:15],{1'b0}};
result[16:31]<={reg_A[17:31],{1'b0}};
result[32:47]<={reg_A[33:47],{1'b0}};
result[48:63]<={reg_A[49:63],{1'b0}};
result[64:79]<={reg_A[65:79],{1'b0}};
result[80:95]<={reg_A[81:95],{1'b0}};
result[96:111]<={reg_A[97:111],{1'b0}};
result[112:127]<={reg_A[113:127],{1'b0}};
end
4'd2:
begin
result[0:15]<={reg_A[2:15],{2{1'b0}}};
result[16:31]<={reg_A[18:31],{2{1'b0}}};
result[32:47]<={reg_A[34:47],{2{1'b0}}};
result[48:63]<={reg_A[50:63],{2{1'b0}}};
result[64:79]<={reg_A[66:79],{2{1'b0}}};
result[80:95]<={reg_A[82:95],{2{1'b0}}};
result[96:111]<={reg_A[98:111],{2{1'b0}}};
result[112:127]<={reg_A[114:127],{2{1'b0}}};
end
4'd3:
begin
result[0:15]<={reg_A[3:15],{3{1'b0}}};
result[16:31]<={reg_A[19:31],{3{1'b0}}};
result[32:47]<={reg_A[35:47],{3{1'b0}}};
result[48:63]<={reg_A[51:63],{3{1'b0}}};
result[64:79]<={reg_A[67:79],{3{1'b0}}};
result[80:95]<={reg_A[83:95],{3{1'b0}}};
result[96:111]<={reg_A[99:111],{3{1'b0}}};
result[112:127]<={reg_A[115:127],{3{1'b0}}};
end
4'd4:
begin
result[0:15]<={reg_A[4:15],{4{1'b0}}};
result[16:31]<={reg_A[20:31],{4{1'b0}}};
result[32:47]<={reg_A[36:47],{4{1'b0}}};
result[48:63]<={reg_A[52:63],{4{1'b0}}};
result[64:79]<={reg_A[68:79],{4{1'b0}}};
result[80:95]<={reg_A[84:95],{4{1'b0}}};
result[96:111]<={reg_A[100:111],{4{1'b0}}};
result[112:127]<={reg_A[116:127],{4{1'b0}}};
end
4'd5:
begin
result[0:15]<={reg_A[5:15],{5{1'b0}}};
result[16:31]<={reg_A[21:31],{5{1'b0}}};
result[32:47]<={reg_A[37:47],{5{1'b0}}};
result[48:63]<={reg_A[52:63],{5{1'b0}}};
result[64:79]<={reg_A[69:79],{5{1'b0}}};
result[80:95]<={reg_A[85:95],{5{1'b0}}};
result[96:111]<={reg_A[101:111],{5{1'b0}}};
result[112:127]<={reg_A[117:127],{5{1'b0}}};
end
4'd6:
begin
result[0:15]<={reg_A[6:15],{6{1'b0}}};
result[16:31]<={reg_A[22:31],{6{1'b0}}};
result[32:47]<={reg_A[38:47],{6{1'b0}}};
result[48:63]<={reg_A[53:63],{6{1'b0}}};
result[64:79]<={reg_A[70:79],{6{1'b0}}};
result[80:95]<={reg_A[86:95],{6{1'b0}}};
result[96:111]<={reg_A[102:111],{6{1'b0}}};
result[112:127]<={reg_A[118:127],{6{1'b0}}};
end
4'd7:
begin
result[0:15]<={reg_A[7:15],{7{1'b0}}};
result[16:31]<={reg_A[23:31],{7{1'b0}}};
result[32:47]<={reg_A[39:47],{7{1'b0}}};
result[48:63]<={reg_A[54:63],{7{1'b0}}};
result[64:79]<={reg_A[71:79],{7{1'b0}}};
result[80:95]<={reg_A[87:95],{7{1'b0}}};
result[96:111]<={reg_A[103:111],{7{1'b0}}};
result[112:127]<={reg_A[119:127],{7{1'b0}}};
end
4'd8:
begin
result[0:15]<={reg_A[8:15],{8{1'b0}}};
result[16:31]<={reg_A[24:31],{8{1'b0}}};
result[32:47]<={reg_A[40:47],{8{1'b0}}};
result[48:63]<={reg_A[55:63],{8{1'b0}}};
result[64:79]<={reg_A[72:79],{8{1'b0}}};
result[80:95]<={reg_A[88:95],{8{1'b0}}};
result[96:111]<={reg_A[104:111],{8{1'b0}}};
result[112:127]<={reg_A[120:127],{8{1'b0}}};
end
4'd9:
begin
result[0:15]<={reg_A[9:15],{9{1'b0}}};
result[16:31]<={reg_A[25:31],{9{1'b0}}};
result[32:47]<={reg_A[41:47],{9{1'b0}}};
result[48:63]<={reg_A[56:63],{9{1'b0}}};
result[64:79]<={reg_A[73:79],{9{1'b0}}};
result[80:95]<={reg_A[89:95],{9{1'b0}}};
result[96:111]<={reg_A[105:111],{9{1'b0}}};
result[112:127]<={reg_A[121:127],{9{1'b0}}};
end
4'd10:
begin
result[0:15]<={reg_A[10:15],{10{1'b0}}};
result[16:31]<={reg_A[26:31],{10{1'b0}}};
result[32:47]<={reg_A[42:47],{10{1'b0}}};
result[48:63]<={reg_A[58:63],{10{1'b0}}};
result[64:79]<={reg_A[74:79],{10{1'b0}}};
result[80:95]<={reg_A[90:95],{10{1'b0}}};
result[96:111]<={reg_A[106:111],{10{1'b0}}};
result[112:127]<={reg_A[122:127],{10{1'b0}}};
end
4'd11:
begin
result[0:15]<={reg_A[11:15],{11{1'b0}}};
result[16:31]<={reg_A[27:31],{11{1'b0}}};
result[32:47]<={reg_A[43:47],{11{1'b0}}};
result[48:63]<={reg_A[59:63],{11{1'b0}}};
result[64:79]<={reg_A[75:79],{11{1'b0}}};
result[80:95]<={reg_A[91:95],{11{1'b0}}};
result[96:111]<={reg_A[107:111],{11{1'b0}}};
result[112:127]<={reg_A[123:127],{11{1'b0}}};
end
4'd12:
begin
result[0:15]<={reg_A[12:15],{12{1'b0}}};
result[16:31]<={reg_A[28:31],{12{1'b0}}};
result[32:47]<={reg_A[44:47],{12{1'b0}}};
result[48:63]<={reg_A[60:63],{12{1'b0}}};
result[64:79]<={reg_A[76:79],{12{1'b0}}};
result[80:95]<={reg_A[92:95],{12{1'b0}}};
result[96:111]<={reg_A[108:111],{12{1'b0}}};
result[112:127]<={reg_A[124:127],{12{1'b0}}};
end
4'd13:
begin
result[0:15]<={reg_A[13:15],{13{1'b0}}};
result[16:31]<={reg_A[29:31],{13{1'b0}}};
result[32:47]<={reg_A[45:47],{13{1'b0}}};
result[48:63]<={reg_A[61:63],{13{1'b0}}};
result[64:79]<={reg_A[77:79],{13{1'b0}}};
result[80:95]<={reg_A[93:95],{13{1'b0}}};
result[96:111]<={reg_A[109:111],{13{1'b0}}};
result[112:127]<={reg_A[125:127],{13{1'b0}}};
end
4'd14:
begin
result[0:15]<={reg_A[14:15],{14{1'b0}}};
result[16:31]<={reg_A[30:31],{14{1'b0}}};
result[32:47]<={reg_A[46:47],{14{1'b0}}};
result[48:63]<={reg_A[62:63],{14{1'b0}}};
result[64:79]<={reg_A[78:79],{14{1'b0}}};
result[80:95]<={reg_A[94:95],{14{1'b0}}};
result[96:111]<={reg_A[110:111],{14{1'b0}}};
result[112:127]<={reg_A[126:127],{14{1'b0}}};
end
4'd15:
begin
result[0:15]<={reg_A[15],{15{1'b0}}};
result[16:31]<={reg_A[31],{15{1'b0}}};
result[32:47]<={reg_A[47],{15{1'b0}}};
result[48:63]<={reg_A[63],{15{1'b0}}};
result[64:79]<={reg_A[79],{15{1'b0}}};
result[80:95]<={reg_A[95],{15{1'b0}}};
result[96:111]<={reg_A[111],{15{1'b0}}};
result[112:127]<={reg_A[127],{15{1'b0}}};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={reg_A[1:31],{1'b0}};
result[32:63]<={reg_A[33:63],{1'b0}};
result[64:95]<={reg_A[65:95],{1'b0}};
result[96:127]<={reg_A[97:127],{1'b0}};
end
5'd2:
begin
result[0:31]<={reg_A[2:31],{2{1'b0}}};
result[32:63]<={reg_A[34:63],{2{1'b0}}};
result[64:95]<={reg_A[66:95],{2{1'b0}}};
result[96:127]<={reg_A[98:127],{2{1'b0}}};
end
5'd3:
begin
result[0:31]<={reg_A[3:31],{3{1'b0}}};
result[32:63]<={reg_A[35:63],{3{1'b0}}};
result[64:95]<={reg_A[67:95],{3{1'b0}}};
result[96:127]<={reg_A[99:127],{3{1'b0}}};
end
5'd4:
begin
result[0:31]<={reg_A[4:31],{4{1'b0}}};
result[32:63]<={reg_A[36:63],{4{1'b0}}};
result[64:95]<={reg_A[68:95],{4{1'b0}}};
result[96:127]<={reg_A[100:127],{4{1'b0}}};
end
5'd5:
begin
result[0:31]<={reg_A[5:31],{5{1'b0}}};
result[32:63]<={reg_A[37:63],{5{1'b0}}};
result[64:95]<={reg_A[69:95],{5{1'b0}}};
result[96:127]<={reg_A[101:127],{5{1'b0}}};
end
5'd6:
begin
result[0:31]<={reg_A[6:31],{6{1'b0}}};
result[32:63]<={reg_A[38:63],{6{1'b0}}};
result[64:95]<={reg_A[70:95],{6{1'b0}}};
result[96:127]<={reg_A[102:127],{6{1'b0}}};
end
5'd7:
begin
result[0:31]<={reg_A[7:31],{7{1'b0}}};
result[32:63]<={reg_A[39:63],{7{1'b0}}};
result[64:95]<={reg_A[71:95],{7{1'b0}}};
result[96:127]<={reg_A[103:127],{7{1'b0}}};
end
5'd8:
begin
result[0:31]<={reg_A[8:31],{8{1'b0}}};
result[32:63]<={reg_A[40:63],{8{1'b0}}};
result[64:95]<={reg_A[72:95],{8{1'b0}}};
result[96:127]<={reg_A[104:127],{8{1'b0}}};
end
5'd9:
begin
result[0:31]<={reg_A[9:31],{9{1'b0}}};
result[32:63]<={reg_A[41:63],{9{1'b0}}};
result[64:95]<={reg_A[73:95],{9{1'b0}}};
result[96:127]<={reg_A[105:127],{9{1'b0}}};
end
5'd10:
begin
result[0:31]<={reg_A[10:31],{10{1'b0}}};
result[32:63]<={reg_A[42:63],{10{1'b0}}};
result[64:95]<={reg_A[74:95],{10{1'b0}}};
result[96:127]<={reg_A[106:127],{10{1'b0}}};
end
5'd11:
begin
result[0:31]<={reg_A[11:31],{11{1'b0}}};
result[32:63]<={reg_A[43:63],{11{1'b0}}};
result[64:95]<={reg_A[75:95],{11{1'b0}}};
result[96:127]<={reg_A[107:127],{11{1'b0}}};
end
5'd12:
begin
result[0:31]<={reg_A[12:31],{12{1'b0}}};
result[32:63]<={reg_A[44:63],{12{1'b0}}};
result[64:95]<={reg_A[76:95],{12{1'b0}}};
result[96:127]<={reg_A[108:127],{12{1'b0}}};
end
5'd13:
begin
result[0:31]<={reg_A[13:31],{13{1'b0}}};
result[32:63]<={reg_A[45:63],{13{1'b0}}};
result[64:95]<={reg_A[77:95],{13{1'b0}}};
result[96:127]<={reg_A[109:127],{13{1'b0}}};
end
5'd14:
begin
result[0:31]<={reg_A[14:31],{14{1'b0}}};
result[32:63]<={reg_A[46:63],{14{1'b0}}};
result[64:95]<={reg_A[78:95],{14{1'b0}}};
result[96:127]<={reg_A[110:127],{14{1'b0}}};
end
5'd15:
begin
result[0:31]<={reg_A[15:31],{15{1'b0}}};
result[32:63]<={reg_A[47:63],{15{1'b0}}};
result[64:95]<={reg_A[79:95],{15{1'b0}}};
result[96:127]<={reg_A[111:127],{15{1'b0}}};
end
5'd16:
begin
result[0:31]<={reg_A[16:31],{16{1'b0}}};
result[32:63]<={reg_A[48:63],{16{1'b0}}};
result[64:95]<={reg_A[80:95],{16{1'b0}}};
result[96:127]<={reg_A[112:127],{16{1'b0}}};
end
5'd17:
begin
result[0:31]<={reg_A[17:31],{17{1'b0}}};
result[32:63]<={reg_A[49:63],{17{1'b0}}};
result[64:95]<={reg_A[81:95],{17{1'b0}}};
result[96:127]<={reg_A[113:127],{17{1'b0}}};
end
5'd18:
begin
result[0:31]<={reg_A[18:31],{18{1'b0}}};
result[32:63]<={reg_A[50:63],{18{1'b0}}};
result[64:95]<={reg_A[82:95],{18{1'b0}}};
result[96:127]<={reg_A[114:127],{18{1'b0}}};
end
5'd19:
begin
result[0:31]<={reg_A[19:31],{19{1'b0}}};
result[32:63]<={reg_A[51:63],{19{1'b0}}};
result[64:95]<={reg_A[83:95],{19{1'b0}}};
result[96:127]<={reg_A[115:127],{19{1'b0}}};
end
5'd20:
begin
result[0:31]<={reg_A[20:31],{20{1'b0}}};
result[32:63]<={reg_A[52:63],{20{1'b0}}};
result[64:95]<={reg_A[84:95],{20{1'b0}}};
result[96:127]<={reg_A[116:127],{20{1'b0}}};
end
5'd21:
begin
result[0:31]<={reg_A[21:31],{21{1'b0}}};
result[32:63]<={reg_A[53:63],{21{1'b0}}};
result[64:95]<={reg_A[85:95],{21{1'b0}}};
result[96:127]<={reg_A[117:127],{21{1'b0}}};
end
5'd22:
begin
result[0:31]<={reg_A[22:31],{22{1'b0}}};
result[32:63]<={reg_A[54:63],{22{1'b0}}};
result[64:95]<={reg_A[86:95],{22{1'b0}}};
result[96:127]<={reg_A[118:127],{22{1'b0}}};
end
5'd23:
begin
result[0:31]<={reg_A[23:31],{23{1'b0}}};
result[32:63]<={reg_A[55:63],{23{1'b0}}};
result[64:95]<={reg_A[87:95],{23{1'b0}}};
result[96:127]<={reg_A[119:127],{23{1'b0}}};
end
5'd24:
begin
result[0:31]<={reg_A[24:31],{24{1'b0}}};
result[32:63]<={reg_A[56:63],{24{1'b0}}};
result[64:95]<={reg_A[88:95],{24{1'b0}}};
result[96:127]<={reg_A[120:127],{24{1'b0}}};
end
5'd25:
begin
result[0:31]<={reg_A[25:31],{25{1'b0}}};
result[32:63]<={reg_A[57:63],{25{1'b0}}};
result[64:95]<={reg_A[89:95],{25{1'b0}}};
result[96:127]<={reg_A[121:127],{25{1'b0}}};
end
5'd26:
begin
result[0:31]<={reg_A[26:31],{26{1'b0}}};
result[32:63]<={reg_A[58:63],{26{1'b0}}};
result[64:95]<={reg_A[90:95],{26{1'b0}}};
result[96:127]<={reg_A[122:127],{26{1'b0}}};
end
5'd27:
begin
result[0:31]<={reg_A[27:31],{27{1'b0}}};
result[32:63]<={reg_A[59:63],{27{1'b0}}};
result[64:95]<={reg_A[91:95],{27{1'b0}}};
result[96:127]<={reg_A[123:127],{27{1'b0}}};
end
5'd28:
begin
result[0:31]<={reg_A[28:31],{28{1'b0}}};
result[32:63]<={reg_A[60:63],{28{1'b0}}};
result[64:95]<={reg_A[92:95],{28{1'b0}}};
result[96:127]<={reg_A[124:127],{28{1'b0}}};
end
5'd29:
begin
result[0:31]<={reg_A[29:31],{29{1'b0}}};
result[32:63]<={reg_A[61:63],{29{1'b0}}};
result[64:95]<={reg_A[93:95],{29{1'b0}}};
result[96:127]<={reg_A[125:127],{29{1'b0}}};
end
5'd30:
begin
result[0:31]<={reg_A[30:31],{30{1'b0}}};
result[32:63]<={reg_A[62:63],{30{1'b0}}};
result[64:95]<={reg_A[94:95],{30{1'b0}}};
result[96:127]<={reg_A[126:127],{30{1'b0}}};
end
5'd31:
begin
result[0:31]<={reg_A[31],{31{1'b0}}};
result[32:63]<={reg_A[63],{31{1'b0}}};
result[64:95]<={reg_A[95],{31{1'b0}}};
result[96:127]<={reg_A[127],{31{1'b0}}};
end
endcase
end
endcase
end
// ==============================================================
// SRLI instruction
`aluwsrli:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{1'b0},reg_A[0:6]};
result[8:15]<={{1'b0},reg_A[8:14]};
result[16:23]<={{1'b0},reg_A[16:22]};
result[24:31]<={{1'b0},reg_A[24:30]};
result[32:39]<={{1'b0},reg_A[32:38]};
result[40:47]<={{1'b0},reg_A[40:46]};
result[48:55]<={{1'b0},reg_A[48:54]};
result[56:63]<={{1'b0},reg_A[56:62]};
result[64:71]<={{1'b0},reg_A[64:70]};
result[72:79]<={{1'b0},reg_A[72:78]};
result[80:87]<={{1'b0},reg_A[80:86]};
result[88:95]<={{1'b0},reg_A[88:94]};
result[96:103]<={{1'b0},reg_A[96:102]};
result[104:111]<={{1'b0},reg_A[104:110]};
result[112:119]<={{1'b0},reg_A[112:118]};
result[120:127]<={{1'b0},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{1'b0}},reg_A[0:5]};
result[8:15]<={{2{1'b0}},reg_A[8:13]};
result[16:23]<={{2{1'b0}},reg_A[16:21]};
result[24:31]<={{2{1'b0}},reg_A[24:29]};
result[32:39]<={{2{1'b0}},reg_A[32:37]};
result[40:47]<={{2{1'b0}},reg_A[40:45]};
result[48:55]<={{2{1'b0}},reg_A[48:53]};
result[56:63]<={{2{1'b0}},reg_A[56:61]};
result[64:71]<={{2{1'b0}},reg_A[64:69]};
result[72:79]<={{2{1'b0}},reg_A[72:77]};
result[80:87]<={{2{1'b0}},reg_A[80:85]};
result[88:95]<={{2{1'b0}},reg_A[88:93]};
result[96:103]<={{2{1'b0}},reg_A[96:101]};
result[104:111]<={{2{1'b0}},reg_A[104:109]};
result[112:119]<={{2{1'b0}},reg_A[112:117]};
result[120:127]<={{2{1'b0}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{1'b0}},reg_A[0:4]};
result[8:15]<={{3{1'b0}},reg_A[8:12]};
result[16:23]<={{3{1'b0}},reg_A[16:20]};
result[24:31]<={{3{1'b0}},reg_A[24:28]};
result[32:39]<={{3{1'b0}},reg_A[32:36]};
result[40:47]<={{3{1'b0}},reg_A[40:44]};
result[48:55]<={{3{1'b0}},reg_A[48:52]};
result[56:63]<={{3{1'b0}},reg_A[56:60]};
result[64:71]<={{3{1'b0}},reg_A[64:68]};
result[72:79]<={{3{1'b0}},reg_A[72:76]};
result[80:87]<={{3{1'b0}},reg_A[80:84]};
result[88:95]<={{3{1'b0}},reg_A[88:92]};
result[96:103]<={{3{1'b0}},reg_A[96:100]};
result[104:111]<={{3{1'b0}},reg_A[104:108]};
result[112:119]<={{3{1'b0}},reg_A[112:116]};
result[120:127]<={{3{1'b0}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{1'b0}},reg_A[0:3]};
result[8:15]<={{4{1'b0}},reg_A[8:11]};
result[16:23]<={{4{1'b0}},reg_A[16:19]};
result[24:31]<={{4{1'b0}},reg_A[24:27]};
result[32:39]<={{4{1'b0}},reg_A[32:35]};
result[40:47]<={{4{1'b0}},reg_A[40:43]};
result[48:55]<={{4{1'b0}},reg_A[48:51]};
result[56:63]<={{4{1'b0}},reg_A[56:69]};
result[64:71]<={{4{1'b0}},reg_A[64:67]};
result[72:79]<={{4{1'b0}},reg_A[72:75]};
result[80:87]<={{4{1'b0}},reg_A[80:83]};
result[88:95]<={{4{1'b0}},reg_A[88:91]};
result[96:103]<={{4{1'b0}},reg_A[96:99]};
result[104:111]<={{4{1'b0}},reg_A[104:107]};
result[112:119]<={{4{1'b0}},reg_A[112:115]};
result[120:127]<={{4{1'b0}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{1'b0}},reg_A[0:2]};
result[8:15]<={{5{1'b0}},reg_A[8:10]};
result[16:23]<={{5{1'b0}},reg_A[16:18]};
result[24:31]<={{5{1'b0}},reg_A[24:26]};
result[32:39]<={{5{1'b0}},reg_A[32:34]};
result[40:47]<={{5{1'b0}},reg_A[40:42]};
result[48:55]<={{5{1'b0}},reg_A[48:50]};
result[56:63]<={{5{1'b0}},reg_A[56:68]};
result[64:71]<={{5{1'b0}},reg_A[64:66]};
result[72:79]<={{5{1'b0}},reg_A[72:74]};
result[80:87]<={{5{1'b0}},reg_A[80:82]};
result[88:95]<={{5{1'b0}},reg_A[88:90]};
result[96:103]<={{5{1'b0}},reg_A[96:98]};
result[104:111]<={{5{1'b0}},reg_A[104:106]};
result[112:119]<={{5{1'b0}},reg_A[112:114]};
result[120:127]<={{5{1'b0}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{1'b0}},reg_A[0:1]};
result[8:15]<={{6{1'b0}},reg_A[8:9]};
result[16:23]<={{6{1'b0}},reg_A[16:17]};
result[24:31]<={{6{1'b0}},reg_A[24:25]};
result[32:39]<={{6{1'b0}},reg_A[32:33]};
result[40:47]<={{6{1'b0}},reg_A[40:41]};
result[48:55]<={{6{1'b0}},reg_A[48:49]};
result[56:63]<={{6{1'b0}},reg_A[56:67]};
result[64:71]<={{6{1'b0}},reg_A[64:65]};
result[72:79]<={{6{1'b0}},reg_A[72:73]};
result[80:87]<={{6{1'b0}},reg_A[80:81]};
result[88:95]<={{6{1'b0}},reg_A[88:89]};
result[96:103]<={{6{1'b0}},reg_A[96:97]};
result[104:111]<={{6{1'b0}},reg_A[104:105]};
result[112:119]<={{6{1'b0}},reg_A[112:113]};
result[120:127]<={{6{1'b0}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{1'b0}},reg_A[0]};
result[8:15]<={{7{1'b0}},reg_A[8]};
result[16:23]<={{7{1'b0}},reg_A[16]};
result[24:31]<={{7{1'b0}},reg_A[24]};
result[32:39]<={{7{1'b0}},reg_A[32]};
result[40:47]<={{7{1'b0}},reg_A[40]};
result[48:55]<={{7{1'b0}},reg_A[48]};
result[56:63]<={{7{1'b0}},reg_A[56]};
result[64:71]<={{7{1'b0}},reg_A[64]};
result[72:79]<={{7{1'b0}},reg_A[72]};
result[80:87]<={{7{1'b0}},reg_A[80]};
result[88:95]<={{7{1'b0}},reg_A[88]};
result[96:103]<={{7{1'b0}},reg_A[96]};
result[104:111]<={{7{1'b0}},reg_A[104]};
result[112:119]<={{7{1'b0}},reg_A[112]};
result[120:127]<={{7{1'b0}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{1'b0},reg_A[0:14]};
result[16:31]<={{1'b0},reg_A[16:30]};
result[32:47]<={{1'b0},reg_A[32:46]};
result[48:63]<={{1'b0},reg_A[48:62]};
result[64:79]<={{1'b0},reg_A[64:78]};
result[80:95]<={{1'b0},reg_A[80:94]};
result[96:111]<={{1'b0},reg_A[96:110]};
result[112:127]<={{1'b0},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{1'b0}},reg_A[0:13]};
result[16:31]<={{2{1'b0}},reg_A[16:29]};
result[32:47]<={{2{1'b0}},reg_A[32:45]};
result[48:63]<={{2{1'b0}},reg_A[48:61]};
result[64:79]<={{2{1'b0}},reg_A[64:77]};
result[80:95]<={{2{1'b0}},reg_A[80:93]};
result[96:111]<={{2{1'b0}},reg_A[96:109]};
result[112:127]<={{2{1'b0}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{1'b0}},reg_A[0:12]};
result[16:31]<={{3{1'b0}},reg_A[16:28]};
result[32:47]<={{3{1'b0}},reg_A[32:44]};
result[48:63]<={{3{1'b0}},reg_A[48:60]};
result[64:79]<={{3{1'b0}},reg_A[64:76]};
result[80:95]<={{3{1'b0}},reg_A[80:92]};
result[96:111]<={{3{1'b0}},reg_A[96:108]};
result[112:127]<={{3{1'b0}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{1'b0}},reg_A[0:11]};
result[16:31]<={{4{1'b0}},reg_A[16:27]};
result[32:47]<={{4{1'b0}},reg_A[32:43]};
result[48:63]<={{4{1'b0}},reg_A[48:59]};
result[64:79]<={{4{1'b0}},reg_A[64:75]};
result[80:95]<={{4{1'b0}},reg_A[80:91]};
result[96:111]<={{4{1'b0}},reg_A[96:107]};
result[112:127]<={{4{1'b0}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{1'b0}},reg_A[0:10]};
result[16:31]<={{5{1'b0}},reg_A[16:26]};
result[32:47]<={{5{1'b0}},reg_A[32:42]};
result[48:63]<={{5{1'b0}},reg_A[48:58]};
result[64:79]<={{5{1'b0}},reg_A[64:74]};
result[80:95]<={{5{1'b0}},reg_A[80:90]};
result[96:111]<={{5{1'b0}},reg_A[96:106]};
result[112:127]<={{5{1'b0}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{1'b0}},reg_A[0:9]};
result[16:31]<={{6{1'b0}},reg_A[16:25]};
result[32:47]<={{6{1'b0}},reg_A[32:41]};
result[48:63]<={{6{1'b0}},reg_A[48:57]};
result[64:79]<={{6{1'b0}},reg_A[64:73]};
result[80:95]<={{6{1'b0}},reg_A[80:89]};
result[96:111]<={{6{1'b0}},reg_A[96:105]};
result[112:127]<={{6{1'b0}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{1'b0}},reg_A[0:8]};
result[16:31]<={{7{1'b0}},reg_A[16:24]};
result[32:47]<={{7{1'b0}},reg_A[32:40]};
result[48:63]<={{7{1'b0}},reg_A[48:56]};
result[64:79]<={{7{1'b0}},reg_A[64:72]};
result[80:95]<={{7{1'b0}},reg_A[80:88]};
result[96:111]<={{7{1'b0}},reg_A[96:104]};
result[112:127]<={{7{1'b0}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{1'b0}},reg_A[0:7]};
result[16:31]<={{8{1'b0}},reg_A[16:23]};
result[32:47]<={{8{1'b0}},reg_A[32:39]};
result[48:63]<={{8{1'b0}},reg_A[48:55]};
result[64:79]<={{8{1'b0}},reg_A[64:71]};
result[80:95]<={{8{1'b0}},reg_A[80:87]};
result[96:111]<={{8{1'b0}},reg_A[96:103]};
result[112:127]<={{8{1'b0}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{1'b0}},reg_A[0:6]};
result[16:31]<={{9{1'b0}},reg_A[16:22]};
result[32:47]<={{9{1'b0}},reg_A[32:38]};
result[48:63]<={{9{1'b0}},reg_A[48:54]};
result[64:79]<={{9{1'b0}},reg_A[64:70]};
result[80:95]<={{9{1'b0}},reg_A[80:86]};
result[96:111]<={{9{1'b0}},reg_A[96:102]};
result[112:127]<={{9{1'b0}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{1'b0}},reg_A[0:5]};
result[16:31]<={{10{1'b0}},reg_A[16:21]};
result[32:47]<={{10{1'b0}},reg_A[32:37]};
result[48:63]<={{10{1'b0}},reg_A[48:53]};
result[64:79]<={{10{1'b0}},reg_A[64:69]};
result[80:95]<={{10{1'b0}},reg_A[80:85]};
result[96:111]<={{10{1'b0}},reg_A[96:101]};
result[112:127]<={{10{1'b0}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{1'b0}},reg_A[0:4]};
result[16:31]<={{11{1'b0}},reg_A[16:20]};
result[32:47]<={{11{1'b0}},reg_A[32:36]};
result[48:63]<={{11{1'b0}},reg_A[48:52]};
result[64:79]<={{11{1'b0}},reg_A[64:68]};
result[80:95]<={{11{1'b0}},reg_A[80:84]};
result[96:111]<={{11{1'b0}},reg_A[96:100]};
result[112:127]<={{11{1'b0}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{1'b0}},reg_A[0:3]};
result[16:31]<={{12{1'b0}},reg_A[16:19]};
result[32:47]<={{12{1'b0}},reg_A[32:35]};
result[48:63]<={{12{1'b0}},reg_A[48:51]};
result[64:79]<={{12{1'b0}},reg_A[64:67]};
result[80:95]<={{12{1'b0}},reg_A[80:83]};
result[96:111]<={{12{1'b0}},reg_A[96:99]};
result[112:127]<={{12{1'b0}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{1'b0}},reg_A[0:2]};
result[16:31]<={{13{1'b0}},reg_A[16:18]};
result[32:47]<={{13{1'b0}},reg_A[32:34]};
result[48:63]<={{13{1'b0}},reg_A[48:50]};
result[64:79]<={{13{1'b0}},reg_A[64:66]};
result[80:95]<={{13{1'b0}},reg_A[80:82]};
result[96:111]<={{13{1'b0}},reg_A[96:98]};
result[112:127]<={{13{1'b0}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{1'b0}},reg_A[0:1]};
result[16:31]<={{14{1'b0}},reg_A[16:17]};
result[32:47]<={{14{1'b0}},reg_A[32:33]};
result[48:63]<={{14{1'b0}},reg_A[48:49]};
result[64:79]<={{14{1'b0}},reg_A[64:65]};
result[80:95]<={{14{1'b0}},reg_A[80:81]};
result[96:111]<={{14{1'b0}},reg_A[96:97]};
result[112:127]<={{14{1'b0}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{1'b0}},reg_A[0]};
result[16:31]<={{15{1'b0}},reg_A[16]};
result[32:47]<={{15{1'b0}},reg_A[32]};
result[48:63]<={{15{1'b0}},reg_A[48]};
result[64:79]<={{15{1'b0}},reg_A[64]};
result[80:95]<={{15{1'b0}},reg_A[80]};
result[96:111]<={{15{1'b0}},reg_A[96]};
result[112:127]<={{15{1'b0}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{1'b0},reg_A[0:30]};
result[32:63]<={{1'b0},reg_A[32:62]};
result[64:95]<={{1'b0},reg_A[64:94]};
result[96:127]<={{1'b0},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{1'b0}},reg_A[0:29]};
result[32:63]<={{2{1'b0}},reg_A[32:61]};
result[64:95]<={{2{1'b0}},reg_A[64:93]};
result[96:127]<={{2{1'b0}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{1'b0}},reg_A[0:28]};
result[32:63]<={{3{1'b0}},reg_A[32:60]};
result[64:95]<={{3{1'b0}},reg_A[64:92]};
result[96:127]<={{3{1'b0}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{1'b0}},reg_A[0:27]};
result[32:63]<={{4{1'b0}},reg_A[32:59]};
result[64:95]<={{4{1'b0}},reg_A[64:91]};
result[96:127]<={{4{1'b0}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{1'b0}},reg_A[0:26]};
result[32:63]<={{5{1'b0}},reg_A[32:58]};
result[64:95]<={{5{1'b0}},reg_A[64:90]};
result[96:127]<={{5{1'b0}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{1'b0}},reg_A[0:25]};
result[32:63]<={{6{1'b0}},reg_A[32:57]};
result[64:95]<={{6{1'b0}},reg_A[64:89]};
result[96:127]<={{6{1'b0}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{1'b0}},reg_A[0:24]};
result[32:63]<={{7{1'b0}},reg_A[32:56]};
result[64:95]<={{7{1'b0}},reg_A[64:88]};
result[96:127]<={{7{1'b0}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{1'b0}},reg_A[0:23]};
result[32:63]<={{8{1'b0}},reg_A[32:55]};
result[64:95]<={{8{1'b0}},reg_A[64:87]};
result[96:127]<={{8{1'b0}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{1'b0}},reg_A[0:22]};
result[32:63]<={{9{1'b0}},reg_A[32:54]};
result[64:95]<={{9{1'b0}},reg_A[64:86]};
result[96:127]<={{9{1'b0}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{1'b0}},reg_A[0:21]};
result[32:63]<={{10{1'b0}},reg_A[32:53]};
result[64:95]<={{10{1'b0}},reg_A[64:85]};
result[96:127]<={{10{1'b0}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{1'b0}},reg_A[0:20]};
result[32:63]<={{11{1'b0}},reg_A[32:52]};
result[64:95]<={{11{1'b0}},reg_A[64:84]};
result[96:127]<={{11{1'b0}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{1'b0}},reg_A[0:19]};
result[32:63]<={{12{1'b0}},reg_A[32:51]};
result[64:95]<={{12{1'b0}},reg_A[64:83]};
result[96:127]<={{12{1'b0}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{1'b0}},reg_A[0:18]};
result[32:63]<={{13{1'b0}},reg_A[32:50]};
result[64:95]<={{13{1'b0}},reg_A[64:82]};
result[96:127]<={{13{1'b0}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{1'b0}},reg_A[0:17]};
result[32:63]<={{14{1'b0}},reg_A[32:49]};
result[64:95]<={{14{1'b0}},reg_A[64:81]};
result[96:127]<={{14{1'b0}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{1'b0}},reg_A[0:16]};
result[32:63]<={{15{1'b0}},reg_A[32:48]};
result[64:95]<={{15{1'b0}},reg_A[64:80]};
result[96:127]<={{15{1'b0}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{1'b0}},reg_A[0:15]};
result[32:63]<={{16{1'b0}},reg_A[32:47]};
result[64:95]<={{16{1'b0}},reg_A[64:79]};
result[96:127]<={{16{1'b0}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{1'b0}},reg_A[0:14]};
result[32:63]<={{17{1'b0}},reg_A[32:46]};
result[64:95]<={{17{1'b0}},reg_A[64:78]};
result[96:127]<={{17{1'b0}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{1'b0}},reg_A[0:13]};
result[32:63]<={{18{1'b0}},reg_A[32:45]};
result[64:95]<={{18{1'b0}},reg_A[64:77]};
result[96:127]<={{18{1'b0}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{1'b0}},reg_A[0:12]};
result[32:63]<={{19{1'b0}},reg_A[32:44]};
result[64:95]<={{19{1'b0}},reg_A[64:76]};
result[96:127]<={{19{1'b0}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{1'b0}},reg_A[0:11]};
result[32:63]<={{20{1'b0}},reg_A[32:43]};
result[64:95]<={{20{1'b0}},reg_A[64:75]};
result[96:127]<={{20{1'b0}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{1'b0}},reg_A[0:10]};
result[32:63]<={{21{1'b0}},reg_A[32:42]};
result[64:95]<={{21{1'b0}},reg_A[64:74]};
result[96:127]<={{21{1'b0}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{1'b0}},reg_A[0:9]};
result[32:63]<={{22{1'b0}},reg_A[32:41]};
result[64:95]<={{22{1'b0}},reg_A[64:73]};
result[96:127]<={{22{1'b0}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{1'b0}},reg_A[0:8]};
result[32:63]<={{23{1'b0}},reg_A[32:40]};
result[64:95]<={{23{1'b0}},reg_A[64:72]};
result[96:127]<={{23{1'b0}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{1'b0}},reg_A[0:7]};
result[32:63]<={{24{1'b0}},reg_A[32:39]};
result[64:95]<={{24{1'b0}},reg_A[64:71]};
result[96:127]<={{24{1'b0}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{1'b0}},reg_A[0:6]};
result[32:63]<={{25{1'b0}},reg_A[32:38]};
result[64:95]<={{25{1'b0}},reg_A[64:70]};
result[96:127]<={{25{1'b0}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{1'b0}},reg_A[0:5]};
result[32:63]<={{26{1'b0}},reg_A[32:37]};
result[64:95]<={{26{1'b0}},reg_A[64:69]};
result[96:127]<={{26{1'b0}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{1'b0}},reg_A[0:4]};
result[32:63]<={{27{1'b0}},reg_A[32:36]};
result[64:95]<={{27{1'b0}},reg_A[64:68]};
result[96:127]<={{27{1'b0}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{1'b0}},reg_A[0:3]};
result[32:63]<={{28{1'b0}},reg_A[32:35]};
result[64:95]<={{28{1'b0}},reg_A[64:67]};
result[96:127]<={{28{1'b0}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{1'b0}},reg_A[0:2]};
result[32:63]<={{29{1'b0}},reg_A[32:34]};
result[64:95]<={{29{1'b0}},reg_A[64:66]};
result[96:127]<={{29{1'b0}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{1'b0}},reg_A[0:1]};
result[32:63]<={{30{1'b0}},reg_A[32:33]};
result[64:95]<={{30{1'b0}},reg_A[64:65]};
result[96:127]<={{30{1'b0}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{1'b0}},reg_A[0]};
result[32:63]<={{31{1'b0}},reg_A[32]};
result[64:95]<={{31{1'b0}},reg_A[64]};
result[96:127]<={{31{1'b0}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRAI instruction
`aluwsrai:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[2:4])
3'd0:
begin
result[0:127]<=reg_A[0:127];
end
3'd1:
begin
result[0:7]<={{reg_A[0]},reg_A[0:6]};
result[8:15]<={{reg_A[8]},reg_A[8:14]};
result[16:23]<={{reg_A[16]},reg_A[16:22]};
result[24:31]<={{reg_A[24]},reg_A[24:30]};
result[32:39]<={{reg_A[32]},reg_A[32:38]};
result[40:47]<={{reg_A[40]},reg_A[40:46]};
result[48:55]<={{reg_A[48]},reg_A[48:54]};
result[56:63]<={{reg_A[56]},reg_A[56:62]};
result[64:71]<={{reg_A[64]},reg_A[64:70]};
result[72:79]<={{reg_A[72]},reg_A[72:78]};
result[80:87]<={{reg_A[80]},reg_A[80:86]};
result[88:95]<={{reg_A[88]},reg_A[88:94]};
result[96:103]<={{reg_A[96]},reg_A[96:102]};
result[104:111]<={{reg_A[104]},reg_A[104:110]};
result[112:119]<={{reg_A[112]},reg_A[112:118]};
result[120:127]<={{reg_A[120]},reg_A[120:126]};
end
3'd2:
begin
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
end
3'd3:
begin
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
end
3'd4:
begin
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
result[56:63]<={{4{reg_A[56]}},reg_A[56:69]};
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
end
3'd5:
begin
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
result[56:63]<={{5{reg_A[56]}},reg_A[56:68]};
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
end
3'd6:
begin
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
result[56:63]<={{6{reg_A[56]}},reg_A[56:67]};
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
end
3'd7:
begin
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
end
endcase
end
`w16:
begin
case(reg_B[1:4])
4'd0:
begin
result[0:127]<=reg_A[0:127];
end
4'd1:
begin
result[0:15]<={{reg_A[0]},reg_A[0:14]};
result[16:31]<={{reg_A[16]},reg_A[16:30]};
result[32:47]<={{reg_A[32]},reg_A[32:46]};
result[48:63]<={{reg_A[48]},reg_A[48:62]};
result[64:79]<={{reg_A[64]},reg_A[64:78]};
result[80:95]<={{reg_A[80]},reg_A[80:94]};
result[96:111]<={{reg_A[96]},reg_A[96:110]};
result[112:127]<={{reg_A[112]},reg_A[112:126]};
end
4'd2:
begin
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
end
4'd3:
begin
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
end
4'd4:
begin
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
result[16:31]<={{4{reg_A[8]}},reg_A[16:27]};
result[32:47]<={{4{reg_A[16]}},reg_A[32:43]};
result[48:63]<={{4{reg_A[32]}},reg_A[48:59]};
result[64:79]<={{4{reg_A[48]}},reg_A[64:75]};
result[80:95]<={{4{reg_A[64]}},reg_A[80:91]};
result[96:111]<={{4{reg_A[80]}},reg_A[96:107]};
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
end
4'd5:
begin
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
end
4'd6:
begin
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
end
4'd7:
begin
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
end
4'd8:
begin
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
end
4'd9:
begin
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
end
4'd10:
begin
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
end
4'd11:
begin
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
end
4'd12:
begin
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
end
4'd13:
begin
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
end
4'd14:
begin
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
end
4'd15:
begin
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
end
endcase
end
`w32:
begin
case(reg_B[0:4])
5'd0:
begin
result[0:127]<=reg_A[0:127];
end
5'd1:
begin
result[0:31]<={{reg_A[0]},reg_A[0:30]};
result[32:63]<={{reg_A[32]},reg_A[32:62]};
result[64:95]<={{reg_A[64]},reg_A[64:94]};
result[96:127]<={{reg_A[96]},reg_A[96:126]};
end
5'd2:
begin
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
end
5'd3:
begin
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
end
5'd4:
begin
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
end
5'd5:
begin
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
end
5'd6:
begin
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
end
5'd7:
begin
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
end
5'd8:
begin
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
end
5'd9:
begin
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
end
5'd10:
begin
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
end
5'd11:
begin
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
end
5'd12:
begin
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
end
5'd13:
begin
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
end
5'd14:
begin
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
end
5'd15:
begin
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
end
5'd16:
begin
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
end
5'd17:
begin
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
end
5'd18:
begin
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
end
5'd19:
begin
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
end
5'd20:
begin
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
end
5'd21:
begin
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
end
5'd22:
begin
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
end
5'd23:
begin
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
end
5'd24:
begin
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
end
5'd25:
begin
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
end
5'd26:
begin
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
end
5'd27:
begin
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
end
5'd28:
begin
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
end
5'd29:
begin
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
end
5'd30:
begin
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
end
5'd31:
begin
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
end
endcase
end
endcase
end
// ==============================================================
// SRA instruction
`aluwsra:
begin
case(ctrl_ww)
`w8:
begin
case(reg_B[5:7]) // byte 0
3'd0:
result[0:7]<=reg_A[0:7];
3'd1:
result[0:7]<={{1{reg_A[0]}},reg_A[0:6]};
3'd2:
result[0:7]<={{2{reg_A[0]}},reg_A[0:5]};
3'd3:
result[0:7]<={{3{reg_A[0]}},reg_A[0:4]};
3'd4:
result[0:7]<={{4{reg_A[0]}},reg_A[0:3]};
3'd5:
result[0:7]<={{5{reg_A[0]}},reg_A[0:2]};
3'd6:
result[0:7]<={{6{reg_A[0]}},reg_A[0:1]};
3'd7:
result[0:7]<={{7{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[13:15]) // byte 1
3'd0:
result[8:15]<=reg_A[8:15];
3'd1:
result[8:15]<={{1{reg_A[8]}},reg_A[8:14]};
3'd2:
result[8:15]<={{2{reg_A[8]}},reg_A[8:13]};
3'd3:
result[8:15]<={{3{reg_A[8]}},reg_A[8:12]};
3'd4:
result[8:15]<={{4{reg_A[8]}},reg_A[8:11]};
3'd5:
result[8:15]<={{5{reg_A[8]}},reg_A[8:10]};
3'd6:
result[8:15]<={{6{reg_A[8]}},reg_A[8:9]};
3'd7:
result[8:15]<={{7{reg_A[8]}},reg_A[8]};
endcase
case(reg_B[21:23]) // byte 2
3'd0:
result[16:23]<=reg_A[16:23];
3'd1:
result[16:23]<={{1{reg_A[16]}},reg_A[16:22]};
3'd2:
result[16:23]<={{2{reg_A[16]}},reg_A[16:21]};
3'd3:
result[16:23]<={{3{reg_A[16]}},reg_A[16:20]};
3'd4:
result[16:23]<={{4{reg_A[16]}},reg_A[16:19]};
3'd5:
result[16:23]<={{5{reg_A[16]}},reg_A[16:18]};
3'd6:
result[16:23]<={{6{reg_A[16]}},reg_A[16:17]};
3'd7:
result[16:23]<={{7{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[29:31]) // byte 3
3'd0:
result[24:31]<=reg_A[24:31];
3'd1:
result[24:31]<={{1{reg_A[24]}},reg_A[24:30]};
3'd2:
result[24:31]<={{2{reg_A[24]}},reg_A[24:29]};
3'd3:
result[24:31]<={{3{reg_A[24]}},reg_A[24:28]};
3'd4:
result[24:31]<={{4{reg_A[24]}},reg_A[24:27]};
3'd5:
result[24:31]<={{5{reg_A[24]}},reg_A[24:26]};
3'd6:
result[24:31]<={{6{reg_A[24]}},reg_A[24:25]};
3'd7:
result[24:31]<={{7{reg_A[24]}},reg_A[24]};
endcase
case(reg_B[37:39]) // byte 4
3'd0:
result[32:39]<=reg_A[32:39];
3'd1:
result[32:39]<={{1{reg_A[32]}},reg_A[32:38]};
3'd2:
result[32:39]<={{2{reg_A[32]}},reg_A[32:37]};
3'd3:
result[32:39]<={{3{reg_A[32]}},reg_A[32:36]};
3'd4:
result[32:39]<={{4{reg_A[32]}},reg_A[32:35]};
3'd5:
result[32:39]<={{5{reg_A[32]}},reg_A[32:34]};
3'd6:
result[32:39]<={{6{reg_A[32]}},reg_A[32:33]};
3'd7:
result[32:39]<={{7{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[45:47]) // byte 5
3'd0:
result[40:47]<=reg_A[40:47];
3'd1:
result[40:47]<={{1{reg_A[40]}},reg_A[40:46]};
3'd2:
result[40:47]<={{2{reg_A[40]}},reg_A[40:45]};
3'd3:
result[40:47]<={{3{reg_A[40]}},reg_A[40:44]};
3'd4:
result[40:47]<={{4{reg_A[40]}},reg_A[40:43]};
3'd5:
result[40:47]<={{5{reg_A[40]}},reg_A[40:42]};
3'd6:
result[40:47]<={{6{reg_A[40]}},reg_A[40:41]};
3'd7:
result[40:47]<={{7{reg_A[40]}},reg_A[40]};
endcase
case(reg_B[53:55]) // byte 6
3'd0:
result[48:55]<=reg_A[48:55];
3'd1:
result[48:55]<={{1{reg_A[48]}},reg_A[48:54]};
3'd2:
result[48:55]<={{2{reg_A[48]}},reg_A[48:53]};
3'd3:
result[48:55]<={{3{reg_A[48]}},reg_A[48:52]};
3'd4:
result[48:55]<={{4{reg_A[48]}},reg_A[48:51]};
3'd5:
result[48:55]<={{5{reg_A[48]}},reg_A[48:50]};
3'd6:
result[48:55]<={{6{reg_A[48]}},reg_A[48:49]};
3'd7:
result[48:55]<={{7{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[61:63]) // byte 7
3'd0:
result[56:63]<=reg_A[56:63];
3'd1:
result[56:63]<={{1{reg_A[56]}},reg_A[56:62]};
3'd2:
result[56:63]<={{2{reg_A[56]}},reg_A[56:61]};
3'd3:
result[56:63]<={{3{reg_A[56]}},reg_A[56:60]};
3'd4:
result[56:63]<={{4{reg_A[56]}},reg_A[56:59]};
3'd5:
result[56:63]<={{5{reg_A[56]}},reg_A[56:58]};
3'd6:
result[56:63]<={{6{reg_A[56]}},reg_A[56:57]};
3'd7:
result[56:63]<={{7{reg_A[56]}},reg_A[56]};
endcase
case(reg_B[69:71]) // byte 8
3'd0:
result[64:71]<=reg_A[64:71];
3'd1:
result[64:71]<={{1{reg_A[64]}},reg_A[64:70]};
3'd2:
result[64:71]<={{2{reg_A[64]}},reg_A[64:69]};
3'd3:
result[64:71]<={{3{reg_A[64]}},reg_A[64:68]};
3'd4:
result[64:71]<={{4{reg_A[64]}},reg_A[64:67]};
3'd5:
result[64:71]<={{5{reg_A[64]}},reg_A[64:66]};
3'd6:
result[64:71]<={{6{reg_A[64]}},reg_A[64:65]};
3'd7:
result[64:71]<={{7{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[77:79]) // byte 9
3'd0:
result[72:79]<=reg_A[72:79];
3'd1:
result[72:79]<={{1{reg_A[72]}},reg_A[72:78]};
3'd2:
result[72:79]<={{2{reg_A[72]}},reg_A[72:77]};
3'd3:
result[72:79]<={{3{reg_A[72]}},reg_A[72:76]};
3'd4:
result[72:79]<={{4{reg_A[72]}},reg_A[72:75]};
3'd5:
result[72:79]<={{5{reg_A[72]}},reg_A[72:74]};
3'd6:
result[72:79]<={{6{reg_A[72]}},reg_A[72:73]};
3'd7:
result[72:79]<={{7{reg_A[72]}},reg_A[72]};
endcase
case(reg_B[85:87]) // byte 10
3'd0:
result[80:87]<=reg_A[80:87];
3'd1:
result[80:87]<={{1{reg_A[80]}},reg_A[80:86]};
3'd2:
result[80:87]<={{2{reg_A[80]}},reg_A[80:85]};
3'd3:
result[80:87]<={{3{reg_A[80]}},reg_A[80:84]};
3'd4:
result[80:87]<={{4{reg_A[80]}},reg_A[80:83]};
3'd5:
result[80:87]<={{5{reg_A[80]}},reg_A[80:82]};
3'd6:
result[80:87]<={{6{reg_A[80]}},reg_A[80:81]};
3'd7:
result[80:87]<={{7{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[93:95]) // byte 11
3'd0:
result[88:95]<=reg_A[88:95];
3'd1:
result[88:95]<={{1{reg_A[88]}},reg_A[88:94]};
3'd2:
result[88:95]<={{2{reg_A[88]}},reg_A[88:93]};
3'd3:
result[88:95]<={{3{reg_A[88]}},reg_A[88:92]};
3'd4:
result[88:95]<={{4{reg_A[88]}},reg_A[88:91]};
3'd5:
result[88:95]<={{5{reg_A[88]}},reg_A[88:90]};
3'd6:
result[88:95]<={{6{reg_A[88]}},reg_A[88:89]};
3'd7:
result[88:95]<={{7{reg_A[88]}},reg_A[88]};
endcase
case(reg_B[101:103]) // byte 12
3'd0:
result[96:103]<=reg_A[96:103];
3'd1:
result[96:103]<={{1{reg_A[96]}},reg_A[96:102]};
3'd2:
result[96:103]<={{2{reg_A[96]}},reg_A[96:101]};
3'd3:
result[96:103]<={{3{reg_A[96]}},reg_A[96:100]};
3'd4:
result[96:103]<={{4{reg_A[96]}},reg_A[96:99]};
3'd5:
result[96:103]<={{5{reg_A[96]}},reg_A[96:98]};
3'd6:
result[96:103]<={{6{reg_A[96]}},reg_A[96:97]};
3'd7:
result[96:103]<={{7{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[109:111]) // byte 13
3'd0:
result[104:111]<=reg_A[104:111];
3'd1:
result[104:111]<={{1{reg_A[104]}},reg_A[104:110]};
3'd2:
result[104:111]<={{2{reg_A[104]}},reg_A[104:109]};
3'd3:
result[104:111]<={{3{reg_A[104]}},reg_A[104:108]};
3'd4:
result[104:111]<={{4{reg_A[104]}},reg_A[104:107]};
3'd5:
result[104:111]<={{5{reg_A[104]}},reg_A[104:106]};
3'd6:
result[104:111]<={{6{reg_A[104]}},reg_A[104:105]};
3'd7:
result[104:111]<={{7{reg_A[104]}},reg_A[104]};
endcase
case(reg_B[117:119]) // byte 14
3'd0:
result[112:119]<=reg_A[112:119];
3'd1:
result[112:119]<={{1{reg_A[112]}},reg_A[112:118]};
3'd2:
result[112:119]<={{2{reg_A[112]}},reg_A[112:117]};
3'd3:
result[112:119]<={{3{reg_A[112]}},reg_A[112:116]};
3'd4:
result[112:119]<={{4{reg_A[112]}},reg_A[112:115]};
3'd5:
result[112:119]<={{5{reg_A[112]}},reg_A[112:114]};
3'd6:
result[112:119]<={{6{reg_A[112]}},reg_A[112:113]};
3'd7:
result[112:119]<={{7{reg_A[112]}},reg_A[112]};
endcase
case(reg_B[125:127]) // byte 15
3'd0:
result[120:127]<=reg_A[120:127];
3'd1:
result[120:127]<={{1{reg_A[120]}},reg_A[120:126]};
3'd2:
result[120:127]<={{2{reg_A[120]}},reg_A[120:125]};
3'd3:
result[120:127]<={{3{reg_A[120]}},reg_A[120:124]};
3'd4:
result[120:127]<={{4{reg_A[120]}},reg_A[120:123]};
3'd5:
result[120:127]<={{5{reg_A[120]}},reg_A[120:122]};
3'd6:
result[120:127]<={{6{reg_A[120]}},reg_A[120:121]};
3'd7:
result[120:127]<={{7{reg_A[120]}},reg_A[120]};
endcase
end
`w16:
begin
case(reg_B[12:15]) // word0
4'd0:
result[0:15]<=reg_A[0:15];
4'd1:
result[0:15]<={{1{reg_A[0]}},reg_A[0:14]};
4'd2:
result[0:15]<={{2{reg_A[0]}},reg_A[0:13]};
4'd3:
result[0:15]<={{3{reg_A[0]}},reg_A[0:12]};
4'd4:
result[0:15]<={{4{reg_A[0]}},reg_A[0:11]};
4'd5:
result[0:15]<={{5{reg_A[0]}},reg_A[0:10]};
4'd6:
result[0:15]<={{6{reg_A[0]}},reg_A[0:9]};
4'd7:
result[0:15]<={{7{reg_A[0]}},reg_A[0:8]};
4'd8:
result[0:15]<={{8{reg_A[0]}},reg_A[0:7]};
4'd9:
result[0:15]<={{9{reg_A[0]}},reg_A[0:6]};
4'd10:
result[0:15]<={{10{reg_A[0]}},reg_A[0:5]};
4'd11:
result[0:15]<={{11{reg_A[0]}},reg_A[0:4]};
4'd12:
result[0:15]<={{12{reg_A[0]}},reg_A[0:3]};
4'd13:
result[0:15]<={{13{reg_A[0]}},reg_A[0:2]};
4'd14:
result[0:15]<={{14{reg_A[0]}},reg_A[0:1]};
4'd15:
result[0:15]<={{15{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[28:31]) //word1
4'd0:
result[16:31]<=reg_A[16:31];
4'd1:
result[16:31]<={{1{reg_A[16]}},reg_A[16:30]};
4'd2:
result[16:31]<={{2{reg_A[16]}},reg_A[16:29]};
4'd3:
result[16:31]<={{3{reg_A[16]}},reg_A[16:28]};
4'd4:
result[16:31]<={{4{reg_A[16]}},reg_A[16:27]};
4'd5:
result[16:31]<={{5{reg_A[16]}},reg_A[16:26]};
4'd6:
result[16:31]<={{6{reg_A[16]}},reg_A[16:25]};
4'd7:
result[16:31]<={{7{reg_A[16]}},reg_A[16:24]};
4'd8:
result[16:31]<={{8{reg_A[16]}},reg_A[16:23]};
4'd9:
result[16:31]<={{9{reg_A[16]}},reg_A[16:22]};
4'd10:
result[16:31]<={{10{reg_A[16]}},reg_A[16:21]};
4'd11:
result[16:31]<={{11{reg_A[16]}},reg_A[16:20]};
4'd12:
result[16:31]<={{12{reg_A[16]}},reg_A[16:19]};
4'd13:
result[16:31]<={{13{reg_A[16]}},reg_A[16:18]};
4'd14:
result[16:31]<={{14{reg_A[16]}},reg_A[16:17]};
4'd15:
result[16:31]<={{15{reg_A[16]}},reg_A[16]};
endcase
case(reg_B[44:47]) // word2
4'd0:
result[32:47]<=reg_A[32:47];
4'd1:
result[32:47]<={{1{reg_A[32]}},reg_A[32:46]};
4'd2:
result[32:47]<={{2{reg_A[32]}},reg_A[32:45]};
4'd3:
result[32:47]<={{3{reg_A[32]}},reg_A[32:44]};
4'd4:
result[32:47]<={{4{reg_A[32]}},reg_A[32:43]};
4'd5:
result[32:47]<={{5{reg_A[32]}},reg_A[32:42]};
4'd6:
result[32:47]<={{6{reg_A[32]}},reg_A[32:41]};
4'd7:
result[32:47]<={{7{reg_A[32]}},reg_A[32:40]};
4'd8:
result[32:47]<={{8{reg_A[32]}},reg_A[32:39]};
4'd9:
result[32:47]<={{9{reg_A[32]}},reg_A[32:38]};
4'd10:
result[32:47]<={{10{reg_A[32]}},reg_A[32:37]};
4'd11:
result[32:47]<={{11{reg_A[32]}},reg_A[32:36]};
4'd12:
result[32:47]<={{12{reg_A[32]}},reg_A[32:35]};
4'd13:
result[32:47]<={{13{reg_A[32]}},reg_A[32:34]};
4'd14:
result[32:47]<={{14{reg_A[32]}},reg_A[32:33]};
4'd15:
result[32:47]<={{15{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[60:63]) // word3
4'd0:
result[48:63]<=reg_A[48:63];
4'd1:
result[48:63]<={{1{reg_A[48]}},reg_A[48:62]};
4'd2:
result[48:63]<={{2{reg_A[48]}},reg_A[48:61]};
4'd3:
result[48:63]<={{3{reg_A[48]}},reg_A[48:60]};
4'd4:
result[48:63]<={{4{reg_A[48]}},reg_A[48:59]};
4'd5:
result[48:63]<={{5{reg_A[48]}},reg_A[48:58]};
4'd6:
result[48:63]<={{6{reg_A[48]}},reg_A[48:57]};
4'd7:
result[48:63]<={{7{reg_A[48]}},reg_A[48:56]};
4'd8:
result[48:63]<={{8{reg_A[48]}},reg_A[48:55]};
4'd9:
result[48:63]<={{9{reg_A[48]}},reg_A[48:54]};
4'd10:
result[48:63]<={{10{reg_A[48]}},reg_A[48:53]};
4'd11:
result[48:63]<={{11{reg_A[48]}},reg_A[48:52]};
4'd12:
result[48:63]<={{12{reg_A[48]}},reg_A[48:51]};
4'd13:
result[48:63]<={{13{reg_A[48]}},reg_A[48:50]};
4'd14:
result[48:63]<={{14{reg_A[48]}},reg_A[48:49]};
4'd15:
result[48:63]<={{15{reg_A[48]}},reg_A[48]};
endcase
case(reg_B[76:79]) // word4
4'd0:
result[64:79]<=reg_A[64:79];
4'd1:
result[64:79]<={{1{reg_A[64]}},reg_A[64:78]};
4'd2:
result[64:79]<={{2{reg_A[64]}},reg_A[64:77]};
4'd3:
result[64:79]<={{3{reg_A[64]}},reg_A[64:76]};
4'd4:
result[64:79]<={{4{reg_A[64]}},reg_A[64:75]};
4'd5:
result[64:79]<={{5{reg_A[64]}},reg_A[64:74]};
4'd6:
result[64:79]<={{6{reg_A[64]}},reg_A[64:73]};
4'd7:
result[64:79]<={{7{reg_A[64]}},reg_A[64:72]};
4'd8:
result[64:79]<={{8{reg_A[64]}},reg_A[64:71]};
4'd9:
result[64:79]<={{9{reg_A[64]}},reg_A[64:70]};
4'd10:
result[64:79]<={{10{reg_A[64]}},reg_A[64:69]};
4'd11:
result[64:79]<={{11{reg_A[64]}},reg_A[64:68]};
4'd12:
result[64:79]<={{12{reg_A[64]}},reg_A[64:67]};
4'd13:
result[64:79]<={{13{reg_A[64]}},reg_A[64:66]};
4'd14:
result[64:79]<={{14{reg_A[64]}},reg_A[64:65]};
4'd15:
result[64:79]<={{15{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[92:95]) // word5
4'd0:
result[80:95]<=reg_A[80:95];
4'd1:
result[80:95]<={{1{reg_A[80]}},reg_A[80:94]};
4'd2:
result[80:95]<={{2{reg_A[80]}},reg_A[80:93]};
4'd3:
result[80:95]<={{3{reg_A[80]}},reg_A[80:92]};
4'd4:
result[80:95]<={{4{reg_A[80]}},reg_A[80:91]};
4'd5:
result[80:95]<={{5{reg_A[80]}},reg_A[80:90]};
4'd6:
result[80:95]<={{6{reg_A[80]}},reg_A[80:89]};
4'd7:
result[80:95]<={{7{reg_A[80]}},reg_A[80:88]};
4'd8:
result[80:95]<={{8{reg_A[80]}},reg_A[80:87]};
4'd9:
result[80:95]<={{9{reg_A[80]}},reg_A[80:86]};
4'd10:
result[80:95]<={{10{reg_A[80]}},reg_A[80:85]};
4'd11:
result[80:95]<={{11{reg_A[80]}},reg_A[80:84]};
4'd12:
result[80:95]<={{12{reg_A[80]}},reg_A[80:83]};
4'd13:
result[80:95]<={{13{reg_A[80]}},reg_A[80:82]};
4'd14:
result[80:95]<={{14{reg_A[80]}},reg_A[80:81]};
4'd15:
result[80:95]<={{15{reg_A[80]}},reg_A[80]};
endcase
case(reg_B[92:111]) // word6
4'd0:
result[96:111]<=reg_A[96:111];
4'd1:
result[96:111]<={{1{reg_A[96]}},reg_A[96:110]};
4'd2:
result[96:111]<={{2{reg_A[96]}},reg_A[96:109]};
4'd3:
result[96:111]<={{3{reg_A[96]}},reg_A[96:108]};
4'd4:
result[96:111]<={{4{reg_A[96]}},reg_A[96:107]};
4'd5:
result[96:111]<={{5{reg_A[96]}},reg_A[96:106]};
4'd6:
result[96:111]<={{6{reg_A[96]}},reg_A[96:105]};
4'd7:
result[96:111]<={{7{reg_A[96]}},reg_A[96:104]};
4'd8:
result[96:111]<={{8{reg_A[96]}},reg_A[96:103]};
4'd9:
result[96:111]<={{9{reg_A[96]}},reg_A[96:102]};
4'd10:
result[96:111]<={{10{reg_A[96]}},reg_A[96:101]};
4'd11:
result[96:111]<={{11{reg_A[96]}},reg_A[96:100]};
4'd12:
result[96:111]<={{12{reg_A[96]}},reg_A[96:99]};
4'd13:
result[96:111]<={{13{reg_A[96]}},reg_A[96:98]};
4'd14:
result[96:111]<={{14{reg_A[96]}},reg_A[96:97]};
4'd15:
result[96:111]<={{15{reg_A[96]}},reg_A[96]};
endcase
case(reg_B[92:127]) // word7
4'd0:
result[112:127]<=reg_A[112:127];
4'd1:
result[112:127]<={{1{reg_A[112]}},reg_A[112:126]};
4'd2:
result[112:127]<={{2{reg_A[112]}},reg_A[112:125]};
4'd3:
result[112:127]<={{3{reg_A[112]}},reg_A[112:124]};
4'd4:
result[112:127]<={{4{reg_A[112]}},reg_A[112:123]};
4'd5:
result[112:127]<={{5{reg_A[112]}},reg_A[112:122]};
4'd6:
result[112:127]<={{6{reg_A[112]}},reg_A[112:121]};
4'd7:
result[112:127]<={{7{reg_A[112]}},reg_A[112:120]};
4'd8:
result[112:127]<={{8{reg_A[112]}},reg_A[112:119]};
4'd9:
result[112:127]<={{9{reg_A[112]}},reg_A[112:118]};
4'd10:
result[112:127]<={{10{reg_A[112]}},reg_A[112:117]};
4'd11:
result[112:127]<={{11{reg_A[112]}},reg_A[112:116]};
4'd12:
result[112:127]<={{12{reg_A[112]}},reg_A[112:115]};
4'd13:
result[112:127]<={{13{reg_A[112]}},reg_A[112:114]};
4'd14:
result[112:127]<={{14{reg_A[112]}},reg_A[112:113]};
4'd15:
result[112:127]<={{15{reg_A[112]}},reg_A[112]};
endcase
end
`w32:
begin
case(reg_B[27:31])
5'd0:
result[0:31]<=reg_A[0:31];
5'd1:
result[0:31]<={{1{reg_A[0]}},reg_A[0:30]};
5'd2:
result[0:31]<={{2{reg_A[0]}},reg_A[0:29]};
5'd3:
result[0:31]<={{3{reg_A[0]}},reg_A[0:28]};
5'd4:
result[0:31]<={{4{reg_A[0]}},reg_A[0:27]};
5'd5:
result[0:31]<={{5{reg_A[0]}},reg_A[0:26]};
5'd6:
result[0:31]<={{6{reg_A[0]}},reg_A[0:25]};
5'd7:
result[0:31]<={{7{reg_A[0]}},reg_A[0:24]};
5'd8:
result[0:31]<={{8{reg_A[0]}},reg_A[0:23]};
5'd9:
result[0:31]<={{9{reg_A[0]}},reg_A[0:22]};
5'd10:
result[0:31]<={{10{reg_A[0]}},reg_A[0:21]};
5'd11:
result[0:31]<={{11{reg_A[0]}},reg_A[0:20]};
5'd12:
result[0:31]<={{12{reg_A[0]}},reg_A[0:19]};
5'd13:
result[0:31]<={{13{reg_A[0]}},reg_A[0:18]};
5'd14:
result[0:31]<={{14{reg_A[0]}},reg_A[0:17]};
5'd15:
result[0:31]<={{15{reg_A[0]}},reg_A[0:16]};
5'd16:
result[0:31]<={{16{reg_A[0]}},reg_A[0:15]};
5'd17:
result[0:31]<={{17{reg_A[0]}},reg_A[0:14]};
5'd18:
result[0:31]<={{18{reg_A[0]}},reg_A[0:13]};
5'd19:
result[0:31]<={{19{reg_A[0]}},reg_A[0:12]};
5'd20:
result[0:31]<={{20{reg_A[0]}},reg_A[0:11]};
5'd21:
result[0:31]<={{21{reg_A[0]}},reg_A[0:10]};
5'd22:
result[0:31]<={{22{reg_A[0]}},reg_A[0:9]};
5'd23:
result[0:31]<={{23{reg_A[0]}},reg_A[0:8]};
5'd24:
result[0:31]<={{24{reg_A[0]}},reg_A[0:7]};
5'd25:
result[0:31]<={{25{reg_A[0]}},reg_A[0:6]};
5'd26:
result[0:31]<={{26{reg_A[0]}},reg_A[0:5]};
5'd27:
result[0:31]<={{27{reg_A[0]}},reg_A[0:4]};
5'd28:
result[0:31]<={{28{reg_A[0]}},reg_A[0:3]};
5'd29:
result[0:31]<={{29{reg_A[0]}},reg_A[0:2]};
5'd30:
result[0:31]<={{30{reg_A[0]}},reg_A[0:1]};
5'd31:
result[0:31]<={{31{reg_A[0]}},reg_A[0]};
endcase
case(reg_B[59:63])
5'd0:
result[32:63]<=reg_A[32:63];
5'd1:
result[32:63]<={{1{reg_A[32]}},reg_A[32:62]};
5'd2:
result[32:63]<={{2{reg_A[32]}},reg_A[32:61]};
5'd3:
result[32:63]<={{3{reg_A[32]}},reg_A[32:60]};
5'd4:
result[32:63]<={{4{reg_A[32]}},reg_A[32:59]};
5'd5:
result[32:63]<={{5{reg_A[32]}},reg_A[32:58]};
5'd6:
result[32:63]<={{6{reg_A[32]}},reg_A[32:57]};
5'd7:
result[32:63]<={{7{reg_A[32]}},reg_A[32:56]};
5'd8:
result[32:63]<={{8{reg_A[32]}},reg_A[32:55]};
5'd9:
result[32:63]<={{9{reg_A[32]}},reg_A[32:54]};
5'd10:
result[32:63]<={{10{reg_A[32]}},reg_A[32:53]};
5'd11:
result[32:63]<={{11{reg_A[32]}},reg_A[32:52]};
5'd12:
result[32:63]<={{12{reg_A[32]}},reg_A[32:51]};
5'd13:
result[32:63]<={{13{reg_A[32]}},reg_A[32:50]};
5'd14:
result[32:63]<={{14{reg_A[32]}},reg_A[32:49]};
5'd15:
result[32:63]<={{15{reg_A[32]}},reg_A[32:48]};
5'd16:
result[32:63]<={{16{reg_A[32]}},reg_A[32:47]};
5'd17:
result[32:63]<={{17{reg_A[32]}},reg_A[32:46]};
5'd18:
result[32:63]<={{18{reg_A[32]}},reg_A[32:45]};
5'd19:
result[32:63]<={{19{reg_A[32]}},reg_A[32:44]};
5'd20:
result[32:63]<={{20{reg_A[32]}},reg_A[32:43]};
5'd21:
result[32:63]<={{21{reg_A[32]}},reg_A[32:42]};
5'd22:
result[32:63]<={{22{reg_A[32]}},reg_A[32:41]};
5'd23:
result[32:63]<={{23{reg_A[32]}},reg_A[32:40]};
5'd24:
result[32:63]<={{24{reg_A[32]}},reg_A[32:39]};
5'd25:
result[32:63]<={{25{reg_A[32]}},reg_A[32:38]};
5'd26:
result[32:63]<={{26{reg_A[32]}},reg_A[32:37]};
5'd27:
result[32:63]<={{27{reg_A[32]}},reg_A[32:36]};
5'd28:
result[32:63]<={{28{reg_A[32]}},reg_A[32:35]};
5'd29:
result[32:63]<={{29{reg_A[32]}},reg_A[32:34]};
5'd30:
result[32:63]<={{30{reg_A[32]}},reg_A[32:33]};
5'd31:
result[32:63]<={{31{reg_A[32]}},reg_A[32]};
endcase
case(reg_B[91:95])
5'd0:
result[64:95]<=reg_A[64:95];
5'd1:
result[64:95]<={{1{reg_A[64]}},reg_A[64:94]};
5'd2:
result[64:95]<={{2{reg_A[64]}},reg_A[64:93]};
5'd3:
result[64:95]<={{3{reg_A[64]}},reg_A[64:92]};
5'd4:
result[64:95]<={{4{reg_A[64]}},reg_A[64:91]};
5'd5:
result[64:95]<={{5{reg_A[64]}},reg_A[64:90]};
5'd6:
result[64:95]<={{6{reg_A[64]}},reg_A[64:89]};
5'd7:
result[64:95]<={{7{reg_A[64]}},reg_A[64:88]};
5'd8:
result[64:95]<={{8{reg_A[64]}},reg_A[64:87]};
5'd9:
result[64:95]<={{9{reg_A[64]}},reg_A[64:86]};
5'd10:
result[64:95]<={{10{reg_A[64]}},reg_A[64:85]};
5'd11:
result[64:95]<={{11{reg_A[64]}},reg_A[64:84]};
5'd12:
result[64:95]<={{12{reg_A[64]}},reg_A[64:83]};
5'd13:
result[64:95]<={{13{reg_A[64]}},reg_A[64:82]};
5'd14:
result[64:95]<={{14{reg_A[64]}},reg_A[64:81]};
5'd15:
result[64:95]<={{15{reg_A[64]}},reg_A[64:80]};
5'd16:
result[64:95]<={{16{reg_A[64]}},reg_A[64:79]};
5'd17:
result[64:95]<={{17{reg_A[64]}},reg_A[64:78]};
5'd18:
result[64:95]<={{18{reg_A[64]}},reg_A[64:77]};
5'd19:
result[64:95]<={{19{reg_A[64]}},reg_A[64:76]};
5'd20:
result[64:95]<={{20{reg_A[64]}},reg_A[64:75]};
5'd21:
result[64:95]<={{21{reg_A[64]}},reg_A[64:74]};
5'd22:
result[64:95]<={{22{reg_A[64]}},reg_A[64:73]};
5'd23:
result[64:95]<={{23{reg_A[64]}},reg_A[64:72]};
5'd24:
result[64:95]<={{24{reg_A[64]}},reg_A[64:71]};
5'd25:
result[64:95]<={{25{reg_A[64]}},reg_A[64:70]};
5'd26:
result[64:95]<={{26{reg_A[64]}},reg_A[64:69]};
5'd27:
result[64:95]<={{27{reg_A[64]}},reg_A[64:68]};
5'd28:
result[64:95]<={{28{reg_A[64]}},reg_A[64:67]};
5'd29:
result[64:95]<={{29{reg_A[64]}},reg_A[64:66]};
5'd30:
result[64:95]<={{30{reg_A[64]}},reg_A[64:65]};
5'd31:
result[64:95]<={{31{reg_A[64]}},reg_A[64]};
endcase
case(reg_B[123:127])
5'd0:
result[96:127]<=reg_A[96:127];
5'd1:
result[96:127]<={{1{reg_A[96]}},reg_A[96:126]};
5'd2:
result[96:127]<={{2{reg_A[96]}},reg_A[96:125]};
5'd3:
result[96:127]<={{3{reg_A[96]}},reg_A[96:124]};
5'd4:
result[96:127]<={{4{reg_A[96]}},reg_A[96:123]};
5'd5:
result[96:127]<={{5{reg_A[96]}},reg_A[96:122]};
5'd6:
result[96:127]<={{6{reg_A[96]}},reg_A[96:121]};
5'd7:
result[96:127]<={{7{reg_A[96]}},reg_A[96:120]};
5'd8:
result[96:127]<={{8{reg_A[96]}},reg_A[96:119]};
5'd9:
result[96:127]<={{9{reg_A[96]}},reg_A[96:118]};
5'd10:
result[96:127]<={{10{reg_A[96]}},reg_A[96:117]};
5'd11:
result[96:127]<={{11{reg_A[96]}},reg_A[96:116]};
5'd12:
result[96:127]<={{12{reg_A[96]}},reg_A[96:115]};
5'd13:
result[96:127]<={{13{reg_A[96]}},reg_A[96:114]};
5'd14:
result[96:127]<={{14{reg_A[96]}},reg_A[96:113]};
5'd15:
result[96:127]<={{15{reg_A[96]}},reg_A[96:112]};
5'd16:
result[96:127]<={{16{reg_A[96]}},reg_A[96:111]};
5'd17:
result[96:127]<={{17{reg_A[96]}},reg_A[96:110]};
5'd18:
result[96:127]<={{18{reg_A[96]}},reg_A[96:109]};
5'd19:
result[96:127]<={{19{reg_A[96]}},reg_A[96:108]};
5'd20:
result[96:127]<={{20{reg_A[96]}},reg_A[96:107]};
5'd21:
result[96:127]<={{21{reg_A[96]}},reg_A[96:106]};
5'd22:
result[96:127]<={{22{reg_A[96]}},reg_A[96:105]};
5'd23:
result[96:127]<={{23{reg_A[96]}},reg_A[96:104]};
5'd24:
result[96:127]<={{24{reg_A[96]}},reg_A[96:103]};
5'd25:
result[96:127]<={{25{reg_A[96]}},reg_A[96:102]};
5'd26:
result[96:127]<={{26{reg_A[96]}},reg_A[96:101]};
5'd27:
result[96:127]<={{27{reg_A[96]}},reg_A[96:100]};
5'd28:
result[96:127]<={{28{reg_A[96]}},reg_A[96:99]};
5'd29:
result[96:127]<={{29{reg_A[96]}},reg_A[96:98]};
5'd30:
result[96:127]<={{30{reg_A[96]}},reg_A[96:97]};
5'd31:
result[96:127]<={{31{reg_A[96]}},reg_A[96]};
endcase
end
endcase
end
// ==================================================================
default:
begin
// Default arithmetic/logic operation
result<=128'd0;
end
endcase
end
endmodule
|
(************************************************************************)
(* v * The Coq Proof Assistant / The Coq Development Team *)
(* <O___,, * INRIA - CNRS - LIX - LRI - PPS - Copyright 1999-2015 *)
(* \VV/ **************************************************************)
(* // * This file is distributed under the terms of the *)
(* * GNU Lesser General Public License Version 2.1 *)
(************************************************************************)
Require Import
Bool ZAxioms ZMulOrder ZPow ZDivFloor ZSgnAbs ZParity NZLog.
(** Derived properties of bitwise operations *)
Module Type ZBitsProp
(Import A : ZAxiomsSig')
(Import B : ZMulOrderProp A)
(Import C : ZParityProp A B)
(Import D : ZSgnAbsProp A B)
(Import E : ZPowProp A B C D)
(Import F : ZDivProp A B D)
(Import G : NZLog2Prop A A A B E).
Include BoolEqualityFacts A.
Ltac order_nz := try apply pow_nonzero; order'.
Ltac order_pos' := try apply abs_nonneg; order_pos.
Hint Rewrite div_0_l mod_0_l div_1_r mod_1_r : nz.
(** Some properties of power and division *)
Lemma pow_sub_r : forall a b c, a~=0 -> 0<=c<=b -> a^(b-c) == a^b / a^c.
Proof.
intros a b c Ha (H,H'). rewrite <- (sub_simpl_r b c) at 2.
rewrite pow_add_r; trivial.
rewrite div_mul. reflexivity.
now apply pow_nonzero.
now apply le_0_sub.
Qed.
Lemma pow_div_l : forall a b c, b~=0 -> 0<=c -> a mod b == 0 ->
(a/b)^c == a^c / b^c.
Proof.
intros a b c Hb Hc H. rewrite (div_mod a b Hb) at 2.
rewrite H, add_0_r, pow_mul_l, mul_comm, div_mul. reflexivity.
now apply pow_nonzero.
Qed.
(** An injection from bits [true] and [false] to numbers 1 and 0.
We declare it as a (local) coercion for shorter statements. *)
Definition b2z (b:bool) := if b then 1 else 0.
Local Coercion b2z : bool >-> t.
Instance b2z_wd : Proper (Logic.eq ==> eq) b2z := _.
Lemma exists_div2 a : exists a' (b:bool), a == 2*a' + b.
Proof.
elim (Even_or_Odd a); [intros (a',H)| intros (a',H)].
exists a'. exists false. now nzsimpl.
exists a'. exists true. now simpl.
Qed.
(** We can compact [testbit_odd_0] [testbit_even_0]
[testbit_even_succ] [testbit_odd_succ] in only two lemmas. *)
Lemma testbit_0_r a (b:bool) : testbit (2*a+b) 0 = b.
Proof.
destruct b; simpl; rewrite ?add_0_r.
apply testbit_odd_0.
apply testbit_even_0.
Qed.
Lemma testbit_succ_r a (b:bool) n : 0<=n ->
testbit (2*a+b) (succ n) = testbit a n.
Proof.
destruct b; simpl; rewrite ?add_0_r.
now apply testbit_odd_succ.
now apply testbit_even_succ.
Qed.
(** Alternative caracterisations of [testbit] *)
(** This concise equation could have been taken as specification
for testbit in the interface, but it would have been hard to
implement with little initial knowledge about div and mod *)
Lemma testbit_spec' a n : 0<=n -> a.[n] == (a / 2^n) mod 2.
Proof.
intro Hn. revert a. apply le_ind with (4:=Hn).
solve_proper.
intros a. nzsimpl.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_0_r. apply mod_unique with a'; trivial.
left. destruct b; split; simpl; order'.
clear n Hn. intros n Hn IH a.
destruct (exists_div2 a) as (a' & b & H). rewrite H at 1.
rewrite testbit_succ_r, IH by trivial. f_equiv.
rewrite pow_succ_r, <- div_div by order_pos. f_equiv.
apply div_unique with b; trivial.
left. destruct b; split; simpl; order'.
Qed.
(** This caracterisation that uses only basic operations and
power was initially taken as specification for testbit.
We describe [a] as having a low part and a high part, with
the corresponding bit in the middle. This caracterisation
is moderatly complex to implement, but also moderately
usable... *)
Lemma testbit_spec a n : 0<=n ->
exists l h, 0<=l<2^n /\ a == l + (a.[n] + 2*h)*2^n.
Proof.
intro Hn. exists (a mod 2^n). exists (a / 2^n / 2). split.
apply mod_pos_bound; order_pos.
rewrite add_comm, mul_comm, (add_comm a.[n]).
rewrite (div_mod a (2^n)) at 1 by order_nz. do 2 f_equiv.
rewrite testbit_spec' by trivial. apply div_mod. order'.
Qed.
Lemma testbit_true : forall a n, 0<=n ->
(a.[n] = true <-> (a / 2^n) mod 2 == 1).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_false : forall a n, 0<=n ->
(a.[n] = false <-> (a / 2^n) mod 2 == 0).
Proof.
intros a n Hn.
rewrite <- testbit_spec' by trivial.
destruct a.[n]; split; simpl; now try order'.
Qed.
Lemma testbit_eqb : forall a n, 0<=n ->
a.[n] = eqb ((a / 2^n) mod 2) 1.
Proof.
intros a n Hn.
apply eq_true_iff_eq. now rewrite testbit_true, eqb_eq.
Qed.
(** Results about the injection [b2z] *)
Lemma b2z_inj : forall (a0 b0:bool), a0 == b0 -> a0 = b0.
Proof.
intros [|] [|]; simpl; trivial; order'.
Qed.
Lemma add_b2z_double_div2 : forall (a0:bool) a, (a0+2*a)/2 == a.
Proof.
intros a0 a. rewrite mul_comm, div_add by order'.
now rewrite div_small, add_0_l by (destruct a0; split; simpl; order').
Qed.
Lemma add_b2z_double_bit0 : forall (a0:bool) a, (a0+2*a).[0] = a0.
Proof.
intros a0 a. apply b2z_inj.
rewrite testbit_spec' by order.
nzsimpl. rewrite mul_comm, mod_add by order'.
now rewrite mod_small by (destruct a0; split; simpl; order').
Qed.
Lemma b2z_div2 : forall (a0:bool), a0/2 == 0.
Proof.
intros a0. rewrite <- (add_b2z_double_div2 a0 0). now nzsimpl.
Qed.
Lemma b2z_bit0 : forall (a0:bool), a0.[0] = a0.
Proof.
intros a0. rewrite <- (add_b2z_double_bit0 a0 0) at 2. now nzsimpl.
Qed.
(** The specification of testbit by low and high parts is complete *)
Lemma testbit_unique : forall a n (a0:bool) l h,
0<=l<2^n -> a == l + (a0 + 2*h)*2^n -> a.[n] = a0.
Proof.
intros a n a0 l h Hl EQ.
assert (0<=n).
destruct (le_gt_cases 0 n) as [Hn|Hn]; trivial.
rewrite pow_neg_r in Hl by trivial. destruct Hl; order.
apply b2z_inj. rewrite testbit_spec' by trivial.
symmetry. apply mod_unique with h.
left; destruct a0; simpl; split; order'.
symmetry. apply div_unique with l.
now left.
now rewrite add_comm, (add_comm _ a0), mul_comm.
Qed.
(** All bits of number 0 are 0 *)
Lemma bits_0 : forall n, 0.[n] = false.
Proof.
intros n.
destruct (le_gt_cases 0 n).
apply testbit_false; trivial. nzsimpl; order_nz.
now apply testbit_neg_r.
Qed.
(** For negative numbers, we are actually doing two's complement *)
Lemma bits_opp : forall a n, 0<=n -> (-a).[n] = negb (P a).[n].
Proof.
intros a n Hn.
destruct (testbit_spec (-a) n Hn) as (l & h & Hl & EQ).
fold (b2z (-a).[n]) in EQ.
apply negb_sym.
apply testbit_unique with (2^n-l-1) (-h-1).
split.
apply lt_succ_r. rewrite sub_1_r, succ_pred. now apply lt_0_sub.
apply le_succ_l. rewrite sub_1_r, succ_pred. apply le_sub_le_add_r.
rewrite <- (add_0_r (2^n)) at 1. now apply add_le_mono_l.
rewrite <- add_sub_swap, sub_1_r. f_equiv.
apply opp_inj. rewrite opp_add_distr, opp_sub_distr.
rewrite (add_comm _ l), <- add_assoc.
rewrite EQ at 1. apply add_cancel_l.
rewrite <- opp_add_distr.
rewrite <- (mul_1_l (2^n)) at 2. rewrite <- mul_add_distr_r.
rewrite <- mul_opp_l.
f_equiv.
rewrite !opp_add_distr.
rewrite <- mul_opp_r.
rewrite opp_sub_distr, opp_involutive.
rewrite (add_comm h).
rewrite mul_add_distr_l.
rewrite !add_assoc.
apply add_cancel_r.
rewrite mul_1_r.
rewrite add_comm, add_assoc, !add_opp_r, sub_1_r, two_succ, pred_succ.
destruct (-a).[n]; simpl. now rewrite sub_0_r. now nzsimpl'.
Qed.
(** All bits of number (-1) are 1 *)
Lemma bits_m1 : forall n, 0<=n -> (-1).[n] = true.
Proof.
intros. now rewrite bits_opp, one_succ, pred_succ, bits_0.
Qed.
(** Various ways to refer to the lowest bit of a number *)
Lemma bit0_odd : forall a, a.[0] = odd a.
Proof.
intros. symmetry.
destruct (exists_div2 a) as (a' & b & EQ).
rewrite EQ, testbit_0_r, add_comm, odd_add_mul_2.
destruct b; simpl; apply odd_1 || apply odd_0.
Qed.
Lemma bit0_eqb : forall a, a.[0] = eqb (a mod 2) 1.
Proof.
intros a. rewrite testbit_eqb by order. now nzsimpl.
Qed.
Lemma bit0_mod : forall a, a.[0] == a mod 2.
Proof.
intros a. rewrite testbit_spec' by order. now nzsimpl.
Qed.
(** Hence testing a bit is equivalent to shifting and testing parity *)
Lemma testbit_odd : forall a n, a.[n] = odd (a>>n).
Proof.
intros. now rewrite <- bit0_odd, shiftr_spec, add_0_l.
Qed.
(** [log2] gives the highest nonzero bit of positive numbers *)
Lemma bit_log2 : forall a, 0<a -> a.[log2 a] = true.
Proof.
intros a Ha.
assert (Ha' := log2_nonneg a).
destruct (log2_spec_alt a Ha) as (r & EQ & Hr).
rewrite EQ at 1.
rewrite testbit_true, add_comm by trivial.
rewrite <- (mul_1_l (2^log2 a)) at 1.
rewrite div_add by order_nz.
rewrite div_small; trivial.
rewrite add_0_l. apply mod_small. split; order'.
Qed.
Lemma bits_above_log2 : forall a n, 0<=a -> log2 a < n ->
a.[n] = false.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 a). apply log2_nonneg. order'.
rewrite testbit_false by trivial.
rewrite div_small. nzsimpl; order'.
split. order. apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
(** Hence the number of bits of [a] is [1+log2 a]
(see [Pos.size_nat] and [Pos.size]).
*)
(** For negative numbers, things are the other ways around:
log2 gives the highest zero bit (for numbers below -1).
*)
Lemma bit_log2_neg : forall a, a < -1 -> a.[log2 (P (-a))] = false.
Proof.
intros a Ha.
rewrite <- (opp_involutive a) at 1.
rewrite bits_opp.
apply negb_false_iff.
apply bit_log2.
apply opp_lt_mono in Ha. rewrite opp_involutive in Ha.
apply lt_succ_lt_pred. now rewrite <- one_succ.
apply log2_nonneg.
Qed.
Lemma bits_above_log2_neg : forall a n, a < 0 -> log2 (P (-a)) < n ->
a.[n] = true.
Proof.
intros a n Ha H.
assert (Hn : 0<=n).
transitivity (log2 (P (-a))). apply log2_nonneg. order'.
rewrite <- (opp_involutive a), bits_opp, negb_true_iff by trivial.
apply bits_above_log2; trivial.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
(** Accesing a high enough bit of a number gives its sign *)
Lemma bits_iff_nonneg : forall a n, log2 (abs a) < n ->
(0<=a <-> a.[n] = false).
Proof.
intros a n Hn. split; intros H.
rewrite abs_eq in Hn; trivial. now apply bits_above_log2.
destruct (le_gt_cases 0 a); trivial.
rewrite abs_neq in Hn by order.
rewrite bits_above_log2_neg in H; try easy.
apply le_lt_trans with (log2 (-a)); trivial.
apply log2_le_mono. apply le_pred_l.
Qed.
Lemma bits_iff_nonneg' : forall a,
0<=a <-> a.[S (log2 (abs a))] = false.
Proof.
intros. apply bits_iff_nonneg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_nonneg_ex : forall a,
0<=a <-> (exists k, forall m, k<m -> a.[m] = false).
Proof.
intros a. split.
intros Ha. exists (log2 a). intros m Hm. now apply bits_above_log2.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_nonneg', Hk, lt_succ_r.
apply (bits_iff_nonneg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg : forall a n, log2 (abs a) < n ->
(a<0 <-> a.[n] = true).
Proof.
intros a n Hn.
now rewrite lt_nge, <- not_false_iff_true, (bits_iff_nonneg a n).
Qed.
Lemma bits_iff_neg' : forall a, a<0 <-> a.[S (log2 (abs a))] = true.
Proof.
intros. apply bits_iff_neg. apply lt_succ_diag_r.
Qed.
Lemma bits_iff_neg_ex : forall a,
a<0 <-> (exists k, forall m, k<m -> a.[m] = true).
Proof.
intros a. split.
intros Ha. exists (log2 (P (-a))). intros m Hm. now apply bits_above_log2_neg.
intros (k,Hk). destruct (le_gt_cases k (log2 (abs a))).
now apply bits_iff_neg', Hk, lt_succ_r.
apply (bits_iff_neg a (S k)).
now apply lt_succ_r, lt_le_incl.
apply Hk. apply lt_succ_diag_r.
Qed.
(** Testing bits after division or multiplication by a power of two *)
Lemma div2_bits : forall a n, 0<=n -> (a/2).[n] = a.[S n].
Proof.
intros a n Hn.
apply eq_true_iff_eq. rewrite 2 testbit_true by order_pos.
rewrite pow_succ_r by trivial.
now rewrite div_div by order_pos.
Qed.
Lemma div_pow2_bits : forall a n m, 0<=n -> 0<=m -> (a/2^n).[m] = a.[m+n].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m Hm. now nzsimpl.
clear n Hn. intros n Hn IH a m Hm. nzsimpl; trivial.
rewrite <- div_div by order_pos.
now rewrite IH, div2_bits by order_pos.
Qed.
Lemma double_bits_succ : forall a n, (2*a).[S n] = a.[n].
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now rewrite <- div2_bits, mul_comm, div_mul by order'.
rewrite (testbit_neg_r a n Hn).
apply le_succ_l in Hn. le_elim Hn.
now rewrite testbit_neg_r.
now rewrite Hn, bit0_odd, odd_mul, odd_2.
Qed.
Lemma double_bits : forall a n, (2*a).[n] = a.[P n].
Proof.
intros a n. rewrite <- (succ_pred n) at 1. apply double_bits_succ.
Qed.
Lemma mul_pow2_bits_add : forall a n m, 0<=n -> (a*2^n).[n+m] = a.[m].
Proof.
intros a n m Hn. revert a m. apply le_ind with (4:=Hn).
solve_proper.
intros a m. now nzsimpl.
clear n Hn. intros n Hn IH a m. nzsimpl; trivial.
rewrite mul_assoc, (mul_comm _ 2), <- mul_assoc.
now rewrite double_bits_succ.
Qed.
Lemma mul_pow2_bits : forall a n m, 0<=n -> (a*2^n).[m] = a.[m-n].
Proof.
intros.
rewrite <- (add_simpl_r m n) at 1. rewrite add_sub_swap, add_comm.
now apply mul_pow2_bits_add.
Qed.
Lemma mul_pow2_bits_low : forall a n m, m<n -> (a*2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n).
rewrite mul_pow2_bits by trivial.
apply testbit_neg_r. now apply lt_sub_0.
now rewrite pow_neg_r, mul_0_r, bits_0.
Qed.
(** Selecting the low part of a number can be done by a modulo *)
Lemma mod_pow2_bits_high : forall a n m, 0<=n<=m ->
(a mod 2^n).[m] = false.
Proof.
intros a n m (Hn,H).
destruct (mod_pos_bound a (2^n)) as [LE LT]. order_pos.
le_elim LE.
apply bits_above_log2; try order.
apply lt_le_trans with n; trivial.
apply log2_lt_pow2; trivial.
now rewrite <- LE, bits_0.
Qed.
Lemma mod_pow2_bits_low : forall a n m, m<n ->
(a mod 2^n).[m] = a.[m].
Proof.
intros a n m H.
destruct (le_gt_cases 0 m) as [Hm|Hm]; [|now rewrite !testbit_neg_r].
rewrite testbit_eqb; trivial.
rewrite <- (mod_add _ (2^(P (n-m))*(a/2^n))) by order'.
rewrite <- div_add by order_nz.
rewrite (mul_comm _ 2), mul_assoc, <- pow_succ_r, succ_pred.
rewrite mul_comm, mul_assoc, <- pow_add_r, (add_comm m), sub_add; trivial.
rewrite add_comm, <- div_mod by order_nz.
symmetry. apply testbit_eqb; trivial.
apply le_0_sub; order.
now apply lt_le_pred, lt_0_sub.
Qed.
(** We now prove that having the same bits implies equality.
For that we use a notion of equality over functional
streams of bits. *)
Definition eqf (f g:t -> bool) := forall n:t, f n = g n.
Instance eqf_equiv : Equivalence eqf.
Proof.
split; congruence.
Qed.
Local Infix "===" := eqf (at level 70, no associativity).
Instance testbit_eqf : Proper (eq==>eqf) testbit.
Proof.
intros a a' Ha n. now rewrite Ha.
Qed.
(** Only zero corresponds to the always-false stream. *)
Lemma bits_inj_0 :
forall a, (forall n, a.[n] = false) -> a == 0.
Proof.
intros a H. destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]]; trivial.
apply (bits_above_log2_neg a (S (log2 (P (-a))))) in Ha.
now rewrite H in Ha.
apply lt_succ_diag_r.
apply bit_log2 in Ha. now rewrite H in Ha.
Qed.
(** If two numbers produce the same stream of bits, they are equal. *)
Lemma bits_inj : forall a b, testbit a === testbit b -> a == b.
Proof.
assert (AUX : forall n, 0<=n -> forall a b,
0<=a<2^n -> testbit a === testbit b -> a == b).
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
intros a b Ha H. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
assert (Ha' : a == 0) by (destruct Ha; order).
rewrite Ha' in *.
symmetry. apply bits_inj_0.
intros m. now rewrite <- H, bits_0.
clear n Hn. intros n Hn IH a b (Ha,Ha') H.
rewrite (div_mod a 2), (div_mod b 2) by order'.
f_equiv; [ | now rewrite <- 2 bit0_mod, H].
f_equiv.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
intros m.
destruct (le_gt_cases 0 m).
rewrite 2 div2_bits by trivial. apply H.
now rewrite 2 testbit_neg_r.
intros a b H.
destruct (le_gt_cases 0 a) as [Ha|Ha].
apply (AUX a); trivial. split; trivial.
apply pow_gt_lin_r; order'.
apply succ_inj, opp_inj.
assert (0 <= - S a).
apply opp_le_mono. now rewrite opp_involutive, opp_0, le_succ_l.
apply (AUX (-(S a))); trivial. split; trivial.
apply pow_gt_lin_r; order'.
intros m. destruct (le_gt_cases 0 m).
now rewrite 2 bits_opp, 2 pred_succ, H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff : forall a b, testbit a === testbit b <-> a == b.
Proof.
split. apply bits_inj. intros EQ; now rewrite EQ.
Qed.
(** In fact, checking the bits at positive indexes is enough. *)
Lemma bits_inj' : forall a b,
(forall n, 0<=n -> a.[n] = b.[n]) -> a == b.
Proof.
intros a b H. apply bits_inj.
intros n. destruct (le_gt_cases 0 n).
now apply H.
now rewrite 2 testbit_neg_r.
Qed.
Lemma bits_inj_iff' : forall a b, (forall n, 0<=n -> a.[n] = b.[n]) <-> a == b.
Proof.
split. apply bits_inj'. intros EQ n Hn; now rewrite EQ.
Qed.
Ltac bitwise := apply bits_inj'; intros ?m ?Hm; autorewrite with bitwise.
Hint Rewrite lxor_spec lor_spec land_spec ldiff_spec bits_0 : bitwise.
(** The streams of bits that correspond to a numbers are
exactly the ones which are stationary after some point. *)
Lemma are_bits : forall (f:t->bool), Proper (eq==>Logic.eq) f ->
((exists n, forall m, 0<=m -> f m = n.[m]) <->
(exists k, forall m, k<=m -> f m = f k)).
Proof.
intros f Hf. split.
intros (a,H).
destruct (le_gt_cases 0 a).
exists (S (log2 a)). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 a); order_pos.
exists (S (log2 (P (-a)))). intros m Hm. apply le_succ_l in Hm.
rewrite 2 H, 2 bits_above_log2_neg; trivial using lt_succ_diag_r.
order_pos. apply le_trans with (log2 (P (-a))); order_pos.
intros (k,Hk).
destruct (lt_ge_cases k 0) as [LT|LE].
case_eq (f 0); intros H0.
exists (-1). intros m Hm. rewrite bits_m1, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
exists 0. intros m Hm. rewrite bits_0, Hk by order.
symmetry; rewrite <- H0. apply Hk; order.
revert f Hf Hk. apply le_ind with (4:=LE).
(* compat : solve_proper fails here *)
apply proper_sym_impl_iff. exact eq_sym.
clear k LE. intros k k' Hk IH f Hf H. apply IH; trivial.
now setoid_rewrite Hk.
(* /compat *)
intros f Hf H0. destruct (f 0).
exists (-1). intros m Hm. now rewrite bits_m1, H0.
exists 0. intros m Hm. now rewrite bits_0, H0.
clear k LE. intros k LE IH f Hf Hk.
destruct (IH (fun m => f (S m))) as (n, Hn).
solve_proper.
intros m Hm. apply Hk. now rewrite <- succ_le_mono.
exists (f 0 + 2*n). intros m Hm.
le_elim Hm.
rewrite <- (succ_pred m), Hn, <- div2_bits.
rewrite mul_comm, div_add, b2z_div2, add_0_l; trivial. order'.
now rewrite <- lt_succ_r, succ_pred.
now rewrite <- lt_succ_r, succ_pred.
rewrite <- Hm.
symmetry. apply add_b2z_double_bit0.
Qed.
(** * Properties of shifts *)
(** First, a unified specification for [shiftl] : the [shiftl_spec]
below (combined with [testbit_neg_r]) is equivalent to
[shiftl_spec_low] and [shiftl_spec_high]. *)
Lemma shiftl_spec : forall a n m, 0<=m -> (a << n).[m] = a.[m-n].
Proof.
intros.
destruct (le_gt_cases n m).
now apply shiftl_spec_high.
rewrite shiftl_spec_low, testbit_neg_r; trivial. now apply lt_sub_0.
Qed.
(** A shiftl by a negative number is a shiftr, and vice-versa *)
Lemma shiftr_opp_r : forall a n, a >> (-n) == a << n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, add_opp_r.
Qed.
Lemma shiftl_opp_r : forall a n, a << (-n) == a >> n.
Proof.
intros. bitwise. now rewrite shiftr_spec, shiftl_spec, sub_opp_r.
Qed.
(** Shifts correspond to multiplication or division by a power of two *)
Lemma shiftr_div_pow2 : forall a n, 0<=n -> a >> n == a / 2^n.
Proof.
intros. bitwise. now rewrite shiftr_spec, div_pow2_bits.
Qed.
Lemma shiftr_mul_pow2 : forall a n, n<=0 -> a >> n == a * 2^(-n).
Proof.
intros. bitwise. rewrite shiftr_spec, mul_pow2_bits; trivial.
now rewrite sub_opp_r.
now apply opp_nonneg_nonpos.
Qed.
Lemma shiftl_mul_pow2 : forall a n, 0<=n -> a << n == a * 2^n.
Proof.
intros. bitwise. now rewrite shiftl_spec, mul_pow2_bits.
Qed.
Lemma shiftl_div_pow2 : forall a n, n<=0 -> a << n == a / 2^(-n).
Proof.
intros. bitwise. rewrite shiftl_spec, div_pow2_bits; trivial.
now rewrite add_opp_r.
now apply opp_nonneg_nonpos.
Qed.
(** Shifts are morphisms *)
Instance shiftr_wd : Proper (eq==>eq==>eq) shiftr.
Proof.
intros a a' Ha n n' Hn.
destruct (le_ge_cases n 0) as [H|H]; assert (H':=H); rewrite Hn in H'.
now rewrite 2 shiftr_mul_pow2, Ha, Hn.
now rewrite 2 shiftr_div_pow2, Ha, Hn.
Qed.
Instance shiftl_wd : Proper (eq==>eq==>eq) shiftl.
Proof.
intros a a' Ha n n' Hn. now rewrite <- 2 shiftr_opp_r, Ha, Hn.
Qed.
(** We could also have specified shiftl with an addition on the left. *)
Lemma shiftl_spec_alt : forall a n m, 0<=n -> (a << n).[m+n] = a.[m].
Proof.
intros. now rewrite shiftl_mul_pow2, mul_pow2_bits, add_simpl_r.
Qed.
(** Chaining several shifts. The only case for which
there isn't any simple expression is a true shiftr
followed by a true shiftl.
*)
Lemma shiftl_shiftl : forall a n m, 0<=n ->
(a << n) << m == a << (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 2 (shiftl_spec _ _ m) by trivial.
rewrite add_comm, sub_add_distr.
destruct (le_gt_cases 0 (m-p)) as [H|H].
now rewrite shiftl_spec.
rewrite 2 testbit_neg_r; trivial.
apply lt_sub_0. now apply lt_le_trans with 0.
Qed.
Lemma shiftr_shiftl_l : forall a n m, 0<=n ->
(a << n) >> m == a << (n-m).
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_shiftl, add_opp_r.
Qed.
Lemma shiftr_shiftl_r : forall a n m, 0<=n ->
(a << n) >> m == a >> (m-n).
Proof.
intros. now rewrite <- 2 shiftl_opp_r, shiftl_shiftl, opp_sub_distr, add_comm.
Qed.
Lemma shiftr_shiftr : forall a n m, 0<=m ->
(a >> n) >> m == a >> (n+m).
Proof.
intros a n p Hn. bitwise.
rewrite 3 shiftr_spec; trivial.
now rewrite (add_comm n p), add_assoc.
now apply add_nonneg_nonneg.
Qed.
(** shifts and constants *)
Lemma shiftl_1_l : forall n, 1 << n == 2^n.
Proof.
intros n. destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
rewrite shiftl_div_pow2, div_1_l, pow_neg_r; try order.
apply pow_gt_1. order'. now apply opp_pos_neg.
Qed.
Lemma shiftl_0_r : forall a, a << 0 == a.
Proof.
intros. rewrite shiftl_mul_pow2 by order. now nzsimpl.
Qed.
Lemma shiftr_0_r : forall a, a >> 0 == a.
Proof.
intros. now rewrite <- shiftl_opp_r, opp_0, shiftl_0_r.
Qed.
Lemma shiftl_0_l : forall n, 0 << n == 0.
Proof.
intros.
destruct (le_ge_cases 0 n).
rewrite shiftl_mul_pow2 by trivial. now nzsimpl.
rewrite shiftl_div_pow2 by trivial.
rewrite <- opp_nonneg_nonpos in H. nzsimpl; order_nz.
Qed.
Lemma shiftr_0_l : forall n, 0 >> n == 0.
Proof.
intros. now rewrite <- shiftl_opp_r, shiftl_0_l.
Qed.
Lemma shiftl_eq_0_iff : forall a n, 0<=n -> (a << n == 0 <-> a == 0).
Proof.
intros a n Hn.
rewrite shiftl_mul_pow2 by trivial. rewrite eq_mul_0. split.
intros [H | H]; trivial. contradict H; order_nz.
intros H. now left.
Qed.
Lemma shiftr_eq_0_iff : forall a n,
a >> n == 0 <-> a==0 \/ (0<a /\ log2 a < n).
Proof.
intros a n.
destruct (le_gt_cases 0 n) as [Hn|Hn].
rewrite shiftr_div_pow2, div_small_iff by order_nz.
destruct (lt_trichotomy a 0) as [LT|[EQ|LT]].
split.
intros [(H,_)|(H,H')]. order. generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]; order.
rewrite EQ. split. now left. intros _; left. split; order_pos.
split. intros [(H,H')|(H,H')]; right. split; trivial.
apply log2_lt_pow2; trivial.
generalize (pow_nonneg 2 n le_0_2); order.
intros [H|(H,H')]. order. left.
split. order. now apply log2_lt_pow2.
rewrite shiftr_mul_pow2 by order. rewrite eq_mul_0.
split; intros [H|H].
now left.
elim (pow_nonzero 2 (-n)); try apply opp_nonneg_nonpos; order'.
now left.
destruct H. generalize (log2_nonneg a); order.
Qed.
Lemma shiftr_eq_0 : forall a n, 0<=a -> log2 a < n -> a >> n == 0.
Proof.
intros a n Ha H. apply shiftr_eq_0_iff.
le_elim Ha. right. now split. now left.
Qed.
(** Properties of [div2]. *)
Lemma div2_div : forall a, div2 a == a/2.
Proof.
intros. rewrite div2_spec, shiftr_div_pow2. now nzsimpl. order'.
Qed.
Instance div2_wd : Proper (eq==>eq) div2.
Proof.
intros a a' Ha. now rewrite 2 div2_div, Ha.
Qed.
Lemma div2_odd : forall a, a == 2*(div2 a) + odd a.
Proof.
intros a. rewrite div2_div, <- bit0_odd, bit0_mod.
apply div_mod. order'.
Qed.
(** Properties of [lxor] and others, directly deduced
from properties of [xorb] and others. *)
Instance lxor_wd : Proper (eq ==> eq ==> eq) lxor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance land_wd : Proper (eq ==> eq ==> eq) land.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance lor_wd : Proper (eq ==> eq ==> eq) lor.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Instance ldiff_wd : Proper (eq ==> eq ==> eq) ldiff.
Proof.
intros a a' Ha b b' Hb. bitwise. now rewrite Ha, Hb.
Qed.
Lemma lxor_eq : forall a a', lxor a a' == 0 -> a == a'.
Proof.
intros a a' H. bitwise. apply xorb_eq.
now rewrite <- lxor_spec, H, bits_0.
Qed.
Lemma lxor_nilpotent : forall a, lxor a a == 0.
Proof.
intros. bitwise. apply xorb_nilpotent.
Qed.
Lemma lxor_eq_0_iff : forall a a', lxor a a' == 0 <-> a == a'.
Proof.
split. apply lxor_eq. intros EQ; rewrite EQ; apply lxor_nilpotent.
Qed.
Lemma lxor_0_l : forall a, lxor 0 a == a.
Proof.
intros. bitwise. apply xorb_false_l.
Qed.
Lemma lxor_0_r : forall a, lxor a 0 == a.
Proof.
intros. bitwise. apply xorb_false_r.
Qed.
Lemma lxor_comm : forall a b, lxor a b == lxor b a.
Proof.
intros. bitwise. apply xorb_comm.
Qed.
Lemma lxor_assoc :
forall a b c, lxor (lxor a b) c == lxor a (lxor b c).
Proof.
intros. bitwise. apply xorb_assoc.
Qed.
Lemma lor_0_l : forall a, lor 0 a == a.
Proof.
intros. bitwise. trivial.
Qed.
Lemma lor_0_r : forall a, lor a 0 == a.
Proof.
intros. bitwise. apply orb_false_r.
Qed.
Lemma lor_comm : forall a b, lor a b == lor b a.
Proof.
intros. bitwise. apply orb_comm.
Qed.
Lemma lor_assoc :
forall a b c, lor a (lor b c) == lor (lor a b) c.
Proof.
intros. bitwise. apply orb_assoc.
Qed.
Lemma lor_diag : forall a, lor a a == a.
Proof.
intros. bitwise. apply orb_diag.
Qed.
Lemma lor_eq_0_l : forall a b, lor a b == 0 -> a == 0.
Proof.
intros a b H. bitwise.
apply (orb_false_iff a.[m] b.[m]).
now rewrite <- lor_spec, H, bits_0.
Qed.
Lemma lor_eq_0_iff : forall a b, lor a b == 0 <-> a == 0 /\ b == 0.
Proof.
intros a b. split.
split. now apply lor_eq_0_l in H.
rewrite lor_comm in H. now apply lor_eq_0_l in H.
intros (EQ,EQ'). now rewrite EQ, lor_0_l.
Qed.
Lemma land_0_l : forall a, land 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma land_0_r : forall a, land a 0 == 0.
Proof.
intros. bitwise. apply andb_false_r.
Qed.
Lemma land_comm : forall a b, land a b == land b a.
Proof.
intros. bitwise. apply andb_comm.
Qed.
Lemma land_assoc :
forall a b c, land a (land b c) == land (land a b) c.
Proof.
intros. bitwise. apply andb_assoc.
Qed.
Lemma land_diag : forall a, land a a == a.
Proof.
intros. bitwise. apply andb_diag.
Qed.
Lemma ldiff_0_l : forall a, ldiff 0 a == 0.
Proof.
intros. bitwise. trivial.
Qed.
Lemma ldiff_0_r : forall a, ldiff a 0 == a.
Proof.
intros. bitwise. now rewrite andb_true_r.
Qed.
Lemma ldiff_diag : forall a, ldiff a a == 0.
Proof.
intros. bitwise. apply andb_negb_r.
Qed.
Lemma lor_land_distr_l : forall a b c,
lor (land a b) c == land (lor a c) (lor b c).
Proof.
intros. bitwise. apply orb_andb_distrib_l.
Qed.
Lemma lor_land_distr_r : forall a b c,
lor a (land b c) == land (lor a b) (lor a c).
Proof.
intros. bitwise. apply orb_andb_distrib_r.
Qed.
Lemma land_lor_distr_l : forall a b c,
land (lor a b) c == lor (land a c) (land b c).
Proof.
intros. bitwise. apply andb_orb_distrib_l.
Qed.
Lemma land_lor_distr_r : forall a b c,
land a (lor b c) == lor (land a b) (land a c).
Proof.
intros. bitwise. apply andb_orb_distrib_r.
Qed.
Lemma ldiff_ldiff_l : forall a b c,
ldiff (ldiff a b) c == ldiff a (lor b c).
Proof.
intros. bitwise. now rewrite negb_orb, andb_assoc.
Qed.
Lemma lor_ldiff_and : forall a b,
lor (ldiff a b) (land a b) == a.
Proof.
intros. bitwise.
now rewrite <- andb_orb_distrib_r, orb_comm, orb_negb_r, andb_true_r.
Qed.
Lemma land_ldiff : forall a b,
land (ldiff a b) b == 0.
Proof.
intros. bitwise.
now rewrite <-andb_assoc, (andb_comm (negb _)), andb_negb_r, andb_false_r.
Qed.
(** Properties of [setbit] and [clearbit] *)
Definition setbit a n := lor a (1 << n).
Definition clearbit a n := ldiff a (1 << n).
Lemma setbit_spec' : forall a n, setbit a n == lor a (2^n).
Proof.
intros. unfold setbit. now rewrite shiftl_1_l.
Qed.
Lemma clearbit_spec' : forall a n, clearbit a n == ldiff a (2^n).
Proof.
intros. unfold clearbit. now rewrite shiftl_1_l.
Qed.
Instance setbit_wd : Proper (eq==>eq==>eq) setbit.
Proof. unfold setbit. solve_proper. Qed.
Instance clearbit_wd : Proper (eq==>eq==>eq) clearbit.
Proof. unfold clearbit. solve_proper. Qed.
Lemma pow2_bits_true : forall n, 0<=n -> (2^n).[n] = true.
Proof.
intros. rewrite <- (mul_1_l (2^n)).
now rewrite mul_pow2_bits, sub_diag, bit0_odd, odd_1.
Qed.
Lemma pow2_bits_false : forall n m, n~=m -> (2^n).[m] = false.
Proof.
intros.
destruct (le_gt_cases 0 n); [|now rewrite pow_neg_r, bits_0].
destruct (le_gt_cases n m).
rewrite <- (mul_1_l (2^n)), mul_pow2_bits; trivial.
rewrite <- (succ_pred (m-n)), <- div2_bits.
now rewrite div_small, bits_0 by (split; order').
rewrite <- lt_succ_r, succ_pred, lt_0_sub. order.
rewrite <- (mul_1_l (2^n)), mul_pow2_bits_low; trivial.
Qed.
Lemma pow2_bits_eqb : forall n m, 0<=n -> (2^n).[m] = eqb n m.
Proof.
intros n m Hn. apply eq_true_iff_eq. rewrite eqb_eq. split.
destruct (eq_decidable n m) as [H|H]. trivial.
now rewrite (pow2_bits_false _ _ H).
intros EQ. rewrite EQ. apply pow2_bits_true; order.
Qed.
Lemma setbit_eqb : forall a n m, 0<=n ->
(setbit a n).[m] = eqb n m || a.[m].
Proof.
intros. now rewrite setbit_spec', lor_spec, pow2_bits_eqb, orb_comm.
Qed.
Lemma setbit_iff : forall a n m, 0<=n ->
((setbit a n).[m] = true <-> n==m \/ a.[m] = true).
Proof.
intros. now rewrite setbit_eqb, orb_true_iff, eqb_eq.
Qed.
Lemma setbit_eq : forall a n, 0<=n -> (setbit a n).[n] = true.
Proof.
intros. apply setbit_iff; trivial. now left.
Qed.
Lemma setbit_neq : forall a n m, 0<=n -> n~=m ->
(setbit a n).[m] = a.[m].
Proof.
intros a n m Hn H. rewrite setbit_eqb; trivial.
rewrite <- eqb_eq in H. apply not_true_is_false in H. now rewrite H.
Qed.
Lemma clearbit_eqb : forall a n m,
(clearbit a n).[m] = a.[m] && negb (eqb n m).
Proof.
intros.
destruct (le_gt_cases 0 m); [| now rewrite 2 testbit_neg_r].
rewrite clearbit_spec', ldiff_spec. f_equal. f_equal.
destruct (le_gt_cases 0 n) as [Hn|Hn].
now apply pow2_bits_eqb.
symmetry. rewrite pow_neg_r, bits_0, <- not_true_iff_false, eqb_eq; order.
Qed.
Lemma clearbit_iff : forall a n m,
(clearbit a n).[m] = true <-> a.[m] = true /\ n~=m.
Proof.
intros. rewrite clearbit_eqb, andb_true_iff, <- eqb_eq.
now rewrite negb_true_iff, not_true_iff_false.
Qed.
Lemma clearbit_eq : forall a n, (clearbit a n).[n] = false.
Proof.
intros. rewrite clearbit_eqb, (proj2 (eqb_eq _ _) (eq_refl n)).
apply andb_false_r.
Qed.
Lemma clearbit_neq : forall a n m, n~=m ->
(clearbit a n).[m] = a.[m].
Proof.
intros a n m H. rewrite clearbit_eqb.
rewrite <- eqb_eq in H. apply not_true_is_false in H. rewrite H.
apply andb_true_r.
Qed.
(** Shifts of bitwise operations *)
Lemma shiftl_lxor : forall a b n,
(lxor a b) << n == lxor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lxor_spec.
Qed.
Lemma shiftr_lxor : forall a b n,
(lxor a b) >> n == lxor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lxor_spec.
Qed.
Lemma shiftl_land : forall a b n,
(land a b) << n == land (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, land_spec.
Qed.
Lemma shiftr_land : forall a b n,
(land a b) >> n == land (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, land_spec.
Qed.
Lemma shiftl_lor : forall a b n,
(lor a b) << n == lor (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, lor_spec.
Qed.
Lemma shiftr_lor : forall a b n,
(lor a b) >> n == lor (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, lor_spec.
Qed.
Lemma shiftl_ldiff : forall a b n,
(ldiff a b) << n == ldiff (a << n) (b << n).
Proof.
intros. bitwise. now rewrite !shiftl_spec, ldiff_spec.
Qed.
Lemma shiftr_ldiff : forall a b n,
(ldiff a b) >> n == ldiff (a >> n) (b >> n).
Proof.
intros. bitwise. now rewrite !shiftr_spec, ldiff_spec.
Qed.
(** For integers, we do have a binary complement function *)
Definition lnot a := P (-a).
Instance lnot_wd : Proper (eq==>eq) lnot.
Proof. unfold lnot. solve_proper. Qed.
Lemma lnot_spec : forall a n, 0<=n -> (lnot a).[n] = negb a.[n].
Proof.
intros. unfold lnot. rewrite <- (opp_involutive a) at 2.
rewrite bits_opp, negb_involutive; trivial.
Qed.
Lemma lnot_involutive : forall a, lnot (lnot a) == a.
Proof.
intros a. bitwise. now rewrite 2 lnot_spec, negb_involutive.
Qed.
Lemma lnot_0 : lnot 0 == -1.
Proof.
unfold lnot. now rewrite opp_0, <- sub_1_r, sub_0_l.
Qed.
Lemma lnot_m1 : lnot (-1) == 0.
Proof.
unfold lnot. now rewrite opp_involutive, one_succ, pred_succ.
Qed.
(** Complement and other operations *)
Lemma lor_m1_r : forall a, lor a (-1) == -1.
Proof.
intros. bitwise. now rewrite bits_m1, orb_true_r.
Qed.
Lemma lor_m1_l : forall a, lor (-1) a == -1.
Proof.
intros. now rewrite lor_comm, lor_m1_r.
Qed.
Lemma land_m1_r : forall a, land a (-1) == a.
Proof.
intros. bitwise. now rewrite bits_m1, andb_true_r.
Qed.
Lemma land_m1_l : forall a, land (-1) a == a.
Proof.
intros. now rewrite land_comm, land_m1_r.
Qed.
Lemma ldiff_m1_r : forall a, ldiff a (-1) == 0.
Proof.
intros. bitwise. now rewrite bits_m1, andb_false_r.
Qed.
Lemma ldiff_m1_l : forall a, ldiff (-1) a == lnot a.
Proof.
intros. bitwise. now rewrite lnot_spec, bits_m1.
Qed.
Lemma lor_lnot_diag : forall a, lor a (lnot a) == -1.
Proof.
intros a. bitwise. rewrite lnot_spec, bits_m1; trivial.
now destruct a.[m].
Qed.
Lemma add_lnot_diag : forall a, a + lnot a == -1.
Proof.
intros a. unfold lnot.
now rewrite add_pred_r, add_opp_r, sub_diag, one_succ, opp_succ, opp_0.
Qed.
Lemma ldiff_land : forall a b, ldiff a b == land a (lnot b).
Proof.
intros. bitwise. now rewrite lnot_spec.
Qed.
Lemma land_lnot_diag : forall a, land a (lnot a) == 0.
Proof.
intros. now rewrite <- ldiff_land, ldiff_diag.
Qed.
Lemma lnot_lor : forall a b, lnot (lor a b) == land (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, lor_spec, negb_orb.
Qed.
Lemma lnot_land : forall a b, lnot (land a b) == lor (lnot a) (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, land_spec, negb_andb.
Qed.
Lemma lnot_ldiff : forall a b, lnot (ldiff a b) == lor (lnot a) b.
Proof.
intros a b. bitwise.
now rewrite !lnot_spec, ldiff_spec, negb_andb, negb_involutive.
Qed.
Lemma lxor_lnot_lnot : forall a b, lxor (lnot a) (lnot b) == lxor a b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, xorb_negb_negb.
Qed.
Lemma lnot_lxor_l : forall a b, lnot (lxor a b) == lxor (lnot a) b.
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_l.
Qed.
Lemma lnot_lxor_r : forall a b, lnot (lxor a b) == lxor a (lnot b).
Proof.
intros a b. bitwise. now rewrite !lnot_spec, !lxor_spec, negb_xorb_r.
Qed.
Lemma lxor_m1_r : forall a, lxor a (-1) == lnot a.
Proof.
intros. now rewrite <- (lxor_0_r (lnot a)), <- lnot_m1, lxor_lnot_lnot.
Qed.
Lemma lxor_m1_l : forall a, lxor (-1) a == lnot a.
Proof.
intros. now rewrite lxor_comm, lxor_m1_r.
Qed.
Lemma lxor_lor : forall a b, land a b == 0 ->
lxor a b == lor a b.
Proof.
intros a b H. bitwise.
assert (a.[m] && b.[m] = false)
by now rewrite <- land_spec, H, bits_0.
now destruct a.[m], b.[m].
Qed.
Lemma lnot_shiftr : forall a n, 0<=n -> lnot (a >> n) == (lnot a) >> n.
Proof.
intros a n Hn. bitwise.
now rewrite lnot_spec, 2 shiftr_spec, lnot_spec by order_pos.
Qed.
(** [(ones n)] is [2^n-1], the number with [n] digits 1 *)
Definition ones n := P (1<<n).
Instance ones_wd : Proper (eq==>eq) ones.
Proof. unfold ones. solve_proper. Qed.
Lemma ones_equiv : forall n, ones n == P (2^n).
Proof.
intros. unfold ones.
destruct (le_gt_cases 0 n).
now rewrite shiftl_mul_pow2, mul_1_l.
f_equiv. rewrite pow_neg_r; trivial.
rewrite <- shiftr_opp_r. apply shiftr_eq_0_iff. right; split.
order'. rewrite log2_1. now apply opp_pos_neg.
Qed.
Lemma ones_add : forall n m, 0<=n -> 0<=m ->
ones (m+n) == 2^m * ones n + ones m.
Proof.
intros n m Hn Hm. rewrite !ones_equiv.
rewrite <- !sub_1_r, mul_sub_distr_l, mul_1_r, <- pow_add_r by trivial.
rewrite add_sub_assoc, sub_add. reflexivity.
Qed.
Lemma ones_div_pow2 : forall n m, 0<=m<=n -> ones n / 2^m == ones (n-m).
Proof.
intros n m (Hm,H). symmetry. apply div_unique with (ones m).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_mod_pow2 : forall n m, 0<=m<=n -> (ones n) mod (2^m) == ones m.
Proof.
intros n m (Hm,H). symmetry. apply mod_unique with (ones (n-m)).
left. rewrite ones_equiv. split.
rewrite <- lt_succ_r, succ_pred. order_pos.
now rewrite <- le_succ_l, succ_pred.
rewrite <- (sub_add m n) at 1. rewrite (add_comm _ m).
apply ones_add; trivial. now apply le_0_sub.
Qed.
Lemma ones_spec_low : forall n m, 0<=m<n -> (ones n).[m] = true.
Proof.
intros n m (Hm,H). apply testbit_true; trivial.
rewrite ones_div_pow2 by (split; order).
rewrite <- (pow_1_r 2). rewrite ones_mod_pow2.
rewrite ones_equiv. now nzsimpl'.
split. order'. apply le_add_le_sub_r. nzsimpl. now apply le_succ_l.
Qed.
Lemma ones_spec_high : forall n m, 0<=n<=m -> (ones n).[m] = false.
Proof.
intros n m (Hn,H). le_elim Hn.
apply bits_above_log2; rewrite ones_equiv.
rewrite <-lt_succ_r, succ_pred; order_pos.
rewrite log2_pred_pow2; trivial. now rewrite <-le_succ_l, succ_pred.
rewrite ones_equiv. now rewrite <- Hn, pow_0_r, one_succ, pred_succ, bits_0.
Qed.
Lemma ones_spec_iff : forall n m, 0<=n ->
((ones n).[m] = true <-> 0<=m<n).
Proof.
intros n m Hn. split. intros H.
destruct (lt_ge_cases m 0) as [Hm|Hm].
now rewrite testbit_neg_r in H.
split; trivial. apply lt_nge. intro H'. rewrite ones_spec_high in H.
discriminate. now split.
apply ones_spec_low.
Qed.
Lemma lor_ones_low : forall a n, 0<=a -> log2 a < n ->
lor a (ones n) == ones n.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; try split; trivial.
now apply lt_le_trans with n.
apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, orb_true_r; try split; trivial.
Qed.
Lemma land_ones : forall a n, 0<=n -> land a (ones n) == a mod 2^n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, mod_pow2_bits_high, andb_false_r;
try split; trivial.
rewrite ones_spec_low, mod_pow2_bits_low, andb_true_r;
try split; trivial.
Qed.
Lemma land_ones_low : forall a n, 0<=a -> log2 a < n ->
land a (ones n) == a.
Proof.
intros a n Ha H.
assert (Hn : 0<=n) by (generalize (log2_nonneg a); order).
rewrite land_ones; trivial. apply mod_small.
split; trivial.
apply log2_lt_cancel. now rewrite log2_pow2.
Qed.
Lemma ldiff_ones_r : forall a n, 0<=n ->
ldiff a (ones n) == (a >> n) << n.
Proof.
intros a n Hn. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, shiftl_spec_high, shiftr_spec; trivial.
rewrite sub_add; trivial. apply andb_true_r.
now apply le_0_sub.
now split.
rewrite ones_spec_low, shiftl_spec_low, andb_false_r;
try split; trivial.
Qed.
Lemma ldiff_ones_r_low : forall a n, 0<=a -> log2 a < n ->
ldiff a (ones n) == 0.
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, andb_false_r; try split; trivial.
Qed.
Lemma ldiff_ones_l_low : forall a n, 0<=a -> log2 a < n ->
ldiff (ones n) a == lxor a (ones n).
Proof.
intros a n Ha H. bitwise. destruct (le_gt_cases n m).
rewrite ones_spec_high, bits_above_log2; trivial.
now apply lt_le_trans with n.
split; trivial. now apply le_trans with (log2 a); order_pos.
rewrite ones_spec_low, xorb_true_r; try split; trivial.
Qed.
(** Bitwise operations and sign *)
Lemma shiftl_nonneg : forall a n, 0 <= (a << n) <-> 0 <= a.
Proof.
intros a n.
destruct (le_ge_cases 0 n) as [Hn|Hn].
(* 0<=n *)
rewrite 2 bits_iff_nonneg_ex. split; intros (k,Hk).
exists (k-n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite <- (add_simpl_r m n), <- (shiftl_spec a n) by order_pos.
apply Hk. now apply lt_sub_lt_add_r.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftl_spec by trivial. apply Hk. now apply lt_add_lt_sub_r.
(* n<=0*)
rewrite <- shiftr_opp_r, 2 bits_iff_nonneg_ex. split; intros (k,Hk).
destruct (le_gt_cases 0 k).
exists (k-n). intros m Hm. apply lt_sub_lt_add_r in Hm.
rewrite <- (add_simpl_r m n), <- add_opp_r, <- (shiftr_spec a (-n)).
now apply Hk. order.
assert (EQ : a >> (-n) == 0).
apply bits_inj'. intros m Hm. rewrite bits_0. apply Hk; order.
apply shiftr_eq_0_iff in EQ.
rewrite <- bits_iff_nonneg_ex. destruct EQ as [EQ|[LT _]]; order.
exists (k+n). intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec by trivial. apply Hk.
rewrite add_opp_r. now apply lt_add_lt_sub_r.
Qed.
Lemma shiftl_neg : forall a n, (a << n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftl_nonneg.
Qed.
Lemma shiftr_nonneg : forall a n, 0 <= (a >> n) <-> 0 <= a.
Proof.
intros. rewrite <- shiftl_opp_r. apply shiftl_nonneg.
Qed.
Lemma shiftr_neg : forall a n, (a >> n) < 0 <-> a < 0.
Proof.
intros a n. now rewrite 2 lt_nge, shiftr_nonneg.
Qed.
Lemma div2_nonneg : forall a, 0 <= div2 a <-> 0 <= a.
Proof.
intros. rewrite div2_spec. apply shiftr_nonneg.
Qed.
Lemma div2_neg : forall a, div2 a < 0 <-> a < 0.
Proof.
intros a. now rewrite 2 lt_nge, div2_nonneg.
Qed.
Lemma lor_nonneg : forall a b, 0 <= lor a b <-> 0<=a /\ 0<=b.
Proof.
intros a b.
rewrite 3 bits_iff_nonneg_ex. split. intros (k,Hk).
split; exists k; intros m Hm; apply (orb_false_elim a.[m] b.[m]);
rewrite <- lor_spec; now apply Hk.
intros ((k,Hk),(k',Hk')).
destruct (le_ge_cases k k'); [ exists k' | exists k ];
intros m Hm; rewrite lor_spec, Hk, Hk'; trivial; order.
Qed.
Lemma lor_neg : forall a b, lor a b < 0 <-> a < 0 \/ b < 0.
Proof.
intros a b. rewrite 3 lt_nge, lor_nonneg. split.
apply not_and. apply le_decidable.
now intros [H|H] (H',H'').
Qed.
Lemma lnot_nonneg : forall a, 0 <= lnot a <-> a < 0.
Proof.
intros a; unfold lnot.
now rewrite <- opp_succ, opp_nonneg_nonpos, le_succ_l.
Qed.
Lemma lnot_neg : forall a, lnot a < 0 <-> 0 <= a.
Proof.
intros a. now rewrite le_ngt, lt_nge, lnot_nonneg.
Qed.
Lemma land_nonneg : forall a b, 0 <= land a b <-> 0<=a \/ 0<=b.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_nonneg,
lor_neg, !lnot_neg.
Qed.
Lemma land_neg : forall a b, land a b < 0 <-> a < 0 /\ b < 0.
Proof.
intros a b.
now rewrite <- (lnot_involutive (land a b)), lnot_land, lnot_neg,
lor_nonneg, !lnot_nonneg.
Qed.
Lemma ldiff_nonneg : forall a b, 0 <= ldiff a b <-> 0<=a \/ b<0.
Proof.
intros. now rewrite ldiff_land, land_nonneg, lnot_nonneg.
Qed.
Lemma ldiff_neg : forall a b, ldiff a b < 0 <-> a<0 /\ 0<=b.
Proof.
intros. now rewrite ldiff_land, land_neg, lnot_neg.
Qed.
Lemma lxor_nonneg : forall a b, 0 <= lxor a b <-> (0<=a <-> 0<=b).
Proof.
assert (H : forall a b, 0<=a -> 0<=b -> 0<=lxor a b).
intros a b. rewrite 3 bits_iff_nonneg_ex. intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
assert (H' : forall a b, 0<=a -> b<0 -> lxor a b<0).
intros a b. rewrite bits_iff_nonneg_ex, 2 bits_iff_neg_ex.
intros (k,Hk) (k', Hk').
destruct (le_ge_cases k k'); [ exists k' | exists k];
intros m Hm; rewrite lxor_spec, Hk, Hk'; trivial; order.
intros a b.
split.
intros Hab. split.
intros Ha. destruct (le_gt_cases 0 b) as [Hb|Hb]; trivial.
generalize (H' _ _ Ha Hb). order.
intros Hb. destruct (le_gt_cases 0 a) as [Ha|Ha]; trivial.
generalize (H' _ _ Hb Ha). rewrite lxor_comm. order.
intros E.
destruct (le_gt_cases 0 a) as [Ha|Ha]. apply H; trivial. apply E; trivial.
destruct (le_gt_cases 0 b) as [Hb|Hb]. apply H; trivial. apply E; trivial.
rewrite <- lxor_lnot_lnot. apply H; now apply lnot_nonneg.
Qed.
(** Bitwise operations and log2 *)
Lemma log2_bits_unique : forall a n,
a.[n] = true ->
(forall m, n<m -> a.[m] = false) ->
log2 a == n.
Proof.
intros a n H H'.
destruct (lt_trichotomy a 0) as [Ha|[Ha|Ha]].
(* a < 0 *)
destruct (proj1 (bits_iff_neg_ex a) Ha) as (k,Hk).
destruct (le_gt_cases n k).
specialize (Hk (S k) (lt_succ_diag_r _)).
rewrite H' in Hk. discriminate. apply lt_succ_r; order.
specialize (H' (S n) (lt_succ_diag_r _)).
rewrite Hk in H'. discriminate. apply lt_succ_r; order.
(* a = 0 *)
now rewrite Ha, bits_0 in H.
(* 0 < a *)
apply le_antisymm; apply le_ngt; intros LT.
specialize (H' _ LT). now rewrite bit_log2 in H'.
now rewrite bits_above_log2 in H by order.
Qed.
Lemma log2_shiftr : forall a n, 0<a -> log2 (a >> n) == max 0 (log2 a - n).
Proof.
intros a n Ha.
destruct (le_gt_cases 0 (log2 a - n));
[rewrite max_r | rewrite max_l]; try order.
apply log2_bits_unique.
now rewrite shiftr_spec, sub_add, bit_log2.
intros m Hm.
destruct (le_gt_cases 0 m); [|now rewrite testbit_neg_r].
rewrite shiftr_spec; trivial. apply bits_above_log2; try order.
now apply lt_sub_lt_add_r.
rewrite lt_sub_lt_add_r, add_0_l in H.
apply log2_nonpos. apply le_lteq; right.
apply shiftr_eq_0_iff. right. now split.
Qed.
Lemma log2_shiftl : forall a n, 0<a -> 0<=n -> log2 (a << n) == log2 a + n.
Proof.
intros a n Ha Hn.
rewrite shiftl_mul_pow2, add_comm by trivial.
now apply log2_mul_pow2.
Qed.
Lemma log2_shiftl' : forall a n, 0<a -> log2 (a << n) == max 0 (log2 a + n).
Proof.
intros a n Ha.
rewrite <- shiftr_opp_r, log2_shiftr by trivial.
destruct (le_gt_cases 0 (log2 a + n));
[rewrite 2 max_r | rewrite 2 max_l]; rewrite ?sub_opp_r; try order.
Qed.
Lemma log2_lor : forall a b, 0<=a -> 0<=b ->
log2 (lor a b) == max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lor a b) == log2 b).
intros a b Ha H.
le_elim Ha; [|now rewrite <- Ha, lor_0_l].
apply log2_bits_unique.
now rewrite lor_spec, bit_log2, orb_true_r by order.
intros m Hm. assert (H' := log2_le_mono _ _ H).
now rewrite lor_spec, 2 bits_above_log2 by order.
(* main *)
intros a b Ha Hb. destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono.
now apply AUX.
rewrite max_l by now apply log2_le_mono.
rewrite lor_comm. now apply AUX.
Qed.
Lemma log2_land : forall a b, 0<=a -> 0<=b ->
log2 (land a b) <= min (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (land a b) <= log2 a).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= land a b) by (apply land_nonneg; now left).
le_elim H.
generalize (bit_log2 (land a b) H).
now rewrite land_spec, bits_above_log2.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite min_l by now apply log2_le_mono. now apply AUX.
rewrite min_r by now apply log2_le_mono. rewrite land_comm. now apply AUX.
Qed.
Lemma log2_lxor : forall a b, 0<=a -> 0<=b ->
log2 (lxor a b) <= max (log2 a) (log2 b).
Proof.
assert (AUX : forall a b, 0<=a -> a<=b -> log2 (lxor a b) <= log2 b).
intros a b Ha Hb.
apply le_ngt. intros LT.
assert (H : 0 <= lxor a b) by (apply lxor_nonneg; split; order).
le_elim H.
generalize (bit_log2 (lxor a b) H).
rewrite lxor_spec, 2 bits_above_log2; try order. discriminate.
apply le_lt_trans with (log2 b); trivial. now apply log2_le_mono.
rewrite <- H in LT. apply log2_lt_cancel in LT; order.
(* main *)
intros a b Ha Hb.
destruct (le_ge_cases a b) as [H|H].
rewrite max_r by now apply log2_le_mono. now apply AUX.
rewrite max_l by now apply log2_le_mono. rewrite lxor_comm. now apply AUX.
Qed.
(** Bitwise operations and arithmetical operations *)
Local Notation xor3 a b c := (xorb (xorb a b) c).
Local Notation lxor3 a b c := (lxor (lxor a b) c).
Local Notation nextcarry a b c := ((a&&b) || (c && (a||b))).
Local Notation lnextcarry a b c := (lor (land a b) (land c (lor a b))).
Lemma add_bit0 : forall a b, (a+b).[0] = xorb a.[0] b.[0].
Proof.
intros. now rewrite !bit0_odd, odd_add.
Qed.
Lemma add3_bit0 : forall a b c,
(a+b+c).[0] = xor3 a.[0] b.[0] c.[0].
Proof.
intros. now rewrite !add_bit0.
Qed.
Lemma add3_bits_div2 : forall (a0 b0 c0 : bool),
(a0 + b0 + c0)/2 == nextcarry a0 b0 c0.
Proof.
assert (H : 1+1 == 2) by now nzsimpl'.
intros [|] [|] [|]; simpl; rewrite ?add_0_l, ?add_0_r, ?H;
(apply div_same; order') || (apply div_small; split; order') || idtac.
symmetry. apply div_unique with 1. left; split; order'. now nzsimpl'.
Qed.
Lemma add_carry_div2 : forall a b (c0:bool),
(a + b + c0)/2 == a/2 + b/2 + nextcarry a.[0] b.[0] c0.
Proof.
intros.
rewrite <- add3_bits_div2.
rewrite (add_comm ((a/2)+_)).
rewrite <- div_add by order'.
f_equiv.
rewrite <- !div2_div, mul_comm, mul_add_distr_l.
rewrite (div2_odd a), <- bit0_odd at 1.
rewrite (div2_odd b), <- bit0_odd at 1.
rewrite add_shuffle1.
rewrite <-(add_assoc _ _ c0). apply add_comm.
Qed.
(** The main result concerning addition: we express the bits of the sum
in term of bits of [a] and [b] and of some carry stream which is also
recursively determined by another equation.
*)
Lemma add_carry_bits_aux : forall n, 0<=n ->
forall a b (c0:bool), -(2^n) <= a < 2^n -> -(2^n) <= b < 2^n ->
exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros n Hn. apply le_ind with (4:=Hn).
solve_proper.
(* base *)
intros a b c0. rewrite !pow_0_r, !one_succ, !lt_succ_r, <- !one_succ.
intros (Ha1,Ha2) (Hb1,Hb2).
le_elim Ha1; rewrite <- ?le_succ_l, ?succ_m1 in Ha1;
le_elim Hb1; rewrite <- ?le_succ_l, ?succ_m1 in Hb1.
(* base, a = 0, b = 0 *)
exists c0.
rewrite (le_antisymm _ _ Ha2 Ha1), (le_antisymm _ _ Hb2 Hb1).
rewrite !add_0_l, !lxor_0_l, !lor_0_r, !land_0_r, !lor_0_r.
rewrite b2z_div2, b2z_bit0; now repeat split.
(* base, a = 0, b = -1 *)
exists (-c0). rewrite <- Hb1, (le_antisymm _ _ Ha2 Ha1). repeat split.
rewrite add_0_l, lxor_0_l, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_l, !lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = 0 *)
exists (-c0). rewrite <- Ha1, (le_antisymm _ _ Hb2 Hb1). repeat split.
rewrite add_0_r, lxor_0_r, lxor_m1_l.
unfold lnot. now rewrite opp_involutive, add_comm, add_opp_r, sub_1_r.
rewrite land_0_r, lor_0_r, lor_0_l, land_m1_r.
symmetry. apply div_unique with c0. left; destruct c0; simpl; split; order'.
now rewrite two_succ, mul_succ_l, mul_1_l, add_opp_r, sub_add.
rewrite bit0_odd, odd_opp; destruct c0; simpl; apply odd_1 || apply odd_0.
(* base, a = -1, b = -1 *)
exists (c0 + 2*(-1)). rewrite <- Ha1, <- Hb1. repeat split.
rewrite lxor_m1_l, lnot_m1, lxor_0_l.
now rewrite two_succ, mul_succ_l, mul_1_l, add_comm, add_assoc.
rewrite land_m1_l, lor_m1_l.
apply add_b2z_double_div2.
apply add_b2z_double_bit0.
(* step *)
clear n Hn. intros n Hn IH a b c0 Ha Hb.
set (c1:=nextcarry a.[0] b.[0] c0).
destruct (IH (a/2) (b/2) c1) as (c & IH1 & IH2 & Hc); clear IH.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
split.
apply div_le_lower_bound. order'. now rewrite mul_opp_r, <- pow_succ_r.
apply div_lt_upper_bound. order'. now rewrite <- pow_succ_r.
exists (c0 + 2*c). repeat split.
(* step, add *)
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, <- 2 lxor_spec by trivial.
f_equiv.
rewrite add_b2z_double_div2, <- IH1. apply add_carry_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0, add3_bit0, b2z_bit0.
(* step, carry *)
rewrite add_b2z_double_div2.
bitwise.
le_elim Hm.
rewrite <- (succ_pred m), lt_succ_r in Hm.
rewrite <- (succ_pred m), <- !div2_bits, IH2 by trivial.
autorewrite with bitwise. now rewrite add_b2z_double_div2.
rewrite <- Hm.
now rewrite add_b2z_double_bit0.
(* step, carry0 *)
apply add_b2z_double_bit0.
Qed.
Lemma add_carry_bits : forall a b (c0:bool), exists c,
a+b+c0 == lxor3 a b c /\ c/2 == lnextcarry a b c /\ c.[0] = c0.
Proof.
intros a b c0.
set (n := max (abs a) (abs b)).
apply (add_carry_bits_aux n).
(* positivity *)
unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; order_pos'.
(* bound for a *)
assert (Ha : abs a < 2^n).
apply lt_le_trans with (2^(abs a)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Ha. destruct Ha; split; order.
(* bound for b *)
assert (Hb : abs b < 2^n).
apply lt_le_trans with (2^(abs b)). apply pow_gt_lin_r; order_pos'.
apply pow_le_mono_r. order'. unfold n.
destruct (le_ge_cases (abs a) (abs b));
[rewrite max_r|rewrite max_l]; try order.
apply abs_lt in Hb. destruct Hb; split; order.
Qed.
(** Particular case : the second bit of an addition *)
Lemma add_bit1 : forall a b,
(a+b).[1] = xor3 a.[1] b.[1] (a.[0] && b.[0]).
Proof.
intros a b.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
autorewrite with bitwise. f_equal.
rewrite one_succ, <- div2_bits, EQ2 by order.
autorewrite with bitwise.
rewrite Hc. simpl. apply orb_false_r.
Qed.
(** In an addition, there will be no carries iff there is
no common bits in the numbers to add *)
Lemma nocarry_equiv : forall a b c,
c/2 == lnextcarry a b c -> c.[0] = false ->
(c == 0 <-> land a b == 0).
Proof.
intros a b c H H'.
split. intros EQ; rewrite EQ in *.
rewrite div_0_l in H by order'.
symmetry in H. now apply lor_eq_0_l in H.
intros EQ. rewrite EQ, lor_0_l in H.
apply bits_inj'. intros n Hn. rewrite bits_0.
apply le_ind with (4:=Hn).
solve_proper.
trivial.
clear n Hn. intros n Hn IH.
rewrite <- div2_bits, H; trivial.
autorewrite with bitwise.
now rewrite IH.
Qed.
(** When there is no common bits, the addition is just a xor *)
Lemma add_nocarry_lxor : forall a b, land a b == 0 ->
a+b == lxor a b.
Proof.
intros a b H.
destruct (add_carry_bits a b false) as (c & EQ1 & EQ2 & Hc).
simpl in EQ1; rewrite add_0_r in EQ1. rewrite EQ1.
apply (nocarry_equiv a b c) in H; trivial.
rewrite H. now rewrite lxor_0_r.
Qed.
(** A null [ldiff] implies being smaller *)
Lemma ldiff_le : forall a b, 0<=b -> ldiff a b == 0 -> 0 <= a <= b.
Proof.
assert (AUX : forall n, 0<=n ->
forall a b, 0 <= a < 2^n -> 0<=b -> ldiff a b == 0 -> a <= b).
intros n Hn. apply le_ind with (4:=Hn); clear n Hn.
solve_proper.
intros a b Ha Hb _. rewrite pow_0_r, one_succ, lt_succ_r in Ha.
setoid_replace a with 0 by (destruct Ha; order'); trivial.
intros n Hn IH a b (Ha,Ha') Hb H.
assert (NEQ : 2 ~= 0) by order'.
rewrite (div_mod a 2 NEQ), (div_mod b 2 NEQ).
apply add_le_mono.
apply mul_le_mono_pos_l; try order'.
apply IH.
split. apply div_pos; order'.
apply div_lt_upper_bound; try order'. now rewrite <- pow_succ_r.
apply div_pos; order'.
rewrite <- (pow_1_r 2), <- 2 shiftr_div_pow2 by order'.
rewrite <- shiftr_ldiff, H, shiftr_div_pow2, pow_1_r, div_0_l; order'.
rewrite <- 2 bit0_mod.
apply bits_inj_iff in H. specialize (H 0).
rewrite ldiff_spec, bits_0 in H.
destruct a.[0], b.[0]; try discriminate; simpl; order'.
(* main *)
intros a b Hb Hd.
assert (Ha : 0<=a).
apply le_ngt; intros Ha'. apply (lt_irrefl 0). rewrite <- Hd at 1.
apply ldiff_neg. now split.
split; trivial. apply (AUX a); try split; trivial. apply pow_gt_lin_r; order'.
Qed.
(** Subtraction can be a ldiff when the opposite ldiff is null. *)
Lemma sub_nocarry_ldiff : forall a b, ldiff b a == 0 ->
a-b == ldiff a b.
Proof.
intros a b H.
apply add_cancel_r with b.
rewrite sub_add.
symmetry.
rewrite add_nocarry_lxor; trivial.
bitwise.
apply bits_inj_iff in H. specialize (H m).
rewrite ldiff_spec, bits_0 in H.
now destruct a.[m], b.[m].
apply land_ldiff.
Qed.
(** Adding numbers with no common bits cannot lead to a much bigger number *)
Lemma add_nocarry_lt_pow2 : forall a b n, land a b == 0 ->
a < 2^n -> b < 2^n -> a+b < 2^n.
Proof.
intros a b n H Ha Hb.
destruct (le_gt_cases a 0) as [Ha'|Ha'].
apply le_lt_trans with (0+b). now apply add_le_mono_r. now nzsimpl.
destruct (le_gt_cases b 0) as [Hb'|Hb'].
apply le_lt_trans with (a+0). now apply add_le_mono_l. now nzsimpl.
rewrite add_nocarry_lxor by order.
destruct (lt_ge_cases 0 (lxor a b)); [|apply le_lt_trans with 0; order_pos].
apply log2_lt_pow2; trivial.
apply log2_lt_pow2 in Ha; trivial.
apply log2_lt_pow2 in Hb; trivial.
apply le_lt_trans with (max (log2 a) (log2 b)).
apply log2_lxor; order.
destruct (le_ge_cases (log2 a) (log2 b));
[rewrite max_r|rewrite max_l]; order.
Qed.
Lemma add_nocarry_mod_lt_pow2 : forall a b n, 0<=n -> land a b == 0 ->
a mod 2^n + b mod 2^n < 2^n.
Proof.
intros a b n Hn H.
apply add_nocarry_lt_pow2.
bitwise.
destruct (le_gt_cases n m).
rewrite mod_pow2_bits_high; now split.
now rewrite !mod_pow2_bits_low, <- land_spec, H, bits_0.
apply mod_pos_bound; order_pos.
apply mod_pos_bound; order_pos.
Qed.
End ZBitsProp.
|
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2004 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
reg [255:0] a;
reg [60:0] divisor;
reg [60:0] qq;
reg [60:0] rq;
reg signed [60:0] qqs;
reg signed [60:0] rqs;
always @* begin
qq = a[60:0] / divisor;
rq = a[60:0] % divisor;
qqs = $signed(a[60:0]) / $signed(divisor);
rqs = $signed(a[60:0]) % $signed(divisor);
end
integer cyc; initial cyc=1;
always @ (posedge clk) begin
if (cyc!=0) begin
cyc <= cyc + 1;
//$write("%d: %x %x %x %x\n", cyc, qq, rq, qqs, rqs);
if (cyc==1) begin
a <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
divisor <= 61'h12371;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
end
if (cyc==2) begin
a <= 256'h0e17c88f3d5fe51a982646c8e2bd68c3e236ddfddddbdad20a48e039c9f395b8;
divisor <= 61'h1238123771;
a[60] <= 1'b0; divisor[60] <= 1'b0; // Unsigned
if (qq!==61'h00000403ad81c0da) $stop;
if (rq!==61'h00000000000090ec) $stop;
if (qqs!==61'h00000403ad81c0da) $stop;
if (rqs!==61'h00000000000090ec) $stop;
end
if (cyc==3) begin
a <= 256'h0e17c88f00d5fe51a982646c8002bd68c3e236ddfd00ddbdad20a48e00f395b8;
divisor <= 61'hf1b;
a[60] <= 1'b1; divisor[60] <= 1'b0; // Signed
if (qq!==61'h000000000090832e) $stop;
if (rq!==61'h0000000334becc6a) $stop;
if (qqs!==61'h000000000090832e) $stop;
if (rqs!==61'h0000000334becc6a) $stop;
end
if (cyc==4) begin
a[60] <= 1'b0; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0001eda37cca1be8) $stop;
if (rq!==61'h0000000000000c40) $stop;
if (qqs!==61'h1fffcf5187c76510) $stop;
if (rqs!==61'h1ffffffffffffd08) $stop;
end
if (cyc==5) begin
a[60] <= 1'b1; divisor[60] <= 1'b1; // Signed
if (qq!==61'h0000000000000000) $stop;
if (rq!==61'h0d20a48e00f395b8) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h0d20a48e00f395b8) $stop;
end
if (cyc==6) begin
if (qq!==61'h0000000000000001) $stop;
if (rq!==61'h0d20a48e00f3869d) $stop;
if (qqs!==61'h0000000000000000) $stop;
if (rqs!==61'h1d20a48e00f395b8) $stop;
end
// Div by zero
if (cyc==9) begin
divisor <= 61'd0;
end
if (cyc==10) begin
`ifdef verilator
if (qq !== {61{1'b0}}) $stop;
if (rq !== {61{1'b0}}) $stop;
`else
if (qq !== {61{1'bx}}) $stop;
if (rq !== {61{1'bx}}) $stop;
`endif
if ({16{1'bx}} !== 16'd1/16'd0) $stop; // No div by zero errors
if ({16{1'bx}} !== 16'd1%16'd0) $stop; // No div by zero errors
end
if (cyc==19) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
end
endmodule
|
//Legal Notice: (C)2012 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_test_component_ram_module (
// inputs:
data,
rdaddress,
rdclken,
wraddress,
wrclock,
wren,
// outputs:
q
)
;
output [ 15: 0] q;
input [ 15: 0] data;
input [ 21: 0] rdaddress;
input rdclken;
input [ 21: 0] wraddress;
input wrclock;
input wren;
reg [ 15: 0] mem_array [4194303: 0];
wire [ 15: 0] q;
reg [ 21: 0] read_address;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
always @(rdaddress)
begin
read_address = rdaddress;
end
// Data read is asynchronous.
assign q = mem_array[read_address];
initial
$readmemh("sdram_0.dat", mem_array);
always @(posedge wrclock)
begin
// Write data
if (wren)
mem_array[wraddress] <= data;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
//synthesis read_comments_as_HDL on
// always @(rdaddress)
// begin
// read_address = rdaddress;
// end
//
//
// lpm_ram_dp lpm_ram_dp_component
// (
// .data (data),
// .q (q),
// .rdaddress (read_address),
// .rdclken (rdclken),
// .wraddress (wraddress),
// .wrclock (wrclock),
// .wren (wren)
// );
//
// defparam lpm_ram_dp_component.lpm_file = "UNUSED",
// lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
// lpm_ram_dp_component.lpm_indata = "REGISTERED",
// lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
// lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
// lpm_ram_dp_component.lpm_width = 16,
// lpm_ram_dp_component.lpm_widthad = 22,
// lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
// lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_test_component (
// inputs:
clk,
zs_addr,
zs_ba,
zs_cas_n,
zs_cke,
zs_cs_n,
zs_dqm,
zs_ras_n,
zs_we_n,
// outputs:
zs_dq
)
;
inout [ 15: 0] zs_dq;
input clk;
input [ 11: 0] zs_addr;
input [ 1: 0] zs_ba;
input zs_cas_n;
input zs_cke;
input zs_cs_n;
input [ 1: 0] zs_dqm;
input zs_ras_n;
input zs_we_n;
wire [ 23: 0] CODE;
wire [ 11: 0] a;
wire [ 7: 0] addr_col;
reg [ 13: 0] addr_crb;
wire [ 1: 0] ba;
wire cas_n;
wire cke;
wire [ 2: 0] cmd_code;
wire cs_n;
wire [ 1: 0] dqm;
wire [ 2: 0] index;
reg [ 2: 0] latency;
wire [ 1: 0] mask;
wire [ 15: 0] mem_bytes;
wire ras_n;
reg [ 21: 0] rd_addr_pipe_0;
reg [ 21: 0] rd_addr_pipe_1;
reg [ 21: 0] rd_addr_pipe_2;
reg [ 1: 0] rd_mask_pipe_0;
reg [ 1: 0] rd_mask_pipe_1;
reg [ 1: 0] rd_mask_pipe_2;
reg [ 2: 0] rd_valid_pipe;
wire [ 21: 0] read_addr;
wire [ 15: 0] read_data;
wire [ 1: 0] read_mask;
wire [ 15: 0] read_temp;
wire read_valid;
wire [ 15: 0] rmw_temp;
wire [ 21: 0] test_addr;
wire [ 23: 0] txt_code;
wire we_n;
wire [ 15: 0] zs_dq;
initial
begin
$write("\n");
$write("************************************************************\n");
$write("This testbench includes an SOPC Builder Generated Altera model:\n");
$write("'sdram_0_test_component.v', to simulate accesses to SDRAM.\n");
$write("Initial contents are loaded from the file: 'sdram_0.dat'.\n");
$write("************************************************************\n");
end
//Synchronous write when (CODE == 24'h205752 (write))
sdram_0_test_component_ram_module sdram_0_test_component_ram
(
.data (rmw_temp),
.q (read_data),
.rdaddress ((CODE == 24'h205752) ? test_addr : read_addr),
.rdclken (1'b1),
.wraddress (test_addr),
.wrclock (clk),
.wren (CODE == 24'h205752)
);
assign cke = zs_cke;
assign cs_n = zs_cs_n;
assign ras_n = zs_ras_n;
assign cas_n = zs_cas_n;
assign we_n = zs_we_n;
assign dqm = zs_dqm;
assign ba = zs_ba;
assign a = zs_addr;
assign cmd_code = {ras_n, cas_n, we_n};
assign CODE = (&cs_n) ? 24'h494e48 : txt_code;
assign addr_col = a[7 : 0];
assign test_addr = {addr_crb, addr_col};
assign mem_bytes = read_data;
assign rmw_temp[7 : 0] = dqm[0] ? mem_bytes[7 : 0] : zs_dq[7 : 0];
assign rmw_temp[15 : 8] = dqm[1] ? mem_bytes[15 : 8] : zs_dq[15 : 8];
// Handle Input.
always @(posedge clk)
begin
// No Activity of Clock Disabled
if (cke)
begin
// LMR: Get CAS_Latency.
if (CODE == 24'h4c4d52)
latency <= a[6 : 4];
// ACT: Get Row/Bank Address.
if (CODE == 24'h414354)
addr_crb <= {ba[1], a, ba[0]};
rd_valid_pipe[2] <= rd_valid_pipe[1];
rd_valid_pipe[1] <= rd_valid_pipe[0];
rd_valid_pipe[0] <= CODE == 24'h205244;
rd_addr_pipe_2 <= rd_addr_pipe_1;
rd_addr_pipe_1 <= rd_addr_pipe_0;
rd_addr_pipe_0 <= test_addr;
rd_mask_pipe_2 <= rd_mask_pipe_1;
rd_mask_pipe_1 <= rd_mask_pipe_0;
rd_mask_pipe_0 <= dqm;
end
end
assign read_temp[7 : 0] = mask[0] ? 8'bz : read_data[7 : 0];
assign read_temp[15 : 8] = mask[1] ? 8'bz : read_data[15 : 8];
//use index to select which pipeline stage drives addr
assign read_addr = (index == 0)? rd_addr_pipe_0 :
(index == 1)? rd_addr_pipe_1 :
rd_addr_pipe_2;
//use index to select which pipeline stage drives mask
assign read_mask = (index == 0)? rd_mask_pipe_0 :
(index == 1)? rd_mask_pipe_1 :
rd_mask_pipe_2;
//use index to select which pipeline stage drives valid
assign read_valid = (index == 0)? rd_valid_pipe[0] :
(index == 1)? rd_valid_pipe[1] :
rd_valid_pipe[2];
assign index = latency - 1'b1;
assign mask = read_mask;
assign zs_dq = read_valid ? read_temp : {16{1'bz}};
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
assign txt_code = (cmd_code == 3'h0)? 24'h4c4d52 :
(cmd_code == 3'h1)? 24'h415246 :
(cmd_code == 3'h2)? 24'h505245 :
(cmd_code == 3'h3)? 24'h414354 :
(cmd_code == 3'h4)? 24'h205752 :
(cmd_code == 3'h5)? 24'h205244 :
(cmd_code == 3'h6)? 24'h425354 :
(cmd_code == 3'h7)? 24'h4e4f50 :
24'h424144;
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
|
`include "defines.v"
module cp0_reg(
input wire clk,
input wire rst,
input wire we_i,
input wire[4:0] waddr_i,
input wire[4:0] raddr_i,
input wire[`RegBus] data_i,
input wire[31:0] excepttype_i,
input wire[5:0] int_i,
input wire[`RegBus] current_inst_addr_i,
input wire is_in_delayslot_i,
output reg[`RegBus] data_o,
output reg[`RegBus] count_o,
output reg[`RegBus] compare_o,
output reg[`RegBus] status_o,
output reg[`RegBus] cause_o,
output reg[`RegBus] epc_o,
output reg[`RegBus] config_o,
output reg[`RegBus] prid_o,
output reg timer_int_o
);
always @ (posedge clk) begin
if(rst == `RstEnable) begin
count_o <= `ZeroWord;
compare_o <= `ZeroWord;
//status¼Ä´æÆ÷µÄCUΪ0001£¬±íʾд¦ÀíÆ÷CP0´æÔÚ
status_o <= 32'b00010000000000000000000000000000;
cause_o <= `ZeroWord;
epc_o <= `ZeroWord;
//config¼Ä´æÆ÷µÄBEΪ1£¬±íʾBig-Endian£»MTΪ00£¬±íʾûÓÐMMU
config_o <= 32'b00000000000000001000000000000000;
//ÖÆ×÷ÕßÊÇL£¬¶ÔÓ¦µÄÊÇ0x48£¬ÀàÐÍÊÇ0x1£¬»ù±¾ÀàÐÍ£¬°æ±¾ºÅÊÇ1.0
prid_o <= 32'b00000000010011000000000100000010;
timer_int_o <= `InterruptNotAssert;
end else begin
count_o <= count_o + 1 ;
cause_o[15:10] <= int_i;
if(compare_o != `ZeroWord && count_o == compare_o) begin
timer_int_o <= `InterruptAssert;
end
if(we_i == `WriteEnable) begin
case (waddr_i)
`CP0_REG_COUNT: begin
count_o <= data_i;
end
`CP0_REG_COMPARE: begin
compare_o <= data_i;
//count_o <= `ZeroWord;
timer_int_o <= `InterruptNotAssert;
end
`CP0_REG_STATUS: begin
status_o <= data_i;
end
`CP0_REG_EPC: begin
epc_o <= data_i;
end
`CP0_REG_CAUSE: begin
//cause¼Ä´æÆ÷Ö»ÓÐIP[1:0]¡¢IV¡¢WP×Ö¶ÎÊÇ¿ÉдµÄ
cause_o[9:8] <= data_i[9:8];
cause_o[23] <= data_i[23];
cause_o[22] <= data_i[22];
end
endcase //case addr_i
end
case (excepttype_i)
32'h00000001: begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b00000;
end
32'h00000008: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01000;
end
32'h0000000a: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01010;
end
32'h0000000d: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
cause_o[31] <= 1'b1;
end else begin
epc_o <= current_inst_addr_i;
cause_o[31] <= 1'b0;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01101;
end
32'h0000000c: begin
if(status_o[1] == 1'b0) begin
if(is_in_delayslot_i == `InDelaySlot ) begin
epc_o <= current_inst_addr_i - 4 ;
end else begin
epc_o <= current_inst_addr_i;
end
end
status_o[1] <= 1'b1;
cause_o[6:2] <= 5'b01100;
end
32'h0000000e: begin
status_o[1] <= 1'b0;
end
default: begin
end
endcase
end //if
end //always
always @ (*) begin
if(rst == `RstEnable) begin
data_o <= `ZeroWord;
end else begin
case (raddr_i)
`CP0_REG_COUNT: begin
data_o <= count_o ;
end
`CP0_REG_COMPARE: begin
data_o <= compare_o ;
end
`CP0_REG_STATUS: begin
data_o <= status_o ;
end
`CP0_REG_CAUSE: begin
data_o <= cause_o ;
end
`CP0_REG_EPC: begin
data_o <= epc_o ;
end
`CP0_REG_PrId: begin
data_o <= prid_o ;
end
`CP0_REG_CONFIG: begin
data_o <= config_o ;
end
default: begin
end
endcase //case addr_i
end //if
end //always
endmodule |
///////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995/2005 Xilinx, Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 10.1i
// \ \ Description : Xilinx Timing Simulation Library Component
// / / Source Synchronous Output Serializer
// /___/ /\ Filename : OSERDES.v
// \ \ / \ Timestamp : Thu Mar 11 16:44:07 PST 2005
// \___\/\___\
//
// Revision:
// 03/23/04 - Initial version.
// 03/11/05 - Added LOC parameter, removed GSR ports and initialized outpus.
// 05/30/06 - CR 232324 -- Added timing checks for SR/REV wrt negedge CLKDIV
// 08/21/06 - CR 210819 -- Added timing checks for DDR mode
// 06/06/07 - Fixed timescale values
// 01/08/08 - CR 458156 -- enabled TRISTATE_WIDTH to be 1 in DDR mode.
// 04/16/08 - CR 468871 Negative SetupHold fix
// 04/23/09 - CR 516748 simprim only fix
// 06/01/09 - CR 523601 simprim only (timing) fix for Tristate Output
// 12/13/11 - Added `celldefine and `endcelldefine (CR 524859).
// 10/22/14 - Added #1 to $finish (CR 808642).
// End Revision
`timescale 1 ps / 1 ps
`celldefine
module OSERDES (OQ, SHIFTOUT1, SHIFTOUT2, TQ,
CLK, CLKDIV, D1, D2, D3, D4, D5, D6, OCE, REV, SHIFTIN1, SHIFTIN2, SR, T1, T2, T3, T4, TCE);
parameter DATA_RATE_OQ = "DDR";
parameter DATA_RATE_TQ = "DDR";
parameter integer DATA_WIDTH = 4;
parameter [0:0] INIT_OQ = 1'b0;
parameter [0:0] INIT_TQ = 1'b0;
parameter SERDES_MODE = "MASTER";
parameter [0:0] SRVAL_OQ = 1'b0;
parameter [0:0] SRVAL_TQ = 1'b0;
parameter integer TRISTATE_WIDTH = 4;
`ifdef XIL_TIMING
parameter LOC = "UNPLACED";
`endif
output OQ;
output SHIFTOUT1;
output SHIFTOUT2;
output TQ;
input CLK;
input CLKDIV;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
tri0 GSR = glbl.GSR;
input OCE;
input REV;
input SHIFTIN1;
input SHIFTIN2;
input SR;
input T1;
input T2;
input T3;
input T4;
input TCE;
reg c23, c45, c67;
reg t1r, t2r, t3r, t4r;
reg io_sdata_edge, io_odata_edge, io_ddr_data;
reg iot_sdata_edge, iot_odata_edge, iot_ddr_data;
reg data1, data2, data3, data4, data5, data6;
reg serdes_mode_int, serdes_int;
reg data_rate_oq_int, ddr_clk_edge_int;
reg [1:0] data_rate_tq_int, tristate_width_int;
reg [1:0] sel;
reg d1r, d2r, d3r, d4r, d5r, d6r;
reg q0, q1, q2, q3;
reg d1rnk2, d2rnk2, d2nrnk2, d3rnk2, d4rnk2, d5rnk2, d6rnk2;
reg qt1, qt2, qt2n;
reg load, qhr, qlr, mux;
reg data1t, data2t;
reg oq_out = INIT_OQ, tq_out = INIT_TQ;
reg [3:0] data_width_int;
reg notifier;
wire oqsr, oqrev;
wire tqsr, tqrev;
wire c2p, c3;
wire [2:0] sel1_4;
wire [3:0] sel5_6;
wire [4:0] sel_tri;
wire [6:0] seltq;
wire [3:0] seloq;
wire clk_in;
wire clkdiv_in;
wire d1_in;
wire d2_in;
wire d3_in;
wire d4_in;
wire d5_in;
wire d6_in;
wire gsr_in;
wire oce_in;
wire sr_in;
wire rev_in;
wire shiftin1_in;
wire shiftin2_in;
wire t1_in;
wire t2_in;
wire t3_in;
wire t4_in;
wire tce_in;
wire shiftout1_out;
wire shiftout2_out;
buf b_oq (OQ, oq_out);
buf b_shiftout1 (SHIFTOUT1, shiftout1_out);
buf b_shiftout2 (SHIFTOUT2, shiftout2_out);
buf b_tq (TQ, tq_out);
buf b_clk (clk_in, CLK);
buf b_clkdiv (clkdiv_in, CLKDIV);
buf b_d1 (d1_in, D1);
buf b_d2 (d2_in, D2);
buf b_d3 (d3_in, D3);
buf b_d4 (d4_in, D4);
buf b_d5 (d5_in, D5);
buf b_d6 (d6_in, D6);
buf b_gsr (gsr_in, GSR);
buf b_oce (oce_in, OCE);
buf b_r (sr_in, SR);
buf b_s (rev_in, REV);
buf b_shiftin1 (shiftin1_in, SHIFTIN1);
buf b_shiftin2 (shiftin2_in, SHIFTIN2);
buf b_t1 (t1_in, T1);
buf b_t2 (t2_in, T2);
buf b_t3 (t3_in, T3);
buf b_t4 (t4_in, T4);
buf b_tce (tce_in, TCE);
// workaround for XSIM
wire rev_in_AND_NOT_sr_in = rev_in & !sr_in;
wire NOT_rev_in_AND_sr_in = !rev_in & sr_in;
/////////////////////////////////////////////////////////
//
// Delay assignments
//
/////////////////////////////////////////////////////////
// Data output delays
localparam io_ffd = 1; // clock to out delay for flip flops driven by clk
localparam io_ffcd = 1; // clock to out delay for flip flops driven by clkdiv
localparam io_mxd = 1; // 60 ps mux delay
localparam io_mxr1 = 1; // mux before 2nd rank of flops
// Programmable load generator
localparam ffdcnt = 1;
localparam mxdcnt = 1;
// CR 516748
// localparam ffrst = 145; // clock to out delay for flop in PLSG
localparam ffrst = 45; // clock to out delay for flop in PLSG
// Tristate output delays
localparam iot_ffd = 1;
// CR 523601
// localparam iot_mxd = 1;
localparam iot_mxd = 20;
/////////////////////////////////////////////////////////////
always @(gsr_in)
if (gsr_in) begin
assign oq_out = INIT_OQ;
assign d1rnk2 = INIT_OQ;
assign d2rnk2 = INIT_OQ;
assign d2nrnk2 = INIT_OQ;
assign d6rnk2 = 1'b0;
assign d5rnk2 = 1'b0;
assign d4rnk2 = 1'b0;
assign d3rnk2 = 1'b0;
assign d6r = 1'b0;
assign d5r = 1'b0;
assign d4r = 1'b0;
assign d3r = 1'b0;
assign d2r = 1'b0;
assign d1r = 1'b0;
// PLG
assign q3 = 1'b0;
assign q2 = 1'b0;
assign q1 = 1'b0;
assign q0 = 1'b0;
// Tristate output
assign tq_out = INIT_TQ;
assign qt1 = INIT_TQ;
assign qt2 = INIT_TQ;
assign qt2n = INIT_TQ;
assign t4r = 1'b0;
assign t3r = 1'b0;
assign t2r = 1'b0;
assign t1r = 1'b0;
end
else begin
deassign oq_out;
deassign d1rnk2;
deassign d2rnk2;
deassign d2nrnk2;
deassign d6rnk2;
deassign d5rnk2;
deassign d4rnk2;
deassign d3rnk2;
deassign d6r;
deassign d5r;
deassign d4r;
deassign d3r;
deassign d2r;
deassign d1r;
// PLG
deassign q3;
deassign q2;
deassign q1;
deassign q0;
// Tristate output
deassign tq_out;
deassign qt1;
deassign qt2;
deassign qt2n;
deassign t4r;
deassign t3r;
deassign t2r;
deassign t1r;
end
initial begin
case (SERDES_MODE)
"MASTER" : serdes_mode_int <= 1'b0;
"SLAVE" : serdes_mode_int <= 1'b1;
default : begin
$display("Attribute Syntax Error : The attribute SERDES_MODE on OSERDES instance %m is set to %s. Legal values for this attribute are MASTER or SLAVE", SERDES_MODE);
#1 $finish;
end
endcase // case(SERDES_MODE)
serdes_int <= 1'b1; // SERDES = TRUE
ddr_clk_edge_int <= 1'b1; // DDR_CLK_EDGE = SAME_EDGE
case (DATA_RATE_OQ)
"SDR" : data_rate_oq_int <= 1'b1;
"DDR" : data_rate_oq_int <= 1'b0;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_OQ on OSERDES instance %m is set to %s. Legal values for this attribute are SDR or DDR", DATA_RATE_OQ);
#1 $finish;
end
endcase // case(DATA_RATE_OQ)
case (DATA_WIDTH)
2, 3, 4, 5, 6, 7, 8, 10 : data_width_int = DATA_WIDTH[3:0];
default : begin
$display("Attribute Syntax Error : The attribute DATA_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 2, 3, 4, 5, 6, 7, 8, or 10", DATA_WIDTH);
#1 $finish;
end
endcase // case(DATA_WIDTH)
case (DATA_RATE_TQ)
"BUF" : data_rate_tq_int <= 2'b00;
"SDR" : data_rate_tq_int <= 2'b01;
"DDR" : data_rate_tq_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute DATA_RATE_TQ on OSERDES instance %m is set to %s. Legal values for this attribute are BUF, SDR or DDR", DATA_RATE_TQ);
#1 $finish;
end
endcase // case(DATA_RATE_TQ)
case (TRISTATE_WIDTH)
1 : tristate_width_int <= 2'b00;
2 : tristate_width_int <= 2'b01;
4 : tristate_width_int <= 2'b10;
default : begin
$display("Attribute Syntax Error : The attribute TRISTATE_WIDTH on OSERDES instance %m is set to %d. Legal values for this attribute are 1, 2 or 4", TRISTATE_WIDTH);
#1 $finish;
end
endcase // case(TRISTATE_WIDTH)
end // initial begin
assign shiftout1_out = d3rnk2 & serdes_mode_int;
assign shiftout2_out = d4rnk2 & serdes_mode_int;
assign c2p = (clk_in & ddr_clk_edge_int) | (!clk_in & !ddr_clk_edge_int);
assign c3 = !c2p;
assign sel1_4 = {serdes_int, load, data_rate_oq_int};
assign sel5_6 = {serdes_int, serdes_mode_int, load, data_rate_oq_int};
// Tristate output
assign sel_tri = {load, data_rate_tq_int, tristate_width_int};
assign seloq = {oce_in, data_rate_oq_int, oqsr, oqrev};
assign seltq = {tce_in, data_rate_tq_int, tristate_width_int, tqsr, tqrev};
assign oqsr = (sr_in & !SRVAL_OQ) | (rev_in & SRVAL_OQ);
assign oqrev = (sr_in & SRVAL_OQ) | (rev_in & !SRVAL_OQ);
assign tqsr = (sr_in & !SRVAL_TQ) | (rev_in & SRVAL_TQ);
assign tqrev = (sr_in & SRVAL_TQ) | (rev_in & !SRVAL_TQ);
// 3 flops to create DDR operations of 4 latches
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d1rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d1rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d1rnk2 <= # io_ffd data1;
else if (oce_in == 1'b0) // to match with HW
d1rnk2 <= # io_ffd oq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2rnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2rnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2rnk2 <= # io_ffd data2;
else if (oce_in == 1'b0) // to match with HW
d2rnk2 <= # io_ffd oq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_OQ == 1'b1))
d2nrnk2 <= # io_ffd SRVAL_OQ;
else if (rev_in == 1'b1)
d2nrnk2 <= # io_ffd !SRVAL_OQ;
else if (oce_in == 1'b1)
d2nrnk2 <= # io_ffd d2rnk2;
else if (oce_in == 1'b0) // to match with HW
d2nrnk2 <= # io_ffd oq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// last 4 flops which only have reset and init
// asynchronous operation
always @ (posedge clk_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d3rnk2 <= # io_ffd 1'b0;
d4rnk2 <= # io_ffd 1'b0;
d5rnk2 <= # io_ffd 1'b0;
d6rnk2 <= # io_ffd 1'b0;
end
else begin
d3rnk2 <= # io_ffd data3;
d4rnk2 <= # io_ffd data4;
d5rnk2 <= # io_ffd data5;
d6rnk2 <= # io_ffd data6;
end
end // always @ (posedge clk_in or posedge sr_in)
// First rank of flops for input data
// asynchronous operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
d1r <= # io_ffcd 1'b0;
d2r <= # io_ffcd 1'b0;
d3r <= # io_ffcd 1'b0;
d4r <= # io_ffcd 1'b0;
d5r <= # io_ffcd 1'b0;
d6r <= # io_ffcd 1'b0;
end
else begin
d1r <= # io_ffcd d1_in;
d2r <= # io_ffcd d2_in;
d3r <= # io_ffcd d3_in;
d4r <= # io_ffcd d4_in;
d5r <= # io_ffcd d5_in;
d6r <= # io_ffcd d6_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Muxs for 2nd rank of flops
always @ (sel1_4 or d1r or d2rnk2 or d3rnk2) begin
casex (sel1_4)
3'b100: data1 <= # io_mxr1 d3rnk2;
3'b110: data1 <= # io_mxr1 d1r;
3'b101: data1 <= # io_mxr1 d2rnk2;
3'b111: data1 <= # io_mxr1 d1r;
default: data1 <= # io_mxr1 d3rnk2;
endcase
end
always @ (sel1_4 or d2r or d3rnk2 or d4rnk2) begin
casex (sel1_4)
3'b100: data2 <= # io_mxr1 d4rnk2;
3'b110: data2 <= # io_mxr1 d2r;
3'b101: data2 <= # io_mxr1 d3rnk2;
3'b111: data2 <= # io_mxr1 d2r;
default: data2 <= # io_mxr1 d4rnk2;
endcase
end
//Note: To stop data rate of 00 from being illegal, register data is fed to mux
always @ (sel1_4 or d3r or d4rnk2 or d5rnk2) begin
casex (sel1_4)
3'b100: data3 <= # io_mxr1 d5rnk2;
3'b110: data3 <= # io_mxr1 d3r;
3'b101: data3 <= # io_mxr1 d4rnk2;
3'b111: data3 <= # io_mxr1 d3r;
default: data3 <= # io_mxr1 d5rnk2;
endcase
end
always @ (sel1_4 or d4r or d5rnk2 or d6rnk2) begin
casex (sel1_4)
3'b100: data4 <= # io_mxr1 d6rnk2;
3'b110: data4 <= # io_mxr1 d4r;
3'b101: data4 <= # io_mxr1 d5rnk2;
3'b111: data4 <= # io_mxr1 d4r;
default: data4 <= # io_mxr1 d6rnk2;
endcase
end
always @ (sel5_6 or d5r or d6rnk2 or shiftin1_in) begin
casex (sel5_6)
4'b1000: data5 <= # io_mxr1 shiftin1_in;
4'b1010: data5 <= # io_mxr1 d5r;
4'b1001: data5 <= # io_mxr1 d6rnk2;
4'b1011: data5 <= # io_mxr1 d5r;
4'b1100: data5 <= # io_mxr1 1'b0;
4'b1110: data5 <= # io_mxr1 d5r;
4'b1101: data5 <= # io_mxr1 d6rnk2;
4'b1111: data5 <= # io_mxr1 d5r;
default: data5 <= # io_mxr1 shiftin1_in;
endcase
end
always @ (sel5_6 or D6 or d6r or shiftin1_in or shiftin2_in) begin
casex (sel5_6)
4'b1000: data6 <= # io_mxr1 shiftin2_in;
4'b1010: data6 <= # io_mxr1 d6r;
4'b1001: data6 <= # io_mxr1 shiftin1_in;
4'b1011: data6 <= # io_mxr1 d6r;
4'b1100: data6 <= # io_mxr1 1'b0;
4'b1110: data6 <= # io_mxr1 d6r;
4'b1101: data6 <= # io_mxr1 1'b0;
4'b1111: data6 <= # io_mxr1 d6r;
default: data6 <= # io_mxr1 shiftin2_in;
endcase
end
// Logic to generate same edge data from d1rnk2 and d2nrnk2;
always @ (clk_in or c3 or d1rnk2 or d2nrnk2) begin
io_sdata_edge <= # io_mxd (d1rnk2 & clk_in) | (d2nrnk2 & c3);
end
// Mux to create opposite edge DDR data from d1rnk2 and d2rnk2
always @(clk_in or d1rnk2 or d2rnk2) begin
case (clk_in)
1'b0: io_odata_edge <= # io_mxd d2rnk2;
1'b1: io_odata_edge <= # io_mxd d1rnk2;
default: io_odata_edge <= # io_mxd d1rnk2;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @(io_sdata_edge or io_odata_edge or ddr_clk_edge_int) begin
io_ddr_data <= # io_mxd (io_odata_edge & !ddr_clk_edge_int) | (io_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate OQ
always @ (seloq or d1rnk2 or io_ddr_data or oq_out) begin
casex (seloq)
4'bXX01: oq_out <= # io_mxd 1'b1;
4'bXX10: oq_out <= # io_mxd 1'b0;
4'bXX11: oq_out <= # io_mxd 1'b0;
4'b0000: oq_out <= # io_mxd oq_out;
4'b0100: oq_out <= # io_mxd oq_out;
4'b1000: oq_out <= # io_mxd io_ddr_data;
4'b1100: oq_out <= # io_mxd d1rnk2;
default: oq_out <= # io_mxd io_ddr_data;
endcase
end
// Set value of counter in bitslip controller
always @ (data_rate_oq_int or data_width_int) begin
casex ({data_rate_oq_int, data_width_int})
5'b00100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b00110: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b01000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b01010: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10010: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10011: begin c23 <= 1'b1; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b00; end
5'b10100: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b01; end
5'b10101: begin c23 <= 1'b0; c45 <= 1'b1; c67 <= 1'b0; sel <= 2'b01; end
5'b10110: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b10; end
5'b10111: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b1; sel <= 2'b10; end
5'b11000: begin c23 <= 1'b0; c45 <= 1'b0; c67 <= 1'b0; sel <= 2'b11; end
default: begin
$display("DATA_WIDTH %d and DATA_RATE_OQ %s at time %t ns are illegal.", DATA_WIDTH, DATA_RATE_OQ, $time/1000.0);
$finish;
end
endcase
end // always @ (data_rate_oq_int or data_width_int)
///////////////////////////////////////////////////////////////
// Programmable Load Generator (PLG)
// Divide by 2-8 counter with load enable output
//////////////////////////////////////////////////////////////////
// flops for counter
// asynchronous reset
always @ (posedge qhr or posedge clk_in) begin
if (qhr) begin
q0 <= # ffdcnt 1'b0;
q1 <= # ffdcnt 1'b0;
q2 <= # ffdcnt 1'b0;
q3 <= # ffdcnt 1'b0;
end
else begin
q3 <= # ffdcnt q2;
q2 <= # ffdcnt (!(!q0 & !q2) & q1);
q1 <= # ffdcnt q0;
q0 <= # ffdcnt mux;
end
end // always @ (posedge qhr or posedge clk_in)
// mux settings for counter
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: mux <= # mxdcnt (!q0 & !(c23 & q1));
2'b01: mux <= # mxdcnt (!q1 & !(c45 & q2));
2'b10: mux <= # mxdcnt (!q2 & !(c67 & q3));
2'b11: mux <= # mxdcnt !q3;
default: mux <= # mxdcnt 1'b0;
endcase
end
// mux decoding for load signal
always @ (sel or c23 or c45 or c67 or q0 or q1 or q2 or q3) begin
case (sel)
2'b00: load <= # mxdcnt q0;
2'b01: load <= # mxdcnt q0 & q1;
2'b10: load <= # mxdcnt q0 & q2;
2'b11: load <= # mxdcnt q0 & q3;
default: load <= # mxdcnt 1'b0;
endcase
end
// flops to reset counter
// Low speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clkdiv_in) begin
if (sr_in == 1'b1)
qlr <= # ffrst 1'b1;
else
qlr <= # ffrst 1'b0;
end // always @ (posedge sr_in or posedge clkdiv_in)
// High speed flop
// asynchronous reset
always @ (posedge sr_in or posedge clk_in) begin
if (sr_in == 1'b1)
qhr <= # ffdcnt 1'b1;
else
qhr <= # ffdcnt qlr;
end // always @ (posedge sr_in or posedge clk_in)
///////////////////////////////////////////////////////
//
// Tristate Output cell
//
////////////////////////////////////////////////////////
// 3 flops to create DDR operations of 4 latches
// Representation of top latch
// asynchronous operation
always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt1 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt1 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt1 <= # iot_ffd data1t;
else if (tce_in == 1'b0)
qt1 <= # iot_ffd tq_out;
end // always @ (posedge clk_in or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 2nd latch
// asynchronous operation
always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2 <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2 <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2 <= # iot_ffd data2t;
else if (tce_in == 1'b0)
qt2 <= # iot_ffd tq_out;
end // always @ (posedge c2p or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// Representation of 3rd flop ( latch and output latch)
// asynchronous operation
always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in) begin
if (sr_in == 1'b1 & !(rev_in == 1'b1 & SRVAL_TQ == 1'b1))
qt2n <= # iot_ffd SRVAL_TQ;
else if (rev_in == 1'b1)
qt2n <= # iot_ffd !SRVAL_TQ;
else if (tce_in == 1'b1)
qt2n <= # iot_ffd qt2;
else if (tce_in == 1'b0)
qt2n <= # iot_ffd tq_out;
end // always @ (posedge c3 or posedge sr_in or posedge rev_in or posedge rev_in_AND_NOT_sr_in or posedge NOT_rev_in_AND_sr_in)
// First rank of flops
// asynchronous reset operation
always @ (posedge clkdiv_in or posedge sr_in) begin
if (sr_in == 1'b1) begin
t1r <= # iot_ffd 1'b0;
t2r <= # iot_ffd 1'b0;
t3r <= # iot_ffd 1'b0;
t4r <= # iot_ffd 1'b0;
end
else begin
t1r <= # iot_ffd t1_in;
t2r <= # iot_ffd t2_in;
t3r <= # iot_ffd t3_in;
t4r <= # iot_ffd t4_in;
end
end // always @ (posedge clkdiv_in or posedge sr_in)
// Data Muxs for tristate otuput signals
always @ (sel_tri or t1_in or t1r or t3r) begin
casex (sel_tri)
5'b00000: data1t <= # iot_mxd t1_in;
5'b10000: data1t <= # iot_mxd t1_in;
5'bX0000: data1t <= # iot_mxd t1_in;
5'b00100: data1t <= # iot_mxd t1_in;
5'b10100: data1t <= # iot_mxd t1_in;
5'bX0100: data1t <= # iot_mxd t1_in;
5'b01001: data1t <= # iot_mxd t1_in;
5'b11001: data1t <= # iot_mxd t1_in;
5'b01010: data1t <= # iot_mxd t3r;
5'b11010: data1t <= # iot_mxd t1r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// For data 2, width of 1 is inserted as acceptable for buf and sdr
// The capability exists in the device if the feature is added
always @ (sel_tri or t2_in or t2r or t4r) begin
casex (sel_tri)
5'b00000: data2t <= # iot_mxd t2_in;
5'b00100: data2t <= # iot_mxd t2_in;
5'b10000: data2t <= # iot_mxd t2_in;
5'b10100: data2t <= # iot_mxd t2_in;
5'bX0000: data2t <= # iot_mxd t2_in;
5'bX0100: data2t <= # iot_mxd t2_in;
5'b00X00: data2t <= # iot_mxd t2_in;
5'b10X00: data2t <= # iot_mxd t2_in;
5'bX0X00: data2t <= # iot_mxd t2_in;
5'b01001: data2t <= # iot_mxd t2_in;
5'b11001: data2t <= # iot_mxd t2_in;
5'bX1001: data2t <= # iot_mxd t2_in;
5'b01010: data2t <= # iot_mxd t4r;
5'b11010: data2t <= # iot_mxd t2r;
// CR 458156 -- allow/enabled TRISTATE_WIDTH to be 1 in DDR mode. No func change, but removed warnings
5'b01000: ;
5'b11000: ;
5'bX1000: ;
default: begin
$display("DATA_RATE_TQ %s and/or TRISTATE_WIDTH %d at time %t ns are not supported by OSERDES", DATA_RATE_TQ, TRISTATE_WIDTH, $time/1000.0);
$finish;
end
endcase
end
// Logic to generate same edge data from qt1, qt3;
always @ (clk_in or c3 or qt1 or qt2n) begin
iot_sdata_edge <= # iot_mxd (qt1 & clk_in) | (qt2n & c3);
end
// Mux to create opposite edge DDR function
always @ (clk_in or qt1 or qt2) begin
case (clk_in)
1'b0: iot_odata_edge <= # iot_mxd qt2;
1'b1: iot_odata_edge <= # iot_mxd qt1;
default: iot_odata_edge <= 1'b0;
endcase
end
// Logic to same edge and opposite data into just ddr data
always @ (iot_sdata_edge or iot_odata_edge or ddr_clk_edge_int) begin
iot_ddr_data <= # iot_mxd (iot_odata_edge & !ddr_clk_edge_int) | (iot_sdata_edge & ddr_clk_edge_int);
end
// Output mux to generate TQ
// Note that the TQ mux can also support T2 combinatorial or
// registered outputs. Those modes are not support in this model.
always @ (seltq or data1t or iot_ddr_data or qt1 or tq_out) begin
casex (seltq)
7'bX01XX01: tq_out <= # iot_mxd 1'b1;
7'bX10XX01: tq_out <= # iot_mxd 1'b1;
7'bX01XX10: tq_out <= # iot_mxd 1'b0;
7'bX10XX10: tq_out <= # iot_mxd 1'b0;
7'bX01XX11: tq_out <= # iot_mxd 1'b0;
7'bX10XX11: tq_out <= # iot_mxd 1'b0;
7'bX0000XX: tq_out <= # iot_mxd data1t;
7'b0010000: tq_out <= # iot_mxd tq_out;
7'b0100100: tq_out <= # iot_mxd tq_out;
7'b0101000: tq_out <= # iot_mxd tq_out;
7'b1010000: tq_out <= # iot_mxd qt1;
7'b1100100: tq_out <= # iot_mxd iot_ddr_data;
7'b1101000: tq_out <= # iot_mxd iot_ddr_data;
default: tq_out <= # iot_mxd iot_ddr_data;
endcase
end
//*** Timing Checks Start here
`ifndef XIL_TIMING
assign clk_in = CLK;
assign oce_in = OCE;
assign tce_in = TCE;
assign clkdiv_in = CLKDIV;
assign d1_in = D1;
assign d2_in = D2;
assign d3_in = D3;
assign d4_in = D4;
assign d5_in = D5;
assign d6_in = D6;
assign rev_in = REV;
assign sr_in = SR;
assign t1_in = T1;
assign t2_in = T2;
assign t3_in = T3;
assign t4_in = T4;
`endif
specify
(CLK => OQ) = (100:100:100, 100:100:100);
(CLK => TQ) = (100:100:100, 100:100:100);
`ifdef XIL_TIMING
(SR => OQ) = (0:0:0, 0:0:0);
(REV => OQ) = (0:0:0, 0:0:0);
(T1 => TQ) = (0:0:0, 0:0:0);
(SR => TQ) = (0:0:0, 0:0:0);
(REV => TQ) = (0:0:0, 0:0:0);
$setuphold (posedge CLKDIV, posedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, negedge D1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d1_in);
$setuphold (posedge CLKDIV, posedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, negedge D2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d2_in);
$setuphold (posedge CLKDIV, posedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, negedge D3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d3_in);
$setuphold (posedge CLKDIV, posedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, negedge D4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d4_in);
$setuphold (posedge CLKDIV, posedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, negedge D5, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d5_in);
$setuphold (posedge CLKDIV, posedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLKDIV, negedge D6, 0:0:0, 0:0:0, notifier, , , clkdiv_in, d6_in);
$setuphold (posedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (posedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (posedge CLKDIV, posedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, negedge T1, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t1_in);
$setuphold (posedge CLKDIV, posedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, negedge T2, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t2_in);
$setuphold (posedge CLKDIV, posedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, negedge T3, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t3_in);
$setuphold (posedge CLKDIV, posedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLKDIV, negedge T4, 0:0:0, 0:0:0, notifier, , , clkdiv_in, t4_in);
$setuphold (posedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, posedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (negedge CLK, negedge OCE, 0:0:0, 0:0:0, notifier, , , clk_in, oce_in);
$setuphold (posedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (posedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, posedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$setuphold (negedge CLK, negedge TCE, 0:0:0, 0:0:0, notifier, , , clk_in, tce_in);
$period (posedge CLK, 0:0:0, notifier);
$period (posedge CLKDIV, 0:0:0, notifier);
$recrem (negedge REV, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, posedge CLKDIV, 0:0:0, 0:0:0, notifier);
// CR 232324
$setuphold (posedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, posedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (negedge CLKDIV, negedge REV, 0:0:0, 0:0:0, notifier, , , clkdiv_in, rev_in);
$setuphold (posedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (posedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, posedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
$setuphold (negedge CLKDIV, negedge SR, 0:0:0, 0:0:0, notifier, , , clkdiv_in, sr_in);
// CR 210819
$setuphold (negedge CLK, posedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, negedge T1, 0:0:0, 0:0:0, notifier, , , clk_in, t1_in);
$setuphold (negedge CLK, posedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$setuphold (negedge CLK, negedge T2, 0:0:0, 0:0:0, notifier, , , clk_in, t2_in);
$recrem (negedge REV, negedge CLK, 0:0:0, 0:0:0, notifier);
$recrem (negedge SR, negedge CLK, 0:0:0, 0:0:0, notifier);
$width (posedge CLK, 0:0:0, 0, notifier);
$width (posedge CLKDIV, 0:0:0, 0, notifier);
$width (negedge CLK, 0:0:0, 0, notifier);
$width (negedge CLKDIV, 0:0:0, 0, notifier);
`endif
specparam PATHPULSE$ = 0;
endspecify
endmodule // OSERDES
`endcelldefine
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file DMA_READ_QUEUE.v when simulating
// the core, DMA_READ_QUEUE. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module DMA_READ_QUEUE(
clk,
srst,
din,
wr_en,
rd_en,
dout,
full,
empty
);
input clk;
input srst;
input [63 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(1),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(5),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(0),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(0),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(1),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(0),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(2),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("512x72"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(15),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(14),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(5),
.C_RD_DEPTH(16),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(4),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(1),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(5),
.C_WR_DEPTH(16),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(4),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.CLK(clk),
.SRST(srst),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.BACKUP(),
.BACKUP_MARKER(),
.RST(),
.WR_CLK(),
.WR_RST(),
.RD_CLK(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
///////////////////////////////////////////////////////
// Copyright (c) 2011 Xilinx Inc.
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
///////////////////////////////////////////////////////
//
// ____ ___
// / /\/ /
// /___/ \ / Vendor : Xilinx
// \ \ \/ Version : 13.1
// \ \ Description :
// / /
// /__/ /\ Filename : PCIE_3_0.uniprim.v
// \ \ / \
// \__\/\__ \
//
// Generated by : /home/chen/xfoundry/HEAD/env/Databases/CAEInterfaces/LibraryWriters/bin/ltw.pl
// Revision: 1.0
// 01/18/13 - 695630 - added drp monitor
///////////////////////////////////////////////////////
`timescale 1 ps / 1 ps
`celldefine
module PCIE_3_0 (
CFGCURRENTSPEED,
CFGDPASUBSTATECHANGE,
CFGERRCOROUT,
CFGERRFATALOUT,
CFGERRNONFATALOUT,
CFGEXTFUNCTIONNUMBER,
CFGEXTREADRECEIVED,
CFGEXTREGISTERNUMBER,
CFGEXTWRITEBYTEENABLE,
CFGEXTWRITEDATA,
CFGEXTWRITERECEIVED,
CFGFCCPLD,
CFGFCCPLH,
CFGFCNPD,
CFGFCNPH,
CFGFCPD,
CFGFCPH,
CFGFLRINPROCESS,
CFGFUNCTIONPOWERSTATE,
CFGFUNCTIONSTATUS,
CFGHOTRESETOUT,
CFGINPUTUPDATEDONE,
CFGINTERRUPTAOUTPUT,
CFGINTERRUPTBOUTPUT,
CFGINTERRUPTCOUTPUT,
CFGINTERRUPTDOUTPUT,
CFGINTERRUPTMSIDATA,
CFGINTERRUPTMSIENABLE,
CFGINTERRUPTMSIFAIL,
CFGINTERRUPTMSIMASKUPDATE,
CFGINTERRUPTMSIMMENABLE,
CFGINTERRUPTMSISENT,
CFGINTERRUPTMSIVFENABLE,
CFGINTERRUPTMSIXENABLE,
CFGINTERRUPTMSIXFAIL,
CFGINTERRUPTMSIXMASK,
CFGINTERRUPTMSIXSENT,
CFGINTERRUPTMSIXVFENABLE,
CFGINTERRUPTMSIXVFMASK,
CFGINTERRUPTSENT,
CFGLINKPOWERSTATE,
CFGLOCALERROR,
CFGLTRENABLE,
CFGLTSSMSTATE,
CFGMAXPAYLOAD,
CFGMAXREADREQ,
CFGMCUPDATEDONE,
CFGMGMTREADDATA,
CFGMGMTREADWRITEDONE,
CFGMSGRECEIVED,
CFGMSGRECEIVEDDATA,
CFGMSGRECEIVEDTYPE,
CFGMSGTRANSMITDONE,
CFGNEGOTIATEDWIDTH,
CFGOBFFENABLE,
CFGPERFUNCSTATUSDATA,
CFGPERFUNCTIONUPDATEDONE,
CFGPHYLINKDOWN,
CFGPHYLINKSTATUS,
CFGPLSTATUSCHANGE,
CFGPOWERSTATECHANGEINTERRUPT,
CFGRCBSTATUS,
CFGTPHFUNCTIONNUM,
CFGTPHREQUESTERENABLE,
CFGTPHSTMODE,
CFGTPHSTTADDRESS,
CFGTPHSTTREADENABLE,
CFGTPHSTTWRITEBYTEVALID,
CFGTPHSTTWRITEDATA,
CFGTPHSTTWRITEENABLE,
CFGVFFLRINPROCESS,
CFGVFPOWERSTATE,
CFGVFSTATUS,
CFGVFTPHREQUESTERENABLE,
CFGVFTPHSTMODE,
DBGDATAOUT,
DRPDO,
DRPRDY,
MAXISCQTDATA,
MAXISCQTKEEP,
MAXISCQTLAST,
MAXISCQTUSER,
MAXISCQTVALID,
MAXISRCTDATA,
MAXISRCTKEEP,
MAXISRCTLAST,
MAXISRCTUSER,
MAXISRCTVALID,
MICOMPLETIONRAMREADADDRESSAL,
MICOMPLETIONRAMREADADDRESSAU,
MICOMPLETIONRAMREADADDRESSBL,
MICOMPLETIONRAMREADADDRESSBU,
MICOMPLETIONRAMREADENABLEL,
MICOMPLETIONRAMREADENABLEU,
MICOMPLETIONRAMWRITEADDRESSAL,
MICOMPLETIONRAMWRITEADDRESSAU,
MICOMPLETIONRAMWRITEADDRESSBL,
MICOMPLETIONRAMWRITEADDRESSBU,
MICOMPLETIONRAMWRITEDATAL,
MICOMPLETIONRAMWRITEDATAU,
MICOMPLETIONRAMWRITEENABLEL,
MICOMPLETIONRAMWRITEENABLEU,
MIREPLAYRAMADDRESS,
MIREPLAYRAMREADENABLE,
MIREPLAYRAMWRITEDATA,
MIREPLAYRAMWRITEENABLE,
MIREQUESTRAMREADADDRESSA,
MIREQUESTRAMREADADDRESSB,
MIREQUESTRAMREADENABLE,
MIREQUESTRAMWRITEADDRESSA,
MIREQUESTRAMWRITEADDRESSB,
MIREQUESTRAMWRITEDATA,
MIREQUESTRAMWRITEENABLE,
PCIECQNPREQCOUNT,
PCIERQSEQNUM,
PCIERQSEQNUMVLD,
PCIERQTAG,
PCIERQTAGAV,
PCIERQTAGVLD,
PCIETFCNPDAV,
PCIETFCNPHAV,
PIPERX0EQCONTROL,
PIPERX0EQLPLFFS,
PIPERX0EQLPTXPRESET,
PIPERX0EQPRESET,
PIPERX0POLARITY,
PIPERX1EQCONTROL,
PIPERX1EQLPLFFS,
PIPERX1EQLPTXPRESET,
PIPERX1EQPRESET,
PIPERX1POLARITY,
PIPERX2EQCONTROL,
PIPERX2EQLPLFFS,
PIPERX2EQLPTXPRESET,
PIPERX2EQPRESET,
PIPERX2POLARITY,
PIPERX3EQCONTROL,
PIPERX3EQLPLFFS,
PIPERX3EQLPTXPRESET,
PIPERX3EQPRESET,
PIPERX3POLARITY,
PIPERX4EQCONTROL,
PIPERX4EQLPLFFS,
PIPERX4EQLPTXPRESET,
PIPERX4EQPRESET,
PIPERX4POLARITY,
PIPERX5EQCONTROL,
PIPERX5EQLPLFFS,
PIPERX5EQLPTXPRESET,
PIPERX5EQPRESET,
PIPERX5POLARITY,
PIPERX6EQCONTROL,
PIPERX6EQLPLFFS,
PIPERX6EQLPTXPRESET,
PIPERX6EQPRESET,
PIPERX6POLARITY,
PIPERX7EQCONTROL,
PIPERX7EQLPLFFS,
PIPERX7EQLPTXPRESET,
PIPERX7EQPRESET,
PIPERX7POLARITY,
PIPETX0CHARISK,
PIPETX0COMPLIANCE,
PIPETX0DATA,
PIPETX0DATAVALID,
PIPETX0ELECIDLE,
PIPETX0EQCONTROL,
PIPETX0EQDEEMPH,
PIPETX0EQPRESET,
PIPETX0POWERDOWN,
PIPETX0STARTBLOCK,
PIPETX0SYNCHEADER,
PIPETX1CHARISK,
PIPETX1COMPLIANCE,
PIPETX1DATA,
PIPETX1DATAVALID,
PIPETX1ELECIDLE,
PIPETX1EQCONTROL,
PIPETX1EQDEEMPH,
PIPETX1EQPRESET,
PIPETX1POWERDOWN,
PIPETX1STARTBLOCK,
PIPETX1SYNCHEADER,
PIPETX2CHARISK,
PIPETX2COMPLIANCE,
PIPETX2DATA,
PIPETX2DATAVALID,
PIPETX2ELECIDLE,
PIPETX2EQCONTROL,
PIPETX2EQDEEMPH,
PIPETX2EQPRESET,
PIPETX2POWERDOWN,
PIPETX2STARTBLOCK,
PIPETX2SYNCHEADER,
PIPETX3CHARISK,
PIPETX3COMPLIANCE,
PIPETX3DATA,
PIPETX3DATAVALID,
PIPETX3ELECIDLE,
PIPETX3EQCONTROL,
PIPETX3EQDEEMPH,
PIPETX3EQPRESET,
PIPETX3POWERDOWN,
PIPETX3STARTBLOCK,
PIPETX3SYNCHEADER,
PIPETX4CHARISK,
PIPETX4COMPLIANCE,
PIPETX4DATA,
PIPETX4DATAVALID,
PIPETX4ELECIDLE,
PIPETX4EQCONTROL,
PIPETX4EQDEEMPH,
PIPETX4EQPRESET,
PIPETX4POWERDOWN,
PIPETX4STARTBLOCK,
PIPETX4SYNCHEADER,
PIPETX5CHARISK,
PIPETX5COMPLIANCE,
PIPETX5DATA,
PIPETX5DATAVALID,
PIPETX5ELECIDLE,
PIPETX5EQCONTROL,
PIPETX5EQDEEMPH,
PIPETX5EQPRESET,
PIPETX5POWERDOWN,
PIPETX5STARTBLOCK,
PIPETX5SYNCHEADER,
PIPETX6CHARISK,
PIPETX6COMPLIANCE,
PIPETX6DATA,
PIPETX6DATAVALID,
PIPETX6ELECIDLE,
PIPETX6EQCONTROL,
PIPETX6EQDEEMPH,
PIPETX6EQPRESET,
PIPETX6POWERDOWN,
PIPETX6STARTBLOCK,
PIPETX6SYNCHEADER,
PIPETX7CHARISK,
PIPETX7COMPLIANCE,
PIPETX7DATA,
PIPETX7DATAVALID,
PIPETX7ELECIDLE,
PIPETX7EQCONTROL,
PIPETX7EQDEEMPH,
PIPETX7EQPRESET,
PIPETX7POWERDOWN,
PIPETX7STARTBLOCK,
PIPETX7SYNCHEADER,
PIPETXDEEMPH,
PIPETXMARGIN,
PIPETXRATE,
PIPETXRCVRDET,
PIPETXRESET,
PIPETXSWING,
PLEQINPROGRESS,
PLEQPHASE,
PLGEN3PCSRXSLIDE,
SAXISCCTREADY,
SAXISRQTREADY,
CFGCONFIGSPACEENABLE,
CFGDEVID,
CFGDSBUSNUMBER,
CFGDSDEVICENUMBER,
CFGDSFUNCTIONNUMBER,
CFGDSN,
CFGDSPORTNUMBER,
CFGERRCORIN,
CFGERRUNCORIN,
CFGEXTREADDATA,
CFGEXTREADDATAVALID,
CFGFCSEL,
CFGFLRDONE,
CFGHOTRESETIN,
CFGINPUTUPDATEREQUEST,
CFGINTERRUPTINT,
CFGINTERRUPTMSIATTR,
CFGINTERRUPTMSIFUNCTIONNUMBER,
CFGINTERRUPTMSIINT,
CFGINTERRUPTMSIPENDINGSTATUS,
CFGINTERRUPTMSISELECT,
CFGINTERRUPTMSITPHPRESENT,
CFGINTERRUPTMSITPHSTTAG,
CFGINTERRUPTMSITPHTYPE,
CFGINTERRUPTMSIXADDRESS,
CFGINTERRUPTMSIXDATA,
CFGINTERRUPTMSIXINT,
CFGINTERRUPTPENDING,
CFGLINKTRAININGENABLE,
CFGMCUPDATEREQUEST,
CFGMGMTADDR,
CFGMGMTBYTEENABLE,
CFGMGMTREAD,
CFGMGMTTYPE1CFGREGACCESS,
CFGMGMTWRITE,
CFGMGMTWRITEDATA,
CFGMSGTRANSMIT,
CFGMSGTRANSMITDATA,
CFGMSGTRANSMITTYPE,
CFGPERFUNCSTATUSCONTROL,
CFGPERFUNCTIONNUMBER,
CFGPERFUNCTIONOUTPUTREQUEST,
CFGPOWERSTATECHANGEACK,
CFGREQPMTRANSITIONL23READY,
CFGREVID,
CFGSUBSYSID,
CFGSUBSYSVENDID,
CFGTPHSTTREADDATA,
CFGTPHSTTREADDATAVALID,
CFGVENDID,
CFGVFFLRDONE,
CORECLK,
CORECLKMICOMPLETIONRAML,
CORECLKMICOMPLETIONRAMU,
CORECLKMIREPLAYRAM,
CORECLKMIREQUESTRAM,
DRPADDR,
DRPCLK,
DRPDI,
DRPEN,
DRPWE,
MAXISCQTREADY,
MAXISRCTREADY,
MGMTRESETN,
MGMTSTICKYRESETN,
MICOMPLETIONRAMREADDATA,
MIREPLAYRAMREADDATA,
MIREQUESTRAMREADDATA,
PCIECQNPREQ,
PIPECLK,
PIPEEQFS,
PIPEEQLF,
PIPERESETN,
PIPERX0CHARISK,
PIPERX0DATA,
PIPERX0DATAVALID,
PIPERX0ELECIDLE,
PIPERX0EQDONE,
PIPERX0EQLPADAPTDONE,
PIPERX0EQLPLFFSSEL,
PIPERX0EQLPNEWTXCOEFFORPRESET,
PIPERX0PHYSTATUS,
PIPERX0STARTBLOCK,
PIPERX0STATUS,
PIPERX0SYNCHEADER,
PIPERX0VALID,
PIPERX1CHARISK,
PIPERX1DATA,
PIPERX1DATAVALID,
PIPERX1ELECIDLE,
PIPERX1EQDONE,
PIPERX1EQLPADAPTDONE,
PIPERX1EQLPLFFSSEL,
PIPERX1EQLPNEWTXCOEFFORPRESET,
PIPERX1PHYSTATUS,
PIPERX1STARTBLOCK,
PIPERX1STATUS,
PIPERX1SYNCHEADER,
PIPERX1VALID,
PIPERX2CHARISK,
PIPERX2DATA,
PIPERX2DATAVALID,
PIPERX2ELECIDLE,
PIPERX2EQDONE,
PIPERX2EQLPADAPTDONE,
PIPERX2EQLPLFFSSEL,
PIPERX2EQLPNEWTXCOEFFORPRESET,
PIPERX2PHYSTATUS,
PIPERX2STARTBLOCK,
PIPERX2STATUS,
PIPERX2SYNCHEADER,
PIPERX2VALID,
PIPERX3CHARISK,
PIPERX3DATA,
PIPERX3DATAVALID,
PIPERX3ELECIDLE,
PIPERX3EQDONE,
PIPERX3EQLPADAPTDONE,
PIPERX3EQLPLFFSSEL,
PIPERX3EQLPNEWTXCOEFFORPRESET,
PIPERX3PHYSTATUS,
PIPERX3STARTBLOCK,
PIPERX3STATUS,
PIPERX3SYNCHEADER,
PIPERX3VALID,
PIPERX4CHARISK,
PIPERX4DATA,
PIPERX4DATAVALID,
PIPERX4ELECIDLE,
PIPERX4EQDONE,
PIPERX4EQLPADAPTDONE,
PIPERX4EQLPLFFSSEL,
PIPERX4EQLPNEWTXCOEFFORPRESET,
PIPERX4PHYSTATUS,
PIPERX4STARTBLOCK,
PIPERX4STATUS,
PIPERX4SYNCHEADER,
PIPERX4VALID,
PIPERX5CHARISK,
PIPERX5DATA,
PIPERX5DATAVALID,
PIPERX5ELECIDLE,
PIPERX5EQDONE,
PIPERX5EQLPADAPTDONE,
PIPERX5EQLPLFFSSEL,
PIPERX5EQLPNEWTXCOEFFORPRESET,
PIPERX5PHYSTATUS,
PIPERX5STARTBLOCK,
PIPERX5STATUS,
PIPERX5SYNCHEADER,
PIPERX5VALID,
PIPERX6CHARISK,
PIPERX6DATA,
PIPERX6DATAVALID,
PIPERX6ELECIDLE,
PIPERX6EQDONE,
PIPERX6EQLPADAPTDONE,
PIPERX6EQLPLFFSSEL,
PIPERX6EQLPNEWTXCOEFFORPRESET,
PIPERX6PHYSTATUS,
PIPERX6STARTBLOCK,
PIPERX6STATUS,
PIPERX6SYNCHEADER,
PIPERX6VALID,
PIPERX7CHARISK,
PIPERX7DATA,
PIPERX7DATAVALID,
PIPERX7ELECIDLE,
PIPERX7EQDONE,
PIPERX7EQLPADAPTDONE,
PIPERX7EQLPLFFSSEL,
PIPERX7EQLPNEWTXCOEFFORPRESET,
PIPERX7PHYSTATUS,
PIPERX7STARTBLOCK,
PIPERX7STATUS,
PIPERX7SYNCHEADER,
PIPERX7VALID,
PIPETX0EQCOEFF,
PIPETX0EQDONE,
PIPETX1EQCOEFF,
PIPETX1EQDONE,
PIPETX2EQCOEFF,
PIPETX2EQDONE,
PIPETX3EQCOEFF,
PIPETX3EQDONE,
PIPETX4EQCOEFF,
PIPETX4EQDONE,
PIPETX5EQCOEFF,
PIPETX5EQDONE,
PIPETX6EQCOEFF,
PIPETX6EQDONE,
PIPETX7EQCOEFF,
PIPETX7EQDONE,
PLDISABLESCRAMBLER,
PLEQRESETEIEOSCOUNT,
PLGEN3PCSDISABLE,
PLGEN3PCSRXSYNCDONE,
RECCLK,
RESETN,
SAXISCCTDATA,
SAXISCCTKEEP,
SAXISCCTLAST,
SAXISCCTUSER,
SAXISCCTVALID,
SAXISRQTDATA,
SAXISRQTKEEP,
SAXISRQTLAST,
SAXISRQTUSER,
SAXISRQTVALID,
USERCLK
);
`ifdef XIL_TIMING //Simprim
parameter LOC = "UNPLACED";
`endif
parameter ARI_CAP_ENABLE = "FALSE";
parameter AXISTEN_IF_CC_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_CC_PARITY_CHK = "TRUE";
parameter AXISTEN_IF_CQ_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_ENABLE_CLIENT_TAG = "FALSE";
parameter [17:0] AXISTEN_IF_ENABLE_MSG_ROUTE = 18'h00000;
parameter AXISTEN_IF_ENABLE_RX_MSG_INTFC = "FALSE";
parameter AXISTEN_IF_RC_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_RC_STRADDLE = "FALSE";
parameter AXISTEN_IF_RQ_ALIGNMENT_MODE = "FALSE";
parameter AXISTEN_IF_RQ_PARITY_CHK = "TRUE";
parameter [1:0] AXISTEN_IF_WIDTH = 2'h2;
parameter CRM_CORE_CLK_FREQ_500 = "TRUE";
parameter [1:0] CRM_USER_CLK_FREQ = 2'h2;
parameter [7:0] DNSTREAM_LINK_NUM = 8'h00;
parameter [1:0] GEN3_PCS_AUTO_REALIGN = 2'h1;
parameter GEN3_PCS_RX_ELECIDLE_INTERNAL = "TRUE";
parameter [8:0] LL_ACK_TIMEOUT = 9'h000;
parameter LL_ACK_TIMEOUT_EN = "FALSE";
parameter integer LL_ACK_TIMEOUT_FUNC = 0;
parameter [15:0] LL_CPL_FC_UPDATE_TIMER = 16'h0000;
parameter LL_CPL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_FC_UPDATE_TIMER = 16'h0000;
parameter LL_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_NP_FC_UPDATE_TIMER = 16'h0000;
parameter LL_NP_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [15:0] LL_P_FC_UPDATE_TIMER = 16'h0000;
parameter LL_P_FC_UPDATE_TIMER_OVERRIDE = "FALSE";
parameter [8:0] LL_REPLAY_TIMEOUT = 9'h000;
parameter LL_REPLAY_TIMEOUT_EN = "FALSE";
parameter integer LL_REPLAY_TIMEOUT_FUNC = 0;
parameter [9:0] LTR_TX_MESSAGE_MINIMUM_INTERVAL = 10'h0FA;
parameter LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE = "FALSE";
parameter LTR_TX_MESSAGE_ON_LTR_ENABLE = "FALSE";
parameter PF0_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter PF0_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [11:0] PF0_AER_CAP_NEXTPTR = 12'h000;
parameter [11:0] PF0_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] PF0_ARI_CAP_NEXT_FUNC = 8'h00;
parameter [3:0] PF0_ARI_CAP_VER = 4'h1;
parameter [4:0] PF0_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR0_CONTROL = 3'h4;
parameter [4:0] PF0_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF0_BAR1_CONTROL = 3'h0;
parameter [4:0] PF0_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR2_CONTROL = 3'h4;
parameter [4:0] PF0_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR3_CONTROL = 3'h0;
parameter [4:0] PF0_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR4_CONTROL = 3'h4;
parameter [4:0] PF0_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_BAR5_CONTROL = 3'h0;
parameter [7:0] PF0_BIST_REGISTER = 8'h00;
parameter [7:0] PF0_CAPABILITY_POINTER = 8'h50;
parameter [23:0] PF0_CLASS_CODE = 24'h000000;
parameter [15:0] PF0_DEVICE_ID = 16'h0000;
parameter PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT = "TRUE";
parameter PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE = "TRUE";
parameter PF0_DEV_CAP2_LTR_SUPPORT = "TRUE";
parameter [1:0] PF0_DEV_CAP2_OBFF_SUPPORT = 2'h0;
parameter PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT = "FALSE";
parameter integer PF0_DEV_CAP_ENDPOINT_L0S_LATENCY = 0;
parameter integer PF0_DEV_CAP_ENDPOINT_L1_LATENCY = 0;
parameter PF0_DEV_CAP_EXT_TAG_SUPPORTED = "TRUE";
parameter PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE = "TRUE";
parameter [2:0] PF0_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
parameter [11:0] PF0_DPA_CAP_NEXTPTR = 12'h000;
parameter [4:0] PF0_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
parameter PF0_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
parameter [7:0] PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
parameter [3:0] PF0_DPA_CAP_VER = 4'h1;
parameter [11:0] PF0_DSN_CAP_NEXTPTR = 12'h10C;
parameter [4:0] PF0_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
parameter PF0_EXPANSION_ROM_ENABLE = "FALSE";
parameter [7:0] PF0_INTERRUPT_LINE = 8'h00;
parameter [2:0] PF0_INTERRUPT_PIN = 3'h1;
parameter integer PF0_LINK_CAP_ASPM_SUPPORT = 0;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 = 7;
parameter integer PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 = 7;
parameter integer PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 = 7;
parameter PF0_LINK_STATUS_SLOT_CLOCK_CONFIG = "TRUE";
parameter [9:0] PF0_LTR_CAP_MAX_NOSNOOP_LAT = 10'h000;
parameter [9:0] PF0_LTR_CAP_MAX_SNOOP_LAT = 10'h000;
parameter [11:0] PF0_LTR_CAP_NEXTPTR = 12'h000;
parameter [3:0] PF0_LTR_CAP_VER = 4'h1;
parameter [7:0] PF0_MSIX_CAP_NEXTPTR = 8'h00;
parameter integer PF0_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] PF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer PF0_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] PF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] PF0_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer PF0_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] PF0_MSI_CAP_NEXTPTR = 8'h00;
parameter [11:0] PF0_PB_CAP_NEXTPTR = 12'h000;
parameter PF0_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
parameter [3:0] PF0_PB_CAP_VER = 4'h1;
parameter [7:0] PF0_PM_CAP_ID = 8'h01;
parameter [7:0] PF0_PM_CAP_NEXTPTR = 8'h00;
parameter PF0_PM_CAP_PMESUPPORT_D0 = "TRUE";
parameter PF0_PM_CAP_PMESUPPORT_D1 = "TRUE";
parameter PF0_PM_CAP_PMESUPPORT_D3HOT = "TRUE";
parameter PF0_PM_CAP_SUPP_D1_STATE = "TRUE";
parameter [2:0] PF0_PM_CAP_VER_ID = 3'h3;
parameter PF0_PM_CSR_NOSOFTRESET = "TRUE";
parameter PF0_RBAR_CAP_ENABLE = "FALSE";
parameter [2:0] PF0_RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] PF0_RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] PF0_RBAR_CAP_INDEX2 = 3'h0;
parameter [11:0] PF0_RBAR_CAP_NEXTPTR = 12'h000;
parameter [19:0] PF0_RBAR_CAP_SIZE0 = 20'h00000;
parameter [19:0] PF0_RBAR_CAP_SIZE1 = 20'h00000;
parameter [19:0] PF0_RBAR_CAP_SIZE2 = 20'h00000;
parameter [3:0] PF0_RBAR_CAP_VER = 4'h1;
parameter [2:0] PF0_RBAR_NUM = 3'h1;
parameter [7:0] PF0_REVISION_ID = 8'h00;
parameter [4:0] PF0_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR0_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF0_SRIOV_BAR1_CONTROL = 3'h0;
parameter [4:0] PF0_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR2_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR3_CONTROL = 3'h0;
parameter [4:0] PF0_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR4_CONTROL = 3'h4;
parameter [4:0] PF0_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF0_SRIOV_BAR5_CONTROL = 3'h0;
parameter [15:0] PF0_SRIOV_CAP_INITIAL_VF = 16'h0000;
parameter [11:0] PF0_SRIOV_CAP_NEXTPTR = 12'h000;
parameter [15:0] PF0_SRIOV_CAP_TOTAL_VF = 16'h0000;
parameter [3:0] PF0_SRIOV_CAP_VER = 4'h1;
parameter [15:0] PF0_SRIOV_FIRST_VF_OFFSET = 16'h0000;
parameter [15:0] PF0_SRIOV_FUNC_DEP_LINK = 16'h0000;
parameter [31:0] PF0_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
parameter [15:0] PF0_SRIOV_VF_DEVICE_ID = 16'h0000;
parameter [15:0] PF0_SUBSYSTEM_ID = 16'h0000;
parameter PF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter PF0_TPHR_CAP_ENABLE = "FALSE";
parameter PF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] PF0_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] PF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] PF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] PF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] PF0_TPHR_CAP_VER = 4'h1;
parameter [11:0] PF0_VC_CAP_NEXTPTR = 12'h000;
parameter [3:0] PF0_VC_CAP_VER = 4'h1;
parameter PF1_AER_CAP_ECRC_CHECK_CAPABLE = "FALSE";
parameter PF1_AER_CAP_ECRC_GEN_CAPABLE = "FALSE";
parameter [11:0] PF1_AER_CAP_NEXTPTR = 12'h000;
parameter [11:0] PF1_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] PF1_ARI_CAP_NEXT_FUNC = 8'h00;
parameter [4:0] PF1_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR0_CONTROL = 3'h4;
parameter [4:0] PF1_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF1_BAR1_CONTROL = 3'h0;
parameter [4:0] PF1_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR2_CONTROL = 3'h4;
parameter [4:0] PF1_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR3_CONTROL = 3'h0;
parameter [4:0] PF1_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR4_CONTROL = 3'h4;
parameter [4:0] PF1_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_BAR5_CONTROL = 3'h0;
parameter [7:0] PF1_BIST_REGISTER = 8'h00;
parameter [7:0] PF1_CAPABILITY_POINTER = 8'h50;
parameter [23:0] PF1_CLASS_CODE = 24'h000000;
parameter [15:0] PF1_DEVICE_ID = 16'h0000;
parameter [2:0] PF1_DEV_CAP_MAX_PAYLOAD_SIZE = 3'h3;
parameter [11:0] PF1_DPA_CAP_NEXTPTR = 12'h000;
parameter [4:0] PF1_DPA_CAP_SUB_STATE_CONTROL = 5'h00;
parameter PF1_DPA_CAP_SUB_STATE_CONTROL_EN = "TRUE";
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 = 8'h00;
parameter [7:0] PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 = 8'h00;
parameter [3:0] PF1_DPA_CAP_VER = 4'h1;
parameter [11:0] PF1_DSN_CAP_NEXTPTR = 12'h10C;
parameter [4:0] PF1_EXPANSION_ROM_APERTURE_SIZE = 5'h03;
parameter PF1_EXPANSION_ROM_ENABLE = "FALSE";
parameter [7:0] PF1_INTERRUPT_LINE = 8'h00;
parameter [2:0] PF1_INTERRUPT_PIN = 3'h1;
parameter [7:0] PF1_MSIX_CAP_NEXTPTR = 8'h00;
parameter integer PF1_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] PF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer PF1_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] PF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] PF1_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer PF1_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] PF1_MSI_CAP_NEXTPTR = 8'h00;
parameter [11:0] PF1_PB_CAP_NEXTPTR = 12'h000;
parameter PF1_PB_CAP_SYSTEM_ALLOCATED = "FALSE";
parameter [3:0] PF1_PB_CAP_VER = 4'h1;
parameter [7:0] PF1_PM_CAP_ID = 8'h01;
parameter [7:0] PF1_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] PF1_PM_CAP_VER_ID = 3'h3;
parameter PF1_RBAR_CAP_ENABLE = "FALSE";
parameter [2:0] PF1_RBAR_CAP_INDEX0 = 3'h0;
parameter [2:0] PF1_RBAR_CAP_INDEX1 = 3'h0;
parameter [2:0] PF1_RBAR_CAP_INDEX2 = 3'h0;
parameter [11:0] PF1_RBAR_CAP_NEXTPTR = 12'h000;
parameter [19:0] PF1_RBAR_CAP_SIZE0 = 20'h00000;
parameter [19:0] PF1_RBAR_CAP_SIZE1 = 20'h00000;
parameter [19:0] PF1_RBAR_CAP_SIZE2 = 20'h00000;
parameter [3:0] PF1_RBAR_CAP_VER = 4'h1;
parameter [2:0] PF1_RBAR_NUM = 3'h1;
parameter [7:0] PF1_REVISION_ID = 8'h00;
parameter [4:0] PF1_SRIOV_BAR0_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR0_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR1_APERTURE_SIZE = 5'h00;
parameter [2:0] PF1_SRIOV_BAR1_CONTROL = 3'h0;
parameter [4:0] PF1_SRIOV_BAR2_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR2_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR3_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR3_CONTROL = 3'h0;
parameter [4:0] PF1_SRIOV_BAR4_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR4_CONTROL = 3'h4;
parameter [4:0] PF1_SRIOV_BAR5_APERTURE_SIZE = 5'h03;
parameter [2:0] PF1_SRIOV_BAR5_CONTROL = 3'h0;
parameter [15:0] PF1_SRIOV_CAP_INITIAL_VF = 16'h0000;
parameter [11:0] PF1_SRIOV_CAP_NEXTPTR = 12'h000;
parameter [15:0] PF1_SRIOV_CAP_TOTAL_VF = 16'h0000;
parameter [3:0] PF1_SRIOV_CAP_VER = 4'h1;
parameter [15:0] PF1_SRIOV_FIRST_VF_OFFSET = 16'h0000;
parameter [15:0] PF1_SRIOV_FUNC_DEP_LINK = 16'h0000;
parameter [31:0] PF1_SRIOV_SUPPORTED_PAGE_SIZE = 32'h00000000;
parameter [15:0] PF1_SRIOV_VF_DEVICE_ID = 16'h0000;
parameter [15:0] PF1_SUBSYSTEM_ID = 16'h0000;
parameter PF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter PF1_TPHR_CAP_ENABLE = "FALSE";
parameter PF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] PF1_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] PF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] PF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] PF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] PF1_TPHR_CAP_VER = 4'h1;
parameter PL_DISABLE_EI_INFER_IN_L0 = "FALSE";
parameter PL_DISABLE_GEN3_DC_BALANCE = "FALSE";
parameter PL_DISABLE_SCRAMBLING = "FALSE";
parameter PL_DISABLE_UPCONFIG_CAPABLE = "FALSE";
parameter PL_EQ_ADAPT_DISABLE_COEFF_CHECK = "FALSE";
parameter PL_EQ_ADAPT_DISABLE_PRESET_CHECK = "FALSE";
parameter [4:0] PL_EQ_ADAPT_ITER_COUNT = 5'h02;
parameter [1:0] PL_EQ_ADAPT_REJECT_RETRY_COUNT = 2'h1;
parameter PL_EQ_BYPASS_PHASE23 = "FALSE";
parameter PL_EQ_SHORT_ADAPT_PHASE = "FALSE";
parameter [15:0] PL_LANE0_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE1_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE2_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE3_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE4_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE5_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE6_EQ_CONTROL = 16'h3F00;
parameter [15:0] PL_LANE7_EQ_CONTROL = 16'h3F00;
parameter [2:0] PL_LINK_CAP_MAX_LINK_SPEED = 3'h4;
parameter [3:0] PL_LINK_CAP_MAX_LINK_WIDTH = 4'h8;
parameter integer PL_N_FTS_COMCLK_GEN1 = 255;
parameter integer PL_N_FTS_COMCLK_GEN2 = 255;
parameter integer PL_N_FTS_COMCLK_GEN3 = 255;
parameter integer PL_N_FTS_GEN1 = 255;
parameter integer PL_N_FTS_GEN2 = 255;
parameter integer PL_N_FTS_GEN3 = 255;
parameter PL_SIM_FAST_LINK_TRAINING = "FALSE";
parameter PL_UPSTREAM_FACING = "TRUE";
parameter [15:0] PM_ASPML0S_TIMEOUT = 16'h05DC;
parameter [19:0] PM_ASPML1_ENTRY_DELAY = 20'h00000;
parameter PM_ENABLE_SLOT_POWER_CAPTURE = "TRUE";
parameter [31:0] PM_L1_REENTRY_DELAY = 32'h00000000;
parameter [19:0] PM_PME_SERVICE_TIMEOUT_DELAY = 20'h186A0;
parameter [15:0] PM_PME_TURNOFF_ACK_DELAY = 16'h0064;
parameter SIM_VERSION = "1.0";
parameter integer SPARE_BIT0 = 0;
parameter integer SPARE_BIT1 = 0;
parameter integer SPARE_BIT2 = 0;
parameter integer SPARE_BIT3 = 0;
parameter integer SPARE_BIT4 = 0;
parameter integer SPARE_BIT5 = 0;
parameter integer SPARE_BIT6 = 0;
parameter integer SPARE_BIT7 = 0;
parameter integer SPARE_BIT8 = 0;
parameter [7:0] SPARE_BYTE0 = 8'h00;
parameter [7:0] SPARE_BYTE1 = 8'h00;
parameter [7:0] SPARE_BYTE2 = 8'h00;
parameter [7:0] SPARE_BYTE3 = 8'h00;
parameter [31:0] SPARE_WORD0 = 32'h00000000;
parameter [31:0] SPARE_WORD1 = 32'h00000000;
parameter [31:0] SPARE_WORD2 = 32'h00000000;
parameter [31:0] SPARE_WORD3 = 32'h00000000;
parameter SRIOV_CAP_ENABLE = "FALSE";
parameter [23:0] TL_COMPL_TIMEOUT_REG0 = 24'hBEBC20;
parameter [27:0] TL_COMPL_TIMEOUT_REG1 = 28'h0000000;
parameter [11:0] TL_CREDITS_CD = 12'h3E0;
parameter [7:0] TL_CREDITS_CH = 8'h20;
parameter [11:0] TL_CREDITS_NPD = 12'h028;
parameter [7:0] TL_CREDITS_NPH = 8'h20;
parameter [11:0] TL_CREDITS_PD = 12'h198;
parameter [7:0] TL_CREDITS_PH = 8'h20;
parameter TL_ENABLE_MESSAGE_RID_CHECK_ENABLE = "TRUE";
parameter TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
parameter TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE = "FALSE";
parameter TL_LEGACY_MODE_ENABLE = "FALSE";
parameter TL_PF_ENABLE_REG = "FALSE";
parameter TL_TAG_MGMT_ENABLE = "TRUE";
parameter [11:0] VF0_ARI_CAP_NEXTPTR = 12'h000;
parameter [7:0] VF0_CAPABILITY_POINTER = 8'h50;
parameter integer VF0_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF0_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF0_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF0_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF0_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF0_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF0_PM_CAP_ID = 8'h01;
parameter [7:0] VF0_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF0_PM_CAP_VER_ID = 3'h3;
parameter VF0_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF0_TPHR_CAP_ENABLE = "FALSE";
parameter VF0_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF0_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF0_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF0_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF0_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF0_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF1_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF1_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF1_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF1_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF1_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF1_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF1_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF1_PM_CAP_ID = 8'h01;
parameter [7:0] VF1_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF1_PM_CAP_VER_ID = 3'h3;
parameter VF1_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF1_TPHR_CAP_ENABLE = "FALSE";
parameter VF1_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF1_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF1_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF1_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF1_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF1_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF2_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF2_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF2_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF2_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF2_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF2_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF2_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF2_PM_CAP_ID = 8'h01;
parameter [7:0] VF2_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF2_PM_CAP_VER_ID = 3'h3;
parameter VF2_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF2_TPHR_CAP_ENABLE = "FALSE";
parameter VF2_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF2_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF2_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF2_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF2_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF2_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF3_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF3_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF3_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF3_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF3_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF3_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF3_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF3_PM_CAP_ID = 8'h01;
parameter [7:0] VF3_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF3_PM_CAP_VER_ID = 3'h3;
parameter VF3_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF3_TPHR_CAP_ENABLE = "FALSE";
parameter VF3_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF3_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF3_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF3_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF3_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF3_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF4_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF4_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF4_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF4_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF4_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF4_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF4_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF4_PM_CAP_ID = 8'h01;
parameter [7:0] VF4_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF4_PM_CAP_VER_ID = 3'h3;
parameter VF4_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF4_TPHR_CAP_ENABLE = "FALSE";
parameter VF4_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF4_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF4_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF4_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF4_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF4_TPHR_CAP_VER = 4'h1;
parameter [11:0] VF5_ARI_CAP_NEXTPTR = 12'h000;
parameter integer VF5_MSIX_CAP_PBA_BIR = 0;
parameter [28:0] VF5_MSIX_CAP_PBA_OFFSET = 29'h00000050;
parameter integer VF5_MSIX_CAP_TABLE_BIR = 0;
parameter [28:0] VF5_MSIX_CAP_TABLE_OFFSET = 29'h00000040;
parameter [10:0] VF5_MSIX_CAP_TABLE_SIZE = 11'h000;
parameter integer VF5_MSI_CAP_MULTIMSGCAP = 0;
parameter [7:0] VF5_PM_CAP_ID = 8'h01;
parameter [7:0] VF5_PM_CAP_NEXTPTR = 8'h00;
parameter [2:0] VF5_PM_CAP_VER_ID = 3'h3;
parameter VF5_TPHR_CAP_DEV_SPECIFIC_MODE = "TRUE";
parameter VF5_TPHR_CAP_ENABLE = "FALSE";
parameter VF5_TPHR_CAP_INT_VEC_MODE = "TRUE";
parameter [11:0] VF5_TPHR_CAP_NEXTPTR = 12'h000;
parameter [2:0] VF5_TPHR_CAP_ST_MODE_SEL = 3'h0;
parameter [1:0] VF5_TPHR_CAP_ST_TABLE_LOC = 2'h0;
parameter [10:0] VF5_TPHR_CAP_ST_TABLE_SIZE = 11'h000;
parameter [3:0] VF5_TPHR_CAP_VER = 4'h1;
localparam in_delay = 0;
localparam out_delay = 0;
localparam INCLK_DELAY = 0;
localparam OUTCLK_DELAY = 0;
output CFGERRCOROUT;
output CFGERRFATALOUT;
output CFGERRNONFATALOUT;
output CFGEXTREADRECEIVED;
output CFGEXTWRITERECEIVED;
output CFGHOTRESETOUT;
output CFGINPUTUPDATEDONE;
output CFGINTERRUPTAOUTPUT;
output CFGINTERRUPTBOUTPUT;
output CFGINTERRUPTCOUTPUT;
output CFGINTERRUPTDOUTPUT;
output CFGINTERRUPTMSIFAIL;
output CFGINTERRUPTMSIMASKUPDATE;
output CFGINTERRUPTMSISENT;
output CFGINTERRUPTMSIXFAIL;
output CFGINTERRUPTMSIXSENT;
output CFGINTERRUPTSENT;
output CFGLOCALERROR;
output CFGLTRENABLE;
output CFGMCUPDATEDONE;
output CFGMGMTREADWRITEDONE;
output CFGMSGRECEIVED;
output CFGMSGTRANSMITDONE;
output CFGPERFUNCTIONUPDATEDONE;
output CFGPHYLINKDOWN;
output CFGPLSTATUSCHANGE;
output CFGPOWERSTATECHANGEINTERRUPT;
output CFGTPHSTTREADENABLE;
output CFGTPHSTTWRITEENABLE;
output DRPRDY;
output MAXISCQTLAST;
output MAXISCQTVALID;
output MAXISRCTLAST;
output MAXISRCTVALID;
output PCIERQSEQNUMVLD;
output PCIERQTAGVLD;
output PIPERX0POLARITY;
output PIPERX1POLARITY;
output PIPERX2POLARITY;
output PIPERX3POLARITY;
output PIPERX4POLARITY;
output PIPERX5POLARITY;
output PIPERX6POLARITY;
output PIPERX7POLARITY;
output PIPETX0COMPLIANCE;
output PIPETX0DATAVALID;
output PIPETX0ELECIDLE;
output PIPETX0STARTBLOCK;
output PIPETX1COMPLIANCE;
output PIPETX1DATAVALID;
output PIPETX1ELECIDLE;
output PIPETX1STARTBLOCK;
output PIPETX2COMPLIANCE;
output PIPETX2DATAVALID;
output PIPETX2ELECIDLE;
output PIPETX2STARTBLOCK;
output PIPETX3COMPLIANCE;
output PIPETX3DATAVALID;
output PIPETX3ELECIDLE;
output PIPETX3STARTBLOCK;
output PIPETX4COMPLIANCE;
output PIPETX4DATAVALID;
output PIPETX4ELECIDLE;
output PIPETX4STARTBLOCK;
output PIPETX5COMPLIANCE;
output PIPETX5DATAVALID;
output PIPETX5ELECIDLE;
output PIPETX5STARTBLOCK;
output PIPETX6COMPLIANCE;
output PIPETX6DATAVALID;
output PIPETX6ELECIDLE;
output PIPETX6STARTBLOCK;
output PIPETX7COMPLIANCE;
output PIPETX7DATAVALID;
output PIPETX7ELECIDLE;
output PIPETX7STARTBLOCK;
output PIPETXDEEMPH;
output PIPETXRCVRDET;
output PIPETXRESET;
output PIPETXSWING;
output PLEQINPROGRESS;
output [11:0] CFGFCCPLD;
output [11:0] CFGFCNPD;
output [11:0] CFGFCPD;
output [11:0] CFGVFSTATUS;
output [143:0] MIREPLAYRAMWRITEDATA;
output [143:0] MIREQUESTRAMWRITEDATA;
output [15:0] CFGPERFUNCSTATUSDATA;
output [15:0] DBGDATAOUT;
output [15:0] DRPDO;
output [17:0] CFGVFPOWERSTATE;
output [17:0] CFGVFTPHSTMODE;
output [1:0] CFGDPASUBSTATECHANGE;
output [1:0] CFGFLRINPROCESS;
output [1:0] CFGINTERRUPTMSIENABLE;
output [1:0] CFGINTERRUPTMSIXENABLE;
output [1:0] CFGINTERRUPTMSIXMASK;
output [1:0] CFGLINKPOWERSTATE;
output [1:0] CFGOBFFENABLE;
output [1:0] CFGPHYLINKSTATUS;
output [1:0] CFGRCBSTATUS;
output [1:0] CFGTPHREQUESTERENABLE;
output [1:0] MIREPLAYRAMREADENABLE;
output [1:0] MIREPLAYRAMWRITEENABLE;
output [1:0] PCIERQTAGAV;
output [1:0] PCIETFCNPDAV;
output [1:0] PCIETFCNPHAV;
output [1:0] PIPERX0EQCONTROL;
output [1:0] PIPERX1EQCONTROL;
output [1:0] PIPERX2EQCONTROL;
output [1:0] PIPERX3EQCONTROL;
output [1:0] PIPERX4EQCONTROL;
output [1:0] PIPERX5EQCONTROL;
output [1:0] PIPERX6EQCONTROL;
output [1:0] PIPERX7EQCONTROL;
output [1:0] PIPETX0CHARISK;
output [1:0] PIPETX0EQCONTROL;
output [1:0] PIPETX0POWERDOWN;
output [1:0] PIPETX0SYNCHEADER;
output [1:0] PIPETX1CHARISK;
output [1:0] PIPETX1EQCONTROL;
output [1:0] PIPETX1POWERDOWN;
output [1:0] PIPETX1SYNCHEADER;
output [1:0] PIPETX2CHARISK;
output [1:0] PIPETX2EQCONTROL;
output [1:0] PIPETX2POWERDOWN;
output [1:0] PIPETX2SYNCHEADER;
output [1:0] PIPETX3CHARISK;
output [1:0] PIPETX3EQCONTROL;
output [1:0] PIPETX3POWERDOWN;
output [1:0] PIPETX3SYNCHEADER;
output [1:0] PIPETX4CHARISK;
output [1:0] PIPETX4EQCONTROL;
output [1:0] PIPETX4POWERDOWN;
output [1:0] PIPETX4SYNCHEADER;
output [1:0] PIPETX5CHARISK;
output [1:0] PIPETX5EQCONTROL;
output [1:0] PIPETX5POWERDOWN;
output [1:0] PIPETX5SYNCHEADER;
output [1:0] PIPETX6CHARISK;
output [1:0] PIPETX6EQCONTROL;
output [1:0] PIPETX6POWERDOWN;
output [1:0] PIPETX6SYNCHEADER;
output [1:0] PIPETX7CHARISK;
output [1:0] PIPETX7EQCONTROL;
output [1:0] PIPETX7POWERDOWN;
output [1:0] PIPETX7SYNCHEADER;
output [1:0] PIPETXRATE;
output [1:0] PLEQPHASE;
output [255:0] MAXISCQTDATA;
output [255:0] MAXISRCTDATA;
output [2:0] CFGCURRENTSPEED;
output [2:0] CFGMAXPAYLOAD;
output [2:0] CFGMAXREADREQ;
output [2:0] CFGTPHFUNCTIONNUM;
output [2:0] PIPERX0EQPRESET;
output [2:0] PIPERX1EQPRESET;
output [2:0] PIPERX2EQPRESET;
output [2:0] PIPERX3EQPRESET;
output [2:0] PIPERX4EQPRESET;
output [2:0] PIPERX5EQPRESET;
output [2:0] PIPERX6EQPRESET;
output [2:0] PIPERX7EQPRESET;
output [2:0] PIPETXMARGIN;
output [31:0] CFGEXTWRITEDATA;
output [31:0] CFGINTERRUPTMSIDATA;
output [31:0] CFGMGMTREADDATA;
output [31:0] CFGTPHSTTWRITEDATA;
output [31:0] PIPETX0DATA;
output [31:0] PIPETX1DATA;
output [31:0] PIPETX2DATA;
output [31:0] PIPETX3DATA;
output [31:0] PIPETX4DATA;
output [31:0] PIPETX5DATA;
output [31:0] PIPETX6DATA;
output [31:0] PIPETX7DATA;
output [3:0] CFGEXTWRITEBYTEENABLE;
output [3:0] CFGNEGOTIATEDWIDTH;
output [3:0] CFGTPHSTTWRITEBYTEVALID;
output [3:0] MICOMPLETIONRAMREADENABLEL;
output [3:0] MICOMPLETIONRAMREADENABLEU;
output [3:0] MICOMPLETIONRAMWRITEENABLEL;
output [3:0] MICOMPLETIONRAMWRITEENABLEU;
output [3:0] MIREQUESTRAMREADENABLE;
output [3:0] MIREQUESTRAMWRITEENABLE;
output [3:0] PCIERQSEQNUM;
output [3:0] PIPERX0EQLPTXPRESET;
output [3:0] PIPERX1EQLPTXPRESET;
output [3:0] PIPERX2EQLPTXPRESET;
output [3:0] PIPERX3EQLPTXPRESET;
output [3:0] PIPERX4EQLPTXPRESET;
output [3:0] PIPERX5EQLPTXPRESET;
output [3:0] PIPERX6EQLPTXPRESET;
output [3:0] PIPERX7EQLPTXPRESET;
output [3:0] PIPETX0EQPRESET;
output [3:0] PIPETX1EQPRESET;
output [3:0] PIPETX2EQPRESET;
output [3:0] PIPETX3EQPRESET;
output [3:0] PIPETX4EQPRESET;
output [3:0] PIPETX5EQPRESET;
output [3:0] PIPETX6EQPRESET;
output [3:0] PIPETX7EQPRESET;
output [3:0] SAXISCCTREADY;
output [3:0] SAXISRQTREADY;
output [4:0] CFGMSGRECEIVEDTYPE;
output [4:0] CFGTPHSTTADDRESS;
output [5:0] CFGFUNCTIONPOWERSTATE;
output [5:0] CFGINTERRUPTMSIMMENABLE;
output [5:0] CFGINTERRUPTMSIVFENABLE;
output [5:0] CFGINTERRUPTMSIXVFENABLE;
output [5:0] CFGINTERRUPTMSIXVFMASK;
output [5:0] CFGLTSSMSTATE;
output [5:0] CFGTPHSTMODE;
output [5:0] CFGVFFLRINPROCESS;
output [5:0] CFGVFTPHREQUESTERENABLE;
output [5:0] PCIECQNPREQCOUNT;
output [5:0] PCIERQTAG;
output [5:0] PIPERX0EQLPLFFS;
output [5:0] PIPERX1EQLPLFFS;
output [5:0] PIPERX2EQLPLFFS;
output [5:0] PIPERX3EQLPLFFS;
output [5:0] PIPERX4EQLPLFFS;
output [5:0] PIPERX5EQLPLFFS;
output [5:0] PIPERX6EQLPLFFS;
output [5:0] PIPERX7EQLPLFFS;
output [5:0] PIPETX0EQDEEMPH;
output [5:0] PIPETX1EQDEEMPH;
output [5:0] PIPETX2EQDEEMPH;
output [5:0] PIPETX3EQDEEMPH;
output [5:0] PIPETX4EQDEEMPH;
output [5:0] PIPETX5EQDEEMPH;
output [5:0] PIPETX6EQDEEMPH;
output [5:0] PIPETX7EQDEEMPH;
output [71:0] MICOMPLETIONRAMWRITEDATAL;
output [71:0] MICOMPLETIONRAMWRITEDATAU;
output [74:0] MAXISRCTUSER;
output [7:0] CFGEXTFUNCTIONNUMBER;
output [7:0] CFGFCCPLH;
output [7:0] CFGFCNPH;
output [7:0] CFGFCPH;
output [7:0] CFGFUNCTIONSTATUS;
output [7:0] CFGMSGRECEIVEDDATA;
output [7:0] MAXISCQTKEEP;
output [7:0] MAXISRCTKEEP;
output [7:0] PLGEN3PCSRXSLIDE;
output [84:0] MAXISCQTUSER;
output [8:0] MIREPLAYRAMADDRESS;
output [8:0] MIREQUESTRAMREADADDRESSA;
output [8:0] MIREQUESTRAMREADADDRESSB;
output [8:0] MIREQUESTRAMWRITEADDRESSA;
output [8:0] MIREQUESTRAMWRITEADDRESSB;
output [9:0] CFGEXTREGISTERNUMBER;
output [9:0] MICOMPLETIONRAMREADADDRESSAL;
output [9:0] MICOMPLETIONRAMREADADDRESSAU;
output [9:0] MICOMPLETIONRAMREADADDRESSBL;
output [9:0] MICOMPLETIONRAMREADADDRESSBU;
output [9:0] MICOMPLETIONRAMWRITEADDRESSAL;
output [9:0] MICOMPLETIONRAMWRITEADDRESSAU;
output [9:0] MICOMPLETIONRAMWRITEADDRESSBL;
output [9:0] MICOMPLETIONRAMWRITEADDRESSBU;
input CFGCONFIGSPACEENABLE;
input CFGERRCORIN;
input CFGERRUNCORIN;
input CFGEXTREADDATAVALID;
input CFGHOTRESETIN;
input CFGINPUTUPDATEREQUEST;
input CFGINTERRUPTMSITPHPRESENT;
input CFGINTERRUPTMSIXINT;
input CFGLINKTRAININGENABLE;
input CFGMCUPDATEREQUEST;
input CFGMGMTREAD;
input CFGMGMTTYPE1CFGREGACCESS;
input CFGMGMTWRITE;
input CFGMSGTRANSMIT;
input CFGPERFUNCTIONOUTPUTREQUEST;
input CFGPOWERSTATECHANGEACK;
input CFGREQPMTRANSITIONL23READY;
input CFGTPHSTTREADDATAVALID;
input CORECLK;
input CORECLKMICOMPLETIONRAML;
input CORECLKMICOMPLETIONRAMU;
input CORECLKMIREPLAYRAM;
input CORECLKMIREQUESTRAM;
input DRPCLK;
input DRPEN;
input DRPWE;
input MGMTRESETN;
input MGMTSTICKYRESETN;
input PCIECQNPREQ;
input PIPECLK;
input PIPERESETN;
input PIPERX0DATAVALID;
input PIPERX0ELECIDLE;
input PIPERX0EQDONE;
input PIPERX0EQLPADAPTDONE;
input PIPERX0EQLPLFFSSEL;
input PIPERX0PHYSTATUS;
input PIPERX0STARTBLOCK;
input PIPERX0VALID;
input PIPERX1DATAVALID;
input PIPERX1ELECIDLE;
input PIPERX1EQDONE;
input PIPERX1EQLPADAPTDONE;
input PIPERX1EQLPLFFSSEL;
input PIPERX1PHYSTATUS;
input PIPERX1STARTBLOCK;
input PIPERX1VALID;
input PIPERX2DATAVALID;
input PIPERX2ELECIDLE;
input PIPERX2EQDONE;
input PIPERX2EQLPADAPTDONE;
input PIPERX2EQLPLFFSSEL;
input PIPERX2PHYSTATUS;
input PIPERX2STARTBLOCK;
input PIPERX2VALID;
input PIPERX3DATAVALID;
input PIPERX3ELECIDLE;
input PIPERX3EQDONE;
input PIPERX3EQLPADAPTDONE;
input PIPERX3EQLPLFFSSEL;
input PIPERX3PHYSTATUS;
input PIPERX3STARTBLOCK;
input PIPERX3VALID;
input PIPERX4DATAVALID;
input PIPERX4ELECIDLE;
input PIPERX4EQDONE;
input PIPERX4EQLPADAPTDONE;
input PIPERX4EQLPLFFSSEL;
input PIPERX4PHYSTATUS;
input PIPERX4STARTBLOCK;
input PIPERX4VALID;
input PIPERX5DATAVALID;
input PIPERX5ELECIDLE;
input PIPERX5EQDONE;
input PIPERX5EQLPADAPTDONE;
input PIPERX5EQLPLFFSSEL;
input PIPERX5PHYSTATUS;
input PIPERX5STARTBLOCK;
input PIPERX5VALID;
input PIPERX6DATAVALID;
input PIPERX6ELECIDLE;
input PIPERX6EQDONE;
input PIPERX6EQLPADAPTDONE;
input PIPERX6EQLPLFFSSEL;
input PIPERX6PHYSTATUS;
input PIPERX6STARTBLOCK;
input PIPERX6VALID;
input PIPERX7DATAVALID;
input PIPERX7ELECIDLE;
input PIPERX7EQDONE;
input PIPERX7EQLPADAPTDONE;
input PIPERX7EQLPLFFSSEL;
input PIPERX7PHYSTATUS;
input PIPERX7STARTBLOCK;
input PIPERX7VALID;
input PIPETX0EQDONE;
input PIPETX1EQDONE;
input PIPETX2EQDONE;
input PIPETX3EQDONE;
input PIPETX4EQDONE;
input PIPETX5EQDONE;
input PIPETX6EQDONE;
input PIPETX7EQDONE;
input PLDISABLESCRAMBLER;
input PLEQRESETEIEOSCOUNT;
input PLGEN3PCSDISABLE;
input RECCLK;
input RESETN;
input SAXISCCTLAST;
input SAXISCCTVALID;
input SAXISRQTLAST;
input SAXISRQTVALID;
input USERCLK;
input [10:0] DRPADDR;
input [143:0] MICOMPLETIONRAMREADDATA;
input [143:0] MIREPLAYRAMREADDATA;
input [143:0] MIREQUESTRAMREADDATA;
input [15:0] CFGDEVID;
input [15:0] CFGSUBSYSID;
input [15:0] CFGSUBSYSVENDID;
input [15:0] CFGVENDID;
input [15:0] DRPDI;
input [17:0] PIPERX0EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX1EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX2EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX3EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX4EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX5EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX6EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPERX7EQLPNEWTXCOEFFORPRESET;
input [17:0] PIPETX0EQCOEFF;
input [17:0] PIPETX1EQCOEFF;
input [17:0] PIPETX2EQCOEFF;
input [17:0] PIPETX3EQCOEFF;
input [17:0] PIPETX4EQCOEFF;
input [17:0] PIPETX5EQCOEFF;
input [17:0] PIPETX6EQCOEFF;
input [17:0] PIPETX7EQCOEFF;
input [18:0] CFGMGMTADDR;
input [1:0] CFGFLRDONE;
input [1:0] CFGINTERRUPTMSITPHTYPE;
input [1:0] CFGINTERRUPTPENDING;
input [1:0] PIPERX0CHARISK;
input [1:0] PIPERX0SYNCHEADER;
input [1:0] PIPERX1CHARISK;
input [1:0] PIPERX1SYNCHEADER;
input [1:0] PIPERX2CHARISK;
input [1:0] PIPERX2SYNCHEADER;
input [1:0] PIPERX3CHARISK;
input [1:0] PIPERX3SYNCHEADER;
input [1:0] PIPERX4CHARISK;
input [1:0] PIPERX4SYNCHEADER;
input [1:0] PIPERX5CHARISK;
input [1:0] PIPERX5SYNCHEADER;
input [1:0] PIPERX6CHARISK;
input [1:0] PIPERX6SYNCHEADER;
input [1:0] PIPERX7CHARISK;
input [1:0] PIPERX7SYNCHEADER;
input [21:0] MAXISCQTREADY;
input [21:0] MAXISRCTREADY;
input [255:0] SAXISCCTDATA;
input [255:0] SAXISRQTDATA;
input [2:0] CFGDSFUNCTIONNUMBER;
input [2:0] CFGFCSEL;
input [2:0] CFGINTERRUPTMSIATTR;
input [2:0] CFGINTERRUPTMSIFUNCTIONNUMBER;
input [2:0] CFGMSGTRANSMITTYPE;
input [2:0] CFGPERFUNCSTATUSCONTROL;
input [2:0] CFGPERFUNCTIONNUMBER;
input [2:0] PIPERX0STATUS;
input [2:0] PIPERX1STATUS;
input [2:0] PIPERX2STATUS;
input [2:0] PIPERX3STATUS;
input [2:0] PIPERX4STATUS;
input [2:0] PIPERX5STATUS;
input [2:0] PIPERX6STATUS;
input [2:0] PIPERX7STATUS;
input [31:0] CFGEXTREADDATA;
input [31:0] CFGINTERRUPTMSIINT;
input [31:0] CFGINTERRUPTMSIXDATA;
input [31:0] CFGMGMTWRITEDATA;
input [31:0] CFGMSGTRANSMITDATA;
input [31:0] CFGTPHSTTREADDATA;
input [31:0] PIPERX0DATA;
input [31:0] PIPERX1DATA;
input [31:0] PIPERX2DATA;
input [31:0] PIPERX3DATA;
input [31:0] PIPERX4DATA;
input [31:0] PIPERX5DATA;
input [31:0] PIPERX6DATA;
input [31:0] PIPERX7DATA;
input [32:0] SAXISCCTUSER;
input [3:0] CFGINTERRUPTINT;
input [3:0] CFGINTERRUPTMSISELECT;
input [3:0] CFGMGMTBYTEENABLE;
input [4:0] CFGDSDEVICENUMBER;
input [59:0] SAXISRQTUSER;
input [5:0] CFGVFFLRDONE;
input [5:0] PIPEEQFS;
input [5:0] PIPEEQLF;
input [63:0] CFGDSN;
input [63:0] CFGINTERRUPTMSIPENDINGSTATUS;
input [63:0] CFGINTERRUPTMSIXADDRESS;
input [7:0] CFGDSBUSNUMBER;
input [7:0] CFGDSPORTNUMBER;
input [7:0] CFGREVID;
input [7:0] PLGEN3PCSRXSYNCDONE;
input [7:0] SAXISCCTKEEP;
input [7:0] SAXISRQTKEEP;
input [8:0] CFGINTERRUPTMSITPHSTTAG;
reg SIM_VERSION_BINARY;
reg [0:0] ARI_CAP_ENABLE_BINARY;
reg [0:0] AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_CC_PARITY_CHK_BINARY;
reg [0:0] AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY;
reg [0:0] AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY;
reg [0:0] AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_RC_STRADDLE_BINARY;
reg [0:0] AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY;
reg [0:0] AXISTEN_IF_RQ_PARITY_CHK_BINARY;
reg [0:0] CRM_CORE_CLK_FREQ_500_BINARY;
reg [0:0] GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY;
reg [0:0] LL_ACK_TIMEOUT_EN_BINARY;
reg [0:0] LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY;
reg [0:0] LL_REPLAY_TIMEOUT_EN_BINARY;
reg [0:0] LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY;
reg [0:0] LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY;
reg [0:0] PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY;
reg [0:0] PF0_DEV_CAP2_LTR_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY;
reg [0:0] PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY;
reg [0:0] PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY;
reg [0:0] PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY;
reg [0:0] PF0_EXPANSION_ROM_ENABLE_BINARY;
reg [0:0] PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY;
reg [0:0] PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D0_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D1_BINARY;
reg [0:0] PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY;
reg [0:0] PF0_PM_CAP_SUPP_D1_STATE_BINARY;
reg [0:0] PF0_PM_CSR_NOSOFTRESET_BINARY;
reg [0:0] PF0_RBAR_CAP_ENABLE_BINARY;
reg [0:0] PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] PF0_TPHR_CAP_ENABLE_BINARY;
reg [0:0] PF0_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY;
reg [0:0] PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY;
reg [0:0] PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY;
reg [0:0] PF1_EXPANSION_ROM_ENABLE_BINARY;
reg [0:0] PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY;
reg [0:0] PF1_RBAR_CAP_ENABLE_BINARY;
reg [0:0] PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] PF1_TPHR_CAP_ENABLE_BINARY;
reg [0:0] PF1_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] PL_DISABLE_EI_INFER_IN_L0_BINARY;
reg [0:0] PL_DISABLE_GEN3_DC_BALANCE_BINARY;
reg [0:0] PL_DISABLE_SCRAMBLING_BINARY;
reg [0:0] PL_DISABLE_UPCONFIG_CAPABLE_BINARY;
reg [0:0] PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY;
reg [0:0] PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY;
reg [0:0] PL_EQ_BYPASS_PHASE23_BINARY;
reg [0:0] PL_EQ_SHORT_ADAPT_PHASE_BINARY;
reg [0:0] PL_SIM_FAST_LINK_TRAINING_BINARY;
reg [0:0] PL_UPSTREAM_FACING_BINARY;
reg [0:0] PM_ENABLE_SLOT_POWER_CAPTURE_BINARY;
reg [0:0] SPARE_BIT0_BINARY;
reg [0:0] SPARE_BIT1_BINARY;
reg [0:0] SPARE_BIT2_BINARY;
reg [0:0] SPARE_BIT3_BINARY;
reg [0:0] SPARE_BIT4_BINARY;
reg [0:0] SPARE_BIT5_BINARY;
reg [0:0] SPARE_BIT6_BINARY;
reg [0:0] SPARE_BIT7_BINARY;
reg [0:0] SPARE_BIT8_BINARY;
reg [0:0] SRIOV_CAP_ENABLE_BINARY;
reg [0:0] TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY;
reg [0:0] TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY;
reg [0:0] TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY;
reg [0:0] TL_LEGACY_MODE_ENABLE_BINARY;
reg [0:0] TL_PF_ENABLE_REG_BINARY;
reg [0:0] TL_TAG_MGMT_ENABLE_BINARY;
reg [0:0] VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF0_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF0_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF1_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF1_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF2_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF2_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF3_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF3_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF4_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF4_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [0:0] VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY;
reg [0:0] VF5_TPHR_CAP_ENABLE_BINARY;
reg [0:0] VF5_TPHR_CAP_INT_VEC_MODE_BINARY;
reg [1:0] LL_ACK_TIMEOUT_FUNC_BINARY;
reg [1:0] LL_REPLAY_TIMEOUT_FUNC_BINARY;
reg [1:0] PF0_LINK_CAP_ASPM_SUPPORT_BINARY;
reg [2:0] PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY;
reg [2:0] PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY;
reg [2:0] PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY;
reg [2:0] PF0_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] PF0_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] PF0_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] PF1_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] PF1_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] PF1_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF0_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF0_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF0_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF1_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF1_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF1_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF2_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF2_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF2_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF3_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF3_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF3_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF4_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF4_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF4_MSI_CAP_MULTIMSGCAP_BINARY;
reg [2:0] VF5_MSIX_CAP_PBA_BIR_BINARY;
reg [2:0] VF5_MSIX_CAP_TABLE_BIR_BINARY;
reg [2:0] VF5_MSI_CAP_MULTIMSGCAP_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN1_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN2_BINARY;
reg [7:0] PL_N_FTS_COMCLK_GEN3_BINARY;
reg [7:0] PL_N_FTS_GEN1_BINARY;
reg [7:0] PL_N_FTS_GEN2_BINARY;
reg [7:0] PL_N_FTS_GEN3_BINARY;
reg notifier;
initial begin
case (ARI_CAP_ENABLE)
"FALSE" : ARI_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : ARI_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute ARI_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", ARI_CAP_ENABLE);
#1 $finish;
end
endcase
case (AXISTEN_IF_CC_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_CC_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CC_ALIGNMENT_MODE);
#1 $finish;
end
endcase
case (AXISTEN_IF_CC_PARITY_CHK)
"TRUE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b1;
"FALSE" : AXISTEN_IF_CC_PARITY_CHK_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CC_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_CC_PARITY_CHK);
#1 $finish;
end
endcase
case (AXISTEN_IF_CQ_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_CQ_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_CQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_CQ_ALIGNMENT_MODE);
#1 $finish;
end
endcase
case (AXISTEN_IF_ENABLE_CLIENT_TAG)
"FALSE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_ENABLE_CLIENT_TAG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_CLIENT_TAG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_CLIENT_TAG);
#1 $finish;
end
endcase
case (AXISTEN_IF_ENABLE_RX_MSG_INTFC)
"FALSE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_ENABLE_RX_MSG_INTFC_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_ENABLE_RX_MSG_INTFC on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_ENABLE_RX_MSG_INTFC);
#1 $finish;
end
endcase
case (AXISTEN_IF_RC_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RC_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_ALIGNMENT_MODE);
#1 $finish;
end
endcase
case (AXISTEN_IF_RC_STRADDLE)
"FALSE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RC_STRADDLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RC_STRADDLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RC_STRADDLE);
#1 $finish;
end
endcase
case (AXISTEN_IF_RQ_ALIGNMENT_MODE)
"FALSE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b0;
"TRUE" : AXISTEN_IF_RQ_ALIGNMENT_MODE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_ALIGNMENT_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", AXISTEN_IF_RQ_ALIGNMENT_MODE);
#1 $finish;
end
endcase
case (AXISTEN_IF_RQ_PARITY_CHK)
"TRUE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b1;
"FALSE" : AXISTEN_IF_RQ_PARITY_CHK_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute AXISTEN_IF_RQ_PARITY_CHK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", AXISTEN_IF_RQ_PARITY_CHK);
#1 $finish;
end
endcase
case (CRM_CORE_CLK_FREQ_500)
"TRUE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b1;
"FALSE" : CRM_CORE_CLK_FREQ_500_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute CRM_CORE_CLK_FREQ_500 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", CRM_CORE_CLK_FREQ_500);
#1 $finish;
end
endcase
case (GEN3_PCS_RX_ELECIDLE_INTERNAL)
"TRUE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b1;
"FALSE" : GEN3_PCS_RX_ELECIDLE_INTERNAL_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute GEN3_PCS_RX_ELECIDLE_INTERNAL on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", GEN3_PCS_RX_ELECIDLE_INTERNAL);
#1 $finish;
end
endcase
case (LL_ACK_TIMEOUT_EN)
"FALSE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_ACK_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_ACK_TIMEOUT_EN);
#1 $finish;
end
endcase
case (LL_CPL_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_CPL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_CPL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_CPL_FC_UPDATE_TIMER_OVERRIDE);
#1 $finish;
end
endcase
case (LL_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_FC_UPDATE_TIMER_OVERRIDE);
#1 $finish;
end
endcase
case (LL_NP_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_NP_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_NP_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_NP_FC_UPDATE_TIMER_OVERRIDE);
#1 $finish;
end
endcase
case (LL_P_FC_UPDATE_TIMER_OVERRIDE)
"FALSE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b0;
"TRUE" : LL_P_FC_UPDATE_TIMER_OVERRIDE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_P_FC_UPDATE_TIMER_OVERRIDE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_P_FC_UPDATE_TIMER_OVERRIDE);
#1 $finish;
end
endcase
case (LL_REPLAY_TIMEOUT_EN)
"FALSE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b0;
"TRUE" : LL_REPLAY_TIMEOUT_EN_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LL_REPLAY_TIMEOUT_EN);
#1 $finish;
end
endcase
case (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE)
"FALSE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b0;
"TRUE" : LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE);
#1 $finish;
end
endcase
case (LTR_TX_MESSAGE_ON_LTR_ENABLE)
"FALSE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b0;
"TRUE" : LTR_TX_MESSAGE_ON_LTR_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute LTR_TX_MESSAGE_ON_LTR_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", LTR_TX_MESSAGE_ON_LTR_ENABLE);
#1 $finish;
end
endcase
case (PF0_AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : PF0_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_CHECK_CAPABLE);
#1 $finish;
end
endcase
case (PF0_AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : PF0_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_AER_CAP_ECRC_GEN_CAPABLE);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT)
"TRUE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE)
"TRUE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_LTR_SUPPORT)
"TRUE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP2_LTR_SUPPORT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_LTR_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP2_LTR_SUPPORT);
#1 $finish;
end
endcase
case (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT)
"FALSE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b0;
"TRUE" : PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT);
#1 $finish;
end
endcase
case (PF0_DEV_CAP_EXT_TAG_SUPPORTED)
"TRUE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP_EXT_TAG_SUPPORTED_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_EXT_TAG_SUPPORTED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_EXT_TAG_SUPPORTED);
#1 $finish;
end
endcase
case (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE)
"TRUE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b1;
"FALSE" : PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE);
#1 $finish;
end
endcase
case (PF0_DPA_CAP_SUB_STATE_CONTROL_EN)
"TRUE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1;
"FALSE" : PF0_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_DPA_CAP_SUB_STATE_CONTROL_EN);
#1 $finish;
end
endcase
case (PF0_EXPANSION_ROM_ENABLE)
"FALSE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_EXPANSION_ROM_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_EXPANSION_ROM_ENABLE);
#1 $finish;
end
endcase
case (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG)
"TRUE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b1;
"FALSE" : PF0_LINK_STATUS_SLOT_CLOCK_CONFIG_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_STATUS_SLOT_CLOCK_CONFIG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_LINK_STATUS_SLOT_CLOCK_CONFIG);
#1 $finish;
end
endcase
case (PF0_PB_CAP_SYSTEM_ALLOCATED)
"FALSE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0;
"TRUE" : PF0_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_PB_CAP_SYSTEM_ALLOCATED);
#1 $finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D0)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D0_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D0);
#1 $finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D1)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D1_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D1 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D1);
#1 $finish;
end
endcase
case (PF0_PM_CAP_PMESUPPORT_D3HOT)
"TRUE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_PMESUPPORT_D3HOT_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_PMESUPPORT_D3HOT on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_PMESUPPORT_D3HOT);
#1 $finish;
end
endcase
case (PF0_PM_CAP_SUPP_D1_STATE)
"TRUE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b1;
"FALSE" : PF0_PM_CAP_SUPP_D1_STATE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CAP_SUPP_D1_STATE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CAP_SUPP_D1_STATE);
#1 $finish;
end
endcase
case (PF0_PM_CSR_NOSOFTRESET)
"TRUE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b1;
"FALSE" : PF0_PM_CSR_NOSOFTRESET_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_PM_CSR_NOSOFTRESET on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_PM_CSR_NOSOFTRESET);
#1 $finish;
end
endcase
case (PF0_RBAR_CAP_ENABLE)
"FALSE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_RBAR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_RBAR_CAP_ENABLE);
#1 $finish;
end
endcase
case (PF0_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : PF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (PF0_TPHR_CAP_ENABLE)
"FALSE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF0_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF0_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (PF0_TPHR_CAP_INT_VEC_MODE)
"TRUE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : PF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF0_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (PF1_AER_CAP_ECRC_CHECK_CAPABLE)
"FALSE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b0;
"TRUE" : PF1_AER_CAP_ECRC_CHECK_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_CHECK_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_CHECK_CAPABLE);
#1 $finish;
end
endcase
case (PF1_AER_CAP_ECRC_GEN_CAPABLE)
"FALSE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b0;
"TRUE" : PF1_AER_CAP_ECRC_GEN_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_AER_CAP_ECRC_GEN_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_AER_CAP_ECRC_GEN_CAPABLE);
#1 $finish;
end
endcase
case (PF1_DPA_CAP_SUB_STATE_CONTROL_EN)
"TRUE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b1;
"FALSE" : PF1_DPA_CAP_SUB_STATE_CONTROL_EN_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_DPA_CAP_SUB_STATE_CONTROL_EN on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_DPA_CAP_SUB_STATE_CONTROL_EN);
#1 $finish;
end
endcase
case (PF1_EXPANSION_ROM_ENABLE)
"FALSE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_EXPANSION_ROM_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_EXPANSION_ROM_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_EXPANSION_ROM_ENABLE);
#1 $finish;
end
endcase
case (PF1_PB_CAP_SYSTEM_ALLOCATED)
"FALSE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b0;
"TRUE" : PF1_PB_CAP_SYSTEM_ALLOCATED_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_PB_CAP_SYSTEM_ALLOCATED on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_PB_CAP_SYSTEM_ALLOCATED);
#1 $finish;
end
endcase
case (PF1_RBAR_CAP_ENABLE)
"FALSE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_RBAR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_RBAR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_RBAR_CAP_ENABLE);
#1 $finish;
end
endcase
case (PF1_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : PF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (PF1_TPHR_CAP_ENABLE)
"FALSE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : PF1_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PF1_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (PF1_TPHR_CAP_INT_VEC_MODE)
"TRUE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : PF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PF1_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (PL_DISABLE_EI_INFER_IN_L0)
"FALSE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b0;
"TRUE" : PL_DISABLE_EI_INFER_IN_L0_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_EI_INFER_IN_L0 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_EI_INFER_IN_L0);
#1 $finish;
end
endcase
case (PL_DISABLE_GEN3_DC_BALANCE)
"FALSE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b0;
"TRUE" : PL_DISABLE_GEN3_DC_BALANCE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_GEN3_DC_BALANCE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_GEN3_DC_BALANCE);
#1 $finish;
end
endcase
case (PL_DISABLE_SCRAMBLING)
"FALSE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b0;
"TRUE" : PL_DISABLE_SCRAMBLING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_SCRAMBLING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_SCRAMBLING);
#1 $finish;
end
endcase
case (PL_DISABLE_UPCONFIG_CAPABLE)
"FALSE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b0;
"TRUE" : PL_DISABLE_UPCONFIG_CAPABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_DISABLE_UPCONFIG_CAPABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_DISABLE_UPCONFIG_CAPABLE);
#1 $finish;
end
endcase
case (PL_EQ_ADAPT_DISABLE_COEFF_CHECK)
"FALSE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b0;
"TRUE" : PL_EQ_ADAPT_DISABLE_COEFF_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_COEFF_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_COEFF_CHECK);
#1 $finish;
end
endcase
case (PL_EQ_ADAPT_DISABLE_PRESET_CHECK)
"FALSE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b0;
"TRUE" : PL_EQ_ADAPT_DISABLE_PRESET_CHECK_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_ADAPT_DISABLE_PRESET_CHECK on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_ADAPT_DISABLE_PRESET_CHECK);
#1 $finish;
end
endcase
case (PL_EQ_BYPASS_PHASE23)
"FALSE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b0;
"TRUE" : PL_EQ_BYPASS_PHASE23_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_BYPASS_PHASE23 on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_BYPASS_PHASE23);
#1 $finish;
end
endcase
case (PL_EQ_SHORT_ADAPT_PHASE)
"FALSE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b0;
"TRUE" : PL_EQ_SHORT_ADAPT_PHASE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_EQ_SHORT_ADAPT_PHASE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_EQ_SHORT_ADAPT_PHASE);
#1 $finish;
end
endcase
case (PL_SIM_FAST_LINK_TRAINING)
"FALSE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b0;
"TRUE" : PL_SIM_FAST_LINK_TRAINING_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute PL_SIM_FAST_LINK_TRAINING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", PL_SIM_FAST_LINK_TRAINING);
#1 $finish;
end
endcase
case (PL_UPSTREAM_FACING)
"TRUE" : PL_UPSTREAM_FACING_BINARY = 1'b1;
"FALSE" : PL_UPSTREAM_FACING_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PL_UPSTREAM_FACING on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PL_UPSTREAM_FACING);
#1 $finish;
end
endcase
case (PM_ENABLE_SLOT_POWER_CAPTURE)
"TRUE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b1;
"FALSE" : PM_ENABLE_SLOT_POWER_CAPTURE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute PM_ENABLE_SLOT_POWER_CAPTURE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", PM_ENABLE_SLOT_POWER_CAPTURE);
#1 $finish;
end
endcase
case (SIM_VERSION)
"1.0" : SIM_VERSION_BINARY = 0;
"1.1" : SIM_VERSION_BINARY = 0;
"1.2" : SIM_VERSION_BINARY = 0;
"1.3" : SIM_VERSION_BINARY = 0;
"2.0" : SIM_VERSION_BINARY = 0;
"3.0" : SIM_VERSION_BINARY = 0;
"4.0" : SIM_VERSION_BINARY = 0;
default : begin
$display("Attribute Syntax Error : The Attribute SIM_VERSION on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are 1.0, 1.1, 1.2, 1.3, 2.0, 3.0, or 4.0.", SIM_VERSION);
#1 $finish;
end
endcase
case (SRIOV_CAP_ENABLE)
"FALSE" : SRIOV_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : SRIOV_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute SRIOV_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", SRIOV_CAP_ENABLE);
#1 $finish;
end
endcase
case (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE)
"TRUE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b1;
"FALSE" : TL_ENABLE_MESSAGE_RID_CHECK_ENABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TL_ENABLE_MESSAGE_RID_CHECK_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_ENABLE_MESSAGE_RID_CHECK_ENABLE);
#1 $finish;
end
endcase
case (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE)
"FALSE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE);
#1 $finish;
end
endcase
case (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE)
"FALSE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE);
#1 $finish;
end
endcase
case (TL_LEGACY_MODE_ENABLE)
"FALSE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b0;
"TRUE" : TL_LEGACY_MODE_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_LEGACY_MODE_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_LEGACY_MODE_ENABLE);
#1 $finish;
end
endcase
case (TL_PF_ENABLE_REG)
"FALSE" : TL_PF_ENABLE_REG_BINARY = 1'b0;
"TRUE" : TL_PF_ENABLE_REG_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute TL_PF_ENABLE_REG on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", TL_PF_ENABLE_REG);
#1 $finish;
end
endcase
case (TL_TAG_MGMT_ENABLE)
"TRUE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b1;
"FALSE" : TL_TAG_MGMT_ENABLE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute TL_TAG_MGMT_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", TL_TAG_MGMT_ENABLE);
#1 $finish;
end
endcase
case (VF0_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF0_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF0_TPHR_CAP_ENABLE)
"FALSE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF0_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF0_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF0_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF0_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF0_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF0_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (VF1_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF1_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF1_TPHR_CAP_ENABLE)
"FALSE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF1_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF1_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF1_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF1_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF1_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF1_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (VF2_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF2_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF2_TPHR_CAP_ENABLE)
"FALSE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF2_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF2_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF2_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF2_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF2_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF2_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (VF3_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF3_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF3_TPHR_CAP_ENABLE)
"FALSE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF3_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF3_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF3_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF3_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF3_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF3_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (VF4_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF4_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF4_TPHR_CAP_ENABLE)
"FALSE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF4_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF4_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF4_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF4_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF4_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF4_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
case (VF5_TPHR_CAP_DEV_SPECIFIC_MODE)
"TRUE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b1;
"FALSE" : VF5_TPHR_CAP_DEV_SPECIFIC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_DEV_SPECIFIC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_DEV_SPECIFIC_MODE);
#1 $finish;
end
endcase
case (VF5_TPHR_CAP_ENABLE)
"FALSE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b0;
"TRUE" : VF5_TPHR_CAP_ENABLE_BINARY = 1'b1;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_ENABLE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are FALSE, or TRUE.", VF5_TPHR_CAP_ENABLE);
#1 $finish;
end
endcase
case (VF5_TPHR_CAP_INT_VEC_MODE)
"TRUE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b1;
"FALSE" : VF5_TPHR_CAP_INT_VEC_MODE_BINARY = 1'b0;
default : begin
$display("Attribute Syntax Error : The Attribute VF5_TPHR_CAP_INT_VEC_MODE on X_PCIE_3_0 instance %m is set to %s. Legal values for this attribute are TRUE, or FALSE.", VF5_TPHR_CAP_INT_VEC_MODE);
#1 $finish;
end
endcase
if ((LL_ACK_TIMEOUT_FUNC >= 0) && (LL_ACK_TIMEOUT_FUNC <= 3))
LL_ACK_TIMEOUT_FUNC_BINARY = LL_ACK_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_ACK_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_ACK_TIMEOUT_FUNC);
#1 $finish;
end
if ((LL_REPLAY_TIMEOUT_FUNC >= 0) && (LL_REPLAY_TIMEOUT_FUNC <= 3))
LL_REPLAY_TIMEOUT_FUNC_BINARY = LL_REPLAY_TIMEOUT_FUNC;
else begin
$display("Attribute Syntax Error : The Attribute LL_REPLAY_TIMEOUT_FUNC on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", LL_REPLAY_TIMEOUT_FUNC);
#1 $finish;
end
if ((PF0_DEV_CAP_ENDPOINT_L0S_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY <= 7))
PF0_DEV_CAP_ENDPOINT_L0S_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L0S_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L0S_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L0S_LATENCY);
#1 $finish;
end
if ((PF0_DEV_CAP_ENDPOINT_L1_LATENCY >= 0) && (PF0_DEV_CAP_ENDPOINT_L1_LATENCY <= 7))
PF0_DEV_CAP_ENDPOINT_L1_LATENCY_BINARY = PF0_DEV_CAP_ENDPOINT_L1_LATENCY;
else begin
$display("Attribute Syntax Error : The Attribute PF0_DEV_CAP_ENDPOINT_L1_LATENCY on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_DEV_CAP_ENDPOINT_L1_LATENCY);
#1 $finish;
end
if ((PF0_LINK_CAP_ASPM_SUPPORT >= 0) && (PF0_LINK_CAP_ASPM_SUPPORT <= 3))
PF0_LINK_CAP_ASPM_SUPPORT_BINARY = PF0_LINK_CAP_ASPM_SUPPORT;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_ASPM_SUPPORT on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 3.", PF0_LINK_CAP_ASPM_SUPPORT);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2);
#1 $finish;
end
if ((PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 <= 7))
PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2);
#1 $finish;
end
if ((PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 >= 0) && (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 <= 7))
PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3_BINARY = PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3);
#1 $finish;
end
if ((PF0_MSIX_CAP_PBA_BIR >= 0) && (PF0_MSIX_CAP_PBA_BIR <= 7))
PF0_MSIX_CAP_PBA_BIR_BINARY = PF0_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((PF0_MSIX_CAP_TABLE_BIR >= 0) && (PF0_MSIX_CAP_TABLE_BIR <= 7))
PF0_MSIX_CAP_TABLE_BIR_BINARY = PF0_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((PF0_MSI_CAP_MULTIMSGCAP >= 0) && (PF0_MSI_CAP_MULTIMSGCAP <= 7))
PF0_MSI_CAP_MULTIMSGCAP_BINARY = PF0_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute PF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF0_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((PF1_MSIX_CAP_PBA_BIR >= 0) && (PF1_MSIX_CAP_PBA_BIR <= 7))
PF1_MSIX_CAP_PBA_BIR_BINARY = PF1_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((PF1_MSIX_CAP_TABLE_BIR >= 0) && (PF1_MSIX_CAP_TABLE_BIR <= 7))
PF1_MSIX_CAP_TABLE_BIR_BINARY = PF1_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((PF1_MSI_CAP_MULTIMSGCAP >= 0) && (PF1_MSI_CAP_MULTIMSGCAP <= 7))
PF1_MSI_CAP_MULTIMSGCAP_BINARY = PF1_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute PF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", PF1_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((PL_N_FTS_COMCLK_GEN1 >= 0) && (PL_N_FTS_COMCLK_GEN1 <= 255))
PL_N_FTS_COMCLK_GEN1_BINARY = PL_N_FTS_COMCLK_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN1);
#1 $finish;
end
if ((PL_N_FTS_COMCLK_GEN2 >= 0) && (PL_N_FTS_COMCLK_GEN2 <= 255))
PL_N_FTS_COMCLK_GEN2_BINARY = PL_N_FTS_COMCLK_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN2);
#1 $finish;
end
if ((PL_N_FTS_COMCLK_GEN3 >= 0) && (PL_N_FTS_COMCLK_GEN3 <= 255))
PL_N_FTS_COMCLK_GEN3_BINARY = PL_N_FTS_COMCLK_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_COMCLK_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_COMCLK_GEN3);
#1 $finish;
end
if ((PL_N_FTS_GEN1 >= 0) && (PL_N_FTS_GEN1 <= 255))
PL_N_FTS_GEN1_BINARY = PL_N_FTS_GEN1;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN1);
#1 $finish;
end
if ((PL_N_FTS_GEN2 >= 0) && (PL_N_FTS_GEN2 <= 255))
PL_N_FTS_GEN2_BINARY = PL_N_FTS_GEN2;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN2);
#1 $finish;
end
if ((PL_N_FTS_GEN3 >= 0) && (PL_N_FTS_GEN3 <= 255))
PL_N_FTS_GEN3_BINARY = PL_N_FTS_GEN3;
else begin
$display("Attribute Syntax Error : The Attribute PL_N_FTS_GEN3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 255.", PL_N_FTS_GEN3);
#1 $finish;
end
if ((SPARE_BIT0 >= 0) && (SPARE_BIT0 <= 1))
SPARE_BIT0_BINARY = SPARE_BIT0;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT0 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT0);
#1 $finish;
end
if ((SPARE_BIT1 >= 0) && (SPARE_BIT1 <= 1))
SPARE_BIT1_BINARY = SPARE_BIT1;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT1 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT1);
#1 $finish;
end
if ((SPARE_BIT2 >= 0) && (SPARE_BIT2 <= 1))
SPARE_BIT2_BINARY = SPARE_BIT2;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT2 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT2);
#1 $finish;
end
if ((SPARE_BIT3 >= 0) && (SPARE_BIT3 <= 1))
SPARE_BIT3_BINARY = SPARE_BIT3;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT3 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT3);
#1 $finish;
end
if ((SPARE_BIT4 >= 0) && (SPARE_BIT4 <= 1))
SPARE_BIT4_BINARY = SPARE_BIT4;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT4 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT4);
#1 $finish;
end
if ((SPARE_BIT5 >= 0) && (SPARE_BIT5 <= 1))
SPARE_BIT5_BINARY = SPARE_BIT5;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT5 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT5);
#1 $finish;
end
if ((SPARE_BIT6 >= 0) && (SPARE_BIT6 <= 1))
SPARE_BIT6_BINARY = SPARE_BIT6;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT6 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT6);
#1 $finish;
end
if ((SPARE_BIT7 >= 0) && (SPARE_BIT7 <= 1))
SPARE_BIT7_BINARY = SPARE_BIT7;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT7 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT7);
#1 $finish;
end
if ((SPARE_BIT8 >= 0) && (SPARE_BIT8 <= 1))
SPARE_BIT8_BINARY = SPARE_BIT8;
else begin
$display("Attribute Syntax Error : The Attribute SPARE_BIT8 on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 1.", SPARE_BIT8);
#1 $finish;
end
if ((VF0_MSIX_CAP_PBA_BIR >= 0) && (VF0_MSIX_CAP_PBA_BIR <= 7))
VF0_MSIX_CAP_PBA_BIR_BINARY = VF0_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF0_MSIX_CAP_TABLE_BIR >= 0) && (VF0_MSIX_CAP_TABLE_BIR <= 7))
VF0_MSIX_CAP_TABLE_BIR_BINARY = VF0_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF0_MSI_CAP_MULTIMSGCAP >= 0) && (VF0_MSI_CAP_MULTIMSGCAP <= 7))
VF0_MSI_CAP_MULTIMSGCAP_BINARY = VF0_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF0_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF0_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((VF1_MSIX_CAP_PBA_BIR >= 0) && (VF1_MSIX_CAP_PBA_BIR <= 7))
VF1_MSIX_CAP_PBA_BIR_BINARY = VF1_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF1_MSIX_CAP_TABLE_BIR >= 0) && (VF1_MSIX_CAP_TABLE_BIR <= 7))
VF1_MSIX_CAP_TABLE_BIR_BINARY = VF1_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF1_MSI_CAP_MULTIMSGCAP >= 0) && (VF1_MSI_CAP_MULTIMSGCAP <= 7))
VF1_MSI_CAP_MULTIMSGCAP_BINARY = VF1_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF1_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF1_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((VF2_MSIX_CAP_PBA_BIR >= 0) && (VF2_MSIX_CAP_PBA_BIR <= 7))
VF2_MSIX_CAP_PBA_BIR_BINARY = VF2_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF2_MSIX_CAP_TABLE_BIR >= 0) && (VF2_MSIX_CAP_TABLE_BIR <= 7))
VF2_MSIX_CAP_TABLE_BIR_BINARY = VF2_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF2_MSI_CAP_MULTIMSGCAP >= 0) && (VF2_MSI_CAP_MULTIMSGCAP <= 7))
VF2_MSI_CAP_MULTIMSGCAP_BINARY = VF2_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF2_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF2_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((VF3_MSIX_CAP_PBA_BIR >= 0) && (VF3_MSIX_CAP_PBA_BIR <= 7))
VF3_MSIX_CAP_PBA_BIR_BINARY = VF3_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF3_MSIX_CAP_TABLE_BIR >= 0) && (VF3_MSIX_CAP_TABLE_BIR <= 7))
VF3_MSIX_CAP_TABLE_BIR_BINARY = VF3_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF3_MSI_CAP_MULTIMSGCAP >= 0) && (VF3_MSI_CAP_MULTIMSGCAP <= 7))
VF3_MSI_CAP_MULTIMSGCAP_BINARY = VF3_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF3_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF3_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((VF4_MSIX_CAP_PBA_BIR >= 0) && (VF4_MSIX_CAP_PBA_BIR <= 7))
VF4_MSIX_CAP_PBA_BIR_BINARY = VF4_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF4_MSIX_CAP_TABLE_BIR >= 0) && (VF4_MSIX_CAP_TABLE_BIR <= 7))
VF4_MSIX_CAP_TABLE_BIR_BINARY = VF4_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF4_MSI_CAP_MULTIMSGCAP >= 0) && (VF4_MSI_CAP_MULTIMSGCAP <= 7))
VF4_MSI_CAP_MULTIMSGCAP_BINARY = VF4_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF4_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF4_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
if ((VF5_MSIX_CAP_PBA_BIR >= 0) && (VF5_MSIX_CAP_PBA_BIR <= 7))
VF5_MSIX_CAP_PBA_BIR_BINARY = VF5_MSIX_CAP_PBA_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_PBA_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_PBA_BIR);
#1 $finish;
end
if ((VF5_MSIX_CAP_TABLE_BIR >= 0) && (VF5_MSIX_CAP_TABLE_BIR <= 7))
VF5_MSIX_CAP_TABLE_BIR_BINARY = VF5_MSIX_CAP_TABLE_BIR;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSIX_CAP_TABLE_BIR on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSIX_CAP_TABLE_BIR);
#1 $finish;
end
if ((VF5_MSI_CAP_MULTIMSGCAP >= 0) && (VF5_MSI_CAP_MULTIMSGCAP <= 7))
VF5_MSI_CAP_MULTIMSGCAP_BINARY = VF5_MSI_CAP_MULTIMSGCAP;
else begin
$display("Attribute Syntax Error : The Attribute VF5_MSI_CAP_MULTIMSGCAP on X_PCIE_3_0 instance %m is set to %d. Legal values for this attribute are 0 to 7.", VF5_MSI_CAP_MULTIMSGCAP);
#1 $finish;
end
end
wire [11:0] delay_CFGFCCPLD;
wire [11:0] delay_CFGFCNPD;
wire [11:0] delay_CFGFCPD;
wire [11:0] delay_CFGVFSTATUS;
wire [143:0] delay_MIREPLAYRAMWRITEDATA;
wire [143:0] delay_MIREQUESTRAMWRITEDATA;
wire [15:0] delay_CFGPERFUNCSTATUSDATA;
wire [15:0] delay_DBGDATAOUT;
wire [15:0] delay_DRPDO;
wire [17:0] delay_CFGVFPOWERSTATE;
wire [17:0] delay_CFGVFTPHSTMODE;
wire [1:0] delay_CFGDPASUBSTATECHANGE;
wire [1:0] delay_CFGFLRINPROCESS;
wire [1:0] delay_CFGINTERRUPTMSIENABLE;
wire [1:0] delay_CFGINTERRUPTMSIXENABLE;
wire [1:0] delay_CFGINTERRUPTMSIXMASK;
wire [1:0] delay_CFGLINKPOWERSTATE;
wire [1:0] delay_CFGOBFFENABLE;
wire [1:0] delay_CFGPHYLINKSTATUS;
wire [1:0] delay_CFGRCBSTATUS;
wire [1:0] delay_CFGTPHREQUESTERENABLE;
wire [1:0] delay_MIREPLAYRAMREADENABLE;
wire [1:0] delay_MIREPLAYRAMWRITEENABLE;
wire [1:0] delay_PCIERQTAGAV;
wire [1:0] delay_PCIETFCNPDAV;
wire [1:0] delay_PCIETFCNPHAV;
wire [1:0] delay_PIPERX0EQCONTROL;
wire [1:0] delay_PIPERX1EQCONTROL;
wire [1:0] delay_PIPERX2EQCONTROL;
wire [1:0] delay_PIPERX3EQCONTROL;
wire [1:0] delay_PIPERX4EQCONTROL;
wire [1:0] delay_PIPERX5EQCONTROL;
wire [1:0] delay_PIPERX6EQCONTROL;
wire [1:0] delay_PIPERX7EQCONTROL;
wire [1:0] delay_PIPETX0CHARISK;
wire [1:0] delay_PIPETX0EQCONTROL;
wire [1:0] delay_PIPETX0POWERDOWN;
wire [1:0] delay_PIPETX0SYNCHEADER;
wire [1:0] delay_PIPETX1CHARISK;
wire [1:0] delay_PIPETX1EQCONTROL;
wire [1:0] delay_PIPETX1POWERDOWN;
wire [1:0] delay_PIPETX1SYNCHEADER;
wire [1:0] delay_PIPETX2CHARISK;
wire [1:0] delay_PIPETX2EQCONTROL;
wire [1:0] delay_PIPETX2POWERDOWN;
wire [1:0] delay_PIPETX2SYNCHEADER;
wire [1:0] delay_PIPETX3CHARISK;
wire [1:0] delay_PIPETX3EQCONTROL;
wire [1:0] delay_PIPETX3POWERDOWN;
wire [1:0] delay_PIPETX3SYNCHEADER;
wire [1:0] delay_PIPETX4CHARISK;
wire [1:0] delay_PIPETX4EQCONTROL;
wire [1:0] delay_PIPETX4POWERDOWN;
wire [1:0] delay_PIPETX4SYNCHEADER;
wire [1:0] delay_PIPETX5CHARISK;
wire [1:0] delay_PIPETX5EQCONTROL;
wire [1:0] delay_PIPETX5POWERDOWN;
wire [1:0] delay_PIPETX5SYNCHEADER;
wire [1:0] delay_PIPETX6CHARISK;
wire [1:0] delay_PIPETX6EQCONTROL;
wire [1:0] delay_PIPETX6POWERDOWN;
wire [1:0] delay_PIPETX6SYNCHEADER;
wire [1:0] delay_PIPETX7CHARISK;
wire [1:0] delay_PIPETX7EQCONTROL;
wire [1:0] delay_PIPETX7POWERDOWN;
wire [1:0] delay_PIPETX7SYNCHEADER;
wire [1:0] delay_PIPETXRATE;
wire [1:0] delay_PLEQPHASE;
wire [255:0] delay_MAXISCQTDATA;
wire [255:0] delay_MAXISRCTDATA;
wire [2:0] delay_CFGCURRENTSPEED;
wire [2:0] delay_CFGMAXPAYLOAD;
wire [2:0] delay_CFGMAXREADREQ;
wire [2:0] delay_CFGTPHFUNCTIONNUM;
wire [2:0] delay_PIPERX0EQPRESET;
wire [2:0] delay_PIPERX1EQPRESET;
wire [2:0] delay_PIPERX2EQPRESET;
wire [2:0] delay_PIPERX3EQPRESET;
wire [2:0] delay_PIPERX4EQPRESET;
wire [2:0] delay_PIPERX5EQPRESET;
wire [2:0] delay_PIPERX6EQPRESET;
wire [2:0] delay_PIPERX7EQPRESET;
wire [2:0] delay_PIPETXMARGIN;
wire [31:0] delay_CFGEXTWRITEDATA;
wire [31:0] delay_CFGINTERRUPTMSIDATA;
wire [31:0] delay_CFGMGMTREADDATA;
wire [31:0] delay_CFGTPHSTTWRITEDATA;
wire [31:0] delay_PIPETX0DATA;
wire [31:0] delay_PIPETX1DATA;
wire [31:0] delay_PIPETX2DATA;
wire [31:0] delay_PIPETX3DATA;
wire [31:0] delay_PIPETX4DATA;
wire [31:0] delay_PIPETX5DATA;
wire [31:0] delay_PIPETX6DATA;
wire [31:0] delay_PIPETX7DATA;
wire [3:0] delay_CFGEXTWRITEBYTEENABLE;
wire [3:0] delay_CFGNEGOTIATEDWIDTH;
wire [3:0] delay_CFGTPHSTTWRITEBYTEVALID;
wire [3:0] delay_MICOMPLETIONRAMREADENABLEL;
wire [3:0] delay_MICOMPLETIONRAMREADENABLEU;
wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEL;
wire [3:0] delay_MICOMPLETIONRAMWRITEENABLEU;
wire [3:0] delay_MIREQUESTRAMREADENABLE;
wire [3:0] delay_MIREQUESTRAMWRITEENABLE;
wire [3:0] delay_PCIERQSEQNUM;
wire [3:0] delay_PIPERX0EQLPTXPRESET;
wire [3:0] delay_PIPERX1EQLPTXPRESET;
wire [3:0] delay_PIPERX2EQLPTXPRESET;
wire [3:0] delay_PIPERX3EQLPTXPRESET;
wire [3:0] delay_PIPERX4EQLPTXPRESET;
wire [3:0] delay_PIPERX5EQLPTXPRESET;
wire [3:0] delay_PIPERX6EQLPTXPRESET;
wire [3:0] delay_PIPERX7EQLPTXPRESET;
wire [3:0] delay_PIPETX0EQPRESET;
wire [3:0] delay_PIPETX1EQPRESET;
wire [3:0] delay_PIPETX2EQPRESET;
wire [3:0] delay_PIPETX3EQPRESET;
wire [3:0] delay_PIPETX4EQPRESET;
wire [3:0] delay_PIPETX5EQPRESET;
wire [3:0] delay_PIPETX6EQPRESET;
wire [3:0] delay_PIPETX7EQPRESET;
wire [3:0] delay_SAXISCCTREADY;
wire [3:0] delay_SAXISRQTREADY;
wire [4:0] delay_CFGMSGRECEIVEDTYPE;
wire [4:0] delay_CFGTPHSTTADDRESS;
wire [5:0] delay_CFGFUNCTIONPOWERSTATE;
wire [5:0] delay_CFGINTERRUPTMSIMMENABLE;
wire [5:0] delay_CFGINTERRUPTMSIVFENABLE;
wire [5:0] delay_CFGINTERRUPTMSIXVFENABLE;
wire [5:0] delay_CFGINTERRUPTMSIXVFMASK;
wire [5:0] delay_CFGLTSSMSTATE;
wire [5:0] delay_CFGTPHSTMODE;
wire [5:0] delay_CFGVFFLRINPROCESS;
wire [5:0] delay_CFGVFTPHREQUESTERENABLE;
wire [5:0] delay_PCIECQNPREQCOUNT;
wire [5:0] delay_PCIERQTAG;
wire [5:0] delay_PIPERX0EQLPLFFS;
wire [5:0] delay_PIPERX1EQLPLFFS;
wire [5:0] delay_PIPERX2EQLPLFFS;
wire [5:0] delay_PIPERX3EQLPLFFS;
wire [5:0] delay_PIPERX4EQLPLFFS;
wire [5:0] delay_PIPERX5EQLPLFFS;
wire [5:0] delay_PIPERX6EQLPLFFS;
wire [5:0] delay_PIPERX7EQLPLFFS;
wire [5:0] delay_PIPETX0EQDEEMPH;
wire [5:0] delay_PIPETX1EQDEEMPH;
wire [5:0] delay_PIPETX2EQDEEMPH;
wire [5:0] delay_PIPETX3EQDEEMPH;
wire [5:0] delay_PIPETX4EQDEEMPH;
wire [5:0] delay_PIPETX5EQDEEMPH;
wire [5:0] delay_PIPETX6EQDEEMPH;
wire [5:0] delay_PIPETX7EQDEEMPH;
wire [71:0] delay_MICOMPLETIONRAMWRITEDATAL;
wire [71:0] delay_MICOMPLETIONRAMWRITEDATAU;
wire [74:0] delay_MAXISRCTUSER;
wire [7:0] delay_CFGEXTFUNCTIONNUMBER;
wire [7:0] delay_CFGFCCPLH;
wire [7:0] delay_CFGFCNPH;
wire [7:0] delay_CFGFCPH;
wire [7:0] delay_CFGFUNCTIONSTATUS;
wire [7:0] delay_CFGMSGRECEIVEDDATA;
wire [7:0] delay_MAXISCQTKEEP;
wire [7:0] delay_MAXISRCTKEEP;
wire [7:0] delay_PLGEN3PCSRXSLIDE;
wire [84:0] delay_MAXISCQTUSER;
wire [8:0] delay_MIREPLAYRAMADDRESS;
wire [8:0] delay_MIREQUESTRAMREADADDRESSA;
wire [8:0] delay_MIREQUESTRAMREADADDRESSB;
wire [8:0] delay_MIREQUESTRAMWRITEADDRESSA;
wire [8:0] delay_MIREQUESTRAMWRITEADDRESSB;
wire [9:0] delay_CFGEXTREGISTERNUMBER;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAL;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSAU;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBL;
wire [9:0] delay_MICOMPLETIONRAMREADADDRESSBU;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAL;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSAU;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBL;
wire [9:0] delay_MICOMPLETIONRAMWRITEADDRESSBU;
wire delay_CFGERRCOROUT;
wire delay_CFGERRFATALOUT;
wire delay_CFGERRNONFATALOUT;
wire delay_CFGEXTREADRECEIVED;
wire delay_CFGEXTWRITERECEIVED;
wire delay_CFGHOTRESETOUT;
wire delay_CFGINPUTUPDATEDONE;
wire delay_CFGINTERRUPTAOUTPUT;
wire delay_CFGINTERRUPTBOUTPUT;
wire delay_CFGINTERRUPTCOUTPUT;
wire delay_CFGINTERRUPTDOUTPUT;
wire delay_CFGINTERRUPTMSIFAIL;
wire delay_CFGINTERRUPTMSIMASKUPDATE;
wire delay_CFGINTERRUPTMSISENT;
wire delay_CFGINTERRUPTMSIXFAIL;
wire delay_CFGINTERRUPTMSIXSENT;
wire delay_CFGINTERRUPTSENT;
wire delay_CFGLOCALERROR;
wire delay_CFGLTRENABLE;
wire delay_CFGMCUPDATEDONE;
wire delay_CFGMGMTREADWRITEDONE;
wire delay_CFGMSGRECEIVED;
wire delay_CFGMSGTRANSMITDONE;
wire delay_CFGPERFUNCTIONUPDATEDONE;
wire delay_CFGPHYLINKDOWN;
wire delay_CFGPLSTATUSCHANGE;
wire delay_CFGPOWERSTATECHANGEINTERRUPT;
wire delay_CFGTPHSTTREADENABLE;
wire delay_CFGTPHSTTWRITEENABLE;
wire delay_DRPRDY;
wire delay_MAXISCQTLAST;
wire delay_MAXISCQTVALID;
wire delay_MAXISRCTLAST;
wire delay_MAXISRCTVALID;
wire delay_PCIERQSEQNUMVLD;
wire delay_PCIERQTAGVLD;
wire delay_PIPERX0POLARITY;
wire delay_PIPERX1POLARITY;
wire delay_PIPERX2POLARITY;
wire delay_PIPERX3POLARITY;
wire delay_PIPERX4POLARITY;
wire delay_PIPERX5POLARITY;
wire delay_PIPERX6POLARITY;
wire delay_PIPERX7POLARITY;
wire delay_PIPETX0COMPLIANCE;
wire delay_PIPETX0DATAVALID;
wire delay_PIPETX0ELECIDLE;
wire delay_PIPETX0STARTBLOCK;
wire delay_PIPETX1COMPLIANCE;
wire delay_PIPETX1DATAVALID;
wire delay_PIPETX1ELECIDLE;
wire delay_PIPETX1STARTBLOCK;
wire delay_PIPETX2COMPLIANCE;
wire delay_PIPETX2DATAVALID;
wire delay_PIPETX2ELECIDLE;
wire delay_PIPETX2STARTBLOCK;
wire delay_PIPETX3COMPLIANCE;
wire delay_PIPETX3DATAVALID;
wire delay_PIPETX3ELECIDLE;
wire delay_PIPETX3STARTBLOCK;
wire delay_PIPETX4COMPLIANCE;
wire delay_PIPETX4DATAVALID;
wire delay_PIPETX4ELECIDLE;
wire delay_PIPETX4STARTBLOCK;
wire delay_PIPETX5COMPLIANCE;
wire delay_PIPETX5DATAVALID;
wire delay_PIPETX5ELECIDLE;
wire delay_PIPETX5STARTBLOCK;
wire delay_PIPETX6COMPLIANCE;
wire delay_PIPETX6DATAVALID;
wire delay_PIPETX6ELECIDLE;
wire delay_PIPETX6STARTBLOCK;
wire delay_PIPETX7COMPLIANCE;
wire delay_PIPETX7DATAVALID;
wire delay_PIPETX7ELECIDLE;
wire delay_PIPETX7STARTBLOCK;
wire delay_PIPETXDEEMPH;
wire delay_PIPETXRCVRDET;
wire delay_PIPETXRESET;
wire delay_PIPETXSWING;
wire delay_PLEQINPROGRESS;
wire [10:0] delay_DRPADDR;
wire [143:0] delay_MICOMPLETIONRAMREADDATA;
wire [143:0] delay_MIREPLAYRAMREADDATA;
wire [143:0] delay_MIREQUESTRAMREADDATA;
wire [15:0] delay_CFGDEVID;
wire [15:0] delay_CFGSUBSYSID;
wire [15:0] delay_CFGSUBSYSVENDID;
wire [15:0] delay_CFGVENDID;
wire [15:0] delay_DRPDI;
wire [17:0] delay_PIPERX0EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX1EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX2EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX3EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX4EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX5EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX6EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPERX7EQLPNEWTXCOEFFORPRESET;
wire [17:0] delay_PIPETX0EQCOEFF;
wire [17:0] delay_PIPETX1EQCOEFF;
wire [17:0] delay_PIPETX2EQCOEFF;
wire [17:0] delay_PIPETX3EQCOEFF;
wire [17:0] delay_PIPETX4EQCOEFF;
wire [17:0] delay_PIPETX5EQCOEFF;
wire [17:0] delay_PIPETX6EQCOEFF;
wire [17:0] delay_PIPETX7EQCOEFF;
wire [18:0] delay_CFGMGMTADDR;
wire [1:0] delay_CFGFLRDONE;
wire [1:0] delay_CFGINTERRUPTMSITPHTYPE;
wire [1:0] delay_CFGINTERRUPTPENDING;
wire [1:0] delay_PIPERX0CHARISK;
wire [1:0] delay_PIPERX0SYNCHEADER;
wire [1:0] delay_PIPERX1CHARISK;
wire [1:0] delay_PIPERX1SYNCHEADER;
wire [1:0] delay_PIPERX2CHARISK;
wire [1:0] delay_PIPERX2SYNCHEADER;
wire [1:0] delay_PIPERX3CHARISK;
wire [1:0] delay_PIPERX3SYNCHEADER;
wire [1:0] delay_PIPERX4CHARISK;
wire [1:0] delay_PIPERX4SYNCHEADER;
wire [1:0] delay_PIPERX5CHARISK;
wire [1:0] delay_PIPERX5SYNCHEADER;
wire [1:0] delay_PIPERX6CHARISK;
wire [1:0] delay_PIPERX6SYNCHEADER;
wire [1:0] delay_PIPERX7CHARISK;
wire [1:0] delay_PIPERX7SYNCHEADER;
wire [21:0] delay_MAXISCQTREADY;
wire [21:0] delay_MAXISRCTREADY;
wire [255:0] delay_SAXISCCTDATA;
wire [255:0] delay_SAXISRQTDATA;
wire [2:0] delay_CFGDSFUNCTIONNUMBER;
wire [2:0] delay_CFGFCSEL;
wire [2:0] delay_CFGINTERRUPTMSIATTR;
wire [2:0] delay_CFGINTERRUPTMSIFUNCTIONNUMBER;
wire [2:0] delay_CFGMSGTRANSMITTYPE;
wire [2:0] delay_CFGPERFUNCSTATUSCONTROL;
wire [2:0] delay_CFGPERFUNCTIONNUMBER;
wire [2:0] delay_PIPERX0STATUS;
wire [2:0] delay_PIPERX1STATUS;
wire [2:0] delay_PIPERX2STATUS;
wire [2:0] delay_PIPERX3STATUS;
wire [2:0] delay_PIPERX4STATUS;
wire [2:0] delay_PIPERX5STATUS;
wire [2:0] delay_PIPERX6STATUS;
wire [2:0] delay_PIPERX7STATUS;
wire [31:0] delay_CFGEXTREADDATA;
wire [31:0] delay_CFGINTERRUPTMSIINT;
wire [31:0] delay_CFGINTERRUPTMSIXDATA;
wire [31:0] delay_CFGMGMTWRITEDATA;
wire [31:0] delay_CFGMSGTRANSMITDATA;
wire [31:0] delay_CFGTPHSTTREADDATA;
wire [31:0] delay_PIPERX0DATA;
wire [31:0] delay_PIPERX1DATA;
wire [31:0] delay_PIPERX2DATA;
wire [31:0] delay_PIPERX3DATA;
wire [31:0] delay_PIPERX4DATA;
wire [31:0] delay_PIPERX5DATA;
wire [31:0] delay_PIPERX6DATA;
wire [31:0] delay_PIPERX7DATA;
wire [32:0] delay_SAXISCCTUSER;
wire [3:0] delay_CFGINTERRUPTINT;
wire [3:0] delay_CFGINTERRUPTMSISELECT;
wire [3:0] delay_CFGMGMTBYTEENABLE;
wire [4:0] delay_CFGDSDEVICENUMBER;
wire [59:0] delay_SAXISRQTUSER;
wire [5:0] delay_CFGVFFLRDONE;
wire [5:0] delay_PIPEEQFS;
wire [5:0] delay_PIPEEQLF;
wire [63:0] delay_CFGDSN;
wire [63:0] delay_CFGINTERRUPTMSIPENDINGSTATUS;
wire [63:0] delay_CFGINTERRUPTMSIXADDRESS;
wire [7:0] delay_CFGDSBUSNUMBER;
wire [7:0] delay_CFGDSPORTNUMBER;
wire [7:0] delay_CFGREVID;
wire [7:0] delay_PLGEN3PCSRXSYNCDONE;
wire [7:0] delay_SAXISCCTKEEP;
wire [7:0] delay_SAXISRQTKEEP;
wire [8:0] delay_CFGINTERRUPTMSITPHSTTAG;
wire delay_CFGCONFIGSPACEENABLE;
wire delay_CFGERRCORIN;
wire delay_CFGERRUNCORIN;
wire delay_CFGEXTREADDATAVALID;
wire delay_CFGHOTRESETIN;
wire delay_CFGINPUTUPDATEREQUEST;
wire delay_CFGINTERRUPTMSITPHPRESENT;
wire delay_CFGINTERRUPTMSIXINT;
wire delay_CFGLINKTRAININGENABLE;
wire delay_CFGMCUPDATEREQUEST;
wire delay_CFGMGMTREAD;
wire delay_CFGMGMTTYPE1CFGREGACCESS;
wire delay_CFGMGMTWRITE;
wire delay_CFGMSGTRANSMIT;
wire delay_CFGPERFUNCTIONOUTPUTREQUEST;
wire delay_CFGPOWERSTATECHANGEACK;
wire delay_CFGREQPMTRANSITIONL23READY;
wire delay_CFGTPHSTTREADDATAVALID;
wire delay_CORECLK;
wire delay_CORECLKMICOMPLETIONRAML;
wire delay_CORECLKMICOMPLETIONRAMU;
wire delay_CORECLKMIREPLAYRAM;
wire delay_CORECLKMIREQUESTRAM;
wire delay_DRPCLK;
wire delay_DRPEN;
wire delay_DRPWE;
wire delay_MGMTRESETN;
wire delay_MGMTSTICKYRESETN;
wire delay_PCIECQNPREQ;
wire delay_PIPECLK;
wire delay_PIPERESETN;
wire delay_PIPERX0DATAVALID;
wire delay_PIPERX0ELECIDLE;
wire delay_PIPERX0EQDONE;
wire delay_PIPERX0EQLPADAPTDONE;
wire delay_PIPERX0EQLPLFFSSEL;
wire delay_PIPERX0PHYSTATUS;
wire delay_PIPERX0STARTBLOCK;
wire delay_PIPERX0VALID;
wire delay_PIPERX1DATAVALID;
wire delay_PIPERX1ELECIDLE;
wire delay_PIPERX1EQDONE;
wire delay_PIPERX1EQLPADAPTDONE;
wire delay_PIPERX1EQLPLFFSSEL;
wire delay_PIPERX1PHYSTATUS;
wire delay_PIPERX1STARTBLOCK;
wire delay_PIPERX1VALID;
wire delay_PIPERX2DATAVALID;
wire delay_PIPERX2ELECIDLE;
wire delay_PIPERX2EQDONE;
wire delay_PIPERX2EQLPADAPTDONE;
wire delay_PIPERX2EQLPLFFSSEL;
wire delay_PIPERX2PHYSTATUS;
wire delay_PIPERX2STARTBLOCK;
wire delay_PIPERX2VALID;
wire delay_PIPERX3DATAVALID;
wire delay_PIPERX3ELECIDLE;
wire delay_PIPERX3EQDONE;
wire delay_PIPERX3EQLPADAPTDONE;
wire delay_PIPERX3EQLPLFFSSEL;
wire delay_PIPERX3PHYSTATUS;
wire delay_PIPERX3STARTBLOCK;
wire delay_PIPERX3VALID;
wire delay_PIPERX4DATAVALID;
wire delay_PIPERX4ELECIDLE;
wire delay_PIPERX4EQDONE;
wire delay_PIPERX4EQLPADAPTDONE;
wire delay_PIPERX4EQLPLFFSSEL;
wire delay_PIPERX4PHYSTATUS;
wire delay_PIPERX4STARTBLOCK;
wire delay_PIPERX4VALID;
wire delay_PIPERX5DATAVALID;
wire delay_PIPERX5ELECIDLE;
wire delay_PIPERX5EQDONE;
wire delay_PIPERX5EQLPADAPTDONE;
wire delay_PIPERX5EQLPLFFSSEL;
wire delay_PIPERX5PHYSTATUS;
wire delay_PIPERX5STARTBLOCK;
wire delay_PIPERX5VALID;
wire delay_PIPERX6DATAVALID;
wire delay_PIPERX6ELECIDLE;
wire delay_PIPERX6EQDONE;
wire delay_PIPERX6EQLPADAPTDONE;
wire delay_PIPERX6EQLPLFFSSEL;
wire delay_PIPERX6PHYSTATUS;
wire delay_PIPERX6STARTBLOCK;
wire delay_PIPERX6VALID;
wire delay_PIPERX7DATAVALID;
wire delay_PIPERX7ELECIDLE;
wire delay_PIPERX7EQDONE;
wire delay_PIPERX7EQLPADAPTDONE;
wire delay_PIPERX7EQLPLFFSSEL;
wire delay_PIPERX7PHYSTATUS;
wire delay_PIPERX7STARTBLOCK;
wire delay_PIPERX7VALID;
wire delay_PIPETX0EQDONE;
wire delay_PIPETX1EQDONE;
wire delay_PIPETX2EQDONE;
wire delay_PIPETX3EQDONE;
wire delay_PIPETX4EQDONE;
wire delay_PIPETX5EQDONE;
wire delay_PIPETX6EQDONE;
wire delay_PIPETX7EQDONE;
wire delay_PLDISABLESCRAMBLER;
wire delay_PLEQRESETEIEOSCOUNT;
wire delay_PLGEN3PCSDISABLE;
wire delay_RECCLK;
wire delay_RESETN;
wire delay_SAXISCCTLAST;
wire delay_SAXISCCTVALID;
wire delay_SAXISRQTLAST;
wire delay_SAXISRQTVALID;
wire delay_USERCLK;
//drp monitor
reg drpen_r1 = 1'b0;
reg drpen_r2 = 1'b0;
reg drpwe_r1 = 1'b0;
reg drpwe_r2 = 1'b0;
reg [1:0] sfsm = 2'b01;
localparam FSM_IDLE = 2'b01;
localparam FSM_WAIT = 2'b10;
always @(posedge delay_DRPCLK)
begin
// pipeline the DRPEN and DRPWE
drpen_r1 <= delay_DRPEN;
drpwe_r1 <= delay_DRPWE;
drpen_r2 <= drpen_r1;
drpwe_r2 <= drpwe_r1;
// Check - if DRPEN or DRPWE is more than 1 DCLK
if ((drpen_r1 == 1'b1) && (drpen_r2 == 1'b1))
begin
$display("DRC Error : DRPEN is high for more than 1 DRPCLK on %m instance");
$finish;
end
if ((drpwe_r1 == 1'b1) && (drpwe_r2 == 1'b1))
begin
$display("DRC Error : DRPWE is high for more than 1 DRPCLK on %m instance");
$finish;
end
//After the 1st DRPEN pulse, check the DRPEN and DRPRDY.
case (sfsm)
FSM_IDLE:
begin
if(delay_DRPEN == 1'b1)
sfsm <= FSM_WAIT;
end
FSM_WAIT:
begin
// After the 1st DRPEN, 4 cases can happen
// DRPEN DRPRDY NEXT STATE
// 0 0 FSM_WAIT - wait for DRPRDY
// 0 1 FSM_IDLE - normal operation
// 1 0 FSM_WAIT - display error and wait for DRPRDY
// 1 1 FSM_WAIT - normal operation. Per UG470, DRPEN and DRPRDY can be at the same cycle.
//Add the check for another DPREN pulse
if(delay_DRPEN === 1'b1 && delay_DRPRDY === 1'b0)
begin
$display("DRC Error : DRPEN is enabled before DRPRDY returns on %m instance");
$finish;
end
//Add the check for another DRPWE pulse
if ((delay_DRPWE === 1'b1) && (delay_DRPEN === 1'b0))
begin
$display("DRC Error : DRPWE is enabled before DRPRDY returns on %m instance");
$finish;
end
if ((delay_DRPRDY === 1'b1) && (delay_DRPEN === 1'b0))
begin
sfsm <= FSM_IDLE;
end
if ((delay_DRPRDY === 1'b1)&& (delay_DRPEN === 1'b1))
begin
sfsm <= FSM_WAIT;
end
end
default:
begin
$display("DRC Error : Default state in DRP FSM.");
$finish;
end
endcase
end // always @ (posedge delay_DRPCLK)
//end drp monitor
assign #(out_delay) CFGCURRENTSPEED = delay_CFGCURRENTSPEED;
assign #(out_delay) CFGDPASUBSTATECHANGE = delay_CFGDPASUBSTATECHANGE;
assign #(out_delay) CFGERRCOROUT = delay_CFGERRCOROUT;
assign #(out_delay) CFGERRFATALOUT = delay_CFGERRFATALOUT;
assign #(out_delay) CFGERRNONFATALOUT = delay_CFGERRNONFATALOUT;
assign #(out_delay) CFGEXTFUNCTIONNUMBER = delay_CFGEXTFUNCTIONNUMBER;
assign #(out_delay) CFGEXTREADRECEIVED = delay_CFGEXTREADRECEIVED;
assign #(out_delay) CFGEXTREGISTERNUMBER = delay_CFGEXTREGISTERNUMBER;
assign #(out_delay) CFGEXTWRITEBYTEENABLE = delay_CFGEXTWRITEBYTEENABLE;
assign #(out_delay) CFGEXTWRITEDATA = delay_CFGEXTWRITEDATA;
assign #(out_delay) CFGEXTWRITERECEIVED = delay_CFGEXTWRITERECEIVED;
assign #(out_delay) CFGFCCPLD = delay_CFGFCCPLD;
assign #(out_delay) CFGFCCPLH = delay_CFGFCCPLH;
assign #(out_delay) CFGFCNPD = delay_CFGFCNPD;
assign #(out_delay) CFGFCNPH = delay_CFGFCNPH;
assign #(out_delay) CFGFCPD = delay_CFGFCPD;
assign #(out_delay) CFGFCPH = delay_CFGFCPH;
assign #(out_delay) CFGFLRINPROCESS = delay_CFGFLRINPROCESS;
assign #(out_delay) CFGFUNCTIONPOWERSTATE = delay_CFGFUNCTIONPOWERSTATE;
assign #(out_delay) CFGFUNCTIONSTATUS = delay_CFGFUNCTIONSTATUS;
assign #(out_delay) CFGHOTRESETOUT = delay_CFGHOTRESETOUT;
assign #(out_delay) CFGINPUTUPDATEDONE = delay_CFGINPUTUPDATEDONE;
assign #(out_delay) CFGINTERRUPTAOUTPUT = delay_CFGINTERRUPTAOUTPUT;
assign #(out_delay) CFGINTERRUPTBOUTPUT = delay_CFGINTERRUPTBOUTPUT;
assign #(out_delay) CFGINTERRUPTCOUTPUT = delay_CFGINTERRUPTCOUTPUT;
assign #(out_delay) CFGINTERRUPTDOUTPUT = delay_CFGINTERRUPTDOUTPUT;
assign #(out_delay) CFGINTERRUPTMSIDATA = delay_CFGINTERRUPTMSIDATA;
assign #(out_delay) CFGINTERRUPTMSIENABLE = delay_CFGINTERRUPTMSIENABLE;
assign #(out_delay) CFGINTERRUPTMSIFAIL = delay_CFGINTERRUPTMSIFAIL;
assign #(out_delay) CFGINTERRUPTMSIMASKUPDATE = delay_CFGINTERRUPTMSIMASKUPDATE;
assign #(out_delay) CFGINTERRUPTMSIMMENABLE = delay_CFGINTERRUPTMSIMMENABLE;
assign #(out_delay) CFGINTERRUPTMSISENT = delay_CFGINTERRUPTMSISENT;
assign #(out_delay) CFGINTERRUPTMSIVFENABLE = delay_CFGINTERRUPTMSIVFENABLE;
assign #(out_delay) CFGINTERRUPTMSIXENABLE = delay_CFGINTERRUPTMSIXENABLE;
assign #(out_delay) CFGINTERRUPTMSIXFAIL = delay_CFGINTERRUPTMSIXFAIL;
assign #(out_delay) CFGINTERRUPTMSIXMASK = delay_CFGINTERRUPTMSIXMASK;
assign #(out_delay) CFGINTERRUPTMSIXSENT = delay_CFGINTERRUPTMSIXSENT;
assign #(out_delay) CFGINTERRUPTMSIXVFENABLE = delay_CFGINTERRUPTMSIXVFENABLE;
assign #(out_delay) CFGINTERRUPTMSIXVFMASK = delay_CFGINTERRUPTMSIXVFMASK;
assign #(out_delay) CFGINTERRUPTSENT = delay_CFGINTERRUPTSENT;
assign #(out_delay) CFGLINKPOWERSTATE = delay_CFGLINKPOWERSTATE;
assign #(out_delay) CFGLOCALERROR = delay_CFGLOCALERROR;
assign #(out_delay) CFGLTRENABLE = delay_CFGLTRENABLE;
assign #(out_delay) CFGLTSSMSTATE = delay_CFGLTSSMSTATE;
assign #(out_delay) CFGMAXPAYLOAD = delay_CFGMAXPAYLOAD;
assign #(out_delay) CFGMAXREADREQ = delay_CFGMAXREADREQ;
assign #(out_delay) CFGMCUPDATEDONE = delay_CFGMCUPDATEDONE;
assign #(out_delay) CFGMGMTREADDATA = delay_CFGMGMTREADDATA;
assign #(out_delay) CFGMGMTREADWRITEDONE = delay_CFGMGMTREADWRITEDONE;
assign #(out_delay) CFGMSGRECEIVED = delay_CFGMSGRECEIVED;
assign #(out_delay) CFGMSGRECEIVEDDATA = delay_CFGMSGRECEIVEDDATA;
assign #(out_delay) CFGMSGRECEIVEDTYPE = delay_CFGMSGRECEIVEDTYPE;
assign #(out_delay) CFGMSGTRANSMITDONE = delay_CFGMSGTRANSMITDONE;
assign #(out_delay) CFGNEGOTIATEDWIDTH = delay_CFGNEGOTIATEDWIDTH;
assign #(out_delay) CFGOBFFENABLE = delay_CFGOBFFENABLE;
assign #(out_delay) CFGPERFUNCSTATUSDATA = delay_CFGPERFUNCSTATUSDATA;
assign #(out_delay) CFGPERFUNCTIONUPDATEDONE = delay_CFGPERFUNCTIONUPDATEDONE;
assign #(out_delay) CFGPHYLINKDOWN = delay_CFGPHYLINKDOWN;
assign #(out_delay) CFGPHYLINKSTATUS = delay_CFGPHYLINKSTATUS;
assign #(out_delay) CFGPLSTATUSCHANGE = delay_CFGPLSTATUSCHANGE;
assign #(out_delay) CFGPOWERSTATECHANGEINTERRUPT = delay_CFGPOWERSTATECHANGEINTERRUPT;
assign #(out_delay) CFGRCBSTATUS = delay_CFGRCBSTATUS;
assign #(out_delay) CFGTPHFUNCTIONNUM = delay_CFGTPHFUNCTIONNUM;
assign #(out_delay) CFGTPHREQUESTERENABLE = delay_CFGTPHREQUESTERENABLE;
assign #(out_delay) CFGTPHSTMODE = delay_CFGTPHSTMODE;
assign #(out_delay) CFGTPHSTTADDRESS = delay_CFGTPHSTTADDRESS;
assign #(out_delay) CFGTPHSTTREADENABLE = delay_CFGTPHSTTREADENABLE;
assign #(out_delay) CFGTPHSTTWRITEBYTEVALID = delay_CFGTPHSTTWRITEBYTEVALID;
assign #(out_delay) CFGTPHSTTWRITEDATA = delay_CFGTPHSTTWRITEDATA;
assign #(out_delay) CFGTPHSTTWRITEENABLE = delay_CFGTPHSTTWRITEENABLE;
assign #(out_delay) CFGVFFLRINPROCESS = delay_CFGVFFLRINPROCESS;
assign #(out_delay) CFGVFPOWERSTATE = delay_CFGVFPOWERSTATE;
assign #(out_delay) CFGVFSTATUS = delay_CFGVFSTATUS;
assign #(out_delay) CFGVFTPHREQUESTERENABLE = delay_CFGVFTPHREQUESTERENABLE;
assign #(out_delay) CFGVFTPHSTMODE = delay_CFGVFTPHSTMODE;
assign #(out_delay) DBGDATAOUT = delay_DBGDATAOUT;
assign #(out_delay) DRPDO = delay_DRPDO;
assign #(out_delay) DRPRDY = delay_DRPRDY;
assign #(out_delay) MAXISCQTDATA = delay_MAXISCQTDATA;
assign #(out_delay) MAXISCQTKEEP = delay_MAXISCQTKEEP;
assign #(out_delay) MAXISCQTLAST = delay_MAXISCQTLAST;
assign #(out_delay) MAXISCQTUSER = delay_MAXISCQTUSER;
assign #(out_delay) MAXISCQTVALID = delay_MAXISCQTVALID;
assign #(out_delay) MAXISRCTDATA = delay_MAXISRCTDATA;
assign #(out_delay) MAXISRCTKEEP = delay_MAXISRCTKEEP;
assign #(out_delay) MAXISRCTLAST = delay_MAXISRCTLAST;
assign #(out_delay) MAXISRCTUSER = delay_MAXISRCTUSER;
assign #(out_delay) MAXISRCTVALID = delay_MAXISRCTVALID;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAL = delay_MICOMPLETIONRAMREADADDRESSAL;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSAU = delay_MICOMPLETIONRAMREADADDRESSAU;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBL = delay_MICOMPLETIONRAMREADADDRESSBL;
assign #(out_delay) MICOMPLETIONRAMREADADDRESSBU = delay_MICOMPLETIONRAMREADADDRESSBU;
assign #(out_delay) MICOMPLETIONRAMREADENABLEL = delay_MICOMPLETIONRAMREADENABLEL;
assign #(out_delay) MICOMPLETIONRAMREADENABLEU = delay_MICOMPLETIONRAMREADENABLEU;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAL = delay_MICOMPLETIONRAMWRITEADDRESSAL;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSAU = delay_MICOMPLETIONRAMWRITEADDRESSAU;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBL = delay_MICOMPLETIONRAMWRITEADDRESSBL;
assign #(out_delay) MICOMPLETIONRAMWRITEADDRESSBU = delay_MICOMPLETIONRAMWRITEADDRESSBU;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAL = delay_MICOMPLETIONRAMWRITEDATAL;
assign #(out_delay) MICOMPLETIONRAMWRITEDATAU = delay_MICOMPLETIONRAMWRITEDATAU;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEL = delay_MICOMPLETIONRAMWRITEENABLEL;
assign #(out_delay) MICOMPLETIONRAMWRITEENABLEU = delay_MICOMPLETIONRAMWRITEENABLEU;
assign #(out_delay) MIREPLAYRAMADDRESS = delay_MIREPLAYRAMADDRESS;
assign #(out_delay) MIREPLAYRAMREADENABLE = delay_MIREPLAYRAMREADENABLE;
assign #(out_delay) MIREPLAYRAMWRITEDATA = delay_MIREPLAYRAMWRITEDATA;
assign #(out_delay) MIREPLAYRAMWRITEENABLE = delay_MIREPLAYRAMWRITEENABLE;
assign #(out_delay) MIREQUESTRAMREADADDRESSA = delay_MIREQUESTRAMREADADDRESSA;
assign #(out_delay) MIREQUESTRAMREADADDRESSB = delay_MIREQUESTRAMREADADDRESSB;
assign #(out_delay) MIREQUESTRAMREADENABLE = delay_MIREQUESTRAMREADENABLE;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSA = delay_MIREQUESTRAMWRITEADDRESSA;
assign #(out_delay) MIREQUESTRAMWRITEADDRESSB = delay_MIREQUESTRAMWRITEADDRESSB;
assign #(out_delay) MIREQUESTRAMWRITEDATA = delay_MIREQUESTRAMWRITEDATA;
assign #(out_delay) MIREQUESTRAMWRITEENABLE = delay_MIREQUESTRAMWRITEENABLE;
assign #(out_delay) PCIECQNPREQCOUNT = delay_PCIECQNPREQCOUNT;
assign #(out_delay) PCIERQSEQNUM = delay_PCIERQSEQNUM;
assign #(out_delay) PCIERQSEQNUMVLD = delay_PCIERQSEQNUMVLD;
assign #(out_delay) PCIERQTAG = delay_PCIERQTAG;
assign #(out_delay) PCIERQTAGAV = delay_PCIERQTAGAV;
assign #(out_delay) PCIERQTAGVLD = delay_PCIERQTAGVLD;
assign #(out_delay) PCIETFCNPDAV = delay_PCIETFCNPDAV;
assign #(out_delay) PCIETFCNPHAV = delay_PCIETFCNPHAV;
assign #(out_delay) PIPERX0EQCONTROL = delay_PIPERX0EQCONTROL;
assign #(out_delay) PIPERX0EQLPLFFS = delay_PIPERX0EQLPLFFS;
assign #(out_delay) PIPERX0EQLPTXPRESET = delay_PIPERX0EQLPTXPRESET;
assign #(out_delay) PIPERX0EQPRESET = delay_PIPERX0EQPRESET;
assign #(out_delay) PIPERX0POLARITY = delay_PIPERX0POLARITY;
assign #(out_delay) PIPERX1EQCONTROL = delay_PIPERX1EQCONTROL;
assign #(out_delay) PIPERX1EQLPLFFS = delay_PIPERX1EQLPLFFS;
assign #(out_delay) PIPERX1EQLPTXPRESET = delay_PIPERX1EQLPTXPRESET;
assign #(out_delay) PIPERX1EQPRESET = delay_PIPERX1EQPRESET;
assign #(out_delay) PIPERX1POLARITY = delay_PIPERX1POLARITY;
assign #(out_delay) PIPERX2EQCONTROL = delay_PIPERX2EQCONTROL;
assign #(out_delay) PIPERX2EQLPLFFS = delay_PIPERX2EQLPLFFS;
assign #(out_delay) PIPERX2EQLPTXPRESET = delay_PIPERX2EQLPTXPRESET;
assign #(out_delay) PIPERX2EQPRESET = delay_PIPERX2EQPRESET;
assign #(out_delay) PIPERX2POLARITY = delay_PIPERX2POLARITY;
assign #(out_delay) PIPERX3EQCONTROL = delay_PIPERX3EQCONTROL;
assign #(out_delay) PIPERX3EQLPLFFS = delay_PIPERX3EQLPLFFS;
assign #(out_delay) PIPERX3EQLPTXPRESET = delay_PIPERX3EQLPTXPRESET;
assign #(out_delay) PIPERX3EQPRESET = delay_PIPERX3EQPRESET;
assign #(out_delay) PIPERX3POLARITY = delay_PIPERX3POLARITY;
assign #(out_delay) PIPERX4EQCONTROL = delay_PIPERX4EQCONTROL;
assign #(out_delay) PIPERX4EQLPLFFS = delay_PIPERX4EQLPLFFS;
assign #(out_delay) PIPERX4EQLPTXPRESET = delay_PIPERX4EQLPTXPRESET;
assign #(out_delay) PIPERX4EQPRESET = delay_PIPERX4EQPRESET;
assign #(out_delay) PIPERX4POLARITY = delay_PIPERX4POLARITY;
assign #(out_delay) PIPERX5EQCONTROL = delay_PIPERX5EQCONTROL;
assign #(out_delay) PIPERX5EQLPLFFS = delay_PIPERX5EQLPLFFS;
assign #(out_delay) PIPERX5EQLPTXPRESET = delay_PIPERX5EQLPTXPRESET;
assign #(out_delay) PIPERX5EQPRESET = delay_PIPERX5EQPRESET;
assign #(out_delay) PIPERX5POLARITY = delay_PIPERX5POLARITY;
assign #(out_delay) PIPERX6EQCONTROL = delay_PIPERX6EQCONTROL;
assign #(out_delay) PIPERX6EQLPLFFS = delay_PIPERX6EQLPLFFS;
assign #(out_delay) PIPERX6EQLPTXPRESET = delay_PIPERX6EQLPTXPRESET;
assign #(out_delay) PIPERX6EQPRESET = delay_PIPERX6EQPRESET;
assign #(out_delay) PIPERX6POLARITY = delay_PIPERX6POLARITY;
assign #(out_delay) PIPERX7EQCONTROL = delay_PIPERX7EQCONTROL;
assign #(out_delay) PIPERX7EQLPLFFS = delay_PIPERX7EQLPLFFS;
assign #(out_delay) PIPERX7EQLPTXPRESET = delay_PIPERX7EQLPTXPRESET;
assign #(out_delay) PIPERX7EQPRESET = delay_PIPERX7EQPRESET;
assign #(out_delay) PIPERX7POLARITY = delay_PIPERX7POLARITY;
assign #(out_delay) PIPETX0CHARISK = delay_PIPETX0CHARISK;
assign #(out_delay) PIPETX0COMPLIANCE = delay_PIPETX0COMPLIANCE;
assign #(out_delay) PIPETX0DATA = delay_PIPETX0DATA;
assign #(out_delay) PIPETX0DATAVALID = delay_PIPETX0DATAVALID;
assign #(out_delay) PIPETX0ELECIDLE = delay_PIPETX0ELECIDLE;
assign #(out_delay) PIPETX0EQCONTROL = delay_PIPETX0EQCONTROL;
assign #(out_delay) PIPETX0EQDEEMPH = delay_PIPETX0EQDEEMPH;
assign #(out_delay) PIPETX0EQPRESET = delay_PIPETX0EQPRESET;
assign #(out_delay) PIPETX0POWERDOWN = delay_PIPETX0POWERDOWN;
assign #(out_delay) PIPETX0STARTBLOCK = delay_PIPETX0STARTBLOCK;
assign #(out_delay) PIPETX0SYNCHEADER = delay_PIPETX0SYNCHEADER;
assign #(out_delay) PIPETX1CHARISK = delay_PIPETX1CHARISK;
assign #(out_delay) PIPETX1COMPLIANCE = delay_PIPETX1COMPLIANCE;
assign #(out_delay) PIPETX1DATA = delay_PIPETX1DATA;
assign #(out_delay) PIPETX1DATAVALID = delay_PIPETX1DATAVALID;
assign #(out_delay) PIPETX1ELECIDLE = delay_PIPETX1ELECIDLE;
assign #(out_delay) PIPETX1EQCONTROL = delay_PIPETX1EQCONTROL;
assign #(out_delay) PIPETX1EQDEEMPH = delay_PIPETX1EQDEEMPH;
assign #(out_delay) PIPETX1EQPRESET = delay_PIPETX1EQPRESET;
assign #(out_delay) PIPETX1POWERDOWN = delay_PIPETX1POWERDOWN;
assign #(out_delay) PIPETX1STARTBLOCK = delay_PIPETX1STARTBLOCK;
assign #(out_delay) PIPETX1SYNCHEADER = delay_PIPETX1SYNCHEADER;
assign #(out_delay) PIPETX2CHARISK = delay_PIPETX2CHARISK;
assign #(out_delay) PIPETX2COMPLIANCE = delay_PIPETX2COMPLIANCE;
assign #(out_delay) PIPETX2DATA = delay_PIPETX2DATA;
assign #(out_delay) PIPETX2DATAVALID = delay_PIPETX2DATAVALID;
assign #(out_delay) PIPETX2ELECIDLE = delay_PIPETX2ELECIDLE;
assign #(out_delay) PIPETX2EQCONTROL = delay_PIPETX2EQCONTROL;
assign #(out_delay) PIPETX2EQDEEMPH = delay_PIPETX2EQDEEMPH;
assign #(out_delay) PIPETX2EQPRESET = delay_PIPETX2EQPRESET;
assign #(out_delay) PIPETX2POWERDOWN = delay_PIPETX2POWERDOWN;
assign #(out_delay) PIPETX2STARTBLOCK = delay_PIPETX2STARTBLOCK;
assign #(out_delay) PIPETX2SYNCHEADER = delay_PIPETX2SYNCHEADER;
assign #(out_delay) PIPETX3CHARISK = delay_PIPETX3CHARISK;
assign #(out_delay) PIPETX3COMPLIANCE = delay_PIPETX3COMPLIANCE;
assign #(out_delay) PIPETX3DATA = delay_PIPETX3DATA;
assign #(out_delay) PIPETX3DATAVALID = delay_PIPETX3DATAVALID;
assign #(out_delay) PIPETX3ELECIDLE = delay_PIPETX3ELECIDLE;
assign #(out_delay) PIPETX3EQCONTROL = delay_PIPETX3EQCONTROL;
assign #(out_delay) PIPETX3EQDEEMPH = delay_PIPETX3EQDEEMPH;
assign #(out_delay) PIPETX3EQPRESET = delay_PIPETX3EQPRESET;
assign #(out_delay) PIPETX3POWERDOWN = delay_PIPETX3POWERDOWN;
assign #(out_delay) PIPETX3STARTBLOCK = delay_PIPETX3STARTBLOCK;
assign #(out_delay) PIPETX3SYNCHEADER = delay_PIPETX3SYNCHEADER;
assign #(out_delay) PIPETX4CHARISK = delay_PIPETX4CHARISK;
assign #(out_delay) PIPETX4COMPLIANCE = delay_PIPETX4COMPLIANCE;
assign #(out_delay) PIPETX4DATA = delay_PIPETX4DATA;
assign #(out_delay) PIPETX4DATAVALID = delay_PIPETX4DATAVALID;
assign #(out_delay) PIPETX4ELECIDLE = delay_PIPETX4ELECIDLE;
assign #(out_delay) PIPETX4EQCONTROL = delay_PIPETX4EQCONTROL;
assign #(out_delay) PIPETX4EQDEEMPH = delay_PIPETX4EQDEEMPH;
assign #(out_delay) PIPETX4EQPRESET = delay_PIPETX4EQPRESET;
assign #(out_delay) PIPETX4POWERDOWN = delay_PIPETX4POWERDOWN;
assign #(out_delay) PIPETX4STARTBLOCK = delay_PIPETX4STARTBLOCK;
assign #(out_delay) PIPETX4SYNCHEADER = delay_PIPETX4SYNCHEADER;
assign #(out_delay) PIPETX5CHARISK = delay_PIPETX5CHARISK;
assign #(out_delay) PIPETX5COMPLIANCE = delay_PIPETX5COMPLIANCE;
assign #(out_delay) PIPETX5DATA = delay_PIPETX5DATA;
assign #(out_delay) PIPETX5DATAVALID = delay_PIPETX5DATAVALID;
assign #(out_delay) PIPETX5ELECIDLE = delay_PIPETX5ELECIDLE;
assign #(out_delay) PIPETX5EQCONTROL = delay_PIPETX5EQCONTROL;
assign #(out_delay) PIPETX5EQDEEMPH = delay_PIPETX5EQDEEMPH;
assign #(out_delay) PIPETX5EQPRESET = delay_PIPETX5EQPRESET;
assign #(out_delay) PIPETX5POWERDOWN = delay_PIPETX5POWERDOWN;
assign #(out_delay) PIPETX5STARTBLOCK = delay_PIPETX5STARTBLOCK;
assign #(out_delay) PIPETX5SYNCHEADER = delay_PIPETX5SYNCHEADER;
assign #(out_delay) PIPETX6CHARISK = delay_PIPETX6CHARISK;
assign #(out_delay) PIPETX6COMPLIANCE = delay_PIPETX6COMPLIANCE;
assign #(out_delay) PIPETX6DATA = delay_PIPETX6DATA;
assign #(out_delay) PIPETX6DATAVALID = delay_PIPETX6DATAVALID;
assign #(out_delay) PIPETX6ELECIDLE = delay_PIPETX6ELECIDLE;
assign #(out_delay) PIPETX6EQCONTROL = delay_PIPETX6EQCONTROL;
assign #(out_delay) PIPETX6EQDEEMPH = delay_PIPETX6EQDEEMPH;
assign #(out_delay) PIPETX6EQPRESET = delay_PIPETX6EQPRESET;
assign #(out_delay) PIPETX6POWERDOWN = delay_PIPETX6POWERDOWN;
assign #(out_delay) PIPETX6STARTBLOCK = delay_PIPETX6STARTBLOCK;
assign #(out_delay) PIPETX6SYNCHEADER = delay_PIPETX6SYNCHEADER;
assign #(out_delay) PIPETX7CHARISK = delay_PIPETX7CHARISK;
assign #(out_delay) PIPETX7COMPLIANCE = delay_PIPETX7COMPLIANCE;
assign #(out_delay) PIPETX7DATA = delay_PIPETX7DATA;
assign #(out_delay) PIPETX7DATAVALID = delay_PIPETX7DATAVALID;
assign #(out_delay) PIPETX7ELECIDLE = delay_PIPETX7ELECIDLE;
assign #(out_delay) PIPETX7EQCONTROL = delay_PIPETX7EQCONTROL;
assign #(out_delay) PIPETX7EQDEEMPH = delay_PIPETX7EQDEEMPH;
assign #(out_delay) PIPETX7EQPRESET = delay_PIPETX7EQPRESET;
assign #(out_delay) PIPETX7POWERDOWN = delay_PIPETX7POWERDOWN;
assign #(out_delay) PIPETX7STARTBLOCK = delay_PIPETX7STARTBLOCK;
assign #(out_delay) PIPETX7SYNCHEADER = delay_PIPETX7SYNCHEADER;
assign #(out_delay) PIPETXDEEMPH = delay_PIPETXDEEMPH;
assign #(out_delay) PIPETXMARGIN = delay_PIPETXMARGIN;
assign #(out_delay) PIPETXRATE = delay_PIPETXRATE;
assign #(out_delay) PIPETXRCVRDET = delay_PIPETXRCVRDET;
assign #(out_delay) PIPETXRESET = delay_PIPETXRESET;
assign #(out_delay) PIPETXSWING = delay_PIPETXSWING;
assign #(out_delay) PLEQINPROGRESS = delay_PLEQINPROGRESS;
assign #(out_delay) PLEQPHASE = delay_PLEQPHASE;
assign #(out_delay) PLGEN3PCSRXSLIDE = delay_PLGEN3PCSRXSLIDE;
assign #(out_delay) SAXISCCTREADY = delay_SAXISCCTREADY;
assign #(out_delay) SAXISRQTREADY = delay_SAXISRQTREADY;
`ifndef XIL_TIMING // unisim
assign #(INCLK_DELAY) delay_CORECLK = CORECLK;
assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML;
assign #(INCLK_DELAY) delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU;
assign #(INCLK_DELAY) delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM;
assign #(INCLK_DELAY) delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM;
assign #(INCLK_DELAY) delay_DRPCLK = DRPCLK;
assign #(INCLK_DELAY) delay_PIPECLK = PIPECLK;
assign #(INCLK_DELAY) delay_RECCLK = RECCLK;
assign #(INCLK_DELAY) delay_USERCLK = USERCLK;
assign #(in_delay) delay_CFGCONFIGSPACEENABLE = CFGCONFIGSPACEENABLE;
assign #(in_delay) delay_CFGDEVID = CFGDEVID;
assign #(in_delay) delay_CFGDSBUSNUMBER = CFGDSBUSNUMBER;
assign #(in_delay) delay_CFGDSDEVICENUMBER = CFGDSDEVICENUMBER;
assign #(in_delay) delay_CFGDSFUNCTIONNUMBER = CFGDSFUNCTIONNUMBER;
assign #(in_delay) delay_CFGDSN = CFGDSN;
assign #(in_delay) delay_CFGDSPORTNUMBER = CFGDSPORTNUMBER;
assign #(in_delay) delay_CFGERRCORIN = CFGERRCORIN;
assign #(in_delay) delay_CFGERRUNCORIN = CFGERRUNCORIN;
assign #(in_delay) delay_CFGEXTREADDATA = CFGEXTREADDATA;
assign #(in_delay) delay_CFGEXTREADDATAVALID = CFGEXTREADDATAVALID;
assign #(in_delay) delay_CFGFCSEL = CFGFCSEL;
assign #(in_delay) delay_CFGFLRDONE = CFGFLRDONE;
assign #(in_delay) delay_CFGHOTRESETIN = CFGHOTRESETIN;
assign #(in_delay) delay_CFGINPUTUPDATEREQUEST = CFGINPUTUPDATEREQUEST;
assign #(in_delay) delay_CFGINTERRUPTINT = CFGINTERRUPTINT;
assign #(in_delay) delay_CFGINTERRUPTMSIATTR = CFGINTERRUPTMSIATTR;
assign #(in_delay) delay_CFGINTERRUPTMSIFUNCTIONNUMBER = CFGINTERRUPTMSIFUNCTIONNUMBER;
assign #(in_delay) delay_CFGINTERRUPTMSIINT = CFGINTERRUPTMSIINT;
assign #(in_delay) delay_CFGINTERRUPTMSIPENDINGSTATUS = CFGINTERRUPTMSIPENDINGSTATUS;
assign #(in_delay) delay_CFGINTERRUPTMSISELECT = CFGINTERRUPTMSISELECT;
assign #(in_delay) delay_CFGINTERRUPTMSITPHPRESENT = CFGINTERRUPTMSITPHPRESENT;
assign #(in_delay) delay_CFGINTERRUPTMSITPHSTTAG = CFGINTERRUPTMSITPHSTTAG;
assign #(in_delay) delay_CFGINTERRUPTMSITPHTYPE = CFGINTERRUPTMSITPHTYPE;
assign #(in_delay) delay_CFGINTERRUPTMSIXADDRESS = CFGINTERRUPTMSIXADDRESS;
assign #(in_delay) delay_CFGINTERRUPTMSIXDATA = CFGINTERRUPTMSIXDATA;
assign #(in_delay) delay_CFGINTERRUPTMSIXINT = CFGINTERRUPTMSIXINT;
assign #(in_delay) delay_CFGINTERRUPTPENDING = CFGINTERRUPTPENDING;
assign #(in_delay) delay_CFGLINKTRAININGENABLE = CFGLINKTRAININGENABLE;
assign #(in_delay) delay_CFGMCUPDATEREQUEST = CFGMCUPDATEREQUEST;
assign #(in_delay) delay_CFGMGMTADDR = CFGMGMTADDR;
assign #(in_delay) delay_CFGMGMTBYTEENABLE = CFGMGMTBYTEENABLE;
assign #(in_delay) delay_CFGMGMTREAD = CFGMGMTREAD;
assign #(in_delay) delay_CFGMGMTTYPE1CFGREGACCESS = CFGMGMTTYPE1CFGREGACCESS;
assign #(in_delay) delay_CFGMGMTWRITE = CFGMGMTWRITE;
assign #(in_delay) delay_CFGMGMTWRITEDATA = CFGMGMTWRITEDATA;
assign #(in_delay) delay_CFGMSGTRANSMIT = CFGMSGTRANSMIT;
assign #(in_delay) delay_CFGMSGTRANSMITDATA = CFGMSGTRANSMITDATA;
assign #(in_delay) delay_CFGMSGTRANSMITTYPE = CFGMSGTRANSMITTYPE;
assign #(in_delay) delay_CFGPERFUNCSTATUSCONTROL = CFGPERFUNCSTATUSCONTROL;
assign #(in_delay) delay_CFGPERFUNCTIONNUMBER = CFGPERFUNCTIONNUMBER;
assign #(in_delay) delay_CFGPERFUNCTIONOUTPUTREQUEST = CFGPERFUNCTIONOUTPUTREQUEST;
assign #(in_delay) delay_CFGPOWERSTATECHANGEACK = CFGPOWERSTATECHANGEACK;
assign #(in_delay) delay_CFGREQPMTRANSITIONL23READY = CFGREQPMTRANSITIONL23READY;
assign #(in_delay) delay_CFGREVID = CFGREVID;
assign #(in_delay) delay_CFGSUBSYSID = CFGSUBSYSID;
assign #(in_delay) delay_CFGSUBSYSVENDID = CFGSUBSYSVENDID;
assign #(in_delay) delay_CFGTPHSTTREADDATA = CFGTPHSTTREADDATA;
assign #(in_delay) delay_CFGTPHSTTREADDATAVALID = CFGTPHSTTREADDATAVALID;
assign #(in_delay) delay_CFGVENDID = CFGVENDID;
assign #(in_delay) delay_CFGVFFLRDONE = CFGVFFLRDONE;
assign #(in_delay) delay_DRPADDR = DRPADDR;
assign #(in_delay) delay_DRPDI = DRPDI;
assign #(in_delay) delay_DRPEN = DRPEN;
assign #(in_delay) delay_DRPWE = DRPWE;
assign #(in_delay) delay_MAXISCQTREADY = MAXISCQTREADY;
assign #(in_delay) delay_MAXISRCTREADY = MAXISRCTREADY;
assign #(in_delay) delay_MGMTRESETN = MGMTRESETN;
assign #(in_delay) delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN;
assign #(in_delay) delay_MICOMPLETIONRAMREADDATA = MICOMPLETIONRAMREADDATA;
assign #(in_delay) delay_MIREPLAYRAMREADDATA = MIREPLAYRAMREADDATA;
assign #(in_delay) delay_MIREQUESTRAMREADDATA = MIREQUESTRAMREADDATA;
assign #(in_delay) delay_PCIECQNPREQ = PCIECQNPREQ;
assign #(in_delay) delay_PIPEEQFS = PIPEEQFS;
assign #(in_delay) delay_PIPEEQLF = PIPEEQLF;
assign #(in_delay) delay_PIPERESETN = PIPERESETN;
assign #(in_delay) delay_PIPERX0CHARISK = PIPERX0CHARISK;
assign #(in_delay) delay_PIPERX0DATA = PIPERX0DATA;
assign #(in_delay) delay_PIPERX0DATAVALID = PIPERX0DATAVALID;
assign #(in_delay) delay_PIPERX0ELECIDLE = PIPERX0ELECIDLE;
assign #(in_delay) delay_PIPERX0EQDONE = PIPERX0EQDONE;
assign #(in_delay) delay_PIPERX0EQLPADAPTDONE = PIPERX0EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX0EQLPLFFSSEL = PIPERX0EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX0EQLPNEWTXCOEFFORPRESET = PIPERX0EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX0PHYSTATUS = PIPERX0PHYSTATUS;
assign #(in_delay) delay_PIPERX0STARTBLOCK = PIPERX0STARTBLOCK;
assign #(in_delay) delay_PIPERX0STATUS = PIPERX0STATUS;
assign #(in_delay) delay_PIPERX0SYNCHEADER = PIPERX0SYNCHEADER;
assign #(in_delay) delay_PIPERX0VALID = PIPERX0VALID;
assign #(in_delay) delay_PIPERX1CHARISK = PIPERX1CHARISK;
assign #(in_delay) delay_PIPERX1DATA = PIPERX1DATA;
assign #(in_delay) delay_PIPERX1DATAVALID = PIPERX1DATAVALID;
assign #(in_delay) delay_PIPERX1ELECIDLE = PIPERX1ELECIDLE;
assign #(in_delay) delay_PIPERX1EQDONE = PIPERX1EQDONE;
assign #(in_delay) delay_PIPERX1EQLPADAPTDONE = PIPERX1EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX1EQLPLFFSSEL = PIPERX1EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX1EQLPNEWTXCOEFFORPRESET = PIPERX1EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX1PHYSTATUS = PIPERX1PHYSTATUS;
assign #(in_delay) delay_PIPERX1STARTBLOCK = PIPERX1STARTBLOCK;
assign #(in_delay) delay_PIPERX1STATUS = PIPERX1STATUS;
assign #(in_delay) delay_PIPERX1SYNCHEADER = PIPERX1SYNCHEADER;
assign #(in_delay) delay_PIPERX1VALID = PIPERX1VALID;
assign #(in_delay) delay_PIPERX2CHARISK = PIPERX2CHARISK;
assign #(in_delay) delay_PIPERX2DATA = PIPERX2DATA;
assign #(in_delay) delay_PIPERX2DATAVALID = PIPERX2DATAVALID;
assign #(in_delay) delay_PIPERX2ELECIDLE = PIPERX2ELECIDLE;
assign #(in_delay) delay_PIPERX2EQDONE = PIPERX2EQDONE;
assign #(in_delay) delay_PIPERX2EQLPADAPTDONE = PIPERX2EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX2EQLPLFFSSEL = PIPERX2EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX2EQLPNEWTXCOEFFORPRESET = PIPERX2EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX2PHYSTATUS = PIPERX2PHYSTATUS;
assign #(in_delay) delay_PIPERX2STARTBLOCK = PIPERX2STARTBLOCK;
assign #(in_delay) delay_PIPERX2STATUS = PIPERX2STATUS;
assign #(in_delay) delay_PIPERX2SYNCHEADER = PIPERX2SYNCHEADER;
assign #(in_delay) delay_PIPERX2VALID = PIPERX2VALID;
assign #(in_delay) delay_PIPERX3CHARISK = PIPERX3CHARISK;
assign #(in_delay) delay_PIPERX3DATA = PIPERX3DATA;
assign #(in_delay) delay_PIPERX3DATAVALID = PIPERX3DATAVALID;
assign #(in_delay) delay_PIPERX3ELECIDLE = PIPERX3ELECIDLE;
assign #(in_delay) delay_PIPERX3EQDONE = PIPERX3EQDONE;
assign #(in_delay) delay_PIPERX3EQLPADAPTDONE = PIPERX3EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX3EQLPLFFSSEL = PIPERX3EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX3EQLPNEWTXCOEFFORPRESET = PIPERX3EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX3PHYSTATUS = PIPERX3PHYSTATUS;
assign #(in_delay) delay_PIPERX3STARTBLOCK = PIPERX3STARTBLOCK;
assign #(in_delay) delay_PIPERX3STATUS = PIPERX3STATUS;
assign #(in_delay) delay_PIPERX3SYNCHEADER = PIPERX3SYNCHEADER;
assign #(in_delay) delay_PIPERX3VALID = PIPERX3VALID;
assign #(in_delay) delay_PIPERX4CHARISK = PIPERX4CHARISK;
assign #(in_delay) delay_PIPERX4DATA = PIPERX4DATA;
assign #(in_delay) delay_PIPERX4DATAVALID = PIPERX4DATAVALID;
assign #(in_delay) delay_PIPERX4ELECIDLE = PIPERX4ELECIDLE;
assign #(in_delay) delay_PIPERX4EQDONE = PIPERX4EQDONE;
assign #(in_delay) delay_PIPERX4EQLPADAPTDONE = PIPERX4EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX4EQLPLFFSSEL = PIPERX4EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX4EQLPNEWTXCOEFFORPRESET = PIPERX4EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX4PHYSTATUS = PIPERX4PHYSTATUS;
assign #(in_delay) delay_PIPERX4STARTBLOCK = PIPERX4STARTBLOCK;
assign #(in_delay) delay_PIPERX4STATUS = PIPERX4STATUS;
assign #(in_delay) delay_PIPERX4SYNCHEADER = PIPERX4SYNCHEADER;
assign #(in_delay) delay_PIPERX4VALID = PIPERX4VALID;
assign #(in_delay) delay_PIPERX5CHARISK = PIPERX5CHARISK;
assign #(in_delay) delay_PIPERX5DATA = PIPERX5DATA;
assign #(in_delay) delay_PIPERX5DATAVALID = PIPERX5DATAVALID;
assign #(in_delay) delay_PIPERX5ELECIDLE = PIPERX5ELECIDLE;
assign #(in_delay) delay_PIPERX5EQDONE = PIPERX5EQDONE;
assign #(in_delay) delay_PIPERX5EQLPADAPTDONE = PIPERX5EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX5EQLPLFFSSEL = PIPERX5EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX5EQLPNEWTXCOEFFORPRESET = PIPERX5EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX5PHYSTATUS = PIPERX5PHYSTATUS;
assign #(in_delay) delay_PIPERX5STARTBLOCK = PIPERX5STARTBLOCK;
assign #(in_delay) delay_PIPERX5STATUS = PIPERX5STATUS;
assign #(in_delay) delay_PIPERX5SYNCHEADER = PIPERX5SYNCHEADER;
assign #(in_delay) delay_PIPERX5VALID = PIPERX5VALID;
assign #(in_delay) delay_PIPERX6CHARISK = PIPERX6CHARISK;
assign #(in_delay) delay_PIPERX6DATA = PIPERX6DATA;
assign #(in_delay) delay_PIPERX6DATAVALID = PIPERX6DATAVALID;
assign #(in_delay) delay_PIPERX6ELECIDLE = PIPERX6ELECIDLE;
assign #(in_delay) delay_PIPERX6EQDONE = PIPERX6EQDONE;
assign #(in_delay) delay_PIPERX6EQLPADAPTDONE = PIPERX6EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX6EQLPLFFSSEL = PIPERX6EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX6EQLPNEWTXCOEFFORPRESET = PIPERX6EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX6PHYSTATUS = PIPERX6PHYSTATUS;
assign #(in_delay) delay_PIPERX6STARTBLOCK = PIPERX6STARTBLOCK;
assign #(in_delay) delay_PIPERX6STATUS = PIPERX6STATUS;
assign #(in_delay) delay_PIPERX6SYNCHEADER = PIPERX6SYNCHEADER;
assign #(in_delay) delay_PIPERX6VALID = PIPERX6VALID;
assign #(in_delay) delay_PIPERX7CHARISK = PIPERX7CHARISK;
assign #(in_delay) delay_PIPERX7DATA = PIPERX7DATA;
assign #(in_delay) delay_PIPERX7DATAVALID = PIPERX7DATAVALID;
assign #(in_delay) delay_PIPERX7ELECIDLE = PIPERX7ELECIDLE;
assign #(in_delay) delay_PIPERX7EQDONE = PIPERX7EQDONE;
assign #(in_delay) delay_PIPERX7EQLPADAPTDONE = PIPERX7EQLPADAPTDONE;
assign #(in_delay) delay_PIPERX7EQLPLFFSSEL = PIPERX7EQLPLFFSSEL;
assign #(in_delay) delay_PIPERX7EQLPNEWTXCOEFFORPRESET = PIPERX7EQLPNEWTXCOEFFORPRESET;
assign #(in_delay) delay_PIPERX7PHYSTATUS = PIPERX7PHYSTATUS;
assign #(in_delay) delay_PIPERX7STARTBLOCK = PIPERX7STARTBLOCK;
assign #(in_delay) delay_PIPERX7STATUS = PIPERX7STATUS;
assign #(in_delay) delay_PIPERX7SYNCHEADER = PIPERX7SYNCHEADER;
assign #(in_delay) delay_PIPERX7VALID = PIPERX7VALID;
assign #(in_delay) delay_PIPETX0EQCOEFF = PIPETX0EQCOEFF;
assign #(in_delay) delay_PIPETX0EQDONE = PIPETX0EQDONE;
assign #(in_delay) delay_PIPETX1EQCOEFF = PIPETX1EQCOEFF;
assign #(in_delay) delay_PIPETX1EQDONE = PIPETX1EQDONE;
assign #(in_delay) delay_PIPETX2EQCOEFF = PIPETX2EQCOEFF;
assign #(in_delay) delay_PIPETX2EQDONE = PIPETX2EQDONE;
assign #(in_delay) delay_PIPETX3EQCOEFF = PIPETX3EQCOEFF;
assign #(in_delay) delay_PIPETX3EQDONE = PIPETX3EQDONE;
assign #(in_delay) delay_PIPETX4EQCOEFF = PIPETX4EQCOEFF;
assign #(in_delay) delay_PIPETX4EQDONE = PIPETX4EQDONE;
assign #(in_delay) delay_PIPETX5EQCOEFF = PIPETX5EQCOEFF;
assign #(in_delay) delay_PIPETX5EQDONE = PIPETX5EQDONE;
assign #(in_delay) delay_PIPETX6EQCOEFF = PIPETX6EQCOEFF;
assign #(in_delay) delay_PIPETX6EQDONE = PIPETX6EQDONE;
assign #(in_delay) delay_PIPETX7EQCOEFF = PIPETX7EQCOEFF;
assign #(in_delay) delay_PIPETX7EQDONE = PIPETX7EQDONE;
assign #(in_delay) delay_PLDISABLESCRAMBLER = PLDISABLESCRAMBLER;
assign #(in_delay) delay_PLEQRESETEIEOSCOUNT = PLEQRESETEIEOSCOUNT;
assign #(in_delay) delay_PLGEN3PCSDISABLE = PLGEN3PCSDISABLE;
assign #(in_delay) delay_PLGEN3PCSRXSYNCDONE = PLGEN3PCSRXSYNCDONE;
assign #(in_delay) delay_RESETN = RESETN;
assign #(in_delay) delay_SAXISCCTDATA = SAXISCCTDATA;
assign #(in_delay) delay_SAXISCCTKEEP = SAXISCCTKEEP;
assign #(in_delay) delay_SAXISCCTLAST = SAXISCCTLAST;
assign #(in_delay) delay_SAXISCCTUSER = SAXISCCTUSER;
assign #(in_delay) delay_SAXISCCTVALID = SAXISCCTVALID;
assign #(in_delay) delay_SAXISRQTDATA = SAXISRQTDATA;
assign #(in_delay) delay_SAXISRQTKEEP = SAXISRQTKEEP;
assign #(in_delay) delay_SAXISRQTLAST = SAXISRQTLAST;
assign #(in_delay) delay_SAXISRQTUSER = SAXISRQTUSER;
assign #(in_delay) delay_SAXISRQTVALID = SAXISRQTVALID;
`endif // `ifndef XIL_TIMING
`ifdef XIL_TIMING //Simprim
assign delay_CORECLKMICOMPLETIONRAML = CORECLKMICOMPLETIONRAML;
assign delay_CORECLKMICOMPLETIONRAMU = CORECLKMICOMPLETIONRAMU;
assign delay_CORECLKMIREPLAYRAM = CORECLKMIREPLAYRAM;
assign delay_CORECLKMIREQUESTRAM = CORECLKMIREQUESTRAM;
assign delay_MGMTRESETN = MGMTRESETN;
assign delay_MGMTSTICKYRESETN = MGMTSTICKYRESETN;
assign delay_PIPERESETN = PIPERESETN;
assign delay_RESETN = RESETN;
`endif
B_PCIE_3_0 #(
.ARI_CAP_ENABLE (ARI_CAP_ENABLE),
.AXISTEN_IF_CC_ALIGNMENT_MODE (AXISTEN_IF_CC_ALIGNMENT_MODE),
.AXISTEN_IF_CC_PARITY_CHK (AXISTEN_IF_CC_PARITY_CHK),
.AXISTEN_IF_CQ_ALIGNMENT_MODE (AXISTEN_IF_CQ_ALIGNMENT_MODE),
.AXISTEN_IF_ENABLE_CLIENT_TAG (AXISTEN_IF_ENABLE_CLIENT_TAG),
.AXISTEN_IF_ENABLE_MSG_ROUTE (AXISTEN_IF_ENABLE_MSG_ROUTE),
.AXISTEN_IF_ENABLE_RX_MSG_INTFC (AXISTEN_IF_ENABLE_RX_MSG_INTFC),
.AXISTEN_IF_RC_ALIGNMENT_MODE (AXISTEN_IF_RC_ALIGNMENT_MODE),
.AXISTEN_IF_RC_STRADDLE (AXISTEN_IF_RC_STRADDLE),
.AXISTEN_IF_RQ_ALIGNMENT_MODE (AXISTEN_IF_RQ_ALIGNMENT_MODE),
.AXISTEN_IF_RQ_PARITY_CHK (AXISTEN_IF_RQ_PARITY_CHK),
.AXISTEN_IF_WIDTH (AXISTEN_IF_WIDTH),
.CRM_CORE_CLK_FREQ_500 (CRM_CORE_CLK_FREQ_500),
.CRM_USER_CLK_FREQ (CRM_USER_CLK_FREQ),
.DNSTREAM_LINK_NUM (DNSTREAM_LINK_NUM),
.GEN3_PCS_AUTO_REALIGN (GEN3_PCS_AUTO_REALIGN),
.GEN3_PCS_RX_ELECIDLE_INTERNAL (GEN3_PCS_RX_ELECIDLE_INTERNAL),
.LL_ACK_TIMEOUT (LL_ACK_TIMEOUT),
.LL_ACK_TIMEOUT_EN (LL_ACK_TIMEOUT_EN),
.LL_ACK_TIMEOUT_FUNC (LL_ACK_TIMEOUT_FUNC),
.LL_CPL_FC_UPDATE_TIMER (LL_CPL_FC_UPDATE_TIMER),
.LL_CPL_FC_UPDATE_TIMER_OVERRIDE (LL_CPL_FC_UPDATE_TIMER_OVERRIDE),
.LL_FC_UPDATE_TIMER (LL_FC_UPDATE_TIMER),
.LL_FC_UPDATE_TIMER_OVERRIDE (LL_FC_UPDATE_TIMER_OVERRIDE),
.LL_NP_FC_UPDATE_TIMER (LL_NP_FC_UPDATE_TIMER),
.LL_NP_FC_UPDATE_TIMER_OVERRIDE (LL_NP_FC_UPDATE_TIMER_OVERRIDE),
.LL_P_FC_UPDATE_TIMER (LL_P_FC_UPDATE_TIMER),
.LL_P_FC_UPDATE_TIMER_OVERRIDE (LL_P_FC_UPDATE_TIMER_OVERRIDE),
.LL_REPLAY_TIMEOUT (LL_REPLAY_TIMEOUT),
.LL_REPLAY_TIMEOUT_EN (LL_REPLAY_TIMEOUT_EN),
.LL_REPLAY_TIMEOUT_FUNC (LL_REPLAY_TIMEOUT_FUNC),
.LTR_TX_MESSAGE_MINIMUM_INTERVAL (LTR_TX_MESSAGE_MINIMUM_INTERVAL),
.LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE (LTR_TX_MESSAGE_ON_FUNC_POWER_STATE_CHANGE),
.LTR_TX_MESSAGE_ON_LTR_ENABLE (LTR_TX_MESSAGE_ON_LTR_ENABLE),
.PF0_AER_CAP_ECRC_CHECK_CAPABLE (PF0_AER_CAP_ECRC_CHECK_CAPABLE),
.PF0_AER_CAP_ECRC_GEN_CAPABLE (PF0_AER_CAP_ECRC_GEN_CAPABLE),
.PF0_AER_CAP_NEXTPTR (PF0_AER_CAP_NEXTPTR),
.PF0_ARI_CAP_NEXTPTR (PF0_ARI_CAP_NEXTPTR),
.PF0_ARI_CAP_NEXT_FUNC (PF0_ARI_CAP_NEXT_FUNC),
.PF0_ARI_CAP_VER (PF0_ARI_CAP_VER),
.PF0_BAR0_APERTURE_SIZE (PF0_BAR0_APERTURE_SIZE),
.PF0_BAR0_CONTROL (PF0_BAR0_CONTROL),
.PF0_BAR1_APERTURE_SIZE (PF0_BAR1_APERTURE_SIZE),
.PF0_BAR1_CONTROL (PF0_BAR1_CONTROL),
.PF0_BAR2_APERTURE_SIZE (PF0_BAR2_APERTURE_SIZE),
.PF0_BAR2_CONTROL (PF0_BAR2_CONTROL),
.PF0_BAR3_APERTURE_SIZE (PF0_BAR3_APERTURE_SIZE),
.PF0_BAR3_CONTROL (PF0_BAR3_CONTROL),
.PF0_BAR4_APERTURE_SIZE (PF0_BAR4_APERTURE_SIZE),
.PF0_BAR4_CONTROL (PF0_BAR4_CONTROL),
.PF0_BAR5_APERTURE_SIZE (PF0_BAR5_APERTURE_SIZE),
.PF0_BAR5_CONTROL (PF0_BAR5_CONTROL),
.PF0_BIST_REGISTER (PF0_BIST_REGISTER),
.PF0_CAPABILITY_POINTER (PF0_CAPABILITY_POINTER),
.PF0_CLASS_CODE (PF0_CLASS_CODE),
.PF0_DEVICE_ID (PF0_DEVICE_ID),
.PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_128B_CAS_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_32B_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT (PF0_DEV_CAP2_64B_ATOMIC_COMPLETER_SUPPORT),
.PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE (PF0_DEV_CAP2_CPL_TIMEOUT_DISABLE),
.PF0_DEV_CAP2_LTR_SUPPORT (PF0_DEV_CAP2_LTR_SUPPORT),
.PF0_DEV_CAP2_OBFF_SUPPORT (PF0_DEV_CAP2_OBFF_SUPPORT),
.PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT (PF0_DEV_CAP2_TPH_COMPLETER_SUPPORT),
.PF0_DEV_CAP_ENDPOINT_L0S_LATENCY (PF0_DEV_CAP_ENDPOINT_L0S_LATENCY),
.PF0_DEV_CAP_ENDPOINT_L1_LATENCY (PF0_DEV_CAP_ENDPOINT_L1_LATENCY),
.PF0_DEV_CAP_EXT_TAG_SUPPORTED (PF0_DEV_CAP_EXT_TAG_SUPPORTED),
.PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE (PF0_DEV_CAP_FUNCTION_LEVEL_RESET_CAPABLE),
.PF0_DEV_CAP_MAX_PAYLOAD_SIZE (PF0_DEV_CAP_MAX_PAYLOAD_SIZE),
.PF0_DPA_CAP_NEXTPTR (PF0_DPA_CAP_NEXTPTR),
.PF0_DPA_CAP_SUB_STATE_CONTROL (PF0_DPA_CAP_SUB_STATE_CONTROL),
.PF0_DPA_CAP_SUB_STATE_CONTROL_EN (PF0_DPA_CAP_SUB_STATE_CONTROL_EN),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
.PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF0_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
.PF0_DPA_CAP_VER (PF0_DPA_CAP_VER),
.PF0_DSN_CAP_NEXTPTR (PF0_DSN_CAP_NEXTPTR),
.PF0_EXPANSION_ROM_APERTURE_SIZE (PF0_EXPANSION_ROM_APERTURE_SIZE),
.PF0_EXPANSION_ROM_ENABLE (PF0_EXPANSION_ROM_ENABLE),
.PF0_INTERRUPT_LINE (PF0_INTERRUPT_LINE),
.PF0_INTERRUPT_PIN (PF0_INTERRUPT_PIN),
.PF0_LINK_CAP_ASPM_SUPPORT (PF0_LINK_CAP_ASPM_SUPPORT),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN1),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN2),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_COMCLK_GEN3),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN1),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN2),
.PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L0S_EXIT_LATENCY_GEN3),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN1),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN2),
.PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_COMCLK_GEN3),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN1),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN2),
.PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3 (PF0_LINK_CAP_L1_EXIT_LATENCY_GEN3),
.PF0_LINK_STATUS_SLOT_CLOCK_CONFIG (PF0_LINK_STATUS_SLOT_CLOCK_CONFIG),
.PF0_LTR_CAP_MAX_NOSNOOP_LAT (PF0_LTR_CAP_MAX_NOSNOOP_LAT),
.PF0_LTR_CAP_MAX_SNOOP_LAT (PF0_LTR_CAP_MAX_SNOOP_LAT),
.PF0_LTR_CAP_NEXTPTR (PF0_LTR_CAP_NEXTPTR),
.PF0_LTR_CAP_VER (PF0_LTR_CAP_VER),
.PF0_MSIX_CAP_NEXTPTR (PF0_MSIX_CAP_NEXTPTR),
.PF0_MSIX_CAP_PBA_BIR (PF0_MSIX_CAP_PBA_BIR),
.PF0_MSIX_CAP_PBA_OFFSET (PF0_MSIX_CAP_PBA_OFFSET),
.PF0_MSIX_CAP_TABLE_BIR (PF0_MSIX_CAP_TABLE_BIR),
.PF0_MSIX_CAP_TABLE_OFFSET (PF0_MSIX_CAP_TABLE_OFFSET),
.PF0_MSIX_CAP_TABLE_SIZE (PF0_MSIX_CAP_TABLE_SIZE),
.PF0_MSI_CAP_MULTIMSGCAP (PF0_MSI_CAP_MULTIMSGCAP),
.PF0_MSI_CAP_NEXTPTR (PF0_MSI_CAP_NEXTPTR),
.PF0_PB_CAP_NEXTPTR (PF0_PB_CAP_NEXTPTR),
.PF0_PB_CAP_SYSTEM_ALLOCATED (PF0_PB_CAP_SYSTEM_ALLOCATED),
.PF0_PB_CAP_VER (PF0_PB_CAP_VER),
.PF0_PM_CAP_ID (PF0_PM_CAP_ID),
.PF0_PM_CAP_NEXTPTR (PF0_PM_CAP_NEXTPTR),
.PF0_PM_CAP_PMESUPPORT_D0 (PF0_PM_CAP_PMESUPPORT_D0),
.PF0_PM_CAP_PMESUPPORT_D1 (PF0_PM_CAP_PMESUPPORT_D1),
.PF0_PM_CAP_PMESUPPORT_D3HOT (PF0_PM_CAP_PMESUPPORT_D3HOT),
.PF0_PM_CAP_SUPP_D1_STATE (PF0_PM_CAP_SUPP_D1_STATE),
.PF0_PM_CAP_VER_ID (PF0_PM_CAP_VER_ID),
.PF0_PM_CSR_NOSOFTRESET (PF0_PM_CSR_NOSOFTRESET),
.PF0_RBAR_CAP_ENABLE (PF0_RBAR_CAP_ENABLE),
.PF0_RBAR_CAP_INDEX0 (PF0_RBAR_CAP_INDEX0),
.PF0_RBAR_CAP_INDEX1 (PF0_RBAR_CAP_INDEX1),
.PF0_RBAR_CAP_INDEX2 (PF0_RBAR_CAP_INDEX2),
.PF0_RBAR_CAP_NEXTPTR (PF0_RBAR_CAP_NEXTPTR),
.PF0_RBAR_CAP_SIZE0 (PF0_RBAR_CAP_SIZE0),
.PF0_RBAR_CAP_SIZE1 (PF0_RBAR_CAP_SIZE1),
.PF0_RBAR_CAP_SIZE2 (PF0_RBAR_CAP_SIZE2),
.PF0_RBAR_CAP_VER (PF0_RBAR_CAP_VER),
.PF0_RBAR_NUM (PF0_RBAR_NUM),
.PF0_REVISION_ID (PF0_REVISION_ID),
.PF0_SRIOV_BAR0_APERTURE_SIZE (PF0_SRIOV_BAR0_APERTURE_SIZE),
.PF0_SRIOV_BAR0_CONTROL (PF0_SRIOV_BAR0_CONTROL),
.PF0_SRIOV_BAR1_APERTURE_SIZE (PF0_SRIOV_BAR1_APERTURE_SIZE),
.PF0_SRIOV_BAR1_CONTROL (PF0_SRIOV_BAR1_CONTROL),
.PF0_SRIOV_BAR2_APERTURE_SIZE (PF0_SRIOV_BAR2_APERTURE_SIZE),
.PF0_SRIOV_BAR2_CONTROL (PF0_SRIOV_BAR2_CONTROL),
.PF0_SRIOV_BAR3_APERTURE_SIZE (PF0_SRIOV_BAR3_APERTURE_SIZE),
.PF0_SRIOV_BAR3_CONTROL (PF0_SRIOV_BAR3_CONTROL),
.PF0_SRIOV_BAR4_APERTURE_SIZE (PF0_SRIOV_BAR4_APERTURE_SIZE),
.PF0_SRIOV_BAR4_CONTROL (PF0_SRIOV_BAR4_CONTROL),
.PF0_SRIOV_BAR5_APERTURE_SIZE (PF0_SRIOV_BAR5_APERTURE_SIZE),
.PF0_SRIOV_BAR5_CONTROL (PF0_SRIOV_BAR5_CONTROL),
.PF0_SRIOV_CAP_INITIAL_VF (PF0_SRIOV_CAP_INITIAL_VF),
.PF0_SRIOV_CAP_NEXTPTR (PF0_SRIOV_CAP_NEXTPTR),
.PF0_SRIOV_CAP_TOTAL_VF (PF0_SRIOV_CAP_TOTAL_VF),
.PF0_SRIOV_CAP_VER (PF0_SRIOV_CAP_VER),
.PF0_SRIOV_FIRST_VF_OFFSET (PF0_SRIOV_FIRST_VF_OFFSET),
.PF0_SRIOV_FUNC_DEP_LINK (PF0_SRIOV_FUNC_DEP_LINK),
.PF0_SRIOV_SUPPORTED_PAGE_SIZE (PF0_SRIOV_SUPPORTED_PAGE_SIZE),
.PF0_SRIOV_VF_DEVICE_ID (PF0_SRIOV_VF_DEVICE_ID),
.PF0_SUBSYSTEM_ID (PF0_SUBSYSTEM_ID),
.PF0_TPHR_CAP_DEV_SPECIFIC_MODE (PF0_TPHR_CAP_DEV_SPECIFIC_MODE),
.PF0_TPHR_CAP_ENABLE (PF0_TPHR_CAP_ENABLE),
.PF0_TPHR_CAP_INT_VEC_MODE (PF0_TPHR_CAP_INT_VEC_MODE),
.PF0_TPHR_CAP_NEXTPTR (PF0_TPHR_CAP_NEXTPTR),
.PF0_TPHR_CAP_ST_MODE_SEL (PF0_TPHR_CAP_ST_MODE_SEL),
.PF0_TPHR_CAP_ST_TABLE_LOC (PF0_TPHR_CAP_ST_TABLE_LOC),
.PF0_TPHR_CAP_ST_TABLE_SIZE (PF0_TPHR_CAP_ST_TABLE_SIZE),
.PF0_TPHR_CAP_VER (PF0_TPHR_CAP_VER),
.PF0_VC_CAP_NEXTPTR (PF0_VC_CAP_NEXTPTR),
.PF0_VC_CAP_VER (PF0_VC_CAP_VER),
.PF1_AER_CAP_ECRC_CHECK_CAPABLE (PF1_AER_CAP_ECRC_CHECK_CAPABLE),
.PF1_AER_CAP_ECRC_GEN_CAPABLE (PF1_AER_CAP_ECRC_GEN_CAPABLE),
.PF1_AER_CAP_NEXTPTR (PF1_AER_CAP_NEXTPTR),
.PF1_ARI_CAP_NEXTPTR (PF1_ARI_CAP_NEXTPTR),
.PF1_ARI_CAP_NEXT_FUNC (PF1_ARI_CAP_NEXT_FUNC),
.PF1_BAR0_APERTURE_SIZE (PF1_BAR0_APERTURE_SIZE),
.PF1_BAR0_CONTROL (PF1_BAR0_CONTROL),
.PF1_BAR1_APERTURE_SIZE (PF1_BAR1_APERTURE_SIZE),
.PF1_BAR1_CONTROL (PF1_BAR1_CONTROL),
.PF1_BAR2_APERTURE_SIZE (PF1_BAR2_APERTURE_SIZE),
.PF1_BAR2_CONTROL (PF1_BAR2_CONTROL),
.PF1_BAR3_APERTURE_SIZE (PF1_BAR3_APERTURE_SIZE),
.PF1_BAR3_CONTROL (PF1_BAR3_CONTROL),
.PF1_BAR4_APERTURE_SIZE (PF1_BAR4_APERTURE_SIZE),
.PF1_BAR4_CONTROL (PF1_BAR4_CONTROL),
.PF1_BAR5_APERTURE_SIZE (PF1_BAR5_APERTURE_SIZE),
.PF1_BAR5_CONTROL (PF1_BAR5_CONTROL),
.PF1_BIST_REGISTER (PF1_BIST_REGISTER),
.PF1_CAPABILITY_POINTER (PF1_CAPABILITY_POINTER),
.PF1_CLASS_CODE (PF1_CLASS_CODE),
.PF1_DEVICE_ID (PF1_DEVICE_ID),
.PF1_DEV_CAP_MAX_PAYLOAD_SIZE (PF1_DEV_CAP_MAX_PAYLOAD_SIZE),
.PF1_DPA_CAP_NEXTPTR (PF1_DPA_CAP_NEXTPTR),
.PF1_DPA_CAP_SUB_STATE_CONTROL (PF1_DPA_CAP_SUB_STATE_CONTROL),
.PF1_DPA_CAP_SUB_STATE_CONTROL_EN (PF1_DPA_CAP_SUB_STATE_CONTROL_EN),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION0),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION1),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION2),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION3),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION4),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION5),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION6),
.PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7 (PF1_DPA_CAP_SUB_STATE_POWER_ALLOCATION7),
.PF1_DPA_CAP_VER (PF1_DPA_CAP_VER),
.PF1_DSN_CAP_NEXTPTR (PF1_DSN_CAP_NEXTPTR),
.PF1_EXPANSION_ROM_APERTURE_SIZE (PF1_EXPANSION_ROM_APERTURE_SIZE),
.PF1_EXPANSION_ROM_ENABLE (PF1_EXPANSION_ROM_ENABLE),
.PF1_INTERRUPT_LINE (PF1_INTERRUPT_LINE),
.PF1_INTERRUPT_PIN (PF1_INTERRUPT_PIN),
.PF1_MSIX_CAP_NEXTPTR (PF1_MSIX_CAP_NEXTPTR),
.PF1_MSIX_CAP_PBA_BIR (PF1_MSIX_CAP_PBA_BIR),
.PF1_MSIX_CAP_PBA_OFFSET (PF1_MSIX_CAP_PBA_OFFSET),
.PF1_MSIX_CAP_TABLE_BIR (PF1_MSIX_CAP_TABLE_BIR),
.PF1_MSIX_CAP_TABLE_OFFSET (PF1_MSIX_CAP_TABLE_OFFSET),
.PF1_MSIX_CAP_TABLE_SIZE (PF1_MSIX_CAP_TABLE_SIZE),
.PF1_MSI_CAP_MULTIMSGCAP (PF1_MSI_CAP_MULTIMSGCAP),
.PF1_MSI_CAP_NEXTPTR (PF1_MSI_CAP_NEXTPTR),
.PF1_PB_CAP_NEXTPTR (PF1_PB_CAP_NEXTPTR),
.PF1_PB_CAP_SYSTEM_ALLOCATED (PF1_PB_CAP_SYSTEM_ALLOCATED),
.PF1_PB_CAP_VER (PF1_PB_CAP_VER),
.PF1_PM_CAP_ID (PF1_PM_CAP_ID),
.PF1_PM_CAP_NEXTPTR (PF1_PM_CAP_NEXTPTR),
.PF1_PM_CAP_VER_ID (PF1_PM_CAP_VER_ID),
.PF1_RBAR_CAP_ENABLE (PF1_RBAR_CAP_ENABLE),
.PF1_RBAR_CAP_INDEX0 (PF1_RBAR_CAP_INDEX0),
.PF1_RBAR_CAP_INDEX1 (PF1_RBAR_CAP_INDEX1),
.PF1_RBAR_CAP_INDEX2 (PF1_RBAR_CAP_INDEX2),
.PF1_RBAR_CAP_NEXTPTR (PF1_RBAR_CAP_NEXTPTR),
.PF1_RBAR_CAP_SIZE0 (PF1_RBAR_CAP_SIZE0),
.PF1_RBAR_CAP_SIZE1 (PF1_RBAR_CAP_SIZE1),
.PF1_RBAR_CAP_SIZE2 (PF1_RBAR_CAP_SIZE2),
.PF1_RBAR_CAP_VER (PF1_RBAR_CAP_VER),
.PF1_RBAR_NUM (PF1_RBAR_NUM),
.PF1_REVISION_ID (PF1_REVISION_ID),
.PF1_SRIOV_BAR0_APERTURE_SIZE (PF1_SRIOV_BAR0_APERTURE_SIZE),
.PF1_SRIOV_BAR0_CONTROL (PF1_SRIOV_BAR0_CONTROL),
.PF1_SRIOV_BAR1_APERTURE_SIZE (PF1_SRIOV_BAR1_APERTURE_SIZE),
.PF1_SRIOV_BAR1_CONTROL (PF1_SRIOV_BAR1_CONTROL),
.PF1_SRIOV_BAR2_APERTURE_SIZE (PF1_SRIOV_BAR2_APERTURE_SIZE),
.PF1_SRIOV_BAR2_CONTROL (PF1_SRIOV_BAR2_CONTROL),
.PF1_SRIOV_BAR3_APERTURE_SIZE (PF1_SRIOV_BAR3_APERTURE_SIZE),
.PF1_SRIOV_BAR3_CONTROL (PF1_SRIOV_BAR3_CONTROL),
.PF1_SRIOV_BAR4_APERTURE_SIZE (PF1_SRIOV_BAR4_APERTURE_SIZE),
.PF1_SRIOV_BAR4_CONTROL (PF1_SRIOV_BAR4_CONTROL),
.PF1_SRIOV_BAR5_APERTURE_SIZE (PF1_SRIOV_BAR5_APERTURE_SIZE),
.PF1_SRIOV_BAR5_CONTROL (PF1_SRIOV_BAR5_CONTROL),
.PF1_SRIOV_CAP_INITIAL_VF (PF1_SRIOV_CAP_INITIAL_VF),
.PF1_SRIOV_CAP_NEXTPTR (PF1_SRIOV_CAP_NEXTPTR),
.PF1_SRIOV_CAP_TOTAL_VF (PF1_SRIOV_CAP_TOTAL_VF),
.PF1_SRIOV_CAP_VER (PF1_SRIOV_CAP_VER),
.PF1_SRIOV_FIRST_VF_OFFSET (PF1_SRIOV_FIRST_VF_OFFSET),
.PF1_SRIOV_FUNC_DEP_LINK (PF1_SRIOV_FUNC_DEP_LINK),
.PF1_SRIOV_SUPPORTED_PAGE_SIZE (PF1_SRIOV_SUPPORTED_PAGE_SIZE),
.PF1_SRIOV_VF_DEVICE_ID (PF1_SRIOV_VF_DEVICE_ID),
.PF1_SUBSYSTEM_ID (PF1_SUBSYSTEM_ID),
.PF1_TPHR_CAP_DEV_SPECIFIC_MODE (PF1_TPHR_CAP_DEV_SPECIFIC_MODE),
.PF1_TPHR_CAP_ENABLE (PF1_TPHR_CAP_ENABLE),
.PF1_TPHR_CAP_INT_VEC_MODE (PF1_TPHR_CAP_INT_VEC_MODE),
.PF1_TPHR_CAP_NEXTPTR (PF1_TPHR_CAP_NEXTPTR),
.PF1_TPHR_CAP_ST_MODE_SEL (PF1_TPHR_CAP_ST_MODE_SEL),
.PF1_TPHR_CAP_ST_TABLE_LOC (PF1_TPHR_CAP_ST_TABLE_LOC),
.PF1_TPHR_CAP_ST_TABLE_SIZE (PF1_TPHR_CAP_ST_TABLE_SIZE),
.PF1_TPHR_CAP_VER (PF1_TPHR_CAP_VER),
.PL_DISABLE_EI_INFER_IN_L0 (PL_DISABLE_EI_INFER_IN_L0),
.PL_DISABLE_GEN3_DC_BALANCE (PL_DISABLE_GEN3_DC_BALANCE),
.PL_DISABLE_SCRAMBLING (PL_DISABLE_SCRAMBLING),
.PL_DISABLE_UPCONFIG_CAPABLE (PL_DISABLE_UPCONFIG_CAPABLE),
.PL_EQ_ADAPT_DISABLE_COEFF_CHECK (PL_EQ_ADAPT_DISABLE_COEFF_CHECK),
.PL_EQ_ADAPT_DISABLE_PRESET_CHECK (PL_EQ_ADAPT_DISABLE_PRESET_CHECK),
.PL_EQ_ADAPT_ITER_COUNT (PL_EQ_ADAPT_ITER_COUNT),
.PL_EQ_ADAPT_REJECT_RETRY_COUNT (PL_EQ_ADAPT_REJECT_RETRY_COUNT),
.PL_EQ_BYPASS_PHASE23 (PL_EQ_BYPASS_PHASE23),
.PL_EQ_SHORT_ADAPT_PHASE (PL_EQ_SHORT_ADAPT_PHASE),
.PL_LANE0_EQ_CONTROL (PL_LANE0_EQ_CONTROL),
.PL_LANE1_EQ_CONTROL (PL_LANE1_EQ_CONTROL),
.PL_LANE2_EQ_CONTROL (PL_LANE2_EQ_CONTROL),
.PL_LANE3_EQ_CONTROL (PL_LANE3_EQ_CONTROL),
.PL_LANE4_EQ_CONTROL (PL_LANE4_EQ_CONTROL),
.PL_LANE5_EQ_CONTROL (PL_LANE5_EQ_CONTROL),
.PL_LANE6_EQ_CONTROL (PL_LANE6_EQ_CONTROL),
.PL_LANE7_EQ_CONTROL (PL_LANE7_EQ_CONTROL),
.PL_LINK_CAP_MAX_LINK_SPEED (PL_LINK_CAP_MAX_LINK_SPEED),
.PL_LINK_CAP_MAX_LINK_WIDTH (PL_LINK_CAP_MAX_LINK_WIDTH),
.PL_N_FTS_COMCLK_GEN1 (PL_N_FTS_COMCLK_GEN1),
.PL_N_FTS_COMCLK_GEN2 (PL_N_FTS_COMCLK_GEN2),
.PL_N_FTS_COMCLK_GEN3 (PL_N_FTS_COMCLK_GEN3),
.PL_N_FTS_GEN1 (PL_N_FTS_GEN1),
.PL_N_FTS_GEN2 (PL_N_FTS_GEN2),
.PL_N_FTS_GEN3 (PL_N_FTS_GEN3),
.PL_SIM_FAST_LINK_TRAINING (PL_SIM_FAST_LINK_TRAINING),
.PL_UPSTREAM_FACING (PL_UPSTREAM_FACING),
.PM_ASPML0S_TIMEOUT (PM_ASPML0S_TIMEOUT),
.PM_ASPML1_ENTRY_DELAY (PM_ASPML1_ENTRY_DELAY),
.PM_ENABLE_SLOT_POWER_CAPTURE (PM_ENABLE_SLOT_POWER_CAPTURE),
.PM_L1_REENTRY_DELAY (PM_L1_REENTRY_DELAY),
.PM_PME_SERVICE_TIMEOUT_DELAY (PM_PME_SERVICE_TIMEOUT_DELAY),
.PM_PME_TURNOFF_ACK_DELAY (PM_PME_TURNOFF_ACK_DELAY),
.SIM_VERSION (SIM_VERSION),
.SPARE_BIT0 (SPARE_BIT0),
.SPARE_BIT1 (SPARE_BIT1),
.SPARE_BIT2 (SPARE_BIT2),
.SPARE_BIT3 (SPARE_BIT3),
.SPARE_BIT4 (SPARE_BIT4),
.SPARE_BIT5 (SPARE_BIT5),
.SPARE_BIT6 (SPARE_BIT6),
.SPARE_BIT7 (SPARE_BIT7),
.SPARE_BIT8 (SPARE_BIT8),
.SPARE_BYTE0 (SPARE_BYTE0),
.SPARE_BYTE1 (SPARE_BYTE1),
.SPARE_BYTE2 (SPARE_BYTE2),
.SPARE_BYTE3 (SPARE_BYTE3),
.SPARE_WORD0 (SPARE_WORD0),
.SPARE_WORD1 (SPARE_WORD1),
.SPARE_WORD2 (SPARE_WORD2),
.SPARE_WORD3 (SPARE_WORD3),
.SRIOV_CAP_ENABLE (SRIOV_CAP_ENABLE),
.TL_COMPL_TIMEOUT_REG0 (TL_COMPL_TIMEOUT_REG0),
.TL_COMPL_TIMEOUT_REG1 (TL_COMPL_TIMEOUT_REG1),
.TL_CREDITS_CD (TL_CREDITS_CD),
.TL_CREDITS_CH (TL_CREDITS_CH),
.TL_CREDITS_NPD (TL_CREDITS_NPD),
.TL_CREDITS_NPH (TL_CREDITS_NPH),
.TL_CREDITS_PD (TL_CREDITS_PD),
.TL_CREDITS_PH (TL_CREDITS_PH),
.TL_ENABLE_MESSAGE_RID_CHECK_ENABLE (TL_ENABLE_MESSAGE_RID_CHECK_ENABLE),
.TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE (TL_EXTENDED_CFG_EXTEND_INTERFACE_ENABLE),
.TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE (TL_LEGACY_CFG_EXTEND_INTERFACE_ENABLE),
.TL_LEGACY_MODE_ENABLE (TL_LEGACY_MODE_ENABLE),
.TL_PF_ENABLE_REG (TL_PF_ENABLE_REG),
.TL_TAG_MGMT_ENABLE (TL_TAG_MGMT_ENABLE),
.VF0_ARI_CAP_NEXTPTR (VF0_ARI_CAP_NEXTPTR),
.VF0_CAPABILITY_POINTER (VF0_CAPABILITY_POINTER),
.VF0_MSIX_CAP_PBA_BIR (VF0_MSIX_CAP_PBA_BIR),
.VF0_MSIX_CAP_PBA_OFFSET (VF0_MSIX_CAP_PBA_OFFSET),
.VF0_MSIX_CAP_TABLE_BIR (VF0_MSIX_CAP_TABLE_BIR),
.VF0_MSIX_CAP_TABLE_OFFSET (VF0_MSIX_CAP_TABLE_OFFSET),
.VF0_MSIX_CAP_TABLE_SIZE (VF0_MSIX_CAP_TABLE_SIZE),
.VF0_MSI_CAP_MULTIMSGCAP (VF0_MSI_CAP_MULTIMSGCAP),
.VF0_PM_CAP_ID (VF0_PM_CAP_ID),
.VF0_PM_CAP_NEXTPTR (VF0_PM_CAP_NEXTPTR),
.VF0_PM_CAP_VER_ID (VF0_PM_CAP_VER_ID),
.VF0_TPHR_CAP_DEV_SPECIFIC_MODE (VF0_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF0_TPHR_CAP_ENABLE (VF0_TPHR_CAP_ENABLE),
.VF0_TPHR_CAP_INT_VEC_MODE (VF0_TPHR_CAP_INT_VEC_MODE),
.VF0_TPHR_CAP_NEXTPTR (VF0_TPHR_CAP_NEXTPTR),
.VF0_TPHR_CAP_ST_MODE_SEL (VF0_TPHR_CAP_ST_MODE_SEL),
.VF0_TPHR_CAP_ST_TABLE_LOC (VF0_TPHR_CAP_ST_TABLE_LOC),
.VF0_TPHR_CAP_ST_TABLE_SIZE (VF0_TPHR_CAP_ST_TABLE_SIZE),
.VF0_TPHR_CAP_VER (VF0_TPHR_CAP_VER),
.VF1_ARI_CAP_NEXTPTR (VF1_ARI_CAP_NEXTPTR),
.VF1_MSIX_CAP_PBA_BIR (VF1_MSIX_CAP_PBA_BIR),
.VF1_MSIX_CAP_PBA_OFFSET (VF1_MSIX_CAP_PBA_OFFSET),
.VF1_MSIX_CAP_TABLE_BIR (VF1_MSIX_CAP_TABLE_BIR),
.VF1_MSIX_CAP_TABLE_OFFSET (VF1_MSIX_CAP_TABLE_OFFSET),
.VF1_MSIX_CAP_TABLE_SIZE (VF1_MSIX_CAP_TABLE_SIZE),
.VF1_MSI_CAP_MULTIMSGCAP (VF1_MSI_CAP_MULTIMSGCAP),
.VF1_PM_CAP_ID (VF1_PM_CAP_ID),
.VF1_PM_CAP_NEXTPTR (VF1_PM_CAP_NEXTPTR),
.VF1_PM_CAP_VER_ID (VF1_PM_CAP_VER_ID),
.VF1_TPHR_CAP_DEV_SPECIFIC_MODE (VF1_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF1_TPHR_CAP_ENABLE (VF1_TPHR_CAP_ENABLE),
.VF1_TPHR_CAP_INT_VEC_MODE (VF1_TPHR_CAP_INT_VEC_MODE),
.VF1_TPHR_CAP_NEXTPTR (VF1_TPHR_CAP_NEXTPTR),
.VF1_TPHR_CAP_ST_MODE_SEL (VF1_TPHR_CAP_ST_MODE_SEL),
.VF1_TPHR_CAP_ST_TABLE_LOC (VF1_TPHR_CAP_ST_TABLE_LOC),
.VF1_TPHR_CAP_ST_TABLE_SIZE (VF1_TPHR_CAP_ST_TABLE_SIZE),
.VF1_TPHR_CAP_VER (VF1_TPHR_CAP_VER),
.VF2_ARI_CAP_NEXTPTR (VF2_ARI_CAP_NEXTPTR),
.VF2_MSIX_CAP_PBA_BIR (VF2_MSIX_CAP_PBA_BIR),
.VF2_MSIX_CAP_PBA_OFFSET (VF2_MSIX_CAP_PBA_OFFSET),
.VF2_MSIX_CAP_TABLE_BIR (VF2_MSIX_CAP_TABLE_BIR),
.VF2_MSIX_CAP_TABLE_OFFSET (VF2_MSIX_CAP_TABLE_OFFSET),
.VF2_MSIX_CAP_TABLE_SIZE (VF2_MSIX_CAP_TABLE_SIZE),
.VF2_MSI_CAP_MULTIMSGCAP (VF2_MSI_CAP_MULTIMSGCAP),
.VF2_PM_CAP_ID (VF2_PM_CAP_ID),
.VF2_PM_CAP_NEXTPTR (VF2_PM_CAP_NEXTPTR),
.VF2_PM_CAP_VER_ID (VF2_PM_CAP_VER_ID),
.VF2_TPHR_CAP_DEV_SPECIFIC_MODE (VF2_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF2_TPHR_CAP_ENABLE (VF2_TPHR_CAP_ENABLE),
.VF2_TPHR_CAP_INT_VEC_MODE (VF2_TPHR_CAP_INT_VEC_MODE),
.VF2_TPHR_CAP_NEXTPTR (VF2_TPHR_CAP_NEXTPTR),
.VF2_TPHR_CAP_ST_MODE_SEL (VF2_TPHR_CAP_ST_MODE_SEL),
.VF2_TPHR_CAP_ST_TABLE_LOC (VF2_TPHR_CAP_ST_TABLE_LOC),
.VF2_TPHR_CAP_ST_TABLE_SIZE (VF2_TPHR_CAP_ST_TABLE_SIZE),
.VF2_TPHR_CAP_VER (VF2_TPHR_CAP_VER),
.VF3_ARI_CAP_NEXTPTR (VF3_ARI_CAP_NEXTPTR),
.VF3_MSIX_CAP_PBA_BIR (VF3_MSIX_CAP_PBA_BIR),
.VF3_MSIX_CAP_PBA_OFFSET (VF3_MSIX_CAP_PBA_OFFSET),
.VF3_MSIX_CAP_TABLE_BIR (VF3_MSIX_CAP_TABLE_BIR),
.VF3_MSIX_CAP_TABLE_OFFSET (VF3_MSIX_CAP_TABLE_OFFSET),
.VF3_MSIX_CAP_TABLE_SIZE (VF3_MSIX_CAP_TABLE_SIZE),
.VF3_MSI_CAP_MULTIMSGCAP (VF3_MSI_CAP_MULTIMSGCAP),
.VF3_PM_CAP_ID (VF3_PM_CAP_ID),
.VF3_PM_CAP_NEXTPTR (VF3_PM_CAP_NEXTPTR),
.VF3_PM_CAP_VER_ID (VF3_PM_CAP_VER_ID),
.VF3_TPHR_CAP_DEV_SPECIFIC_MODE (VF3_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF3_TPHR_CAP_ENABLE (VF3_TPHR_CAP_ENABLE),
.VF3_TPHR_CAP_INT_VEC_MODE (VF3_TPHR_CAP_INT_VEC_MODE),
.VF3_TPHR_CAP_NEXTPTR (VF3_TPHR_CAP_NEXTPTR),
.VF3_TPHR_CAP_ST_MODE_SEL (VF3_TPHR_CAP_ST_MODE_SEL),
.VF3_TPHR_CAP_ST_TABLE_LOC (VF3_TPHR_CAP_ST_TABLE_LOC),
.VF3_TPHR_CAP_ST_TABLE_SIZE (VF3_TPHR_CAP_ST_TABLE_SIZE),
.VF3_TPHR_CAP_VER (VF3_TPHR_CAP_VER),
.VF4_ARI_CAP_NEXTPTR (VF4_ARI_CAP_NEXTPTR),
.VF4_MSIX_CAP_PBA_BIR (VF4_MSIX_CAP_PBA_BIR),
.VF4_MSIX_CAP_PBA_OFFSET (VF4_MSIX_CAP_PBA_OFFSET),
.VF4_MSIX_CAP_TABLE_BIR (VF4_MSIX_CAP_TABLE_BIR),
.VF4_MSIX_CAP_TABLE_OFFSET (VF4_MSIX_CAP_TABLE_OFFSET),
.VF4_MSIX_CAP_TABLE_SIZE (VF4_MSIX_CAP_TABLE_SIZE),
.VF4_MSI_CAP_MULTIMSGCAP (VF4_MSI_CAP_MULTIMSGCAP),
.VF4_PM_CAP_ID (VF4_PM_CAP_ID),
.VF4_PM_CAP_NEXTPTR (VF4_PM_CAP_NEXTPTR),
.VF4_PM_CAP_VER_ID (VF4_PM_CAP_VER_ID),
.VF4_TPHR_CAP_DEV_SPECIFIC_MODE (VF4_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF4_TPHR_CAP_ENABLE (VF4_TPHR_CAP_ENABLE),
.VF4_TPHR_CAP_INT_VEC_MODE (VF4_TPHR_CAP_INT_VEC_MODE),
.VF4_TPHR_CAP_NEXTPTR (VF4_TPHR_CAP_NEXTPTR),
.VF4_TPHR_CAP_ST_MODE_SEL (VF4_TPHR_CAP_ST_MODE_SEL),
.VF4_TPHR_CAP_ST_TABLE_LOC (VF4_TPHR_CAP_ST_TABLE_LOC),
.VF4_TPHR_CAP_ST_TABLE_SIZE (VF4_TPHR_CAP_ST_TABLE_SIZE),
.VF4_TPHR_CAP_VER (VF4_TPHR_CAP_VER),
.VF5_ARI_CAP_NEXTPTR (VF5_ARI_CAP_NEXTPTR),
.VF5_MSIX_CAP_PBA_BIR (VF5_MSIX_CAP_PBA_BIR),
.VF5_MSIX_CAP_PBA_OFFSET (VF5_MSIX_CAP_PBA_OFFSET),
.VF5_MSIX_CAP_TABLE_BIR (VF5_MSIX_CAP_TABLE_BIR),
.VF5_MSIX_CAP_TABLE_OFFSET (VF5_MSIX_CAP_TABLE_OFFSET),
.VF5_MSIX_CAP_TABLE_SIZE (VF5_MSIX_CAP_TABLE_SIZE),
.VF5_MSI_CAP_MULTIMSGCAP (VF5_MSI_CAP_MULTIMSGCAP),
.VF5_PM_CAP_ID (VF5_PM_CAP_ID),
.VF5_PM_CAP_NEXTPTR (VF5_PM_CAP_NEXTPTR),
.VF5_PM_CAP_VER_ID (VF5_PM_CAP_VER_ID),
.VF5_TPHR_CAP_DEV_SPECIFIC_MODE (VF5_TPHR_CAP_DEV_SPECIFIC_MODE),
.VF5_TPHR_CAP_ENABLE (VF5_TPHR_CAP_ENABLE),
.VF5_TPHR_CAP_INT_VEC_MODE (VF5_TPHR_CAP_INT_VEC_MODE),
.VF5_TPHR_CAP_NEXTPTR (VF5_TPHR_CAP_NEXTPTR),
.VF5_TPHR_CAP_ST_MODE_SEL (VF5_TPHR_CAP_ST_MODE_SEL),
.VF5_TPHR_CAP_ST_TABLE_LOC (VF5_TPHR_CAP_ST_TABLE_LOC),
.VF5_TPHR_CAP_ST_TABLE_SIZE (VF5_TPHR_CAP_ST_TABLE_SIZE),
.VF5_TPHR_CAP_VER (VF5_TPHR_CAP_VER))
B_PCIE_3_0_INST (
.CFGCURRENTSPEED (delay_CFGCURRENTSPEED),
.CFGDPASUBSTATECHANGE (delay_CFGDPASUBSTATECHANGE),
.CFGERRCOROUT (delay_CFGERRCOROUT),
.CFGERRFATALOUT (delay_CFGERRFATALOUT),
.CFGERRNONFATALOUT (delay_CFGERRNONFATALOUT),
.CFGEXTFUNCTIONNUMBER (delay_CFGEXTFUNCTIONNUMBER),
.CFGEXTREADRECEIVED (delay_CFGEXTREADRECEIVED),
.CFGEXTREGISTERNUMBER (delay_CFGEXTREGISTERNUMBER),
.CFGEXTWRITEBYTEENABLE (delay_CFGEXTWRITEBYTEENABLE),
.CFGEXTWRITEDATA (delay_CFGEXTWRITEDATA),
.CFGEXTWRITERECEIVED (delay_CFGEXTWRITERECEIVED),
.CFGFCCPLD (delay_CFGFCCPLD),
.CFGFCCPLH (delay_CFGFCCPLH),
.CFGFCNPD (delay_CFGFCNPD),
.CFGFCNPH (delay_CFGFCNPH),
.CFGFCPD (delay_CFGFCPD),
.CFGFCPH (delay_CFGFCPH),
.CFGFLRINPROCESS (delay_CFGFLRINPROCESS),
.CFGFUNCTIONPOWERSTATE (delay_CFGFUNCTIONPOWERSTATE),
.CFGFUNCTIONSTATUS (delay_CFGFUNCTIONSTATUS),
.CFGHOTRESETOUT (delay_CFGHOTRESETOUT),
.CFGINPUTUPDATEDONE (delay_CFGINPUTUPDATEDONE),
.CFGINTERRUPTAOUTPUT (delay_CFGINTERRUPTAOUTPUT),
.CFGINTERRUPTBOUTPUT (delay_CFGINTERRUPTBOUTPUT),
.CFGINTERRUPTCOUTPUT (delay_CFGINTERRUPTCOUTPUT),
.CFGINTERRUPTDOUTPUT (delay_CFGINTERRUPTDOUTPUT),
.CFGINTERRUPTMSIDATA (delay_CFGINTERRUPTMSIDATA),
.CFGINTERRUPTMSIENABLE (delay_CFGINTERRUPTMSIENABLE),
.CFGINTERRUPTMSIFAIL (delay_CFGINTERRUPTMSIFAIL),
.CFGINTERRUPTMSIMASKUPDATE (delay_CFGINTERRUPTMSIMASKUPDATE),
.CFGINTERRUPTMSIMMENABLE (delay_CFGINTERRUPTMSIMMENABLE),
.CFGINTERRUPTMSISENT (delay_CFGINTERRUPTMSISENT),
.CFGINTERRUPTMSIVFENABLE (delay_CFGINTERRUPTMSIVFENABLE),
.CFGINTERRUPTMSIXENABLE (delay_CFGINTERRUPTMSIXENABLE),
.CFGINTERRUPTMSIXFAIL (delay_CFGINTERRUPTMSIXFAIL),
.CFGINTERRUPTMSIXMASK (delay_CFGINTERRUPTMSIXMASK),
.CFGINTERRUPTMSIXSENT (delay_CFGINTERRUPTMSIXSENT),
.CFGINTERRUPTMSIXVFENABLE (delay_CFGINTERRUPTMSIXVFENABLE),
.CFGINTERRUPTMSIXVFMASK (delay_CFGINTERRUPTMSIXVFMASK),
.CFGINTERRUPTSENT (delay_CFGINTERRUPTSENT),
.CFGLINKPOWERSTATE (delay_CFGLINKPOWERSTATE),
.CFGLOCALERROR (delay_CFGLOCALERROR),
.CFGLTRENABLE (delay_CFGLTRENABLE),
.CFGLTSSMSTATE (delay_CFGLTSSMSTATE),
.CFGMAXPAYLOAD (delay_CFGMAXPAYLOAD),
.CFGMAXREADREQ (delay_CFGMAXREADREQ),
.CFGMCUPDATEDONE (delay_CFGMCUPDATEDONE),
.CFGMGMTREADDATA (delay_CFGMGMTREADDATA),
.CFGMGMTREADWRITEDONE (delay_CFGMGMTREADWRITEDONE),
.CFGMSGRECEIVED (delay_CFGMSGRECEIVED),
.CFGMSGRECEIVEDDATA (delay_CFGMSGRECEIVEDDATA),
.CFGMSGRECEIVEDTYPE (delay_CFGMSGRECEIVEDTYPE),
.CFGMSGTRANSMITDONE (delay_CFGMSGTRANSMITDONE),
.CFGNEGOTIATEDWIDTH (delay_CFGNEGOTIATEDWIDTH),
.CFGOBFFENABLE (delay_CFGOBFFENABLE),
.CFGPERFUNCSTATUSDATA (delay_CFGPERFUNCSTATUSDATA),
.CFGPERFUNCTIONUPDATEDONE (delay_CFGPERFUNCTIONUPDATEDONE),
.CFGPHYLINKDOWN (delay_CFGPHYLINKDOWN),
.CFGPHYLINKSTATUS (delay_CFGPHYLINKSTATUS),
.CFGPLSTATUSCHANGE (delay_CFGPLSTATUSCHANGE),
.CFGPOWERSTATECHANGEINTERRUPT (delay_CFGPOWERSTATECHANGEINTERRUPT),
.CFGRCBSTATUS (delay_CFGRCBSTATUS),
.CFGTPHFUNCTIONNUM (delay_CFGTPHFUNCTIONNUM),
.CFGTPHREQUESTERENABLE (delay_CFGTPHREQUESTERENABLE),
.CFGTPHSTMODE (delay_CFGTPHSTMODE),
.CFGTPHSTTADDRESS (delay_CFGTPHSTTADDRESS),
.CFGTPHSTTREADENABLE (delay_CFGTPHSTTREADENABLE),
.CFGTPHSTTWRITEBYTEVALID (delay_CFGTPHSTTWRITEBYTEVALID),
.CFGTPHSTTWRITEDATA (delay_CFGTPHSTTWRITEDATA),
.CFGTPHSTTWRITEENABLE (delay_CFGTPHSTTWRITEENABLE),
.CFGVFFLRINPROCESS (delay_CFGVFFLRINPROCESS),
.CFGVFPOWERSTATE (delay_CFGVFPOWERSTATE),
.CFGVFSTATUS (delay_CFGVFSTATUS),
.CFGVFTPHREQUESTERENABLE (delay_CFGVFTPHREQUESTERENABLE),
.CFGVFTPHSTMODE (delay_CFGVFTPHSTMODE),
.DBGDATAOUT (delay_DBGDATAOUT),
.DRPDO (delay_DRPDO),
.DRPRDY (delay_DRPRDY),
.MAXISCQTDATA (delay_MAXISCQTDATA),
.MAXISCQTKEEP (delay_MAXISCQTKEEP),
.MAXISCQTLAST (delay_MAXISCQTLAST),
.MAXISCQTUSER (delay_MAXISCQTUSER),
.MAXISCQTVALID (delay_MAXISCQTVALID),
.MAXISRCTDATA (delay_MAXISRCTDATA),
.MAXISRCTKEEP (delay_MAXISRCTKEEP),
.MAXISRCTLAST (delay_MAXISRCTLAST),
.MAXISRCTUSER (delay_MAXISRCTUSER),
.MAXISRCTVALID (delay_MAXISRCTVALID),
.MICOMPLETIONRAMREADADDRESSAL (delay_MICOMPLETIONRAMREADADDRESSAL),
.MICOMPLETIONRAMREADADDRESSAU (delay_MICOMPLETIONRAMREADADDRESSAU),
.MICOMPLETIONRAMREADADDRESSBL (delay_MICOMPLETIONRAMREADADDRESSBL),
.MICOMPLETIONRAMREADADDRESSBU (delay_MICOMPLETIONRAMREADADDRESSBU),
.MICOMPLETIONRAMREADENABLEL (delay_MICOMPLETIONRAMREADENABLEL),
.MICOMPLETIONRAMREADENABLEU (delay_MICOMPLETIONRAMREADENABLEU),
.MICOMPLETIONRAMWRITEADDRESSAL (delay_MICOMPLETIONRAMWRITEADDRESSAL),
.MICOMPLETIONRAMWRITEADDRESSAU (delay_MICOMPLETIONRAMWRITEADDRESSAU),
.MICOMPLETIONRAMWRITEADDRESSBL (delay_MICOMPLETIONRAMWRITEADDRESSBL),
.MICOMPLETIONRAMWRITEADDRESSBU (delay_MICOMPLETIONRAMWRITEADDRESSBU),
.MICOMPLETIONRAMWRITEDATAL (delay_MICOMPLETIONRAMWRITEDATAL),
.MICOMPLETIONRAMWRITEDATAU (delay_MICOMPLETIONRAMWRITEDATAU),
.MICOMPLETIONRAMWRITEENABLEL (delay_MICOMPLETIONRAMWRITEENABLEL),
.MICOMPLETIONRAMWRITEENABLEU (delay_MICOMPLETIONRAMWRITEENABLEU),
.MIREPLAYRAMADDRESS (delay_MIREPLAYRAMADDRESS),
.MIREPLAYRAMREADENABLE (delay_MIREPLAYRAMREADENABLE),
.MIREPLAYRAMWRITEDATA (delay_MIREPLAYRAMWRITEDATA),
.MIREPLAYRAMWRITEENABLE (delay_MIREPLAYRAMWRITEENABLE),
.MIREQUESTRAMREADADDRESSA (delay_MIREQUESTRAMREADADDRESSA),
.MIREQUESTRAMREADADDRESSB (delay_MIREQUESTRAMREADADDRESSB),
.MIREQUESTRAMREADENABLE (delay_MIREQUESTRAMREADENABLE),
.MIREQUESTRAMWRITEADDRESSA (delay_MIREQUESTRAMWRITEADDRESSA),
.MIREQUESTRAMWRITEADDRESSB (delay_MIREQUESTRAMWRITEADDRESSB),
.MIREQUESTRAMWRITEDATA (delay_MIREQUESTRAMWRITEDATA),
.MIREQUESTRAMWRITEENABLE (delay_MIREQUESTRAMWRITEENABLE),
.PCIECQNPREQCOUNT (delay_PCIECQNPREQCOUNT),
.PCIERQSEQNUM (delay_PCIERQSEQNUM),
.PCIERQSEQNUMVLD (delay_PCIERQSEQNUMVLD),
.PCIERQTAG (delay_PCIERQTAG),
.PCIERQTAGAV (delay_PCIERQTAGAV),
.PCIERQTAGVLD (delay_PCIERQTAGVLD),
.PCIETFCNPDAV (delay_PCIETFCNPDAV),
.PCIETFCNPHAV (delay_PCIETFCNPHAV),
.PIPERX0EQCONTROL (delay_PIPERX0EQCONTROL),
.PIPERX0EQLPLFFS (delay_PIPERX0EQLPLFFS),
.PIPERX0EQLPTXPRESET (delay_PIPERX0EQLPTXPRESET),
.PIPERX0EQPRESET (delay_PIPERX0EQPRESET),
.PIPERX0POLARITY (delay_PIPERX0POLARITY),
.PIPERX1EQCONTROL (delay_PIPERX1EQCONTROL),
.PIPERX1EQLPLFFS (delay_PIPERX1EQLPLFFS),
.PIPERX1EQLPTXPRESET (delay_PIPERX1EQLPTXPRESET),
.PIPERX1EQPRESET (delay_PIPERX1EQPRESET),
.PIPERX1POLARITY (delay_PIPERX1POLARITY),
.PIPERX2EQCONTROL (delay_PIPERX2EQCONTROL),
.PIPERX2EQLPLFFS (delay_PIPERX2EQLPLFFS),
.PIPERX2EQLPTXPRESET (delay_PIPERX2EQLPTXPRESET),
.PIPERX2EQPRESET (delay_PIPERX2EQPRESET),
.PIPERX2POLARITY (delay_PIPERX2POLARITY),
.PIPERX3EQCONTROL (delay_PIPERX3EQCONTROL),
.PIPERX3EQLPLFFS (delay_PIPERX3EQLPLFFS),
.PIPERX3EQLPTXPRESET (delay_PIPERX3EQLPTXPRESET),
.PIPERX3EQPRESET (delay_PIPERX3EQPRESET),
.PIPERX3POLARITY (delay_PIPERX3POLARITY),
.PIPERX4EQCONTROL (delay_PIPERX4EQCONTROL),
.PIPERX4EQLPLFFS (delay_PIPERX4EQLPLFFS),
.PIPERX4EQLPTXPRESET (delay_PIPERX4EQLPTXPRESET),
.PIPERX4EQPRESET (delay_PIPERX4EQPRESET),
.PIPERX4POLARITY (delay_PIPERX4POLARITY),
.PIPERX5EQCONTROL (delay_PIPERX5EQCONTROL),
.PIPERX5EQLPLFFS (delay_PIPERX5EQLPLFFS),
.PIPERX5EQLPTXPRESET (delay_PIPERX5EQLPTXPRESET),
.PIPERX5EQPRESET (delay_PIPERX5EQPRESET),
.PIPERX5POLARITY (delay_PIPERX5POLARITY),
.PIPERX6EQCONTROL (delay_PIPERX6EQCONTROL),
.PIPERX6EQLPLFFS (delay_PIPERX6EQLPLFFS),
.PIPERX6EQLPTXPRESET (delay_PIPERX6EQLPTXPRESET),
.PIPERX6EQPRESET (delay_PIPERX6EQPRESET),
.PIPERX6POLARITY (delay_PIPERX6POLARITY),
.PIPERX7EQCONTROL (delay_PIPERX7EQCONTROL),
.PIPERX7EQLPLFFS (delay_PIPERX7EQLPLFFS),
.PIPERX7EQLPTXPRESET (delay_PIPERX7EQLPTXPRESET),
.PIPERX7EQPRESET (delay_PIPERX7EQPRESET),
.PIPERX7POLARITY (delay_PIPERX7POLARITY),
.PIPETX0CHARISK (delay_PIPETX0CHARISK),
.PIPETX0COMPLIANCE (delay_PIPETX0COMPLIANCE),
.PIPETX0DATA (delay_PIPETX0DATA),
.PIPETX0DATAVALID (delay_PIPETX0DATAVALID),
.PIPETX0ELECIDLE (delay_PIPETX0ELECIDLE),
.PIPETX0EQCONTROL (delay_PIPETX0EQCONTROL),
.PIPETX0EQDEEMPH (delay_PIPETX0EQDEEMPH),
.PIPETX0EQPRESET (delay_PIPETX0EQPRESET),
.PIPETX0POWERDOWN (delay_PIPETX0POWERDOWN),
.PIPETX0STARTBLOCK (delay_PIPETX0STARTBLOCK),
.PIPETX0SYNCHEADER (delay_PIPETX0SYNCHEADER),
.PIPETX1CHARISK (delay_PIPETX1CHARISK),
.PIPETX1COMPLIANCE (delay_PIPETX1COMPLIANCE),
.PIPETX1DATA (delay_PIPETX1DATA),
.PIPETX1DATAVALID (delay_PIPETX1DATAVALID),
.PIPETX1ELECIDLE (delay_PIPETX1ELECIDLE),
.PIPETX1EQCONTROL (delay_PIPETX1EQCONTROL),
.PIPETX1EQDEEMPH (delay_PIPETX1EQDEEMPH),
.PIPETX1EQPRESET (delay_PIPETX1EQPRESET),
.PIPETX1POWERDOWN (delay_PIPETX1POWERDOWN),
.PIPETX1STARTBLOCK (delay_PIPETX1STARTBLOCK),
.PIPETX1SYNCHEADER (delay_PIPETX1SYNCHEADER),
.PIPETX2CHARISK (delay_PIPETX2CHARISK),
.PIPETX2COMPLIANCE (delay_PIPETX2COMPLIANCE),
.PIPETX2DATA (delay_PIPETX2DATA),
.PIPETX2DATAVALID (delay_PIPETX2DATAVALID),
.PIPETX2ELECIDLE (delay_PIPETX2ELECIDLE),
.PIPETX2EQCONTROL (delay_PIPETX2EQCONTROL),
.PIPETX2EQDEEMPH (delay_PIPETX2EQDEEMPH),
.PIPETX2EQPRESET (delay_PIPETX2EQPRESET),
.PIPETX2POWERDOWN (delay_PIPETX2POWERDOWN),
.PIPETX2STARTBLOCK (delay_PIPETX2STARTBLOCK),
.PIPETX2SYNCHEADER (delay_PIPETX2SYNCHEADER),
.PIPETX3CHARISK (delay_PIPETX3CHARISK),
.PIPETX3COMPLIANCE (delay_PIPETX3COMPLIANCE),
.PIPETX3DATA (delay_PIPETX3DATA),
.PIPETX3DATAVALID (delay_PIPETX3DATAVALID),
.PIPETX3ELECIDLE (delay_PIPETX3ELECIDLE),
.PIPETX3EQCONTROL (delay_PIPETX3EQCONTROL),
.PIPETX3EQDEEMPH (delay_PIPETX3EQDEEMPH),
.PIPETX3EQPRESET (delay_PIPETX3EQPRESET),
.PIPETX3POWERDOWN (delay_PIPETX3POWERDOWN),
.PIPETX3STARTBLOCK (delay_PIPETX3STARTBLOCK),
.PIPETX3SYNCHEADER (delay_PIPETX3SYNCHEADER),
.PIPETX4CHARISK (delay_PIPETX4CHARISK),
.PIPETX4COMPLIANCE (delay_PIPETX4COMPLIANCE),
.PIPETX4DATA (delay_PIPETX4DATA),
.PIPETX4DATAVALID (delay_PIPETX4DATAVALID),
.PIPETX4ELECIDLE (delay_PIPETX4ELECIDLE),
.PIPETX4EQCONTROL (delay_PIPETX4EQCONTROL),
.PIPETX4EQDEEMPH (delay_PIPETX4EQDEEMPH),
.PIPETX4EQPRESET (delay_PIPETX4EQPRESET),
.PIPETX4POWERDOWN (delay_PIPETX4POWERDOWN),
.PIPETX4STARTBLOCK (delay_PIPETX4STARTBLOCK),
.PIPETX4SYNCHEADER (delay_PIPETX4SYNCHEADER),
.PIPETX5CHARISK (delay_PIPETX5CHARISK),
.PIPETX5COMPLIANCE (delay_PIPETX5COMPLIANCE),
.PIPETX5DATA (delay_PIPETX5DATA),
.PIPETX5DATAVALID (delay_PIPETX5DATAVALID),
.PIPETX5ELECIDLE (delay_PIPETX5ELECIDLE),
.PIPETX5EQCONTROL (delay_PIPETX5EQCONTROL),
.PIPETX5EQDEEMPH (delay_PIPETX5EQDEEMPH),
.PIPETX5EQPRESET (delay_PIPETX5EQPRESET),
.PIPETX5POWERDOWN (delay_PIPETX5POWERDOWN),
.PIPETX5STARTBLOCK (delay_PIPETX5STARTBLOCK),
.PIPETX5SYNCHEADER (delay_PIPETX5SYNCHEADER),
.PIPETX6CHARISK (delay_PIPETX6CHARISK),
.PIPETX6COMPLIANCE (delay_PIPETX6COMPLIANCE),
.PIPETX6DATA (delay_PIPETX6DATA),
.PIPETX6DATAVALID (delay_PIPETX6DATAVALID),
.PIPETX6ELECIDLE (delay_PIPETX6ELECIDLE),
.PIPETX6EQCONTROL (delay_PIPETX6EQCONTROL),
.PIPETX6EQDEEMPH (delay_PIPETX6EQDEEMPH),
.PIPETX6EQPRESET (delay_PIPETX6EQPRESET),
.PIPETX6POWERDOWN (delay_PIPETX6POWERDOWN),
.PIPETX6STARTBLOCK (delay_PIPETX6STARTBLOCK),
.PIPETX6SYNCHEADER (delay_PIPETX6SYNCHEADER),
.PIPETX7CHARISK (delay_PIPETX7CHARISK),
.PIPETX7COMPLIANCE (delay_PIPETX7COMPLIANCE),
.PIPETX7DATA (delay_PIPETX7DATA),
.PIPETX7DATAVALID (delay_PIPETX7DATAVALID),
.PIPETX7ELECIDLE (delay_PIPETX7ELECIDLE),
.PIPETX7EQCONTROL (delay_PIPETX7EQCONTROL),
.PIPETX7EQDEEMPH (delay_PIPETX7EQDEEMPH),
.PIPETX7EQPRESET (delay_PIPETX7EQPRESET),
.PIPETX7POWERDOWN (delay_PIPETX7POWERDOWN),
.PIPETX7STARTBLOCK (delay_PIPETX7STARTBLOCK),
.PIPETX7SYNCHEADER (delay_PIPETX7SYNCHEADER),
.PIPETXDEEMPH (delay_PIPETXDEEMPH),
.PIPETXMARGIN (delay_PIPETXMARGIN),
.PIPETXRATE (delay_PIPETXRATE),
.PIPETXRCVRDET (delay_PIPETXRCVRDET),
.PIPETXRESET (delay_PIPETXRESET),
.PIPETXSWING (delay_PIPETXSWING),
.PLEQINPROGRESS (delay_PLEQINPROGRESS),
.PLEQPHASE (delay_PLEQPHASE),
.PLGEN3PCSRXSLIDE (delay_PLGEN3PCSRXSLIDE),
.SAXISCCTREADY (delay_SAXISCCTREADY),
.SAXISRQTREADY (delay_SAXISRQTREADY),
.CFGCONFIGSPACEENABLE (delay_CFGCONFIGSPACEENABLE),
.CFGDEVID (delay_CFGDEVID),
.CFGDSBUSNUMBER (delay_CFGDSBUSNUMBER),
.CFGDSDEVICENUMBER (delay_CFGDSDEVICENUMBER),
.CFGDSFUNCTIONNUMBER (delay_CFGDSFUNCTIONNUMBER),
.CFGDSN (delay_CFGDSN),
.CFGDSPORTNUMBER (delay_CFGDSPORTNUMBER),
.CFGERRCORIN (delay_CFGERRCORIN),
.CFGERRUNCORIN (delay_CFGERRUNCORIN),
.CFGEXTREADDATA (delay_CFGEXTREADDATA),
.CFGEXTREADDATAVALID (delay_CFGEXTREADDATAVALID),
.CFGFCSEL (delay_CFGFCSEL),
.CFGFLRDONE (delay_CFGFLRDONE),
.CFGHOTRESETIN (delay_CFGHOTRESETIN),
.CFGINPUTUPDATEREQUEST (delay_CFGINPUTUPDATEREQUEST),
.CFGINTERRUPTINT (delay_CFGINTERRUPTINT),
.CFGINTERRUPTMSIATTR (delay_CFGINTERRUPTMSIATTR),
.CFGINTERRUPTMSIFUNCTIONNUMBER (delay_CFGINTERRUPTMSIFUNCTIONNUMBER),
.CFGINTERRUPTMSIINT (delay_CFGINTERRUPTMSIINT),
.CFGINTERRUPTMSIPENDINGSTATUS (delay_CFGINTERRUPTMSIPENDINGSTATUS),
.CFGINTERRUPTMSISELECT (delay_CFGINTERRUPTMSISELECT),
.CFGINTERRUPTMSITPHPRESENT (delay_CFGINTERRUPTMSITPHPRESENT),
.CFGINTERRUPTMSITPHSTTAG (delay_CFGINTERRUPTMSITPHSTTAG),
.CFGINTERRUPTMSITPHTYPE (delay_CFGINTERRUPTMSITPHTYPE),
.CFGINTERRUPTMSIXADDRESS (delay_CFGINTERRUPTMSIXADDRESS),
.CFGINTERRUPTMSIXDATA (delay_CFGINTERRUPTMSIXDATA),
.CFGINTERRUPTMSIXINT (delay_CFGINTERRUPTMSIXINT),
.CFGINTERRUPTPENDING (delay_CFGINTERRUPTPENDING),
.CFGLINKTRAININGENABLE (delay_CFGLINKTRAININGENABLE),
.CFGMCUPDATEREQUEST (delay_CFGMCUPDATEREQUEST),
.CFGMGMTADDR (delay_CFGMGMTADDR),
.CFGMGMTBYTEENABLE (delay_CFGMGMTBYTEENABLE),
.CFGMGMTREAD (delay_CFGMGMTREAD),
.CFGMGMTTYPE1CFGREGACCESS (delay_CFGMGMTTYPE1CFGREGACCESS),
.CFGMGMTWRITE (delay_CFGMGMTWRITE),
.CFGMGMTWRITEDATA (delay_CFGMGMTWRITEDATA),
.CFGMSGTRANSMIT (delay_CFGMSGTRANSMIT),
.CFGMSGTRANSMITDATA (delay_CFGMSGTRANSMITDATA),
.CFGMSGTRANSMITTYPE (delay_CFGMSGTRANSMITTYPE),
.CFGPERFUNCSTATUSCONTROL (delay_CFGPERFUNCSTATUSCONTROL),
.CFGPERFUNCTIONNUMBER (delay_CFGPERFUNCTIONNUMBER),
.CFGPERFUNCTIONOUTPUTREQUEST (delay_CFGPERFUNCTIONOUTPUTREQUEST),
.CFGPOWERSTATECHANGEACK (delay_CFGPOWERSTATECHANGEACK),
.CFGREQPMTRANSITIONL23READY (delay_CFGREQPMTRANSITIONL23READY),
.CFGREVID (delay_CFGREVID),
.CFGSUBSYSID (delay_CFGSUBSYSID),
.CFGSUBSYSVENDID (delay_CFGSUBSYSVENDID),
.CFGTPHSTTREADDATA (delay_CFGTPHSTTREADDATA),
.CFGTPHSTTREADDATAVALID (delay_CFGTPHSTTREADDATAVALID),
.CFGVENDID (delay_CFGVENDID),
.CFGVFFLRDONE (delay_CFGVFFLRDONE),
.CORECLK (delay_CORECLK),
.CORECLKMICOMPLETIONRAML (delay_CORECLKMICOMPLETIONRAML),
.CORECLKMICOMPLETIONRAMU (delay_CORECLKMICOMPLETIONRAMU),
.CORECLKMIREPLAYRAM (delay_CORECLKMIREPLAYRAM),
.CORECLKMIREQUESTRAM (delay_CORECLKMIREQUESTRAM),
.DRPADDR (delay_DRPADDR),
.DRPCLK (delay_DRPCLK),
.DRPDI (delay_DRPDI),
.DRPEN (delay_DRPEN),
.DRPWE (delay_DRPWE),
.MAXISCQTREADY (delay_MAXISCQTREADY),
.MAXISRCTREADY (delay_MAXISRCTREADY),
.MGMTRESETN (delay_MGMTRESETN),
.MGMTSTICKYRESETN (delay_MGMTSTICKYRESETN),
.MICOMPLETIONRAMREADDATA (delay_MICOMPLETIONRAMREADDATA),
.MIREPLAYRAMREADDATA (delay_MIREPLAYRAMREADDATA),
.MIREQUESTRAMREADDATA (delay_MIREQUESTRAMREADDATA),
.PCIECQNPREQ (delay_PCIECQNPREQ),
.PIPECLK (delay_PIPECLK),
.PIPEEQFS (delay_PIPEEQFS),
.PIPEEQLF (delay_PIPEEQLF),
.PIPERESETN (delay_PIPERESETN),
.PIPERX0CHARISK (delay_PIPERX0CHARISK),
.PIPERX0DATA (delay_PIPERX0DATA),
.PIPERX0DATAVALID (delay_PIPERX0DATAVALID),
.PIPERX0ELECIDLE (delay_PIPERX0ELECIDLE),
.PIPERX0EQDONE (delay_PIPERX0EQDONE),
.PIPERX0EQLPADAPTDONE (delay_PIPERX0EQLPADAPTDONE),
.PIPERX0EQLPLFFSSEL (delay_PIPERX0EQLPLFFSSEL),
.PIPERX0EQLPNEWTXCOEFFORPRESET (delay_PIPERX0EQLPNEWTXCOEFFORPRESET),
.PIPERX0PHYSTATUS (delay_PIPERX0PHYSTATUS),
.PIPERX0STARTBLOCK (delay_PIPERX0STARTBLOCK),
.PIPERX0STATUS (delay_PIPERX0STATUS),
.PIPERX0SYNCHEADER (delay_PIPERX0SYNCHEADER),
.PIPERX0VALID (delay_PIPERX0VALID),
.PIPERX1CHARISK (delay_PIPERX1CHARISK),
.PIPERX1DATA (delay_PIPERX1DATA),
.PIPERX1DATAVALID (delay_PIPERX1DATAVALID),
.PIPERX1ELECIDLE (delay_PIPERX1ELECIDLE),
.PIPERX1EQDONE (delay_PIPERX1EQDONE),
.PIPERX1EQLPADAPTDONE (delay_PIPERX1EQLPADAPTDONE),
.PIPERX1EQLPLFFSSEL (delay_PIPERX1EQLPLFFSSEL),
.PIPERX1EQLPNEWTXCOEFFORPRESET (delay_PIPERX1EQLPNEWTXCOEFFORPRESET),
.PIPERX1PHYSTATUS (delay_PIPERX1PHYSTATUS),
.PIPERX1STARTBLOCK (delay_PIPERX1STARTBLOCK),
.PIPERX1STATUS (delay_PIPERX1STATUS),
.PIPERX1SYNCHEADER (delay_PIPERX1SYNCHEADER),
.PIPERX1VALID (delay_PIPERX1VALID),
.PIPERX2CHARISK (delay_PIPERX2CHARISK),
.PIPERX2DATA (delay_PIPERX2DATA),
.PIPERX2DATAVALID (delay_PIPERX2DATAVALID),
.PIPERX2ELECIDLE (delay_PIPERX2ELECIDLE),
.PIPERX2EQDONE (delay_PIPERX2EQDONE),
.PIPERX2EQLPADAPTDONE (delay_PIPERX2EQLPADAPTDONE),
.PIPERX2EQLPLFFSSEL (delay_PIPERX2EQLPLFFSSEL),
.PIPERX2EQLPNEWTXCOEFFORPRESET (delay_PIPERX2EQLPNEWTXCOEFFORPRESET),
.PIPERX2PHYSTATUS (delay_PIPERX2PHYSTATUS),
.PIPERX2STARTBLOCK (delay_PIPERX2STARTBLOCK),
.PIPERX2STATUS (delay_PIPERX2STATUS),
.PIPERX2SYNCHEADER (delay_PIPERX2SYNCHEADER),
.PIPERX2VALID (delay_PIPERX2VALID),
.PIPERX3CHARISK (delay_PIPERX3CHARISK),
.PIPERX3DATA (delay_PIPERX3DATA),
.PIPERX3DATAVALID (delay_PIPERX3DATAVALID),
.PIPERX3ELECIDLE (delay_PIPERX3ELECIDLE),
.PIPERX3EQDONE (delay_PIPERX3EQDONE),
.PIPERX3EQLPADAPTDONE (delay_PIPERX3EQLPADAPTDONE),
.PIPERX3EQLPLFFSSEL (delay_PIPERX3EQLPLFFSSEL),
.PIPERX3EQLPNEWTXCOEFFORPRESET (delay_PIPERX3EQLPNEWTXCOEFFORPRESET),
.PIPERX3PHYSTATUS (delay_PIPERX3PHYSTATUS),
.PIPERX3STARTBLOCK (delay_PIPERX3STARTBLOCK),
.PIPERX3STATUS (delay_PIPERX3STATUS),
.PIPERX3SYNCHEADER (delay_PIPERX3SYNCHEADER),
.PIPERX3VALID (delay_PIPERX3VALID),
.PIPERX4CHARISK (delay_PIPERX4CHARISK),
.PIPERX4DATA (delay_PIPERX4DATA),
.PIPERX4DATAVALID (delay_PIPERX4DATAVALID),
.PIPERX4ELECIDLE (delay_PIPERX4ELECIDLE),
.PIPERX4EQDONE (delay_PIPERX4EQDONE),
.PIPERX4EQLPADAPTDONE (delay_PIPERX4EQLPADAPTDONE),
.PIPERX4EQLPLFFSSEL (delay_PIPERX4EQLPLFFSSEL),
.PIPERX4EQLPNEWTXCOEFFORPRESET (delay_PIPERX4EQLPNEWTXCOEFFORPRESET),
.PIPERX4PHYSTATUS (delay_PIPERX4PHYSTATUS),
.PIPERX4STARTBLOCK (delay_PIPERX4STARTBLOCK),
.PIPERX4STATUS (delay_PIPERX4STATUS),
.PIPERX4SYNCHEADER (delay_PIPERX4SYNCHEADER),
.PIPERX4VALID (delay_PIPERX4VALID),
.PIPERX5CHARISK (delay_PIPERX5CHARISK),
.PIPERX5DATA (delay_PIPERX5DATA),
.PIPERX5DATAVALID (delay_PIPERX5DATAVALID),
.PIPERX5ELECIDLE (delay_PIPERX5ELECIDLE),
.PIPERX5EQDONE (delay_PIPERX5EQDONE),
.PIPERX5EQLPADAPTDONE (delay_PIPERX5EQLPADAPTDONE),
.PIPERX5EQLPLFFSSEL (delay_PIPERX5EQLPLFFSSEL),
.PIPERX5EQLPNEWTXCOEFFORPRESET (delay_PIPERX5EQLPNEWTXCOEFFORPRESET),
.PIPERX5PHYSTATUS (delay_PIPERX5PHYSTATUS),
.PIPERX5STARTBLOCK (delay_PIPERX5STARTBLOCK),
.PIPERX5STATUS (delay_PIPERX5STATUS),
.PIPERX5SYNCHEADER (delay_PIPERX5SYNCHEADER),
.PIPERX5VALID (delay_PIPERX5VALID),
.PIPERX6CHARISK (delay_PIPERX6CHARISK),
.PIPERX6DATA (delay_PIPERX6DATA),
.PIPERX6DATAVALID (delay_PIPERX6DATAVALID),
.PIPERX6ELECIDLE (delay_PIPERX6ELECIDLE),
.PIPERX6EQDONE (delay_PIPERX6EQDONE),
.PIPERX6EQLPADAPTDONE (delay_PIPERX6EQLPADAPTDONE),
.PIPERX6EQLPLFFSSEL (delay_PIPERX6EQLPLFFSSEL),
.PIPERX6EQLPNEWTXCOEFFORPRESET (delay_PIPERX6EQLPNEWTXCOEFFORPRESET),
.PIPERX6PHYSTATUS (delay_PIPERX6PHYSTATUS),
.PIPERX6STARTBLOCK (delay_PIPERX6STARTBLOCK),
.PIPERX6STATUS (delay_PIPERX6STATUS),
.PIPERX6SYNCHEADER (delay_PIPERX6SYNCHEADER),
.PIPERX6VALID (delay_PIPERX6VALID),
.PIPERX7CHARISK (delay_PIPERX7CHARISK),
.PIPERX7DATA (delay_PIPERX7DATA),
.PIPERX7DATAVALID (delay_PIPERX7DATAVALID),
.PIPERX7ELECIDLE (delay_PIPERX7ELECIDLE),
.PIPERX7EQDONE (delay_PIPERX7EQDONE),
.PIPERX7EQLPADAPTDONE (delay_PIPERX7EQLPADAPTDONE),
.PIPERX7EQLPLFFSSEL (delay_PIPERX7EQLPLFFSSEL),
.PIPERX7EQLPNEWTXCOEFFORPRESET (delay_PIPERX7EQLPNEWTXCOEFFORPRESET),
.PIPERX7PHYSTATUS (delay_PIPERX7PHYSTATUS),
.PIPERX7STARTBLOCK (delay_PIPERX7STARTBLOCK),
.PIPERX7STATUS (delay_PIPERX7STATUS),
.PIPERX7SYNCHEADER (delay_PIPERX7SYNCHEADER),
.PIPERX7VALID (delay_PIPERX7VALID),
.PIPETX0EQCOEFF (delay_PIPETX0EQCOEFF),
.PIPETX0EQDONE (delay_PIPETX0EQDONE),
.PIPETX1EQCOEFF (delay_PIPETX1EQCOEFF),
.PIPETX1EQDONE (delay_PIPETX1EQDONE),
.PIPETX2EQCOEFF (delay_PIPETX2EQCOEFF),
.PIPETX2EQDONE (delay_PIPETX2EQDONE),
.PIPETX3EQCOEFF (delay_PIPETX3EQCOEFF),
.PIPETX3EQDONE (delay_PIPETX3EQDONE),
.PIPETX4EQCOEFF (delay_PIPETX4EQCOEFF),
.PIPETX4EQDONE (delay_PIPETX4EQDONE),
.PIPETX5EQCOEFF (delay_PIPETX5EQCOEFF),
.PIPETX5EQDONE (delay_PIPETX5EQDONE),
.PIPETX6EQCOEFF (delay_PIPETX6EQCOEFF),
.PIPETX6EQDONE (delay_PIPETX6EQDONE),
.PIPETX7EQCOEFF (delay_PIPETX7EQCOEFF),
.PIPETX7EQDONE (delay_PIPETX7EQDONE),
.PLDISABLESCRAMBLER (delay_PLDISABLESCRAMBLER),
.PLEQRESETEIEOSCOUNT (delay_PLEQRESETEIEOSCOUNT),
.PLGEN3PCSDISABLE (delay_PLGEN3PCSDISABLE),
.PLGEN3PCSRXSYNCDONE (delay_PLGEN3PCSRXSYNCDONE),
.RECCLK (delay_RECCLK),
.RESETN (delay_RESETN),
.SAXISCCTDATA (delay_SAXISCCTDATA),
.SAXISCCTKEEP (delay_SAXISCCTKEEP),
.SAXISCCTLAST (delay_SAXISCCTLAST),
.SAXISCCTUSER (delay_SAXISCCTUSER),
.SAXISCCTVALID (delay_SAXISCCTVALID),
.SAXISRQTDATA (delay_SAXISRQTDATA),
.SAXISRQTKEEP (delay_SAXISRQTKEEP),
.SAXISRQTLAST (delay_SAXISRQTLAST),
.SAXISRQTUSER (delay_SAXISRQTUSER),
.SAXISRQTVALID (delay_SAXISRQTVALID),
.USERCLK (delay_USERCLK)
);
specify
`ifdef XIL_TIMING // Simprim
$period (posedge CORECLK, 0:0:0, notifier);
$period (posedge CORECLKMICOMPLETIONRAML, 0:0:0, notifier);
$period (posedge CORECLKMICOMPLETIONRAMU, 0:0:0, notifier);
$period (posedge CORECLKMIREPLAYRAM, 0:0:0, notifier);
$period (posedge CORECLKMIREQUESTRAM, 0:0:0, notifier);
$period (posedge DRPCLK, 0:0:0, notifier);
$period (posedge PIPECLK, 0:0:0, notifier);
$period (posedge RECCLK, 0:0:0, notifier);
$period (posedge USERCLK, 0:0:0, notifier);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]);
$setuphold (posedge CORECLK, negedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MICOMPLETIONRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MICOMPLETIONRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MIREPLAYRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREPLAYRAMREADDATA[9]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[0]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[100], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[100]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[101], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[101]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[102], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[102]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[103], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[103]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[104], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[104]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[105], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[105]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[106], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[106]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[107], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[107]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[108], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[108]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[109], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[109]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[10]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[110], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[110]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[111], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[111]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[112], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[112]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[113], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[113]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[114], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[114]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[115], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[115]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[116], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[116]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[117], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[117]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[118], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[118]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[119], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[119]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[11]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[120], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[120]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[121], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[121]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[122], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[122]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[123], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[123]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[124], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[124]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[125], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[125]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[126], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[126]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[127], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[127]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[128], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[128]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[129], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[129]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[12]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[130], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[130]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[131], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[131]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[132], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[132]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[133], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[133]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[134], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[134]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[135], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[135]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[136], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[136]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[137], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[137]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[138], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[138]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[139], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[139]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[13]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[140], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[140]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[141], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[141]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[142], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[142]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[143], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[143]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[14]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[15]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[16]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[17]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[18]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[19]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[1]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[20]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[21]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[22]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[23]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[24]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[25]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[26]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[27]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[28]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[29]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[2]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[30]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[31]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[32], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[32]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[33], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[33]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[34], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[34]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[35], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[35]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[36], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[36]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[37], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[37]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[38], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[38]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[39], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[39]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[3]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[40], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[40]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[41], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[41]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[42], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[42]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[43], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[43]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[44], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[44]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[45], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[45]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[46], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[46]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[47], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[47]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[48], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[48]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[49], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[49]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[4]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[50], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[50]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[51], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[51]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[52], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[52]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[53], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[53]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[54], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[54]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[55], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[55]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[56], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[56]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[57], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[57]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[58], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[58]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[59], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[59]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[5]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[60], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[60]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[61], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[61]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[62], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[62]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[63], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[63]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[64], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[64]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[65], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[65]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[66], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[66]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[67], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[67]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[68], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[68]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[69], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[69]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[6]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[70], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[70]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[71], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[71]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[72], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[72]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[73], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[73]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[74], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[74]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[75], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[75]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[76], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[76]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[77], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[77]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[78], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[78]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[79], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[79]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[7]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[80], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[80]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[81], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[81]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[82], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[82]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[83], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[83]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[84], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[84]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[85], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[85]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[86], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[86]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[87], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[87]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[88], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[88]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[89], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[89]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[8]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[90], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[90]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[91], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[91]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[92], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[92]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[93], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[93]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[94], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[94]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[95], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[95]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[96], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[96]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[97], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[97]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[98], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[98]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[99], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[99]);
$setuphold (posedge CORECLK, posedge MIREQUESTRAMREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_CORECLK, delay_MIREQUESTRAMREADDATA[9]);
$setuphold (posedge DRPCLK, negedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, negedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]);
$setuphold (posedge DRPCLK, negedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, negedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, negedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, negedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, negedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, negedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, negedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, negedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, negedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]);
$setuphold (posedge DRPCLK, negedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, negedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, negedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, negedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, negedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, negedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, negedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, negedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, negedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, negedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, negedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, negedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, negedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, negedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, negedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, negedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, negedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, negedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge DRPCLK, posedge DRPADDR[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[0]);
$setuphold (posedge DRPCLK, posedge DRPADDR[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[10]);
$setuphold (posedge DRPCLK, posedge DRPADDR[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[1]);
$setuphold (posedge DRPCLK, posedge DRPADDR[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[2]);
$setuphold (posedge DRPCLK, posedge DRPADDR[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[3]);
$setuphold (posedge DRPCLK, posedge DRPADDR[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[4]);
$setuphold (posedge DRPCLK, posedge DRPADDR[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[5]);
$setuphold (posedge DRPCLK, posedge DRPADDR[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[6]);
$setuphold (posedge DRPCLK, posedge DRPADDR[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[7]);
$setuphold (posedge DRPCLK, posedge DRPADDR[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[8]);
$setuphold (posedge DRPCLK, posedge DRPADDR[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPADDR[9]);
$setuphold (posedge DRPCLK, posedge DRPDI[0], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[0]);
$setuphold (posedge DRPCLK, posedge DRPDI[10], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[10]);
$setuphold (posedge DRPCLK, posedge DRPDI[11], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[11]);
$setuphold (posedge DRPCLK, posedge DRPDI[12], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[12]);
$setuphold (posedge DRPCLK, posedge DRPDI[13], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[13]);
$setuphold (posedge DRPCLK, posedge DRPDI[14], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[14]);
$setuphold (posedge DRPCLK, posedge DRPDI[15], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[15]);
$setuphold (posedge DRPCLK, posedge DRPDI[1], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[1]);
$setuphold (posedge DRPCLK, posedge DRPDI[2], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[2]);
$setuphold (posedge DRPCLK, posedge DRPDI[3], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[3]);
$setuphold (posedge DRPCLK, posedge DRPDI[4], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[4]);
$setuphold (posedge DRPCLK, posedge DRPDI[5], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[5]);
$setuphold (posedge DRPCLK, posedge DRPDI[6], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[6]);
$setuphold (posedge DRPCLK, posedge DRPDI[7], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[7]);
$setuphold (posedge DRPCLK, posedge DRPDI[8], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[8]);
$setuphold (posedge DRPCLK, posedge DRPDI[9], 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPDI[9]);
$setuphold (posedge DRPCLK, posedge DRPEN, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPEN);
$setuphold (posedge DRPCLK, posedge DRPWE, 0:0:0, 0:0:0, notifier,,, delay_DRPCLK, delay_DRPWE);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]);
$setuphold (posedge PIPECLK, negedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, negedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]);
$setuphold (posedge PIPECLK, negedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE);
$setuphold (posedge PIPECLK, negedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER);
$setuphold (posedge PIPECLK, negedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT);
$setuphold (posedge PIPECLK, negedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQFS[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQFS[5]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[0]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[1]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[2]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[3]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[4]);
$setuphold (posedge PIPECLK, posedge PIPEEQLF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPEEQLF[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX0EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX0EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX1EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX1EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX2EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX2EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX3EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX3EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX4EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX4EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX5EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX5EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX6EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX6EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQDONE);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPADAPTDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPADAPTDONE);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPLFFSSEL, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPLFFSSEL);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[0]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[10]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[11]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[12]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[13]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[14]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[15]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[16]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[17]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[1]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[2]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[3]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[4]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[5]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[6]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[7]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[8]);
$setuphold (posedge PIPECLK, posedge PIPERX7EQLPNEWTXCOEFFORPRESET[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPERX7EQLPNEWTXCOEFFORPRESET[9]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX0EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX0EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX1EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX1EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX2EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX2EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX3EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX3EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX4EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX4EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX5EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX5EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX6EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX6EQDONE);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[0], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[0]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[10], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[10]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[11], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[11]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[12], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[12]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[13], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[13]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[14], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[14]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[15], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[15]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[16], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[16]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[17], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[17]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[1], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[1]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[2], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[2]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[3], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[3]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[4], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[4]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[5], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[5]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[6], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[6]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[7], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[7]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[8], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[8]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQCOEFF[9], 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQCOEFF[9]);
$setuphold (posedge PIPECLK, posedge PIPETX7EQDONE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PIPETX7EQDONE);
$setuphold (posedge PIPECLK, posedge PLDISABLESCRAMBLER, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLDISABLESCRAMBLER);
$setuphold (posedge PIPECLK, posedge PLEQRESETEIEOSCOUNT, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLEQRESETEIEOSCOUNT);
$setuphold (posedge PIPECLK, posedge PLGEN3PCSDISABLE, 0:0:0, 0:0:0, notifier,,, delay_PIPECLK, delay_PLGEN3PCSDISABLE);
$setuphold (posedge RECCLK, negedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID);
$setuphold (posedge RECCLK, negedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID);
$setuphold (posedge RECCLK, negedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID);
$setuphold (posedge RECCLK, negedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID);
$setuphold (posedge RECCLK, negedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID);
$setuphold (posedge RECCLK, negedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID);
$setuphold (posedge RECCLK, negedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID);
$setuphold (posedge RECCLK, negedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge RECCLK, negedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge RECCLK, negedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]);
$setuphold (posedge RECCLK, negedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]);
$setuphold (posedge RECCLK, negedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge RECCLK, negedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge RECCLK, negedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge RECCLK, negedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]);
$setuphold (posedge RECCLK, negedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]);
$setuphold (posedge RECCLK, negedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]);
$setuphold (posedge RECCLK, negedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]);
$setuphold (posedge RECCLK, posedge PIPERX0CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX0CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX0DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX0DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX0ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX0PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX0STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX0STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX0SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX0VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX0VALID);
$setuphold (posedge RECCLK, posedge PIPERX1CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX1CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX1DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX1DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX1ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX1PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX1STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX1STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX1SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX1VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX1VALID);
$setuphold (posedge RECCLK, posedge PIPERX2CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX2CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX2DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX2DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX2ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX2PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX2STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX2STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX2SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX2VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX2VALID);
$setuphold (posedge RECCLK, posedge PIPERX3CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX3CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX3DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX3DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX3ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX3PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX3STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX3STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX3SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX3VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX3VALID);
$setuphold (posedge RECCLK, posedge PIPERX4CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX4CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX4DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX4DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX4ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX4PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX4STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX4STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX4SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX4VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX4VALID);
$setuphold (posedge RECCLK, posedge PIPERX5CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX5CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX5DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX5DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX5ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX5PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX5STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX5STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX5SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX5VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX5VALID);
$setuphold (posedge RECCLK, posedge PIPERX6CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX6CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX6DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX6DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX6ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX6PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX6STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX6STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX6SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX6VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX6VALID);
$setuphold (posedge RECCLK, posedge PIPERX7CHARISK[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[0]);
$setuphold (posedge RECCLK, posedge PIPERX7CHARISK[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7CHARISK[1]);
$setuphold (posedge RECCLK, posedge PIPERX7DATAVALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATAVALID);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[0]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[10], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[10]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[11], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[11]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[12], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[12]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[13], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[13]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[14], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[14]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[15], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[15]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[16], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[16]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[17], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[17]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[18], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[18]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[19], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[19]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[1]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[20], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[20]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[21], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[21]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[22], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[22]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[23], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[23]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[24], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[24]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[25], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[25]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[26], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[26]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[27], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[27]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[28], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[28]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[29], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[29]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[2]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[30], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[30]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[31], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[31]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[3]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[4]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[5]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[6]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[7]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[8], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[8]);
$setuphold (posedge RECCLK, posedge PIPERX7DATA[9], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7DATA[9]);
$setuphold (posedge RECCLK, posedge PIPERX7ELECIDLE, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7ELECIDLE);
$setuphold (posedge RECCLK, posedge PIPERX7PHYSTATUS, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7PHYSTATUS);
$setuphold (posedge RECCLK, posedge PIPERX7STARTBLOCK, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STARTBLOCK);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[0]);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[1]);
$setuphold (posedge RECCLK, posedge PIPERX7STATUS[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7STATUS[2]);
$setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[0]);
$setuphold (posedge RECCLK, posedge PIPERX7SYNCHEADER[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7SYNCHEADER[1]);
$setuphold (posedge RECCLK, posedge PIPERX7VALID, 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PIPERX7VALID);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[0], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[0]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[1], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[1]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[2], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[2]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[3], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[3]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[4], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[4]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[5], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[5]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[6], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[6]);
$setuphold (posedge RECCLK, posedge PLGEN3PCSRXSYNCDONE[7], 0:0:0, 0:0:0, notifier,,, delay_RECCLK, delay_PLGEN3PCSRXSYNCDONE[7]);
$setuphold (posedge USERCLK, negedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE);
$setuphold (posedge USERCLK, negedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK, negedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK, negedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK, negedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK, negedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK, negedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK, negedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK, negedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK, negedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK, negedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK, negedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK, negedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK, negedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK, negedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK, negedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK, negedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK, negedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]);
$setuphold (posedge USERCLK, negedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]);
$setuphold (posedge USERCLK, negedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]);
$setuphold (posedge USERCLK, negedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]);
$setuphold (posedge USERCLK, negedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]);
$setuphold (posedge USERCLK, negedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]);
$setuphold (posedge USERCLK, negedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]);
$setuphold (posedge USERCLK, negedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]);
$setuphold (posedge USERCLK, negedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]);
$setuphold (posedge USERCLK, negedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]);
$setuphold (posedge USERCLK, negedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]);
$setuphold (posedge USERCLK, negedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]);
$setuphold (posedge USERCLK, negedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]);
$setuphold (posedge USERCLK, negedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]);
$setuphold (posedge USERCLK, negedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]);
$setuphold (posedge USERCLK, negedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]);
$setuphold (posedge USERCLK, negedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]);
$setuphold (posedge USERCLK, negedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]);
$setuphold (posedge USERCLK, negedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]);
$setuphold (posedge USERCLK, negedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]);
$setuphold (posedge USERCLK, negedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]);
$setuphold (posedge USERCLK, negedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]);
$setuphold (posedge USERCLK, negedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]);
$setuphold (posedge USERCLK, negedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]);
$setuphold (posedge USERCLK, negedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]);
$setuphold (posedge USERCLK, negedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]);
$setuphold (posedge USERCLK, negedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]);
$setuphold (posedge USERCLK, negedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]);
$setuphold (posedge USERCLK, negedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]);
$setuphold (posedge USERCLK, negedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]);
$setuphold (posedge USERCLK, negedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]);
$setuphold (posedge USERCLK, negedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]);
$setuphold (posedge USERCLK, negedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]);
$setuphold (posedge USERCLK, negedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]);
$setuphold (posedge USERCLK, negedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]);
$setuphold (posedge USERCLK, negedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]);
$setuphold (posedge USERCLK, negedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]);
$setuphold (posedge USERCLK, negedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]);
$setuphold (posedge USERCLK, negedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]);
$setuphold (posedge USERCLK, negedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]);
$setuphold (posedge USERCLK, negedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]);
$setuphold (posedge USERCLK, negedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]);
$setuphold (posedge USERCLK, negedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]);
$setuphold (posedge USERCLK, negedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]);
$setuphold (posedge USERCLK, negedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]);
$setuphold (posedge USERCLK, negedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]);
$setuphold (posedge USERCLK, negedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]);
$setuphold (posedge USERCLK, negedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]);
$setuphold (posedge USERCLK, negedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]);
$setuphold (posedge USERCLK, negedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]);
$setuphold (posedge USERCLK, negedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]);
$setuphold (posedge USERCLK, negedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]);
$setuphold (posedge USERCLK, negedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]);
$setuphold (posedge USERCLK, negedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]);
$setuphold (posedge USERCLK, negedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]);
$setuphold (posedge USERCLK, negedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]);
$setuphold (posedge USERCLK, negedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]);
$setuphold (posedge USERCLK, negedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]);
$setuphold (posedge USERCLK, negedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]);
$setuphold (posedge USERCLK, negedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]);
$setuphold (posedge USERCLK, negedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]);
$setuphold (posedge USERCLK, negedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]);
$setuphold (posedge USERCLK, negedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]);
$setuphold (posedge USERCLK, negedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]);
$setuphold (posedge USERCLK, negedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]);
$setuphold (posedge USERCLK, negedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN);
$setuphold (posedge USERCLK, negedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]);
$setuphold (posedge USERCLK, negedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]);
$setuphold (posedge USERCLK, negedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]);
$setuphold (posedge USERCLK, negedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]);
$setuphold (posedge USERCLK, negedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN);
$setuphold (posedge USERCLK, negedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]);
$setuphold (posedge USERCLK, negedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]);
$setuphold (posedge USERCLK, negedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE);
$setuphold (posedge USERCLK, negedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD);
$setuphold (posedge USERCLK, negedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]);
$setuphold (posedge USERCLK, negedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]);
$setuphold (posedge USERCLK, negedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, negedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST);
$setuphold (posedge USERCLK, negedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK);
$setuphold (posedge USERCLK, negedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY);
$setuphold (posedge USERCLK, negedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]);
$setuphold (posedge USERCLK, negedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]);
$setuphold (posedge USERCLK, negedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]);
$setuphold (posedge USERCLK, negedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]);
$setuphold (posedge USERCLK, negedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]);
$setuphold (posedge USERCLK, negedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]);
$setuphold (posedge USERCLK, negedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]);
$setuphold (posedge USERCLK, negedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK, negedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]);
$setuphold (posedge USERCLK, negedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]);
$setuphold (posedge USERCLK, negedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK, negedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK, negedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK, negedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK, negedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK, negedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK, negedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK, negedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK, negedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK, negedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK, negedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK, negedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK, negedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK, negedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK, negedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK, negedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]);
$setuphold (posedge USERCLK, negedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]);
$setuphold (posedge USERCLK, negedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]);
$setuphold (posedge USERCLK, negedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]);
$setuphold (posedge USERCLK, negedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]);
$setuphold (posedge USERCLK, negedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]);
$setuphold (posedge USERCLK, negedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]);
$setuphold (posedge USERCLK, negedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]);
$setuphold (posedge USERCLK, negedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]);
$setuphold (posedge USERCLK, negedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]);
$setuphold (posedge USERCLK, negedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID);
$setuphold (posedge USERCLK, posedge CFGCONFIGSPACEENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGCONFIGSPACEENABLE);
$setuphold (posedge USERCLK, posedge CFGDEVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[0]);
$setuphold (posedge USERCLK, posedge CFGDEVID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[10]);
$setuphold (posedge USERCLK, posedge CFGDEVID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[11]);
$setuphold (posedge USERCLK, posedge CFGDEVID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[12]);
$setuphold (posedge USERCLK, posedge CFGDEVID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[13]);
$setuphold (posedge USERCLK, posedge CFGDEVID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[14]);
$setuphold (posedge USERCLK, posedge CFGDEVID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[15]);
$setuphold (posedge USERCLK, posedge CFGDEVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[1]);
$setuphold (posedge USERCLK, posedge CFGDEVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[2]);
$setuphold (posedge USERCLK, posedge CFGDEVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[3]);
$setuphold (posedge USERCLK, posedge CFGDEVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[4]);
$setuphold (posedge USERCLK, posedge CFGDEVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[5]);
$setuphold (posedge USERCLK, posedge CFGDEVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[6]);
$setuphold (posedge USERCLK, posedge CFGDEVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[7]);
$setuphold (posedge USERCLK, posedge CFGDEVID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[8]);
$setuphold (posedge USERCLK, posedge CFGDEVID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDEVID[9]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[5]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[6]);
$setuphold (posedge USERCLK, posedge CFGDSBUSNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSBUSNUMBER[7]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSDEVICENUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSDEVICENUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[0]);
$setuphold (posedge USERCLK, posedge CFGDSN[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[10]);
$setuphold (posedge USERCLK, posedge CFGDSN[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[11]);
$setuphold (posedge USERCLK, posedge CFGDSN[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[12]);
$setuphold (posedge USERCLK, posedge CFGDSN[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[13]);
$setuphold (posedge USERCLK, posedge CFGDSN[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[14]);
$setuphold (posedge USERCLK, posedge CFGDSN[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[15]);
$setuphold (posedge USERCLK, posedge CFGDSN[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[16]);
$setuphold (posedge USERCLK, posedge CFGDSN[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[17]);
$setuphold (posedge USERCLK, posedge CFGDSN[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[18]);
$setuphold (posedge USERCLK, posedge CFGDSN[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[19]);
$setuphold (posedge USERCLK, posedge CFGDSN[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[1]);
$setuphold (posedge USERCLK, posedge CFGDSN[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[20]);
$setuphold (posedge USERCLK, posedge CFGDSN[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[21]);
$setuphold (posedge USERCLK, posedge CFGDSN[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[22]);
$setuphold (posedge USERCLK, posedge CFGDSN[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[23]);
$setuphold (posedge USERCLK, posedge CFGDSN[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[24]);
$setuphold (posedge USERCLK, posedge CFGDSN[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[25]);
$setuphold (posedge USERCLK, posedge CFGDSN[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[26]);
$setuphold (posedge USERCLK, posedge CFGDSN[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[27]);
$setuphold (posedge USERCLK, posedge CFGDSN[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[28]);
$setuphold (posedge USERCLK, posedge CFGDSN[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[29]);
$setuphold (posedge USERCLK, posedge CFGDSN[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[2]);
$setuphold (posedge USERCLK, posedge CFGDSN[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[30]);
$setuphold (posedge USERCLK, posedge CFGDSN[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[31]);
$setuphold (posedge USERCLK, posedge CFGDSN[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[32]);
$setuphold (posedge USERCLK, posedge CFGDSN[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[33]);
$setuphold (posedge USERCLK, posedge CFGDSN[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[34]);
$setuphold (posedge USERCLK, posedge CFGDSN[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[35]);
$setuphold (posedge USERCLK, posedge CFGDSN[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[36]);
$setuphold (posedge USERCLK, posedge CFGDSN[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[37]);
$setuphold (posedge USERCLK, posedge CFGDSN[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[38]);
$setuphold (posedge USERCLK, posedge CFGDSN[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[39]);
$setuphold (posedge USERCLK, posedge CFGDSN[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[3]);
$setuphold (posedge USERCLK, posedge CFGDSN[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[40]);
$setuphold (posedge USERCLK, posedge CFGDSN[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[41]);
$setuphold (posedge USERCLK, posedge CFGDSN[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[42]);
$setuphold (posedge USERCLK, posedge CFGDSN[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[43]);
$setuphold (posedge USERCLK, posedge CFGDSN[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[44]);
$setuphold (posedge USERCLK, posedge CFGDSN[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[45]);
$setuphold (posedge USERCLK, posedge CFGDSN[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[46]);
$setuphold (posedge USERCLK, posedge CFGDSN[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[47]);
$setuphold (posedge USERCLK, posedge CFGDSN[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[48]);
$setuphold (posedge USERCLK, posedge CFGDSN[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[49]);
$setuphold (posedge USERCLK, posedge CFGDSN[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[4]);
$setuphold (posedge USERCLK, posedge CFGDSN[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[50]);
$setuphold (posedge USERCLK, posedge CFGDSN[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[51]);
$setuphold (posedge USERCLK, posedge CFGDSN[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[52]);
$setuphold (posedge USERCLK, posedge CFGDSN[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[53]);
$setuphold (posedge USERCLK, posedge CFGDSN[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[54]);
$setuphold (posedge USERCLK, posedge CFGDSN[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[55]);
$setuphold (posedge USERCLK, posedge CFGDSN[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[56]);
$setuphold (posedge USERCLK, posedge CFGDSN[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[57]);
$setuphold (posedge USERCLK, posedge CFGDSN[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[58]);
$setuphold (posedge USERCLK, posedge CFGDSN[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[59]);
$setuphold (posedge USERCLK, posedge CFGDSN[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[5]);
$setuphold (posedge USERCLK, posedge CFGDSN[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[60]);
$setuphold (posedge USERCLK, posedge CFGDSN[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[61]);
$setuphold (posedge USERCLK, posedge CFGDSN[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[62]);
$setuphold (posedge USERCLK, posedge CFGDSN[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[63]);
$setuphold (posedge USERCLK, posedge CFGDSN[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[6]);
$setuphold (posedge USERCLK, posedge CFGDSN[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[7]);
$setuphold (posedge USERCLK, posedge CFGDSN[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[8]);
$setuphold (posedge USERCLK, posedge CFGDSN[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSN[9]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[3]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[4]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[5]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[6]);
$setuphold (posedge USERCLK, posedge CFGDSPORTNUMBER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGDSPORTNUMBER[7]);
$setuphold (posedge USERCLK, posedge CFGERRCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRCORIN);
$setuphold (posedge USERCLK, posedge CFGERRUNCORIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGERRUNCORIN);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATAVALID);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[0]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[10]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[11]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[12]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[13]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[14]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[15]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[16]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[17]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[18]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[19]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[1]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[20]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[21]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[22]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[23]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[24]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[25]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[26]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[27]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[28]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[29]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[2]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[30]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[31]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[3]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[4]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[5]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[6]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[7]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[8]);
$setuphold (posedge USERCLK, posedge CFGEXTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGEXTREADDATA[9]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[0]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[1]);
$setuphold (posedge USERCLK, posedge CFGFCSEL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFCSEL[2]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[0]);
$setuphold (posedge USERCLK, posedge CFGFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGFLRDONE[1]);
$setuphold (posedge USERCLK, posedge CFGHOTRESETIN, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGHOTRESETIN);
$setuphold (posedge USERCLK, posedge CFGINPUTUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINPUTUPDATEREQUEST);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTINT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIATTR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIATTR[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIINT[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIINT[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[32]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[33]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[34]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[35]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[36]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[37]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[38]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[39]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[40]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[41]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[42]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[43]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[44]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[45]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[46]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[47]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[48]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[49]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[50]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[51]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[52]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[53]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[54]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[55]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[56]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[57]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[58]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[59]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[60]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[61]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[62]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[63]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIPENDINGSTATUS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIPENDINGSTATUS[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSISELECT[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSISELECT[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHPRESENT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHPRESENT);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHSTTAG[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHSTTAG[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSITPHTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSITPHTYPE[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[32]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[33]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[34]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[35]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[36]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[37]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[38]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[39]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[40]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[41]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[42]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[43]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[44]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[45]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[46]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[47]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[48]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[49]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[50]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[51]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[52]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[53]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[54]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[55]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[56]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[57]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[58]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[59]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[60]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[61]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[62]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[63]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXADDRESS[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXADDRESS[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[10]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[11]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[12]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[13]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[14]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[15]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[16]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[17]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[18]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[19]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[1]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[20]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[21]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[22]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[23]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[24]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[25]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[26]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[27]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[28]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[29]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[2]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[30]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[31]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[3]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[4]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[5]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[6]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[7]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[8]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXDATA[9]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTMSIXINT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTMSIXINT);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[0]);
$setuphold (posedge USERCLK, posedge CFGINTERRUPTPENDING[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGINTERRUPTPENDING[1]);
$setuphold (posedge USERCLK, posedge CFGLINKTRAININGENABLE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGLINKTRAININGENABLE);
$setuphold (posedge USERCLK, posedge CFGMCUPDATEREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMCUPDATEREQUEST);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTADDR[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTADDR[9]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTBYTEENABLE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTBYTEENABLE[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTREAD, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTREAD);
$setuphold (posedge USERCLK, posedge CFGMGMTTYPE1CFGREGACCESS, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTTYPE1CFGREGACCESS);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITE, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITE);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[0]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[10]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[11]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[12]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[13]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[14]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[15]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[16]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[17]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[18]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[19]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[1]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[20]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[21]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[22]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[23]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[24]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[25]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[26]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[27]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[28]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[29]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[2]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[30]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[31]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[3]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[4]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[5]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[6]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[7]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[8]);
$setuphold (posedge USERCLK, posedge CFGMGMTWRITEDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMGMTWRITEDATA[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMIT, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMIT);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[10]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[11]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[12]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[13]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[14]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[15]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[16]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[17]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[18]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[19]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[20]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[21]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[22]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[23]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[24]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[25]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[26]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[27]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[28]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[29]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[2]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[30]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[31]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[3]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[4]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[5]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[6]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[7]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[8]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITDATA[9]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[0]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[1]);
$setuphold (posedge USERCLK, posedge CFGMSGTRANSMITTYPE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGMSGTRANSMITTYPE[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCSTATUSCONTROL[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCSTATUSCONTROL[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[0]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[1]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONNUMBER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONNUMBER[2]);
$setuphold (posedge USERCLK, posedge CFGPERFUNCTIONOUTPUTREQUEST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPERFUNCTIONOUTPUTREQUEST);
$setuphold (posedge USERCLK, posedge CFGPOWERSTATECHANGEACK, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGPOWERSTATECHANGEACK);
$setuphold (posedge USERCLK, posedge CFGREQPMTRANSITIONL23READY, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREQPMTRANSITIONL23READY);
$setuphold (posedge USERCLK, posedge CFGREVID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[0]);
$setuphold (posedge USERCLK, posedge CFGREVID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[1]);
$setuphold (posedge USERCLK, posedge CFGREVID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[2]);
$setuphold (posedge USERCLK, posedge CFGREVID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[3]);
$setuphold (posedge USERCLK, posedge CFGREVID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[4]);
$setuphold (posedge USERCLK, posedge CFGREVID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[5]);
$setuphold (posedge USERCLK, posedge CFGREVID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[6]);
$setuphold (posedge USERCLK, posedge CFGREVID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGREVID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSID[9]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[0]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[10]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[11]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[12]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[13]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[14]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[15]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[1]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[2]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[3]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[4]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[5]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[6]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[7]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[8]);
$setuphold (posedge USERCLK, posedge CFGSUBSYSVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGSUBSYSVENDID[9]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATAVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATAVALID);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[0]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[10]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[11]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[12]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[13]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[14]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[15]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[16]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[17]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[18]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[19]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[1]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[20]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[21]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[22]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[23]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[24]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[25]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[26]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[27]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[28]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[29]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[2]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[30]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[31]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[3]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[4]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[5]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[6]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[7]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[8]);
$setuphold (posedge USERCLK, posedge CFGTPHSTTREADDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGTPHSTTREADDATA[9]);
$setuphold (posedge USERCLK, posedge CFGVENDID[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[0]);
$setuphold (posedge USERCLK, posedge CFGVENDID[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[10]);
$setuphold (posedge USERCLK, posedge CFGVENDID[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[11]);
$setuphold (posedge USERCLK, posedge CFGVENDID[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[12]);
$setuphold (posedge USERCLK, posedge CFGVENDID[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[13]);
$setuphold (posedge USERCLK, posedge CFGVENDID[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[14]);
$setuphold (posedge USERCLK, posedge CFGVENDID[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[15]);
$setuphold (posedge USERCLK, posedge CFGVENDID[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[1]);
$setuphold (posedge USERCLK, posedge CFGVENDID[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[2]);
$setuphold (posedge USERCLK, posedge CFGVENDID[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[3]);
$setuphold (posedge USERCLK, posedge CFGVENDID[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[4]);
$setuphold (posedge USERCLK, posedge CFGVENDID[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[5]);
$setuphold (posedge USERCLK, posedge CFGVENDID[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[6]);
$setuphold (posedge USERCLK, posedge CFGVENDID[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[7]);
$setuphold (posedge USERCLK, posedge CFGVENDID[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[8]);
$setuphold (posedge USERCLK, posedge CFGVENDID[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVENDID[9]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[0]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[1]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[2]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[3]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[4]);
$setuphold (posedge USERCLK, posedge CFGVFFLRDONE[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_CFGVFFLRDONE[5]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[0]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[10]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[11]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[12]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[13]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[14]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[15]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[16]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[17]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[18]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[19]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[1]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[20]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[21]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[2]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[3]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[4]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[5]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[6]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[7]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[8]);
$setuphold (posedge USERCLK, posedge MAXISCQTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISCQTREADY[9]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[0]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[10]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[11]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[12]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[13]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[14]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[15]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[16]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[17]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[18]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[19]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[1]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[20]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[21]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[2]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[3]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[4]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[5]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[6]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[7]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[8]);
$setuphold (posedge USERCLK, posedge MAXISRCTREADY[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_MAXISRCTREADY[9]);
$setuphold (posedge USERCLK, posedge PCIECQNPREQ, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_PCIECQNPREQ);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[100]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[101]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[102]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[103]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[104]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[105]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[106]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[107]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[108]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[109]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[110]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[111]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[112]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[113]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[114]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[115]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[116]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[117]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[118]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[119]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[120]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[121]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[122]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[123]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[124]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[125]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[126]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[127]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[128]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[129]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[130]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[131]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[132]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[133]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[134]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[135]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[136]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[137]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[138]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[139]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[140]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[141]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[142]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[143]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[144]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[145]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[146]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[147]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[148]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[149]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[150]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[151]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[152]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[153]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[154]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[155]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[156]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[157]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[158]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[159]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[160]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[161]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[162]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[163]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[164]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[165]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[166]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[167]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[168]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[169]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[170]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[171]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[172]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[173]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[174]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[175]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[176]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[177]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[178]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[179]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[180]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[181]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[182]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[183]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[184]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[185]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[186]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[187]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[188]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[189]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[190]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[191]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[192]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[193]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[194]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[195]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[196]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[197]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[198]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[199]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[200]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[201]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[202]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[203]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[204]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[205]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[206]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[207]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[208]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[209]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[210]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[211]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[212]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[213]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[214]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[215]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[216]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[217]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[218]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[219]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[220]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[221]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[222]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[223]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[224]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[225]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[226]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[227]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[228]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[229]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[230]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[231]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[232]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[233]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[234]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[235]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[236]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[237]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[238]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[239]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[240]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[241]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[242]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[243]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[244]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[245]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[246]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[247]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[248]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[249]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[250]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[251]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[252]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[253]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[254]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[255]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[33]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[34]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[35]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[36]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[37]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[38]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[39]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[40]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[41]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[42]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[43]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[44]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[45]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[46]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[47]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[48]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[49]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[50]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[51]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[52]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[53]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[54]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[55]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[56]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[57]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[58]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[59]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[60]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[61]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[62]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[63]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[64]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[65]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[66]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[67]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[68]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[69]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[70]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[71]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[72]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[73]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[74]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[75]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[76]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[77]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[78]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[79]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[80]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[81]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[82]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[83]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[84]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[85]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[86]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[87]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[88]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[89]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[90]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[91]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[92]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[93]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[94]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[95]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[96]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[97]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[98]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[99]);
$setuphold (posedge USERCLK, posedge SAXISCCTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTDATA[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTKEEP[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTLAST);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[0]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[10]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[11]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[12]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[13]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[14]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[15]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[16]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[17]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[18]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[19]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[1]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[20]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[21]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[22]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[23]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[24]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[25]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[26]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[27]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[28]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[29]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[2]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[30]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[31]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[32]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[3]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[4]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[5]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[6]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[7]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[8]);
$setuphold (posedge USERCLK, posedge SAXISCCTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTUSER[9]);
$setuphold (posedge USERCLK, posedge SAXISCCTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISCCTVALID);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[100], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[100]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[101], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[101]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[102], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[102]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[103], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[103]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[104], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[104]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[105], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[105]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[106], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[106]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[107], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[107]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[108], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[108]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[109], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[109]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[110], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[110]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[111], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[111]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[112], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[112]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[113], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[113]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[114], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[114]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[115], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[115]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[116], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[116]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[117], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[117]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[118], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[118]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[119], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[119]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[120], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[120]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[121], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[121]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[122], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[122]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[123], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[123]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[124], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[124]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[125], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[125]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[126], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[126]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[127], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[127]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[128], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[128]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[129], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[129]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[130], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[130]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[131], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[131]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[132], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[132]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[133], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[133]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[134], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[134]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[135], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[135]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[136], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[136]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[137], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[137]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[138], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[138]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[139], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[139]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[140], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[140]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[141], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[141]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[142], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[142]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[143], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[143]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[144], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[144]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[145], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[145]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[146], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[146]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[147], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[147]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[148], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[148]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[149], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[149]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[150], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[150]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[151], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[151]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[152], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[152]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[153], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[153]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[154], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[154]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[155], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[155]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[156], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[156]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[157], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[157]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[158], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[158]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[159], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[159]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[160], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[160]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[161], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[161]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[162], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[162]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[163], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[163]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[164], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[164]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[165], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[165]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[166], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[166]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[167], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[167]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[168], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[168]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[169], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[169]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[170], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[170]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[171], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[171]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[172], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[172]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[173], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[173]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[174], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[174]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[175], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[175]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[176], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[176]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[177], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[177]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[178], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[178]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[179], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[179]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[180], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[180]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[181], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[181]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[182], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[182]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[183], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[183]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[184], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[184]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[185], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[185]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[186], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[186]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[187], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[187]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[188], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[188]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[189], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[189]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[190], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[190]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[191], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[191]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[192], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[192]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[193], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[193]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[194], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[194]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[195], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[195]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[196], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[196]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[197], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[197]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[198], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[198]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[199], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[199]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[200], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[200]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[201], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[201]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[202], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[202]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[203], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[203]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[204], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[204]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[205], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[205]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[206], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[206]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[207], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[207]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[208], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[208]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[209], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[209]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[210], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[210]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[211], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[211]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[212], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[212]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[213], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[213]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[214], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[214]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[215], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[215]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[216], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[216]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[217], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[217]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[218], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[218]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[219], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[219]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[220], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[220]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[221], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[221]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[222], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[222]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[223], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[223]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[224], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[224]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[225], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[225]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[226], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[226]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[227], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[227]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[228], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[228]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[229], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[229]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[230], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[230]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[231], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[231]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[232], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[232]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[233], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[233]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[234], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[234]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[235], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[235]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[236], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[236]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[237], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[237]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[238], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[238]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[239], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[239]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[240], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[240]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[241], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[241]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[242], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[242]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[243], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[243]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[244], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[244]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[245], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[245]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[246], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[246]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[247], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[247]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[248], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[248]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[249], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[249]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[250], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[250]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[251], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[251]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[252], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[252]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[253], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[253]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[254], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[254]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[255], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[255]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[60], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[60]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[61], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[61]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[62], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[62]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[63], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[63]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[64], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[64]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[65], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[65]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[66], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[66]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[67], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[67]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[68], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[68]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[69], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[69]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[70], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[70]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[71], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[71]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[72], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[72]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[73], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[73]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[74], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[74]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[75], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[75]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[76], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[76]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[77], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[77]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[78], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[78]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[79], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[79]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[80], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[80]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[81], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[81]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[82], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[82]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[83], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[83]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[84], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[84]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[85], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[85]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[86], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[86]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[87], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[87]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[88], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[88]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[89], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[89]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[90], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[90]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[91], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[91]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[92], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[92]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[93], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[93]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[94], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[94]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[95], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[95]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[96], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[96]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[97], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[97]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[98], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[98]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[99], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[99]);
$setuphold (posedge USERCLK, posedge SAXISRQTDATA[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTDATA[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTKEEP[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTKEEP[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTLAST, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTLAST);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[0], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[0]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[10], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[10]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[11], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[11]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[12], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[12]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[13], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[13]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[14], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[14]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[15], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[15]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[16], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[16]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[17], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[17]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[18], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[18]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[19], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[19]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[1], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[1]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[20], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[20]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[21], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[21]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[22], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[22]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[23], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[23]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[24], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[24]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[25], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[25]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[26], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[26]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[27], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[27]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[28], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[28]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[29], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[29]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[2], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[2]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[30], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[30]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[31], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[31]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[32], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[32]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[33], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[33]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[34], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[34]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[35], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[35]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[36], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[36]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[37], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[37]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[38], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[38]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[39], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[39]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[3], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[3]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[40], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[40]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[41], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[41]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[42], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[42]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[43], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[43]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[44], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[44]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[45], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[45]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[46], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[46]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[47], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[47]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[48], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[48]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[49], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[49]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[4], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[4]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[50], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[50]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[51], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[51]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[52], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[52]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[53], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[53]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[54], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[54]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[55], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[55]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[56], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[56]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[57], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[57]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[58], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[58]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[59], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[59]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[5], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[5]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[6], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[6]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[7], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[7]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[8], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[8]);
$setuphold (posedge USERCLK, posedge SAXISRQTUSER[9], 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTUSER[9]);
$setuphold (posedge USERCLK, posedge SAXISRQTVALID, 0:0:0, 0:0:0, notifier,,, delay_USERCLK, delay_SAXISRQTVALID);
`endif
( CORECLK *> DBGDATAOUT[0]) = (0, 0);
( CORECLK *> DBGDATAOUT[10]) = (0, 0);
( CORECLK *> DBGDATAOUT[11]) = (0, 0);
( CORECLK *> DBGDATAOUT[12]) = (0, 0);
( CORECLK *> DBGDATAOUT[13]) = (0, 0);
( CORECLK *> DBGDATAOUT[14]) = (0, 0);
( CORECLK *> DBGDATAOUT[15]) = (0, 0);
( CORECLK *> DBGDATAOUT[1]) = (0, 0);
( CORECLK *> DBGDATAOUT[2]) = (0, 0);
( CORECLK *> DBGDATAOUT[3]) = (0, 0);
( CORECLK *> DBGDATAOUT[4]) = (0, 0);
( CORECLK *> DBGDATAOUT[5]) = (0, 0);
( CORECLK *> DBGDATAOUT[6]) = (0, 0);
( CORECLK *> DBGDATAOUT[7]) = (0, 0);
( CORECLK *> DBGDATAOUT[8]) = (0, 0);
( CORECLK *> DBGDATAOUT[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADADDRESSBL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMREADENABLEL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEADDRESSBL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[10]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[11]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[12]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[13]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[14]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[15]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[16]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[17]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[18]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[19]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[20]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[21]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[22]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[23]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[24]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[25]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[26]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[27]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[28]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[29]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[30]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[31]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[32]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[33]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[34]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[35]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[36]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[37]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[38]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[39]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[40]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[41]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[42]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[43]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[44]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[45]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[46]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[47]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[48]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[49]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[4]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[50]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[51]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[52]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[53]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[54]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[55]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[56]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[57]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[58]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[59]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[5]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[60]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[61]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[62]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[63]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[64]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[65]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[66]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[67]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[68]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[69]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[6]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[70]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[71]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[7]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[8]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEDATAL[9]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[0]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[1]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[2]) = (0, 0);
( CORECLKMICOMPLETIONRAML *> MICOMPLETIONRAMWRITEENABLEL[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADADDRESSBU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMREADENABLEU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEADDRESSBU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[10]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[11]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[12]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[13]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[14]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[15]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[16]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[17]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[18]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[19]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[20]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[21]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[22]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[23]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[24]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[25]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[26]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[27]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[28]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[29]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[30]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[31]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[32]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[33]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[34]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[35]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[36]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[37]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[38]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[39]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[3]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[40]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[41]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[42]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[43]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[44]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[45]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[46]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[47]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[48]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[49]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[4]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[50]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[51]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[52]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[53]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[54]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[55]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[56]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[57]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[58]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[59]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[5]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[60]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[61]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[62]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[63]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[64]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[65]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[66]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[67]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[68]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[69]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[6]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[70]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[71]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[7]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[8]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEDATAU[9]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[0]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[1]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[2]) = (0, 0);
( CORECLKMICOMPLETIONRAMU *> MICOMPLETIONRAMWRITEENABLEU[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[2]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[4]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[5]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[6]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[7]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMADDRESS[8]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMREADENABLE[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[100]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[101]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[102]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[103]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[104]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[105]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[106]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[107]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[108]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[109]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[10]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[110]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[111]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[112]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[113]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[114]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[115]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[116]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[117]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[118]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[119]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[11]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[120]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[121]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[122]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[123]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[124]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[125]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[126]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[127]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[128]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[129]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[12]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[130]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[131]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[132]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[133]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[134]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[135]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[136]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[137]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[138]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[139]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[13]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[140]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[141]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[142]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[143]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[14]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[15]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[16]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[17]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[18]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[19]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[1]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[20]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[21]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[22]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[23]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[24]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[25]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[26]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[27]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[28]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[29]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[2]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[30]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[31]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[32]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[33]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[34]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[35]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[36]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[37]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[38]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[39]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[3]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[40]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[41]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[42]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[43]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[44]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[45]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[46]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[47]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[48]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[49]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[4]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[50]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[51]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[52]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[53]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[54]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[55]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[56]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[57]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[58]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[59]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[5]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[60]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[61]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[62]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[63]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[64]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[65]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[66]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[67]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[68]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[69]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[6]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[70]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[71]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[72]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[73]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[74]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[75]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[76]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[77]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[78]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[79]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[7]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[80]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[81]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[82]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[83]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[84]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[85]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[86]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[87]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[88]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[89]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[8]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[90]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[91]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[92]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[93]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[94]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[95]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[96]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[97]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[98]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[99]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEDATA[9]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[0]) = (0, 0);
( CORECLKMIREPLAYRAM *> MIREPLAYRAMWRITEENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADADDRESSB[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMREADENABLE[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEADDRESSB[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[100]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[101]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[102]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[103]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[104]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[105]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[106]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[107]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[108]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[109]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[10]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[110]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[111]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[112]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[113]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[114]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[115]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[116]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[117]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[118]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[119]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[11]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[120]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[121]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[122]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[123]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[124]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[125]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[126]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[127]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[128]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[129]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[12]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[130]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[131]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[132]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[133]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[134]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[135]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[136]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[137]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[138]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[139]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[13]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[140]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[141]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[142]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[143]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[14]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[15]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[16]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[17]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[18]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[19]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[20]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[21]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[22]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[23]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[24]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[25]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[26]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[27]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[28]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[29]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[30]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[31]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[32]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[33]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[34]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[35]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[36]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[37]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[38]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[39]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[3]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[40]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[41]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[42]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[43]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[44]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[45]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[46]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[47]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[48]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[49]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[4]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[50]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[51]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[52]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[53]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[54]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[55]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[56]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[57]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[58]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[59]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[5]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[60]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[61]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[62]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[63]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[64]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[65]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[66]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[67]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[68]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[69]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[6]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[70]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[71]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[72]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[73]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[74]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[75]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[76]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[77]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[78]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[79]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[7]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[80]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[81]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[82]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[83]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[84]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[85]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[86]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[87]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[88]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[89]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[8]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[90]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[91]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[92]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[93]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[94]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[95]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[96]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[97]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[98]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[99]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEDATA[9]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[0]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[1]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[2]) = (0, 0);
( CORECLKMIREQUESTRAM *> MIREQUESTRAMWRITEENABLE[3]) = (0, 0);
( DRPCLK *> DRPDO[0]) = (0, 0);
( DRPCLK *> DRPDO[10]) = (0, 0);
( DRPCLK *> DRPDO[11]) = (0, 0);
( DRPCLK *> DRPDO[12]) = (0, 0);
( DRPCLK *> DRPDO[13]) = (0, 0);
( DRPCLK *> DRPDO[14]) = (0, 0);
( DRPCLK *> DRPDO[15]) = (0, 0);
( DRPCLK *> DRPDO[1]) = (0, 0);
( DRPCLK *> DRPDO[2]) = (0, 0);
( DRPCLK *> DRPDO[3]) = (0, 0);
( DRPCLK *> DRPDO[4]) = (0, 0);
( DRPCLK *> DRPDO[5]) = (0, 0);
( DRPCLK *> DRPDO[6]) = (0, 0);
( DRPCLK *> DRPDO[7]) = (0, 0);
( DRPCLK *> DRPDO[8]) = (0, 0);
( DRPCLK *> DRPDO[9]) = (0, 0);
( DRPCLK *> DRPRDY) = (0, 0);
( PIPECLK *> PIPERX0EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX0EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX0EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX0EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX0EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX0POLARITY) = (0, 0);
( PIPECLK *> PIPERX1EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX1EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX1EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX1EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX1EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX1POLARITY) = (0, 0);
( PIPECLK *> PIPERX2EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX2EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX2EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX2EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX2EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX2POLARITY) = (0, 0);
( PIPECLK *> PIPERX3EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX3EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX3EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX3EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX3EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX3POLARITY) = (0, 0);
( PIPECLK *> PIPERX4EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX4EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX4EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX4EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX4EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX4POLARITY) = (0, 0);
( PIPECLK *> PIPERX5EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX5EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX5EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX5EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX5EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX5POLARITY) = (0, 0);
( PIPECLK *> PIPERX6EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX6EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX6EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX6EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX6EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX6POLARITY) = (0, 0);
( PIPECLK *> PIPERX7EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPERX7EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[0]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[2]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[3]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[4]) = (0, 0);
( PIPECLK *> PIPERX7EQLPLFFS[5]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX7EQLPTXPRESET[3]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPERX7EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPERX7POLARITY) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX0CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX0COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX0DATAVALID) = (0, 0);
( PIPECLK *> PIPETX0DATA[0]) = (0, 0);
( PIPECLK *> PIPETX0DATA[10]) = (0, 0);
( PIPECLK *> PIPETX0DATA[11]) = (0, 0);
( PIPECLK *> PIPETX0DATA[12]) = (0, 0);
( PIPECLK *> PIPETX0DATA[13]) = (0, 0);
( PIPECLK *> PIPETX0DATA[14]) = (0, 0);
( PIPECLK *> PIPETX0DATA[15]) = (0, 0);
( PIPECLK *> PIPETX0DATA[16]) = (0, 0);
( PIPECLK *> PIPETX0DATA[17]) = (0, 0);
( PIPECLK *> PIPETX0DATA[18]) = (0, 0);
( PIPECLK *> PIPETX0DATA[19]) = (0, 0);
( PIPECLK *> PIPETX0DATA[1]) = (0, 0);
( PIPECLK *> PIPETX0DATA[20]) = (0, 0);
( PIPECLK *> PIPETX0DATA[21]) = (0, 0);
( PIPECLK *> PIPETX0DATA[22]) = (0, 0);
( PIPECLK *> PIPETX0DATA[23]) = (0, 0);
( PIPECLK *> PIPETX0DATA[24]) = (0, 0);
( PIPECLK *> PIPETX0DATA[25]) = (0, 0);
( PIPECLK *> PIPETX0DATA[26]) = (0, 0);
( PIPECLK *> PIPETX0DATA[27]) = (0, 0);
( PIPECLK *> PIPETX0DATA[28]) = (0, 0);
( PIPECLK *> PIPETX0DATA[29]) = (0, 0);
( PIPECLK *> PIPETX0DATA[2]) = (0, 0);
( PIPECLK *> PIPETX0DATA[30]) = (0, 0);
( PIPECLK *> PIPETX0DATA[31]) = (0, 0);
( PIPECLK *> PIPETX0DATA[3]) = (0, 0);
( PIPECLK *> PIPETX0DATA[4]) = (0, 0);
( PIPECLK *> PIPETX0DATA[5]) = (0, 0);
( PIPECLK *> PIPETX0DATA[6]) = (0, 0);
( PIPECLK *> PIPETX0DATA[7]) = (0, 0);
( PIPECLK *> PIPETX0DATA[8]) = (0, 0);
( PIPECLK *> PIPETX0DATA[9]) = (0, 0);
( PIPECLK *> PIPETX0ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX0EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX0EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX0EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX0EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX0POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX0STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX0SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX0SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX1CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX1COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX1DATAVALID) = (0, 0);
( PIPECLK *> PIPETX1DATA[0]) = (0, 0);
( PIPECLK *> PIPETX1DATA[10]) = (0, 0);
( PIPECLK *> PIPETX1DATA[11]) = (0, 0);
( PIPECLK *> PIPETX1DATA[12]) = (0, 0);
( PIPECLK *> PIPETX1DATA[13]) = (0, 0);
( PIPECLK *> PIPETX1DATA[14]) = (0, 0);
( PIPECLK *> PIPETX1DATA[15]) = (0, 0);
( PIPECLK *> PIPETX1DATA[16]) = (0, 0);
( PIPECLK *> PIPETX1DATA[17]) = (0, 0);
( PIPECLK *> PIPETX1DATA[18]) = (0, 0);
( PIPECLK *> PIPETX1DATA[19]) = (0, 0);
( PIPECLK *> PIPETX1DATA[1]) = (0, 0);
( PIPECLK *> PIPETX1DATA[20]) = (0, 0);
( PIPECLK *> PIPETX1DATA[21]) = (0, 0);
( PIPECLK *> PIPETX1DATA[22]) = (0, 0);
( PIPECLK *> PIPETX1DATA[23]) = (0, 0);
( PIPECLK *> PIPETX1DATA[24]) = (0, 0);
( PIPECLK *> PIPETX1DATA[25]) = (0, 0);
( PIPECLK *> PIPETX1DATA[26]) = (0, 0);
( PIPECLK *> PIPETX1DATA[27]) = (0, 0);
( PIPECLK *> PIPETX1DATA[28]) = (0, 0);
( PIPECLK *> PIPETX1DATA[29]) = (0, 0);
( PIPECLK *> PIPETX1DATA[2]) = (0, 0);
( PIPECLK *> PIPETX1DATA[30]) = (0, 0);
( PIPECLK *> PIPETX1DATA[31]) = (0, 0);
( PIPECLK *> PIPETX1DATA[3]) = (0, 0);
( PIPECLK *> PIPETX1DATA[4]) = (0, 0);
( PIPECLK *> PIPETX1DATA[5]) = (0, 0);
( PIPECLK *> PIPETX1DATA[6]) = (0, 0);
( PIPECLK *> PIPETX1DATA[7]) = (0, 0);
( PIPECLK *> PIPETX1DATA[8]) = (0, 0);
( PIPECLK *> PIPETX1DATA[9]) = (0, 0);
( PIPECLK *> PIPETX1ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX1EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX1EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX1EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX1EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX1POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX1STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX1SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX1SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX2CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX2COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX2DATAVALID) = (0, 0);
( PIPECLK *> PIPETX2DATA[0]) = (0, 0);
( PIPECLK *> PIPETX2DATA[10]) = (0, 0);
( PIPECLK *> PIPETX2DATA[11]) = (0, 0);
( PIPECLK *> PIPETX2DATA[12]) = (0, 0);
( PIPECLK *> PIPETX2DATA[13]) = (0, 0);
( PIPECLK *> PIPETX2DATA[14]) = (0, 0);
( PIPECLK *> PIPETX2DATA[15]) = (0, 0);
( PIPECLK *> PIPETX2DATA[16]) = (0, 0);
( PIPECLK *> PIPETX2DATA[17]) = (0, 0);
( PIPECLK *> PIPETX2DATA[18]) = (0, 0);
( PIPECLK *> PIPETX2DATA[19]) = (0, 0);
( PIPECLK *> PIPETX2DATA[1]) = (0, 0);
( PIPECLK *> PIPETX2DATA[20]) = (0, 0);
( PIPECLK *> PIPETX2DATA[21]) = (0, 0);
( PIPECLK *> PIPETX2DATA[22]) = (0, 0);
( PIPECLK *> PIPETX2DATA[23]) = (0, 0);
( PIPECLK *> PIPETX2DATA[24]) = (0, 0);
( PIPECLK *> PIPETX2DATA[25]) = (0, 0);
( PIPECLK *> PIPETX2DATA[26]) = (0, 0);
( PIPECLK *> PIPETX2DATA[27]) = (0, 0);
( PIPECLK *> PIPETX2DATA[28]) = (0, 0);
( PIPECLK *> PIPETX2DATA[29]) = (0, 0);
( PIPECLK *> PIPETX2DATA[2]) = (0, 0);
( PIPECLK *> PIPETX2DATA[30]) = (0, 0);
( PIPECLK *> PIPETX2DATA[31]) = (0, 0);
( PIPECLK *> PIPETX2DATA[3]) = (0, 0);
( PIPECLK *> PIPETX2DATA[4]) = (0, 0);
( PIPECLK *> PIPETX2DATA[5]) = (0, 0);
( PIPECLK *> PIPETX2DATA[6]) = (0, 0);
( PIPECLK *> PIPETX2DATA[7]) = (0, 0);
( PIPECLK *> PIPETX2DATA[8]) = (0, 0);
( PIPECLK *> PIPETX2DATA[9]) = (0, 0);
( PIPECLK *> PIPETX2ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX2EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX2EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX2EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX2EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX2POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX2STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX2SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX2SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX3CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX3COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX3DATAVALID) = (0, 0);
( PIPECLK *> PIPETX3DATA[0]) = (0, 0);
( PIPECLK *> PIPETX3DATA[10]) = (0, 0);
( PIPECLK *> PIPETX3DATA[11]) = (0, 0);
( PIPECLK *> PIPETX3DATA[12]) = (0, 0);
( PIPECLK *> PIPETX3DATA[13]) = (0, 0);
( PIPECLK *> PIPETX3DATA[14]) = (0, 0);
( PIPECLK *> PIPETX3DATA[15]) = (0, 0);
( PIPECLK *> PIPETX3DATA[16]) = (0, 0);
( PIPECLK *> PIPETX3DATA[17]) = (0, 0);
( PIPECLK *> PIPETX3DATA[18]) = (0, 0);
( PIPECLK *> PIPETX3DATA[19]) = (0, 0);
( PIPECLK *> PIPETX3DATA[1]) = (0, 0);
( PIPECLK *> PIPETX3DATA[20]) = (0, 0);
( PIPECLK *> PIPETX3DATA[21]) = (0, 0);
( PIPECLK *> PIPETX3DATA[22]) = (0, 0);
( PIPECLK *> PIPETX3DATA[23]) = (0, 0);
( PIPECLK *> PIPETX3DATA[24]) = (0, 0);
( PIPECLK *> PIPETX3DATA[25]) = (0, 0);
( PIPECLK *> PIPETX3DATA[26]) = (0, 0);
( PIPECLK *> PIPETX3DATA[27]) = (0, 0);
( PIPECLK *> PIPETX3DATA[28]) = (0, 0);
( PIPECLK *> PIPETX3DATA[29]) = (0, 0);
( PIPECLK *> PIPETX3DATA[2]) = (0, 0);
( PIPECLK *> PIPETX3DATA[30]) = (0, 0);
( PIPECLK *> PIPETX3DATA[31]) = (0, 0);
( PIPECLK *> PIPETX3DATA[3]) = (0, 0);
( PIPECLK *> PIPETX3DATA[4]) = (0, 0);
( PIPECLK *> PIPETX3DATA[5]) = (0, 0);
( PIPECLK *> PIPETX3DATA[6]) = (0, 0);
( PIPECLK *> PIPETX3DATA[7]) = (0, 0);
( PIPECLK *> PIPETX3DATA[8]) = (0, 0);
( PIPECLK *> PIPETX3DATA[9]) = (0, 0);
( PIPECLK *> PIPETX3ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX3EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX3EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX3EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX3EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX3POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX3STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX3SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX3SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX4CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX4COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX4DATAVALID) = (0, 0);
( PIPECLK *> PIPETX4DATA[0]) = (0, 0);
( PIPECLK *> PIPETX4DATA[10]) = (0, 0);
( PIPECLK *> PIPETX4DATA[11]) = (0, 0);
( PIPECLK *> PIPETX4DATA[12]) = (0, 0);
( PIPECLK *> PIPETX4DATA[13]) = (0, 0);
( PIPECLK *> PIPETX4DATA[14]) = (0, 0);
( PIPECLK *> PIPETX4DATA[15]) = (0, 0);
( PIPECLK *> PIPETX4DATA[16]) = (0, 0);
( PIPECLK *> PIPETX4DATA[17]) = (0, 0);
( PIPECLK *> PIPETX4DATA[18]) = (0, 0);
( PIPECLK *> PIPETX4DATA[19]) = (0, 0);
( PIPECLK *> PIPETX4DATA[1]) = (0, 0);
( PIPECLK *> PIPETX4DATA[20]) = (0, 0);
( PIPECLK *> PIPETX4DATA[21]) = (0, 0);
( PIPECLK *> PIPETX4DATA[22]) = (0, 0);
( PIPECLK *> PIPETX4DATA[23]) = (0, 0);
( PIPECLK *> PIPETX4DATA[24]) = (0, 0);
( PIPECLK *> PIPETX4DATA[25]) = (0, 0);
( PIPECLK *> PIPETX4DATA[26]) = (0, 0);
( PIPECLK *> PIPETX4DATA[27]) = (0, 0);
( PIPECLK *> PIPETX4DATA[28]) = (0, 0);
( PIPECLK *> PIPETX4DATA[29]) = (0, 0);
( PIPECLK *> PIPETX4DATA[2]) = (0, 0);
( PIPECLK *> PIPETX4DATA[30]) = (0, 0);
( PIPECLK *> PIPETX4DATA[31]) = (0, 0);
( PIPECLK *> PIPETX4DATA[3]) = (0, 0);
( PIPECLK *> PIPETX4DATA[4]) = (0, 0);
( PIPECLK *> PIPETX4DATA[5]) = (0, 0);
( PIPECLK *> PIPETX4DATA[6]) = (0, 0);
( PIPECLK *> PIPETX4DATA[7]) = (0, 0);
( PIPECLK *> PIPETX4DATA[8]) = (0, 0);
( PIPECLK *> PIPETX4DATA[9]) = (0, 0);
( PIPECLK *> PIPETX4ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX4EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX4EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX4EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX4EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX4POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX4STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX4SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX4SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX5CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX5COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX5DATAVALID) = (0, 0);
( PIPECLK *> PIPETX5DATA[0]) = (0, 0);
( PIPECLK *> PIPETX5DATA[10]) = (0, 0);
( PIPECLK *> PIPETX5DATA[11]) = (0, 0);
( PIPECLK *> PIPETX5DATA[12]) = (0, 0);
( PIPECLK *> PIPETX5DATA[13]) = (0, 0);
( PIPECLK *> PIPETX5DATA[14]) = (0, 0);
( PIPECLK *> PIPETX5DATA[15]) = (0, 0);
( PIPECLK *> PIPETX5DATA[16]) = (0, 0);
( PIPECLK *> PIPETX5DATA[17]) = (0, 0);
( PIPECLK *> PIPETX5DATA[18]) = (0, 0);
( PIPECLK *> PIPETX5DATA[19]) = (0, 0);
( PIPECLK *> PIPETX5DATA[1]) = (0, 0);
( PIPECLK *> PIPETX5DATA[20]) = (0, 0);
( PIPECLK *> PIPETX5DATA[21]) = (0, 0);
( PIPECLK *> PIPETX5DATA[22]) = (0, 0);
( PIPECLK *> PIPETX5DATA[23]) = (0, 0);
( PIPECLK *> PIPETX5DATA[24]) = (0, 0);
( PIPECLK *> PIPETX5DATA[25]) = (0, 0);
( PIPECLK *> PIPETX5DATA[26]) = (0, 0);
( PIPECLK *> PIPETX5DATA[27]) = (0, 0);
( PIPECLK *> PIPETX5DATA[28]) = (0, 0);
( PIPECLK *> PIPETX5DATA[29]) = (0, 0);
( PIPECLK *> PIPETX5DATA[2]) = (0, 0);
( PIPECLK *> PIPETX5DATA[30]) = (0, 0);
( PIPECLK *> PIPETX5DATA[31]) = (0, 0);
( PIPECLK *> PIPETX5DATA[3]) = (0, 0);
( PIPECLK *> PIPETX5DATA[4]) = (0, 0);
( PIPECLK *> PIPETX5DATA[5]) = (0, 0);
( PIPECLK *> PIPETX5DATA[6]) = (0, 0);
( PIPECLK *> PIPETX5DATA[7]) = (0, 0);
( PIPECLK *> PIPETX5DATA[8]) = (0, 0);
( PIPECLK *> PIPETX5DATA[9]) = (0, 0);
( PIPECLK *> PIPETX5ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX5EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX5EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX5EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX5EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX5POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX5STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX5SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX5SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX6CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX6COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX6DATAVALID) = (0, 0);
( PIPECLK *> PIPETX6DATA[0]) = (0, 0);
( PIPECLK *> PIPETX6DATA[10]) = (0, 0);
( PIPECLK *> PIPETX6DATA[11]) = (0, 0);
( PIPECLK *> PIPETX6DATA[12]) = (0, 0);
( PIPECLK *> PIPETX6DATA[13]) = (0, 0);
( PIPECLK *> PIPETX6DATA[14]) = (0, 0);
( PIPECLK *> PIPETX6DATA[15]) = (0, 0);
( PIPECLK *> PIPETX6DATA[16]) = (0, 0);
( PIPECLK *> PIPETX6DATA[17]) = (0, 0);
( PIPECLK *> PIPETX6DATA[18]) = (0, 0);
( PIPECLK *> PIPETX6DATA[19]) = (0, 0);
( PIPECLK *> PIPETX6DATA[1]) = (0, 0);
( PIPECLK *> PIPETX6DATA[20]) = (0, 0);
( PIPECLK *> PIPETX6DATA[21]) = (0, 0);
( PIPECLK *> PIPETX6DATA[22]) = (0, 0);
( PIPECLK *> PIPETX6DATA[23]) = (0, 0);
( PIPECLK *> PIPETX6DATA[24]) = (0, 0);
( PIPECLK *> PIPETX6DATA[25]) = (0, 0);
( PIPECLK *> PIPETX6DATA[26]) = (0, 0);
( PIPECLK *> PIPETX6DATA[27]) = (0, 0);
( PIPECLK *> PIPETX6DATA[28]) = (0, 0);
( PIPECLK *> PIPETX6DATA[29]) = (0, 0);
( PIPECLK *> PIPETX6DATA[2]) = (0, 0);
( PIPECLK *> PIPETX6DATA[30]) = (0, 0);
( PIPECLK *> PIPETX6DATA[31]) = (0, 0);
( PIPECLK *> PIPETX6DATA[3]) = (0, 0);
( PIPECLK *> PIPETX6DATA[4]) = (0, 0);
( PIPECLK *> PIPETX6DATA[5]) = (0, 0);
( PIPECLK *> PIPETX6DATA[6]) = (0, 0);
( PIPECLK *> PIPETX6DATA[7]) = (0, 0);
( PIPECLK *> PIPETX6DATA[8]) = (0, 0);
( PIPECLK *> PIPETX6DATA[9]) = (0, 0);
( PIPECLK *> PIPETX6ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX6EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX6EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX6EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX6EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX6POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX6STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX6SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX6SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[0]) = (0, 0);
( PIPECLK *> PIPETX7CHARISK[1]) = (0, 0);
( PIPECLK *> PIPETX7COMPLIANCE) = (0, 0);
( PIPECLK *> PIPETX7DATAVALID) = (0, 0);
( PIPECLK *> PIPETX7DATA[0]) = (0, 0);
( PIPECLK *> PIPETX7DATA[10]) = (0, 0);
( PIPECLK *> PIPETX7DATA[11]) = (0, 0);
( PIPECLK *> PIPETX7DATA[12]) = (0, 0);
( PIPECLK *> PIPETX7DATA[13]) = (0, 0);
( PIPECLK *> PIPETX7DATA[14]) = (0, 0);
( PIPECLK *> PIPETX7DATA[15]) = (0, 0);
( PIPECLK *> PIPETX7DATA[16]) = (0, 0);
( PIPECLK *> PIPETX7DATA[17]) = (0, 0);
( PIPECLK *> PIPETX7DATA[18]) = (0, 0);
( PIPECLK *> PIPETX7DATA[19]) = (0, 0);
( PIPECLK *> PIPETX7DATA[1]) = (0, 0);
( PIPECLK *> PIPETX7DATA[20]) = (0, 0);
( PIPECLK *> PIPETX7DATA[21]) = (0, 0);
( PIPECLK *> PIPETX7DATA[22]) = (0, 0);
( PIPECLK *> PIPETX7DATA[23]) = (0, 0);
( PIPECLK *> PIPETX7DATA[24]) = (0, 0);
( PIPECLK *> PIPETX7DATA[25]) = (0, 0);
( PIPECLK *> PIPETX7DATA[26]) = (0, 0);
( PIPECLK *> PIPETX7DATA[27]) = (0, 0);
( PIPECLK *> PIPETX7DATA[28]) = (0, 0);
( PIPECLK *> PIPETX7DATA[29]) = (0, 0);
( PIPECLK *> PIPETX7DATA[2]) = (0, 0);
( PIPECLK *> PIPETX7DATA[30]) = (0, 0);
( PIPECLK *> PIPETX7DATA[31]) = (0, 0);
( PIPECLK *> PIPETX7DATA[3]) = (0, 0);
( PIPECLK *> PIPETX7DATA[4]) = (0, 0);
( PIPECLK *> PIPETX7DATA[5]) = (0, 0);
( PIPECLK *> PIPETX7DATA[6]) = (0, 0);
( PIPECLK *> PIPETX7DATA[7]) = (0, 0);
( PIPECLK *> PIPETX7DATA[8]) = (0, 0);
( PIPECLK *> PIPETX7DATA[9]) = (0, 0);
( PIPECLK *> PIPETX7ELECIDLE) = (0, 0);
( PIPECLK *> PIPETX7EQCONTROL[0]) = (0, 0);
( PIPECLK *> PIPETX7EQCONTROL[1]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[0]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[1]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[2]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[3]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[4]) = (0, 0);
( PIPECLK *> PIPETX7EQDEEMPH[5]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[0]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[1]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[2]) = (0, 0);
( PIPECLK *> PIPETX7EQPRESET[3]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[0]) = (0, 0);
( PIPECLK *> PIPETX7POWERDOWN[1]) = (0, 0);
( PIPECLK *> PIPETX7STARTBLOCK) = (0, 0);
( PIPECLK *> PIPETX7SYNCHEADER[0]) = (0, 0);
( PIPECLK *> PIPETX7SYNCHEADER[1]) = (0, 0);
( PIPECLK *> PIPETXDEEMPH) = (0, 0);
( PIPECLK *> PIPETXMARGIN[0]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[1]) = (0, 0);
( PIPECLK *> PIPETXMARGIN[2]) = (0, 0);
( PIPECLK *> PIPETXRATE[0]) = (0, 0);
( PIPECLK *> PIPETXRATE[1]) = (0, 0);
( PIPECLK *> PIPETXRCVRDET) = (0, 0);
( PIPECLK *> PIPETXRESET) = (0, 0);
( PIPECLK *> PIPETXSWING) = (0, 0);
( PIPECLK *> PLEQINPROGRESS) = (0, 0);
( PIPECLK *> PLEQPHASE[0]) = (0, 0);
( PIPECLK *> PLEQPHASE[1]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[0]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[1]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[2]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[3]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[4]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[5]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[6]) = (0, 0);
( RECCLK *> PLGEN3PCSRXSLIDE[7]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[0]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[1]) = (0, 0);
( USERCLK *> CFGCURRENTSPEED[2]) = (0, 0);
( USERCLK *> CFGDPASUBSTATECHANGE[0]) = (0, 0);
( USERCLK *> CFGDPASUBSTATECHANGE[1]) = (0, 0);
( USERCLK *> CFGERRCOROUT) = (0, 0);
( USERCLK *> CFGERRFATALOUT) = (0, 0);
( USERCLK *> CFGERRNONFATALOUT) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[0]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[1]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[2]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[3]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[4]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[5]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[6]) = (0, 0);
( USERCLK *> CFGEXTFUNCTIONNUMBER[7]) = (0, 0);
( USERCLK *> CFGEXTREADRECEIVED) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[0]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[1]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[2]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[3]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[4]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[5]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[6]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[7]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[8]) = (0, 0);
( USERCLK *> CFGEXTREGISTERNUMBER[9]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[0]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[1]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[2]) = (0, 0);
( USERCLK *> CFGEXTWRITEBYTEENABLE[3]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[0]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[10]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[11]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[12]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[13]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[14]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[15]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[16]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[17]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[18]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[19]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[1]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[20]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[21]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[22]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[23]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[24]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[25]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[26]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[27]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[28]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[29]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[2]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[30]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[31]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[3]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[4]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[5]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[6]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[7]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[8]) = (0, 0);
( USERCLK *> CFGEXTWRITEDATA[9]) = (0, 0);
( USERCLK *> CFGEXTWRITERECEIVED) = (0, 0);
( USERCLK *> CFGFCCPLD[0]) = (0, 0);
( USERCLK *> CFGFCCPLD[10]) = (0, 0);
( USERCLK *> CFGFCCPLD[11]) = (0, 0);
( USERCLK *> CFGFCCPLD[1]) = (0, 0);
( USERCLK *> CFGFCCPLD[2]) = (0, 0);
( USERCLK *> CFGFCCPLD[3]) = (0, 0);
( USERCLK *> CFGFCCPLD[4]) = (0, 0);
( USERCLK *> CFGFCCPLD[5]) = (0, 0);
( USERCLK *> CFGFCCPLD[6]) = (0, 0);
( USERCLK *> CFGFCCPLD[7]) = (0, 0);
( USERCLK *> CFGFCCPLD[8]) = (0, 0);
( USERCLK *> CFGFCCPLD[9]) = (0, 0);
( USERCLK *> CFGFCCPLH[0]) = (0, 0);
( USERCLK *> CFGFCCPLH[1]) = (0, 0);
( USERCLK *> CFGFCCPLH[2]) = (0, 0);
( USERCLK *> CFGFCCPLH[3]) = (0, 0);
( USERCLK *> CFGFCCPLH[4]) = (0, 0);
( USERCLK *> CFGFCCPLH[5]) = (0, 0);
( USERCLK *> CFGFCCPLH[6]) = (0, 0);
( USERCLK *> CFGFCCPLH[7]) = (0, 0);
( USERCLK *> CFGFCNPD[0]) = (0, 0);
( USERCLK *> CFGFCNPD[10]) = (0, 0);
( USERCLK *> CFGFCNPD[11]) = (0, 0);
( USERCLK *> CFGFCNPD[1]) = (0, 0);
( USERCLK *> CFGFCNPD[2]) = (0, 0);
( USERCLK *> CFGFCNPD[3]) = (0, 0);
( USERCLK *> CFGFCNPD[4]) = (0, 0);
( USERCLK *> CFGFCNPD[5]) = (0, 0);
( USERCLK *> CFGFCNPD[6]) = (0, 0);
( USERCLK *> CFGFCNPD[7]) = (0, 0);
( USERCLK *> CFGFCNPD[8]) = (0, 0);
( USERCLK *> CFGFCNPD[9]) = (0, 0);
( USERCLK *> CFGFCNPH[0]) = (0, 0);
( USERCLK *> CFGFCNPH[1]) = (0, 0);
( USERCLK *> CFGFCNPH[2]) = (0, 0);
( USERCLK *> CFGFCNPH[3]) = (0, 0);
( USERCLK *> CFGFCNPH[4]) = (0, 0);
( USERCLK *> CFGFCNPH[5]) = (0, 0);
( USERCLK *> CFGFCNPH[6]) = (0, 0);
( USERCLK *> CFGFCNPH[7]) = (0, 0);
( USERCLK *> CFGFCPD[0]) = (0, 0);
( USERCLK *> CFGFCPD[10]) = (0, 0);
( USERCLK *> CFGFCPD[11]) = (0, 0);
( USERCLK *> CFGFCPD[1]) = (0, 0);
( USERCLK *> CFGFCPD[2]) = (0, 0);
( USERCLK *> CFGFCPD[3]) = (0, 0);
( USERCLK *> CFGFCPD[4]) = (0, 0);
( USERCLK *> CFGFCPD[5]) = (0, 0);
( USERCLK *> CFGFCPD[6]) = (0, 0);
( USERCLK *> CFGFCPD[7]) = (0, 0);
( USERCLK *> CFGFCPD[8]) = (0, 0);
( USERCLK *> CFGFCPD[9]) = (0, 0);
( USERCLK *> CFGFCPH[0]) = (0, 0);
( USERCLK *> CFGFCPH[1]) = (0, 0);
( USERCLK *> CFGFCPH[2]) = (0, 0);
( USERCLK *> CFGFCPH[3]) = (0, 0);
( USERCLK *> CFGFCPH[4]) = (0, 0);
( USERCLK *> CFGFCPH[5]) = (0, 0);
( USERCLK *> CFGFCPH[6]) = (0, 0);
( USERCLK *> CFGFCPH[7]) = (0, 0);
( USERCLK *> CFGFLRINPROCESS[0]) = (0, 0);
( USERCLK *> CFGFLRINPROCESS[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[2]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[3]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[4]) = (0, 0);
( USERCLK *> CFGFUNCTIONPOWERSTATE[5]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[0]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[1]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[2]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[3]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[4]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[5]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[6]) = (0, 0);
( USERCLK *> CFGFUNCTIONSTATUS[7]) = (0, 0);
( USERCLK *> CFGHOTRESETOUT) = (0, 0);
( USERCLK *> CFGINPUTUPDATEDONE) = (0, 0);
( USERCLK *> CFGINTERRUPTAOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTBOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTCOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTDOUTPUT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[10]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[11]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[12]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[13]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[14]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[15]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[16]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[17]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[18]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[19]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[20]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[21]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[22]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[23]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[24]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[25]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[26]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[27]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[28]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[29]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[30]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[31]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[6]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[7]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[8]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIDATA[9]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIFAIL) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMASKUPDATE) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIMMENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSISENT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIVFENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXFAIL) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXMASK[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXMASK[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXSENT) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFENABLE[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[0]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[1]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[2]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[3]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[4]) = (0, 0);
( USERCLK *> CFGINTERRUPTMSIXVFMASK[5]) = (0, 0);
( USERCLK *> CFGINTERRUPTSENT) = (0, 0);
( USERCLK *> CFGLINKPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGLINKPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGLOCALERROR) = (0, 0);
( USERCLK *> CFGLTRENABLE) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[0]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[1]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[2]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[3]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[4]) = (0, 0);
( USERCLK *> CFGLTSSMSTATE[5]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[0]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[1]) = (0, 0);
( USERCLK *> CFGMAXPAYLOAD[2]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[0]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[1]) = (0, 0);
( USERCLK *> CFGMAXREADREQ[2]) = (0, 0);
( USERCLK *> CFGMCUPDATEDONE) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[0]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[10]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[11]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[12]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[13]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[14]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[15]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[16]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[17]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[18]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[19]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[1]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[20]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[21]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[22]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[23]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[24]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[25]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[26]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[27]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[28]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[29]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[2]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[30]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[31]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[3]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[4]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[5]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[6]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[7]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[8]) = (0, 0);
( USERCLK *> CFGMGMTREADDATA[9]) = (0, 0);
( USERCLK *> CFGMGMTREADWRITEDONE) = (0, 0);
( USERCLK *> CFGMSGRECEIVED) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[0]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[1]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[2]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[3]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[4]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[5]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[6]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDDATA[7]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[0]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[1]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[2]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[3]) = (0, 0);
( USERCLK *> CFGMSGRECEIVEDTYPE[4]) = (0, 0);
( USERCLK *> CFGMSGTRANSMITDONE) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[0]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[1]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[2]) = (0, 0);
( USERCLK *> CFGNEGOTIATEDWIDTH[3]) = (0, 0);
( USERCLK *> CFGOBFFENABLE[0]) = (0, 0);
( USERCLK *> CFGOBFFENABLE[1]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[0]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[10]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[11]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[12]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[13]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[14]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[15]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[1]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[2]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[3]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[4]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[5]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[6]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[7]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[8]) = (0, 0);
( USERCLK *> CFGPERFUNCSTATUSDATA[9]) = (0, 0);
( USERCLK *> CFGPERFUNCTIONUPDATEDONE) = (0, 0);
( USERCLK *> CFGPHYLINKDOWN) = (0, 0);
( USERCLK *> CFGPHYLINKSTATUS[0]) = (0, 0);
( USERCLK *> CFGPHYLINKSTATUS[1]) = (0, 0);
( USERCLK *> CFGPLSTATUSCHANGE) = (0, 0);
( USERCLK *> CFGPOWERSTATECHANGEINTERRUPT) = (0, 0);
( USERCLK *> CFGRCBSTATUS[0]) = (0, 0);
( USERCLK *> CFGRCBSTATUS[1]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[0]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[1]) = (0, 0);
( USERCLK *> CFGTPHFUNCTIONNUM[2]) = (0, 0);
( USERCLK *> CFGTPHREQUESTERENABLE[0]) = (0, 0);
( USERCLK *> CFGTPHREQUESTERENABLE[1]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[0]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[1]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[2]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[3]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[4]) = (0, 0);
( USERCLK *> CFGTPHSTMODE[5]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[0]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[1]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[2]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[3]) = (0, 0);
( USERCLK *> CFGTPHSTTADDRESS[4]) = (0, 0);
( USERCLK *> CFGTPHSTTREADENABLE) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[0]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[1]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[2]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEBYTEVALID[3]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[0]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[10]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[11]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[12]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[13]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[14]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[15]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[16]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[17]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[18]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[19]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[1]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[20]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[21]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[22]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[23]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[24]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[25]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[26]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[27]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[28]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[29]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[2]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[30]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[31]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[3]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[4]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[5]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[6]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[7]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[8]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEDATA[9]) = (0, 0);
( USERCLK *> CFGTPHSTTWRITEENABLE) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[0]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[1]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[2]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[3]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[4]) = (0, 0);
( USERCLK *> CFGVFFLRINPROCESS[5]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[0]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[10]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[11]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[12]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[13]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[14]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[15]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[16]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[17]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[1]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[2]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[3]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[4]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[5]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[6]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[7]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[8]) = (0, 0);
( USERCLK *> CFGVFPOWERSTATE[9]) = (0, 0);
( USERCLK *> CFGVFSTATUS[0]) = (0, 0);
( USERCLK *> CFGVFSTATUS[10]) = (0, 0);
( USERCLK *> CFGVFSTATUS[11]) = (0, 0);
( USERCLK *> CFGVFSTATUS[1]) = (0, 0);
( USERCLK *> CFGVFSTATUS[2]) = (0, 0);
( USERCLK *> CFGVFSTATUS[3]) = (0, 0);
( USERCLK *> CFGVFSTATUS[4]) = (0, 0);
( USERCLK *> CFGVFSTATUS[5]) = (0, 0);
( USERCLK *> CFGVFSTATUS[6]) = (0, 0);
( USERCLK *> CFGVFSTATUS[7]) = (0, 0);
( USERCLK *> CFGVFSTATUS[8]) = (0, 0);
( USERCLK *> CFGVFSTATUS[9]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[0]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[1]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[2]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[3]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[4]) = (0, 0);
( USERCLK *> CFGVFTPHREQUESTERENABLE[5]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[0]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[10]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[11]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[12]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[13]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[14]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[15]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[16]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[17]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[1]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[2]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[3]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[4]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[5]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[6]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[7]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[8]) = (0, 0);
( USERCLK *> CFGVFTPHSTMODE[9]) = (0, 0);
( USERCLK *> MAXISCQTDATA[0]) = (0, 0);
( USERCLK *> MAXISCQTDATA[100]) = (0, 0);
( USERCLK *> MAXISCQTDATA[101]) = (0, 0);
( USERCLK *> MAXISCQTDATA[102]) = (0, 0);
( USERCLK *> MAXISCQTDATA[103]) = (0, 0);
( USERCLK *> MAXISCQTDATA[104]) = (0, 0);
( USERCLK *> MAXISCQTDATA[105]) = (0, 0);
( USERCLK *> MAXISCQTDATA[106]) = (0, 0);
( USERCLK *> MAXISCQTDATA[107]) = (0, 0);
( USERCLK *> MAXISCQTDATA[108]) = (0, 0);
( USERCLK *> MAXISCQTDATA[109]) = (0, 0);
( USERCLK *> MAXISCQTDATA[10]) = (0, 0);
( USERCLK *> MAXISCQTDATA[110]) = (0, 0);
( USERCLK *> MAXISCQTDATA[111]) = (0, 0);
( USERCLK *> MAXISCQTDATA[112]) = (0, 0);
( USERCLK *> MAXISCQTDATA[113]) = (0, 0);
( USERCLK *> MAXISCQTDATA[114]) = (0, 0);
( USERCLK *> MAXISCQTDATA[115]) = (0, 0);
( USERCLK *> MAXISCQTDATA[116]) = (0, 0);
( USERCLK *> MAXISCQTDATA[117]) = (0, 0);
( USERCLK *> MAXISCQTDATA[118]) = (0, 0);
( USERCLK *> MAXISCQTDATA[119]) = (0, 0);
( USERCLK *> MAXISCQTDATA[11]) = (0, 0);
( USERCLK *> MAXISCQTDATA[120]) = (0, 0);
( USERCLK *> MAXISCQTDATA[121]) = (0, 0);
( USERCLK *> MAXISCQTDATA[122]) = (0, 0);
( USERCLK *> MAXISCQTDATA[123]) = (0, 0);
( USERCLK *> MAXISCQTDATA[124]) = (0, 0);
( USERCLK *> MAXISCQTDATA[125]) = (0, 0);
( USERCLK *> MAXISCQTDATA[126]) = (0, 0);
( USERCLK *> MAXISCQTDATA[127]) = (0, 0);
( USERCLK *> MAXISCQTDATA[128]) = (0, 0);
( USERCLK *> MAXISCQTDATA[129]) = (0, 0);
( USERCLK *> MAXISCQTDATA[12]) = (0, 0);
( USERCLK *> MAXISCQTDATA[130]) = (0, 0);
( USERCLK *> MAXISCQTDATA[131]) = (0, 0);
( USERCLK *> MAXISCQTDATA[132]) = (0, 0);
( USERCLK *> MAXISCQTDATA[133]) = (0, 0);
( USERCLK *> MAXISCQTDATA[134]) = (0, 0);
( USERCLK *> MAXISCQTDATA[135]) = (0, 0);
( USERCLK *> MAXISCQTDATA[136]) = (0, 0);
( USERCLK *> MAXISCQTDATA[137]) = (0, 0);
( USERCLK *> MAXISCQTDATA[138]) = (0, 0);
( USERCLK *> MAXISCQTDATA[139]) = (0, 0);
( USERCLK *> MAXISCQTDATA[13]) = (0, 0);
( USERCLK *> MAXISCQTDATA[140]) = (0, 0);
( USERCLK *> MAXISCQTDATA[141]) = (0, 0);
( USERCLK *> MAXISCQTDATA[142]) = (0, 0);
( USERCLK *> MAXISCQTDATA[143]) = (0, 0);
( USERCLK *> MAXISCQTDATA[144]) = (0, 0);
( USERCLK *> MAXISCQTDATA[145]) = (0, 0);
( USERCLK *> MAXISCQTDATA[146]) = (0, 0);
( USERCLK *> MAXISCQTDATA[147]) = (0, 0);
( USERCLK *> MAXISCQTDATA[148]) = (0, 0);
( USERCLK *> MAXISCQTDATA[149]) = (0, 0);
( USERCLK *> MAXISCQTDATA[14]) = (0, 0);
( USERCLK *> MAXISCQTDATA[150]) = (0, 0);
( USERCLK *> MAXISCQTDATA[151]) = (0, 0);
( USERCLK *> MAXISCQTDATA[152]) = (0, 0);
( USERCLK *> MAXISCQTDATA[153]) = (0, 0);
( USERCLK *> MAXISCQTDATA[154]) = (0, 0);
( USERCLK *> MAXISCQTDATA[155]) = (0, 0);
( USERCLK *> MAXISCQTDATA[156]) = (0, 0);
( USERCLK *> MAXISCQTDATA[157]) = (0, 0);
( USERCLK *> MAXISCQTDATA[158]) = (0, 0);
( USERCLK *> MAXISCQTDATA[159]) = (0, 0);
( USERCLK *> MAXISCQTDATA[15]) = (0, 0);
( USERCLK *> MAXISCQTDATA[160]) = (0, 0);
( USERCLK *> MAXISCQTDATA[161]) = (0, 0);
( USERCLK *> MAXISCQTDATA[162]) = (0, 0);
( USERCLK *> MAXISCQTDATA[163]) = (0, 0);
( USERCLK *> MAXISCQTDATA[164]) = (0, 0);
( USERCLK *> MAXISCQTDATA[165]) = (0, 0);
( USERCLK *> MAXISCQTDATA[166]) = (0, 0);
( USERCLK *> MAXISCQTDATA[167]) = (0, 0);
( USERCLK *> MAXISCQTDATA[168]) = (0, 0);
( USERCLK *> MAXISCQTDATA[169]) = (0, 0);
( USERCLK *> MAXISCQTDATA[16]) = (0, 0);
( USERCLK *> MAXISCQTDATA[170]) = (0, 0);
( USERCLK *> MAXISCQTDATA[171]) = (0, 0);
( USERCLK *> MAXISCQTDATA[172]) = (0, 0);
( USERCLK *> MAXISCQTDATA[173]) = (0, 0);
( USERCLK *> MAXISCQTDATA[174]) = (0, 0);
( USERCLK *> MAXISCQTDATA[175]) = (0, 0);
( USERCLK *> MAXISCQTDATA[176]) = (0, 0);
( USERCLK *> MAXISCQTDATA[177]) = (0, 0);
( USERCLK *> MAXISCQTDATA[178]) = (0, 0);
( USERCLK *> MAXISCQTDATA[179]) = (0, 0);
( USERCLK *> MAXISCQTDATA[17]) = (0, 0);
( USERCLK *> MAXISCQTDATA[180]) = (0, 0);
( USERCLK *> MAXISCQTDATA[181]) = (0, 0);
( USERCLK *> MAXISCQTDATA[182]) = (0, 0);
( USERCLK *> MAXISCQTDATA[183]) = (0, 0);
( USERCLK *> MAXISCQTDATA[184]) = (0, 0);
( USERCLK *> MAXISCQTDATA[185]) = (0, 0);
( USERCLK *> MAXISCQTDATA[186]) = (0, 0);
( USERCLK *> MAXISCQTDATA[187]) = (0, 0);
( USERCLK *> MAXISCQTDATA[188]) = (0, 0);
( USERCLK *> MAXISCQTDATA[189]) = (0, 0);
( USERCLK *> MAXISCQTDATA[18]) = (0, 0);
( USERCLK *> MAXISCQTDATA[190]) = (0, 0);
( USERCLK *> MAXISCQTDATA[191]) = (0, 0);
( USERCLK *> MAXISCQTDATA[192]) = (0, 0);
( USERCLK *> MAXISCQTDATA[193]) = (0, 0);
( USERCLK *> MAXISCQTDATA[194]) = (0, 0);
( USERCLK *> MAXISCQTDATA[195]) = (0, 0);
( USERCLK *> MAXISCQTDATA[196]) = (0, 0);
( USERCLK *> MAXISCQTDATA[197]) = (0, 0);
( USERCLK *> MAXISCQTDATA[198]) = (0, 0);
( USERCLK *> MAXISCQTDATA[199]) = (0, 0);
( USERCLK *> MAXISCQTDATA[19]) = (0, 0);
( USERCLK *> MAXISCQTDATA[1]) = (0, 0);
( USERCLK *> MAXISCQTDATA[200]) = (0, 0);
( USERCLK *> MAXISCQTDATA[201]) = (0, 0);
( USERCLK *> MAXISCQTDATA[202]) = (0, 0);
( USERCLK *> MAXISCQTDATA[203]) = (0, 0);
( USERCLK *> MAXISCQTDATA[204]) = (0, 0);
( USERCLK *> MAXISCQTDATA[205]) = (0, 0);
( USERCLK *> MAXISCQTDATA[206]) = (0, 0);
( USERCLK *> MAXISCQTDATA[207]) = (0, 0);
( USERCLK *> MAXISCQTDATA[208]) = (0, 0);
( USERCLK *> MAXISCQTDATA[209]) = (0, 0);
( USERCLK *> MAXISCQTDATA[20]) = (0, 0);
( USERCLK *> MAXISCQTDATA[210]) = (0, 0);
( USERCLK *> MAXISCQTDATA[211]) = (0, 0);
( USERCLK *> MAXISCQTDATA[212]) = (0, 0);
( USERCLK *> MAXISCQTDATA[213]) = (0, 0);
( USERCLK *> MAXISCQTDATA[214]) = (0, 0);
( USERCLK *> MAXISCQTDATA[215]) = (0, 0);
( USERCLK *> MAXISCQTDATA[216]) = (0, 0);
( USERCLK *> MAXISCQTDATA[217]) = (0, 0);
( USERCLK *> MAXISCQTDATA[218]) = (0, 0);
( USERCLK *> MAXISCQTDATA[219]) = (0, 0);
( USERCLK *> MAXISCQTDATA[21]) = (0, 0);
( USERCLK *> MAXISCQTDATA[220]) = (0, 0);
( USERCLK *> MAXISCQTDATA[221]) = (0, 0);
( USERCLK *> MAXISCQTDATA[222]) = (0, 0);
( USERCLK *> MAXISCQTDATA[223]) = (0, 0);
( USERCLK *> MAXISCQTDATA[224]) = (0, 0);
( USERCLK *> MAXISCQTDATA[225]) = (0, 0);
( USERCLK *> MAXISCQTDATA[226]) = (0, 0);
( USERCLK *> MAXISCQTDATA[227]) = (0, 0);
( USERCLK *> MAXISCQTDATA[228]) = (0, 0);
( USERCLK *> MAXISCQTDATA[229]) = (0, 0);
( USERCLK *> MAXISCQTDATA[22]) = (0, 0);
( USERCLK *> MAXISCQTDATA[230]) = (0, 0);
( USERCLK *> MAXISCQTDATA[231]) = (0, 0);
( USERCLK *> MAXISCQTDATA[232]) = (0, 0);
( USERCLK *> MAXISCQTDATA[233]) = (0, 0);
( USERCLK *> MAXISCQTDATA[234]) = (0, 0);
( USERCLK *> MAXISCQTDATA[235]) = (0, 0);
( USERCLK *> MAXISCQTDATA[236]) = (0, 0);
( USERCLK *> MAXISCQTDATA[237]) = (0, 0);
( USERCLK *> MAXISCQTDATA[238]) = (0, 0);
( USERCLK *> MAXISCQTDATA[239]) = (0, 0);
( USERCLK *> MAXISCQTDATA[23]) = (0, 0);
( USERCLK *> MAXISCQTDATA[240]) = (0, 0);
( USERCLK *> MAXISCQTDATA[241]) = (0, 0);
( USERCLK *> MAXISCQTDATA[242]) = (0, 0);
( USERCLK *> MAXISCQTDATA[243]) = (0, 0);
( USERCLK *> MAXISCQTDATA[244]) = (0, 0);
( USERCLK *> MAXISCQTDATA[245]) = (0, 0);
( USERCLK *> MAXISCQTDATA[246]) = (0, 0);
( USERCLK *> MAXISCQTDATA[247]) = (0, 0);
( USERCLK *> MAXISCQTDATA[248]) = (0, 0);
( USERCLK *> MAXISCQTDATA[249]) = (0, 0);
( USERCLK *> MAXISCQTDATA[24]) = (0, 0);
( USERCLK *> MAXISCQTDATA[250]) = (0, 0);
( USERCLK *> MAXISCQTDATA[251]) = (0, 0);
( USERCLK *> MAXISCQTDATA[252]) = (0, 0);
( USERCLK *> MAXISCQTDATA[253]) = (0, 0);
( USERCLK *> MAXISCQTDATA[254]) = (0, 0);
( USERCLK *> MAXISCQTDATA[255]) = (0, 0);
( USERCLK *> MAXISCQTDATA[25]) = (0, 0);
( USERCLK *> MAXISCQTDATA[26]) = (0, 0);
( USERCLK *> MAXISCQTDATA[27]) = (0, 0);
( USERCLK *> MAXISCQTDATA[28]) = (0, 0);
( USERCLK *> MAXISCQTDATA[29]) = (0, 0);
( USERCLK *> MAXISCQTDATA[2]) = (0, 0);
( USERCLK *> MAXISCQTDATA[30]) = (0, 0);
( USERCLK *> MAXISCQTDATA[31]) = (0, 0);
( USERCLK *> MAXISCQTDATA[32]) = (0, 0);
( USERCLK *> MAXISCQTDATA[33]) = (0, 0);
( USERCLK *> MAXISCQTDATA[34]) = (0, 0);
( USERCLK *> MAXISCQTDATA[35]) = (0, 0);
( USERCLK *> MAXISCQTDATA[36]) = (0, 0);
( USERCLK *> MAXISCQTDATA[37]) = (0, 0);
( USERCLK *> MAXISCQTDATA[38]) = (0, 0);
( USERCLK *> MAXISCQTDATA[39]) = (0, 0);
( USERCLK *> MAXISCQTDATA[3]) = (0, 0);
( USERCLK *> MAXISCQTDATA[40]) = (0, 0);
( USERCLK *> MAXISCQTDATA[41]) = (0, 0);
( USERCLK *> MAXISCQTDATA[42]) = (0, 0);
( USERCLK *> MAXISCQTDATA[43]) = (0, 0);
( USERCLK *> MAXISCQTDATA[44]) = (0, 0);
( USERCLK *> MAXISCQTDATA[45]) = (0, 0);
( USERCLK *> MAXISCQTDATA[46]) = (0, 0);
( USERCLK *> MAXISCQTDATA[47]) = (0, 0);
( USERCLK *> MAXISCQTDATA[48]) = (0, 0);
( USERCLK *> MAXISCQTDATA[49]) = (0, 0);
( USERCLK *> MAXISCQTDATA[4]) = (0, 0);
( USERCLK *> MAXISCQTDATA[50]) = (0, 0);
( USERCLK *> MAXISCQTDATA[51]) = (0, 0);
( USERCLK *> MAXISCQTDATA[52]) = (0, 0);
( USERCLK *> MAXISCQTDATA[53]) = (0, 0);
( USERCLK *> MAXISCQTDATA[54]) = (0, 0);
( USERCLK *> MAXISCQTDATA[55]) = (0, 0);
( USERCLK *> MAXISCQTDATA[56]) = (0, 0);
( USERCLK *> MAXISCQTDATA[57]) = (0, 0);
( USERCLK *> MAXISCQTDATA[58]) = (0, 0);
( USERCLK *> MAXISCQTDATA[59]) = (0, 0);
( USERCLK *> MAXISCQTDATA[5]) = (0, 0);
( USERCLK *> MAXISCQTDATA[60]) = (0, 0);
( USERCLK *> MAXISCQTDATA[61]) = (0, 0);
( USERCLK *> MAXISCQTDATA[62]) = (0, 0);
( USERCLK *> MAXISCQTDATA[63]) = (0, 0);
( USERCLK *> MAXISCQTDATA[64]) = (0, 0);
( USERCLK *> MAXISCQTDATA[65]) = (0, 0);
( USERCLK *> MAXISCQTDATA[66]) = (0, 0);
( USERCLK *> MAXISCQTDATA[67]) = (0, 0);
( USERCLK *> MAXISCQTDATA[68]) = (0, 0);
( USERCLK *> MAXISCQTDATA[69]) = (0, 0);
( USERCLK *> MAXISCQTDATA[6]) = (0, 0);
( USERCLK *> MAXISCQTDATA[70]) = (0, 0);
( USERCLK *> MAXISCQTDATA[71]) = (0, 0);
( USERCLK *> MAXISCQTDATA[72]) = (0, 0);
( USERCLK *> MAXISCQTDATA[73]) = (0, 0);
( USERCLK *> MAXISCQTDATA[74]) = (0, 0);
( USERCLK *> MAXISCQTDATA[75]) = (0, 0);
( USERCLK *> MAXISCQTDATA[76]) = (0, 0);
( USERCLK *> MAXISCQTDATA[77]) = (0, 0);
( USERCLK *> MAXISCQTDATA[78]) = (0, 0);
( USERCLK *> MAXISCQTDATA[79]) = (0, 0);
( USERCLK *> MAXISCQTDATA[7]) = (0, 0);
( USERCLK *> MAXISCQTDATA[80]) = (0, 0);
( USERCLK *> MAXISCQTDATA[81]) = (0, 0);
( USERCLK *> MAXISCQTDATA[82]) = (0, 0);
( USERCLK *> MAXISCQTDATA[83]) = (0, 0);
( USERCLK *> MAXISCQTDATA[84]) = (0, 0);
( USERCLK *> MAXISCQTDATA[85]) = (0, 0);
( USERCLK *> MAXISCQTDATA[86]) = (0, 0);
( USERCLK *> MAXISCQTDATA[87]) = (0, 0);
( USERCLK *> MAXISCQTDATA[88]) = (0, 0);
( USERCLK *> MAXISCQTDATA[89]) = (0, 0);
( USERCLK *> MAXISCQTDATA[8]) = (0, 0);
( USERCLK *> MAXISCQTDATA[90]) = (0, 0);
( USERCLK *> MAXISCQTDATA[91]) = (0, 0);
( USERCLK *> MAXISCQTDATA[92]) = (0, 0);
( USERCLK *> MAXISCQTDATA[93]) = (0, 0);
( USERCLK *> MAXISCQTDATA[94]) = (0, 0);
( USERCLK *> MAXISCQTDATA[95]) = (0, 0);
( USERCLK *> MAXISCQTDATA[96]) = (0, 0);
( USERCLK *> MAXISCQTDATA[97]) = (0, 0);
( USERCLK *> MAXISCQTDATA[98]) = (0, 0);
( USERCLK *> MAXISCQTDATA[99]) = (0, 0);
( USERCLK *> MAXISCQTDATA[9]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[0]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[1]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[2]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[3]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[4]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[5]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[6]) = (0, 0);
( USERCLK *> MAXISCQTKEEP[7]) = (0, 0);
( USERCLK *> MAXISCQTLAST) = (0, 0);
( USERCLK *> MAXISCQTUSER[0]) = (0, 0);
( USERCLK *> MAXISCQTUSER[10]) = (0, 0);
( USERCLK *> MAXISCQTUSER[11]) = (0, 0);
( USERCLK *> MAXISCQTUSER[12]) = (0, 0);
( USERCLK *> MAXISCQTUSER[13]) = (0, 0);
( USERCLK *> MAXISCQTUSER[14]) = (0, 0);
( USERCLK *> MAXISCQTUSER[15]) = (0, 0);
( USERCLK *> MAXISCQTUSER[16]) = (0, 0);
( USERCLK *> MAXISCQTUSER[17]) = (0, 0);
( USERCLK *> MAXISCQTUSER[18]) = (0, 0);
( USERCLK *> MAXISCQTUSER[19]) = (0, 0);
( USERCLK *> MAXISCQTUSER[1]) = (0, 0);
( USERCLK *> MAXISCQTUSER[20]) = (0, 0);
( USERCLK *> MAXISCQTUSER[21]) = (0, 0);
( USERCLK *> MAXISCQTUSER[22]) = (0, 0);
( USERCLK *> MAXISCQTUSER[23]) = (0, 0);
( USERCLK *> MAXISCQTUSER[24]) = (0, 0);
( USERCLK *> MAXISCQTUSER[25]) = (0, 0);
( USERCLK *> MAXISCQTUSER[26]) = (0, 0);
( USERCLK *> MAXISCQTUSER[27]) = (0, 0);
( USERCLK *> MAXISCQTUSER[28]) = (0, 0);
( USERCLK *> MAXISCQTUSER[29]) = (0, 0);
( USERCLK *> MAXISCQTUSER[2]) = (0, 0);
( USERCLK *> MAXISCQTUSER[30]) = (0, 0);
( USERCLK *> MAXISCQTUSER[31]) = (0, 0);
( USERCLK *> MAXISCQTUSER[32]) = (0, 0);
( USERCLK *> MAXISCQTUSER[33]) = (0, 0);
( USERCLK *> MAXISCQTUSER[34]) = (0, 0);
( USERCLK *> MAXISCQTUSER[35]) = (0, 0);
( USERCLK *> MAXISCQTUSER[36]) = (0, 0);
( USERCLK *> MAXISCQTUSER[37]) = (0, 0);
( USERCLK *> MAXISCQTUSER[38]) = (0, 0);
( USERCLK *> MAXISCQTUSER[39]) = (0, 0);
( USERCLK *> MAXISCQTUSER[3]) = (0, 0);
( USERCLK *> MAXISCQTUSER[40]) = (0, 0);
( USERCLK *> MAXISCQTUSER[41]) = (0, 0);
( USERCLK *> MAXISCQTUSER[42]) = (0, 0);
( USERCLK *> MAXISCQTUSER[43]) = (0, 0);
( USERCLK *> MAXISCQTUSER[44]) = (0, 0);
( USERCLK *> MAXISCQTUSER[45]) = (0, 0);
( USERCLK *> MAXISCQTUSER[46]) = (0, 0);
( USERCLK *> MAXISCQTUSER[47]) = (0, 0);
( USERCLK *> MAXISCQTUSER[48]) = (0, 0);
( USERCLK *> MAXISCQTUSER[49]) = (0, 0);
( USERCLK *> MAXISCQTUSER[4]) = (0, 0);
( USERCLK *> MAXISCQTUSER[50]) = (0, 0);
( USERCLK *> MAXISCQTUSER[51]) = (0, 0);
( USERCLK *> MAXISCQTUSER[52]) = (0, 0);
( USERCLK *> MAXISCQTUSER[53]) = (0, 0);
( USERCLK *> MAXISCQTUSER[54]) = (0, 0);
( USERCLK *> MAXISCQTUSER[55]) = (0, 0);
( USERCLK *> MAXISCQTUSER[56]) = (0, 0);
( USERCLK *> MAXISCQTUSER[57]) = (0, 0);
( USERCLK *> MAXISCQTUSER[58]) = (0, 0);
( USERCLK *> MAXISCQTUSER[59]) = (0, 0);
( USERCLK *> MAXISCQTUSER[5]) = (0, 0);
( USERCLK *> MAXISCQTUSER[60]) = (0, 0);
( USERCLK *> MAXISCQTUSER[61]) = (0, 0);
( USERCLK *> MAXISCQTUSER[62]) = (0, 0);
( USERCLK *> MAXISCQTUSER[63]) = (0, 0);
( USERCLK *> MAXISCQTUSER[64]) = (0, 0);
( USERCLK *> MAXISCQTUSER[65]) = (0, 0);
( USERCLK *> MAXISCQTUSER[66]) = (0, 0);
( USERCLK *> MAXISCQTUSER[67]) = (0, 0);
( USERCLK *> MAXISCQTUSER[68]) = (0, 0);
( USERCLK *> MAXISCQTUSER[69]) = (0, 0);
( USERCLK *> MAXISCQTUSER[6]) = (0, 0);
( USERCLK *> MAXISCQTUSER[70]) = (0, 0);
( USERCLK *> MAXISCQTUSER[71]) = (0, 0);
( USERCLK *> MAXISCQTUSER[72]) = (0, 0);
( USERCLK *> MAXISCQTUSER[73]) = (0, 0);
( USERCLK *> MAXISCQTUSER[74]) = (0, 0);
( USERCLK *> MAXISCQTUSER[75]) = (0, 0);
( USERCLK *> MAXISCQTUSER[76]) = (0, 0);
( USERCLK *> MAXISCQTUSER[77]) = (0, 0);
( USERCLK *> MAXISCQTUSER[78]) = (0, 0);
( USERCLK *> MAXISCQTUSER[79]) = (0, 0);
( USERCLK *> MAXISCQTUSER[7]) = (0, 0);
( USERCLK *> MAXISCQTUSER[80]) = (0, 0);
( USERCLK *> MAXISCQTUSER[81]) = (0, 0);
( USERCLK *> MAXISCQTUSER[82]) = (0, 0);
( USERCLK *> MAXISCQTUSER[83]) = (0, 0);
( USERCLK *> MAXISCQTUSER[84]) = (0, 0);
( USERCLK *> MAXISCQTUSER[8]) = (0, 0);
( USERCLK *> MAXISCQTUSER[9]) = (0, 0);
( USERCLK *> MAXISCQTVALID) = (0, 0);
( USERCLK *> MAXISRCTDATA[0]) = (0, 0);
( USERCLK *> MAXISRCTDATA[100]) = (0, 0);
( USERCLK *> MAXISRCTDATA[101]) = (0, 0);
( USERCLK *> MAXISRCTDATA[102]) = (0, 0);
( USERCLK *> MAXISRCTDATA[103]) = (0, 0);
( USERCLK *> MAXISRCTDATA[104]) = (0, 0);
( USERCLK *> MAXISRCTDATA[105]) = (0, 0);
( USERCLK *> MAXISRCTDATA[106]) = (0, 0);
( USERCLK *> MAXISRCTDATA[107]) = (0, 0);
( USERCLK *> MAXISRCTDATA[108]) = (0, 0);
( USERCLK *> MAXISRCTDATA[109]) = (0, 0);
( USERCLK *> MAXISRCTDATA[10]) = (0, 0);
( USERCLK *> MAXISRCTDATA[110]) = (0, 0);
( USERCLK *> MAXISRCTDATA[111]) = (0, 0);
( USERCLK *> MAXISRCTDATA[112]) = (0, 0);
( USERCLK *> MAXISRCTDATA[113]) = (0, 0);
( USERCLK *> MAXISRCTDATA[114]) = (0, 0);
( USERCLK *> MAXISRCTDATA[115]) = (0, 0);
( USERCLK *> MAXISRCTDATA[116]) = (0, 0);
( USERCLK *> MAXISRCTDATA[117]) = (0, 0);
( USERCLK *> MAXISRCTDATA[118]) = (0, 0);
( USERCLK *> MAXISRCTDATA[119]) = (0, 0);
( USERCLK *> MAXISRCTDATA[11]) = (0, 0);
( USERCLK *> MAXISRCTDATA[120]) = (0, 0);
( USERCLK *> MAXISRCTDATA[121]) = (0, 0);
( USERCLK *> MAXISRCTDATA[122]) = (0, 0);
( USERCLK *> MAXISRCTDATA[123]) = (0, 0);
( USERCLK *> MAXISRCTDATA[124]) = (0, 0);
( USERCLK *> MAXISRCTDATA[125]) = (0, 0);
( USERCLK *> MAXISRCTDATA[126]) = (0, 0);
( USERCLK *> MAXISRCTDATA[127]) = (0, 0);
( USERCLK *> MAXISRCTDATA[128]) = (0, 0);
( USERCLK *> MAXISRCTDATA[129]) = (0, 0);
( USERCLK *> MAXISRCTDATA[12]) = (0, 0);
( USERCLK *> MAXISRCTDATA[130]) = (0, 0);
( USERCLK *> MAXISRCTDATA[131]) = (0, 0);
( USERCLK *> MAXISRCTDATA[132]) = (0, 0);
( USERCLK *> MAXISRCTDATA[133]) = (0, 0);
( USERCLK *> MAXISRCTDATA[134]) = (0, 0);
( USERCLK *> MAXISRCTDATA[135]) = (0, 0);
( USERCLK *> MAXISRCTDATA[136]) = (0, 0);
( USERCLK *> MAXISRCTDATA[137]) = (0, 0);
( USERCLK *> MAXISRCTDATA[138]) = (0, 0);
( USERCLK *> MAXISRCTDATA[139]) = (0, 0);
( USERCLK *> MAXISRCTDATA[13]) = (0, 0);
( USERCLK *> MAXISRCTDATA[140]) = (0, 0);
( USERCLK *> MAXISRCTDATA[141]) = (0, 0);
( USERCLK *> MAXISRCTDATA[142]) = (0, 0);
( USERCLK *> MAXISRCTDATA[143]) = (0, 0);
( USERCLK *> MAXISRCTDATA[144]) = (0, 0);
( USERCLK *> MAXISRCTDATA[145]) = (0, 0);
( USERCLK *> MAXISRCTDATA[146]) = (0, 0);
( USERCLK *> MAXISRCTDATA[147]) = (0, 0);
( USERCLK *> MAXISRCTDATA[148]) = (0, 0);
( USERCLK *> MAXISRCTDATA[149]) = (0, 0);
( USERCLK *> MAXISRCTDATA[14]) = (0, 0);
( USERCLK *> MAXISRCTDATA[150]) = (0, 0);
( USERCLK *> MAXISRCTDATA[151]) = (0, 0);
( USERCLK *> MAXISRCTDATA[152]) = (0, 0);
( USERCLK *> MAXISRCTDATA[153]) = (0, 0);
( USERCLK *> MAXISRCTDATA[154]) = (0, 0);
( USERCLK *> MAXISRCTDATA[155]) = (0, 0);
( USERCLK *> MAXISRCTDATA[156]) = (0, 0);
( USERCLK *> MAXISRCTDATA[157]) = (0, 0);
( USERCLK *> MAXISRCTDATA[158]) = (0, 0);
( USERCLK *> MAXISRCTDATA[159]) = (0, 0);
( USERCLK *> MAXISRCTDATA[15]) = (0, 0);
( USERCLK *> MAXISRCTDATA[160]) = (0, 0);
( USERCLK *> MAXISRCTDATA[161]) = (0, 0);
( USERCLK *> MAXISRCTDATA[162]) = (0, 0);
( USERCLK *> MAXISRCTDATA[163]) = (0, 0);
( USERCLK *> MAXISRCTDATA[164]) = (0, 0);
( USERCLK *> MAXISRCTDATA[165]) = (0, 0);
( USERCLK *> MAXISRCTDATA[166]) = (0, 0);
( USERCLK *> MAXISRCTDATA[167]) = (0, 0);
( USERCLK *> MAXISRCTDATA[168]) = (0, 0);
( USERCLK *> MAXISRCTDATA[169]) = (0, 0);
( USERCLK *> MAXISRCTDATA[16]) = (0, 0);
( USERCLK *> MAXISRCTDATA[170]) = (0, 0);
( USERCLK *> MAXISRCTDATA[171]) = (0, 0);
( USERCLK *> MAXISRCTDATA[172]) = (0, 0);
( USERCLK *> MAXISRCTDATA[173]) = (0, 0);
( USERCLK *> MAXISRCTDATA[174]) = (0, 0);
( USERCLK *> MAXISRCTDATA[175]) = (0, 0);
( USERCLK *> MAXISRCTDATA[176]) = (0, 0);
( USERCLK *> MAXISRCTDATA[177]) = (0, 0);
( USERCLK *> MAXISRCTDATA[178]) = (0, 0);
( USERCLK *> MAXISRCTDATA[179]) = (0, 0);
( USERCLK *> MAXISRCTDATA[17]) = (0, 0);
( USERCLK *> MAXISRCTDATA[180]) = (0, 0);
( USERCLK *> MAXISRCTDATA[181]) = (0, 0);
( USERCLK *> MAXISRCTDATA[182]) = (0, 0);
( USERCLK *> MAXISRCTDATA[183]) = (0, 0);
( USERCLK *> MAXISRCTDATA[184]) = (0, 0);
( USERCLK *> MAXISRCTDATA[185]) = (0, 0);
( USERCLK *> MAXISRCTDATA[186]) = (0, 0);
( USERCLK *> MAXISRCTDATA[187]) = (0, 0);
( USERCLK *> MAXISRCTDATA[188]) = (0, 0);
( USERCLK *> MAXISRCTDATA[189]) = (0, 0);
( USERCLK *> MAXISRCTDATA[18]) = (0, 0);
( USERCLK *> MAXISRCTDATA[190]) = (0, 0);
( USERCLK *> MAXISRCTDATA[191]) = (0, 0);
( USERCLK *> MAXISRCTDATA[192]) = (0, 0);
( USERCLK *> MAXISRCTDATA[193]) = (0, 0);
( USERCLK *> MAXISRCTDATA[194]) = (0, 0);
( USERCLK *> MAXISRCTDATA[195]) = (0, 0);
( USERCLK *> MAXISRCTDATA[196]) = (0, 0);
( USERCLK *> MAXISRCTDATA[197]) = (0, 0);
( USERCLK *> MAXISRCTDATA[198]) = (0, 0);
( USERCLK *> MAXISRCTDATA[199]) = (0, 0);
( USERCLK *> MAXISRCTDATA[19]) = (0, 0);
( USERCLK *> MAXISRCTDATA[1]) = (0, 0);
( USERCLK *> MAXISRCTDATA[200]) = (0, 0);
( USERCLK *> MAXISRCTDATA[201]) = (0, 0);
( USERCLK *> MAXISRCTDATA[202]) = (0, 0);
( USERCLK *> MAXISRCTDATA[203]) = (0, 0);
( USERCLK *> MAXISRCTDATA[204]) = (0, 0);
( USERCLK *> MAXISRCTDATA[205]) = (0, 0);
( USERCLK *> MAXISRCTDATA[206]) = (0, 0);
( USERCLK *> MAXISRCTDATA[207]) = (0, 0);
( USERCLK *> MAXISRCTDATA[208]) = (0, 0);
( USERCLK *> MAXISRCTDATA[209]) = (0, 0);
( USERCLK *> MAXISRCTDATA[20]) = (0, 0);
( USERCLK *> MAXISRCTDATA[210]) = (0, 0);
( USERCLK *> MAXISRCTDATA[211]) = (0, 0);
( USERCLK *> MAXISRCTDATA[212]) = (0, 0);
( USERCLK *> MAXISRCTDATA[213]) = (0, 0);
( USERCLK *> MAXISRCTDATA[214]) = (0, 0);
( USERCLK *> MAXISRCTDATA[215]) = (0, 0);
( USERCLK *> MAXISRCTDATA[216]) = (0, 0);
( USERCLK *> MAXISRCTDATA[217]) = (0, 0);
( USERCLK *> MAXISRCTDATA[218]) = (0, 0);
( USERCLK *> MAXISRCTDATA[219]) = (0, 0);
( USERCLK *> MAXISRCTDATA[21]) = (0, 0);
( USERCLK *> MAXISRCTDATA[220]) = (0, 0);
( USERCLK *> MAXISRCTDATA[221]) = (0, 0);
( USERCLK *> MAXISRCTDATA[222]) = (0, 0);
( USERCLK *> MAXISRCTDATA[223]) = (0, 0);
( USERCLK *> MAXISRCTDATA[224]) = (0, 0);
( USERCLK *> MAXISRCTDATA[225]) = (0, 0);
( USERCLK *> MAXISRCTDATA[226]) = (0, 0);
( USERCLK *> MAXISRCTDATA[227]) = (0, 0);
( USERCLK *> MAXISRCTDATA[228]) = (0, 0);
( USERCLK *> MAXISRCTDATA[229]) = (0, 0);
( USERCLK *> MAXISRCTDATA[22]) = (0, 0);
( USERCLK *> MAXISRCTDATA[230]) = (0, 0);
( USERCLK *> MAXISRCTDATA[231]) = (0, 0);
( USERCLK *> MAXISRCTDATA[232]) = (0, 0);
( USERCLK *> MAXISRCTDATA[233]) = (0, 0);
( USERCLK *> MAXISRCTDATA[234]) = (0, 0);
( USERCLK *> MAXISRCTDATA[235]) = (0, 0);
( USERCLK *> MAXISRCTDATA[236]) = (0, 0);
( USERCLK *> MAXISRCTDATA[237]) = (0, 0);
( USERCLK *> MAXISRCTDATA[238]) = (0, 0);
( USERCLK *> MAXISRCTDATA[239]) = (0, 0);
( USERCLK *> MAXISRCTDATA[23]) = (0, 0);
( USERCLK *> MAXISRCTDATA[240]) = (0, 0);
( USERCLK *> MAXISRCTDATA[241]) = (0, 0);
( USERCLK *> MAXISRCTDATA[242]) = (0, 0);
( USERCLK *> MAXISRCTDATA[243]) = (0, 0);
( USERCLK *> MAXISRCTDATA[244]) = (0, 0);
( USERCLK *> MAXISRCTDATA[245]) = (0, 0);
( USERCLK *> MAXISRCTDATA[246]) = (0, 0);
( USERCLK *> MAXISRCTDATA[247]) = (0, 0);
( USERCLK *> MAXISRCTDATA[248]) = (0, 0);
( USERCLK *> MAXISRCTDATA[249]) = (0, 0);
( USERCLK *> MAXISRCTDATA[24]) = (0, 0);
( USERCLK *> MAXISRCTDATA[250]) = (0, 0);
( USERCLK *> MAXISRCTDATA[251]) = (0, 0);
( USERCLK *> MAXISRCTDATA[252]) = (0, 0);
( USERCLK *> MAXISRCTDATA[253]) = (0, 0);
( USERCLK *> MAXISRCTDATA[254]) = (0, 0);
( USERCLK *> MAXISRCTDATA[255]) = (0, 0);
( USERCLK *> MAXISRCTDATA[25]) = (0, 0);
( USERCLK *> MAXISRCTDATA[26]) = (0, 0);
( USERCLK *> MAXISRCTDATA[27]) = (0, 0);
( USERCLK *> MAXISRCTDATA[28]) = (0, 0);
( USERCLK *> MAXISRCTDATA[29]) = (0, 0);
( USERCLK *> MAXISRCTDATA[2]) = (0, 0);
( USERCLK *> MAXISRCTDATA[30]) = (0, 0);
( USERCLK *> MAXISRCTDATA[31]) = (0, 0);
( USERCLK *> MAXISRCTDATA[32]) = (0, 0);
( USERCLK *> MAXISRCTDATA[33]) = (0, 0);
( USERCLK *> MAXISRCTDATA[34]) = (0, 0);
( USERCLK *> MAXISRCTDATA[35]) = (0, 0);
( USERCLK *> MAXISRCTDATA[36]) = (0, 0);
( USERCLK *> MAXISRCTDATA[37]) = (0, 0);
( USERCLK *> MAXISRCTDATA[38]) = (0, 0);
( USERCLK *> MAXISRCTDATA[39]) = (0, 0);
( USERCLK *> MAXISRCTDATA[3]) = (0, 0);
( USERCLK *> MAXISRCTDATA[40]) = (0, 0);
( USERCLK *> MAXISRCTDATA[41]) = (0, 0);
( USERCLK *> MAXISRCTDATA[42]) = (0, 0);
( USERCLK *> MAXISRCTDATA[43]) = (0, 0);
( USERCLK *> MAXISRCTDATA[44]) = (0, 0);
( USERCLK *> MAXISRCTDATA[45]) = (0, 0);
( USERCLK *> MAXISRCTDATA[46]) = (0, 0);
( USERCLK *> MAXISRCTDATA[47]) = (0, 0);
( USERCLK *> MAXISRCTDATA[48]) = (0, 0);
( USERCLK *> MAXISRCTDATA[49]) = (0, 0);
( USERCLK *> MAXISRCTDATA[4]) = (0, 0);
( USERCLK *> MAXISRCTDATA[50]) = (0, 0);
( USERCLK *> MAXISRCTDATA[51]) = (0, 0);
( USERCLK *> MAXISRCTDATA[52]) = (0, 0);
( USERCLK *> MAXISRCTDATA[53]) = (0, 0);
( USERCLK *> MAXISRCTDATA[54]) = (0, 0);
( USERCLK *> MAXISRCTDATA[55]) = (0, 0);
( USERCLK *> MAXISRCTDATA[56]) = (0, 0);
( USERCLK *> MAXISRCTDATA[57]) = (0, 0);
( USERCLK *> MAXISRCTDATA[58]) = (0, 0);
( USERCLK *> MAXISRCTDATA[59]) = (0, 0);
( USERCLK *> MAXISRCTDATA[5]) = (0, 0);
( USERCLK *> MAXISRCTDATA[60]) = (0, 0);
( USERCLK *> MAXISRCTDATA[61]) = (0, 0);
( USERCLK *> MAXISRCTDATA[62]) = (0, 0);
( USERCLK *> MAXISRCTDATA[63]) = (0, 0);
( USERCLK *> MAXISRCTDATA[64]) = (0, 0);
( USERCLK *> MAXISRCTDATA[65]) = (0, 0);
( USERCLK *> MAXISRCTDATA[66]) = (0, 0);
( USERCLK *> MAXISRCTDATA[67]) = (0, 0);
( USERCLK *> MAXISRCTDATA[68]) = (0, 0);
( USERCLK *> MAXISRCTDATA[69]) = (0, 0);
( USERCLK *> MAXISRCTDATA[6]) = (0, 0);
( USERCLK *> MAXISRCTDATA[70]) = (0, 0);
( USERCLK *> MAXISRCTDATA[71]) = (0, 0);
( USERCLK *> MAXISRCTDATA[72]) = (0, 0);
( USERCLK *> MAXISRCTDATA[73]) = (0, 0);
( USERCLK *> MAXISRCTDATA[74]) = (0, 0);
( USERCLK *> MAXISRCTDATA[75]) = (0, 0);
( USERCLK *> MAXISRCTDATA[76]) = (0, 0);
( USERCLK *> MAXISRCTDATA[77]) = (0, 0);
( USERCLK *> MAXISRCTDATA[78]) = (0, 0);
( USERCLK *> MAXISRCTDATA[79]) = (0, 0);
( USERCLK *> MAXISRCTDATA[7]) = (0, 0);
( USERCLK *> MAXISRCTDATA[80]) = (0, 0);
( USERCLK *> MAXISRCTDATA[81]) = (0, 0);
( USERCLK *> MAXISRCTDATA[82]) = (0, 0);
( USERCLK *> MAXISRCTDATA[83]) = (0, 0);
( USERCLK *> MAXISRCTDATA[84]) = (0, 0);
( USERCLK *> MAXISRCTDATA[85]) = (0, 0);
( USERCLK *> MAXISRCTDATA[86]) = (0, 0);
( USERCLK *> MAXISRCTDATA[87]) = (0, 0);
( USERCLK *> MAXISRCTDATA[88]) = (0, 0);
( USERCLK *> MAXISRCTDATA[89]) = (0, 0);
( USERCLK *> MAXISRCTDATA[8]) = (0, 0);
( USERCLK *> MAXISRCTDATA[90]) = (0, 0);
( USERCLK *> MAXISRCTDATA[91]) = (0, 0);
( USERCLK *> MAXISRCTDATA[92]) = (0, 0);
( USERCLK *> MAXISRCTDATA[93]) = (0, 0);
( USERCLK *> MAXISRCTDATA[94]) = (0, 0);
( USERCLK *> MAXISRCTDATA[95]) = (0, 0);
( USERCLK *> MAXISRCTDATA[96]) = (0, 0);
( USERCLK *> MAXISRCTDATA[97]) = (0, 0);
( USERCLK *> MAXISRCTDATA[98]) = (0, 0);
( USERCLK *> MAXISRCTDATA[99]) = (0, 0);
( USERCLK *> MAXISRCTDATA[9]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[0]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[1]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[2]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[3]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[4]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[5]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[6]) = (0, 0);
( USERCLK *> MAXISRCTKEEP[7]) = (0, 0);
( USERCLK *> MAXISRCTLAST) = (0, 0);
( USERCLK *> MAXISRCTUSER[0]) = (0, 0);
( USERCLK *> MAXISRCTUSER[10]) = (0, 0);
( USERCLK *> MAXISRCTUSER[11]) = (0, 0);
( USERCLK *> MAXISRCTUSER[12]) = (0, 0);
( USERCLK *> MAXISRCTUSER[13]) = (0, 0);
( USERCLK *> MAXISRCTUSER[14]) = (0, 0);
( USERCLK *> MAXISRCTUSER[15]) = (0, 0);
( USERCLK *> MAXISRCTUSER[16]) = (0, 0);
( USERCLK *> MAXISRCTUSER[17]) = (0, 0);
( USERCLK *> MAXISRCTUSER[18]) = (0, 0);
( USERCLK *> MAXISRCTUSER[19]) = (0, 0);
( USERCLK *> MAXISRCTUSER[1]) = (0, 0);
( USERCLK *> MAXISRCTUSER[20]) = (0, 0);
( USERCLK *> MAXISRCTUSER[21]) = (0, 0);
( USERCLK *> MAXISRCTUSER[22]) = (0, 0);
( USERCLK *> MAXISRCTUSER[23]) = (0, 0);
( USERCLK *> MAXISRCTUSER[24]) = (0, 0);
( USERCLK *> MAXISRCTUSER[25]) = (0, 0);
( USERCLK *> MAXISRCTUSER[26]) = (0, 0);
( USERCLK *> MAXISRCTUSER[27]) = (0, 0);
( USERCLK *> MAXISRCTUSER[28]) = (0, 0);
( USERCLK *> MAXISRCTUSER[29]) = (0, 0);
( USERCLK *> MAXISRCTUSER[2]) = (0, 0);
( USERCLK *> MAXISRCTUSER[30]) = (0, 0);
( USERCLK *> MAXISRCTUSER[31]) = (0, 0);
( USERCLK *> MAXISRCTUSER[32]) = (0, 0);
( USERCLK *> MAXISRCTUSER[33]) = (0, 0);
( USERCLK *> MAXISRCTUSER[34]) = (0, 0);
( USERCLK *> MAXISRCTUSER[35]) = (0, 0);
( USERCLK *> MAXISRCTUSER[36]) = (0, 0);
( USERCLK *> MAXISRCTUSER[37]) = (0, 0);
( USERCLK *> MAXISRCTUSER[38]) = (0, 0);
( USERCLK *> MAXISRCTUSER[39]) = (0, 0);
( USERCLK *> MAXISRCTUSER[3]) = (0, 0);
( USERCLK *> MAXISRCTUSER[40]) = (0, 0);
( USERCLK *> MAXISRCTUSER[41]) = (0, 0);
( USERCLK *> MAXISRCTUSER[42]) = (0, 0);
( USERCLK *> MAXISRCTUSER[43]) = (0, 0);
( USERCLK *> MAXISRCTUSER[44]) = (0, 0);
( USERCLK *> MAXISRCTUSER[45]) = (0, 0);
( USERCLK *> MAXISRCTUSER[46]) = (0, 0);
( USERCLK *> MAXISRCTUSER[47]) = (0, 0);
( USERCLK *> MAXISRCTUSER[48]) = (0, 0);
( USERCLK *> MAXISRCTUSER[49]) = (0, 0);
( USERCLK *> MAXISRCTUSER[4]) = (0, 0);
( USERCLK *> MAXISRCTUSER[50]) = (0, 0);
( USERCLK *> MAXISRCTUSER[51]) = (0, 0);
( USERCLK *> MAXISRCTUSER[52]) = (0, 0);
( USERCLK *> MAXISRCTUSER[53]) = (0, 0);
( USERCLK *> MAXISRCTUSER[54]) = (0, 0);
( USERCLK *> MAXISRCTUSER[55]) = (0, 0);
( USERCLK *> MAXISRCTUSER[56]) = (0, 0);
( USERCLK *> MAXISRCTUSER[57]) = (0, 0);
( USERCLK *> MAXISRCTUSER[58]) = (0, 0);
( USERCLK *> MAXISRCTUSER[59]) = (0, 0);
( USERCLK *> MAXISRCTUSER[5]) = (0, 0);
( USERCLK *> MAXISRCTUSER[60]) = (0, 0);
( USERCLK *> MAXISRCTUSER[61]) = (0, 0);
( USERCLK *> MAXISRCTUSER[62]) = (0, 0);
( USERCLK *> MAXISRCTUSER[63]) = (0, 0);
( USERCLK *> MAXISRCTUSER[64]) = (0, 0);
( USERCLK *> MAXISRCTUSER[65]) = (0, 0);
( USERCLK *> MAXISRCTUSER[66]) = (0, 0);
( USERCLK *> MAXISRCTUSER[67]) = (0, 0);
( USERCLK *> MAXISRCTUSER[68]) = (0, 0);
( USERCLK *> MAXISRCTUSER[69]) = (0, 0);
( USERCLK *> MAXISRCTUSER[6]) = (0, 0);
( USERCLK *> MAXISRCTUSER[70]) = (0, 0);
( USERCLK *> MAXISRCTUSER[71]) = (0, 0);
( USERCLK *> MAXISRCTUSER[72]) = (0, 0);
( USERCLK *> MAXISRCTUSER[73]) = (0, 0);
( USERCLK *> MAXISRCTUSER[74]) = (0, 0);
( USERCLK *> MAXISRCTUSER[7]) = (0, 0);
( USERCLK *> MAXISRCTUSER[8]) = (0, 0);
( USERCLK *> MAXISRCTUSER[9]) = (0, 0);
( USERCLK *> MAXISRCTVALID) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[0]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[1]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[2]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[3]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[4]) = (0, 0);
( USERCLK *> PCIECQNPREQCOUNT[5]) = (0, 0);
( USERCLK *> PCIERQSEQNUMVLD) = (0, 0);
( USERCLK *> PCIERQSEQNUM[0]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[1]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[2]) = (0, 0);
( USERCLK *> PCIERQSEQNUM[3]) = (0, 0);
( USERCLK *> PCIERQTAGAV[0]) = (0, 0);
( USERCLK *> PCIERQTAGAV[1]) = (0, 0);
( USERCLK *> PCIERQTAGVLD) = (0, 0);
( USERCLK *> PCIERQTAG[0]) = (0, 0);
( USERCLK *> PCIERQTAG[1]) = (0, 0);
( USERCLK *> PCIERQTAG[2]) = (0, 0);
( USERCLK *> PCIERQTAG[3]) = (0, 0);
( USERCLK *> PCIERQTAG[4]) = (0, 0);
( USERCLK *> PCIERQTAG[5]) = (0, 0);
( USERCLK *> PCIETFCNPDAV[0]) = (0, 0);
( USERCLK *> PCIETFCNPDAV[1]) = (0, 0);
( USERCLK *> PCIETFCNPHAV[0]) = (0, 0);
( USERCLK *> PCIETFCNPHAV[1]) = (0, 0);
( USERCLK *> SAXISCCTREADY[0]) = (0, 0);
( USERCLK *> SAXISCCTREADY[1]) = (0, 0);
( USERCLK *> SAXISCCTREADY[2]) = (0, 0);
( USERCLK *> SAXISCCTREADY[3]) = (0, 0);
( USERCLK *> SAXISRQTREADY[0]) = (0, 0);
( USERCLK *> SAXISRQTREADY[1]) = (0, 0);
( USERCLK *> SAXISRQTREADY[2]) = (0, 0);
( USERCLK *> SAXISRQTREADY[3]) = (0, 0);
specparam PATHPULSE$ = 0;
endspecify
endmodule
`endcelldefine
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : pcie_7x_0_core_top_pcie2_top.v
// Version : 3.0
//--------------------------------------------------------------------------------
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module pcie_7x_0_core_top_pcie2_top # (
parameter c_component_name ="pcie_7x_v3_0",
parameter dev_port_type ="0000",
parameter c_dev_port_type ="0",
parameter c_header_type ="00",
parameter c_upstream_facing ="TRUE",
parameter max_lnk_wdt = "000100",
parameter max_lnk_spd = "1",
parameter c_gen1 = 1'b0,
parameter c_int_width = 64,
parameter pci_exp_int_freq = 2,
parameter c_pcie_fast_config = 0,
parameter bar_0 = "FFFFFF80",
parameter bar_1 = "00000000",
parameter bar_2 = "00000000",
parameter bar_3 = "00000000",
parameter bar_4 = "00000000",
parameter bar_5 = "00000000",
parameter xrom_bar = "00000000",
parameter cost_table = 1,
parameter ven_id = "10EE",
parameter dev_id = "7028",
parameter rev_id = "00",
parameter subsys_ven_id = "10EE",
parameter subsys_id = "0007",
parameter class_code = "058000",
parameter cardbus_cis_ptr = "00000000",
parameter cap_ver = "2",
parameter c_pcie_cap_slot_implemented = "FALSE",
parameter mps = "010",
parameter cmps = "2",
parameter ext_tag_fld_sup = "FALSE",
parameter c_dev_control_ext_tag_default = "FALSE",
parameter phantm_func_sup = "00",
parameter c_phantom_functions = "0",
parameter ep_l0s_accpt_lat = "000",
parameter c_ep_l0s_accpt_lat = "0",
parameter ep_l1_accpt_lat = "111",
parameter c_ep_l1_accpt_lat = "7",
parameter c_cpl_timeout_disable_sup = "FALSE",
parameter c_cpl_timeout_range = "0010",
parameter c_cpl_timeout_ranges_sup = "2",
parameter c_buf_opt_bma = "TRUE",
parameter c_perf_level_high = "TRUE",
parameter c_tx_last_tlp = "29",
parameter c_rx_ram_limit = "7FF",
parameter c_fc_ph = "32",
parameter c_fc_pd = "437",
parameter c_fc_nph = "12",
parameter c_fc_npd = "24",
parameter c_fc_cplh = "36",
parameter c_fc_cpld = "461",
parameter c_cpl_inf = "TRUE",
parameter c_cpl_infinite = "TRUE",
parameter c_surprise_dn_err_cap = "FALSE",
parameter c_dll_lnk_actv_cap = "FALSE",
parameter c_lnk_bndwdt_notif = "FALSE",
parameter c_external_clocking = "TRUE",
parameter c_trgt_lnk_spd = "0",
parameter c_hw_auton_spd_disable = "FALSE",
parameter c_de_emph = "FALSE",
parameter slot_clk = "TRUE",
parameter c_rcb = "0",
parameter c_root_cap_crs = "FALSE",
parameter c_slot_cap_attn_butn = "FALSE",
parameter c_slot_cap_attn_ind = "FALSE",
parameter c_slot_cap_pwr_ctrl = "FALSE",
parameter c_slot_cap_pwr_ind = "FALSE",
parameter c_slot_cap_hotplug_surprise = "FALSE",
parameter c_slot_cap_hotplug_cap = "FALSE",
parameter c_slot_cap_mrl = "FALSE",
parameter c_slot_cap_elec_interlock = "FALSE",
parameter c_slot_cap_no_cmd_comp_sup = "FALSE",
parameter c_slot_cap_pwr_limit_value = "0",
parameter c_slot_cap_pwr_limit_scale = "0",
parameter c_slot_cap_physical_slot_num = "0",
parameter intx = "TRUE",
parameter int_pin = "1",
parameter c_msi_cap_on = "TRUE",
parameter c_pm_cap_next_ptr = "48",
parameter c_msi_64b_addr = "TRUE",
parameter c_msi = "0",
parameter c_msi_mult_msg_extn = "0",
parameter c_msi_per_vctr_mask_cap = "FALSE",
parameter c_msix_cap_on = "FALSE",
parameter c_msix_next_ptr = "00",
parameter c_pcie_cap_next_ptr = "00",
parameter c_msix_table_size = "000",
parameter c_msix_table_offset = "0",
parameter c_msix_table_bir = "0",
parameter c_msix_pba_offset = "0",
parameter c_msix_pba_bir = "0",
parameter dsi = "0",
parameter c_dsi_bool = "FALSE",
parameter d1_sup = "0",
parameter c_d1_support = "FALSE",
parameter d2_sup = "0",
parameter c_d2_support = "FALSE",
parameter pme_sup = "0F",
parameter c_pme_support = "0F",
parameter no_soft_rst = "TRUE",
parameter pwr_con_d0_state = "00",
parameter con_scl_fctr_d0_state = "0",
parameter pwr_con_d1_state = "00",
parameter con_scl_fctr_d1_state = "0",
parameter pwr_con_d2_state = "00",
parameter con_scl_fctr_d2_state = "0",
parameter pwr_con_d3_state = "00",
parameter con_scl_fctr_d3_state = "0",
parameter pwr_dis_d0_state = "00",
parameter dis_scl_fctr_d0_state = "0",
parameter pwr_dis_d1_state = "00",
parameter dis_scl_fctr_d1_state = "0",
parameter pwr_dis_d2_state = "00",
parameter dis_scl_fctr_d2_state = "0",
parameter pwr_dis_d3_state = "00",
parameter dis_scl_fctr_d3_state = "0",
parameter c_dsn_cap_enabled = "TRUE",
parameter c_dsn_base_ptr = "100",
parameter c_vc_cap_enabled = "FALSE",
parameter c_vc_base_ptr = "000",
parameter c_vc_cap_reject_snoop = "FALSE",
parameter c_vsec_cap_enabled = "FALSE",
parameter c_vsec_base_ptr = "000",
parameter c_vsec_next_ptr = "000",
parameter c_dsn_next_ptr = "000",
parameter c_vc_next_ptr = "000",
parameter c_pci_cfg_space_addr = "3F",
parameter c_ext_pci_cfg_space_addr = "3FF",
parameter c_last_cfg_dw = "10C",
parameter c_enable_msg_route = "00000000000",
parameter bram_lat = "0",
parameter c_rx_raddr_lat = "0",
parameter c_rx_rdata_lat = "2",
parameter c_rx_write_lat = "0",
parameter c_tx_raddr_lat = "0",
parameter c_tx_rdata_lat = "2",
parameter c_tx_write_lat = "0",
parameter c_ll_ack_timeout_enable = "FALSE",
parameter c_ll_ack_timeout_function = "0",
parameter c_ll_ack_timeout = "0000",
parameter c_ll_replay_timeout_enable = "FALSE",
parameter c_ll_replay_timeout_func = "1",
parameter c_ll_replay_timeout = "0000",
parameter c_dis_lane_reverse = "TRUE",
parameter c_upconfig_capable = "TRUE",
parameter c_disable_scrambling = "FALSE",
parameter c_disable_tx_aspm_l0s = "0",
parameter c_rev_gt_order = "FALSE",
parameter c_pcie_dbg_ports = "FALSE",
parameter pci_exp_ref_freq = "0",
parameter c_xlnx_ref_board = "NONE",
parameter c_pcie_blk_locn = "0",
parameter c_ur_atomic = "FALSE",
parameter c_dev_cap2_atomicop32_completer_supported = "FALSE",
parameter c_dev_cap2_atomicop64_completer_supported = "FALSE",
parameter c_dev_cap2_cas128_completer_supported = "FALSE",
parameter c_dev_cap2_tph_completer_supported = "00",
parameter c_dev_cap2_ari_forwarding_supported = "FALSE",
parameter c_dev_cap2_atomicop_routing_supported = "FALSE",
parameter c_link_cap_aspm_optionality = "FALSE",
parameter c_aer_cap_on = "FALSE",
parameter c_aer_base_ptr = "000",
parameter c_aer_cap_nextptr = "000",
parameter c_aer_cap_ecrc_check_capable = "FALSE",
parameter c_aer_cap_multiheader = "FALSE",
parameter c_aer_cap_permit_rooterr_update = "FALSE",
parameter c_rbar_cap_on = "FALSE",
parameter c_rbar_base_ptr = "000",
parameter c_rbar_cap_nextptr = "000",
parameter c_rbar_num = "0",
parameter c_rbar_cap_sup0 = "00001",
parameter c_rbar_cap_index0 = "0",
parameter c_rbar_cap_control_encodedbar0 = "00",
parameter c_rbar_cap_sup1 = "00001",
parameter c_rbar_cap_index1 = "0",
parameter c_rbar_cap_control_encodedbar1 = "00",
parameter c_rbar_cap_sup2 = "00001",
parameter c_rbar_cap_index2 = "0",
parameter c_rbar_cap_control_encodedbar2 = "00",
parameter c_rbar_cap_sup3 = "00001",
parameter c_rbar_cap_index3 = "0",
parameter c_rbar_cap_control_encodedbar3 = "00",
parameter c_rbar_cap_sup4 = "00001",
parameter c_rbar_cap_index4 = "0",
parameter c_rbar_cap_control_encodedbar4 = "00",
parameter c_rbar_cap_sup5 = "00001",
parameter c_rbar_cap_index5 = "0",
parameter c_rbar_cap_control_encodedbar5 = "00",
parameter c_recrc_check = "0",
parameter c_recrc_check_trim = "FALSE",
parameter c_disable_rx_poisoned_resp = "FALSE",
parameter c_trn_np_fc = "TRUE",
parameter c_ur_inv_req = "TRUE",
parameter c_ur_prs_response = "TRUE",
parameter c_silicon_rev = "1",
parameter c_aer_cap_optional_err_support = "000000",
parameter PIPE_SIM = "FALSE",
parameter PCIE_EXT_CLK = "TRUE",
parameter PCIE_EXT_GT_COMMON = "FALSE",
parameter EXT_CH_GT_DRP = "TRUE",
parameter TRANSCEIVER_CTRL_STATUS_PORTS = "FALSE",
parameter SHARED_LOGIC_IN_CORE = "FALSE",
parameter PL_INTERFACE = "TRUE",
parameter CFG_MGMT_IF = "TRUE",
parameter CFG_CTL_IF = "TRUE",
parameter CFG_STATUS_IF = "TRUE",
parameter RCV_MSG_IF = "TRUE",
parameter CFG_FC_IF = "TRUE" ,
parameter ERR_REPORTING_IF = "TRUE",
parameter c_aer_cap_ecrc_gen_capable = "FALSE",
parameter EXT_PIPE_INTERFACE = "FALSE",
parameter EXT_STARTUP_PRIMITIVE = "FALSE",
parameter integer LINK_CAP_MAX_LINK_WIDTH = 6'h8,
parameter integer C_DATA_WIDTH = 64,
parameter integer KEEP_WIDTH = C_DATA_WIDTH / 8
)
(
//----------------------------------------------------------------------------------------------------------------//
// 1. PCI Express (pci_exp) Interface //
//----------------------------------------------------------------------------------------------------------------//
// Tx
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txn,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_txp,
// Rx
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxn,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pci_exp_rxp,
//----------------------------------------------------------------------------------------------------------------//
// 2. Clock & GT COMMON Sharing Interface //
//----------------------------------------------------------------------------------------------------------------//
// Shared Logic Internal
output int_pclk_out_slave,
output int_pipe_rxusrclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_rxoutclk_out,
output int_dclk_out,
output int_userclk1_out,
output int_userclk2_out,
output int_oobclk_out,
output int_mmcm_lock_out,
output [1:0] int_qplllock_out,
output [1:0] int_qplloutclk_out,
output [1:0] int_qplloutrefclk_out,
input [(LINK_CAP_MAX_LINK_WIDTH-1):0] int_pclk_sel_slave,
// Shared Logic External - Clocks
input pipe_pclk_in,
input pipe_rxusrclk_in,
input [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_in,
input pipe_dclk_in,
input pipe_userclk1_in,
input pipe_userclk2_in,
input pipe_oobclk_in,
input pipe_mmcm_lock_in,
output pipe_txoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_rxoutclk_out,
output [(LINK_CAP_MAX_LINK_WIDTH - 1) : 0] pipe_pclk_sel_out,
output pipe_gen3_out,
// Shared Logic External - GT COMMON
input [11:0] qpll_drp_crscode,
input [17:0] qpll_drp_fsm,
input [1:0] qpll_drp_done,
input [1:0] qpll_drp_reset,
input [1:0] qpll_qplllock,
input [1:0] qpll_qplloutclk,
input [1:0] qpll_qplloutrefclk,
output qpll_qplld,
output [1:0] qpll_qpllreset,
output qpll_drp_clk,
output qpll_drp_rst_n,
output qpll_drp_ovrd,
output qpll_drp_gen3,
output qpll_drp_start,
//----------------------------------------------------------------------------------------------------------------//
// 3. AXI-S Interface //
//----------------------------------------------------------------------------------------------------------------//
// Common
output user_clk_out,
output user_reset_out,
output user_lnk_up,
output user_app_rdy,
// AXI TX
//-----------
output [5:0] tx_buf_av,
output tx_err_drop,
output tx_cfg_req,
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata,
input s_axis_tx_tvalid,
output s_axis_tx_tready,
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep,
input s_axis_tx_tlast,
input [3:0] s_axis_tx_tuser,
input tx_cfg_gnt,
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata,
output m_axis_rx_tvalid,
input m_axis_rx_tready,
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep,
output m_axis_rx_tlast,
output [21:0] m_axis_rx_tuser,
input rx_np_ok,
input rx_np_req,
// Flow Control
output [11:0] fc_cpld,
output [7:0] fc_cplh,
output [11:0] fc_npd,
output [7:0] fc_nph,
output [11:0] fc_pd,
output [7:0] fc_ph,
input [2:0] fc_sel,
//----------------------------------------------------------------------------------------------------------------//
// 4. Configuration (CFG) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
output [31:0] cfg_mgmt_do,
output cfg_mgmt_rd_wr_done,
output [15:0] cfg_status,
output [15:0] cfg_command,
output [15:0] cfg_dstatus,
output [15:0] cfg_dcommand,
output [15:0] cfg_lstatus,
output [15:0] cfg_lcommand,
output [15:0] cfg_dcommand2,
output [2:0] cfg_pcie_link_state,
output cfg_pmcsr_pme_en,
output [1:0] cfg_pmcsr_powerstate,
output cfg_pmcsr_pme_status,
output cfg_received_func_lvl_rst,
// Management Interface
input [31:0] cfg_mgmt_di,
input [3:0] cfg_mgmt_byte_en,
input [9:0] cfg_mgmt_dwaddr,
input cfg_mgmt_wr_en,
input cfg_mgmt_rd_en,
input cfg_mgmt_wr_readonly,
// Error Reporting Interface
input cfg_err_ecrc,
input cfg_err_ur,
input cfg_err_cpl_timeout,
input cfg_err_cpl_unexpect,
input cfg_err_cpl_abort,
input cfg_err_posted,
input cfg_err_cor,
input cfg_err_atomic_egress_blocked,
input cfg_err_internal_cor,
input cfg_err_malformed,
input cfg_err_mc_blocked,
input cfg_err_poisoned,
input cfg_err_norecovery,
input [47:0] cfg_err_tlp_cpl_header,
output cfg_err_cpl_rdy,
input cfg_err_locked,
input cfg_err_acs,
input cfg_err_internal_uncor,
input cfg_trn_pending,
input cfg_pm_halt_aspm_l0s,
input cfg_pm_halt_aspm_l1,
input cfg_pm_force_state_en,
input [1:0] cfg_pm_force_state,
input [63:0] cfg_dsn,
output cfg_msg_received,
output [15:0] cfg_msg_data,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
// Interrupt Interface Signals
input cfg_interrupt,
output cfg_interrupt_rdy,
input cfg_interrupt_assert,
input [7:0] cfg_interrupt_di,
output [7:0] cfg_interrupt_do,
output [2:0] cfg_interrupt_mmenable,
output cfg_interrupt_msienable,
output cfg_interrupt_msixenable,
output cfg_interrupt_msixfm,
input cfg_interrupt_stat,
input [4:0] cfg_pciecap_interrupt_msgnum,
output cfg_to_turnoff,
input cfg_turnoff_ok,
output [7:0] cfg_bus_number,
output [4:0] cfg_device_number,
output [2:0] cfg_function_number,
input cfg_pm_wake,
output cfg_msg_received_pm_as_nak,
output cfg_msg_received_setslotpowerlimit,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input cfg_pm_send_pme_to,
input [7:0] cfg_ds_bus_number,
input [4:0] cfg_ds_device_number,
input [2:0] cfg_ds_function_number,
input cfg_mgmt_wr_rw1c_as_rw,
output cfg_bridge_serr_en,
output cfg_slot_control_electromech_il_ctl_pulse,
output cfg_root_control_syserr_corr_err_en,
output cfg_root_control_syserr_non_fatal_err_en,
output cfg_root_control_syserr_fatal_err_en,
output cfg_root_control_pme_int_en,
output cfg_aer_rooterr_corr_err_reporting_en,
output cfg_aer_rooterr_non_fatal_err_reporting_en,
output cfg_aer_rooterr_fatal_err_reporting_en,
output cfg_aer_rooterr_corr_err_received,
output cfg_aer_rooterr_non_fatal_err_received,
output cfg_aer_rooterr_fatal_err_received,
output cfg_msg_received_err_cor,
output cfg_msg_received_err_non_fatal,
output cfg_msg_received_err_fatal,
output cfg_msg_received_pm_pme,
output cfg_msg_received_pme_to_ack,
output cfg_msg_received_assert_int_a,
output cfg_msg_received_assert_int_b,
output cfg_msg_received_assert_int_c,
output cfg_msg_received_assert_int_d,
output cfg_msg_received_deassert_int_a,
output cfg_msg_received_deassert_int_b,
output cfg_msg_received_deassert_int_c,
output cfg_msg_received_deassert_int_d,
//----------------------------------------------------------------------------------------------------------------//
// 5. Physical Layer Control and Status (PL) Interface //
//----------------------------------------------------------------------------------------------------------------//
//------------------------------------------------//
// EP and RP //
//------------------------------------------------//
input [1:0] pl_directed_link_change,
input [1:0] pl_directed_link_width,
input pl_directed_link_speed,
input pl_directed_link_auton,
input pl_upstream_prefer_deemph,
output pl_sel_lnk_rate,
output [1:0] pl_sel_lnk_width,
output [5:0] pl_ltssm_state,
output [1:0] pl_lane_reversal_mode,
output pl_phy_lnk_up,
output [2:0] pl_tx_pm_state,
output [1:0] pl_rx_pm_state,
output pl_link_upcfg_cap,
output pl_link_gen2_cap,
output pl_link_partner_gen2_supported,
output [2:0] pl_initial_link_width,
output pl_directed_change_done,
//------------------------------------------------//
// EP Only //
//------------------------------------------------//
output pl_received_hot_rst,
//------------------------------------------------//
// RP Only //
//------------------------------------------------//
input pl_transmit_hot_rst,
input pl_downstream_deemph_source,
//----------------------------------------------------------------------------------------------------------------//
// 6. AER interface //
//----------------------------------------------------------------------------------------------------------------//
input [127:0] cfg_err_aer_headerlog,
input [4:0] cfg_aer_interrupt_msgnum,
output cfg_err_aer_headerlog_set,
output cfg_aer_ecrc_check_en,
output cfg_aer_ecrc_gen_en,
//----------------------------------------------------------------------------------------------------------------//
// 7. VC interface //
//----------------------------------------------------------------------------------------------------------------//
output [6:0] cfg_vc_tcvc_map,
//----------------------------------------------------------------------------------------------------------------//
// 8. PCIe DRP (PCIe DRP) Interface //
//----------------------------------------------------------------------------------------------------------------//
input pcie_drp_clk,
input pcie_drp_en,
input pcie_drp_we,
input [8:0] pcie_drp_addr,
input [15:0] pcie_drp_di,
output pcie_drp_rdy,
output [15:0] pcie_drp_do,
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: STARTUP primitive Interface - only used in Tandem configurations //
//----------------------------------------------------------------------------------------------------------------//
// This input should be used when the startup block is generated exteranl to the PCI Express Core
input startup_eos_in, // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
output wire startup_cfgclk, // 1-bit output: Configuration main clock output
output wire startup_cfgmclk, // 1-bit output: Configuration internal oscillator clock output
output wire startup_eos, // 1-bit output: Active high output signal indicating the End Of Startup
output wire startup_preq, // 1-bit output: PROGRAM request to fabric output
input wire startup_clk, // 1-bit input: User start-up clock input
input wire startup_gsr, // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
input wire startup_gts, // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
input wire startup_keyclearb, // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
input wire startup_pack, // 1-bit input: PROGRAM acknowledge input
input wire startup_usrcclko, // 1-bit input: User CCLK input
input wire startup_usrcclkts, // 1-bit input: User CCLK 3-state enable input
input wire startup_usrdoneo, // 1-bit input: User DONE pin output control
input wire startup_usrdonets, // 1-bit input: User DONE 3-state enable output
//----------------------------------------------------------------------------------------------------------------//
// PCIe Fast Config: ICAP primitive Interface - only used in Tandem PCIe configuration //
//----------------------------------------------------------------------------------------------------------------//
input wire icap_clk,
input wire icap_csib,
input wire icap_rdwrb,
input wire [31:0] icap_i,
output wire [31:0] icap_o,
input [ 2:0] pipe_txprbssel,
input [ 2:0] pipe_rxprbssel,
input pipe_txprbsforceerr,
input pipe_rxprbscntreset,
input [ 2:0] pipe_loopback,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_rxprbserr,
output [4:0] pipe_rst_fsm,
output [11:0] pipe_qrst_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*5)-1:0] pipe_rate_fsm,
output [(LINK_CAP_MAX_LINK_WIDTH*6)-1:0] pipe_sync_fsm_tx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_sync_fsm_rx,
output [(LINK_CAP_MAX_LINK_WIDTH*7)-1:0] pipe_drp_fsm,
output pipe_rst_idle,
output pipe_qrst_idle,
output pipe_rate_idle,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_eyescandataerror,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxstatus,
output [(LINK_CAP_MAX_LINK_WIDTH*15)-1:0] pipe_dmonitorout,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_cpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH-1)>>2:0] pipe_qpll_lock,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxpmaresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH*3)-1:0] pipe_rxbufstatus,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txphinitdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_txdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxphaligndone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxdlysresetdone,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxsyncdone,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxdisperr,
output [(LINK_CAP_MAX_LINK_WIDTH*8)-1:0] pipe_rxnotintable,
output [(LINK_CAP_MAX_LINK_WIDTH)-1:0] pipe_rxcommadet,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] gt_ch_drp_rdy,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_0,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_1,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_2,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_3,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_4,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_5,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_6,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_7,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_8,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] pipe_debug_9,
output [31:0] pipe_debug,
//--------------Channel DRP---------------------------------
output ext_ch_gt_drpclk,
input [(LINK_CAP_MAX_LINK_WIDTH*9)-1:0] ext_ch_gt_drpaddr,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpen,
input [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdi,
input [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drpwe,
output [(LINK_CAP_MAX_LINK_WIDTH*16)-1:0] ext_ch_gt_drpdo,
output [LINK_CAP_MAX_LINK_WIDTH-1:0] ext_ch_gt_drprdy,
//----------------------------------------------------------------------------------------------------------------//
// PIPE PORTS to TOP Level For PIPE SIMULATION with 3rd Party IP/BFM/Xilinx BFM
//----------------------------------------------------------------------------------------------------------------//
input wire [ 3:0] common_commands_in,
input wire [24:0] pipe_rx_0_sigs,
input wire [24:0] pipe_rx_1_sigs,
input wire [24:0] pipe_rx_2_sigs,
input wire [24:0] pipe_rx_3_sigs,
input wire [24:0] pipe_rx_4_sigs,
input wire [24:0] pipe_rx_5_sigs,
input wire [24:0] pipe_rx_6_sigs,
input wire [24:0] pipe_rx_7_sigs,
output wire [11:0] common_commands_out,
output wire [22:0] pipe_tx_0_sigs,
output wire [22:0] pipe_tx_1_sigs,
output wire [22:0] pipe_tx_2_sigs,
output wire [22:0] pipe_tx_3_sigs,
output wire [22:0] pipe_tx_4_sigs,
output wire [22:0] pipe_tx_5_sigs,
output wire [22:0] pipe_tx_6_sigs,
output wire [22:0] pipe_tx_7_sigs,
//----------------------------------------------------------------------------------------------------------------//
input wire pipe_mmcm_rst_n, // Async | Async
input wire sys_clk,
input wire sys_rst_n
);
pcie_7x_0_core_top_core_top # (
.LINK_CAP_MAX_LINK_WIDTH (LINK_CAP_MAX_LINK_WIDTH),
.C_DATA_WIDTH (C_DATA_WIDTH),
.KEEP_WIDTH (KEEP_WIDTH)
) inst
(
.pci_exp_txn(pci_exp_txn),
.pci_exp_txp(pci_exp_txp),
.pci_exp_rxn(pci_exp_rxn),
.pci_exp_rxp(pci_exp_rxp),
.int_pclk_out_slave(int_pclk_out_slave),
.int_pipe_rxusrclk_out(int_pipe_rxusrclk_out),
.int_rxoutclk_out(int_rxoutclk_out),
.int_dclk_out(int_dclk_out),
.int_userclk1_out(int_userclk1_out),
.int_mmcm_lock_out(int_mmcm_lock_out),
.int_userclk2_out(int_userclk2_out),
.int_oobclk_out(int_oobclk_out),
.int_qplllock_out(int_qplllock_out),
.int_qplloutclk_out(int_qplloutclk_out),
.int_qplloutrefclk_out(int_qplloutrefclk_out),
.int_pclk_sel_slave(int_pclk_sel_slave),
.pipe_pclk_in(pipe_pclk_in),
.pipe_rxusrclk_in(pipe_rxusrclk_in),
.pipe_rxoutclk_in(pipe_rxoutclk_in),
.pipe_dclk_in(pipe_dclk_in),
.pipe_userclk1_in(pipe_userclk1_in),
.pipe_userclk2_in(pipe_userclk2_in),
.pipe_oobclk_in(pipe_oobclk_in),
.pipe_mmcm_lock_in(pipe_mmcm_lock_in),
.pipe_txoutclk_out(pipe_txoutclk_out),
.pipe_rxoutclk_out(pipe_rxoutclk_out),
.pipe_pclk_sel_out(pipe_pclk_sel_out),
.pipe_gen3_out(pipe_gen3_out),
.user_clk_out(user_clk_out),
.user_reset_out(user_reset_out),
.user_lnk_up(user_lnk_up),
.user_app_rdy(user_app_rdy),
.tx_buf_av(tx_buf_av),
.tx_err_drop(tx_err_drop),
.tx_cfg_req(tx_cfg_req),
.s_axis_tx_tready(s_axis_tx_tready),
.s_axis_tx_tdata(s_axis_tx_tdata),
.s_axis_tx_tkeep(s_axis_tx_tkeep),
.s_axis_tx_tuser(s_axis_tx_tuser),
.s_axis_tx_tlast(s_axis_tx_tlast),
.s_axis_tx_tvalid(s_axis_tx_tvalid),
.tx_cfg_gnt(tx_cfg_gnt),
.m_axis_rx_tdata(m_axis_rx_tdata),
.m_axis_rx_tkeep(m_axis_rx_tkeep),
.m_axis_rx_tlast(m_axis_rx_tlast),
.m_axis_rx_tvalid(m_axis_rx_tvalid),
.m_axis_rx_tready(m_axis_rx_tready),
.m_axis_rx_tuser(m_axis_rx_tuser),
.rx_np_ok(rx_np_ok),
.rx_np_req(rx_np_req),
.fc_cpld(fc_cpld),
.fc_cplh(fc_cplh),
.fc_npd(fc_npd),
.fc_nph(fc_nph),
.fc_pd(fc_pd),
.fc_ph(fc_ph),
.fc_sel(fc_sel),
.cfg_status(cfg_status),
.cfg_command(cfg_command),
.cfg_dstatus(cfg_dstatus),
.cfg_dcommand(cfg_dcommand),
.cfg_lstatus(cfg_lstatus),
.cfg_lcommand(cfg_lcommand),
.cfg_dcommand2(cfg_dcommand2),
.cfg_pcie_link_state(cfg_pcie_link_state),
.cfg_pmcsr_pme_en(cfg_pmcsr_pme_en),
.cfg_pmcsr_powerstate(cfg_pmcsr_powerstate),
.cfg_pmcsr_pme_status(cfg_pmcsr_pme_status),
.cfg_received_func_lvl_rst(cfg_received_func_lvl_rst),
.cfg_mgmt_do(cfg_mgmt_do),
.cfg_mgmt_rd_wr_done(cfg_mgmt_rd_wr_done),
.cfg_mgmt_di(cfg_mgmt_di),
.cfg_mgmt_byte_en(cfg_mgmt_byte_en),
.cfg_mgmt_dwaddr(cfg_mgmt_dwaddr),
.cfg_mgmt_wr_en(cfg_mgmt_wr_en),
.cfg_mgmt_rd_en(cfg_mgmt_rd_en),
.cfg_mgmt_wr_readonly(cfg_mgmt_wr_readonly),
.cfg_err_ecrc(cfg_err_ecrc),
.cfg_err_ur(cfg_err_ur),
.cfg_err_cpl_timeout(cfg_err_cpl_timeout),
.cfg_err_cpl_unexpect(cfg_err_cpl_unexpect),
.cfg_err_cpl_abort(cfg_err_cpl_abort),
.cfg_err_posted(cfg_err_posted),
.cfg_err_cor(cfg_err_cor),
.cfg_err_atomic_egress_blocked(cfg_err_atomic_egress_blocked),
.cfg_err_internal_cor(cfg_err_internal_cor),
.cfg_err_malformed(cfg_err_malformed),
.cfg_err_mc_blocked(cfg_err_mc_blocked),
.cfg_err_poisoned(cfg_err_poisoned),
.cfg_err_norecovery(cfg_err_norecovery),
.cfg_err_tlp_cpl_header(cfg_err_tlp_cpl_header),
.cfg_err_cpl_rdy(cfg_err_cpl_rdy),
.cfg_err_locked(cfg_err_locked),
.cfg_err_acs(cfg_err_acs),
.cfg_err_internal_uncor(cfg_err_internal_uncor),
.cfg_trn_pending(cfg_trn_pending),
.cfg_pm_halt_aspm_l0s(cfg_pm_halt_aspm_l0s),
.cfg_pm_halt_aspm_l1(cfg_pm_halt_aspm_l1),
.cfg_pm_force_state_en(cfg_pm_force_state_en),
.cfg_pm_force_state(cfg_pm_force_state),
.cfg_dsn(cfg_dsn),
.cfg_msg_received(cfg_msg_received),
.cfg_msg_data(cfg_msg_data),
.cfg_interrupt(cfg_interrupt),
.cfg_interrupt_rdy(cfg_interrupt_rdy),
.cfg_interrupt_assert(cfg_interrupt_assert),
.cfg_interrupt_di(cfg_interrupt_di),
.cfg_interrupt_do(cfg_interrupt_do),
.cfg_interrupt_mmenable(cfg_interrupt_mmenable),
.cfg_interrupt_msienable(cfg_interrupt_msienable),
.cfg_interrupt_msixenable(cfg_interrupt_msixenable),
.cfg_interrupt_msixfm(cfg_interrupt_msixfm),
.cfg_interrupt_stat(cfg_interrupt_stat),
.cfg_pciecap_interrupt_msgnum(cfg_pciecap_interrupt_msgnum),
.cfg_to_turnoff(cfg_to_turnoff),
.cfg_turnoff_ok(cfg_turnoff_ok),
.cfg_bus_number(cfg_bus_number),
.cfg_device_number(cfg_device_number),
.cfg_function_number(cfg_function_number),
.cfg_pm_wake(cfg_pm_wake),
.cfg_msg_received_setslotpowerlimit(cfg_msg_received_setslotpowerlimit),
.cfg_pm_send_pme_to(cfg_pm_send_pme_to),
.cfg_ds_bus_number(cfg_ds_bus_number),
.cfg_ds_device_number(cfg_ds_device_number),
.cfg_ds_function_number(cfg_ds_function_number),
.cfg_mgmt_wr_rw1c_as_rw(cfg_mgmt_wr_rw1c_as_rw),
.cfg_bridge_serr_en(cfg_bridge_serr_en),
.cfg_slot_control_electromech_il_ctl_pulse(cfg_slot_control_electromech_il_ctl_pulse),
.cfg_root_control_syserr_corr_err_en(cfg_root_control_syserr_corr_err_en),
.cfg_root_control_syserr_non_fatal_err_en(cfg_root_control_syserr_non_fatal_err_en),
.cfg_root_control_syserr_fatal_err_en(cfg_root_control_syserr_fatal_err_en),
.cfg_root_control_pme_int_en(cfg_root_control_pme_int_en),
.cfg_aer_rooterr_corr_err_reporting_en(cfg_aer_rooterr_corr_err_reporting_en),
.cfg_aer_rooterr_non_fatal_err_reporting_en(cfg_aer_rooterr_non_fatal_err_reporting_en),
.cfg_aer_rooterr_fatal_err_reporting_en(cfg_aer_rooterr_fatal_err_reporting_en),
.cfg_aer_rooterr_corr_err_received(cfg_aer_rooterr_corr_err_received),
.cfg_aer_rooterr_non_fatal_err_received(cfg_aer_rooterr_non_fatal_err_received),
.cfg_aer_rooterr_fatal_err_received(cfg_aer_rooterr_fatal_err_received),
.cfg_msg_received_err_cor(cfg_msg_received_err_cor),
.cfg_msg_received_err_non_fatal(cfg_msg_received_err_non_fatal),
.cfg_msg_received_err_fatal(cfg_msg_received_err_fatal),
.cfg_msg_received_pm_as_nak(cfg_msg_received_pm_as_nak),
.cfg_msg_received_pm_pme(cfg_msg_received_pm_pme),
.cfg_msg_received_pme_to_ack(cfg_msg_received_pme_to_ack),
.cfg_msg_received_assert_int_a(cfg_msg_received_assert_int_a),
.cfg_msg_received_assert_int_b(cfg_msg_received_assert_int_b),
.cfg_msg_received_assert_int_c(cfg_msg_received_assert_int_c),
.cfg_msg_received_assert_int_d(cfg_msg_received_assert_int_d),
.cfg_msg_received_deassert_int_a(cfg_msg_received_deassert_int_a),
.cfg_msg_received_deassert_int_b(cfg_msg_received_deassert_int_b),
.cfg_msg_received_deassert_int_c(cfg_msg_received_deassert_int_c),
.cfg_msg_received_deassert_int_d(cfg_msg_received_deassert_int_d),
.pl_directed_link_change(pl_directed_link_change),
.pl_directed_link_width(pl_directed_link_width),
.pl_directed_link_speed(pl_directed_link_speed),
.pl_directed_link_auton(pl_directed_link_auton),
.pl_upstream_prefer_deemph(pl_upstream_prefer_deemph),
.pl_sel_lnk_rate(pl_sel_lnk_rate),
.pl_sel_lnk_width(pl_sel_lnk_width),
.pl_ltssm_state(pl_ltssm_state),
.pl_lane_reversal_mode(pl_lane_reversal_mode),
.pl_phy_lnk_up(pl_phy_lnk_up),
.pl_tx_pm_state(pl_tx_pm_state),
.pl_rx_pm_state(pl_rx_pm_state),
.pl_link_upcfg_cap(pl_link_upcfg_cap),
.pl_link_gen2_cap(pl_link_gen2_cap),
.pl_link_partner_gen2_supported(pl_link_partner_gen2_supported),
.pl_initial_link_width(pl_initial_link_width),
.pl_directed_change_done(pl_directed_change_done),
.pl_received_hot_rst(pl_received_hot_rst),
.pl_transmit_hot_rst(pl_transmit_hot_rst),
.pl_downstream_deemph_source(pl_downstream_deemph_source),
.cfg_err_aer_headerlog(cfg_err_aer_headerlog),
.cfg_aer_interrupt_msgnum(cfg_aer_interrupt_msgnum),
.cfg_err_aer_headerlog_set(cfg_err_aer_headerlog_set),
.cfg_aer_ecrc_check_en(cfg_aer_ecrc_check_en),
.cfg_aer_ecrc_gen_en(cfg_aer_ecrc_gen_en),
.cfg_vc_tcvc_map(cfg_vc_tcvc_map),
.pcie_drp_clk(pcie_drp_clk),
.pcie_drp_en(pcie_drp_en),
.pcie_drp_we(pcie_drp_we),
.pcie_drp_addr(pcie_drp_addr),
.pcie_drp_di(pcie_drp_di),
.pcie_drp_rdy(pcie_drp_rdy),
.pcie_drp_do(pcie_drp_do),
// STARTUP primitive interface - Can only be used with Tandem Configurations
// This input should be used when the startup block is generated exteranl to the PCI Express Core
.startup_eos_in(startup_eos_in), // 1-bit input: This signal should be driven by the EOS output of the STARTUP primitive.
// These inputs and outputs may be use when the startup block is generated internal to the PCI Express Core.
.startup_cfgclk(startup_cfgclk), // 1-bit output: Configuration main clock output
.startup_cfgmclk(startup_cfgmclk), // 1-bit output: Configuration internal oscillator clock output
.startup_eos(startup_eos), // 1-bit output: Active high output signal indicating the End Of Startup.
.startup_preq(startup_preq), // 1-bit output: PROGRAM request to fabric output
.startup_clk(startup_clk), // 1-bit input: User start-up clock input
.startup_gsr(startup_gsr), // 1-bit input: Global Set/Reset input (GSR cannot be used for the port name)
.startup_gts(startup_gts), // 1-bit input: Global 3-state input (GTS cannot be used for the port name)
.startup_keyclearb(startup_keyclearb), // 1-bit input: Clear AES Decrypter Key input from Battery-Backed RAM (BBRAM)
.startup_pack(startup_pack), // 1-bit input: PROGRAM acknowledge input
.startup_usrcclko(startup_usrcclko), // 1-bit input: User CCLK input
.startup_usrcclkts(startup_usrcclkts), // 1-bit input: User CCLK 3-state enable input
.startup_usrdoneo(startup_usrdoneo), // 1-bit input: User DONE pin output control
.startup_usrdonets(startup_usrdonets), // 1-bit input: User DONE 3-state enable output
// ICAP primitive interface - Can only be used with Tandem PCIe Configuration
.icap_clk(icap_clk),
.icap_csib(icap_csib),
.icap_rdwrb(icap_rdwrb),
.icap_i(icap_i),
.icap_o(icap_o),
//External GT COMMON Ports
.qpll_drp_crscode ( qpll_drp_crscode ),
.qpll_drp_fsm ( qpll_drp_fsm ),
.qpll_drp_done ( qpll_drp_done ),
.qpll_drp_reset ( qpll_drp_reset ),
.qpll_qplllock ( qpll_qplllock ),
.qpll_qplloutclk ( qpll_qplloutclk ),
.qpll_qplloutrefclk ( qpll_qplloutrefclk ),
.qpll_qplld ( qpll_qplld ),
.qpll_qpllreset ( qpll_qpllreset ),
.qpll_drp_clk ( qpll_drp_clk ),
.qpll_drp_rst_n ( qpll_drp_rst_n ),
.qpll_drp_ovrd ( qpll_drp_ovrd ),
.qpll_drp_gen3 ( qpll_drp_gen3),
.qpll_drp_start ( qpll_drp_start ),
//------------TRANSCEIVER DEBUG-----------------------------------
//Drive these inputs to 0s
.ext_ch_gt_drpclk (ext_ch_gt_drpclk),
.ext_ch_gt_drpaddr (ext_ch_gt_drpaddr),
.ext_ch_gt_drpen (ext_ch_gt_drpen),
.ext_ch_gt_drpdi (ext_ch_gt_drpdi),
.ext_ch_gt_drpwe (ext_ch_gt_drpwe),
.ext_ch_gt_drpdo (ext_ch_gt_drpdo),
.ext_ch_gt_drprdy (ext_ch_gt_drprdy ),
.pipe_txprbssel (pipe_txprbssel),
.pipe_rxprbssel (pipe_rxprbssel),
.pipe_txprbsforceerr (pipe_txprbsforceerr),
.pipe_rxprbscntreset (pipe_rxprbscntreset),
.pipe_loopback (pipe_loopback ),
.pipe_rxprbserr (pipe_rxprbserr),
.pipe_rst_fsm (pipe_rst_fsm),
.pipe_qrst_fsm (pipe_qrst_fsm),
.pipe_rate_fsm (pipe_rate_fsm),
.pipe_sync_fsm_tx (pipe_sync_fsm_tx),
.pipe_sync_fsm_rx (pipe_sync_fsm_rx),
.pipe_drp_fsm (pipe_drp_fsm),
.pipe_rst_idle (pipe_rst_idle),
.pipe_qrst_idle (pipe_qrst_idle),
.pipe_rate_idle (pipe_rate_idle),
.pipe_eyescandataerror (pipe_eyescandataerror),
.pipe_rxstatus (pipe_rxstatus),
.pipe_dmonitorout (pipe_dmonitorout),
.pipe_cpll_lock ( pipe_cpll_lock ),
.pipe_qpll_lock ( pipe_qpll_lock ),
.pipe_rxpmaresetdone ( pipe_rxpmaresetdone ),
.pipe_rxbufstatus ( pipe_rxbufstatus ),
.pipe_txphaligndone ( pipe_txphaligndone ),
.pipe_txphinitdone ( pipe_txphinitdone ),
.pipe_txdlysresetdone ( pipe_txdlysresetdone ),
.pipe_rxphaligndone ( pipe_rxphaligndone ),
.pipe_rxdlysresetdone ( pipe_rxdlysresetdone ),
.pipe_rxsyncdone ( pipe_rxsyncdone ),
.pipe_rxdisperr ( pipe_rxdisperr ),
.pipe_rxnotintable ( pipe_rxnotintable ),
.pipe_rxcommadet ( pipe_rxcommadet ),
//---------- CHANNEL DRP --------------------------------
.gt_ch_drp_rdy (gt_ch_drp_rdy),
.pipe_debug_0 (pipe_debug_0),
.pipe_debug_1 (pipe_debug_1),
.pipe_debug_2 (pipe_debug_2),
.pipe_debug_3 (pipe_debug_3),
.pipe_debug_4 (pipe_debug_4),
.pipe_debug_5 (pipe_debug_5),
.pipe_debug_6 (pipe_debug_6),
.pipe_debug_7 (pipe_debug_7),
.pipe_debug_8 (pipe_debug_8),
.pipe_debug_9 (pipe_debug_9),
.pipe_debug (pipe_debug),
.common_commands_in ( common_commands_in ),
.pipe_rx_0_sigs ( pipe_rx_0_sigs ),
.pipe_rx_1_sigs ( pipe_rx_1_sigs ),
.pipe_rx_2_sigs ( pipe_rx_2_sigs ),
.pipe_rx_3_sigs ( pipe_rx_3_sigs ),
.pipe_rx_4_sigs ( pipe_rx_4_sigs ),
.pipe_rx_5_sigs ( pipe_rx_5_sigs ),
.pipe_rx_6_sigs ( pipe_rx_6_sigs ),
.pipe_rx_7_sigs ( pipe_rx_7_sigs ),
.common_commands_out ( common_commands_out ),
.pipe_tx_0_sigs ( pipe_tx_0_sigs ),
.pipe_tx_1_sigs ( pipe_tx_1_sigs ),
.pipe_tx_2_sigs ( pipe_tx_2_sigs ),
.pipe_tx_3_sigs ( pipe_tx_3_sigs ),
.pipe_tx_4_sigs ( pipe_tx_4_sigs ),
.pipe_tx_5_sigs ( pipe_tx_5_sigs ),
.pipe_tx_6_sigs ( pipe_tx_6_sigs ),
.pipe_tx_7_sigs ( pipe_tx_7_sigs ),
.pipe_mmcm_rst_n (pipe_mmcm_rst_n), // Async | Async
.sys_clk (sys_clk),
.sys_rst_n (sys_rst_n)
);
endmodule
|
// handles transmission over UART
module uart_tx
(
input wire clk,
input wire reset,
input wire tx_start,
input wire s_tick,
input wire [7:0] din,
output reg tx_done_tick,
output wire tx
);
parameter DBIT = 8;
parameter SB_TICK = 16;
localparam IDLE = 0;
localparam START = 1;
localparam DATA = 2;
localparam STOP = 3;
reg [1:0] state_reg, state_next;
reg [3:0] s_reg, s_next;
reg [2:0] n_reg, n_next;
reg [7:0] b_reg, b_next;
reg tx_reg, tx_next;
always @ (posedge clk, posedge reset) begin
if (reset) begin
state_reg <= IDLE;
s_reg <= 0;
n_reg <= 0;
b_reg <= 0;
tx_reg <= 1;
end
else begin
state_reg <= state_next;
s_reg <= s_next;
n_reg <= n_next;
b_reg <= b_next;
tx_reg <= tx_next;
end
end
// state machine works as follows:
// if it is in idle mode, it waits for a start
// signal to begin, otherwise it continues to send 0s to UART (meaning there is nothing available yet)
// then it goes into start mode once some data has been inputted, it does the write
// starting at START for 8 bits before moving back to idle
always @ (state_reg, s_reg, n_reg, b_reg, s_tick, tx_reg, tx_start, din) begin
state_next <= state_reg;
s_next <= s_reg;
n_next <= n_reg;
b_next <= b_reg;
tx_next <= tx_reg;
tx_done_tick <= 0;
case (state_reg)
IDLE: begin
tx_next <= 1;
if (tx_start) begin
state_next <= START;
s_next <= 0;
b_next <= din;
end
end
START: begin
tx_next <= 0;
if (s_tick) begin
if (s_reg == 15) begin
state_next <= DATA;
s_next <= 0;
n_next <= 0;
end
else
s_next <= s_reg + 1;
end
end
DATA: begin
tx_next <= b_reg[0];
if (s_tick) begin
if (s_reg == 15) begin
s_next <= 0;
b_next <= {1'b0, b_reg[7:1]};
if (n_reg == DBIT-1)
state_next <= STOP;
else
n_next <= n_reg + 1;
end
else
s_next <= s_reg + 1;
end
end
STOP: begin
tx_next <= 1;
if (s_tick) begin
if (s_reg == SB_TICK-1) begin
state_next <= IDLE;
tx_done_tick <= 1;
end
else
s_next <= s_reg + 1;
end
end
endcase
end
assign tx = tx_reg;
endmodule
|
/*
* Copyright (c) 2000 Steve Wilson ([email protected])
*
* This source code is free software; you can redistribute it
* and/or modify it in source code form under the terms of the GNU
* General Public License as published by the Free Software
* Foundation; either version 2 of the License, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
*/
/*
* This checks bit select from/to vectors with odd bit arrangements.
*/
module test;
reg [1:4] a;
reg [4:1] b;
integer i;
initial begin
a = 4'b1100;
for (i = 1 ; i <= 4 ; i = i + 1)
b[i] = a[i];
$display("a=%b, b=%b", a, b);
if (b !== 4'b0011) begin
$display("FAILED -- b == %b", b);
$finish;
end
$display("PASSED");
end
endmodule
|
//-----------------------------------------------------------------------------
//
// (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//-----------------------------------------------------------------------------
// Project : Series-7 Integrated Block for PCI Express
// File : PCIEBus_axi_basic_top.v
// Version : 1.11
// //
// Description: //
// TRN/AXI4-S Bridge top level module. Instantiates RX and TX modules. //
// //
// Notes: //
// Optional notes section. //
// //
// Hierarchical: //
// axi_basic_top //
// //
//----------------------------------------------------------------------------//
`timescale 1ps/1ps
module PCIEBus_axi_basic_top #(
parameter C_DATA_WIDTH = 128, // RX/TX interface data width
parameter C_FAMILY = "X7", // Targeted FPGA family
parameter C_ROOT_PORT = "FALSE", // PCIe block is in root port mode
parameter C_PM_PRIORITY = "FALSE", // Disable TX packet boundary thrtl
parameter TCQ = 1, // Clock to Q time
// Do not override parameters below this line
parameter REM_WIDTH = (C_DATA_WIDTH == 128) ? 2 : 1, // trem/rrem width
parameter KEEP_WIDTH = C_DATA_WIDTH / 8 // KEEP width
) (
//---------------------------------------------//
// User Design I/O //
//---------------------------------------------//
// AXI TX
//-----------
input [C_DATA_WIDTH-1:0] s_axis_tx_tdata, // TX data from user
input s_axis_tx_tvalid, // TX data is valid
output s_axis_tx_tready, // TX ready for data
input [KEEP_WIDTH-1:0] s_axis_tx_tkeep, // TX strobe byte enables
input s_axis_tx_tlast, // TX data is last
input [3:0] s_axis_tx_tuser, // TX user signals
// AXI RX
//-----------
output [C_DATA_WIDTH-1:0] m_axis_rx_tdata, // RX data to user
output m_axis_rx_tvalid, // RX data is valid
input m_axis_rx_tready, // RX ready for data
output [KEEP_WIDTH-1:0] m_axis_rx_tkeep, // RX strobe byte enables
output m_axis_rx_tlast, // RX data is last
output [21:0] m_axis_rx_tuser, // RX user signals
// User Misc.
//-----------
input user_turnoff_ok, // Turnoff OK from user
input user_tcfg_gnt, // Send cfg OK from user
//---------------------------------------------//
// PCIe Block I/O //
//---------------------------------------------//
// TRN TX
//-----------
output [C_DATA_WIDTH-1:0] trn_td, // TX data from block
output trn_tsof, // TX start of packet
output trn_teof, // TX end of packet
output trn_tsrc_rdy, // TX source ready
input trn_tdst_rdy, // TX destination ready
output trn_tsrc_dsc, // TX source discontinue
output [REM_WIDTH-1:0] trn_trem, // TX remainder
output trn_terrfwd, // TX error forward
output trn_tstr, // TX streaming enable
input [5:0] trn_tbuf_av, // TX buffers available
output trn_tecrc_gen, // TX ECRC generate
// TRN RX
//-----------
input [C_DATA_WIDTH-1:0] trn_rd, // RX data from block
input trn_rsof, // RX start of packet
input trn_reof, // RX end of packet
input trn_rsrc_rdy, // RX source ready
output trn_rdst_rdy, // RX destination ready
input trn_rsrc_dsc, // RX source discontinue
input [REM_WIDTH-1:0] trn_rrem, // RX remainder
input trn_rerrfwd, // RX error forward
input [6:0] trn_rbar_hit, // RX BAR hit
input trn_recrc_err, // RX ECRC error
// TRN Misc.
//-----------
input trn_tcfg_req, // TX config request
output trn_tcfg_gnt, // RX config grant
input trn_lnk_up, // PCIe link up
// 7 Series/Virtex6 PM
//-----------
input [2:0] cfg_pcie_link_state, // Encoded PCIe link state
// Virtex6 PM
//-----------
input cfg_pm_send_pme_to, // PM send PME turnoff msg
input [1:0] cfg_pmcsr_powerstate, // PMCSR power state
input [31:0] trn_rdllp_data, // RX DLLP data
input trn_rdllp_src_rdy, // RX DLLP source ready
// Virtex6/Spartan6 PM
//-----------
input cfg_to_turnoff, // Turnoff request
output cfg_turnoff_ok, // Turnoff grant
// System
//-----------
output [2:0] np_counter, // Non-posted counter
input user_clk, // user clock from block
input user_rst // user reset from block
);
//---------------------------------------------//
// RX Data Pipeline //
//---------------------------------------------//
PCIEBus_axi_basic_rx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) rx_inst (
// Outgoing AXI TX
//-----------
.m_axis_rx_tdata( m_axis_rx_tdata ),
.m_axis_rx_tvalid( m_axis_rx_tvalid ),
.m_axis_rx_tready( m_axis_rx_tready ),
.m_axis_rx_tkeep( m_axis_rx_tkeep ),
.m_axis_rx_tlast( m_axis_rx_tlast ),
.m_axis_rx_tuser( m_axis_rx_tuser ),
// Incoming TRN RX
//-----------
.trn_rd( trn_rd ),
.trn_rsof( trn_rsof ),
.trn_reof( trn_reof ),
.trn_rsrc_rdy( trn_rsrc_rdy ),
.trn_rdst_rdy( trn_rdst_rdy ),
.trn_rsrc_dsc( trn_rsrc_dsc ),
.trn_rrem( trn_rrem ),
.trn_rerrfwd( trn_rerrfwd ),
.trn_rbar_hit( trn_rbar_hit ),
.trn_recrc_err( trn_recrc_err ),
// System
//-----------
.np_counter( np_counter ),
.user_clk( user_clk ),
.user_rst( user_rst )
);
//---------------------------------------------//
// TX Data Pipeline //
//---------------------------------------------//
PCIEBus_axi_basic_tx #(
.C_DATA_WIDTH( C_DATA_WIDTH ),
.C_FAMILY( C_FAMILY ),
.C_ROOT_PORT( C_ROOT_PORT ),
.C_PM_PRIORITY( C_PM_PRIORITY ),
.TCQ( TCQ ),
.REM_WIDTH( REM_WIDTH ),
.KEEP_WIDTH( KEEP_WIDTH )
) tx_inst (
// Incoming AXI RX
//-----------
.s_axis_tx_tdata( s_axis_tx_tdata ),
.s_axis_tx_tvalid( s_axis_tx_tvalid ),
.s_axis_tx_tready( s_axis_tx_tready ),
.s_axis_tx_tkeep( s_axis_tx_tkeep ),
.s_axis_tx_tlast( s_axis_tx_tlast ),
.s_axis_tx_tuser( s_axis_tx_tuser ),
// User Misc.
//-----------
.user_turnoff_ok( user_turnoff_ok ),
.user_tcfg_gnt( user_tcfg_gnt ),
// Outgoing TRN TX
//-----------
.trn_td( trn_td ),
.trn_tsof( trn_tsof ),
.trn_teof( trn_teof ),
.trn_tsrc_rdy( trn_tsrc_rdy ),
.trn_tdst_rdy( trn_tdst_rdy ),
.trn_tsrc_dsc( trn_tsrc_dsc ),
.trn_trem( trn_trem ),
.trn_terrfwd( trn_terrfwd ),
.trn_tstr( trn_tstr ),
.trn_tbuf_av( trn_tbuf_av ),
.trn_tecrc_gen( trn_tecrc_gen ),
// TRN Misc.
//-----------
.trn_tcfg_req( trn_tcfg_req ),
.trn_tcfg_gnt( trn_tcfg_gnt ),
.trn_lnk_up( trn_lnk_up ),
// 7 Series/Virtex6 PM
//-----------
.cfg_pcie_link_state( cfg_pcie_link_state ),
// Virtex6 PM
//-----------
.cfg_pm_send_pme_to( cfg_pm_send_pme_to ),
.cfg_pmcsr_powerstate( cfg_pmcsr_powerstate ),
.trn_rdllp_data( trn_rdllp_data ),
.trn_rdllp_src_rdy( trn_rdllp_src_rdy ),
// Spartan6 PM
//-----------
.cfg_to_turnoff( cfg_to_turnoff ),
.cfg_turnoff_ok( cfg_turnoff_ok ),
// System
//-----------
.user_clk( user_clk ),
.user_rst( user_rst )
);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__ISO1P_BLACKBOX_V
`define SKY130_FD_SC_LP__ISO1P_BLACKBOX_V
/**
* iso1p: ????.
*
* Verilog stub definition (black box without power pins).
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__iso1p (
X ,
A ,
SLEEP
);
output X ;
input A ;
input SLEEP;
// Voltage supply signals
supply1 KAPWR;
supply0 VGND ;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__ISO1P_BLACKBOX_V
|
//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0
//Legal Notice: (C)2014 Altera Corporation. All rights reserved. Your
//use of Altera Corporation's design tools, logic functions and other
//software and tools, and its AMPP partner logic functions, and any
//output files any of the foregoing (including device programming or
//simulation files), and any associated documentation or information are
//expressly subject to the terms and conditions of the Altera Program
//License Subscription Agreement or other applicable license agreement,
//including, without limitation, that your use is for the sole purpose
//of programming logic devices manufactured by Altera and sold by Altera
//or its authorized distributors. Please refer to the applicable
//agreement for further details.
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arbitrator (
// inputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest,
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
reset_n,
// outputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata,
cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer
)
;
output [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
output [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
output [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
output Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
output [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
output cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
output d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
input [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
input Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input reset_n;
wire [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allow_new_arb_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable;
reg [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter;
wire [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
wire [ 2: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer;
wire [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
reg Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
reg Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_saved_grant_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
reg d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 27: 0] shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master;
wire wait_for_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
end
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave));
//assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
assign cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = ({cpu_0_data_master_address_to_slave[27 : 10] , 10'b0} == 28'h400) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter set values, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values = 1;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant = 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer ? (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_set_values - 1) : |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter ? (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter - 1) : 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants all slave grants, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants = |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer = ~(Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read | Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write);
//end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer & (~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allgrants) | (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter <= 0;
else if (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_counter_enable)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable <= 0;
else if ((|Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector & end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave) | (end_xfer_arb_share_counter_term_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_non_bursting_master_requests))
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable <= |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
end
//cpu_0/data_master Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 = |Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arb_share_counter_next_value;
//cpu_0/data_master Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//cpu_0/data_master saved-grant Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave = cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//allow new arb cycle for Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_master_qreq_vector = 1;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n = reset_n;
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer first transaction, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_firsttransfer = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer ? Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer : Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer first transaction, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer = ~(Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_slavearbiterlockenable & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_any_continuerequest);
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer <= 1'b1;
else if (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer)
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reg_firsttransfer <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_unreg_firsttransfer;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_beginbursttransfer_internal = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_begins_xfer;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read assignment, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_read;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write assignment, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_write;
assign shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address = shifted_address_to_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_from_cpu_0_data_master >> 2;
//d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer <= 1;
else
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer <= Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
end
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read in a cycle, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_read = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_read_cycle;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write in a cycle, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waits_for_write = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle & Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle assignment, which is an e_assign
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle = cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_in_a_write_cycle;
assign wait_for_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_counter = 0;
//Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable byte enable port mux, which is an e_mux
assign Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable = (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//Altera_UP_SD_Card_Avalon_Interface_0/avalon_sdcard_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module clocks_avalon_clocks_slave_arbitrator (
// inputs:
clk,
clocks_avalon_clocks_slave_readdata,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_dbs_address,
cpu_0_data_master_read,
cpu_0_data_master_write,
reset_n,
// outputs:
clocks_avalon_clocks_slave_address,
clocks_avalon_clocks_slave_readdata_from_sa,
cpu_0_data_master_granted_clocks_avalon_clocks_slave,
cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave,
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
cpu_0_data_master_requests_clocks_avalon_clocks_slave,
d1_clocks_avalon_clocks_slave_end_xfer,
registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave
)
;
output clocks_avalon_clocks_slave_address;
output [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
output cpu_0_data_master_granted_clocks_avalon_clocks_slave;
output cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
output cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
output cpu_0_data_master_requests_clocks_avalon_clocks_slave;
output d1_clocks_avalon_clocks_slave_end_xfer;
output registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input clk;
input [ 7: 0] clocks_avalon_clocks_slave_readdata;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 1: 0] cpu_0_data_master_dbs_address;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input reset_n;
wire clocks_avalon_clocks_slave_address;
wire clocks_avalon_clocks_slave_allgrants;
wire clocks_avalon_clocks_slave_allow_new_arb_cycle;
wire clocks_avalon_clocks_slave_any_bursting_master_saved_grant;
wire clocks_avalon_clocks_slave_any_continuerequest;
wire clocks_avalon_clocks_slave_arb_counter_enable;
reg [ 2: 0] clocks_avalon_clocks_slave_arb_share_counter;
wire [ 2: 0] clocks_avalon_clocks_slave_arb_share_counter_next_value;
wire [ 2: 0] clocks_avalon_clocks_slave_arb_share_set_values;
wire clocks_avalon_clocks_slave_beginbursttransfer_internal;
wire clocks_avalon_clocks_slave_begins_xfer;
wire clocks_avalon_clocks_slave_end_xfer;
wire clocks_avalon_clocks_slave_firsttransfer;
wire clocks_avalon_clocks_slave_grant_vector;
wire clocks_avalon_clocks_slave_in_a_read_cycle;
wire clocks_avalon_clocks_slave_in_a_write_cycle;
wire clocks_avalon_clocks_slave_master_qreq_vector;
wire clocks_avalon_clocks_slave_non_bursting_master_requests;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
reg clocks_avalon_clocks_slave_reg_firsttransfer;
reg clocks_avalon_clocks_slave_slavearbiterlockenable;
wire clocks_avalon_clocks_slave_slavearbiterlockenable2;
wire clocks_avalon_clocks_slave_unreg_firsttransfer;
wire clocks_avalon_clocks_slave_waits_for_read;
wire clocks_avalon_clocks_slave_waits_for_write;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_clocks_avalon_clocks_slave;
wire cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
reg cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in;
wire cpu_0_data_master_requests_clocks_avalon_clocks_slave;
wire cpu_0_data_master_saved_grant_clocks_avalon_clocks_slave;
reg d1_clocks_avalon_clocks_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
wire registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire wait_for_clocks_avalon_clocks_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~clocks_avalon_clocks_slave_end_xfer;
end
assign clocks_avalon_clocks_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave));
//assign clocks_avalon_clocks_slave_readdata_from_sa = clocks_avalon_clocks_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign clocks_avalon_clocks_slave_readdata_from_sa = clocks_avalon_clocks_slave_readdata;
assign cpu_0_data_master_requests_clocks_avalon_clocks_slave = (({cpu_0_data_master_address_to_slave[27 : 1] , 1'b0} == 28'h28) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in;
//clocks_avalon_clocks_slave_arb_share_counter set values, which is an e_mux
assign clocks_avalon_clocks_slave_arb_share_set_values = (cpu_0_data_master_granted_clocks_avalon_clocks_slave)? 4 :
1;
//clocks_avalon_clocks_slave_non_bursting_master_requests mux, which is an e_mux
assign clocks_avalon_clocks_slave_non_bursting_master_requests = cpu_0_data_master_requests_clocks_avalon_clocks_slave;
//clocks_avalon_clocks_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign clocks_avalon_clocks_slave_any_bursting_master_saved_grant = 0;
//clocks_avalon_clocks_slave_arb_share_counter_next_value assignment, which is an e_assign
assign clocks_avalon_clocks_slave_arb_share_counter_next_value = clocks_avalon_clocks_slave_firsttransfer ? (clocks_avalon_clocks_slave_arb_share_set_values - 1) : |clocks_avalon_clocks_slave_arb_share_counter ? (clocks_avalon_clocks_slave_arb_share_counter - 1) : 0;
//clocks_avalon_clocks_slave_allgrants all slave grants, which is an e_mux
assign clocks_avalon_clocks_slave_allgrants = |clocks_avalon_clocks_slave_grant_vector;
//clocks_avalon_clocks_slave_end_xfer assignment, which is an e_assign
assign clocks_avalon_clocks_slave_end_xfer = ~(clocks_avalon_clocks_slave_waits_for_read | clocks_avalon_clocks_slave_waits_for_write);
//end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave = clocks_avalon_clocks_slave_end_xfer & (~clocks_avalon_clocks_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//clocks_avalon_clocks_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign clocks_avalon_clocks_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & clocks_avalon_clocks_slave_allgrants) | (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & ~clocks_avalon_clocks_slave_non_bursting_master_requests);
//clocks_avalon_clocks_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_arb_share_counter <= 0;
else if (clocks_avalon_clocks_slave_arb_counter_enable)
clocks_avalon_clocks_slave_arb_share_counter <= clocks_avalon_clocks_slave_arb_share_counter_next_value;
end
//clocks_avalon_clocks_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_slavearbiterlockenable <= 0;
else if ((|clocks_avalon_clocks_slave_master_qreq_vector & end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave) | (end_xfer_arb_share_counter_term_clocks_avalon_clocks_slave & ~clocks_avalon_clocks_slave_non_bursting_master_requests))
clocks_avalon_clocks_slave_slavearbiterlockenable <= |clocks_avalon_clocks_slave_arb_share_counter_next_value;
end
//cpu_0/data_master clocks/avalon_clocks_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = clocks_avalon_clocks_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//clocks_avalon_clocks_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign clocks_avalon_clocks_slave_slavearbiterlockenable2 = |clocks_avalon_clocks_slave_arb_share_counter_next_value;
//cpu_0/data_master clocks/avalon_clocks_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = clocks_avalon_clocks_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//clocks_avalon_clocks_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign clocks_avalon_clocks_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave = cpu_0_data_master_requests_clocks_avalon_clocks_slave & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register))));
//cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_read & ~clocks_avalon_clocks_slave_waits_for_read & ~(|cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register = {cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register, cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register_in};
//cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register <= p1_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave, which is an e_mux
assign cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave_shift_register;
//master is always granted when requested
assign cpu_0_data_master_granted_clocks_avalon_clocks_slave = cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
//cpu_0/data_master saved-grant clocks/avalon_clocks_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_clocks_avalon_clocks_slave = cpu_0_data_master_requests_clocks_avalon_clocks_slave;
//allow new arb cycle for clocks/avalon_clocks_slave, which is an e_assign
assign clocks_avalon_clocks_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign clocks_avalon_clocks_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign clocks_avalon_clocks_slave_master_qreq_vector = 1;
//clocks_avalon_clocks_slave_firsttransfer first transaction, which is an e_assign
assign clocks_avalon_clocks_slave_firsttransfer = clocks_avalon_clocks_slave_begins_xfer ? clocks_avalon_clocks_slave_unreg_firsttransfer : clocks_avalon_clocks_slave_reg_firsttransfer;
//clocks_avalon_clocks_slave_unreg_firsttransfer first transaction, which is an e_assign
assign clocks_avalon_clocks_slave_unreg_firsttransfer = ~(clocks_avalon_clocks_slave_slavearbiterlockenable & clocks_avalon_clocks_slave_any_continuerequest);
//clocks_avalon_clocks_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
clocks_avalon_clocks_slave_reg_firsttransfer <= 1'b1;
else if (clocks_avalon_clocks_slave_begins_xfer)
clocks_avalon_clocks_slave_reg_firsttransfer <= clocks_avalon_clocks_slave_unreg_firsttransfer;
end
//clocks_avalon_clocks_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign clocks_avalon_clocks_slave_beginbursttransfer_internal = clocks_avalon_clocks_slave_begins_xfer;
//clocks_avalon_clocks_slave_address mux, which is an e_mux
assign clocks_avalon_clocks_slave_address = {cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1 : 0]};
//d1_clocks_avalon_clocks_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_clocks_avalon_clocks_slave_end_xfer <= 1;
else
d1_clocks_avalon_clocks_slave_end_xfer <= clocks_avalon_clocks_slave_end_xfer;
end
//clocks_avalon_clocks_slave_waits_for_read in a cycle, which is an e_mux
assign clocks_avalon_clocks_slave_waits_for_read = clocks_avalon_clocks_slave_in_a_read_cycle & 0;
//clocks_avalon_clocks_slave_in_a_read_cycle assignment, which is an e_assign
assign clocks_avalon_clocks_slave_in_a_read_cycle = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = clocks_avalon_clocks_slave_in_a_read_cycle;
//clocks_avalon_clocks_slave_waits_for_write in a cycle, which is an e_mux
assign clocks_avalon_clocks_slave_waits_for_write = clocks_avalon_clocks_slave_in_a_write_cycle & 0;
//clocks_avalon_clocks_slave_in_a_write_cycle assignment, which is an e_assign
assign clocks_avalon_clocks_slave_in_a_write_cycle = cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = clocks_avalon_clocks_slave_in_a_write_cycle;
assign wait_for_clocks_avalon_clocks_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//clocks/avalon_clocks_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_jtag_debug_module_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_debugaccess,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
cpu_0_jtag_debug_module_readdata,
cpu_0_jtag_debug_module_resetrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_jtag_debug_module_address,
cpu_0_jtag_debug_module_begintransfer,
cpu_0_jtag_debug_module_byteenable,
cpu_0_jtag_debug_module_chipselect,
cpu_0_jtag_debug_module_debugaccess,
cpu_0_jtag_debug_module_readdata_from_sa,
cpu_0_jtag_debug_module_reset_n,
cpu_0_jtag_debug_module_resetrequest_from_sa,
cpu_0_jtag_debug_module_write,
cpu_0_jtag_debug_module_writedata,
d1_cpu_0_jtag_debug_module_end_xfer
)
;
output cpu_0_data_master_granted_cpu_0_jtag_debug_module;
output cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_data_master_requests_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
output cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
output [ 8: 0] cpu_0_jtag_debug_module_address;
output cpu_0_jtag_debug_module_begintransfer;
output [ 3: 0] cpu_0_jtag_debug_module_byteenable;
output cpu_0_jtag_debug_module_chipselect;
output cpu_0_jtag_debug_module_debugaccess;
output [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
output cpu_0_jtag_debug_module_reset_n;
output cpu_0_jtag_debug_module_resetrequest_from_sa;
output cpu_0_jtag_debug_module_write;
output [ 31: 0] cpu_0_jtag_debug_module_writedata;
output d1_cpu_0_jtag_debug_module_end_xfer;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_debugaccess;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input [ 31: 0] cpu_0_jtag_debug_module_readdata;
input cpu_0_jtag_debug_module_resetrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_allgrants;
wire cpu_0_jtag_debug_module_allow_new_arb_cycle;
wire cpu_0_jtag_debug_module_any_bursting_master_saved_grant;
wire cpu_0_jtag_debug_module_any_continuerequest;
reg [ 1: 0] cpu_0_jtag_debug_module_arb_addend;
wire cpu_0_jtag_debug_module_arb_counter_enable;
reg [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_counter_next_value;
wire [ 2: 0] cpu_0_jtag_debug_module_arb_share_set_values;
wire [ 1: 0] cpu_0_jtag_debug_module_arb_winner;
wire cpu_0_jtag_debug_module_arbitration_holdoff_internal;
wire cpu_0_jtag_debug_module_beginbursttransfer_internal;
wire cpu_0_jtag_debug_module_begins_xfer;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire [ 3: 0] cpu_0_jtag_debug_module_chosen_master_double_vector;
wire [ 1: 0] cpu_0_jtag_debug_module_chosen_master_rot_left;
wire cpu_0_jtag_debug_module_debugaccess;
wire cpu_0_jtag_debug_module_end_xfer;
wire cpu_0_jtag_debug_module_firsttransfer;
wire [ 1: 0] cpu_0_jtag_debug_module_grant_vector;
wire cpu_0_jtag_debug_module_in_a_read_cycle;
wire cpu_0_jtag_debug_module_in_a_write_cycle;
wire [ 1: 0] cpu_0_jtag_debug_module_master_qreq_vector;
wire cpu_0_jtag_debug_module_non_bursting_master_requests;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
reg cpu_0_jtag_debug_module_reg_firsttransfer;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
reg [ 1: 0] cpu_0_jtag_debug_module_saved_chosen_master_vector;
reg cpu_0_jtag_debug_module_slavearbiterlockenable;
wire cpu_0_jtag_debug_module_slavearbiterlockenable2;
wire cpu_0_jtag_debug_module_unreg_firsttransfer;
wire cpu_0_jtag_debug_module_waits_for_read;
wire cpu_0_jtag_debug_module_waits_for_write;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
reg d1_cpu_0_jtag_debug_module_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
reg last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
wire [ 27: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master;
wire wait_for_cpu_0_jtag_debug_module_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~cpu_0_jtag_debug_module_end_xfer;
end
assign cpu_0_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module));
//assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_readdata_from_sa = cpu_0_jtag_debug_module_readdata;
assign cpu_0_data_master_requests_cpu_0_jtag_debug_module = ({cpu_0_data_master_address_to_slave[27 : 11] , 11'b0} == 28'h800) & (cpu_0_data_master_read | cpu_0_data_master_write);
//cpu_0_jtag_debug_module_arb_share_counter set values, which is an e_mux
assign cpu_0_jtag_debug_module_arb_share_set_values = 1;
//cpu_0_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
assign cpu_0_jtag_debug_module_non_bursting_master_requests = cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module |
cpu_0_data_master_requests_cpu_0_jtag_debug_module |
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
assign cpu_0_jtag_debug_module_any_bursting_master_saved_grant = 0;
//cpu_0_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
assign cpu_0_jtag_debug_module_arb_share_counter_next_value = cpu_0_jtag_debug_module_firsttransfer ? (cpu_0_jtag_debug_module_arb_share_set_values - 1) : |cpu_0_jtag_debug_module_arb_share_counter ? (cpu_0_jtag_debug_module_arb_share_counter - 1) : 0;
//cpu_0_jtag_debug_module_allgrants all slave grants, which is an e_mux
assign cpu_0_jtag_debug_module_allgrants = (|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector) |
(|cpu_0_jtag_debug_module_grant_vector);
//cpu_0_jtag_debug_module_end_xfer assignment, which is an e_assign
assign cpu_0_jtag_debug_module_end_xfer = ~(cpu_0_jtag_debug_module_waits_for_read | cpu_0_jtag_debug_module_waits_for_write);
//end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_end_xfer & (~cpu_0_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//cpu_0_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
assign cpu_0_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & cpu_0_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests);
//cpu_0_jtag_debug_module_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_share_counter <= 0;
else if (cpu_0_jtag_debug_module_arb_counter_enable)
cpu_0_jtag_debug_module_arb_share_counter <= cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_slavearbiterlockenable <= 0;
else if ((|cpu_0_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_0_jtag_debug_module & ~cpu_0_jtag_debug_module_non_bursting_master_requests))
cpu_0_jtag_debug_module_slavearbiterlockenable <= |cpu_0_jtag_debug_module_arb_share_counter_next_value;
end
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//cpu_0_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign cpu_0_jtag_debug_module_slavearbiterlockenable2 = |cpu_0_jtag_debug_module_arb_share_counter_next_value;
//cpu_0/data_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master cpu_0/jtag_debug_module arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = cpu_0_jtag_debug_module_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
assign cpu_0_jtag_debug_module_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_data_master_requests_cpu_0_jtag_debug_module & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_jtag_debug_module_writedata mux, which is an e_mux
assign cpu_0_jtag_debug_module_writedata = cpu_0_data_master_writedata;
assign cpu_0_instruction_master_requests_cpu_0_jtag_debug_module = (({cpu_0_instruction_master_address_to_slave[27 : 11] , 11'b0} == 28'h800) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted cpu_0/jtag_debug_module last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module <= cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module ? 1 : (cpu_0_jtag_debug_module_arbitration_holdoff_internal | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) ? 0 : last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_cpu_0_jtag_debug_module & cpu_0_data_master_requests_cpu_0_jtag_debug_module;
assign cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module = cpu_0_instruction_master_requests_cpu_0_jtag_debug_module & ~(cpu_0_data_master_arbiterlock);
//allow new arb cycle for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/instruction_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[0];
//cpu_0/instruction_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[0] && cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
//cpu_0/data_master assignment into master qualified-requests vector for cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_jtag_debug_module_master_qreq_vector[1] = cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
//cpu_0/data_master grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_granted_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_grant_vector[1];
//cpu_0/data_master saved-grant cpu_0/jtag_debug_module, which is an e_assign
assign cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module = cpu_0_jtag_debug_module_arb_winner[1] && cpu_0_data_master_requests_cpu_0_jtag_debug_module;
//cpu_0/jtag_debug_module chosen-master double-vector, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_double_vector = {cpu_0_jtag_debug_module_master_qreq_vector, cpu_0_jtag_debug_module_master_qreq_vector} & ({~cpu_0_jtag_debug_module_master_qreq_vector, ~cpu_0_jtag_debug_module_master_qreq_vector} + cpu_0_jtag_debug_module_arb_addend);
//stable onehot encoding of arb winner
assign cpu_0_jtag_debug_module_arb_winner = (cpu_0_jtag_debug_module_allow_new_arb_cycle & | cpu_0_jtag_debug_module_grant_vector) ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
//saved cpu_0_jtag_debug_module_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= 0;
else if (cpu_0_jtag_debug_module_allow_new_arb_cycle)
cpu_0_jtag_debug_module_saved_chosen_master_vector <= |cpu_0_jtag_debug_module_grant_vector ? cpu_0_jtag_debug_module_grant_vector : cpu_0_jtag_debug_module_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign cpu_0_jtag_debug_module_grant_vector = {(cpu_0_jtag_debug_module_chosen_master_double_vector[1] | cpu_0_jtag_debug_module_chosen_master_double_vector[3]),
(cpu_0_jtag_debug_module_chosen_master_double_vector[0] | cpu_0_jtag_debug_module_chosen_master_double_vector[2])};
//cpu_0/jtag_debug_module chosen master rotated left, which is an e_assign
assign cpu_0_jtag_debug_module_chosen_master_rot_left = (cpu_0_jtag_debug_module_arb_winner << 1) ? (cpu_0_jtag_debug_module_arb_winner << 1) : 1;
//cpu_0/jtag_debug_module's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_arb_addend <= 1;
else if (|cpu_0_jtag_debug_module_grant_vector)
cpu_0_jtag_debug_module_arb_addend <= cpu_0_jtag_debug_module_end_xfer? cpu_0_jtag_debug_module_chosen_master_rot_left : cpu_0_jtag_debug_module_grant_vector;
end
assign cpu_0_jtag_debug_module_begintransfer = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_reset_n assignment, which is an e_assign
assign cpu_0_jtag_debug_module_reset_n = reset_n;
//assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign cpu_0_jtag_debug_module_resetrequest_from_sa = cpu_0_jtag_debug_module_resetrequest;
assign cpu_0_jtag_debug_module_chipselect = cpu_0_data_master_granted_cpu_0_jtag_debug_module | cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
//cpu_0_jtag_debug_module_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_firsttransfer = cpu_0_jtag_debug_module_begins_xfer ? cpu_0_jtag_debug_module_unreg_firsttransfer : cpu_0_jtag_debug_module_reg_firsttransfer;
//cpu_0_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
assign cpu_0_jtag_debug_module_unreg_firsttransfer = ~(cpu_0_jtag_debug_module_slavearbiterlockenable & cpu_0_jtag_debug_module_any_continuerequest);
//cpu_0_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_jtag_debug_module_reg_firsttransfer <= 1'b1;
else if (cpu_0_jtag_debug_module_begins_xfer)
cpu_0_jtag_debug_module_reg_firsttransfer <= cpu_0_jtag_debug_module_unreg_firsttransfer;
end
//cpu_0_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign cpu_0_jtag_debug_module_beginbursttransfer_internal = cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign cpu_0_jtag_debug_module_arbitration_holdoff_internal = cpu_0_jtag_debug_module_begins_xfer & cpu_0_jtag_debug_module_firsttransfer;
//cpu_0_jtag_debug_module_write assignment, which is an e_mux
assign cpu_0_jtag_debug_module_write = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//cpu_0_jtag_debug_module_address mux, which is an e_mux
assign cpu_0_jtag_debug_module_address = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? (shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_data_master >> 2) :
(shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_cpu_0_jtag_debug_module_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_cpu_0_jtag_debug_module_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_cpu_0_jtag_debug_module_end_xfer <= 1;
else
d1_cpu_0_jtag_debug_module_end_xfer <= cpu_0_jtag_debug_module_end_xfer;
end
//cpu_0_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_read = cpu_0_jtag_debug_module_in_a_read_cycle & cpu_0_jtag_debug_module_begins_xfer;
//cpu_0_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_read_cycle = (cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = cpu_0_jtag_debug_module_in_a_read_cycle;
//cpu_0_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
assign cpu_0_jtag_debug_module_waits_for_write = cpu_0_jtag_debug_module_in_a_write_cycle & 0;
//cpu_0_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
assign cpu_0_jtag_debug_module_in_a_write_cycle = cpu_0_data_master_granted_cpu_0_jtag_debug_module & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = cpu_0_jtag_debug_module_in_a_write_cycle;
assign wait_for_cpu_0_jtag_debug_module_counter = 0;
//cpu_0_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
assign cpu_0_jtag_debug_module_byteenable = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_byteenable :
-1;
//debugaccess mux, which is an e_mux
assign cpu_0_jtag_debug_module_debugaccess = (cpu_0_data_master_granted_cpu_0_jtag_debug_module)? cpu_0_data_master_debugaccess :
0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0/jtag_debug_module enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_cpu_0_jtag_debug_module + cpu_0_instruction_master_granted_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_cpu_0_jtag_debug_module + cpu_0_instruction_master_saved_grant_cpu_0_jtag_debug_module > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_data_master_arbitrator (
// inputs:
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa,
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa,
clk,
clocks_avalon_clocks_slave_readdata_from_sa,
cpu_0_data_master_address,
cpu_0_data_master_byteenable_nios_system_clock_1_in,
cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_granted_clocks_avalon_clocks_slave,
cpu_0_data_master_granted_cpu_0_jtag_debug_module,
cpu_0_data_master_granted_input1_s1,
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_granted_nios_system_clock_0_in,
cpu_0_data_master_granted_nios_system_clock_1_in,
cpu_0_data_master_granted_onchip_memory2_0_s1,
cpu_0_data_master_granted_output1_s1,
cpu_0_data_master_granted_sdram_0_s1,
cpu_0_data_master_granted_sysid_control_slave,
cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave,
cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_data_master_qualified_request_input1_s1,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_nios_system_clock_0_in,
cpu_0_data_master_qualified_request_nios_system_clock_1_in,
cpu_0_data_master_qualified_request_onchip_memory2_0_s1,
cpu_0_data_master_qualified_request_output1_s1,
cpu_0_data_master_qualified_request_sdram_0_s1,
cpu_0_data_master_qualified_request_sysid_control_slave,
cpu_0_data_master_read,
cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_data_master_read_data_valid_input1_s1,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_nios_system_clock_0_in,
cpu_0_data_master_read_data_valid_nios_system_clock_1_in,
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_data_master_read_data_valid_output1_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_data_master_read_data_valid_sysid_control_slave,
cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave,
cpu_0_data_master_requests_clocks_avalon_clocks_slave,
cpu_0_data_master_requests_cpu_0_jtag_debug_module,
cpu_0_data_master_requests_input1_s1,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_nios_system_clock_0_in,
cpu_0_data_master_requests_nios_system_clock_1_in,
cpu_0_data_master_requests_onchip_memory2_0_s1,
cpu_0_data_master_requests_output1_s1,
cpu_0_data_master_requests_sdram_0_s1,
cpu_0_data_master_requests_sysid_control_slave,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer,
d1_clocks_avalon_clocks_slave_end_xfer,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_input1_s1_end_xfer,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
d1_nios_system_clock_0_in_end_xfer,
d1_nios_system_clock_1_in_end_xfer,
d1_onchip_memory2_0_s1_end_xfer,
d1_output1_s1_end_xfer,
d1_sdram_0_s1_end_xfer,
d1_sysid_control_slave_end_xfer,
input1_s1_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
nios_system_clock_0_in_readdata_from_sa,
nios_system_clock_0_in_waitrequest_from_sa,
nios_system_clock_1_in_readdata_from_sa,
nios_system_clock_1_in_waitrequest_from_sa,
onchip_memory2_0_s1_readdata_from_sa,
output1_s1_readdata_from_sa,
registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
reset_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_waitrequest_from_sa,
sysid_control_slave_readdata_from_sa,
// outputs:
cpu_0_data_master_address_to_slave,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_irq,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_readdata,
cpu_0_data_master_waitrequest
)
;
output [ 27: 0] cpu_0_data_master_address_to_slave;
output [ 1: 0] cpu_0_data_master_dbs_address;
output [ 7: 0] cpu_0_data_master_dbs_write_8;
output [ 31: 0] cpu_0_data_master_irq;
output cpu_0_data_master_no_byte_enables_and_last_term;
output [ 31: 0] cpu_0_data_master_readdata;
output cpu_0_data_master_waitrequest;
input [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
input Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
input clk;
input [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
input [ 27: 0] cpu_0_data_master_address;
input cpu_0_data_master_byteenable_nios_system_clock_1_in;
input cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_granted_clocks_avalon_clocks_slave;
input cpu_0_data_master_granted_cpu_0_jtag_debug_module;
input cpu_0_data_master_granted_input1_s1;
input cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_granted_nios_system_clock_0_in;
input cpu_0_data_master_granted_nios_system_clock_1_in;
input cpu_0_data_master_granted_onchip_memory2_0_s1;
input cpu_0_data_master_granted_output1_s1;
input cpu_0_data_master_granted_sdram_0_s1;
input cpu_0_data_master_granted_sysid_control_slave;
input cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
input cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_data_master_qualified_request_input1_s1;
input cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_qualified_request_nios_system_clock_0_in;
input cpu_0_data_master_qualified_request_nios_system_clock_1_in;
input cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
input cpu_0_data_master_qualified_request_output1_s1;
input cpu_0_data_master_qualified_request_sdram_0_s1;
input cpu_0_data_master_qualified_request_sysid_control_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_data_master_read_data_valid_input1_s1;
input cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
input cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
input cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input cpu_0_data_master_read_data_valid_output1_s1;
input cpu_0_data_master_read_data_valid_sdram_0_s1;
input cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
input cpu_0_data_master_read_data_valid_sysid_control_slave;
input cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
input cpu_0_data_master_requests_clocks_avalon_clocks_slave;
input cpu_0_data_master_requests_cpu_0_jtag_debug_module;
input cpu_0_data_master_requests_input1_s1;
input cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
input cpu_0_data_master_requests_nios_system_clock_0_in;
input cpu_0_data_master_requests_nios_system_clock_1_in;
input cpu_0_data_master_requests_onchip_memory2_0_s1;
input cpu_0_data_master_requests_output1_s1;
input cpu_0_data_master_requests_sdram_0_s1;
input cpu_0_data_master_requests_sysid_control_slave;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
input d1_clocks_avalon_clocks_slave_end_xfer;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_input1_s1_end_xfer;
input d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
input d1_nios_system_clock_0_in_end_xfer;
input d1_nios_system_clock_1_in_end_xfer;
input d1_onchip_memory2_0_s1_end_xfer;
input d1_output1_s1_end_xfer;
input d1_sdram_0_s1_end_xfer;
input d1_sysid_control_slave_end_xfer;
input [ 31: 0] input1_s1_readdata_from_sa;
input jtag_uart_0_avalon_jtag_slave_irq_from_sa;
input [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
input jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
input [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
input nios_system_clock_0_in_waitrequest_from_sa;
input [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
input nios_system_clock_1_in_waitrequest_from_sa;
input [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
input [ 31: 0] output1_s1_readdata_from_sa;
input registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
input registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata_from_sa;
input sdram_0_s1_waitrequest_from_sa;
input [ 31: 0] sysid_control_slave_readdata_from_sa;
wire [ 27: 0] cpu_0_data_master_address_to_slave;
reg [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 1: 0] cpu_0_data_master_dbs_increment;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire [ 31: 0] cpu_0_data_master_irq;
reg cpu_0_data_master_no_byte_enables_and_last_term;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_run;
reg cpu_0_data_master_waitrequest;
reg [ 7: 0] dbs_8_reg_segment_0;
reg [ 7: 0] dbs_8_reg_segment_1;
reg [ 7: 0] dbs_8_reg_segment_2;
wire dbs_count_enable;
wire dbs_counter_overflow;
wire last_dbs_term_and_run;
wire [ 1: 0] next_dbs_address;
wire [ 7: 0] p1_dbs_8_reg_segment_0;
wire [ 7: 0] p1_dbs_8_reg_segment_1;
wire [ 7: 0] p1_dbs_8_reg_segment_2;
wire [ 31: 0] p1_registered_cpu_0_data_master_readdata;
wire pre_dbs_count_enable;
wire r_0;
wire r_1;
wire r_2;
reg [ 31: 0] registered_cpu_0_data_master_readdata;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave) & ((~cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) | ~cpu_0_data_master_requests_clocks_avalon_clocks_slave)) & ((~cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave | ~cpu_0_data_master_write | (1 & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_requests_cpu_0_jtag_debug_module) & (cpu_0_data_master_granted_cpu_0_jtag_debug_module | ~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & ((~cpu_0_data_master_qualified_request_input1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_input1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write))));
//cascaded wait assignment, which is an e_assign
assign cpu_0_data_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~cpu_0_data_master_requests_nios_system_clock_0_in) & ((~cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~nios_system_clock_0_in_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & ((~cpu_0_data_master_qualified_request_nios_system_clock_0_in | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~nios_system_clock_0_in_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((cpu_0_data_master_qualified_request_nios_system_clock_1_in | ((cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in & cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0])) | ~cpu_0_data_master_requests_nios_system_clock_1_in)) & ((~cpu_0_data_master_qualified_request_nios_system_clock_1_in | ~cpu_0_data_master_read | (1 & ~nios_system_clock_1_in_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_nios_system_clock_1_in | ~cpu_0_data_master_write | (1 & ~nios_system_clock_1_in_waitrequest_from_sa & (cpu_0_data_master_dbs_address[1] & cpu_0_data_master_dbs_address[0]) & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 | ~cpu_0_data_master_requests_onchip_memory2_0_s1) & (cpu_0_data_master_granted_onchip_memory2_0_s1 | ~cpu_0_data_master_qualified_request_onchip_memory2_0_s1) & ((~cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | ~cpu_0_data_master_read | (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & (cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_requests_output1_s1) & ((~cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_output1_s1 | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write))) & 1 & (cpu_0_data_master_qualified_request_sdram_0_s1 | cpu_0_data_master_read_data_valid_sdram_0_s1 | ~cpu_0_data_master_requests_sdram_0_s1) & (cpu_0_data_master_granted_sdram_0_s1 | ~cpu_0_data_master_qualified_request_sdram_0_s1);
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = ((~cpu_0_data_master_qualified_request_sdram_0_s1 | ~cpu_0_data_master_read | (cpu_0_data_master_read_data_valid_sdram_0_s1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sdram_0_s1 | ~(cpu_0_data_master_read | cpu_0_data_master_write) | (1 & ~sdram_0_s1_waitrequest_from_sa & (cpu_0_data_master_read | cpu_0_data_master_write)))) & 1 & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_read | (1 & 1 & cpu_0_data_master_read))) & ((~cpu_0_data_master_qualified_request_sysid_control_slave | ~cpu_0_data_master_write | (1 & cpu_0_data_master_write)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_data_master_address_to_slave = cpu_0_data_master_address[27 : 0];
//unpredictable registered wait state incoming data, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
registered_cpu_0_data_master_readdata <= 0;
else
registered_cpu_0_data_master_readdata <= p1_registered_cpu_0_data_master_readdata;
end
//registered readdata mux, which is an e_mux
assign p1_registered_cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave}} | Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | jtag_uart_0_avalon_jtag_slave_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_nios_system_clock_0_in}} | nios_system_clock_0_in_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_nios_system_clock_1_in}} | {nios_system_clock_1_in_readdata_from_sa[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_sdram_0_s1}} | sdram_0_s1_readdata_from_sa);
//cpu_0/data_master readdata mux, which is an e_mux
assign cpu_0_data_master_readdata = ({32 {~cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_clocks_avalon_clocks_slave}} | {clocks_avalon_clocks_slave_readdata_from_sa[7 : 0],
dbs_8_reg_segment_2,
dbs_8_reg_segment_1,
dbs_8_reg_segment_0}) &
({32 {~cpu_0_data_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_input1_s1}} | input1_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_nios_system_clock_0_in}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_nios_system_clock_1_in}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_onchip_memory2_0_s1}} | onchip_memory2_0_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_output1_s1}} | output1_s1_readdata_from_sa) &
({32 {~cpu_0_data_master_requests_sdram_0_s1}} | registered_cpu_0_data_master_readdata) &
({32 {~cpu_0_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa);
//actual waitrequest port, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_waitrequest <= ~0;
else
cpu_0_data_master_waitrequest <= ~((~(cpu_0_data_master_read | cpu_0_data_master_write))? 0: (cpu_0_data_master_run & cpu_0_data_master_waitrequest));
end
//input to dbs-8 stored 0, which is an e_mux
assign p1_dbs_8_reg_segment_0 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_0 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 0))
dbs_8_reg_segment_0 <= p1_dbs_8_reg_segment_0;
end
//input to dbs-8 stored 1, which is an e_mux
assign p1_dbs_8_reg_segment_1 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_1 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 1))
dbs_8_reg_segment_1 <= p1_dbs_8_reg_segment_1;
end
//input to dbs-8 stored 2, which is an e_mux
assign p1_dbs_8_reg_segment_2 = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? clocks_avalon_clocks_slave_readdata_from_sa :
nios_system_clock_1_in_readdata_from_sa;
//dbs register for dbs-8 segment 2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
dbs_8_reg_segment_2 <= 0;
else if (dbs_count_enable & ((cpu_0_data_master_dbs_address[1 : 0]) == 2))
dbs_8_reg_segment_2 <= p1_dbs_8_reg_segment_2;
end
//dbs count increment, which is an e_mux
assign cpu_0_data_master_dbs_increment = (cpu_0_data_master_requests_clocks_avalon_clocks_slave)? 1 :
(cpu_0_data_master_requests_nios_system_clock_1_in)? 1 :
0;
//dbs counter overflow, which is an e_assign
assign dbs_counter_overflow = cpu_0_data_master_dbs_address[1] & !(next_dbs_address[1]);
//next master address, which is an e_assign
assign next_dbs_address = cpu_0_data_master_dbs_address + cpu_0_data_master_dbs_increment;
//dbs count enable, which is an e_mux
assign dbs_count_enable = pre_dbs_count_enable &
(~(cpu_0_data_master_requests_clocks_avalon_clocks_slave & ~cpu_0_data_master_waitrequest & cpu_0_data_master_write)) &
(~(cpu_0_data_master_requests_nios_system_clock_1_in & ~cpu_0_data_master_waitrequest));
//dbs counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_dbs_address <= 0;
else if (dbs_count_enable)
cpu_0_data_master_dbs_address <= next_dbs_address;
end
//pre dbs count enable, which is an e_mux
assign pre_dbs_count_enable = cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave |
(cpu_0_data_master_granted_clocks_avalon_clocks_slave & cpu_0_data_master_write & 1 & 1) |
(((~cpu_0_data_master_no_byte_enables_and_last_term) & cpu_0_data_master_requests_nios_system_clock_1_in & cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in)) |
(cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read & 1 & 1 & ~nios_system_clock_1_in_waitrequest_from_sa) |
(cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write & 1 & 1 & ~nios_system_clock_1_in_waitrequest_from_sa);
//irq assign, which is an e_assign
assign cpu_0_data_master_irq = {1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
1'b0,
jtag_uart_0_avalon_jtag_slave_irq_from_sa};
//no_byte_enables_and_last_term, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_no_byte_enables_and_last_term <= 0;
else
cpu_0_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
end
//compute the last dbs term, which is an e_mux
assign last_dbs_term_and_run = (cpu_0_data_master_dbs_address == 2'b11) & cpu_0_data_master_write & !cpu_0_data_master_byteenable_nios_system_clock_1_in;
//mux write dbs 2, which is an e_mux
assign cpu_0_data_master_dbs_write_8 = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_writedata[7 : 0] :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_writedata[15 : 8] :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_writedata[23 : 16] :
cpu_0_data_master_writedata[31 : 24];
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module cpu_0_instruction_master_arbitrator (
// inputs:
clk,
cpu_0_instruction_master_address,
cpu_0_instruction_master_granted_cpu_0_jtag_debug_module,
cpu_0_instruction_master_granted_onchip_memory2_0_s1,
cpu_0_instruction_master_granted_sdram_0_s1,
cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module,
cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1,
cpu_0_instruction_master_qualified_request_sdram_0_s1,
cpu_0_instruction_master_read,
cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module,
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_instruction_master_requests_cpu_0_jtag_debug_module,
cpu_0_instruction_master_requests_onchip_memory2_0_s1,
cpu_0_instruction_master_requests_sdram_0_s1,
cpu_0_jtag_debug_module_readdata_from_sa,
d1_cpu_0_jtag_debug_module_end_xfer,
d1_onchip_memory2_0_s1_end_xfer,
d1_sdram_0_s1_end_xfer,
onchip_memory2_0_s1_readdata_from_sa,
reset_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_waitrequest_from_sa,
// outputs:
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_readdata,
cpu_0_instruction_master_waitrequest
)
;
output [ 27: 0] cpu_0_instruction_master_address_to_slave;
output [ 31: 0] cpu_0_instruction_master_readdata;
output cpu_0_instruction_master_waitrequest;
input clk;
input [ 27: 0] cpu_0_instruction_master_address;
input cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_granted_onchip_memory2_0_s1;
input cpu_0_instruction_master_granted_sdram_0_s1;
input cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
input cpu_0_instruction_master_qualified_request_sdram_0_s1;
input cpu_0_instruction_master_read;
input cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
input cpu_0_instruction_master_read_data_valid_sdram_0_s1;
input cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
input cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
input cpu_0_instruction_master_requests_onchip_memory2_0_s1;
input cpu_0_instruction_master_requests_sdram_0_s1;
input [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
input d1_cpu_0_jtag_debug_module_end_xfer;
input d1_onchip_memory2_0_s1_end_xfer;
input d1_sdram_0_s1_end_xfer;
input [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata_from_sa;
input sdram_0_s1_waitrequest_from_sa;
reg active_and_waiting_last_time;
reg [ 27: 0] cpu_0_instruction_master_address_last_time;
wire [ 27: 0] cpu_0_instruction_master_address_to_slave;
reg cpu_0_instruction_master_read_last_time;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_run;
wire cpu_0_instruction_master_waitrequest;
wire r_0;
wire r_1;
wire r_2;
//r_0 master_run cascaded wait assignment, which is an e_assign
assign r_0 = 1 & (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module) & (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module) & ((~cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module | ~cpu_0_instruction_master_read | (1 & ~d1_cpu_0_jtag_debug_module_end_xfer & cpu_0_instruction_master_read)));
//cascaded wait assignment, which is an e_assign
assign cpu_0_instruction_master_run = r_0 & r_1 & r_2;
//r_1 master_run cascaded wait assignment, which is an e_assign
assign r_1 = 1 & (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 | cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 | ~cpu_0_instruction_master_requests_onchip_memory2_0_s1) & (cpu_0_instruction_master_granted_onchip_memory2_0_s1 | ~cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1) & ((~cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 & cpu_0_instruction_master_read))) & 1 & (cpu_0_instruction_master_qualified_request_sdram_0_s1 | cpu_0_instruction_master_read_data_valid_sdram_0_s1 | ~cpu_0_instruction_master_requests_sdram_0_s1);
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = (cpu_0_instruction_master_granted_sdram_0_s1 | ~cpu_0_instruction_master_qualified_request_sdram_0_s1) & ((~cpu_0_instruction_master_qualified_request_sdram_0_s1 | ~cpu_0_instruction_master_read | (cpu_0_instruction_master_read_data_valid_sdram_0_s1 & cpu_0_instruction_master_read)));
//optimize select-logic by passing only those address bits which matter.
assign cpu_0_instruction_master_address_to_slave = cpu_0_instruction_master_address[27 : 0];
//cpu_0/instruction_master readdata mux, which is an e_mux
assign cpu_0_instruction_master_readdata = ({32 {~cpu_0_instruction_master_requests_cpu_0_jtag_debug_module}} | cpu_0_jtag_debug_module_readdata_from_sa) &
({32 {~cpu_0_instruction_master_requests_onchip_memory2_0_s1}} | onchip_memory2_0_s1_readdata_from_sa) &
({32 {~cpu_0_instruction_master_requests_sdram_0_s1}} | sdram_0_s1_readdata_from_sa);
//actual waitrequest port, which is an e_assign
assign cpu_0_instruction_master_waitrequest = ~cpu_0_instruction_master_run;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//cpu_0_instruction_master_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_address_last_time <= 0;
else
cpu_0_instruction_master_address_last_time <= cpu_0_instruction_master_address;
end
//cpu_0/instruction_master waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= cpu_0_instruction_master_waitrequest & (cpu_0_instruction_master_read);
end
//cpu_0_instruction_master_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_address != cpu_0_instruction_master_address_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_address did not heed wait!!!", $time);
$stop;
end
end
//cpu_0_instruction_master_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_last_time <= 0;
else
cpu_0_instruction_master_read_last_time <= cpu_0_instruction_master_read;
end
//cpu_0_instruction_master_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (cpu_0_instruction_master_read != cpu_0_instruction_master_read_last_time))
begin
$write("%0d ns: cpu_0_instruction_master_read did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module input1_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
input1_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_input1_s1,
cpu_0_data_master_qualified_request_input1_s1,
cpu_0_data_master_read_data_valid_input1_s1,
cpu_0_data_master_requests_input1_s1,
d1_input1_s1_end_xfer,
input1_s1_address,
input1_s1_readdata_from_sa,
input1_s1_reset_n
)
;
output cpu_0_data_master_granted_input1_s1;
output cpu_0_data_master_qualified_request_input1_s1;
output cpu_0_data_master_read_data_valid_input1_s1;
output cpu_0_data_master_requests_input1_s1;
output d1_input1_s1_end_xfer;
output [ 1: 0] input1_s1_address;
output [ 31: 0] input1_s1_readdata_from_sa;
output input1_s1_reset_n;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input [ 31: 0] input1_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_input1_s1;
wire cpu_0_data_master_qualified_request_input1_s1;
wire cpu_0_data_master_read_data_valid_input1_s1;
wire cpu_0_data_master_requests_input1_s1;
wire cpu_0_data_master_saved_grant_input1_s1;
reg d1_input1_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_input1_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] input1_s1_address;
wire input1_s1_allgrants;
wire input1_s1_allow_new_arb_cycle;
wire input1_s1_any_bursting_master_saved_grant;
wire input1_s1_any_continuerequest;
wire input1_s1_arb_counter_enable;
reg [ 2: 0] input1_s1_arb_share_counter;
wire [ 2: 0] input1_s1_arb_share_counter_next_value;
wire [ 2: 0] input1_s1_arb_share_set_values;
wire input1_s1_beginbursttransfer_internal;
wire input1_s1_begins_xfer;
wire input1_s1_end_xfer;
wire input1_s1_firsttransfer;
wire input1_s1_grant_vector;
wire input1_s1_in_a_read_cycle;
wire input1_s1_in_a_write_cycle;
wire input1_s1_master_qreq_vector;
wire input1_s1_non_bursting_master_requests;
wire [ 31: 0] input1_s1_readdata_from_sa;
reg input1_s1_reg_firsttransfer;
wire input1_s1_reset_n;
reg input1_s1_slavearbiterlockenable;
wire input1_s1_slavearbiterlockenable2;
wire input1_s1_unreg_firsttransfer;
wire input1_s1_waits_for_read;
wire input1_s1_waits_for_write;
wire [ 27: 0] shifted_address_to_input1_s1_from_cpu_0_data_master;
wire wait_for_input1_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~input1_s1_end_xfer;
end
assign input1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_input1_s1));
//assign input1_s1_readdata_from_sa = input1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign input1_s1_readdata_from_sa = input1_s1_readdata;
assign cpu_0_data_master_requests_input1_s1 = (({cpu_0_data_master_address_to_slave[27 : 4] , 4'b0} == 28'h10) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//input1_s1_arb_share_counter set values, which is an e_mux
assign input1_s1_arb_share_set_values = 1;
//input1_s1_non_bursting_master_requests mux, which is an e_mux
assign input1_s1_non_bursting_master_requests = cpu_0_data_master_requests_input1_s1;
//input1_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign input1_s1_any_bursting_master_saved_grant = 0;
//input1_s1_arb_share_counter_next_value assignment, which is an e_assign
assign input1_s1_arb_share_counter_next_value = input1_s1_firsttransfer ? (input1_s1_arb_share_set_values - 1) : |input1_s1_arb_share_counter ? (input1_s1_arb_share_counter - 1) : 0;
//input1_s1_allgrants all slave grants, which is an e_mux
assign input1_s1_allgrants = |input1_s1_grant_vector;
//input1_s1_end_xfer assignment, which is an e_assign
assign input1_s1_end_xfer = ~(input1_s1_waits_for_read | input1_s1_waits_for_write);
//end_xfer_arb_share_counter_term_input1_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_input1_s1 = input1_s1_end_xfer & (~input1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//input1_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign input1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_input1_s1 & input1_s1_allgrants) | (end_xfer_arb_share_counter_term_input1_s1 & ~input1_s1_non_bursting_master_requests);
//input1_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_arb_share_counter <= 0;
else if (input1_s1_arb_counter_enable)
input1_s1_arb_share_counter <= input1_s1_arb_share_counter_next_value;
end
//input1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_slavearbiterlockenable <= 0;
else if ((|input1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_input1_s1) | (end_xfer_arb_share_counter_term_input1_s1 & ~input1_s1_non_bursting_master_requests))
input1_s1_slavearbiterlockenable <= |input1_s1_arb_share_counter_next_value;
end
//cpu_0/data_master input1/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = input1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//input1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign input1_s1_slavearbiterlockenable2 = |input1_s1_arb_share_counter_next_value;
//cpu_0/data_master input1/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = input1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//input1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign input1_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_input1_s1 = cpu_0_data_master_requests_input1_s1;
//master is always granted when requested
assign cpu_0_data_master_granted_input1_s1 = cpu_0_data_master_qualified_request_input1_s1;
//cpu_0/data_master saved-grant input1/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_input1_s1 = cpu_0_data_master_requests_input1_s1;
//allow new arb cycle for input1/s1, which is an e_assign
assign input1_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign input1_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign input1_s1_master_qreq_vector = 1;
//input1_s1_reset_n assignment, which is an e_assign
assign input1_s1_reset_n = reset_n;
//input1_s1_firsttransfer first transaction, which is an e_assign
assign input1_s1_firsttransfer = input1_s1_begins_xfer ? input1_s1_unreg_firsttransfer : input1_s1_reg_firsttransfer;
//input1_s1_unreg_firsttransfer first transaction, which is an e_assign
assign input1_s1_unreg_firsttransfer = ~(input1_s1_slavearbiterlockenable & input1_s1_any_continuerequest);
//input1_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
input1_s1_reg_firsttransfer <= 1'b1;
else if (input1_s1_begins_xfer)
input1_s1_reg_firsttransfer <= input1_s1_unreg_firsttransfer;
end
//input1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign input1_s1_beginbursttransfer_internal = input1_s1_begins_xfer;
assign shifted_address_to_input1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//input1_s1_address mux, which is an e_mux
assign input1_s1_address = shifted_address_to_input1_s1_from_cpu_0_data_master >> 2;
//d1_input1_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_input1_s1_end_xfer <= 1;
else
d1_input1_s1_end_xfer <= input1_s1_end_xfer;
end
//input1_s1_waits_for_read in a cycle, which is an e_mux
assign input1_s1_waits_for_read = input1_s1_in_a_read_cycle & input1_s1_begins_xfer;
//input1_s1_in_a_read_cycle assignment, which is an e_assign
assign input1_s1_in_a_read_cycle = cpu_0_data_master_granted_input1_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = input1_s1_in_a_read_cycle;
//input1_s1_waits_for_write in a cycle, which is an e_mux
assign input1_s1_waits_for_write = input1_s1_in_a_write_cycle & 0;
//input1_s1_in_a_write_cycle assignment, which is an e_assign
assign input1_s1_in_a_write_cycle = cpu_0_data_master_granted_input1_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = input1_s1_in_a_write_cycle;
assign wait_for_input1_s1_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//input1/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module jtag_uart_0_avalon_jtag_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
jtag_uart_0_avalon_jtag_slave_dataavailable,
jtag_uart_0_avalon_jtag_slave_irq,
jtag_uart_0_avalon_jtag_slave_readdata,
jtag_uart_0_avalon_jtag_slave_readyfordata,
jtag_uart_0_avalon_jtag_slave_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave,
cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave,
d1_jtag_uart_0_avalon_jtag_slave_end_xfer,
jtag_uart_0_avalon_jtag_slave_address,
jtag_uart_0_avalon_jtag_slave_chipselect,
jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa,
jtag_uart_0_avalon_jtag_slave_irq_from_sa,
jtag_uart_0_avalon_jtag_slave_read_n,
jtag_uart_0_avalon_jtag_slave_readdata_from_sa,
jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa,
jtag_uart_0_avalon_jtag_slave_reset_n,
jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa,
jtag_uart_0_avalon_jtag_slave_write_n,
jtag_uart_0_avalon_jtag_slave_writedata
)
;
output cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
output cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
output d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
output jtag_uart_0_avalon_jtag_slave_address;
output jtag_uart_0_avalon_jtag_slave_chipselect;
output jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
output jtag_uart_0_avalon_jtag_slave_irq_from_sa;
output jtag_uart_0_avalon_jtag_slave_read_n;
output [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
output jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
output jtag_uart_0_avalon_jtag_slave_reset_n;
output jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
output jtag_uart_0_avalon_jtag_slave_write_n;
output [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input jtag_uart_0_avalon_jtag_slave_dataavailable;
input jtag_uart_0_avalon_jtag_slave_irq;
input [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
input jtag_uart_0_avalon_jtag_slave_readyfordata;
input jtag_uart_0_avalon_jtag_slave_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave;
reg d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire jtag_uart_0_avalon_jtag_slave_address;
wire jtag_uart_0_avalon_jtag_slave_allgrants;
wire jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle;
wire jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant;
wire jtag_uart_0_avalon_jtag_slave_any_continuerequest;
wire jtag_uart_0_avalon_jtag_slave_arb_counter_enable;
reg [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter;
wire [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
wire [ 2: 0] jtag_uart_0_avalon_jtag_slave_arb_share_set_values;
wire jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal;
wire jtag_uart_0_avalon_jtag_slave_begins_xfer;
wire jtag_uart_0_avalon_jtag_slave_chipselect;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_end_xfer;
wire jtag_uart_0_avalon_jtag_slave_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_grant_vector;
wire jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
wire jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
wire jtag_uart_0_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_0_avalon_jtag_slave_master_qreq_vector;
wire jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests;
wire jtag_uart_0_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
reg jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_reset_n;
reg jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable;
wire jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2;
wire jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
wire jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_0_avalon_jtag_slave_waits_for_read;
wire jtag_uart_0_avalon_jtag_slave_waits_for_write;
wire jtag_uart_0_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
wire [ 27: 0] shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master;
wire wait_for_jtag_uart_0_avalon_jtag_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~jtag_uart_0_avalon_jtag_slave_end_xfer;
end
assign jtag_uart_0_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave));
//assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_readdata_from_sa = jtag_uart_0_avalon_jtag_slave_readdata;
assign cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave = ({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h20) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_0_avalon_jtag_slave_dataavailable;
//assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_0_avalon_jtag_slave_readyfordata;
//assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_0_avalon_jtag_slave_waitrequest;
//jtag_uart_0_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_arb_share_set_values = 1;
//jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
//jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant = 0;
//jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_0_avalon_jtag_slave_firsttransfer ? (jtag_uart_0_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_0_avalon_jtag_slave_arb_share_counter ? (jtag_uart_0_avalon_jtag_slave_arb_share_counter - 1) : 0;
//jtag_uart_0_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_allgrants = |jtag_uart_0_avalon_jtag_slave_grant_vector;
//jtag_uart_0_avalon_jtag_slave_end_xfer assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_end_xfer = ~(jtag_uart_0_avalon_jtag_slave_waits_for_read | jtag_uart_0_avalon_jtag_slave_waits_for_write);
//end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave = jtag_uart_0_avalon_jtag_slave_end_xfer & (~jtag_uart_0_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//jtag_uart_0_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & jtag_uart_0_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests);
//jtag_uart_0_avalon_jtag_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_arb_share_counter <= 0;
else if (jtag_uart_0_avalon_jtag_slave_arb_counter_enable)
jtag_uart_0_avalon_jtag_slave_arb_share_counter <= jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
end
//jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= 0;
else if ((|jtag_uart_0_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_0_avalon_jtag_slave & ~jtag_uart_0_avalon_jtag_slave_non_bursting_master_requests))
jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
end
//cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_0_avalon_jtag_slave_arb_share_counter_next_value;
//cpu_0/data_master jtag_uart_0/avalon_jtag_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//jtag_uart_0_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//jtag_uart_0_avalon_jtag_slave_writedata mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
//cpu_0/data_master saved-grant jtag_uart_0/avalon_jtag_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_jtag_uart_0_avalon_jtag_slave = cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
//allow new arb cycle for jtag_uart_0/avalon_jtag_slave, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign jtag_uart_0_avalon_jtag_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign jtag_uart_0_avalon_jtag_slave_master_qreq_vector = 1;
//jtag_uart_0_avalon_jtag_slave_reset_n assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_reset_n = reset_n;
assign jtag_uart_0_avalon_jtag_slave_chipselect = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
//jtag_uart_0_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_firsttransfer = jtag_uart_0_avalon_jtag_slave_begins_xfer ? jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_0_avalon_jtag_slave_reg_firsttransfer;
//jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_0_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_0_avalon_jtag_slave_any_continuerequest);
//jtag_uart_0_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
else if (jtag_uart_0_avalon_jtag_slave_begins_xfer)
jtag_uart_0_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_0_avalon_jtag_slave_unreg_firsttransfer;
end
//jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_0_avalon_jtag_slave_begins_xfer;
//~jtag_uart_0_avalon_jtag_slave_read_n assignment, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_read_n = ~(cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_read);
//~jtag_uart_0_avalon_jtag_slave_write_n assignment, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_write_n = ~(cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_write);
assign shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//jtag_uart_0_avalon_jtag_slave_address mux, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_address = shifted_address_to_jtag_uart_0_avalon_jtag_slave_from_cpu_0_data_master >> 2;
//d1_jtag_uart_0_avalon_jtag_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= 1;
else
d1_jtag_uart_0_avalon_jtag_slave_end_xfer <= jtag_uart_0_avalon_jtag_slave_end_xfer;
end
//jtag_uart_0_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_waits_for_read = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_0_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_in_a_read_cycle = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = jtag_uart_0_avalon_jtag_slave_in_a_read_cycle;
//jtag_uart_0_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
assign jtag_uart_0_avalon_jtag_slave_waits_for_write = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle & jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
//jtag_uart_0_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_in_a_write_cycle = cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = jtag_uart_0_avalon_jtag_slave_in_a_write_cycle;
assign wait_for_jtag_uart_0_avalon_jtag_slave_counter = 0;
//assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
assign jtag_uart_0_avalon_jtag_slave_irq_from_sa = jtag_uart_0_avalon_jtag_slave_irq;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//jtag_uart_0/avalon_jtag_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_0_in_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
nios_system_clock_0_in_endofpacket,
nios_system_clock_0_in_readdata,
nios_system_clock_0_in_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_granted_nios_system_clock_0_in,
cpu_0_data_master_qualified_request_nios_system_clock_0_in,
cpu_0_data_master_read_data_valid_nios_system_clock_0_in,
cpu_0_data_master_requests_nios_system_clock_0_in,
d1_nios_system_clock_0_in_end_xfer,
nios_system_clock_0_in_address,
nios_system_clock_0_in_byteenable,
nios_system_clock_0_in_endofpacket_from_sa,
nios_system_clock_0_in_nativeaddress,
nios_system_clock_0_in_read,
nios_system_clock_0_in_readdata_from_sa,
nios_system_clock_0_in_reset_n,
nios_system_clock_0_in_waitrequest_from_sa,
nios_system_clock_0_in_write,
nios_system_clock_0_in_writedata
)
;
output cpu_0_data_master_granted_nios_system_clock_0_in;
output cpu_0_data_master_qualified_request_nios_system_clock_0_in;
output cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
output cpu_0_data_master_requests_nios_system_clock_0_in;
output d1_nios_system_clock_0_in_end_xfer;
output [ 2: 0] nios_system_clock_0_in_address;
output [ 3: 0] nios_system_clock_0_in_byteenable;
output nios_system_clock_0_in_endofpacket_from_sa;
output nios_system_clock_0_in_nativeaddress;
output nios_system_clock_0_in_read;
output [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
output nios_system_clock_0_in_reset_n;
output nios_system_clock_0_in_waitrequest_from_sa;
output nios_system_clock_0_in_write;
output [ 31: 0] nios_system_clock_0_in_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input nios_system_clock_0_in_endofpacket;
input [ 31: 0] nios_system_clock_0_in_readdata;
input nios_system_clock_0_in_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_nios_system_clock_0_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_0_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
wire cpu_0_data_master_requests_nios_system_clock_0_in;
wire cpu_0_data_master_saved_grant_nios_system_clock_0_in;
reg d1_nios_system_clock_0_in_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_nios_system_clock_0_in;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 2: 0] nios_system_clock_0_in_address;
wire nios_system_clock_0_in_allgrants;
wire nios_system_clock_0_in_allow_new_arb_cycle;
wire nios_system_clock_0_in_any_bursting_master_saved_grant;
wire nios_system_clock_0_in_any_continuerequest;
wire nios_system_clock_0_in_arb_counter_enable;
reg [ 2: 0] nios_system_clock_0_in_arb_share_counter;
wire [ 2: 0] nios_system_clock_0_in_arb_share_counter_next_value;
wire [ 2: 0] nios_system_clock_0_in_arb_share_set_values;
wire nios_system_clock_0_in_beginbursttransfer_internal;
wire nios_system_clock_0_in_begins_xfer;
wire [ 3: 0] nios_system_clock_0_in_byteenable;
wire nios_system_clock_0_in_end_xfer;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_in_firsttransfer;
wire nios_system_clock_0_in_grant_vector;
wire nios_system_clock_0_in_in_a_read_cycle;
wire nios_system_clock_0_in_in_a_write_cycle;
wire nios_system_clock_0_in_master_qreq_vector;
wire nios_system_clock_0_in_nativeaddress;
wire nios_system_clock_0_in_non_bursting_master_requests;
wire nios_system_clock_0_in_read;
wire [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
reg nios_system_clock_0_in_reg_firsttransfer;
wire nios_system_clock_0_in_reset_n;
reg nios_system_clock_0_in_slavearbiterlockenable;
wire nios_system_clock_0_in_slavearbiterlockenable2;
wire nios_system_clock_0_in_unreg_firsttransfer;
wire nios_system_clock_0_in_waitrequest_from_sa;
wire nios_system_clock_0_in_waits_for_read;
wire nios_system_clock_0_in_waits_for_write;
wire nios_system_clock_0_in_write;
wire [ 31: 0] nios_system_clock_0_in_writedata;
wire wait_for_nios_system_clock_0_in_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~nios_system_clock_0_in_end_xfer;
end
assign nios_system_clock_0_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_nios_system_clock_0_in));
//assign nios_system_clock_0_in_readdata_from_sa = nios_system_clock_0_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_readdata_from_sa = nios_system_clock_0_in_readdata;
assign cpu_0_data_master_requests_nios_system_clock_0_in = ({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h38) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign nios_system_clock_0_in_waitrequest_from_sa = nios_system_clock_0_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_waitrequest_from_sa = nios_system_clock_0_in_waitrequest;
//nios_system_clock_0_in_arb_share_counter set values, which is an e_mux
assign nios_system_clock_0_in_arb_share_set_values = 1;
//nios_system_clock_0_in_non_bursting_master_requests mux, which is an e_mux
assign nios_system_clock_0_in_non_bursting_master_requests = cpu_0_data_master_requests_nios_system_clock_0_in;
//nios_system_clock_0_in_any_bursting_master_saved_grant mux, which is an e_mux
assign nios_system_clock_0_in_any_bursting_master_saved_grant = 0;
//nios_system_clock_0_in_arb_share_counter_next_value assignment, which is an e_assign
assign nios_system_clock_0_in_arb_share_counter_next_value = nios_system_clock_0_in_firsttransfer ? (nios_system_clock_0_in_arb_share_set_values - 1) : |nios_system_clock_0_in_arb_share_counter ? (nios_system_clock_0_in_arb_share_counter - 1) : 0;
//nios_system_clock_0_in_allgrants all slave grants, which is an e_mux
assign nios_system_clock_0_in_allgrants = |nios_system_clock_0_in_grant_vector;
//nios_system_clock_0_in_end_xfer assignment, which is an e_assign
assign nios_system_clock_0_in_end_xfer = ~(nios_system_clock_0_in_waits_for_read | nios_system_clock_0_in_waits_for_write);
//end_xfer_arb_share_counter_term_nios_system_clock_0_in arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_nios_system_clock_0_in = nios_system_clock_0_in_end_xfer & (~nios_system_clock_0_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//nios_system_clock_0_in_arb_share_counter arbitration counter enable, which is an e_assign
assign nios_system_clock_0_in_arb_counter_enable = (end_xfer_arb_share_counter_term_nios_system_clock_0_in & nios_system_clock_0_in_allgrants) | (end_xfer_arb_share_counter_term_nios_system_clock_0_in & ~nios_system_clock_0_in_non_bursting_master_requests);
//nios_system_clock_0_in_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_arb_share_counter <= 0;
else if (nios_system_clock_0_in_arb_counter_enable)
nios_system_clock_0_in_arb_share_counter <= nios_system_clock_0_in_arb_share_counter_next_value;
end
//nios_system_clock_0_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_slavearbiterlockenable <= 0;
else if ((|nios_system_clock_0_in_master_qreq_vector & end_xfer_arb_share_counter_term_nios_system_clock_0_in) | (end_xfer_arb_share_counter_term_nios_system_clock_0_in & ~nios_system_clock_0_in_non_bursting_master_requests))
nios_system_clock_0_in_slavearbiterlockenable <= |nios_system_clock_0_in_arb_share_counter_next_value;
end
//cpu_0/data_master nios_system_clock_0/in arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = nios_system_clock_0_in_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//nios_system_clock_0_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign nios_system_clock_0_in_slavearbiterlockenable2 = |nios_system_clock_0_in_arb_share_counter_next_value;
//cpu_0/data_master nios_system_clock_0/in arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = nios_system_clock_0_in_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//nios_system_clock_0_in_any_continuerequest at least one master continues requesting, which is an e_assign
assign nios_system_clock_0_in_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_nios_system_clock_0_in = cpu_0_data_master_requests_nios_system_clock_0_in & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//nios_system_clock_0_in_writedata mux, which is an e_mux
assign nios_system_clock_0_in_writedata = cpu_0_data_master_writedata;
//assign nios_system_clock_0_in_endofpacket_from_sa = nios_system_clock_0_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_0_in_endofpacket_from_sa = nios_system_clock_0_in_endofpacket;
//master is always granted when requested
assign cpu_0_data_master_granted_nios_system_clock_0_in = cpu_0_data_master_qualified_request_nios_system_clock_0_in;
//cpu_0/data_master saved-grant nios_system_clock_0/in, which is an e_assign
assign cpu_0_data_master_saved_grant_nios_system_clock_0_in = cpu_0_data_master_requests_nios_system_clock_0_in;
//allow new arb cycle for nios_system_clock_0/in, which is an e_assign
assign nios_system_clock_0_in_allow_new_arb_cycle = 1;
//placeholder chosen master
assign nios_system_clock_0_in_grant_vector = 1;
//placeholder vector of master qualified-requests
assign nios_system_clock_0_in_master_qreq_vector = 1;
//nios_system_clock_0_in_reset_n assignment, which is an e_assign
assign nios_system_clock_0_in_reset_n = reset_n;
//nios_system_clock_0_in_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_0_in_firsttransfer = nios_system_clock_0_in_begins_xfer ? nios_system_clock_0_in_unreg_firsttransfer : nios_system_clock_0_in_reg_firsttransfer;
//nios_system_clock_0_in_unreg_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_0_in_unreg_firsttransfer = ~(nios_system_clock_0_in_slavearbiterlockenable & nios_system_clock_0_in_any_continuerequest);
//nios_system_clock_0_in_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_in_reg_firsttransfer <= 1'b1;
else if (nios_system_clock_0_in_begins_xfer)
nios_system_clock_0_in_reg_firsttransfer <= nios_system_clock_0_in_unreg_firsttransfer;
end
//nios_system_clock_0_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign nios_system_clock_0_in_beginbursttransfer_internal = nios_system_clock_0_in_begins_xfer;
//nios_system_clock_0_in_read assignment, which is an e_mux
assign nios_system_clock_0_in_read = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_read;
//nios_system_clock_0_in_write assignment, which is an e_mux
assign nios_system_clock_0_in_write = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_write;
//nios_system_clock_0_in_address mux, which is an e_mux
assign nios_system_clock_0_in_address = cpu_0_data_master_address_to_slave;
//slaveid nios_system_clock_0_in_nativeaddress nativeaddress mux, which is an e_mux
assign nios_system_clock_0_in_nativeaddress = cpu_0_data_master_address_to_slave >> 2;
//d1_nios_system_clock_0_in_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_nios_system_clock_0_in_end_xfer <= 1;
else
d1_nios_system_clock_0_in_end_xfer <= nios_system_clock_0_in_end_xfer;
end
//nios_system_clock_0_in_waits_for_read in a cycle, which is an e_mux
assign nios_system_clock_0_in_waits_for_read = nios_system_clock_0_in_in_a_read_cycle & nios_system_clock_0_in_waitrequest_from_sa;
//nios_system_clock_0_in_in_a_read_cycle assignment, which is an e_assign
assign nios_system_clock_0_in_in_a_read_cycle = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = nios_system_clock_0_in_in_a_read_cycle;
//nios_system_clock_0_in_waits_for_write in a cycle, which is an e_mux
assign nios_system_clock_0_in_waits_for_write = nios_system_clock_0_in_in_a_write_cycle & nios_system_clock_0_in_waitrequest_from_sa;
//nios_system_clock_0_in_in_a_write_cycle assignment, which is an e_assign
assign nios_system_clock_0_in_in_a_write_cycle = cpu_0_data_master_granted_nios_system_clock_0_in & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = nios_system_clock_0_in_in_a_write_cycle;
assign wait_for_nios_system_clock_0_in_counter = 0;
//nios_system_clock_0_in_byteenable byte enable port mux, which is an e_mux
assign nios_system_clock_0_in_byteenable = (cpu_0_data_master_granted_nios_system_clock_0_in)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_0/in enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_0_out_arbitrator (
// inputs:
clk,
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer,
nios_system_clock_0_out_address,
nios_system_clock_0_out_byteenable,
nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_read,
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_write,
nios_system_clock_0_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa,
// outputs:
nios_system_clock_0_out_address_to_slave,
nios_system_clock_0_out_readdata,
nios_system_clock_0_out_reset_n,
nios_system_clock_0_out_waitrequest
)
;
output [ 2: 0] nios_system_clock_0_out_address_to_slave;
output [ 31: 0] nios_system_clock_0_out_readdata;
output nios_system_clock_0_out_reset_n;
output nios_system_clock_0_out_waitrequest;
input clk;
input d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
input [ 2: 0] nios_system_clock_0_out_address;
input [ 3: 0] nios_system_clock_0_out_byteenable;
input nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_read;
input nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
input nios_system_clock_0_out_write;
input [ 31: 0] nios_system_clock_0_out_writedata;
input reset_n;
input [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
reg active_and_waiting_last_time;
reg [ 2: 0] nios_system_clock_0_out_address_last_time;
wire [ 2: 0] nios_system_clock_0_out_address_to_slave;
reg [ 3: 0] nios_system_clock_0_out_byteenable_last_time;
reg nios_system_clock_0_out_read_last_time;
wire [ 31: 0] nios_system_clock_0_out_readdata;
wire nios_system_clock_0_out_reset_n;
wire nios_system_clock_0_out_run;
wire nios_system_clock_0_out_waitrequest;
reg nios_system_clock_0_out_write_last_time;
reg [ 31: 0] nios_system_clock_0_out_writedata_last_time;
wire r_2;
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave | ~nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave) & ((~nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | ~nios_system_clock_0_out_read | (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read))) & ((~nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave | ~(nios_system_clock_0_out_read | nios_system_clock_0_out_write) | (1 & (nios_system_clock_0_out_read | nios_system_clock_0_out_write))));
//cascaded wait assignment, which is an e_assign
assign nios_system_clock_0_out_run = r_2;
//optimize select-logic by passing only those address bits which matter.
assign nios_system_clock_0_out_address_to_slave = nios_system_clock_0_out_address;
//nios_system_clock_0/out readdata mux, which is an e_mux
assign nios_system_clock_0_out_readdata = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
//actual waitrequest port, which is an e_assign
assign nios_system_clock_0_out_waitrequest = ~nios_system_clock_0_out_run;
//nios_system_clock_0_out_reset_n assignment, which is an e_assign
assign nios_system_clock_0_out_reset_n = reset_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_0_out_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_address_last_time <= 0;
else
nios_system_clock_0_out_address_last_time <= nios_system_clock_0_out_address;
end
//nios_system_clock_0/out waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= nios_system_clock_0_out_waitrequest & (nios_system_clock_0_out_read | nios_system_clock_0_out_write);
end
//nios_system_clock_0_out_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_address != nios_system_clock_0_out_address_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_address did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_byteenable check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_byteenable_last_time <= 0;
else
nios_system_clock_0_out_byteenable_last_time <= nios_system_clock_0_out_byteenable;
end
//nios_system_clock_0_out_byteenable matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_byteenable != nios_system_clock_0_out_byteenable_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_byteenable did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_read_last_time <= 0;
else
nios_system_clock_0_out_read_last_time <= nios_system_clock_0_out_read;
end
//nios_system_clock_0_out_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_read != nios_system_clock_0_out_read_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_read did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_write_last_time <= 0;
else
nios_system_clock_0_out_write_last_time <= nios_system_clock_0_out_write;
end
//nios_system_clock_0_out_write matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_write != nios_system_clock_0_out_write_last_time))
begin
$write("%0d ns: nios_system_clock_0_out_write did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_0_out_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_writedata_last_time <= 0;
else
nios_system_clock_0_out_writedata_last_time <= nios_system_clock_0_out_writedata;
end
//nios_system_clock_0_out_writedata matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_0_out_writedata != nios_system_clock_0_out_writedata_last_time) & nios_system_clock_0_out_write)
begin
$write("%0d ns: nios_system_clock_0_out_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_1_in_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_dbs_address,
cpu_0_data_master_dbs_write_8,
cpu_0_data_master_no_byte_enables_and_last_term,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
nios_system_clock_1_in_endofpacket,
nios_system_clock_1_in_readdata,
nios_system_clock_1_in_waitrequest,
reset_n,
// outputs:
cpu_0_data_master_byteenable_nios_system_clock_1_in,
cpu_0_data_master_granted_nios_system_clock_1_in,
cpu_0_data_master_qualified_request_nios_system_clock_1_in,
cpu_0_data_master_read_data_valid_nios_system_clock_1_in,
cpu_0_data_master_requests_nios_system_clock_1_in,
d1_nios_system_clock_1_in_end_xfer,
nios_system_clock_1_in_address,
nios_system_clock_1_in_endofpacket_from_sa,
nios_system_clock_1_in_nativeaddress,
nios_system_clock_1_in_read,
nios_system_clock_1_in_readdata_from_sa,
nios_system_clock_1_in_reset_n,
nios_system_clock_1_in_waitrequest_from_sa,
nios_system_clock_1_in_write,
nios_system_clock_1_in_writedata
)
;
output cpu_0_data_master_byteenable_nios_system_clock_1_in;
output cpu_0_data_master_granted_nios_system_clock_1_in;
output cpu_0_data_master_qualified_request_nios_system_clock_1_in;
output cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
output cpu_0_data_master_requests_nios_system_clock_1_in;
output d1_nios_system_clock_1_in_end_xfer;
output [ 12: 0] nios_system_clock_1_in_address;
output nios_system_clock_1_in_endofpacket_from_sa;
output [ 12: 0] nios_system_clock_1_in_nativeaddress;
output nios_system_clock_1_in_read;
output [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
output nios_system_clock_1_in_reset_n;
output nios_system_clock_1_in_waitrequest_from_sa;
output nios_system_clock_1_in_write;
output [ 7: 0] nios_system_clock_1_in_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input [ 1: 0] cpu_0_data_master_dbs_address;
input [ 7: 0] cpu_0_data_master_dbs_write_8;
input cpu_0_data_master_no_byte_enables_and_last_term;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input nios_system_clock_1_in_endofpacket;
input [ 7: 0] nios_system_clock_1_in_readdata;
input nios_system_clock_1_in_waitrequest;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_nios_system_clock_1_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_1_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
wire cpu_0_data_master_requests_nios_system_clock_1_in;
wire cpu_0_data_master_saved_grant_nios_system_clock_1_in;
reg d1_nios_system_clock_1_in_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_nios_system_clock_1_in;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 12: 0] nios_system_clock_1_in_address;
wire nios_system_clock_1_in_allgrants;
wire nios_system_clock_1_in_allow_new_arb_cycle;
wire nios_system_clock_1_in_any_bursting_master_saved_grant;
wire nios_system_clock_1_in_any_continuerequest;
wire nios_system_clock_1_in_arb_counter_enable;
reg [ 2: 0] nios_system_clock_1_in_arb_share_counter;
wire [ 2: 0] nios_system_clock_1_in_arb_share_counter_next_value;
wire [ 2: 0] nios_system_clock_1_in_arb_share_set_values;
wire nios_system_clock_1_in_beginbursttransfer_internal;
wire nios_system_clock_1_in_begins_xfer;
wire nios_system_clock_1_in_end_xfer;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire nios_system_clock_1_in_firsttransfer;
wire nios_system_clock_1_in_grant_vector;
wire nios_system_clock_1_in_in_a_read_cycle;
wire nios_system_clock_1_in_in_a_write_cycle;
wire nios_system_clock_1_in_master_qreq_vector;
wire [ 12: 0] nios_system_clock_1_in_nativeaddress;
wire nios_system_clock_1_in_non_bursting_master_requests;
wire nios_system_clock_1_in_pretend_byte_enable;
wire nios_system_clock_1_in_read;
wire [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
reg nios_system_clock_1_in_reg_firsttransfer;
wire nios_system_clock_1_in_reset_n;
reg nios_system_clock_1_in_slavearbiterlockenable;
wire nios_system_clock_1_in_slavearbiterlockenable2;
wire nios_system_clock_1_in_unreg_firsttransfer;
wire nios_system_clock_1_in_waitrequest_from_sa;
wire nios_system_clock_1_in_waits_for_read;
wire nios_system_clock_1_in_waits_for_write;
wire nios_system_clock_1_in_write;
wire [ 7: 0] nios_system_clock_1_in_writedata;
wire wait_for_nios_system_clock_1_in_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~nios_system_clock_1_in_end_xfer;
end
assign nios_system_clock_1_in_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_nios_system_clock_1_in));
//assign nios_system_clock_1_in_readdata_from_sa = nios_system_clock_1_in_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_readdata_from_sa = nios_system_clock_1_in_readdata;
assign cpu_0_data_master_requests_nios_system_clock_1_in = ({cpu_0_data_master_address_to_slave[27 : 13] , 13'b0} == 28'h2000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign nios_system_clock_1_in_waitrequest_from_sa = nios_system_clock_1_in_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_waitrequest_from_sa = nios_system_clock_1_in_waitrequest;
//nios_system_clock_1_in_arb_share_counter set values, which is an e_mux
assign nios_system_clock_1_in_arb_share_set_values = (cpu_0_data_master_granted_nios_system_clock_1_in)? 4 :
1;
//nios_system_clock_1_in_non_bursting_master_requests mux, which is an e_mux
assign nios_system_clock_1_in_non_bursting_master_requests = cpu_0_data_master_requests_nios_system_clock_1_in;
//nios_system_clock_1_in_any_bursting_master_saved_grant mux, which is an e_mux
assign nios_system_clock_1_in_any_bursting_master_saved_grant = 0;
//nios_system_clock_1_in_arb_share_counter_next_value assignment, which is an e_assign
assign nios_system_clock_1_in_arb_share_counter_next_value = nios_system_clock_1_in_firsttransfer ? (nios_system_clock_1_in_arb_share_set_values - 1) : |nios_system_clock_1_in_arb_share_counter ? (nios_system_clock_1_in_arb_share_counter - 1) : 0;
//nios_system_clock_1_in_allgrants all slave grants, which is an e_mux
assign nios_system_clock_1_in_allgrants = |nios_system_clock_1_in_grant_vector;
//nios_system_clock_1_in_end_xfer assignment, which is an e_assign
assign nios_system_clock_1_in_end_xfer = ~(nios_system_clock_1_in_waits_for_read | nios_system_clock_1_in_waits_for_write);
//end_xfer_arb_share_counter_term_nios_system_clock_1_in arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_nios_system_clock_1_in = nios_system_clock_1_in_end_xfer & (~nios_system_clock_1_in_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//nios_system_clock_1_in_arb_share_counter arbitration counter enable, which is an e_assign
assign nios_system_clock_1_in_arb_counter_enable = (end_xfer_arb_share_counter_term_nios_system_clock_1_in & nios_system_clock_1_in_allgrants) | (end_xfer_arb_share_counter_term_nios_system_clock_1_in & ~nios_system_clock_1_in_non_bursting_master_requests);
//nios_system_clock_1_in_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_arb_share_counter <= 0;
else if (nios_system_clock_1_in_arb_counter_enable)
nios_system_clock_1_in_arb_share_counter <= nios_system_clock_1_in_arb_share_counter_next_value;
end
//nios_system_clock_1_in_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_slavearbiterlockenable <= 0;
else if ((|nios_system_clock_1_in_master_qreq_vector & end_xfer_arb_share_counter_term_nios_system_clock_1_in) | (end_xfer_arb_share_counter_term_nios_system_clock_1_in & ~nios_system_clock_1_in_non_bursting_master_requests))
nios_system_clock_1_in_slavearbiterlockenable <= |nios_system_clock_1_in_arb_share_counter_next_value;
end
//cpu_0/data_master nios_system_clock_1/in arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = nios_system_clock_1_in_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//nios_system_clock_1_in_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign nios_system_clock_1_in_slavearbiterlockenable2 = |nios_system_clock_1_in_arb_share_counter_next_value;
//cpu_0/data_master nios_system_clock_1/in arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = nios_system_clock_1_in_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//nios_system_clock_1_in_any_continuerequest at least one master continues requesting, which is an e_assign
assign nios_system_clock_1_in_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_nios_system_clock_1_in = cpu_0_data_master_requests_nios_system_clock_1_in & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest)) | ((~cpu_0_data_master_waitrequest | cpu_0_data_master_no_byte_enables_and_last_term | !cpu_0_data_master_byteenable_nios_system_clock_1_in) & cpu_0_data_master_write));
//nios_system_clock_1_in_writedata mux, which is an e_mux
assign nios_system_clock_1_in_writedata = cpu_0_data_master_dbs_write_8;
//assign nios_system_clock_1_in_endofpacket_from_sa = nios_system_clock_1_in_endofpacket so that symbol knows where to group signals which may go to master only, which is an e_assign
assign nios_system_clock_1_in_endofpacket_from_sa = nios_system_clock_1_in_endofpacket;
//master is always granted when requested
assign cpu_0_data_master_granted_nios_system_clock_1_in = cpu_0_data_master_qualified_request_nios_system_clock_1_in;
//cpu_0/data_master saved-grant nios_system_clock_1/in, which is an e_assign
assign cpu_0_data_master_saved_grant_nios_system_clock_1_in = cpu_0_data_master_requests_nios_system_clock_1_in;
//allow new arb cycle for nios_system_clock_1/in, which is an e_assign
assign nios_system_clock_1_in_allow_new_arb_cycle = 1;
//placeholder chosen master
assign nios_system_clock_1_in_grant_vector = 1;
//placeholder vector of master qualified-requests
assign nios_system_clock_1_in_master_qreq_vector = 1;
//nios_system_clock_1_in_reset_n assignment, which is an e_assign
assign nios_system_clock_1_in_reset_n = reset_n;
//nios_system_clock_1_in_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_1_in_firsttransfer = nios_system_clock_1_in_begins_xfer ? nios_system_clock_1_in_unreg_firsttransfer : nios_system_clock_1_in_reg_firsttransfer;
//nios_system_clock_1_in_unreg_firsttransfer first transaction, which is an e_assign
assign nios_system_clock_1_in_unreg_firsttransfer = ~(nios_system_clock_1_in_slavearbiterlockenable & nios_system_clock_1_in_any_continuerequest);
//nios_system_clock_1_in_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_in_reg_firsttransfer <= 1'b1;
else if (nios_system_clock_1_in_begins_xfer)
nios_system_clock_1_in_reg_firsttransfer <= nios_system_clock_1_in_unreg_firsttransfer;
end
//nios_system_clock_1_in_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign nios_system_clock_1_in_beginbursttransfer_internal = nios_system_clock_1_in_begins_xfer;
//nios_system_clock_1_in_read assignment, which is an e_mux
assign nios_system_clock_1_in_read = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read;
//nios_system_clock_1_in_write assignment, which is an e_mux
assign nios_system_clock_1_in_write = ((cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write)) & nios_system_clock_1_in_pretend_byte_enable;
//nios_system_clock_1_in_address mux, which is an e_mux
assign nios_system_clock_1_in_address = {cpu_0_data_master_address_to_slave >> 2,
cpu_0_data_master_dbs_address[1 : 0]};
//slaveid nios_system_clock_1_in_nativeaddress nativeaddress mux, which is an e_mux
assign nios_system_clock_1_in_nativeaddress = cpu_0_data_master_address_to_slave >> 2;
//d1_nios_system_clock_1_in_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_nios_system_clock_1_in_end_xfer <= 1;
else
d1_nios_system_clock_1_in_end_xfer <= nios_system_clock_1_in_end_xfer;
end
//nios_system_clock_1_in_waits_for_read in a cycle, which is an e_mux
assign nios_system_clock_1_in_waits_for_read = nios_system_clock_1_in_in_a_read_cycle & nios_system_clock_1_in_waitrequest_from_sa;
//nios_system_clock_1_in_in_a_read_cycle assignment, which is an e_assign
assign nios_system_clock_1_in_in_a_read_cycle = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = nios_system_clock_1_in_in_a_read_cycle;
//nios_system_clock_1_in_waits_for_write in a cycle, which is an e_mux
assign nios_system_clock_1_in_waits_for_write = nios_system_clock_1_in_in_a_write_cycle & nios_system_clock_1_in_waitrequest_from_sa;
//nios_system_clock_1_in_in_a_write_cycle assignment, which is an e_assign
assign nios_system_clock_1_in_in_a_write_cycle = cpu_0_data_master_granted_nios_system_clock_1_in & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = nios_system_clock_1_in_in_a_write_cycle;
assign wait_for_nios_system_clock_1_in_counter = 0;
//nios_system_clock_1_in_pretend_byte_enable byte enable port mux, which is an e_mux
assign nios_system_clock_1_in_pretend_byte_enable = (cpu_0_data_master_granted_nios_system_clock_1_in)? cpu_0_data_master_byteenable_nios_system_clock_1_in :
-1;
assign {cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1,
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0} = cpu_0_data_master_byteenable;
assign cpu_0_data_master_byteenable_nios_system_clock_1_in = ((cpu_0_data_master_dbs_address[1 : 0] == 0))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_0 :
((cpu_0_data_master_dbs_address[1 : 0] == 1))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_1 :
((cpu_0_data_master_dbs_address[1 : 0] == 2))? cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_2 :
cpu_0_data_master_byteenable_nios_system_clock_1_in_segment_3;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_1/in enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_clock_1_out_arbitrator (
// inputs:
clk,
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer,
nios_system_clock_1_out_address,
nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_read,
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_write,
nios_system_clock_1_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa,
// outputs:
nios_system_clock_1_out_address_to_slave,
nios_system_clock_1_out_readdata,
nios_system_clock_1_out_reset_n,
nios_system_clock_1_out_waitrequest
)
;
output [ 12: 0] nios_system_clock_1_out_address_to_slave;
output [ 7: 0] nios_system_clock_1_out_readdata;
output nios_system_clock_1_out_reset_n;
output nios_system_clock_1_out_waitrequest;
input clk;
input d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
input [ 12: 0] nios_system_clock_1_out_address;
input nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_read;
input nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
input nios_system_clock_1_out_write;
input [ 7: 0] nios_system_clock_1_out_writedata;
input reset_n;
input [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
input video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
reg active_and_waiting_last_time;
reg [ 12: 0] nios_system_clock_1_out_address_last_time;
wire [ 12: 0] nios_system_clock_1_out_address_to_slave;
reg nios_system_clock_1_out_read_last_time;
wire [ 7: 0] nios_system_clock_1_out_readdata;
wire nios_system_clock_1_out_reset_n;
wire nios_system_clock_1_out_run;
wire nios_system_clock_1_out_waitrequest;
reg nios_system_clock_1_out_write_last_time;
reg [ 7: 0] nios_system_clock_1_out_writedata_last_time;
wire r_2;
//r_2 master_run cascaded wait assignment, which is an e_assign
assign r_2 = 1 & (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave) & ((~nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~nios_system_clock_1_out_read | (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read))) & ((~nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave | ~(nios_system_clock_1_out_read | nios_system_clock_1_out_write) | (1 & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa & (nios_system_clock_1_out_read | nios_system_clock_1_out_write))));
//cascaded wait assignment, which is an e_assign
assign nios_system_clock_1_out_run = r_2;
//optimize select-logic by passing only those address bits which matter.
assign nios_system_clock_1_out_address_to_slave = nios_system_clock_1_out_address;
//nios_system_clock_1/out readdata mux, which is an e_mux
assign nios_system_clock_1_out_readdata = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
//actual waitrequest port, which is an e_assign
assign nios_system_clock_1_out_waitrequest = ~nios_system_clock_1_out_run;
//nios_system_clock_1_out_reset_n assignment, which is an e_assign
assign nios_system_clock_1_out_reset_n = reset_n;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//nios_system_clock_1_out_address check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_address_last_time <= 0;
else
nios_system_clock_1_out_address_last_time <= nios_system_clock_1_out_address;
end
//nios_system_clock_1/out waited last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
active_and_waiting_last_time <= 0;
else
active_and_waiting_last_time <= nios_system_clock_1_out_waitrequest & (nios_system_clock_1_out_read | nios_system_clock_1_out_write);
end
//nios_system_clock_1_out_address matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_address != nios_system_clock_1_out_address_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_address did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_read check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_read_last_time <= 0;
else
nios_system_clock_1_out_read_last_time <= nios_system_clock_1_out_read;
end
//nios_system_clock_1_out_read matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_read != nios_system_clock_1_out_read_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_read did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_write check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_write_last_time <= 0;
else
nios_system_clock_1_out_write_last_time <= nios_system_clock_1_out_write;
end
//nios_system_clock_1_out_write matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_write != nios_system_clock_1_out_write_last_time))
begin
$write("%0d ns: nios_system_clock_1_out_write did not heed wait!!!", $time);
$stop;
end
end
//nios_system_clock_1_out_writedata check against wait, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_writedata_last_time <= 0;
else
nios_system_clock_1_out_writedata_last_time <= nios_system_clock_1_out_writedata;
end
//nios_system_clock_1_out_writedata matches last port_name, which is an e_process
always @(posedge clk)
begin
if (active_and_waiting_last_time & (nios_system_clock_1_out_writedata != nios_system_clock_1_out_writedata_last_time) & nios_system_clock_1_out_write)
begin
$write("%0d ns: nios_system_clock_1_out_writedata did not heed wait!!!", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module onchip_memory2_0_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
onchip_memory2_0_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_onchip_memory2_0_s1,
cpu_0_data_master_qualified_request_onchip_memory2_0_s1,
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_data_master_requests_onchip_memory2_0_s1,
cpu_0_instruction_master_granted_onchip_memory2_0_s1,
cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1,
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1,
cpu_0_instruction_master_requests_onchip_memory2_0_s1,
d1_onchip_memory2_0_s1_end_xfer,
onchip_memory2_0_s1_address,
onchip_memory2_0_s1_byteenable,
onchip_memory2_0_s1_chipselect,
onchip_memory2_0_s1_clken,
onchip_memory2_0_s1_readdata_from_sa,
onchip_memory2_0_s1_reset,
onchip_memory2_0_s1_write,
onchip_memory2_0_s1_writedata,
registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1
)
;
output cpu_0_data_master_granted_onchip_memory2_0_s1;
output cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
output cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
output cpu_0_data_master_requests_onchip_memory2_0_s1;
output cpu_0_instruction_master_granted_onchip_memory2_0_s1;
output cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
output cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
output cpu_0_instruction_master_requests_onchip_memory2_0_s1;
output d1_onchip_memory2_0_s1_end_xfer;
output [ 11: 0] onchip_memory2_0_s1_address;
output [ 3: 0] onchip_memory2_0_s1_byteenable;
output onchip_memory2_0_s1_chipselect;
output onchip_memory2_0_s1_clken;
output [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
output onchip_memory2_0_s1_reset;
output onchip_memory2_0_s1_write;
output [ 31: 0] onchip_memory2_0_s1_writedata;
output registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input [ 31: 0] onchip_memory2_0_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_onchip_memory2_0_s1;
wire cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
reg cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
wire cpu_0_data_master_requests_onchip_memory2_0_s1;
wire cpu_0_data_master_saved_grant_onchip_memory2_0_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_onchip_memory2_0_s1;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
reg cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
wire cpu_0_instruction_master_requests_onchip_memory2_0_s1;
wire cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1;
reg d1_onchip_memory2_0_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_onchip_memory2_0_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1;
wire [ 11: 0] onchip_memory2_0_s1_address;
wire onchip_memory2_0_s1_allgrants;
wire onchip_memory2_0_s1_allow_new_arb_cycle;
wire onchip_memory2_0_s1_any_bursting_master_saved_grant;
wire onchip_memory2_0_s1_any_continuerequest;
reg [ 1: 0] onchip_memory2_0_s1_arb_addend;
wire onchip_memory2_0_s1_arb_counter_enable;
reg [ 2: 0] onchip_memory2_0_s1_arb_share_counter;
wire [ 2: 0] onchip_memory2_0_s1_arb_share_counter_next_value;
wire [ 2: 0] onchip_memory2_0_s1_arb_share_set_values;
wire [ 1: 0] onchip_memory2_0_s1_arb_winner;
wire onchip_memory2_0_s1_arbitration_holdoff_internal;
wire onchip_memory2_0_s1_beginbursttransfer_internal;
wire onchip_memory2_0_s1_begins_xfer;
wire [ 3: 0] onchip_memory2_0_s1_byteenable;
wire onchip_memory2_0_s1_chipselect;
wire [ 3: 0] onchip_memory2_0_s1_chosen_master_double_vector;
wire [ 1: 0] onchip_memory2_0_s1_chosen_master_rot_left;
wire onchip_memory2_0_s1_clken;
wire onchip_memory2_0_s1_end_xfer;
wire onchip_memory2_0_s1_firsttransfer;
wire [ 1: 0] onchip_memory2_0_s1_grant_vector;
wire onchip_memory2_0_s1_in_a_read_cycle;
wire onchip_memory2_0_s1_in_a_write_cycle;
wire [ 1: 0] onchip_memory2_0_s1_master_qreq_vector;
wire onchip_memory2_0_s1_non_bursting_master_requests;
wire [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
reg onchip_memory2_0_s1_reg_firsttransfer;
wire onchip_memory2_0_s1_reset;
reg [ 1: 0] onchip_memory2_0_s1_saved_chosen_master_vector;
reg onchip_memory2_0_s1_slavearbiterlockenable;
wire onchip_memory2_0_s1_slavearbiterlockenable2;
wire onchip_memory2_0_s1_unreg_firsttransfer;
wire onchip_memory2_0_s1_waits_for_read;
wire onchip_memory2_0_s1_waits_for_write;
wire onchip_memory2_0_s1_write;
wire [ 31: 0] onchip_memory2_0_s1_writedata;
wire p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire [ 27: 0] shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master;
wire wait_for_onchip_memory2_0_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~onchip_memory2_0_s1_end_xfer;
end
assign onchip_memory2_0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_onchip_memory2_0_s1 | cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1));
//assign onchip_memory2_0_s1_readdata_from_sa = onchip_memory2_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign onchip_memory2_0_s1_readdata_from_sa = onchip_memory2_0_s1_readdata;
assign cpu_0_data_master_requests_onchip_memory2_0_s1 = ({cpu_0_data_master_address_to_slave[27 : 14] , 14'b0} == 28'h10000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//registered rdv signal_name registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 assignment, which is an e_assign
assign registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in;
//onchip_memory2_0_s1_arb_share_counter set values, which is an e_mux
assign onchip_memory2_0_s1_arb_share_set_values = 1;
//onchip_memory2_0_s1_non_bursting_master_requests mux, which is an e_mux
assign onchip_memory2_0_s1_non_bursting_master_requests = cpu_0_data_master_requests_onchip_memory2_0_s1 |
cpu_0_instruction_master_requests_onchip_memory2_0_s1 |
cpu_0_data_master_requests_onchip_memory2_0_s1 |
cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign onchip_memory2_0_s1_any_bursting_master_saved_grant = 0;
//onchip_memory2_0_s1_arb_share_counter_next_value assignment, which is an e_assign
assign onchip_memory2_0_s1_arb_share_counter_next_value = onchip_memory2_0_s1_firsttransfer ? (onchip_memory2_0_s1_arb_share_set_values - 1) : |onchip_memory2_0_s1_arb_share_counter ? (onchip_memory2_0_s1_arb_share_counter - 1) : 0;
//onchip_memory2_0_s1_allgrants all slave grants, which is an e_mux
assign onchip_memory2_0_s1_allgrants = (|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector) |
(|onchip_memory2_0_s1_grant_vector);
//onchip_memory2_0_s1_end_xfer assignment, which is an e_assign
assign onchip_memory2_0_s1_end_xfer = ~(onchip_memory2_0_s1_waits_for_read | onchip_memory2_0_s1_waits_for_write);
//end_xfer_arb_share_counter_term_onchip_memory2_0_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_onchip_memory2_0_s1 = onchip_memory2_0_s1_end_xfer & (~onchip_memory2_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//onchip_memory2_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign onchip_memory2_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & onchip_memory2_0_s1_allgrants) | (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & ~onchip_memory2_0_s1_non_bursting_master_requests);
//onchip_memory2_0_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_arb_share_counter <= 0;
else if (onchip_memory2_0_s1_arb_counter_enable)
onchip_memory2_0_s1_arb_share_counter <= onchip_memory2_0_s1_arb_share_counter_next_value;
end
//onchip_memory2_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_slavearbiterlockenable <= 0;
else if ((|onchip_memory2_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_onchip_memory2_0_s1) | (end_xfer_arb_share_counter_term_onchip_memory2_0_s1 & ~onchip_memory2_0_s1_non_bursting_master_requests))
onchip_memory2_0_s1_slavearbiterlockenable <= |onchip_memory2_0_s1_arb_share_counter_next_value;
end
//cpu_0/data_master onchip_memory2_0/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = onchip_memory2_0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//onchip_memory2_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign onchip_memory2_0_s1_slavearbiterlockenable2 = |onchip_memory2_0_s1_arb_share_counter_next_value;
//cpu_0/data_master onchip_memory2_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = onchip_memory2_0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master onchip_memory2_0/s1 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = onchip_memory2_0_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master onchip_memory2_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = onchip_memory2_0_s1_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted onchip_memory2_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 <= cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 ? 1 : (onchip_memory2_0_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_onchip_memory2_0_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_onchip_memory2_0_s1 & cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign onchip_memory2_0_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_onchip_memory2_0_s1 = cpu_0_data_master_requests_onchip_memory2_0_s1 & ~((cpu_0_data_master_read & ((|cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_read & ~onchip_memory2_0_s1_waits_for_read & ~(|cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register);
//shift register p1 cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register = {cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register, cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register_in};
//cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register <= 0;
else
cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register <= p1_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
end
//local readdatavalid cpu_0_data_master_read_data_valid_onchip_memory2_0_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_data_master_read_data_valid_onchip_memory2_0_s1_shift_register;
//onchip_memory2_0_s1_writedata mux, which is an e_mux
assign onchip_memory2_0_s1_writedata = cpu_0_data_master_writedata;
//mux onchip_memory2_0_s1_clken, which is an e_mux
assign onchip_memory2_0_s1_clken = 1'b1;
assign cpu_0_instruction_master_requests_onchip_memory2_0_s1 = (({cpu_0_instruction_master_address_to_slave[27 : 14] , 14'b0} == 28'h10000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted onchip_memory2_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 <= cpu_0_data_master_saved_grant_onchip_memory2_0_s1 ? 1 : (onchip_memory2_0_s1_arbitration_holdoff_internal | ~cpu_0_data_master_requests_onchip_memory2_0_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_onchip_memory2_0_s1 & cpu_0_data_master_requests_onchip_memory2_0_s1;
assign cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 = cpu_0_instruction_master_requests_onchip_memory2_0_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register))) | cpu_0_data_master_arbiterlock);
//cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in mux for readlatency shift register, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in = cpu_0_instruction_master_granted_onchip_memory2_0_s1 & cpu_0_instruction_master_read & ~onchip_memory2_0_s1_waits_for_read & ~(|cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register);
//shift register p1 cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register = {cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register, cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register_in};
//cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register <= 0;
else
cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register <= p1_cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
end
//local readdatavalid cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 = cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1_shift_register;
//allow new arb cycle for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
//cpu_0/instruction_master grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_instruction_master_granted_onchip_memory2_0_s1 = onchip_memory2_0_s1_grant_vector[0];
//cpu_0/instruction_master saved-grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 = onchip_memory2_0_s1_arb_winner[0] && cpu_0_instruction_master_requests_onchip_memory2_0_s1;
//cpu_0/data_master assignment into master qualified-requests vector for onchip_memory2_0/s1, which is an e_assign
assign onchip_memory2_0_s1_master_qreq_vector[1] = cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
//cpu_0/data_master grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_data_master_granted_onchip_memory2_0_s1 = onchip_memory2_0_s1_grant_vector[1];
//cpu_0/data_master saved-grant onchip_memory2_0/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_onchip_memory2_0_s1 = onchip_memory2_0_s1_arb_winner[1] && cpu_0_data_master_requests_onchip_memory2_0_s1;
//onchip_memory2_0/s1 chosen-master double-vector, which is an e_assign
assign onchip_memory2_0_s1_chosen_master_double_vector = {onchip_memory2_0_s1_master_qreq_vector, onchip_memory2_0_s1_master_qreq_vector} & ({~onchip_memory2_0_s1_master_qreq_vector, ~onchip_memory2_0_s1_master_qreq_vector} + onchip_memory2_0_s1_arb_addend);
//stable onehot encoding of arb winner
assign onchip_memory2_0_s1_arb_winner = (onchip_memory2_0_s1_allow_new_arb_cycle & | onchip_memory2_0_s1_grant_vector) ? onchip_memory2_0_s1_grant_vector : onchip_memory2_0_s1_saved_chosen_master_vector;
//saved onchip_memory2_0_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_saved_chosen_master_vector <= 0;
else if (onchip_memory2_0_s1_allow_new_arb_cycle)
onchip_memory2_0_s1_saved_chosen_master_vector <= |onchip_memory2_0_s1_grant_vector ? onchip_memory2_0_s1_grant_vector : onchip_memory2_0_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign onchip_memory2_0_s1_grant_vector = {(onchip_memory2_0_s1_chosen_master_double_vector[1] | onchip_memory2_0_s1_chosen_master_double_vector[3]),
(onchip_memory2_0_s1_chosen_master_double_vector[0] | onchip_memory2_0_s1_chosen_master_double_vector[2])};
//onchip_memory2_0/s1 chosen master rotated left, which is an e_assign
assign onchip_memory2_0_s1_chosen_master_rot_left = (onchip_memory2_0_s1_arb_winner << 1) ? (onchip_memory2_0_s1_arb_winner << 1) : 1;
//onchip_memory2_0/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_arb_addend <= 1;
else if (|onchip_memory2_0_s1_grant_vector)
onchip_memory2_0_s1_arb_addend <= onchip_memory2_0_s1_end_xfer? onchip_memory2_0_s1_chosen_master_rot_left : onchip_memory2_0_s1_grant_vector;
end
//~onchip_memory2_0_s1_reset assignment, which is an e_assign
assign onchip_memory2_0_s1_reset = ~reset_n;
assign onchip_memory2_0_s1_chipselect = cpu_0_data_master_granted_onchip_memory2_0_s1 | cpu_0_instruction_master_granted_onchip_memory2_0_s1;
//onchip_memory2_0_s1_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_0_s1_firsttransfer = onchip_memory2_0_s1_begins_xfer ? onchip_memory2_0_s1_unreg_firsttransfer : onchip_memory2_0_s1_reg_firsttransfer;
//onchip_memory2_0_s1_unreg_firsttransfer first transaction, which is an e_assign
assign onchip_memory2_0_s1_unreg_firsttransfer = ~(onchip_memory2_0_s1_slavearbiterlockenable & onchip_memory2_0_s1_any_continuerequest);
//onchip_memory2_0_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
onchip_memory2_0_s1_reg_firsttransfer <= 1'b1;
else if (onchip_memory2_0_s1_begins_xfer)
onchip_memory2_0_s1_reg_firsttransfer <= onchip_memory2_0_s1_unreg_firsttransfer;
end
//onchip_memory2_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign onchip_memory2_0_s1_beginbursttransfer_internal = onchip_memory2_0_s1_begins_xfer;
//onchip_memory2_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign onchip_memory2_0_s1_arbitration_holdoff_internal = onchip_memory2_0_s1_begins_xfer & onchip_memory2_0_s1_firsttransfer;
//onchip_memory2_0_s1_write assignment, which is an e_mux
assign onchip_memory2_0_s1_write = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_write;
assign shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//onchip_memory2_0_s1_address mux, which is an e_mux
assign onchip_memory2_0_s1_address = (cpu_0_data_master_granted_onchip_memory2_0_s1)? (shifted_address_to_onchip_memory2_0_s1_from_cpu_0_data_master >> 2) :
(shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_onchip_memory2_0_s1_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_onchip_memory2_0_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_onchip_memory2_0_s1_end_xfer <= 1;
else
d1_onchip_memory2_0_s1_end_xfer <= onchip_memory2_0_s1_end_xfer;
end
//onchip_memory2_0_s1_waits_for_read in a cycle, which is an e_mux
assign onchip_memory2_0_s1_waits_for_read = onchip_memory2_0_s1_in_a_read_cycle & 0;
//onchip_memory2_0_s1_in_a_read_cycle assignment, which is an e_assign
assign onchip_memory2_0_s1_in_a_read_cycle = (cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_onchip_memory2_0_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = onchip_memory2_0_s1_in_a_read_cycle;
//onchip_memory2_0_s1_waits_for_write in a cycle, which is an e_mux
assign onchip_memory2_0_s1_waits_for_write = onchip_memory2_0_s1_in_a_write_cycle & 0;
//onchip_memory2_0_s1_in_a_write_cycle assignment, which is an e_assign
assign onchip_memory2_0_s1_in_a_write_cycle = cpu_0_data_master_granted_onchip_memory2_0_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = onchip_memory2_0_s1_in_a_write_cycle;
assign wait_for_onchip_memory2_0_s1_counter = 0;
//onchip_memory2_0_s1_byteenable byte enable port mux, which is an e_mux
assign onchip_memory2_0_s1_byteenable = (cpu_0_data_master_granted_onchip_memory2_0_s1)? cpu_0_data_master_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//onchip_memory2_0/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_onchip_memory2_0_s1 + cpu_0_instruction_master_granted_onchip_memory2_0_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_onchip_memory2_0_s1 + cpu_0_instruction_master_saved_grant_onchip_memory2_0_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module output1_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
output1_s1_readdata,
reset_n,
// outputs:
cpu_0_data_master_granted_output1_s1,
cpu_0_data_master_qualified_request_output1_s1,
cpu_0_data_master_read_data_valid_output1_s1,
cpu_0_data_master_requests_output1_s1,
d1_output1_s1_end_xfer,
output1_s1_address,
output1_s1_chipselect,
output1_s1_readdata_from_sa,
output1_s1_reset_n,
output1_s1_write_n,
output1_s1_writedata
)
;
output cpu_0_data_master_granted_output1_s1;
output cpu_0_data_master_qualified_request_output1_s1;
output cpu_0_data_master_read_data_valid_output1_s1;
output cpu_0_data_master_requests_output1_s1;
output d1_output1_s1_end_xfer;
output [ 1: 0] output1_s1_address;
output output1_s1_chipselect;
output [ 31: 0] output1_s1_readdata_from_sa;
output output1_s1_reset_n;
output output1_s1_write_n;
output [ 31: 0] output1_s1_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 31: 0] output1_s1_readdata;
input reset_n;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_output1_s1;
wire cpu_0_data_master_qualified_request_output1_s1;
wire cpu_0_data_master_read_data_valid_output1_s1;
wire cpu_0_data_master_requests_output1_s1;
wire cpu_0_data_master_saved_grant_output1_s1;
reg d1_output1_s1_end_xfer;
reg d1_reasons_to_wait;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_output1_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 1: 0] output1_s1_address;
wire output1_s1_allgrants;
wire output1_s1_allow_new_arb_cycle;
wire output1_s1_any_bursting_master_saved_grant;
wire output1_s1_any_continuerequest;
wire output1_s1_arb_counter_enable;
reg [ 2: 0] output1_s1_arb_share_counter;
wire [ 2: 0] output1_s1_arb_share_counter_next_value;
wire [ 2: 0] output1_s1_arb_share_set_values;
wire output1_s1_beginbursttransfer_internal;
wire output1_s1_begins_xfer;
wire output1_s1_chipselect;
wire output1_s1_end_xfer;
wire output1_s1_firsttransfer;
wire output1_s1_grant_vector;
wire output1_s1_in_a_read_cycle;
wire output1_s1_in_a_write_cycle;
wire output1_s1_master_qreq_vector;
wire output1_s1_non_bursting_master_requests;
wire [ 31: 0] output1_s1_readdata_from_sa;
reg output1_s1_reg_firsttransfer;
wire output1_s1_reset_n;
reg output1_s1_slavearbiterlockenable;
wire output1_s1_slavearbiterlockenable2;
wire output1_s1_unreg_firsttransfer;
wire output1_s1_waits_for_read;
wire output1_s1_waits_for_write;
wire output1_s1_write_n;
wire [ 31: 0] output1_s1_writedata;
wire [ 27: 0] shifted_address_to_output1_s1_from_cpu_0_data_master;
wire wait_for_output1_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~output1_s1_end_xfer;
end
assign output1_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_output1_s1));
//assign output1_s1_readdata_from_sa = output1_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign output1_s1_readdata_from_sa = output1_s1_readdata;
assign cpu_0_data_master_requests_output1_s1 = ({cpu_0_data_master_address_to_slave[27 : 4] , 4'b0} == 28'h0) & (cpu_0_data_master_read | cpu_0_data_master_write);
//output1_s1_arb_share_counter set values, which is an e_mux
assign output1_s1_arb_share_set_values = 1;
//output1_s1_non_bursting_master_requests mux, which is an e_mux
assign output1_s1_non_bursting_master_requests = cpu_0_data_master_requests_output1_s1;
//output1_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign output1_s1_any_bursting_master_saved_grant = 0;
//output1_s1_arb_share_counter_next_value assignment, which is an e_assign
assign output1_s1_arb_share_counter_next_value = output1_s1_firsttransfer ? (output1_s1_arb_share_set_values - 1) : |output1_s1_arb_share_counter ? (output1_s1_arb_share_counter - 1) : 0;
//output1_s1_allgrants all slave grants, which is an e_mux
assign output1_s1_allgrants = |output1_s1_grant_vector;
//output1_s1_end_xfer assignment, which is an e_assign
assign output1_s1_end_xfer = ~(output1_s1_waits_for_read | output1_s1_waits_for_write);
//end_xfer_arb_share_counter_term_output1_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_output1_s1 = output1_s1_end_xfer & (~output1_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//output1_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign output1_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_output1_s1 & output1_s1_allgrants) | (end_xfer_arb_share_counter_term_output1_s1 & ~output1_s1_non_bursting_master_requests);
//output1_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_arb_share_counter <= 0;
else if (output1_s1_arb_counter_enable)
output1_s1_arb_share_counter <= output1_s1_arb_share_counter_next_value;
end
//output1_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_slavearbiterlockenable <= 0;
else if ((|output1_s1_master_qreq_vector & end_xfer_arb_share_counter_term_output1_s1) | (end_xfer_arb_share_counter_term_output1_s1 & ~output1_s1_non_bursting_master_requests))
output1_s1_slavearbiterlockenable <= |output1_s1_arb_share_counter_next_value;
end
//cpu_0/data_master output1/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = output1_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//output1_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign output1_s1_slavearbiterlockenable2 = |output1_s1_arb_share_counter_next_value;
//cpu_0/data_master output1/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = output1_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//output1_s1_any_continuerequest at least one master continues requesting, which is an e_assign
assign output1_s1_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_output1_s1 = cpu_0_data_master_requests_output1_s1 & ~(((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write));
//output1_s1_writedata mux, which is an e_mux
assign output1_s1_writedata = cpu_0_data_master_writedata;
//master is always granted when requested
assign cpu_0_data_master_granted_output1_s1 = cpu_0_data_master_qualified_request_output1_s1;
//cpu_0/data_master saved-grant output1/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_output1_s1 = cpu_0_data_master_requests_output1_s1;
//allow new arb cycle for output1/s1, which is an e_assign
assign output1_s1_allow_new_arb_cycle = 1;
//placeholder chosen master
assign output1_s1_grant_vector = 1;
//placeholder vector of master qualified-requests
assign output1_s1_master_qreq_vector = 1;
//output1_s1_reset_n assignment, which is an e_assign
assign output1_s1_reset_n = reset_n;
assign output1_s1_chipselect = cpu_0_data_master_granted_output1_s1;
//output1_s1_firsttransfer first transaction, which is an e_assign
assign output1_s1_firsttransfer = output1_s1_begins_xfer ? output1_s1_unreg_firsttransfer : output1_s1_reg_firsttransfer;
//output1_s1_unreg_firsttransfer first transaction, which is an e_assign
assign output1_s1_unreg_firsttransfer = ~(output1_s1_slavearbiterlockenable & output1_s1_any_continuerequest);
//output1_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
output1_s1_reg_firsttransfer <= 1'b1;
else if (output1_s1_begins_xfer)
output1_s1_reg_firsttransfer <= output1_s1_unreg_firsttransfer;
end
//output1_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign output1_s1_beginbursttransfer_internal = output1_s1_begins_xfer;
//~output1_s1_write_n assignment, which is an e_mux
assign output1_s1_write_n = ~(cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_write);
assign shifted_address_to_output1_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//output1_s1_address mux, which is an e_mux
assign output1_s1_address = shifted_address_to_output1_s1_from_cpu_0_data_master >> 2;
//d1_output1_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_output1_s1_end_xfer <= 1;
else
d1_output1_s1_end_xfer <= output1_s1_end_xfer;
end
//output1_s1_waits_for_read in a cycle, which is an e_mux
assign output1_s1_waits_for_read = output1_s1_in_a_read_cycle & output1_s1_begins_xfer;
//output1_s1_in_a_read_cycle assignment, which is an e_assign
assign output1_s1_in_a_read_cycle = cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = output1_s1_in_a_read_cycle;
//output1_s1_waits_for_write in a cycle, which is an e_mux
assign output1_s1_waits_for_write = output1_s1_in_a_write_cycle & 0;
//output1_s1_in_a_write_cycle assignment, which is an e_assign
assign output1_s1_in_a_write_cycle = cpu_0_data_master_granted_output1_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = output1_s1_in_a_write_cycle;
assign wait_for_output1_s1_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//output1/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_2;
reg full_3;
reg full_4;
reg full_5;
reg full_6;
wire full_7;
reg [ 3: 0] how_many_ones;
wire [ 3: 0] one_count_minus_one;
wire [ 3: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p1_full_1;
wire p1_stage_1;
wire p2_full_2;
wire p2_stage_2;
wire p3_full_3;
wire p3_stage_3;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
reg stage_0;
reg stage_1;
reg stage_2;
reg stage_3;
reg stage_4;
reg stage_5;
reg stage_6;
wire [ 3: 0] updated_one_count;
assign data_out = stage_0;
assign full = full_6;
assign empty = !full_0;
assign full_7 = 0;
//data_6, which is an e_mux
assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
data_in;
//data_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_6 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_6))
if (sync_reset & full_6 & !((full_7 == 0) & read & write))
stage_6 <= 0;
else
stage_6 <= p6_stage_6;
end
//control_6, which is an e_mux
assign p6_full_6 = ((read & !write) == 0)? full_5 :
0;
//control_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_6 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_6 <= 0;
else
full_6 <= p6_full_6;
end
//data_5, which is an e_mux
assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
stage_6;
//data_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_5 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_5))
if (sync_reset & full_5 & !((full_6 == 0) & read & write))
stage_5 <= 0;
else
stage_5 <= p5_stage_5;
end
//control_5, which is an e_mux
assign p5_full_5 = ((read & !write) == 0)? full_4 :
full_6;
//control_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_5 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_5 <= 0;
else
full_5 <= p5_full_5;
end
//data_4, which is an e_mux
assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
stage_5;
//data_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_4 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_4))
if (sync_reset & full_4 & !((full_5 == 0) & read & write))
stage_4 <= 0;
else
stage_4 <= p4_stage_4;
end
//control_4, which is an e_mux
assign p4_full_4 = ((read & !write) == 0)? full_3 :
full_5;
//control_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_4 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_4 <= 0;
else
full_4 <= p4_full_4;
end
//data_3, which is an e_mux
assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
stage_4;
//data_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_3 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_3))
if (sync_reset & full_3 & !((full_4 == 0) & read & write))
stage_3 <= 0;
else
stage_3 <= p3_stage_3;
end
//control_3, which is an e_mux
assign p3_full_3 = ((read & !write) == 0)? full_2 :
full_4;
//control_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_3 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_3 <= 0;
else
full_3 <= p3_full_3;
end
//data_2, which is an e_mux
assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
stage_3;
//data_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_2 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_2))
if (sync_reset & full_2 & !((full_3 == 0) & read & write))
stage_2 <= 0;
else
stage_2 <= p2_stage_2;
end
//control_2, which is an e_mux
assign p2_full_2 = ((read & !write) == 0)? full_1 :
full_3;
//control_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_2 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_2 <= 0;
else
full_2 <= p2_full_2;
end
//data_1, which is an e_mux
assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
stage_2;
//data_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_1 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_1))
if (sync_reset & full_1 & !((full_2 == 0) & read & write))
stage_1 <= 0;
else
stage_1 <= p1_stage_1;
end
//control_1, which is an e_mux
assign p1_full_1 = ((read & !write) == 0)? full_0 :
full_2;
//control_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_1 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_1 <= 0;
else
full_1 <= p1_full_1;
end
//data_0, which is an e_mux
assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
stage_1;
//data_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_0 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_0))
if (sync_reset & full_0 & !((full_1 == 0) & read & write))
stage_0 <= 0;
else
stage_0 <= p0_stage_0;
end
//control_0, which is an e_mux
assign p0_full_0 = ((read & !write) == 0)? 1 :
full_1;
//control_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_0 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo & ~write)
full_0 <= 0;
else
full_0 <= p0_full_0;
end
assign one_count_plus_one = how_many_ones + 1;
assign one_count_minus_one = how_many_ones - 1;
//updated_one_count, which is an e_mux
assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
((((clear_fifo | sync_reset) & write)))? |data_in :
((read & (|data_in) & write & (|stage_0)))? how_many_ones :
((write & (|data_in)))? one_count_plus_one :
((read & (|stage_0)))? one_count_minus_one :
how_many_ones;
//counts how many ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
how_many_ones <= 0;
else if (clear_fifo | sync_reset | read | write)
how_many_ones <= updated_one_count;
end
//this fifo contains ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_contains_ones_n <= 1;
else if (clear_fifo | sync_reset | read | write)
fifo_contains_ones_n <= ~(|updated_one_count);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module (
// inputs:
clear_fifo,
clk,
data_in,
read,
reset_n,
sync_reset,
write,
// outputs:
data_out,
empty,
fifo_contains_ones_n,
full
)
;
output data_out;
output empty;
output fifo_contains_ones_n;
output full;
input clear_fifo;
input clk;
input data_in;
input read;
input reset_n;
input sync_reset;
input write;
wire data_out;
wire empty;
reg fifo_contains_ones_n;
wire full;
reg full_0;
reg full_1;
reg full_2;
reg full_3;
reg full_4;
reg full_5;
reg full_6;
wire full_7;
reg [ 3: 0] how_many_ones;
wire [ 3: 0] one_count_minus_one;
wire [ 3: 0] one_count_plus_one;
wire p0_full_0;
wire p0_stage_0;
wire p1_full_1;
wire p1_stage_1;
wire p2_full_2;
wire p2_stage_2;
wire p3_full_3;
wire p3_stage_3;
wire p4_full_4;
wire p4_stage_4;
wire p5_full_5;
wire p5_stage_5;
wire p6_full_6;
wire p6_stage_6;
reg stage_0;
reg stage_1;
reg stage_2;
reg stage_3;
reg stage_4;
reg stage_5;
reg stage_6;
wire [ 3: 0] updated_one_count;
assign data_out = stage_0;
assign full = full_6;
assign empty = !full_0;
assign full_7 = 0;
//data_6, which is an e_mux
assign p6_stage_6 = ((full_7 & ~clear_fifo) == 0)? data_in :
data_in;
//data_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_6 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_6))
if (sync_reset & full_6 & !((full_7 == 0) & read & write))
stage_6 <= 0;
else
stage_6 <= p6_stage_6;
end
//control_6, which is an e_mux
assign p6_full_6 = ((read & !write) == 0)? full_5 :
0;
//control_reg_6, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_6 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_6 <= 0;
else
full_6 <= p6_full_6;
end
//data_5, which is an e_mux
assign p5_stage_5 = ((full_6 & ~clear_fifo) == 0)? data_in :
stage_6;
//data_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_5 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_5))
if (sync_reset & full_5 & !((full_6 == 0) & read & write))
stage_5 <= 0;
else
stage_5 <= p5_stage_5;
end
//control_5, which is an e_mux
assign p5_full_5 = ((read & !write) == 0)? full_4 :
full_6;
//control_reg_5, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_5 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_5 <= 0;
else
full_5 <= p5_full_5;
end
//data_4, which is an e_mux
assign p4_stage_4 = ((full_5 & ~clear_fifo) == 0)? data_in :
stage_5;
//data_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_4 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_4))
if (sync_reset & full_4 & !((full_5 == 0) & read & write))
stage_4 <= 0;
else
stage_4 <= p4_stage_4;
end
//control_4, which is an e_mux
assign p4_full_4 = ((read & !write) == 0)? full_3 :
full_5;
//control_reg_4, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_4 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_4 <= 0;
else
full_4 <= p4_full_4;
end
//data_3, which is an e_mux
assign p3_stage_3 = ((full_4 & ~clear_fifo) == 0)? data_in :
stage_4;
//data_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_3 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_3))
if (sync_reset & full_3 & !((full_4 == 0) & read & write))
stage_3 <= 0;
else
stage_3 <= p3_stage_3;
end
//control_3, which is an e_mux
assign p3_full_3 = ((read & !write) == 0)? full_2 :
full_4;
//control_reg_3, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_3 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_3 <= 0;
else
full_3 <= p3_full_3;
end
//data_2, which is an e_mux
assign p2_stage_2 = ((full_3 & ~clear_fifo) == 0)? data_in :
stage_3;
//data_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_2 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_2))
if (sync_reset & full_2 & !((full_3 == 0) & read & write))
stage_2 <= 0;
else
stage_2 <= p2_stage_2;
end
//control_2, which is an e_mux
assign p2_full_2 = ((read & !write) == 0)? full_1 :
full_3;
//control_reg_2, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_2 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_2 <= 0;
else
full_2 <= p2_full_2;
end
//data_1, which is an e_mux
assign p1_stage_1 = ((full_2 & ~clear_fifo) == 0)? data_in :
stage_2;
//data_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_1 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_1))
if (sync_reset & full_1 & !((full_2 == 0) & read & write))
stage_1 <= 0;
else
stage_1 <= p1_stage_1;
end
//control_1, which is an e_mux
assign p1_full_1 = ((read & !write) == 0)? full_0 :
full_2;
//control_reg_1, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_1 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo)
full_1 <= 0;
else
full_1 <= p1_full_1;
end
//data_0, which is an e_mux
assign p0_stage_0 = ((full_1 & ~clear_fifo) == 0)? data_in :
stage_1;
//data_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
stage_0 <= 0;
else if (clear_fifo | sync_reset | read | (write & !full_0))
if (sync_reset & full_0 & !((full_1 == 0) & read & write))
stage_0 <= 0;
else
stage_0 <= p0_stage_0;
end
//control_0, which is an e_mux
assign p0_full_0 = ((read & !write) == 0)? 1 :
full_1;
//control_reg_0, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
full_0 <= 0;
else if (clear_fifo | (read ^ write) | (write & !full_0))
if (clear_fifo & ~write)
full_0 <= 0;
else
full_0 <= p0_full_0;
end
assign one_count_plus_one = how_many_ones + 1;
assign one_count_minus_one = how_many_ones - 1;
//updated_one_count, which is an e_mux
assign updated_one_count = ((((clear_fifo | sync_reset) & !write)))? 0 :
((((clear_fifo | sync_reset) & write)))? |data_in :
((read & (|data_in) & write & (|stage_0)))? how_many_ones :
((write & (|data_in)))? one_count_plus_one :
((read & (|stage_0)))? one_count_minus_one :
how_many_ones;
//counts how many ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
how_many_ones <= 0;
else if (clear_fifo | sync_reset | read | write)
how_many_ones <= updated_one_count;
end
//this fifo contains ones in the data pipeline, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
fifo_contains_ones_n <= 1;
else if (clear_fifo | sync_reset | read | write)
fifo_contains_ones_n <= ~(|updated_one_count);
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sdram_0_s1_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_byteenable,
cpu_0_data_master_read,
cpu_0_data_master_waitrequest,
cpu_0_data_master_write,
cpu_0_data_master_writedata,
cpu_0_instruction_master_address_to_slave,
cpu_0_instruction_master_read,
reset_n,
sdram_0_s1_readdata,
sdram_0_s1_readdatavalid,
sdram_0_s1_waitrequest,
// outputs:
cpu_0_data_master_granted_sdram_0_s1,
cpu_0_data_master_qualified_request_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1,
cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_data_master_requests_sdram_0_s1,
cpu_0_instruction_master_granted_sdram_0_s1,
cpu_0_instruction_master_qualified_request_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1,
cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register,
cpu_0_instruction_master_requests_sdram_0_s1,
d1_sdram_0_s1_end_xfer,
sdram_0_s1_address,
sdram_0_s1_byteenable_n,
sdram_0_s1_chipselect,
sdram_0_s1_read_n,
sdram_0_s1_readdata_from_sa,
sdram_0_s1_reset_n,
sdram_0_s1_waitrequest_from_sa,
sdram_0_s1_write_n,
sdram_0_s1_writedata
)
;
output cpu_0_data_master_granted_sdram_0_s1;
output cpu_0_data_master_qualified_request_sdram_0_s1;
output cpu_0_data_master_read_data_valid_sdram_0_s1;
output cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
output cpu_0_data_master_requests_sdram_0_s1;
output cpu_0_instruction_master_granted_sdram_0_s1;
output cpu_0_instruction_master_qualified_request_sdram_0_s1;
output cpu_0_instruction_master_read_data_valid_sdram_0_s1;
output cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
output cpu_0_instruction_master_requests_sdram_0_s1;
output d1_sdram_0_s1_end_xfer;
output [ 24: 0] sdram_0_s1_address;
output [ 3: 0] sdram_0_s1_byteenable_n;
output sdram_0_s1_chipselect;
output sdram_0_s1_read_n;
output [ 31: 0] sdram_0_s1_readdata_from_sa;
output sdram_0_s1_reset_n;
output sdram_0_s1_waitrequest_from_sa;
output sdram_0_s1_write_n;
output [ 31: 0] sdram_0_s1_writedata;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input [ 3: 0] cpu_0_data_master_byteenable;
input cpu_0_data_master_read;
input cpu_0_data_master_waitrequest;
input cpu_0_data_master_write;
input [ 31: 0] cpu_0_data_master_writedata;
input [ 27: 0] cpu_0_instruction_master_address_to_slave;
input cpu_0_instruction_master_read;
input reset_n;
input [ 31: 0] sdram_0_s1_readdata;
input sdram_0_s1_readdatavalid;
input sdram_0_s1_waitrequest;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sdram_0_s1;
wire cpu_0_data_master_qualified_request_sdram_0_s1;
wire cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
wire cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_data_master_requests_sdram_0_s1;
wire cpu_0_data_master_saved_grant_sdram_0_s1;
wire cpu_0_instruction_master_arbiterlock;
wire cpu_0_instruction_master_arbiterlock2;
wire cpu_0_instruction_master_continuerequest;
wire cpu_0_instruction_master_granted_sdram_0_s1;
wire cpu_0_instruction_master_qualified_request_sdram_0_s1;
wire cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
wire cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_instruction_master_requests_sdram_0_s1;
wire cpu_0_instruction_master_saved_grant_sdram_0_s1;
reg d1_reasons_to_wait;
reg d1_sdram_0_s1_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sdram_0_s1;
wire in_a_read_cycle;
wire in_a_write_cycle;
reg last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1;
reg last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1;
wire [ 24: 0] sdram_0_s1_address;
wire sdram_0_s1_allgrants;
wire sdram_0_s1_allow_new_arb_cycle;
wire sdram_0_s1_any_bursting_master_saved_grant;
wire sdram_0_s1_any_continuerequest;
reg [ 1: 0] sdram_0_s1_arb_addend;
wire sdram_0_s1_arb_counter_enable;
reg [ 2: 0] sdram_0_s1_arb_share_counter;
wire [ 2: 0] sdram_0_s1_arb_share_counter_next_value;
wire [ 2: 0] sdram_0_s1_arb_share_set_values;
wire [ 1: 0] sdram_0_s1_arb_winner;
wire sdram_0_s1_arbitration_holdoff_internal;
wire sdram_0_s1_beginbursttransfer_internal;
wire sdram_0_s1_begins_xfer;
wire [ 3: 0] sdram_0_s1_byteenable_n;
wire sdram_0_s1_chipselect;
wire [ 3: 0] sdram_0_s1_chosen_master_double_vector;
wire [ 1: 0] sdram_0_s1_chosen_master_rot_left;
wire sdram_0_s1_end_xfer;
wire sdram_0_s1_firsttransfer;
wire [ 1: 0] sdram_0_s1_grant_vector;
wire sdram_0_s1_in_a_read_cycle;
wire sdram_0_s1_in_a_write_cycle;
wire [ 1: 0] sdram_0_s1_master_qreq_vector;
wire sdram_0_s1_move_on_to_next_transaction;
wire sdram_0_s1_non_bursting_master_requests;
wire sdram_0_s1_read_n;
wire [ 31: 0] sdram_0_s1_readdata_from_sa;
wire sdram_0_s1_readdatavalid_from_sa;
reg sdram_0_s1_reg_firsttransfer;
wire sdram_0_s1_reset_n;
reg [ 1: 0] sdram_0_s1_saved_chosen_master_vector;
reg sdram_0_s1_slavearbiterlockenable;
wire sdram_0_s1_slavearbiterlockenable2;
wire sdram_0_s1_unreg_firsttransfer;
wire sdram_0_s1_waitrequest_from_sa;
wire sdram_0_s1_waits_for_read;
wire sdram_0_s1_waits_for_write;
wire sdram_0_s1_write_n;
wire [ 31: 0] sdram_0_s1_writedata;
wire [ 27: 0] shifted_address_to_sdram_0_s1_from_cpu_0_data_master;
wire [ 27: 0] shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master;
wire wait_for_sdram_0_s1_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sdram_0_s1_end_xfer;
end
assign sdram_0_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sdram_0_s1 | cpu_0_instruction_master_qualified_request_sdram_0_s1));
//assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_readdata_from_sa = sdram_0_s1_readdata;
assign cpu_0_data_master_requests_sdram_0_s1 = ({cpu_0_data_master_address_to_slave[27] , 27'b0} == 28'h8000000) & (cpu_0_data_master_read | cpu_0_data_master_write);
//assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_waitrequest_from_sa = sdram_0_s1_waitrequest;
//assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sdram_0_s1_readdatavalid_from_sa = sdram_0_s1_readdatavalid;
//sdram_0_s1_arb_share_counter set values, which is an e_mux
assign sdram_0_s1_arb_share_set_values = 1;
//sdram_0_s1_non_bursting_master_requests mux, which is an e_mux
assign sdram_0_s1_non_bursting_master_requests = cpu_0_data_master_requests_sdram_0_s1 |
cpu_0_instruction_master_requests_sdram_0_s1 |
cpu_0_data_master_requests_sdram_0_s1 |
cpu_0_instruction_master_requests_sdram_0_s1;
//sdram_0_s1_any_bursting_master_saved_grant mux, which is an e_mux
assign sdram_0_s1_any_bursting_master_saved_grant = 0;
//sdram_0_s1_arb_share_counter_next_value assignment, which is an e_assign
assign sdram_0_s1_arb_share_counter_next_value = sdram_0_s1_firsttransfer ? (sdram_0_s1_arb_share_set_values - 1) : |sdram_0_s1_arb_share_counter ? (sdram_0_s1_arb_share_counter - 1) : 0;
//sdram_0_s1_allgrants all slave grants, which is an e_mux
assign sdram_0_s1_allgrants = (|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector) |
(|sdram_0_s1_grant_vector);
//sdram_0_s1_end_xfer assignment, which is an e_assign
assign sdram_0_s1_end_xfer = ~(sdram_0_s1_waits_for_read | sdram_0_s1_waits_for_write);
//end_xfer_arb_share_counter_term_sdram_0_s1 arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sdram_0_s1 = sdram_0_s1_end_xfer & (~sdram_0_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sdram_0_s1_arb_share_counter arbitration counter enable, which is an e_assign
assign sdram_0_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_sdram_0_s1 & sdram_0_s1_allgrants) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests);
//sdram_0_s1_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_arb_share_counter <= 0;
else if (sdram_0_s1_arb_counter_enable)
sdram_0_s1_arb_share_counter <= sdram_0_s1_arb_share_counter_next_value;
end
//sdram_0_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_slavearbiterlockenable <= 0;
else if ((|sdram_0_s1_master_qreq_vector & end_xfer_arb_share_counter_term_sdram_0_s1) | (end_xfer_arb_share_counter_term_sdram_0_s1 & ~sdram_0_s1_non_bursting_master_requests))
sdram_0_s1_slavearbiterlockenable <= |sdram_0_s1_arb_share_counter_next_value;
end
//cpu_0/data_master sdram_0/s1 arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sdram_0_s1_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sdram_0_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sdram_0_s1_slavearbiterlockenable2 = |sdram_0_s1_arb_share_counter_next_value;
//cpu_0/data_master sdram_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//cpu_0/instruction_master sdram_0/s1 arbiterlock, which is an e_assign
assign cpu_0_instruction_master_arbiterlock = sdram_0_s1_slavearbiterlockenable & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master sdram_0/s1 arbiterlock2, which is an e_assign
assign cpu_0_instruction_master_arbiterlock2 = sdram_0_s1_slavearbiterlockenable2 & cpu_0_instruction_master_continuerequest;
//cpu_0/instruction_master granted sdram_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 <= 0;
else
last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 <= cpu_0_instruction_master_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | ~cpu_0_instruction_master_requests_sdram_0_s1) ? 0 : last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1;
end
//cpu_0_instruction_master_continuerequest continued request, which is an e_mux
assign cpu_0_instruction_master_continuerequest = last_cycle_cpu_0_instruction_master_granted_slave_sdram_0_s1 & cpu_0_instruction_master_requests_sdram_0_s1;
//sdram_0_s1_any_continuerequest at least one master continues requesting, which is an e_mux
assign sdram_0_s1_any_continuerequest = cpu_0_instruction_master_continuerequest |
cpu_0_data_master_continuerequest;
assign cpu_0_data_master_qualified_request_sdram_0_s1 = cpu_0_data_master_requests_sdram_0_s1 & ~((cpu_0_data_master_read & (~cpu_0_data_master_waitrequest | (|cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register))) | ((~cpu_0_data_master_waitrequest) & cpu_0_data_master_write) | cpu_0_instruction_master_arbiterlock);
//unique name for sdram_0_s1_move_on_to_next_transaction, which is an e_assign
assign sdram_0_s1_move_on_to_next_transaction = sdram_0_s1_readdatavalid_from_sa;
//rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1_module rdv_fifo_for_cpu_0_data_master_to_sdram_0_s1
(
.clear_fifo (1'b0),
.clk (clk),
.data_in (cpu_0_data_master_granted_sdram_0_s1),
.data_out (cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1),
.empty (),
.fifo_contains_ones_n (cpu_0_data_master_rdv_fifo_empty_sdram_0_s1),
.full (),
.read (sdram_0_s1_move_on_to_next_transaction),
.reset_n (reset_n),
.sync_reset (1'b0),
.write (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
);
assign cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register = ~cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
//local readdatavalid cpu_0_data_master_read_data_valid_sdram_0_s1, which is an e_mux
assign cpu_0_data_master_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & cpu_0_data_master_rdv_fifo_output_from_sdram_0_s1) & ~ cpu_0_data_master_rdv_fifo_empty_sdram_0_s1;
//sdram_0_s1_writedata mux, which is an e_mux
assign sdram_0_s1_writedata = cpu_0_data_master_writedata;
assign cpu_0_instruction_master_requests_sdram_0_s1 = (({cpu_0_instruction_master_address_to_slave[27] , 27'b0} == 28'h8000000) & (cpu_0_instruction_master_read)) & cpu_0_instruction_master_read;
//cpu_0/data_master granted sdram_0/s1 last time, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 <= 0;
else
last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 <= cpu_0_data_master_saved_grant_sdram_0_s1 ? 1 : (sdram_0_s1_arbitration_holdoff_internal | ~cpu_0_data_master_requests_sdram_0_s1) ? 0 : last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1;
end
//cpu_0_data_master_continuerequest continued request, which is an e_mux
assign cpu_0_data_master_continuerequest = last_cycle_cpu_0_data_master_granted_slave_sdram_0_s1 & cpu_0_data_master_requests_sdram_0_s1;
assign cpu_0_instruction_master_qualified_request_sdram_0_s1 = cpu_0_instruction_master_requests_sdram_0_s1 & ~((cpu_0_instruction_master_read & ((|cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register))) | cpu_0_data_master_arbiterlock);
//rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1, which is an e_fifo_with_registered_outputs
rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1_module rdv_fifo_for_cpu_0_instruction_master_to_sdram_0_s1
(
.clear_fifo (1'b0),
.clk (clk),
.data_in (cpu_0_instruction_master_granted_sdram_0_s1),
.data_out (cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1),
.empty (),
.fifo_contains_ones_n (cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1),
.full (),
.read (sdram_0_s1_move_on_to_next_transaction),
.reset_n (reset_n),
.sync_reset (1'b0),
.write (in_a_read_cycle & ~sdram_0_s1_waits_for_read)
);
assign cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register = ~cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
//local readdatavalid cpu_0_instruction_master_read_data_valid_sdram_0_s1, which is an e_mux
assign cpu_0_instruction_master_read_data_valid_sdram_0_s1 = (sdram_0_s1_readdatavalid_from_sa & cpu_0_instruction_master_rdv_fifo_output_from_sdram_0_s1) & ~ cpu_0_instruction_master_rdv_fifo_empty_sdram_0_s1;
//allow new arb cycle for sdram_0/s1, which is an e_assign
assign sdram_0_s1_allow_new_arb_cycle = ~cpu_0_data_master_arbiterlock & ~cpu_0_instruction_master_arbiterlock;
//cpu_0/instruction_master assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
assign sdram_0_s1_master_qreq_vector[0] = cpu_0_instruction_master_qualified_request_sdram_0_s1;
//cpu_0/instruction_master grant sdram_0/s1, which is an e_assign
assign cpu_0_instruction_master_granted_sdram_0_s1 = sdram_0_s1_grant_vector[0];
//cpu_0/instruction_master saved-grant sdram_0/s1, which is an e_assign
assign cpu_0_instruction_master_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[0] && cpu_0_instruction_master_requests_sdram_0_s1;
//cpu_0/data_master assignment into master qualified-requests vector for sdram_0/s1, which is an e_assign
assign sdram_0_s1_master_qreq_vector[1] = cpu_0_data_master_qualified_request_sdram_0_s1;
//cpu_0/data_master grant sdram_0/s1, which is an e_assign
assign cpu_0_data_master_granted_sdram_0_s1 = sdram_0_s1_grant_vector[1];
//cpu_0/data_master saved-grant sdram_0/s1, which is an e_assign
assign cpu_0_data_master_saved_grant_sdram_0_s1 = sdram_0_s1_arb_winner[1] && cpu_0_data_master_requests_sdram_0_s1;
//sdram_0/s1 chosen-master double-vector, which is an e_assign
assign sdram_0_s1_chosen_master_double_vector = {sdram_0_s1_master_qreq_vector, sdram_0_s1_master_qreq_vector} & ({~sdram_0_s1_master_qreq_vector, ~sdram_0_s1_master_qreq_vector} + sdram_0_s1_arb_addend);
//stable onehot encoding of arb winner
assign sdram_0_s1_arb_winner = (sdram_0_s1_allow_new_arb_cycle & | sdram_0_s1_grant_vector) ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;
//saved sdram_0_s1_grant_vector, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_saved_chosen_master_vector <= 0;
else if (sdram_0_s1_allow_new_arb_cycle)
sdram_0_s1_saved_chosen_master_vector <= |sdram_0_s1_grant_vector ? sdram_0_s1_grant_vector : sdram_0_s1_saved_chosen_master_vector;
end
//onehot encoding of chosen master
assign sdram_0_s1_grant_vector = {(sdram_0_s1_chosen_master_double_vector[1] | sdram_0_s1_chosen_master_double_vector[3]),
(sdram_0_s1_chosen_master_double_vector[0] | sdram_0_s1_chosen_master_double_vector[2])};
//sdram_0/s1 chosen master rotated left, which is an e_assign
assign sdram_0_s1_chosen_master_rot_left = (sdram_0_s1_arb_winner << 1) ? (sdram_0_s1_arb_winner << 1) : 1;
//sdram_0/s1's addend for next-master-grant
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_arb_addend <= 1;
else if (|sdram_0_s1_grant_vector)
sdram_0_s1_arb_addend <= sdram_0_s1_end_xfer? sdram_0_s1_chosen_master_rot_left : sdram_0_s1_grant_vector;
end
//sdram_0_s1_reset_n assignment, which is an e_assign
assign sdram_0_s1_reset_n = reset_n;
assign sdram_0_s1_chipselect = cpu_0_data_master_granted_sdram_0_s1 | cpu_0_instruction_master_granted_sdram_0_s1;
//sdram_0_s1_firsttransfer first transaction, which is an e_assign
assign sdram_0_s1_firsttransfer = sdram_0_s1_begins_xfer ? sdram_0_s1_unreg_firsttransfer : sdram_0_s1_reg_firsttransfer;
//sdram_0_s1_unreg_firsttransfer first transaction, which is an e_assign
assign sdram_0_s1_unreg_firsttransfer = ~(sdram_0_s1_slavearbiterlockenable & sdram_0_s1_any_continuerequest);
//sdram_0_s1_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sdram_0_s1_reg_firsttransfer <= 1'b1;
else if (sdram_0_s1_begins_xfer)
sdram_0_s1_reg_firsttransfer <= sdram_0_s1_unreg_firsttransfer;
end
//sdram_0_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sdram_0_s1_beginbursttransfer_internal = sdram_0_s1_begins_xfer;
//sdram_0_s1_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
assign sdram_0_s1_arbitration_holdoff_internal = sdram_0_s1_begins_xfer & sdram_0_s1_firsttransfer;
//~sdram_0_s1_read_n assignment, which is an e_mux
assign sdram_0_s1_read_n = ~((cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sdram_0_s1 & cpu_0_instruction_master_read));
//~sdram_0_s1_write_n assignment, which is an e_mux
assign sdram_0_s1_write_n = ~(cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_write);
assign shifted_address_to_sdram_0_s1_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//sdram_0_s1_address mux, which is an e_mux
assign sdram_0_s1_address = (cpu_0_data_master_granted_sdram_0_s1)? (shifted_address_to_sdram_0_s1_from_cpu_0_data_master >> 2) :
(shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master >> 2);
assign shifted_address_to_sdram_0_s1_from_cpu_0_instruction_master = cpu_0_instruction_master_address_to_slave;
//d1_sdram_0_s1_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sdram_0_s1_end_xfer <= 1;
else
d1_sdram_0_s1_end_xfer <= sdram_0_s1_end_xfer;
end
//sdram_0_s1_waits_for_read in a cycle, which is an e_mux
assign sdram_0_s1_waits_for_read = sdram_0_s1_in_a_read_cycle & sdram_0_s1_waitrequest_from_sa;
//sdram_0_s1_in_a_read_cycle assignment, which is an e_assign
assign sdram_0_s1_in_a_read_cycle = (cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_read) | (cpu_0_instruction_master_granted_sdram_0_s1 & cpu_0_instruction_master_read);
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sdram_0_s1_in_a_read_cycle;
//sdram_0_s1_waits_for_write in a cycle, which is an e_mux
assign sdram_0_s1_waits_for_write = sdram_0_s1_in_a_write_cycle & sdram_0_s1_waitrequest_from_sa;
//sdram_0_s1_in_a_write_cycle assignment, which is an e_assign
assign sdram_0_s1_in_a_write_cycle = cpu_0_data_master_granted_sdram_0_s1 & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sdram_0_s1_in_a_write_cycle;
assign wait_for_sdram_0_s1_counter = 0;
//~sdram_0_s1_byteenable_n byte enable port mux, which is an e_mux
assign sdram_0_s1_byteenable_n = ~((cpu_0_data_master_granted_sdram_0_s1)? cpu_0_data_master_byteenable :
-1);
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sdram_0/s1 enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_granted_sdram_0_s1 + cpu_0_instruction_master_granted_sdram_0_s1 > 1)
begin
$write("%0d ns: > 1 of grant signals are active simultaneously", $time);
$stop;
end
end
//saved_grant signals are active simultaneously, which is an e_process
always @(posedge clk)
begin
if (cpu_0_data_master_saved_grant_sdram_0_s1 + cpu_0_instruction_master_saved_grant_sdram_0_s1 > 1)
begin
$write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
$stop;
end
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module sysid_control_slave_arbitrator (
// inputs:
clk,
cpu_0_data_master_address_to_slave,
cpu_0_data_master_read,
cpu_0_data_master_write,
reset_n,
sysid_control_slave_readdata,
// outputs:
cpu_0_data_master_granted_sysid_control_slave,
cpu_0_data_master_qualified_request_sysid_control_slave,
cpu_0_data_master_read_data_valid_sysid_control_slave,
cpu_0_data_master_requests_sysid_control_slave,
d1_sysid_control_slave_end_xfer,
sysid_control_slave_address,
sysid_control_slave_readdata_from_sa,
sysid_control_slave_reset_n
)
;
output cpu_0_data_master_granted_sysid_control_slave;
output cpu_0_data_master_qualified_request_sysid_control_slave;
output cpu_0_data_master_read_data_valid_sysid_control_slave;
output cpu_0_data_master_requests_sysid_control_slave;
output d1_sysid_control_slave_end_xfer;
output sysid_control_slave_address;
output [ 31: 0] sysid_control_slave_readdata_from_sa;
output sysid_control_slave_reset_n;
input clk;
input [ 27: 0] cpu_0_data_master_address_to_slave;
input cpu_0_data_master_read;
input cpu_0_data_master_write;
input reset_n;
input [ 31: 0] sysid_control_slave_readdata;
wire cpu_0_data_master_arbiterlock;
wire cpu_0_data_master_arbiterlock2;
wire cpu_0_data_master_continuerequest;
wire cpu_0_data_master_granted_sysid_control_slave;
wire cpu_0_data_master_qualified_request_sysid_control_slave;
wire cpu_0_data_master_read_data_valid_sysid_control_slave;
wire cpu_0_data_master_requests_sysid_control_slave;
wire cpu_0_data_master_saved_grant_sysid_control_slave;
reg d1_reasons_to_wait;
reg d1_sysid_control_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_sysid_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire [ 27: 0] shifted_address_to_sysid_control_slave_from_cpu_0_data_master;
wire sysid_control_slave_address;
wire sysid_control_slave_allgrants;
wire sysid_control_slave_allow_new_arb_cycle;
wire sysid_control_slave_any_bursting_master_saved_grant;
wire sysid_control_slave_any_continuerequest;
wire sysid_control_slave_arb_counter_enable;
reg [ 2: 0] sysid_control_slave_arb_share_counter;
wire [ 2: 0] sysid_control_slave_arb_share_counter_next_value;
wire [ 2: 0] sysid_control_slave_arb_share_set_values;
wire sysid_control_slave_beginbursttransfer_internal;
wire sysid_control_slave_begins_xfer;
wire sysid_control_slave_end_xfer;
wire sysid_control_slave_firsttransfer;
wire sysid_control_slave_grant_vector;
wire sysid_control_slave_in_a_read_cycle;
wire sysid_control_slave_in_a_write_cycle;
wire sysid_control_slave_master_qreq_vector;
wire sysid_control_slave_non_bursting_master_requests;
wire [ 31: 0] sysid_control_slave_readdata_from_sa;
reg sysid_control_slave_reg_firsttransfer;
wire sysid_control_slave_reset_n;
reg sysid_control_slave_slavearbiterlockenable;
wire sysid_control_slave_slavearbiterlockenable2;
wire sysid_control_slave_unreg_firsttransfer;
wire sysid_control_slave_waits_for_read;
wire sysid_control_slave_waits_for_write;
wire wait_for_sysid_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~sysid_control_slave_end_xfer;
end
assign sysid_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_0_data_master_qualified_request_sysid_control_slave));
//assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata;
assign cpu_0_data_master_requests_sysid_control_slave = (({cpu_0_data_master_address_to_slave[27 : 3] , 3'b0} == 28'h30) & (cpu_0_data_master_read | cpu_0_data_master_write)) & cpu_0_data_master_read;
//sysid_control_slave_arb_share_counter set values, which is an e_mux
assign sysid_control_slave_arb_share_set_values = 1;
//sysid_control_slave_non_bursting_master_requests mux, which is an e_mux
assign sysid_control_slave_non_bursting_master_requests = cpu_0_data_master_requests_sysid_control_slave;
//sysid_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign sysid_control_slave_any_bursting_master_saved_grant = 0;
//sysid_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign sysid_control_slave_arb_share_counter_next_value = sysid_control_slave_firsttransfer ? (sysid_control_slave_arb_share_set_values - 1) : |sysid_control_slave_arb_share_counter ? (sysid_control_slave_arb_share_counter - 1) : 0;
//sysid_control_slave_allgrants all slave grants, which is an e_mux
assign sysid_control_slave_allgrants = |sysid_control_slave_grant_vector;
//sysid_control_slave_end_xfer assignment, which is an e_assign
assign sysid_control_slave_end_xfer = ~(sysid_control_slave_waits_for_read | sysid_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_sysid_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_sysid_control_slave = sysid_control_slave_end_xfer & (~sysid_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//sysid_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign sysid_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_control_slave & sysid_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests);
//sysid_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_arb_share_counter <= 0;
else if (sysid_control_slave_arb_counter_enable)
sysid_control_slave_arb_share_counter <= sysid_control_slave_arb_share_counter_next_value;
end
//sysid_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_slavearbiterlockenable <= 0;
else if ((|sysid_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_control_slave) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests))
sysid_control_slave_slavearbiterlockenable <= |sysid_control_slave_arb_share_counter_next_value;
end
//cpu_0/data_master sysid/control_slave arbiterlock, which is an e_assign
assign cpu_0_data_master_arbiterlock = sysid_control_slave_slavearbiterlockenable & cpu_0_data_master_continuerequest;
//sysid_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign sysid_control_slave_slavearbiterlockenable2 = |sysid_control_slave_arb_share_counter_next_value;
//cpu_0/data_master sysid/control_slave arbiterlock2, which is an e_assign
assign cpu_0_data_master_arbiterlock2 = sysid_control_slave_slavearbiterlockenable2 & cpu_0_data_master_continuerequest;
//sysid_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign sysid_control_slave_any_continuerequest = 1;
//cpu_0_data_master_continuerequest continued request, which is an e_assign
assign cpu_0_data_master_continuerequest = 1;
assign cpu_0_data_master_qualified_request_sysid_control_slave = cpu_0_data_master_requests_sysid_control_slave;
//master is always granted when requested
assign cpu_0_data_master_granted_sysid_control_slave = cpu_0_data_master_qualified_request_sysid_control_slave;
//cpu_0/data_master saved-grant sysid/control_slave, which is an e_assign
assign cpu_0_data_master_saved_grant_sysid_control_slave = cpu_0_data_master_requests_sysid_control_slave;
//allow new arb cycle for sysid/control_slave, which is an e_assign
assign sysid_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign sysid_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign sysid_control_slave_master_qreq_vector = 1;
//sysid_control_slave_reset_n assignment, which is an e_assign
assign sysid_control_slave_reset_n = reset_n;
//sysid_control_slave_firsttransfer first transaction, which is an e_assign
assign sysid_control_slave_firsttransfer = sysid_control_slave_begins_xfer ? sysid_control_slave_unreg_firsttransfer : sysid_control_slave_reg_firsttransfer;
//sysid_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign sysid_control_slave_unreg_firsttransfer = ~(sysid_control_slave_slavearbiterlockenable & sysid_control_slave_any_continuerequest);
//sysid_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
sysid_control_slave_reg_firsttransfer <= 1'b1;
else if (sysid_control_slave_begins_xfer)
sysid_control_slave_reg_firsttransfer <= sysid_control_slave_unreg_firsttransfer;
end
//sysid_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign sysid_control_slave_beginbursttransfer_internal = sysid_control_slave_begins_xfer;
assign shifted_address_to_sysid_control_slave_from_cpu_0_data_master = cpu_0_data_master_address_to_slave;
//sysid_control_slave_address mux, which is an e_mux
assign sysid_control_slave_address = shifted_address_to_sysid_control_slave_from_cpu_0_data_master >> 2;
//d1_sysid_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_sysid_control_slave_end_xfer <= 1;
else
d1_sysid_control_slave_end_xfer <= sysid_control_slave_end_xfer;
end
//sysid_control_slave_waits_for_read in a cycle, which is an e_mux
assign sysid_control_slave_waits_for_read = sysid_control_slave_in_a_read_cycle & sysid_control_slave_begins_xfer;
//sysid_control_slave_in_a_read_cycle assignment, which is an e_assign
assign sysid_control_slave_in_a_read_cycle = cpu_0_data_master_granted_sysid_control_slave & cpu_0_data_master_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = sysid_control_slave_in_a_read_cycle;
//sysid_control_slave_waits_for_write in a cycle, which is an e_mux
assign sysid_control_slave_waits_for_write = sysid_control_slave_in_a_write_cycle & 0;
//sysid_control_slave_in_a_write_cycle assignment, which is an e_assign
assign sysid_control_slave_in_a_write_cycle = cpu_0_data_master_granted_sysid_control_slave & cpu_0_data_master_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = sysid_control_slave_in_a_write_cycle;
assign wait_for_sysid_control_slave_counter = 0;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//sysid/control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_buffer_slave_arbitrator (
// inputs:
clk,
nios_system_clock_1_out_address_to_slave,
nios_system_clock_1_out_read,
nios_system_clock_1_out_write,
nios_system_clock_1_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest,
// outputs:
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer,
nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_address,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_read,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_write,
video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata
)
;
output d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
output nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
output [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
output [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
output video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
output [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
input clk;
input [ 12: 0] nios_system_clock_1_out_address_to_slave;
input nios_system_clock_1_out_read;
input nios_system_clock_1_out_write;
input [ 7: 0] nios_system_clock_1_out_writedata;
input reset_n;
input [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
input video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
reg d1_reasons_to_wait;
reg d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire nios_system_clock_1_out_arbiterlock;
wire nios_system_clock_1_out_arbiterlock2;
wire nios_system_clock_1_out_continuerequest;
wire nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
reg nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in;
wire nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
wire [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_allow_new_arb_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer;
reg video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
wire wait_for_video_character_buffer_with_dma_0_avalon_char_buffer_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
end
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer = ~d1_reasons_to_wait & ((nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave));
//assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
assign nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave = (1) & (nios_system_clock_1_out_read | nios_system_clock_1_out_write);
//assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa = video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter set values, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values = 1;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant = 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value = video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer ? (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_set_values - 1) : |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter ? (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter - 1) : 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants all slave grants, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants = |video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer = ~(video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read | video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write);
//end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave = video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer & (~video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & video_character_buffer_with_dma_0_avalon_char_buffer_slave_allgrants) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter <= 0;
else if (video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_counter_enable)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable <= 0;
else if ((|video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector & end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_non_bursting_master_requests))
video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable <= |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
end
//nios_system_clock_1/out video_character_buffer_with_dma_0/avalon_char_buffer_slave arbiterlock, which is an e_assign
assign nios_system_clock_1_out_arbiterlock = video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable & nios_system_clock_1_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 = |video_character_buffer_with_dma_0_avalon_char_buffer_slave_arb_share_counter_next_value;
//nios_system_clock_1/out video_character_buffer_with_dma_0/avalon_char_buffer_slave arbiterlock2, which is an e_assign
assign nios_system_clock_1_out_arbiterlock2 = video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable2 & nios_system_clock_1_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest = 1;
//nios_system_clock_1_out_continuerequest continued request, which is an e_assign
assign nios_system_clock_1_out_continuerequest = 1;
assign nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave & ~((nios_system_clock_1_out_read & ((|nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register))));
//nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read & ~video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read & ~(|nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register);
//shift register p1 nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register = {nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register, nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register_in};
//nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register <= 0;
else
nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register <= p1_nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
end
//local readdatavalid nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave, which is an e_mux
assign nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave_shift_register;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata = nios_system_clock_1_out_writedata;
//master is always granted when requested
assign nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//nios_system_clock_1/out saved-grant video_character_buffer_with_dma_0/avalon_char_buffer_slave, which is an e_assign
assign nios_system_clock_1_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_buffer_slave = nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//allow new arb cycle for video_character_buffer_with_dma_0/avalon_char_buffer_slave, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_master_qreq_vector = 1;
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_firsttransfer = video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer ? video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer : video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer = ~(video_character_buffer_with_dma_0_avalon_char_buffer_slave_slavearbiterlockenable & video_character_buffer_with_dma_0_avalon_char_buffer_slave_any_continuerequest);
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer <= 1'b1;
else if (video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer)
video_character_buffer_with_dma_0_avalon_char_buffer_slave_reg_firsttransfer <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_unreg_firsttransfer;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_beginbursttransfer_internal = video_character_buffer_with_dma_0_avalon_char_buffer_slave_begins_xfer;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_read assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_read = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_write assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_write = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_write;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_address mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_address = nios_system_clock_1_out_address_to_slave;
//d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer <= 1;
else
d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer <= video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
end
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_read = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle & video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_read_cycle;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_waits_for_write = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle & video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle = nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave & nios_system_clock_1_out_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = video_character_buffer_with_dma_0_avalon_char_buffer_slave_in_a_write_cycle;
assign wait_for_video_character_buffer_with_dma_0_avalon_char_buffer_slave_counter = 0;
//video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable byte enable port mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable = (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave)? {1 {1'b1}} :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//video_character_buffer_with_dma_0/avalon_char_buffer_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_control_slave_arbitrator (
// inputs:
clk,
nios_system_clock_0_out_address_to_slave,
nios_system_clock_0_out_byteenable,
nios_system_clock_0_out_read,
nios_system_clock_0_out_write,
nios_system_clock_0_out_writedata,
reset_n,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata,
// outputs:
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer,
nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave,
nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave,
video_character_buffer_with_dma_0_avalon_char_control_slave_address,
video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable,
video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect,
video_character_buffer_with_dma_0_avalon_char_control_slave_read,
video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa,
video_character_buffer_with_dma_0_avalon_char_control_slave_reset,
video_character_buffer_with_dma_0_avalon_char_control_slave_write,
video_character_buffer_with_dma_0_avalon_char_control_slave_writedata
)
;
output d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
output nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
output nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
output video_character_buffer_with_dma_0_avalon_char_control_slave_address;
output [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
output video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
output video_character_buffer_with_dma_0_avalon_char_control_slave_read;
output [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
output video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
output video_character_buffer_with_dma_0_avalon_char_control_slave_write;
output [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
input clk;
input [ 2: 0] nios_system_clock_0_out_address_to_slave;
input [ 3: 0] nios_system_clock_0_out_byteenable;
input nios_system_clock_0_out_read;
input nios_system_clock_0_out_write;
input [ 31: 0] nios_system_clock_0_out_writedata;
input reset_n;
input [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
reg d1_reasons_to_wait;
reg d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
reg enable_nonzero_assertions;
wire end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire in_a_read_cycle;
wire in_a_write_cycle;
wire nios_system_clock_0_out_arbiterlock;
wire nios_system_clock_0_out_arbiterlock2;
wire nios_system_clock_0_out_continuerequest;
wire nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
reg nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in;
wire nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
wire [ 2: 0] shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_allow_new_arb_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer;
wire [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_read;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
reg video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_write;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
wire wait_for_video_character_buffer_with_dma_0_avalon_char_control_slave_counter;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_reasons_to_wait <= 0;
else
d1_reasons_to_wait <= ~video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
end
assign video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer = ~d1_reasons_to_wait & ((nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave));
//assign video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa = video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
assign nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave = (1) & (nios_system_clock_0_out_read | nios_system_clock_0_out_write);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter set values, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values = 1;
//video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant = 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value = video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer ? (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_set_values - 1) : |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter ? (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter - 1) : 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants all slave grants, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants = |video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector;
//video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer = ~(video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read | video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write);
//end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave arb share counter enable term, which is an e_assign
assign end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave = video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer & (~video_character_buffer_with_dma_0_avalon_char_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & video_character_buffer_with_dma_0_avalon_char_control_slave_allgrants) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & ~video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests);
//video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter counter, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter <= 0;
else if (video_character_buffer_with_dma_0_avalon_char_control_slave_arb_counter_enable)
video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter <= video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable <= 0;
else if ((|video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave) | (end_xfer_arb_share_counter_term_video_character_buffer_with_dma_0_avalon_char_control_slave & ~video_character_buffer_with_dma_0_avalon_char_control_slave_non_bursting_master_requests))
video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable <= |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
end
//nios_system_clock_0/out video_character_buffer_with_dma_0/avalon_char_control_slave arbiterlock, which is an e_assign
assign nios_system_clock_0_out_arbiterlock = video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable & nios_system_clock_0_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 = |video_character_buffer_with_dma_0_avalon_char_control_slave_arb_share_counter_next_value;
//nios_system_clock_0/out video_character_buffer_with_dma_0/avalon_char_control_slave arbiterlock2, which is an e_assign
assign nios_system_clock_0_out_arbiterlock2 = video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable2 & nios_system_clock_0_out_continuerequest;
//video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest = 1;
//nios_system_clock_0_out_continuerequest continued request, which is an e_assign
assign nios_system_clock_0_out_continuerequest = 1;
assign nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave & ~((nios_system_clock_0_out_read & ((|nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register))));
//nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in mux for readlatency shift register, which is an e_mux
assign nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read & ~video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read & ~(|nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register);
//shift register p1 nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register in if flush, otherwise shift left, which is an e_mux
assign p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register = {nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register, nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register_in};
//nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register <= 0;
else
nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register <= p1_nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
end
//local readdatavalid nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave, which is an e_mux
assign nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave_shift_register;
//video_character_buffer_with_dma_0_avalon_char_control_slave_writedata mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_writedata = nios_system_clock_0_out_writedata;
//master is always granted when requested
assign nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
//nios_system_clock_0/out saved-grant video_character_buffer_with_dma_0/avalon_char_control_slave, which is an e_assign
assign nios_system_clock_0_out_saved_grant_video_character_buffer_with_dma_0_avalon_char_control_slave = nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
//allow new arb cycle for video_character_buffer_with_dma_0/avalon_char_control_slave, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_allow_new_arb_cycle = 1;
//placeholder chosen master
assign video_character_buffer_with_dma_0_avalon_char_control_slave_grant_vector = 1;
//placeholder vector of master qualified-requests
assign video_character_buffer_with_dma_0_avalon_char_control_slave_master_qreq_vector = 1;
//~video_character_buffer_with_dma_0_avalon_char_control_slave_reset assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_reset = ~reset_n;
assign video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_firsttransfer = video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer ? video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer : video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer;
//video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer first transaction, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer = ~(video_character_buffer_with_dma_0_avalon_char_control_slave_slavearbiterlockenable & video_character_buffer_with_dma_0_avalon_char_control_slave_any_continuerequest);
//video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer first transaction, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer <= 1'b1;
else if (video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer)
video_character_buffer_with_dma_0_avalon_char_control_slave_reg_firsttransfer <= video_character_buffer_with_dma_0_avalon_char_control_slave_unreg_firsttransfer;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_beginbursttransfer_internal = video_character_buffer_with_dma_0_avalon_char_control_slave_begins_xfer;
//video_character_buffer_with_dma_0_avalon_char_control_slave_read assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_read = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read;
//video_character_buffer_with_dma_0_avalon_char_control_slave_write assignment, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_write = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_write;
assign shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out = nios_system_clock_0_out_address_to_slave;
//video_character_buffer_with_dma_0_avalon_char_control_slave_address mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_address = shifted_address_to_video_character_buffer_with_dma_0_avalon_char_control_slave_from_nios_system_clock_0_out >> 2;
//d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer register, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer <= 1;
else
d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer <= video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
end
//video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_read = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle & 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_read;
//in_a_read_cycle assignment, which is an e_mux
assign in_a_read_cycle = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_read_cycle;
//video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write in a cycle, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_waits_for_write = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle & 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle assignment, which is an e_assign
assign video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle = nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave & nios_system_clock_0_out_write;
//in_a_write_cycle assignment, which is an e_mux
assign in_a_write_cycle = video_character_buffer_with_dma_0_avalon_char_control_slave_in_a_write_cycle;
assign wait_for_video_character_buffer_with_dma_0_avalon_char_control_slave_counter = 0;
//video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable byte enable port mux, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable = (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave)? nios_system_clock_0_out_byteenable :
-1;
//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
//video_character_buffer_with_dma_0/avalon_char_control_slave enable non-zero assertions, which is an e_register
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
enable_nonzero_assertions <= 0;
else
enable_nonzero_assertions <= 1'b1;
end
//////////////// END SIMULATION-ONLY CONTENTS
//synthesis translate_on
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_character_buffer_with_dma_0_avalon_char_source_arbitrator (
// inputs:
clk,
reset_n,
video_character_buffer_with_dma_0_avalon_char_source_data,
video_character_buffer_with_dma_0_avalon_char_source_endofpacket,
video_character_buffer_with_dma_0_avalon_char_source_startofpacket,
video_character_buffer_with_dma_0_avalon_char_source_valid,
video_vga_controller_0_avalon_vga_sink_ready_from_sa,
// outputs:
video_character_buffer_with_dma_0_avalon_char_source_ready
)
;
output video_character_buffer_with_dma_0_avalon_char_source_ready;
input clk;
input reset_n;
input [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
input video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_valid;
input video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_source_ready;
//mux video_character_buffer_with_dma_0_avalon_char_source_ready, which is an e_mux
assign video_character_buffer_with_dma_0_avalon_char_source_ready = video_vga_controller_0_avalon_vga_sink_ready_from_sa;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module video_vga_controller_0_avalon_vga_sink_arbitrator (
// inputs:
clk,
reset_n,
video_character_buffer_with_dma_0_avalon_char_source_data,
video_character_buffer_with_dma_0_avalon_char_source_endofpacket,
video_character_buffer_with_dma_0_avalon_char_source_startofpacket,
video_character_buffer_with_dma_0_avalon_char_source_valid,
video_vga_controller_0_avalon_vga_sink_ready,
// outputs:
video_vga_controller_0_avalon_vga_sink_data,
video_vga_controller_0_avalon_vga_sink_endofpacket,
video_vga_controller_0_avalon_vga_sink_ready_from_sa,
video_vga_controller_0_avalon_vga_sink_reset,
video_vga_controller_0_avalon_vga_sink_startofpacket,
video_vga_controller_0_avalon_vga_sink_valid
)
;
output [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
output video_vga_controller_0_avalon_vga_sink_endofpacket;
output video_vga_controller_0_avalon_vga_sink_ready_from_sa;
output video_vga_controller_0_avalon_vga_sink_reset;
output video_vga_controller_0_avalon_vga_sink_startofpacket;
output video_vga_controller_0_avalon_vga_sink_valid;
input clk;
input reset_n;
input [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
input video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
input video_character_buffer_with_dma_0_avalon_char_source_valid;
input video_vga_controller_0_avalon_vga_sink_ready;
wire [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
wire video_vga_controller_0_avalon_vga_sink_endofpacket;
wire video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_vga_controller_0_avalon_vga_sink_reset;
wire video_vga_controller_0_avalon_vga_sink_startofpacket;
wire video_vga_controller_0_avalon_vga_sink_valid;
//mux video_vga_controller_0_avalon_vga_sink_data, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_data = video_character_buffer_with_dma_0_avalon_char_source_data;
//mux video_vga_controller_0_avalon_vga_sink_endofpacket, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_endofpacket = video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
//assign video_vga_controller_0_avalon_vga_sink_ready_from_sa = video_vga_controller_0_avalon_vga_sink_ready so that symbol knows where to group signals which may go to master only, which is an e_assign
assign video_vga_controller_0_avalon_vga_sink_ready_from_sa = video_vga_controller_0_avalon_vga_sink_ready;
//mux video_vga_controller_0_avalon_vga_sink_startofpacket, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_startofpacket = video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
//mux video_vga_controller_0_avalon_vga_sink_valid, which is an e_mux
assign video_vga_controller_0_avalon_vga_sink_valid = video_character_buffer_with_dma_0_avalon_char_source_valid;
//~video_vga_controller_0_avalon_vga_sink_reset assignment, which is an e_assign
assign video_vga_controller_0_avalon_vga_sink_reset = ~reset_n;
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_reset_clk_0_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system_reset_vga_clock_domain_synch_module (
// inputs:
clk,
data_in,
reset_n,
// outputs:
data_out
)
;
output data_out;
input clk;
input data_in;
input reset_n;
reg data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "{-from \"*\"} CUT=ON ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
reg data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101" */;
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_in_d1 <= 0;
else
data_in_d1 <= data_in;
end
always @(posedge clk or negedge reset_n)
begin
if (reset_n == 0)
data_out <= 0;
else
data_out <= data_in_d1;
end
endmodule
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module nios_system (
// 1) global signals:
clk_0,
clocks_SDRAM_CLK_out,
clocks_sys_clk_out,
reset_n,
vga_clock,
// the_Altera_UP_SD_Card_Avalon_Interface_0
b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0,
// the_input1
in_port_to_the_input1,
// the_output1
out_port_from_the_output1,
// the_sdram_0
zs_addr_from_the_sdram_0,
zs_ba_from_the_sdram_0,
zs_cas_n_from_the_sdram_0,
zs_cke_from_the_sdram_0,
zs_cs_n_from_the_sdram_0,
zs_dq_to_and_from_the_sdram_0,
zs_dqm_from_the_sdram_0,
zs_ras_n_from_the_sdram_0,
zs_we_n_from_the_sdram_0,
// the_video_vga_controller_0
VGA_BLANK_from_the_video_vga_controller_0,
VGA_B_from_the_video_vga_controller_0,
VGA_CLK_from_the_video_vga_controller_0,
VGA_G_from_the_video_vga_controller_0,
VGA_HS_from_the_video_vga_controller_0,
VGA_R_from_the_video_vga_controller_0,
VGA_SYNC_from_the_video_vga_controller_0,
VGA_VS_from_the_video_vga_controller_0
)
;
output VGA_BLANK_from_the_video_vga_controller_0;
output [ 7: 0] VGA_B_from_the_video_vga_controller_0;
output VGA_CLK_from_the_video_vga_controller_0;
output [ 7: 0] VGA_G_from_the_video_vga_controller_0;
output VGA_HS_from_the_video_vga_controller_0;
output [ 7: 0] VGA_R_from_the_video_vga_controller_0;
output VGA_SYNC_from_the_video_vga_controller_0;
output VGA_VS_from_the_video_vga_controller_0;
inout b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
inout b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
inout b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
output clocks_SDRAM_CLK_out;
output clocks_sys_clk_out;
output o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
output [ 7: 0] out_port_from_the_output1;
output [ 12: 0] zs_addr_from_the_sdram_0;
output [ 1: 0] zs_ba_from_the_sdram_0;
output zs_cas_n_from_the_sdram_0;
output zs_cke_from_the_sdram_0;
output zs_cs_n_from_the_sdram_0;
inout [ 31: 0] zs_dq_to_and_from_the_sdram_0;
output [ 3: 0] zs_dqm_from_the_sdram_0;
output zs_ras_n_from_the_sdram_0;
output zs_we_n_from_the_sdram_0;
input clk_0;
input [ 7: 0] in_port_to_the_input1;
input reset_n;
input vga_clock;
wire [ 7: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address;
wire [ 3: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa;
wire Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write;
wire [ 31: 0] Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata;
wire VGA_BLANK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_B_from_the_video_vga_controller_0;
wire VGA_CLK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_G_from_the_video_vga_controller_0;
wire VGA_HS_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_R_from_the_video_vga_controller_0;
wire VGA_SYNC_from_the_video_vga_controller_0;
wire VGA_VS_from_the_video_vga_controller_0;
wire b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire clk_0_reset_n;
wire clocks_SDRAM_CLK_out;
wire clocks_avalon_clocks_slave_address;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata;
wire [ 7: 0] clocks_avalon_clocks_slave_readdata_from_sa;
wire clocks_sys_clk_out;
wire [ 27: 0] cpu_0_data_master_address;
wire [ 27: 0] cpu_0_data_master_address_to_slave;
wire [ 3: 0] cpu_0_data_master_byteenable;
wire cpu_0_data_master_byteenable_nios_system_clock_1_in;
wire [ 1: 0] cpu_0_data_master_dbs_address;
wire [ 7: 0] cpu_0_data_master_dbs_write_8;
wire cpu_0_data_master_debugaccess;
wire cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_granted_clocks_avalon_clocks_slave;
wire cpu_0_data_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_data_master_granted_input1_s1;
wire cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_granted_nios_system_clock_0_in;
wire cpu_0_data_master_granted_nios_system_clock_1_in;
wire cpu_0_data_master_granted_onchip_memory2_0_s1;
wire cpu_0_data_master_granted_output1_s1;
wire cpu_0_data_master_granted_sdram_0_s1;
wire cpu_0_data_master_granted_sysid_control_slave;
wire [ 31: 0] cpu_0_data_master_irq;
wire cpu_0_data_master_no_byte_enables_and_last_term;
wire cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave;
wire cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_data_master_qualified_request_input1_s1;
wire cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_qualified_request_nios_system_clock_0_in;
wire cpu_0_data_master_qualified_request_nios_system_clock_1_in;
wire cpu_0_data_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_data_master_qualified_request_output1_s1;
wire cpu_0_data_master_qualified_request_sdram_0_s1;
wire cpu_0_data_master_qualified_request_sysid_control_slave;
wire cpu_0_data_master_read;
wire cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_data_master_read_data_valid_input1_s1;
wire cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_read_data_valid_nios_system_clock_0_in;
wire cpu_0_data_master_read_data_valid_nios_system_clock_1_in;
wire cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire cpu_0_data_master_read_data_valid_output1_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1;
wire cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register;
wire cpu_0_data_master_read_data_valid_sysid_control_slave;
wire [ 31: 0] cpu_0_data_master_readdata;
wire cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave;
wire cpu_0_data_master_requests_clocks_avalon_clocks_slave;
wire cpu_0_data_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_data_master_requests_input1_s1;
wire cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave;
wire cpu_0_data_master_requests_nios_system_clock_0_in;
wire cpu_0_data_master_requests_nios_system_clock_1_in;
wire cpu_0_data_master_requests_onchip_memory2_0_s1;
wire cpu_0_data_master_requests_output1_s1;
wire cpu_0_data_master_requests_sdram_0_s1;
wire cpu_0_data_master_requests_sysid_control_slave;
wire cpu_0_data_master_waitrequest;
wire cpu_0_data_master_write;
wire [ 31: 0] cpu_0_data_master_writedata;
wire [ 27: 0] cpu_0_instruction_master_address;
wire [ 27: 0] cpu_0_instruction_master_address_to_slave;
wire cpu_0_instruction_master_granted_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_granted_onchip_memory2_0_s1;
wire cpu_0_instruction_master_granted_sdram_0_s1;
wire cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1;
wire cpu_0_instruction_master_qualified_request_sdram_0_s1;
wire cpu_0_instruction_master_read;
wire cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1;
wire cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register;
wire [ 31: 0] cpu_0_instruction_master_readdata;
wire cpu_0_instruction_master_requests_cpu_0_jtag_debug_module;
wire cpu_0_instruction_master_requests_onchip_memory2_0_s1;
wire cpu_0_instruction_master_requests_sdram_0_s1;
wire cpu_0_instruction_master_waitrequest;
wire [ 8: 0] cpu_0_jtag_debug_module_address;
wire cpu_0_jtag_debug_module_begintransfer;
wire [ 3: 0] cpu_0_jtag_debug_module_byteenable;
wire cpu_0_jtag_debug_module_chipselect;
wire cpu_0_jtag_debug_module_debugaccess;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata;
wire [ 31: 0] cpu_0_jtag_debug_module_readdata_from_sa;
wire cpu_0_jtag_debug_module_reset_n;
wire cpu_0_jtag_debug_module_resetrequest;
wire cpu_0_jtag_debug_module_resetrequest_from_sa;
wire cpu_0_jtag_debug_module_write;
wire [ 31: 0] cpu_0_jtag_debug_module_writedata;
wire d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer;
wire d1_clocks_avalon_clocks_slave_end_xfer;
wire d1_cpu_0_jtag_debug_module_end_xfer;
wire d1_input1_s1_end_xfer;
wire d1_jtag_uart_0_avalon_jtag_slave_end_xfer;
wire d1_nios_system_clock_0_in_end_xfer;
wire d1_nios_system_clock_1_in_end_xfer;
wire d1_onchip_memory2_0_s1_end_xfer;
wire d1_output1_s1_end_xfer;
wire d1_sdram_0_s1_end_xfer;
wire d1_sysid_control_slave_end_xfer;
wire d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer;
wire d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer;
wire [ 1: 0] input1_s1_address;
wire [ 31: 0] input1_s1_readdata;
wire [ 31: 0] input1_s1_readdata_from_sa;
wire input1_s1_reset_n;
wire jtag_uart_0_avalon_jtag_slave_address;
wire jtag_uart_0_avalon_jtag_slave_chipselect;
wire jtag_uart_0_avalon_jtag_slave_dataavailable;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_irq;
wire jtag_uart_0_avalon_jtag_slave_irq_from_sa;
wire jtag_uart_0_avalon_jtag_slave_read_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_readdata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
wire jtag_uart_0_avalon_jtag_slave_reset_n;
wire jtag_uart_0_avalon_jtag_slave_waitrequest;
wire jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa;
wire jtag_uart_0_avalon_jtag_slave_write_n;
wire [ 31: 0] jtag_uart_0_avalon_jtag_slave_writedata;
wire [ 2: 0] nios_system_clock_0_in_address;
wire [ 3: 0] nios_system_clock_0_in_byteenable;
wire nios_system_clock_0_in_endofpacket;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_in_nativeaddress;
wire nios_system_clock_0_in_read;
wire [ 31: 0] nios_system_clock_0_in_readdata;
wire [ 31: 0] nios_system_clock_0_in_readdata_from_sa;
wire nios_system_clock_0_in_reset_n;
wire nios_system_clock_0_in_waitrequest;
wire nios_system_clock_0_in_waitrequest_from_sa;
wire nios_system_clock_0_in_write;
wire [ 31: 0] nios_system_clock_0_in_writedata;
wire [ 2: 0] nios_system_clock_0_out_address;
wire [ 2: 0] nios_system_clock_0_out_address_to_slave;
wire [ 3: 0] nios_system_clock_0_out_byteenable;
wire nios_system_clock_0_out_endofpacket;
wire nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_nativeaddress;
wire nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_read;
wire nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire [ 31: 0] nios_system_clock_0_out_readdata;
wire nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave;
wire nios_system_clock_0_out_reset_n;
wire nios_system_clock_0_out_waitrequest;
wire nios_system_clock_0_out_write;
wire [ 31: 0] nios_system_clock_0_out_writedata;
wire [ 12: 0] nios_system_clock_1_in_address;
wire nios_system_clock_1_in_endofpacket;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire [ 12: 0] nios_system_clock_1_in_nativeaddress;
wire nios_system_clock_1_in_read;
wire [ 7: 0] nios_system_clock_1_in_readdata;
wire [ 7: 0] nios_system_clock_1_in_readdata_from_sa;
wire nios_system_clock_1_in_reset_n;
wire nios_system_clock_1_in_waitrequest;
wire nios_system_clock_1_in_waitrequest_from_sa;
wire nios_system_clock_1_in_write;
wire [ 7: 0] nios_system_clock_1_in_writedata;
wire [ 12: 0] nios_system_clock_1_out_address;
wire [ 12: 0] nios_system_clock_1_out_address_to_slave;
wire nios_system_clock_1_out_endofpacket;
wire nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire [ 12: 0] nios_system_clock_1_out_nativeaddress;
wire nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_read;
wire nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire [ 7: 0] nios_system_clock_1_out_readdata;
wire nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave;
wire nios_system_clock_1_out_reset_n;
wire nios_system_clock_1_out_waitrequest;
wire nios_system_clock_1_out_write;
wire [ 7: 0] nios_system_clock_1_out_writedata;
wire o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire [ 11: 0] onchip_memory2_0_s1_address;
wire [ 3: 0] onchip_memory2_0_s1_byteenable;
wire onchip_memory2_0_s1_chipselect;
wire onchip_memory2_0_s1_clken;
wire [ 31: 0] onchip_memory2_0_s1_readdata;
wire [ 31: 0] onchip_memory2_0_s1_readdata_from_sa;
wire onchip_memory2_0_s1_reset;
wire onchip_memory2_0_s1_write;
wire [ 31: 0] onchip_memory2_0_s1_writedata;
wire out_clk_clocks_SDRAM_CLK;
wire out_clk_clocks_sys_clk;
wire [ 7: 0] out_port_from_the_output1;
wire [ 1: 0] output1_s1_address;
wire output1_s1_chipselect;
wire [ 31: 0] output1_s1_readdata;
wire [ 31: 0] output1_s1_readdata_from_sa;
wire output1_s1_reset_n;
wire output1_s1_write_n;
wire [ 31: 0] output1_s1_writedata;
wire registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave;
wire registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1;
wire reset_n_sources;
wire [ 24: 0] sdram_0_s1_address;
wire [ 3: 0] sdram_0_s1_byteenable_n;
wire sdram_0_s1_chipselect;
wire sdram_0_s1_read_n;
wire [ 31: 0] sdram_0_s1_readdata;
wire [ 31: 0] sdram_0_s1_readdata_from_sa;
wire sdram_0_s1_readdatavalid;
wire sdram_0_s1_reset_n;
wire sdram_0_s1_waitrequest;
wire sdram_0_s1_waitrequest_from_sa;
wire sdram_0_s1_write_n;
wire [ 31: 0] sdram_0_s1_writedata;
wire sysid_control_slave_address;
wire sysid_control_slave_clock;
wire [ 31: 0] sysid_control_slave_readdata;
wire [ 31: 0] sysid_control_slave_readdata_from_sa;
wire sysid_control_slave_reset_n;
wire vga_clock_reset_n;
wire [ 12: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_address;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_read;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_buffer_slave_write;
wire [ 7: 0] video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_address;
wire [ 3: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_read;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_reset;
wire video_character_buffer_with_dma_0_avalon_char_control_slave_write;
wire [ 31: 0] video_character_buffer_with_dma_0_avalon_char_control_slave_writedata;
wire [ 29: 0] video_character_buffer_with_dma_0_avalon_char_source_data;
wire video_character_buffer_with_dma_0_avalon_char_source_endofpacket;
wire video_character_buffer_with_dma_0_avalon_char_source_ready;
wire video_character_buffer_with_dma_0_avalon_char_source_startofpacket;
wire video_character_buffer_with_dma_0_avalon_char_source_valid;
wire [ 29: 0] video_vga_controller_0_avalon_vga_sink_data;
wire video_vga_controller_0_avalon_vga_sink_endofpacket;
wire video_vga_controller_0_avalon_vga_sink_ready;
wire video_vga_controller_0_avalon_vga_sink_ready_from_sa;
wire video_vga_controller_0_avalon_vga_sink_reset;
wire video_vga_controller_0_avalon_vga_sink_startofpacket;
wire video_vga_controller_0_avalon_vga_sink_valid;
wire [ 12: 0] zs_addr_from_the_sdram_0;
wire [ 1: 0] zs_ba_from_the_sdram_0;
wire zs_cas_n_from_the_sdram_0;
wire zs_cke_from_the_sdram_0;
wire zs_cs_n_from_the_sdram_0;
wire [ 31: 0] zs_dq_to_and_from_the_sdram_0;
wire [ 3: 0] zs_dqm_from_the_sdram_0;
wire zs_ras_n_from_the_sdram_0;
wire zs_we_n_from_the_sdram_0;
Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_arbitrator the_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave
(
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata),
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer (d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer),
.reset_n (clk_0_reset_n)
);
Altera_UP_SD_Card_Avalon_Interface_0 the_Altera_UP_SD_Card_Avalon_Interface_0
(
.b_SD_cmd (b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat (b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat3 (b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.i_avalon_address (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_address),
.i_avalon_byteenable (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_byteenable),
.i_avalon_chip_select (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_chipselect),
.i_avalon_read (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_read),
.i_avalon_write (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_write),
.i_avalon_writedata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_writedata),
.i_clock (clk_0),
.i_reset_n (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_reset_n),
.o_SD_clock (o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.o_avalon_readdata (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata),
.o_avalon_waitrequest (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest)
);
clocks_avalon_clocks_slave_arbitrator the_clocks_avalon_clocks_slave
(
.clk (clk_0),
.clocks_avalon_clocks_slave_address (clocks_avalon_clocks_slave_address),
.clocks_avalon_clocks_slave_readdata (clocks_avalon_clocks_slave_readdata),
.clocks_avalon_clocks_slave_readdata_from_sa (clocks_avalon_clocks_slave_readdata_from_sa),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_granted_clocks_avalon_clocks_slave (cpu_0_data_master_granted_clocks_avalon_clocks_slave),
.cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave (cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.cpu_0_data_master_requests_clocks_avalon_clocks_slave (cpu_0_data_master_requests_clocks_avalon_clocks_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_clocks_avalon_clocks_slave_end_xfer (d1_clocks_avalon_clocks_slave_end_xfer),
.registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.reset_n (clk_0_reset_n)
);
//clocks_SDRAM_CLK_out out_clk assignment, which is an e_assign
assign clocks_SDRAM_CLK_out = out_clk_clocks_SDRAM_CLK;
//clocks_sys_clk_out out_clk assignment, which is an e_assign
assign clocks_sys_clk_out = out_clk_clocks_sys_clk;
clocks the_clocks
(
.CLOCK_50 (clk_0),
.SDRAM_CLK (out_clk_clocks_SDRAM_CLK),
.address (clocks_avalon_clocks_slave_address),
.readdata (clocks_avalon_clocks_slave_readdata),
.sys_clk (out_clk_clocks_sys_clk)
);
cpu_0_jtag_debug_module_arbitrator the_cpu_0_jtag_debug_module
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_debugaccess (cpu_0_data_master_debugaccess),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.cpu_0_jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.cpu_0_jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.cpu_0_jtag_debug_module_chipselect (cpu_0_jtag_debug_module_chipselect),
.cpu_0_jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.cpu_0_jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.cpu_0_jtag_debug_module_reset_n (cpu_0_jtag_debug_module_reset_n),
.cpu_0_jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.cpu_0_jtag_debug_module_resetrequest_from_sa (cpu_0_jtag_debug_module_resetrequest_from_sa),
.cpu_0_jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.cpu_0_jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.reset_n (clk_0_reset_n)
);
cpu_0_data_master_arbitrator the_cpu_0_data_master
(
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_readdata_from_sa),
.Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa (Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_waitrequest_from_sa),
.clk (clk_0),
.clocks_avalon_clocks_slave_readdata_from_sa (clocks_avalon_clocks_slave_readdata_from_sa),
.cpu_0_data_master_address (cpu_0_data_master_address),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable_nios_system_clock_1_in (cpu_0_data_master_byteenable_nios_system_clock_1_in),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_granted_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_granted_clocks_avalon_clocks_slave (cpu_0_data_master_granted_clocks_avalon_clocks_slave),
.cpu_0_data_master_granted_cpu_0_jtag_debug_module (cpu_0_data_master_granted_cpu_0_jtag_debug_module),
.cpu_0_data_master_granted_input1_s1 (cpu_0_data_master_granted_input1_s1),
.cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_granted_nios_system_clock_0_in (cpu_0_data_master_granted_nios_system_clock_0_in),
.cpu_0_data_master_granted_nios_system_clock_1_in (cpu_0_data_master_granted_nios_system_clock_1_in),
.cpu_0_data_master_granted_onchip_memory2_0_s1 (cpu_0_data_master_granted_onchip_memory2_0_s1),
.cpu_0_data_master_granted_output1_s1 (cpu_0_data_master_granted_output1_s1),
.cpu_0_data_master_granted_sdram_0_s1 (cpu_0_data_master_granted_sdram_0_s1),
.cpu_0_data_master_granted_sysid_control_slave (cpu_0_data_master_granted_sysid_control_slave),
.cpu_0_data_master_irq (cpu_0_data_master_irq),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_qualified_request_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave (cpu_0_data_master_qualified_request_clocks_avalon_clocks_slave),
.cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_data_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_data_master_qualified_request_input1_s1 (cpu_0_data_master_qualified_request_input1_s1),
.cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_nios_system_clock_0_in (cpu_0_data_master_qualified_request_nios_system_clock_0_in),
.cpu_0_data_master_qualified_request_nios_system_clock_1_in (cpu_0_data_master_qualified_request_nios_system_clock_1_in),
.cpu_0_data_master_qualified_request_onchip_memory2_0_s1 (cpu_0_data_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_data_master_qualified_request_output1_s1 (cpu_0_data_master_qualified_request_output1_s1),
.cpu_0_data_master_qualified_request_sdram_0_s1 (cpu_0_data_master_qualified_request_sdram_0_s1),
.cpu_0_data_master_qualified_request_sysid_control_slave (cpu_0_data_master_qualified_request_sysid_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_read_data_valid_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_data_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_data_master_read_data_valid_input1_s1 (cpu_0_data_master_read_data_valid_input1_s1),
.cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_read_data_valid_nios_system_clock_0_in (cpu_0_data_master_read_data_valid_nios_system_clock_0_in),
.cpu_0_data_master_read_data_valid_nios_system_clock_1_in (cpu_0_data_master_read_data_valid_nios_system_clock_1_in),
.cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_data_master_read_data_valid_output1_s1 (cpu_0_data_master_read_data_valid_output1_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1 (cpu_0_data_master_read_data_valid_sdram_0_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_data_master_read_data_valid_sysid_control_slave (cpu_0_data_master_read_data_valid_sysid_control_slave),
.cpu_0_data_master_readdata (cpu_0_data_master_readdata),
.cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave (cpu_0_data_master_requests_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave),
.cpu_0_data_master_requests_clocks_avalon_clocks_slave (cpu_0_data_master_requests_clocks_avalon_clocks_slave),
.cpu_0_data_master_requests_cpu_0_jtag_debug_module (cpu_0_data_master_requests_cpu_0_jtag_debug_module),
.cpu_0_data_master_requests_input1_s1 (cpu_0_data_master_requests_input1_s1),
.cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_requests_nios_system_clock_0_in (cpu_0_data_master_requests_nios_system_clock_0_in),
.cpu_0_data_master_requests_nios_system_clock_1_in (cpu_0_data_master_requests_nios_system_clock_1_in),
.cpu_0_data_master_requests_onchip_memory2_0_s1 (cpu_0_data_master_requests_onchip_memory2_0_s1),
.cpu_0_data_master_requests_output1_s1 (cpu_0_data_master_requests_output1_s1),
.cpu_0_data_master_requests_sdram_0_s1 (cpu_0_data_master_requests_sdram_0_s1),
.cpu_0_data_master_requests_sysid_control_slave (cpu_0_data_master_requests_sysid_control_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer (d1_Altera_UP_SD_Card_Avalon_Interface_0_avalon_sdcard_slave_end_xfer),
.d1_clocks_avalon_clocks_slave_end_xfer (d1_clocks_avalon_clocks_slave_end_xfer),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_input1_s1_end_xfer (d1_input1_s1_end_xfer),
.d1_jtag_uart_0_avalon_jtag_slave_end_xfer (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
.d1_nios_system_clock_0_in_end_xfer (d1_nios_system_clock_0_in_end_xfer),
.d1_nios_system_clock_1_in_end_xfer (d1_nios_system_clock_1_in_end_xfer),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.d1_output1_s1_end_xfer (d1_output1_s1_end_xfer),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.d1_sysid_control_slave_end_xfer (d1_sysid_control_slave_end_xfer),
.input1_s1_readdata_from_sa (input1_s1_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_irq_from_sa (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
.jtag_uart_0_avalon_jtag_slave_readdata_from_sa (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
.nios_system_clock_0_in_readdata_from_sa (nios_system_clock_0_in_readdata_from_sa),
.nios_system_clock_0_in_waitrequest_from_sa (nios_system_clock_0_in_waitrequest_from_sa),
.nios_system_clock_1_in_readdata_from_sa (nios_system_clock_1_in_readdata_from_sa),
.nios_system_clock_1_in_waitrequest_from_sa (nios_system_clock_1_in_waitrequest_from_sa),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.output1_s1_readdata_from_sa (output1_s1_readdata_from_sa),
.registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave (registered_cpu_0_data_master_read_data_valid_clocks_avalon_clocks_slave),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.reset_n (clk_0_reset_n),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa),
.sysid_control_slave_readdata_from_sa (sysid_control_slave_readdata_from_sa)
);
cpu_0_instruction_master_arbitrator the_cpu_0_instruction_master
(
.clk (clk_0),
.cpu_0_instruction_master_address (cpu_0_instruction_master_address),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_cpu_0_jtag_debug_module (cpu_0_instruction_master_granted_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_granted_onchip_memory2_0_s1 (cpu_0_instruction_master_granted_onchip_memory2_0_s1),
.cpu_0_instruction_master_granted_sdram_0_s1 (cpu_0_instruction_master_granted_sdram_0_s1),
.cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module (cpu_0_instruction_master_qualified_request_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_instruction_master_qualified_request_sdram_0_s1 (cpu_0_instruction_master_qualified_request_sdram_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module (cpu_0_instruction_master_read_data_valid_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1 (cpu_0_instruction_master_read_data_valid_sdram_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_instruction_master_readdata (cpu_0_instruction_master_readdata),
.cpu_0_instruction_master_requests_cpu_0_jtag_debug_module (cpu_0_instruction_master_requests_cpu_0_jtag_debug_module),
.cpu_0_instruction_master_requests_onchip_memory2_0_s1 (cpu_0_instruction_master_requests_onchip_memory2_0_s1),
.cpu_0_instruction_master_requests_sdram_0_s1 (cpu_0_instruction_master_requests_sdram_0_s1),
.cpu_0_instruction_master_waitrequest (cpu_0_instruction_master_waitrequest),
.cpu_0_jtag_debug_module_readdata_from_sa (cpu_0_jtag_debug_module_readdata_from_sa),
.d1_cpu_0_jtag_debug_module_end_xfer (d1_cpu_0_jtag_debug_module_end_xfer),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.reset_n (clk_0_reset_n),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa)
);
cpu_0 the_cpu_0
(
.clk (clk_0),
.d_address (cpu_0_data_master_address),
.d_byteenable (cpu_0_data_master_byteenable),
.d_irq (cpu_0_data_master_irq),
.d_read (cpu_0_data_master_read),
.d_readdata (cpu_0_data_master_readdata),
.d_waitrequest (cpu_0_data_master_waitrequest),
.d_write (cpu_0_data_master_write),
.d_writedata (cpu_0_data_master_writedata),
.i_address (cpu_0_instruction_master_address),
.i_read (cpu_0_instruction_master_read),
.i_readdata (cpu_0_instruction_master_readdata),
.i_waitrequest (cpu_0_instruction_master_waitrequest),
.jtag_debug_module_address (cpu_0_jtag_debug_module_address),
.jtag_debug_module_begintransfer (cpu_0_jtag_debug_module_begintransfer),
.jtag_debug_module_byteenable (cpu_0_jtag_debug_module_byteenable),
.jtag_debug_module_debugaccess (cpu_0_jtag_debug_module_debugaccess),
.jtag_debug_module_debugaccess_to_roms (cpu_0_data_master_debugaccess),
.jtag_debug_module_readdata (cpu_0_jtag_debug_module_readdata),
.jtag_debug_module_resetrequest (cpu_0_jtag_debug_module_resetrequest),
.jtag_debug_module_select (cpu_0_jtag_debug_module_chipselect),
.jtag_debug_module_write (cpu_0_jtag_debug_module_write),
.jtag_debug_module_writedata (cpu_0_jtag_debug_module_writedata),
.reset_n (cpu_0_jtag_debug_module_reset_n)
);
input1_s1_arbitrator the_input1_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_input1_s1 (cpu_0_data_master_granted_input1_s1),
.cpu_0_data_master_qualified_request_input1_s1 (cpu_0_data_master_qualified_request_input1_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_input1_s1 (cpu_0_data_master_read_data_valid_input1_s1),
.cpu_0_data_master_requests_input1_s1 (cpu_0_data_master_requests_input1_s1),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_input1_s1_end_xfer (d1_input1_s1_end_xfer),
.input1_s1_address (input1_s1_address),
.input1_s1_readdata (input1_s1_readdata),
.input1_s1_readdata_from_sa (input1_s1_readdata_from_sa),
.input1_s1_reset_n (input1_s1_reset_n),
.reset_n (clk_0_reset_n)
);
input1 the_input1
(
.address (input1_s1_address),
.clk (clk_0),
.in_port (in_port_to_the_input1),
.readdata (input1_s1_readdata),
.reset_n (input1_s1_reset_n)
);
jtag_uart_0_avalon_jtag_slave_arbitrator the_jtag_uart_0_avalon_jtag_slave
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_granted_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_qualified_request_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_read_data_valid_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave (cpu_0_data_master_requests_jtag_uart_0_avalon_jtag_slave),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_jtag_uart_0_avalon_jtag_slave_end_xfer (d1_jtag_uart_0_avalon_jtag_slave_end_xfer),
.jtag_uart_0_avalon_jtag_slave_address (jtag_uart_0_avalon_jtag_slave_address),
.jtag_uart_0_avalon_jtag_slave_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect),
.jtag_uart_0_avalon_jtag_slave_dataavailable (jtag_uart_0_avalon_jtag_slave_dataavailable),
.jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa (jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa),
.jtag_uart_0_avalon_jtag_slave_irq (jtag_uart_0_avalon_jtag_slave_irq),
.jtag_uart_0_avalon_jtag_slave_irq_from_sa (jtag_uart_0_avalon_jtag_slave_irq_from_sa),
.jtag_uart_0_avalon_jtag_slave_read_n (jtag_uart_0_avalon_jtag_slave_read_n),
.jtag_uart_0_avalon_jtag_slave_readdata (jtag_uart_0_avalon_jtag_slave_readdata),
.jtag_uart_0_avalon_jtag_slave_readdata_from_sa (jtag_uart_0_avalon_jtag_slave_readdata_from_sa),
.jtag_uart_0_avalon_jtag_slave_readyfordata (jtag_uart_0_avalon_jtag_slave_readyfordata),
.jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa (jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa),
.jtag_uart_0_avalon_jtag_slave_reset_n (jtag_uart_0_avalon_jtag_slave_reset_n),
.jtag_uart_0_avalon_jtag_slave_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest),
.jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa (jtag_uart_0_avalon_jtag_slave_waitrequest_from_sa),
.jtag_uart_0_avalon_jtag_slave_write_n (jtag_uart_0_avalon_jtag_slave_write_n),
.jtag_uart_0_avalon_jtag_slave_writedata (jtag_uart_0_avalon_jtag_slave_writedata),
.reset_n (clk_0_reset_n)
);
jtag_uart_0 the_jtag_uart_0
(
.av_address (jtag_uart_0_avalon_jtag_slave_address),
.av_chipselect (jtag_uart_0_avalon_jtag_slave_chipselect),
.av_irq (jtag_uart_0_avalon_jtag_slave_irq),
.av_read_n (jtag_uart_0_avalon_jtag_slave_read_n),
.av_readdata (jtag_uart_0_avalon_jtag_slave_readdata),
.av_waitrequest (jtag_uart_0_avalon_jtag_slave_waitrequest),
.av_write_n (jtag_uart_0_avalon_jtag_slave_write_n),
.av_writedata (jtag_uart_0_avalon_jtag_slave_writedata),
.clk (clk_0),
.dataavailable (jtag_uart_0_avalon_jtag_slave_dataavailable),
.readyfordata (jtag_uart_0_avalon_jtag_slave_readyfordata),
.rst_n (jtag_uart_0_avalon_jtag_slave_reset_n)
);
nios_system_clock_0_in_arbitrator the_nios_system_clock_0_in
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_nios_system_clock_0_in (cpu_0_data_master_granted_nios_system_clock_0_in),
.cpu_0_data_master_qualified_request_nios_system_clock_0_in (cpu_0_data_master_qualified_request_nios_system_clock_0_in),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_nios_system_clock_0_in (cpu_0_data_master_read_data_valid_nios_system_clock_0_in),
.cpu_0_data_master_requests_nios_system_clock_0_in (cpu_0_data_master_requests_nios_system_clock_0_in),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_nios_system_clock_0_in_end_xfer (d1_nios_system_clock_0_in_end_xfer),
.nios_system_clock_0_in_address (nios_system_clock_0_in_address),
.nios_system_clock_0_in_byteenable (nios_system_clock_0_in_byteenable),
.nios_system_clock_0_in_endofpacket (nios_system_clock_0_in_endofpacket),
.nios_system_clock_0_in_endofpacket_from_sa (nios_system_clock_0_in_endofpacket_from_sa),
.nios_system_clock_0_in_nativeaddress (nios_system_clock_0_in_nativeaddress),
.nios_system_clock_0_in_read (nios_system_clock_0_in_read),
.nios_system_clock_0_in_readdata (nios_system_clock_0_in_readdata),
.nios_system_clock_0_in_readdata_from_sa (nios_system_clock_0_in_readdata_from_sa),
.nios_system_clock_0_in_reset_n (nios_system_clock_0_in_reset_n),
.nios_system_clock_0_in_waitrequest (nios_system_clock_0_in_waitrequest),
.nios_system_clock_0_in_waitrequest_from_sa (nios_system_clock_0_in_waitrequest_from_sa),
.nios_system_clock_0_in_write (nios_system_clock_0_in_write),
.nios_system_clock_0_in_writedata (nios_system_clock_0_in_writedata),
.reset_n (clk_0_reset_n)
);
nios_system_clock_0_out_arbitrator the_nios_system_clock_0_out
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer),
.nios_system_clock_0_out_address (nios_system_clock_0_out_address),
.nios_system_clock_0_out_address_to_slave (nios_system_clock_0_out_address_to_slave),
.nios_system_clock_0_out_byteenable (nios_system_clock_0_out_byteenable),
.nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_read (nios_system_clock_0_out_read),
.nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_readdata (nios_system_clock_0_out_readdata),
.nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_reset_n (nios_system_clock_0_out_reset_n),
.nios_system_clock_0_out_waitrequest (nios_system_clock_0_out_waitrequest),
.nios_system_clock_0_out_write (nios_system_clock_0_out_write),
.nios_system_clock_0_out_writedata (nios_system_clock_0_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa)
);
nios_system_clock_0 the_nios_system_clock_0
(
.master_address (nios_system_clock_0_out_address),
.master_byteenable (nios_system_clock_0_out_byteenable),
.master_clk (vga_clock),
.master_endofpacket (nios_system_clock_0_out_endofpacket),
.master_nativeaddress (nios_system_clock_0_out_nativeaddress),
.master_read (nios_system_clock_0_out_read),
.master_readdata (nios_system_clock_0_out_readdata),
.master_reset_n (nios_system_clock_0_out_reset_n),
.master_waitrequest (nios_system_clock_0_out_waitrequest),
.master_write (nios_system_clock_0_out_write),
.master_writedata (nios_system_clock_0_out_writedata),
.slave_address (nios_system_clock_0_in_address),
.slave_byteenable (nios_system_clock_0_in_byteenable),
.slave_clk (clk_0),
.slave_endofpacket (nios_system_clock_0_in_endofpacket),
.slave_nativeaddress (nios_system_clock_0_in_nativeaddress),
.slave_read (nios_system_clock_0_in_read),
.slave_readdata (nios_system_clock_0_in_readdata),
.slave_reset_n (nios_system_clock_0_in_reset_n),
.slave_waitrequest (nios_system_clock_0_in_waitrequest),
.slave_write (nios_system_clock_0_in_write),
.slave_writedata (nios_system_clock_0_in_writedata)
);
nios_system_clock_1_in_arbitrator the_nios_system_clock_1_in
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_byteenable_nios_system_clock_1_in (cpu_0_data_master_byteenable_nios_system_clock_1_in),
.cpu_0_data_master_dbs_address (cpu_0_data_master_dbs_address),
.cpu_0_data_master_dbs_write_8 (cpu_0_data_master_dbs_write_8),
.cpu_0_data_master_granted_nios_system_clock_1_in (cpu_0_data_master_granted_nios_system_clock_1_in),
.cpu_0_data_master_no_byte_enables_and_last_term (cpu_0_data_master_no_byte_enables_and_last_term),
.cpu_0_data_master_qualified_request_nios_system_clock_1_in (cpu_0_data_master_qualified_request_nios_system_clock_1_in),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_nios_system_clock_1_in (cpu_0_data_master_read_data_valid_nios_system_clock_1_in),
.cpu_0_data_master_requests_nios_system_clock_1_in (cpu_0_data_master_requests_nios_system_clock_1_in),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_nios_system_clock_1_in_end_xfer (d1_nios_system_clock_1_in_end_xfer),
.nios_system_clock_1_in_address (nios_system_clock_1_in_address),
.nios_system_clock_1_in_endofpacket (nios_system_clock_1_in_endofpacket),
.nios_system_clock_1_in_endofpacket_from_sa (nios_system_clock_1_in_endofpacket_from_sa),
.nios_system_clock_1_in_nativeaddress (nios_system_clock_1_in_nativeaddress),
.nios_system_clock_1_in_read (nios_system_clock_1_in_read),
.nios_system_clock_1_in_readdata (nios_system_clock_1_in_readdata),
.nios_system_clock_1_in_readdata_from_sa (nios_system_clock_1_in_readdata_from_sa),
.nios_system_clock_1_in_reset_n (nios_system_clock_1_in_reset_n),
.nios_system_clock_1_in_waitrequest (nios_system_clock_1_in_waitrequest),
.nios_system_clock_1_in_waitrequest_from_sa (nios_system_clock_1_in_waitrequest_from_sa),
.nios_system_clock_1_in_write (nios_system_clock_1_in_write),
.nios_system_clock_1_in_writedata (nios_system_clock_1_in_writedata),
.reset_n (clk_0_reset_n)
);
nios_system_clock_1_out_arbitrator the_nios_system_clock_1_out
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer),
.nios_system_clock_1_out_address (nios_system_clock_1_out_address),
.nios_system_clock_1_out_address_to_slave (nios_system_clock_1_out_address_to_slave),
.nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_read (nios_system_clock_1_out_read),
.nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_readdata (nios_system_clock_1_out_readdata),
.nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_reset_n (nios_system_clock_1_out_reset_n),
.nios_system_clock_1_out_waitrequest (nios_system_clock_1_out_waitrequest),
.nios_system_clock_1_out_write (nios_system_clock_1_out_write),
.nios_system_clock_1_out_writedata (nios_system_clock_1_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa)
);
nios_system_clock_1 the_nios_system_clock_1
(
.master_address (nios_system_clock_1_out_address),
.master_clk (vga_clock),
.master_endofpacket (nios_system_clock_1_out_endofpacket),
.master_nativeaddress (nios_system_clock_1_out_nativeaddress),
.master_read (nios_system_clock_1_out_read),
.master_readdata (nios_system_clock_1_out_readdata),
.master_reset_n (nios_system_clock_1_out_reset_n),
.master_waitrequest (nios_system_clock_1_out_waitrequest),
.master_write (nios_system_clock_1_out_write),
.master_writedata (nios_system_clock_1_out_writedata),
.slave_address (nios_system_clock_1_in_address),
.slave_clk (clk_0),
.slave_endofpacket (nios_system_clock_1_in_endofpacket),
.slave_nativeaddress (nios_system_clock_1_in_nativeaddress),
.slave_read (nios_system_clock_1_in_read),
.slave_readdata (nios_system_clock_1_in_readdata),
.slave_reset_n (nios_system_clock_1_in_reset_n),
.slave_waitrequest (nios_system_clock_1_in_waitrequest),
.slave_write (nios_system_clock_1_in_write),
.slave_writedata (nios_system_clock_1_in_writedata)
);
onchip_memory2_0_s1_arbitrator the_onchip_memory2_0_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_onchip_memory2_0_s1 (cpu_0_data_master_granted_onchip_memory2_0_s1),
.cpu_0_data_master_qualified_request_onchip_memory2_0_s1 (cpu_0_data_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_data_master_requests_onchip_memory2_0_s1 (cpu_0_data_master_requests_onchip_memory2_0_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_onchip_memory2_0_s1 (cpu_0_instruction_master_granted_onchip_memory2_0_s1),
.cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1 (cpu_0_instruction_master_qualified_request_onchip_memory2_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1 (cpu_0_instruction_master_read_data_valid_onchip_memory2_0_s1),
.cpu_0_instruction_master_requests_onchip_memory2_0_s1 (cpu_0_instruction_master_requests_onchip_memory2_0_s1),
.d1_onchip_memory2_0_s1_end_xfer (d1_onchip_memory2_0_s1_end_xfer),
.onchip_memory2_0_s1_address (onchip_memory2_0_s1_address),
.onchip_memory2_0_s1_byteenable (onchip_memory2_0_s1_byteenable),
.onchip_memory2_0_s1_chipselect (onchip_memory2_0_s1_chipselect),
.onchip_memory2_0_s1_clken (onchip_memory2_0_s1_clken),
.onchip_memory2_0_s1_readdata (onchip_memory2_0_s1_readdata),
.onchip_memory2_0_s1_readdata_from_sa (onchip_memory2_0_s1_readdata_from_sa),
.onchip_memory2_0_s1_reset (onchip_memory2_0_s1_reset),
.onchip_memory2_0_s1_write (onchip_memory2_0_s1_write),
.onchip_memory2_0_s1_writedata (onchip_memory2_0_s1_writedata),
.registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1 (registered_cpu_0_data_master_read_data_valid_onchip_memory2_0_s1),
.reset_n (clk_0_reset_n)
);
onchip_memory2_0 the_onchip_memory2_0
(
.address (onchip_memory2_0_s1_address),
.byteenable (onchip_memory2_0_s1_byteenable),
.chipselect (onchip_memory2_0_s1_chipselect),
.clk (clk_0),
.clken (onchip_memory2_0_s1_clken),
.readdata (onchip_memory2_0_s1_readdata),
.reset (onchip_memory2_0_s1_reset),
.write (onchip_memory2_0_s1_write),
.writedata (onchip_memory2_0_s1_writedata)
);
output1_s1_arbitrator the_output1_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_output1_s1 (cpu_0_data_master_granted_output1_s1),
.cpu_0_data_master_qualified_request_output1_s1 (cpu_0_data_master_qualified_request_output1_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_output1_s1 (cpu_0_data_master_read_data_valid_output1_s1),
.cpu_0_data_master_requests_output1_s1 (cpu_0_data_master_requests_output1_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.d1_output1_s1_end_xfer (d1_output1_s1_end_xfer),
.output1_s1_address (output1_s1_address),
.output1_s1_chipselect (output1_s1_chipselect),
.output1_s1_readdata (output1_s1_readdata),
.output1_s1_readdata_from_sa (output1_s1_readdata_from_sa),
.output1_s1_reset_n (output1_s1_reset_n),
.output1_s1_write_n (output1_s1_write_n),
.output1_s1_writedata (output1_s1_writedata),
.reset_n (clk_0_reset_n)
);
output1 the_output1
(
.address (output1_s1_address),
.chipselect (output1_s1_chipselect),
.clk (clk_0),
.out_port (out_port_from_the_output1),
.readdata (output1_s1_readdata),
.reset_n (output1_s1_reset_n),
.write_n (output1_s1_write_n),
.writedata (output1_s1_writedata)
);
sdram_0_s1_arbitrator the_sdram_0_s1
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_byteenable (cpu_0_data_master_byteenable),
.cpu_0_data_master_granted_sdram_0_s1 (cpu_0_data_master_granted_sdram_0_s1),
.cpu_0_data_master_qualified_request_sdram_0_s1 (cpu_0_data_master_qualified_request_sdram_0_s1),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sdram_0_s1 (cpu_0_data_master_read_data_valid_sdram_0_s1),
.cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_data_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_data_master_requests_sdram_0_s1 (cpu_0_data_master_requests_sdram_0_s1),
.cpu_0_data_master_waitrequest (cpu_0_data_master_waitrequest),
.cpu_0_data_master_write (cpu_0_data_master_write),
.cpu_0_data_master_writedata (cpu_0_data_master_writedata),
.cpu_0_instruction_master_address_to_slave (cpu_0_instruction_master_address_to_slave),
.cpu_0_instruction_master_granted_sdram_0_s1 (cpu_0_instruction_master_granted_sdram_0_s1),
.cpu_0_instruction_master_qualified_request_sdram_0_s1 (cpu_0_instruction_master_qualified_request_sdram_0_s1),
.cpu_0_instruction_master_read (cpu_0_instruction_master_read),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1 (cpu_0_instruction_master_read_data_valid_sdram_0_s1),
.cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register (cpu_0_instruction_master_read_data_valid_sdram_0_s1_shift_register),
.cpu_0_instruction_master_requests_sdram_0_s1 (cpu_0_instruction_master_requests_sdram_0_s1),
.d1_sdram_0_s1_end_xfer (d1_sdram_0_s1_end_xfer),
.reset_n (clk_0_reset_n),
.sdram_0_s1_address (sdram_0_s1_address),
.sdram_0_s1_byteenable_n (sdram_0_s1_byteenable_n),
.sdram_0_s1_chipselect (sdram_0_s1_chipselect),
.sdram_0_s1_read_n (sdram_0_s1_read_n),
.sdram_0_s1_readdata (sdram_0_s1_readdata),
.sdram_0_s1_readdata_from_sa (sdram_0_s1_readdata_from_sa),
.sdram_0_s1_readdatavalid (sdram_0_s1_readdatavalid),
.sdram_0_s1_reset_n (sdram_0_s1_reset_n),
.sdram_0_s1_waitrequest (sdram_0_s1_waitrequest),
.sdram_0_s1_waitrequest_from_sa (sdram_0_s1_waitrequest_from_sa),
.sdram_0_s1_write_n (sdram_0_s1_write_n),
.sdram_0_s1_writedata (sdram_0_s1_writedata)
);
sdram_0 the_sdram_0
(
.az_addr (sdram_0_s1_address),
.az_be_n (sdram_0_s1_byteenable_n),
.az_cs (sdram_0_s1_chipselect),
.az_data (sdram_0_s1_writedata),
.az_rd_n (sdram_0_s1_read_n),
.az_wr_n (sdram_0_s1_write_n),
.clk (clk_0),
.reset_n (sdram_0_s1_reset_n),
.za_data (sdram_0_s1_readdata),
.za_valid (sdram_0_s1_readdatavalid),
.za_waitrequest (sdram_0_s1_waitrequest),
.zs_addr (zs_addr_from_the_sdram_0),
.zs_ba (zs_ba_from_the_sdram_0),
.zs_cas_n (zs_cas_n_from_the_sdram_0),
.zs_cke (zs_cke_from_the_sdram_0),
.zs_cs_n (zs_cs_n_from_the_sdram_0),
.zs_dq (zs_dq_to_and_from_the_sdram_0),
.zs_dqm (zs_dqm_from_the_sdram_0),
.zs_ras_n (zs_ras_n_from_the_sdram_0),
.zs_we_n (zs_we_n_from_the_sdram_0)
);
sysid_control_slave_arbitrator the_sysid_control_slave
(
.clk (clk_0),
.cpu_0_data_master_address_to_slave (cpu_0_data_master_address_to_slave),
.cpu_0_data_master_granted_sysid_control_slave (cpu_0_data_master_granted_sysid_control_slave),
.cpu_0_data_master_qualified_request_sysid_control_slave (cpu_0_data_master_qualified_request_sysid_control_slave),
.cpu_0_data_master_read (cpu_0_data_master_read),
.cpu_0_data_master_read_data_valid_sysid_control_slave (cpu_0_data_master_read_data_valid_sysid_control_slave),
.cpu_0_data_master_requests_sysid_control_slave (cpu_0_data_master_requests_sysid_control_slave),
.cpu_0_data_master_write (cpu_0_data_master_write),
.d1_sysid_control_slave_end_xfer (d1_sysid_control_slave_end_xfer),
.reset_n (clk_0_reset_n),
.sysid_control_slave_address (sysid_control_slave_address),
.sysid_control_slave_readdata (sysid_control_slave_readdata),
.sysid_control_slave_readdata_from_sa (sysid_control_slave_readdata_from_sa),
.sysid_control_slave_reset_n (sysid_control_slave_reset_n)
);
sysid the_sysid
(
.address (sysid_control_slave_address),
.clock (sysid_control_slave_clock),
.readdata (sysid_control_slave_readdata),
.reset_n (sysid_control_slave_reset_n)
);
video_character_buffer_with_dma_0_avalon_char_buffer_slave_arbitrator the_video_character_buffer_with_dma_0_avalon_char_buffer_slave
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_buffer_slave_end_xfer),
.nios_system_clock_1_out_address_to_slave (nios_system_clock_1_out_address_to_slave),
.nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_granted_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_read (nios_system_clock_1_out_read),
.nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave (nios_system_clock_1_out_requests_video_character_buffer_with_dma_0_avalon_char_buffer_slave),
.nios_system_clock_1_out_write (nios_system_clock_1_out_write),
.nios_system_clock_1_out_writedata (nios_system_clock_1_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_address (video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable (video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect (video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_read (video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest_from_sa),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_write (video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
.video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata)
);
video_character_buffer_with_dma_0_avalon_char_control_slave_arbitrator the_video_character_buffer_with_dma_0_avalon_char_control_slave
(
.clk (vga_clock),
.d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer (d1_video_character_buffer_with_dma_0_avalon_char_control_slave_end_xfer),
.nios_system_clock_0_out_address_to_slave (nios_system_clock_0_out_address_to_slave),
.nios_system_clock_0_out_byteenable (nios_system_clock_0_out_byteenable),
.nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_granted_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_qualified_request_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_read (nios_system_clock_0_out_read),
.nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_read_data_valid_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave (nios_system_clock_0_out_requests_video_character_buffer_with_dma_0_avalon_char_control_slave),
.nios_system_clock_0_out_write (nios_system_clock_0_out_write),
.nios_system_clock_0_out_writedata (nios_system_clock_0_out_writedata),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_control_slave_address (video_character_buffer_with_dma_0_avalon_char_control_slave_address),
.video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable (video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
.video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect (video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect),
.video_character_buffer_with_dma_0_avalon_char_control_slave_read (video_character_buffer_with_dma_0_avalon_char_control_slave_read),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
.video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata_from_sa),
.video_character_buffer_with_dma_0_avalon_char_control_slave_reset (video_character_buffer_with_dma_0_avalon_char_control_slave_reset),
.video_character_buffer_with_dma_0_avalon_char_control_slave_write (video_character_buffer_with_dma_0_avalon_char_control_slave_write),
.video_character_buffer_with_dma_0_avalon_char_control_slave_writedata (video_character_buffer_with_dma_0_avalon_char_control_slave_writedata)
);
video_character_buffer_with_dma_0_avalon_char_source_arbitrator the_video_character_buffer_with_dma_0_avalon_char_source
(
.clk (vga_clock),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_source_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.video_character_buffer_with_dma_0_avalon_char_source_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_ready (video_character_buffer_with_dma_0_avalon_char_source_ready),
.video_character_buffer_with_dma_0_avalon_char_source_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_valid (video_character_buffer_with_dma_0_avalon_char_source_valid),
.video_vga_controller_0_avalon_vga_sink_ready_from_sa (video_vga_controller_0_avalon_vga_sink_ready_from_sa)
);
video_character_buffer_with_dma_0 the_video_character_buffer_with_dma_0
(
.buf_address (video_character_buffer_with_dma_0_avalon_char_buffer_slave_address),
.buf_byteenable (video_character_buffer_with_dma_0_avalon_char_buffer_slave_byteenable),
.buf_chipselect (video_character_buffer_with_dma_0_avalon_char_buffer_slave_chipselect),
.buf_read (video_character_buffer_with_dma_0_avalon_char_buffer_slave_read),
.buf_readdata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_readdata),
.buf_waitrequest (video_character_buffer_with_dma_0_avalon_char_buffer_slave_waitrequest),
.buf_write (video_character_buffer_with_dma_0_avalon_char_buffer_slave_write),
.buf_writedata (video_character_buffer_with_dma_0_avalon_char_buffer_slave_writedata),
.clk (vga_clock),
.ctrl_address (video_character_buffer_with_dma_0_avalon_char_control_slave_address),
.ctrl_byteenable (video_character_buffer_with_dma_0_avalon_char_control_slave_byteenable),
.ctrl_chipselect (video_character_buffer_with_dma_0_avalon_char_control_slave_chipselect),
.ctrl_read (video_character_buffer_with_dma_0_avalon_char_control_slave_read),
.ctrl_readdata (video_character_buffer_with_dma_0_avalon_char_control_slave_readdata),
.ctrl_write (video_character_buffer_with_dma_0_avalon_char_control_slave_write),
.ctrl_writedata (video_character_buffer_with_dma_0_avalon_char_control_slave_writedata),
.reset (video_character_buffer_with_dma_0_avalon_char_control_slave_reset),
.stream_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.stream_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.stream_ready (video_character_buffer_with_dma_0_avalon_char_source_ready),
.stream_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.stream_valid (video_character_buffer_with_dma_0_avalon_char_source_valid)
);
video_vga_controller_0_avalon_vga_sink_arbitrator the_video_vga_controller_0_avalon_vga_sink
(
.clk (vga_clock),
.reset_n (vga_clock_reset_n),
.video_character_buffer_with_dma_0_avalon_char_source_data (video_character_buffer_with_dma_0_avalon_char_source_data),
.video_character_buffer_with_dma_0_avalon_char_source_endofpacket (video_character_buffer_with_dma_0_avalon_char_source_endofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_startofpacket (video_character_buffer_with_dma_0_avalon_char_source_startofpacket),
.video_character_buffer_with_dma_0_avalon_char_source_valid (video_character_buffer_with_dma_0_avalon_char_source_valid),
.video_vga_controller_0_avalon_vga_sink_data (video_vga_controller_0_avalon_vga_sink_data),
.video_vga_controller_0_avalon_vga_sink_endofpacket (video_vga_controller_0_avalon_vga_sink_endofpacket),
.video_vga_controller_0_avalon_vga_sink_ready (video_vga_controller_0_avalon_vga_sink_ready),
.video_vga_controller_0_avalon_vga_sink_ready_from_sa (video_vga_controller_0_avalon_vga_sink_ready_from_sa),
.video_vga_controller_0_avalon_vga_sink_reset (video_vga_controller_0_avalon_vga_sink_reset),
.video_vga_controller_0_avalon_vga_sink_startofpacket (video_vga_controller_0_avalon_vga_sink_startofpacket),
.video_vga_controller_0_avalon_vga_sink_valid (video_vga_controller_0_avalon_vga_sink_valid)
);
video_vga_controller_0 the_video_vga_controller_0
(
.VGA_B (VGA_B_from_the_video_vga_controller_0),
.VGA_BLANK (VGA_BLANK_from_the_video_vga_controller_0),
.VGA_CLK (VGA_CLK_from_the_video_vga_controller_0),
.VGA_G (VGA_G_from_the_video_vga_controller_0),
.VGA_HS (VGA_HS_from_the_video_vga_controller_0),
.VGA_R (VGA_R_from_the_video_vga_controller_0),
.VGA_SYNC (VGA_SYNC_from_the_video_vga_controller_0),
.VGA_VS (VGA_VS_from_the_video_vga_controller_0),
.clk (vga_clock),
.data (video_vga_controller_0_avalon_vga_sink_data),
.endofpacket (video_vga_controller_0_avalon_vga_sink_endofpacket),
.ready (video_vga_controller_0_avalon_vga_sink_ready),
.reset (video_vga_controller_0_avalon_vga_sink_reset),
.startofpacket (video_vga_controller_0_avalon_vga_sink_startofpacket),
.valid (video_vga_controller_0_avalon_vga_sink_valid)
);
//reset is asserted asynchronously and deasserted synchronously
nios_system_reset_clk_0_domain_synch_module nios_system_reset_clk_0_domain_synch
(
.clk (clk_0),
.data_in (1'b1),
.data_out (clk_0_reset_n),
.reset_n (reset_n_sources)
);
//reset sources mux, which is an e_mux
assign reset_n_sources = ~(~reset_n |
0 |
cpu_0_jtag_debug_module_resetrequest_from_sa |
cpu_0_jtag_debug_module_resetrequest_from_sa |
0);
//reset is asserted asynchronously and deasserted synchronously
nios_system_reset_vga_clock_domain_synch_module nios_system_reset_vga_clock_domain_synch
(
.clk (vga_clock),
.data_in (1'b1),
.data_out (vga_clock_reset_n),
.reset_n (reset_n_sources)
);
//nios_system_clock_0_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
assign nios_system_clock_0_out_endofpacket = 0;
//nios_system_clock_1_out_endofpacket of type endofpacket does not connect to anything so wire it to default (0)
assign nios_system_clock_1_out_endofpacket = 0;
//sysid_control_slave_clock of type clock does not connect to anything so wire it to default (0)
assign sysid_control_slave_clock = 0;
endmodule
//synthesis translate_off
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above
// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif
`include "c:/altera/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/quartus/eda/sim_lib/220model.v"
`include "c:/altera/quartus/eda/sim_lib/sgate.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_vga_controller/hdl/altera_up_avalon_video_vga_timing.v"
`include "video_vga_controller_0.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_character_buffer_with_dma/hdl/altera_up_video_128_character_rom.v"
`include "C:/altera/ip/University_Program/Audio_Video/Video/altera_up_avalon_video_character_buffer_with_dma/hdl/altera_up_video_fb_color_rom.v"
`include "video_character_buffer_with_dma_0.v"
`include "clocks.v"
// Altera_UP_SD_Card_Avalon_Interface_0.vhd
`include "sdram_0.v"
`include "nios_system_clock_1.v"
`include "sysid.v"
`include "cpu_0_test_bench.v"
`include "cpu_0_oci_test_bench.v"
`include "cpu_0_jtag_debug_module_tck.v"
`include "cpu_0_jtag_debug_module_sysclk.v"
`include "cpu_0_jtag_debug_module_wrapper.v"
`include "cpu_0.v"
`include "output1.v"
`include "input1.v"
`include "jtag_uart_0.v"
`include "onchip_memory2_0.v"
`include "nios_system_clock_0.v"
`timescale 1ns / 1ps
module test_bench
;
wire VGA_BLANK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_B_from_the_video_vga_controller_0;
wire VGA_CLK_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_G_from_the_video_vga_controller_0;
wire VGA_HS_from_the_video_vga_controller_0;
wire [ 7: 0] VGA_R_from_the_video_vga_controller_0;
wire VGA_SYNC_from_the_video_vga_controller_0;
wire VGA_VS_from_the_video_vga_controller_0;
wire b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire clk;
reg clk_0;
wire clocks_SDRAM_CLK_out;
wire clocks_sys_clk_out;
wire [ 7: 0] in_port_to_the_input1;
wire jtag_uart_0_avalon_jtag_slave_dataavailable_from_sa;
wire jtag_uart_0_avalon_jtag_slave_readyfordata_from_sa;
wire nios_system_clock_0_in_endofpacket_from_sa;
wire nios_system_clock_0_out_endofpacket;
wire nios_system_clock_0_out_nativeaddress;
wire nios_system_clock_1_in_endofpacket_from_sa;
wire nios_system_clock_1_out_endofpacket;
wire [ 12: 0] nios_system_clock_1_out_nativeaddress;
wire o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0;
wire [ 7: 0] out_port_from_the_output1;
reg reset_n;
wire sysid_control_slave_clock;
reg vga_clock;
wire [ 12: 0] zs_addr_from_the_sdram_0;
wire [ 1: 0] zs_ba_from_the_sdram_0;
wire zs_cas_n_from_the_sdram_0;
wire zs_cke_from_the_sdram_0;
wire zs_cs_n_from_the_sdram_0;
wire [ 31: 0] zs_dq_to_and_from_the_sdram_0;
wire [ 3: 0] zs_dqm_from_the_sdram_0;
wire zs_ras_n_from_the_sdram_0;
wire zs_we_n_from_the_sdram_0;
// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
// add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>
//Set us up the Dut
nios_system DUT
(
.VGA_BLANK_from_the_video_vga_controller_0 (VGA_BLANK_from_the_video_vga_controller_0),
.VGA_B_from_the_video_vga_controller_0 (VGA_B_from_the_video_vga_controller_0),
.VGA_CLK_from_the_video_vga_controller_0 (VGA_CLK_from_the_video_vga_controller_0),
.VGA_G_from_the_video_vga_controller_0 (VGA_G_from_the_video_vga_controller_0),
.VGA_HS_from_the_video_vga_controller_0 (VGA_HS_from_the_video_vga_controller_0),
.VGA_R_from_the_video_vga_controller_0 (VGA_R_from_the_video_vga_controller_0),
.VGA_SYNC_from_the_video_vga_controller_0 (VGA_SYNC_from_the_video_vga_controller_0),
.VGA_VS_from_the_video_vga_controller_0 (VGA_VS_from_the_video_vga_controller_0),
.b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_cmd_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_dat3_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (b_SD_dat_to_and_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.clk_0 (clk_0),
.clocks_SDRAM_CLK_out (clocks_SDRAM_CLK_out),
.clocks_sys_clk_out (clocks_sys_clk_out),
.in_port_to_the_input1 (in_port_to_the_input1),
.o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0 (o_SD_clock_from_the_Altera_UP_SD_Card_Avalon_Interface_0),
.out_port_from_the_output1 (out_port_from_the_output1),
.reset_n (reset_n),
.vga_clock (vga_clock),
.zs_addr_from_the_sdram_0 (zs_addr_from_the_sdram_0),
.zs_ba_from_the_sdram_0 (zs_ba_from_the_sdram_0),
.zs_cas_n_from_the_sdram_0 (zs_cas_n_from_the_sdram_0),
.zs_cke_from_the_sdram_0 (zs_cke_from_the_sdram_0),
.zs_cs_n_from_the_sdram_0 (zs_cs_n_from_the_sdram_0),
.zs_dq_to_and_from_the_sdram_0 (zs_dq_to_and_from_the_sdram_0),
.zs_dqm_from_the_sdram_0 (zs_dqm_from_the_sdram_0),
.zs_ras_n_from_the_sdram_0 (zs_ras_n_from_the_sdram_0),
.zs_we_n_from_the_sdram_0 (zs_we_n_from_the_sdram_0)
);
initial
clk_0 = 1'b0;
always
#10 clk_0 <= ~clk_0;
initial
begin
reset_n <= 0;
#200 reset_n <= 1;
end
initial
vga_clock = 1'b0;
always
#20 vga_clock <= ~vga_clock;
endmodule
//synthesis translate_on |
/*
* In The Name Of God
* ========================================
* [] File Name : cache.v
*
* [] Creation Date : 04-03-2015
*
* [] Last Modified : Wed 01 Apr 2015 09:12:09 AM IRDT
*
* [] Created By : Parham Alvani ([email protected])
* =======================================
*/
module cache (enable, index, word, comp,
write, tag_in, data_in, valid_in,
rst, hit, dirty, tag_out,
data_out, valid, ack);
parameter N = 15;
reg [0:3] counter;
input enable;
input [0:3] index;
input [0:1] word;
input comp;
input write;
input [0:4] tag_in;
input [0:15] data_in;
input valid_in;
input rst;
output reg hit;
output reg dirty;
output reg [0:4] tag_out;
output reg [0:15] data_out;
output reg valid;
output reg ack;
reg set_en [0:N];
reg [0:1] set_word [0:N];
reg set_cmp [0:N];
reg set_wr [0:N];
reg [0:4] set_tag_in [0:N];
reg [0:15] set_in [0:N];
reg set_valid_in [0:N];
reg set_rst [0:N];
wire set_hit [0:N];
wire set_dirty_out [0:N];
wire [0:4] set_tag_out [0:N];
wire [0:15] set_out [0:N];
wire set_valid_out [0:N];
wire set_ack [0:N];
generate
genvar i;
for (i = 0; i < N; i = i + 1) begin
set set_ins(set_en[i], set_word[i], set_cmp[i], set_wr[i], set_rst[i],
set_tag_in[i], set_in[i], set_valid_in[i], set_hit[i], set_dirty_out[i],
set_tag_out[i], set_out[i], set_valid_out[i], set_ack[i]);
end
endgenerate
always @ (enable) begin
ack = 1'b0;
if (enable) begin
if (rst) begin
for (counter = 0; counter < N; counter = counter + 1) begin
set_en[counter] = 1'b1;
set_rst[counter] = 1'b1;
wait (set_ack[counter]) begin
set_en[counter] = 1'b0;
set_rst[counter] = 1'b0;
end
end
ack = 1'b1;
end else begin
set_word[index] = word;
set_cmp[index] = comp;
set_wr[index] = write;
set_tag_in[index] = tag_in;
set_in[index] = data_in;
set_valid_in[index] = valid_in;
set_en[index] = 1'b1;
wait (set_ack[index]) begin
hit = set_hit[index];
dirty = set_dirty_out[index];
tag_out = set_tag_out[index];
valid = set_valid_out[index];
data_out = set_out[index];
end
ack = 1'b1;
end
end else begin
set_en[index] = 1'b0;
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__NAND3B_TB_V
`define SKY130_FD_SC_MS__NAND3B_TB_V
/**
* nand3b: 3-input NAND, first input inverted.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ms__nand3b.v"
module top();
// Inputs are registered
reg A_N;
reg B;
reg C;
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
wire Y;
initial
begin
// Initial state is x for all inputs.
A_N = 1'bX;
B = 1'bX;
C = 1'bX;
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 A_N = 1'b0;
#40 B = 1'b0;
#60 C = 1'b0;
#80 VGND = 1'b0;
#100 VNB = 1'b0;
#120 VPB = 1'b0;
#140 VPWR = 1'b0;
#160 A_N = 1'b1;
#180 B = 1'b1;
#200 C = 1'b1;
#220 VGND = 1'b1;
#240 VNB = 1'b1;
#260 VPB = 1'b1;
#280 VPWR = 1'b1;
#300 A_N = 1'b0;
#320 B = 1'b0;
#340 C = 1'b0;
#360 VGND = 1'b0;
#380 VNB = 1'b0;
#400 VPB = 1'b0;
#420 VPWR = 1'b0;
#440 VPWR = 1'b1;
#460 VPB = 1'b1;
#480 VNB = 1'b1;
#500 VGND = 1'b1;
#520 C = 1'b1;
#540 B = 1'b1;
#560 A_N = 1'b1;
#580 VPWR = 1'bx;
#600 VPB = 1'bx;
#620 VNB = 1'bx;
#640 VGND = 1'bx;
#660 C = 1'bx;
#680 B = 1'bx;
#700 A_N = 1'bx;
end
sky130_fd_sc_ms__nand3b dut (.A_N(A_N), .B(B), .C(C), .VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB), .Y(Y));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_MS__NAND3B_TB_V
|
module branch_wait
(/*AUTOARG*/
// Outputs
pending_branches_arry,
// Inputs
clk, rst, alu_valid, alu_branch, alu_wfid, f_salu_branch_en,
f_salu_branch_wfid
);
input clk, rst;
// Issued alu info
input alu_valid, alu_branch;
input [`WF_ID_LENGTH-1:0] alu_wfid;
// Salu signals with outcome of branch
input f_salu_branch_en;
input [`WF_ID_LENGTH-1:0] f_salu_branch_wfid;
// Output - list of pending branches
output [`WF_PER_CU-1:0] pending_branches_arry;
/**
* Branch wait is a reg that marks all wf with a pending branch.
* Pending branches start when a branch instruction is issued
* and end when salu signals the outcome of the branch
**/
wire alu_branch_valid;
wire [`WF_PER_CU-1:0] alu_branch_decoded,
salu_branch_decoded;
wire [`WF_PER_CU-1:0] pending_branch, next_pending_branch;
assign pending_branches_arry = pending_branch;
// Decoder for the issued branch
decoder_6b_40b_en alu_brach_decoder
(
.addr_in(alu_wfid),
.out(alu_branch_decoded),
.en(alu_branch_valid)
);
// Decoder for the finished branch by fetch
decoder_6b_40b_en issue_Value_decoder
(
.addr_in(f_salu_branch_wfid),
.out(salu_branch_decoded),
.en(f_salu_branch_en)
);
dff pending_branch_ff[`WF_PER_CU-1:0]
(
.q(pending_branch),
.d(next_pending_branch),
.clk(clk),
.rst(rst)
);
assign alu_branch_valid = alu_valid && alu_branch;
assign next_pending_branch
= ( pending_branch | (alu_branch_decoded) ) &
~(salu_branch_decoded);
endmodule
|
`timescale 1ns / 1ps
// synopsys template
module matrix_mult_N_M_1
#(
parameter N=3,
parameter M=32
)
(
clk,
rst,
g_input,
e_input,
o
);
input clk,rst;
input[N*M-1:0] g_input;
input[N*N*M-1:0] e_input;
output[N*M-1:0] o;
wire [M-1:0] xi[N-1:0];
wire [M-1:0] yij[N-1:0][N-1:0];
reg [M-1:0] oi[N-1:0];
wire [2*M-1:0] xyij[N-1:0][N-1:0];
wire [M-1:0] oij[N-1:0][N:0];
genvar i;
genvar j;
genvar k;
generate
for (i=0;i<N;i=i+1)
begin:ASS_ROW
assign xi[i] = g_input[M*(i+1)-1:M*(i)];
assign o[M*(i+1)-1:M*(i)] = oi[i];
for (j=0;j<N;j=j+1)
begin:ASS_COL
assign yij[i][j] = e_input[M*(N*i+j+1)-1:M*(N*i+j)];
end
end
endgenerate
generate
for (i=0;i<N;i=i+1)
begin:MUL_ROW
for (k=0;k<N;k=k+1)
begin:MULT_O
//assign xyij[i][k] = xi[k]*yij[k][i];
MULT
#(
.N(M)
)
MULT_
(
.A(xi[k]),
.B(yij[k][i]),
.O(xyij[i][k])
);
end
end
endgenerate
generate
for (i=0;i<N;i=i+1)
begin:ASS_O
assign oij[i][0] = oi[i];
end
endgenerate
generate
for (i=0;i<N;i=i+1)
begin:ADD_ROW
for (k=0;k<N;k=k+1)
begin:ADD_O
ADD
#(
.N(M)
)
ADD_
(
.A(xyij[i][k][M-1:0]),
.B(oij[i][k]),
.CI(1'b0),
.S(oij[i][k+1]),
.CO()
);
end
end
endgenerate
generate
for (i=0;i<N;i=i+1)
begin:REG_ROW
always@(posedge clk or posedge rst)
begin
if(rst)
begin
oi[i] <= 'b0;
end
else
begin
oi[i] <= oij[i][N];
end
end
end
endgenerate
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_buffered_fifo(clock, resetn,
data_in, valid_in, stall_out,
data_out, valid_out, stall_in);
parameter DATA_WIDTH = 32;
parameter DEPTH = 64;
parameter EXTRA_FIFO_SPACE = 32; //256;
parameter IMPLEMENTATION_MODE = "MLAB";
localparam REAL_DEPTH=DEPTH-EXTRA_FIFO_SPACE;
input clock, resetn;
input [DATA_WIDTH-1:0] data_in;
input valid_in;
output stall_out;
output [DATA_WIDTH-1:0] data_out;
output valid_out;
input stall_in;
wire fifo_almost_full;
generate
if (IMPLEMENTATION_MODE == "RAM")
begin
acl_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
else
begin
acl_mlab_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(data_in), .data_out(data_out), .valid_in(valid_in),
.valid_out( valid_out ), .stall_in(stall_in), .stall_out(),
.almost_full( fifo_almost_full ) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = DEPTH;
defparam fifo_a.ALMOST_FULL_VALUE = REAL_DEPTH;
end
endgenerate
assign stall_out = fifo_almost_full;
endmodule
|
`timescale 1ns / 1ps
// Copyright (C) 2008 Schuyler Eldridge, Boston University
//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation, either version 3 of the License.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program. If not, see <http://www.gnu.org/licenses/>.
module mux(opA,opB,sum,dsp_sel,out);
input [3:0] opA,opB;
input [4:0] sum;
input [1:0] dsp_sel;
output [3:0] out;
reg cout;
always @ (sum)
begin
if (sum[4] == 1)
cout <= 4'b0001;
else
cout <= 4'b0000;
end
reg out;
always @(dsp_sel,sum,cout,opB,opA)
begin
if (dsp_sel == 2'b00)
out <= sum[3:0];
else if (dsp_sel == 2'b01)
out <= cout;
else if (dsp_sel == 2'b10)
out <= opB;
else if (dsp_sel == 2'b11)
out <= opA;
end
endmodule
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module acl_fp_convert_with_rounding(clock, resetn, dataa, result, valid_in, valid_out, stall_in, stall_out, enable);
// Latency = 5.
parameter UNSIGNED = 1;
parameter ROUNDING_MODE = 0;
parameter HIGH_CAPACITY = 1;
// Rounding mode values are:
// 0 - round to nearest even
// 1 - round to nearest with ties away from zero
// 2 - round towards zero (truncation)
// 3 - round up
// 4 - round down
input clock;
input enable, resetn;
input [31:0] dataa;
output [31:0] result;
input valid_in, stall_in;
output stall_out, valid_out;
// STAGE 0 - extract input data into format we can work with.
wire sign_0;
wire [7:0] exp_0;
wire [22:0] man_0;
wire [23:0] implied_man_0;
assign {sign_0, exp_0, man_0} = dataa;
assign implied_man_0 = (|exp_0) ? {1'b1, man_0} : 24'd0;
// STAGE 1
reg sign_c1;
reg [31:0] man_c1;
reg [8:0] shift_amount_c1;
reg [7:0] exp_c1;
reg valid_c1;
wire stall_c1;
wire enable_c1;
assign stall_out = stall_c1 & valid_c1;
assign enable_c1 = (HIGH_CAPACITY == 1) ? (~stall_c1 | ~valid_c1) : enable;
always @( posedge clock or negedge resetn)
begin
if( ~resetn )
begin
sign_c1 <= 1'bx;
man_c1 <= 32'dx;
shift_amount_c1 <= 9'dx;
exp_c1 <= 8'dx;
valid_c1 <= 1'b0;
end
else if (enable_c1)
begin
sign_c1 <= sign_0;
valid_c1 <= valid_in;
if (UNSIGNED == 1)
begin
man_c1 <= {implied_man_0, 8'd0};
shift_amount_c1 <= 9'd158 - exp_0;
end
else
begin
man_c1 <= {1'b0, implied_man_0, 7'd0};
shift_amount_c1 <= 9'd157 - exp_0;
end
exp_c1 <= exp_0;
end
end
// STAGE 2
reg sign_c2;
reg [34:0] extended_mantissa_c2;
reg [4:0] shift_amount_c2;
reg valid_c2;
wire stall_c2;
wire enable_c2 = (HIGH_CAPACITY == 1) ? (~stall_c2 | ~valid_c2) : enable;
assign stall_c1 = stall_c2 & valid_c2;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
sign_c2 <= 1'bx;
extended_mantissa_c2 <= 35'dx;
shift_amount_c2 <= 5'dx;
valid_c2 <= 1'b0;
end
else if (enable_c2)
begin
sign_c2 <= sign_c1;
valid_c2 <= valid_c1;
shift_amount_c2 <= (shift_amount_c1[4:0]) & {5{(~(&exp_c1)) & ~shift_amount_c1[8]}};
// Now handle the corner cases of NaN and INF. Make it maximum positive or negative integer depending on the sign.
// Then handle overflow and regular shifting.
if ((UNSIGNED == 1) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {32'hffffffff, 3'd0};
else if ((UNSIGNED == 0) && (exp_c1 == 8'hff))
extended_mantissa_c2 <= {32'h7fffffff + sign_c1, 3'd0};
else if (shift_amount_c1[8])
extended_mantissa_c2 <= {(UNSIGNED == 0) ? 32'h7fffffff + sign_c1 : 32'hffffffff, 3'd0}; // Overflow/Saturation.
else if (|shift_amount_c1[7:6])
begin
// Shift by more than 64+
sign_c2 <= sign_c1 & (|man_c1[31:8]);
extended_mantissa_c2 <= {34'd0, |man_c1[31:8]};
end
else if (|shift_amount_c1[5])
begin
// Shift by 32+
extended_mantissa_c2 <= {32'd0, man_c1[31:30], |man_c1[29:8]};
end
else
extended_mantissa_c2 <= {man_c1, 3'd0};
end
end
// STAGE 3
reg [34:0] extended_mantissa_c3;
reg [2:0] shift_amount_c3;
reg valid_c3;
reg sign_c3;
wire stall_c3;
wire enable_c3 = (HIGH_CAPACITY == 1) ? (~valid_c3 | ~stall_c3) : enable;
assign stall_c2 = valid_c3 & stall_c3;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c3 <= 35'dx;
sign_c3 <= 1'bx;
shift_amount_c3 <= 3'dx;
valid_c3 <= 1'b0;
end
else if (enable_c3)
begin
valid_c3 <= valid_c2;
sign_c3 <= sign_c2;
shift_amount_c3 <= shift_amount_c2[2:0];
case (shift_amount_c2[4:3])
2'b11: extended_mantissa_c3 <= {24'd0, extended_mantissa_c2[34:25], |extended_mantissa_c2[24:0]};
2'b10: extended_mantissa_c3 <= {16'd0, extended_mantissa_c2[34:17], |extended_mantissa_c2[16:0]};
2'b01: extended_mantissa_c3 <= {8'd0, extended_mantissa_c2[34:9], |extended_mantissa_c2[8:0]};
2'b00: extended_mantissa_c3 <= extended_mantissa_c2;
endcase
end
end
// STAGE 4
reg [34:0] extended_mantissa_c4;
reg sign_c4;
reg valid_c4;
wire stall_c4;
wire enable_c4 = (HIGH_CAPACITY == 1) ? (~valid_c4 | ~stall_c4) : enable;
assign stall_c3 = valid_c4 & stall_c4;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
extended_mantissa_c4 <= 35'dx;
sign_c4 <= 1'dx;
valid_c4 <= 1'b0;
end
else if (enable_c4)
begin
valid_c4 <= valid_c3;
sign_c4 <= sign_c3;
case (shift_amount_c3)
3'b111: extended_mantissa_c4 <= {7'd0, extended_mantissa_c3[34:8], |extended_mantissa_c3[7:0]};
3'b110: extended_mantissa_c4 <= {6'd0, extended_mantissa_c3[34:7], |extended_mantissa_c3[6:0]};
3'b101: extended_mantissa_c4 <= {5'd0, extended_mantissa_c3[34:6], |extended_mantissa_c3[5:0]};
3'b100: extended_mantissa_c4 <= {4'd0, extended_mantissa_c3[34:5], |extended_mantissa_c3[4:0]};
3'b011: extended_mantissa_c4 <= {3'd0, extended_mantissa_c3[34:4], |extended_mantissa_c3[3:0]};
3'b010: extended_mantissa_c4 <= {2'd0, extended_mantissa_c3[34:3], |extended_mantissa_c3[2:0]};
3'b001: extended_mantissa_c4 <= {1'd0, extended_mantissa_c3[34:2], |extended_mantissa_c3[1:0]};
3'b000: extended_mantissa_c4 <= extended_mantissa_c3;
endcase
end
end
// STAGE 5
reg [32:0] result_c5;
reg valid_c5;
wire stall_c5;
wire enable_c5 = (HIGH_CAPACITY == 1) ? (~valid_c5 | ~stall_c5) : enable;
assign stall_c4 = valid_c5 & stall_c5;
assign stall_c5 = stall_in;
always @( posedge clock or negedge resetn)
begin
if (~resetn)
begin
result_c5 <= 33'dx;
valid_c5 <= 1'b0;
end
else if (enable_c5)
begin
valid_c5 <= valid_c4;
case(ROUNDING_MODE)
2:
begin // 2 is round to zero
if (UNSIGNED == 0)
begin
result_c5 <= ({33{sign_c4}} ^ ({1'b0, extended_mantissa_c4[34:3]})) + {1'b0, sign_c4};
end
else
begin
result_c5 <= (sign_c4) ? 33'd0 : {1'b0, extended_mantissa_c4[34:3]};
end
end
4:
begin // 4 is round down
if (|extended_mantissa_c4[2:0])
begin
if (UNSIGNED == 0)
begin
result_c5 <= (sign_c4) ? (({33{sign_c4}} ^ (extended_mantissa_c4[34:3] + 1'b1)) + 1'b1) : extended_mantissa_c4[34:3];
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3];
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
3:
begin // 3 is round up
if (|extended_mantissa_c4[2:0])
begin
if (UNSIGNED == 0)
begin
result_c5 <= (sign_c4) ? (({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + 1'b1) : (extended_mantissa_c4[34:3] + 1'b1);
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
1:
begin // 1 is round to nearest with ties rounded away from zero.
if (extended_mantissa_c4[2])
begin
if (UNSIGNED == 0)
begin
result_c5 <= ({33{sign_c4}} ^ (extended_mantissa_c4[34:3] + 1'b1)) + sign_c4;
end
else
begin
result_c5 <= (sign_c4) ? 32'd0 : extended_mantissa_c4[34:3] + 1'b1;
end
end
else
begin
if (UNSIGNED == 0)
result_c5 <= ({33{sign_c4}} ^ extended_mantissa_c4[34:3]) + sign_c4;
else
result_c5 <= {32{~sign_c4}} & extended_mantissa_c4[34:3];
end
end
default:
begin // 0 and default are round to nearest even
if (UNSIGNED == 0)
begin
if ((extended_mantissa_c4[3:0] == 4'hc) | (extended_mantissa_c4[2] & (|extended_mantissa_c4[1:0])))
result_c5 <= ({33{sign_c4}} ^ {1'b0, extended_mantissa_c4[34:3]}) + {1'b0,~sign_c4};
else
result_c5 <= ({33{sign_c4}} ^ {1'b0, extended_mantissa_c4[34:3]}) + sign_c4;
end
else
begin
if ((extended_mantissa_c4[3:0] == 4'hc) | (extended_mantissa_c4[2] & (|extended_mantissa_c4[1:0])))
result_c5 <= (sign_c4) ? 33'd0 : {1'b0, extended_mantissa_c4[34:3]} + 1'b1;
else
result_c5 <= {33{~sign_c4}} & {1'b0, extended_mantissa_c4[34:3]};
end
end
endcase
end
end
assign result = (UNSIGNED == 1) ? ({32{result_c5[32]}} | result_c5[31:0]) : ((result_c5[32] ^ result_c5[31]) ? {result_c5[32], {31{~result_c5[32]}}} : result_c5[31:0]);
assign valid_out = valid_c5;
endmodule
|
/*
** -----------------------------------------------------------------------------**
** quantizator353.v
**
** Quantizator module for JPEG compressor
**
** Copyright (C) 2002-2010 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** This file is part of X353
** X353 is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
`timescale 1ns/1ps
// will add extracted DC (8 bits) to data from DCT here that will make data 12 bits (signed) long.
// It will be possible to make a sequincial multiplier for DC - but I'll skip this opportunity now.
//********** TODO: switch to 16-bit tables instead of the 12-bit ones **************
module quantizator(clk, // pixel clock
en, // enable (0 resets counter)
sclk, // system clock, twqe, twce, ta,tdi - valid @negedge (ra, tdi - 2 cycles ahead
twqe, // enable write to a quantization table
twce, // enable write to a coring table
ta, // [6:0] table address
tdi, // [15:0] table data in (8 LSBs - quantization data)
// readback, // readback data
ctypei, // component type input (Y/C)
dci, // [7:0] - average value in a block - subtracted before DCT
first_stb, //this is first stb pulse in a frame
stb, // strobe that writes ctypei, dci
tsi, // table (quality) select [2:0]
pre_start,// marks first input pixel (one before)
first_in, // first block in (valid @ start)
first_out, // valid @ ds
di, // [11:0] pixel data in (signed)
do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
dv, // data out valid
ds, // data out strobe (one ahead of the start of dv)
dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
// dc_tdo_stb,
dcc_en, // enable dcc (sync to beginning of a new frame)
hfc_sel, // hight frequency components select [2:0] (includes components with both numbers >=hfc_sel
// hfc_sel == 3'h7 - now high frequency output - just 3 words - brightness and 2 color diffs
color_first, // first MCU in a frame
coring_num, // coring table pair number (0..7)
dcc_vld, // single cycle when dcc_data is valid
dcc_data, // [15:0] dc component data out (for reading by software)
n000, // input [7:0] number of zero pixels (255 if 256) - to be multiplexed with dcc
n255); // input [7:0] number of 0xff pixels (255 if 256) - to be multiplexed with dcc
input clk;
input en;
input sclk;
input twqe;
input twce;
input [ 8:0] ta;
input [15:0] tdi;
input ctypei;
input [ 8:0] dci; // now normal signed number
input first_stb; //this is first stb pulse in a frame
input stb;
input [ 2:0] tsi;
input pre_start;
input first_in; // first block in (valid @ start)
output first_out; // valid @ ds
input [12:0] di;
output[12:0] do;
output dv;
output ds;
output [15:0] dc_tdo;
input dcc_en;
input [2:0] hfc_sel;
input color_first;
input [2:0] coring_num; // Coring table number (0..7)
output dcc_vld;
output[15:0] dcc_data;
input [7:0] n000;
input [7:0] n255;
wire [3:0] tdco; // coring table output
reg [3:0] tbac; // coring memory table number (LSB - color)
reg coring_range; // input <16, use coring LUT
wire [15:0] tdo;
reg [ 9:0] tba; // table output (use) address
wire [15:0] zigzag_q;
reg wpage,
rpage;
wire [5:0] zwa;
reg [5:0] zra;
reg [12:0] qdo;
reg [12:0] qdo0;
reg zwe;
reg [12:0] d1;
reg [12:0] d2,d3; // registered data in, converted to sign+ absolute value
wire [27:0] qmul;
wire start_a;
reg [15:0] tdor;
reg [20:0] qmulr; // added 7 bits to total8 fractional for biasing/zero bin
wire start_out;
wire start_z;
reg ds;
reg dv;
reg [ 8:0] dc1; // registered DC average - with restored sign
// for fifo for ctype, dc
wire ctype;
wire [8:0] dc;
wire next_dv;
reg [ 5:0] start;
wire [15:0] dcc_data;
wire dcc_stb;
reg dcc_vld;
reg dcc_run;
reg dcc_first;
reg dcc_Y;
reg [1:0] ctype_prev;
reg [12:0] dcc_acc;
reg [12:0] hfc_acc;
wire hfc_en;
reg hfc_copy; // copy hfc_acc to dcc_acc
wire [10:0] d2_dct; // 11 bits enough, convetred to positive (before - 0 was in the middle - pixel value 128) - dcc only
reg sel_satnum; // select saturation numbers - dcc only
reg twqe_d; //twqe delayed (write MSW)
reg twce_d; //twce delayed (write MSW)
reg [15:0] dc_tdo;
reg [15:0] pre_dc_tdo;
wire copy_dc_tdo;
wire first_in; // first block in (valid @ pre_start)
reg first_interm, first_out; // valid @ ds
wire [2:0] ts;
wire [2:0] coring_sel;
reg [2:0] block_mem_ra;
reg [2:0] block_mem_wa;
reg [2:0] block_mem_wa_save;
reg [15:0] block_mem[0:7];
wire [15:0] block_mem_o=block_mem[block_mem_ra[2:0]];
assign dc[8:0]= block_mem_o[8:0];
assign ctype= block_mem_o[9];
assign ts[2:0]= block_mem_o[12:10];
assign coring_sel[2:0]= block_mem_o[15:13];
assign start_a=start[5];
assign start_z=start[4];
assign dcc_stb=start[2];
always @ (posedge clk) begin
if (stb) block_mem[block_mem_wa[2:0]] <= {coring_num[2:0],tsi[2:0], ctypei, dci[8:0]};
if (!en) block_mem_wa[2:0] <= 3'h0;
else if (stb) block_mem_wa[2:0] <= block_mem_wa[2:0] +1;
if (stb && first_stb) block_mem_wa_save[2:0] <= block_mem_wa[2:0];
if (!en) block_mem_ra[2:0] <= 3'h0;
else if (pre_start) block_mem_ra[2:0] <= first_in?block_mem_wa_save[2:0]:(block_mem_ra[2:0] +1);
end
assign d2_dct[10:0]={!d2[11] ^ ctype_prev[0], d2[9:0]};
assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
assign do[12:0]=zigzag_q[12:0];
// assign qmul[23:0]=tdor[11:0]*d3[11:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin
d1[12:0] <= di[12:0];
//inv_sign
// dc1[8:0] <= start[0]?{{2{~dc[7]}},dc[6:0]}:9'b0; // sync to d1[8:0]ctype valid at start, not later
dc1[8:0] <= start[0]?dc[8:0]:9'b0; // sync to d1[8:0]ctype valid at start, not later
d2[12:0] <= {dc1[8],dc1[8:0],3'b0} + d1[12:0];
d3[12] <= d2[12];
d3[11:0] <= d2[12]? -d2[11:0]:d2[11:0];
if (start[0] || !en) tba[9:6] <= {ts[2:0],ctype};
/// TODO - make sure ctype switches at needed time (compensate if needed) *****************************************
if (start[3] || !en) tbac[3:0] <= {coring_sel[2:0],ctype}; // table number to use
if (start[0]) tba[5:0] <= 6'b0;
else if (tba[5:0]!=6'h3f) tba[5:0] <= tba[5:0]+1;
tdor[15:0] <= tdo[15:0]; // registered table data out
if (start[3]) pre_dc_tdo[15:0] <= tdor[15:0]; //16-bit q. tables)
if (copy_dc_tdo) dc_tdo[15:0] <= pre_dc_tdo[15:0];
qmulr[19:0] <= qmul[27:8]; // absolute value
qmulr[20] <= d3[12]; // sign
qdo0[12] <= qmulr[20]; // sign
// tdco[3:0] - same timing as qdo0;
// use lookup table from 8 bits of absolute value (4.4 - 4 fractional) to calculate 4 bit coring output that would replace output
// if input is less thahn 16. For larger values the true rounding will be used.
// Absolute values here have quantization coefficients already applied, so we can use the same coring table for all DCT coefficients.
// there are be 16 tables - 8 Y/C pairs to switch
qdo0[11:0] <= qmulr[19:8] + qmulr[7]; // true rounding of the absolute value
coring_range<= !(|qmulr[19:12]) && !(&qmulr[11:7]) ; // valid with qdo0
// qdo[11:0] <= coring_range? {8'h0,tdco[3:0]}:qdo0[11:0];
qdo[11:0] <= coring_range? (qdo0[12]?-{8'h0,tdco[3:0]}:{8'h0,tdco[3:0]}):(qdo0[12]?-qdo0[11:0]:qdo0[11:0]);
qdo[12] <= qdo0[12] && (!coring_range || (tdco[3:0]!=4'h0));
if (start_out) rpage <= wpage;
if (start_out) zra[5:0] <= 6'b0;
else if (zra[5:0]!=6'h3f) zra[5:0] <=zra[5:0]+1; // conserving energy
ds <= start_out;
dv <= next_dv;
if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm;
// zwe???
zwe <= en && (start_a || (zwe && (zwa[5:0]!=6'h3f)));
if (!en) wpage <= 1'b0;
else if (start_a) wpage <= ~wpage;
end
always @ (posedge clk) begin
sel_satnum <= dcc_run && (start[0]? (ctype_prev[1:0]==2'b10): sel_satnum);
hfc_copy <= dcc_run && (hfc_sel[2:0]!=3'h7) && (tba[5:0]==6'h1f) && ctype_prev[0] && ctype_prev[1];
start[5:0] <= {start[4:0], pre_start}; // needed?
if (!dcc_en) dcc_run <= 1'b0;
else if (start[0]) dcc_run <= 1'b1;
if (!dcc_en) ctype_prev[1:0] <= 2'b11;
else if (start[0]) ctype_prev[1:0] <= {ctype_prev[0],ctype && dcc_run};
if (dcc_stb || hfc_copy) dcc_acc[12:0] <= hfc_copy?
hfc_acc[12:0]:
{(d2_dct[10]&&ctype_prev[0]),(d2_dct[10]&&ctype_prev[0]),d2_dct[10:0]}+((ctype_prev[0] || ctype_prev[1])?13'h0:dcc_acc[12:0]);
if (!dcc_run || hfc_copy) hfc_acc <=13'b0;
else if (hfc_en) hfc_acc <= hfc_acc + {2'b0, d3[10:0]};
if (dcc_stb) dcc_first <= color_first && dcc_run && dcc_stb && ctype && !ctype_prev[0];
if (dcc_stb) dcc_Y <= dcc_run && dcc_stb && ctype && !ctype_prev[0];
dcc_vld <= (dcc_run && dcc_stb && (ctype || ctype_prev[0] || sel_satnum)) || hfc_copy;
end
SRL16 i_hfc_en (.Q(hfc_en), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(clk),
.D(((tba[2:0]>hfc_sel[2:0]) || (tba[5:3]>hfc_sel[2:0])) && dcc_run && !ctype_prev[0])); // dly=1+1
zigzag i_zigzag( .clk(clk),
.start(start_z),
.q(zwa[5:0]));
always @ (negedge sclk) twqe_d <= twqe;
always @ (negedge sclk) twce_d <= twce;
RAMB16_S18_S18 i_quant_table (
.DOA(tdo[15:0]), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({tba[9:6],tba[2:0],tba[5:3]}), // Port A 10-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(16'b0), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.DOB(), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({ta[8:0],twqe_d}), // Port B 10-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(tdi[15:0]), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(1'b1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(twqe || twqe_d) // Port B Write Enable Input
);
RAMB16_S4_S18 i_coring_table (
.DOA(tdco[3:0]), // Port A 4-bit Data Output
.ADDRA({tbac[3:0],qmulr[11:4]}), // Port A 12-bit Address Input
.CLKA(clk), // Port A Clock
.DIA(4'b0), // Port A 4-bit Data Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(1'b0), // Port A Write Enable Input
.DOB(), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({ta[8:0],twce_d}), // Port B 10-bit Address Input
.CLKB(!sclk), // Port B Clock
.DIB(tdi[15:0]), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(1'b1), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(twce || twce_d) // Port B Write Enable Input
);
RAMB16_S18_S18 i_zigzagbuf (
.DOA(), // Port A 16-bit Data Output
.DOPA(), // Port A 2-bit Parity Output
.ADDRA({3'b0,wpage,zwa[5:0]}), // Port A 10-bit Address Input
.CLKA(clk), // Port A Clock
.DIA({3'b0,qdo[12:0]}), // Port A 16-bit Data Input
.DIPA(2'b0), // Port A 2-bit parity Input
.ENA(1'b1), // Port A RAM Enable Input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input
.WEA(zwe), // Port A Write Enable Input
.DOB(zigzag_q[15:0]), // Port B 16-bit Data Output
.DOPB(), // Port B 2-bit Parity Output
.ADDRB({3'b0,rpage,zra[5:0]}), // Port B 10-bit Address Input
.CLKB(clk), // Port B Clock
.DIB(16'b0), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(next_dv), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
);
endmodule
// Alternative ZigZag distributed ROM. More convinient, but extra resources. Use upper half of quantization table to save slices.
module zigzag (clk,
start,
q);
input clk, start;
output [5:0] q;
reg [5:0] a;
reg [5:0] q;
wire [4:0] rom_a;
wire [5:0] rom_q;
assign rom_a[4:0]=a[5]?(~a[4:0]):a[4:0];
always @ (posedge clk) begin
if (start) a[5:0] <= 6'b0;
// else a[5:0] <= a[5:0]+1; // may add if (a[5:0]!=6'h3f) to make cleaner simulation and conserve energy
else if (a[5:0]!=6'h3f) a[5:0] <= a[5:0]+1;
q[5:0] <= a[5]? (~rom_q[5:0]):rom_q[5:0];
end
ROM32X1 #(.INIT(32'hC67319CC)) i_z0 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[0]));
ROM32X1 #(.INIT(32'h611A7896)) i_z1 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[1]));
ROM32X1 #(.INIT(32'h6357A260)) i_z2 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[2]));
ROM32X1 #(.INIT(32'h4A040C18)) i_z3 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[3]));
ROM32X1 #(.INIT(32'h8C983060)) i_z4 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[4]));
ROM32X1 #(.INIT(32'hF0E0C080)) i_z5 ( .A0(rom_a[0]), .A1(rom_a[1]), .A2(rom_a[2]), .A3(rom_a[3]), .A4(rom_a[4]), .O(rom_q[5]));
endmodule
|
////////////////////////////////////////////////////////////////////////////////
// Copyright (c) 1995-2011 Xilinx, Inc. All rights reserved.
////////////////////////////////////////////////////////////////////////////////
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: O.87xd
// \ \ Application: netgen
// / / Filename: fifo_138x512.v
// /___/ /\ Timestamp: Thu Nov 8 18:37:40 2012
// \ \ / \
// \___\/\___\
//
// Command : -w -sim -ofmt verilog /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x512.ngc /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x512.v
// Device : 5vlx330ff1760-1
// Input file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x512.ngc
// Output file : /home/ktown/caeSMVMv2/coregen/tmp/_cg/fifo_138x512.v
// # of Modules : 1
// Design Name : fifo_138x512
// Xilinx : /remote/Xilinx/13.4/ISE/
//
// Purpose:
// This verilog netlist is a verification model and uses simulation
// primitives which may not represent the true implementation of the
// device, however the netlist is functionally correct and should not
// be modified. This file cannot be synthesized and should only be used
// with supported simulation tools.
//
// Reference:
// Command Line Tools User Guide, Chapter 23 and Synthesis and Simulation Design Guide, Chapter 6
//
////////////////////////////////////////////////////////////////////////////////
`timescale 1 ns/1 ps
module fifo_138x512 (
clk, rd_en, empty, wr_en, full, srst, dout, din
)/* synthesis syn_black_box syn_noprune=1 */;
input clk;
input rd_en;
output empty;
input wr_en;
output full;
input srst;
output [137 : 0] dout;
input [137 : 0] din;
// synthesis translate_off
wire N0;
wire N1;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ;
wire \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED ;
wire \NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 ;
wire [3 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet ;
wire [4 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 ;
wire [7 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy ;
wire [0 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count ;
wire [8 : 0] \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 ;
assign
empty = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 ,
full = \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 ;
GND XST_GND (
.G(N0)
);
VCC XST_VCC (
.P(N1)
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_i_24 )
);
FD #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 )
);
FD #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i (
.C(clk),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 ),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_90 )
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [7])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [6])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [5])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [4])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [3])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [2])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1> (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [1])
);
XORCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<0> (
.CI(N0),
.LI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<0> (
.CI(N0),
.DI(N1),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2])
);
FDSE #(
.INIT ( 1'b1 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [0]),
.S(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Result [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_8 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_7 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_6 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_5 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_4 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_3 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_2 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_1 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1])
);
FDRE #(
.INIT ( 1'b0 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1_0 (
.C(clk),
.CE(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.D(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.R(srst),
.Q(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/carrynet [0])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[4].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 )
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[3].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [3])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[2].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [2])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[1].gms.ms (
.CI(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0]),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [1])
);
MUXCY \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/gmux.gm[0].gm1.m1 (
.CI(N1),
.DI(N0),
.S(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/carrynet [0])
);
LUT3 #(
.INIT ( 8'hF4 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en1 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I1(rd_en),
.I2(srst),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/ram_wr_en_i1 (
.I0(wr_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en )
);
LUT2 #(
.INIT ( 4'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/ram_rd_en_i1 (
.I0(rd_en),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en )
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [4])
);
LUT2 #(
.INIT ( 4'h9 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_4_not00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [4])
);
LUT4 #(
.INIT ( 16'h8421 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [3])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_3_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [3])
);
LUT4 #(
.INIT ( 16'h8421 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [2])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_2_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [2])
);
LUT4 #(
.INIT ( 16'h8421 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [1])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_1_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [1])
);
LUT4 #(
.INIT ( 16'h8421 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c1/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/c0/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c2/v1 [0])
);
LUT4 #(
.INIT ( 16'h9009 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1_0_and00001 (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1]),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1]),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0]),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/c1/v1 [0])
);
LUT6 #(
.INIT ( 64'h1110101051505050 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux00001 (
.I0(srst),
.I1(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_rd_en ),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_fb_i_89 ),
.I3(wr_en),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/gwss.wsts/ram_full_i_mux0000 )
);
LUT6 #(
.INIT ( 64'hAAFEAAFAFAFEFAFA ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux00001 (
.I0(srst),
.I1(rd_en),
.I2(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_22 ),
.I3(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.I4(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp1 ),
.I5(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/comp0 ),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/grss.rsts/ram_empty_fb_i_mux0000 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<7>_rt_39 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<6>_rt_37 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<5>_rt_35 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<4>_rt_33 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<3>_rt_31 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<2>_rt_29 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_cy<1>_rt_27 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [7]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<7>_rt_106 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [6]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<6>_rt_104 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [5]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<5>_rt_102 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [4]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<4>_rt_100 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [3]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<3>_rt_98 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [2]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<2>_rt_96 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [1]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_cy<1>_rt_94 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_xor<8>_rt_41 )
);
LUT1 #(
.INIT ( 2'h2 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt (
.I0(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [8]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_xor<8>_rt_108 )
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/Mcount_count_lut [0])
);
INV \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut<0>_INV_0 (
.I(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count [0]),
.O(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/Mcount_count_lut [0])
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({din[70], din[69], din[68], din[67], din[66], din[65], din[64], din[63], din[61], din[60], din[59], din[58], din[57], din[56], din[55],
din[54], din[52], din[51], din[50], din[49], din[48], din[47], din[46], din[45], din[43], din[42], din[41], din[40], din[39], din[38], din[37],
din[36], din[34], din[33], din[32], din[31], din[30], din[29], din[28], din[27], din[25], din[24], din[23], din[22], din[21], din[20], din[19],
din[18], din[16], din[15], din[14], din[13], din[12], din[11], din[10], din[9], din[7], din[6], din[5], din[4], din[3], din[2], din[1], din[0]}),
.DIP({din[71], din[62], din[53], din[44], din[35], din[26], din[17], din[8]}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({dout[70], dout[69], dout[68], dout[67], dout[66], dout[65], dout[64], dout[63], dout[61], dout[60], dout[59], dout[58], dout[57], dout[56],
dout[55], dout[54], dout[52], dout[51], dout[50], dout[49], dout[48], dout[47], dout[46], dout[45], dout[43], dout[42], dout[41], dout[40], dout[39],
dout[38], dout[37], dout[36], dout[34], dout[33], dout[32], dout[31], dout[30], dout[29], dout[28], dout[27], dout[25], dout[24], dout[23], dout[22],
dout[21], dout[20], dout[19], dout[18], dout[16], dout[15], dout[14], dout[13], dout[12], dout[11], dout[10], dout[9], dout[7], dout[6], dout[5],
dout[4], dout[3], dout[2], dout[1], dout[0]}),
.DOP({dout[71], dout[62], dout[53], dout[44], dout[35], dout[26], dout[17], dout[8]}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[0].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
RAMB36SDP_EXP #(
.DO_REG ( 0 ),
.EN_ECC_READ ( "FALSE" ),
.EN_ECC_SCRUB ( "FALSE" ),
.EN_ECC_WRITE ( "FALSE" ),
.INIT_7E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT ( 72'h000000000000000000 ),
.SRVAL ( 72'h000000000000000000 ),
.INIT_00 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_01 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_02 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_03 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_04 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_05 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_06 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_07 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_08 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_09 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_10 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_11 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_12 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_13 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_14 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_15 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_16 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_17 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_18 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_19 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_1F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_20 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_21 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_22 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_23 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_24 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_25 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_26 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_27 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_28 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_29 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_2F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_30 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_31 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_32 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_33 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_34 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_35 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_36 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_37 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_38 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_39 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_3F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_40 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_41 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_42 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_43 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_44 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_45 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_46 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_47 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_48 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_49 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_4F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_50 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_51 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_52 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_53 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_54 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_55 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_56 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_57 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_58 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_59 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_5F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_60 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_61 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_62 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_63 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_64 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_65 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_66 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_67 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_68 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_69 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_6F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_70 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_71 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_72 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_73 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_74 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_75 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_76 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_77 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_78 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_79 ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7A ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7B ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7C ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_7D ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INIT_FILE ( "NONE" ),
.SIM_COLLISION_CHECK ( "ALL" ),
.SIM_MODE ( "SAFE" ),
.INITP_0E ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ),
.INITP_0F ( 256'h0000000000000000000000000000000000000000000000000000000000000000 ))
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP (
.RDENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.RDENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/tmp_ram_rd_en ),
.WRENU(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.WRENL(\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ),
.SSRU(srst),
.SSRL(srst),
.RDCLKU(clk),
.RDCLKL(clk),
.WRCLKU(clk),
.WRCLKL(clk),
.RDRCLKU(clk),
.RDRCLKL(clk),
.REGCEU(N0),
.REGCEL(N0),
.SBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_SBITERR_UNCONNECTED )
,
.DBITERR
(\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DBITERR_UNCONNECTED )
,
.DI({din[137], din[136], din[135], din[134], din[133], din[132], din[131], din[130], din[129], din[128], din[127], din[126], din[125], din[124],
din[123], din[122], din[121], din[120], din[119], din[118], din[117], din[116], din[115], din[114], din[112], din[111], din[110], din[109], din[108],
din[107], din[106], din[105], din[104], din[103], din[102], din[101], din[100], din[99], din[98], din[97], din[96], din[95], din[94], din[93], din[92]
, din[91], din[90], din[89], din[88], din[87], din[86], din[85], din[84], din[83], din[82], din[81], din[79], din[78], din[77], din[76], din[75],
din[74], din[73], din[72]}),
.DIP({N0, N0, N0, din[113], N0, N0, N0, din[80]}),
.RDADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRL<0>_UNCONNECTED
}),
.RDADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.rd/rpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_RDADDRU<0>_UNCONNECTED
}),
.WRADDRL({N1, \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRL<0>_UNCONNECTED
}),
.WRADDRU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [8],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [7],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [6],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [5],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [4],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [3],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [2],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [1],
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.gl0.wr/wpntr/count_d1 [0],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_WRADDRU<0>_UNCONNECTED
}),
.WEU({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.WEL({\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en ,
\U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en , \U0/xst_fifo_generator/gconvfifo.rf/grf.rf/ram_wr_en }),
.DO({dout[137], dout[136], dout[135], dout[134], dout[133], dout[132], dout[131], dout[130], dout[129], dout[128], dout[127], dout[126], dout[125]
, dout[124], dout[123], dout[122], dout[121], dout[120], dout[119], dout[118], dout[117], dout[116], dout[115], dout[114], dout[112], dout[111],
dout[110], dout[109], dout[108], dout[107], dout[106], dout[105], dout[104], dout[103], dout[102], dout[101], dout[100], dout[99], dout[98], dout[97]
, dout[96], dout[95], dout[94], dout[93], dout[92], dout[91], dout[90], dout[89], dout[88], dout[87], dout[86], dout[85], dout[84], dout[83], dout[82]
, dout[81], dout[79], dout[78], dout[77], dout[76], dout[75], dout[74], dout[73], dout[72]}),
.DOP({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<5>_UNCONNECTED
, dout[113],
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_DOP<1>_UNCONNECTED
, dout[80]}),
.ECCPARITY({
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<7>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<6>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<5>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<4>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<3>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<2>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<1>_UNCONNECTED
,
\NLW_U0/xst_fifo_generator/gconvfifo.rf/grf.rf/gntv_or_sync_fifo.mem/gbm.gbmg.gbmga.ngecc.bmg/gnativebmg.native_blk_mem_gen/valid.cstr/ramloop[1].ram.r/v5_noinit.ram/SDP.WIDE_PRIM36.noeccerr.SDP_ECCPARITY<0>_UNCONNECTED
})
);
// synthesis translate_on
endmodule
// synthesis translate_off
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
// synthesis translate_on
|
`timescale 1ns / 1ps
/*
Copyright (C) 2016-2017, Stephen J. Leary
All rights reserved.
This file is part of TF530 (Terrible Fire 030 Accelerator).
TF530 is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
TF530 is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with TF530. If not, see <http://www.gnu.org/licenses/>.
*/
module tf530_ram(
input CLKCPU,
input RESET,
input A0,
input A1,
input [8:2] AB,
input [23:12] A,
inout [7:0] D,
input [1:0] SIZ,
input IDEINT,
input IDEWAIT,
output INT2,
input AS20,
input RW20,
input DS20,
// cache and burst control
input CBREQ,
output CBACK,
output CIIN,
output STERM,
// 32 bit internal cycle.
// i.e. assert OVR
output INTCYCLE,
// spare / debug
output SPARE,
// ram chip control
output [3:0] RAMCS,
output RAMOE
);
reg AS20_D = 1'b1;
reg DS20_D = 1'b1;
reg STERM_D = 1'b1;
wire BUS_CYCLE = (~DS20_D | DS20);
reg configured = 'b0;
reg shutup = 'b0;
reg [7:0] data_out = 'h00;
reg [7:0] base = 'h40;
wire GAYLE_INT2;
wire [7:0] GAYLE_DOUT;
//
wire IDE_ACCESS = (A[23:15] != {8'hDA, 1'b0}) | DS20 | AS20;
// $DE0000 or $DA8000 (Ignores A18)
wire GAYLE_REGS = (A[23:15] != {8'hDA, 1'b1});
wire GAYLE_ID= (A[23:15] != {8'hDE, 1'b0});
wire GAYLE_ACCESS = (GAYLE_ID & GAYLE_REGS) | DS20 | AS20;
wire GAYLE_READ = (GAYLE_ACCESS | ~RW20);
gayle GAYLE(
.CLKCPU ( CLKCPU ),
.RESET ( RESET ),
.CS ( GAYLE_ACCESS ),
.DS ( DS20 ),
.RW ( RW20 ),
.A18 ( A[18] ),
.A ( {1,b0, A[13:12]}),
.IDE_INT( IDEINT ),
.INT2 ( GAYLE_INT2 ),
.DIN ( D ),
.DOUT ( GAYLE_DOUT )
);
// 0xE80000
wire Z2_ACCESS = ({A[23:16]} != {8'hE8}) | AS20 | DS20 | shutup | configured;
wire Z2_READ = (Z2_ACCESS | ~RW20);
wire Z2_WRITE = (Z2_ACCESS | RW20);
wire RAM_ACCESS = ({A[23:21]} != {base[7:5]}) | AS20 | DS20 | ~configured;
wire [6:0] zaddr = {AB[7:2],A1};
always @(posedge CLKCPU) begin
AS20_D <= AS20;
DS20_D <= DS20;
STERM_D <= INTCYCLE | ~STERM_D;
if (RESET == 1'b0) begin
configured <= 1'b0;
shutup <= 1'b0;
STERM_D <= 1'b1;
end else begin
if (Z2_WRITE === 1'b0) begin
case (zaddr)
'h24: begin
base[7:4] <= D[7:4];
configured <= 1'b1;
end
'h25: base[3:0] <= D[7:4];
'h26: shutup <= 1'b1;
endcase
end
data_out <= 8'hff;
// the Gayle/Gary ID shift register.
if (Z2_READ == 1'b0) begin
// zorro config ROM
case (zaddr)
'h00: data_out[7:4] <= 4'he;
'h01: data_out[7:4] <= 4'h6;
'h02: data_out[7:4] <= 4'h7;
'h03: data_out[7:4] <= 4'h7;
'h04: data_out[7:4] <= 4'h7;
'h08: data_out[7:4] <= 4'he;
'h09: data_out[7:4] <= 4'hc;
'h0a: data_out[7:4] <= 4'h2;
'h0b: data_out[7:4] <= 4'h7;
'h10: data_out[7:4] <= 4'hc;
'h12: data_out[7:4] <= 4'hc;
'h13: data_out[7:4] <= 4'h6;
endcase
end else if (GAYLE_READ == 1'b0) begin
data_out <= GAYLE_DOUT;
end
end
end
wire RAMCS3n = A1 | A0; //
wire RAMCS2n = (~SIZ[1] & SIZ[0] & ~A0) | A1;
wire RAMCS1n = (SIZ[1] & ~SIZ[0] & ~A1 & ~A0) | (~SIZ[1] & SIZ[0] & ~A1) |(A1 & A0);
wire RAMCS0n = (~SIZ[1] & SIZ[0] & ~A1 ) | (~SIZ[1] & SIZ[0] & ~A0 ) | (SIZ[1] & ~A1 & ~A0 ) | (SIZ[1] & ~SIZ[0] & ~A1 );
// disable all the RAM.
assign RAMOE = RAM_ACCESS;
assign RAMCS = {RAMCS3n | RAM_ACCESS, RAMCS2n | RAM_ACCESS, RAMCS1n | RAM_ACCESS , RAMCS0n | RAM_ACCESS};
assign INTCYCLE = RAM_ACCESS & GAYLE_ACCESS;
// disable all burst control.
assign STERM = STERM_D;
assign CBACK = 1'b1; //STERM_D | CBREQ;
// cache the sram.
assign CIIN = 1'b0; //~RAM_ACCESS;
assign INT2 = GAYLE_INT2 ? 1'b0 : 1'bz;
assign D = Z2_READ & GAYLE_READ ? 8'bzzzzzzzz : data_out;
endmodule
|
/**
\file "inverters-syntax-err.v"
Chain a bunch of inverters between VPI/VCS and prsim, shoelacing.
$Id: inverters.v,v 1.3 2010/04/06 00:08:35 fang Exp $
Thanks to Ilya Ganusov for contributing this test.
*/
`timescale 1ns/1ps
`include "clkgen.v"
module timeunit;
initial $timeformat(-9,1," ns",9);
endmodule
module TOP;
wire in;
reg out0, out1, out2, out3, out;
clk_gen #(.HALF_PERIOD(1)) clk(in);
// prsim stuff
initial
begin
// @haco@ inverters.haco-c
$prsim("inverters.haco-c");
$prsim_cmd("echo $start of simulation");
$prsim_cmd("get in0 X"); // bad command
// should fail stop
$to_prsim("TOP.in", "in0");
$to_prsim("TOP.out0", "in1");
$to_prsim("TOP.out1", "in2");
$to_prsim("TOP.out2", "in3");
$to_prsim("TOP.out3", "in4");
$from_prsim("out0","TOP.out0");
$from_prsim("out1","TOP.out1");
$from_prsim("out2","TOP.out2");
$from_prsim("out3","TOP.out3");
$from_prsim("out4","TOP.out");
end
initial #45 $finish;
always @(in)
begin
$display("at time %7.3f, observed in %b", $realtime,in);
end
always @(out)
begin
$display("at time %7.3f, observed out = %b", $realtime,out);
end
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module dma_done_fifo # (
parameter P_FIFO_DATA_WIDTH = 21,
parameter P_FIFO_DEPTH_WIDTH = 4
)
(
input clk,
input rst_n,
input wr0_en,
input [P_FIFO_DATA_WIDTH-1:0] wr0_data,
output wr0_rdy_n,
output full_n,
input rd_en,
output [P_FIFO_DATA_WIDTH-1:0] rd_data,
output empty_n,
input wr1_clk,
input wr1_rst_n,
input wr1_en,
input [P_FIFO_DATA_WIDTH-1:0] wr1_data,
output wr1_rdy_n
);
localparam P_FIFO_ALLOC_WIDTH = 0; //128 bits
localparam S_IDLE = 2'b01;
localparam S_WRITE = 2'b10;
reg [1:0] cur_state;
reg [1:0] next_state;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_front_addr_p1;
wire [P_FIFO_DEPTH_WIDTH-1:0] w_front_addr;
reg [P_FIFO_DEPTH_WIDTH:0] r_rear_addr;
reg r_wr0_req;
reg r_wr1_req;
reg r_wr0_req_ack;
reg r_wr1_req_ack;
reg [1:0] r_wr_gnt;
wire w_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_en_d2;
reg r_wr1_en_sync;
reg r_wr1_en_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_wr1_rdy_n_sync_d2;
reg r_wr1_rdy_n;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data_sync;
reg r_wr_en;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr_data;
reg [P_FIFO_DATA_WIDTH-1:0] r_wr0_data;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [P_FIFO_DATA_WIDTH-1:0] r_wr1_data;
assign wr0_rdy_n = r_wr0_req;
assign wr1_rdy_n = r_wr1_rdy_n;
always @(posedge wr1_clk)
begin
r_wr1_en_sync_d1 <= wr1_en;
r_wr1_en_sync <= r_wr1_en_sync_d1 | wr1_en;
if(wr1_en == 1) begin
r_wr1_data_sync <= wr1_data;
end
r_wr1_rdy_n_sync <= r_wr1_req;
r_wr1_rdy_n_sync_d1 <= r_wr1_rdy_n_sync;
r_wr1_rdy_n_sync_d2 <= r_wr1_rdy_n_sync_d1;
end
always @(posedge wr1_clk or negedge wr1_rst_n)
begin
if(wr1_rst_n == 0) begin
r_wr1_rdy_n <= 0;
end
else begin
if(wr1_en == 1)
r_wr1_rdy_n <= 1;
else if(r_wr1_rdy_n_sync_d1 == 0 && r_wr1_rdy_n_sync_d2 == 1)
r_wr1_rdy_n <= 0;
end
end
assign w_wr1_en = r_wr1_en_d1 & ~r_wr1_en_d2;
always @(posedge clk)
begin
if(wr0_en == 1) begin
r_wr0_data <= wr0_data;
end
r_wr1_en <= r_wr1_en_sync;
r_wr1_en_d1 <= r_wr1_en;
r_wr1_en_d2 <= r_wr1_en_d1;
if(w_wr1_en == 1) begin
r_wr1_data <= r_wr1_data_sync;
end
end
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_wr0_req <= 0;
r_wr1_req <= 0;
end
else begin
if(r_wr0_req_ack == 1)
r_wr0_req <= 0;
else if(wr0_en == 1)
r_wr0_req <= 1;
if(r_wr1_req_ack == 1)
r_wr1_req <= 0;
else if(w_wr1_en == 1)
r_wr1_req <= 1;
end
end
always @ (posedge clk or negedge rst_n)
begin
if(rst_n == 0)
cur_state <= S_IDLE;
else
cur_state <= next_state;
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
if((r_wr0_req == 1 || r_wr1_req == 1) && (full_n == 1))
next_state <= S_WRITE;
else
next_state <= S_IDLE;
end
S_WRITE: begin
next_state <= S_IDLE;
end
default: begin
next_state <= S_IDLE;
end
endcase
end
always @ (posedge clk)
begin
case(cur_state)
S_IDLE: begin
if(r_wr0_req == 1)
r_wr_gnt <= 2'b01;
else if(r_wr1_req == 1)
r_wr_gnt <= 2'b10;
end
S_WRITE: begin
end
default: begin
end
endcase
end
always @ (*)
begin
case(cur_state)
S_IDLE: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
S_WRITE: begin
r_wr_en <= 1;
r_wr0_req_ack <= r_wr_gnt[0];
r_wr1_req_ack <= r_wr_gnt[1];
end
default: begin
r_wr_en <= 0;
r_wr0_req_ack <= 0;
r_wr1_req_ack <= 0;
end
endcase
end
always @ (*)
begin
case(r_wr_gnt) // synthesis parallel_case full_case
2'b01: r_wr_data <= r_wr0_data;
2'b10: r_wr_data <= r_wr1_data;
endcase
end
assign full_n = ~((r_rear_addr[P_FIFO_DEPTH_WIDTH] ^ r_front_addr[P_FIFO_DEPTH_WIDTH])
& (r_rear_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]
== r_front_addr[P_FIFO_DEPTH_WIDTH-1:P_FIFO_ALLOC_WIDTH]));
assign empty_n = ~(r_front_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]
== r_rear_addr[P_FIFO_DEPTH_WIDTH:P_FIFO_ALLOC_WIDTH]);
always @(posedge clk or negedge rst_n)
begin
if (rst_n == 0) begin
r_front_addr <= 0;
r_front_addr_p1 <= 1;
r_rear_addr <= 0;
end
else begin
if (rd_en == 1) begin
r_front_addr <= r_front_addr_p1;
r_front_addr_p1 <= r_front_addr_p1 + 1;
end
if (r_wr_en == 1) begin
r_rear_addr <= r_rear_addr + 1;
end
end
end
assign w_front_addr = (rd_en == 1) ? r_front_addr_p1[P_FIFO_DEPTH_WIDTH-1:0]
: r_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
localparam LP_DEVICE = "7SERIES";
localparam LP_BRAM_SIZE = "18Kb";
localparam LP_DOB_REG = 0;
localparam LP_READ_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_WIDTH = P_FIFO_DATA_WIDTH;
localparam LP_WRITE_MODE = "READ_FIRST";
localparam LP_WE_WIDTH = 4;
localparam LP_ADDR_TOTAL_WITDH = 9;
localparam LP_ADDR_ZERO_PAD_WITDH = LP_ADDR_TOTAL_WITDH - P_FIFO_DEPTH_WIDTH;
generate
wire [LP_ADDR_TOTAL_WITDH-1:0] rdaddr;
wire [LP_ADDR_TOTAL_WITDH-1:0] wraddr;
wire [LP_ADDR_ZERO_PAD_WITDH-1:0] zero_padding = 0;
if(LP_ADDR_ZERO_PAD_WITDH == 0) begin : calc_addr
assign rdaddr = w_front_addr[P_FIFO_DEPTH_WIDTH-1:0];
assign wraddr = r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0];
end
else begin
assign rdaddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], w_front_addr[P_FIFO_DEPTH_WIDTH-1:0]};
assign wraddr = {zero_padding[LP_ADDR_ZERO_PAD_WITDH-1:0], r_rear_addr[P_FIFO_DEPTH_WIDTH-1:0]};
end
endgenerate
BRAM_SDP_MACRO #(
.DEVICE (LP_DEVICE),
.BRAM_SIZE (LP_BRAM_SIZE),
.DO_REG (LP_DOB_REG),
.READ_WIDTH (LP_READ_WIDTH),
.WRITE_WIDTH (LP_WRITE_WIDTH),
.WRITE_MODE (LP_WRITE_MODE)
)
ramb18sdp_0(
.DO (rd_data[LP_READ_WIDTH-1:0]),
.DI (r_wr_data[LP_WRITE_WIDTH-1:0]),
.RDADDR (rdaddr),
.RDCLK (clk),
.RDEN (1'b1),
.REGCE (1'b1),
.RST (1'b0),
.WE ({LP_WE_WIDTH{1'b1}}),
.WRADDR (wraddr),
.WRCLK (clk),
.WREN (r_wr_en)
);
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
//altera message_off 10230
`include "alt_mem_ddrx_define.iv"
`timescale 1 ps / 1 ps
module alt_mem_ddrx_cmd_gen
# (parameter
// cmd_gen settings
CFG_LOCAL_ADDR_WIDTH = 33,
CFG_LOCAL_SIZE_WIDTH = 3,
CFG_LOCAL_ID_WIDTH = 8,
CFG_INT_SIZE_WIDTH = 4,
CFG_PORT_WIDTH_COL_ADDR_WIDTH = 4,
CFG_PORT_WIDTH_ROW_ADDR_WIDTH = 5,
CFG_PORT_WIDTH_BANK_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_CS_ADDR_WIDTH = 2,
CFG_PORT_WIDTH_BURST_LENGTH = 5,
CFG_PORT_WIDTH_ADDR_ORDER = 2,
CFG_DWIDTH_RATIO = 2, // 2-FR,4-HR,8-QR
CFG_CTL_QUEUE_DEPTH = 8,
CFG_MEM_IF_CHIP = 1, // one hot
CFG_MEM_IF_CS_WIDTH = 1, // binary coded
CFG_MEM_IF_BA_WIDTH = 3,
CFG_MEM_IF_ROW_WIDTH = 13,
CFG_MEM_IF_COL_WIDTH = 10,
CFG_DATA_ID_WIDTH = 10,
CFG_ENABLE_QUEUE = 1,
CFG_ENABLE_BURST_MERGE = 1,
CFG_CMD_GEN_OUTPUT_REG = 0,
CFG_CTL_TBP_NUM = 4,
CFG_CTL_SHADOW_TBP_NUM = 4,
MIN_COL = 8,
MIN_ROW = 12,
MIN_BANK = 2,
MIN_CS = 1
)
(
ctl_clk,
ctl_reset_n,
// tbp interface
tbp_full,
tbp_load,
tbp_read,
tbp_write,
tbp_chipsel,
tbp_bank,
tbp_row,
tbp_col,
tbp_shadow_chipsel,
tbp_shadow_bank,
tbp_shadow_row,
cmd_gen_load,
cmd_gen_chipsel,
cmd_gen_bank,
cmd_gen_row,
cmd_gen_col,
cmd_gen_write,
cmd_gen_read,
cmd_gen_multicast,
cmd_gen_size,
cmd_gen_localid,
cmd_gen_dataid,
cmd_gen_priority,
cmd_gen_rmw_correct,
cmd_gen_rmw_partial,
cmd_gen_autopch,
cmd_gen_complete,
cmd_gen_same_chipsel_addr,
cmd_gen_same_bank_addr,
cmd_gen_same_row_addr,
cmd_gen_same_col_addr,
cmd_gen_same_read_cmd,
cmd_gen_same_write_cmd,
cmd_gen_same_shadow_chipsel_addr,
cmd_gen_same_shadow_bank_addr,
cmd_gen_same_shadow_row_addr,
// input interface
cmd_gen_full,
cmd_valid,
cmd_address,
cmd_write,
cmd_read,
cmd_id,
cmd_multicast,
cmd_size,
cmd_priority,
cmd_autoprecharge,
// datapath interface
proc_busy,
proc_load,
proc_load_dataid,
proc_write,
proc_read,
proc_size,
proc_localid,
wdatap_free_id_valid, // from wdata path
wdatap_free_id_dataid, // from wdata path
rdatap_free_id_valid, // from rdata path
rdatap_free_id_dataid, // from rdata path
tbp_load_index,
data_complete,
data_rmw_complete,
// nodm and ecc signal
errcmd_ready,
errcmd_valid,
errcmd_chipsel,
errcmd_bank,
errcmd_row,
errcmd_column,
errcmd_size,
errcmd_localid,
data_partial_be,
// configuration ports
cfg_enable_cmd_split,
cfg_burst_length,
cfg_addr_order,
cfg_enable_ecc,
cfg_enable_no_dm,
cfg_col_addr_width,
cfg_row_addr_width,
cfg_bank_addr_width,
cfg_cs_addr_width
);
localparam MAX_COL = CFG_MEM_IF_COL_WIDTH;
localparam MAX_ROW = CFG_MEM_IF_ROW_WIDTH;
localparam MAX_BANK = CFG_MEM_IF_BA_WIDTH;
localparam MAX_CS = CFG_MEM_IF_CS_WIDTH;
localparam BUFFER_WIDTH = 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + CFG_DATA_ID_WIDTH + CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_COL_WIDTH;
localparam CFG_LOCAL_ADDR_BITSELECT_WIDTH = log2(CFG_LOCAL_ADDR_WIDTH);
localparam INT_LOCAL_ADDR_WIDTH = 2**CFG_LOCAL_ADDR_BITSELECT_WIDTH;
input ctl_clk;
input ctl_reset_n;
input tbp_full;
input [CFG_CTL_TBP_NUM-1:0] tbp_load;
input [CFG_CTL_TBP_NUM-1:0] tbp_read;
input [CFG_CTL_TBP_NUM-1:0] tbp_write;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_chipsel;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_bank;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_row;
input [(CFG_CTL_TBP_NUM*CFG_MEM_IF_COL_WIDTH)-1:0] tbp_col;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_CS_WIDTH)-1:0] tbp_shadow_chipsel;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_BA_WIDTH)-1:0] tbp_shadow_bank;
input [(CFG_CTL_SHADOW_TBP_NUM*CFG_MEM_IF_ROW_WIDTH)-1:0] tbp_shadow_row;
output cmd_gen_load;
output [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
output [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
output [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
output [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
output cmd_gen_write;
output cmd_gen_read;
output cmd_gen_multicast;
output [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
output [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
output [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
output cmd_gen_priority;
output cmd_gen_rmw_correct;
output cmd_gen_rmw_partial;
output cmd_gen_autopch;
output cmd_gen_complete;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
output [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
output [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
output cmd_gen_full;
input cmd_valid;
input [CFG_LOCAL_ADDR_WIDTH-1:0] cmd_address;
input cmd_write;
input cmd_read;
input [CFG_LOCAL_ID_WIDTH-1:0] cmd_id;
input cmd_multicast;
input [CFG_LOCAL_SIZE_WIDTH-1:0] cmd_size;
input cmd_priority;
input cmd_autoprecharge;
output proc_busy;
output proc_load;
output proc_load_dataid;
output proc_write;
output proc_read;
output [CFG_INT_SIZE_WIDTH-1:0] proc_size;
output [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
input wdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] wdatap_free_id_dataid;
input rdatap_free_id_valid;
input [CFG_DATA_ID_WIDTH-1:0] rdatap_free_id_dataid;
output [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
input [CFG_CTL_TBP_NUM-1:0] data_complete;
input data_rmw_complete;
output errcmd_ready; // high means cmd_gen accepts command
input errcmd_valid;
input [CFG_MEM_IF_CS_WIDTH-1:0] errcmd_chipsel;
input [CFG_MEM_IF_BA_WIDTH-1:0] errcmd_bank;
input [CFG_MEM_IF_ROW_WIDTH-1:0] errcmd_row;
input [CFG_MEM_IF_COL_WIDTH-1:0] errcmd_column;
input [CFG_INT_SIZE_WIDTH-1:0] errcmd_size;
input [CFG_LOCAL_ID_WIDTH - 1 : 0] errcmd_localid;
input data_partial_be;
input cfg_enable_cmd_split;
input [CFG_PORT_WIDTH_BURST_LENGTH-1:0] cfg_burst_length; // this contains immediate BL value, max is 31
input [CFG_PORT_WIDTH_ADDR_ORDER-1:0] cfg_addr_order; // 0 is chiprowbankcol , 1 is chipbankrowcol , 2 is rowchipbankcol
input cfg_enable_ecc;
input cfg_enable_no_dm;
input [CFG_PORT_WIDTH_COL_ADDR_WIDTH-1:0] cfg_col_addr_width;
input [CFG_PORT_WIDTH_ROW_ADDR_WIDTH-1:0] cfg_row_addr_width;
input [CFG_PORT_WIDTH_BANK_ADDR_WIDTH-1:0] cfg_bank_addr_width;
input [CFG_PORT_WIDTH_CS_ADDR_WIDTH-1:0] cfg_cs_addr_width;
// === address mapping
integer n;
integer j;
integer k;
integer m;
wire [INT_LOCAL_ADDR_WIDTH-1:0] int_cmd_address;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_col_addr;
// === command splitting block
reg [CFG_MEM_IF_CS_WIDTH-1:0] split_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] split_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] split_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] split_col_addr;
reg split_read;
reg split_write;
reg [CFG_INT_SIZE_WIDTH-1:0] split_size;
reg split_autopch;
reg split_multicast;
reg split_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] split_localid;
reg buf_read_req;
reg buf_write_req;
reg buf_autopch_req;
reg buf_multicast;
reg buf_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] buf_localid;
reg [CFG_LOCAL_SIZE_WIDTH:0] buf_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] buf_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] buf_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] buf_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] buf_col_addr;
reg [CFG_LOCAL_SIZE_WIDTH-1:0] decrmntd_size;
reg [CFG_MEM_IF_CS_WIDTH-1:0] incrmntd_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] incrmntd_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] incrmntd_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] incrmntd_col_addr;
reg [CFG_MEM_IF_CS_WIDTH-1:0] max_chip_from_csr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] max_bank_from_csr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] max_row_from_csr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] max_col_from_csr;
wire copy;
reg [2:0] unaligned_burst; // because planned max native size is 8, unaligned burst can be a max of 7
reg [3:0] native_size; // support native size up to 15, bl16 FR have native size of 8
wire require_gen;
reg deassert_ready;
reg registered;
reg generating;
// === ecc mux
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr_combi;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr_combi;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr_combi;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr_combi;
reg ecc_read_combi;
reg ecc_write_combi;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size_combi;
reg ecc_autopch_combi;
reg ecc_multicast_combi;
reg ecc_priority_combi;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid_combi;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid_combi;
reg [CFG_MEM_IF_CS_WIDTH-1:0] ecc_cs_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] ecc_bank_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] ecc_row_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] ecc_col_addr;
reg ecc_read;
reg ecc_write;
reg [CFG_INT_SIZE_WIDTH-1:0] ecc_size;
reg ecc_autopch;
reg ecc_multicast;
reg ecc_priority;
reg [CFG_LOCAL_ID_WIDTH-1:0] ecc_localid;
reg [CFG_DATA_ID_WIDTH-1:0] ecc_dataid;
reg ecc_int_combi;
reg errcmd_ready_combi;
reg partial_combi;
reg correct_combi;
reg partial_opr_combi;
reg ecc_int;
reg ecc_int_r;
reg errcmd_ready;
reg partial;
reg correct;
reg partial_opr;
wire mux_busy;
wire [CFG_MEM_IF_CS_WIDTH-1:0] muxed_cs_addr;
wire [CFG_MEM_IF_BA_WIDTH-1:0] muxed_bank_addr;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] muxed_row_addr;
wire [CFG_MEM_IF_COL_WIDTH-1:0] muxed_col_addr;
wire muxed_read;
wire muxed_write;
wire [CFG_INT_SIZE_WIDTH-1:0] muxed_size;
wire muxed_autopch;
wire muxed_multicast;
wire muxed_priority;
wire [CFG_LOCAL_ID_WIDTH-1:0] muxed_localid;
wire [CFG_DATA_ID_WIDTH-1:0] muxed_dataid;
wire muxed_complete;
wire muxed_correct;
wire muxed_partial;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_0;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_1;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_2;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_row_addr_3;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] muxed_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] split_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] split_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] split_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] split_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] split_same_write_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd_combi;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] ecc_same_write_cmd;
wire proc_busy;
wire proc_load;
wire proc_load_dataid;
wire proc_write;
wire proc_read;
wire [CFG_INT_SIZE_WIDTH-1:0] proc_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] proc_localid;
reg proc_busy_sig;
reg proc_ecc_busy_sig;
reg proc_load_sig;
reg proc_load_dataid_sig;
reg proc_write_sig;
reg proc_read_sig;
reg [CFG_INT_SIZE_WIDTH-1:0] proc_size_sig;
reg [CFG_LOCAL_ID_WIDTH-1:0] proc_localid_sig;
wire [CFG_CTL_TBP_NUM-1:0] tbp_load_index;
// === merging signals
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_one;
reg [log2(CFG_CTL_QUEUE_DEPTH)-1:0] last_minus_two;
wire can_merge;
reg [CFG_INT_SIZE_WIDTH-1:0] last_size;
reg last_read_req;
reg last_write_req;
reg last_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last_col_addr;
reg [CFG_INT_SIZE_WIDTH-1:0] last2_size;
reg last2_read_req;
reg last2_write_req;
reg last2_multicast;
reg [CFG_MEM_IF_CS_WIDTH-1:0] last2_chip_addr;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] last2_row_addr;
reg [CFG_MEM_IF_BA_WIDTH-1:0] last2_bank_addr;
reg [CFG_MEM_IF_COL_WIDTH-1:0] last2_col_addr;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_chipsel;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_bank;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] cfg_addr_bitsel_row;
// === queue
reg [BUFFER_WIDTH-1:0] pipe[CFG_CTL_QUEUE_DEPTH-1:0];
reg pipefull[CFG_CTL_QUEUE_DEPTH-1:0];
wire fetch;
wire [BUFFER_WIDTH-1:0] buffer_input;
wire write_to_queue;
wire queue_empty;
wire queue_full;
wire cmd_gen_load;
wire [CFG_MEM_IF_CS_WIDTH-1:0] cmd_gen_chipsel;
wire [CFG_MEM_IF_BA_WIDTH-1:0] cmd_gen_bank;
wire [CFG_MEM_IF_ROW_WIDTH-1:0] cmd_gen_row;
wire [CFG_MEM_IF_COL_WIDTH-1:0] cmd_gen_col;
wire cmd_gen_write;
wire cmd_gen_read;
wire cmd_gen_multicast;
wire [CFG_INT_SIZE_WIDTH-1:0] cmd_gen_size;
wire [CFG_LOCAL_ID_WIDTH-1:0] cmd_gen_localid;
wire [CFG_DATA_ID_WIDTH-1:0] cmd_gen_dataid;
wire cmd_gen_priority;
wire cmd_gen_rmw_correct;
wire cmd_gen_rmw_partial;
wire cmd_gen_autopch;
wire cmd_gen_complete;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_chipsel_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_bank_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_row_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_col_addr;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_read_cmd;
wire [CFG_CTL_TBP_NUM-1:0] cmd_gen_same_write_cmd;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_chipsel_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_bank_addr;
wire [CFG_CTL_SHADOW_TBP_NUM-1:0] cmd_gen_same_shadow_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] same_shadow_row_addr;
reg read [CFG_CTL_TBP_NUM-1:0];
reg write [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_CS_WIDTH-1:0] chipsel [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_BA_WIDTH-1:0] bank [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_ROW_WIDTH-1:0] row [CFG_CTL_TBP_NUM-1:0];
reg [CFG_MEM_IF_COL_WIDTH-1:0] col [CFG_CTL_TBP_NUM-1:0];
wire [CFG_MEM_IF_CS_WIDTH-1:0] shadow_chipsel [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_BA_WIDTH-1:0] shadow_bank [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire [CFG_MEM_IF_ROW_WIDTH-1:0] shadow_row [CFG_CTL_SHADOW_TBP_NUM-1:0];
wire one = 1'b1;
wire zero = 1'b0;
//======================= TBP info ===========================
generate
genvar p;
for (p=0; p<CFG_CTL_TBP_NUM; p=p+1)
begin : info_per_tbp
always @ (*)
begin
if (tbp_load[p])
begin
read [p] = cmd_gen_read;
write [p] = cmd_gen_write;
chipsel[p] = cmd_gen_chipsel;
bank [p] = cmd_gen_bank;
row [p] = cmd_gen_row;
col [p] = cmd_gen_col;
end
else
begin
read [p] = tbp_read [p];
write [p] = tbp_write [p];
chipsel[p] = tbp_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
bank [p] = tbp_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
row [p] = tbp_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
col [p] = tbp_col [(p+1)*CFG_MEM_IF_COL_WIDTH-1:p*CFG_MEM_IF_COL_WIDTH];
end
end
end
for (p=0; p<CFG_CTL_SHADOW_TBP_NUM; p=p+1)
begin : info_per_shadow_tbp
assign shadow_chipsel[p] = tbp_shadow_chipsel[(p+1)*CFG_MEM_IF_CS_WIDTH-1:p*CFG_MEM_IF_CS_WIDTH];
assign shadow_bank [p] = tbp_shadow_bank [(p+1)*CFG_MEM_IF_BA_WIDTH-1:p*CFG_MEM_IF_BA_WIDTH];
assign shadow_row [p] = tbp_shadow_row [(p+1)*CFG_MEM_IF_ROW_WIDTH-1:p*CFG_MEM_IF_ROW_WIDTH];
end
endgenerate
//======================= Address Remapping ===========================
// Pre-calculate int_*_addr chipsel, bank, row, col bit select offsets
always @ (*)
begin
// Row width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_row = cfg_cs_addr_width + cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_row = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_row = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Bank width info
if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL)
begin
cfg_addr_bitsel_bank = cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_bank = cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
// Chipsel width info
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL)
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
else // cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL || `MMR_ADDR_ORDER_CS_ROW_BA_COL
begin
cfg_addr_bitsel_chipsel = cfg_bank_addr_width + cfg_row_addr_width + cfg_col_addr_width - log2(CFG_DWIDTH_RATIO);
end
end
assign int_cmd_address = cmd_address;
// Supported addr order
// 0 - chip-row-bank-col
// 1 - chip-bank-row-col
// 2 - row-chip-bank-col
// Derive column address from address
always @(*)
begin : Col_addr_loop
int_col_addr[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0] = int_cmd_address[MIN_COL - log2(CFG_DWIDTH_RATIO) - 1 : 0];
for (n = MIN_COL - log2(CFG_DWIDTH_RATIO);n < MAX_COL;n = n + 1'b1)
begin
if (n < (cfg_col_addr_width - log2(CFG_DWIDTH_RATIO))) // Bit of col_addr can be configured in CSR using cfg_col_addr_width
begin
int_col_addr[n] = int_cmd_address[n];
end
else
begin
int_col_addr[n] = 1'b0;
end
end
int_col_addr = int_col_addr << log2(CFG_DWIDTH_RATIO);
end
// Derive row address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] row_addr_loop_2;
always @(*)
begin : Row_addr_loop
for (j = 0;j < MIN_ROW;j = j + 1'b1) // The purpose of using this for-loop is to get rid of "if (j < cfg_row_addr_width) begin" which causes multiplexers
begin
row_addr_loop_1 = j + cfg_addr_bitsel_row;
int_row_addr[j] = int_cmd_address[row_addr_loop_1];
end
for (j = MIN_ROW;j < MAX_ROW;j = j + 1'b1)
begin
row_addr_loop_2 = j + cfg_addr_bitsel_row;
if(j < cfg_row_addr_width) // Bit of row_addr can be configured in CSR using cfg_row_addr_width
begin
int_row_addr[j] = int_cmd_address[row_addr_loop_2];
end
else
begin
int_row_addr[j] = 1'b0;
end
end
end
// Derive bank address from address
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_1;
reg [CFG_LOCAL_ADDR_BITSELECT_WIDTH-1:0] bank_addr_loop_2;
always @(*)
begin : Bank_addr_loop
for (k = 0;k < MIN_BANK;k = k + 1'b1) // The purpose of using this for-loop is to get rid of "if (k < cfg_bank_addr_width) begin" which causes multiplexers
begin
bank_addr_loop_1 = k + cfg_addr_bitsel_bank;
int_bank_addr[k] = int_cmd_address[bank_addr_loop_1];
end
for (k = MIN_BANK;k < MAX_BANK;k = k + 1'b1)
begin
bank_addr_loop_2 = k + cfg_addr_bitsel_bank;
if (k < cfg_bank_addr_width) // Bit of bank_addr can be configured in CSR using cfg_bank_addr_width
begin
int_bank_addr[k] = int_cmd_address[bank_addr_loop_2];
end
else
begin
int_bank_addr[k] = 1'b0;
end
end
end
// Derive chipsel address from address
always @(*)
begin
m = 0;
if (cfg_cs_addr_width > 1'b0) // If cfg_cs_addr_width =< 1'b1, address doesn't have cs_addr bit
begin
for (m=0; m<MIN_CS; m=m+1'b1) // The purpose of using this for-loop is to get rid of "if (m < cfg_cs_addr_width) begin" which causes multiplexers
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
for (m=MIN_CS; m<MAX_CS; m=m+1'b1)
begin
if (m < cfg_cs_addr_width) // Bit of cs_addr can be configured in CSR using cfg_cs_addr_width
begin
int_cs_addr[m] = int_cmd_address[m + cfg_addr_bitsel_chipsel];
end
else
begin
int_cs_addr[m] = 1'b0;
end
end
end
else // If CFG_MEM_IF_CS_WIDTH = 1, then set cs_addr to 0 (one chip, one rank)
begin
int_cs_addr = {CFG_MEM_IF_CS_WIDTH{1'b0}};
end
end
//===================== end of address remapping =========================
//======================= burst splitting logic ===========================
assign cmd_gen_full = mux_busy | deassert_ready;
assign copy = ~cmd_gen_full & cmd_valid; // Copy current input command info into a register
assign require_gen = (cmd_size > native_size | unaligned_burst + cmd_size > native_size) & cfg_enable_cmd_split; // Indicate that current input command require splitting
// CSR address calculation
always @ (*)
begin
max_chip_from_csr = (2**cfg_cs_addr_width) - 1'b1;
max_bank_from_csr = (2**cfg_bank_addr_width) - 1'b1;
max_row_from_csr = (2**cfg_row_addr_width) - 1'b1;
max_col_from_csr = (2**cfg_col_addr_width) - 1'b1;
end
// Calculate native size for selected burstlength and controller rate
always @ (*)
begin
native_size = cfg_burst_length / CFG_DWIDTH_RATIO; // 1 for bl2 FR, 2 for bl8 HR, ...
end
always @(*)
begin
if (native_size == 1)
begin
unaligned_burst = 0;
end
else if (native_size == 2)
begin
unaligned_burst = {2'd0,int_col_addr[log2(CFG_DWIDTH_RATIO)]};
end
else if (native_size == 4)
begin
unaligned_burst = {1'd0,int_col_addr[(log2(CFG_DWIDTH_RATIO)+1):log2(CFG_DWIDTH_RATIO)]};
end
else // native_size == 8
begin
unaligned_burst = int_col_addr[(log2(CFG_DWIDTH_RATIO)+2):log2(CFG_DWIDTH_RATIO)];
end
end
// Deassert local_ready signal because need to split local command into multiple memory commands
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
deassert_ready <= 0;
end
else
begin
if (copy && require_gen)
begin
deassert_ready <= 1;
end
else if ((buf_size > native_size*2) && cfg_enable_cmd_split)
begin
deassert_ready <= 1;
end
else if (generating && ~mux_busy)
begin
deassert_ready <= 0;
end
end
end
// Assert register signal so that we will pass split command into TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
registered <= 0;
end
else
begin
if (copy && require_gen)
begin
registered <= 1;
end
else
begin
registered <= 0;
end
end
end
// Generating signal will notify that current command in under splitting process
// Signal stays high until the last memory burst aligned command is generated
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
generating <= 0;
end
else
begin
if (registered)
begin
generating <= 1;
end
else if ((generating && buf_size > native_size*2) && cfg_enable_cmd_split)
begin
generating <= 1;
end
else if (~mux_busy)
begin
generating <= 0;
end
end
end
// Determine the correct size
always @(*)
begin
if (!generating)
begin
if ((unaligned_burst + cmd_size < native_size) || !cfg_enable_cmd_split) //(local_size > 1 && !unaligned_burst)
begin
split_size = cmd_size;
end
else
begin
split_size = native_size - unaligned_burst;
end
end
else
begin
if (decrmntd_size > native_size - 1)
begin
split_size = native_size;
end
else
begin
split_size = decrmntd_size;
end
end
end
// MUX logic to determine where to take the command info from
always @(*)
begin
if (!generating) // not generating so take direct input from avalon if
begin
split_read = cmd_read & cmd_valid & ~registered;
split_write = cmd_write & cmd_valid & ~registered;
split_autopch = cmd_autoprecharge;
split_multicast = cmd_multicast;
split_priority = cmd_priority;
split_localid = cmd_id;
split_cs_addr = int_cs_addr;
split_bank_addr = int_bank_addr;
split_row_addr = int_row_addr;
split_col_addr = int_col_addr;
end
else // generating cmd so process buffer content
begin
split_read = buf_read_req;
split_write = buf_write_req;
split_autopch = buf_autopch_req;
split_multicast = buf_multicast;
split_priority = buf_priority;
split_localid = buf_localid;
split_cs_addr = incrmntd_cs_addr;
split_bank_addr = incrmntd_bank_addr;
split_row_addr = incrmntd_row_addr;
if (cfg_burst_length == 2)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:1],1'b0};
end
else if (cfg_burst_length == 4)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:2],2'b00};
end
else if (cfg_burst_length == 8)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:3],3'b000};
end
else // if (cfg_burst_length == 16)
begin
split_col_addr = {incrmntd_col_addr[CFG_MEM_IF_COL_WIDTH-1:4],4'b0000};
end
end
end
// Buffered command info, to be used in split process
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_read_req <= 1'b0;
buf_write_req <= 1'b0;
buf_autopch_req <= 1'b0;
buf_multicast <= 1'b0;
buf_priority <= 1'b0;
buf_localid <= 0;
end
else
begin
if (copy)
begin
buf_read_req <= cmd_read;
buf_write_req <= cmd_write;
buf_autopch_req <= cmd_autoprecharge;
buf_multicast <= cmd_multicast;
buf_priority <= cmd_priority;
buf_localid <= cmd_id;
end
end
end
// Keep track of command size during a split process
// will keep decreasing when a split command was sent to TBP
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_size <= 0;
end
else
begin
if (copy)
begin
buf_size <= cmd_size + unaligned_burst;
end
else if (!registered && buf_size > native_size && ~mux_busy)
begin
buf_size <= buf_size - native_size;
end
end
end
always @(*)
begin
decrmntd_size = buf_size - native_size;
end
// Keep track of command address during a split process
// will keep increasing when a split command was sent to TBP
// also takes into account address order
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
buf_cs_addr <= 0;
buf_bank_addr <= 0;
buf_row_addr <= 0;
buf_col_addr <= 0;
end
else
if (copy)
begin
buf_cs_addr <= int_cs_addr;
buf_bank_addr <= int_bank_addr;
buf_row_addr <= int_row_addr;
buf_col_addr <= int_col_addr;
end
else if (registered || (generating && ~mux_busy))
if ((cfg_burst_length == 16 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:4])
||
(cfg_burst_length == 8 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:3])
||
(cfg_burst_length == 4 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:2])
||
(cfg_burst_length == 2 && buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] == max_col_from_csr[CFG_MEM_IF_COL_WIDTH-1:1])
)
begin
if (cfg_burst_length == 16)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:4] <= 0;
else if (cfg_burst_length == 8)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:3] <= 0;
else if (cfg_burst_length == 4)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:2] <= 0;
else // if (cfg_burst_length == 2)
buf_col_addr[CFG_MEM_IF_COL_WIDTH-1:1] <= 0;
if (cfg_addr_order == `MMR_ADDR_ORDER_ROW_CS_BA_COL) // 2 is rowchipbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
begin
buf_cs_addr <= 0;
if (buf_row_addr == max_row_from_csr)
buf_row_addr <= 0;
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else if (cfg_addr_order == `MMR_ADDR_ORDER_CS_BA_ROW_COL) // 1 is chipbankrowcol
begin
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else // 0 is chiprowbankcol
begin
if (buf_bank_addr == max_bank_from_csr)
begin
buf_bank_addr <= 0;
if (buf_row_addr == max_row_from_csr)
begin
buf_row_addr <= 0;
if (buf_cs_addr == max_chip_from_csr)
buf_cs_addr <= 0;
else
buf_cs_addr <= buf_cs_addr + 1'b1;
end
else
buf_row_addr <= buf_row_addr + 1'b1;
end
else
buf_bank_addr <= buf_bank_addr + 1'b1;
end
end
else
buf_col_addr <= buf_col_addr + cfg_burst_length;
end
always @(*)
begin
incrmntd_cs_addr = buf_cs_addr;
incrmntd_bank_addr = buf_bank_addr;
incrmntd_row_addr = buf_row_addr;
incrmntd_col_addr = buf_col_addr;
end
//======================= end of burst splitting logic ===========================
//====================== ecc mux start ========================
// ECC process info
always @ (*)
begin
ecc_int_combi = ecc_int;
correct_combi = correct;
partial_combi = partial;
errcmd_ready_combi = errcmd_ready;
ecc_dataid_combi = ecc_dataid;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert partial after ECC write was sent to TBP
begin
partial_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (correct)
begin
errcmd_ready_combi = 1'b0;
if (ecc_write && !queue_full && wdatap_free_id_valid) // deassert correct after ECC write was sent to TBP
begin
correct_combi = 1'b0;
ecc_int_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // if there is a auto correction request
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b1;
partial_combi = 1'b0;
errcmd_ready_combi = 1'b1;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // if there is a write request in no-DM or ECC case
begin
ecc_int_combi = 1'b1;
correct_combi = 1'b0;
partial_combi = 1'b1;
ecc_dataid_combi = wdatap_free_id_dataid;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int <= 0;
correct <= 0;
partial <= 0;
errcmd_ready <= 0;
ecc_dataid <= 0;
end
else
begin
ecc_int <= ecc_int_combi;
correct <= correct_combi;
partial <= partial_combi;
errcmd_ready <= errcmd_ready_combi;
ecc_dataid <= ecc_dataid_combi;
end
end
// Buffer for ECC command information
always @ (*)
begin
if (partial || correct)
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
else if (cfg_enable_ecc && errcmd_valid) // take in error command info
begin
ecc_cs_addr_combi = errcmd_chipsel;
ecc_bank_addr_combi = errcmd_bank;
ecc_row_addr_combi = errcmd_row;
ecc_col_addr_combi = errcmd_column;
ecc_size_combi = errcmd_size;
ecc_autopch_combi = 1'b0;
ecc_multicast_combi = 1'b0;
ecc_localid_combi = errcmd_localid;
ecc_priority_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy) // take in command info from split logic
begin
ecc_cs_addr_combi = split_cs_addr;
ecc_bank_addr_combi = split_bank_addr;
ecc_row_addr_combi = split_row_addr;
ecc_col_addr_combi = split_col_addr;
ecc_size_combi = split_size;
ecc_autopch_combi = split_autopch;
ecc_multicast_combi = split_multicast;
ecc_localid_combi = split_localid;
ecc_priority_combi = split_priority;
end
else
begin
ecc_cs_addr_combi = ecc_cs_addr;
ecc_bank_addr_combi = ecc_bank_addr;
ecc_row_addr_combi = ecc_row_addr;
ecc_col_addr_combi = ecc_col_addr;
ecc_size_combi = ecc_size;
ecc_autopch_combi = ecc_autopch;
ecc_multicast_combi = ecc_multicast;
ecc_localid_combi = ecc_localid;
ecc_priority_combi = ecc_priority;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_cs_addr <= 0;
ecc_bank_addr <= 0;
ecc_row_addr <= 0;
ecc_col_addr <= 0;
ecc_size <= 0;
ecc_autopch <= 0;
ecc_multicast <= 0;
ecc_localid <= 0;
ecc_priority <= 0;
end
else
begin
ecc_cs_addr <= ecc_cs_addr_combi;
ecc_bank_addr <= ecc_bank_addr_combi;
ecc_row_addr <= ecc_row_addr_combi;
ecc_col_addr <= ecc_col_addr_combi;
ecc_size <= ecc_size_combi;
ecc_autopch <= ecc_autopch_combi;
ecc_multicast <= ecc_multicast_combi;
ecc_localid <= ecc_localid_combi;
ecc_priority <= ecc_priority_combi;
end
end
// Logic to determine when to issue ECC read/write request
// based on partial_be info from wdata path
// if partial_be is high, it issues a read-modify-write command
// else issues normal write command
always @ (*)
begin
ecc_read_combi = ecc_read;
ecc_write_combi = ecc_write;
partial_opr_combi = partial_opr;
if (partial)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
partial_opr_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (data_complete[0]) // wait for data_complete from wdata path
begin
if (!data_partial_be) // if not partial_be, issues normal write
begin
ecc_write_combi = 1'b1;
end
else // else issues a RMW's read
begin
ecc_read_combi = 1'b1;
partial_opr_combi = 1'b1;
end
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
begin
ecc_write_combi = 1'b1;
end
else
begin
ecc_write_combi = 1'b0;
end
end
end
else if (correct)
begin
if (ecc_write && !queue_full && wdatap_free_id_valid)
begin
ecc_write_combi = 1'b0;
end
else if (ecc_read && !queue_full && rdatap_free_id_valid)
begin
ecc_read_combi = 1'b0;
end
else if (!ecc_write && !ecc_read)
begin
if (data_rmw_complete) // waits till RMW data is complate before issuing RMW's write
ecc_write_combi = 1'b1;
else
ecc_write_combi = 1'b0;
end
end
else if (cfg_enable_ecc && errcmd_valid) // issues a RMW's read when there is a error correction
begin
ecc_read_combi = 1'b1;
ecc_write_combi = 1'b0;
end
else if ((cfg_enable_no_dm || cfg_enable_ecc) && split_write && !mux_busy)
begin
ecc_read_combi = 1'b0;
ecc_write_combi = 1'b0;
end
end
always @(posedge ctl_clk, negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_read <= 1'b0;
ecc_write <= 1'b0;
partial_opr <= 1'b0;
end
else
begin
ecc_read <= ecc_read_combi;
ecc_write <= ecc_write_combi;
partial_opr <= partial_opr_combi;
end
end
// We only need to gate split_read/write in non cmd_gen registered output mode
assign mux_busy = (
queue_full |
errcmd_valid |
(
(cfg_enable_no_dm | cfg_enable_ecc) &
(
ecc_int |
(
!(CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE) &
(
(split_read & ~rdatap_free_id_valid) |
(split_write & ~wdatap_free_id_valid)
)
)
)
)
);
assign muxed_cs_addr = ecc_int ? ecc_cs_addr : split_cs_addr;
assign muxed_bank_addr = ecc_int ? ecc_bank_addr : split_bank_addr;
assign muxed_row_addr = ecc_int ? ecc_row_addr : split_row_addr;
assign muxed_col_addr = ecc_int ? ecc_col_addr : split_col_addr;
assign muxed_read = ecc_int ? (CFG_CMD_GEN_OUTPUT_REG ? (ecc_read & rdatap_free_id_valid) : ecc_read) : split_read & ~errcmd_valid; // We only need to check for free ID valid in CMD_GEN_OUTPUT_REG mode
assign muxed_write = (cfg_enable_no_dm || cfg_enable_ecc) ? ecc_write : split_write & ~errcmd_valid;
assign muxed_size = ecc_int ? ecc_size : split_size;
assign muxed_autopch = ecc_int ? ecc_autopch : split_autopch;
assign muxed_multicast = ecc_int ? ecc_multicast : split_multicast;
assign muxed_localid = ecc_int ? ecc_localid : split_localid;
assign muxed_priority = ecc_int ? ecc_priority : split_priority;
assign muxed_dataid = ecc_int ? ecc_dataid : rdatap_free_id_dataid;
assign muxed_complete = ecc_int ? 1'b1 : split_read;
assign muxed_correct = ecc_int ? correct : 1'b0;
assign muxed_partial = ecc_int ? partial_opr : 1'b0;
assign muxed_same_chipsel_addr = ecc_int_r ? ecc_same_chipsel_addr : split_same_chipsel_addr;
assign muxed_same_bank_addr = ecc_int_r ? ecc_same_bank_addr : split_same_bank_addr;
assign muxed_same_row_addr_0 = ecc_int_r ? ecc_same_row_addr_0 : split_same_row_addr_0;
assign muxed_same_row_addr_1 = ecc_int_r ? ecc_same_row_addr_1 : split_same_row_addr_1;
assign muxed_same_row_addr_2 = ecc_int_r ? ecc_same_row_addr_2 : split_same_row_addr_2;
assign muxed_same_row_addr_3 = ecc_int_r ? ecc_same_row_addr_3 : split_same_row_addr_3;
assign muxed_same_col_addr = ecc_int_r ? ecc_same_col_addr : split_same_col_addr;
assign muxed_same_read_cmd = ecc_int_r ? ecc_same_read_cmd : split_same_read_cmd;
assign muxed_same_write_cmd = ecc_int_r ? ecc_same_write_cmd : split_same_write_cmd;
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
ecc_int_r <= 1'b0;
end
else
begin
ecc_int_r <= ecc_int;
end
end
// Address comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (split_cs_addr == chipsel[j])
begin
split_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
split_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (split_bank_addr == bank[j])
begin
split_same_bank_addr_combi[j] = 1'b1;
end
else
begin
split_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (split_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_0_combi[j] = 1'b0;
end
if (split_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_1_combi[j] = 1'b0;
end
if (split_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_2_combi[j] = 1'b0;
end
if (split_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
split_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
split_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (split_col_addr == col[j])
begin
split_same_col_addr_combi[j] = 1'b1;
end
else
begin
split_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (split_read == read[j])
begin
split_same_read_cmd_combi[j] = 1'b1;
end
else
begin
split_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (split_write == write[j])
begin
split_same_write_cmd_combi[j] = 1'b1;
end
else
begin
split_same_write_cmd_combi[j] = 1'b0;
end
end
end
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
// Chipselect address
if (ecc_cs_addr == chipsel[j])
begin
ecc_same_chipsel_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_chipsel_addr_combi[j] = 1'b0;
end
// Bank addr
if (ecc_bank_addr == bank[j])
begin
ecc_same_bank_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_bank_addr_combi[j] = 1'b0;
end
// Row addr
if (ecc_row_addr[(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(1 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (0 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_0_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_0_combi[j] = 1'b0;
end
if (ecc_row_addr[(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(2 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (1 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_1_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_1_combi[j] = 1'b0;
end
if (ecc_row_addr[(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][(3 * (CFG_MEM_IF_ROW_WIDTH / 4)) - 1 : (2 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_2_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_2_combi[j] = 1'b0;
end
if (ecc_row_addr[CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))] == row[j][CFG_MEM_IF_ROW_WIDTH - 1 : (3 * (CFG_MEM_IF_ROW_WIDTH / 4))])
begin
ecc_same_row_addr_3_combi[j] = 1'b1;
end
else
begin
ecc_same_row_addr_3_combi[j] = 1'b0;
end
// Col addr
if (ecc_col_addr == col[j])
begin
ecc_same_col_addr_combi[j] = 1'b1;
end
else
begin
ecc_same_col_addr_combi[j] = 1'b0;
end
// Read command
if (ecc_read == read[j])
begin
ecc_same_read_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_read_cmd_combi[j] = 1'b0;
end
// Write command
if (ecc_write == write[j])
begin
ecc_same_write_cmd_combi[j] = 1'b1;
end
else
begin
ecc_same_write_cmd_combi[j] = 1'b0;
end
end
end
generate
if (CFG_CMD_GEN_OUTPUT_REG & !CFG_ENABLE_QUEUE)
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
proc_write_sig <= 0;
proc_read_sig <= 0;
proc_size_sig <= 0;
proc_localid_sig <= 0;
proc_load_dataid_sig <= 0;
proc_ecc_busy_sig <= 0;
end
else
begin
if (proc_busy_sig)
begin
// Do nothing, keep old value
end
else
begin
proc_load_dataid_sig <= ~(ecc_int & (ecc_read | ecc_write));
if (ecc_int)
begin
proc_write_sig <= ecc_write & correct;
proc_read_sig <= ecc_read;
proc_size_sig <= ecc_size;
proc_localid_sig <= ecc_localid;
proc_ecc_busy_sig <= (ecc_read & ~rdatap_free_id_valid) | ((ecc_write & correct) & ~wdatap_free_id_valid);
end
else
begin
proc_write_sig <= split_write & ~errcmd_valid;
proc_read_sig <= split_read & ~errcmd_valid;
proc_size_sig <= split_size;
proc_localid_sig <= split_localid;
proc_ecc_busy_sig <= 1'b0;
end
end
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
split_same_chipsel_addr <= 0;
split_same_bank_addr <= 0;
split_same_row_addr_0 <= 0;
split_same_row_addr_1 <= 0;
split_same_row_addr_2 <= 0;
split_same_row_addr_3 <= 0;
split_same_col_addr <= 0;
split_same_read_cmd <= 0;
split_same_write_cmd <= 0;
ecc_same_chipsel_addr <= 0;
ecc_same_bank_addr <= 0;
ecc_same_row_addr_0 <= 0;
ecc_same_row_addr_1 <= 0;
ecc_same_row_addr_2 <= 0;
ecc_same_row_addr_3 <= 0;
ecc_same_col_addr <= 0;
ecc_same_read_cmd <= 0;
ecc_same_write_cmd <= 0;
end
else
begin
split_same_chipsel_addr <= split_same_chipsel_addr_combi;
split_same_bank_addr <= split_same_bank_addr_combi;
split_same_row_addr_0 <= split_same_row_addr_0_combi;
split_same_row_addr_1 <= split_same_row_addr_1_combi;
split_same_row_addr_2 <= split_same_row_addr_2_combi;
split_same_row_addr_3 <= split_same_row_addr_3_combi;
split_same_col_addr <= split_same_col_addr_combi;
split_same_read_cmd <= split_same_read_cmd_combi;
split_same_write_cmd <= split_same_write_cmd_combi;
ecc_same_chipsel_addr <= ecc_same_chipsel_addr_combi;
ecc_same_bank_addr <= ecc_same_bank_addr_combi;
ecc_same_row_addr_0 <= ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 <= ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 <= ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 <= ecc_same_row_addr_3_combi;
ecc_same_col_addr <= ecc_same_col_addr_combi;
ecc_same_read_cmd <= ecc_same_read_cmd_combi;
ecc_same_write_cmd <= ecc_same_write_cmd_combi;
end
end
end
else
begin
always @ (*)
begin
proc_busy_sig = queue_full;
proc_ecc_busy_sig = zero;
proc_load_sig = (proc_read_sig | proc_write_sig) & ((proc_read_sig & rdatap_free_id_valid) | (proc_write_sig & wdatap_free_id_valid));
proc_load_dataid_sig = ~(ecc_int & (ecc_read | ecc_write));
proc_write_sig = ecc_int ? ecc_write & correct : split_write & ~errcmd_valid;
proc_read_sig = ecc_int ? ecc_read : split_read & ~errcmd_valid;
proc_size_sig = ecc_int ? ecc_size : split_size;
proc_localid_sig = ecc_int ? ecc_localid : split_localid;
end
always @ (*)
begin
split_same_chipsel_addr = split_same_chipsel_addr_combi;
split_same_bank_addr = split_same_bank_addr_combi;
split_same_row_addr_0 = split_same_row_addr_0_combi;
split_same_row_addr_1 = split_same_row_addr_1_combi;
split_same_row_addr_2 = split_same_row_addr_2_combi;
split_same_row_addr_3 = split_same_row_addr_3_combi;
split_same_col_addr = split_same_col_addr_combi;
split_same_read_cmd = split_same_read_cmd_combi;
split_same_write_cmd = split_same_write_cmd_combi;
ecc_same_chipsel_addr = ecc_same_chipsel_addr_combi;
ecc_same_bank_addr = ecc_same_bank_addr_combi;
ecc_same_row_addr_0 = ecc_same_row_addr_0_combi;
ecc_same_row_addr_1 = ecc_same_row_addr_1_combi;
ecc_same_row_addr_2 = ecc_same_row_addr_2_combi;
ecc_same_row_addr_3 = ecc_same_row_addr_3_combi;
ecc_same_col_addr = ecc_same_col_addr_combi;
ecc_same_read_cmd = ecc_same_read_cmd_combi;
ecc_same_write_cmd = ecc_same_write_cmd_combi;
end
end
endgenerate
//====================== ecc mux end ========================
//====================== sequential address detector ========================
//Last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n) begin
if (!ctl_reset_n)
begin
last_read_req <= 1'b0;
last_write_req <= 1'b0;
last_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last_read_req <= muxed_read;
last_write_req <= muxed_write;
last_multicast <= muxed_multicast;
last_chip_addr <= muxed_cs_addr;
last_bank_addr <= muxed_bank_addr;
last_row_addr <= muxed_row_addr;
last_col_addr <= muxed_col_addr;
last_size <= muxed_size;
end
else if (can_merge)
begin
last_size <= 2;
end
end
//Second last pipeline entry
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last2_read_req <= 1'b0;
last2_write_req <= 1'b0;
last2_chip_addr <= {CFG_MEM_IF_CS_WIDTH{1'b0}};
last2_row_addr <= {CFG_MEM_IF_ROW_WIDTH{1'b0}};
last2_bank_addr <= {CFG_MEM_IF_BA_WIDTH{1'b0}};
last2_col_addr <= {CFG_MEM_IF_COL_WIDTH{1'b0}};
last2_size <= {CFG_INT_SIZE_WIDTH{1'b0}};
last2_multicast <= 1'b0;
end
else if (write_to_queue)
begin
last2_read_req <= last_read_req;
last2_write_req <= last_write_req;
last2_multicast <= last_multicast;
last2_chip_addr <= last_chip_addr;
last2_bank_addr <= last_bank_addr;
last2_row_addr <= last_row_addr;
last2_col_addr <= last_col_addr;
last2_size <= last_size;
end
end
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
last <= 0;
last_minus_one <= 0;
last_minus_two <= 0;
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
if (write_to_queue)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
else
begin
last <= last - 2;
last_minus_one <= last - 3;
last_minus_two <= last - 4;
end
end
else
begin
if (write_to_queue) begin
// do nothing
end
else if (last != 0)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
// do nothing
end
else if (!queue_empty)
begin
last <= last + 1;
last_minus_one <= last;
last_minus_two <= last - 1;
end
end
else if (can_merge)
begin
last <= last - 1;
last_minus_one <= last - 2;
last_minus_two <= last - 3;
end
end
end
// Merging logic
assign can_merge = (CFG_ENABLE_BURST_MERGE == 1) ?
last != 0
& pipefull[last]
& last2_read_req == last_read_req
& last2_write_req == last_write_req
& last2_multicast == last_multicast
& last2_chip_addr == last_chip_addr
& last2_bank_addr == last_bank_addr
& last2_row_addr == last_row_addr
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 2]) : (last2_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3] == last_col_addr[CFG_MEM_IF_COL_WIDTH-1 : 3]) )
& ((CFG_DWIDTH_RATIO == 2) ? (last2_col_addr[1] == 0 & last_col_addr[1] == 1) : (last2_col_addr[2] == 0 & last_col_addr[2] == 1) )
& last2_size == 1 & last_size == 1
:
1'b0;
//=================== end of sequential address detector ====================
//=============================== queue ===================================
// mapping of buffer_input
assign buffer_input = {muxed_read,muxed_write,muxed_multicast,muxed_autopch,muxed_priority,muxed_complete,muxed_correct,muxed_partial,muxed_dataid,muxed_localid,muxed_size,muxed_cs_addr,muxed_row_addr,muxed_bank_addr,muxed_col_addr};
generate
if (CFG_ENABLE_QUEUE == 1)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
// TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_TBP_NUM; j=j+1)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr = muxed_same_row_addr_0 & muxed_same_row_addr_1 & muxed_same_row_addr_2 & muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
// Chipselect address
if (cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
assign queue_empty = !pipefull[0];
assign queue_full = pipefull[CFG_CTL_QUEUE_DEPTH-1] | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
assign cmd_gen_load = pipefull[0] & ((cfg_enable_no_dm | cfg_enable_ecc) | ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid)));
assign cmd_gen_read = pipe[0][BUFFER_WIDTH-1];
assign cmd_gen_write = pipe[0][BUFFER_WIDTH-2];
assign cmd_gen_multicast = pipe[0][BUFFER_WIDTH-3];
assign cmd_gen_autopch = pipe[0][BUFFER_WIDTH-4];
assign cmd_gen_priority = pipe[0][BUFFER_WIDTH-5];
assign cmd_gen_complete = pipe[0][BUFFER_WIDTH-6];
assign cmd_gen_rmw_correct = pipe[0][BUFFER_WIDTH-7];
assign cmd_gen_rmw_partial = pipe[0][BUFFER_WIDTH-8];
assign cmd_gen_dataid = cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid;
assign cmd_gen_localid = pipe[0][CFG_LOCAL_ID_WIDTH + CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_size = pipe[0][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_chipsel = pipe[0][CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_row = pipe[0][CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_bank = pipe[0][CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_COL_WIDTH];
assign cmd_gen_col = pipe[0][CFG_MEM_IF_COL_WIDTH - 1 : 0];
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
else
begin
wire int_queue_full;
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr;
reg int_register_valid;
reg [CFG_MEM_IF_CS_WIDTH-1:0] int_cmd_gen_chipsel;
reg [CFG_MEM_IF_BA_WIDTH-1:0] int_cmd_gen_bank;
reg [CFG_MEM_IF_ROW_WIDTH-1:0] int_cmd_gen_row;
reg [CFG_MEM_IF_COL_WIDTH-1:0] int_cmd_gen_col;
reg int_cmd_gen_write;
reg int_cmd_gen_read;
reg int_cmd_gen_multicast;
reg [CFG_INT_SIZE_WIDTH-1:0] int_cmd_gen_size;
reg [CFG_LOCAL_ID_WIDTH-1:0] int_cmd_gen_localid;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid;
reg int_cmd_gen_priority;
reg int_cmd_gen_rmw_correct;
reg int_cmd_gen_rmw_partial;
reg int_cmd_gen_autopch;
reg int_cmd_gen_complete;
reg [CFG_DATA_ID_WIDTH-1:0] int_cmd_gen_dataid_mux;
// TBP address and command comparison logic
always @ (*)
begin
int_same_chipsel_addr = muxed_same_chipsel_addr;
int_same_bank_addr = muxed_same_bank_addr;
int_same_row_addr_0 = muxed_same_row_addr_0;
int_same_row_addr_1 = muxed_same_row_addr_1;
int_same_row_addr_2 = muxed_same_row_addr_2;
int_same_row_addr_3 = muxed_same_row_addr_3;
int_same_col_addr = muxed_same_col_addr;
int_same_read_cmd = muxed_same_read_cmd;
int_same_write_cmd = muxed_same_write_cmd;
end
// Shadow TBP address and command comparison logic
always @ (*)
begin
for(j=0; j<CFG_CTL_SHADOW_TBP_NUM; j=j+1)
begin
if (int_queue_full)
begin
// Chipselect address
if (int_cmd_gen_chipsel == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (int_cmd_gen_bank == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (int_cmd_gen_row == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
else
begin
// Chipselect address
if (muxed_cs_addr == shadow_chipsel[j])
begin
int_same_shadow_chipsel_addr[j] = 1'b1;
end
else
begin
int_same_shadow_chipsel_addr[j] = 1'b0;
end
// Bank addr
if (muxed_bank_addr == shadow_bank[j])
begin
int_same_shadow_bank_addr[j] = 1'b1;
end
else
begin
int_same_shadow_bank_addr[j] = 1'b0;
end
// Row addr
if (muxed_row_addr == shadow_row[j])
begin
int_same_shadow_row_addr[j] = 1'b1;
end
else
begin
int_same_shadow_row_addr[j] = 1'b0;
end
end
end
end
if (CFG_CMD_GEN_OUTPUT_REG)
begin
reg [CFG_CTL_TBP_NUM-1:0] int_same_chipsel_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_bank_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_0_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_1_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_2_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_row_addr_3_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_col_addr_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_read_cmd_r;
reg [CFG_CTL_TBP_NUM-1:0] int_same_write_cmd_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_chipsel_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_bank_addr_r;
reg [CFG_CTL_SHADOW_TBP_NUM-1:0] int_same_shadow_row_addr_r;
reg int_ecc_int;
reg int_queue_full_r;
assign int_queue_full = (tbp_full & int_register_valid) | ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid));
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_queue_full_r <= 1'b0;
end
else
begin
int_queue_full_r <= int_queue_full;
end
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 0;
int_cmd_gen_write <= 0;
int_cmd_gen_multicast <= 0;
int_cmd_gen_autopch <= 0;
int_cmd_gen_priority <= 0;
int_cmd_gen_complete <= 0;
int_cmd_gen_rmw_correct <= 0;
int_cmd_gen_rmw_partial <= 0;
int_cmd_gen_dataid <= 0;
int_cmd_gen_localid <= 0;
int_cmd_gen_size <= 0;
int_cmd_gen_chipsel <= 0;
int_cmd_gen_row <= 0;
int_cmd_gen_bank <= 0;
int_cmd_gen_col <= 0;
int_ecc_int <= 0;
end
else
begin
if (fetch)
begin
int_register_valid <= 1'b0;
int_cmd_gen_read <= 1'b0;
int_cmd_gen_write <= 1'b0;
end
if (!int_queue_full)
begin
if (muxed_read || muxed_write)
begin
int_register_valid <= 1'b1;
end
int_cmd_gen_read <= muxed_read;
int_cmd_gen_write <= muxed_write;
int_cmd_gen_multicast <= muxed_multicast;
int_cmd_gen_autopch <= muxed_autopch;
int_cmd_gen_priority <= muxed_priority;
int_cmd_gen_complete <= muxed_complete;
int_cmd_gen_rmw_correct <= muxed_correct;
int_cmd_gen_rmw_partial <= muxed_partial;
int_cmd_gen_dataid <= muxed_dataid;
int_cmd_gen_localid <= muxed_localid;
int_cmd_gen_size <= muxed_size;
int_cmd_gen_chipsel <= muxed_cs_addr;
int_cmd_gen_row <= muxed_row_addr;
int_cmd_gen_bank <= muxed_bank_addr;
int_cmd_gen_col <= muxed_col_addr;
int_ecc_int <= ecc_int;
end
end
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_ecc_int ? int_cmd_gen_dataid : rdatap_free_id_dataid;
end
always @ (posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
int_same_chipsel_addr_r <= 0;
int_same_bank_addr_r <= 0;
int_same_row_addr_0_r <= 0;
int_same_row_addr_1_r <= 0;
int_same_row_addr_2_r <= 0;
int_same_row_addr_3_r <= 0;
int_same_col_addr_r <= 0;
int_same_read_cmd_r <= 0;
int_same_write_cmd_r <= 0;
int_same_shadow_chipsel_addr_r <= 0;
int_same_shadow_bank_addr_r <= 0;
int_same_shadow_row_addr_r <= 0;
end
else
begin
if (int_queue_full & !int_queue_full_r) // positive edge detector
begin
int_same_chipsel_addr_r <= int_same_chipsel_addr;
int_same_bank_addr_r <= int_same_bank_addr;
int_same_row_addr_0_r <= int_same_row_addr_0;
int_same_row_addr_1_r <= int_same_row_addr_1;
int_same_row_addr_2_r <= int_same_row_addr_2;
int_same_row_addr_3_r <= int_same_row_addr_3;
int_same_col_addr_r <= int_same_col_addr;
int_same_read_cmd_r <= int_same_read_cmd;
int_same_write_cmd_r <= int_same_write_cmd;
end
int_same_shadow_chipsel_addr_r <= int_same_shadow_chipsel_addr;
int_same_shadow_bank_addr_r <= int_same_shadow_bank_addr;
int_same_shadow_row_addr_r <= int_same_shadow_row_addr;
end
end
always @ (*)
begin
if (!int_queue_full_r)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1 & int_same_row_addr_2 & int_same_row_addr_3;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
end
else
begin
same_chipsel_addr = int_same_chipsel_addr_r;
same_bank_addr = int_same_bank_addr_r;
same_row_addr = int_same_row_addr_0_r & int_same_row_addr_1_r & int_same_row_addr_2_r & int_same_row_addr_3_r;
same_col_addr = int_same_col_addr_r;
same_read_cmd = int_same_read_cmd_r;
same_write_cmd = int_same_write_cmd_r;
end
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr_r;
same_shadow_bank_addr = int_same_shadow_bank_addr_r;
same_shadow_row_addr = int_same_shadow_row_addr_r;
end
end
else
begin
assign int_queue_full = tbp_full | (~(cfg_enable_no_dm | cfg_enable_ecc) & ((cmd_gen_read & ~rdatap_free_id_valid) | (~cmd_gen_read & ~wdatap_free_id_valid)));
always @ (*)
begin
int_register_valid = one;
int_cmd_gen_read = muxed_read;
int_cmd_gen_write = muxed_write;
int_cmd_gen_multicast = muxed_multicast;
int_cmd_gen_autopch = muxed_autopch;
int_cmd_gen_priority = muxed_priority;
int_cmd_gen_complete = muxed_complete;
int_cmd_gen_rmw_correct = muxed_correct;
int_cmd_gen_rmw_partial = muxed_partial;
int_cmd_gen_dataid = muxed_dataid;
int_cmd_gen_localid = muxed_localid;
int_cmd_gen_size = muxed_size;
int_cmd_gen_chipsel = muxed_cs_addr;
int_cmd_gen_row = muxed_row_addr;
int_cmd_gen_bank = muxed_bank_addr;
int_cmd_gen_col = muxed_col_addr;
end
always @ (*)
begin
int_cmd_gen_dataid_mux = int_cmd_gen_dataid;
end
always @ (*)
begin
same_chipsel_addr = int_same_chipsel_addr;
same_bank_addr = int_same_bank_addr;
same_row_addr = int_same_row_addr_0 & int_same_row_addr_1;
same_col_addr = int_same_col_addr;
same_read_cmd = int_same_read_cmd;
same_write_cmd = int_same_write_cmd;
same_shadow_chipsel_addr = int_same_shadow_chipsel_addr;
same_shadow_bank_addr = int_same_shadow_bank_addr;
same_shadow_row_addr = int_same_shadow_row_addr;
end
end
assign queue_empty = 1;
assign queue_full = int_queue_full;
assign cmd_gen_load = (cmd_gen_read | cmd_gen_write) & ((cmd_gen_read & rdatap_free_id_valid) | (~cmd_gen_read & wdatap_free_id_valid));
assign cmd_gen_read = int_cmd_gen_read;
assign cmd_gen_write = int_cmd_gen_write;
assign cmd_gen_multicast = int_cmd_gen_multicast;
assign cmd_gen_autopch = int_cmd_gen_autopch;
assign cmd_gen_priority = int_cmd_gen_priority;
assign cmd_gen_complete = int_cmd_gen_complete;
assign cmd_gen_rmw_correct = int_cmd_gen_rmw_correct;
assign cmd_gen_rmw_partial = int_cmd_gen_rmw_partial;
assign cmd_gen_dataid = (cfg_enable_no_dm || cfg_enable_ecc) ? int_cmd_gen_dataid_mux : (cmd_gen_read ? rdatap_free_id_dataid : wdatap_free_id_dataid);
assign cmd_gen_localid = int_cmd_gen_localid;
assign cmd_gen_size = int_cmd_gen_size;
assign cmd_gen_chipsel = int_cmd_gen_chipsel;
assign cmd_gen_row = int_cmd_gen_row;
assign cmd_gen_bank = int_cmd_gen_bank;
assign cmd_gen_col = int_cmd_gen_col;
assign cmd_gen_same_chipsel_addr = same_chipsel_addr;
assign cmd_gen_same_bank_addr = same_bank_addr;
assign cmd_gen_same_row_addr = same_row_addr;
assign cmd_gen_same_col_addr = same_col_addr;
assign cmd_gen_same_read_cmd = same_read_cmd;
assign cmd_gen_same_write_cmd = same_write_cmd;
assign cmd_gen_same_shadow_chipsel_addr = same_shadow_chipsel_addr;
assign cmd_gen_same_shadow_bank_addr = same_shadow_bank_addr;
assign cmd_gen_same_shadow_row_addr = same_shadow_row_addr;
end
endgenerate
// avalon_write_req & avalon_read_req is AND with internal_ready in alt_ddrx_avalon_if.v
assign write_to_queue = (muxed_read | muxed_write) & ~queue_full;
assign fetch = cmd_gen_load & ~tbp_full;
// proc signals to datapath
assign proc_busy = (cfg_enable_no_dm || cfg_enable_ecc) ? (proc_busy_sig | proc_ecc_busy_sig) : tbp_full;
assign proc_load = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_sig : cmd_gen_load;
assign proc_load_dataid= (cfg_enable_no_dm || cfg_enable_ecc) ? proc_load_dataid_sig : cmd_gen_load;
assign proc_write = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_write_sig : cmd_gen_write;
assign proc_read = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_read_sig : cmd_gen_read;
assign proc_size = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_size_sig : cmd_gen_size;
assign proc_localid = (cfg_enable_no_dm || cfg_enable_ecc) ? proc_localid_sig : cmd_gen_localid;
assign tbp_load_index = (cfg_enable_no_dm || cfg_enable_ecc) ? 1 : tbp_load;
//pipefull and pipe register chain
//feed 0 to pipefull entry that is empty
always @(posedge ctl_clk or negedge ctl_reset_n)
begin
if (!ctl_reset_n)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
pipefull[j] <= 1'b0;
pipe [j] <= 0;
end
end
else
begin
if (fetch) // fetch and write
begin
if (can_merge && last != 1)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else if (j == last_minus_one)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else if (j == last_minus_two)
begin
pipe[j] <= {pipe[j+1][BUFFER_WIDTH-1:BUFFER_WIDTH-4],2'd2,pipe[j+1][BUFFER_WIDTH-7:0]};
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe[CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
else
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= write_to_queue;
pipe [j] <= buffer_input;
end
else
begin
pipefull[j] <= pipefull[j+1];
pipe [j] <= pipe [j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= pipefull[CFG_CTL_QUEUE_DEPTH-1] & write_to_queue;
pipe [CFG_CTL_QUEUE_DEPTH-1] <= pipe [CFG_CTL_QUEUE_DEPTH-1] & buffer_input;
end
end
else if (write_to_queue) // write only
begin
if (can_merge)
begin
pipe[last] <= buffer_input;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
else
begin
for(j=1; j<CFG_CTL_QUEUE_DEPTH; j=j+1)
begin
if(pipefull[j-1] == 1'b1 & pipefull[j] == 1'b0)
begin
pipefull[j] <= 1'b1;
pipe [j] <= buffer_input;
end
end
if(pipefull[0] == 1'b0)
begin
pipefull[0] <= 1'b1;
pipe [0] <= buffer_input;
end
end
end
else if (can_merge)
begin
for(j=0; j<CFG_CTL_QUEUE_DEPTH-1; j=j+1)
begin
if(pipefull[j] == 1'b1 & pipefull[j+1] == 1'b0)
begin
pipefull[j] <= 1'b0;
end
else
begin
pipefull[j] <= pipefull[j+1];
end
end
pipefull[CFG_CTL_QUEUE_DEPTH-1] <= 1'b0;
pipe[last_minus_one][CFG_INT_SIZE_WIDTH + CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH - 1 : CFG_MEM_IF_CS_WIDTH + CFG_MEM_IF_ROW_WIDTH + CFG_MEM_IF_BA_WIDTH + CFG_MEM_IF_COL_WIDTH] <= 2;
end
end
end
//============================ end of queue ===============================
//----------------------------------------------------------------------------------------------------------------
function integer log2;
input [31:0] value;
integer i;
begin
log2 = 0;
for(i = 0; 2**i < value; i = i + 1)
log2 = i + 1;
end
endfunction
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/27/2016 08:26:13 AM
// Design Name:
// Module Name: Mux_8x1
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Mux_8x1
(
//Input Signals
input wire [2:0] select,
input wire [7:0] ch_0,
input wire [7:0] ch_1,
input wire [7:0] ch_2,
input wire [7:0] ch_3,
input wire [7:0] ch_4,
input wire [7:0] ch_5,
input wire [7:0] ch_6,
input wire [7:0] ch_7,
//Output Signals
output reg [7:0] data_out
);
always @*
begin
case(select)
3'b111: data_out = ch_0;
3'b110: data_out = ch_1;
3'b101: data_out = ch_2;
3'b100: data_out = ch_3;
3'b011: data_out = ch_4;
3'b010: data_out = ch_5;
3'b001: data_out = ch_6;
3'b000: data_out = ch_7;
default : data_out = ch_0;
endcase
end
endmodule
|
/*
* Copyright 2018-2022 F4PGA Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Generated by harness_gen.py
* From: VexRiscv.v
*/
module top(input wire clk, input wire stb, input wire di, output wire do);
localparam integer DIN_N = 134;
localparam integer DOUT_N = 148;
reg [DIN_N-1:0] din;
wire [DOUT_N-1:0] dout;
reg [DIN_N-1:0] din_shr;
reg [DOUT_N-1:0] dout_shr;
always @(posedge clk) begin
din_shr <= {din_shr, di};
dout_shr <= {dout_shr, din_shr[DIN_N-1]};
if (stb) begin
din <= din_shr;
dout_shr <= dout;
end
end
assign do = dout_shr[DOUT_N-1];
VexRiscv dut(
.externalResetVector(din[31:0]),
.timerInterrupt(din[32]),
.externalInterruptArray(din[64:33]),
.iBusWishbone_CYC(dout[0]),
.iBusWishbone_STB(dout[1]),
.iBusWishbone_ACK(din[65]),
.iBusWishbone_WE(dout[2]),
.iBusWishbone_ADR(dout[32:3]),
.iBusWishbone_DAT_MISO(din[97:66]),
.iBusWishbone_DAT_MOSI(dout[64:33]),
.iBusWishbone_SEL(dout[68:65]),
.iBusWishbone_ERR(din[98]),
.iBusWishbone_BTE(dout[70:69]),
.iBusWishbone_CTI(dout[73:71]),
.dBusWishbone_CYC(dout[74]),
.dBusWishbone_STB(dout[75]),
.dBusWishbone_ACK(din[99]),
.dBusWishbone_WE(dout[76]),
.dBusWishbone_ADR(dout[106:77]),
.dBusWishbone_DAT_MISO(din[131:100]),
.dBusWishbone_DAT_MOSI(dout[138:107]),
.dBusWishbone_SEL(dout[142:139]),
.dBusWishbone_ERR(din[132]),
.dBusWishbone_BTE(dout[144:143]),
.dBusWishbone_CTI(dout[147:145]),
.clk(clk),
.reset(din[133])
);
endmodule
|
module main_pll # (parameter SPEED_MHZ = 25) (inclk0, c0);
input inclk0;
output c0;
wire [4:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0),
.activeclock (),
.areset (1'b0),
.clkbad (),
.clkena ({6{1'b1}}),
.clkloss (),
.clkswitch (1'b0),
.configupdate (1'b0),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena ({4{1'b1}}),
.fbin (1'b1),
.fbmimicbidir (),
.fbout (),
// synopsys translate_off
.fref (),
.icdrclk (),
// synopsys translate_on
.locked (),
.pfdena (1'b1),
.phasecounterselect ({4{1'b1}}),
.phasedone (),
.phasestep (1'b1),
.phaseupdown (1'b1),
.pllena (1'b1),
.scanaclr (1'b0),
.scanclk (1'b0),
.scanclkena (1'b1),
.scandata (1'b0),
.scandataout (),
.scandone (),
.scanread (1'b0),
.scanwrite (1'b0),
.sclkout0 (),
.sclkout1 (),
.vcooverrange (),
.vcounderrange ());
defparam
altpll_component.bandwidth_type = "AUTO",
altpll_component.clk0_divide_by = 50,
altpll_component.clk0_duty_cycle = 50,
altpll_component.clk0_multiply_by = SPEED_MHZ,
altpll_component.clk0_phase_shift = "0",
altpll_component.compensate_clock = "CLK0",
altpll_component.inclk0_input_frequency = 20000,
altpll_component.intended_device_family = "Cyclone III",
altpll_component.lpm_hint = "CBX_MODULE_PREFIX=main_pll",
altpll_component.lpm_type = "altpll",
altpll_component.operation_mode = "NORMAL",
altpll_component.pll_type = "AUTO",
altpll_component.port_activeclock = "PORT_UNUSED",
altpll_component.port_areset = "PORT_UNUSED",
altpll_component.port_clkbad0 = "PORT_UNUSED",
altpll_component.port_clkbad1 = "PORT_UNUSED",
altpll_component.port_clkloss = "PORT_UNUSED",
altpll_component.port_clkswitch = "PORT_UNUSED",
altpll_component.port_configupdate = "PORT_UNUSED",
altpll_component.port_fbin = "PORT_UNUSED",
altpll_component.port_inclk0 = "PORT_USED",
altpll_component.port_inclk1 = "PORT_UNUSED",
altpll_component.port_locked = "PORT_UNUSED",
altpll_component.port_pfdena = "PORT_UNUSED",
altpll_component.port_phasecounterselect = "PORT_UNUSED",
altpll_component.port_phasedone = "PORT_UNUSED",
altpll_component.port_phasestep = "PORT_UNUSED",
altpll_component.port_phaseupdown = "PORT_UNUSED",
altpll_component.port_pllena = "PORT_UNUSED",
altpll_component.port_scanaclr = "PORT_UNUSED",
altpll_component.port_scanclk = "PORT_UNUSED",
altpll_component.port_scanclkena = "PORT_UNUSED",
altpll_component.port_scandata = "PORT_UNUSED",
altpll_component.port_scandataout = "PORT_UNUSED",
altpll_component.port_scandone = "PORT_UNUSED",
altpll_component.port_scanread = "PORT_UNUSED",
altpll_component.port_scanwrite = "PORT_UNUSED",
altpll_component.port_clk0 = "PORT_USED",
altpll_component.port_clk1 = "PORT_UNUSED",
altpll_component.port_clk2 = "PORT_UNUSED",
altpll_component.port_clk3 = "PORT_UNUSED",
altpll_component.port_clk4 = "PORT_UNUSED",
altpll_component.port_clk5 = "PORT_UNUSED",
altpll_component.port_clkena0 = "PORT_UNUSED",
altpll_component.port_clkena1 = "PORT_UNUSED",
altpll_component.port_clkena2 = "PORT_UNUSED",
altpll_component.port_clkena3 = "PORT_UNUSED",
altpll_component.port_clkena4 = "PORT_UNUSED",
altpll_component.port_clkena5 = "PORT_UNUSED",
altpll_component.port_extclk0 = "PORT_UNUSED",
altpll_component.port_extclk1 = "PORT_UNUSED",
altpll_component.port_extclk2 = "PORT_UNUSED",
altpll_component.port_extclk3 = "PORT_UNUSED",
altpll_component.width_clock = 5;
endmodule
|
module wb_bfm_tb;
vlog_tb_utils vlog_tb_utils0();
localparam aw = 32;
localparam dw = 32;
reg wb_clk = 1'b1;
reg wb_rst = 1'b1;
always #5 wb_clk <= ~wb_clk;
initial #100 wb_rst <= 0;
wire [aw-1:0] wb_m2s_adr;
wire [dw-1:0] wb_m2s_dat;
wire [3:0] wb_m2s_sel;
wire wb_m2s_we ;
wire wb_m2s_cyc;
wire wb_m2s_stb;
wire [2:0] wb_m2s_cti;
wire [1:0] wb_m2s_bte;
wire [dw-1:0] wb_s2m_dat;
wire wb_s2m_ack;
wire wb_s2m_err;
wire wb_s2m_rty;
wb_master wb_master0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_o (wb_m2s_adr),
.wb_dat_o (wb_m2s_dat),
.wb_sel_o (wb_m2s_sel),
.wb_we_o (wb_m2s_we ),
.wb_cyc_o (wb_m2s_cyc),
.wb_stb_o (wb_m2s_stb),
.wb_cti_o (wb_m2s_cti),
.wb_bte_o (wb_m2s_bte),
.wb_dat_i (wb_s2m_dat),
.wb_ack_i (wb_s2m_ack),
.wb_err_i (wb_s2m_err),
.wb_rty_i (wb_s2m_rty));
wb_bfm_memory #(.DEBUG (0))
wb_mem_model0
(.wb_clk_i (wb_clk),
.wb_rst_i (wb_rst),
.wb_adr_i (wb_m2s_adr),
.wb_dat_i (wb_m2s_dat),
.wb_sel_i (wb_m2s_sel),
.wb_we_i (wb_m2s_we ),
.wb_cyc_i (wb_m2s_cyc),
.wb_stb_i (wb_m2s_stb),
.wb_cti_i (wb_m2s_cti),
.wb_bte_i (wb_m2s_bte),
.wb_dat_o (wb_s2m_dat),
.wb_ack_o (wb_s2m_ack),
.wb_err_o (wb_s2m_err),
.wb_rty_o (wb_s2m_rty));
endmodule
|
// 8bit Memory Module
`default_nettype none
module memory_8bit #(
parameter integer C_S_AXI_ADDR_WIDTH = 32,
parameter integer C_MEMORY_SIZE = 512 // Word (not byte)
)(
input wire clk,
input wire [C_S_AXI_ADDR_WIDTH-1:0] waddr,
input wire [7:0] write_data,
input wire write_enable,
input wire byte_enable,
input wire [C_S_AXI_ADDR_WIDTH-1:0] raddr,
output wire [7:0] read_data
);
// Beyond Circuts, Constant Function in Verilog 2001を参照しました
// http://www.beyond-circuits.com/wordpress/2008/11/constant-functions/
function integer log2;
input integer addr;
begin
addr = addr - 1;
for (log2=0; addr>0; log2=log2+1)
addr = addr >> 1;
end
endfunction
reg [7:0] mem [0:C_MEMORY_SIZE-1];
wire [log2(C_MEMORY_SIZE)-1:0] mem_waddr;
wire [log2(C_MEMORY_SIZE)-1:0] mem_raddr;
integer i;
// initialization
initial begin
for (i=0; i < C_MEMORY_SIZE; i=i+1) begin
mem[i] = 8'd0;
end
end
// The Address is byte address
assign mem_waddr = waddr[(log2(C_MEMORY_SIZE)+log2((C_S_AXI_ADDR_WIDTH/8)))-1:log2((C_S_AXI_ADDR_WIDTH/8))];
assign mem_raddr = raddr[(log2(C_MEMORY_SIZE)+log2((C_S_AXI_ADDR_WIDTH/8)))-1:log2((C_S_AXI_ADDR_WIDTH/8))];
// Write
always @(posedge clk) begin
if (write_enable & byte_enable)
mem[mem_waddr] <= write_data;
end
// Read
// always @(posedge clk) begin
assign read_data = mem[mem_raddr];
// end
endmodule
`default_nettype wire
|
///////////////////////////////////////////////////////////////////////////////
//
// File name: axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm.v
//
///////////////////////////////////////////////////////////////////////////////
`timescale 1ps/1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axi_protocol_converter_v2_1_9_b2s_rd_cmd_fsm (
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk ,
input wire reset ,
output wire s_arready ,
input wire s_arvalid ,
input wire [7:0] s_arlen ,
output wire m_arvalid ,
input wire m_arready ,
// signal to increment to the next mc transaction
output wire next ,
// signal to the fsm there is another transaction required
input wire next_pending ,
// Write Data portion has completed or Read FIFO has a slot available (not
// full)
input wire data_ready ,
// status signal for w_channel when command is written.
output wire a_push ,
output wire r_push
);
////////////////////////////////////////////////////////////////////////////////
// Local parameters
////////////////////////////////////////////////////////////////////////////////
// States
localparam SM_IDLE = 2'b00;
localparam SM_CMD_EN = 2'b01;
localparam SM_CMD_ACCEPTED = 2'b10;
localparam SM_DONE = 2'b11;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
reg [1:0] state;
// synthesis attribute MAX_FANOUT of state is 20;
reg [1:0] state_r1;
reg [1:0] next_state;
reg [7:0] s_arlen_r;
////////////////////////////////////////////////////////////////////////////////
// BEGIN RTL
///////////////////////////////////////////////////////////////////////////////
// register for timing
always @(posedge clk) begin
if (reset) begin
state <= SM_IDLE;
state_r1 <= SM_IDLE;
s_arlen_r <= 0;
end else begin
state <= next_state;
state_r1 <= state;
s_arlen_r <= s_arlen;
end
end
// Next state transitions.
always @( * ) begin
next_state = state;
case (state)
SM_IDLE:
if (s_arvalid & data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_EN:
///////////////////////////////////////////////////////////////////
// Drive m_arvalid downstream in this state
///////////////////////////////////////////////////////////////////
//If there is no fifo space
if (~data_ready & m_arready & next_pending) begin
///////////////////////////////////////////////////////////////////
//There is more to do, wait until data space is available drop valid
next_state = SM_CMD_ACCEPTED;
end else if (m_arready & ~next_pending)begin
next_state = SM_DONE;
end else if (m_arready & next_pending) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_CMD_ACCEPTED:
if (data_ready) begin
next_state = SM_CMD_EN;
end else begin
next_state = state;
end
SM_DONE:
next_state = SM_IDLE;
default:
next_state = SM_IDLE;
endcase
end
// Assign outputs based on current state.
assign m_arvalid = (state == SM_CMD_EN);
assign next = m_arready && (state == SM_CMD_EN);
assign r_push = next;
assign a_push = (state == SM_IDLE);
assign s_arready = ((state == SM_CMD_EN) || (state == SM_DONE)) && (next_state == SM_IDLE);
endmodule
`default_nettype wire
|
// ***************************************************************************
// ***************************************************************************
// Copyright 2011(c) Analog Devices, Inc.
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without modification,
// are permitted provided that the following conditions are met:
// - Redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer.
// - Redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in
// the documentation and/or other materials provided with the
// distribution.
// - Neither the name of Analog Devices, Inc. nor the names of its
// contributors may be used to endorse or promote products derived
// from this software without specific prior written permission.
// - The use of this software may or may not infringe the patent rights
// of one or more patent holders. This license does not release you
// from the requirement that you obtain separate licenses from these
// patent holders to use this software.
// - Use of the software either in source or binary form, must be run
// on or directly connected to an Analog Devices Inc. component.
//
// THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
// INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
// PARTICULAR PURPOSE ARE DISCLAIMED.
//
// IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
// RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
// THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
// ***************************************************************************
`timescale 1ns/100ps
module up_hdmi_tx (
// hdmi interface
hdmi_clk,
hdmi_rst,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_ss_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min,
hdmi_status,
hdmi_tpm_oos,
hdmi_clk_ratio,
// vdma interface
vdma_clk,
vdma_rst,
vdma_ovf,
vdma_unf,
vdma_tpm_oos,
// bus interface
up_rstn,
up_clk,
up_wreq,
up_waddr,
up_wdata,
up_wack,
up_rreq,
up_raddr,
up_rdata,
up_rack);
// parameters
localparam PCORE_VERSION = 32'h00040063;
parameter PCORE_ID = 0;
// hdmi interface
input hdmi_clk;
output hdmi_rst;
output hdmi_full_range;
output hdmi_csc_bypass;
output hdmi_ss_bypass;
output [ 1:0] hdmi_srcsel;
output [23:0] hdmi_const_rgb;
output [15:0] hdmi_hl_active;
output [15:0] hdmi_hl_width;
output [15:0] hdmi_hs_width;
output [15:0] hdmi_he_max;
output [15:0] hdmi_he_min;
output [15:0] hdmi_vf_active;
output [15:0] hdmi_vf_width;
output [15:0] hdmi_vs_width;
output [15:0] hdmi_ve_max;
output [15:0] hdmi_ve_min;
input hdmi_status;
input hdmi_tpm_oos;
input [31:0] hdmi_clk_ratio;
// vdma interface
input vdma_clk;
output vdma_rst;
input vdma_ovf;
input vdma_unf;
input vdma_tpm_oos;
// bus interface
input up_rstn;
input up_clk;
input up_wreq;
input [13:0] up_waddr;
input [31:0] up_wdata;
output up_wack;
input up_rreq;
input [13:0] up_raddr;
output [31:0] up_rdata;
output up_rack;
// internal registers
reg up_wack = 'd0;
reg [31:0] up_scratch = 'd0;
reg up_resetn = 'd0;
reg up_full_range = 'd0;
reg up_csc_bypass = 'd0;
reg up_ss_bypass = 'd0;
reg [ 1:0] up_srcsel = 'd1;
reg [23:0] up_const_rgb = 'd0;
reg up_vdma_ovf = 'd0;
reg up_vdma_unf = 'd0;
reg up_hdmi_tpm_oos = 'd0;
reg up_vdma_tpm_oos = 'd0;
reg [15:0] up_hl_active = 'd0;
reg [15:0] up_hl_width = 'd0;
reg [15:0] up_hs_width = 'd0;
reg [15:0] up_he_max = 'd0;
reg [15:0] up_he_min = 'd0;
reg [15:0] up_vf_active = 'd0;
reg [15:0] up_vf_width = 'd0;
reg [15:0] up_vs_width = 'd0;
reg [15:0] up_ve_max = 'd0;
reg [15:0] up_ve_min = 'd0;
reg up_rack = 'd0;
reg [31:0] up_rdata = 'd0;
// internal signals
wire up_wreq_s;
wire up_rreq_s;
wire up_preset_s;
wire up_hdmi_status_s;
wire up_hdmi_tpm_oos_s;
wire [31:0] up_hdmi_clk_count_s;
wire up_vdma_ovf_s;
wire up_vdma_unf_s;
wire up_vdma_tpm_oos_s;
// decode block select
assign up_wreq_s = (up_waddr[13:12] == 2'd0) ? up_wreq : 1'b0;
assign up_rreq_s = (up_raddr[13:12] == 2'd0) ? up_rreq : 1'b0;
assign up_preset_s = ~up_resetn;
// processor write interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_wack <= 'd0;
up_scratch <= 'd0;
up_resetn <= 'd0;
up_full_range <= 'd0;
up_csc_bypass <= 'd0;
up_ss_bypass <= 'd0;
up_srcsel <= 'd1;
up_const_rgb <= 'd0;
up_vdma_ovf <= 'd0;
up_vdma_unf <= 'd0;
up_hdmi_tpm_oos <= 'd0;
up_vdma_tpm_oos <= 'd0;
up_hl_active <= 'd0;
up_hl_width <= 'd0;
up_hs_width <= 'd0;
up_he_max <= 'd0;
up_he_min <= 'd0;
up_vf_active <= 'd0;
up_vf_width <= 'd0;
up_vs_width <= 'd0;
up_ve_max <= 'd0;
up_ve_min <= 'd0;
end else begin
up_wack <= up_wreq_s;
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h002)) begin
up_scratch <= up_wdata;
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h010)) begin
up_resetn <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h011)) begin
up_ss_bypass <= up_wdata[2];
up_full_range <= up_wdata[1];
up_csc_bypass <= up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h012)) begin
up_srcsel <= up_wdata[1:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h013)) begin
up_const_rgb <= up_wdata[23:0];
end
if (up_vdma_ovf_s == 1'b1) begin
up_vdma_ovf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_vdma_ovf <= up_vdma_ovf & ~up_wdata[1];
end
if (up_vdma_unf_s == 1'b1) begin
up_vdma_unf <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h018)) begin
up_vdma_unf <= up_vdma_unf & ~up_wdata[0];
end
if (up_hdmi_tpm_oos_s == 1'b1) begin
up_hdmi_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_hdmi_tpm_oos <= up_hdmi_tpm_oos & ~up_wdata[1];
end
if (up_vdma_tpm_oos_s == 1'b1) begin
up_vdma_tpm_oos <= 1'b1;
end else if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h019)) begin
up_vdma_tpm_oos <= up_vdma_tpm_oos & ~up_wdata[0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h100)) begin
up_hl_active <= up_wdata[31:16];
up_hl_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h101)) begin
up_hs_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h102)) begin
up_he_max <= up_wdata[31:16];
up_he_min <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h110)) begin
up_vf_active <= up_wdata[31:16];
up_vf_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h111)) begin
up_vs_width <= up_wdata[15:0];
end
if ((up_wreq_s == 1'b1) && (up_waddr[11:0] == 12'h112)) begin
up_ve_max <= up_wdata[31:16];
up_ve_min <= up_wdata[15:0];
end
end
end
// processor read interface
always @(negedge up_rstn or posedge up_clk) begin
if (up_rstn == 0) begin
up_rack <= 'd0;
up_rdata <= 'd0;
end else begin
up_rack <= up_rreq_s;
if (up_rreq_s == 1'b1) begin
case (up_raddr[11:0])
12'h000: up_rdata <= PCORE_VERSION;
12'h001: up_rdata <= PCORE_ID;
12'h002: up_rdata <= up_scratch;
12'h010: up_rdata <= {31'd0, up_resetn};
12'h011: up_rdata <= {29'd0, up_ss_bypass, up_full_range, up_csc_bypass};
12'h012: up_rdata <= {30'd0, up_srcsel};
12'h013: up_rdata <= {8'd0, up_const_rgb};
12'h015: up_rdata <= up_hdmi_clk_count_s;
12'h016: up_rdata <= hdmi_clk_ratio;
12'h017: up_rdata <= {31'd0, up_hdmi_status_s};
12'h018: up_rdata <= {30'd0, up_vdma_ovf, up_vdma_unf};
12'h019: up_rdata <= {30'd0, up_hdmi_tpm_oos, up_vdma_tpm_oos};
12'h100: up_rdata <= {up_hl_active, up_hl_width};
12'h101: up_rdata <= {16'd0, up_hs_width};
12'h102: up_rdata <= {up_he_max, up_he_min};
12'h110: up_rdata <= {up_vf_active, up_vf_width};
12'h111: up_rdata <= {16'd0, up_vs_width};
12'h112: up_rdata <= {up_ve_max, up_ve_min};
default: up_rdata <= 0;
endcase
end else begin
up_rdata <= 32'd0;
end
end
end
// resets
ad_rst i_hdmi_rst_reg (.preset(up_preset_s), .clk(hdmi_clk), .rst(hdmi_rst));
ad_rst i_vdma_rst_reg (.preset(up_preset_s), .clk(vdma_clk), .rst(vdma_rst));
// hdmi control & status
up_xfer_cntrl #(.DATA_WIDTH(189)) i_hdmi_xfer_cntrl (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_cntrl ({ up_ss_bypass,
up_full_range,
up_csc_bypass,
up_srcsel,
up_const_rgb,
up_hl_active,
up_hl_width,
up_hs_width,
up_he_max,
up_he_min,
up_vf_active,
up_vf_width,
up_vs_width,
up_ve_max,
up_ve_min}),
.up_xfer_done (),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_cntrl ({ hdmi_ss_bypass,
hdmi_full_range,
hdmi_csc_bypass,
hdmi_srcsel,
hdmi_const_rgb,
hdmi_hl_active,
hdmi_hl_width,
hdmi_hs_width,
hdmi_he_max,
hdmi_he_min,
hdmi_vf_active,
hdmi_vf_width,
hdmi_vs_width,
hdmi_ve_max,
hdmi_ve_min}));
up_xfer_status #(.DATA_WIDTH(2)) i_hdmi_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_hdmi_status_s,
up_hdmi_tpm_oos_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ hdmi_status,
hdmi_tpm_oos}));
// hdmi clock monitor
up_clock_mon i_hdmi_clock_mon (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_d_count (up_hdmi_clk_count_s),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk));
// vdma control & status
up_xfer_status #(.DATA_WIDTH(3)) i_vdma_xfer_status (
.up_rstn (up_rstn),
.up_clk (up_clk),
.up_data_status ({up_vdma_ovf_s,
up_vdma_unf_s,
up_vdma_tpm_oos_s}),
.d_rst (hdmi_rst),
.d_clk (hdmi_clk),
.d_data_status ({ vdma_ovf,
vdma_unf,
vdma_tpm_oos}));
endmodule
// ***************************************************************************
// ***************************************************************************
|
/*============================================================================
This Verilog source file is part of the Berkeley HardFloat IEEE Floating-Point
Arithmetic Package, Release 1, by John R. Hauser.
Copyright 2019 The Regents of the University of California. All rights
reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
1. Redistributions of source code must retain the above copyright notice,
this list of conditions, and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice,
this list of conditions, and the following disclaimer in the documentation
and/or other materials provided with the distribution.
3. Neither the name of the University nor the names of its contributors may
be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS "AS IS", AND ANY
EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE
DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE FOR ANY
DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
=============================================================================*/
`include "HardFloat_consts.vi"
`include "HardFloat_specialize.vi"
module
addRecF16_add (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
addRecFN#(5, 11)
addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF32_add (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN#(8, 24)
addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF64_add (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN#(11, 53)
addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF128_add (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
addRecFN#(15, 113)
addRecFN(control, 1'b0, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF16_sub (
input [(`floatControlWidth - 1):0] control,
input [16:0] a,
input [16:0] b,
input [2:0] roundingMode,
output [16:0] out,
output [4:0] exceptionFlags
);
addRecFN#(5, 11)
addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF32_sub (
input [(`floatControlWidth - 1):0] control,
input [32:0] a,
input [32:0] b,
input [2:0] roundingMode,
output [32:0] out,
output [4:0] exceptionFlags
);
addRecFN#(8, 24)
addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF64_sub (
input [(`floatControlWidth - 1):0] control,
input [64:0] a,
input [64:0] b,
input [2:0] roundingMode,
output [64:0] out,
output [4:0] exceptionFlags
);
addRecFN#(11, 53)
addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);
endmodule
module
addRecF128_sub (
input [(`floatControlWidth - 1):0] control,
input [128:0] a,
input [128:0] b,
input [2:0] roundingMode,
output [128:0] out,
output [4:0] exceptionFlags
);
addRecFN#(15, 113)
addRecFN(control, 1'b1, a, b, roundingMode, out, exceptionFlags);
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__TAPVGND2_TB_V
`define SKY130_FD_SC_LS__TAPVGND2_TB_V
/**
* tapvgnd2: Tap cell with tap to ground, isolated power connection
* 2 rows down.
*
* Autogenerated test bench.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_ls__tapvgnd2.v"
module top();
// Inputs are registered
reg VPWR;
reg VGND;
reg VPB;
reg VNB;
// Outputs are wires
initial
begin
// Initial state is x for all inputs.
VGND = 1'bX;
VNB = 1'bX;
VPB = 1'bX;
VPWR = 1'bX;
#20 VGND = 1'b0;
#40 VNB = 1'b0;
#60 VPB = 1'b0;
#80 VPWR = 1'b0;
#100 VGND = 1'b1;
#120 VNB = 1'b1;
#140 VPB = 1'b1;
#160 VPWR = 1'b1;
#180 VGND = 1'b0;
#200 VNB = 1'b0;
#220 VPB = 1'b0;
#240 VPWR = 1'b0;
#260 VPWR = 1'b1;
#280 VPB = 1'b1;
#300 VNB = 1'b1;
#320 VGND = 1'b1;
#340 VPWR = 1'bx;
#360 VPB = 1'bx;
#380 VNB = 1'bx;
#400 VGND = 1'bx;
end
sky130_fd_sc_ls__tapvgnd2 dut (.VPWR(VPWR), .VGND(VGND), .VPB(VPB), .VNB(VNB));
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LS__TAPVGND2_TB_V
|
/*
Legal Notice: (C)2009 Altera Corporation. All rights reserved. Your
use of Altera Corporation's design tools, logic functions and other
software and tools, and its AMPP partner logic functions, and any
output files any of the foregoing (including device programming or
simulation files), and any associated documentation or information are
expressly subject to the terms and conditions of the Altera Program
License Subscription Agreement or other applicable license agreement,
including, without limitation, that your use is for the sole purpose
of programming logic devices manufactured by Altera and sold by Altera
or its authorized distributors. Please refer to the applicable
agreement for further details.
*/
/*
Author: JCJB
Date: 08/13/2010
Version 2.5
This write master module is responsible for taking in streaming data and
writing the contents out to memory. It is controlled by a streaming
sink port called the 'command port'. Any information that must be communicated
back to a host such as an error in transfer is made available by the
streaming source port called the 'response port'.
There are various parameters to control the synthesis of this hardware
either for functionality changes or speed/resource optimizations. Some
of the parameters will be hidden in the component GUI since they are derived
from some other parameters. When this master module is used in a MM to MM
transfer disable the packet support since the packet hardware is not needed.
In order to increase the Fmax you should enable only full accesses so that
the unaligned access and byte enable blocks can be reduced to wires. Also
only configure the length width to be as wide as you need as it will typically
be the critical path of this module.
Revision History:
1.0 Initial version which used a simple exported hand shake control scheme.
2.0 Added support for unaligned accesses, stride, and streaming.
2.1 Fixed control logic and removed the early termination enable logic (it's
always on now so for packet transfers make sure the length register is
programmed accordingly.
2.2 Added burst support.
2.3 Added additional conditional code for 8-bit case to avoid synthesis issues.
2.4 Corrected burst bug that prevented full bursts from being presented to the
fabric. Corrected the stop/reset logic to ensure masters can be stopped
or reset while idle.
2.5 Corrected a packet problem where EOP wasn't qualified by ready and valid.
Added 64-bit addressing.
*/
// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on
// turn off superfluous verilog processor warnings
// altera message_level Level1
// altera message_off 10034 10035 10036 10037 10230 10240 10030
module write_master (
clk,
reset,
// descriptor commands sink port
snk_command_data,
snk_command_valid,
snk_command_ready,
// response source port
src_response_data,
src_response_valid,
src_response_ready,
// data path sink port
snk_data,
snk_valid,
snk_ready,
snk_sop,
snk_eop,
snk_empty,
snk_error,
// data path master port
master_address,
master_write,
master_byteenable,
master_writedata,
master_waitrequest,
master_burstcount
);
parameter UNALIGNED_ACCESSES_ENABLE = 0; // when enabled allows transfers to begin from off word boundaries
parameter ONLY_FULL_ACCESS_ENABLE = 0; // when enabled allows transfers to end with partial access, master achieve a much higher fmax when this is enabled
parameter STRIDE_ENABLE = 0; // stride support can only be enabled when unaligned accesses is disabled
parameter STRIDE_WIDTH = 1; // when stride support is enabled this value controls the rate in which the address increases (in words), the stride width + log2(byte enable width) + 1 cannot exceed address width
parameter PACKET_ENABLE = 0;
parameter ERROR_ENABLE = 0;
parameter ERROR_WIDTH = 8; // must be between 1-8, this will only be enabled in the GUI when error enable is turned on
parameter DATA_WIDTH = 32;
parameter BYTE_ENABLE_WIDTH = 4; // set by the .tcl file (hidden in GUI)
parameter BYTE_ENABLE_WIDTH_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter ADDRESS_WIDTH = 32; // set in the .tcl file (hidden in GUI) by the address span of the master
parameter LENGTH_WIDTH = 32; // GUI setting with warning if ADDRESS_WIDTH < LENGTH_WIDTH (waste of logic for the length counter)
parameter ACTUAL_BYTES_TRANSFERRED_WIDTH = 32; // GUI setting which can only be set when packet support is enabled (otherwise it'll be set to 32). A warning will be issued if overrun protection is enabled and this setting is less than the length width.
parameter FIFO_DEPTH = 32;
parameter FIFO_DEPTH_LOG2 = 5; // set by the .tcl file (hidden in GUI)
parameter FIFO_SPEED_OPTIMIZATION = 1; // set by the .tcl file (hidden in GUI) The default will be on since it only impacts the latency of the entire transfer by 1 clock cycle and adds very little additional logic.
parameter SYMBOL_WIDTH = 8; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS = 4; // set by the .tcl file (hidden in GUI)
parameter NUMBER_OF_SYMBOLS_LOG2 = 2; // set by the .tcl file (hidden in GUI)
parameter BURST_ENABLE = 0;
parameter MAX_BURST_COUNT = 2; // must be a power of 2, when BURST_ENABLE = 0 set the maximum burst count to 1 (automatically done in the .tcl file)
parameter MAX_BURST_COUNT_WIDTH = 2; // set by the .tcl file (hidden in GUI) = log2(MAX_BURST_COUNT) + 1
parameter PROGRAMMABLE_BURST_ENABLE = 0; // when enabled the user must set the burst count, if 0 is set then the value MAX_BURST_COUNT will be used instead
parameter BURST_WRAPPING_SUPPORT = 1; // will only be used when bursting is enabled. This cannot be enabled with programmable burst capabilities. Enabling it will make sure the master gets back into burst alignment (data width in bytes * maximum burst count alignment)
localparam FIFO_USE_MEMORY = 1; // set to 0 to use LEs instead, not exposed since FPGAs have a lot of memory these days
localparam BIG_ENDIAN_ACCESS = 0; // hiding this since it can blow your foot off if you are not careful and it's not tested. It's big endian with respect to the write master width and not necessarily to the width of the data type used by a host CPU.
// handy mask for seperating the word address from the byte address bits, so for 32 bit masters this mask is 0x3, for 64 bit masters it'll be 0x7
localparam LSB_MASK = {BYTE_ENABLE_WIDTH_LOG2{1'b1}};
//need to buffer the empty, eop, sop, and error bits. If these are not needed then the logic will be synthesized away
localparam FIFO_WIDTH = (DATA_WIDTH + 2 + NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH); // data, sop, eop, empty, and error bits
localparam ADDRESS_INCREMENT_WIDTH = (BYTE_ENABLE_WIDTH_LOG2 + MAX_BURST_COUNT_WIDTH + STRIDE_WIDTH);
localparam FIXED_STRIDE = 1'b1; // when stride isn't supported this will be the stride value used (i.e. sequential incrementing of the address)
input clk;
input reset;
// descriptor commands sink port
input [255:0] snk_command_data;
input snk_command_valid;
output reg snk_command_ready;
// response source port
output wire [255:0] src_response_data;
output reg src_response_valid;
input src_response_ready;
// data path sink port
input [DATA_WIDTH-1:0] snk_data;
input snk_valid;
output wire snk_ready;
input snk_sop;
input snk_eop;
input [NUMBER_OF_SYMBOLS_LOG2-1:0] snk_empty;
input [ERROR_WIDTH-1:0] snk_error;
// master inputs and outputs
input master_waitrequest;
output wire [ADDRESS_WIDTH-1:0] master_address;
output wire master_write;
output wire [BYTE_ENABLE_WIDTH-1:0] master_byteenable;
output wire [DATA_WIDTH-1:0] master_writedata;
output wire [MAX_BURST_COUNT_WIDTH-1:0] master_burstcount;
// internal wires and registers
wire [63:0] descriptor_address;
wire [31:0] descriptor_length;
wire [15:0] descriptor_stride;
wire descriptor_end_on_eop_enable;
wire [7:0] descriptor_programmable_burst_count;
reg [ADDRESS_WIDTH-1:0] address_counter;
wire [ADDRESS_WIDTH-1:0] address; // unfiltered version of master_address
wire write; // unfiltered version of master_write
reg [LENGTH_WIDTH-1:0] length_counter;
reg [STRIDE_WIDTH-1:0] stride_d1;
wire [STRIDE_WIDTH-1:0] stride_amount; // either set to be stride_d1 or hardcoded to 1 depending on the parameterization
reg descriptor_end_on_eop_enable_d1;
reg [MAX_BURST_COUNT_WIDTH-1:0] programmable_burst_count_d1;
wire [MAX_BURST_COUNT_WIDTH-1:0] maximum_burst_count;
reg [BYTE_ENABLE_WIDTH_LOG2-1:0] start_byte_address; // used to determine how far out of alignement the master started
reg first_access; // used to prevent extra writes when the unaligned access starts and ends during the same write
wire first_word_boundary_not_reached; // set when the first access doesn't reach the next word boundary
reg first_word_boundary_not_reached_d1;
wire increment_address; // enable the address incrementing
wire [ADDRESS_INCREMENT_WIDTH-1:0] address_increment; // amount of bytes to increment the address
wire [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer;
wire short_first_access_enable; // when starting unaligned and the amount of data to transfer reaches the next word boundary
wire short_last_access_enable; // when address is aligned (can be an unaligned buffer transfer) but the amount of data doesn't reach the next word boundary
wire short_first_and_last_access_enable; // when starting unaligned and the amount of data to transfer doesn't reach the next word boundary
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_last_access_size;
wire [ADDRESS_INCREMENT_WIDTH-1:0] short_first_and_last_access_size;
reg [ADDRESS_INCREMENT_WIDTH-1:0] bytes_to_transfer_mux;
wire [FIFO_WIDTH-1:0] fifo_write_data;
wire [FIFO_WIDTH-1:0] fifo_read_data;
wire [FIFO_DEPTH_LOG2-1:0] fifo_used;
wire fifo_write;
wire fifo_read;
wire fifo_empty;
wire fifo_full;
wire [DATA_WIDTH-1:0] fifo_read_data_rearranged; // if big endian support is enabled then this signal has the FIFO output byte lanes reversed
wire go;
wire done;
reg done_d1;
wire done_strobe;
wire [DATA_WIDTH-1:0] buffered_data;
wire [NUMBER_OF_SYMBOLS_LOG2-1:0] buffered_empty;
wire buffered_eop;
wire buffered_sop; // not wired to anything so synthesized away, included for debug purposes
wire [ERROR_WIDTH-1:0] buffered_error;
wire length_sync_reset; // syncronous reset for the length counter for eop support
reg [ACTUAL_BYTES_TRANSFERRED_WIDTH-1:0] actual_bytes_transferred_counter; // width will be in the range of 1-32
wire [31:0] response_actual_bytes_transferred;
wire early_termination;
reg early_termination_d1;
wire eop_enable;
reg [ERROR_WIDTH-1:0] error; // SRFF so that we don't loose any errors if EOP doesn't arrive right away
wire [7:0] response_error; // need to pad upper error bits with zeros if they are not present at the data streaming port
wire sw_stop_in;
wire sw_reset_in;
reg stopped; // SRFF to make sure we don't attempt to stop in the middle of a transfer
reg reset_taken; // FF to make sure we don't attempt to reset the master in the middle of a transfer
wire reset_taken_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst copmletes, 'reset_taken' will use this signal
wire stopped_from_write_burst_control; // in the middle of a burst greater than one, the burst control block will assert this signal after the burst completes, 'stopped' will use this signal
wire stop_state;
wire reset_delayed;
wire write_complete; // handy signal for determining when a write has occured and completed
wire write_stall_from_byte_enable_generator; // partial word access occuring which might take multiple write cycles to complete (or waitrequest has been asserted)
wire write_stall_from_write_burst_control; // when there isn't enough data buffered to start a burst this signal will be asserted
wire [BYTE_ENABLE_WIDTH-1:0] byteenable_masks [0:BYTE_ENABLE_WIDTH-1]; // a bunch of masks that will be provided to unsupported_byteenable
wire [BYTE_ENABLE_WIDTH-1:0] unsupported_byteenable; // input into the byte enable generation block which will take the unsupported byte enable and chop it up into supported transfers
wire [BYTE_ENABLE_WIDTH-1:0] supported_byteenable; // output from the byte enable generation block
wire extra_write; // when asserted master_write will be asserted but the FIFO will not be popped since it will not contain any more data for the transfer
wire st_to_mm_adapter_enable;
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_beat_size; // number of bytes coming in from the data stream when packet support is enabled
wire [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered;
reg [BYTE_ENABLE_WIDTH_LOG2:0] packet_bytes_buffered_d1; // represents the number of bytes buffered in the ST to MM adapter (only applicable for unaligned accesses)
reg eop_seen; // when the beat containing EOP has been popped from the fifo this bit will be set, it will be reset when done is asserted. It is used to determine if an extra write must occur (unaligned accesses only)
/********************************************* REGISTERS ****************************************************************************************/
// registering the stride control bit
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stride_d1 <= 0;
end
else if (go == 1)
begin
stride_d1 <= descriptor_stride[STRIDE_WIDTH-1:0];
end
end
// registering the end on eop bit (will be optimized away if packet support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
descriptor_end_on_eop_enable_d1 <= 1'b0;
end
else if (go == 1)
begin
descriptor_end_on_eop_enable_d1 <= descriptor_end_on_eop_enable;
end
end
// registering the programmable burst count (will be optimized away if this support is disabled)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
programmable_burst_count_d1 <= 0;
end
else if (go == 1)
begin
programmable_burst_count_d1 <= (descriptor_programmable_burst_count == 0)? MAX_BURST_COUNT : descriptor_programmable_burst_count;
end
end
// master address increment counter
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
address_counter <= 0;
end
else
begin
if (go == 1)
begin
address_counter <= descriptor_address[ADDRESS_WIDTH-1:0];
end
else if (increment_address == 1)
begin
address_counter <= address_counter + address_increment;
end
end
end
// master byte address, used to determine how far out of alignment the master began transfering data
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
start_byte_address <= 0;
end
else if (go == 1)
begin
start_byte_address <= descriptor_address[BYTE_ENABLE_WIDTH_LOG2-1:0];
end
end
// first_access will be asserted only for the first write of a transaction, this will be used to filter 'extra_write' for unaligned accesses
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_access <= 0;
end
else
begin
if (go == 1)
begin
first_access <= 1;
end
else if ((first_access == 1) & (increment_address == 1))
begin
first_access <= 0;
end
end
end
// this register is used to determine if the first word boundary will be reached
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
first_word_boundary_not_reached_d1 <= 0;
end
else if (go == 1)
begin
first_word_boundary_not_reached_d1 <= first_word_boundary_not_reached;
end
end
// master length logic, this will typically be the critical path followed by the FIFO
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
length_counter <= 0;
end
else
begin
if (length_sync_reset == 1) // when packet support is enabled the length register might roll over so this sync reset will prevent that from happening (it's also used when a soft reset is triggered)
begin
length_counter <= 0; // when EOP arrives need to stop counting, length=0 is the done condition
end
else if (go == 1)
begin
length_counter <= descriptor_length[LENGTH_WIDTH-1:0];
end
else if (increment_address == 1)
begin
length_counter <= length_counter - bytes_to_transfer; // not using address_increment because stride might be enabled
end
end
end
// master actual bytes transferred logic, this will only be used when packet support is enabled, otherwise the value will be 0
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
actual_bytes_transferred_counter <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
actual_bytes_transferred_counter <= 0;
end
else if(increment_address == 1)
begin
actual_bytes_transferred_counter <= actual_bytes_transferred_counter + bytes_to_transfer;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
done_d1 <= 1; // out of reset the master needs to be 'done' so that the done_strobe doesn't fire
end
else
begin
done_d1 <= done;
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
early_termination_d1 <= 0;
end
else
begin
early_termination_d1 <= early_termination;
end
end
generate
genvar l;
for(l = 0; l < ERROR_WIDTH; l = l + 1)
begin: error_SRFF
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
error[l] <= 0;
end
else
begin
if ((go == 1) | (reset_taken == 1))
begin
error[l] <= 0;
end
else if ((buffered_error[l] == 1) & (done == 0))
begin
error[l] <= 1;
end
end
end
end
endgenerate
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
snk_command_ready <= 1; // have to start ready to take commands
end
else
begin
if (go == 1)
begin
snk_command_ready <= 0;
end
else if (((done == 1) & (src_response_valid == 0)) | (reset_taken == 1)) // need to make sure the response is popped before accepting more commands
begin
snk_command_ready <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
src_response_valid <= 0;
end
else
begin
if (reset_taken == 1)
begin
src_response_valid <= 0;
end
else if (done_strobe == 1)
begin
src_response_valid <= 1; // will be set only once
end
else if ((src_response_valid == 1) & (src_response_ready == 1))
begin
src_response_valid <= 0; // will be reset only once when the dispatcher captures the data
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
stopped <= 0;
end
else
begin
if ((sw_stop_in == 0) | (reset_taken == 1))
begin
stopped <= 0;
end
else if ((sw_stop_in == 1) & (((write_complete == 1) & (stopped_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0))))
begin
stopped <= 1;
end
end
end
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
reset_taken <= 0;
end
else
begin
reset_taken <= (sw_reset_in == 1) & (((write_complete == 1) & (reset_taken_from_write_burst_control == 1)) | ((snk_command_ready == 1) | (master_write == 0)));
end
end
// eop_seen will be set when the last beat of a packet transfer has been popped from the fifo for ST to MM block flushing purposes (extra write)
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
eop_seen <= 0;
end
else
begin
if (done == 1)
begin
eop_seen <= 0;
end
else if ((buffered_eop == 1) & (write_complete == 1))
begin
eop_seen <= 1;
end
end
end
// when unaligned accesses are enabled packet_bytes_buffered_d1 is the number of bytes buffered in the ST to MM block from the previous beat
always @ (posedge clk or posedge reset)
begin
if (reset)
begin
packet_bytes_buffered_d1 <= 0;
end
else
begin
if (go == 1)
begin
packet_bytes_buffered_d1 <= 0;
end
else if (write_complete == 1)
begin
packet_bytes_buffered_d1 <= packet_bytes_buffered;
end
end
end
/********************************************* END REGISTERS ************************************************************************************/
/********************************************* MODULE INSTANTIATIONS ****************************************************************************/
/* buffered sop, eop, empty, error, data (in that order). sop, eop, and empty are only used when packet support is enabled,
likewise error is only used when error support is enabled */
scfifo the_st_to_master_fifo (
.aclr (reset),
.clock (clk),
.data (fifo_write_data),
.full (fifo_full),
.empty (fifo_empty),
.q (fifo_read_data),
.rdreq (fifo_read),
.usedw (fifo_used),
.wrreq (fifo_write)
);
defparam the_st_to_master_fifo.lpm_width = FIFO_WIDTH;
defparam the_st_to_master_fifo.lpm_widthu = FIFO_DEPTH_LOG2;
defparam the_st_to_master_fifo.lpm_numwords = FIFO_DEPTH;
defparam the_st_to_master_fifo.lpm_showahead = "ON"; // slower but doesn't require complex control logic to time with waitrequest
defparam the_st_to_master_fifo.use_eab = (FIFO_USE_MEMORY == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.add_ram_output_register = (FIFO_SPEED_OPTIMIZATION == 1)? "ON" : "OFF";
defparam the_st_to_master_fifo.underflow_checking = "OFF";
defparam the_st_to_master_fifo.overflow_checking = "OFF";
/* This module will barrelshift the data from the FIFO when unaligned accesses is enabled (we are using
part of the FIFO word when off boundary). When unaligned accesses is disabled then the data passes
as wires. The byte enable generator might require multiple cycles to perform partial accesses so a
'stall' bit is used (triggers a stall like waitrequest)
*/
ST_to_MM_Adapter the_ST_to_MM_Adapter (
.clk (clk),
.reset (reset),
.enable (st_to_mm_adapter_enable),
.address (descriptor_address[ADDRESS_WIDTH-1:0]),
.start (go),
.waitrequest (master_waitrequest),
.stall (write_stall_from_byte_enable_generator | write_stall_from_write_burst_control),
.write_data (master_writedata),
.fifo_data (buffered_data),
.fifo_empty (fifo_empty),
.fifo_readack (fifo_read)
);
defparam the_ST_to_MM_Adapter.DATA_WIDTH = DATA_WIDTH;
defparam the_ST_to_MM_Adapter.BYTEENABLE_WIDTH_LOG2 = BYTE_ENABLE_WIDTH_LOG2;
defparam the_ST_to_MM_Adapter.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_ST_to_MM_Adapter.UNALIGNED_ACCESS_ENABLE = UNALIGNED_ACCESSES_ENABLE;
/* this block is responsible for presenting the fabric with supported byte enable combinations which can
take multiple cycles, if full word only support is enabled this block will reduce to wires during synthesis */
byte_enable_generator the_byte_enable_generator (
.clk (clk),
.reset (reset),
.write_in (write),
.byteenable_in (unsupported_byteenable),
.waitrequest_out (write_stall_from_byte_enable_generator),
.byteenable_out (supported_byteenable),
.waitrequest_in (master_waitrequest | write_stall_from_write_burst_control)
);
defparam the_byte_enable_generator.BYTEENABLE_WIDTH = BYTE_ENABLE_WIDTH;
// this block will be used to drive write, address, and burstcount to the fabric
write_burst_control the_write_burst_control (
.clk (clk),
.reset (reset),
.sw_reset (sw_reset_in),
.sw_stop (sw_stop_in),
.length (length_counter),
.eop_enabled (descriptor_end_on_eop_enable_d1),
.eop (snk_eop),
.ready (snk_ready),
.valid (snk_valid),
.early_termination (early_termination),
.address_in (address),
.write_in (write),
.max_burst_count (maximum_burst_count),
.write_fifo_used ({fifo_full,fifo_used}),
.waitrequest (master_waitrequest),
.short_first_access_enable (short_first_access_enable),
.short_last_access_enable (short_last_access_enable),
.short_first_and_last_access_enable (short_first_and_last_access_enable),
.address_out (master_address),
.write_out (master_write), // filtered version of 'write'
.burst_count (master_burstcount),
.stall (write_stall_from_write_burst_control),
.reset_taken (reset_taken_from_write_burst_control),
.stopped (stopped_from_write_burst_control)
);
defparam the_write_burst_control.BURST_ENABLE = BURST_ENABLE;
defparam the_write_burst_control.BURST_COUNT_WIDTH = MAX_BURST_COUNT_WIDTH;
defparam the_write_burst_control.WORD_SIZE = BYTE_ENABLE_WIDTH;
defparam the_write_burst_control.WORD_SIZE_LOG2 = (DATA_WIDTH == 8)? 0 : BYTE_ENABLE_WIDTH_LOG2; // need to make sure log2(word size) is 0 instead of 1 here when the data width is 8 bits
defparam the_write_burst_control.ADDRESS_WIDTH = ADDRESS_WIDTH;
defparam the_write_burst_control.LENGTH_WIDTH = LENGTH_WIDTH;
defparam the_write_burst_control.WRITE_FIFO_USED_WIDTH = FIFO_DEPTH_LOG2;
defparam the_write_burst_control.BURST_WRAPPING_SUPPORT = BURST_WRAPPING_SUPPORT;
/********************************************* END MODULE INSTANTIATIONS ************************************************************************/
/********************************************* CONTROL AND COMBINATIONAL SIGNALS ****************************************************************/
// breakout the descriptor information into more manageable names
assign descriptor_address = {snk_command_data[123:92], snk_command_data[31:0]}; // 64-bit addressing support
assign descriptor_length = snk_command_data[63:32];
assign descriptor_programmable_burst_count = snk_command_data[75:68];
assign descriptor_stride = snk_command_data[91:76];
assign descriptor_end_on_eop_enable = snk_command_data[64];
assign sw_stop_in = snk_command_data[66];
assign sw_reset_in = snk_command_data[67];
assign stride_amount = (STRIDE_ENABLE == 1)? stride_d1[STRIDE_WIDTH-1:0] : FIXED_STRIDE; // hardcoding to FIXED_STRIDE when stride capabilities are disabled
assign maximum_burst_count = (PROGRAMMABLE_BURST_ENABLE == 1)? programmable_burst_count_d1 : MAX_BURST_COUNT;
assign eop_enable = (PACKET_ENABLE == 1)? descriptor_end_on_eop_enable_d1 : 1'b0; // no eop or early termination support when packet support is disabled
assign done_strobe = (done == 1) & (done_d1 == 0) & (reset_taken == 0); // set_done asserts the done register so this strobe fires when the last write completes
assign response_error = (ERROR_ENABLE == 1)? error : 8'b00000000;
assign response_actual_bytes_transferred = (PACKET_ENABLE == 1)? actual_bytes_transferred_counter : 32'h00000000;
// transfer size amounts for special cases (starting unaligned, ending with a partial word, starting unaligned and ending with a partial word on the same write)
assign short_first_access_size = BYTE_ENABLE_WIDTH - start_byte_address;
assign short_last_access_size = (eop_enable == 1)? (packet_beat_size + packet_bytes_buffered_d1) : (length_counter & LSB_MASK);
assign short_first_and_last_access_size = (eop_enable == 1)? (BYTE_ENABLE_WIDTH - buffered_empty) : (length_counter & LSB_MASK);
/* special case transfer enables and counter increment values (address_counter, length_counter, and actual_bytes_transferred)
short_first_access_enable is for transfers that start aligned but reach the next word boundary
short_last_access_enable is for transfers that are not the first transfer but don't end with on a word boundary
short_first_and_last_access_enable is for transfers that start and end with a single transfer and don't end on a word boundary (may or may not be aligned)
*/
generate
if (UNALIGNED_ACCESSES_ENABLE == 1)
begin
// all three enables are mutually exclusive to provide one-hot encoding for the bytes to transfer mux
assign short_first_access_enable = (start_byte_address != 0) & (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) >= BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 0));
assign short_last_access_enable = (first_access == 0) & ((eop_enable == 1)? ((packet_beat_size + packet_bytes_buffered_d1) < BYTE_ENABLE_WIDTH): (length_counter < BYTE_ENABLE_WIDTH));
assign short_first_and_last_access_enable = (first_access == 1) & ((eop_enable == 1)? ((start_byte_address + BYTE_ENABLE_WIDTH - buffered_empty) < BYTE_ENABLE_WIDTH) : (first_word_boundary_not_reached_d1 == 1));
assign bytes_to_transfer = bytes_to_transfer_mux;
assign address_increment = bytes_to_transfer_mux; // can't use stride when unaligned accesses are enabled
end
else if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = 0;
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = BYTE_ENABLE_WIDTH;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH; // the byte address portion of the address_counter is grounded to make sure the address presented to the fabric is aligned
end
end
else // must be aligned but can end with any number of bytes
begin
assign short_first_access_enable = 0;
assign short_last_access_enable = (eop_enable == 1)? (buffered_eop == 1) : (length_counter < BYTE_ENABLE_WIDTH); // less than a word to transfer
assign short_first_and_last_access_enable = 0;
assign bytes_to_transfer = bytes_to_transfer_mux;
if (STRIDE_ENABLE == 1)
begin
assign address_increment = BYTE_ENABLE_WIDTH * stride_amount;
end
else
begin
assign address_increment = BYTE_ENABLE_WIDTH;
end
end
endgenerate
// the control logic ensures this mux is one-hot with the fall through being the typical full word aligned access
always @ (short_first_access_enable or short_last_access_enable or short_first_and_last_access_enable or short_first_access_size or short_last_access_size or short_first_and_last_access_size)
begin
case ({short_first_and_last_access_enable, short_last_access_enable, short_first_access_enable})
3'b001: bytes_to_transfer_mux = short_first_access_size; // unaligned and reaches the next word boundary
3'b010: bytes_to_transfer_mux = short_last_access_size; // aligned and does not reach the next word boundary
3'b100: bytes_to_transfer_mux = short_first_and_last_access_size; // unaligned and does not reach the next word boundary
default: bytes_to_transfer_mux = BYTE_ENABLE_WIDTH; // aligned and reaches the next word boundary (i.e. a full word transfer)
endcase
end
// Avalon-ST is network order (a.k.a. big endian) so we need to reverse the symbols before jamming them into the FIFO, changing the symbol width to something other than 8 might break something...
generate
genvar i;
for(i = 0; i < DATA_WIDTH; i = i + SYMBOL_WIDTH) // the data width is always a multiple of the symbol width
begin: symbol_swap
assign fifo_write_data[i +SYMBOL_WIDTH -1: i] = snk_data[DATA_WIDTH -i -1: DATA_WIDTH -i - SYMBOL_WIDTH];
end
endgenerate
// sticking the error, empty, eop, and eop bits at the top of the FIFO write data, flooring empty to zero when eop is not asserted (empty is only valid on eop cycles)
assign fifo_write_data[FIFO_WIDTH-1:DATA_WIDTH] = {snk_error, (snk_eop == 1)? snk_empty:0, snk_sop, snk_eop};
// swap the bytes if big endian is enabled (remember that this isn't tested so use at your own risk and make sure you understand the software impact this has)
generate
if(BIG_ENDIAN_ACCESS == 1)
begin
genvar j;
for(j=0; j < DATA_WIDTH; j = j + 8)
begin: byte_swap
assign fifo_read_data_rearranged[j +8 -1: j] = fifo_read_data[DATA_WIDTH -j -1: DATA_WIDTH -j - 8];
assign master_byteenable[j/8] = supported_byteenable[(DATA_WIDTH -j -1)/8];
end
end
else
begin
assign fifo_read_data_rearranged = fifo_read_data[DATA_WIDTH-1:0]; // little endian so no byte swapping necessary
assign master_byteenable = supported_byteenable; // dito
end
endgenerate
// fifo read data is in the format of {error, empty, sop, eop, data} with the following widths {ERROR_WIDTH, NUMBER_OF_SYMBOLS_LOG2, 1, 1, DATA_WIDTH}
assign buffered_data = fifo_read_data_rearranged;
assign buffered_error = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 + ERROR_WIDTH -1: DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2];
generate
if (PACKET_ENABLE == 1)
begin
assign buffered_eop = fifo_read_data[DATA_WIDTH];
assign buffered_sop = fifo_read_data[DATA_WIDTH +1];
if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign buffered_empty = 0; // ignore the empty signal and assume it was a full beat
end
else
begin
assign buffered_empty = fifo_read_data[DATA_WIDTH +2 +NUMBER_OF_SYMBOLS_LOG2 -1: DATA_WIDTH +2]; // empty is packed into the upper FIFO bits
end
end
else
begin
assign buffered_empty = 0;
assign buffered_eop = 0;
assign buffered_sop = 0;
end
endgenerate
/* Generating mask bits based on the size of the transfer before the unaligned access adjustment. This is based on the
transfer size to determine how many byte enables would be asserted in the aligned case. Afterwards the
byte enables will be shifted left based on how far out of alignment the address counter is (should only happen for the
first transfer). If the data path is 32 bits wide then the following masks are generated:
Transfer Size Index Mask
1 0 0001
2 1 0011
3 2 0111
4 3 1111
Note that the index is just the transfer size minus one
*/
generate if (BYTE_ENABLE_WIDTH > 1)
begin
genvar k;
for (k = 0; k < BYTE_ENABLE_WIDTH; k = k + 1)
begin: byte_enable_loop
assign byteenable_masks[k] = { {(BYTE_ENABLE_WIDTH-k-1){1'b0}}, {(k+1){1'b1}} }; // Byte enable width - k zeros followed by k ones
end
end
else
begin
assign byteenable_masks[0] = 1'b1; // will be stubbed at top level
end
endgenerate
/* byteenable_mask is based on an aligned access determined by the transfer size. This value is then shifted
to the left by the unaligned offset (first transfer only) to compensate for the unaligned offset so that the
correct byte enables are enabled. When the accesses are aligned then no barrelshifting is needed and when full
accesses are used then all byte enables will be asserted always. */
generate if (ONLY_FULL_ACCESS_ENABLE == 1)
begin
assign unsupported_byteenable = {BYTE_ENABLE_WIDTH{1'b1}}; // always full accesses so the byte enables are all ones
end
else if (UNALIGNED_ACCESSES_ENABLE == 0)
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1]; // aligned so no unaligned adjustment required
end
else // unaligned case
begin
assign unsupported_byteenable = byteenable_masks[bytes_to_transfer_mux - 1] << (address_counter & LSB_MASK); // barrelshift adjusts for unaligned start address
end
endgenerate
generate if (BYTE_ENABLE_WIDTH > 1)
begin
assign address = address_counter & { {(ADDRESS_WIDTH-BYTE_ENABLE_WIDTH_LOG2){1'b1}}, {BYTE_ENABLE_WIDTH_LOG2{1'b0}} }; // masking LSBs (byte offsets) since the address counter might not be aligned for the first transfer
end
else
begin
assign address = address_counter; // don't need to mask any bits as the address will only advance one byte at a time
end
endgenerate
assign done = (length_counter == 0) | ((PACKET_ENABLE == 1) & (eop_enable == 1) & (eop_seen == 1) & (extra_write == 0));
assign packet_beat_size = (eop_seen == 1) ? 0 : (BYTE_ENABLE_WIDTH - buffered_empty); // when the eop arrives we can't add more to packet_bytes_buffered_d1
assign packet_bytes_buffered = packet_beat_size + packet_bytes_buffered_d1 - bytes_to_transfer;
// extra_write is only applicable when unaligned accesses are performed. This extra access gets the remaining data buffered in the ST to MM adapter block written to memory
assign extra_write = (UNALIGNED_ACCESSES_ENABLE == 1) & (((PACKET_ENABLE == 1) & (eop_enable == 1))?
((eop_seen == 1) & (packet_bytes_buffered_d1 != 0)) : // when packets are used if there are left over bytes buffered after eop is seen perform an extra write
((first_access == 0) & (start_byte_address != 0) & (short_last_access_enable == 1) & (start_byte_address >= length_counter[BYTE_ENABLE_WIDTH_LOG2-1:0]))); // non-packet transfer and there are extra bytes buffered so performing an extra access
assign first_word_boundary_not_reached = (descriptor_length < BYTE_ENABLE_WIDTH) & // length is less than the word size
(((descriptor_length & LSB_MASK) + (descriptor_address & LSB_MASK)) < BYTE_ENABLE_WIDTH); // start address + length doesn't reach the next word boundary (not used for packet transfers)
assign write = ((fifo_empty == 0) | (extra_write == 1)) & (done == 0) & (stopped == 0);
assign st_to_mm_adapter_enable = (done == 0) & (extra_write == 0);
assign write_complete = (write == 1) & (master_waitrequest == 0) & (write_stall_from_byte_enable_generator == 0) & (write_stall_from_write_burst_control == 0); // writing still occuring and no reasons to prevent the write cycle from completing
assign increment_address = ((write == 1) & (write_complete == 1)) & (stopped == 0);
assign go = (snk_command_valid == 1) & (snk_command_ready == 1); // go with be one cycle since done will be set to 0 on the next cycle (length will be non-zero)
assign snk_ready = (fifo_full == 0) & // need to make sure more streaming data doesn't come in when the FIFO is full
(((PACKET_ENABLE == 1) & (snk_sop == 1) & (fifo_empty == 0)) != 1); // need to make sure that only one packet is buffered at any given time (sop will continue to be asserted until the buffer is written out)
assign length_sync_reset = (((reset_taken == 1) | (early_termination_d1 == 1)) & (done == 0)) | (done_strobe == 1); // abrupt stop cases or packet transfer just completed (otherwise the length register will reach 0 by itself)
assign fifo_write = (snk_ready == 1) & (snk_valid == 1);
assign early_termination = (eop_enable == 1) & (write_complete == 1) & (length_counter < bytes_to_transfer); // packet transfer and the length counter is about to roll over so stop transfering
assign stop_state = stopped;
assign reset_delayed = (reset_taken == 0) & (sw_reset_in == 1);
assign src_response_data = {{212{1'b0}}, done_strobe, early_termination_d1, response_error, stop_state, reset_delayed, response_actual_bytes_transferred};
/********************************************* END CONTROL AND COMBINATIONAL SIGNALS ************************************************************/
endmodule
|
/**********************************************************
-- (c) Copyright 2011 - 2014 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). A Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
//
// THIS NOTICE MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
//
//
// Owner: Gary Martin
// Revision: $Id: //depot/icm/proj/common/head/rtl/v32_cmt/rtl/phy/phy_4lanes.v#6 $
// $Author: gary $
// $DateTime: 2010/05/11 18:05:17 $
// $Change: 490882 $
// Description:
// This verilog file is the parameterizable 4-byte lane phy primitive top
// This module may be ganged to create an N-lane phy.
//
// History:
// Date Engineer Description
// 04/01/2010 G. Martin Initial Checkin.
//
///////////////////////////////////////////////////////////
**********************************************************/
`timescale 1ps/1ps
`define PC_DATA_OFFSET_RANGE 22:17
module mig_7series_v2_3_ddr_phy_4lanes #(
parameter GENERATE_IDELAYCTRL = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 1,
parameter BANK_TYPE = "HP_IO", // # = "HP_IO", "HPL_IO", "HR_IO", "HRL_IO"
parameter BYTELANES_DDR_CK = 24'b0010_0010_0010_0010_0010_0010,
parameter NUM_DDR_CK = 1,
// next three parameter fields correspond to byte lanes for lane order DCBA
parameter BYTE_LANES = 4'b1111, // lane existence, one per lane
parameter DATA_CTL_N = 4'b1111, // data or control, per lane
parameter BITLANES = 48'hffff_ffff_ffff,
parameter BITLANES_OUTONLY = 48'h0000_0000_0000,
parameter LANE_REMAP = 16'h3210,// 4-bit index
// used to rewire to one of four
// input/output buss lanes
// example: 0321 remaps lanes as:
// D->A
// C->D
// B->C
// A->B
parameter LAST_BANK = "FALSE",
parameter USE_PRE_POST_FIFO = "FALSE",
parameter RCLK_SELECT_LANE = "B",
parameter real TCK = 0.00,
parameter SYNTHESIS = "FALSE",
parameter PO_CTL_COARSE_BYPASS = "FALSE",
parameter PO_FINE_DELAY = 0,
parameter PI_SEL_CLK_OFFSET = 0,
// phy_control paramter used in other paramsters
parameter PC_CLK_RATIO = 4,
//phaser_in parameters
parameter A_PI_FREQ_REF_DIV = "NONE",
parameter A_PI_CLKOUT_DIV = 2,
parameter A_PI_BURST_MODE = "TRUE",
parameter A_PI_OUTPUT_CLK_SRC = "DELAYED_REF" , //"DELAYED_REF",
parameter A_PI_FINE_DELAY = 60,
parameter A_PI_SYNC_IN_DIV_RST = "TRUE",
parameter B_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter B_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter B_PI_BURST_MODE = A_PI_BURST_MODE,
parameter B_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter B_PI_FINE_DELAY = A_PI_FINE_DELAY,
parameter B_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter C_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter C_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter C_PI_BURST_MODE = A_PI_BURST_MODE,
parameter C_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter C_PI_FINE_DELAY = 0,
parameter C_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
parameter D_PI_FREQ_REF_DIV = A_PI_FREQ_REF_DIV,
parameter D_PI_CLKOUT_DIV = A_PI_CLKOUT_DIV,
parameter D_PI_BURST_MODE = A_PI_BURST_MODE,
parameter D_PI_OUTPUT_CLK_SRC = A_PI_OUTPUT_CLK_SRC,
parameter D_PI_FINE_DELAY = 0,
parameter D_PI_SYNC_IN_DIV_RST = A_PI_SYNC_IN_DIV_RST,
//phaser_out parameters
parameter A_PO_CLKOUT_DIV = (DATA_CTL_N[0] == 0) ? PC_CLK_RATIO : 2,
parameter A_PO_FINE_DELAY = PO_FINE_DELAY,
parameter A_PO_COARSE_DELAY = 0,
parameter A_PO_OCLK_DELAY = 0,
parameter A_PO_OCLKDELAY_INV = "FALSE",
parameter A_PO_OUTPUT_CLK_SRC = "DELAYED_REF",
parameter A_PO_SYNC_IN_DIV_RST = "TRUE",
//parameter A_PO_SYNC_IN_DIV_RST = "FALSE",
parameter B_PO_CLKOUT_DIV = (DATA_CTL_N[1] == 0) ? PC_CLK_RATIO : 2,
parameter B_PO_FINE_DELAY = PO_FINE_DELAY,
parameter B_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter B_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter B_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter B_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter B_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter C_PO_CLKOUT_DIV = (DATA_CTL_N[2] == 0) ? PC_CLK_RATIO : 2,
parameter C_PO_FINE_DELAY = PO_FINE_DELAY,
parameter C_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter C_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter C_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter C_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter C_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter D_PO_CLKOUT_DIV = (DATA_CTL_N[3] == 0) ? PC_CLK_RATIO : 2,
parameter D_PO_FINE_DELAY = PO_FINE_DELAY,
parameter D_PO_COARSE_DELAY = A_PO_COARSE_DELAY,
parameter D_PO_OCLK_DELAY = A_PO_OCLK_DELAY,
parameter D_PO_OCLKDELAY_INV = A_PO_OCLKDELAY_INV,
parameter D_PO_OUTPUT_CLK_SRC = A_PO_OUTPUT_CLK_SRC,
parameter D_PO_SYNC_IN_DIV_RST = A_PO_SYNC_IN_DIV_RST,
parameter A_IDELAYE2_IDELAY_TYPE = "VARIABLE",
parameter A_IDELAYE2_IDELAY_VALUE = 00,
parameter B_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter B_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter C_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter C_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
parameter D_IDELAYE2_IDELAY_TYPE = A_IDELAYE2_IDELAY_TYPE,
parameter D_IDELAYE2_IDELAY_VALUE = A_IDELAYE2_IDELAY_VALUE,
// phy_control parameters
parameter PC_BURST_MODE = "TRUE",
parameter PC_DATA_CTL_N = DATA_CTL_N,
parameter PC_CMD_OFFSET = 0,
parameter PC_RD_CMD_OFFSET_0 = 0,
parameter PC_RD_CMD_OFFSET_1 = 0,
parameter PC_RD_CMD_OFFSET_2 = 0,
parameter PC_RD_CMD_OFFSET_3 = 0,
parameter PC_CO_DURATION = 1,
parameter PC_DI_DURATION = 1,
parameter PC_DO_DURATION = 1,
parameter PC_RD_DURATION_0 = 0,
parameter PC_RD_DURATION_1 = 0,
parameter PC_RD_DURATION_2 = 0,
parameter PC_RD_DURATION_3 = 0,
parameter PC_WR_CMD_OFFSET_0 = 5,
parameter PC_WR_CMD_OFFSET_1 = 5,
parameter PC_WR_CMD_OFFSET_2 = 5,
parameter PC_WR_CMD_OFFSET_3 = 5,
parameter PC_WR_DURATION_0 = 6,
parameter PC_WR_DURATION_1 = 6,
parameter PC_WR_DURATION_2 = 6,
parameter PC_WR_DURATION_3 = 6,
parameter PC_AO_WRLVL_EN = 0,
parameter PC_AO_TOGGLE = 4'b0101, // odd bits are toggle (CKE)
parameter PC_FOUR_WINDOW_CLOCKS = 63,
parameter PC_EVENTS_DELAY = 18,
parameter PC_PHY_COUNT_EN = "TRUE",
parameter PC_SYNC_MODE = "TRUE",
parameter PC_DISABLE_SEQ_MATCH = "TRUE",
parameter PC_MULTI_REGION = "FALSE",
// io fifo parameters
parameter A_OF_ARRAY_MODE = (DATA_CTL_N[0] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter B_OF_ARRAY_MODE = (DATA_CTL_N[1] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter C_OF_ARRAY_MODE = (DATA_CTL_N[2] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter D_OF_ARRAY_MODE = (DATA_CTL_N[3] == 1) ? "ARRAY_MODE_8_X_4" : "ARRAY_MODE_4_X_4",
parameter OF_ALMOST_EMPTY_VALUE = 1,
parameter OF_ALMOST_FULL_VALUE = 1,
parameter OF_OUTPUT_DISABLE = "TRUE",
parameter OF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
parameter A_OS_DATA_RATE = "DDR",
parameter A_OS_DATA_WIDTH = 4,
parameter B_OS_DATA_RATE = A_OS_DATA_RATE,
parameter B_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter C_OS_DATA_RATE = A_OS_DATA_RATE,
parameter C_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter D_OS_DATA_RATE = A_OS_DATA_RATE,
parameter D_OS_DATA_WIDTH = A_OS_DATA_WIDTH,
parameter A_IF_ARRAY_MODE = "ARRAY_MODE_4_X_8",
parameter B_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter C_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter D_IF_ARRAY_MODE = A_IF_ARRAY_MODE,
parameter IF_ALMOST_EMPTY_VALUE = 1,
parameter IF_ALMOST_FULL_VALUE = 1,
parameter IF_SYNCHRONOUS_MODE = PC_SYNC_MODE,
// this is used locally, not for external pushdown
// NOTE: the 0+ is needed in each to coerce to integer for addition.
// otherwise 4x 1'b values are added producing a 1'b value.
parameter HIGHEST_LANE = LAST_BANK == "FALSE" ? 4 : (BYTE_LANES[3] ? 4 : BYTE_LANES[2] ? 3 : BYTE_LANES[1] ? 2 : 1),
parameter N_CTL_LANES = ((0+(!DATA_CTL_N[0]) & BYTE_LANES[0]) + (0+(!DATA_CTL_N[1]) & BYTE_LANES[1]) + (0+(!DATA_CTL_N[2]) & BYTE_LANES[2]) + (0+(!DATA_CTL_N[3]) & BYTE_LANES[3])),
parameter N_BYTE_LANES = (0+BYTE_LANES[0]) + (0+BYTE_LANES[1]) + (0+BYTE_LANES[2]) + (0+BYTE_LANES[3]),
parameter N_DATA_LANES = N_BYTE_LANES - N_CTL_LANES,
// assume odt per rank + any declared cke's
parameter AUXOUT_WIDTH = 4,
parameter LP_DDR_CK_WIDTH = 2
,parameter CKE_ODT_AUX = "FALSE"
)
(
//`include "phy.vh"
input rst,
input phy_clk,
input phy_ctl_clk,
input freq_refclk,
input mem_refclk,
input mem_refclk_div4,
input pll_lock,
input sync_pulse,
input idelayctrl_refclk,
input [HIGHEST_LANE*80-1:0] phy_dout,
input phy_cmd_wr_en,
input phy_data_wr_en,
input phy_rd_en,
input phy_ctl_mstr_empty,
input [31:0] phy_ctl_wd,
input [`PC_DATA_OFFSET_RANGE] data_offset,
input phy_ctl_wr,
input if_empty_def,
input phyGo,
input input_sink,
output [(LP_DDR_CK_WIDTH*24)-1:0] ddr_clk, // to memory
output rclk,
output if_a_empty,
output if_empty,
output byte_rd_en,
output if_empty_or,
output if_empty_and,
output of_ctl_a_full,
output of_data_a_full,
output of_ctl_full,
output of_data_full,
output pre_data_a_full,
output [HIGHEST_LANE*80-1:0]phy_din, // assume input bus same size as output bus
output phy_ctl_empty,
output phy_ctl_a_full,
output phy_ctl_full,
output [HIGHEST_LANE*12-1:0]mem_dq_out,
output [HIGHEST_LANE*12-1:0]mem_dq_ts,
input [HIGHEST_LANE*10-1:0]mem_dq_in,
output [HIGHEST_LANE-1:0] mem_dqs_out,
output [HIGHEST_LANE-1:0] mem_dqs_ts,
input [HIGHEST_LANE-1:0] mem_dqs_in,
input [1:0] byte_rd_en_oth_banks,
output [AUXOUT_WIDTH-1:0] aux_out,
output reg rst_out = 0,
output reg mcGo=0,
output phy_ctl_ready,
output ref_dll_lock,
input if_rst,
input phy_read_calib,
input phy_write_calib,
input idelay_inc,
input idelay_ce,
input idelay_ld,
input [2:0] calib_sel,
input calib_zero_ctrl,
input [HIGHEST_LANE-1:0] calib_zero_lanes,
input calib_in_common,
input po_fine_enable,
input po_coarse_enable,
input po_fine_inc,
input po_coarse_inc,
input po_counter_load_en,
input po_counter_read_en,
input [8:0] po_counter_load_val,
input po_sel_fine_oclk_delay,
output reg po_coarse_overflow,
output reg po_fine_overflow,
output reg [8:0] po_counter_read_val,
input pi_rst_dqs_find,
input pi_fine_enable,
input pi_fine_inc,
input pi_counter_load_en,
input pi_counter_read_en,
input [5:0] pi_counter_load_val,
output reg pi_fine_overflow,
output reg [5:0] pi_counter_read_val,
output reg pi_dqs_found,
output pi_dqs_found_all,
output pi_dqs_found_any,
output [HIGHEST_LANE-1:0] pi_phase_locked_lanes,
output [HIGHEST_LANE-1:0] pi_dqs_found_lanes,
output reg pi_dqs_out_of_range,
output reg pi_phase_locked,
output pi_phase_locked_all,
input [29:0] fine_delay,
input fine_delay_sel
);
localparam DATA_CTL_A = (~DATA_CTL_N[0]);
localparam DATA_CTL_B = (~DATA_CTL_N[1]);
localparam DATA_CTL_C = (~DATA_CTL_N[2]);
localparam DATA_CTL_D = (~DATA_CTL_N[3]);
localparam PRESENT_CTL_A = BYTE_LANES[0] && ! DATA_CTL_N[0];
localparam PRESENT_CTL_B = BYTE_LANES[1] && ! DATA_CTL_N[1];
localparam PRESENT_CTL_C = BYTE_LANES[2] && ! DATA_CTL_N[2];
localparam PRESENT_CTL_D = BYTE_LANES[3] && ! DATA_CTL_N[3];
localparam PRESENT_DATA_A = BYTE_LANES[0] && DATA_CTL_N[0];
localparam PRESENT_DATA_B = BYTE_LANES[1] && DATA_CTL_N[1];
localparam PRESENT_DATA_C = BYTE_LANES[2] && DATA_CTL_N[2];
localparam PRESENT_DATA_D = BYTE_LANES[3] && DATA_CTL_N[3];
localparam PC_DATA_CTL_A = (DATA_CTL_A) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_B = (DATA_CTL_B) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_C = (DATA_CTL_C) ? "FALSE" : "TRUE";
localparam PC_DATA_CTL_D = (DATA_CTL_D) ? "FALSE" : "TRUE";
localparam A_PO_COARSE_BYPASS = (DATA_CTL_A) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam B_PO_COARSE_BYPASS = (DATA_CTL_B) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam C_PO_COARSE_BYPASS = (DATA_CTL_C) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam D_PO_COARSE_BYPASS = (DATA_CTL_D) ? PO_CTL_COARSE_BYPASS : "FALSE";
localparam IO_A_START = 41;
localparam IO_A_END = 40;
localparam IO_B_START = 43;
localparam IO_B_END = 42;
localparam IO_C_START = 45;
localparam IO_C_END = 44;
localparam IO_D_START = 47;
localparam IO_D_END = 46;
localparam IO_A_X_START = (HIGHEST_LANE * 10) + 1;
localparam IO_A_X_END = (IO_A_X_START-1);
localparam IO_B_X_START = (IO_A_X_START + 2);
localparam IO_B_X_END = (IO_B_X_START -1);
localparam IO_C_X_START = (IO_B_X_START + 2);
localparam IO_C_X_END = (IO_C_X_START -1);
localparam IO_D_X_START = (IO_C_X_START + 2);
localparam IO_D_X_END = (IO_D_X_START -1);
localparam MSB_BURST_PEND_PO = 3;
localparam MSB_BURST_PEND_PI = 7;
localparam MSB_RANK_SEL_I = MSB_BURST_PEND_PI + 8;
localparam PHASER_CTL_BUS_WIDTH = MSB_RANK_SEL_I + 1;
wire [1:0] oserdes_dqs;
wire [1:0] oserdes_dqs_ts;
wire [1:0] oserdes_dq_ts;
wire [PHASER_CTL_BUS_WIDTH-1:0] phaser_ctl_bus;
wire [7:0] in_rank;
wire [11:0] IO_A;
wire [11:0] IO_B;
wire [11:0] IO_C;
wire [11:0] IO_D;
wire [319:0] phy_din_remap;
reg A_po_counter_read_en;
wire [8:0] A_po_counter_read_val;
reg A_pi_counter_read_en;
wire [5:0] A_pi_counter_read_val;
wire A_pi_fine_overflow;
wire A_po_coarse_overflow;
wire A_po_fine_overflow;
wire A_pi_dqs_found;
wire A_pi_dqs_out_of_range;
wire A_pi_phase_locked;
wire A_pi_iserdes_rst;
reg A_pi_fine_enable;
reg A_pi_fine_inc;
reg A_pi_counter_load_en;
reg [5:0] A_pi_counter_load_val;
reg A_pi_rst_dqs_find;
reg A_po_fine_enable;
reg A_po_coarse_enable;
reg A_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg A_po_sel_fine_oclk_delay;
reg A_po_coarse_inc;
reg A_po_counter_load_en;
reg [8:0] A_po_counter_load_val;
wire A_rclk;
reg A_idelay_ce;
reg A_idelay_ld;
reg [29:0] A_fine_delay;
reg A_fine_delay_sel;
reg B_po_counter_read_en;
wire [8:0] B_po_counter_read_val;
reg B_pi_counter_read_en;
wire [5:0] B_pi_counter_read_val;
wire B_pi_fine_overflow;
wire B_po_coarse_overflow;
wire B_po_fine_overflow;
wire B_pi_phase_locked;
wire B_pi_iserdes_rst;
wire B_pi_dqs_found;
wire B_pi_dqs_out_of_range;
reg B_pi_fine_enable;
reg B_pi_fine_inc;
reg B_pi_counter_load_en;
reg [5:0] B_pi_counter_load_val;
reg B_pi_rst_dqs_find;
reg B_po_fine_enable;
reg B_po_coarse_enable;
reg B_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg B_po_coarse_inc;
reg B_po_sel_fine_oclk_delay;
reg B_po_counter_load_en;
reg [8:0] B_po_counter_load_val;
wire B_rclk;
reg B_idelay_ce;
reg B_idelay_ld;
reg [29:0] B_fine_delay;
reg B_fine_delay_sel;
reg C_pi_fine_inc;
reg D_pi_fine_inc;
reg C_pi_fine_enable;
reg D_pi_fine_enable;
reg C_po_counter_load_en;
reg D_po_counter_load_en;
reg C_po_coarse_inc;
reg D_po_coarse_inc;
reg C_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg D_po_fine_inc /* synthesis syn_maxfan = 3 */;
reg C_po_sel_fine_oclk_delay;
reg D_po_sel_fine_oclk_delay;
reg [5:0] C_pi_counter_load_val;
reg [5:0] D_pi_counter_load_val;
reg [8:0] C_po_counter_load_val;
reg [8:0] D_po_counter_load_val;
reg C_po_coarse_enable;
reg D_po_coarse_enable;
reg C_po_fine_enable;
reg D_po_fine_enable;
wire C_po_coarse_overflow;
wire D_po_coarse_overflow;
wire C_po_fine_overflow;
wire D_po_fine_overflow;
wire [8:0] C_po_counter_read_val;
wire [8:0] D_po_counter_read_val;
reg C_po_counter_read_en;
reg D_po_counter_read_en;
wire C_pi_dqs_found;
wire D_pi_dqs_found;
wire C_pi_fine_overflow;
wire D_pi_fine_overflow;
reg C_pi_counter_read_en;
reg D_pi_counter_read_en;
reg C_pi_counter_load_en;
reg D_pi_counter_load_en;
wire C_pi_phase_locked;
wire C_pi_iserdes_rst;
wire D_pi_phase_locked;
wire D_pi_iserdes_rst;
wire C_pi_dqs_out_of_range;
wire D_pi_dqs_out_of_range;
wire [5:0] C_pi_counter_read_val;
wire [5:0] D_pi_counter_read_val;
wire C_rclk;
wire D_rclk;
reg C_idelay_ce;
reg D_idelay_ce;
reg C_idelay_ld;
reg D_idelay_ld;
reg C_pi_rst_dqs_find;
reg D_pi_rst_dqs_find;
reg [29:0] C_fine_delay;
reg [29:0] D_fine_delay;
reg C_fine_delay_sel;
reg D_fine_delay_sel;
wire pi_iserdes_rst;
wire A_if_empty;
wire B_if_empty;
wire C_if_empty;
wire D_if_empty;
wire A_byte_rd_en;
wire B_byte_rd_en;
wire C_byte_rd_en;
wire D_byte_rd_en;
wire A_if_a_empty;
wire B_if_a_empty;
wire C_if_a_empty;
wire D_if_a_empty;
//wire A_if_full;
//wire B_if_full;
//wire C_if_full;
//wire D_if_full;
//wire A_of_empty;
//wire B_of_empty;
//wire C_of_empty;
//wire D_of_empty;
wire A_of_full;
wire B_of_full;
wire C_of_full;
wire D_of_full;
wire A_of_ctl_full;
wire B_of_ctl_full;
wire C_of_ctl_full;
wire D_of_ctl_full;
wire A_of_data_full;
wire B_of_data_full;
wire C_of_data_full;
wire D_of_data_full;
wire A_of_a_full;
wire B_of_a_full;
wire C_of_a_full;
wire D_of_a_full;
wire A_pre_fifo_a_full;
wire B_pre_fifo_a_full;
wire C_pre_fifo_a_full;
wire D_pre_fifo_a_full;
wire A_of_ctl_a_full;
wire B_of_ctl_a_full;
wire C_of_ctl_a_full;
wire D_of_ctl_a_full;
wire A_of_data_a_full;
wire B_of_data_a_full;
wire C_of_data_a_full;
wire D_of_data_a_full;
wire A_pre_data_a_full;
wire B_pre_data_a_full;
wire C_pre_data_a_full;
wire D_pre_data_a_full;
wire [LP_DDR_CK_WIDTH*6-1:0] A_ddr_clk; // for generation
wire [LP_DDR_CK_WIDTH*6-1:0] B_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] C_ddr_clk; //
wire [LP_DDR_CK_WIDTH*6-1:0] D_ddr_clk; //
wire [3:0] dummy_data;
wire [31:0] _phy_ctl_wd;
wire [1:0] phy_encalib;
assign pi_dqs_found_all =
(! PRESENT_DATA_A | A_pi_dqs_found) &
(! PRESENT_DATA_B | B_pi_dqs_found) &
(! PRESENT_DATA_C | C_pi_dqs_found) &
(! PRESENT_DATA_D | D_pi_dqs_found) ;
assign pi_dqs_found_any =
( PRESENT_DATA_A & A_pi_dqs_found) |
( PRESENT_DATA_B & B_pi_dqs_found) |
( PRESENT_DATA_C & C_pi_dqs_found) |
( PRESENT_DATA_D & D_pi_dqs_found) ;
assign pi_phase_locked_all =
(! PRESENT_DATA_A | A_pi_phase_locked) &
(! PRESENT_DATA_B | B_pi_phase_locked) &
(! PRESENT_DATA_C | C_pi_phase_locked) &
(! PRESENT_DATA_D | D_pi_phase_locked);
wire dangling_inputs = (& dummy_data) & input_sink & 1'b0; // this reduces all constant 0 values to 1 signal
// which is combined into another signals such that
// the other signal isn't changed. The purpose
// is to fake the tools into ignoring dangling inputs.
// Because it is anded with 1'b0, the contributing signals
// are folded as constants or trimmed.
assign if_empty = !if_empty_def ? (A_if_empty | B_if_empty | C_if_empty | D_if_empty) : (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign byte_rd_en = !if_empty_def ? (A_byte_rd_en & B_byte_rd_en & C_byte_rd_en & D_byte_rd_en) :
(A_byte_rd_en | B_byte_rd_en | C_byte_rd_en | D_byte_rd_en);
assign if_empty_or = (A_if_empty | B_if_empty | C_if_empty | D_if_empty);
assign if_empty_and = (A_if_empty & B_if_empty & C_if_empty & D_if_empty);
assign if_a_empty = A_if_a_empty | B_if_a_empty | C_if_a_empty | D_if_a_empty;
//assign if_full = A_if_full | B_if_full | C_if_full | D_if_full ;
//assign of_empty = A_of_empty & B_of_empty & C_of_empty & D_of_empty;
assign of_ctl_full = A_of_ctl_full | B_of_ctl_full | C_of_ctl_full | D_of_ctl_full ;
assign of_data_full = A_of_data_full | B_of_data_full | C_of_data_full | D_of_data_full ;
assign of_ctl_a_full = A_of_ctl_a_full | B_of_ctl_a_full | C_of_ctl_a_full | D_of_ctl_a_full ;
assign of_data_a_full = A_of_data_a_full | B_of_data_a_full | C_of_data_a_full | D_of_data_a_full | dangling_inputs ;
assign pre_data_a_full = A_pre_data_a_full | B_pre_data_a_full | C_pre_data_a_full | D_pre_data_a_full;
function [79:0] part_select_80;
input [319:0] vector;
input [1:0] select;
begin
case (select)
2'b00 : part_select_80[79:0] = vector[1*80-1:0*80];
2'b01 : part_select_80[79:0] = vector[2*80-1:1*80];
2'b10 : part_select_80[79:0] = vector[3*80-1:2*80];
2'b11 : part_select_80[79:0] = vector[4*80-1:3*80];
endcase
end
endfunction
wire [319:0] phy_dout_remap;
reg rst_out_trig = 1'b0;
reg [31:0] rclk_delay;
reg rst_edge1 = 1'b0;
reg rst_edge2 = 1'b0;
reg rst_edge3 = 1'b0;
reg rst_edge_detect = 1'b0;
wire rclk_;
reg rst_out_start = 1'b0 ;
reg rst_primitives=0;
reg A_rst_primitives=0;
reg B_rst_primitives=0;
reg C_rst_primitives=0;
reg D_rst_primitives=0;
`ifdef USE_PHY_CONTROL_TEST
wire [15:0] test_output;
wire [15:0] test_input;
wire [2:0] test_select=0;
wire scan_enable = 0;
`endif
generate
genvar i;
if (RCLK_SELECT_LANE == "A") begin
assign rclk_ = A_rclk;
assign pi_iserdes_rst = A_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "B") begin
assign rclk_ = B_rclk;
assign pi_iserdes_rst = B_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "C") begin
assign rclk_ = C_rclk;
assign pi_iserdes_rst = C_pi_iserdes_rst;
end
else if (RCLK_SELECT_LANE == "D") begin
assign rclk_ = D_rclk;
assign pi_iserdes_rst = D_pi_iserdes_rst;
end
else begin
assign rclk_ = B_rclk; // default
end
endgenerate
assign ddr_clk[LP_DDR_CK_WIDTH*6-1:0] = A_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*12-1:LP_DDR_CK_WIDTH*6] = B_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*18-1:LP_DDR_CK_WIDTH*12] = C_ddr_clk;
assign ddr_clk[LP_DDR_CK_WIDTH*24-1:LP_DDR_CK_WIDTH*18] = D_ddr_clk;
assign pi_phase_locked_lanes =
{(! PRESENT_DATA_A[0] | A_pi_phase_locked),
(! PRESENT_DATA_B[0] | B_pi_phase_locked) ,
(! PRESENT_DATA_C[0] | C_pi_phase_locked) ,
(! PRESENT_DATA_D[0] | D_pi_phase_locked)};
assign pi_dqs_found_lanes = {D_pi_dqs_found, C_pi_dqs_found, B_pi_dqs_found, A_pi_dqs_found};
// this block scrubs X from rclk_delay[11]
reg rclk_delay_11;
always @(rclk_delay[11]) begin : rclk_delay_11_blk
if ( rclk_delay[11])
rclk_delay_11 = 1;
else
rclk_delay_11 = 0;
end
always @(posedge phy_clk or posedge rst ) begin
// scrub 4-state values from rclk_delay[11]
if ( rst) begin
rst_out <= #1 0;
end
else begin
if ( rclk_delay_11)
rst_out <= #1 1;
end
end
always @(posedge phy_clk ) begin
// phy_ctl_ready drives reset of the system
rst_primitives <= !phy_ctl_ready ;
A_rst_primitives <= rst_primitives ;
B_rst_primitives <= rst_primitives ;
C_rst_primitives <= rst_primitives ;
D_rst_primitives <= rst_primitives ;
rclk_delay <= #1 (rclk_delay << 1) | (!rst_primitives && phyGo);
mcGo <= #1 rst_out ;
end
generate
if (BYTE_LANES[0]) begin
assign dummy_data[0] = 0;
end
else begin
assign dummy_data[0] = &phy_dout_remap[1*80-1:0*80];
end
if (BYTE_LANES[1]) begin
assign dummy_data[1] = 0;
end
else begin
assign dummy_data[1] = &phy_dout_remap[2*80-1:1*80];
end
if (BYTE_LANES[2]) begin
assign dummy_data[2] = 0;
end
else begin
assign dummy_data[2] = &phy_dout_remap[3*80-1:2*80];
end
if (BYTE_LANES[3]) begin
assign dummy_data[3] = 0;
end
else begin
assign dummy_data[3] = &phy_dout_remap[4*80-1:3*80];
end
if (PRESENT_DATA_A) begin
assign A_of_data_full = A_of_full;
assign A_of_ctl_full = 0;
assign A_of_data_a_full = A_of_a_full;
assign A_of_ctl_a_full = 0;
assign A_pre_data_a_full = A_pre_fifo_a_full;
end
else begin
assign A_of_ctl_full = A_of_full;
assign A_of_data_full = 0;
assign A_of_ctl_a_full = A_of_a_full;
assign A_of_data_a_full = 0;
assign A_pre_data_a_full = 0;
end
if (PRESENT_DATA_B) begin
assign B_of_data_full = B_of_full;
assign B_of_ctl_full = 0;
assign B_of_data_a_full = B_of_a_full;
assign B_of_ctl_a_full = 0;
assign B_pre_data_a_full = B_pre_fifo_a_full;
end
else begin
assign B_of_ctl_full = B_of_full;
assign B_of_data_full = 0;
assign B_of_ctl_a_full = B_of_a_full;
assign B_of_data_a_full = 0;
assign B_pre_data_a_full = 0;
end
if (PRESENT_DATA_C) begin
assign C_of_data_full = C_of_full;
assign C_of_ctl_full = 0;
assign C_of_data_a_full = C_of_a_full;
assign C_of_ctl_a_full = 0;
assign C_pre_data_a_full = C_pre_fifo_a_full;
end
else begin
assign C_of_ctl_full = C_of_full;
assign C_of_data_full = 0;
assign C_of_ctl_a_full = C_of_a_full;
assign C_of_data_a_full = 0;
assign C_pre_data_a_full = 0;
end
if (PRESENT_DATA_D) begin
assign D_of_data_full = D_of_full;
assign D_of_ctl_full = 0;
assign D_of_data_a_full = D_of_a_full;
assign D_of_ctl_a_full = 0;
assign D_pre_data_a_full = D_pre_fifo_a_full;
end
else begin
assign D_of_ctl_full = D_of_full;
assign D_of_data_full = 0;
assign D_of_ctl_a_full = D_of_a_full;
assign D_of_data_a_full = 0;
assign D_pre_data_a_full = 0;
end
// byte lane must exist and be data lane.
if (PRESENT_DATA_A )
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[79:0];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[79:0];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[79:0];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[79:0];
endcase
else
case ( LANE_REMAP[1:0] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_B )
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[159:80];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[159:80];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[159:80];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[159:80];
endcase
else
if (HIGHEST_LANE > 1)
case ( LANE_REMAP[5:4] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_C)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[239:160];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[239:160];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[239:160];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[239:160];
endcase
else
if (HIGHEST_LANE > 2)
case ( LANE_REMAP[9:8] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (PRESENT_DATA_D )
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = phy_din_remap[319:240];
2'b01 : assign phy_din[2*80-1:80] = phy_din_remap[319:240];
2'b10 : assign phy_din[3*80-1:160] = phy_din_remap[319:240];
2'b11 : assign phy_din[4*80-1:240] = phy_din_remap[319:240];
endcase
else
if (HIGHEST_LANE > 3)
case ( LANE_REMAP[13:12] )
2'b00 : assign phy_din[1*80-1:0] = 80'h0;
2'b01 : assign phy_din[2*80-1:80] = 80'h0;
2'b10 : assign phy_din[3*80-1:160] = 80'h0;
2'b11 : assign phy_din[4*80-1:240] = 80'h0;
endcase
if (HIGHEST_LANE > 1)
assign _phy_ctl_wd = {phy_ctl_wd[31:23], data_offset, phy_ctl_wd[16:0]};
if (HIGHEST_LANE == 1)
assign _phy_ctl_wd = phy_ctl_wd;
//BUFR #(.BUFR_DIVIDE ("1")) rclk_buf(.I(rclk_), .O(rclk), .CE (1'b1), .CLR (pi_iserdes_rst));
BUFIO rclk_buf(.I(rclk_), .O(rclk) );
if ( BYTE_LANES[0] ) begin : ddr_byte_lane_A
assign phy_dout_remap[79:0] = part_select_80(phy_dout, (LANE_REMAP[1:0]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("A"),
.PO_DATA_CTL (PC_DATA_CTL_N[0] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[11:0]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[11:0]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (A_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (A_PI_BURST_MODE),
.PI_CLKOUT_DIV (A_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (A_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (A_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (A_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (A_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (A_PO_CLKOUT_DIV),
.PO_FINE_DELAY (A_PO_FINE_DELAY),
.PO_COARSE_BYPASS (A_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (A_PO_COARSE_DELAY),
.PO_OCLK_DELAY (A_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (A_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (A_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (A_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (A_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (A_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (A_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (A_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_A(
.mem_dq_out (mem_dq_out[11:0]),
.mem_dq_ts (mem_dq_ts[11:0]),
.mem_dq_in (mem_dq_in[9:0]),
.mem_dqs_out (mem_dqs_out[0]),
.mem_dqs_ts (mem_dqs_ts[0]),
.mem_dqs_in (mem_dqs_in[0]),
.rst (A_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (A_ddr_clk),
.rclk (A_rclk),
.pi_dqs_found (A_pi_dqs_found),
.dqs_out_of_range (A_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (A_if_a_empty),
.if_empty (A_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*A_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*A_of_empty*/),
.of_a_full (A_of_a_full),
.of_full (A_of_full),
.pre_fifo_a_full (A_pre_fifo_a_full),
.phy_din (phy_din_remap[79:0]),
.phy_dout (phy_dout_remap[79:0]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({B_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (A_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (A_idelay_ce),
.idelay_ld (A_idelay_ld),
.pi_rst_dqs_find (A_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (A_po_fine_enable),
.po_coarse_enable (A_po_coarse_enable),
.po_fine_inc (A_po_fine_inc),
.po_coarse_inc (A_po_coarse_inc),
.po_counter_load_en (A_po_counter_load_en),
.po_counter_read_en (A_po_counter_read_en),
.po_counter_load_val (A_po_counter_load_val),
.po_coarse_overflow (A_po_coarse_overflow),
.po_fine_overflow (A_po_fine_overflow),
.po_counter_read_val (A_po_counter_read_val),
.po_sel_fine_oclk_delay(A_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (A_pi_fine_enable),
.pi_fine_inc (A_pi_fine_inc),
.pi_counter_load_en (A_pi_counter_load_en),
.pi_counter_read_en (A_pi_counter_read_en),
.pi_counter_load_val (A_pi_counter_load_val),
.pi_fine_overflow (A_pi_fine_overflow),
.pi_counter_read_val (A_pi_counter_read_val),
.pi_iserdes_rst (A_pi_iserdes_rst),
.pi_phase_locked (A_pi_phase_locked),
.fine_delay (A_fine_delay),
.fine_delay_sel (A_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_A
assign A_of_a_full = 1'b0;
assign A_of_full = 1'b0;
assign A_pre_fifo_a_full = 1'b0;
assign A_if_empty = 1'b0;
assign A_byte_rd_en = 1'b1;
assign A_if_a_empty = 1'b0;
assign A_pi_phase_locked = 1;
assign A_pi_dqs_found = 1;
assign A_rclk = 0;
assign A_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign A_pi_counter_read_val = 0;
assign A_po_counter_read_val = 0;
assign A_pi_fine_overflow = 0;
assign A_po_coarse_overflow = 0;
assign A_po_fine_overflow = 0;
end
if ( BYTE_LANES[1] ) begin : ddr_byte_lane_B
assign phy_dout_remap[159:80] = part_select_80(phy_dout, (LANE_REMAP[5:4]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("B"),
.PO_DATA_CTL (PC_DATA_CTL_N[1] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[23:12]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[23:12]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (B_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (B_PI_BURST_MODE),
.PI_CLKOUT_DIV (B_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (B_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (B_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (B_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (B_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (B_PO_CLKOUT_DIV),
.PO_FINE_DELAY (B_PO_FINE_DELAY),
.PO_COARSE_BYPASS (B_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (B_PO_COARSE_DELAY),
.PO_OCLK_DELAY (B_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (B_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (B_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (B_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (B_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (B_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (B_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (B_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_B(
.mem_dq_out (mem_dq_out[23:12]),
.mem_dq_ts (mem_dq_ts[23:12]),
.mem_dq_in (mem_dq_in[19:10]),
.mem_dqs_out (mem_dqs_out[1]),
.mem_dqs_ts (mem_dqs_ts[1]),
.mem_dqs_in (mem_dqs_in[1]),
.rst (B_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (B_ddr_clk),
.rclk (B_rclk),
.pi_dqs_found (B_pi_dqs_found),
.dqs_out_of_range (B_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (B_if_a_empty),
.if_empty (B_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*B_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*B_of_empty*/),
.of_a_full (B_of_a_full),
.of_full (B_of_full),
.pre_fifo_a_full (B_pre_fifo_a_full),
.phy_din (phy_din_remap[159:80]),
.phy_dout (phy_dout_remap[159:80]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,C_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (B_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (B_idelay_ce),
.idelay_ld (B_idelay_ld),
.pi_rst_dqs_find (B_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (B_po_fine_enable),
.po_coarse_enable (B_po_coarse_enable),
.po_fine_inc (B_po_fine_inc),
.po_coarse_inc (B_po_coarse_inc),
.po_counter_load_en (B_po_counter_load_en),
.po_counter_read_en (B_po_counter_read_en),
.po_counter_load_val (B_po_counter_load_val),
.po_coarse_overflow (B_po_coarse_overflow),
.po_fine_overflow (B_po_fine_overflow),
.po_counter_read_val (B_po_counter_read_val),
.po_sel_fine_oclk_delay(B_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (B_pi_fine_enable),
.pi_fine_inc (B_pi_fine_inc),
.pi_counter_load_en (B_pi_counter_load_en),
.pi_counter_read_en (B_pi_counter_read_en),
.pi_counter_load_val (B_pi_counter_load_val),
.pi_fine_overflow (B_pi_fine_overflow),
.pi_counter_read_val (B_pi_counter_read_val),
.pi_iserdes_rst (B_pi_iserdes_rst),
.pi_phase_locked (B_pi_phase_locked),
.fine_delay (B_fine_delay),
.fine_delay_sel (B_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_B
assign B_of_a_full = 1'b0;
assign B_of_full = 1'b0;
assign B_pre_fifo_a_full = 1'b0;
assign B_if_empty = 1'b0;
assign B_if_a_empty = 1'b0;
assign B_byte_rd_en = 1'b1;
assign B_pi_phase_locked = 1;
assign B_pi_dqs_found = 1;
assign B_rclk = 0;
assign B_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign B_pi_counter_read_val = 0;
assign B_po_counter_read_val = 0;
assign B_pi_fine_overflow = 0;
assign B_po_coarse_overflow = 0;
assign B_po_fine_overflow = 0;
end
if ( BYTE_LANES[2] ) begin : ddr_byte_lane_C
assign phy_dout_remap[239:160] = part_select_80(phy_dout, (LANE_REMAP[9:8]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("C"),
.PO_DATA_CTL (PC_DATA_CTL_N[2] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[35:24]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[35:24]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (C_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (C_PI_BURST_MODE),
.PI_CLKOUT_DIV (C_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (C_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (C_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (C_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (C_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (C_PO_CLKOUT_DIV),
.PO_FINE_DELAY (C_PO_FINE_DELAY),
.PO_COARSE_BYPASS (C_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (C_PO_COARSE_DELAY),
.PO_OCLK_DELAY (C_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (C_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (C_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (C_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (C_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (C_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (C_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (C_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_C(
.mem_dq_out (mem_dq_out[35:24]),
.mem_dq_ts (mem_dq_ts[35:24]),
.mem_dq_in (mem_dq_in[29:20]),
.mem_dqs_out (mem_dqs_out[2]),
.mem_dqs_ts (mem_dqs_ts[2]),
.mem_dqs_in (mem_dqs_in[2]),
.rst (C_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (C_ddr_clk),
.rclk (C_rclk),
.pi_dqs_found (C_pi_dqs_found),
.dqs_out_of_range (C_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (C_if_a_empty),
.if_empty (C_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*C_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*C_of_empty*/),
.of_a_full (C_of_a_full),
.of_full (C_of_full),
.pre_fifo_a_full (C_pre_fifo_a_full),
.phy_din (phy_din_remap[239:160]),
.phy_dout (phy_dout_remap[239:160]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,D_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (C_byte_rd_en),
// calibration signals
.idelay_inc (idelay_inc),
.idelay_ce (C_idelay_ce),
.idelay_ld (C_idelay_ld),
.pi_rst_dqs_find (C_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (C_po_fine_enable),
.po_coarse_enable (C_po_coarse_enable),
.po_fine_inc (C_po_fine_inc),
.po_coarse_inc (C_po_coarse_inc),
.po_counter_load_en (C_po_counter_load_en),
.po_counter_read_en (C_po_counter_read_en),
.po_counter_load_val (C_po_counter_load_val),
.po_coarse_overflow (C_po_coarse_overflow),
.po_fine_overflow (C_po_fine_overflow),
.po_counter_read_val (C_po_counter_read_val),
.po_sel_fine_oclk_delay(C_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (C_pi_fine_enable),
.pi_fine_inc (C_pi_fine_inc),
.pi_counter_load_en (C_pi_counter_load_en),
.pi_counter_read_en (C_pi_counter_read_en),
.pi_counter_load_val (C_pi_counter_load_val),
.pi_fine_overflow (C_pi_fine_overflow),
.pi_counter_read_val (C_pi_counter_read_val),
.pi_iserdes_rst (C_pi_iserdes_rst),
.pi_phase_locked (C_pi_phase_locked),
.fine_delay (C_fine_delay),
.fine_delay_sel (C_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_C
assign C_of_a_full = 1'b0;
assign C_of_full = 1'b0;
assign C_pre_fifo_a_full = 1'b0;
assign C_if_empty = 1'b0;
assign C_byte_rd_en = 1'b1;
assign C_if_a_empty = 1'b0;
assign C_pi_phase_locked = 1;
assign C_pi_dqs_found = 1;
assign C_rclk = 0;
assign C_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign C_pi_counter_read_val = 0;
assign C_po_counter_read_val = 0;
assign C_pi_fine_overflow = 0;
assign C_po_coarse_overflow = 0;
assign C_po_fine_overflow = 0;
end
if ( BYTE_LANES[3] ) begin : ddr_byte_lane_D
assign phy_dout_remap[319:240] = part_select_80(phy_dout, (LANE_REMAP[13:12]));
mig_7series_v2_3_ddr_byte_lane #
(
.ABCD ("D"),
.PO_DATA_CTL (PC_DATA_CTL_N[3] ? "TRUE" : "FALSE"),
.BITLANES (BITLANES[47:36]),
.BITLANES_OUTONLY (BITLANES_OUTONLY[47:36]),
.OF_ALMOST_EMPTY_VALUE (OF_ALMOST_EMPTY_VALUE),
.OF_ALMOST_FULL_VALUE (OF_ALMOST_FULL_VALUE),
.OF_SYNCHRONOUS_MODE (OF_SYNCHRONOUS_MODE),
//.OF_OUTPUT_DISABLE (OF_OUTPUT_DISABLE),
//.OF_ARRAY_MODE (D_OF_ARRAY_MODE),
//.IF_ARRAY_MODE (IF_ARRAY_MODE),
.IF_ALMOST_EMPTY_VALUE (IF_ALMOST_EMPTY_VALUE),
.IF_ALMOST_FULL_VALUE (IF_ALMOST_FULL_VALUE),
.IF_SYNCHRONOUS_MODE (IF_SYNCHRONOUS_MODE),
.IODELAY_GRP (IODELAY_GRP),
.FPGA_SPEED_GRADE (FPGA_SPEED_GRADE),
.BANK_TYPE (BANK_TYPE),
.BYTELANES_DDR_CK (BYTELANES_DDR_CK),
.RCLK_SELECT_LANE (RCLK_SELECT_LANE),
.USE_PRE_POST_FIFO (USE_PRE_POST_FIFO),
.SYNTHESIS (SYNTHESIS),
.TCK (TCK),
.PC_CLK_RATIO (PC_CLK_RATIO),
.PI_BURST_MODE (D_PI_BURST_MODE),
.PI_CLKOUT_DIV (D_PI_CLKOUT_DIV),
.PI_FREQ_REF_DIV (D_PI_FREQ_REF_DIV),
.PI_FINE_DELAY (D_PI_FINE_DELAY),
.PI_OUTPUT_CLK_SRC (D_PI_OUTPUT_CLK_SRC),
.PI_SYNC_IN_DIV_RST (D_PI_SYNC_IN_DIV_RST),
.PI_SEL_CLK_OFFSET (PI_SEL_CLK_OFFSET),
.PO_CLKOUT_DIV (D_PO_CLKOUT_DIV),
.PO_FINE_DELAY (D_PO_FINE_DELAY),
.PO_COARSE_BYPASS (D_PO_COARSE_BYPASS),
.PO_COARSE_DELAY (D_PO_COARSE_DELAY),
.PO_OCLK_DELAY (D_PO_OCLK_DELAY),
.PO_OCLKDELAY_INV (D_PO_OCLKDELAY_INV),
.PO_OUTPUT_CLK_SRC (D_PO_OUTPUT_CLK_SRC),
.PO_SYNC_IN_DIV_RST (D_PO_SYNC_IN_DIV_RST),
.OSERDES_DATA_RATE (D_OS_DATA_RATE),
.OSERDES_DATA_WIDTH (D_OS_DATA_WIDTH),
.IDELAYE2_IDELAY_TYPE (D_IDELAYE2_IDELAY_TYPE),
.IDELAYE2_IDELAY_VALUE (D_IDELAYE2_IDELAY_VALUE)
,.CKE_ODT_AUX (CKE_ODT_AUX)
)
ddr_byte_lane_D(
.mem_dq_out (mem_dq_out[47:36]),
.mem_dq_ts (mem_dq_ts[47:36]),
.mem_dq_in (mem_dq_in[39:30]),
.mem_dqs_out (mem_dqs_out[3]),
.mem_dqs_ts (mem_dqs_ts[3]),
.mem_dqs_in (mem_dqs_in[3]),
.rst (D_rst_primitives),
.phy_clk (phy_clk),
.freq_refclk (freq_refclk),
.mem_refclk (mem_refclk),
.idelayctrl_refclk (idelayctrl_refclk),
.sync_pulse (sync_pulse),
.ddr_ck_out (D_ddr_clk),
.rclk (D_rclk),
.pi_dqs_found (D_pi_dqs_found),
.dqs_out_of_range (D_pi_dqs_out_of_range),
.if_empty_def (if_empty_def),
.if_a_empty (D_if_a_empty),
.if_empty (D_if_empty),
.if_a_full (/*if_a_full*/),
.if_full (/*D_if_full*/),
.of_a_empty (/*of_a_empty*/),
.of_empty (/*D_of_empty*/),
.of_a_full (D_of_a_full),
.of_full (D_of_full),
.pre_fifo_a_full (D_pre_fifo_a_full),
.phy_din (phy_din_remap[319:240]),
.phy_dout (phy_dout_remap[319:240]),
.phy_cmd_wr_en (phy_cmd_wr_en),
.phy_data_wr_en (phy_data_wr_en),
.phy_rd_en (phy_rd_en),
.phaser_ctl_bus (phaser_ctl_bus),
.idelay_inc (idelay_inc),
.idelay_ce (D_idelay_ce),
.idelay_ld (D_idelay_ld),
.if_rst (if_rst),
.byte_rd_en_oth_lanes ({A_byte_rd_en,B_byte_rd_en,C_byte_rd_en}),
.byte_rd_en_oth_banks (byte_rd_en_oth_banks),
.byte_rd_en (D_byte_rd_en),
// calibration signals
.pi_rst_dqs_find (D_pi_rst_dqs_find),
.po_en_calib (phy_encalib),
.po_fine_enable (D_po_fine_enable),
.po_coarse_enable (D_po_coarse_enable),
.po_fine_inc (D_po_fine_inc),
.po_coarse_inc (D_po_coarse_inc),
.po_counter_load_en (D_po_counter_load_en),
.po_counter_read_en (D_po_counter_read_en),
.po_counter_load_val (D_po_counter_load_val),
.po_coarse_overflow (D_po_coarse_overflow),
.po_fine_overflow (D_po_fine_overflow),
.po_counter_read_val (D_po_counter_read_val),
.po_sel_fine_oclk_delay(D_po_sel_fine_oclk_delay),
.pi_en_calib (phy_encalib),
.pi_fine_enable (D_pi_fine_enable),
.pi_fine_inc (D_pi_fine_inc),
.pi_counter_load_en (D_pi_counter_load_en),
.pi_counter_read_en (D_pi_counter_read_en),
.pi_counter_load_val (D_pi_counter_load_val),
.pi_fine_overflow (D_pi_fine_overflow),
.pi_counter_read_val (D_pi_counter_read_val),
.pi_iserdes_rst (D_pi_iserdes_rst),
.pi_phase_locked (D_pi_phase_locked),
.fine_delay (D_fine_delay),
.fine_delay_sel (D_fine_delay_sel)
);
end
else begin : no_ddr_byte_lane_D
assign D_of_a_full = 1'b0;
assign D_of_full = 1'b0;
assign D_pre_fifo_a_full = 1'b0;
assign D_if_empty = 1'b0;
assign D_byte_rd_en = 1'b1;
assign D_if_a_empty = 1'b0;
assign D_rclk = 0;
assign D_ddr_clk = {LP_DDR_CK_WIDTH*6{1'b0}};
assign D_pi_dqs_found = 1;
assign D_pi_phase_locked = 1;
assign D_pi_counter_read_val = 0;
assign D_po_counter_read_val = 0;
assign D_pi_fine_overflow = 0;
assign D_po_coarse_overflow = 0;
assign D_po_fine_overflow = 0;
end
endgenerate
assign phaser_ctl_bus[MSB_RANK_SEL_I : MSB_RANK_SEL_I - 7] = in_rank;
PHY_CONTROL #(
.AO_WRLVL_EN ( PC_AO_WRLVL_EN),
.AO_TOGGLE ( PC_AO_TOGGLE),
.BURST_MODE ( PC_BURST_MODE),
.CO_DURATION ( PC_CO_DURATION ),
.CLK_RATIO ( PC_CLK_RATIO),
.DATA_CTL_A_N ( PC_DATA_CTL_A),
.DATA_CTL_B_N ( PC_DATA_CTL_B),
.DATA_CTL_C_N ( PC_DATA_CTL_C),
.DATA_CTL_D_N ( PC_DATA_CTL_D),
.DI_DURATION ( PC_DI_DURATION ),
.DO_DURATION ( PC_DO_DURATION ),
.EVENTS_DELAY ( PC_EVENTS_DELAY),
.FOUR_WINDOW_CLOCKS ( PC_FOUR_WINDOW_CLOCKS),
.MULTI_REGION ( PC_MULTI_REGION ),
.PHY_COUNT_ENABLE ( PC_PHY_COUNT_EN),
.DISABLE_SEQ_MATCH ( PC_DISABLE_SEQ_MATCH),
.SYNC_MODE ( PC_SYNC_MODE),
.CMD_OFFSET ( PC_CMD_OFFSET),
.RD_CMD_OFFSET_0 ( PC_RD_CMD_OFFSET_0),
.RD_CMD_OFFSET_1 ( PC_RD_CMD_OFFSET_1),
.RD_CMD_OFFSET_2 ( PC_RD_CMD_OFFSET_2),
.RD_CMD_OFFSET_3 ( PC_RD_CMD_OFFSET_3),
.RD_DURATION_0 ( PC_RD_DURATION_0),
.RD_DURATION_1 ( PC_RD_DURATION_1),
.RD_DURATION_2 ( PC_RD_DURATION_2),
.RD_DURATION_3 ( PC_RD_DURATION_3),
.WR_CMD_OFFSET_0 ( PC_WR_CMD_OFFSET_0),
.WR_CMD_OFFSET_1 ( PC_WR_CMD_OFFSET_1),
.WR_CMD_OFFSET_2 ( PC_WR_CMD_OFFSET_2),
.WR_CMD_OFFSET_3 ( PC_WR_CMD_OFFSET_3),
.WR_DURATION_0 ( PC_WR_DURATION_0),
.WR_DURATION_1 ( PC_WR_DURATION_1),
.WR_DURATION_2 ( PC_WR_DURATION_2),
.WR_DURATION_3 ( PC_WR_DURATION_3)
) phy_control_i (
.AUXOUTPUT (aux_out),
.INBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PI:MSB_BURST_PEND_PI-3]),
.INRANKA (in_rank[1:0]),
.INRANKB (in_rank[3:2]),
.INRANKC (in_rank[5:4]),
.INRANKD (in_rank[7:6]),
.OUTBURSTPENDING (phaser_ctl_bus[MSB_BURST_PEND_PO:MSB_BURST_PEND_PO-3]),
.PCENABLECALIB (phy_encalib),
.PHYCTLALMOSTFULL (phy_ctl_a_full),
.PHYCTLEMPTY (phy_ctl_empty),
.PHYCTLFULL (phy_ctl_full),
.PHYCTLREADY (phy_ctl_ready),
.MEMREFCLK (mem_refclk),
.PHYCLK (phy_ctl_clk),
.PHYCTLMSTREMPTY (phy_ctl_mstr_empty),
.PHYCTLWD (_phy_ctl_wd),
.PHYCTLWRENABLE (phy_ctl_wr),
.PLLLOCK (pll_lock),
.REFDLLLOCK (ref_dll_lock), // is reset while !locked
.RESET (rst),
.SYNCIN (sync_pulse),
.READCALIBENABLE (phy_read_calib),
.WRITECALIBENABLE (phy_write_calib)
`ifdef USE_PHY_CONTROL_TEST
, .TESTINPUT (16'b0),
.TESTOUTPUT (test_output),
.TESTSELECT (test_select),
.SCANENABLEN (scan_enable)
`endif
);
// register outputs to give extra slack in timing
always @(posedge phy_clk ) begin
case (calib_sel[1:0])
2'h0: begin
po_coarse_overflow <= #1 A_po_coarse_overflow;
po_fine_overflow <= #1 A_po_fine_overflow;
po_counter_read_val <= #1 A_po_counter_read_val;
pi_fine_overflow <= #1 A_pi_fine_overflow;
pi_counter_read_val<= #1 A_pi_counter_read_val;
pi_phase_locked <= #1 A_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 A_pi_dqs_found;
pi_dqs_out_of_range <= #1 A_pi_dqs_out_of_range;
end
2'h1: begin
po_coarse_overflow <= #1 B_po_coarse_overflow;
po_fine_overflow <= #1 B_po_fine_overflow;
po_counter_read_val <= #1 B_po_counter_read_val;
pi_fine_overflow <= #1 B_pi_fine_overflow;
pi_counter_read_val <= #1 B_pi_counter_read_val;
pi_phase_locked <= #1 B_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 B_pi_dqs_found;
pi_dqs_out_of_range <= #1 B_pi_dqs_out_of_range;
end
2'h2: begin
po_coarse_overflow <= #1 C_po_coarse_overflow;
po_fine_overflow <= #1 C_po_fine_overflow;
po_counter_read_val <= #1 C_po_counter_read_val;
pi_fine_overflow <= #1 C_pi_fine_overflow;
pi_counter_read_val <= #1 C_pi_counter_read_val;
pi_phase_locked <= #1 C_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 C_pi_dqs_found;
pi_dqs_out_of_range <= #1 C_pi_dqs_out_of_range;
end
2'h3: begin
po_coarse_overflow <= #1 D_po_coarse_overflow;
po_fine_overflow <= #1 D_po_fine_overflow;
po_counter_read_val <= #1 D_po_counter_read_val;
pi_fine_overflow <= #1 D_pi_fine_overflow;
pi_counter_read_val <= #1 D_pi_counter_read_val;
pi_phase_locked <= #1 D_pi_phase_locked;
if ( calib_in_common)
pi_dqs_found <= #1 pi_dqs_found_any;
else
pi_dqs_found <= #1 D_pi_dqs_found;
pi_dqs_out_of_range <= #1 D_pi_dqs_out_of_range;
end
default: begin
po_coarse_overflow <= po_coarse_overflow;
end
endcase
end
wire B_mux_ctrl;
wire C_mux_ctrl;
wire D_mux_ctrl;
generate
if (HIGHEST_LANE > 1)
assign B_mux_ctrl = ( !calib_zero_lanes[1] && ( ! calib_zero_ctrl || DATA_CTL_N[1]));
else
assign B_mux_ctrl = 0;
if (HIGHEST_LANE > 2)
assign C_mux_ctrl = ( !calib_zero_lanes[2] && (! calib_zero_ctrl || DATA_CTL_N[2]));
else
assign C_mux_ctrl = 0;
if (HIGHEST_LANE > 3)
assign D_mux_ctrl = ( !calib_zero_lanes[3] && ( ! calib_zero_ctrl || DATA_CTL_N[3]));
else
assign D_mux_ctrl = 0;
endgenerate
always @(*) begin
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
if ( calib_sel[2]) begin
// if this is asserted, all calib signals are deasserted
A_pi_fine_enable = 0;
A_pi_fine_inc = 0;
A_pi_counter_load_en = 0;
A_pi_counter_read_en = 0;
A_pi_counter_load_val = 0;
A_pi_rst_dqs_find = 0;
A_po_fine_enable = 0;
A_po_coarse_enable = 0;
A_po_fine_inc = 0;
A_po_coarse_inc = 0;
A_po_counter_load_en = 0;
A_po_counter_read_en = 0;
A_po_counter_load_val = 0;
A_po_sel_fine_oclk_delay = 0;
A_idelay_ce = 0;
A_idelay_ld = 0;
A_fine_delay = 0;
A_fine_delay_sel = 0;
B_pi_fine_enable = 0;
B_pi_fine_inc = 0;
B_pi_counter_load_en = 0;
B_pi_counter_read_en = 0;
B_pi_counter_load_val = 0;
B_pi_rst_dqs_find = 0;
B_po_fine_enable = 0;
B_po_coarse_enable = 0;
B_po_fine_inc = 0;
B_po_coarse_inc = 0;
B_po_counter_load_en = 0;
B_po_counter_read_en = 0;
B_po_counter_load_val = 0;
B_po_sel_fine_oclk_delay = 0;
B_idelay_ce = 0;
B_idelay_ld = 0;
B_fine_delay = 0;
B_fine_delay_sel = 0;
C_pi_fine_enable = 0;
C_pi_fine_inc = 0;
C_pi_counter_load_en = 0;
C_pi_counter_read_en = 0;
C_pi_counter_load_val = 0;
C_pi_rst_dqs_find = 0;
C_po_fine_enable = 0;
C_po_coarse_enable = 0;
C_po_fine_inc = 0;
C_po_coarse_inc = 0;
C_po_counter_load_en = 0;
C_po_counter_read_en = 0;
C_po_counter_load_val = 0;
C_po_sel_fine_oclk_delay = 0;
C_idelay_ce = 0;
C_idelay_ld = 0;
C_fine_delay = 0;
C_fine_delay_sel = 0;
D_pi_fine_enable = 0;
D_pi_fine_inc = 0;
D_pi_counter_load_en = 0;
D_pi_counter_read_en = 0;
D_pi_counter_load_val = 0;
D_pi_rst_dqs_find = 0;
D_po_fine_enable = 0;
D_po_coarse_enable = 0;
D_po_fine_inc = 0;
D_po_coarse_inc = 0;
D_po_counter_load_en = 0;
D_po_counter_read_en = 0;
D_po_counter_load_val = 0;
D_po_sel_fine_oclk_delay = 0;
D_idelay_ce = 0;
D_idelay_ld = 0;
D_fine_delay = 0;
D_fine_delay_sel = 0;
end else
if (calib_in_common) begin
// if this is asserted, each signal is broadcast to all phasers
// in common
if ( !calib_zero_lanes[0] && (! calib_zero_ctrl || DATA_CTL_N[0])) begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
if ( B_mux_ctrl) begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
if ( C_mux_ctrl) begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
if ( D_mux_ctrl) begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_read_en = po_counter_read_en;
D_po_counter_load_val = po_counter_load_val;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
end
else begin
// otherwise, only a single phaser is selected
case (calib_sel[1:0])
0: begin
A_pi_fine_enable = pi_fine_enable;
A_pi_fine_inc = pi_fine_inc;
A_pi_counter_load_en = pi_counter_load_en;
A_pi_counter_read_en = pi_counter_read_en;
A_pi_counter_load_val = pi_counter_load_val;
A_pi_rst_dqs_find = pi_rst_dqs_find;
A_po_fine_enable = po_fine_enable;
A_po_coarse_enable = po_coarse_enable;
A_po_fine_inc = po_fine_inc;
A_po_coarse_inc = po_coarse_inc;
A_po_counter_load_en = po_counter_load_en;
A_po_counter_read_en = po_counter_read_en;
A_po_counter_load_val = po_counter_load_val;
A_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
A_idelay_ce = idelay_ce;
A_idelay_ld = idelay_ld;
A_fine_delay = fine_delay ;
A_fine_delay_sel = fine_delay_sel;
end
1: begin
B_pi_fine_enable = pi_fine_enable;
B_pi_fine_inc = pi_fine_inc;
B_pi_counter_load_en = pi_counter_load_en;
B_pi_counter_read_en = pi_counter_read_en;
B_pi_counter_load_val = pi_counter_load_val;
B_pi_rst_dqs_find = pi_rst_dqs_find;
B_po_fine_enable = po_fine_enable;
B_po_coarse_enable = po_coarse_enable;
B_po_fine_inc = po_fine_inc;
B_po_coarse_inc = po_coarse_inc;
B_po_counter_load_en = po_counter_load_en;
B_po_counter_read_en = po_counter_read_en;
B_po_counter_load_val = po_counter_load_val;
B_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
B_idelay_ce = idelay_ce;
B_idelay_ld = idelay_ld;
B_fine_delay = fine_delay ;
B_fine_delay_sel = fine_delay_sel;
end
2: begin
C_pi_fine_enable = pi_fine_enable;
C_pi_fine_inc = pi_fine_inc;
C_pi_counter_load_en = pi_counter_load_en;
C_pi_counter_read_en = pi_counter_read_en;
C_pi_counter_load_val = pi_counter_load_val;
C_pi_rst_dqs_find = pi_rst_dqs_find;
C_po_fine_enable = po_fine_enable;
C_po_coarse_enable = po_coarse_enable;
C_po_fine_inc = po_fine_inc;
C_po_coarse_inc = po_coarse_inc;
C_po_counter_load_en = po_counter_load_en;
C_po_counter_read_en = po_counter_read_en;
C_po_counter_load_val = po_counter_load_val;
C_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
C_idelay_ce = idelay_ce;
C_idelay_ld = idelay_ld;
C_fine_delay = fine_delay ;
C_fine_delay_sel = fine_delay_sel;
end
3: begin
D_pi_fine_enable = pi_fine_enable;
D_pi_fine_inc = pi_fine_inc;
D_pi_counter_load_en = pi_counter_load_en;
D_pi_counter_read_en = pi_counter_read_en;
D_pi_counter_load_val = pi_counter_load_val;
D_pi_rst_dqs_find = pi_rst_dqs_find;
D_po_fine_enable = po_fine_enable;
D_po_coarse_enable = po_coarse_enable;
D_po_fine_inc = po_fine_inc;
D_po_coarse_inc = po_coarse_inc;
D_po_counter_load_en = po_counter_load_en;
D_po_counter_load_val = po_counter_load_val;
D_po_counter_read_en = po_counter_read_en;
D_po_sel_fine_oclk_delay = po_sel_fine_oclk_delay;
D_idelay_ce = idelay_ce;
D_idelay_ld = idelay_ld;
D_fine_delay = fine_delay ;
D_fine_delay_sel = fine_delay_sel;
end
endcase
end
end
//obligatory phaser-ref
PHASER_REF phaser_ref_i(
.LOCKED (ref_dll_lock),
.CLKIN (freq_refclk),
.PWRDWN (1'b0),
.RST ( ! pll_lock)
);
// optional idelay_ctrl
generate
if ( GENERATE_IDELAYCTRL == "TRUE")
IDELAYCTRL idelayctrl (
.RDY (/*idelayctrl_rdy*/),
.REFCLK (idelayctrl_refclk),
.RST (rst)
);
endgenerate
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Basic Phase accumulator for DDS
module phase_acc (clk,reset,enable,strobe,serial_addr,serial_data,serial_strobe,phase);
parameter FREQADDR = 0;
parameter PHASEADDR = 0;
parameter resolution = 32;
input clk, reset, enable, strobe;
input [6:0] serial_addr;
input [31:0] serial_data;
input serial_strobe;
output reg [resolution-1:0] phase;
wire [resolution-1:0] freq;
setting_reg #(FREQADDR) sr_rxfreq0(.clock(clk),.reset(1'b0),.strobe(serial_strobe),.addr(serial_addr),.in(serial_data),.out(freq));
always @(posedge clk)
if(reset)
phase <= #1 32'b0;
else if(serial_strobe & (serial_addr == PHASEADDR))
phase <= #1 serial_data;
else if(enable & strobe)
phase <= #1 phase + freq;
endmodule // phase_acc
|
`timescale 1ns / 100ps
// UART Protocol Layer
module QMFIR_uart_if (/*AUTOARG*/
// Outputs
uart_dout, uart_addr, uart_mem_we, uart_mem_re, reg_we, uart_tx,
// Inputs
uart_mem_i, uart_reg_i, clk, arst_n, uart_rx
);
output [31:0] uart_dout;
output [13:0] uart_addr;
output uart_mem_we;
output uart_mem_re;
output reg_we;
output uart_tx;
input [23:0] uart_mem_i;
input [23:0] uart_reg_i;
input clk;
input arst_n;
input uart_rx;
reg [15:0] cmd;
reg [31:0] uart_dout;
parameter stIdle = 0;
parameter stCmd1 = 1;
parameter stCmd2 = 2;
parameter stData1 = 3;
parameter stData2 = 4;
parameter stData3 = 5;
parameter stData4 = 6;
parameter stWr = 7;
parameter stRd = 8;
reg [3:0] state;
reg [7:0] din_i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire [7:0] dout_o; // From uart_ of sasc_top.v
wire empty_o; // From uart_ of sasc_top.v
wire full_o; // From uart_ of sasc_top.v
wire sio_ce; // From baud_ of sasc_brg.v
wire sio_ce_x4; // From baud_ of sasc_brg.v
// End of automatics
wire cmdRd;
wire cmdMem;
reg re_i;
reg we_i;
sasc_top uart_ (// Outputs
.txd_o (uart_tx),
.rts_o (),
// Inputs
.rxd_i (uart_rx),
.cts_i (1'b0),
.rst_n (arst_n),
/*AUTOINST*/
// Outputs
.dout_o (dout_o[7:0]),
.full_o (full_o),
.empty_o (empty_o),
// Inputs
.clk (clk),
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
.din_i (din_i[7:0]),
.re_i (re_i),
.we_i (we_i));
sasc_brg baud_ (/*AUTOINST*/
// Outputs
.sio_ce (sio_ce),
.sio_ce_x4 (sio_ce_x4),
// Inputs
.clk (clk),
.arst_n (arst_n));
always @ (posedge clk or negedge arst_n)
if (~arst_n)
state <= stIdle;
else
case (state)
stIdle : if (~empty_o) state <= stCmd1;
stCmd1 : if (~empty_o) state <= stCmd2;
stCmd2 : if (cmdRd) state <= stRd; // read
else if (~empty_o) state <= stData1; // write
stData1: if (cmdRd) state <= stData2; // read
else if (~empty_o) state <= stData2; // write
stData2: if (cmdRd) state <= stData3; // read
else if (~empty_o) state <= stData3; // write
stData3: if (cmdRd) state <= stData4; // read done
else if (~empty_o) state <= stData4; //write
stData4: if (cmdRd) state <= stIdle;
else state <= stWr; // write commit
stWr: state <= stIdle;
stRd: state <= stData1;
endcase // case(state)
// --------------- Command Word Capture ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n) cmd <= 0;
else
begin
if (state==stIdle) cmd[15:8] <= dout_o[7:0];
if (state==stCmd1) cmd[7:0] <= dout_o[7:0];
end
assign cmdRd = ~cmd[15];
assign cmdMem = cmd[14];
assign uart_addr = cmd[13:0];
// --------------- Write Command ----------------- //
always @ (posedge clk or negedge arst_n)
if (~arst_n)
uart_dout <= 0;
else
begin
if (state==stCmd2 & ~cmdRd) uart_dout[31:24] <= dout_o[7:0];
if (state==stData1 & ~cmdRd) uart_dout[23:16] <= dout_o[7:0];
if (state==stData2 & ~cmdRd) uart_dout[15:8] <= dout_o[7:0];
if (state==stData3 & ~cmdRd) uart_dout[7:0] <= dout_o[7:0];
end
always @ (/*AS*/cmdRd or empty_o or state)
case (state)
stIdle : re_i = ~empty_o;
stCmd1 : re_i = ~empty_o;
stCmd2 : re_i = ~empty_o & ~cmdRd;
stData1: re_i = ~empty_o & ~cmdRd;
stData2: re_i = ~empty_o & ~cmdRd;
stData3: re_i = ~empty_o & ~cmdRd;
default: re_i = 0;
endcase // case(state)
assign uart_mem_we = (state==stWr) & cmdMem;
assign reg_we = (state==stWr) & ~cmdMem;
// --------------- Read Command ----------------- //
always @ (/*AS*/cmdMem or state or uart_mem_i or uart_reg_i)
case (state)
stData2: din_i[7:0] = cmdMem ? uart_mem_i[23:16] : uart_reg_i[23:16];
stData3: din_i[7:0] = cmdMem ? uart_mem_i[15:8] : uart_reg_i[15:8];
stData4: din_i[7:0] = cmdMem ? uart_mem_i[7:0] : uart_reg_i[7:0];
default: din_i[7:0] = cmdMem ? 0 : 0;
endcase // case(state)
always @ (/*AS*/cmdRd or state)
case (state)
stData1: we_i = cmdRd;
stData2: we_i = cmdRd;
stData3: we_i = cmdRd;
stData4: we_i = cmdRd;
default: we_i = 0;
endcase // case(state)
assign uart_mem_re = (state==stRd);
endmodule // QMFIR_uart_if
|
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: clk_doubler.v
// Megafunction Name(s):
// altpll
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 4.2 Build 156 11/29/2004 SJ Web Edition
// ************************************************************
//Copyright (C) 1991-2004 Altera Corporation
//Any megafunction design, and related netlist (encrypted or decrypted),
//support information, device programming or simulation file, and any other
//associated documentation or information provided by Altera or a partner
//under Altera's Megafunction Partnership Program may be used only
//to program PLD devices (but not masked PLD devices) from Altera. Any
//other use of such megafunction design, netlist, support information,
//device programming or simulation file, or any other related documentation
//or information is prohibited for any other purpose, including, but not
//limited to modification, reverse engineering, de-compiling, or use with
//any other silicon devices, unless such use is explicitly licensed under
//a separate agreement with Altera or a megafunction partner. Title to the
//intellectual property, including patents, copyrights, trademarks, trade
//secrets, or maskworks, embodied in any such megafunction design, netlist,
//support information, device programming or simulation file, or any other
//related documentation or information provided by Altera or a megafunction
//partner, remains with Altera, the megafunction partner, or their respective
//licensors. No other licenses, including any licenses needed under any third
//party's intellectual property, are provided herein.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module clk_doubler (
inclk0,
c0);
input inclk0;
output c0;
wire [5:0] sub_wire0;
wire [0:0] sub_wire4 = 1'h0;
wire [0:0] sub_wire1 = sub_wire0[0:0];
wire c0 = sub_wire1;
wire sub_wire2 = inclk0;
wire [1:0] sub_wire3 = {sub_wire4, sub_wire2};
altpll altpll_component (
.inclk (sub_wire3),
.clk (sub_wire0)
// synopsys translate_off
,
.activeclock (),
.areset (),
.clkbad (),
.clkena (),
.clkloss (),
.clkswitch (),
.enable0 (),
.enable1 (),
.extclk (),
.extclkena (),
.fbin (),
.locked (),
.pfdena (),
.pllena (),
.scanaclr (),
.scanclk (),
.scandata (),
.scandataout (),
.scandone (),
.scanread (),
.scanwrite (),
.sclkout0 (),
.sclkout1 ()
// synopsys translate_on
);
defparam
altpll_component.clk0_duty_cycle = 50,
altpll_component.lpm_type = "altpll",
altpll_component.clk0_multiply_by = 2,
altpll_component.inclk0_input_frequency = 15625,
altpll_component.clk0_divide_by = 1,
altpll_component.pll_type = "AUTO",
altpll_component.intended_device_family = "Cyclone",
altpll_component.operation_mode = "NORMAL",
altpll_component.compensate_clock = "CLK0",
altpll_component.clk0_phase_shift = "0";
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: MIRROR_CLK0 STRING "0"
// Retrieval info: PRIVATE: PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: SPREAD_USE STRING "0"
// Retrieval info: PRIVATE: SPREAD_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: GLOCK_COUNTER_EDIT NUMERIC "1048575"
// Retrieval info: PRIVATE: SRC_SYNCH_COMP_RADIO STRING "0"
// Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
// Retrieval info: PRIVATE: PHASE_SHIFT0 STRING "0.00000000"
// Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
// Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "0"
// Retrieval info: PRIVATE: SPREAD_PERCENT STRING "0.500"
// Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
// Retrieval info: PRIVATE: PLL_ARESET_CHECK STRING "0"
// Retrieval info: PRIVATE: STICKY_CLK0 STRING "1"
// Retrieval info: PRIVATE: BANDWIDTH STRING "1.000"
// Retrieval info: PRIVATE: BANDWIDTH_USE_CUSTOM STRING "0"
// Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
// Retrieval info: PRIVATE: SPREAD_FREQ STRING "50.000"
// Retrieval info: PRIVATE: BANDWIDTH_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
// Retrieval info: PRIVATE: PLL_ENHPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
// Retrieval info: PRIVATE: USE_CLK0 STRING "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: SCAN_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: ZERO_DELAY_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_PFDENA_CHECK STRING "0"
// Retrieval info: PRIVATE: CREATE_CLKBAD_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK1_FREQ_EDIT STRING "100.000"
// Retrieval info: PRIVATE: CUR_DEDICATED_CLK STRING "c0"
// Retrieval info: PRIVATE: PLL_FASTPLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: ACTIVECLK_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_FREQ_UNIT STRING "MHz"
// Retrieval info: PRIVATE: INCLK0_FREQ_UNIT_COMBO STRING "MHz"
// Retrieval info: PRIVATE: GLOCKED_MODE_CHECK STRING "0"
// Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: CUR_FBIN_CLK STRING "e0"
// Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
// Retrieval info: PRIVATE: INCLK1_FREQ_UNIT_CHANGED STRING "1"
// Retrieval info: PRIVATE: HAS_MANUAL_SWITCHOVER STRING "1"
// Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
// Retrieval info: PRIVATE: PLL_AUTOPLL_CHECK NUMERIC "1"
// Retrieval info: PRIVATE: CLKLOSS_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_AUTO STRING "1"
// Retrieval info: PRIVATE: SHORT_SCAN_RADIO STRING "0"
// Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "512.000"
// Retrieval info: PRIVATE: CLKSWITCH_CHECK STRING "0"
// Retrieval info: PRIVATE: SPREAD_FREQ_UNIT STRING "KHz"
// Retrieval info: PRIVATE: PLL_ENA_CHECK STRING "0"
// Retrieval info: PRIVATE: INCLK0_FREQ_EDIT STRING "64.000"
// Retrieval info: PRIVATE: CNX_NO_COMPENSATE_RADIO STRING "0"
// Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
// Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "100.000"
// Retrieval info: PRIVATE: PRIMARY_CLK_COMBO STRING "inclk0"
// Retrieval info: PRIVATE: CREATE_INCLK1_CHECK STRING "0"
// Retrieval info: PRIVATE: SACN_INPUTS_CHECK STRING "0"
// Retrieval info: PRIVATE: DEV_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LOCK_LOSS_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: SWITCHOVER_COUNT_EDIT NUMERIC "1"
// Retrieval info: PRIVATE: SWITCHOVER_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_PRESET STRING "Low"
// Retrieval info: PRIVATE: GLOCKED_FEATURE_ENABLED STRING "0"
// Retrieval info: PRIVATE: USE_CLKENA0 STRING "0"
// Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
// Retrieval info: PRIVATE: CLKBAD_SWITCHOVER_CHECK STRING "0"
// Retrieval info: PRIVATE: BANDWIDTH_USE_PRESET STRING "0"
// Retrieval info: PRIVATE: PLL_LVDS_PLL_CHECK NUMERIC "0"
// Retrieval info: PRIVATE: DEVICE_FAMILY NUMERIC "11"
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: CONSTANT: CLK0_DUTY_CYCLE NUMERIC "50"
// Retrieval info: CONSTANT: LPM_TYPE STRING "altpll"
// Retrieval info: CONSTANT: CLK0_MULTIPLY_BY NUMERIC "2"
// Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "15625"
// Retrieval info: CONSTANT: CLK0_DIVIDE_BY NUMERIC "1"
// Retrieval info: CONSTANT: PLL_TYPE STRING "AUTO"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: OPERATION_MODE STRING "NORMAL"
// Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
// Retrieval info: CONSTANT: CLK0_PHASE_SHIFT STRING "0"
// Retrieval info: USED_PORT: c0 0 0 0 0 OUTPUT VCC "c0"
// Retrieval info: USED_PORT: @clk 0 0 6 0 OUTPUT VCC "@clk[5..0]"
// Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT GND "inclk0"
// Retrieval info: USED_PORT: @extclk 0 0 4 0 OUTPUT VCC "@extclk[3..0]"
// Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
// Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
// Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.v TRUE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.inc FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.cmp FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler.bsf FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_inst.v FALSE FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL clk_doubler_bb.v TRUE FALSE
|
//*****************************************************************************
// (c) Copyright 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// Description
// This module instantiates the clock synchronization logic. It passes the
// incoming signal through two flops to ensure metastability.
//
//*****************************************************************************
`timescale 1ps / 1ps
`default_nettype none
(* DowngradeIPIdentifiedWarnings="yes" *)
module axis_infrastructure_v1_1_0_clock_synchronizer # (
///////////////////////////////////////////////////////////////////////////////
// Parameter Definitions
///////////////////////////////////////////////////////////////////////////////
parameter integer C_NUM_STAGES = 4
)
(
///////////////////////////////////////////////////////////////////////////////
// Port Declarations
///////////////////////////////////////////////////////////////////////////////
input wire clk,
input wire synch_in ,
output wire synch_out
);
////////////////////////////////////////////////////////////////////////////////
// Local Parameters
////////////////////////////////////////////////////////////////////////////////
localparam integer P_SYNCH_D_WIDTH = (C_NUM_STAGES > 0) ? C_NUM_STAGES : 1;
////////////////////////////////////////////////////////////////////////////////
// Wires/Reg declarations
////////////////////////////////////////////////////////////////////////////////
(* ASYNC_REG = "TRUE" *) reg [P_SYNCH_D_WIDTH-1:0] synch_d = 'b0;
generate
if (C_NUM_STAGES > 0) begin : gen_synchronizer
genvar i;
always @(posedge clk) begin
synch_d[0] <= synch_in;
end
for (i = 1; i < C_NUM_STAGES ; i = i + 1) begin : gen_stage
always @(posedge clk) begin
synch_d[i] <= synch_d[i-1];
end
end
assign synch_out = synch_d[C_NUM_STAGES-1];
end
else begin : gen_no_synchronizer
assign synch_out = synch_in;
end
endgenerate
endmodule
`default_nettype wire
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03.07.2016 12:23:24
// Design Name:
// Module Name: tb_top
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tb_top();
parameter DATA_W_IN_BYTES = 4;
parameter ADDR_W_IN_BITS = 10;
parameter DCADDR_LOW_BIT_W = 8;
parameter DCADDR_STROBE_MEM_SEG = 2;
parameter PERIOD = 1000;
// AXI interface control signals
reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_AWADDR; // Write channel Protection type. This signal indicates the // privilege and security level of the transaction; and whether // the transaction is a data access or an instruction access.
reg [2 : 0] S_AXI_AWPROT; // Write address valid. This signal indicates that the master signaling // valid write address and control information.
reg S_AXI_AWVALID; // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
wire S_AXI_AWREADY; // Write data (issued by master; acceped by Slave)
reg [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_WDATA; // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
reg [DATA_W_IN_BYTES-1 : 0] S_AXI_WSTRB; // Write valid. This signal indicates that valid write // data and strobes are available.
reg S_AXI_WVALID; // Write ready. This signal indicates that the slave // can accept the write data.
wire S_AXI_WREADY; // Write response. This signal indicates the status // of the write transaction.
wire [1 : 0] S_AXI_BRESP; // Write response valid. This signal indicates that the channel // is signaling a valid write response.
wire S_AXI_BVALID; // Response ready. This signal indicates that the master // can accept a write response.
reg S_AXI_BREADY; // Read address (issued by master; acceped by Slave)
reg [(ADDR_W_IN_BITS)-1 : 0] S_AXI_ARADDR; // Protection type. This signal indicates the privilege // and security level of the transaction; and whether the // transaction is a data access or an instruction access.
reg [2 : 0] S_AXI_ARPROT; // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
reg S_AXI_ARVALID; // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
wire S_AXI_ARREADY; // Read data (issued by slave)
wire [(DATA_W_IN_BYTES*8) - 1:0] S_AXI_RDATA; // Read response. This signal indicates the status of the // read transfer.
reg [(DATA_W_IN_BYTES*8) - 1:0] read_data; //
wire [1 : 0] S_AXI_RRESP; // Read valid. This signal indicates that the channel is signaling the required read data.
wire S_AXI_RVALID; // Read ready. This signal indicates that the master can accept the read data and response information.
reg S_AXI_RREADY; //
// Bank IP R/W control strobes
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_start; // read start strobe
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_rd_done; // read done strobe
// wire [DCADDR_LOW_BIT_W - 1:0] bank_rd_addr; // read address bus
// reg [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data=0; // read data bus
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_start; // write start strobe
// wire [DCADDR_STROBE_MEM_SEG - 1:0] bank_wr_done; // write done strobe
// wire [DCADDR_LOW_BIT_W - 1:0] bank_wr_addr; // write address bus
// wire [(DATA_W_IN_BYTES*8) - 1:0] bank_wr_data; // write data bus
// Clock & reset for registers
reg ACLK; // Clock source
reg ARESETn; // Reset source
// wire [(DATA_W_IN_BYTES*8) - 1:0] bank_rd_data_bus[DCADDR_STROBE_MEM_SEG-1:0]; // read data bus
// wire [(ADDR_W_IN_BITS)-1:DCADDR_LOW_BIT_W] decode_rd_addr; // used external to the block to select the correct returning data
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
pc_ctrl #(
.DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
.ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
.DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W ),
.DCADDR_STROBE_MEM_SEG (DCADDR_STROBE_MEM_SEG )
) jjreg_top_ctrl_i (
.S_AXI_AWADDR (S_AXI_AWADDR ), // Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether // the transaction is a data access or an instruction access.
.S_AXI_AWPROT (S_AXI_AWPROT ), // Write address valid. This signal indicates that the master signaling // valid write address and control information.
.S_AXI_AWVALID (S_AXI_AWVALID ), // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
.S_AXI_AWREADY (S_AXI_AWREADY ), // Write data (issued by master, acceped by Slave)
.S_AXI_WDATA (S_AXI_WDATA ), // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
.S_AXI_WSTRB (S_AXI_WSTRB ), // Write valid. This signal indicates that valid write // data and strobes are available.
.S_AXI_WVALID (S_AXI_WVALID ), // Write ready. This signal indicates that the slave // can accept the write data.
.S_AXI_WREADY (S_AXI_WREADY ), // Write response. This signal indicates the status // of the write transaction.
.S_AXI_BRESP (S_AXI_BRESP ), // Write response valid. This signal indicates that the channel // is signaling a valid write response.
.S_AXI_BVALID (S_AXI_BVALID ), // Response ready. This signal indicates that the master // can accept a write response.
.S_AXI_BREADY (S_AXI_BREADY ), // Read address (issued by master, acceped by Slave)
.S_AXI_ARADDR (S_AXI_ARADDR ), // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
.S_AXI_ARPROT (S_AXI_ARPROT ), // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
.S_AXI_ARVALID (S_AXI_ARVALID ), // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
.S_AXI_ARREADY (S_AXI_ARREADY ), // Read data (issued by slave)
.S_AXI_RDATA (S_AXI_RDATA ), // Read response. This signal indicates the status of the // read transfer.
.S_AXI_RRESP (S_AXI_RRESP ), // Read valid. This signal indicates that the channel is signaling the required read data.
.S_AXI_RVALID (S_AXI_RVALID ), // Read ready. This signal indicates that the master can accept the read data and response information.
.S_AXI_RREADY (S_AXI_RREADY ),
.ACLK (ACLK ), // Clock source
.ARESETn (ARESETn ) // Reset source
);
////------------------------------------------------------------------------------
////
////------------------------------------------------------------------------------
//jjreg_axi4lite_regif #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W ),
// .DCADDR_STROBE_MEM_SEG (DCADDR_STROBE_MEM_SEG )
//) jjreg_axi4lite_regif_i (
// .S_AXI_AWADDR (S_AXI_AWADDR ), // Write channel Protection type. This signal indicates the // privilege and security level of the transaction, and whether // the transaction is a data access or an instruction access.
// .S_AXI_AWPROT (S_AXI_AWPROT ), // Write address valid. This signal indicates that the master signaling // valid write address and control information.
// .S_AXI_AWVALID (S_AXI_AWVALID ), // Write address ready. This signal indicates that the slave is ready // to accept an address and associated control signals.
// .S_AXI_AWREADY (S_AXI_AWREADY ), // Write data (issued by master, acceped by Slave)
// .S_AXI_WDATA (S_AXI_WDATA ), // Write strobes. This signal indicates which byte lanes hold // valid data. There is one write strobe bit for each eight // bits of the write data bus.
// .S_AXI_WSTRB (S_AXI_WSTRB ), // Write valid. This signal indicates that valid write // data and strobes are available.
// .S_AXI_WVALID (S_AXI_WVALID ), // Write ready. This signal indicates that the slave // can accept the write data.
// .S_AXI_WREADY (S_AXI_WREADY ), // Write response. This signal indicates the status // of the write transaction.
// .S_AXI_BRESP (S_AXI_BRESP ), // Write response valid. This signal indicates that the channel // is signaling a valid write response.
// .S_AXI_BVALID (S_AXI_BVALID ), // Response ready. This signal indicates that the master // can accept a write response.
// .S_AXI_BREADY (S_AXI_BREADY ), // Read address (issued by master, acceped by Slave)
// .S_AXI_ARADDR (S_AXI_ARADDR ), // Protection type. This signal indicates the privilege // and security level of the transaction, and whether the // transaction is a data access or an instruction access.
// .S_AXI_ARPROT (S_AXI_ARPROT ), // Read address valid. This signal indicates that the channel // is signaling valid read address and control information.
// .S_AXI_ARVALID (S_AXI_ARVALID ), // Read address ready. This signal indicates that the slave is // ready to accept an address and associated control signals.
// .S_AXI_ARREADY (S_AXI_ARREADY ), // Read data (issued by slave)
// .S_AXI_RDATA (S_AXI_RDATA ), // Read response. This signal indicates the status of the // read transfer.
// .S_AXI_RRESP (S_AXI_RRESP ), // Read valid. This signal indicates that the channel is signaling the required read data.
// .S_AXI_RVALID (S_AXI_RVALID ), // Read ready. This signal indicates that the master can accept the read data and response information.
// .S_AXI_RREADY (S_AXI_RREADY ),
// .reg_bank_rd_start (bank_rd_start ), // read start strobe
// .reg_bank_rd_done (bank_rd_done ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data ), // read data bus
// .decode_rd_addr (decode_rd_addr),
// .reg_bank_wr_start (bank_wr_start ), // write start strobe
// .reg_bank_wr_done (bank_wr_done ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//always @(*) begin
// case(decode_rd_addr)
// 0:bank_rd_data = bank_rd_data_bus[0];
// 1:bank_rd_data = bank_rd_data_bus[1];
// 2:bank_rd_data = bank_rd_data_bus[2];
// default:bank_rd_data = bank_rd_data_bus[0];
// endcase
//end
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_0_i (
// .reg_bank_rd_start (bank_rd_start[0] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[0] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[0] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[0] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[0] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_1_i (
// .reg_bank_rd_start (bank_rd_start[1] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[1] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[1] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[1] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[1] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//jjreg_tmp_reg_basic #(
// .DATA_W_IN_BYTES (DATA_W_IN_BYTES ),
// .ADDR_W_IN_BITS (ADDR_W_IN_BITS ),
// .DCADDR_LOW_BIT_W (DCADDR_LOW_BIT_W )
//) jjreg_tmp_reg_basic_2_i (
// .reg_bank_rd_start (bank_rd_start[2] ), // read start strobe
// .reg_bank_rd_done (bank_rd_done[2] ), // read done strobe
// .reg_bank_rd_addr (bank_rd_addr ), // read address bus
// .reg_bank_rd_data (bank_rd_data_bus[2] ), // read data bus
// .reg_bank_wr_start (bank_wr_start[2] ), // write start strobe
// .reg_bank_wr_done (bank_wr_done[2] ), // write done strobe
// .reg_bank_wr_addr (bank_wr_addr ), // write address bus
// .reg_bank_wr_data (bank_wr_data ), // write data bus
// .ACLK (ACLK ), // Clock source
// .ARESETn (ARESETn ) // Reset source
//);
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
always begin
ACLK = 1'b0;
#(PERIOD/2) ACLK = 1'b1;
#(PERIOD/2);
end
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
initial begin
wait_aclk_cycles_for_to(200);
end
initial begin
ARESETn = 0;
initialise_axi_inputs();
wait_aclk_cycles(20);
ARESETn = 1;
wait_aclk_cycles(20);
// bank_rd_data = 44;
axi_read('h20,read_data);
axi_write('h20,33);
// bank_rd_data = 49;
axi_read('h20,read_data);
wait_aclk_cycles(20);
axi_write('h00_00,'h0);
axi_write('h00_00,'hff);
axi_write('h01_00,'h1);
axi_write('h02_00,'h2);
axi_read('h00_00,read_data);
axi_read('h01_00,read_data);
axi_read('h02_00,read_data);
axi_read('h04_00,read_data);
$stop;
end
task initialise_axi_inputs;
begin
S_AXI_AWADDR = 'd0;
S_AXI_AWPROT = 'd0;
S_AXI_AWVALID = 'd0;
S_AXI_WDATA = 'd0;
S_AXI_WSTRB = 'd0;
S_AXI_WVALID = 'd0;
S_AXI_BREADY = 'd0;
S_AXI_ARADDR = 'd0;
S_AXI_ARPROT = 'd0;
S_AXI_ARVALID = 'd0;
S_AXI_RREADY = 'd0;
end
endtask
//------------------------------------------------------------------------------
//
//------------------------------------------------------------------------------
task axi_read;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
output [(DATA_W_IN_BYTES*8) - 1:0] DATA;
begin
@(posedge ACLK);
S_AXI_ARADDR <= ADDR;
S_AXI_ARPROT <= 'd0;
S_AXI_ARVALID <= 'd1;
S_AXI_RREADY <= 'd1; // This can be high as xfer starts
@(posedge ACLK);
while( S_AXI_ARREADY == 'd0 )
@(posedge ACLK);
S_AXI_ARVALID <= 'd0;
while( S_AXI_RVALID == 'd0 )
@(posedge ACLK);
S_AXI_RREADY <= 'd0;
DATA <= S_AXI_RDATA;
// S_AXI_RRESP
end
endtask
task axi_write;
input [(ADDR_W_IN_BITS)-1 : 0] ADDR;
input [(DATA_W_IN_BYTES*8) - 1:0] DATA;
begin
@(posedge ACLK);
S_AXI_AWADDR <= ADDR;
S_AXI_AWPROT <= 'd0;
S_AXI_AWVALID <= 'd1;
S_AXI_WVALID <= 'd1;
S_AXI_WDATA <= DATA;
@(posedge ACLK);
while( (S_AXI_AWREADY & S_AXI_WREADY) == 'd0 )
@(posedge ACLK);
S_AXI_AWVALID <= 'd0;
S_AXI_WVALID <= 'd0;
S_AXI_BREADY <= 'd1;
while( S_AXI_BVALID == 'd0 )
@(posedge ACLK);
S_AXI_BREADY <= 'd0;
// @(posedge ACLK);
// S_AXI_BREADY <= 'd0;
end
endtask
task wait_aclk_cycles_for_to;
input [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
$display("---ERROR simulation timeout!");
$stop;
end
endtask
task wait_aclk_cycles;
input [31 : 0] cycles;
begin
while( cycles > 'd0 ) begin
@(posedge ACLK);
cycles = cycles - 'd1;
end
end
endtask
endmodule
|
module sub(output logic [1:-1] oned,
output logic [1:-1] [2:-1] twod,
output logic [1:-1] [2:-1] [3:-3] threed);
endmodule
module dut (
);
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
logic [1:-1] b_oned; // From subb of sub.v
logic [3:-3] b_threed; // From subb of sub.v
logic [2:-1] b_twod; // From subb of sub.v
logic [1:-1] c_oned; // From subc of sub.v
logic [x][y] [3:-3] c_threed; // From subc of sub.v
logic [x] [2:-1] c_twod; // From subc of sub.v
logic [1:-1] d_oned; // From subd of sub.v
logic [1:-1][2:-1] [3:-3] d_threed; // From subd of sub.v
logic [1:-1] [2:-1] d_twod; // From subd of sub.v
logic [1:-1] oned; // From sub1 of sub.v
logic [1:-1][2:-1] [3:-3] threed; // From sub1 of sub.v
logic [1:-1] [2:-1] twod; // From sub1 of sub.v
// End of automatics
/* sub AUTO_TEMPLATE ();
*/
sub sub1 (/*AUTOINST*/
// Outputs
.oned (oned[1:-1]),
.twod (twod/*[1:-1][2:-1]*/),
.threed (threed/*[1:-1][2:-1][3:-3]*/));
/* sub AUTO_TEMPLATE (
.oned (b_oned[]),
.twod (b_twod[]),
.threed (b_threed[]));
*/
// NOTE this results in the wrong declaration for b_twod/b_threed
sub subb (/*AUTOINST*/
// Outputs
.oned (b_oned[1:-1]), // Templated
.twod (b_twod[2:-1]), // Templated
.threed (b_threed[3:-3])); // Templated
/* sub AUTO_TEMPLATE (
.oned (c_oned[]),
.twod (c_twod[x][]),
.threed (c_threed[x][y][]));
*/
sub subc (/*AUTOINST*/
// Outputs
.oned (c_oned[1:-1]), // Templated
.twod (c_twod[x][2:-1]), // Templated
.threed (c_threed[x][y][3:-3])); // Templated
/* sub AUTO_TEMPLATE (
.oned (d_oned[][]),
.twod (d_twod[][]),
.threed (d_threed[][]));
*/
sub subd (/*AUTOINST*/
// Outputs
.oned (d_oned[1:-1]), // Templated
.twod (d_twod/*[1:-1][2:-1]*/), // Templated
.threed (d_threed/*[1:-1][2:-1][3:-3]*/)); // Templated
endmodule
|
`define CLOG2(x) \
(x <= 2) ? 1 : \
(x <= 4) ? 2 : \
(x <= 8) ? 3 : \
(x <= 16) ? 4 : \
(x <= 32) ? 5 : \
(x <= 64) ? 6 : \
(x <= 128) ? 7 : \
(x <= 256) ? 8 : \
-1
module sync_fifo #(
parameter DEPTH = 3,
parameter DATA_W = 32,
parameter ASSERT_OVERFLOW = 1,
parameter ASSERT_UNDERFLOW = 1,
parameter ENABLE_BYPASS = 0
)
(
input clk,
input rstn,
input [DATA_W-1:0] fifo_data_in,
input fifo_push,
output [DATA_W-1:0] fifo_data_out,
input fifo_pop,
output fifo_full,
output fifo_empty,
input fifo_flush
);
localparam DEPTH_LOG2 = `CLOG2(DEPTH);
reg [DATA_W-1:0] mem [0:DEPTH-1];
reg [DEPTH_LOG2-1:0] head, n_head;
reg [DEPTH_LOG2-1:0] tail, n_tail;
wire empty;
wire full;
reg push_last;
assign fifo_data_out = mem[tail];
assign fifo_full = full;
assign fifo_empty = empty;
always @ (*) begin
if (head < DEPTH-1) begin
n_head = head + 'h1;
end
else begin
n_head = 'h0;
end
end
always @ (*) begin
if (tail < DEPTH-1) begin
n_tail = tail + 'h1;
end
else begin
n_tail = 'h0;
end
end
generate
if (ENABLE_BYPASS) begin
assign full = (push_last && (head == tail) && !fifo_pop) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail) && !fifo_push) ? 1'b1 : 1'b0;
end
else begin
assign full = (push_last && (head == tail)) ? 1'b1 : 1'b0;
assign empty = (!push_last && (head == tail)) ? 1'b1 : 1'b0;
end
endgenerate
generate
if (ASSERT_OVERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_push && full) begin
$display("ERROR: FIFO OVERFLOW");
$finish;
end
end
end
if (ASSERT_UNDERFLOW) begin
always @ (posedge clk) begin
if (clk && !fifo_flush && fifo_pop && empty) begin
$display("ERROR: FIFO UNDERFLOW");
$finish;
end
end
end
endgenerate
always @ (posedge clk, negedge rstn) begin
if (~rstn) begin
head <= 'h0;
tail <= 'h0;
push_last <= 'h0;
end
else begin
if (fifo_flush) begin
tail <= 'h0;
head <= 'h0;
push_last <= 'h0;
end
else if (!((full && fifo_push) || (empty && fifo_pop))) begin
if (fifo_push) begin
mem[head] <= fifo_data_in;
head <= n_head;
end
if (fifo_pop) begin
tail <= n_tail;
end
if (fifo_push && !fifo_pop) begin
push_last = 'h1;
end
else if (!fifo_push && fifo_pop) begin
push_last = 'h0;
end
end
end
end
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V
`define SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V
/**
* a2bb2o: 2-input AND, both inputs inverted, into first input, and
* 2-input AND into 2nd input of 2-input OR.
*
* X = ((!A1 & !A2) | (B1 & B2))
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ms__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ms__a2bb2o (
X ,
A1_N,
A2_N,
B1 ,
B2 ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output X ;
input A1_N;
input A2_N;
input B1 ;
input B2 ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire and0_out ;
wire nor0_out ;
wire or0_out_X ;
wire pwrgood_pp0_out_X;
// Name Output Other arguments
and and0 (and0_out , B1, B2 );
nor nor0 (nor0_out , A1_N, A2_N );
or or0 (or0_out_X , nor0_out, and0_out );
sky130_fd_sc_ms__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_X, or0_out_X, VPWR, VGND);
buf buf0 (X , pwrgood_pp0_out_X );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__A2BB2O_BEHAVIORAL_PP_V |
//*****************************************************************************
// (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: phy_read.v
// /___/ /\ Date Last Modified: $Date: 2010/02/26 08:58:34 $
// \ \ / \ Date Created: Aug 03 2009
// \___\/\___\
//
//Device: Virtex-6
//Design Name: DDR3 SDRAM
//Purpose:
// Top-level module for PHY-layer read logic
// 1. Read clock (capture, resync) generation
// 2. Synchronization of control from MC into resync clock domain
// 3. Synchronization of data/valid into MC clock domain
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: phy_read.v,v 1.3 2010/02/26 08:58:34 pboya Exp $
**$Date: 2010/02/26 08:58:34 $
**$Author: pboya $
**$Revision: 1.3 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/M/mig_v3_4/data/dlib/virtex6/ddr3_sdram/verilog/rtl/phy/phy_read.v,v $
******************************************************************************/
`timescale 1ps/1ps
module phy_read #
(
parameter TCQ = 100, // clk->out delay (sim only)
parameter nCK_PER_CLK = 2, // # of memory clocks per CLK
parameter CLK_PERIOD = 3333, // Internal clock period (in ps)
parameter REFCLK_FREQ = 300.0, // IODELAY Reference Clock freq (MHz)
parameter DQS_WIDTH = 8, // # of DQS (strobe)
parameter DQ_WIDTH = 64, // # of DQ (data)
parameter DRAM_WIDTH = 8, // # of DQ per DQS
parameter IODELAY_GRP = "IODELAY_MIG", // May be assigned unique name
// when mult IP cores in design
parameter nDQS_COL0 = 4, // # DQS groups in I/O column #1
parameter nDQS_COL1 = 4, // # DQS groups in I/O column #2
parameter nDQS_COL2 = 0, // # DQS groups in I/O column #3
parameter nDQS_COL3 = 0, // # DQS groups in I/O column #4
parameter DQS_LOC_COL0 = 32'h03020100, // DQS grps in col #1
parameter DQS_LOC_COL1 = 32'h07060504, // DQS grps in col #2
parameter DQS_LOC_COL2 = 0, // DQS grps in col #3
parameter DQS_LOC_COL3 = 0 // DQS grps in col #4
)
(
input clk_mem,
input clk,
input clk_rd_base,
input rst,
// Read clock generation/distribution signals
input dlyrst_cpt,
input [DQS_WIDTH-1:0] dlyce_cpt,
input [DQS_WIDTH-1:0] dlyinc_cpt,
input dlyrst_rsync,
input [3:0] dlyce_rsync,
input [3:0] dlyinc_rsync,
output [DQS_WIDTH-1:0] clk_cpt,
output [3:0] clk_rsync,
output [3:0] rst_rsync,
output rdpath_rdy,
// Control for command sync logic
input mc_data_sel,
input [4:0] rd_active_dly,
// Captured data in resync clock domain
input [DQ_WIDTH-1:0] rd_data_rise0,
input [DQ_WIDTH-1:0] rd_data_fall0,
input [DQ_WIDTH-1:0] rd_data_rise1,
input [DQ_WIDTH-1:0] rd_data_fall1,
input [DQS_WIDTH-1:0] rd_dqs_rise0,
input [DQS_WIDTH-1:0] rd_dqs_fall0,
input [DQS_WIDTH-1:0] rd_dqs_rise1,
input [DQS_WIDTH-1:0] rd_dqs_fall1,
// DFI signals from MC/PHY rdlvl logic
input dfi_rddata_en,
input phy_rddata_en,
// Synchronized data/valid back to MC/PHY rdlvl logic
output dfi_rddata_valid,
output dfi_rddata_valid_phy,
output [4*DQ_WIDTH-1:0] dfi_rddata,
output [4*DQS_WIDTH-1:0] dfi_rd_dqs,
// Debug bus
output [5*DQS_WIDTH-1:0] dbg_cpt_tap_cnt, // CPT IODELAY tap count
output [19:0] dbg_rsync_tap_cnt, // RSYNC IODELAY tap count
output [255:0] dbg_phy_read //general purpose debug
);
//***************************************************************************
// Assign signals for Debug Port
//***************************************************************************
// Currently no assignments - add as needed
assign dbg_phy_read = 'b0;
//***************************************************************************
// Read clocks (capture, resynchronization) generation
//***************************************************************************
phy_rdclk_gen #
(
.TCQ (TCQ),
.nCK_PER_CLK (nCK_PER_CLK),
.CLK_PERIOD (CLK_PERIOD),
.DQS_WIDTH (DQS_WIDTH),
.REFCLK_FREQ (REFCLK_FREQ),
.IODELAY_GRP (IODELAY_GRP),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3)
)
u_phy_rdclk_gen
(
.clk_mem (clk_mem),
.clk (clk),
.clk_rd_base (clk_rd_base),
.rst (rst),
.dlyrst_cpt (dlyrst_cpt),
.dlyce_cpt (dlyce_cpt),
.dlyinc_cpt (dlyinc_cpt),
.dlyrst_rsync (dlyrst_rsync),
.dlyce_rsync (dlyce_rsync),
.dlyinc_rsync (dlyinc_rsync),
.clk_cpt (clk_cpt),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.dbg_cpt_tap_cnt (dbg_cpt_tap_cnt),
.dbg_rsync_tap_cnt (dbg_rsync_tap_cnt)
);
//***************************************************************************
// Synchronization of read enable signal from MC/PHY rdlvl logic
//***************************************************************************
phy_rdctrl_sync #
(
.TCQ (TCQ)
)
u_phy_rdctrl_sync
(
.clk (clk),
.rst_rsync (rst_rsync[0]),
.mc_data_sel (mc_data_sel),
.rd_active_dly (rd_active_dly),
.dfi_rddata_en (dfi_rddata_en),
.phy_rddata_en (phy_rddata_en),
.dfi_rddata_valid (dfi_rddata_valid),
.dfi_rddata_valid_phy (dfi_rddata_valid_phy),
.rdpath_rdy (rdpath_rdy)
);
//***************************************************************************
// Synchronization of read data and accompanying valid signal back to MC/
// PHY rdlvl logic
//***************************************************************************
phy_rddata_sync #
(
.TCQ (TCQ),
.DQ_WIDTH (DQ_WIDTH),
.DQS_WIDTH (DQS_WIDTH),
.DRAM_WIDTH (DRAM_WIDTH),
.nDQS_COL0 (nDQS_COL0),
.nDQS_COL1 (nDQS_COL1),
.nDQS_COL2 (nDQS_COL2),
.nDQS_COL3 (nDQS_COL3),
.DQS_LOC_COL0 (DQS_LOC_COL0),
.DQS_LOC_COL1 (DQS_LOC_COL1),
.DQS_LOC_COL2 (DQS_LOC_COL2),
.DQS_LOC_COL3 (DQS_LOC_COL3)
)
u_phy_rddata_sync
(
.clk (clk),
.clk_rsync (clk_rsync),
.rst_rsync (rst_rsync),
.rd_data_rise0 (rd_data_rise0),
.rd_data_fall0 (rd_data_fall0),
.rd_data_rise1 (rd_data_rise1),
.rd_data_fall1 (rd_data_fall1),
.rd_dqs_rise0 (rd_dqs_rise0),
.rd_dqs_fall0 (rd_dqs_fall0),
.rd_dqs_rise1 (rd_dqs_rise1),
.rd_dqs_fall1 (rd_dqs_fall1),
.dfi_rddata (dfi_rddata),
.dfi_rd_dqs (dfi_rd_dqs)
);
endmodule
|
//Autogenerated on 2015-11-03 15:35:14.418243
`timescale 1 ns / 1 ps
module step_curve_new
(
input clk,
input [15:0]stage_PIPELINE_SHIFT_IN_cntr,
output reg CAL,
output CS,
output IS1,
output IS2,
output reg LE,
output reg R12,
output reg RBI,
output reg RESET,
output reg RPHI1,
output reg RPHI2,
output reg SBI,
output reg SEB,
output reg SPHI1,
output reg SPHI2,
output SR,
output [15:0]Aref,
output [15:0]RG,
output [15:0]Vana,
output [15:0]Vthr,
input reset_gen
);
reg [31:0]counter;
reg [7:0]stage;
reg [15:0]stage_iter;
reg ISSR;
assign IS1=ISSR;
assign IS2=ISSR;
assign SR=ISSR;
assign CS=0;
assign Vthr=16'H0025;
assign Aref=16'H0033;
assign Vana=16'H0066;
assign RG=16'H0033;
always @(posedge clk) begin
if(reset_gen == 1) begin
counter <= 0;
stage <= 0;
stage_iter <= 0;
end
else begin
if(stage == 0) begin
if(counter == 0) begin
CAL <= 1;
SBI <= 1;
SPHI1 <= 1;
SPHI2 <= 1;
SEB <= 0;
ISSR <= 0;
RESET <= 1;
R12 <= 0;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 9) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 1) begin
if(counter == 0) begin
CAL <= 1;
SBI <= 0;
SPHI1 <= 1;
SPHI2 <= 1;
SEB <= 1;
ISSR <= 1;
RESET <= 1;
R12 <= 1;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 2) begin
SPHI1 <= 0;
SPHI2 <= 0;
end
if(counter == 8) begin
SEB <= 0;
end
if(counter == 16) begin
RESET <= 0;
end
if(counter == 23) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 2) begin
if(counter == 0) begin
CAL <= 1;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 0;
ISSR <= 1;
RESET <= 0;
R12 <= 1;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 1) begin
SBI <= 1;
SPHI1 <= 1;
end
if(counter == 2) begin
SPHI1 <= 0;
end
if(counter == 3) begin
SBI <= 0;
SPHI2 <= 1;
end
if(counter == 4) begin
SPHI2 <= 0;
end
if(counter == 5) begin
SPHI1 <= 1;
end
if(counter == 6) begin
SPHI1 <= 0;
end
if(counter == 7) begin
SPHI2 <= 1;
end
if(counter == 8) begin
SPHI2 <= 0;
end
if(counter == 9) begin
SPHI1 <= 1;
end
if(counter == 10) begin
SPHI1 <= 0;
end
if(counter == 11) begin
SPHI2 <= 1;
end
if(counter == 12) begin
SPHI2 <= 0;
end
if(counter == 13) begin
SPHI1 <= 1;
end
if(counter == 14) begin
SPHI1 <= 0;
end
if(counter == 15) begin
SPHI2 <= 1;
end
if(counter == 16) begin
SPHI2 <= 0;
end
if(counter == 17) begin
SPHI1 <= 1;
end
if(counter == 18) begin
SPHI1 <= 0;
end
if(counter == 19) begin
SPHI2 <= 1;
end
if(counter == 20) begin
SPHI2 <= 0;
end
if(counter == 21) begin
SPHI1 <= 1;
end
if(counter == 22) begin
SPHI1 <= 0;
end
if(counter == 23) begin
SPHI2 <= 1;
end
if(counter == 24) begin
SPHI2 <= 0;
end
if(counter == 25) begin
SPHI1 <= 1;
end
if(counter == 26) begin
SPHI1 <= 0;
end
if(counter == 27) begin
SPHI2 <= 1;
end
if(counter == 28) begin
SPHI2 <= 0;
end
if(counter == 29) begin
CAL <= 0;
SPHI1 <= 1;
end
if(counter == 30) begin
SPHI1 <= 0;
end
if(counter == 31) begin
SPHI2 <= 1;
end
if(counter == 32) begin
SPHI2 <= 0;
end
if(counter == 33) begin
SPHI1 <= 1;
end
if(counter == 34) begin
SPHI1 <= 0;
end
if(counter == 35) begin
SPHI2 <= 1;
end
if(counter == 36) begin
SPHI2 <= 0;
end
if(counter == 37) begin
SPHI1 <= 1;
end
if(counter == 38) begin
SPHI1 <= 0;
end
if(counter == 39) begin
SPHI2 <= 1;
end
if(counter == 40) begin
SPHI2 <= 0;
end
if(counter == 41) begin
SPHI1 <= 1;
end
if(counter == 42) begin
SPHI1 <= 0;
end
if(counter == 43) begin
SPHI2 <= 1;
end
if(counter == 44) begin
SPHI2 <= 0;
end
if(counter == 45) begin
SPHI1 <= 1;
end
if(counter == 46) begin
SPHI1 <= 0;
end
if(counter == 47) begin
SPHI2 <= 1;
end
if(counter == 48) begin
SPHI2 <= 0;
end
if(counter == 49) begin
SPHI1 <= 1;
end
if(counter == 50) begin
SPHI1 <= 0;
end
if(counter == 51) begin
SPHI2 <= 1;
end
if(counter == 52) begin
SPHI2 <= 0;
end
if(counter == 53) begin
SPHI1 <= 1;
end
if(counter == 54) begin
SPHI1 <= 0;
end
if(counter == 55) begin
SPHI2 <= 1;
end
if(counter == 56) begin
SPHI2 <= 0;
end
if(counter == 57) begin
SPHI1 <= 1;
end
if(counter == 58) begin
SPHI1 <= 0;
end
if(counter == 59) begin
SPHI2 <= 1;
end
if(counter == 60) begin
SPHI2 <= 0;
end
if(counter == 61) begin
SPHI1 <= 1;
end
if(counter == 62) begin
SPHI1 <= 0;
end
if(counter == 63) begin
SPHI2 <= 1;
end
if(counter == 64) begin
SPHI2 <= 0;
end
if(counter == 64) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 3) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 0;
ISSR <= 1;
RESET <= 0;
R12 <= 1;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 1) begin
RESET <= 1;
end
if(counter == 3) begin
SEB <= 1;
end
if(counter == 4) begin
ISSR <= 0;
end
if(counter == 5) begin
R12 <= 0;
end
if(counter == 13) begin
SPHI1 <= 1;
SPHI2 <= 1;
end
if(counter == 17) begin
SPHI1 <= 0;
SPHI2 <= 0;
end
if(counter == 24) begin
SBI <= 1;
SPHI1 <= 1;
end
if(counter == 25) begin
SPHI1 <= 0;
end
if(counter == 26) begin
SPHI2 <= 1;
end
if(counter == 27) begin
SBI <= 0;
SPHI2 <= 0;
end
if(counter == 27) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 4) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 1;
SPHI2 <= 0;
SEB <= 1;
ISSR <= 0;
RESET <= 1;
R12 <= 0;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 1) begin
SPHI1 <= 0;
end
if(counter == 2) begin
SPHI2 <= 1;
end
if(counter == 3) begin
SPHI2 <= 0;
end
if(counter == 3) begin
if(stage_iter == stage_PIPELINE_SHIFT_IN_cntr-1) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 5) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
ISSR <= 0;
RESET <= 1;
R12 <= 0;
RBI <= 1;
RPHI1 <= 1;
RPHI2 <= 1;
LE <= 1;
end
if(counter == 2) begin
LE <= 0;
end
if(counter == 6) begin
RESET <= 0;
end
if(counter == 21) begin
SEB <= 0;
end
if(counter == 29) begin
SEB <= 1;
end
if(counter == 34) begin
RBI <= 0;
end
if(counter == 37) begin
RPHI1 <= 0;
RPHI2 <= 0;
end
if(counter == 38) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 6) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
ISSR <= 0;
RESET <= 0;
R12 <= 0;
RBI <= 0;
RPHI1 <= 0;
RPHI2 <= 0;
LE <= 0;
end
if(counter == 2) begin
RBI <= 1;
RPHI1 <= 1;
end
if(counter == 4) begin
RPHI1 <= 0;
end
if(counter == 5) begin
RBI <= 0;
end
if(counter == 8) begin
LE <= 1;
end
if(counter == 11) begin
if(stage_iter == 0) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
if(stage == 7) begin
if(counter == 0) begin
CAL <= 0;
SBI <= 0;
SPHI1 <= 0;
SPHI2 <= 0;
SEB <= 1;
ISSR <= 0;
RESET <= 0;
R12 <= 0;
RBI <= 0;
RPHI1 <= 0;
RPHI2 <= 0;
LE <= 1;
end
if(counter == 1) begin
RPHI2 <= 1;
end
if(counter == 21) begin
RPHI2 <= 0;
end
if(counter == 22) begin
RPHI1 <= 1;
end
if(counter == 22) begin
if(stage_iter == 134) begin
stage <= (stage + 1) % 8;
stage_iter <= 0;
end
else begin
stage_iter <= stage_iter + 1;
end
counter <= 0;
end
else begin
counter <= counter + 1;
end
end
end
end
endmodule |
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 24080 $
// $Date: 2011-05-18 19:32:52 +0000 (Wed, 18 May 2011) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
// Dual-Ported BRAM (READ FIRST)
module BRAM2(CLKA,
ENA,
WEA,
ADDRA,
DIA,
DOA,
CLKB,
ENB,
WEB,
ADDRB,
DIB,
DOB
);
parameter PIPELINED = 0;
parameter ADDR_WIDTH = 1;
parameter DATA_WIDTH = 1;
parameter MEMSIZE = 1;
input CLKA;
input ENA;
input WEA;
input [ADDR_WIDTH-1:0] ADDRA;
input [DATA_WIDTH-1:0] DIA;
output [DATA_WIDTH-1:0] DOA;
input CLKB;
input ENB;
input WEB;
input [ADDR_WIDTH-1:0] ADDRB;
input [DATA_WIDTH-1:0] DIB;
output [DATA_WIDTH-1:0] DOB;
reg [DATA_WIDTH-1:0] RAM[0:MEMSIZE-1] /* synthesis syn_ramstyle="no_rw_check" */ ;
reg [DATA_WIDTH-1:0] DOA_R;
reg [DATA_WIDTH-1:0] DOB_R;
reg [DATA_WIDTH-1:0] DOA_D1_R;
reg [DATA_WIDTH-1:0] DOB_D1_R;
`ifdef BSV_NO_INITIAL_BLOCKS
`else
// synopsys translate_off
integer i;
initial
begin : init_block
for (i = 0; i < MEMSIZE; i = i + 1) begin
RAM[i] = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
DOA_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOA_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
DOB_D1_R = { ((DATA_WIDTH+1)/2) { 2'b10 } };
end
// synopsys translate_on
`endif // !`ifdef BSV_NO_INITIAL_BLOCKS
always @(posedge CLKA) begin
DOA_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRA];
if (ENA) begin
if (WEA) begin
RAM[ADDRA] <= `BSV_ASSIGNMENT_DELAY DIA;
end
end
end
always @(posedge CLKB) begin
DOB_R <= `BSV_ASSIGNMENT_DELAY RAM[ADDRB];
if (ENB) begin
if (WEB) begin
RAM[ADDRB] <= `BSV_ASSIGNMENT_DELAY DIB;
end
end
end
// Pipeline
always @(posedge CLKA)
DOA_D1_R <= DOA_R;
always @(posedge CLKB)
DOB_D1_R <= DOB_R;
// Output drivers
assign DOA = (PIPELINED) ? DOA_D1_R : DOA_R;
assign DOB = (PIPELINED) ? DOB_D1_R : DOB_R;
endmodule // BRAM2
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file rd_fifo_256to64.v when simulating
// the core, rd_fifo_256to64. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module rd_fifo_256to64(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
rd_data_count,
wr_data_count,
prog_full
);
input rst;
input wr_clk;
input rd_clk;
input [255 : 0] din;
input wr_en;
input rd_en;
output [63 : 0] dout;
output full;
output empty;
output [11 : 0] rd_data_count;
output [9 : 0] wr_data_count;
output prog_full;
// synthesis translate_off
FIFO_GENERATOR_V9_3 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(256),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(64),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("kintex7"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(1),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(0),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(1),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(0),
.C_PROG_EMPTY_TYPE_RACH(0),
.C_PROG_EMPTY_TYPE_RDCH(0),
.C_PROG_EMPTY_TYPE_WACH(0),
.C_PROG_EMPTY_TYPE_WDCH(0),
.C_PROG_EMPTY_TYPE_WRCH(0),
.C_PROG_FULL_THRESH_ASSERT_VAL(500),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(499),
.C_PROG_FULL_TYPE(1),
.C_PROG_FULL_TYPE_AXIS(0),
.C_PROG_FULL_TYPE_RACH(0),
.C_PROG_FULL_TYPE_RDCH(0),
.C_PROG_FULL_TYPE_WACH(0),
.C_PROG_FULL_TYPE_WDCH(0),
.C_PROG_FULL_TYPE_WRCH(0),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(12),
.C_RD_DEPTH(4096),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(12),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.RD_DATA_COUNT(rd_data_count),
.WR_DATA_COUNT(wr_data_count),
.PROG_FULL(prog_full),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.VALID(),
.UNDERFLOW(),
.DATA_COUNT(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_AW_PROG_FULL(),
.AXI_AW_PROG_EMPTY(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_W_PROG_FULL(),
.AXI_W_PROG_EMPTY(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_B_PROG_FULL(),
.AXI_B_PROG_EMPTY(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_AR_PROG_FULL(),
.AXI_AR_PROG_EMPTY(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXI_R_PROG_FULL(),
.AXI_R_PROG_EMPTY(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW(),
.AXIS_PROG_FULL(),
.AXIS_PROG_EMPTY()
);
// synthesis translate_on
endmodule
|
// Copyright (c) 2000-2009 Bluespec, Inc.
// Permission is hereby granted, free of charge, to any person obtaining a copy
// of this software and associated documentation files (the "Software"), to deal
// in the Software without restriction, including without limitation the rights
// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
// copies of the Software, and to permit persons to whom the Software is
// furnished to do so, subject to the following conditions:
// The above copyright notice and this permission notice shall be included in
// all copies or substantial portions of the Software.
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
// THE SOFTWARE.
//
// $Revision: 17872 $
// $Date: 2009-09-18 14:32:56 +0000 (Fri, 18 Sep 2009) $
`ifdef BSV_ASSIGNMENT_DELAY
`else
`define BSV_ASSIGNMENT_DELAY
`endif
module ResetInverter(RESET_IN, RESET_OUT);
input RESET_IN; // input reset
output RESET_OUT; // output reset
wire RESET_OUT;
assign RESET_OUT = ! RESET_IN ;
endmodule // ResetInverter
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_shr(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall,
i_datab, i_datab_valid, o_datab_stall,
o_dataout, i_dataout_stall, o_dataout_valid);
parameter DATA_WIDTH = 32;
parameter CONFIG_WIDTH= 5;
parameter FIFO_DEPTH = 64;
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [CONFIG_WIDTH-1:0] i_datab;
input i_dataa_valid, i_datab_valid;
output o_dataa_stall, o_datab_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_dataout_stall;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_stalled;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( is_fifo_a_valid ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( is_fifo_b_valid ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = CONFIG_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & ~i_dataout_stall);
assign o_dataout = dataa >> datab;
assign o_dataout_valid = is_fifo_a_valid & is_fifo_b_valid;
endmodule
|
// (C) 2001-2013 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// $Id: //acds/rel/12.1sp1/ip/merlin/altera_reset_controller/altera_reset_synchronizer.v#1 $
// $Revision: #1 $
// $Date: 2012/10/10 $
// $Author: swbranch $
// -----------------------------------------------
// Reset Synchronizer
// -----------------------------------------------
`timescale 1 ns / 1 ns
module altera_reset_synchronizer
#(
parameter ASYNC_RESET = 1,
parameter DEPTH = 2
)
(
input reset_in /* synthesis ALTERA_ATTRIBUTE = "SUPPRESS_DA_RULE_INTERNAL=R101" */,
input clk,
output reset_out
);
// -----------------------------------------------
// Synchronizer register chain. We cannot reuse the
// standard synchronizer in this implementation
// because our timing constraints are different.
//
// Instead of cutting the timing path to the d-input
// on the first flop we need to cut the aclr input.
//
// We omit the "preserve" attribute on the final
// output register, so that the synthesis tool can
// duplicate it where needed.
// -----------------------------------------------
(*preserve*) reg [DEPTH-1:0] altera_reset_synchronizer_int_chain;
reg altera_reset_synchronizer_int_chain_out;
generate if (ASYNC_RESET) begin
// -----------------------------------------------
// Assert asynchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk or posedge reset_in) begin
if (reset_in) begin
altera_reset_synchronizer_int_chain <= {DEPTH{1'b1}};
altera_reset_synchronizer_int_chain_out <= 1'b1;
end
else begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= 0;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end else begin
// -----------------------------------------------
// Assert synchronously, deassert synchronously.
// -----------------------------------------------
always @(posedge clk) begin
altera_reset_synchronizer_int_chain[DEPTH-2:0] <= altera_reset_synchronizer_int_chain[DEPTH-1:1];
altera_reset_synchronizer_int_chain[DEPTH-1] <= reset_in;
altera_reset_synchronizer_int_chain_out <= altera_reset_synchronizer_int_chain[0];
end
assign reset_out = altera_reset_synchronizer_int_chain_out;
end
endgenerate
endmodule
|
// (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
// DO NOT MODIFY THIS FILE.
// IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
// IP Revision: 5
`timescale 1ns/1ps
(* DowngradeIPIdentifiedWarnings = "yes" *)
module bram_4096 (
clka,
ena,
wea,
addra,
dina,
douta
);
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK" *)
input wire clka;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA EN" *)
input wire ena;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA WE" *)
input wire [0 : 0] wea;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR" *)
input wire [11 : 0] addra;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN" *)
input wire [19 : 0] dina;
(* X_INTERFACE_INFO = "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT" *)
output wire [19 : 0] douta;
blk_mem_gen_v8_3_5 #(
.C_FAMILY("zynq"),
.C_XDEVICEFAMILY("zynq"),
.C_ELABORATION_DIR("./"),
.C_INTERFACE_TYPE(0),
.C_AXI_TYPE(1),
.C_AXI_SLAVE_TYPE(0),
.C_USE_BRAM_BLOCK(0),
.C_ENABLE_32BIT_ADDRESS(0),
.C_CTRL_ECC_ALGO("NONE"),
.C_HAS_AXI_ID(0),
.C_AXI_ID_WIDTH(4),
.C_MEM_TYPE(0),
.C_BYTE_SIZE(9),
.C_ALGORITHM(1),
.C_PRIM_TYPE(1),
.C_LOAD_INIT_FILE(1),
.C_INIT_FILE_NAME("bram_4096.mif"),
.C_INIT_FILE("bram_4096.mem"),
.C_USE_DEFAULT_DATA(0),
.C_DEFAULT_DATA("0"),
.C_HAS_RSTA(0),
.C_RST_PRIORITY_A("CE"),
.C_RSTRAM_A(0),
.C_INITA_VAL("0"),
.C_HAS_ENA(1),
.C_HAS_REGCEA(0),
.C_USE_BYTE_WEA(0),
.C_WEA_WIDTH(1),
.C_WRITE_MODE_A("WRITE_FIRST"),
.C_WRITE_WIDTH_A(20),
.C_READ_WIDTH_A(20),
.C_WRITE_DEPTH_A(4096),
.C_READ_DEPTH_A(4096),
.C_ADDRA_WIDTH(12),
.C_HAS_RSTB(0),
.C_RST_PRIORITY_B("CE"),
.C_RSTRAM_B(0),
.C_INITB_VAL("0"),
.C_HAS_ENB(0),
.C_HAS_REGCEB(0),
.C_USE_BYTE_WEB(0),
.C_WEB_WIDTH(1),
.C_WRITE_MODE_B("WRITE_FIRST"),
.C_WRITE_WIDTH_B(20),
.C_READ_WIDTH_B(20),
.C_WRITE_DEPTH_B(4096),
.C_READ_DEPTH_B(4096),
.C_ADDRB_WIDTH(12),
.C_HAS_MEM_OUTPUT_REGS_A(1),
.C_HAS_MEM_OUTPUT_REGS_B(0),
.C_HAS_MUX_OUTPUT_REGS_A(0),
.C_HAS_MUX_OUTPUT_REGS_B(0),
.C_MUX_PIPELINE_STAGES(0),
.C_HAS_SOFTECC_INPUT_REGS_A(0),
.C_HAS_SOFTECC_OUTPUT_REGS_B(0),
.C_USE_SOFTECC(0),
.C_USE_ECC(0),
.C_EN_ECC_PIPE(0),
.C_HAS_INJECTERR(0),
.C_SIM_COLLISION_CHECK("ALL"),
.C_COMMON_CLK(0),
.C_DISABLE_WARN_BHV_COLL(0),
.C_EN_SLEEP_PIN(0),
.C_USE_URAM(0),
.C_EN_RDADDRA_CHG(0),
.C_EN_RDADDRB_CHG(0),
.C_EN_DEEPSLEEP_PIN(0),
.C_EN_SHUTDOWN_PIN(0),
.C_EN_SAFETY_CKT(0),
.C_DISABLE_WARN_BHV_RANGE(0),
.C_COUNT_36K_BRAM("2"),
.C_COUNT_18K_BRAM("1"),
.C_EST_POWER_SUMMARY("Estimated Power for IP : 6.3587 mW")
) inst (
.clka(clka),
.rsta(1'D0),
.ena(ena),
.regcea(1'D0),
.wea(wea),
.addra(addra),
.dina(dina),
.douta(douta),
.clkb(1'D0),
.rstb(1'D0),
.enb(1'D0),
.regceb(1'D0),
.web(1'B0),
.addrb(12'B0),
.dinb(20'B0),
.doutb(),
.injectsbiterr(1'D0),
.injectdbiterr(1'D0),
.eccpipece(1'D0),
.sbiterr(),
.dbiterr(),
.rdaddrecc(),
.sleep(1'D0),
.deepsleep(1'D0),
.shutdown(1'D0),
.rsta_busy(),
.rstb_busy(),
.s_aclk(1'H0),
.s_aresetn(1'D0),
.s_axi_awid(4'B0),
.s_axi_awaddr(32'B0),
.s_axi_awlen(8'B0),
.s_axi_awsize(3'B0),
.s_axi_awburst(2'B0),
.s_axi_awvalid(1'D0),
.s_axi_awready(),
.s_axi_wdata(20'B0),
.s_axi_wstrb(1'B0),
.s_axi_wlast(1'D0),
.s_axi_wvalid(1'D0),
.s_axi_wready(),
.s_axi_bid(),
.s_axi_bresp(),
.s_axi_bvalid(),
.s_axi_bready(1'D0),
.s_axi_arid(4'B0),
.s_axi_araddr(32'B0),
.s_axi_arlen(8'B0),
.s_axi_arsize(3'B0),
.s_axi_arburst(2'B0),
.s_axi_arvalid(1'D0),
.s_axi_arready(),
.s_axi_rid(),
.s_axi_rdata(),
.s_axi_rresp(),
.s_axi_rlast(),
.s_axi_rvalid(),
.s_axi_rready(1'D0),
.s_axi_injectsbiterr(1'D0),
.s_axi_injectdbiterr(1'D0),
.s_axi_sbiterr(),
.s_axi_dbiterr(),
.s_axi_rdaddrecc()
);
endmodule
|
Require Import Coq.ZArith.Zpower Coq.ZArith.ZArith.
Require Import Crypto.Util.ListUtil.
Require Import Crypto.Util.ZUtil.
Require Crypto.BaseSystem.
Require Import Coq.Lists.List.
Local Open Scope Z_scope.
Section Pow2Base.
Context (limb_widths : list Z).
Local Notation "w[ i ]" := (nth_default 0 limb_widths i).
Fixpoint base_from_limb_widths limb_widths :=
match limb_widths with
| nil => nil
| w :: lw => 1 :: map (Z.mul (two_p w)) (base_from_limb_widths lw)
end.
Local Notation base := (base_from_limb_widths limb_widths).
Definition bounded us := forall i, 0 <= nth_default 0 us i < 2 ^ w[i].
Definition upper_bound := 2 ^ (sum_firstn limb_widths (length limb_widths)).
Function decode_bitwise' us i acc :=
match i with
| O => acc
| S i' => decode_bitwise' us i' (Z.lor (nth_default 0 us i') (Z.shiftl acc w[i']))
end.
Definition decode_bitwise us := decode_bitwise' us (length us) 0.
(* i is current index, counts down *)
Fixpoint encode' z i :=
match i with
| O => nil
| S i' => let lw := sum_firstn limb_widths in
encode' z i' ++ (Z.shiftr (Z.land z (Z.ones (lw i))) (lw i')) :: nil
end.
Definition encodeZ x:= encode' x (length limb_widths).
(** ** Carrying *)
Section carrying.
(** Here we implement addition and multiplication with simple
carrying. *)
Notation log_cap i := (nth_default 0 limb_widths i).
Definition add_to_nth n (x:Z) xs :=
update_nth n (fun y => x + y) xs.
Definition carry_single i := fun di =>
(Z.pow2_mod di (log_cap i),
Z.shiftr di (log_cap i)).
(* [fi] is fed [length us] and [S i] and produces the index of
the digit to which value should be added;
[fc] modifies the carried value before adding it to that digit *)
Definition carry_gen fc fi i := fun us =>
let i := fi i in
let di := nth_default 0 us i in
let '(di', ci) := carry_single i di in
let us' := set_nth i di' us in
add_to_nth (fi (S i)) (fc ci) us'.
(* carry_simple does not modify the carried value, and always adds it
to the digit with index [S i] *)
Definition carry_simple := carry_gen (fun ci => ci) (fun i => i).
Definition carry_simple_sequence is us := fold_right carry_simple us is.
Fixpoint make_chain i :=
match i with
| O => nil
| S i' => i' :: make_chain i'
end.
Definition full_carry_chain := make_chain (length limb_widths).
Definition carry_simple_full := carry_simple_sequence full_carry_chain.
Definition carry_simple_add us vs := carry_simple_full (BaseSystem.add us vs).
Definition carry_simple_sub us vs := carry_simple_full (BaseSystem.sub us vs).
Definition carry_simple_mul out_base us vs := carry_simple_full (BaseSystem.mul out_base us vs).
End carrying.
End Pow2Base.
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 03/10/2016 04:46:19 PM
// Design Name:
// Module Name: exp_operation
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,
input wire load_b_i,
input wire [EW-1:0] Data_A_i,
input wire [EW-1:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW-1:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
//wire [EW-1:0] Data_B;
wire [EW:0] Data_S;
/////////////////////////////////////////7
//genvar j;
//for (j=0; j<EW; j=j+1)begin
// assign Data_B[j] = PreData_B_i[j] ^ Add_Subt_i;
//end
/////////////////////////////////////////
add_sub_carry_out #(.W(EW)) exp_add_subt(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S (Data_S)
);
//assign Overflow_flag_o = 1'b0;
//assign Underflow_flag_o = 1'b0;
Comparators #(.W_Exp(EW+1)) array_comparators(
.exp(Data_S),
.overflow(Overflow_flag),
.underflow(Underflow_flag)
);
RegisterAdd #(.W(EW)) exp_result(
.clk (clk),
.rst (rst),
.load (load_a_i),
.D (Data_S[EW-1:0]),
.Q (Data_Result_o)
);
RegisterAdd #(.W(1)) Overflow (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(Overflow_flag),
.Q(Overflow_flag_o)
);
RegisterAdd #(.W(1)) Underflow (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Underflow_flag),
.Q(Underflow_flag_o)
);
endmodule
|
/*
* 16-bit bitwise rotate module for Zet
* Copyright (C) 2008-2010 Zeus Gomez Marmolejo <[email protected]>
*
* This file is part of the Zet processor. This processor is free
* hardware; you can redistribute it and/or modify it under the terms of
* the GNU General Public License as published by the Free Software
* Foundation; either version 3, or (at your option) any later version.
*
* Zet is distrubuted in the hope that it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
* or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
* License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Zet; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
module zet_rxr16 (
input [15:0] x,
input ci,
input [ 4:0] y,
input e,
output reg [15:0] w,
output reg co
);
always @(x or ci or y or e)
case (y)
default: {co,w} <= {ci,x};
5'd01: {co,w} <= e ? {x[0], ci, x[15:1]} : {ci, x[0], x[15:1]};
5'd02: {co,w} <= e ? {x[ 1:0], ci, x[15: 2]} : {ci, x[ 1:0], x[15: 2]};
5'd03: {co,w} <= e ? {x[ 2:0], ci, x[15: 3]} : {ci, x[ 2:0], x[15: 3]};
5'd04: {co,w} <= e ? {x[ 3:0], ci, x[15: 4]} : {ci, x[ 3:0], x[15: 4]};
5'd05: {co,w} <= e ? {x[ 4:0], ci, x[15: 5]} : {ci, x[ 4:0], x[15: 5]};
5'd06: {co,w} <= e ? {x[ 5:0], ci, x[15: 6]} : {ci, x[ 5:0], x[15: 6]};
5'd07: {co,w} <= e ? {x[ 6:0], ci, x[15: 7]} : {ci, x[ 6:0], x[15: 7]};
5'd08: {co,w} <= e ? {x[ 7:0], ci, x[15: 8]} : {ci, x[ 7:0], x[15: 8]};
5'd09: {co,w} <= e ? {x[ 8:0], ci, x[15: 9]} : {ci, x[ 8:0], x[15: 9]};
5'd10: {co,w} <= e ? {x[ 9:0], ci, x[15:10]} : {ci, x[ 9:0], x[15:10]};
5'd11: {co,w} <= e ? {x[10:0], ci, x[15:11]} : {ci, x[10:0], x[15:11]};
5'd12: {co,w} <= e ? {x[11:0], ci, x[15:12]} : {ci, x[11:0], x[15:12]};
5'd13: {co,w} <= e ? {x[12:0], ci, x[15:13]} : {ci, x[12:0], x[15:13]};
5'd14: {co,w} <= e ? {x[13:0], ci, x[15:14]} : {ci, x[13:0], x[15:14]};
5'd15: {co,w} <= e ? {x[14:0], ci, x[15]} : {ci, x[14:0], x[15]};
5'd16: {co,w} <= {x,ci};
endcase
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
`define SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V
/**
* nor3b: 3-input NOR, first input inverted.
*
* Y = (!(A | B)) & !C)
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_pwrgood_pp_pg/sky130_fd_sc_ls__udp_pwrgood_pp_pg.v"
`celldefine
module sky130_fd_sc_ls__nor3b (
Y ,
A ,
B ,
C_N ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Y ;
input A ;
input B ;
input C_N ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire nor0_out ;
wire and0_out_Y ;
wire pwrgood_pp0_out_Y;
// Name Output Other arguments
nor nor0 (nor0_out , A, B );
and and0 (and0_out_Y , C_N, nor0_out );
sky130_fd_sc_ls__udp_pwrgood_pp$PG pwrgood_pp0 (pwrgood_pp0_out_Y, and0_out_Y, VPWR, VGND);
buf buf0 (Y , pwrgood_pp0_out_Y );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_LS__NOR3B_FUNCTIONAL_PP_V |
(*
Copyright © 2008 Russell O’Connor
Permission is hereby granted, free of charge, to any person obtaining a copy of
this proof and associated documentation files (the "Proof"), to deal in
the Proof without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
the Proof, and to permit persons to whom the Proof is furnished to do so,
subject to the following conditions:
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Proof.
THE PROOF IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
CONNECTION WITH THE PROOF OR THE USE OR OTHER DEALINGS IN THE PROOF.
*)
Require Export Metric.
Require Import Classification.
Require Import UniformContinuity.
Require Import Prelength.
Require Import Complete.
Require Import CornTac.
Set Implicit Arguments.
(**
** Product Metric
The product of two metric spaces forms a metric space *)
Section ProductSetoid.
Variable X Y : RSetoid.
Definition prod_st_eq (a b:X*Y) :=
st_eq (fst a) (fst b) /\ st_eq (snd a) (snd b).
Lemma prodST : Setoid_Theory _ prod_st_eq.
Proof.
split; unfold prod_st_eq.
intros; split; reflexivity.
intros x y [H1 H2]; split; symmetry; assumption.
intros x y z [H1 H2] [H3 H4]; split.
transitivity (fst y); assumption.
transitivity (snd y); assumption.
Qed.
Definition prodS : RSetoid := Build_RSetoid prodST.
End ProductSetoid.
Section ProductMetric.
Variable X Y : MetricSpace.
Definition prod_ball e (a b:X*Y) :=
ball e (fst a) (fst b) /\ ball e (snd a) (snd b).
Lemma prod_ball_refl : forall e a, prod_ball e a a.
Proof.
intros e a.
split; auto with *.
Qed.
Lemma prod_ball_sym : forall e a b, prod_ball e a b -> prod_ball e b a.
Proof.
intros e a b [H1 H2].
split; auto with *.
Qed.
Lemma prod_ball_triangle : forall e1 e2 a b c, prod_ball e1 a b -> prod_ball e2 b c -> prod_ball (e1 + e2) a c.
Proof.
intros e1 e2 a b c [H1 H2] [H3 H4].
split; eauto with metric.
Qed.
Lemma prod_ball_closed : forall e a b, (forall d, prod_ball (e + d) a b) -> prod_ball e a b.
Proof.
intros e a b H.
unfold prod_ball in *.
split; apply ball_closed; firstorder.
Qed.
Lemma prod_ball_eq : forall a b, (forall e, prod_ball e a b) -> prod_st_eq _ _ a b.
Proof.
intros a b H.
unfold prod_ball in *.
split; apply ball_eq; firstorder.
Qed.
Lemma prod_is_MetricSpace : is_MetricSpace (prodS X Y) prod_ball.
Proof.
split.
exact prod_ball_refl.
exact prod_ball_sym.
exact prod_ball_triangle.
exact prod_ball_closed.
exact prod_ball_eq.
Qed.
Definition ProductMS : MetricSpace.
Proof.
exists (prodS X Y) prod_ball.
abstract ( intros e1 e2 He a1 a2 [Ha0 Ha1] b1 b2 [Hb0 Hb1]; unfold prod_ball;
change (QposEq e1 e2) in He; rewrite -> He, Ha0, Ha1, Hb0, Hb1; reflexivity) using prod_ball_wd.
apply prod_is_MetricSpace.
Defined.
(** Product metrics preserve properties of metric spaces such as
being a prelenght space, being stable, being located, and being deciable
*)
Lemma ProductMS_prelength : PrelengthSpace X -> PrelengthSpace Y -> PrelengthSpace ProductMS.
Proof.
intros HX HY a b e d1 d2 Hed Hab.
destruct (HX (fst a) (fst b) e d1 d2 Hed (proj1 Hab)) as [c1 Hc1].
destruct (HY (snd a) (snd b) e d1 d2 Hed (proj2 Hab)) as [c2 Hc2].
exists (c1,c2); split; assumption.
Defined.
Lemma ProductMS_stable : stableMetric X -> stableMetric Y -> stableMetric ProductMS.
Proof.
unfold stableMetric.
intros H0 H1 e [xl xr] [yl yr] H.
simpl in H.
unfold prod_ball in H.
split.
apply H0; tauto.
apply H1; tauto.
Qed.
(** Furthermore, if a product space is stable, then the components are
stable (assuming the components are non-zero). *)
Lemma ProductMS_stableX : Y -> stableMetric ProductMS -> stableMetric X.
Proof.
unfold stableMetric.
intros a H0 e x y H.
assert (Z:~ ~ ball (m:=ProductMS) e (x,a) (y,a)).
revert H.
cut (ball (m:=X) e x y -> ball (m:=ProductMS) e (x, a) (y, a)).
tauto.
intros H.
split; auto.
apply ball_refl.
destruct (H0 _ _ _ Z).
assumption.
Qed.
Lemma ProductMS_stableY : X -> stableMetric ProductMS -> stableMetric Y.
Proof.
unfold stableMetric.
intros a H0 e x y H.
assert (Z:~ ~ ball (m:=ProductMS) e (a,x) (a,y)).
revert H.
cut (ball (m:=Y) e x y -> ball (m:=ProductMS) e (a,x) (a, y)).
tauto.
intros H.
split; auto.
apply ball_refl.
destruct (H0 _ _ _ Z).
assumption.
Qed.
Lemma ProductMS_located : locatedMetric X -> locatedMetric Y -> locatedMetric ProductMS.
Proof.
unfold locatedMetric.
intros H0 H1 e d x y Hed.
destruct (H0 _ _ (fst x) (fst y) Hed) as [A | A].
destruct (H1 _ _ (snd x) (snd y) Hed) as [B | B].
left.
split; assumption.
right; intros [_ H].
apply B; assumption.
right; intros [H _].
apply A; assumption.
Defined.
Lemma ProductMS_decidable : decidableMetric X -> decidableMetric Y -> decidableMetric ProductMS.
Proof.
unfold decidableMetric.
intros H0 H1 e x y.
destruct (H0 e (fst x) (fst y)) as [A | A].
destruct (H1 e (snd x) (snd y)) as [B | B].
left.
split; assumption.
right; intros [_ H].
apply B; assumption.
right; intros [H _].
apply A; assumption.
Defined.
(** This defines a pairing function with types of a metric space *)
Definition PairMS (x:X) (y:Y) : ProductMS := (x,y).
End ProductMetric.
(* begin hide *)
Implicit Arguments PairMS [X Y].
Add Parametric Morphism X Y : (@PairMS X Y) with signature (@st_eq _) ==> (@st_eq _) ==> (@st_eq _) as PairMS_wd.
Proof.
intros.
split; assumption.
Qed.
(* end hide *)
Open Local Scope uc_scope.
(** [together] forms the tensor of two functions operating between
metric spaces *)
Lemma together_uc : forall A B C D (f:A --> C) (g:B --> D),
is_UniformlyContinuousFunction (fun (p:ProductMS A B) => (f (fst p), g (snd p)):ProductMS C D) (fun x => QposInf_min (mu f x) (mu g x)).
Proof.
intros A B C D f g e a b H.
split; simpl; apply uc_prf; apply ball_ex_weak_le with (QposInf_min (mu f e) (mu g e)).
apply QposInf_min_lb_l.
destruct (QposInf_min (mu f e) (mu g e)) as [q|]; auto.
destruct H; auto.
apply QposInf_min_lb_r.
destruct (QposInf_min (mu f e) (mu g e)) as [q|]; auto.
destruct H; auto.
Qed.
Definition together A B C D (f:A --> C) (g:B --> D) : (ProductMS A B --> ProductMS C D) :=
Build_UniformlyContinuousFunction (together_uc f g).
(** Uniformly continuous functions on the product space can be curried: *)
Section uc_curry.
Context {A B C: MetricSpace} (f: ProductMS A B --> C).
Definition uc_curry_help_prf (a: A): is_UniformlyContinuousFunction (fun b => f (a, b)) (mu f).
Proof with auto.
repeat intro.
destruct f. clear f. simpl in *.
apply uc_prf.
destruct (mu e)...
split... apply ball_refl.
Qed.
Definition uc_curry_help (a: A): B --> C := Build_UniformlyContinuousFunction (uc_curry_help_prf a).
Definition uc_curry_prf: is_UniformlyContinuousFunction uc_curry_help (mu f).
Proof with auto.
repeat intro. simpl.
destruct f. clear f. simpl in *.
apply uc_prf.
destruct (mu e)...
split... apply ball_refl.
Qed.
Definition uc_curry: A --> B --> C := Build_UniformlyContinuousFunction uc_curry_prf.
End uc_curry.
(** Uncurry probably cannot be defined because because there is no way to construct a
uniform modulus of continuity from the domain-indexed set of uni-formly continuous functions.
Hence, we can convert only one way, and so non-curried versions of binary functions are
strictly more valuable than their curried representations. Consequently, it can be argued
that binary functions should always be defined in non-curried form. *)
(** Completion distributes over products: *)
Section completion_distributes.
Context {X Y: MetricSpace}.
Program Definition distrib_Complete (xy: Complete (ProductMS X Y)): ProductMS (Complete X) (Complete Y) :=
(@Build_RegularFunction _ (fun e => fst (approximate xy e)) _, @Build_RegularFunction _ (fun e => snd (approximate xy e)) _).
Next Obligation. repeat intro. apply xy. Qed.
Next Obligation. repeat intro. apply xy. Qed.
Lemma distrib_Complete_uc_prf: is_UniformlyContinuousFunction distrib_Complete (fun e => e).
Proof.
unfold distrib_Complete.
intros ??? H. split; repeat intro; simpl; apply H.
Qed.
Definition distrib_Complete_uc: Complete (ProductMS X Y) --> ProductMS (Complete X) (Complete Y) :=
Build_UniformlyContinuousFunction distrib_Complete_uc_prf.
Program Definition undistrib_Complete (xy: ProductMS (Complete X) (Complete Y)): Complete (ProductMS X Y) :=
@Build_RegularFunction _ (fun e => (approximate (fst xy) e, approximate (snd xy) e)) _.
Next Obligation. split. apply r. apply r0. Qed.
Lemma undistrib_Complete_uc_prf: is_UniformlyContinuousFunction undistrib_Complete (fun e => e).
Proof.
unfold distrib_Complete.
intros ??? H. split; repeat intro; simpl; apply H.
Qed.
Definition undistrib_Complete_uc: ProductMS (Complete X) (Complete Y) --> Complete (ProductMS X Y) :=
Build_UniformlyContinuousFunction undistrib_Complete_uc_prf.
Lemma distrib_after_undistrib_Complete xy: st_eq (distrib_Complete (undistrib_Complete xy)) xy.
Proof.
intros. unfold distrib_Complete, undistrib_Complete. simpl.
unfold prod_st_eq. simpl.
split; apply regFunEq_e; simpl; intros; apply ball_refl.
Qed.
Lemma undistrib_after_distrib_Complete xy: st_eq (undistrib_Complete (distrib_Complete xy)) xy.
Proof.
intros. unfold undistrib_Complete. simpl.
apply regFunEq_e.
split; simpl; apply ball_refl.
Qed.
End completion_distributes.
(** The diagonal function [x ⟼ (x,x)] is a uniformly continuous function
from a metric space X to the product space [X × X] *)
Section diag.
Require Import Unicode.Utf8.
Variable X:MetricSpace.
Definition diag_raw : X → (ProductMS X X) := λ x, (x,x).
Lemma diag_uc : (is_UniformlyContinuousFunction diag_raw (λ ε, ε)%Qpos).
Proof.
repeat try red; intuition.
Qed.
Definition diag: X --> (ProductMS X X) := Build_UniformlyContinuousFunction diag_uc.
End diag. |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__EINVP_SYMBOL_V
`define SKY130_FD_SC_LP__EINVP_SYMBOL_V
/**
* einvp: Tri-state inverter, positive enable.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_lp__einvp (
//# {{data|Data Signals}}
input A ,
output Z ,
//# {{control|Control Signals}}
input TE
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_LP__EINVP_SYMBOL_V
|
//#############################################################################
//# Function: Synchronous FIFO #
//#############################################################################
//# Author: Andreas Olofsson #
//# License: MIT (see LICENSE file in OH! repository) #
//#############################################################################
module oh_fifo_sync #(parameter DW = 104, //FIFO width
parameter DEPTH = 32, //FIFO depth
parameter PROG_FULL = (DEPTH/2),//prog_full threshold
parameter AW = $clog2(DEPTH) //rd_count width
)
(
input clk, // clock
input nreset, // active high async reset
input [DW-1:0] din, // data to write
input wr_en, // write fifo
input rd_en, // read fifo
output [DW-1:0] dout, // output data (next cycle)
output full, // fifo full
output prog_full, // fifo is almost full
output empty, // fifo is empty
output reg [AW-1:0] rd_count // valid entries in fifo
);
reg [AW-1:0] wr_addr;
reg [AW-1:0] rd_addr;
wire fifo_read;
wire fifo_write;
assign empty = (rd_count[AW-1:0] == 0);
assign prog_full = (rd_count[AW-1:0] >= PROG_FULL);
assign full = (rd_count[AW-1:0] == (DEPTH-1));
assign fifo_read = rd_en & ~empty;
assign fifo_write = wr_en & ~full;
always @ ( posedge clk or negedge nreset)
if(!nreset)
begin
wr_addr[AW-1:0] <= 'd0;
rd_addr[AW-1:0] <= 'b0;
rd_count[AW-1:0] <= 'b0;
end
else if(fifo_write & fifo_read)
begin
wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
end
else if(fifo_write)
begin
wr_addr[AW-1:0] <= wr_addr[AW-1:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] + 'd1;
end
else if(fifo_read)
begin
rd_addr[AW-1:0] <= rd_addr[AW-1:0] + 'd1;
rd_count[AW-1:0]<= rd_count[AW-1:0] - 'd1;
end
// GENERIC DUAL PORTED MEMORY
oh_memory_dp
#(.DW(DW),
.DEPTH(DEPTH))
mem (// read port
.rd_dout (dout[DW-1:0]),
.rd_clk (clk),
.rd_en (fifo_read),
.rd_addr (rd_addr[AW-1:0]),
// write port
.wr_clk (clk),
.wr_en (fifo_write),
.wr_wem ({(DW){1'b1}}),
.wr_addr (wr_addr[AW-1:0]),
.wr_din (din[DW-1:0]));
endmodule // oh_fifo_sync
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date:
// Design Name:
// Module Name: ACA_I_N32_Q8
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module ACA_I_N32_Q8(
input [31:0] in1,
input [31:0] in2,
output [32:0] res
);
wire [8:0] temp1,temp2,temp3,temp4,temp5,temp6,temp7,temp8,temp9,temp10;
wire [8:0] temp11,temp12,temp13,temp14,temp15,temp16,temp17,temp18,temp19;
wire [8:0] temp20,temp21,temp22,temp23,temp24,temp25;
assign temp1[8:0] = in1[7:0] + in2[7:0];
assign temp2[8:0] = in1[8:1] + in2[8:1];
assign temp3[8:0] = in1[9:2] + in2[9:2];
assign temp4[8:0] = in1[10:3] + in2[10:3];
assign temp5[8:0] = in1[11:4] + in2[11:4];
assign temp6[8:0] = in1[12:5] + in2[12:5];
assign temp7[8:0] = in1[13:6] + in2[13:6];
assign temp8[8:0] = in1[14:7] + in2[14:7];
assign temp9[8:0] = in1[15:8] + in2[15:8];
assign temp10[8:0] = in1[16:9] + in2[16:9];
assign temp11[8:0] = in1[17:10] + in2[17:10];
assign temp12[8:0] = in1[18:11] + in2[18:11];
assign temp13[8:0] = in1[19:12] + in2[19:12];
assign temp14[8:0] = in1[20:13] + in2[20:13];
assign temp15[8:0] = in1[21:14] + in2[21:14];
assign temp16[8:0] = in1[22:15] + in2[22:15];
assign temp17[8:0] = in1[23:16] + in2[23:16];
assign temp18[8:0] = in1[24:17] + in2[24:17];
assign temp19[8:0] = in1[25:18] + in2[25:18];
assign temp20[8:0] = in1[26:19] + in2[26:19];
assign temp21[8:0] = in1[27:20] + in2[27:20];
assign temp22[8:0] = in1[28:21] + in2[28:21];
assign temp23[8:0] = in1[29:22] + in2[29:22];
assign temp24[8:0] = in1[30:23] + in2[30:23];
assign temp25[8:0] = in1[31:24] + in2[31:24];
assign res[32:0] = {temp25[8:7],temp24[7],temp23[7],temp22[7],temp21[7],temp20[7],temp19[7],temp18[7],temp17[7],temp16[7],temp15[7],temp14[7],temp13[7],temp12[7],temp11[7],temp10[7],temp9[7],temp8[7],temp7[7],temp6[7],temp5[7],temp4[7],temp3[7],temp2[7],temp1[7:0]};
endmodule
|
// -- (c) Copyright 2010 - 2011 Xilinx, Inc. All rights reserved.
// --
// -- This file contains confidential and proprietary information
// -- of Xilinx, Inc. and is protected under U.S. and
// -- international copyright and other intellectual property
// -- laws.
// --
// -- DISCLAIMER
// -- This disclaimer is not a license and does not grant any
// -- rights to the materials distributed herewith. Except as
// -- otherwise provided in a valid license issued to you by
// -- Xilinx, and to the maximum extent permitted by applicable
// -- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// -- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// -- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// -- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// -- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// -- (2) Xilinx shall not be liable (whether in contract or tort,
// -- including negligence, or under any other theory of
// -- liability) for any loss or damage of any kind or nature
// -- related to, arising under or in connection with these
// -- materials, including for any direct, or any indirect,
// -- special, incidental, or consequential loss or damage
// -- (including loss of data, profits, goodwill, or any type of
// -- loss or damage suffered as a result of any action brought
// -- by a third party) even if such damage or loss was
// -- reasonably foreseeable or Xilinx had been advised of the
// -- possibility of the same.
// --
// -- CRITICAL APPLICATIONS
// -- Xilinx products are not designed or intended to be fail-
// -- safe, or for use in any application requiring fail-safe
// -- performance, such as life-support or safety devices or
// -- systems, Class III medical devices, nuclear facilities,
// -- applications related to the deployment of airbags, or any
// -- other applications that could lead to death, personal
// -- injury, or severe property or environmental damage
// -- (individually and collectively, "Critical
// -- Applications"). Customer assumes the sole risk and
// -- liability of any use of Xilinx products in Critical
// -- Applications, subject only to applicable laws and
// -- regulations governing limitations on product liability.
// --
// -- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// -- PART OF THIS FILE AT ALL TIMES.
//-----------------------------------------------------------------------------
//
// Description:
// Optimized COMPARATOR with generic_baseblocks_v2_1_carry logic.
//
// Verilog-standard: Verilog 2001
//--------------------------------------------------------------------------
//
// Structure:
//
//
//--------------------------------------------------------------------------
`timescale 1ps/1ps
(* DowngradeIPIdentifiedWarnings="yes" *)
module generic_baseblocks_v2_1_comparator_mask #
(
parameter C_FAMILY = "virtex6",
// FPGA Family. Current version: virtex6 or spartan6.
parameter integer C_DATA_WIDTH = 4
// Data width for comparator.
)
(
input wire CIN,
input wire [C_DATA_WIDTH-1:0] A,
input wire [C_DATA_WIDTH-1:0] B,
input wire [C_DATA_WIDTH-1:0] M,
output wire COUT
);
/////////////////////////////////////////////////////////////////////////////
// Variables for generating parameter controlled instances.
/////////////////////////////////////////////////////////////////////////////
// Generate variable for bit vector.
genvar lut_cnt;
/////////////////////////////////////////////////////////////////////////////
// Local params
/////////////////////////////////////////////////////////////////////////////
// Bits per LUT for this architecture.
localparam integer C_BITS_PER_LUT = 2;
// Constants for packing levels.
localparam integer C_NUM_LUT = ( C_DATA_WIDTH + C_BITS_PER_LUT - 1 ) / C_BITS_PER_LUT;
//
localparam integer C_FIX_DATA_WIDTH = ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) ? C_NUM_LUT * C_BITS_PER_LUT :
C_DATA_WIDTH;
/////////////////////////////////////////////////////////////////////////////
// Functions
/////////////////////////////////////////////////////////////////////////////
/////////////////////////////////////////////////////////////////////////////
// Internal signals
/////////////////////////////////////////////////////////////////////////////
wire [C_FIX_DATA_WIDTH-1:0] a_local;
wire [C_FIX_DATA_WIDTH-1:0] b_local;
wire [C_FIX_DATA_WIDTH-1:0] m_local;
wire [C_NUM_LUT-1:0] sel;
wire [C_NUM_LUT:0] carry_local;
/////////////////////////////////////////////////////////////////////////////
//
/////////////////////////////////////////////////////////////////////////////
generate
// Assign input to local vectors.
assign carry_local[0] = CIN;
// Extend input data to fit.
if ( C_NUM_LUT * C_BITS_PER_LUT > C_DATA_WIDTH ) begin : USE_EXTENDED_DATA
assign a_local = {A, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign b_local = {B, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
assign m_local = {M, {C_NUM_LUT * C_BITS_PER_LUT - C_DATA_WIDTH{1'b0}}};
end else begin : NO_EXTENDED_DATA
assign a_local = A;
assign b_local = B;
assign m_local = M;
end
// Instantiate one generic_baseblocks_v2_1_carry and per level.
for (lut_cnt = 0; lut_cnt < C_NUM_LUT ; lut_cnt = lut_cnt + 1) begin : LUT_LEVEL
// Create the local select signal
assign sel[lut_cnt] = ( ( a_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) ==
( b_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] &
m_local[lut_cnt*C_BITS_PER_LUT +: C_BITS_PER_LUT] ) );
// Instantiate each LUT level.
generic_baseblocks_v2_1_carry_and #
(
.C_FAMILY(C_FAMILY)
) compare_inst
(
.COUT (carry_local[lut_cnt+1]),
.CIN (carry_local[lut_cnt]),
.S (sel[lut_cnt])
);
end // end for lut_cnt
// Assign output from local vector.
assign COUT = carry_local[C_NUM_LUT];
endgenerate
endmodule
|
//*****************************************************************************
// (c) Copyright 2009 - 2013 Xilinx, Inc. All rights reserved.
//
// This file contains confidential and proprietary information
// of Xilinx, Inc. and is protected under U.S. and
// international copyright and other intellectual property
// laws.
//
// DISCLAIMER
// This disclaimer is not a license and does not grant any
// rights to the materials distributed herewith. Except as
// otherwise provided in a valid license issued to you by
// Xilinx, and to the maximum extent permitted by applicable
// law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
// WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
// AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
// BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
// INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
// (2) Xilinx shall not be liable (whether in contract or tort,
// including negligence, or under any other theory of
// liability) for any loss or damage of any kind or nature
// related to, arising under or in connection with these
// materials, including for any direct, or any indirect,
// special, incidental, or consequential loss or damage
// (including loss of data, profits, goodwill, or any type of
// loss or damage suffered as a result of any action brought
// by a third party) even if such damage or loss was
// reasonably foreseeable or Xilinx had been advised of the
// possibility of the same.
//
// CRITICAL APPLICATIONS
// Xilinx products are not designed or intended to be fail-
// safe, or for use in any application requiring fail-safe
// performance, such as life-support or safety devices or
// systems, Class III medical devices, nuclear facilities,
// applications related to the deployment of airbags, or any
// other applications that could lead to death, personal
// injury, or severe property or environmental damage
// (individually and collectively, "Critical
// Applications"). Customer assumes the sole risk and
// liability of any use of Xilinx products in Critical
// Applications, subject only to applicable laws and
// regulations governing limitations on product liability.
//
// THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
// PART OF THIS FILE AT ALL TIMES.
//
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: %version
// \ \ Application: MIG
// / / Filename: iodelay_ctrl.v
// /___/ /\ Date Last Modified: $Date: 2011/06/02 08:34:56 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: 7 Series
//Design Name: DDR3 SDRAM
//Purpose:
// This module instantiates the IDELAYCTRL primitive, which continously
// calibrates the IODELAY elements in the region to account for varying
// environmental conditions. A 200MHz or 300MHz reference clock (depending
// on the desired IODELAY tap resolution) must be supplied
//Reference:
//Revision History:
//*****************************************************************************
/******************************************************************************
**$Id: iodelay_ctrl.v,v 1.1 2011/06/02 08:34:56 mishra Exp $
**$Date: 2011/06/02 08:34:56 $
**$Author: mishra $
**$Revision: 1.1 $
**$Source: /devl/xcs/repo/env/Databases/ip/src2/O/mig_7series_v1_3/data/dlib/7series/ddr3_sdram/verilog/rtl/clocking/iodelay_ctrl.v,v $
******************************************************************************/
`timescale 1ps/1ps
module mig_7series_v2_3_iodelay_ctrl #
(
parameter TCQ = 100,
// clk->out delay (sim only)
parameter IODELAY_GRP0 = "IODELAY_MIG0",
// May be assigned unique name when
// multiple IP cores used in design
parameter IODELAY_GRP1 = "IODELAY_MIG1",
// May be assigned unique name when
// multiple IP cores used in design
parameter REFCLK_TYPE = "DIFFERENTIAL",
// Reference clock type
// "DIFFERENTIAL","SINGLE_ENDED"
// NO_BUFFER, USE_SYSTEM_CLOCK
parameter SYSCLK_TYPE = "DIFFERENTIAL",
// input clock type
// DIFFERENTIAL, SINGLE_ENDED,
// NO_BUFFER
parameter SYS_RST_PORT = "FALSE",
// "TRUE" - if pin is selected for sys_rst
// and IBUF will be instantiated.
// "FALSE" - if pin is not selected for sys_rst
parameter RST_ACT_LOW = 1,
// Reset input polarity
// (0 = active high, 1 = active low)
parameter DIFF_TERM_REFCLK = "TRUE",
// Differential Termination
parameter FPGA_SPEED_GRADE = 1,
// FPGA speed grade
parameter REF_CLK_MMCM_IODELAY_CTRL = "FALSE"
)
(
input clk_ref_p,
input clk_ref_n,
input clk_ref_i,
input sys_rst,
output [1:0] clk_ref,
output sys_rst_o,
output [1:0] iodelay_ctrl_rdy
);
// # of clock cycles to delay deassertion of reset. Needs to be a fairly
// high number not so much for metastability protection, but to give time
// for reset (i.e. stable clock cycles) to propagate through all state
// machines and to all control signals (i.e. not all control signals have
// resets, instead they rely on base state logic being reset, and the effect
// of that reset propagating through the logic). Need this because we may not
// be getting stable clock cycles while reset asserted (i.e. since reset
// depends on DCM lock status)
// COMMENTED, RC, 01/13/09 - causes pack error in MAP w/ larger #
localparam RST_SYNC_NUM = 15;
// localparam RST_SYNC_NUM = 25;
wire clk_ref_ibufg;
wire clk_ref_mmcm_300;
wire clk_ref_mmcm_400;
wire mmcm_clkfbout;
wire mmcm_Locked;
wire [1:0] rst_ref;
reg [RST_SYNC_NUM-1:0] rst_ref_sync_r [1:0] /* synthesis syn_maxfan = 10 */;
wire rst_tmp_idelay;
wire sys_rst_act_hi;
//***************************************************************************
// If the pin is selected for sys_rst in GUI, IBUF will be instantiated.
// If the pin is not selected in GUI, sys_rst signal is expected to be
// driven internally.
generate
if (SYS_RST_PORT == "TRUE")
IBUF u_sys_rst_ibuf
(
.I (sys_rst),
.O (sys_rst_o)
);
else
assign sys_rst_o = sys_rst;
endgenerate
// Possible inversion of system reset as appropriate
assign sys_rst_act_hi = RST_ACT_LOW ? ~sys_rst_o: sys_rst_o;
//***************************************************************************
// 1) Input buffer for IDELAYCTRL reference clock - handle either a
// differential or single-ended input. Global clock buffer is used to
// drive the rest of FPGA logic.
// 2) For NO_BUFFER option, Reference clock will be driven from internal
// clock i.e., clock is driven from fabric. Input buffers and Global
// clock buffers will not be instaitaed.
// 3) For USE_SYSTEM_CLOCK, input buffer output of system clock will be used
// as the input reference clock. Global clock buffer is used to drive
// the rest of FPGA logic.
//***************************************************************************
generate
if (REFCLK_TYPE == "DIFFERENTIAL") begin: diff_clk_ref
IBUFGDS #
(
.DIFF_TERM (DIFF_TERM_REFCLK),
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_p),
.IB (clk_ref_n),
.O (clk_ref_ibufg)
);
end else if (REFCLK_TYPE == "SINGLE_ENDED") begin : se_clk_ref
IBUFG #
(
.IBUF_LOW_PWR ("FALSE")
)
u_ibufg_clk_ref
(
.I (clk_ref_i),
.O (clk_ref_ibufg)
);
end else if ((REFCLK_TYPE == "NO_BUFFER") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE == "NO_BUFFER")) begin : clk_ref_noibuf_nobuf
assign clk_ref_ibufg = clk_ref_i;
end else if (REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER") begin : clk_ref_noibuf
assign clk_ref_ibufg = clk_ref_i;
end
endgenerate
// reference clock 300MHz and 400MHz generation with MMCM
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: clk_ref_mmcm_gen
MMCME2_ADV
#(.BANDWIDTH ("HIGH"),
.CLKOUT4_CASCADE ("FALSE"),
.COMPENSATION ("INTERNAL"),
.STARTUP_WAIT ("FALSE"),
.DIVCLK_DIVIDE (1),
.CLKFBOUT_MULT_F (6),
.CLKFBOUT_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_DIVIDE_F (4),
.CLKOUT0_PHASE (0.000),
.CLKOUT0_DUTY_CYCLE (0.500),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_DIVIDE (3),
.CLKOUT1_PHASE (0.000),
.CLKOUT1_DUTY_CYCLE (0.500),
.CLKOUT1_USE_FINE_PS ("FALSE"),
.CLKIN1_PERIOD (5),
.REF_JITTER1 (0.000))
mmcm_i
// Output clocks
(.CLKFBOUT (mmcm_clkfbout),
.CLKFBOUTB (),
.CLKOUT0 (clk_ref_mmcm_300),
.CLKOUT0B (),
.CLKOUT1 (clk_ref_mmcm_400),
.CLKOUT1B (),
.CLKOUT2 (),
.CLKOUT2B (),
.CLKOUT3 (),
.CLKOUT3B (),
.CLKOUT4 (),
.CLKOUT5 (),
.CLKOUT6 (),
// Input clock control
.CLKFBIN (mmcm_clkfbout),
.CLKIN1 (clk_ref_ibufg),
.CLKIN2 (1'b0),
// Tied to always select the primary input clock
.CLKINSEL (1'b1),
// Ports for dynamic reconfiguration
.DADDR (7'h0),
.DCLK (1'b0),
.DEN (1'b0),
.DI (16'h0),
.DO (),
.DRDY (),
.DWE (1'b0),
// Ports for dynamic phase shift
.PSCLK (1'b0),
.PSEN (1'b0),
.PSINCDEC (1'b0),
.PSDONE (),
// Other control and status signals
.LOCKED (mmcm_Locked),
.CLKINSTOPPED (),
.CLKFBSTOPPED (),
.PWRDWN (1'b0),
.RST (sys_rst_act_hi));
end
endgenerate
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin : clk_ref_300_400_en
if(FPGA_SPEED_GRADE == 1) begin: clk_ref_300
BUFG u_bufg_clk_ref_300
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_300)
);
end else if (FPGA_SPEED_GRADE == 2 || FPGA_SPEED_GRADE == 3) begin: clk_ref_400
BUFG u_bufg_clk_ref_400
(
.O (clk_ref[1]),
.I (clk_ref_mmcm_400)
);
end
end
endgenerate
generate
if ((REFCLK_TYPE == "DIFFERENTIAL") ||
(REFCLK_TYPE == "SINGLE_ENDED") ||
(REFCLK_TYPE == "USE_SYSTEM_CLOCK" && SYSCLK_TYPE != "NO_BUFFER")) begin: clk_ref_200
BUFG u_bufg_clk_ref
(
.O (clk_ref[0]),
.I (clk_ref_ibufg)
);
end else begin: clk_ref_200_no_buffer
assign clk_ref[0] = clk_ref_i;
end
endgenerate
//*****************************************************************
// IDELAYCTRL reset
// This assumes an external clock signal driving the IDELAYCTRL
// blocks. Otherwise, if a PLL drives IDELAYCTRL, then the PLL
// lock signal will need to be incorporated in this.
//*****************************************************************
// Add PLL lock if PLL drives IDELAYCTRL in user design
assign rst_tmp_idelay = sys_rst_act_hi;
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: rst_ref_gen_1
always @(posedge clk_ref[1] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[1] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[1] <= #TCQ rst_ref_sync_r[1] << 1;
assign rst_ref[1] = rst_ref_sync_r[1][RST_SYNC_NUM-1];
end
endgenerate
always @(posedge clk_ref[0] or posedge rst_tmp_idelay)
if (rst_tmp_idelay)
rst_ref_sync_r[0] <= #TCQ {RST_SYNC_NUM{1'b1}};
else
rst_ref_sync_r[0] <= #TCQ rst_ref_sync_r[0] << 1;
assign rst_ref[0] = rst_ref_sync_r[0][RST_SYNC_NUM-1];
//*****************************************************************
generate
if (REF_CLK_MMCM_IODELAY_CTRL == "TRUE") begin: idelayctrl_gen_1
(* IODELAY_GROUP = IODELAY_GRP1 *) IDELAYCTRL u_idelayctrl_300_400
(
.RDY (iodelay_ctrl_rdy[1]),
.REFCLK (clk_ref[1]),
.RST (rst_ref[1])
);
end
endgenerate
(* IODELAY_GROUP = IODELAY_GRP0 *) IDELAYCTRL u_idelayctrl_200
(
.RDY (iodelay_ctrl_rdy[0]),
.REFCLK (clk_ref[0]),
.RST (rst_ref[0])
);
endmodule
|
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Claire Xenia Wolf <[email protected]>
* 2019 Eddie Hung <[email protected]>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
// The purpose of these mapping rules is to allow preserve all (sufficiently
// wide) $shiftx cells during 'techmap' so that they can be mapped to hard
// resources, rather than being bit-blasted to gates during 'techmap'
// execution
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
(* force_downto *)
input [A_WIDTH-1:0] A;
(* force_downto *)
input [B_WIDTH-1:0] B;
(* force_downto *)
output [Y_WIDTH-1:0] Y;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
generate
if (B_SIGNED) begin
if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && (_TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0 || _TECHMAP_CONSTVAL_B_[B_WIDTH-1] === 1'bx))
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
\$shiftx #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(0),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH-1'd1),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B[B_WIDTH-2:0]), .Y(Y)
);
else
wire _TECHMAP_FAIL_ = 1;
end
else begin
if (((A_WIDTH + Y_WIDTH - 1) / Y_WIDTH) < `MIN_MUX_INPUTS)
wire _TECHMAP_FAIL_ = 1;
else
\$__XILINX_SHIFTX #(
.A_SIGNED(A_SIGNED),
.B_SIGNED(B_SIGNED),
.A_WIDTH(A_WIDTH),
.B_WIDTH(B_WIDTH),
.Y_WIDTH(Y_WIDTH)
) _TECHMAP_REPLACE_ (
.A(A), .B(B), .Y(Y)
);
end
endgenerate
endmodule
|
// Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2013.4 (lin64) Build 353583 Mon Dec 9 17:26:26 MST 2013
// Date : Sat Mar 15 17:18:29 2014
// Host : macbook running 64-bit Arch Linux
// Command : write_verilog -force -mode funcsim
// /home/keith/Documents/VHDL-lib/top/lab_2/part_1/build/lab2_part1.srcs/sources_1/ip/clk_base/clk_base_funcsim.v
// Design : clk_base
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7z020clg484-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
(* core_generation_info = "clk_base,clk_wiz_v5_1,{component_name=clk_base,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}" *)
(* NotValidForBitStream *)
module clk_base
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire clk_100MHz;
wire clk_250MHz;
(* IBUF_LOW_PWR *) wire clk_raw;
wire locked;
clk_baseclk_base_clk_wiz U0
(.clk_100MHz(clk_100MHz),
.clk_250MHz(clk_250MHz),
.clk_raw(clk_raw),
.locked(locked));
endmodule
module clk_baseclk_base_clk_wiz
(clk_raw,
clk_100MHz,
clk_250MHz,
locked);
input clk_raw;
output clk_100MHz;
output clk_250MHz;
output locked;
wire \<const0> ;
wire \<const1> ;
wire clk_100MHz;
wire clk_100MHz_clk_base;
wire clk_250MHz;
wire clk_250MHz_clk_base;
(* IBUF_LOW_PWR *) wire clk_raw;
wire clk_raw_clk_base;
wire clkfbout_buf_clk_base;
wire clkfbout_clk_base;
wire locked;
wire NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED;
wire NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED;
wire NLW_mmcm_adv_inst_DRDY_UNCONNECTED;
wire NLW_mmcm_adv_inst_PSDONE_UNCONNECTED;
wire [15:0]NLW_mmcm_adv_inst_DO_UNCONNECTED;
GND GND
(.G(\<const0> ));
VCC VCC
(.P(\<const1> ));
(* box_type = "PRIMITIVE" *)
BUFG clkf_buf
(.I(clkfbout_clk_base),
.O(clkfbout_buf_clk_base));
(* CAPACITANCE = "DONT_CARE" *)
(* IBUF_DELAY_VALUE = "0" *)
(* IFD_DELAY_VALUE = "AUTO" *)
(* box_type = "PRIMITIVE" *)
IBUF #(
.IOSTANDARD("DEFAULT"))
clkin1_ibufg
(.I(clk_raw),
.O(clk_raw_clk_base));
(* box_type = "PRIMITIVE" *)
BUFG clkout1_buf
(.I(clk_100MHz_clk_base),
.O(clk_100MHz));
(* box_type = "PRIMITIVE" *)
BUFG clkout2_buf
(.I(clk_250MHz_clk_base),
.O(clk_250MHz));
(* box_type = "PRIMITIVE" *)
MMCME2_ADV #(
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT_F(10.000000),
.CLKFBOUT_PHASE(0.000000),
.CLKFBOUT_USE_FINE_PS("FALSE"),
.CLKIN1_PERIOD(10.000000),
.CLKIN2_PERIOD(0.000000),
.CLKOUT0_DIVIDE_F(10.000000),
.CLKOUT0_DUTY_CYCLE(0.500000),
.CLKOUT0_PHASE(0.000000),
.CLKOUT0_USE_FINE_PS("FALSE"),
.CLKOUT1_DIVIDE(4),
.CLKOUT1_DUTY_CYCLE(0.500000),
.CLKOUT1_PHASE(0.000000),
.CLKOUT1_USE_FINE_PS("FALSE"),
.CLKOUT2_DIVIDE(1),
.CLKOUT2_DUTY_CYCLE(0.500000),
.CLKOUT2_PHASE(0.000000),
.CLKOUT2_USE_FINE_PS("FALSE"),
.CLKOUT3_DIVIDE(1),
.CLKOUT3_DUTY_CYCLE(0.500000),
.CLKOUT3_PHASE(0.000000),
.CLKOUT3_USE_FINE_PS("FALSE"),
.CLKOUT4_CASCADE("FALSE"),
.CLKOUT4_DIVIDE(1),
.CLKOUT4_DUTY_CYCLE(0.500000),
.CLKOUT4_PHASE(0.000000),
.CLKOUT4_USE_FINE_PS("FALSE"),
.CLKOUT5_DIVIDE(1),
.CLKOUT5_DUTY_CYCLE(0.500000),
.CLKOUT5_PHASE(0.000000),
.CLKOUT5_USE_FINE_PS("FALSE"),
.CLKOUT6_DIVIDE(1),
.CLKOUT6_DUTY_CYCLE(0.500000),
.CLKOUT6_PHASE(0.000000),
.CLKOUT6_USE_FINE_PS("FALSE"),
.COMPENSATION("ZHOLD"),
.DIVCLK_DIVIDE(1),
.IS_CLKINSEL_INVERTED(1'b0),
.IS_PSEN_INVERTED(1'b0),
.IS_PSINCDEC_INVERTED(1'b0),
.IS_PWRDWN_INVERTED(1'b0),
.IS_RST_INVERTED(1'b0),
.REF_JITTER1(0.010000),
.REF_JITTER2(0.000000),
.SS_EN("FALSE"),
.SS_MODE("CENTER_HIGH"),
.SS_MOD_PERIOD(10000),
.STARTUP_WAIT("FALSE"))
mmcm_adv_inst
(.CLKFBIN(clkfbout_buf_clk_base),
.CLKFBOUT(clkfbout_clk_base),
.CLKFBOUTB(NLW_mmcm_adv_inst_CLKFBOUTB_UNCONNECTED),
.CLKFBSTOPPED(NLW_mmcm_adv_inst_CLKFBSTOPPED_UNCONNECTED),
.CLKIN1(clk_raw_clk_base),
.CLKIN2(\<const0> ),
.CLKINSEL(\<const1> ),
.CLKINSTOPPED(NLW_mmcm_adv_inst_CLKINSTOPPED_UNCONNECTED),
.CLKOUT0(clk_100MHz_clk_base),
.CLKOUT0B(NLW_mmcm_adv_inst_CLKOUT0B_UNCONNECTED),
.CLKOUT1(clk_250MHz_clk_base),
.CLKOUT1B(NLW_mmcm_adv_inst_CLKOUT1B_UNCONNECTED),
.CLKOUT2(NLW_mmcm_adv_inst_CLKOUT2_UNCONNECTED),
.CLKOUT2B(NLW_mmcm_adv_inst_CLKOUT2B_UNCONNECTED),
.CLKOUT3(NLW_mmcm_adv_inst_CLKOUT3_UNCONNECTED),
.CLKOUT3B(NLW_mmcm_adv_inst_CLKOUT3B_UNCONNECTED),
.CLKOUT4(NLW_mmcm_adv_inst_CLKOUT4_UNCONNECTED),
.CLKOUT5(NLW_mmcm_adv_inst_CLKOUT5_UNCONNECTED),
.CLKOUT6(NLW_mmcm_adv_inst_CLKOUT6_UNCONNECTED),
.DADDR({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DCLK(\<const0> ),
.DEN(\<const0> ),
.DI({\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> ,\<const0> }),
.DO(NLW_mmcm_adv_inst_DO_UNCONNECTED[15:0]),
.DRDY(NLW_mmcm_adv_inst_DRDY_UNCONNECTED),
.DWE(\<const0> ),
.LOCKED(locked),
.PSCLK(\<const0> ),
.PSDONE(NLW_mmcm_adv_inst_PSDONE_UNCONNECTED),
.PSEN(\<const0> ),
.PSINCDEC(\<const0> ),
.PWRDWN(\<const0> ),
.RST(\<const0> ));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
//*****************************************************************************
// DISCLAIMER OF LIABILITY
//
// This file contains proprietary and confidential information of
// Xilinx, Inc. ("Xilinx"), that is distributed under a license
// from Xilinx, and may be used, copied and/or disclosed only
// pursuant to the terms of a valid license agreement with Xilinx.
//
// XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION
// ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER
// EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT
// LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT,
// MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx
// does not warrant that functions included in the Materials will
// meet the requirements of Licensee, or that the operation of the
// Materials will be uninterrupted or error-free, or that defects
// in the Materials will be corrected. Furthermore, Xilinx does
// not warrant or make any representations regarding use, or the
// results of the use, of the Materials in terms of correctness,
// accuracy, reliability or otherwise.
//
// Xilinx products are not designed or intended to be fail-safe,
// or for use in any application requiring fail-safe performance,
// such as life-support or safety devices or systems, Class III
// medical devices, nuclear facilities, applications related to
// the deployment of airbags, or any other applications that could
// lead to death, personal injury or severe property or
// environmental damage (individually and collectively, "critical
// applications"). Customer assumes the sole risk and liability
// of any use of Xilinx products in critical applications,
// subject only to applicable laws and regulations governing
// limitations on product liability.
//
// Copyright 2006, 2007, 2008 Xilinx, Inc.
// All rights reserved.
//
// This disclaimer and copyright notice must be retained as part
// of this file at all times.
//*****************************************************************************
// ____ ____
// / /\/ /
// /___/ \ / Vendor: Xilinx
// \ \ \/ Version: 3.4
// \ \ Application: MIG
// / / Filename: ddr2_phy_dq_iob.v
// /___/ /\ Date Last Modified: $Date: 2009/11/03 04:43:17 $
// \ \ / \ Date Created: Wed Aug 16 2006
// \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
// This module places the data in the IOBs.
//Reference:
//Revision History:
// Rev 1.1 - Parameter HIGH_PERFORMANCE_MODE added. PK. 7/10/08
// Rev 1.2 - DIRT strings removed and modified the code. PK. 11/13/08
// Rev 1.3 - Parameter IODELAY_GRP added and constraint IODELAY_GROUP added
// on IODELAY primitive. PK. 11/27/08
//*****************************************************************************
`timescale 1ns/1ps
module ddr2_phy_dq_iob #
(
// Following parameters are for 72-bit RDIMM design (for ML561 Reference
// board design). Actual values may be different. Actual parameters values
// are passed from design top module mig_v3_4 module. Please refer to
// the mig_v3_4 module for actual values.
parameter HIGH_PERFORMANCE_MODE = "TRUE",
parameter IODELAY_GRP = "IODELAY_MIG",
parameter FPGA_SPEED_GRADE = 2
)
(
input clk0,
input clk90,
input clkdiv0,
input rst90,
input dlyinc,
input dlyce,
input dlyrst,
input [1:0] dq_oe_n,
input dqs,
input ce,
input rd_data_sel,
input wr_data_rise,
input wr_data_fall,
output rd_data_rise,
output rd_data_fall,
inout ddr_dq
);
wire dq_iddr_clk;
wire dq_idelay;
wire dq_in;
wire dq_oe_n_r;
wire dq_out;
wire stg2a_out_fall;
wire stg2a_out_rise;
(* XIL_PAR_DELAY = "0 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg2b_out_fall;
(* XIL_PAR_DELAY = "0 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg2b_out_rise;
wire stg3a_out_fall;
wire stg3a_out_rise;
wire stg3b_out_fall;
wire stg3b_out_rise;
//***************************************************************************
// Directed routing constraints for route between IDDR and stage 2 capture
// in fabric.
// Only 2 out of the 12 wire declarations will be used for any given
// instantiation of this module.
// Varies according:
// (1) I/O column (left, center, right) used
// (2) Which I/O in I/O pair (master, slave) used
// Nomenclature: _Xy, X = column (0 = left, 1 = center, 2 = right),
// y = master or slave
//***************************************************************************
// MODIFIED, RC, 06/13/08: Remove all references to DIRT, master/slave
(* XIL_PAR_DELAY = "515 ps", XIL_PAR_SKEW = "55 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_rise_sg3;
(* XIL_PAR_DELAY = "515 ps", XIL_PAR_SKEW = "55 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_fall_sg3;
(* XIL_PAR_DELAY = "575 ps", XIL_PAR_SKEW = "65 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_rise_sg2;
(* XIL_PAR_DELAY = "575 ps", XIL_PAR_SKEW = "65 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_fall_sg2;
(* XIL_PAR_DELAY = "650 ps", XIL_PAR_SKEW = "70 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_rise_sg1;
(* XIL_PAR_DELAY = "650 ps", XIL_PAR_SKEW = "70 ps", XIL_PAR_IP_NAME = "MIG", syn_keep = "1", keep = "TRUE" *)
wire stg1_out_fall_sg1;
//***************************************************************************
// Bidirectional I/O
//***************************************************************************
IOBUF u_iobuf_dq
(
.I (dq_out),
.T (dq_oe_n_r),
.IO (ddr_dq),
.O (dq_in)
);
//***************************************************************************
// Write (output) path
//***************************************************************************
// on a write, rising edge of DQS corresponds to rising edge of CLK180
// (aka falling edge of CLK0 -> rising edge DQS). We also know:
// 1. data must be driven 1/4 clk cycle before corresponding DQS edge
// 2. first rising DQS edge driven on falling edge of CLK0
// 3. rising data must be driven 1/4 cycle before falling edge of CLK0
// 4. therefore, rising data driven on rising edge of CLK
ODDR #
(
.SRTYPE("SYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_oddr_dq
(
.Q (dq_out),
.C (clk90),
.CE (1'b1),
.D1 (wr_data_rise),
.D2 (wr_data_fall),
.R (1'b0),
.S (1'b0)
);
// make sure output is tri-state during reset (DQ_OE_N_R = 1)
ODDR #
(
.SRTYPE("ASYNC"),
.DDR_CLK_EDGE("SAME_EDGE")
)
u_tri_state_dq
(
.Q (dq_oe_n_r),
.C (clk90),
.CE (1'b1),
.D1 (dq_oe_n[0]),
.D2 (dq_oe_n[1]),
.R (1'b0),
.S (rst90)
);
//***************************************************************************
// Read data capture scheme description:
// Data capture consists of 3 ranks of flops, and a MUX
// 1. Rank 1 ("Stage 1"): IDDR captures delayed DDR DQ from memory using
// delayed DQS.
// - Data is split into 2 SDR streams, one each for rise and fall data.
// - BUFIO (DQS) input inverted to IDDR. IDDR configured in SAME_EDGE
// mode. This means that: (1) Q1 = fall data, Q2 = rise data,
// (2) Both rise and fall data are output on falling edge of DQS -
// rather than rise output being output on one edge of DQS, and fall
// data on the other edge if the IDDR were configured in OPPOSITE_EDGE
// mode. This simplifies Stage 2 capture (only one core clock edge
// used, removing effects of duty-cycle-distortion), and saves one
// fabric flop in Rank 3.
// 2. Rank 2 ("Stage 2"): Fabric flops are used to capture output of first
// rank into FPGA clock (CLK) domain. Each rising/falling SDR stream
// from IDDR is feed into two flops, one clocked off rising and one off
// falling edge of CLK. One of these flops is chosen, with the choice
// being the one that reduces # of DQ/DQS taps necessary to align Stage
// 1 and Stage 2. Same edge is used to capture both rise and fall SDR
// streams.
// 3. Rank 3 ("Stage 3"): Removes half-cycle paths in CLK domain from
// output of Rank 2. This stage, like Stage 2, is clocked by CLK. Note
// that Stage 3 can be expanded to also support SERDES functionality
// 4. Output MUX: Selects whether Stage 1 output is aligned to rising or
// falling edge of CLK (i.e. specifically this selects whether IDDR
// rise/fall output is transfered to rising or falling edge of CLK).
// Implementation:
// 1. Rank 1 is implemented using an IDDR primitive
// 2. Rank 2 is implemented using:
// - An RPM to fix the location of the capture flops near the DQ I/O.
// The exact RPM used depends on which I/O column (left, center,
// right) the DQ I/O is placed at - this affects the optimal location
// of the slice flops (or does it - can we always choose the two
// columns to slices to the immediate right of the I/O to use, no
// matter what the column?). The origin of the RPM must be set in the
// UCF file using the RLOC_ORIGIN constraint (where the original is
// based on the DQ I/O location).
// - Directed Routing Constraints ("DIRT strings") to fix the routing
// to the rank 2 fabric flops. This is done to minimize: (1) total
// route delay (and therefore minimize voltage/temperature-related
// variations), and (2) minimize skew both within each rising and
// falling data net, as well as between the rising and falling nets.
// The exact DIRT string used depends on: (1) which I/O column the
// DQ I/O is placed, and (2) whether the DQ I/O is placed on the
// "Master" or "Slave" I/O of a diff pair (DQ is not differential, but
// the routing will be affected by which of each I/O pair is used)
// 3. Rank 3 is implemented using fabric flops. No LOC or DIRT contraints
// are used, tools are expected to place these and meet PERIOD timing
// without constraints (constraints may be necessary for "full" designs,
// in this case, user may need to add LOC constraints - if this is the
// case, there are no constraints - other than meeting PERIOD timing -
// for rank 3 flops.
//***************************************************************************
//***************************************************************************
// MIG 2.2: Define AREA_GROUP = "DDR_CAPTURE_FFS" contain all RPM flops in
// design. In UCF file, add constraint:
// AREA_GROUP "DDR_CAPTURE_FFS" GROUP = CLOSED;
// This is done to prevent MAP from packing unrelated logic into
// the slices used by the RPMs. Doing so may cause the DIRT strings
// that define the IDDR -> fabric flop routing to later become
// unroutable during PAR because the unrelated logic placed by MAP
// may use routing resources required by the DIRT strings. MAP
// does not currently take into account DIRT strings when placing
// logic
//***************************************************************************
// IDELAY to delay incoming data for synchronization purposes
(* IODELAY_GROUP = IODELAY_GRP *) IODELAY #
(
.DELAY_SRC ("I"),
.IDELAY_TYPE ("VARIABLE"),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.IDELAY_VALUE (0),
.ODELAY_VALUE (0)
)
u_idelay_dq
(
.DATAOUT (dq_idelay),
.C (clkdiv0),
.CE (dlyce),
.DATAIN (),
.IDATAIN (dq_in),
.INC (dlyinc),
.ODATAIN (),
.RST (dlyrst),
.T ()
);
//***************************************************************************
// Rank 1 capture: Use IDDR to generate two SDR outputs
//***************************************************************************
// invert clock to IDDR in order to use SAME_EDGE mode (otherwise, we "run
// out of clocks" because DQS is not continuous
assign dq_iddr_clk = ~dqs;
//***************************************************************************
// Rank 2 capture: Use fabric flops to capture Rank 1 output. Use RPM and
// DIRT strings here.
// BEL ("Basic Element of Logic") and relative location constraints for
// second stage capture. C
// Varies according:
// (1) I/O column (left, center, right) used
// (2) Which I/O in I/O pair (master, slave) used
//***************************************************************************
// MODIFIED, RC, 06/13/08: Remove all references to DIRT, master/slave
// Take out generate statements - collapses to a single case
generate
if (FPGA_SPEED_GRADE == 3) begin: gen_stg2_sg3
IDDR #
(
.DDR_CLK_EDGE ("SAME_EDGE")
)
u_iddr_dq
(
.Q1 (stg1_out_fall_sg3),
.Q2 (stg1_out_rise_sg3),
.C (dq_iddr_clk),
.CE (ce),
.D (dq_idelay),
.R (1'b0),
.S (1'b0)
);
//*********************************************************
// Slice #1 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 rising edge domain ("stg2a")
// 2. stg2 falling edge -> stg3 rising edge transfer
//*********************************************************
// Stage 2 capture
FDRSE u_ff_stg2a_fall
(
.Q (stg2a_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg3),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg2a_rise
(
.Q (stg2a_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg3),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
// Stage 3 falling -> rising edge translation
FDRSE u_ff_stg3b_fall
(
.Q (stg3b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg3b_rise
(
.Q (stg3b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
//*********************************************************
// Slice #2 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 falling edge domain ("stg2b")
//*********************************************************
FDRSE_1 u_ff_stg2b_fall
(
.Q (stg2b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg3),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE_1 u_ff_stg2b_rise
(
.Q (stg2b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg3),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end else if (FPGA_SPEED_GRADE == 2) begin: gen_stg2_sg2
IDDR #
(
.DDR_CLK_EDGE ("SAME_EDGE")
)
u_iddr_dq
(
.Q1 (stg1_out_fall_sg2),
.Q2 (stg1_out_rise_sg2),
.C (dq_iddr_clk),
.CE (ce),
.D (dq_idelay),
.R (1'b0),
.S (1'b0)
);
//*********************************************************
// Slice #1 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 rising edge domain ("stg2a")
// 2. stg2 falling edge -> stg3 rising edge transfer
//*********************************************************
// Stage 2 capture
FDRSE u_ff_stg2a_fall
(
.Q (stg2a_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg2),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg2a_rise
(
.Q (stg2a_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg2),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
// Stage 3 falling -> rising edge translation
FDRSE u_ff_stg3b_fall
(
.Q (stg3b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg3b_rise
(
.Q (stg3b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
//*********************************************************
// Slice #2 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 falling edge domain ("stg2b")
//*********************************************************
FDRSE_1 u_ff_stg2b_fall
(
.Q (stg2b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg2),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE_1 u_ff_stg2b_rise
(
.Q (stg2b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg2),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end else if (FPGA_SPEED_GRADE == 1) begin: gen_stg2_sg1
IDDR #
(
.DDR_CLK_EDGE ("SAME_EDGE")
)
u_iddr_dq
(
.Q1 (stg1_out_fall_sg1),
.Q2 (stg1_out_rise_sg1),
.C (dq_iddr_clk),
.CE (ce),
.D (dq_idelay),
.R (1'b0),
.S (1'b0)
);
//*********************************************************
// Slice #1 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 rising edge domain ("stg2a")
// 2. stg2 falling edge -> stg3 rising edge transfer
//*********************************************************
// Stage 2 capture
FDRSE u_ff_stg2a_fall
(
.Q (stg2a_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg1),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg2a_rise
(
.Q (stg2a_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg1),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
// Stage 3 falling -> rising edge translation
FDRSE u_ff_stg3b_fall
(
.Q (stg3b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_fall),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE u_ff_stg3b_rise
(
.Q (stg3b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg2b_out_rise),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
//*********************************************************
// Slice #2 (posedge CLK): Used for:
// 1. IDDR transfer to CLK0 falling edge domain ("stg2b")
//*********************************************************
FDRSE_1 u_ff_stg2b_fall
(
.Q (stg2b_out_fall),
.C (clk0),
.CE (1'b1),
.D (stg1_out_fall_sg1),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
FDRSE_1 u_ff_stg2b_rise
(
.Q (stg2b_out_rise),
.C (clk0),
.CE (1'b1),
.D (stg1_out_rise_sg1),
.R (1'b0),
.S (1'b0)
)/* synthesis syn_preserve = 1 */
/* synthesis syn_replicate = 0 */;
end
endgenerate
//***************************************************************************
// Second stage flops clocked by posedge CLK0 don't need another layer of
// registering
//***************************************************************************
assign stg3a_out_rise = stg2a_out_rise;
assign stg3a_out_fall = stg2a_out_fall;
//*******************************************************************
assign rd_data_rise = (rd_data_sel) ? stg3a_out_rise : stg3b_out_rise;
assign rd_data_fall = (rd_data_sel) ? stg3a_out_fall : stg3b_out_fall;
endmodule
|
// soc_design_niosII_core.v
// This file was auto-generated from altera_nios2_hw.tcl. If you edit it your changes
// will probably be lost.
//
// Generated using ACDS version 16.0 211
`timescale 1 ps / 1 ps
module soc_design_niosII_core (
input wire clk, // clk.clk
input wire reset_n, // reset.reset_n
input wire reset_req, // .reset_req
output wire [26:0] d_address, // data_master.address
output wire [3:0] d_byteenable, // .byteenable
output wire d_read, // .read
input wire [31:0] d_readdata, // .readdata
input wire d_waitrequest, // .waitrequest
output wire d_write, // .write
output wire [31:0] d_writedata, // .writedata
output wire [3:0] d_burstcount, // .burstcount
input wire d_readdatavalid, // .readdatavalid
output wire debug_mem_slave_debugaccess_to_roms, // .debugaccess
output wire [26:0] i_address, // instruction_master.address
output wire i_read, // .read
input wire [31:0] i_readdata, // .readdata
input wire i_waitrequest, // .waitrequest
output wire [3:0] i_burstcount, // .burstcount
input wire i_readdatavalid, // .readdatavalid
input wire [31:0] irq, // irq.irq
output wire debug_reset_request, // debug_reset_request.reset
input wire [8:0] debug_mem_slave_address, // debug_mem_slave.address
input wire [3:0] debug_mem_slave_byteenable, // .byteenable
input wire debug_mem_slave_debugaccess, // .debugaccess
input wire debug_mem_slave_read, // .read
output wire [31:0] debug_mem_slave_readdata, // .readdata
output wire debug_mem_slave_waitrequest, // .waitrequest
input wire debug_mem_slave_write, // .write
input wire [31:0] debug_mem_slave_writedata, // .writedata
output wire dummy_ci_port // custom_instruction_master.readra
);
soc_design_niosII_core_cpu cpu (
.clk (clk), // clk.clk
.reset_n (reset_n), // reset.reset_n
.reset_req (reset_req), // .reset_req
.d_address (d_address), // data_master.address
.d_byteenable (d_byteenable), // .byteenable
.d_read (d_read), // .read
.d_readdata (d_readdata), // .readdata
.d_waitrequest (d_waitrequest), // .waitrequest
.d_write (d_write), // .write
.d_writedata (d_writedata), // .writedata
.d_burstcount (d_burstcount), // .burstcount
.d_readdatavalid (d_readdatavalid), // .readdatavalid
.debug_mem_slave_debugaccess_to_roms (debug_mem_slave_debugaccess_to_roms), // .debugaccess
.i_address (i_address), // instruction_master.address
.i_read (i_read), // .read
.i_readdata (i_readdata), // .readdata
.i_waitrequest (i_waitrequest), // .waitrequest
.i_burstcount (i_burstcount), // .burstcount
.i_readdatavalid (i_readdatavalid), // .readdatavalid
.irq (irq), // irq.irq
.debug_reset_request (debug_reset_request), // debug_reset_request.reset
.debug_mem_slave_address (debug_mem_slave_address), // debug_mem_slave.address
.debug_mem_slave_byteenable (debug_mem_slave_byteenable), // .byteenable
.debug_mem_slave_debugaccess (debug_mem_slave_debugaccess), // .debugaccess
.debug_mem_slave_read (debug_mem_slave_read), // .read
.debug_mem_slave_readdata (debug_mem_slave_readdata), // .readdata
.debug_mem_slave_waitrequest (debug_mem_slave_waitrequest), // .waitrequest
.debug_mem_slave_write (debug_mem_slave_write), // .write
.debug_mem_slave_writedata (debug_mem_slave_writedata), // .writedata
.dummy_ci_port (dummy_ci_port) // custom_instruction_master.readra
);
endmodule
|
module main;
// Declare word1 as a VARIABLE
struct packed {
logic [7:0] high;
logic [7:0] low;
} word1;
// Declare word2, word3 as a NET
wire struct packed {
logic [7:0] high;
logic [7:0] low;
} word2, word3;
assign word2.high = word1.high;
assign word2.low = word1.low;
assign {word3.high, word3.low} = {word1.low, word1.high};
initial begin
word1 = 16'haa_55;
if (word1.high !== 8'haa || word1.low !== 8'h55) begin
$display("FAILED: word1 = %h, word1.high = %h, word1.low = %h",
word1, word1.high, word1.low);
$finish;
end
#1 /* Make sure word2 assign propagates */;
if (word2.high !== 8'haa || word2.low !== 8'h55) begin
$display("FAILED: word2 = %h, word2.high = %h, word2.low = %h",
word1, word2.high, word2.low);
$finish;
end
/* and also for word3 */
if (word3.low !== 8'haa || word3.high !== 8'h55) begin
$display("FAILED: word3 = %h, word3.high = %h, word3.low = %h (should be reverse)",
word1, word3.high, word3.low);
$finish;
end
$display("PASSED");
end
endmodule // main
|
////////////////////////////////////////////////////////////////////////////////////
//
// pGB, yet another FPGA fully functional and super fun GB classic clone!
// Copyright (C) 2015-2016 Diego Valverde ([email protected])
//
// This program is free software; you can redistribute it and/or
// modify it under the terms of the GNU General Public License
// as published by the Free Software Foundation; either version 2
// of the License, or (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
//
////////////////////////////////////////////////////////////////////////////////////
// Sound module, channel 1. Squate waves with variable timer, frequency, envelope functions and frequency sweep.
////////////////////////////////////////////////////////////////////////////////////
module osc2
(
input wire iClock,
input wire iReset,
output wire oOut131k,
output wire oOut262k
);
reg [4:0] rOscCounter; // log2(4194204/131072*2) = log2(16)= 4. Last bit corresponds to the output.
always @ (posedge iClock) begin
if (iReset) begin
rOscCounter <= 0;
end
else begin
rOscCounter <= rOscCounter+1;
end
end
assign oOut131k = rOscCounter[4];
assign oOut262k = rOscCounter[3];
endmodule |
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 04/14/2016 06:25:09 AM
// Design Name:
// Module Name: Exp_operation_m
// Project Name:
// Target Devices:
// Tool Versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Exp_Operation_m
#(parameter EW = 8) //Exponent Width
(
input wire clk, //system clock
input wire rst, //reset of the module
input wire load_a_i,//underflow
input wire load_b_i,//overflow
input wire load_c_i,//result
input wire [EW:0] Data_A_i,
input wire [EW:0] Data_B_i,
input wire Add_Subt_i,
///////////////////////////////////////////////////////////////////77
output wire [EW:0] Data_Result_o,
output wire Overflow_flag_o,
output wire Underflow_flag_o
);
///////////////////////////////////////////////
wire [EW:0] Data_S;
wire Overflow_A;
wire Overflow_flag_A;
wire underflow_exp_reg;
wire [EW:0] U_Limit;
/////////////////////////////Exponent calculation///
add_sub_carry_out #(.W(EW+1)) exp_add_subt_m(
.op_mode (Add_Subt_i),
.Data_A (Data_A_i),
.Data_B (Data_B_i),
.Data_S ({Overflow_A,Data_S})
);
RegisterMult #(.W(EW+1)) exp_result_m(
.clk (clk),
.rst (rst),
.load (load_c_i),
.D (Data_S),
.Q (Data_Result_o)
);
//Overflow/////////////////////////////////
RegisterMult#(.W(1)) Oflow_A_m (
.clk(clk),
.rst(rst),
.load(load_b_i),
.D(Overflow_A),
.Q(Overflow_flag_A)
);
assign Overflow_flag_o = Overflow_flag_A | Data_Result_o[EW];
//Underflow//////////////////////////////
Comparator_Less #(.W(EW+1)) Exp_unflow_Comparator_m (
.Data_A(Data_S),
.Data_B(U_Limit),
.less(underflow_exp_reg)
);
RegisterMult #(.W(1)) Underflow_m (
.clk(clk),
.rst(rst),
.load(load_a_i),
.D(underflow_exp_reg),
.Q(Underflow_flag_o)
);
generate
if (EW == 8)
assign U_Limit = 9'd127;
else
assign U_Limit = 12'd1023;
endgenerate
endmodule
|
// ==============================================================
// File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
// Version: 2014.4
// Copyright (C) 2014 Xilinx Inc. All rights reserved.
//
// ==============================================================
`timescale 1 ns / 1 ps
module image_filter_top (
s_axi_CONTROL_BUS_AWADDR,
s_axi_CONTROL_BUS_AWVALID,
s_axi_CONTROL_BUS_AWREADY,
s_axi_CONTROL_BUS_WDATA,
s_axi_CONTROL_BUS_WSTRB,
s_axi_CONTROL_BUS_WVALID,
s_axi_CONTROL_BUS_WREADY,
s_axi_CONTROL_BUS_BRESP,
s_axi_CONTROL_BUS_BVALID,
s_axi_CONTROL_BUS_BREADY,
s_axi_CONTROL_BUS_ARADDR,
s_axi_CONTROL_BUS_ARVALID,
s_axi_CONTROL_BUS_ARREADY,
s_axi_CONTROL_BUS_RDATA,
s_axi_CONTROL_BUS_RRESP,
s_axi_CONTROL_BUS_RVALID,
s_axi_CONTROL_BUS_RREADY,
interrupt,
aresetn,
aclk,
INPUT_STREAM_TDATA,
INPUT_STREAM_TKEEP,
INPUT_STREAM_TSTRB,
INPUT_STREAM_TUSER,
INPUT_STREAM_TLAST,
INPUT_STREAM_TID,
INPUT_STREAM_TDEST,
INPUT_STREAM_TVALID,
INPUT_STREAM_TREADY,
OUTPUT_STREAM_TDATA,
OUTPUT_STREAM_TKEEP,
OUTPUT_STREAM_TSTRB,
OUTPUT_STREAM_TUSER,
OUTPUT_STREAM_TLAST,
OUTPUT_STREAM_TID,
OUTPUT_STREAM_TDEST,
OUTPUT_STREAM_TVALID,
OUTPUT_STREAM_TREADY
);
parameter C_S_AXI_CONTROL_BUS_ADDR_WIDTH = 5;
parameter C_S_AXI_CONTROL_BUS_DATA_WIDTH = 32;
parameter RESET_ACTIVE_LOW = 1;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_AWADDR ;
input s_axi_CONTROL_BUS_AWVALID ;
output s_axi_CONTROL_BUS_AWREADY ;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_WDATA ;
input [C_S_AXI_CONTROL_BUS_DATA_WIDTH/8 - 1:0] s_axi_CONTROL_BUS_WSTRB ;
input s_axi_CONTROL_BUS_WVALID ;
output s_axi_CONTROL_BUS_WREADY ;
output [2 - 1:0] s_axi_CONTROL_BUS_BRESP ;
output s_axi_CONTROL_BUS_BVALID ;
input s_axi_CONTROL_BUS_BREADY ;
input [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_ARADDR ;
input s_axi_CONTROL_BUS_ARVALID ;
output s_axi_CONTROL_BUS_ARREADY ;
output [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_RDATA ;
output [2 - 1:0] s_axi_CONTROL_BUS_RRESP ;
output s_axi_CONTROL_BUS_RVALID ;
input s_axi_CONTROL_BUS_RREADY ;
output interrupt ;
input aresetn ;
input aclk ;
input [32 - 1:0] INPUT_STREAM_TDATA ;
input [4 - 1:0] INPUT_STREAM_TKEEP ;
input [4 - 1:0] INPUT_STREAM_TSTRB ;
input [1 - 1:0] INPUT_STREAM_TUSER ;
input [1 - 1:0] INPUT_STREAM_TLAST ;
input [1 - 1:0] INPUT_STREAM_TID ;
input [1 - 1:0] INPUT_STREAM_TDEST ;
input INPUT_STREAM_TVALID ;
output INPUT_STREAM_TREADY ;
output [32 - 1:0] OUTPUT_STREAM_TDATA ;
output [4 - 1:0] OUTPUT_STREAM_TKEEP ;
output [4 - 1:0] OUTPUT_STREAM_TSTRB ;
output [1 - 1:0] OUTPUT_STREAM_TUSER ;
output [1 - 1:0] OUTPUT_STREAM_TLAST ;
output [1 - 1:0] OUTPUT_STREAM_TID ;
output [1 - 1:0] OUTPUT_STREAM_TDEST ;
output OUTPUT_STREAM_TVALID ;
input OUTPUT_STREAM_TREADY ;
wire [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_AWADDR;
wire s_axi_CONTROL_BUS_AWVALID;
wire s_axi_CONTROL_BUS_AWREADY;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_WDATA;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH/8 - 1:0] s_axi_CONTROL_BUS_WSTRB;
wire s_axi_CONTROL_BUS_WVALID;
wire s_axi_CONTROL_BUS_WREADY;
wire [2 - 1:0] s_axi_CONTROL_BUS_BRESP;
wire s_axi_CONTROL_BUS_BVALID;
wire s_axi_CONTROL_BUS_BREADY;
wire [C_S_AXI_CONTROL_BUS_ADDR_WIDTH - 1:0] s_axi_CONTROL_BUS_ARADDR;
wire s_axi_CONTROL_BUS_ARVALID;
wire s_axi_CONTROL_BUS_ARREADY;
wire [C_S_AXI_CONTROL_BUS_DATA_WIDTH - 1:0] s_axi_CONTROL_BUS_RDATA;
wire [2 - 1:0] s_axi_CONTROL_BUS_RRESP;
wire s_axi_CONTROL_BUS_RVALID;
wire s_axi_CONTROL_BUS_RREADY;
wire interrupt;
wire aresetn;
wire [32 - 1:0] sig_image_filter_rows;
wire [32 - 1:0] sig_image_filter_cols;
wire sig_image_filter_ap_start;
wire sig_image_filter_ap_ready;
wire sig_image_filter_ap_done;
wire sig_image_filter_ap_idle;
wire sig_image_filter_ap_rst_n;
image_filter image_filter_U(
.rows(sig_image_filter_rows),
.cols(sig_image_filter_cols),
.ap_start(sig_image_filter_ap_start),
.ap_ready(sig_image_filter_ap_ready),
.ap_done(sig_image_filter_ap_done),
.ap_idle(sig_image_filter_ap_idle),
.ap_rst_n(sig_image_filter_ap_rst_n),
.ap_clk(aclk),
.INPUT_STREAM_TDATA(INPUT_STREAM_TDATA),
.INPUT_STREAM_TKEEP(INPUT_STREAM_TKEEP),
.INPUT_STREAM_TSTRB(INPUT_STREAM_TSTRB),
.INPUT_STREAM_TUSER(INPUT_STREAM_TUSER),
.INPUT_STREAM_TLAST(INPUT_STREAM_TLAST),
.INPUT_STREAM_TID(INPUT_STREAM_TID),
.INPUT_STREAM_TDEST(INPUT_STREAM_TDEST),
.INPUT_STREAM_TVALID(INPUT_STREAM_TVALID),
.INPUT_STREAM_TREADY(INPUT_STREAM_TREADY),
.OUTPUT_STREAM_TDATA(OUTPUT_STREAM_TDATA),
.OUTPUT_STREAM_TKEEP(OUTPUT_STREAM_TKEEP),
.OUTPUT_STREAM_TSTRB(OUTPUT_STREAM_TSTRB),
.OUTPUT_STREAM_TUSER(OUTPUT_STREAM_TUSER),
.OUTPUT_STREAM_TLAST(OUTPUT_STREAM_TLAST),
.OUTPUT_STREAM_TID(OUTPUT_STREAM_TID),
.OUTPUT_STREAM_TDEST(OUTPUT_STREAM_TDEST),
.OUTPUT_STREAM_TVALID(OUTPUT_STREAM_TVALID),
.OUTPUT_STREAM_TREADY(OUTPUT_STREAM_TREADY)
);
image_filter_CONTROL_BUS_if #(
.C_ADDR_WIDTH(C_S_AXI_CONTROL_BUS_ADDR_WIDTH),
.C_DATA_WIDTH(C_S_AXI_CONTROL_BUS_DATA_WIDTH))
image_filter_CONTROL_BUS_if_U(
.ACLK(aclk),
.ARESETN(aresetn),
.I_rows(sig_image_filter_rows),
.I_cols(sig_image_filter_cols),
.I_ap_start(sig_image_filter_ap_start),
.O_ap_ready(sig_image_filter_ap_ready),
.O_ap_done(sig_image_filter_ap_done),
.O_ap_idle(sig_image_filter_ap_idle),
.AWADDR(s_axi_CONTROL_BUS_AWADDR),
.AWVALID(s_axi_CONTROL_BUS_AWVALID),
.AWREADY(s_axi_CONTROL_BUS_AWREADY),
.WDATA(s_axi_CONTROL_BUS_WDATA),
.WSTRB(s_axi_CONTROL_BUS_WSTRB),
.WVALID(s_axi_CONTROL_BUS_WVALID),
.WREADY(s_axi_CONTROL_BUS_WREADY),
.BRESP(s_axi_CONTROL_BUS_BRESP),
.BVALID(s_axi_CONTROL_BUS_BVALID),
.BREADY(s_axi_CONTROL_BUS_BREADY),
.ARADDR(s_axi_CONTROL_BUS_ARADDR),
.ARVALID(s_axi_CONTROL_BUS_ARVALID),
.ARREADY(s_axi_CONTROL_BUS_ARREADY),
.RDATA(s_axi_CONTROL_BUS_RDATA),
.RRESP(s_axi_CONTROL_BUS_RRESP),
.RVALID(s_axi_CONTROL_BUS_RVALID),
.RREADY(s_axi_CONTROL_BUS_RREADY),
.interrupt(interrupt));
image_filter_ap_rst_n_if #(
.RESET_ACTIVE_LOW(RESET_ACTIVE_LOW))
ap_rst_n_if_U(
.dout(sig_image_filter_ap_rst_n),
.din(aresetn));
endmodule
|
// (C) 2001-2011 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
// altera message_off 10230
module sequencer_scc_sv_phase_decode
# (parameter
AVL_DATA_WIDTH = 32,
DLL_DELAY_CHAIN_LENGTH = 6
)
(
avl_writedata,
dqsi_phase,
dqs_phase_reset,
dqs_phase,
dq_phase_reset,
dq_phase,
dqse_phase_reset,
dqse_phase
);
input [AVL_DATA_WIDTH - 1:0] avl_writedata;
output [2:0] dqsi_phase;
output [6:0] dqs_phase_reset;
output [6:0] dqs_phase;
output [6:0] dq_phase_reset;
output [6:0] dq_phase;
output [5:0] dqse_phase_reset;
output [5:0] dqse_phase;
//USER phase decoding.
reg [2:0] dqsi_phase;
reg [6:0] dqs_phase_reset;
reg [6:0] dqs_phase;
reg [6:0] dq_phase_reset;
reg [6:0] dq_phase;
reg [5:0] dqse_phase_reset;
reg [5:0] dqse_phase;
//USER decode phases
always @ (*) begin
dqsi_phase = 0;
dqs_phase_reset = 0;
//dqs_phase = 0;
dq_phase_reset = 0;
//dq_phase = 0;
dqse_phase_reset = 0;
dqse_phase = 0;
//USER DQSin = 90, DQS = 180, DQ = 90, DQSE = 90
dqsi_phase = 3'b010;
dqse_phase = 6'b001000;
//USER DQS = 315, DQ = 225, DQSE = 225
dqs_phase = 7'b1110110;
dq_phase = 7'b0110100;
dqse_phase = 6'b000110;
case (avl_writedata[4:0])
5'b00000: //USER DQS = 180, DQ = 90, DQSE = 90
begin
dqs_phase = 7'b0010100;
dq_phase = 7'b1000100;
dqse_phase = 6'b000010;
end
5'b00001: //USER DQS = 225, DQ = 135, DQSE = 135
begin
dqs_phase = 7'b0110100;
dq_phase = 7'b1100100;
dqse_phase = 6'b000011;
end
5'b00010: //USER DQS = 270, DQ = 180, DQSE = 180
begin
dqs_phase = 7'b1010100;
dq_phase = 7'b0010100;
dqse_phase = 6'b000100;
end
5'b00011: //USER DQS = 315, DQ = 225, DQSE = 225
begin
dqs_phase = 7'b1110110;
dq_phase = 7'b0110100;
dqse_phase = 6'b000101;
end
5'b00100: //USER DQS = 360, DQ = 270, DQSE = 270
begin
dqs_phase = 7'b0000110;
dq_phase = 7'b1010100;
dqse_phase = 6'b000110;
end
5'b00101: //USER DQS = 405, DQ = 315, DQSE = 315
begin
dqs_phase = 7'b0100110;
dq_phase = 7'b1110110;
dqse_phase = 6'b000111;
end
5'b00110: //USER DQS = 450, DQ = 360, DQSE = 360
begin
dqs_phase = 7'b1000110;
dq_phase = 7'b0000110;
dqse_phase = 6'b000000;
end
5'b00111: //USER DQS = 495, DQ = 405, DQSE = 405
begin
dqs_phase = 7'b1100110;
dq_phase = 7'b0100110;
dqse_phase = 6'b000000;
end
5'b01000: //USER DQS = 540, DQ = 450
begin
dqs_phase = 7'b0010110;
dq_phase = 7'b1000110;
end
5'b01001: //USER DQS = 585, DQ = 495
begin
dqs_phase = 7'b0110110;
dq_phase = 7'b1100110;
end
5'b01010: //USER DQS = 630, DQ = 540
begin
dqs_phase = 7'b1010110;
dq_phase = 7'b0010110;
end
5'b01011: //USER DQS = 675, DQ = 585
begin
dqs_phase = 7'b1111000;
dq_phase = 7'b0110110;
end
5'b01100: //USER DQS = 720, DQ = 630
begin
dqs_phase = 7'b0001000;
dq_phase = 7'b1010110;
end
5'b01101: //USER DQS = 765, DQ = 675
begin
dqs_phase = 7'b0101000;
dq_phase = 7'b1111000;
end
5'b01110: //USER DQS = 810, DQ = 720
begin
dqs_phase = 7'b1001000;
dq_phase = 7'b0001000;
end
5'b01111: //USER DQS = 855, DQ = 765
begin
dqs_phase = 7'b1101000;
dq_phase = 7'b0101000;
end
5'b10000: //USER DQS = 900, DQ = 810
begin
dqs_phase = 7'b0011000;
dq_phase = 7'b1001000;
end
5'b10001: //USER DQS = 945, DQ = 855
begin
dqs_phase = 7'b0111000;
dq_phase = 7'b1101000;
end
5'b10010: //USER DQS = 990, DQ = 900
begin
dqs_phase = 7'b1011000;
dq_phase = 7'b0011000;
end
5'b10011: //USER DQS = 1035, DQ = 945
begin
dqs_phase = 7'b1111010;
dq_phase = 7'b0111000;
end
5'b10100: //USER DQS = 1080, DQ = 990
begin
dqs_phase = 7'b0001010;
dq_phase = 7'b1011000;
end
5'b10101: //USER DQS = 1125, DQ = 1035
begin
dqs_phase = 7'b0101010;
dq_phase = 7'b1111010;
end
5'b10110: //USER DQS = 1170, DQ = 1080
begin
dqs_phase = 7'b1001010;
dq_phase = 7'b0001010;
end
5'b10111: //USER DQS = 1215, DQ = 1125
begin
dqs_phase = 7'b1101010;
dq_phase = 7'b0101010;
end
5'b11000: //USER DQS = 1260, DQ = 1170
begin
dqs_phase = 7'b0011010;
dq_phase = 7'b1001010;
end
5'b11001: //USER DQS = 1305, DQ = 1215
begin
dqs_phase = 7'b0111010;
dq_phase = 7'b1101010;
end
5'b11010: //USER DQS = 1350, DQ = 1260
begin
dqs_phase = 7'b1011010;
dq_phase = 7'b0011010;
end
5'b11011: //USER DQS = 1395, DQ = 1305
begin
dqs_phase = 7'b1111010;
dq_phase = 7'b0111010;
end
default : begin end
endcase
end
endmodule
|
//wb_i2c.v
/////////////////////////////////////////////////////////////////////
//// ////
//// WISHBONE revB.2 compliant I2C Master controller Top-level ////
//// ////
//// ////
//// Author: Richard Herveille ////
//// [email protected] ////
//// www.asics.ws ////
//// ////
//// Downloaded from: http://www.opencores.org/projects/i2c/ ////
//// ////
/////////////////////////////////////////////////////////////////////
//// ////
//// Copyright (C) 2001 Richard Herveille ////
//// [email protected] ////
//// ////
//// This source file may be used and distributed without ////
//// restriction provided that this copyright statement is not ////
//// removed from the file and that any derivative work contains ////
//// the original copyright notice and the associated disclaimer.////
//// ////
//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
//// POSSIBILITY OF SUCH DAMAGE. ////
//// ////
/////////////////////////////////////////////////////////////////////
/*
Adapted from OpenCores I2C project
Author: [email protected]
*/
/*
Self Defining Bus (SDB)
Set the Vendor ID (Hexidecimal 64-bit Number)
SDB_VENDOR_ID:0x800000000000C594
Set the Device ID (Hexcidecimal 32-bit Number)
SDB_DEVICE_ID:0x00000000
Set the version of the Core XX.XXX.XXX Example: 01.000.000
SDB_CORE_VERSION:00.000.001
Set the Device Name: (19 UNICODE characters)
SDB_NAME:wb_i2c
Set the class of the device (16 bits) Set as 0
SDB_ABI_CLASS:0
Set the ABI Major Version: (8-bits)
SDB_ABI_VERSION_MAJOR:0x04
Set the ABI Minor Version (8-bits)
SDB_ABI_VERSION_MINOR:0x01
Set the Module URL (63 Unicode Characters)
SDB_MODULE_URL:http://www.example.com
Set the date of module YYYY/MM/DD
SDB_DATE:2015/01/07
Device is executable (True/False)
SDB_EXECUTABLE:True
Device is readable (True/False)
SDB_READABLE:True
Device is writeable (True/False)
SDB_WRITEABLE:True
Device Size: Number of Registers
SDB_SIZE:7
*/
`include "project_defines.v"
`include "timescale.v"
`define CLK_DIVIDE_100KHZ (`CLOCK_RATE/(5 * 100000) - 1)
`define CLK_DIVIDE_400KHZ (`CLOCK_RATE/(5 * 400000) - 1)
module wb_i2c (
input clk,
input rst,
//wishbone slave signals
input i_wbs_we,
input i_wbs_stb,
input i_wbs_cyc,
input [3:0] i_wbs_sel,
input [31:0] i_wbs_adr,
input [31:0] i_wbs_dat,
output reg [31:0] o_wbs_dat,
output reg o_wbs_ack,
output reg o_wbs_int,
inout scl,
inout sda
);
localparam ADDR_CONTROL = 32'h00000000;
localparam ADDR_STATUS = 32'h00000001;
localparam ADDR_CLOCK_RATE = 32'h00000002;
localparam ADDR_CLOCK_DIVIDER = 32'h00000003;
localparam ADDR_COMMAND = 32'h00000004;
localparam ADDR_TRANSMIT = 32'h00000005;
localparam ADDR_RECEIVE = 32'h00000006;
//Registers/Wires
reg [15:0] clock_divider;
reg [7:0] control;
reg [7:0] transmit;
wire [7:0] receive;
reg [7:0] command;
wire [7:0] status;
wire done;
//core enable signal
wire core_en;
wire ien;
//Control Register bits
wire start;
wire stop;
wire read;
wire write;
wire ack;
reg iack;
wire core_reset;
//Status Register
wire irxack;
reg rxack; //Received acknowledge from slave
reg tip; //Tranfer in progress
reg irq_flag; //interrupt pending flag
wire i2c_busy; //busy (start sigal detected)
wire i2c_al; //arbitration lost
reg al; //arbitration lost
//Assigns
//Command
assign start = command[0];
assign stop = command[1];
assign read = command[2];
assign write = command[3];
assign ack = command[4];
// Control
assign core_en = control[0];
assign ien = control[1];
assign set_100khz = control[2];
assign set_400khz = control[3];
assign core_reset = control[7];
// assign status register bits
assign status[7] = rxack;
assign status[6] = i2c_busy;
assign status[5] = al;
assign status[4:2] = 3'h0; // reserved
assign status[1] = tip;
assign status[0] = irq_flag;
assign scl = scl_oen ? 1'hZ : scl_out;
assign sda = sda_oen ? 1'hZ : sda_out;
i2c_master_byte_ctrl byte_controller (
.clk (clk ),
.rst (rst | core_reset ),
.nReset (1 ),
.ena (core_en ),
.clk_cnt (clock_divider ),
.start (start ),
.stop (stop ),
.read (read ),
.write (write ),
.ack_in (ack ),
.din (transmit ),
.cmd_ack (done ),
.ack_out (irxack ),
.dout (receive ),
.i2c_busy (i2c_busy ),
.i2c_al (i2c_al ),
.scl_i (scl ),
.scl_o (scl_out ),
.scl_oen (scl_oen ),
.sda_i (sda ),
.sda_o (sda_out ),
.sda_oen (sda_oen )
);
//blocks
always @ (posedge clk) begin
if (rst) begin
o_wbs_dat <= 32'h0;
o_wbs_ack <= 0;
o_wbs_int <= 0;
clock_divider <= `CLK_DIVIDE_100KHZ;
control <= 8'h01;
transmit <= 8'h00;
command <= 8'h00;
al <= 0;
rxack <= 0;
tip <= 0;
irq_flag <= 0;
iack <= 0;
end
else begin
iack <= 0;
//when the master acks our ack, then put our ack down
if (o_wbs_ack & ~ i_wbs_stb)begin
o_wbs_ack <= 0;
//clear IRQ ACK bit
command[0] <= 0;
end
if (i_wbs_stb & i_wbs_cyc) begin
//master is requesting something
o_wbs_int <= 0;
//acknowledge an interrupt
iack <= 1;
if (i_wbs_we) begin
//write request
case (i_wbs_adr)
ADDR_CONTROL: begin
control <= i_wbs_dat[7:0];
end
ADDR_CLOCK_DIVIDER: begin
clock_divider <= i_wbs_dat[15:0];
end
ADDR_COMMAND: begin
command <= i_wbs_dat[7:0];
end
ADDR_TRANSMIT: begin
transmit <= i_wbs_dat[7:0];
end
default: begin
end
endcase
end
else begin
//reset the interrupt when the user reads anything
//read request
case (i_wbs_adr)
ADDR_CONTROL: begin
o_wbs_dat <= {24'h000000, control};
end
ADDR_STATUS: begin
o_wbs_dat <= {24'h000000, status};
end
ADDR_CLOCK_RATE: begin
o_wbs_dat <= `CLOCK_RATE;
end
ADDR_CLOCK_DIVIDER: begin
o_wbs_dat <= {16'h0000, clock_divider};
end
ADDR_COMMAND: begin
o_wbs_dat <= {24'h000000, command};
end
ADDR_TRANSMIT: begin
o_wbs_dat <= {24'h000000, transmit};
end
ADDR_RECEIVE: begin
o_wbs_dat <= {24'h000000, receive};
end
default: begin
o_wbs_dat <= 32'h0000000;
end
endcase
end
o_wbs_ack <= 1;
end
//clear the reserved bits
command[7:5] <= 2'b00;
if (set_100khz) begin
clock_divider <= `CLK_DIVIDE_100KHZ;
//reset the control so they don't keep firing off
control[2] <= 0;
control[3] <= 0;
end
if (set_400khz) begin
//reset the control so they don't keep firing off
clock_divider <= `CLK_DIVIDE_400KHZ;
control[2] <= 0;
control[3] <= 0;
end
if (core_reset) begin
control[7] <= 0;
end
//control/status
al <= i2c_al | (al & ~start);
rxack <= irxack;
tip <= (read | write);
irq_flag <= (done | i2c_al | irq_flag) & ~iack; // interrupt request flag is always generated
if (irq_flag && ien) begin
//interrupt enable and irq_flag fired off
o_wbs_int <= 1;
end
//Handle Status/Control oneshots
if (done | i2c_al) begin
command[3:0] <= 4'h0;
end
end
end
endmodule
|
`timescale 1ns/1ps
`define INDEX(x,y) x*y +: y
module tb_register ;
localparam REGISTER_NUM_REGISTERS = 16 ;
localparam REGISTER_NUM_DATA_IN = 2 ;
localparam REGISTER_NUM_DATA_OUT = 4 ;
localparam REGISTER_NUM_SEL_BITS = $clog2(REGISTER_NUM_REGISTERS) ;
localparam REGISTER_WIDTH_DATA = 32 ;
localparam REGISTER_NUM_WRITE_TESTS = 128 ;
reg r_clk ;
reg [REGISTER_NUM_DATA_IN-1:0] r_we ;
reg [REGISTER_NUM_DATA_OUT-1:0] r_re ;
reg [REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS-1:0] r_data_in_sel ;
reg [REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS-1:0] r_data_out_sel ;
reg [REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA-1:0] r_data_in ;
wire [REGISTER_NUM_DATA_OUT*REGISTER_WIDTH_DATA-1:0] w_data_out ;
register dut (
.i_clk (r_clk),
.i_we (r_we),
.i_re (r_re),
.i_data_in_sel (r_data_in_sel),
.i_data_out_sel (r_data_out_sel),
.i_data_in (r_data_in),
.o_data_out (w_data_out)
) ;
initial begin
r_clk = 0 ;
r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
end
initial begin
$dumpfile ("tb_register.dump") ;
$dumpvars ;
end
initial begin
$display("\t|%10s |%4s |%4s |%13s |%18s |%4s |%14s |%34s |","time","clk","we","data_in_sel","data_in","re",
"data_out_sel","data_out") ;
$monitor("\t|%10t |%4h |%4h |%13h |%18h |%4h |%14h |%34h |",$time,r_clk,r_we,r_data_in_sel,r_data_in,r_re,
r_data_out_sel, w_data_out) ;
end
always begin
#50 r_clk = !r_clk ;
end
initial begin : Test_Cases
integer i ;
for (i=0; i<REGISTER_NUM_WRITE_TESTS; i=i+1) begin : Writing_Test
#20 r_we[$urandom%REGISTER_NUM_DATA_IN] = $random ;
r_data_in_sel[`INDEX($clog2(r_we),REGISTER_NUM_SEL_BITS)] = $random ;
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)] = $random ;
r_re = 1'b1 ;
r_data_out_sel[`INDEX(0,REGISTER_NUM_SEL_BITS)] = r_data_in_sel[`INDEX($clog2(r_we),
REGISTER_NUM_SEL_BITS)] ;
#150 if ((r_we != {REGISTER_NUM_DATA_IN{1'b0}}) && (w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)] !=
r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)])) begin
$display ("Write error at time %0t",$time) ;
$display ("Expected value: %0h, Actual value: %0h", r_data_in[`INDEX($clog2(r_we),REGISTER_WIDTH_DATA)],
w_data_out[`INDEX(0,REGISTER_WIDTH_DATA)]) ;
$stop ;
end
#30 r_we = {REGISTER_NUM_DATA_IN{1'b0}} ;
r_data_in_sel = {REGISTER_NUM_DATA_IN*REGISTER_NUM_SEL_BITS{1'b0}} ;
r_data_in = {REGISTER_NUM_DATA_IN*REGISTER_WIDTH_DATA{1'b0}} ;
r_re = {REGISTER_NUM_DATA_OUT{1'b0}} ;
r_data_out_sel = {REGISTER_NUM_DATA_OUT*REGISTER_NUM_SEL_BITS{1'b0}} ;
end
$stop ;
end
endmodule
|
module memtest00(clk, setA, setB, y);
input clk, setA, setB;
output y;
reg mem [1:0];
always @(posedge clk) begin
if (setA) mem[0] <= 0; // this is line 9
if (setB) mem[0] <= 1; // this is line 10
end
assign y = mem[0];
endmodule
// ----------------------------------------------------------
module memtest01(clk, wr_en, wr_addr, wr_value, rd_addr, rd_value);
input clk, wr_en;
input [3:0] wr_addr, rd_addr;
input [7:0] wr_value;
output reg [7:0] rd_value;
reg [7:0] data [15:0];
always @(posedge clk)
if (wr_en)
data[wr_addr] <= wr_value;
always @(posedge clk)
rd_value <= data[rd_addr];
endmodule
// ----------------------------------------------------------
module memtest02(clk, setA, setB, addr, bit, y1, y2, y3, y4);
input clk, setA, setB;
input [1:0] addr;
input [2:0] bit;
output reg y1, y2;
output y3, y4;
reg [7:0] mem1 [3:0];
(* mem2reg *)
reg [7:0] mem2 [3:0];
always @(posedge clk) begin
if (setA) begin
mem1[0] <= 10;
mem1[1] <= 20;
mem1[2] <= 30;
mem2[0] <= 17;
mem2[1] <= 27;
mem2[2] <= 37;
end
if (setB) begin
mem1[0] <= 1;
mem1[1] <= 2;
mem1[2] <= 3;
mem2[0] <= 71;
mem2[1] <= 72;
mem2[2] <= 73;
end
y1 <= mem1[addr][bit];
y2 <= mem2[addr][bit];
end
assign y3 = mem1[addr][bit];
assign y4 = mem2[addr][bit];
endmodule
// ----------------------------------------------------------
module memtest03(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output reg [3:0] rd_data;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_data <= memory[rd_addr];
end
endmodule
// ----------------------------------------------------------
module memtest04(clk, wr_addr, wr_data, wr_enable, rd_addr, rd_data);
input clk, wr_enable;
input [3:0] wr_addr, wr_data, rd_addr;
output [3:0] rd_data;
reg rd_addr_buf;
reg [3:0] memory [0:15];
always @(posedge clk) begin
if (wr_enable)
memory[wr_addr] <= wr_data;
rd_addr_buf <= rd_addr;
end
assign rd_data = memory[rd_addr_buf];
endmodule
// ----------------------------------------------------------
module memtest05(clk, addr, wdata, rdata, wen);
input clk;
input [1:0] addr;
input [7:0] wdata;
output reg [7:0] rdata;
input [3:0] wen;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
for (i = 0; i < 4; i = i+1)
if (wen[i]) mem[addr][i*2 +: 2] <= wdata[i*2 +: 2];
rdata <= mem[addr];
end
endmodule
// ----------------------------------------------------------
module memtest06_sync(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule
module memtest06_async(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
(* gentb_constant=0 *) wire rst;
reg [7:0] test [0:7];
integer i;
always @(posedge clk or posedge rst) begin
if (rst) begin
for (i=0; i<8; i=i+1)
test[i] <= 0;
end else begin
test[0][2] <= din[1];
test[0][5] <= test[0][2];
test[idx][3] <= din[idx];
test[idx][6] <= test[idx][2];
test[idx][idx] <= !test[idx][idx];
end
end
assign dout = test[idx];
endmodule
// ----------------------------------------------------------
module memtest07(clk, addr, woffset, wdata, rdata);
input clk;
input [1:0] addr;
input [3:0] wdata;
input [1:0] woffset;
output reg [7:0] rdata;
reg [7:0] mem [0:3];
integer i;
always @(posedge clk) begin
mem[addr][woffset +: 4] <= wdata;
rdata <= mem[addr];
end
endmodule
// ----------------------------------------------------------
module memtest08(input clk, input [3:0] a, b, c, output reg [3:0] y);
reg [3:0] mem [0:15] [0:15];
always @(posedge clk) begin
y <= mem[a][b];
mem[a][b] <= c;
end
endmodule
// ----------------------------------------------------------
module memtest09 (
input clk,
input [3:0] a_addr, a_din, b_addr, b_din,
input a_wen, b_wen,
output reg [3:0] a_dout, b_dout
);
reg [3:0] memory [10:35];
always @(posedge clk) begin
if (a_wen)
memory[10 + a_addr] <= a_din;
a_dout <= memory[10 + a_addr];
end
always @(posedge clk) begin
if (b_wen && (10 + a_addr != 20 + b_addr || !a_wen))
memory[20 + b_addr] <= b_din;
b_dout <= memory[20 + b_addr];
end
endmodule
// ----------------------------------------------------------
module memtest10(input clk, input [5:0] din, output [5:0] dout);
reg [5:0] queue [0:3];
integer i;
always @(posedge clk) begin
queue[0] <= din;
for (i = 1; i < 4; i=i+1) begin
queue[i] <= queue[i-1];
end
end
assign dout = queue[3];
endmodule
// ----------------------------------------------------------
module memtest11(clk, wen, waddr, raddr, wdata, rdata);
input clk, wen;
input [1:0] waddr, raddr;
input [7:0] wdata;
output [7:0] rdata;
reg [7:0] mem [3:0];
assign rdata = mem[raddr];
always @(posedge clk) begin
if (wen)
mem[waddr] <= wdata;
else
mem[waddr] <= mem[waddr];
end
endmodule
// ----------------------------------------------------------
module memtest12 (
input clk,
input [1:0] adr,
input [1:0] din,
output reg [1:0] q
);
reg [1:0] ram [3:0];
always@(posedge clk)
{ram[adr], q} <= {din, ram[adr]};
endmodule
// ----------------------------------------------------------
module memtest13 (
input clk, rst,
input [1:0] a1, a2, a3, a4, a5, a6,
input [3:0] off1, off2,
input [31:5] din1,
input [3:0] din2, din3,
output reg [3:0] dout1, dout2,
output reg [31:5] dout3
);
reg [31:5] mem [0:3];
always @(posedge clk) begin
if (rst) begin
mem[0] <= 0;
mem[1] <= 0;
mem[2] <= 0;
mem[3] <= 0;
end else begin
mem[a1] <= din1;
mem[a2][14:11] <= din2;
mem[a3][5 + off1 +: 4] <= din3;
dout1 <= mem[a4][12:9];
dout2 <= mem[a5][5 + off2 +: 4];
dout3 <= mem[a6];
end
end
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__O21BA_M_V
`define SKY130_FD_SC_LP__O21BA_M_V
/**
* o21ba: 2-input OR into first input of 2-input AND,
* 2nd input inverted.
*
* X = ((A1 | A2) & !B1_N)
*
* Verilog wrapper for o21ba with size minimum.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__o21ba.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_m (
X ,
A1 ,
A2 ,
B1_N,
VPWR,
VGND,
VPB ,
VNB
);
output X ;
input A1 ;
input A2 ;
input B1_N;
input VPWR;
input VGND;
input VPB ;
input VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__o21ba_m (
X ,
A1 ,
A2 ,
B1_N
);
output X ;
input A1 ;
input A2 ;
input B1_N;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__o21ba base (
.X(X),
.A1(A1),
.A2(A2),
.B1_N(B1_N)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__O21BA_M_V
|
module premuat_8(
enable,
inverse,
i_0,
i_1,
i_2,
i_3,
i_4,
i_5,
i_6,
i_7,
o_0,
o_1,
o_2,
o_3,
o_4,
o_5,
o_6,
o_7
);
// ********************************************
//
// INPUT / OUTPUT DECLARATION
//
// ********************************************
input enable;
input inverse;
input signed [27:0] i_0;
input signed [27:0] i_1;
input signed [27:0] i_2;
input signed [27:0] i_3;
input signed [27:0] i_4;
input signed [27:0] i_5;
input signed [27:0] i_6;
input signed [27:0] i_7;
output signed [27:0] o_0;
output signed [27:0] o_1;
output signed [27:0] o_2;
output signed [27:0] o_3;
output signed [27:0] o_4;
output signed [27:0] o_5;
output signed [27:0] o_6;
output signed [27:0] o_7;
// ********************************************
//
// REG DECLARATION
//
// ********************************************
reg signed [27:0] o1;
reg signed [27:0] o2;
reg signed [27:0] o3;
reg signed [27:0] o4;
reg signed [27:0] o5;
reg signed [27:0] o6;
// ********************************************
//
// Combinational Logic
//
// ********************************************
always@(*)
if(inverse)
begin
o1=i_2;
o2=i_4;
o3=i_6;
o4=i_1;
o5=i_3;
o6=i_5;
end
else
begin
o1=i_4;
o2=i_1;
o3=i_5;
o4=i_2;
o5=i_6;
o6=i_3;
end
assign o_0=i_0;
assign o_1=enable?o1:i_1;
assign o_2=enable?o2:i_2;
assign o_3=enable?o3:i_3;
assign o_4=enable?o4:i_4;
assign o_5=enable?o5:i_5;
assign o_6=enable?o6:i_6;
assign o_7=i_7;
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*******************************************************************************
* This file is owned and controlled by Xilinx and must be used solely *
* for design, simulation, implementation and creation of design files *
* limited to Xilinx devices or technologies. Use with non-Xilinx *
* devices or technologies is expressly prohibited and immediately *
* terminates your license. *
* *
* XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" SOLELY *
* FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY *
* PROVIDING THIS DESIGN, CODE, OR INFORMATION AS ONE POSSIBLE *
* IMPLEMENTATION OF THIS FEATURE, APPLICATION OR STANDARD, XILINX IS *
* MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY *
* CLAIMS OF INFRINGEMENT, AND YOU ARE RESPONSIBLE FOR OBTAINING ANY *
* RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY *
* DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE *
* IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR *
* REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF *
* INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A *
* PARTICULAR PURPOSE. *
* *
* Xilinx products are not intended for use in life support appliances, *
* devices, or systems. Use in such applications are expressly *
* prohibited. *
* *
* (c) Copyright 1995-2014 Xilinx, Inc. *
* All rights reserved. *
*******************************************************************************/
// You must compile the wrapper file RD_FLASH_POST_FIFO.v when simulating
// the core, RD_FLASH_POST_FIFO. When compiling the wrapper file, be sure to
// reference the XilinxCoreLib Verilog simulation library. For detailed
// instructions, please refer to the "CORE Generator Help".
// The synthesis directives "translate_off/translate_on" specified below are
// supported by Xilinx, Mentor Graphics and Synplicity synthesis
// tools. Ensure they are correct for your synthesis tool(s).
`timescale 1ns/1ps
module RD_FLASH_POST_FIFO(
rst,
wr_clk,
rd_clk,
din,
wr_en,
rd_en,
dout,
full,
empty,
valid
);
input rst;
input wr_clk;
input rd_clk;
input [63 : 0] din;
input wr_en;
input rd_en;
output [255 : 0] dout;
output full;
output empty;
output valid;
// synthesis translate_off
FIFO_GENERATOR_V8_4 #(
.C_ADD_NGC_CONSTRAINT(0),
.C_APPLICATION_TYPE_AXIS(0),
.C_APPLICATION_TYPE_RACH(0),
.C_APPLICATION_TYPE_RDCH(0),
.C_APPLICATION_TYPE_WACH(0),
.C_APPLICATION_TYPE_WDCH(0),
.C_APPLICATION_TYPE_WRCH(0),
.C_AXI_ADDR_WIDTH(32),
.C_AXI_ARUSER_WIDTH(1),
.C_AXI_AWUSER_WIDTH(1),
.C_AXI_BUSER_WIDTH(1),
.C_AXI_DATA_WIDTH(64),
.C_AXI_ID_WIDTH(4),
.C_AXI_RUSER_WIDTH(1),
.C_AXI_TYPE(0),
.C_AXI_WUSER_WIDTH(1),
.C_AXIS_TDATA_WIDTH(64),
.C_AXIS_TDEST_WIDTH(4),
.C_AXIS_TID_WIDTH(8),
.C_AXIS_TKEEP_WIDTH(4),
.C_AXIS_TSTRB_WIDTH(4),
.C_AXIS_TUSER_WIDTH(4),
.C_AXIS_TYPE(0),
.C_COMMON_CLOCK(0),
.C_COUNT_TYPE(0),
.C_DATA_COUNT_WIDTH(10),
.C_DEFAULT_VALUE("BlankString"),
.C_DIN_WIDTH(64),
.C_DIN_WIDTH_AXIS(1),
.C_DIN_WIDTH_RACH(32),
.C_DIN_WIDTH_RDCH(64),
.C_DIN_WIDTH_WACH(32),
.C_DIN_WIDTH_WDCH(64),
.C_DIN_WIDTH_WRCH(2),
.C_DOUT_RST_VAL("0"),
.C_DOUT_WIDTH(256),
.C_ENABLE_RLOCS(0),
.C_ENABLE_RST_SYNC(1),
.C_ERROR_INJECTION_TYPE(0),
.C_ERROR_INJECTION_TYPE_AXIS(0),
.C_ERROR_INJECTION_TYPE_RACH(0),
.C_ERROR_INJECTION_TYPE_RDCH(0),
.C_ERROR_INJECTION_TYPE_WACH(0),
.C_ERROR_INJECTION_TYPE_WDCH(0),
.C_ERROR_INJECTION_TYPE_WRCH(0),
.C_FAMILY("virtex6"),
.C_FULL_FLAGS_RST_VAL(1),
.C_HAS_ALMOST_EMPTY(0),
.C_HAS_ALMOST_FULL(0),
.C_HAS_AXI_ARUSER(0),
.C_HAS_AXI_AWUSER(0),
.C_HAS_AXI_BUSER(0),
.C_HAS_AXI_RD_CHANNEL(0),
.C_HAS_AXI_RUSER(0),
.C_HAS_AXI_WR_CHANNEL(0),
.C_HAS_AXI_WUSER(0),
.C_HAS_AXIS_TDATA(0),
.C_HAS_AXIS_TDEST(0),
.C_HAS_AXIS_TID(0),
.C_HAS_AXIS_TKEEP(0),
.C_HAS_AXIS_TLAST(0),
.C_HAS_AXIS_TREADY(1),
.C_HAS_AXIS_TSTRB(0),
.C_HAS_AXIS_TUSER(0),
.C_HAS_BACKUP(0),
.C_HAS_DATA_COUNT(0),
.C_HAS_DATA_COUNTS_AXIS(0),
.C_HAS_DATA_COUNTS_RACH(0),
.C_HAS_DATA_COUNTS_RDCH(0),
.C_HAS_DATA_COUNTS_WACH(0),
.C_HAS_DATA_COUNTS_WDCH(0),
.C_HAS_DATA_COUNTS_WRCH(0),
.C_HAS_INT_CLK(0),
.C_HAS_MASTER_CE(0),
.C_HAS_MEMINIT_FILE(0),
.C_HAS_OVERFLOW(0),
.C_HAS_PROG_FLAGS_AXIS(0),
.C_HAS_PROG_FLAGS_RACH(0),
.C_HAS_PROG_FLAGS_RDCH(0),
.C_HAS_PROG_FLAGS_WACH(0),
.C_HAS_PROG_FLAGS_WDCH(0),
.C_HAS_PROG_FLAGS_WRCH(0),
.C_HAS_RD_DATA_COUNT(0),
.C_HAS_RD_RST(0),
.C_HAS_RST(1),
.C_HAS_SLAVE_CE(0),
.C_HAS_SRST(0),
.C_HAS_UNDERFLOW(0),
.C_HAS_VALID(1),
.C_HAS_WR_ACK(0),
.C_HAS_WR_DATA_COUNT(0),
.C_HAS_WR_RST(0),
.C_IMPLEMENTATION_TYPE(2),
.C_IMPLEMENTATION_TYPE_AXIS(1),
.C_IMPLEMENTATION_TYPE_RACH(1),
.C_IMPLEMENTATION_TYPE_RDCH(1),
.C_IMPLEMENTATION_TYPE_WACH(1),
.C_IMPLEMENTATION_TYPE_WDCH(1),
.C_IMPLEMENTATION_TYPE_WRCH(1),
.C_INIT_WR_PNTR_VAL(0),
.C_INTERFACE_TYPE(0),
.C_MEMORY_TYPE(1),
.C_MIF_FILE_NAME("BlankString"),
.C_MSGON_VAL(1),
.C_OPTIMIZATION_MODE(0),
.C_OVERFLOW_LOW(0),
.C_PRELOAD_LATENCY(0),
.C_PRELOAD_REGS(1),
.C_PRIM_FIFO_TYPE("1kx36"),
.C_PROG_EMPTY_THRESH_ASSERT_VAL(4),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH(1022),
.C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH(1022),
.C_PROG_EMPTY_THRESH_NEGATE_VAL(5),
.C_PROG_EMPTY_TYPE(0),
.C_PROG_EMPTY_TYPE_AXIS(5),
.C_PROG_EMPTY_TYPE_RACH(5),
.C_PROG_EMPTY_TYPE_RDCH(5),
.C_PROG_EMPTY_TYPE_WACH(5),
.C_PROG_EMPTY_TYPE_WDCH(5),
.C_PROG_EMPTY_TYPE_WRCH(5),
.C_PROG_FULL_THRESH_ASSERT_VAL(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_AXIS(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_RDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WACH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WDCH(1023),
.C_PROG_FULL_THRESH_ASSERT_VAL_WRCH(1023),
.C_PROG_FULL_THRESH_NEGATE_VAL(1022),
.C_PROG_FULL_TYPE(0),
.C_PROG_FULL_TYPE_AXIS(5),
.C_PROG_FULL_TYPE_RACH(5),
.C_PROG_FULL_TYPE_RDCH(5),
.C_PROG_FULL_TYPE_WACH(5),
.C_PROG_FULL_TYPE_WDCH(5),
.C_PROG_FULL_TYPE_WRCH(5),
.C_RACH_TYPE(0),
.C_RD_DATA_COUNT_WIDTH(8),
.C_RD_DEPTH(256),
.C_RD_FREQ(1),
.C_RD_PNTR_WIDTH(8),
.C_RDCH_TYPE(0),
.C_REG_SLICE_MODE_AXIS(0),
.C_REG_SLICE_MODE_RACH(0),
.C_REG_SLICE_MODE_RDCH(0),
.C_REG_SLICE_MODE_WACH(0),
.C_REG_SLICE_MODE_WDCH(0),
.C_REG_SLICE_MODE_WRCH(0),
.C_SYNCHRONIZER_STAGE(2),
.C_UNDERFLOW_LOW(0),
.C_USE_COMMON_OVERFLOW(0),
.C_USE_COMMON_UNDERFLOW(0),
.C_USE_DEFAULT_SETTINGS(0),
.C_USE_DOUT_RST(1),
.C_USE_ECC(0),
.C_USE_ECC_AXIS(0),
.C_USE_ECC_RACH(0),
.C_USE_ECC_RDCH(0),
.C_USE_ECC_WACH(0),
.C_USE_ECC_WDCH(0),
.C_USE_ECC_WRCH(0),
.C_USE_EMBEDDED_REG(0),
.C_USE_FIFO16_FLAGS(0),
.C_USE_FWFT_DATA_COUNT(0),
.C_VALID_LOW(0),
.C_WACH_TYPE(0),
.C_WDCH_TYPE(0),
.C_WR_ACK_LOW(0),
.C_WR_DATA_COUNT_WIDTH(10),
.C_WR_DEPTH(1024),
.C_WR_DEPTH_AXIS(1024),
.C_WR_DEPTH_RACH(16),
.C_WR_DEPTH_RDCH(1024),
.C_WR_DEPTH_WACH(16),
.C_WR_DEPTH_WDCH(1024),
.C_WR_DEPTH_WRCH(16),
.C_WR_FREQ(1),
.C_WR_PNTR_WIDTH(10),
.C_WR_PNTR_WIDTH_AXIS(10),
.C_WR_PNTR_WIDTH_RACH(4),
.C_WR_PNTR_WIDTH_RDCH(10),
.C_WR_PNTR_WIDTH_WACH(4),
.C_WR_PNTR_WIDTH_WDCH(10),
.C_WR_PNTR_WIDTH_WRCH(4),
.C_WR_RESPONSE_LATENCY(1),
.C_WRCH_TYPE(0)
)
inst (
.RST(rst),
.WR_CLK(wr_clk),
.RD_CLK(rd_clk),
.DIN(din),
.WR_EN(wr_en),
.RD_EN(rd_en),
.DOUT(dout),
.FULL(full),
.EMPTY(empty),
.VALID(valid),
.BACKUP(),
.BACKUP_MARKER(),
.CLK(),
.SRST(),
.WR_RST(),
.RD_RST(),
.PROG_EMPTY_THRESH(),
.PROG_EMPTY_THRESH_ASSERT(),
.PROG_EMPTY_THRESH_NEGATE(),
.PROG_FULL_THRESH(),
.PROG_FULL_THRESH_ASSERT(),
.PROG_FULL_THRESH_NEGATE(),
.INT_CLK(),
.INJECTDBITERR(),
.INJECTSBITERR(),
.ALMOST_FULL(),
.WR_ACK(),
.OVERFLOW(),
.ALMOST_EMPTY(),
.UNDERFLOW(),
.DATA_COUNT(),
.RD_DATA_COUNT(),
.WR_DATA_COUNT(),
.PROG_FULL(),
.PROG_EMPTY(),
.SBITERR(),
.DBITERR(),
.M_ACLK(),
.S_ACLK(),
.S_ARESETN(),
.M_ACLK_EN(),
.S_ACLK_EN(),
.S_AXI_AWID(),
.S_AXI_AWADDR(),
.S_AXI_AWLEN(),
.S_AXI_AWSIZE(),
.S_AXI_AWBURST(),
.S_AXI_AWLOCK(),
.S_AXI_AWCACHE(),
.S_AXI_AWPROT(),
.S_AXI_AWQOS(),
.S_AXI_AWREGION(),
.S_AXI_AWUSER(),
.S_AXI_AWVALID(),
.S_AXI_AWREADY(),
.S_AXI_WID(),
.S_AXI_WDATA(),
.S_AXI_WSTRB(),
.S_AXI_WLAST(),
.S_AXI_WUSER(),
.S_AXI_WVALID(),
.S_AXI_WREADY(),
.S_AXI_BID(),
.S_AXI_BRESP(),
.S_AXI_BUSER(),
.S_AXI_BVALID(),
.S_AXI_BREADY(),
.M_AXI_AWID(),
.M_AXI_AWADDR(),
.M_AXI_AWLEN(),
.M_AXI_AWSIZE(),
.M_AXI_AWBURST(),
.M_AXI_AWLOCK(),
.M_AXI_AWCACHE(),
.M_AXI_AWPROT(),
.M_AXI_AWQOS(),
.M_AXI_AWREGION(),
.M_AXI_AWUSER(),
.M_AXI_AWVALID(),
.M_AXI_AWREADY(),
.M_AXI_WID(),
.M_AXI_WDATA(),
.M_AXI_WSTRB(),
.M_AXI_WLAST(),
.M_AXI_WUSER(),
.M_AXI_WVALID(),
.M_AXI_WREADY(),
.M_AXI_BID(),
.M_AXI_BRESP(),
.M_AXI_BUSER(),
.M_AXI_BVALID(),
.M_AXI_BREADY(),
.S_AXI_ARID(),
.S_AXI_ARADDR(),
.S_AXI_ARLEN(),
.S_AXI_ARSIZE(),
.S_AXI_ARBURST(),
.S_AXI_ARLOCK(),
.S_AXI_ARCACHE(),
.S_AXI_ARPROT(),
.S_AXI_ARQOS(),
.S_AXI_ARREGION(),
.S_AXI_ARUSER(),
.S_AXI_ARVALID(),
.S_AXI_ARREADY(),
.S_AXI_RID(),
.S_AXI_RDATA(),
.S_AXI_RRESP(),
.S_AXI_RLAST(),
.S_AXI_RUSER(),
.S_AXI_RVALID(),
.S_AXI_RREADY(),
.M_AXI_ARID(),
.M_AXI_ARADDR(),
.M_AXI_ARLEN(),
.M_AXI_ARSIZE(),
.M_AXI_ARBURST(),
.M_AXI_ARLOCK(),
.M_AXI_ARCACHE(),
.M_AXI_ARPROT(),
.M_AXI_ARQOS(),
.M_AXI_ARREGION(),
.M_AXI_ARUSER(),
.M_AXI_ARVALID(),
.M_AXI_ARREADY(),
.M_AXI_RID(),
.M_AXI_RDATA(),
.M_AXI_RRESP(),
.M_AXI_RLAST(),
.M_AXI_RUSER(),
.M_AXI_RVALID(),
.M_AXI_RREADY(),
.S_AXIS_TVALID(),
.S_AXIS_TREADY(),
.S_AXIS_TDATA(),
.S_AXIS_TSTRB(),
.S_AXIS_TKEEP(),
.S_AXIS_TLAST(),
.S_AXIS_TID(),
.S_AXIS_TDEST(),
.S_AXIS_TUSER(),
.M_AXIS_TVALID(),
.M_AXIS_TREADY(),
.M_AXIS_TDATA(),
.M_AXIS_TSTRB(),
.M_AXIS_TKEEP(),
.M_AXIS_TLAST(),
.M_AXIS_TID(),
.M_AXIS_TDEST(),
.M_AXIS_TUSER(),
.AXI_AW_INJECTSBITERR(),
.AXI_AW_INJECTDBITERR(),
.AXI_AW_PROG_FULL_THRESH(),
.AXI_AW_PROG_EMPTY_THRESH(),
.AXI_AW_DATA_COUNT(),
.AXI_AW_WR_DATA_COUNT(),
.AXI_AW_RD_DATA_COUNT(),
.AXI_AW_SBITERR(),
.AXI_AW_DBITERR(),
.AXI_AW_OVERFLOW(),
.AXI_AW_UNDERFLOW(),
.AXI_W_INJECTSBITERR(),
.AXI_W_INJECTDBITERR(),
.AXI_W_PROG_FULL_THRESH(),
.AXI_W_PROG_EMPTY_THRESH(),
.AXI_W_DATA_COUNT(),
.AXI_W_WR_DATA_COUNT(),
.AXI_W_RD_DATA_COUNT(),
.AXI_W_SBITERR(),
.AXI_W_DBITERR(),
.AXI_W_OVERFLOW(),
.AXI_W_UNDERFLOW(),
.AXI_B_INJECTSBITERR(),
.AXI_B_INJECTDBITERR(),
.AXI_B_PROG_FULL_THRESH(),
.AXI_B_PROG_EMPTY_THRESH(),
.AXI_B_DATA_COUNT(),
.AXI_B_WR_DATA_COUNT(),
.AXI_B_RD_DATA_COUNT(),
.AXI_B_SBITERR(),
.AXI_B_DBITERR(),
.AXI_B_OVERFLOW(),
.AXI_B_UNDERFLOW(),
.AXI_AR_INJECTSBITERR(),
.AXI_AR_INJECTDBITERR(),
.AXI_AR_PROG_FULL_THRESH(),
.AXI_AR_PROG_EMPTY_THRESH(),
.AXI_AR_DATA_COUNT(),
.AXI_AR_WR_DATA_COUNT(),
.AXI_AR_RD_DATA_COUNT(),
.AXI_AR_SBITERR(),
.AXI_AR_DBITERR(),
.AXI_AR_OVERFLOW(),
.AXI_AR_UNDERFLOW(),
.AXI_R_INJECTSBITERR(),
.AXI_R_INJECTDBITERR(),
.AXI_R_PROG_FULL_THRESH(),
.AXI_R_PROG_EMPTY_THRESH(),
.AXI_R_DATA_COUNT(),
.AXI_R_WR_DATA_COUNT(),
.AXI_R_RD_DATA_COUNT(),
.AXI_R_SBITERR(),
.AXI_R_DBITERR(),
.AXI_R_OVERFLOW(),
.AXI_R_UNDERFLOW(),
.AXIS_INJECTSBITERR(),
.AXIS_INJECTDBITERR(),
.AXIS_PROG_FULL_THRESH(),
.AXIS_PROG_EMPTY_THRESH(),
.AXIS_DATA_COUNT(),
.AXIS_WR_DATA_COUNT(),
.AXIS_RD_DATA_COUNT(),
.AXIS_SBITERR(),
.AXIS_DBITERR(),
.AXIS_OVERFLOW(),
.AXIS_UNDERFLOW()
);
// synthesis translate_on
endmodule
|
// DESCRIPTION: Verilator: Verilog Test module
// This file ONLY is placed under the Creative Commons Public Domain, for
// any use, without warranty, 2008 by Wilson Snyder.
// SPDX-License-Identifier: CC0-1.0
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
integer cyc = 0;
integer v;
reg i;
/*AUTOWIRE*/
// Beginning of automatic wires (for undeclared instantiated-module outputs)
wire oa; // From a of a.v
wire oz; // From z of z.v
// End of automatics
a a (.*);
z z (.*);
always @ (posedge clk) begin
`ifdef TEST_VERBOSE
$write("[%0t] cyc==%0d i=%x oa=%x oz=%x\n", $time, cyc, i, oa, oz);
`endif
cyc <= cyc + 1;
i <= cyc[0];
if (cyc==0) begin
v = 3;
if (v !== 3) $stop;
if (assignin(v) !== 2) $stop;
if (v !== 3) $stop; // Make sure V didn't get changed
end
else if (cyc<10) begin
if (cyc==11 && oz!==1'b0) $stop;
if (cyc==12 && oz!==1'b1) $stop;
if (cyc==12 && oa!==1'b1) $stop;
end
else if (cyc<90) begin
end
else if (cyc==99) begin
$write("*-* All Finished *-*\n");
$finish;
end
end
function integer assignin(input integer i);
i = 2;
assignin = i;
endfunction
endmodule
module a (input i, output oa);
// verilator lint_off ASSIGNIN
assign i = 1'b1;
assign oa = i;
endmodule
module z (input i, output oz);
assign oz = i;
endmodule
|
/*
----------------------------------------------------------------------------------
Copyright (c) 2013-2014
Embedded and Network Computing Lab.
Open SSD Project
Hanyang University
All rights reserved.
----------------------------------------------------------------------------------
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
3. All advertising materials mentioning features or use of this source code
must display the following acknowledgement:
This product includes source code developed
by the Embedded and Network Computing Lab. and the Open SSD Project.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
----------------------------------------------------------------------------------
http://enclab.hanyang.ac.kr/
http://www.openssd-project.org/
http://www.hanyang.ac.kr/
----------------------------------------------------------------------------------
*/
`timescale 1ns / 1ps
module reg_cpu_pcie_sync # (
parameter C_PCIE_ADDR_WIDTH = 36
)
(
input cpu_bus_clk,
input [1:0] nvme_csts_shst,
input nvme_csts_rdy,
input [8:0] sq_valid,
input [7:0] io_sq1_size,
input [7:0] io_sq2_size,
input [7:0] io_sq3_size,
input [7:0] io_sq4_size,
input [7:0] io_sq5_size,
input [7:0] io_sq6_size,
input [7:0] io_sq7_size,
input [7:0] io_sq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr,
input [3:0] io_sq1_cq_vec,
input [3:0] io_sq2_cq_vec,
input [3:0] io_sq3_cq_vec,
input [3:0] io_sq4_cq_vec,
input [3:0] io_sq5_cq_vec,
input [3:0] io_sq6_cq_vec,
input [3:0] io_sq7_cq_vec,
input [3:0] io_sq8_cq_vec,
input [8:0] cq_valid,
input [7:0] io_cq1_size,
input [7:0] io_cq2_size,
input [7:0] io_cq3_size,
input [7:0] io_cq4_size,
input [7:0] io_cq5_size,
input [7:0] io_cq6_size,
input [7:0] io_cq7_size,
input [7:0] io_cq8_size,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr,
input [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr,
input [8:0] io_cq_irq_en,
input [2:0] io_cq1_iv,
input [2:0] io_cq2_iv,
input [2:0] io_cq3_iv,
input [2:0] io_cq4_iv,
input [2:0] io_cq5_iv,
input [2:0] io_cq6_iv,
input [2:0] io_cq7_iv,
input [2:0] io_cq8_iv,
output pcie_link_up_sync,
output [5:0] pl_ltssm_state_sync,
output [15:0] cfg_command_sync,
output [2:0] cfg_interrupt_mmenable_sync,
output cfg_interrupt_msienable_sync,
output cfg_interrupt_msixenable_sync,
output pcie_mreq_err_sync,
output pcie_cpld_err_sync,
output pcie_cpld_len_err_sync,
output nvme_cc_en_sync,
output [1:0] nvme_cc_shn_sync,
input pcie_user_clk,
input pcie_link_up,
input [5:0] pl_ltssm_state,
input [15:0] cfg_command,
input [2:0] cfg_interrupt_mmenable,
input cfg_interrupt_msienable,
input cfg_interrupt_msixenable,
input pcie_mreq_err,
input pcie_cpld_err,
input pcie_cpld_len_err,
input nvme_cc_en,
input [1:0] nvme_cc_shn,
output [1:0] nvme_csts_shst_sync,
output nvme_csts_rdy_sync,
output [8:0] sq_rst_n_sync,
output [8:0] sq_valid_sync,
output [7:0] io_sq1_size_sync,
output [7:0] io_sq2_size_sync,
output [7:0] io_sq3_size_sync,
output [7:0] io_sq4_size_sync,
output [7:0] io_sq5_size_sync,
output [7:0] io_sq6_size_sync,
output [7:0] io_sq7_size_sync,
output [7:0] io_sq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_sq8_bs_addr_sync,
output [3:0] io_sq1_cq_vec_sync,
output [3:0] io_sq2_cq_vec_sync,
output [3:0] io_sq3_cq_vec_sync,
output [3:0] io_sq4_cq_vec_sync,
output [3:0] io_sq5_cq_vec_sync,
output [3:0] io_sq6_cq_vec_sync,
output [3:0] io_sq7_cq_vec_sync,
output [3:0] io_sq8_cq_vec_sync,
output [8:0] cq_rst_n_sync,
output [8:0] cq_valid_sync,
output [7:0] io_cq1_size_sync,
output [7:0] io_cq2_size_sync,
output [7:0] io_cq3_size_sync,
output [7:0] io_cq4_size_sync,
output [7:0] io_cq5_size_sync,
output [7:0] io_cq6_size_sync,
output [7:0] io_cq7_size_sync,
output [7:0] io_cq8_size_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq1_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq2_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq3_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq4_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq5_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq6_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq7_bs_addr_sync,
output [C_PCIE_ADDR_WIDTH-1:2] io_cq8_bs_addr_sync,
output [8:0] io_cq_irq_en_sync,
output [2:0] io_cq1_iv_sync,
output [2:0] io_cq2_iv_sync,
output [2:0] io_cq3_iv_sync,
output [2:0] io_cq4_iv_sync,
output [2:0] io_cq5_iv_sync,
output [2:0] io_cq6_iv_sync,
output [2:0] io_cq7_iv_sync,
output [2:0] io_cq8_iv_sync
);
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_link_up_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [5:0] r_pl_ltssm_state_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [15:0] r_cfg_command_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_cfg_interrupt_mmenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msienable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_cfg_interrupt_msixenable_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_mreq_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_pcie_cpld_len_err_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_cc_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_cc_shn_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [1:0] r_nvme_csts_shst_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg r_nvme_csts_rdy_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_sq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_sq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_sq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq1_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq2_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq3_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq4_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq5_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq6_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq7_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [3:0] r_io_sq8_cq_vec;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d2;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_cq_valid_d3;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq1_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq2_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq3_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq4_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq5_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq6_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq7_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [7:0] r_io_cq8_size;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq1_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq2_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq3_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq4_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq5_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq6_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq7_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [C_PCIE_ADDR_WIDTH-1:2] r_io_cq8_bs_addr;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [8:0] r_io_cq_irq_en_d1;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq1_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq2_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq3_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq4_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq5_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq6_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq7_iv;
(* KEEP = "TRUE", SHIFT_EXTRACT = "NO" *) reg [2:0] r_io_cq8_iv;
assign pcie_link_up_sync = r_pcie_link_up_d1;
assign pl_ltssm_state_sync = r_pl_ltssm_state_d1;
assign cfg_command_sync = r_cfg_command_d1;
assign cfg_interrupt_mmenable_sync = r_cfg_interrupt_mmenable_d1;
assign cfg_interrupt_msienable_sync = r_cfg_interrupt_msienable_d1;
assign cfg_interrupt_msixenable_sync = r_cfg_interrupt_msixenable_d1;
assign pcie_mreq_err_sync = r_pcie_mreq_err_d1;
assign pcie_cpld_err_sync = r_pcie_cpld_err_d1;
assign pcie_cpld_len_err_sync = r_pcie_cpld_len_err_d1;
assign nvme_cc_en_sync = r_nvme_cc_en_d1;
assign nvme_cc_shn_sync = r_nvme_cc_shn_d1;
assign nvme_csts_shst_sync = r_nvme_csts_shst_d1;
assign nvme_csts_rdy_sync = r_nvme_csts_rdy_d1;
assign sq_rst_n_sync = r_sq_valid_d3;
assign sq_valid_sync = r_sq_valid_d1;
assign io_sq1_size_sync = r_io_sq1_size;
assign io_sq2_size_sync = r_io_sq2_size;
assign io_sq3_size_sync = r_io_sq3_size;
assign io_sq4_size_sync = r_io_sq4_size;
assign io_sq5_size_sync = r_io_sq5_size;
assign io_sq6_size_sync = r_io_sq6_size;
assign io_sq7_size_sync = r_io_sq7_size;
assign io_sq8_size_sync = r_io_sq8_size;
assign io_sq1_bs_addr_sync = r_io_sq1_bs_addr;
assign io_sq2_bs_addr_sync = r_io_sq2_bs_addr;
assign io_sq3_bs_addr_sync = r_io_sq3_bs_addr;
assign io_sq4_bs_addr_sync = r_io_sq4_bs_addr;
assign io_sq5_bs_addr_sync = r_io_sq5_bs_addr;
assign io_sq6_bs_addr_sync = r_io_sq6_bs_addr;
assign io_sq7_bs_addr_sync = r_io_sq7_bs_addr;
assign io_sq8_bs_addr_sync = r_io_sq8_bs_addr;
assign io_sq1_cq_vec_sync = r_io_sq1_cq_vec;
assign io_sq2_cq_vec_sync = r_io_sq2_cq_vec;
assign io_sq3_cq_vec_sync = r_io_sq3_cq_vec;
assign io_sq4_cq_vec_sync = r_io_sq4_cq_vec;
assign io_sq5_cq_vec_sync = r_io_sq5_cq_vec;
assign io_sq6_cq_vec_sync = r_io_sq6_cq_vec;
assign io_sq7_cq_vec_sync = r_io_sq7_cq_vec;
assign io_sq8_cq_vec_sync = r_io_sq8_cq_vec;
assign cq_rst_n_sync = r_cq_valid_d3;
assign cq_valid_sync = r_cq_valid_d1;
assign io_cq1_size_sync = r_io_cq1_size;
assign io_cq2_size_sync = r_io_cq2_size;
assign io_cq3_size_sync = r_io_cq3_size;
assign io_cq4_size_sync = r_io_cq4_size;
assign io_cq5_size_sync = r_io_cq5_size;
assign io_cq6_size_sync = r_io_cq6_size;
assign io_cq7_size_sync = r_io_cq7_size;
assign io_cq8_size_sync = r_io_cq8_size;
assign io_cq1_bs_addr_sync = r_io_cq1_bs_addr;
assign io_cq2_bs_addr_sync = r_io_cq2_bs_addr;
assign io_cq3_bs_addr_sync = r_io_cq3_bs_addr;
assign io_cq4_bs_addr_sync = r_io_cq4_bs_addr;
assign io_cq5_bs_addr_sync = r_io_cq5_bs_addr;
assign io_cq6_bs_addr_sync = r_io_cq6_bs_addr;
assign io_cq7_bs_addr_sync = r_io_cq7_bs_addr;
assign io_cq8_bs_addr_sync = r_io_cq8_bs_addr;
assign io_cq_irq_en_sync = r_io_cq_irq_en_d1;
assign io_cq1_iv_sync = r_io_cq1_iv;
assign io_cq2_iv_sync = r_io_cq2_iv;
assign io_cq3_iv_sync = r_io_cq3_iv;
assign io_cq4_iv_sync = r_io_cq4_iv;
assign io_cq5_iv_sync = r_io_cq5_iv;
assign io_cq6_iv_sync = r_io_cq6_iv;
assign io_cq7_iv_sync = r_io_cq7_iv;
assign io_cq8_iv_sync = r_io_cq8_iv;
always @ (posedge cpu_bus_clk)
begin
r_pcie_link_up <= pcie_link_up;
r_pcie_link_up_d1 <= r_pcie_link_up;
r_pl_ltssm_state <= pl_ltssm_state;
r_pl_ltssm_state_d1 <= r_pl_ltssm_state;
r_cfg_command <= cfg_command;
r_cfg_command_d1 <= r_cfg_command;
r_cfg_interrupt_mmenable <= cfg_interrupt_mmenable;
r_cfg_interrupt_mmenable_d1 <= r_cfg_interrupt_mmenable;
r_cfg_interrupt_msienable <= cfg_interrupt_msienable;
r_cfg_interrupt_msienable_d1 <= r_cfg_interrupt_msienable;
r_cfg_interrupt_msixenable <= cfg_interrupt_msixenable;
r_cfg_interrupt_msixenable_d1 <= r_cfg_interrupt_msixenable;
r_pcie_mreq_err <= pcie_mreq_err;
r_pcie_mreq_err_d1 <= r_pcie_mreq_err;
r_pcie_cpld_err <= pcie_cpld_err;
r_pcie_cpld_err_d1 <= r_pcie_cpld_err;
r_pcie_cpld_len_err <= pcie_cpld_len_err;
r_pcie_cpld_len_err_d1 <= r_pcie_cpld_len_err;
r_nvme_cc_en <= nvme_cc_en;
r_nvme_cc_en_d1 <= r_nvme_cc_en;
r_nvme_cc_shn <= nvme_cc_shn;
r_nvme_cc_shn_d1 <= r_nvme_cc_shn;
end
always @ (posedge pcie_user_clk)
begin
r_nvme_csts_shst <= nvme_csts_shst;
r_nvme_csts_shst_d1 <= r_nvme_csts_shst;
r_nvme_csts_rdy <= nvme_csts_rdy;
r_nvme_csts_rdy_d1 <= r_nvme_csts_rdy;
r_sq_valid <= sq_valid;
r_sq_valid_d1 <= r_sq_valid;
r_sq_valid_d2 <= r_sq_valid_d1;
r_sq_valid_d3 <= r_sq_valid_d2;
r_io_sq1_size <= io_sq1_size;
r_io_sq2_size <= io_sq2_size;
r_io_sq3_size <= io_sq3_size;
r_io_sq4_size <= io_sq4_size;
r_io_sq5_size <= io_sq5_size;
r_io_sq6_size <= io_sq6_size;
r_io_sq7_size <= io_sq7_size;
r_io_sq8_size <= io_sq8_size;
r_io_sq1_bs_addr <= io_sq1_bs_addr;
r_io_sq2_bs_addr <= io_sq2_bs_addr;
r_io_sq3_bs_addr <= io_sq3_bs_addr;
r_io_sq4_bs_addr <= io_sq4_bs_addr;
r_io_sq5_bs_addr <= io_sq5_bs_addr;
r_io_sq6_bs_addr <= io_sq6_bs_addr;
r_io_sq7_bs_addr <= io_sq7_bs_addr;
r_io_sq8_bs_addr <= io_sq8_bs_addr;
r_io_sq1_cq_vec <= io_sq1_cq_vec;
r_io_sq2_cq_vec <= io_sq2_cq_vec;
r_io_sq3_cq_vec <= io_sq3_cq_vec;
r_io_sq4_cq_vec <= io_sq4_cq_vec;
r_io_sq5_cq_vec <= io_sq5_cq_vec;
r_io_sq6_cq_vec <= io_sq6_cq_vec;
r_io_sq7_cq_vec <= io_sq7_cq_vec;
r_io_sq8_cq_vec <= io_sq8_cq_vec;
r_cq_valid <= cq_valid;
r_cq_valid_d1 <= r_cq_valid;
r_cq_valid_d2 <= r_cq_valid_d1;
r_cq_valid_d3 <= r_cq_valid_d2;
r_io_cq1_size <= io_cq1_size;
r_io_cq2_size <= io_cq2_size;
r_io_cq3_size <= io_cq3_size;
r_io_cq4_size <= io_cq4_size;
r_io_cq5_size <= io_cq5_size;
r_io_cq6_size <= io_cq6_size;
r_io_cq7_size <= io_cq7_size;
r_io_cq8_size <= io_cq8_size;
r_io_cq1_bs_addr <= io_cq1_bs_addr;
r_io_cq2_bs_addr <= io_cq2_bs_addr;
r_io_cq3_bs_addr <= io_cq3_bs_addr;
r_io_cq4_bs_addr <= io_cq4_bs_addr;
r_io_cq5_bs_addr <= io_cq5_bs_addr;
r_io_cq6_bs_addr <= io_cq6_bs_addr;
r_io_cq7_bs_addr <= io_cq7_bs_addr;
r_io_cq8_bs_addr <= io_cq8_bs_addr;
r_io_cq_irq_en <= io_cq_irq_en;
r_io_cq_irq_en_d1 <= r_io_cq_irq_en;
r_io_cq1_iv <= io_cq1_iv;
r_io_cq2_iv <= io_cq2_iv;
r_io_cq3_iv <= io_cq3_iv;
r_io_cq4_iv <= io_cq4_iv;
r_io_cq5_iv <= io_cq5_iv;
r_io_cq6_iv <= io_cq6_iv;
r_io_cq7_iv <= io_cq7_iv;
r_io_cq8_iv <= io_cq8_iv;
end
endmodule
|
/* -*- tab-width: 4 -*-
*
* Electric(tm) VLSI Design System
*
* File: jtagController.v
*
* Copyright (c) 2005 Sun Microsystems and Static Free Software
*
* Electric(tm) is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 3 of the License, or
* (at your option) any later version.
*
* Electric(tm) is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with Electric(tm); see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 59 Temple Place, Suite 330,
* Boston, Mass 02111-1307, USA.
*/
/* Verilog for cell testCell{sch} from Library jtag */
/* Created on Tue April 26, 2005 11:27:36 */
/* Last revised on Tue April 26, 2005 11:29:37 */
/* Written on Tue April 26, 2005 11:30:54 by Electric VLSI Design System, version 8.02l */
module redFour__NMOSwk_X_1_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
rtranif1 #(100) NMOSfwk_0 (d, s, g);
endmodule /* redFour__NMOSwk_X_1_Delay_100 */
module redFour__PMOSwk_X_0_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule /* redFour__PMOSwk_X_0_833_Delay_100 */
module scanChainFive__scanL(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_4, net_7;
redFour__NMOSwk_X_1_Delay_100 NMOSwk_0(.g(out), .d(in), .s(net_7));
redFour__NMOSwk_X_1_Delay_100 NMOSwk_1(.g(out), .d(net_7), .s(gnd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_0(.g(out), .d(net_4), .s(vdd));
redFour__PMOSwk_X_0_833_Delay_100 PMOSwk_1(.g(out), .d(in), .s(net_4));
not (strong0, strong1) #(100) invV_0 (out, in);
endmodule /* scanChainFive__scanL */
module redFour__NMOS_X_6_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_6_667_Delay_100 */
module redFour__PMOS_X_3_333_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_3_333_Delay_100 */
module scanChainFive__scanP(in, src, drn);
input in;
input src;
output drn;
supply1 vdd;
supply0 gnd;
wire net_1;
redFour__NMOS_X_6_667_Delay_100 NMOS_0(.g(in), .d(drn), .s(src));
redFour__PMOS_X_3_333_Delay_100 PMOS_0(.g(net_1), .d(drn), .s(src));
not (strong0, strong1) #(0) inv_0 (net_1, in);
endmodule /* scanChainFive__scanP */
module scanChainFive__scanRL(phi1, phi2, rd, sin, sout);
input phi1;
input phi2;
input rd;
input sin;
output sout;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_3;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_0), .out(sout));
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_0));
scanChainFive__scanP scanP_1(.in(phi1), .src(net_3), .drn(net_0));
scanChainFive__scanP scanP_2(.in(phi2), .src(sin), .drn(net_2));
endmodule /* scanChainFive__scanRL */
module jtag__BR(SDI, phi1, phi2, read, SDO);
input SDI;
input phi1;
input phi2;
input read;
output SDO;
supply1 vdd;
supply0 gnd;
scanChainFive__scanRL scanRL_0(.phi1(phi1), .phi2(phi2), .rd(read),
.sin(SDI), .sout(SDO));
endmodule /* jtag__BR */
module scanChainFive__scanIRH(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_4, net_6, net_7;
scanChainFive__scanL foo1(.in(net_6), .out(net_7));
scanChainFive__scanL foo2(.in(net_2), .out(sout));
scanChainFive__scanL foo3(.in(net_4), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(wr), .src(sout), .drn(net_4));
scanChainFive__scanP scanP_1(.in(rd), .src(gnd), .drn(net_2));
scanChainFive__scanP scanP_2(.in(mclr), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_7), .drn(net_2));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_6));
endmodule /* scanChainFive__scanIRH */
module scanChainFive__scanIRL(mclr, phi1, phi2, rd, sin, wr, dout, doutb,
sout);
input mclr;
input phi1;
input phi2;
input rd;
input sin;
input wr;
output dout;
output doutb;
output sout;
supply1 vdd;
supply0 gnd;
wire net_2, net_3, net_4, net_6;
scanChainFive__scanL foo1(.in(net_2), .out(net_3));
scanChainFive__scanL foo2(.in(net_4), .out(sout));
scanChainFive__scanL foo3(.in(net_6), .out(doutb));
not (strong0, strong1) #(100) invLT_0 (dout, doutb);
scanChainFive__scanP scanP_0(.in(rd), .src(vdd), .drn(net_4));
scanChainFive__scanP scanP_1(.in(mclr), .src(vdd), .drn(net_6));
scanChainFive__scanP scanP_2(.in(wr), .src(sout), .drn(net_6));
scanChainFive__scanP scanP_3(.in(phi1), .src(net_3), .drn(net_4));
scanChainFive__scanP scanP_4(.in(phi2), .src(sin), .drn(net_2));
endmodule /* scanChainFive__scanIRL */
module jtag__IR(SDI, phi1, phi2, read, reset, write, IR, IRb, SDO);
input SDI;
input phi1;
input phi2;
input read;
input reset;
input write;
output [8:1] IR;
output [8:1] IRb;
output SDO;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_5, net_6, net_7;
scanChainFive__scanIRH scanIRH_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_1), .wr(write), .dout(IR[1]), .doutb(IRb[1]),
.sout(SDO));
scanChainFive__scanIRL scanIRL_0(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_3), .wr(write), .dout(IR[7]), .doutb(IRb[7]),
.sout(net_2));
scanChainFive__scanIRL scanIRL_1(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_5), .wr(write), .dout(IR[5]), .doutb(IRb[5]),
.sout(net_4));
scanChainFive__scanIRL scanIRL_2(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_2), .wr(write), .dout(IR[6]), .doutb(IRb[6]),
.sout(net_5));
scanChainFive__scanIRL scanIRL_3(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_7), .wr(write), .dout(IR[3]), .doutb(IRb[3]),
.sout(net_6));
scanChainFive__scanIRL scanIRL_4(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_6), .wr(write), .dout(IR[2]), .doutb(IRb[2]),
.sout(net_1));
scanChainFive__scanIRL scanIRL_5(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(net_4), .wr(write), .dout(IR[4]), .doutb(IRb[4]),
.sout(net_7));
scanChainFive__scanIRL scanIRL_6(.mclr(reset), .phi1(phi1), .phi2(phi2),
.rd(read), .sin(SDI), .wr(write), .dout(IR[8]), .doutb(IRb[8]),
.sout(net_3));
endmodule /* jtag__IR */
module redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule /* redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1 */
module jtag__IRdecode(IR, IRb, Bypass, ExTest, SamplePreload, ScanPath);
input [4:1] IR;
input [4:1] IRb;
output Bypass;
output ExTest;
output SamplePreload;
output [12:0] ScanPath;
supply1 vdd;
supply0 gnd;
wire H00, H01, H10, H11, L00, L01, L10, L11, net_19, net_21, net_23, net_25;
wire net_26, net_27, net_28, net_29, net_30, net_31, net_32, net_33, net_34;
wire net_35, net_36, net_37;
not (strong0, strong1) #(100) inv_0 (Bypass, net_19);
not (strong0, strong1) #(100) inv_1 (SamplePreload, net_21);
not (strong0, strong1) #(100) inv_2 (ExTest, net_23);
not (strong0, strong1) #(100) inv_3 (ScanPath[12], net_25);
not (strong0, strong1) #(100) inv_4 (ScanPath[11], net_26);
not (strong0, strong1) #(100) inv_5 (ScanPath[10], net_27);
not (strong0, strong1) #(100) inv_6 (ScanPath[9], net_28);
not (strong0, strong1) #(100) inv_7 (ScanPath[8], net_29);
not (strong0, strong1) #(100) inv_8 (ScanPath[7], net_30);
not (strong0, strong1) #(100) inv_9 (ScanPath[6], net_31);
not (strong0, strong1) #(100) inv_10 (ScanPath[5], net_32);
not (strong0, strong1) #(100) inv_11 (ScanPath[4], net_33);
not (strong0, strong1) #(100) inv_12 (ScanPath[3], net_34);
not (strong0, strong1) #(100) inv_13 (ScanPath[2], net_35);
not (strong0, strong1) #(100) inv_14 (ScanPath[1], net_36);
not (strong0, strong1) #(100) inv_15 (ScanPath[0], net_37);
nand (strong0, strong1) #(100) nand2_0 (net_19, L11, H11);
nand (strong0, strong1) #(100) nand2_1 (net_21, L10, H11);
nand (strong0, strong1) #(100) nand2_2 (net_23, L01, H11);
nand (strong0, strong1) #(100) nand2_3 (net_25, L00, H11);
nand (strong0, strong1) #(100) nand2_4 (net_26, L11, H10);
nand (strong0, strong1) #(100) nand2_5 (net_27, L10, H10);
nand (strong0, strong1) #(100) nand2_6 (net_28, L01, H10);
nand (strong0, strong1) #(100) nand2_7 (net_29, L00, H10);
nand (strong0, strong1) #(100) nand2_8 (net_30, L11, H01);
nand (strong0, strong1) #(100) nand2_9 (net_31, L10, H01);
nand (strong0, strong1) #(100) nand2_10 (net_32, L01, H01);
nand (strong0, strong1) #(100) nand2_11 (net_33, L00, H01);
nand (strong0, strong1) #(100) nand2_12 (net_34, L11, H00);
nand (strong0, strong1) #(100) nand2_13 (net_35, L10, H00);
nand (strong0, strong1) #(100) nand2_14 (net_36, L01, H00);
nand (strong0, strong1) #(100) nand2_15 (net_37, L00, H00);
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(IR[1]), .inb(IR[2]), .out(L00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(IRb[1]), .inb(IR[2]), .out(L01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(IR[1]), .inb(IRb[2]), .out(L10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(IRb[1]), .inb(IRb[2]), .out(L11));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(IR[3]), .inb(IR[4]), .out(H00));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_5(.ina(IRb[3]), .inb(IR[4]), .out(H01));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_6(.ina(IR[3]), .inb(IRb[4]), .out(H10));
redFour__nor2n_X_3_Delay_100_drive0_strong0_drive1_strong1
nor2n_7(.ina(IRb[3]), .inb(IRb[4]), .out(H11));
endmodule /* jtag__IRdecode */
module redFour__PMOSwk_X_0_222_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
rtranif0 #(100) PMOSfwk_0 (d, s, g);
endmodule /* redFour__PMOSwk_X_0_222_Delay_100 */
module jtag__clockGen(clk, phi1_fb, phi2_fb, phi1_out, phi2_out);
input clk;
input phi1_fb;
input phi2_fb;
output phi1_out;
output phi2_out;
supply1 vdd;
supply0 gnd;
wire net_0, net_1, net_3, net_4, net_6;
not (strong0, strong1) #(100) inv_0 (phi2_out, net_3);
not (strong0, strong1) #(100) inv_1 (phi1_out, net_6);
not (strong0, strong1) #(100) inv_2 (net_4, clk);
not (strong0, strong1) #(100) invLT_0 (net_0, phi1_fb);
not (strong0, strong1) #(100) invLT_1 (net_1, phi2_fb);
nand (strong0, strong1) #(100) nand2_0 (net_3, net_0, net_4);
nand (strong0, strong1) #(100) nand2_1 (net_6, net_1, clk);
endmodule /* jtag__clockGen */
module jtag__capture_ctl(capture, phi2, sel, out, phi1);
input capture;
input phi2;
input sel;
output out;
input phi1;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4;
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_1, capture);
not (strong0, strong1) #(100) inv_1 (out, net_4);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1);
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
endmodule /* jtag__capture_ctl */
module jtag__shift_ctl(phi1_fb, phi2_fb, sel, shift, phi1_out, phi2_out,
phi1_in, phi2_in);
input phi1_fb;
input phi2_fb;
input sel;
input shift;
output phi1_out;
output phi2_out;
input phi1_in;
input phi2_in;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_4, net_7;
jtag__clockGen clockGen_0(.clk(net_7), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(phi1_out), .phi2_out(phi2_out));
scanChainFive__scanL foo(.in(net_2), .out(net_3));
not (strong0, strong1) #(100) inv_0 (net_7, net_4);
not (strong0, strong1) #(100) inv_1 (net_1, shift);
nand (strong0, strong1) #(100) nand3_0 (net_4, sel, net_3, phi1_in);
scanChainFive__scanP scanP_0(.in(phi2_in), .src(net_1), .drn(net_2));
endmodule /* jtag__shift_ctl */
module jtag__update_ctl(sel, update, out, phi2);
input sel;
input update;
output out;
input phi2;
supply1 vdd;
supply0 gnd;
wire net_1;
not (strong0, strong1) #(100) inv_0 (out, net_1);
nand (strong0, strong1) #(100) nand3_0 (net_1, sel, update, phi2);
endmodule /* jtag__update_ctl */
module jtag__jtagIRControl(capture, phi1_fb, phi1_in, phi2_fb, phi2_in, shift,
update, phi1_out, phi2_out, read, write);
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input shift;
input update;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(vdd),
.out(read), .phi1(phi1_in));
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(vdd),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__update_ctl update_c_0(.sel(vdd), .update(update), .out(write),
.phi2(phi2_in));
endmodule /* jtag__jtagIRControl */
module redFour__NMOS_X_8_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_8_Delay_100 */
module redFour__PMOS_X_4_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_4_Delay_100 */
module jtag__tsinvBig(Din, en, enb, Dout);
input Din;
input en;
input enb;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_13, net_14, net_22, net_23;
redFour__NMOS_X_8_Delay_100 NMOS_0(.g(Din), .d(net_13), .s(gnd));
redFour__NMOS_X_8_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_13));
redFour__NMOS_X_8_Delay_100 NMOS_2(.g(en), .d(Dout), .s(net_23));
redFour__NMOS_X_8_Delay_100 NMOS_3(.g(Din), .d(net_23), .s(gnd));
redFour__PMOS_X_4_Delay_100 PMOS_0(.g(enb), .d(Dout), .s(net_14));
redFour__PMOS_X_4_Delay_100 PMOS_1(.g(Din), .d(net_14), .s(vdd));
redFour__PMOS_X_4_Delay_100 PMOS_2(.g(enb), .d(Dout), .s(net_22));
redFour__PMOS_X_4_Delay_100 PMOS_3(.g(Din), .d(net_22), .s(vdd));
endmodule /* jtag__tsinvBig */
module jtag__jtagScanControl(TDI, capture, phi1_fb, phi1_in, phi2_fb, phi2_in,
sel, shift, update, TDO, phi1_out, phi2_out, read, write);
input TDI;
input capture;
input phi1_fb;
input phi1_in;
input phi2_fb;
input phi2_in;
input sel;
input shift;
input update;
output TDO;
output phi1_out;
output phi2_out;
output read;
output write;
supply1 vdd;
supply0 gnd;
wire net_0, net_2;
jtag__capture_ctl capture__0(.capture(capture), .phi2(phi2_in), .sel(sel),
.out(read), .phi1(phi1_in));
not (strong0, strong1) #(100) inv_0 (net_2, sel);
not (strong0, strong1) #(100) inv_1 (net_0, TDI);
jtag__shift_ctl shift_ct_0(.phi1_fb(phi1_fb), .phi2_fb(phi2_fb), .sel(sel),
.shift(shift), .phi1_out(phi1_out), .phi2_out(phi2_out),
.phi1_in(phi1_in), .phi2_in(phi2_in));
jtag__tsinvBig tsinvBig_0(.Din(net_0), .en(sel), .enb(net_2), .Dout(TDO));
jtag__update_ctl update_c_0(.sel(sel), .update(update), .out(write),
.phi2(phi2_in));
endmodule /* jtag__jtagScanControl */
module redFour__NMOS_X_5_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_5_667_Delay_100 */
module redFour__PMOS_X_2_833_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_2_833_Delay_100 */
module jtag__tsinv(Din, Dout, en, enb);
input Din;
input Dout;
input en;
input enb;
supply1 vdd;
supply0 gnd;
wire net_1, net_2;
redFour__NMOS_X_5_667_Delay_100 NMOS_0(.g(Din), .d(net_1), .s(gnd));
redFour__NMOS_X_5_667_Delay_100 NMOS_1(.g(en), .d(Dout), .s(net_1));
redFour__PMOS_X_2_833_Delay_100 PMOS_0(.g(Din), .d(net_2), .s(vdd));
redFour__PMOS_X_2_833_Delay_100 PMOS_1(.g(enb), .d(Dout), .s(net_2));
endmodule /* jtag__tsinv */
module jtag__mux2_phi2(Din0, Din1, phi2, sel, Dout);
input Din0;
input Din1;
input phi2;
input sel;
output Dout;
supply1 vdd;
supply0 gnd;
wire net_1, net_2, net_3, net_5, net_6;
not (strong0, strong1) #(100) inv_0 (net_5, sel);
not (strong0, strong1) #(100) inv_1 (net_1, net_6);
not (strong0, strong1) #(100) inv_2 (Dout, net_3);
scanChainFive__scanL scanL_0(.in(net_2), .out(net_3));
scanChainFive__scanP scanP_0(.in(phi2), .src(net_1), .drn(net_2));
jtag__tsinv tsinv_0(.Din(Din0), .Dout(net_6), .en(net_5), .enb(sel));
jtag__tsinv tsinv_1(.Din(Din1), .Dout(net_6), .en(sel), .enb(net_5));
endmodule /* jtag__mux2_phi2 */
module jtag__scanAmp1w1648(in, out);
input in;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
tranif1 nmos_0(gnd, net_0, in);
tranif1 nmos_1(gnd, out, net_0);
tranif0 pmos_0(net_0, vdd, in);
tranif0 pmos_1(out, vdd, net_0);
endmodule /* jtag__scanAmp1w1648 */
module redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule /* redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1 */
module redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nand (strong0, strong1) #(100) nand2_0 (out, ina, inb);
endmodule /* redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
module redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1(ina, inb,
out);
input ina;
input inb;
output out;
supply1 vdd;
supply0 gnd;
nor (strong0, strong1) #(100) nor2_0 (out, ina, inb);
endmodule /* redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1 */
module orangeTSMC180nm__wire_R_26m_100_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_100_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_100_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 */
module jtag__o2a(inAa, inAb, inOb, out);
input inAa;
input inAb;
input inOb;
output out;
supply1 vdd;
supply0 gnd;
wire net_0;
nor (strong0, strong1) #(100) nor2_0 (net_0, inAa, inAb);
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(inOb), .inb(net_0), .out(out));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_0));
endmodule /* jtag__o2a */
module orangeTSMC180nm__wire_R_26m_500_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_500_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_500_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 */
module jtag__slaveBit(din, phi2, slave);
input din;
input phi2;
output slave;
supply1 vdd;
supply0 gnd;
wire net_6, net_7;
not (strong0, strong1) #(100) inv_0 (slave, net_7);
scanChainFive__scanL scanL_0(.in(net_6), .out(net_7));
scanChainFive__scanP scanP_0(.in(phi2), .src(din), .drn(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500 wire180_0(.a(slave));
endmodule /* jtag__slaveBit */
module redFour__NMOS_X_1_667_Delay_100(g, d, s);
input g;
input d;
input s;
supply0 gnd;
tranif1 #(100) NMOSf_0 (d, s, g);
endmodule /* redFour__NMOS_X_1_667_Delay_100 */
module orangeTSMC180nm__wire_R_26m_750_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_750_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_750_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 */
module orangeTSMC180nm__wire_R_26m_1000_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_1000_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1000_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 */
module jtag__stateBit(next, phi1, phi2, rst, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rst;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_12, net_13, net_14, net_17;
redFour__NMOS_X_1_667_Delay_100 NMOS_0(.g(rst), .d(net_12), .s(gnd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_17);
not (strong0, strong1) #(100) inv_2 (master, net_13);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_13));
scanChainFive__scanL scanL_1(.in(net_14), .out(net_17));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_13), .drn(net_14));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_0(.a(master));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_1(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_2(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_3(.a(next));
endmodule /* jtag__stateBit */
module redFour__PMOS_X_1_5_Delay_100(g, d, s);
input g;
input d;
input s;
supply1 vdd;
tranif0 #(100) PMOSf_0 (d, s, g);
endmodule /* redFour__PMOS_X_1_5_Delay_100 */
module jtag__stateBitHI(next, phi1, phi2, rstb, master, slave, slaveBar);
input next;
input phi1;
input phi2;
input rstb;
output master;
output slave;
output slaveBar;
supply1 vdd;
supply0 gnd;
wire net_10, net_11, net_12, net_15;
redFour__PMOS_X_1_5_Delay_100 PMOS_0(.g(rstb), .d(net_12), .s(vdd));
not (strong0, strong1) #(100) inv_0 (slave, slaveBar);
not (strong0, strong1) #(100) inv_1 (slaveBar, net_15);
not (strong0, strong1) #(100) inv_2 (master, net_10);
scanChainFive__scanL scanL_0(.in(net_12), .out(net_10));
scanChainFive__scanL scanL_1(.in(net_11), .out(net_15));
scanChainFive__scanP scanP_0(.in(phi1), .src(next), .drn(net_12));
scanChainFive__scanP scanP_1(.in(phi2), .src(net_10), .drn(net_11));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1000 wire180_0(.a(slave));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_500
wire180_1(.a(slaveBar));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(next));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_750 wire180_3(.a(master));
endmodule /* jtag__stateBitHI */
module orangeTSMC180nm__wire_R_26m_675_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_675_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_675_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 */
module orangeTSMC180nm__wire_R_26m_1500_C_0_025f(a);
input a;
supply0 gnd;
endmodule /* orangeTSMC180nm__wire_R_26m_1500_C_0_025f */
module orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500(a);
input a;
supply0 gnd;
orangeTSMC180nm__wire_R_26m_1500_C_0_025f wire_0(.a(a));
endmodule /* orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 */
module jtag__tapCtlJKL(TMS, TRSTb, phi1, phi2, CapDR, CapIR, Idle, PauseDR,
PauseIR, Reset, Reset_s, SelDR, SelIR, ShftDR, ShftIR, UpdDR, UpdIR,
X1DR, X1IR, X2DR, X2IR);
input TMS;
input TRSTb;
input phi1;
input phi2;
output CapDR;
output CapIR;
output Idle;
output PauseDR;
output PauseIR;
output Reset;
output Reset_s;
output SelDR;
output SelIR;
output ShftDR;
output ShftIR;
output UpdDR;
output UpdIR;
output X1DR;
output X1IR;
output X2DR;
output X2IR;
supply1 vdd;
supply0 gnd;
wire net_0, net_2, net_4, net_6, net_12, net_13, net_14, net_15, net_16;
wire net_17, net_18, net_19, net_20, net_22, net_23, net_24, net_25, net_26;
wire net_28, net_29, net_31, net_32, net_34, net_40, net_43, net_44, net_48;
wire net_50, net_52, net_54, net_55, net_56, net_58, net_59, net_60, net_64;
wire net_67, net_68, net_70, net_71, net_72, net_74, net_75, net_76, net_79;
wire net_80, rst, stateBit_1_slave, stateBit_5_slaveBar, stateBit_6_slaveBar;
wire stateBit_9_slaveBar, stateBit_10_slaveBar, stateBit_11_slave;
wire stateBit_12_slave;
not (strong0, strong1) #(100) inv_0 (rst, TRSTb);
not (strong0, strong1) #(100) inv_1 (net_24, net_12);
redFour__nand2n_X_3_5_Delay_100_drive0_strong0_drive1_strong1
nand2n_0(.ina(net_13), .inb(net_14), .out(net_0));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_1(.ina(net_15), .inb(net_16), .out(net_4));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_2(.ina(net_17), .inb(net_18), .out(net_2));
redFour__nand2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nand2n_3(.ina(net_19), .inb(net_20), .out(net_6));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_0(.ina(net_12), .inb(net_23), .out(net_22));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_1(.ina(net_24), .inb(net_26), .out(net_25));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_2(.ina(net_24), .inb(net_29), .out(net_28));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_3(.ina(net_24), .inb(net_32), .out(net_31));
redFour__nor2n_X_1_25_Delay_100_drive0_strong0_drive1_strong1
nor2n_4(.ina(net_12), .inb(net_26), .out(net_34));
jtag__o2a o2a_0(.inAa(net_2), .inAb(net_43), .inOb(net_12), .out(net_40));
jtag__o2a o2a_1(.inAa(net_6), .inAb(net_0), .inOb(net_12), .out(net_44));
jtag__o2a o2a_2(.inAa(net_50), .inAb(net_0), .inOb(net_24), .out(net_48));
jtag__o2a o2a_3(.inAa(net_54), .inAb(net_55), .inOb(net_12), .out(net_52));
jtag__o2a o2a_4(.inAa(net_58), .inAb(net_59), .inOb(net_12), .out(net_56));
jtag__o2a o2a_5(.inAa(net_58), .inAb(net_43), .inOb(net_24), .out(net_60));
jtag__o2a o2a_6(.inAa(net_54), .inAb(net_67), .inOb(net_24), .out(net_64));
jtag__o2a o2a_7(.inAa(net_70), .inAb(net_71), .inOb(net_24), .out(net_68));
jtag__o2a o2a_8(.inAa(net_74), .inAb(net_75), .inOb(net_24), .out(net_72));
jtag__o2a o2a_9(.inAa(Reset_s), .inAb(net_79), .inOb(net_24), .out(net_76));
jtag__o2a o2a_10(.inAa(net_4), .inAb(net_67), .inOb(net_12), .out(net_80));
jtag__slaveBit slaveBit_0(.din(TMS), .phi2(phi2), .slave(net_12));
jtag__stateBit stateBit_0(.next(net_25), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelIR), .slave(net_79), .slaveBar(net_23));
jtag__stateBit stateBit_1(.next(net_48), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(SelDR), .slave(stateBit_1_slave), .slaveBar(net_26));
jtag__stateBit stateBit_2(.next(net_34), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapDR), .slave(net_75), .slaveBar(net_16));
jtag__stateBit stateBit_3(.next(net_22), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(CapIR), .slave(net_71), .slaveBar(net_18));
jtag__stateBit stateBit_4(.next(net_44), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(Idle), .slave(net_50), .slaveBar(net_20));
jtag__stateBit stateBit_5(.next(net_68), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1IR), .slave(net_58), .slaveBar(stateBit_5_slaveBar));
jtag__stateBit stateBit_6(.next(net_72), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X1DR), .slave(net_54), .slaveBar(stateBit_6_slaveBar));
jtag__stateBit stateBit_7(.next(net_80), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftDR), .slave(net_74), .slaveBar(net_15));
jtag__stateBit stateBit_8(.next(net_40), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(ShftIR), .slave(net_70), .slaveBar(net_17));
jtag__stateBit stateBit_9(.next(net_28), .phi1(phi1), .phi2(phi2), .rst(rst),
.master(X2IR), .slave(net_43), .slaveBar(stateBit_9_slaveBar));
jtag__stateBit stateBit_10(.next(net_31), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(X2DR), .slave(net_67),
.slaveBar(stateBit_10_slaveBar));
jtag__stateBit stateBit_11(.next(net_64), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdDR), .slave(stateBit_11_slave),
.slaveBar(net_14));
jtag__stateBit stateBit_12(.next(net_60), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(UpdIR), .slave(stateBit_12_slave),
.slaveBar(net_13));
jtag__stateBit stateBit_13(.next(net_56), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseIR), .slave(net_59), .slaveBar(net_29));
jtag__stateBit stateBit_14(.next(net_52), .phi1(phi1), .phi2(phi2),
.rst(rst), .master(PauseDR), .slave(net_55), .slaveBar(net_32));
jtag__stateBitHI stateBit_15(.next(net_76), .phi1(phi1), .phi2(phi2),
.rstb(TRSTb), .master(Reset), .slave(Reset_s), .slaveBar(net_19));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_0(.a(net_4));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_1(.a(net_2));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_100 wire180_2(.a(net_6));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_675 wire180_3(.a(net_0));
orangeTSMC180nm__wire180_width_3_layer_1_LEWIRE_1_1500 wire180_4(.a(rst));
endmodule /* jtag__tapCtlJKL */
module jtag__jtagControl(TCK, TDI, TDIx, TMS, TRSTb, phi1_fb, phi2_fb, Cap,
ExTest, SelBS, SelDR, Shft, TDOb, Upd, phi1, phi2);
input TCK;
input TDI;
input TDIx;
input TMS;
input TRSTb;
input phi1_fb;
input phi2_fb;
output Cap;
output ExTest;
output SelBS;
output [12:0] SelDR;
output Shft;
output TDOb;
output Upd;
output phi1;
output phi2;
supply1 vdd;
supply0 gnd;
wire jtagScan_0_write, net_0, net_1, net_2, net_3, net_6, net_8, net_10;
wire net_33, net_35, net_37, net_38, net_41, net_47, net_48, net_50, net_51;
wire net_52, net_55, net_56, net_62, net_64, net_68, net_73, net_75, net_79;
wire net_97, net_99, net_103, net_128, tapCtlJK_0_Idle, tapCtlJK_0_PauseDR;
wire tapCtlJK_0_PauseIR, tapCtlJK_0_Reset, tapCtlJK_0_SelDR, tapCtlJK_0_SelIR;
wire tapCtlJK_0_X1DR, tapCtlJK_0_X2DR, tapCtlJK_0_X2IR;
wire [8:1] IR;
wire [8:1] IRb;
jtag__BR BR_0(.SDI(TDI), .phi1(net_68), .phi2(net_73), .read(net_99),
.SDO(net_97));
jtag__IR IR_0(.SDI(TDI), .phi1(net_79), .phi2(net_75), .read(net_55),
.reset(net_56), .write(net_103), .IR(IR[8:1]), .IRb(IRb[8:1]),
.SDO(net_128));
jtag__IRdecode IRdecode_0(.IR(IR[4:1]), .IRb(IRb[4:1]), .Bypass(net_41),
.ExTest(ExTest), .SamplePreload(net_47), .ScanPath(SelDR[12:0]));
redFour__PMOSwk_X_0_222_Delay_100 PMOSwk_0(.g(gnd), .d(TDIx), .s(vdd));
jtag__clockGen clockGen_0(.clk(TCK), .phi1_fb(phi1_fb), .phi2_fb(phi2_fb),
.phi1_out(net_10), .phi2_out(net_8));
not (strong0, strong1) #(100) inv_0 (net_0, net_3);
not (strong0, strong1) #(100) inv_1 (SelBS, net_48);
not (strong0, strong1) #(100) inv_2 (net_6, net_50);
not (strong0, strong1) #(100) inv_3 (Cap, net_37);
not (strong0, strong1) #(100) inv_4 (Shft, net_51);
not (strong0, strong1) #(100) inv_5 (net_51, net_52);
not (strong0, strong1) #(100) inv_6 (Upd, net_38);
jtag__jtagIRControl jtagIRCo_0(.capture(net_62), .phi1_fb(net_79),
.phi1_in(phi1), .phi2_fb(net_75), .phi2_in(phi2), .shift(net_2),
.update(net_64), .phi1_out(net_79), .phi2_out(net_75), .read(net_55),
.write(net_103));
jtag__jtagScanControl jtagScan_0(.TDI(net_97), .capture(Cap),
.phi1_fb(net_68), .phi1_in(phi1), .phi2_fb(net_73), .phi2_in(phi2),
.sel(net_41), .shift(Shft), .update(gnd), .TDO(TDIx), .phi1_out(net_68),
.phi2_out(net_73), .read(net_99), .write(jtagScan_0_write));
jtag__mux2_phi2 mux2_phi_0(.Din0(TDIx), .Din1(net_128), .phi2(phi2),
.sel(net_0), .Dout(net_50));
nand (strong0, strong1) #(100) nand2_0 (net_37, IR[8], net_35);
nand (strong0, strong1) #(100) nand2_1 (net_38, IR[7], net_33);
nor (strong0, strong1) #(100) nor2_0 (net_3, net_1, net_2);
nor (strong0, strong1) #(100) nor2_1 (net_48, net_47, ExTest);
jtag__scanAmp1w1648 scanAmp1_0(.in(net_6), .out(TDOb));
jtag__scanAmp1w1648 scanAmp1_1(.in(net_8), .out(phi2));
jtag__scanAmp1w1648 scanAmp1_2(.in(net_10), .out(phi1));
jtag__tapCtlJKL tapCtlJK_0(.TMS(TMS), .TRSTb(TRSTb), .phi1(phi1),
.phi2(phi2), .CapDR(net_35), .CapIR(net_62), .Idle(tapCtlJK_0_Idle),
.PauseDR(tapCtlJK_0_PauseDR), .PauseIR(tapCtlJK_0_PauseIR),
.Reset(tapCtlJK_0_Reset), .Reset_s(net_56), .SelDR(tapCtlJK_0_SelDR),
.SelIR(tapCtlJK_0_SelIR), .ShftDR(net_52), .ShftIR(net_2),
.UpdDR(net_33), .UpdIR(net_64), .X1DR(tapCtlJK_0_X1DR), .X1IR(net_1),
.X2DR(tapCtlJK_0_X2DR), .X2IR(tapCtlJK_0_X2IR));
endmodule /* jtag__jtagControl */
module jtag__JTAGamp(leaf, root);
input [8:1] leaf;
input [5:1] root;
supply1 vdd;
supply0 gnd;
jtag__scanAmp1w1648 toLeaf_5_(.in(root[5]), .out(leaf[5]));
jtag__scanAmp1w1648 toLeaf_4_(.in(root[4]), .out(leaf[4]));
jtag__scanAmp1w1648 toLeaf_3_(.in(root[3]), .out(leaf[3]));
jtag__scanAmp1w1648 toLeaf_2_(.in(root[2]), .out(leaf[2]));
jtag__scanAmp1w1648 toLeaf_1_(.in(root[1]), .out(leaf[1]));
endmodule /* jtag__JTAGamp */
module jtag__jtagScanCtlWBuf(TDI, cap, phi1, phi2, sel, shift, upd, TDO,
leaf);
input TDI;
input cap;
input phi1;
input phi2;
input sel;
input shift;
input upd;
output TDO;
input [8:1] leaf;
supply1 vdd;
supply0 gnd;
wire [5:2] a;
jtag__JTAGamp JTAGamp_0(.leaf(leaf[8:1]), .root({a[5], a[4], a[3], a[2],
TDI}));
jtag__jtagScanControl jtagScan_0(.TDI(leaf[8]), .capture(cap),
.phi1_fb(leaf[6]), .phi1_in(phi1), .phi2_fb(leaf[7]), .phi2_in(phi2),
.sel(sel), .shift(shift), .update(upd), .TDO(TDO), .phi1_out(a[3]),
.phi2_out(a[2]), .read(a[5]), .write(a[4]));
endmodule /* jtag__jtagScanCtlWBuf */
module jtag__jtagScanCtlGroup(TDI, capture, phi1_in, phi2_in, selBS, sel,
shift, update, TDO, BS, leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6,
leaf7, leaf8, leaf9, leaf10, leaf11, leaf12);
input TDI;
input capture;
input phi1_in;
input phi2_in;
input selBS;
input [12:0] sel;
input shift;
input update;
output TDO;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
jtag__jtagScanCtlWBuf jtagScan_1(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[0]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf0[8:1]));
jtag__jtagScanCtlWBuf jtagScan_2(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[10]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf10[8:1]));
jtag__jtagScanCtlWBuf jtagScan_3(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[12]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf12[8:1]));
jtag__jtagScanCtlWBuf jtagScan_4(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[11]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf11[8:1]));
jtag__jtagScanCtlWBuf jtagScan_5(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[9]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf9[8:1]));
jtag__jtagScanCtlWBuf jtagScan_6(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[8]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf8[8:1]));
jtag__jtagScanCtlWBuf jtagScan_7(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[6]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf6[8:1]));
jtag__jtagScanCtlWBuf jtagScan_8(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[5]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf5[8:1]));
jtag__jtagScanCtlWBuf jtagScan_9(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[4]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf4[8:1]));
jtag__jtagScanCtlWBuf jtagScan_10(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[3]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf3[8:1]));
jtag__jtagScanCtlWBuf jtagScan_11(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[2]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf2[8:1]));
jtag__jtagScanCtlWBuf jtagScan_12(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[1]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf1[8:1]));
jtag__jtagScanCtlWBuf jtagScan_13(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(sel[7]), .shift(shift), .upd(update), .TDO(TDO),
.leaf(leaf7[8:1]));
jtag__jtagScanCtlWBuf jtagScan_16(.TDI(TDI), .cap(capture), .phi1(phi1_in),
.phi2(phi2_in), .sel(selBS), .shift(shift), .upd(update), .TDO(TDO),
.leaf(BS[8:1]));
endmodule /* jtag__jtagScanCtlGroup */
module jtag__jtagCentral_LEIGNORE_1(TCK, TDI, TMS, TRSTb, ExTest, TDOb, BS,
leaf0, leaf1, leaf2, leaf3, leaf4, leaf5, leaf6, leaf7, leaf8, leaf9,
leaf10, leaf11, leaf12);
input TCK;
input TDI;
input TMS;
input TRSTb;
output ExTest;
output TDOb;
input [8:1] BS;
input [8:1] leaf0;
input [8:1] leaf1;
input [8:1] leaf2;
input [8:1] leaf3;
input [8:1] leaf4;
input [8:1] leaf5;
input [8:1] leaf6;
input [8:1] leaf7;
input [8:1] leaf8;
input [8:1] leaf9;
input [8:1] leaf10;
input [8:1] leaf11;
input [8:1] leaf12;
supply1 vdd;
supply0 gnd;
wire net_10, net_14, net_15, net_17, net_24, net_25, net_50;
wire [0:12] net_6;
jtag__jtagControl jtagCont_0(.TCK(TCK), .TDI(TDI), .TDIx(net_15), .TMS(TMS),
.TRSTb(TRSTb), .phi1_fb(net_24), .phi2_fb(net_10), .Cap(net_25),
.ExTest(ExTest), .SelBS(net_50), .SelDR({net_6[0], net_6[1], net_6[2],
net_6[3], net_6[4], net_6[5], net_6[6], net_6[7], net_6[8], net_6[9],
net_6[10], net_6[11], net_6[12]}), .Shft(net_17), .TDOb(TDOb),
.Upd(net_14), .phi1(net_24), .phi2(net_10));
jtag__jtagScanCtlGroup jtagScan_0(.TDI(TDI), .capture(net_25),
.phi1_in(net_24), .phi2_in(net_10), .selBS(net_50), .sel({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[5], net_6[6], net_6[7],
net_6[8], net_6[9], net_6[10], net_6[11], net_6[12]}), .shift(net_17),
.update(net_14), .TDO(net_15), .BS(BS[8:1]), .leaf0(leaf0[8:1]),
.leaf1(leaf1[8:1]), .leaf2(leaf2[8:1]), .leaf3(leaf3[8:1]),
.leaf4(leaf4[8:1]), .leaf5(leaf5[8:1]), .leaf6(leaf6[8:1]),
.leaf7(leaf7[8:1]), .leaf8(leaf8[8:1]), .leaf9(leaf9[8:1]),
.leaf10(leaf10[8:1]), .leaf11(leaf11[8:1]), .leaf12(leaf12[8:1]));
endmodule /* jtag__jtagCentral_LEIGNORE_1 */
module scanFansFour__jtag_endcap(jtag);
input [8:4] jtag;
endmodule /* scanFansFour__jtag_endcap */
module testCell(TCK, TDI, TMS, TRSTb, TDOb);
input TCK;
input TDI;
input TMS;
input TRSTb;
output TDOb;
supply1 vdd;
supply0 gnd;
wire jtagCent_0_ExTest;
wire [4:0] net_5;
wire [4:0] net_6;
wire [4:0] net_7;
wire [4:0] net_8;
wire [4:0] net_9;
wire [4:0] net_10;
wire [4:0] net_11;
wire [4:0] net_12;
wire [4:0] net_13;
wire [4:0] net_14;
wire [4:0] net_15;
wire [4:0] net_16;
wire [4:0] net_17;
wire [4:0] net_18;
jtag__jtagCentral_LEIGNORE_1 jtagCent_0(.TCK(TCK), .TDI(TDI), .TMS(TMS),
.TRSTb(TRSTb), .ExTest(jtagCent_0_ExTest), .TDOb(TDOb), .BS({net_6[0],
net_6[1], net_6[2], net_6[3], net_6[4], net_6[2], net_6[1], net_6[0]}),
.leaf0({net_7[0], net_7[1], net_7[2], net_7[3], net_7[4], net_7[2],
net_7[1], net_7[0]}), .leaf1({net_18[0], net_18[1], net_18[2], net_18[3],
net_18[4], net_18[2], net_18[1], net_18[0]}), .leaf2({net_17[0],
net_17[1], net_17[2], net_17[3], net_17[4], net_17[2], net_17[1],
net_17[0]}), .leaf3({net_16[0], net_16[1], net_16[2], net_16[3],
net_16[4], net_16[2], net_16[1], net_16[0]}), .leaf4({net_15[0],
net_15[1], net_15[2], net_15[3], net_15[4], net_15[2], net_15[1],
net_15[0]}), .leaf5({net_14[0], net_14[1], net_14[2], net_14[3],
net_14[4], net_14[2], net_14[1], net_14[0]}), .leaf6({net_13[0],
net_13[1], net_13[2], net_13[3], net_13[4], net_13[2], net_13[1],
net_13[0]}), .leaf7({net_12[0], net_12[1], net_12[2], net_12[3],
net_12[4], net_12[2], net_12[1], net_12[0]}), .leaf8({net_11[0],
net_11[1], net_11[2], net_11[3], net_11[4], net_11[2], net_11[1],
net_11[0]}), .leaf9({net_10[0], net_10[1], net_10[2], net_10[3],
net_10[4], net_10[2], net_10[1], net_10[0]}), .leaf10({net_9[0],
net_9[1], net_9[2], net_9[3], net_9[4], net_9[2], net_9[1], net_9[0]}),
.leaf11({net_8[0], net_8[1], net_8[2], net_8[3], net_8[4], net_8[2],
net_8[1], net_8[0]}), .leaf12({net_5[0], net_5[1], net_5[2], net_5[3],
net_5[4], net_5[2], net_5[1], net_5[0]}));
scanFansFour__jtag_endcap jtag_end_0(.jtag({net_5[0], net_5[1], net_5[2],
net_5[4], net_5[3]}));
scanFansFour__jtag_endcap jtag_end_1(.jtag({net_8[0], net_8[1], net_8[2],
net_8[4], net_8[3]}));
scanFansFour__jtag_endcap jtag_end_2(.jtag({net_9[0], net_9[1], net_9[2],
net_9[4], net_9[3]}));
scanFansFour__jtag_endcap jtag_end_3(.jtag({net_10[0], net_10[1], net_10[2],
net_10[4], net_10[3]}));
scanFansFour__jtag_endcap jtag_end_4(.jtag({net_11[0], net_11[1], net_11[2],
net_11[4], net_11[3]}));
scanFansFour__jtag_endcap jtag_end_5(.jtag({net_12[0], net_12[1], net_12[2],
net_12[4], net_12[3]}));
scanFansFour__jtag_endcap jtag_end_6(.jtag({net_13[0], net_13[1], net_13[2],
net_13[4], net_13[3]}));
scanFansFour__jtag_endcap jtag_end_7(.jtag({net_14[0], net_14[1], net_14[2],
net_14[4], net_14[3]}));
scanFansFour__jtag_endcap jtag_end_8(.jtag({net_15[0], net_15[1], net_15[2],
net_15[4], net_15[3]}));
scanFansFour__jtag_endcap jtag_end_9(.jtag({net_16[0], net_16[1], net_16[2],
net_16[4], net_16[3]}));
scanFansFour__jtag_endcap jtag_end_10(.jtag({net_17[0], net_17[1], net_17[2],
net_17[4], net_17[3]}));
scanFansFour__jtag_endcap jtag_end_11(.jtag({net_18[0], net_18[1], net_18[2],
net_18[4], net_18[3]}));
scanFansFour__jtag_endcap jtag_end_12(.jtag({net_7[0], net_7[1], net_7[2],
net_7[4], net_7[3]}));
scanFansFour__jtag_endcap jtag_end_13(.jtag({net_6[0], net_6[1], net_6[2],
net_6[4], net_6[3]}));
endmodule /* testCell */
|
// (C) 1992-2014 Altera Corporation. All rights reserved.
// Your use of Altera Corporation's design tools, logic functions and other
// software and tools, and its AMPP partner logic functions, and any output
// files any of the foregoing (including device programming or simulation
// files), and any associated documentation or information are expressly subject
// to the terms and conditions of the Altera Program License Subscription
// Agreement, Altera MegaCore Function License Agreement, or other applicable
// license agreement, including, without limitation, that your use is for the
// sole purpose of programming logic devices manufactured by Altera and sold by
// Altera or its authorized distributors. Please refer to the applicable
// agreement for further details.
module vfabric_pla(clock, resetn,
i_dataa, i_dataa_valid, o_dataa_stall, i_datab, i_datab_valid, o_datab_stall,
i_datac, i_datac_valid, o_datac_stall, i_datad, i_datad_valid, o_datad_stall,
o_dataout, o_dataout_valid, i_stall, i_settings, i_start);
parameter DATA_WIDTH = 1;
parameter CONFIG_WIDTH = 20;
parameter FIFO_DEPTH = 64;
//if upper bits are 0, it means the corresponding data port is not used
input clock, resetn;
input [DATA_WIDTH-1:0] i_dataa;
input [DATA_WIDTH-1:0] i_datab;
input [DATA_WIDTH-1:0] i_datac;
input [DATA_WIDTH-1:0] i_datad;
input i_dataa_valid, i_datab_valid, i_datac_valid, i_datad_valid;
output o_dataa_stall, o_datab_stall, o_datac_stall, o_datad_stall;
output [DATA_WIDTH-1:0] o_dataout;
output o_dataout_valid;
input i_stall;
input [CONFIG_WIDTH-1:0] i_settings;
input i_start;
wire [DATA_WIDTH-1:0] dataa;
wire [DATA_WIDTH-1:0] datab;
wire [DATA_WIDTH-1:0] datac;
wire [DATA_WIDTH-1:0] datad;
//wire [8*DATA_WIDTH-1:0] interim_data;
wire [4*DATA_WIDTH-1:0] interim_data;
wire fifo_a_valid_out;
wire fifo_b_valid_out;
wire fifo_c_valid_out;
wire fifo_d_valid_out;
wire is_fifo_a_valid;
wire is_fifo_b_valid;
wire is_fifo_c_valid;
wire is_fifo_d_valid;
wire is_stalled;
reg [DATA_WIDTH-1:0] and1a;
reg [DATA_WIDTH-1:0] and1b;
reg [DATA_WIDTH-1:0] and2a;
reg [DATA_WIDTH-1:0] and2b;
vfabric_buffered_fifo fifo_a ( .clock(clock), .resetn(resetn),
.data_in(i_dataa), .data_out(dataa), .valid_in(i_dataa_valid),
.valid_out( fifo_a_valid_out ), .stall_in(is_stalled), .stall_out(o_dataa_stall) );
defparam fifo_a.DATA_WIDTH = DATA_WIDTH;
defparam fifo_a.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_b ( .clock(clock), .resetn(resetn),
.data_in(i_datab), .data_out(datab), .valid_in(i_datab_valid),
.valid_out( fifo_b_valid_out ), .stall_in(is_stalled), .stall_out(o_datab_stall) );
defparam fifo_b.DATA_WIDTH = DATA_WIDTH;
defparam fifo_b.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_c ( .clock(clock), .resetn(resetn),
.data_in(i_datac), .data_out(datac), .valid_in(i_datac_valid),
.valid_out( fifo_c_valid_out ), .stall_in(is_stalled), .stall_out(o_datac_stall) );
defparam fifo_c.DATA_WIDTH = DATA_WIDTH;
defparam fifo_c.DEPTH = FIFO_DEPTH;
vfabric_buffered_fifo fifo_d ( .clock(clock), .resetn(resetn),
.data_in(i_datad), .data_out(datad), .valid_in(i_datad_valid),
.valid_out( fifo_d_valid_out ), .stall_in(is_stalled), .stall_out(o_datad_stall) );
defparam fifo_d.DATA_WIDTH = DATA_WIDTH;
defparam fifo_d.DEPTH = FIFO_DEPTH;
assign is_fifo_a_valid = fifo_a_valid_out | ~i_settings[16];
assign is_fifo_b_valid = fifo_b_valid_out | ~i_settings[17];
assign is_fifo_c_valid = fifo_c_valid_out | ~i_settings[18];
assign is_fifo_d_valid = fifo_d_valid_out | ~i_settings[19];
assign is_stalled = ~(is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid & ~i_stall);
genvar i;
generate
for(i = 0; i < DATA_WIDTH; i++)
begin : pla_gen
assign interim_data[4*(i+1)-1:4*i] = {datad[i], datac[i], datab[i], dataa[i]};
assign o_dataout[i] = i_settings[interim_data[4*(i+1)-1:4*i]];
end
endgenerate
//assign interim_data = {datad, datac, datab, dataa};
//assign o_dataout = i_settings[interim_data];
// assign interim_data = {datad, datac, datab, dataa, !datad, !datac, !datab, !dataa};
// assign o_dataout = (interim_data[i_settings[11:9]] & interim_data[i_settings[8:6]] & interim_data[i_settings[5:3]] & interim_data[i_settings[2:0]])
// + (interim_data[i_settings[23:21]] & interim_data[i_settings[20:18]] & interim_data[i_settings[17:15]] & interim_data[i_settings[14:12]]);
assign o_dataout_valid = i_start & is_fifo_a_valid & is_fifo_b_valid & is_fifo_c_valid & is_fifo_d_valid;
endmodule
|
// -*- verilog -*-
//
// USRP - Universal Software Radio Peripheral
//
// Copyright (C) 2003 Matt Ettus
//
// This program is free software; you can redistribute it and/or modify
// it under the terms of the GNU General Public License as published by
// the Free Software Foundation; either version 2 of the License, or
// (at your option) any later version.
//
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
// GNU General Public License for more details.
//
// You should have received a copy of the GNU General Public License
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
// Sign extension "macro"
// bits_out should be greater than bits_in
module sign_extend (in,out);
parameter bits_in=0; // FIXME Quartus insists on a default
parameter bits_out=0;
input [bits_in-1:0] in;
output [bits_out-1:0] out;
assign out = {{(bits_out-bits_in){in[bits_in-1]}},in};
endmodule
|
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_HS__DLXTN_SYMBOL_V
`define SKY130_FD_SC_HS__DLXTN_SYMBOL_V
/**
* dlxtn: Delay latch, inverted enable, single output.
*
* Verilog stub (without power pins) for graphical symbol definition
* generation.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
(* blackbox *)
module sky130_fd_sc_hs__dlxtn (
//# {{data|Data Signals}}
input D ,
output Q ,
//# {{clocks|Clocking}}
input GATE_N
);
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
endmodule
`default_nettype wire
`endif // SKY130_FD_SC_HS__DLXTN_SYMBOL_V
|
// megafunction wizard: %ALTGX_RECONFIG%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb_reconfig
// ============================================================
// File Name: altpcie_reconfig_3cgx.v
// Megafunction Name(s):
// alt_c3gxb_reconfig
//
// Simulation Library Files(s):
//
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
//
// 10.1 Internal Build 128 10/05/2010 SJ Full Version
// ************************************************************
//Copyright (C) 1991-2010 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
//alt_c3gxb_reconfig CBX_AUTO_BLACKBOX="ALL" DEVICE_FAMILY="Cyclone IV GX" ENABLE_BUF_CAL="TRUE" NUMBER_OF_CHANNELS=4 NUMBER_OF_RECONFIG_PORTS=1 RECONFIG_FROMGXB_WIDTH=5 RECONFIG_TOGXB_WIDTH=4 busy offset_cancellation_reset reconfig_clk reconfig_fromgxb reconfig_togxb
//VERSION_BEGIN 10.1 cbx_alt_c3gxb_reconfig 2010:10:05:21:13:55:SJ cbx_alt_cal 2010:10:05:21:13:55:SJ cbx_alt_dprio 2010:10:05:21:13:55:SJ cbx_altsyncram 2010:10:05:21:13:55:SJ cbx_cycloneii 2010:10:05:21:13:55:SJ cbx_lpm_add_sub 2010:10:05:21:13:55:SJ cbx_lpm_compare 2010:10:05:21:13:55:SJ cbx_lpm_counter 2010:10:05:21:13:55:SJ cbx_lpm_decode 2010:10:05:21:13:55:SJ cbx_lpm_mux 2010:10:05:21:13:55:SJ cbx_lpm_shiftreg 2010:10:05:21:13:55:SJ cbx_mgl 2010:10:05:21:28:31:SJ cbx_stratix 2010:10:05:21:13:55:SJ cbx_stratixii 2010:10:05:21:13:55:SJ cbx_stratixiii 2010:10:05:21:13:55:SJ cbx_stratixv 2010:10:05:21:13:55:SJ cbx_util_mgl 2010:10:05:21:13:55:SJ VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//alt_dprio address_width=16 CBX_AUTO_BLACKBOX="ALL" device_family="Cyclone IV GX" quad_address_width=9 address busy datain dataout dpclk dpriodisable dprioin dprioload dprioout quad_address rden reset wren wren_data
//VERSION_BEGIN 10.1 cbx_alt_dprio 2010:10:05:21:13:55:SJ cbx_cycloneii 2010:10:05:21:13:55:SJ cbx_lpm_add_sub 2010:10:05:21:13:55:SJ cbx_lpm_compare 2010:10:05:21:13:55:SJ cbx_lpm_counter 2010:10:05:21:13:55:SJ cbx_lpm_decode 2010:10:05:21:13:55:SJ cbx_lpm_shiftreg 2010:10:05:21:13:55:SJ cbx_mgl 2010:10:05:21:28:31:SJ cbx_stratix 2010:10:05:21:13:55:SJ cbx_stratixii 2010:10:05:21:13:55:SJ VERSION_END
//synthesis_resources = lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 102
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to addr_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to wr_out_data_shift_reg[31]} DPRIO_INTERFACE_REG=ON;{-to rd_out_data_shift_reg[13]} DPRIO_INTERFACE_REG=ON;{-to in_data_shift_reg[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[0]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[1]} DPRIO_INTERFACE_REG=ON;{-to startup_cntr[2]} DPRIO_INTERFACE_REG=ON"} *)
module altpcie_reconfig_3cgx_alt_dprio_v5k
(
address,
busy,
datain,
dataout,
dpclk,
dpriodisable,
dprioin,
dprioload,
dprioout,
quad_address,
rden,
reset,
wren,
wren_data) /* synthesis synthesis_clearbox=2 */;
input [15:0] address;
output busy;
input [15:0] datain;
output [15:0] dataout;
input dpclk;
output dpriodisable;
output dprioin;
output dprioload;
input dprioout;
input [8:0] quad_address;
input rden;
input reset;
input wren;
input wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 [15:0] datain;
tri0 rden;
tri0 reset;
tri0 wren;
tri0 wren_data;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] addr_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] in_data_shift_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [15:0] rd_out_data_shift_reg;
wire [2:0] wire_startup_cntr_d;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [2:0] startup_cntr;
wire [2:0] wire_startup_cntr_ena;
(* ALTERA_ATTRIBUTE = {"POWER_UP_LEVEL=LOW"} *)
reg [2:0] state_mc_reg;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON;POWER_UP_LEVEL=LOW"} *)
reg [31:0] wr_out_data_shift_reg;
wire wire_pre_amble_cmpr_aeb;
wire wire_pre_amble_cmpr_agb;
wire wire_rd_data_output_cmpr_ageb;
wire wire_rd_data_output_cmpr_alb;
wire wire_state_mc_cmpr_aeb;
wire [5:0] wire_state_mc_counter_q;
wire [7:0] wire_state_mc_decode_eq;
wire wire_dprioin_mux_dataout;
wire busy_state;
wire idle_state;
wire rd_addr_done;
wire rd_addr_state;
wire rd_data_done;
wire rd_data_input_state;
wire rd_data_output_state;
wire rd_data_state;
wire rdinc;
wire read_state;
wire s0_to_0;
wire s0_to_1;
wire s1_to_0;
wire s1_to_1;
wire s2_to_0;
wire s2_to_1;
wire startup_done;
wire startup_idle;
wire wr_addr_done;
wire wr_addr_state;
wire wr_data_done;
wire wr_data_state;
wire write_state;
// synopsys translate_off
initial
addr_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) addr_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) addr_shift_reg <= {{2{{2{1'b0}}}}, 1'b0, quad_address[8:0], 2'b10, address};
else addr_shift_reg <= {addr_shift_reg[30:0], 1'b0};
// synopsys translate_off
initial
in_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) in_data_shift_reg <= 16'b0;
else if (rd_data_input_state == 1'b1) in_data_shift_reg <= {in_data_shift_reg[14:0], dprioout};
// synopsys translate_off
initial
rd_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) rd_out_data_shift_reg <= 16'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) rd_out_data_shift_reg <= {{2{1'b0}}, {2{1'b1}}, 1'b0, quad_address, 2'b10};
else rd_out_data_shift_reg <= {rd_out_data_shift_reg[14:0], 1'b0};
// synopsys translate_off
initial
startup_cntr[0:0] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[0:0] == 1'b1)
if (reset == 1'b1) startup_cntr[0:0] <= 1'b0;
else startup_cntr[0:0] <= wire_startup_cntr_d[0:0];
// synopsys translate_off
initial
startup_cntr[1:1] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[1:1] == 1'b1)
if (reset == 1'b1) startup_cntr[1:1] <= 1'b0;
else startup_cntr[1:1] <= wire_startup_cntr_d[1:1];
// synopsys translate_off
initial
startup_cntr[2:2] = 0;
// synopsys translate_on
always @ ( posedge dpclk)
if (wire_startup_cntr_ena[2:2] == 1'b1)
if (reset == 1'b1) startup_cntr[2:2] <= 1'b0;
else startup_cntr[2:2] <= wire_startup_cntr_d[2:2];
assign
wire_startup_cntr_d = {(startup_cntr[2] ^ (startup_cntr[1] & startup_cntr[0])), (startup_cntr[0] ^ startup_cntr[1]), (~ startup_cntr[0])};
assign
wire_startup_cntr_ena = {3{((((rden | wren) | rdinc) | (~ startup_idle)) & (~ startup_done))}};
// synopsys translate_off
initial
state_mc_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) state_mc_reg <= 3'b0;
else state_mc_reg <= {(s2_to_1 | (((~ s2_to_0) & (~ s2_to_1)) & state_mc_reg[2])), (s1_to_1 | (((~ s1_to_0) & (~ s1_to_1)) & state_mc_reg[1])), (s0_to_1 | (((~ s0_to_0) & (~ s0_to_1)) & state_mc_reg[0]))};
// synopsys translate_off
initial
wr_out_data_shift_reg = 0;
// synopsys translate_on
always @ ( posedge dpclk or posedge reset)
if (reset == 1'b1) wr_out_data_shift_reg <= 32'b0;
else
if (wire_pre_amble_cmpr_aeb == 1'b1) wr_out_data_shift_reg <= {{2{1'b0}}, 2'b01, 1'b0, quad_address[8:0], 2'b10, datain};
else wr_out_data_shift_reg <= {wr_out_data_shift_reg[30:0], 1'b0};
lpm_compare pre_amble_cmpr
(
.aeb(wire_pre_amble_cmpr_aeb),
.agb(wire_pre_amble_cmpr_agb),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b011111)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
pre_amble_cmpr.lpm_width = 6,
pre_amble_cmpr.lpm_type = "lpm_compare";
lpm_compare rd_data_output_cmpr
(
.aeb(),
.agb(),
.ageb(wire_rd_data_output_cmpr_ageb),
.alb(wire_rd_data_output_cmpr_alb),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab(6'b110000)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
rd_data_output_cmpr.lpm_width = 6,
rd_data_output_cmpr.lpm_type = "lpm_compare";
lpm_compare state_mc_cmpr
(
.aeb(wire_state_mc_cmpr_aeb),
.agb(),
.ageb(),
.alb(),
.aleb(),
.aneb(),
.dataa(wire_state_mc_counter_q),
.datab({6{1'b1}})
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_cmpr.lpm_width = 6,
state_mc_cmpr.lpm_type = "lpm_compare";
lpm_counter state_mc_counter
(
.clock(dpclk),
.cnt_en((write_state | read_state)),
.cout(),
.eq(),
.q(wire_state_mc_counter_q),
.sclr(reset)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.aload(1'b0),
.aset(1'b0),
.cin(1'b1),
.clk_en(1'b1),
.data({6{1'b0}}),
.sload(1'b0),
.sset(1'b0),
.updown(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_counter.lpm_port_updown = "PORT_UNUSED",
state_mc_counter.lpm_width = 6,
state_mc_counter.lpm_type = "lpm_counter";
lpm_decode state_mc_decode
(
.data(state_mc_reg),
.eq(wire_state_mc_decode_eq)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.aclr(1'b0),
.clken(1'b1),
.clock(1'b0),
.enable(1'b1)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
state_mc_decode.lpm_decodes = 8,
state_mc_decode.lpm_width = 3,
state_mc_decode.lpm_type = "lpm_decode";
or(wire_dprioin_mux_dataout, ((((((wr_addr_state | rd_addr_state) & addr_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & (wr_addr_state | rd_addr_state))) | (((wr_data_state & wr_out_data_shift_reg[31]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & wr_data_state))) | (((rd_data_output_state & rd_out_data_shift_reg[15]) & wire_pre_amble_cmpr_agb) | ((~ wire_pre_amble_cmpr_agb) & rd_data_output_state))), ~(((write_state | rd_addr_state) | rd_data_output_state)));
assign
busy = busy_state,
busy_state = (write_state | read_state),
dataout = in_data_shift_reg,
dpriodisable = (~ (startup_cntr[2] & (startup_cntr[0] | startup_cntr[1]))),
dprioin = wire_dprioin_mux_dataout,
dprioload = (~ ((startup_cntr[0] ^ startup_cntr[1]) & (~ startup_cntr[2]))),
idle_state = wire_state_mc_decode_eq[0],
rd_addr_done = (rd_addr_state & wire_state_mc_cmpr_aeb),
rd_addr_state = (wire_state_mc_decode_eq[5] & startup_done),
rd_data_done = (rd_data_state & wire_state_mc_cmpr_aeb),
rd_data_input_state = (wire_rd_data_output_cmpr_ageb & rd_data_state),
rd_data_output_state = (wire_rd_data_output_cmpr_alb & rd_data_state),
rd_data_state = (wire_state_mc_decode_eq[7] & startup_done),
rdinc = 1'b0,
read_state = (rd_addr_state | rd_data_state),
s0_to_0 = ((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)),
s0_to_1 = (((idle_state & (wren | ((~ wren) & ((rden | rdinc) | wren_data)))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s1_to_0 = (((wr_data_state & wr_data_done) | (rd_data_state & rd_data_done)) | (idle_state & (wren | (((~ wren) & (~ wren_data)) & rden)))),
s1_to_1 = (((idle_state & ((~ wren) & (rdinc | wren_data))) | (wr_addr_state & wr_addr_done)) | (rd_addr_state & rd_addr_done)),
s2_to_0 = ((((wr_addr_state & wr_addr_done) | (wr_data_state & wr_data_done)) | (rd_data_state & rd_data_done)) | (idle_state & (wren | wren_data))),
s2_to_1 = ((idle_state & (((~ wren) & (~ wren_data)) & (rdinc | rden))) | (rd_addr_state & rd_addr_done)),
startup_done = ((startup_cntr[2] & (~ startup_cntr[0])) & startup_cntr[1]),
startup_idle = ((~ startup_cntr[0]) & (~ (startup_cntr[2] ^ startup_cntr[1]))),
wr_addr_done = (wr_addr_state & wire_state_mc_cmpr_aeb),
wr_addr_state = (wire_state_mc_decode_eq[1] & startup_done),
wr_data_done = (wr_data_state & wire_state_mc_cmpr_aeb),
wr_data_state = (wire_state_mc_decode_eq[3] & startup_done),
write_state = (wr_addr_state | wr_data_state);
endmodule //altpcie_reconfig_3cgx_alt_dprio_v5k
//synthesis_resources = alt_cal_c3gxb 1 lpm_compare 3 lpm_counter 1 lpm_decode 1 lut 1 reg 114
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {"{-to address_pres_reg[11]} DPRIO_CHANNEL_NUM=11;{-to address_pres_reg[10]} DPRIO_CHANNEL_NUM=10;{-to address_pres_reg[9]} DPRIO_CHANNEL_NUM=9;{-to address_pres_reg[8]} DPRIO_CHANNEL_NUM=8;{-to address_pres_reg[7]} DPRIO_CHANNEL_NUM=7;{-to address_pres_reg[6]} DPRIO_CHANNEL_NUM=6;{-to address_pres_reg[5]} DPRIO_CHANNEL_NUM=5;{-to address_pres_reg[4]} DPRIO_CHANNEL_NUM=4;{-to address_pres_reg[3]} DPRIO_CHANNEL_NUM=3;{-to address_pres_reg[2]} DPRIO_CHANNEL_NUM=2;{-to address_pres_reg[1]} DPRIO_CHANNEL_NUM=1;{-to address_pres_reg[0]} DPRIO_CHANNEL_NUM=0"} *)
module altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp
(
busy,
offset_cancellation_reset,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb) /* synthesis synthesis_clearbox=2 */;
output busy;
input offset_cancellation_reset;
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output [3:0] reconfig_togxb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 offset_cancellation_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire wire_calibration_c3gxb_busy;
wire [15:0] wire_calibration_c3gxb_dprio_addr;
wire [15:0] wire_calibration_c3gxb_dprio_dataout;
wire wire_calibration_c3gxb_dprio_rden;
wire wire_calibration_c3gxb_dprio_wren;
wire [8:0] wire_calibration_c3gxb_quad_addr;
wire wire_calibration_c3gxb_retain_addr;
wire wire_dprio_busy;
wire [15:0] wire_dprio_dataout;
wire wire_dprio_dpriodisable;
wire wire_dprio_dprioin;
wire wire_dprio_dprioload;
(* ALTERA_ATTRIBUTE = {"PRESERVE_REGISTER=ON"} *)
reg [11:0] address_pres_reg;
wire cal_busy;
wire [0:0] cal_dprioout_wire;
wire [3:0] cal_testbuses;
wire [2:0] channel_address;
wire [15:0] dprio_address;
wire [8:0] quad_address;
wire reconfig_reset_all;
alt_cal_c3gxb calibration_c3gxb
(
.busy(wire_calibration_c3gxb_busy),
.cal_error(),
.clock(reconfig_clk),
.dprio_addr(wire_calibration_c3gxb_dprio_addr),
.dprio_busy(wire_dprio_busy),
.dprio_datain(wire_dprio_dataout),
.dprio_dataout(wire_calibration_c3gxb_dprio_dataout),
.dprio_rden(wire_calibration_c3gxb_dprio_rden),
.dprio_wren(wire_calibration_c3gxb_dprio_wren),
.quad_addr(wire_calibration_c3gxb_quad_addr),
.remap_addr(address_pres_reg),
.reset((offset_cancellation_reset | reconfig_reset_all)),
.retain_addr(wire_calibration_c3gxb_retain_addr),
.testbuses(cal_testbuses)
`ifndef FORMAL_VERIFICATION
// synopsys translate_off
`endif
,
.start(1'b0)
`ifndef FORMAL_VERIFICATION
// synopsys translate_on
`endif
);
defparam
calibration_c3gxb.channel_address_width = 2,
calibration_c3gxb.number_of_channels = 4,
calibration_c3gxb.sim_model_mode = "FALSE",
calibration_c3gxb.lpm_type = "alt_cal_c3gxb";
altpcie_reconfig_3cgx_alt_dprio_v5k dprio
(
.address(({16{wire_calibration_c3gxb_busy}} & dprio_address)),
.busy(wire_dprio_busy),
.datain(({16{wire_calibration_c3gxb_busy}} & wire_calibration_c3gxb_dprio_dataout)),
.dataout(wire_dprio_dataout),
.dpclk(reconfig_clk),
.dpriodisable(wire_dprio_dpriodisable),
.dprioin(wire_dprio_dprioin),
.dprioload(wire_dprio_dprioload),
.dprioout(cal_dprioout_wire),
.quad_address(address_pres_reg[11:3]),
.rden((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_rden)),
.reset(reconfig_reset_all),
.wren((wire_calibration_c3gxb_busy & wire_calibration_c3gxb_dprio_wren)),
.wren_data(wire_calibration_c3gxb_retain_addr));
// synopsys translate_off
initial
address_pres_reg = 0;
// synopsys translate_on
always @ ( posedge reconfig_clk or posedge reconfig_reset_all)
if (reconfig_reset_all == 1'b1) address_pres_reg <= 12'b0;
else address_pres_reg <= {quad_address, channel_address};
assign
busy = cal_busy,
cal_busy = wire_calibration_c3gxb_busy,
cal_dprioout_wire = {reconfig_fromgxb[0]},
cal_testbuses = {reconfig_fromgxb[4:1]},
channel_address = wire_calibration_c3gxb_dprio_addr[14:12],
dprio_address = {wire_calibration_c3gxb_dprio_addr[15], address_pres_reg[2:0], wire_calibration_c3gxb_dprio_addr[11:0]},
quad_address = wire_calibration_c3gxb_quad_addr,
reconfig_reset_all = 1'b0,
reconfig_togxb = {wire_calibration_c3gxb_busy, wire_dprio_dprioload, wire_dprio_dpriodisable, wire_dprio_dprioin};
endmodule //altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp
//VALID FILE
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module altpcie_reconfig_3cgx (
offset_cancellation_reset,
reconfig_clk,
reconfig_fromgxb,
busy,
reconfig_togxb)/* synthesis synthesis_clearbox = 2 */;
input offset_cancellation_reset;
input reconfig_clk;
input [4:0] reconfig_fromgxb;
output busy;
output [3:0] reconfig_togxb;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`endif
tri0 offset_cancellation_reset;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
`endif
wire [3:0] sub_wire0;
wire sub_wire1;
wire [3:0] reconfig_togxb = sub_wire0[3:0];
wire busy = sub_wire1;
altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp altpcie_reconfig_3cgx_alt_c3gxb_reconfig_ffp_component (
.reconfig_clk (reconfig_clk),
.offset_cancellation_reset (offset_cancellation_reset),
.reconfig_fromgxb (reconfig_fromgxb),
.reconfig_togxb (sub_wire0),
.busy (sub_wire1))/* synthesis synthesis_clearbox=2
clearbox_macroname = alt_c3gxb_reconfig
clearbox_defparam = "cbx_blackbox_list=-lpm_mux;intended_device_family=Cyclone IV GX;number_of_channels=4;number_of_reconfig_ports=1;enable_buf_cal=true;reconfig_fromgxb_width=5;reconfig_togxb_width=4;" */;
endmodule
// ============================================================
// CNX file retrieval info
// ============================================================
// Retrieval info: PRIVATE: ADCE NUMERIC "0"
// Retrieval info: PRIVATE: CMU_PLL NUMERIC "0"
// Retrieval info: PRIVATE: DATA_RATE NUMERIC "0"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: PRIVATE: PMA NUMERIC "0"
// Retrieval info: PRIVATE: PROTO_SWITCH NUMERIC "0"
// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
// Retrieval info: CONSTANT: CBX_BLACKBOX_LIST STRING "-lpm_mux"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
// Retrieval info: CONSTANT: NUMBER_OF_CHANNELS NUMERIC "4"
// Retrieval info: CONSTANT: NUMBER_OF_RECONFIG_PORTS NUMERIC "1"
// Retrieval info: CONSTANT: enable_buf_cal STRING "true"
// Retrieval info: CONSTANT: reconfig_fromgxb_width NUMERIC "5"
// Retrieval info: CONSTANT: reconfig_togxb_width NUMERIC "4"
// Retrieval info: USED_PORT: busy 0 0 0 0 OUTPUT NODEFVAL "busy"
// Retrieval info: USED_PORT: reconfig_clk 0 0 0 0 INPUT NODEFVAL "reconfig_clk"
// Retrieval info: USED_PORT: reconfig_fromgxb 0 0 5 0 INPUT NODEFVAL "reconfig_fromgxb[4..0]"
// Retrieval info: USED_PORT: reconfig_togxb 0 0 4 0 OUTPUT NODEFVAL "reconfig_togxb[3..0]"
// Retrieval info: CONNECT: @reconfig_clk 0 0 0 0 reconfig_clk 0 0 0 0
// Retrieval info: CONNECT: @reconfig_fromgxb 0 0 5 0 reconfig_fromgxb 0 0 5 0
// Retrieval info: CONNECT: busy 0 0 0 0 @busy 0 0 0 0
// Retrieval info: CONNECT: reconfig_togxb 0 0 4 0 @reconfig_togxb 0 0 4 0
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.v TRUE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.inc FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.cmp FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx.bsf FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx_inst.v FALSE
// Retrieval info: GEN_FILE: TYPE_NORMAL altpcie_reconfig_3cgx_bb.v TRUE
|
// Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
// --------------------------------------------------------------------------------
// Tool Version: Vivado v.2016.2 (lin64) Build 1577090 Thu Jun 2 16:32:35 MDT 2016
// Date : Sun Sep 25 18:34:17 2016
// Host : jorge-pc running 64-bit Ubuntu 16.04.1 LTS
// Command : write_verilog -mode funcsim -nolib -force -file
// /home/jorge/Documents/Karatsuba_FPU/Add_Sub/ADD_SUB_PIPELINED/ADD_SUB_FUNCIONAL_v1.sim/vector_simulation_add/synth/func/tb_FPU_PIPELINED_FPADDSUB2_vector_testing_func_synth.v
// Design : FPU_PIPELINED_FPADDSUB
// Purpose : This verilog netlist is a functional simulation representation of the design and should not be modified
// or synthesized. This netlist cannot be used for SDF annotated simulation.
// Device : xc7a100tcsg324-1
// --------------------------------------------------------------------------------
`timescale 1 ps / 1 ps
module Comparator
(CO,
\Q_reg[0] ,
D,
DI,
S,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
\Q_reg[30] ,
\Q_reg[30]_0 ,
\Q_reg[9] ,
\Q_reg[21] ,
\Q_reg[30]_1 ,
intAS,
Q,
\Q_reg[31] );
output [0:0]CO;
output [0:0]\Q_reg[0] ;
output [0:0]D;
input [3:0]DI;
input [3:0]S;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [3:0]\Q_reg[30] ;
input [3:0]\Q_reg[30]_0 ;
input [3:0]\Q_reg[9] ;
input [3:0]\Q_reg[21] ;
input [2:0]\Q_reg[30]_1 ;
input intAS;
input [0:0]Q;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [3:0]DI;
wire [0:0]Q;
wire [0:0]\Q_reg[0] ;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[21] ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[30] ;
wire [3:0]\Q_reg[30]_0 ;
wire [2:0]\Q_reg[30]_1 ;
wire [0:0]\Q_reg[31] ;
wire [3:0]\Q_reg[9] ;
wire [3:0]S;
wire eqXY_o_carry__0_n_0;
wire eqXY_o_carry__0_n_1;
wire eqXY_o_carry__0_n_2;
wire eqXY_o_carry__0_n_3;
wire eqXY_o_carry__1_n_2;
wire eqXY_o_carry__1_n_3;
wire eqXY_o_carry_n_0;
wire eqXY_o_carry_n_1;
wire eqXY_o_carry_n_2;
wire eqXY_o_carry_n_3;
wire gtXY_o_carry__0_n_0;
wire gtXY_o_carry__0_n_1;
wire gtXY_o_carry__0_n_2;
wire gtXY_o_carry__0_n_3;
wire gtXY_o_carry__1_n_0;
wire gtXY_o_carry__1_n_1;
wire gtXY_o_carry__1_n_2;
wire gtXY_o_carry__1_n_3;
wire gtXY_o_carry__2_n_1;
wire gtXY_o_carry__2_n_2;
wire gtXY_o_carry__2_n_3;
wire gtXY_o_carry_n_0;
wire gtXY_o_carry_n_1;
wire gtXY_o_carry_n_2;
wire gtXY_o_carry_n_3;
wire intAS;
wire [3:0]NLW_eqXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__0_O_UNCONNECTED;
wire [3:3]NLW_eqXY_o_carry__1_CO_UNCONNECTED;
wire [3:0]NLW_eqXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__0_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__1_O_UNCONNECTED;
wire [3:0]NLW_gtXY_o_carry__2_O_UNCONNECTED;
LUT4 #(
.INIT(16'h8228))
\Q[0]_i_1__1
(.I0(\Q_reg[0] ),
.I1(intAS),
.I2(Q),
.I3(\Q_reg[31] ),
.O(D));
CARRY4 eqXY_o_carry
(.CI(1'b0),
.CO({eqXY_o_carry_n_0,eqXY_o_carry_n_1,eqXY_o_carry_n_2,eqXY_o_carry_n_3}),
.CYINIT(1'b1),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry_O_UNCONNECTED[3:0]),
.S(\Q_reg[9] ));
CARRY4 eqXY_o_carry__0
(.CI(eqXY_o_carry_n_0),
.CO({eqXY_o_carry__0_n_0,eqXY_o_carry__0_n_1,eqXY_o_carry__0_n_2,eqXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[21] ));
CARRY4 eqXY_o_carry__1
(.CI(eqXY_o_carry__0_n_0),
.CO({NLW_eqXY_o_carry__1_CO_UNCONNECTED[3],\Q_reg[0] ,eqXY_o_carry__1_n_2,eqXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O(NLW_eqXY_o_carry__1_O_UNCONNECTED[3:0]),
.S({1'b0,\Q_reg[30]_1 }));
CARRY4 gtXY_o_carry
(.CI(1'b0),
.CO({gtXY_o_carry_n_0,gtXY_o_carry_n_1,gtXY_o_carry_n_2,gtXY_o_carry_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(NLW_gtXY_o_carry_O_UNCONNECTED[3:0]),
.S(S));
CARRY4 gtXY_o_carry__0
(.CI(gtXY_o_carry_n_0),
.CO({gtXY_o_carry__0_n_0,gtXY_o_carry__0_n_1,gtXY_o_carry__0_n_2,gtXY_o_carry__0_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[14] ),
.O(NLW_gtXY_o_carry__0_O_UNCONNECTED[3:0]),
.S(\Q_reg[14]_0 ));
CARRY4 gtXY_o_carry__1
(.CI(gtXY_o_carry__0_n_0),
.CO({gtXY_o_carry__1_n_0,gtXY_o_carry__1_n_1,gtXY_o_carry__1_n_2,gtXY_o_carry__1_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[22] ),
.O(NLW_gtXY_o_carry__1_O_UNCONNECTED[3:0]),
.S(\Q_reg[22]_0 ));
CARRY4 gtXY_o_carry__2
(.CI(gtXY_o_carry__1_n_0),
.CO({CO,gtXY_o_carry__2_n_1,gtXY_o_carry__2_n_2,gtXY_o_carry__2_n_3}),
.CYINIT(1'b0),
.DI(\Q_reg[30] ),
.O(NLW_gtXY_o_carry__2_O_UNCONNECTED[3:0]),
.S(\Q_reg[30]_0 ));
endmodule
(* EW = "8" *) (* EWR = "5" *) (* SW = "23" *)
(* SWR = "26" *) (* W = "32" *)
(* NotValidForBitStream *)
module FPU_PIPELINED_FPADDSUB
(clk,
rst,
beg_OP,
Data_X,
Data_Y,
add_subt,
busy,
overflow_flag,
underflow_flag,
zero_flag,
ready,
final_result_ieee);
input clk;
input rst;
input beg_OP;
input [31:0]Data_X;
input [31:0]Data_Y;
input add_subt;
output busy;
output overflow_flag;
output underflow_flag;
output zero_flag;
output ready;
output [31:0]final_result_ieee;
wire ADD_OVRFLW_NRM;
wire ADD_OVRFLW_SGF;
wire [24:2]DMP_mant_SFG_SWR;
wire [31:0]Data_X;
wire [31:0]Data_X_IBUF;
wire [31:0]Data_Y;
wire [31:0]Data_Y_IBUF;
wire [25:0]\Data_array_SWR[2] ;
wire [25:18]\Data_array_SWR[3] ;
wire [15:14]\Data_array_SWR[4] ;
wire [17:2]\Data_array_SWR[5] ;
wire [25:1]\Data_array_SWR[6] ;
wire EXP_STAGE_DMP_n_1;
wire EXP_STAGE_DMP_n_10;
wire EXP_STAGE_DMP_n_11;
wire EXP_STAGE_DMP_n_12;
wire EXP_STAGE_DMP_n_13;
wire EXP_STAGE_DMP_n_14;
wire EXP_STAGE_DMP_n_15;
wire EXP_STAGE_DMP_n_16;
wire EXP_STAGE_DMP_n_17;
wire EXP_STAGE_DMP_n_18;
wire EXP_STAGE_DMP_n_19;
wire EXP_STAGE_DMP_n_2;
wire EXP_STAGE_DMP_n_20;
wire EXP_STAGE_DMP_n_21;
wire EXP_STAGE_DMP_n_22;
wire EXP_STAGE_DMP_n_23;
wire EXP_STAGE_DMP_n_24;
wire EXP_STAGE_DMP_n_25;
wire EXP_STAGE_DMP_n_26;
wire EXP_STAGE_DMP_n_27;
wire EXP_STAGE_DMP_n_28;
wire EXP_STAGE_DMP_n_29;
wire EXP_STAGE_DMP_n_3;
wire EXP_STAGE_DMP_n_30;
wire EXP_STAGE_DMP_n_31;
wire EXP_STAGE_DMP_n_32;
wire EXP_STAGE_DMP_n_4;
wire EXP_STAGE_DMP_n_5;
wire EXP_STAGE_DMP_n_6;
wire EXP_STAGE_DMP_n_7;
wire EXP_STAGE_DMP_n_8;
wire EXP_STAGE_DMP_n_9;
wire EXP_STAGE_DmP_n_10;
wire EXP_STAGE_DmP_n_11;
wire EXP_STAGE_DmP_n_12;
wire EXP_STAGE_DmP_n_13;
wire EXP_STAGE_DmP_n_14;
wire EXP_STAGE_DmP_n_15;
wire EXP_STAGE_DmP_n_16;
wire EXP_STAGE_DmP_n_17;
wire EXP_STAGE_DmP_n_18;
wire EXP_STAGE_DmP_n_19;
wire EXP_STAGE_DmP_n_20;
wire EXP_STAGE_DmP_n_21;
wire EXP_STAGE_DmP_n_22;
wire EXP_STAGE_DmP_n_23;
wire EXP_STAGE_DmP_n_24;
wire EXP_STAGE_DmP_n_25;
wire EXP_STAGE_DmP_n_26;
wire EXP_STAGE_DmP_n_27;
wire EXP_STAGE_DmP_n_28;
wire EXP_STAGE_DmP_n_3;
wire EXP_STAGE_DmP_n_4;
wire EXP_STAGE_DmP_n_5;
wire EXP_STAGE_DmP_n_6;
wire EXP_STAGE_DmP_n_7;
wire EXP_STAGE_DmP_n_8;
wire EXP_STAGE_DmP_n_9;
wire EXP_STAGE_FLAGS_n_0;
wire EXP_STAGE_FLAGS_n_1;
wire EXP_STAGE_FLAGS_n_2;
wire FSM_enable_input_internal;
wire INPUT_STAGE_OPERANDX_n_0;
wire INPUT_STAGE_OPERANDX_n_1;
wire INPUT_STAGE_OPERANDX_n_10;
wire INPUT_STAGE_OPERANDX_n_11;
wire INPUT_STAGE_OPERANDX_n_12;
wire INPUT_STAGE_OPERANDX_n_13;
wire INPUT_STAGE_OPERANDX_n_14;
wire INPUT_STAGE_OPERANDX_n_15;
wire INPUT_STAGE_OPERANDX_n_16;
wire INPUT_STAGE_OPERANDX_n_17;
wire INPUT_STAGE_OPERANDX_n_18;
wire INPUT_STAGE_OPERANDX_n_19;
wire INPUT_STAGE_OPERANDX_n_2;
wire INPUT_STAGE_OPERANDX_n_20;
wire INPUT_STAGE_OPERANDX_n_21;
wire INPUT_STAGE_OPERANDX_n_22;
wire INPUT_STAGE_OPERANDX_n_23;
wire INPUT_STAGE_OPERANDX_n_24;
wire INPUT_STAGE_OPERANDX_n_25;
wire INPUT_STAGE_OPERANDX_n_26;
wire INPUT_STAGE_OPERANDX_n_27;
wire INPUT_STAGE_OPERANDX_n_28;
wire INPUT_STAGE_OPERANDX_n_29;
wire INPUT_STAGE_OPERANDX_n_3;
wire INPUT_STAGE_OPERANDX_n_30;
wire INPUT_STAGE_OPERANDX_n_31;
wire INPUT_STAGE_OPERANDX_n_32;
wire INPUT_STAGE_OPERANDX_n_33;
wire INPUT_STAGE_OPERANDX_n_34;
wire INPUT_STAGE_OPERANDX_n_35;
wire INPUT_STAGE_OPERANDX_n_36;
wire INPUT_STAGE_OPERANDX_n_37;
wire INPUT_STAGE_OPERANDX_n_38;
wire INPUT_STAGE_OPERANDX_n_39;
wire INPUT_STAGE_OPERANDX_n_40;
wire INPUT_STAGE_OPERANDX_n_41;
wire INPUT_STAGE_OPERANDX_n_42;
wire INPUT_STAGE_OPERANDX_n_43;
wire INPUT_STAGE_OPERANDX_n_44;
wire INPUT_STAGE_OPERANDX_n_45;
wire INPUT_STAGE_OPERANDX_n_46;
wire INPUT_STAGE_OPERANDX_n_47;
wire INPUT_STAGE_OPERANDX_n_48;
wire INPUT_STAGE_OPERANDX_n_49;
wire INPUT_STAGE_OPERANDX_n_5;
wire INPUT_STAGE_OPERANDX_n_50;
wire INPUT_STAGE_OPERANDX_n_51;
wire INPUT_STAGE_OPERANDX_n_52;
wire INPUT_STAGE_OPERANDX_n_53;
wire INPUT_STAGE_OPERANDX_n_54;
wire INPUT_STAGE_OPERANDX_n_55;
wire INPUT_STAGE_OPERANDX_n_56;
wire INPUT_STAGE_OPERANDX_n_57;
wire INPUT_STAGE_OPERANDX_n_58;
wire INPUT_STAGE_OPERANDX_n_59;
wire INPUT_STAGE_OPERANDX_n_6;
wire INPUT_STAGE_OPERANDX_n_60;
wire INPUT_STAGE_OPERANDX_n_61;
wire INPUT_STAGE_OPERANDX_n_62;
wire INPUT_STAGE_OPERANDX_n_63;
wire INPUT_STAGE_OPERANDX_n_64;
wire INPUT_STAGE_OPERANDX_n_65;
wire INPUT_STAGE_OPERANDX_n_66;
wire INPUT_STAGE_OPERANDX_n_67;
wire INPUT_STAGE_OPERANDX_n_68;
wire INPUT_STAGE_OPERANDX_n_69;
wire INPUT_STAGE_OPERANDX_n_7;
wire INPUT_STAGE_OPERANDX_n_70;
wire INPUT_STAGE_OPERANDX_n_71;
wire INPUT_STAGE_OPERANDX_n_72;
wire INPUT_STAGE_OPERANDX_n_8;
wire INPUT_STAGE_OPERANDX_n_9;
wire INPUT_STAGE_OPERANDY_n_0;
wire INPUT_STAGE_OPERANDY_n_10;
wire INPUT_STAGE_OPERANDY_n_11;
wire INPUT_STAGE_OPERANDY_n_12;
wire INPUT_STAGE_OPERANDY_n_13;
wire INPUT_STAGE_OPERANDY_n_14;
wire INPUT_STAGE_OPERANDY_n_15;
wire INPUT_STAGE_OPERANDY_n_16;
wire INPUT_STAGE_OPERANDY_n_17;
wire INPUT_STAGE_OPERANDY_n_18;
wire INPUT_STAGE_OPERANDY_n_19;
wire INPUT_STAGE_OPERANDY_n_2;
wire INPUT_STAGE_OPERANDY_n_20;
wire INPUT_STAGE_OPERANDY_n_21;
wire INPUT_STAGE_OPERANDY_n_22;
wire INPUT_STAGE_OPERANDY_n_23;
wire INPUT_STAGE_OPERANDY_n_24;
wire INPUT_STAGE_OPERANDY_n_25;
wire INPUT_STAGE_OPERANDY_n_26;
wire INPUT_STAGE_OPERANDY_n_27;
wire INPUT_STAGE_OPERANDY_n_28;
wire INPUT_STAGE_OPERANDY_n_29;
wire INPUT_STAGE_OPERANDY_n_3;
wire INPUT_STAGE_OPERANDY_n_30;
wire INPUT_STAGE_OPERANDY_n_31;
wire INPUT_STAGE_OPERANDY_n_32;
wire INPUT_STAGE_OPERANDY_n_33;
wire INPUT_STAGE_OPERANDY_n_4;
wire INPUT_STAGE_OPERANDY_n_5;
wire INPUT_STAGE_OPERANDY_n_6;
wire INPUT_STAGE_OPERANDY_n_7;
wire INPUT_STAGE_OPERANDY_n_8;
wire INPUT_STAGE_OPERANDY_n_9;
wire [3:3]LZD_raw_out_EWR;
wire Magnitude_Comparator_n_2;
wire MuxXY_n_0;
wire MuxXY_n_1;
wire MuxXY_n_10;
wire MuxXY_n_11;
wire MuxXY_n_12;
wire MuxXY_n_13;
wire MuxXY_n_14;
wire MuxXY_n_15;
wire MuxXY_n_16;
wire MuxXY_n_17;
wire MuxXY_n_18;
wire MuxXY_n_19;
wire MuxXY_n_2;
wire MuxXY_n_20;
wire MuxXY_n_21;
wire MuxXY_n_22;
wire MuxXY_n_23;
wire MuxXY_n_24;
wire MuxXY_n_25;
wire MuxXY_n_26;
wire MuxXY_n_27;
wire MuxXY_n_28;
wire MuxXY_n_29;
wire MuxXY_n_3;
wire MuxXY_n_30;
wire MuxXY_n_31;
wire MuxXY_n_32;
wire MuxXY_n_33;
wire MuxXY_n_34;
wire MuxXY_n_35;
wire MuxXY_n_36;
wire MuxXY_n_37;
wire MuxXY_n_38;
wire MuxXY_n_39;
wire MuxXY_n_4;
wire MuxXY_n_40;
wire MuxXY_n_41;
wire MuxXY_n_42;
wire MuxXY_n_43;
wire MuxXY_n_44;
wire MuxXY_n_45;
wire MuxXY_n_46;
wire MuxXY_n_47;
wire MuxXY_n_48;
wire MuxXY_n_49;
wire MuxXY_n_5;
wire MuxXY_n_50;
wire MuxXY_n_51;
wire MuxXY_n_52;
wire MuxXY_n_53;
wire MuxXY_n_54;
wire MuxXY_n_55;
wire MuxXY_n_56;
wire MuxXY_n_57;
wire MuxXY_n_58;
wire MuxXY_n_6;
wire MuxXY_n_7;
wire MuxXY_n_8;
wire MuxXY_n_9;
wire NRM_STAGE_DMP_exp_n_0;
wire NRM_STAGE_DMP_exp_n_1;
wire NRM_STAGE_DMP_exp_n_2;
wire NRM_STAGE_DMP_exp_n_3;
wire NRM_STAGE_DMP_exp_n_4;
wire NRM_STAGE_DMP_exp_n_5;
wire NRM_STAGE_DMP_exp_n_6;
wire NRM_STAGE_DMP_exp_n_7;
wire NRM_STAGE_FLAGS_n_0;
wire NRM_STAGE_FLAGS_n_1;
wire NRM_STAGE_Raw_mant_n_26;
wire NRM_STAGE_Raw_mant_n_28;
wire NRM_STAGE_Raw_mant_n_29;
wire NRM_STAGE_Raw_mant_n_30;
wire OP_FLAG_INIT;
wire OP_FLAG_SFG;
wire OVRFLW_FLAG_FRMT;
wire [25:0]Raw_mant_SGF;
wire SFT2FRMT_STAGE_FLAGS_n_0;
wire SFT2FRMT_STAGE_FLAGS_n_1;
wire SFT2FRMT_STAGE_VARS_n_0;
wire SFT2FRMT_STAGE_VARS_n_1;
wire SFT2FRMT_STAGE_VARS_n_10;
wire SFT2FRMT_STAGE_VARS_n_11;
wire SFT2FRMT_STAGE_VARS_n_12;
wire SFT2FRMT_STAGE_VARS_n_13;
wire SFT2FRMT_STAGE_VARS_n_14;
wire SFT2FRMT_STAGE_VARS_n_15;
wire SFT2FRMT_STAGE_VARS_n_16;
wire SFT2FRMT_STAGE_VARS_n_17;
wire SFT2FRMT_STAGE_VARS_n_18;
wire SFT2FRMT_STAGE_VARS_n_19;
wire SFT2FRMT_STAGE_VARS_n_2;
wire SFT2FRMT_STAGE_VARS_n_20;
wire SFT2FRMT_STAGE_VARS_n_21;
wire SFT2FRMT_STAGE_VARS_n_22;
wire SFT2FRMT_STAGE_VARS_n_23;
wire SFT2FRMT_STAGE_VARS_n_24;
wire SFT2FRMT_STAGE_VARS_n_25;
wire SFT2FRMT_STAGE_VARS_n_26;
wire SFT2FRMT_STAGE_VARS_n_3;
wire SFT2FRMT_STAGE_VARS_n_4;
wire SFT2FRMT_STAGE_VARS_n_5;
wire SFT2FRMT_STAGE_VARS_n_6;
wire SFT2FRMT_STAGE_VARS_n_7;
wire SFT2FRMT_STAGE_VARS_n_9;
wire SGF_STAGE_DMP_n_0;
wire SGF_STAGE_DMP_n_1;
wire SGF_STAGE_DMP_n_10;
wire SGF_STAGE_DMP_n_11;
wire SGF_STAGE_DMP_n_2;
wire SGF_STAGE_DMP_n_3;
wire SGF_STAGE_DMP_n_35;
wire SGF_STAGE_DMP_n_36;
wire SGF_STAGE_DMP_n_37;
wire SGF_STAGE_DMP_n_38;
wire SGF_STAGE_DMP_n_39;
wire SGF_STAGE_DMP_n_4;
wire SGF_STAGE_DMP_n_40;
wire SGF_STAGE_DMP_n_41;
wire SGF_STAGE_DMP_n_42;
wire SGF_STAGE_DMP_n_43;
wire SGF_STAGE_DMP_n_44;
wire SGF_STAGE_DMP_n_45;
wire SGF_STAGE_DMP_n_46;
wire SGF_STAGE_DMP_n_47;
wire SGF_STAGE_DMP_n_48;
wire SGF_STAGE_DMP_n_49;
wire SGF_STAGE_DMP_n_5;
wire SGF_STAGE_DMP_n_50;
wire SGF_STAGE_DMP_n_51;
wire SGF_STAGE_DMP_n_52;
wire SGF_STAGE_DMP_n_53;
wire SGF_STAGE_DMP_n_54;
wire SGF_STAGE_DMP_n_55;
wire SGF_STAGE_DMP_n_6;
wire SGF_STAGE_DMP_n_7;
wire SGF_STAGE_DMP_n_8;
wire SGF_STAGE_DMP_n_9;
wire SGF_STAGE_DmP_mant_n_0;
wire SGF_STAGE_DmP_mant_n_1;
wire SGF_STAGE_DmP_mant_n_10;
wire SGF_STAGE_DmP_mant_n_11;
wire SGF_STAGE_DmP_mant_n_12;
wire SGF_STAGE_DmP_mant_n_13;
wire SGF_STAGE_DmP_mant_n_14;
wire SGF_STAGE_DmP_mant_n_15;
wire SGF_STAGE_DmP_mant_n_16;
wire SGF_STAGE_DmP_mant_n_17;
wire SGF_STAGE_DmP_mant_n_18;
wire SGF_STAGE_DmP_mant_n_19;
wire SGF_STAGE_DmP_mant_n_2;
wire SGF_STAGE_DmP_mant_n_20;
wire SGF_STAGE_DmP_mant_n_21;
wire SGF_STAGE_DmP_mant_n_22;
wire SGF_STAGE_DmP_mant_n_23;
wire SGF_STAGE_DmP_mant_n_24;
wire SGF_STAGE_DmP_mant_n_26;
wire SGF_STAGE_DmP_mant_n_27;
wire SGF_STAGE_DmP_mant_n_28;
wire SGF_STAGE_DmP_mant_n_29;
wire SGF_STAGE_DmP_mant_n_3;
wire SGF_STAGE_DmP_mant_n_30;
wire SGF_STAGE_DmP_mant_n_31;
wire SGF_STAGE_DmP_mant_n_32;
wire SGF_STAGE_DmP_mant_n_33;
wire SGF_STAGE_DmP_mant_n_34;
wire SGF_STAGE_DmP_mant_n_35;
wire SGF_STAGE_DmP_mant_n_36;
wire SGF_STAGE_DmP_mant_n_37;
wire SGF_STAGE_DmP_mant_n_38;
wire SGF_STAGE_DmP_mant_n_39;
wire SGF_STAGE_DmP_mant_n_4;
wire SGF_STAGE_DmP_mant_n_40;
wire SGF_STAGE_DmP_mant_n_41;
wire SGF_STAGE_DmP_mant_n_42;
wire SGF_STAGE_DmP_mant_n_43;
wire SGF_STAGE_DmP_mant_n_44;
wire SGF_STAGE_DmP_mant_n_45;
wire SGF_STAGE_DmP_mant_n_46;
wire SGF_STAGE_DmP_mant_n_47;
wire SGF_STAGE_DmP_mant_n_48;
wire SGF_STAGE_DmP_mant_n_49;
wire SGF_STAGE_DmP_mant_n_5;
wire SGF_STAGE_DmP_mant_n_51;
wire SGF_STAGE_DmP_mant_n_6;
wire SGF_STAGE_DmP_mant_n_7;
wire SGF_STAGE_DmP_mant_n_8;
wire SGF_STAGE_DmP_mant_n_9;
wire SGF_STAGE_FLAGS_n_1;
wire SGF_STAGE_FLAGS_n_2;
wire SHT1_STAGE_DMP_n_0;
wire SHT1_STAGE_DMP_n_1;
wire SHT1_STAGE_DMP_n_10;
wire SHT1_STAGE_DMP_n_11;
wire SHT1_STAGE_DMP_n_12;
wire SHT1_STAGE_DMP_n_13;
wire SHT1_STAGE_DMP_n_14;
wire SHT1_STAGE_DMP_n_15;
wire SHT1_STAGE_DMP_n_16;
wire SHT1_STAGE_DMP_n_17;
wire SHT1_STAGE_DMP_n_18;
wire SHT1_STAGE_DMP_n_19;
wire SHT1_STAGE_DMP_n_2;
wire SHT1_STAGE_DMP_n_20;
wire SHT1_STAGE_DMP_n_21;
wire SHT1_STAGE_DMP_n_22;
wire SHT1_STAGE_DMP_n_23;
wire SHT1_STAGE_DMP_n_24;
wire SHT1_STAGE_DMP_n_25;
wire SHT1_STAGE_DMP_n_26;
wire SHT1_STAGE_DMP_n_27;
wire SHT1_STAGE_DMP_n_28;
wire SHT1_STAGE_DMP_n_29;
wire SHT1_STAGE_DMP_n_3;
wire SHT1_STAGE_DMP_n_30;
wire SHT1_STAGE_DMP_n_4;
wire SHT1_STAGE_DMP_n_5;
wire SHT1_STAGE_DMP_n_6;
wire SHT1_STAGE_DMP_n_7;
wire SHT1_STAGE_DMP_n_8;
wire SHT1_STAGE_DMP_n_9;
wire SHT1_STAGE_DmP_mant_n_0;
wire SHT1_STAGE_DmP_mant_n_1;
wire SHT1_STAGE_DmP_mant_n_10;
wire SHT1_STAGE_DmP_mant_n_11;
wire SHT1_STAGE_DmP_mant_n_12;
wire SHT1_STAGE_DmP_mant_n_13;
wire SHT1_STAGE_DmP_mant_n_14;
wire SHT1_STAGE_DmP_mant_n_15;
wire SHT1_STAGE_DmP_mant_n_16;
wire SHT1_STAGE_DmP_mant_n_17;
wire SHT1_STAGE_DmP_mant_n_18;
wire SHT1_STAGE_DmP_mant_n_19;
wire SHT1_STAGE_DmP_mant_n_2;
wire SHT1_STAGE_DmP_mant_n_20;
wire SHT1_STAGE_DmP_mant_n_21;
wire SHT1_STAGE_DmP_mant_n_22;
wire SHT1_STAGE_DmP_mant_n_3;
wire SHT1_STAGE_DmP_mant_n_4;
wire SHT1_STAGE_DmP_mant_n_5;
wire SHT1_STAGE_DmP_mant_n_6;
wire SHT1_STAGE_DmP_mant_n_7;
wire SHT1_STAGE_DmP_mant_n_8;
wire SHT1_STAGE_DmP_mant_n_9;
wire SHT1_STAGE_FLAGS_n_0;
wire SHT1_STAGE_FLAGS_n_1;
wire SHT1_STAGE_FLAGS_n_2;
wire SHT2_SHIFT_DATA_n_0;
wire SHT2_SHIFT_DATA_n_1;
wire SHT2_SHIFT_DATA_n_2;
wire SHT2_STAGE_DMP_n_0;
wire SHT2_STAGE_DMP_n_1;
wire SHT2_STAGE_DMP_n_10;
wire SHT2_STAGE_DMP_n_11;
wire SHT2_STAGE_DMP_n_12;
wire SHT2_STAGE_DMP_n_13;
wire SHT2_STAGE_DMP_n_14;
wire SHT2_STAGE_DMP_n_15;
wire SHT2_STAGE_DMP_n_16;
wire SHT2_STAGE_DMP_n_17;
wire SHT2_STAGE_DMP_n_18;
wire SHT2_STAGE_DMP_n_19;
wire SHT2_STAGE_DMP_n_2;
wire SHT2_STAGE_DMP_n_20;
wire SHT2_STAGE_DMP_n_21;
wire SHT2_STAGE_DMP_n_22;
wire SHT2_STAGE_DMP_n_23;
wire SHT2_STAGE_DMP_n_24;
wire SHT2_STAGE_DMP_n_25;
wire SHT2_STAGE_DMP_n_26;
wire SHT2_STAGE_DMP_n_27;
wire SHT2_STAGE_DMP_n_28;
wire SHT2_STAGE_DMP_n_29;
wire SHT2_STAGE_DMP_n_3;
wire SHT2_STAGE_DMP_n_30;
wire SHT2_STAGE_DMP_n_4;
wire SHT2_STAGE_DMP_n_5;
wire SHT2_STAGE_DMP_n_6;
wire SHT2_STAGE_DMP_n_7;
wire SHT2_STAGE_DMP_n_8;
wire SHT2_STAGE_DMP_n_9;
wire SHT2_STAGE_FLAGS_n_1;
wire SHT2_STAGE_FLAGS_n_2;
wire SHT2_STAGE_SHFTVARS1_n_0;
wire SHT2_STAGE_SHFTVARS1_n_1;
wire SHT2_STAGE_SHFTVARS1_n_10;
wire SHT2_STAGE_SHFTVARS1_n_11;
wire SHT2_STAGE_SHFTVARS1_n_12;
wire SHT2_STAGE_SHFTVARS1_n_13;
wire SHT2_STAGE_SHFTVARS1_n_2;
wire SHT2_STAGE_SHFTVARS1_n_3;
wire SHT2_STAGE_SHFTVARS1_n_4;
wire SHT2_STAGE_SHFTVARS1_n_5;
wire SHT2_STAGE_SHFTVARS1_n_6;
wire SHT2_STAGE_SHFTVARS1_n_7;
wire SHT2_STAGE_SHFTVARS1_n_8;
wire SHT2_STAGE_SHFTVARS1_n_9;
wire SHT2_STAGE_SHFTVARS2_n_0;
wire SHT2_STAGE_SHFTVARS2_n_1;
wire SHT2_STAGE_SHFTVARS2_n_13;
wire SHT2_STAGE_SHFTVARS2_n_2;
wire SHT2_STAGE_SHFTVARS2_n_3;
wire SHT2_STAGE_SHFTVARS2_n_4;
wire SHT2_STAGE_SHFTVARS2_n_5;
wire SIGN_FLAG_INIT;
wire SIGN_FLAG_SHT2;
wire [4:1]Shift_amount_EXP_EW;
wire [4:0]Shift_amount_SHT1_EWR;
wire [1:1]Shift_reg_FLAGS_7;
wire UNDRFLW_FLAG_FRMT;
wire add_subt;
wire add_subt_IBUF;
wire beg_OP;
wire beg_OP_IBUF;
wire busy;
wire busy_OBUF;
wire clk;
wire clk_IBUF;
wire clk_IBUF_BUFG;
wire enable_Pipeline_input;
wire eqXY;
wire [8:0]exp_rslt_NRM2_EW1;
wire [31:0]final_result_ieee;
wire [31:0]final_result_ieee_OBUF;
wire [31:31]formatted_number_W;
wire gtXY;
wire inst_FRMT_STAGE_n_11;
wire inst_ShiftRegister_n_1;
wire inst_ShiftRegister_n_2;
wire inst_ShiftRegister_n_4;
wire inst_ShiftRegister_n_6;
wire inst_ShiftRegister_n_7;
wire intAS;
wire [31:31]intDX_EWSW;
wire [31:31]intDY_EWSW;
wire left_right_SHT1;
wire left_right_SHT2;
wire load0;
wire load00_out;
wire overflow_flag;
wire overflow_flag_OBUF;
wire p_1_in;
wire ready;
wire ready_OBUF;
wire rst;
wire rst_IBUF;
wire [25:0]sftr_odat_SHT2_SWR;
wire [4:2]shft_value_mux_o_EWR;
wire [4:2]shift_value_SHT2_EWR;
wire underflow_flag;
wire underflow_flag_OBUF;
wire zero_flag;
wire zero_flag_OBUF;
IBUF \Data_X_IBUF[0]_inst
(.I(Data_X[0]),
.O(Data_X_IBUF[0]));
IBUF \Data_X_IBUF[10]_inst
(.I(Data_X[10]),
.O(Data_X_IBUF[10]));
IBUF \Data_X_IBUF[11]_inst
(.I(Data_X[11]),
.O(Data_X_IBUF[11]));
IBUF \Data_X_IBUF[12]_inst
(.I(Data_X[12]),
.O(Data_X_IBUF[12]));
IBUF \Data_X_IBUF[13]_inst
(.I(Data_X[13]),
.O(Data_X_IBUF[13]));
IBUF \Data_X_IBUF[14]_inst
(.I(Data_X[14]),
.O(Data_X_IBUF[14]));
IBUF \Data_X_IBUF[15]_inst
(.I(Data_X[15]),
.O(Data_X_IBUF[15]));
IBUF \Data_X_IBUF[16]_inst
(.I(Data_X[16]),
.O(Data_X_IBUF[16]));
IBUF \Data_X_IBUF[17]_inst
(.I(Data_X[17]),
.O(Data_X_IBUF[17]));
IBUF \Data_X_IBUF[18]_inst
(.I(Data_X[18]),
.O(Data_X_IBUF[18]));
IBUF \Data_X_IBUF[19]_inst
(.I(Data_X[19]),
.O(Data_X_IBUF[19]));
IBUF \Data_X_IBUF[1]_inst
(.I(Data_X[1]),
.O(Data_X_IBUF[1]));
IBUF \Data_X_IBUF[20]_inst
(.I(Data_X[20]),
.O(Data_X_IBUF[20]));
IBUF \Data_X_IBUF[21]_inst
(.I(Data_X[21]),
.O(Data_X_IBUF[21]));
IBUF \Data_X_IBUF[22]_inst
(.I(Data_X[22]),
.O(Data_X_IBUF[22]));
IBUF \Data_X_IBUF[23]_inst
(.I(Data_X[23]),
.O(Data_X_IBUF[23]));
IBUF \Data_X_IBUF[24]_inst
(.I(Data_X[24]),
.O(Data_X_IBUF[24]));
IBUF \Data_X_IBUF[25]_inst
(.I(Data_X[25]),
.O(Data_X_IBUF[25]));
IBUF \Data_X_IBUF[26]_inst
(.I(Data_X[26]),
.O(Data_X_IBUF[26]));
IBUF \Data_X_IBUF[27]_inst
(.I(Data_X[27]),
.O(Data_X_IBUF[27]));
IBUF \Data_X_IBUF[28]_inst
(.I(Data_X[28]),
.O(Data_X_IBUF[28]));
IBUF \Data_X_IBUF[29]_inst
(.I(Data_X[29]),
.O(Data_X_IBUF[29]));
IBUF \Data_X_IBUF[2]_inst
(.I(Data_X[2]),
.O(Data_X_IBUF[2]));
IBUF \Data_X_IBUF[30]_inst
(.I(Data_X[30]),
.O(Data_X_IBUF[30]));
IBUF \Data_X_IBUF[31]_inst
(.I(Data_X[31]),
.O(Data_X_IBUF[31]));
IBUF \Data_X_IBUF[3]_inst
(.I(Data_X[3]),
.O(Data_X_IBUF[3]));
IBUF \Data_X_IBUF[4]_inst
(.I(Data_X[4]),
.O(Data_X_IBUF[4]));
IBUF \Data_X_IBUF[5]_inst
(.I(Data_X[5]),
.O(Data_X_IBUF[5]));
IBUF \Data_X_IBUF[6]_inst
(.I(Data_X[6]),
.O(Data_X_IBUF[6]));
IBUF \Data_X_IBUF[7]_inst
(.I(Data_X[7]),
.O(Data_X_IBUF[7]));
IBUF \Data_X_IBUF[8]_inst
(.I(Data_X[8]),
.O(Data_X_IBUF[8]));
IBUF \Data_X_IBUF[9]_inst
(.I(Data_X[9]),
.O(Data_X_IBUF[9]));
IBUF \Data_Y_IBUF[0]_inst
(.I(Data_Y[0]),
.O(Data_Y_IBUF[0]));
IBUF \Data_Y_IBUF[10]_inst
(.I(Data_Y[10]),
.O(Data_Y_IBUF[10]));
IBUF \Data_Y_IBUF[11]_inst
(.I(Data_Y[11]),
.O(Data_Y_IBUF[11]));
IBUF \Data_Y_IBUF[12]_inst
(.I(Data_Y[12]),
.O(Data_Y_IBUF[12]));
IBUF \Data_Y_IBUF[13]_inst
(.I(Data_Y[13]),
.O(Data_Y_IBUF[13]));
IBUF \Data_Y_IBUF[14]_inst
(.I(Data_Y[14]),
.O(Data_Y_IBUF[14]));
IBUF \Data_Y_IBUF[15]_inst
(.I(Data_Y[15]),
.O(Data_Y_IBUF[15]));
IBUF \Data_Y_IBUF[16]_inst
(.I(Data_Y[16]),
.O(Data_Y_IBUF[16]));
IBUF \Data_Y_IBUF[17]_inst
(.I(Data_Y[17]),
.O(Data_Y_IBUF[17]));
IBUF \Data_Y_IBUF[18]_inst
(.I(Data_Y[18]),
.O(Data_Y_IBUF[18]));
IBUF \Data_Y_IBUF[19]_inst
(.I(Data_Y[19]),
.O(Data_Y_IBUF[19]));
IBUF \Data_Y_IBUF[1]_inst
(.I(Data_Y[1]),
.O(Data_Y_IBUF[1]));
IBUF \Data_Y_IBUF[20]_inst
(.I(Data_Y[20]),
.O(Data_Y_IBUF[20]));
IBUF \Data_Y_IBUF[21]_inst
(.I(Data_Y[21]),
.O(Data_Y_IBUF[21]));
IBUF \Data_Y_IBUF[22]_inst
(.I(Data_Y[22]),
.O(Data_Y_IBUF[22]));
IBUF \Data_Y_IBUF[23]_inst
(.I(Data_Y[23]),
.O(Data_Y_IBUF[23]));
IBUF \Data_Y_IBUF[24]_inst
(.I(Data_Y[24]),
.O(Data_Y_IBUF[24]));
IBUF \Data_Y_IBUF[25]_inst
(.I(Data_Y[25]),
.O(Data_Y_IBUF[25]));
IBUF \Data_Y_IBUF[26]_inst
(.I(Data_Y[26]),
.O(Data_Y_IBUF[26]));
IBUF \Data_Y_IBUF[27]_inst
(.I(Data_Y[27]),
.O(Data_Y_IBUF[27]));
IBUF \Data_Y_IBUF[28]_inst
(.I(Data_Y[28]),
.O(Data_Y_IBUF[28]));
IBUF \Data_Y_IBUF[29]_inst
(.I(Data_Y[29]),
.O(Data_Y_IBUF[29]));
IBUF \Data_Y_IBUF[2]_inst
(.I(Data_Y[2]),
.O(Data_Y_IBUF[2]));
IBUF \Data_Y_IBUF[30]_inst
(.I(Data_Y[30]),
.O(Data_Y_IBUF[30]));
IBUF \Data_Y_IBUF[31]_inst
(.I(Data_Y[31]),
.O(Data_Y_IBUF[31]));
IBUF \Data_Y_IBUF[3]_inst
(.I(Data_Y[3]),
.O(Data_Y_IBUF[3]));
IBUF \Data_Y_IBUF[4]_inst
(.I(Data_Y[4]),
.O(Data_Y_IBUF[4]));
IBUF \Data_Y_IBUF[5]_inst
(.I(Data_Y[5]),
.O(Data_Y_IBUF[5]));
IBUF \Data_Y_IBUF[6]_inst
(.I(Data_Y[6]),
.O(Data_Y_IBUF[6]));
IBUF \Data_Y_IBUF[7]_inst
(.I(Data_Y[7]),
.O(Data_Y_IBUF[7]));
IBUF \Data_Y_IBUF[8]_inst
(.I(Data_Y[8]),
.O(Data_Y_IBUF[8]));
IBUF \Data_Y_IBUF[9]_inst
(.I(Data_Y[9]),
.O(Data_Y_IBUF[9]));
RegisterAdd__parameterized1 EXP_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW[2],EXP_STAGE_DMP_n_1}),
.Q({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.\Q_reg[25]_0 ({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5}),
.\Q_reg[30]_0 ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized2 EXP_STAGE_DmP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW[4:3],Shift_amount_EXP_EW[1]}),
.Q({EXP_STAGE_DmP_n_3,EXP_STAGE_DmP_n_4,EXP_STAGE_DmP_n_5,EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.\Q_reg[27]_0 ({EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9}),
.\Q_reg[27]_1 ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[6]_0 (inst_ShiftRegister_n_1));
RegisterAdd__parameterized3 EXP_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SIGN_FLAG_INIT,OP_FLAG_INIT,Magnitude_Comparator_n_2}),
.Q({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.\Q_reg[6] (inst_ShiftRegister_n_1));
RegisterAdd FRMT_STAGE_DATAOUT
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({formatted_number_W,SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3,SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7,SHT2_SHIFT_DATA_n_0,SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.Q(final_result_ieee_OBUF),
.\Q_reg[0]_0 (inst_ShiftRegister_n_6));
RegisterAdd__parameterized21 FRMT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({OVRFLW_FLAG_FRMT,UNDRFLW_FLAG_FRMT,SHT2_STAGE_FLAGS_n_2,inst_ShiftRegister_n_6}),
.Q({overflow_flag_OBUF,underflow_flag_OBUF,zero_flag_OBUF,ready_OBUF}));
RegisterAdd__parameterized0 INPUT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.E(enable_Pipeline_input),
.add_subt_IBUF(add_subt_IBUF),
.intAS(intAS));
RegisterAdd_0 INPUT_STAGE_OPERANDX
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(OP_FLAG_INIT),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.\Data_X[31] (Data_X_IBUF),
.E(enable_Pipeline_input),
.Q({intDX_EWSW,INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[0]_0 ({INPUT_STAGE_OPERANDX_n_63,INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66}),
.\Q_reg[0]_1 ({INPUT_STAGE_OPERANDX_n_67,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[0]_2 ({INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[2]_0 ({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.\Q_reg[2]_1 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[2]_2 ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[2]_3 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[2]_4 ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[2]_5 ({INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62}),
.\Q_reg[31]_0 ({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.S({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.intAS(intAS));
RegisterAdd_1 INPUT_STAGE_OPERANDY
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(Data_Y_IBUF),
.E(enable_Pipeline_input),
.Q({intDY_EWSW,INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}),
.\Q_reg[2]_0 (INPUT_STAGE_OPERANDY_n_33),
.\Q_reg[30]_0 (INPUT_STAGE_OPERANDX_n_5),
.S(INPUT_STAGE_OPERANDY_n_0));
Comparator Magnitude_Comparator
(.CO(gtXY),
.D(Magnitude_Comparator_n_2),
.DI({INPUT_STAGE_OPERANDX_n_0,INPUT_STAGE_OPERANDX_n_1,INPUT_STAGE_OPERANDX_n_2,INPUT_STAGE_OPERANDX_n_3}),
.Q(intDY_EWSW),
.\Q_reg[0] (eqXY),
.\Q_reg[14] ({INPUT_STAGE_OPERANDX_n_40,INPUT_STAGE_OPERANDX_n_41,INPUT_STAGE_OPERANDX_n_42,INPUT_STAGE_OPERANDX_n_43}),
.\Q_reg[14]_0 ({INPUT_STAGE_OPERANDX_n_44,INPUT_STAGE_OPERANDX_n_45,INPUT_STAGE_OPERANDX_n_46,INPUT_STAGE_OPERANDX_n_47}),
.\Q_reg[21] ({INPUT_STAGE_OPERANDX_n_67,INPUT_STAGE_OPERANDX_n_68,INPUT_STAGE_OPERANDX_n_69,INPUT_STAGE_OPERANDX_n_70}),
.\Q_reg[22] ({INPUT_STAGE_OPERANDX_n_48,INPUT_STAGE_OPERANDX_n_49,INPUT_STAGE_OPERANDX_n_50,INPUT_STAGE_OPERANDX_n_51}),
.\Q_reg[22]_0 ({INPUT_STAGE_OPERANDX_n_52,INPUT_STAGE_OPERANDX_n_53,INPUT_STAGE_OPERANDX_n_54,INPUT_STAGE_OPERANDX_n_55}),
.\Q_reg[30] ({INPUT_STAGE_OPERANDX_n_56,INPUT_STAGE_OPERANDX_n_57,INPUT_STAGE_OPERANDX_n_58,INPUT_STAGE_OPERANDX_n_59}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_33,INPUT_STAGE_OPERANDX_n_60,INPUT_STAGE_OPERANDX_n_61,INPUT_STAGE_OPERANDX_n_62}),
.\Q_reg[30]_1 ({INPUT_STAGE_OPERANDY_n_0,INPUT_STAGE_OPERANDX_n_71,INPUT_STAGE_OPERANDX_n_72}),
.\Q_reg[31] (intDX_EWSW),
.\Q_reg[9] ({INPUT_STAGE_OPERANDX_n_63,INPUT_STAGE_OPERANDX_n_64,INPUT_STAGE_OPERANDX_n_65,INPUT_STAGE_OPERANDX_n_66}),
.S({INPUT_STAGE_OPERANDX_n_36,INPUT_STAGE_OPERANDX_n_37,INPUT_STAGE_OPERANDX_n_38,INPUT_STAGE_OPERANDX_n_39}),
.intAS(intAS));
MultiplexTxT MuxXY
(.CO(gtXY),
.Q({INPUT_STAGE_OPERANDX_n_5,INPUT_STAGE_OPERANDX_n_6,INPUT_STAGE_OPERANDX_n_7,INPUT_STAGE_OPERANDX_n_8,INPUT_STAGE_OPERANDX_n_9,INPUT_STAGE_OPERANDX_n_10,INPUT_STAGE_OPERANDX_n_11,INPUT_STAGE_OPERANDX_n_12,INPUT_STAGE_OPERANDX_n_13,INPUT_STAGE_OPERANDX_n_14,INPUT_STAGE_OPERANDX_n_15,INPUT_STAGE_OPERANDX_n_16,INPUT_STAGE_OPERANDX_n_17,INPUT_STAGE_OPERANDX_n_18,INPUT_STAGE_OPERANDX_n_19,INPUT_STAGE_OPERANDX_n_20,INPUT_STAGE_OPERANDX_n_21,INPUT_STAGE_OPERANDX_n_22,INPUT_STAGE_OPERANDX_n_23,INPUT_STAGE_OPERANDX_n_24,INPUT_STAGE_OPERANDX_n_25,INPUT_STAGE_OPERANDX_n_26,INPUT_STAGE_OPERANDX_n_27,INPUT_STAGE_OPERANDX_n_28,INPUT_STAGE_OPERANDX_n_29,INPUT_STAGE_OPERANDX_n_30,INPUT_STAGE_OPERANDX_n_31,INPUT_STAGE_OPERANDX_n_32,INPUT_STAGE_OPERANDX_n_33,INPUT_STAGE_OPERANDX_n_34,INPUT_STAGE_OPERANDX_n_35}),
.\Q_reg[27] ({MuxXY_n_31,MuxXY_n_32,MuxXY_n_33,MuxXY_n_34,MuxXY_n_35,MuxXY_n_36,MuxXY_n_37,MuxXY_n_38,MuxXY_n_39,MuxXY_n_40,MuxXY_n_41,MuxXY_n_42,MuxXY_n_43,MuxXY_n_44,MuxXY_n_45,MuxXY_n_46,MuxXY_n_47,MuxXY_n_48,MuxXY_n_49,MuxXY_n_50,MuxXY_n_51,MuxXY_n_52,MuxXY_n_53,MuxXY_n_54,MuxXY_n_55,MuxXY_n_56,MuxXY_n_57,MuxXY_n_58}),
.\Q_reg[30] ({MuxXY_n_0,MuxXY_n_1,MuxXY_n_2,MuxXY_n_3,MuxXY_n_4,MuxXY_n_5,MuxXY_n_6,MuxXY_n_7,MuxXY_n_8,MuxXY_n_9,MuxXY_n_10,MuxXY_n_11,MuxXY_n_12,MuxXY_n_13,MuxXY_n_14,MuxXY_n_15,MuxXY_n_16,MuxXY_n_17,MuxXY_n_18,MuxXY_n_19,MuxXY_n_20,MuxXY_n_21,MuxXY_n_22,MuxXY_n_23,MuxXY_n_24,MuxXY_n_25,MuxXY_n_26,MuxXY_n_27,MuxXY_n_28,MuxXY_n_29,MuxXY_n_30}),
.\Q_reg[30]_0 ({INPUT_STAGE_OPERANDY_n_2,INPUT_STAGE_OPERANDY_n_3,INPUT_STAGE_OPERANDY_n_4,INPUT_STAGE_OPERANDY_n_5,INPUT_STAGE_OPERANDY_n_6,INPUT_STAGE_OPERANDY_n_7,INPUT_STAGE_OPERANDY_n_8,INPUT_STAGE_OPERANDY_n_9,INPUT_STAGE_OPERANDY_n_10,INPUT_STAGE_OPERANDY_n_11,INPUT_STAGE_OPERANDY_n_12,INPUT_STAGE_OPERANDY_n_13,INPUT_STAGE_OPERANDY_n_14,INPUT_STAGE_OPERANDY_n_15,INPUT_STAGE_OPERANDY_n_16,INPUT_STAGE_OPERANDY_n_17,INPUT_STAGE_OPERANDY_n_18,INPUT_STAGE_OPERANDY_n_19,INPUT_STAGE_OPERANDY_n_20,INPUT_STAGE_OPERANDY_n_21,INPUT_STAGE_OPERANDY_n_22,INPUT_STAGE_OPERANDY_n_23,INPUT_STAGE_OPERANDY_n_24,INPUT_STAGE_OPERANDY_n_25,INPUT_STAGE_OPERANDY_n_26,INPUT_STAGE_OPERANDY_n_27,INPUT_STAGE_OPERANDY_n_28,INPUT_STAGE_OPERANDY_n_29,INPUT_STAGE_OPERANDY_n_30,INPUT_STAGE_OPERANDY_n_31,INPUT_STAGE_OPERANDY_n_32}));
RegisterAdd__parameterized19 NRM_STAGE_DMP_exp
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.Q({NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[2]_0 (inst_ShiftRegister_n_4),
.\Q_reg[30] ({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11}));
RegisterAdd__parameterized20 NRM_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({NRM_STAGE_FLAGS_n_0,NRM_STAGE_FLAGS_n_1}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[0]_0 (ADD_OVRFLW_NRM),
.\Q_reg[1]_0 ({ADD_OVRFLW_SGF,SGF_STAGE_FLAGS_n_1,SGF_STAGE_FLAGS_n_2}),
.\Q_reg[2]_0 ({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}));
RegisterAdd__parameterized18 NRM_STAGE_Raw_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_1_in),
.D(\Data_array_SWR[2] ),
.Q({inst_ShiftRegister_n_4,Shift_reg_FLAGS_7}),
.\Q_reg[12]_0 ({NRM_STAGE_Raw_mant_n_26,LZD_raw_out_EWR,NRM_STAGE_Raw_mant_n_28,NRM_STAGE_Raw_mant_n_29,NRM_STAGE_Raw_mant_n_30}),
.\Q_reg[1]_0 (OP_FLAG_SFG),
.\Q_reg[1]_1 (Raw_mant_SGF),
.\Q_reg[22]_0 ({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[2]_0 (ADD_OVRFLW_NRM),
.\Q_reg[4]_0 (shft_value_mux_o_EWR),
.\Q_reg[4]_1 (Shift_amount_SHT1_EWR),
.left_right_SHT1(left_right_SHT1));
RegisterAdd__parameterized14 SFT2FRMT_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(ADD_OVRFLW_NRM),
.Q(Shift_reg_FLAGS_7),
.\Q_reg[26] (SFT2FRMT_STAGE_FLAGS_n_0),
.\Q_reg[8] (SFT2FRMT_STAGE_VARS_n_18),
.S(SFT2FRMT_STAGE_FLAGS_n_1));
RegisterAdd__parameterized13 SFT2FRMT_STAGE_VARS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SFT2FRMT_STAGE_VARS_n_0,SFT2FRMT_STAGE_VARS_n_1,SFT2FRMT_STAGE_VARS_n_2,SFT2FRMT_STAGE_VARS_n_3,SFT2FRMT_STAGE_VARS_n_4,SFT2FRMT_STAGE_VARS_n_5,SFT2FRMT_STAGE_VARS_n_6,SFT2FRMT_STAGE_VARS_n_7}),
.DI({SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12}),
.Q({SFT2FRMT_STAGE_VARS_n_18,SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22}),
.\Q_reg[0]_0 (SFT2FRMT_STAGE_FLAGS_n_0),
.\Q_reg[1]_0 (Shift_reg_FLAGS_7),
.\Q_reg[22] ({NRM_STAGE_Raw_mant_n_26,LZD_raw_out_EWR,NRM_STAGE_Raw_mant_n_28,NRM_STAGE_Raw_mant_n_29,NRM_STAGE_Raw_mant_n_30,NRM_STAGE_DMP_exp_n_0,NRM_STAGE_DMP_exp_n_1,NRM_STAGE_DMP_exp_n_2,NRM_STAGE_DMP_exp_n_3,NRM_STAGE_DMP_exp_n_4,NRM_STAGE_DMP_exp_n_5,NRM_STAGE_DMP_exp_n_6,NRM_STAGE_DMP_exp_n_7}),
.\Q_reg[26] ({SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17}),
.\Q_reg[2]_0 (SFT2FRMT_STAGE_VARS_n_14),
.\Q_reg[2]_1 ({SFT2FRMT_STAGE_VARS_n_23,SFT2FRMT_STAGE_VARS_n_24,SFT2FRMT_STAGE_VARS_n_25,SFT2FRMT_STAGE_VARS_n_26}),
.\Q_reg[3]_0 (OVRFLW_FLAG_FRMT),
.\Q_reg[6]_0 (UNDRFLW_FLAG_FRMT),
.\Q_reg[6]_1 (inst_FRMT_STAGE_n_11),
.S(SFT2FRMT_STAGE_VARS_n_13),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
RegisterAdd__parameterized15 SGF_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(SGF_STAGE_DMP_n_51),
.E(load0),
.O({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.Q({SGF_STAGE_DMP_n_4,SGF_STAGE_DMP_n_5,SGF_STAGE_DMP_n_6,SGF_STAGE_DMP_n_7,SGF_STAGE_DMP_n_8,SGF_STAGE_DMP_n_9,SGF_STAGE_DMP_n_10,SGF_STAGE_DMP_n_11,DMP_mant_SFG_SWR}),
.\Q_reg[12]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[16]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[20]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[24]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[24]_1 ({SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28,SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32,SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36,SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40,SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44,SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48,SGF_STAGE_DmP_mant_n_49}),
.\Q_reg[30]_0 ({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[8]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}),
.S(SGF_STAGE_DmP_mant_n_51));
RegisterAdd__parameterized16 SGF_STAGE_DmP_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_1_in),
.D(sftr_odat_SHT2_SWR),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3}),
.Q(DMP_mant_SFG_SWR),
.\Q_reg[12]_0 ({SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11}),
.\Q_reg[16]_0 ({SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15}),
.\Q_reg[20]_0 ({SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19}),
.\Q_reg[22]_0 (SGF_STAGE_DMP_n_51),
.\Q_reg[24]_0 ({SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,SGF_STAGE_DmP_mant_n_23}),
.\Q_reg[24]_1 ({SGF_STAGE_DmP_mant_n_27,SGF_STAGE_DmP_mant_n_28,SGF_STAGE_DmP_mant_n_29,SGF_STAGE_DmP_mant_n_30,SGF_STAGE_DmP_mant_n_31,SGF_STAGE_DmP_mant_n_32,SGF_STAGE_DmP_mant_n_33,SGF_STAGE_DmP_mant_n_34,SGF_STAGE_DmP_mant_n_35,SGF_STAGE_DmP_mant_n_36,SGF_STAGE_DmP_mant_n_37,SGF_STAGE_DmP_mant_n_38,SGF_STAGE_DmP_mant_n_39,SGF_STAGE_DmP_mant_n_40,SGF_STAGE_DmP_mant_n_41,SGF_STAGE_DmP_mant_n_42,SGF_STAGE_DmP_mant_n_43,SGF_STAGE_DmP_mant_n_44,SGF_STAGE_DmP_mant_n_45,SGF_STAGE_DmP_mant_n_46,SGF_STAGE_DmP_mant_n_47,SGF_STAGE_DmP_mant_n_48,SGF_STAGE_DmP_mant_n_49,Raw_mant_SGF[0]}),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_24),
.\Q_reg[25]_1 (SGF_STAGE_DmP_mant_n_26),
.\Q_reg[8]_0 ({SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7}),
.S(SGF_STAGE_DmP_mant_n_51));
RegisterAdd__parameterized17 SGF_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_1_in),
.E(load0),
.O({SGF_STAGE_DmP_mant_n_0,SGF_STAGE_DmP_mant_n_1,SGF_STAGE_DmP_mant_n_2,SGF_STAGE_DmP_mant_n_3}),
.Q(OP_FLAG_SFG),
.\Q_reg[10] ({SGF_STAGE_DmP_mant_n_8,SGF_STAGE_DmP_mant_n_9,SGF_STAGE_DmP_mant_n_10,SGF_STAGE_DmP_mant_n_11}),
.\Q_reg[10]_0 ({SGF_STAGE_DMP_n_39,SGF_STAGE_DMP_n_40,SGF_STAGE_DMP_n_41,SGF_STAGE_DMP_n_42}),
.\Q_reg[14] ({SGF_STAGE_DmP_mant_n_12,SGF_STAGE_DmP_mant_n_13,SGF_STAGE_DmP_mant_n_14,SGF_STAGE_DmP_mant_n_15}),
.\Q_reg[14]_0 ({SGF_STAGE_DMP_n_43,SGF_STAGE_DMP_n_44,SGF_STAGE_DMP_n_45,SGF_STAGE_DMP_n_46}),
.\Q_reg[18] ({SGF_STAGE_DmP_mant_n_16,SGF_STAGE_DmP_mant_n_17,SGF_STAGE_DmP_mant_n_18,SGF_STAGE_DmP_mant_n_19}),
.\Q_reg[18]_0 ({SGF_STAGE_DMP_n_47,SGF_STAGE_DMP_n_48,SGF_STAGE_DMP_n_49,SGF_STAGE_DMP_n_50}),
.\Q_reg[22] ({SGF_STAGE_DmP_mant_n_20,SGF_STAGE_DmP_mant_n_21,SGF_STAGE_DmP_mant_n_22,SGF_STAGE_DmP_mant_n_23}),
.\Q_reg[22]_0 ({SGF_STAGE_DMP_n_52,SGF_STAGE_DMP_n_53,SGF_STAGE_DMP_n_54,SGF_STAGE_DMP_n_55}),
.\Q_reg[22]_1 (SGF_STAGE_DmP_mant_n_24),
.\Q_reg[25] (Raw_mant_SGF[25:1]),
.\Q_reg[25]_0 (SGF_STAGE_DmP_mant_n_26),
.\Q_reg[2]_0 ({ADD_OVRFLW_SGF,SGF_STAGE_FLAGS_n_1,SGF_STAGE_FLAGS_n_2}),
.\Q_reg[2]_1 ({SGF_STAGE_DMP_n_0,SGF_STAGE_DMP_n_1,SGF_STAGE_DMP_n_2,SGF_STAGE_DMP_n_3}),
.\Q_reg[2]_2 ({SIGN_FLAG_SHT2,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[6] ({SGF_STAGE_DmP_mant_n_4,SGF_STAGE_DmP_mant_n_5,SGF_STAGE_DmP_mant_n_6,SGF_STAGE_DmP_mant_n_7}),
.\Q_reg[6]_0 ({SGF_STAGE_DMP_n_35,SGF_STAGE_DMP_n_36,SGF_STAGE_DMP_n_37,SGF_STAGE_DMP_n_38}));
RegisterAdd__parameterized4 SHT1_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_DMP_n_2,EXP_STAGE_DMP_n_3,EXP_STAGE_DMP_n_4,EXP_STAGE_DMP_n_5,EXP_STAGE_DMP_n_6,EXP_STAGE_DMP_n_7,EXP_STAGE_DMP_n_8,EXP_STAGE_DMP_n_9,EXP_STAGE_DMP_n_10,EXP_STAGE_DMP_n_11,EXP_STAGE_DMP_n_12,EXP_STAGE_DMP_n_13,EXP_STAGE_DMP_n_14,EXP_STAGE_DMP_n_15,EXP_STAGE_DMP_n_16,EXP_STAGE_DMP_n_17,EXP_STAGE_DMP_n_18,EXP_STAGE_DMP_n_19,EXP_STAGE_DMP_n_20,EXP_STAGE_DMP_n_21,EXP_STAGE_DMP_n_22,EXP_STAGE_DMP_n_23,EXP_STAGE_DMP_n_24,EXP_STAGE_DMP_n_25,EXP_STAGE_DMP_n_26,EXP_STAGE_DMP_n_27,EXP_STAGE_DMP_n_28,EXP_STAGE_DMP_n_29,EXP_STAGE_DMP_n_30,EXP_STAGE_DMP_n_31,EXP_STAGE_DMP_n_32}),
.Q({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized5 SHT1_STAGE_DmP_mant
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_DmP_n_6,EXP_STAGE_DmP_n_7,EXP_STAGE_DmP_n_8,EXP_STAGE_DmP_n_9,EXP_STAGE_DmP_n_10,EXP_STAGE_DmP_n_11,EXP_STAGE_DmP_n_12,EXP_STAGE_DmP_n_13,EXP_STAGE_DmP_n_14,EXP_STAGE_DmP_n_15,EXP_STAGE_DmP_n_16,EXP_STAGE_DmP_n_17,EXP_STAGE_DmP_n_18,EXP_STAGE_DmP_n_19,EXP_STAGE_DmP_n_20,EXP_STAGE_DmP_n_21,EXP_STAGE_DmP_n_22,EXP_STAGE_DmP_n_23,EXP_STAGE_DmP_n_24,EXP_STAGE_DmP_n_25,EXP_STAGE_DmP_n_26,EXP_STAGE_DmP_n_27,EXP_STAGE_DmP_n_28}),
.Q({SHT1_STAGE_DmP_mant_n_0,SHT1_STAGE_DmP_mant_n_1,SHT1_STAGE_DmP_mant_n_2,SHT1_STAGE_DmP_mant_n_3,SHT1_STAGE_DmP_mant_n_4,SHT1_STAGE_DmP_mant_n_5,SHT1_STAGE_DmP_mant_n_6,SHT1_STAGE_DmP_mant_n_7,SHT1_STAGE_DmP_mant_n_8,SHT1_STAGE_DmP_mant_n_9,SHT1_STAGE_DmP_mant_n_10,SHT1_STAGE_DmP_mant_n_11,SHT1_STAGE_DmP_mant_n_12,SHT1_STAGE_DmP_mant_n_13,SHT1_STAGE_DmP_mant_n_14,SHT1_STAGE_DmP_mant_n_15,SHT1_STAGE_DmP_mant_n_16,SHT1_STAGE_DmP_mant_n_17,SHT1_STAGE_DmP_mant_n_18,SHT1_STAGE_DmP_mant_n_19,SHT1_STAGE_DmP_mant_n_20,SHT1_STAGE_DmP_mant_n_21,SHT1_STAGE_DmP_mant_n_22}),
.\Q_reg[5]_0 (inst_ShiftRegister_n_2));
RegisterAdd__parameterized7 SHT1_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({EXP_STAGE_FLAGS_n_0,EXP_STAGE_FLAGS_n_1,EXP_STAGE_FLAGS_n_2}),
.Q({SHT1_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,SHT1_STAGE_FLAGS_n_2}),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized6 SHT1_STAGE_sft_amount
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({Shift_amount_EXP_EW,EXP_STAGE_DMP_n_1}),
.Q(Shift_amount_SHT1_EWR),
.\Q_reg[5] (inst_ShiftRegister_n_2));
RegisterAdd__parameterized9 SHT2_SHIFT_DATA
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT2_SHIFT_DATA_n_0,SHT2_SHIFT_DATA_n_1,SHT2_SHIFT_DATA_n_2}),
.\Data_array_SWR[4] (\Data_array_SWR[4] ),
.\Data_array_SWR[6] (\Data_array_SWR[6] [1]),
.E(inst_ShiftRegister_n_7),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_13}),
.\Q_reg[0]_0 ({OVRFLW_FLAG_FRMT,UNDRFLW_FLAG_FRMT}),
.\Q_reg[13]_0 (\Data_array_SWR[3] ),
.\Q_reg[25]_0 ({sftr_odat_SHT2_SWR[25:24],sftr_odat_SHT2_SWR[13:12],sftr_odat_SHT2_SWR[0]}),
.\Q_reg[2]_0 (\Data_array_SWR[2] ),
.\Q_reg[4]_0 (shift_value_SHT2_EWR),
.\Q_reg[4]_1 (\Data_array_SWR[6] [25:24]),
.\Q_reg[8]_0 ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [11:2]}));
RegisterAdd__parameterized8 SHT2_STAGE_DMP
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT1_STAGE_DMP_n_0,SHT1_STAGE_DMP_n_1,SHT1_STAGE_DMP_n_2,SHT1_STAGE_DMP_n_3,SHT1_STAGE_DMP_n_4,SHT1_STAGE_DMP_n_5,SHT1_STAGE_DMP_n_6,SHT1_STAGE_DMP_n_7,SHT1_STAGE_DMP_n_8,SHT1_STAGE_DMP_n_9,SHT1_STAGE_DMP_n_10,SHT1_STAGE_DMP_n_11,SHT1_STAGE_DMP_n_12,SHT1_STAGE_DMP_n_13,SHT1_STAGE_DMP_n_14,SHT1_STAGE_DMP_n_15,SHT1_STAGE_DMP_n_16,SHT1_STAGE_DMP_n_17,SHT1_STAGE_DMP_n_18,SHT1_STAGE_DMP_n_19,SHT1_STAGE_DMP_n_20,SHT1_STAGE_DMP_n_21,SHT1_STAGE_DMP_n_22,SHT1_STAGE_DMP_n_23,SHT1_STAGE_DMP_n_24,SHT1_STAGE_DMP_n_25,SHT1_STAGE_DMP_n_26,SHT1_STAGE_DMP_n_27,SHT1_STAGE_DMP_n_28,SHT1_STAGE_DMP_n_29,SHT1_STAGE_DMP_n_30}),
.Q({SHT2_STAGE_DMP_n_0,SHT2_STAGE_DMP_n_1,SHT2_STAGE_DMP_n_2,SHT2_STAGE_DMP_n_3,SHT2_STAGE_DMP_n_4,SHT2_STAGE_DMP_n_5,SHT2_STAGE_DMP_n_6,SHT2_STAGE_DMP_n_7,SHT2_STAGE_DMP_n_8,SHT2_STAGE_DMP_n_9,SHT2_STAGE_DMP_n_10,SHT2_STAGE_DMP_n_11,SHT2_STAGE_DMP_n_12,SHT2_STAGE_DMP_n_13,SHT2_STAGE_DMP_n_14,SHT2_STAGE_DMP_n_15,SHT2_STAGE_DMP_n_16,SHT2_STAGE_DMP_n_17,SHT2_STAGE_DMP_n_18,SHT2_STAGE_DMP_n_19,SHT2_STAGE_DMP_n_20,SHT2_STAGE_DMP_n_21,SHT2_STAGE_DMP_n_22,SHT2_STAGE_DMP_n_23,SHT2_STAGE_DMP_n_24,SHT2_STAGE_DMP_n_25,SHT2_STAGE_DMP_n_26,SHT2_STAGE_DMP_n_27,SHT2_STAGE_DMP_n_28,SHT2_STAGE_DMP_n_29,SHT2_STAGE_DMP_n_30}),
.\Q_reg[4]_0 (busy_OBUF));
RegisterAdd__parameterized12 SHT2_STAGE_FLAGS
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({NRM_STAGE_FLAGS_n_0,SHT1_STAGE_FLAGS_n_1,NRM_STAGE_FLAGS_n_1}),
.Q({SIGN_FLAG_SHT2,SHT2_STAGE_FLAGS_n_1,SHT2_STAGE_FLAGS_n_2}),
.\Q_reg[4] (busy_OBUF));
RegisterAdd__parameterized10 SHT2_STAGE_SHFTVARS1
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT2_STAGE_SHFTVARS1_n_0,SHT2_STAGE_SHFTVARS1_n_1,SHT2_STAGE_SHFTVARS1_n_2,SHT2_STAGE_SHFTVARS1_n_3,SHT2_STAGE_SHFTVARS1_n_4,SHT2_STAGE_SHFTVARS1_n_5,SHT2_STAGE_SHFTVARS1_n_6,SHT2_STAGE_SHFTVARS1_n_7,SHT2_STAGE_SHFTVARS1_n_8,SHT2_STAGE_SHFTVARS1_n_9,SHT2_STAGE_SHFTVARS1_n_10,SHT2_STAGE_SHFTVARS1_n_11,SHT2_STAGE_SHFTVARS1_n_12,SHT2_STAGE_SHFTVARS1_n_13}),
.\Data_array_SWR[4] (\Data_array_SWR[4] ),
.E(inst_ShiftRegister_n_7),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_13}),
.\Q_reg[0] ({OVRFLW_FLAG_FRMT,UNDRFLW_FLAG_FRMT}),
.\Q_reg[0]_0 ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [9:2]}),
.\Q_reg[16] (shift_value_SHT2_EWR),
.\Q_reg[23] ({sftr_odat_SHT2_SWR[23:16],sftr_odat_SHT2_SWR[7:1]}),
.\Q_reg[25] ({\Data_array_SWR[6] [25:24],\Data_array_SWR[6] [15:14],\Data_array_SWR[6] [9:8]}),
.\Q_reg[25]_0 (\Data_array_SWR[3] ),
.\Q_reg[2]_0 (shft_value_mux_o_EWR),
.\Q_reg[4]_0 (\Data_array_SWR[6] [1]));
RegisterAdd__parameterized11 SHT2_STAGE_SHFTVARS2
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D({SHT2_STAGE_SHFTVARS2_n_0,SHT2_STAGE_SHFTVARS2_n_1,SHT2_STAGE_SHFTVARS2_n_2,SHT2_STAGE_SHFTVARS2_n_3,SHT2_STAGE_SHFTVARS2_n_4,SHT2_STAGE_SHFTVARS2_n_5}),
.E(inst_ShiftRegister_n_7),
.Q({left_right_SHT2,SHT2_STAGE_SHFTVARS2_n_13}),
.\Q_reg[0]_0 ({OVRFLW_FLAG_FRMT,UNDRFLW_FLAG_FRMT}),
.\Q_reg[0]_1 ({\Data_array_SWR[5] [17:16],\Data_array_SWR[5] [11:10]}),
.\Q_reg[15] ({sftr_odat_SHT2_SWR[15:14],sftr_odat_SHT2_SWR[11:8]}),
.\Q_reg[1]_0 ({left_right_SHT1,ADD_OVRFLW_NRM}),
.\Q_reg[4] (shift_value_SHT2_EWR[4]),
.\Q_reg[4]_0 ({\Data_array_SWR[6] [15:14],\Data_array_SWR[6] [9:8]}));
IBUF add_subt_IBUF_inst
(.I(add_subt),
.O(add_subt_IBUF));
IBUF beg_OP_IBUF_inst
(.I(beg_OP),
.O(beg_OP_IBUF));
OBUF busy_OBUF_inst
(.I(busy_OBUF),
.O(busy));
BUFG clk_IBUF_BUFG_inst
(.I(clk_IBUF),
.O(clk_IBUF_BUFG));
IBUF clk_IBUF_inst
(.I(clk),
.O(clk_IBUF));
OBUF \final_result_ieee_OBUF[0]_inst
(.I(final_result_ieee_OBUF[0]),
.O(final_result_ieee[0]));
OBUF \final_result_ieee_OBUF[10]_inst
(.I(final_result_ieee_OBUF[10]),
.O(final_result_ieee[10]));
OBUF \final_result_ieee_OBUF[11]_inst
(.I(final_result_ieee_OBUF[11]),
.O(final_result_ieee[11]));
OBUF \final_result_ieee_OBUF[12]_inst
(.I(final_result_ieee_OBUF[12]),
.O(final_result_ieee[12]));
OBUF \final_result_ieee_OBUF[13]_inst
(.I(final_result_ieee_OBUF[13]),
.O(final_result_ieee[13]));
OBUF \final_result_ieee_OBUF[14]_inst
(.I(final_result_ieee_OBUF[14]),
.O(final_result_ieee[14]));
OBUF \final_result_ieee_OBUF[15]_inst
(.I(final_result_ieee_OBUF[15]),
.O(final_result_ieee[15]));
OBUF \final_result_ieee_OBUF[16]_inst
(.I(final_result_ieee_OBUF[16]),
.O(final_result_ieee[16]));
OBUF \final_result_ieee_OBUF[17]_inst
(.I(final_result_ieee_OBUF[17]),
.O(final_result_ieee[17]));
OBUF \final_result_ieee_OBUF[18]_inst
(.I(final_result_ieee_OBUF[18]),
.O(final_result_ieee[18]));
OBUF \final_result_ieee_OBUF[19]_inst
(.I(final_result_ieee_OBUF[19]),
.O(final_result_ieee[19]));
OBUF \final_result_ieee_OBUF[1]_inst
(.I(final_result_ieee_OBUF[1]),
.O(final_result_ieee[1]));
OBUF \final_result_ieee_OBUF[20]_inst
(.I(final_result_ieee_OBUF[20]),
.O(final_result_ieee[20]));
OBUF \final_result_ieee_OBUF[21]_inst
(.I(final_result_ieee_OBUF[21]),
.O(final_result_ieee[21]));
OBUF \final_result_ieee_OBUF[22]_inst
(.I(final_result_ieee_OBUF[22]),
.O(final_result_ieee[22]));
OBUF \final_result_ieee_OBUF[23]_inst
(.I(final_result_ieee_OBUF[23]),
.O(final_result_ieee[23]));
OBUF \final_result_ieee_OBUF[24]_inst
(.I(final_result_ieee_OBUF[24]),
.O(final_result_ieee[24]));
OBUF \final_result_ieee_OBUF[25]_inst
(.I(final_result_ieee_OBUF[25]),
.O(final_result_ieee[25]));
OBUF \final_result_ieee_OBUF[26]_inst
(.I(final_result_ieee_OBUF[26]),
.O(final_result_ieee[26]));
OBUF \final_result_ieee_OBUF[27]_inst
(.I(final_result_ieee_OBUF[27]),
.O(final_result_ieee[27]));
OBUF \final_result_ieee_OBUF[28]_inst
(.I(final_result_ieee_OBUF[28]),
.O(final_result_ieee[28]));
OBUF \final_result_ieee_OBUF[29]_inst
(.I(final_result_ieee_OBUF[29]),
.O(final_result_ieee[29]));
OBUF \final_result_ieee_OBUF[2]_inst
(.I(final_result_ieee_OBUF[2]),
.O(final_result_ieee[2]));
OBUF \final_result_ieee_OBUF[30]_inst
(.I(final_result_ieee_OBUF[30]),
.O(final_result_ieee[30]));
OBUF \final_result_ieee_OBUF[31]_inst
(.I(final_result_ieee_OBUF[31]),
.O(final_result_ieee[31]));
OBUF \final_result_ieee_OBUF[3]_inst
(.I(final_result_ieee_OBUF[3]),
.O(final_result_ieee[3]));
OBUF \final_result_ieee_OBUF[4]_inst
(.I(final_result_ieee_OBUF[4]),
.O(final_result_ieee[4]));
OBUF \final_result_ieee_OBUF[5]_inst
(.I(final_result_ieee_OBUF[5]),
.O(final_result_ieee[5]));
OBUF \final_result_ieee_OBUF[6]_inst
(.I(final_result_ieee_OBUF[6]),
.O(final_result_ieee[6]));
OBUF \final_result_ieee_OBUF[7]_inst
(.I(final_result_ieee_OBUF[7]),
.O(final_result_ieee[7]));
OBUF \final_result_ieee_OBUF[8]_inst
(.I(final_result_ieee_OBUF[8]),
.O(final_result_ieee[8]));
OBUF \final_result_ieee_OBUF[9]_inst
(.I(final_result_ieee_OBUF[9]),
.O(final_result_ieee[9]));
FRMT_STAGE inst_FRMT_STAGE
(.D(formatted_number_W),
.DI({SFT2FRMT_STAGE_VARS_n_9,SFT2FRMT_STAGE_VARS_n_10,SFT2FRMT_STAGE_VARS_n_11,SFT2FRMT_STAGE_VARS_n_12}),
.Q({SFT2FRMT_STAGE_VARS_n_19,SFT2FRMT_STAGE_VARS_n_20,SFT2FRMT_STAGE_VARS_n_21,SFT2FRMT_STAGE_VARS_n_22}),
.\Q_reg[0] (SFT2FRMT_STAGE_FLAGS_n_0),
.\Q_reg[0]_0 (OVRFLW_FLAG_FRMT),
.\Q_reg[0]_1 (SFT2FRMT_STAGE_VARS_n_14),
.\Q_reg[2] (UNDRFLW_FLAG_FRMT),
.\Q_reg[2]_0 (SIGN_FLAG_SHT2),
.\Q_reg[3] (inst_FRMT_STAGE_n_11),
.\Q_reg[6] ({SFT2FRMT_STAGE_VARS_n_23,SFT2FRMT_STAGE_VARS_n_24,SFT2FRMT_STAGE_VARS_n_25,SFT2FRMT_STAGE_VARS_n_26}),
.\Q_reg[7] (SFT2FRMT_STAGE_VARS_n_13),
.S({SFT2FRMT_STAGE_VARS_n_15,SFT2FRMT_STAGE_VARS_n_16,SFT2FRMT_STAGE_VARS_n_17,SFT2FRMT_STAGE_FLAGS_n_1}),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
FSM_INPUT_ENABLE inst_FSM_INPUT_ENABLE
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.D(FSM_enable_input_internal),
.E(load00_out),
.\Q_reg[31] (enable_Pipeline_input),
.beg_OP_IBUF(beg_OP_IBUF));
ShiftRegister inst_ShiftRegister
(.AR(rst_IBUF),
.CLK(clk_IBUF_BUFG),
.CO(p_1_in),
.D(FSM_enable_input_internal),
.E(inst_ShiftRegister_n_7),
.\FSM_sequential_state_reg_reg[2] (load00_out),
.Q({inst_ShiftRegister_n_1,inst_ShiftRegister_n_2,busy_OBUF,inst_ShiftRegister_n_4,Shift_reg_FLAGS_7,inst_ShiftRegister_n_6}),
.\Q_reg[1]_0 (left_right_SHT1),
.\Q_reg[1]_1 (OP_FLAG_SFG),
.\Q_reg[2]_0 (load0));
OBUF overflow_flag_OBUF_inst
(.I(overflow_flag_OBUF),
.O(overflow_flag));
OBUF ready_OBUF_inst
(.I(ready_OBUF),
.O(ready));
sgn_result result_sign_bit
(.CO(gtXY),
.D(SIGN_FLAG_INIT),
.Q(intDY_EWSW),
.\Q_reg[30] (eqXY),
.\Q_reg[31] (intDX_EWSW),
.intAS(intAS));
IBUF rst_IBUF_inst
(.I(rst),
.O(rst_IBUF));
OBUF underflow_flag_OBUF_inst
(.I(underflow_flag_OBUF),
.O(underflow_flag));
OBUF zero_flag_OBUF_inst
(.I(zero_flag_OBUF),
.O(zero_flag));
endmodule
module FRMT_STAGE
(exp_rslt_NRM2_EW1,
D,
\Q_reg[2] ,
\Q_reg[3] ,
Q,
\Q_reg[0] ,
S,
DI,
\Q_reg[6] ,
\Q_reg[7] ,
\Q_reg[2]_0 ,
\Q_reg[0]_0 ,
\Q_reg[0]_1 );
output [8:0]exp_rslt_NRM2_EW1;
output [0:0]D;
output [0:0]\Q_reg[2] ;
output \Q_reg[3] ;
input [3:0]Q;
input \Q_reg[0] ;
input [3:0]S;
input [3:0]DI;
input [3:0]\Q_reg[6] ;
input [0:0]\Q_reg[7] ;
input [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
wire [0:0]D;
wire [3:0]DI;
wire [3:0]Q;
wire \Q_reg[0] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[2] ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg[3] ;
wire [3:0]\Q_reg[6] ;
wire [0:0]\Q_reg[7] ;
wire [3:0]S;
wire [8:0]exp_rslt_NRM2_EW1;
Multiplexer_AC__parameterized1 Exp_Mux
(.D(D),
.DI(DI),
.Q(Q),
.\Q_reg[0] (\Q_reg[0] ),
.\Q_reg[0]_0 (\Q_reg[0]_0 ),
.\Q_reg[0]_1 (\Q_reg[0]_1 ),
.\Q_reg[2] (\Q_reg[2] ),
.\Q_reg[2]_0 (\Q_reg[2]_0 ),
.\Q_reg[3] (\Q_reg[3] ),
.\Q_reg[6] (\Q_reg[6] ),
.\Q_reg[7] (\Q_reg[7] ),
.S(S),
.exp_rslt_NRM2_EW1(exp_rslt_NRM2_EW1));
endmodule
module FSM_INPUT_ENABLE
(E,
\Q_reg[31] ,
D,
beg_OP_IBUF,
CLK,
AR);
output [0:0]E;
output [0:0]\Q_reg[31] ;
output [0:0]D;
input beg_OP_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]E;
wire \FSM_sequential_state_reg[0]_i_1_n_0 ;
wire \FSM_sequential_state_reg[1]_i_1_n_0 ;
wire \FSM_sequential_state_reg[2]_i_1_n_0 ;
wire [0:0]\Q_reg[31] ;
wire beg_OP_IBUF;
(* RTL_KEEP = "yes" *) wire [2:0]state_reg;
LUT4 #(
.INIT(16'h5554))
\FSM_sequential_state_reg[0]_i_1
(.I0(state_reg[0]),
.I1(state_reg[2]),
.I2(beg_OP_IBUF),
.I3(state_reg[1]),
.O(\FSM_sequential_state_reg[0]_i_1_n_0 ));
LUT2 #(
.INIT(4'h6))
\FSM_sequential_state_reg[1]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.O(\FSM_sequential_state_reg[1]_i_1_n_0 ));
LUT3 #(
.INIT(8'h78))
\FSM_sequential_state_reg[2]_i_1
(.I0(state_reg[1]),
.I1(state_reg[0]),
.I2(state_reg[2]),
.O(\FSM_sequential_state_reg[2]_i_1_n_0 ));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[0]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[0]_i_1_n_0 ),
.Q(state_reg[0]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[1]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[1]_i_1_n_0 ),
.Q(state_reg[1]));
(* KEEP = "yes" *)
FDCE #(
.INIT(1'b0))
\FSM_sequential_state_reg_reg[2]
(.C(CLK),
.CE(1'b1),
.CLR(AR),
.D(\FSM_sequential_state_reg[2]_i_1_n_0 ),
.Q(state_reg[2]));
LUT4 #(
.INIT(16'h0700))
\Q[31]_i_1
(.I0(state_reg[0]),
.I1(state_reg[1]),
.I2(state_reg[2]),
.I3(beg_OP_IBUF),
.O(\Q_reg[31] ));
LUT4 #(
.INIT(16'hFFFE))
\Q[6]_i_1__1
(.I0(beg_OP_IBUF),
.I1(state_reg[2]),
.I2(state_reg[0]),
.I3(state_reg[1]),
.O(E));
LUT3 #(
.INIT(8'h15))
enable_input_internal
(.I0(state_reg[2]),
.I1(state_reg[1]),
.I2(state_reg[0]),
.O(D));
endmodule
module MultiplexTxT
(\Q_reg[30] ,
\Q_reg[27] ,
Q,
\Q_reg[30]_0 ,
CO);
output [30:0]\Q_reg[30] ;
output [27:0]\Q_reg[27] ;
input [30:0]Q;
input [30:0]\Q_reg[30]_0 ;
input [0:0]CO;
wire [0:0]CO;
wire [30:0]Q;
wire [27:0]\Q_reg[27] ;
wire [30:0]\Q_reg[30] ;
wire [30:0]\Q_reg[30]_0 ;
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1
(.I0(Q[0]),
.I1(\Q_reg[30]_0 [0]),
.I2(CO),
.O(\Q_reg[30] [0]));
(* SOFT_HLUTNM = "soft_lutpair1" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg[30]_0 [0]),
.I1(Q[0]),
.I2(CO),
.O(\Q_reg[27] [0]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1
(.I0(Q[10]),
.I1(\Q_reg[30]_0 [10]),
.I2(CO),
.O(\Q_reg[30] [10]));
(* SOFT_HLUTNM = "soft_lutpair11" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[30]_0 [10]),
.I1(Q[10]),
.I2(CO),
.O(\Q_reg[27] [10]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1
(.I0(Q[11]),
.I1(\Q_reg[30]_0 [11]),
.I2(CO),
.O(\Q_reg[30] [11]));
(* SOFT_HLUTNM = "soft_lutpair12" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__0
(.I0(\Q_reg[30]_0 [11]),
.I1(Q[11]),
.I2(CO),
.O(\Q_reg[27] [11]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1
(.I0(Q[12]),
.I1(\Q_reg[30]_0 [12]),
.I2(CO),
.O(\Q_reg[30] [12]));
(* SOFT_HLUTNM = "soft_lutpair13" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[30]_0 [12]),
.I1(Q[12]),
.I2(CO),
.O(\Q_reg[27] [12]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1
(.I0(Q[13]),
.I1(\Q_reg[30]_0 [13]),
.I2(CO),
.O(\Q_reg[30] [13]));
(* SOFT_HLUTNM = "soft_lutpair14" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[30]_0 [13]),
.I1(Q[13]),
.I2(CO),
.O(\Q_reg[27] [13]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1
(.I0(Q[14]),
.I1(\Q_reg[30]_0 [14]),
.I2(CO),
.O(\Q_reg[30] [14]));
(* SOFT_HLUTNM = "soft_lutpair15" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[30]_0 [14]),
.I1(Q[14]),
.I2(CO),
.O(\Q_reg[27] [14]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1
(.I0(Q[15]),
.I1(\Q_reg[30]_0 [15]),
.I2(CO),
.O(\Q_reg[30] [15]));
(* SOFT_HLUTNM = "soft_lutpair16" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[30]_0 [15]),
.I1(Q[15]),
.I2(CO),
.O(\Q_reg[27] [15]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1
(.I0(Q[16]),
.I1(\Q_reg[30]_0 [16]),
.I2(CO),
.O(\Q_reg[30] [16]));
(* SOFT_HLUTNM = "soft_lutpair17" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[30]_0 [16]),
.I1(Q[16]),
.I2(CO),
.O(\Q_reg[27] [16]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1
(.I0(Q[17]),
.I1(\Q_reg[30]_0 [17]),
.I2(CO),
.O(\Q_reg[30] [17]));
(* SOFT_HLUTNM = "soft_lutpair18" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[30]_0 [17]),
.I1(Q[17]),
.I2(CO),
.O(\Q_reg[27] [17]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1
(.I0(Q[18]),
.I1(\Q_reg[30]_0 [18]),
.I2(CO),
.O(\Q_reg[30] [18]));
(* SOFT_HLUTNM = "soft_lutpair19" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[30]_0 [18]),
.I1(Q[18]),
.I2(CO),
.O(\Q_reg[27] [18]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1
(.I0(Q[19]),
.I1(\Q_reg[30]_0 [19]),
.I2(CO),
.O(\Q_reg[30] [19]));
(* SOFT_HLUTNM = "soft_lutpair20" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[30]_0 [19]),
.I1(Q[19]),
.I2(CO),
.O(\Q_reg[27] [19]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1
(.I0(Q[1]),
.I1(\Q_reg[30]_0 [1]),
.I2(CO),
.O(\Q_reg[30] [1]));
(* SOFT_HLUTNM = "soft_lutpair2" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__0
(.I0(\Q_reg[30]_0 [1]),
.I1(Q[1]),
.I2(CO),
.O(\Q_reg[27] [1]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1
(.I0(Q[20]),
.I1(\Q_reg[30]_0 [20]),
.I2(CO),
.O(\Q_reg[30] [20]));
(* SOFT_HLUTNM = "soft_lutpair21" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[30]_0 [20]),
.I1(Q[20]),
.I2(CO),
.O(\Q_reg[27] [20]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1
(.I0(Q[21]),
.I1(\Q_reg[30]_0 [21]),
.I2(CO),
.O(\Q_reg[30] [21]));
(* SOFT_HLUTNM = "soft_lutpair22" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[30]_0 [21]),
.I1(Q[21]),
.I2(CO),
.O(\Q_reg[27] [21]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1
(.I0(Q[22]),
.I1(\Q_reg[30]_0 [22]),
.I2(CO),
.O(\Q_reg[30] [22]));
(* SOFT_HLUTNM = "soft_lutpair23" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[30]_0 [22]),
.I1(Q[22]),
.I2(CO),
.O(\Q_reg[27] [22]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1
(.I0(Q[23]),
.I1(\Q_reg[30]_0 [23]),
.I2(CO),
.O(\Q_reg[30] [23]));
(* SOFT_HLUTNM = "soft_lutpair24" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[30]_0 [23]),
.I1(Q[23]),
.I2(CO),
.O(\Q_reg[27] [23]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1
(.I0(Q[24]),
.I1(\Q_reg[30]_0 [24]),
.I2(CO),
.O(\Q_reg[30] [24]));
(* SOFT_HLUTNM = "soft_lutpair25" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[30]_0 [24]),
.I1(Q[24]),
.I2(CO),
.O(\Q_reg[27] [24]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1
(.I0(Q[25]),
.I1(\Q_reg[30]_0 [25]),
.I2(CO),
.O(\Q_reg[30] [25]));
(* SOFT_HLUTNM = "soft_lutpair26" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[30]_0 [25]),
.I1(Q[25]),
.I2(CO),
.O(\Q_reg[27] [25]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1
(.I0(Q[26]),
.I1(\Q_reg[30]_0 [26]),
.I2(CO),
.O(\Q_reg[30] [26]));
(* SOFT_HLUTNM = "soft_lutpair27" *)
LUT3 #(
.INIT(8'hAC))
\Q[26]_i_1__0
(.I0(\Q_reg[30]_0 [26]),
.I1(Q[26]),
.I2(CO),
.O(\Q_reg[27] [26]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1
(.I0(Q[27]),
.I1(\Q_reg[30]_0 [27]),
.I2(CO),
.O(\Q_reg[30] [27]));
(* SOFT_HLUTNM = "soft_lutpair28" *)
LUT3 #(
.INIT(8'hAC))
\Q[27]_i_1__0
(.I0(\Q_reg[30]_0 [27]),
.I1(Q[27]),
.I2(CO),
.O(\Q_reg[27] [27]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[28]_i_1
(.I0(Q[28]),
.I1(\Q_reg[30]_0 [28]),
.I2(CO),
.O(\Q_reg[30] [28]));
(* SOFT_HLUTNM = "soft_lutpair29" *)
LUT3 #(
.INIT(8'hAC))
\Q[29]_i_1
(.I0(Q[29]),
.I1(\Q_reg[30]_0 [29]),
.I2(CO),
.O(\Q_reg[30] [29]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1
(.I0(Q[2]),
.I1(\Q_reg[30]_0 [2]),
.I2(CO),
.O(\Q_reg[30] [2]));
(* SOFT_HLUTNM = "soft_lutpair3" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__0
(.I0(\Q_reg[30]_0 [2]),
.I1(Q[2]),
.I2(CO),
.O(\Q_reg[27] [2]));
LUT3 #(
.INIT(8'hAC))
\Q[30]_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 [30]),
.I2(CO),
.O(\Q_reg[30] [30]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1
(.I0(Q[3]),
.I1(\Q_reg[30]_0 [3]),
.I2(CO),
.O(\Q_reg[30] [3]));
(* SOFT_HLUTNM = "soft_lutpair4" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__0
(.I0(\Q_reg[30]_0 [3]),
.I1(Q[3]),
.I2(CO),
.O(\Q_reg[27] [3]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1
(.I0(Q[4]),
.I1(\Q_reg[30]_0 [4]),
.I2(CO),
.O(\Q_reg[30] [4]));
(* SOFT_HLUTNM = "soft_lutpair5" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__0
(.I0(\Q_reg[30]_0 [4]),
.I1(Q[4]),
.I2(CO),
.O(\Q_reg[27] [4]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1
(.I0(Q[5]),
.I1(\Q_reg[30]_0 [5]),
.I2(CO),
.O(\Q_reg[30] [5]));
(* SOFT_HLUTNM = "soft_lutpair6" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[30]_0 [5]),
.I1(Q[5]),
.I2(CO),
.O(\Q_reg[27] [5]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1
(.I0(Q[6]),
.I1(\Q_reg[30]_0 [6]),
.I2(CO),
.O(\Q_reg[30] [6]));
(* SOFT_HLUTNM = "soft_lutpair7" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[30]_0 [6]),
.I1(Q[6]),
.I2(CO),
.O(\Q_reg[27] [6]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1
(.I0(Q[7]),
.I1(\Q_reg[30]_0 [7]),
.I2(CO),
.O(\Q_reg[30] [7]));
(* SOFT_HLUTNM = "soft_lutpair8" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[30]_0 [7]),
.I1(Q[7]),
.I2(CO),
.O(\Q_reg[27] [7]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1
(.I0(Q[8]),
.I1(\Q_reg[30]_0 [8]),
.I2(CO),
.O(\Q_reg[30] [8]));
(* SOFT_HLUTNM = "soft_lutpair9" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[30]_0 [8]),
.I1(Q[8]),
.I2(CO),
.O(\Q_reg[27] [8]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1
(.I0(Q[9]),
.I1(\Q_reg[30]_0 [9]),
.I2(CO),
.O(\Q_reg[30] [9]));
(* SOFT_HLUTNM = "soft_lutpair10" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[30]_0 [9]),
.I1(Q[9]),
.I2(CO),
.O(\Q_reg[27] [9]));
endmodule
(* ORIG_REF_NAME = "Multiplexer_AC" *)
module Multiplexer_AC__parameterized1
(exp_rslt_NRM2_EW1,
D,
\Q_reg[2] ,
\Q_reg[3] ,
Q,
\Q_reg[0] ,
S,
DI,
\Q_reg[6] ,
\Q_reg[7] ,
\Q_reg[2]_0 ,
\Q_reg[0]_0 ,
\Q_reg[0]_1 );
output [8:0]exp_rslt_NRM2_EW1;
output [0:0]D;
output [0:0]\Q_reg[2] ;
output \Q_reg[3] ;
input [3:0]Q;
input \Q_reg[0] ;
input [3:0]S;
input [3:0]DI;
input [3:0]\Q_reg[6] ;
input [0:0]\Q_reg[7] ;
input [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[0]_0 ;
input \Q_reg[0]_1 ;
wire [0:0]D;
wire [3:0]DI;
wire [3:0]Q;
wire \Q_reg[0] ;
wire [0:0]\Q_reg[0]_0 ;
wire \Q_reg[0]_1 ;
wire [0:0]\Q_reg[2] ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg[3] ;
wire [3:0]\Q_reg[6] ;
wire [0:0]\Q_reg[7] ;
wire [3:0]S;
wire S0_carry__0_n_0;
wire S0_carry__0_n_1;
wire S0_carry__0_n_2;
wire S0_carry__0_n_3;
wire S0_carry_n_0;
wire S0_carry_n_1;
wire S0_carry_n_2;
wire S0_carry_n_3;
wire [8:0]exp_rslt_NRM2_EW1;
wire [3:0]NLW_S0_carry__1_CO_UNCONNECTED;
wire [3:1]NLW_S0_carry__1_O_UNCONNECTED;
LUT5 #(
.INIT(32'h00000001))
\Q[2]_i_1__4
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[6]),
.I2(exp_rslt_NRM2_EW1[8]),
.I3(exp_rslt_NRM2_EW1[7]),
.I4(\Q_reg[0]_1 ),
.O(\Q_reg[2] ));
LUT3 #(
.INIT(8'h0E))
\Q[31]_i_1__0
(.I0(\Q_reg[2] ),
.I1(\Q_reg[2]_0 ),
.I2(\Q_reg[0]_0 ),
.O(D));
LUT4 #(
.INIT(16'h8000))
\Q[3]_i_2__0
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(exp_rslt_NRM2_EW1[4]),
.I2(exp_rslt_NRM2_EW1[6]),
.I3(exp_rslt_NRM2_EW1[7]),
.O(\Q_reg[3] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry
(.CI(1'b0),
.CO({S0_carry_n_0,S0_carry_n_1,S0_carry_n_2,S0_carry_n_3}),
.CYINIT(Q[0]),
.DI({Q[3:1],\Q_reg[0] }),
.O(exp_rslt_NRM2_EW1[3:0]),
.S(S));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry__0
(.CI(S0_carry_n_0),
.CO({S0_carry__0_n_0,S0_carry__0_n_1,S0_carry__0_n_2,S0_carry__0_n_3}),
.CYINIT(1'b0),
.DI(DI),
.O(exp_rslt_NRM2_EW1[7:4]),
.S(\Q_reg[6] ));
(* METHODOLOGY_DRC_VIOS = "{SYNTH-8 {cell *THIS*}}" *)
CARRY4 S0_carry__1
(.CI(S0_carry__0_n_0),
.CO(NLW_S0_carry__1_CO_UNCONNECTED[3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({NLW_S0_carry__1_O_UNCONNECTED[3:1],exp_rslt_NRM2_EW1[8]}),
.S({1'b0,1'b0,1'b0,\Q_reg[7] }));
endmodule
module RegisterAdd
(Q,
\Q_reg[0]_0 ,
D,
CLK,
AR);
output [31:0]Q;
input [0:0]\Q_reg[0]_0 ;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [31:0]Q;
wire [0:0]\Q_reg[0]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[0]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_0
(DI,
Q,
S,
\Q_reg[2]_0 ,
\Q_reg[2]_1 ,
\Q_reg[2]_2 ,
\Q_reg[2]_3 ,
\Q_reg[2]_4 ,
\Q_reg[2]_5 ,
\Q_reg[0]_0 ,
\Q_reg[0]_1 ,
\Q_reg[0]_2 ,
D,
\Q_reg[31]_0 ,
intAS,
E,
\Data_X[31] ,
CLK,
AR);
output [3:0]DI;
output [31:0]Q;
output [3:0]S;
output [3:0]\Q_reg[2]_0 ;
output [3:0]\Q_reg[2]_1 ;
output [3:0]\Q_reg[2]_2 ;
output [3:0]\Q_reg[2]_3 ;
output [3:0]\Q_reg[2]_4 ;
output [2:0]\Q_reg[2]_5 ;
output [3:0]\Q_reg[0]_0 ;
output [3:0]\Q_reg[0]_1 ;
output [1:0]\Q_reg[0]_2 ;
output [0:0]D;
input [31:0]\Q_reg[31]_0 ;
input intAS;
input [0:0]E;
input [31:0]\Data_X[31] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [3:0]DI;
wire [31:0]\Data_X[31] ;
wire [0:0]E;
wire [31:0]Q;
wire [3:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [1:0]\Q_reg[0]_2 ;
wire [3:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [3:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[2]_3 ;
wire [3:0]\Q_reg[2]_4 ;
wire [2:0]\Q_reg[2]_5 ;
wire [31:0]\Q_reg[31]_0 ;
wire [3:0]S;
wire intAS;
LUT3 #(
.INIT(8'h96))
\Q[1]_i_1__2
(.I0(Q[31]),
.I1(\Q_reg[31]_0 [31]),
.I2(intAS),
.O(D));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Data_X[31] [9]),
.Q(Q[9]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_1
(.I0(Q[21]),
.I1(\Q_reg[31]_0 [21]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.I4(\Q_reg[31]_0 [22]),
.I5(Q[22]),
.O(\Q_reg[0]_1 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_2
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [20]),
.I3(Q[20]),
.I4(\Q_reg[31]_0 [19]),
.I5(Q[19]),
.O(\Q_reg[0]_1 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_3
(.I0(Q[15]),
.I1(\Q_reg[31]_0 [15]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.I4(\Q_reg[31]_0 [16]),
.I5(Q[16]),
.O(\Q_reg[0]_1 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__0_i_4
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [14]),
.I3(Q[14]),
.I4(\Q_reg[31]_0 [13]),
.I5(Q[13]),
.O(\Q_reg[0]_1 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_2
(.I0(Q[27]),
.I1(\Q_reg[31]_0 [27]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.I4(\Q_reg[31]_0 [28]),
.I5(Q[28]),
.O(\Q_reg[0]_2 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry__1_i_3
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [26]),
.I3(Q[26]),
.I4(\Q_reg[31]_0 [25]),
.I5(Q[25]),
.O(\Q_reg[0]_2 [0]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_1
(.I0(Q[9]),
.I1(\Q_reg[31]_0 [9]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.I4(\Q_reg[31]_0 [10]),
.I5(Q[10]),
.O(\Q_reg[0]_0 [3]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_2
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [8]),
.I3(Q[8]),
.I4(\Q_reg[31]_0 [7]),
.I5(Q[7]),
.O(\Q_reg[0]_0 [2]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_3
(.I0(Q[3]),
.I1(\Q_reg[31]_0 [3]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.I4(\Q_reg[31]_0 [4]),
.I5(Q[4]),
.O(\Q_reg[0]_0 [1]));
LUT6 #(
.INIT(64'h9009000000009009))
eqXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [2]),
.I3(Q[2]),
.I4(\Q_reg[31]_0 [1]),
.I5(Q[1]),
.O(\Q_reg[0]_0 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_1
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(\Q_reg[31]_0 [15]),
.I3(Q[15]),
.O(\Q_reg[2]_0 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_2
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(\Q_reg[31]_0 [13]),
.I3(Q[13]),
.O(\Q_reg[2]_0 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_3
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(\Q_reg[31]_0 [11]),
.I3(Q[11]),
.O(\Q_reg[2]_0 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__0_i_4
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(\Q_reg[31]_0 [9]),
.I3(Q[9]),
.O(\Q_reg[2]_0 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_5
(.I0(Q[14]),
.I1(\Q_reg[31]_0 [14]),
.I2(Q[15]),
.I3(\Q_reg[31]_0 [15]),
.O(\Q_reg[2]_1 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_6
(.I0(Q[12]),
.I1(\Q_reg[31]_0 [12]),
.I2(Q[13]),
.I3(\Q_reg[31]_0 [13]),
.O(\Q_reg[2]_1 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_7
(.I0(Q[10]),
.I1(\Q_reg[31]_0 [10]),
.I2(Q[11]),
.I3(\Q_reg[31]_0 [11]),
.O(\Q_reg[2]_1 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__0_i_8
(.I0(Q[8]),
.I1(\Q_reg[31]_0 [8]),
.I2(Q[9]),
.I3(\Q_reg[31]_0 [9]),
.O(\Q_reg[2]_1 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_1
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(\Q_reg[31]_0 [23]),
.I3(Q[23]),
.O(\Q_reg[2]_2 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_2
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(\Q_reg[31]_0 [21]),
.I3(Q[21]),
.O(\Q_reg[2]_2 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_3
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(\Q_reg[31]_0 [19]),
.I3(Q[19]),
.O(\Q_reg[2]_2 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__1_i_4
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(\Q_reg[31]_0 [17]),
.I3(Q[17]),
.O(\Q_reg[2]_2 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_5
(.I0(Q[22]),
.I1(\Q_reg[31]_0 [22]),
.I2(Q[23]),
.I3(\Q_reg[31]_0 [23]),
.O(\Q_reg[2]_3 [3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_6
(.I0(Q[20]),
.I1(\Q_reg[31]_0 [20]),
.I2(Q[21]),
.I3(\Q_reg[31]_0 [21]),
.O(\Q_reg[2]_3 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_7
(.I0(Q[18]),
.I1(\Q_reg[31]_0 [18]),
.I2(Q[19]),
.I3(\Q_reg[31]_0 [19]),
.O(\Q_reg[2]_3 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__1_i_8
(.I0(Q[16]),
.I1(\Q_reg[31]_0 [16]),
.I2(Q[17]),
.I3(\Q_reg[31]_0 [17]),
.O(\Q_reg[2]_3 [0]));
LUT2 #(
.INIT(4'h2))
gtXY_o_carry__2_i_1
(.I0(Q[30]),
.I1(\Q_reg[31]_0 [30]),
.O(\Q_reg[2]_4 [3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_2
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(\Q_reg[31]_0 [29]),
.I3(Q[29]),
.O(\Q_reg[2]_4 [2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_3
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(\Q_reg[31]_0 [27]),
.I3(Q[27]),
.O(\Q_reg[2]_4 [1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry__2_i_4
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(\Q_reg[31]_0 [25]),
.I3(Q[25]),
.O(\Q_reg[2]_4 [0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_6
(.I0(Q[28]),
.I1(\Q_reg[31]_0 [28]),
.I2(Q[29]),
.I3(\Q_reg[31]_0 [29]),
.O(\Q_reg[2]_5 [2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_7
(.I0(Q[26]),
.I1(\Q_reg[31]_0 [26]),
.I2(Q[27]),
.I3(\Q_reg[31]_0 [27]),
.O(\Q_reg[2]_5 [1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry__2_i_8
(.I0(Q[24]),
.I1(\Q_reg[31]_0 [24]),
.I2(Q[25]),
.I3(\Q_reg[31]_0 [25]),
.O(\Q_reg[2]_5 [0]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_1
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(\Q_reg[31]_0 [7]),
.I3(Q[7]),
.O(DI[3]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_2
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(\Q_reg[31]_0 [5]),
.I3(Q[5]),
.O(DI[2]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_3
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(\Q_reg[31]_0 [3]),
.I3(Q[3]),
.O(DI[1]));
LUT4 #(
.INIT(16'h2F02))
gtXY_o_carry_i_4
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(\Q_reg[31]_0 [1]),
.I3(Q[1]),
.O(DI[0]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_5
(.I0(Q[6]),
.I1(\Q_reg[31]_0 [6]),
.I2(Q[7]),
.I3(\Q_reg[31]_0 [7]),
.O(S[3]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_6
(.I0(Q[4]),
.I1(\Q_reg[31]_0 [4]),
.I2(Q[5]),
.I3(\Q_reg[31]_0 [5]),
.O(S[2]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_7
(.I0(Q[2]),
.I1(\Q_reg[31]_0 [2]),
.I2(Q[3]),
.I3(\Q_reg[31]_0 [3]),
.O(S[1]));
LUT4 #(
.INIT(16'h9009))
gtXY_o_carry_i_8
(.I0(Q[0]),
.I1(\Q_reg[31]_0 [0]),
.I2(Q[1]),
.I3(\Q_reg[31]_0 [1]),
.O(S[0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd_1
(S,
Q,
\Q_reg[2]_0 ,
\Q_reg[30]_0 ,
E,
D,
CLK,
AR);
output [0:0]S;
output [31:0]Q;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[30]_0 ;
input [0:0]E;
input [31:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [31:0]D;
wire [0:0]E;
wire [31:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[30]_0 ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[31]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[31]),
.Q(Q[31]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
LUT2 #(
.INIT(4'h9))
eqXY_o_carry__1_i_1
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(S));
LUT2 #(
.INIT(4'h9))
gtXY_o_carry__2_i_5
(.I0(Q[30]),
.I1(\Q_reg[30]_0 ),
.O(\Q_reg[2]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized0
(intAS,
E,
add_subt_IBUF,
CLK,
AR);
output intAS;
input [0:0]E;
input add_subt_IBUF;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]E;
wire add_subt_IBUF;
wire intAS;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(add_subt_IBUF),
.Q(intAS));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized1
(D,
Q,
\Q_reg[25]_0 ,
\Q_reg[6]_0 ,
\Q_reg[30]_0 ,
CLK,
AR);
output [1:0]D;
output [30:0]Q;
input [2:0]\Q_reg[25]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [30:0]Q;
wire [2:0]\Q_reg[25]_0 ;
wire [30:0]\Q_reg[30]_0 ;
wire [0:0]\Q_reg[6]_0 ;
LUT2 #(
.INIT(4'h6))
\Q[0]_i_1__2
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.O(D[0]));
LUT6 #(
.INIT(64'h4F04B0FBB0FB4F04))
\Q[2]_i_1__6
(.I0(Q[23]),
.I1(\Q_reg[25]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[25]_0 [1]),
.I4(\Q_reg[25]_0 [2]),
.I5(Q[25]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized10
(D,
\Q_reg[23] ,
\Q_reg[25] ,
\Q_reg[16] ,
\Q_reg[0] ,
Q,
\Q_reg[4]_0 ,
\Q_reg[0]_0 ,
\Q_reg[25]_0 ,
\Data_array_SWR[4] ,
E,
\Q_reg[2]_0 ,
CLK,
AR);
output [13:0]D;
output [14:0]\Q_reg[23] ;
output [5:0]\Q_reg[25] ;
output [2:0]\Q_reg[16] ;
input [1:0]\Q_reg[0] ;
input [1:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [9:0]\Q_reg[0]_0 ;
input [7:0]\Q_reg[25]_0 ;
input [1:0]\Data_array_SWR[4] ;
input [0:0]E;
input [2:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [13:0]D;
wire [1:0]\Data_array_SWR[4] ;
wire [21:18]\Data_array_SWR[5] ;
wire [23:2]\Data_array_SWR[6] ;
wire [0:0]E;
wire [1:0]Q;
wire [1:0]\Q_reg[0] ;
wire [9:0]\Q_reg[0]_0 ;
wire [2:0]\Q_reg[16] ;
wire [14:0]\Q_reg[23] ;
wire [5:0]\Q_reg[25] ;
wire [7:0]\Q_reg[25]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire [0:0]\Q_reg[4]_0 ;
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[0]_i_1__3
(.I0(\Data_array_SWR[6] [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [2]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'h02))
\Q[14]_i_1__1
(.I0(\Q_reg[23] [7]),
.I1(\Q_reg[0] [0]),
.I2(\Q_reg[0] [1]),
.O(D[6]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[14]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4] [0]),
.O(\Q_reg[25] [2]));
(* SOFT_HLUTNM = "soft_lutpair76" *)
LUT3 #(
.INIT(8'h02))
\Q[15]_i_1__1
(.I0(\Q_reg[23] [8]),
.I1(\Q_reg[0] [0]),
.I2(\Q_reg[0] [1]),
.O(D[7]));
LUT6 #(
.INIT(64'hCDC8DDDDCDC88888))
\Q[15]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [1]),
.I5(\Data_array_SWR[4] [1]),
.O(\Q_reg[25] [3]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[16]_i_1__1
(.I0(\Q_reg[25] [1]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0]_0 [8]),
.O(\Q_reg[23] [7]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[16]_i_1__2
(.I0(\Data_array_SWR[6] [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [18]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[8]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[16]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0]_0 [7]),
.O(\Q_reg[25] [1]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[17]_i_1__1
(.I0(\Q_reg[25] [0]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[16] [2]),
.I4(\Q_reg[0]_0 [9]),
.O(\Q_reg[23] [8]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[17]_i_1__2
(.I0(\Data_array_SWR[6] [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [19]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[9]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[17]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0]_0 [6]),
.O(\Q_reg[25] [0]));
LUT3 #(
.INIT(8'hB8))
\Q[18]_i_1__1
(.I0(\Data_array_SWR[6] [7]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [18]),
.O(\Q_reg[23] [9]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[18]_i_1__2
(.I0(\Data_array_SWR[6] [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [20]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[10]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[18]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0]_0 [5]),
.O(\Data_array_SWR[6] [7]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[18]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[6] [18]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\Q[19]_i_1__1
(.I0(\Data_array_SWR[6] [6]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [19]),
.O(\Q_reg[23] [10]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[19]_i_1__2
(.I0(\Data_array_SWR[6] [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [21]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[11]));
LUT6 #(
.INIT(64'hCDC8FFFFCDC80000))
\Q[19]_i_2__0
(.I0(\Q_reg[16] [1]),
.I1(Q[0]),
.I2(\Q_reg[16] [0]),
.I3(\Q_reg[25]_0 [4]),
.I4(\Q_reg[16] [2]),
.I5(\Q_reg[0]_0 [4]),
.O(\Data_array_SWR[6] [6]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[19]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [5]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[6] [19]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\Q[1]_i_1__3
(.I0(\Q_reg[25] [4]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 ),
.O(\Q_reg[23] [0]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[1]_i_1__5
(.I0(\Data_array_SWR[6] [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [3]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_1__1
(.I0(\Data_array_SWR[6] [5]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [20]),
.O(\Q_reg[23] [11]));
(* SOFT_HLUTNM = "soft_lutpair65" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[20]_i_1__2
(.I0(\Data_array_SWR[6] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [22]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[12]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\Q[20]_i_2__0
(.I0(\Data_array_SWR[5] [21]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0]_0 [3]),
.O(\Data_array_SWR[6] [5]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[20]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [6]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[6] [20]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[20]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [7]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[5] [21]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_1__1
(.I0(\Data_array_SWR[6] [4]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [21]),
.O(\Q_reg[23] [12]));
(* SOFT_HLUTNM = "soft_lutpair67" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[21]_i_1__2
(.I0(\Data_array_SWR[6] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [23]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[13]));
(* SOFT_HLUTNM = "soft_lutpair70" *)
LUT3 #(
.INIT(8'hB8))
\Q[21]_i_2__0
(.I0(\Data_array_SWR[5] [20]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0]_0 [2]),
.O(\Data_array_SWR[6] [4]));
LUT6 #(
.INIT(64'hCDC8CDCDCDC8C8C8))
\Q[21]_i_3
(.I0(\Q_reg[16] [2]),
.I1(Q[0]),
.I2(\Q_reg[16] [1]),
.I3(\Q_reg[25]_0 [7]),
.I4(\Q_reg[16] [0]),
.I5(\Q_reg[25]_0 [3]),
.O(\Data_array_SWR[6] [21]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[21]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [6]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [2]),
.O(\Data_array_SWR[5] [20]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_1__1
(.I0(\Data_array_SWR[6] [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [22]),
.O(\Q_reg[23] [13]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\Q[22]_i_2__0
(.I0(\Data_array_SWR[5] [19]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0]_0 [1]),
.O(\Data_array_SWR[6] [3]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[22]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [4]),
.O(\Data_array_SWR[6] [22]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[22]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [5]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [1]),
.O(\Data_array_SWR[5] [19]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_1__2
(.I0(\Data_array_SWR[6] [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [23]),
.O(\Q_reg[23] [14]));
(* SOFT_HLUTNM = "soft_lutpair68" *)
LUT3 #(
.INIT(8'hB8))
\Q[23]_i_2__0
(.I0(\Data_array_SWR[5] [18]),
.I1(\Q_reg[16] [2]),
.I2(\Q_reg[0]_0 [0]),
.O(\Data_array_SWR[6] [2]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[23]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [5]),
.O(\Data_array_SWR[6] [23]));
LUT5 #(
.INIT(32'hB8BBB888))
\Q[23]_i_4
(.I0(Q[0]),
.I1(\Q_reg[16] [1]),
.I2(\Q_reg[25]_0 [4]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [0]),
.O(\Data_array_SWR[5] [18]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[24]_i_3
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [6]),
.O(\Q_reg[25] [4]));
LUT5 #(
.INIT(32'hF0F1F0E0))
\Q[25]_i_4__0
(.I0(\Q_reg[16] [2]),
.I1(\Q_reg[16] [1]),
.I2(Q[0]),
.I3(\Q_reg[16] [0]),
.I4(\Q_reg[25]_0 [7]),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair69" *)
LUT3 #(
.INIT(8'hB8))
\Q[2]_i_1__5
(.I0(\Data_array_SWR[6] [23]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [2]),
.O(\Q_reg[23] [1]));
(* SOFT_HLUTNM = "soft_lutpair63" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[2]_i_1__8
(.I0(\Data_array_SWR[6] [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [4]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair72" *)
LUT3 #(
.INIT(8'hB8))
\Q[3]_i_1__3
(.I0(\Data_array_SWR[6] [22]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [3]),
.O(\Q_reg[23] [2]));
(* SOFT_HLUTNM = "soft_lutpair64" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[3]_i_1__5
(.I0(\Data_array_SWR[6] [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [5]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair74" *)
LUT3 #(
.INIT(8'hB8))
\Q[4]_i_1__2
(.I0(\Data_array_SWR[6] [21]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [4]),
.O(\Q_reg[23] [3]));
(* SOFT_HLUTNM = "soft_lutpair62" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[4]_i_1__4
(.I0(\Data_array_SWR[6] [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [6]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair71" *)
LUT3 #(
.INIT(8'hB8))
\Q[5]_i_1__1
(.I0(\Data_array_SWR[6] [20]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [5]),
.O(\Q_reg[23] [4]));
(* SOFT_HLUTNM = "soft_lutpair66" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[5]_i_1__2
(.I0(\Data_array_SWR[6] [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [7]),
.I3(\Q_reg[0] [0]),
.I4(\Q_reg[0] [1]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair73" *)
LUT3 #(
.INIT(8'hB8))
\Q[6]_i_1__3
(.I0(\Data_array_SWR[6] [19]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [6]),
.O(\Q_reg[23] [5]));
(* SOFT_HLUTNM = "soft_lutpair75" *)
LUT3 #(
.INIT(8'hB8))
\Q[7]_i_1__2
(.I0(\Data_array_SWR[6] [18]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [7]),
.O(\Q_reg[23] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(\Q_reg[16] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(\Q_reg[16] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(\Q_reg[16] [2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized11
(D,
\Q_reg[15] ,
Q,
\Q_reg[0]_0 ,
\Q_reg[4] ,
\Q_reg[0]_1 ,
\Q_reg[4]_0 ,
E,
\Q_reg[1]_0 ,
CLK,
AR);
output [5:0]D;
output [5:0]\Q_reg[15] ;
output [1:0]Q;
input [1:0]\Q_reg[0]_0 ;
input [0:0]\Q_reg[4] ;
input [3:0]\Q_reg[0]_1 ;
input [3:0]\Q_reg[4]_0 ;
input [0:0]E;
input [1:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [5:0]D;
wire [11:10]\Data_array_SWR[6] ;
wire [0:0]E;
wire [1:0]Q;
wire [1:0]\Q_reg[0]_0 ;
wire [3:0]\Q_reg[0]_1 ;
wire [5:0]\Q_reg[15] ;
wire [1:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[4] ;
wire [3:0]\Q_reg[4]_0 ;
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\Q[10]_i_1__2
(.I0(\Q_reg[4]_0 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [10]),
.O(\Q_reg[15] [2]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\Q[11]_i_1__3
(.I0(\Q_reg[4]_0 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [11]),
.O(\Q_reg[15] [3]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[12]_i_1__3
(.I0(\Data_array_SWR[6] [11]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [2]),
.I3(\Q_reg[0]_0 [0]),
.I4(\Q_reg[0]_0 [1]),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[13]_i_1__2
(.I0(\Data_array_SWR[6] [10]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [3]),
.I3(\Q_reg[0]_0 [0]),
.I4(\Q_reg[0]_0 [1]),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair81" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_1__2
(.I0(\Data_array_SWR[6] [11]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [2]),
.O(\Q_reg[15] [4]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_1 [1]),
.O(\Data_array_SWR[6] [11]));
(* SOFT_HLUTNM = "soft_lutpair80" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_1__2
(.I0(\Data_array_SWR[6] [10]),
.I1(Q[1]),
.I2(\Q_reg[4]_0 [3]),
.O(\Q_reg[15] [5]));
(* SOFT_HLUTNM = "soft_lutpair82" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_1 [0]),
.O(\Data_array_SWR[6] [10]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'h02))
\Q[6]_i_1__2
(.I0(\Q_reg[15] [0]),
.I1(\Q_reg[0]_0 [0]),
.I2(\Q_reg[0]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair79" *)
LUT3 #(
.INIT(8'h02))
\Q[7]_i_1__1
(.I0(\Q_reg[15] [1]),
.I1(\Q_reg[0]_0 [0]),
.I2(\Q_reg[0]_0 [1]),
.O(D[1]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[8]_i_1__1
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_1 [3]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [0]),
.O(\Q_reg[15] [0]));
(* SOFT_HLUTNM = "soft_lutpair78" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[8]_i_1__3
(.I0(\Q_reg[4]_0 [3]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [10]),
.I3(\Q_reg[0]_0 [0]),
.I4(\Q_reg[0]_0 [1]),
.O(D[2]));
LUT5 #(
.INIT(32'hB8FFB800))
\Q[9]_i_1__1
(.I0(Q[0]),
.I1(\Q_reg[4] ),
.I2(\Q_reg[0]_1 [2]),
.I3(Q[1]),
.I4(\Q_reg[4]_0 [1]),
.O(\Q_reg[15] [1]));
(* SOFT_HLUTNM = "soft_lutpair77" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[9]_i_1__3
(.I0(\Q_reg[4]_0 [2]),
.I1(Q[1]),
.I2(\Data_array_SWR[6] [11]),
.I3(\Q_reg[0]_0 [0]),
.I4(\Q_reg[0]_0 [1]),
.O(D[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(Q[1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized12
(Q,
\Q_reg[4] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[4] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[4] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized13
(D,
\Q_reg[3]_0 ,
DI,
S,
\Q_reg[2]_0 ,
\Q_reg[26] ,
Q,
\Q_reg[2]_1 ,
exp_rslt_NRM2_EW1,
\Q_reg[6]_0 ,
\Q_reg[6]_1 ,
\Q_reg[0]_0 ,
\Q_reg[1]_0 ,
\Q_reg[22] ,
CLK,
AR);
output [7:0]D;
output [0:0]\Q_reg[3]_0 ;
output [3:0]DI;
output [0:0]S;
output \Q_reg[2]_0 ;
output [2:0]\Q_reg[26] ;
output [4:0]Q;
output [3:0]\Q_reg[2]_1 ;
input [8:0]exp_rslt_NRM2_EW1;
input [0:0]\Q_reg[6]_0 ;
input \Q_reg[6]_1 ;
input \Q_reg[0]_0 ;
input [0:0]\Q_reg[1]_0 ;
input [12:0]\Q_reg[22] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]D;
wire [3:0]DI;
wire [4:0]Q;
wire \Q_reg[0]_0 ;
wire [0:0]\Q_reg[1]_0 ;
wire [12:0]\Q_reg[22] ;
wire [2:0]\Q_reg[26] ;
wire \Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [0:0]\Q_reg[3]_0 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg[6]_1 ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[9] ;
wire [0:0]S;
wire [8:0]exp_rslt_NRM2_EW1;
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hFE))
\Q[23]_i_1__1
(.I0(exp_rslt_NRM2_EW1[0]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair40" *)
LUT3 #(
.INIT(8'hFE))
\Q[24]_i_1__1
(.I0(exp_rslt_NRM2_EW1[1]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hFE))
\Q[25]_i_1__1
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[2]));
(* SOFT_HLUTNM = "soft_lutpair41" *)
LUT3 #(
.INIT(8'hFE))
\Q[26]_i_1
(.I0(exp_rslt_NRM2_EW1[3]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[3]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hFE))
\Q[27]_i_1
(.I0(exp_rslt_NRM2_EW1[4]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[4]));
(* SOFT_HLUTNM = "soft_lutpair42" *)
LUT3 #(
.INIT(8'hFE))
\Q[28]_i_1
(.I0(exp_rslt_NRM2_EW1[5]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[5]));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hFE))
\Q[29]_i_1
(.I0(exp_rslt_NRM2_EW1[6]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[6]));
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[2]_i_2__0
(.I0(exp_rslt_NRM2_EW1[2]),
.I1(exp_rslt_NRM2_EW1[0]),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[4]),
.I4(exp_rslt_NRM2_EW1[3]),
.O(\Q_reg[2]_0 ));
(* SOFT_HLUTNM = "soft_lutpair43" *)
LUT3 #(
.INIT(8'hFE))
\Q[30]_i_1
(.I0(exp_rslt_NRM2_EW1[7]),
.I1(\Q_reg[6]_0 ),
.I2(\Q_reg[3]_0 ),
.O(D[7]));
LUT6 #(
.INIT(64'hEAAAAAAAAAAAAAAA))
\Q[3]_i_1__2
(.I0(exp_rslt_NRM2_EW1[8]),
.I1(\Q_reg[6]_1 ),
.I2(exp_rslt_NRM2_EW1[1]),
.I3(exp_rslt_NRM2_EW1[0]),
.I4(exp_rslt_NRM2_EW1[3]),
.I5(exp_rslt_NRM2_EW1[2]),
.O(\Q_reg[3]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [4]),
.Q(DI[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [5]),
.Q(DI[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [6]),
.Q(DI[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [8]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[1]_0 ),
.CLR(AR),
.D(\Q_reg[22] [9]),
.Q(\Q_reg_n_0_[9] ));
LUT1 #(
.INIT(2'h1))
S0_carry__0_i_1
(.I0(DI[2]),
.O(DI[1]));
LUT2 #(
.INIT(4'h9))
S0_carry__0_i_2
(.I0(DI[3]),
.I1(\Q_reg_n_0_[7] ),
.O(\Q_reg[2]_1 [3]));
LUT2 #(
.INIT(4'h9))
S0_carry__0_i_3
(.I0(DI[2]),
.I1(DI[3]),
.O(\Q_reg[2]_1 [2]));
LUT2 #(
.INIT(4'h6))
S0_carry__0_i_4
(.I0(DI[2]),
.I1(\Q_reg[0]_0 ),
.O(\Q_reg[2]_1 [1]));
LUT3 #(
.INIT(8'h1E))
S0_carry__0_i_5
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg_n_0_[12] ),
.I2(DI[0]),
.O(\Q_reg[2]_1 [0]));
LUT1 #(
.INIT(2'h1))
S0_carry__1_i_1
(.I0(\Q_reg_n_0_[7] ),
.O(S));
LUT3 #(
.INIT(8'h1E))
S0_carry_i_1
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg_n_0_[11] ),
.I2(Q[3]),
.O(\Q_reg[26] [2]));
LUT3 #(
.INIT(8'h1E))
S0_carry_i_2
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg_n_0_[10] ),
.I2(Q[2]),
.O(\Q_reg[26] [1]));
LUT3 #(
.INIT(8'h1E))
S0_carry_i_3
(.I0(\Q_reg[0]_0 ),
.I1(\Q_reg_n_0_[9] ),
.I2(Q[1]),
.O(\Q_reg[26] [0]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized14
(\Q_reg[26] ,
S,
Q,
D,
CLK,
AR,
\Q_reg[8] );
output \Q_reg[26] ;
output [0:0]S;
input [0:0]Q;
input [0:0]D;
input CLK;
input [0:0]AR;
input [0:0]\Q_reg[8] ;
wire [0:0]AR;
wire CLK;
wire [0:0]D;
wire [0:0]Q;
wire \Q_reg[26] ;
wire [0:0]\Q_reg[8] ;
wire [0:0]S;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q),
.CLR(AR),
.D(D),
.Q(\Q_reg[26] ));
LUT2 #(
.INIT(4'hE))
S0_carry_i_4
(.I0(\Q_reg[26] ),
.I1(\Q_reg[8] ),
.O(S));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized15
(O,
Q,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
CO,
\Q_reg[24]_0 ,
S,
E,
\Q_reg[30]_0 ,
CLK,
AR,
\Q_reg[24]_1 );
output [3:0]O;
output [30:0]Q;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [0:0]CO;
output [3:0]\Q_reg[24]_0 ;
input [0:0]S;
input [0:0]E;
input [30:0]\Q_reg[30]_0 ;
input CLK;
input [0:0]AR;
input [22:0]\Q_reg[24]_1 ;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [30:0]Q;
wire \Q[12]_i_10_n_0 ;
wire \Q[12]_i_11_n_0 ;
wire \Q[12]_i_8_n_0 ;
wire \Q[12]_i_9_n_0 ;
wire \Q[16]_i_10_n_0 ;
wire \Q[16]_i_11_n_0 ;
wire \Q[16]_i_8_n_0 ;
wire \Q[16]_i_9_n_0 ;
wire \Q[20]_i_10_n_0 ;
wire \Q[20]_i_11_n_0 ;
wire \Q[20]_i_8_n_0 ;
wire \Q[20]_i_9_n_0 ;
wire \Q[24]_i_10_n_0 ;
wire \Q[24]_i_11_n_0 ;
wire \Q[24]_i_8_n_0 ;
wire \Q[24]_i_9_n_0 ;
wire \Q[4]_i_10_n_0 ;
wire \Q[4]_i_11_n_0 ;
wire \Q[4]_i_9_n_0 ;
wire \Q[8]_i_10_n_0 ;
wire \Q[8]_i_11_n_0 ;
wire \Q[8]_i_8_n_0 ;
wire \Q[8]_i_9_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_3_n_0 ;
wire \Q_reg[12]_i_3_n_1 ;
wire \Q_reg[12]_i_3_n_2 ;
wire \Q_reg[12]_i_3_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_3_n_0 ;
wire \Q_reg[16]_i_3_n_1 ;
wire \Q_reg[16]_i_3_n_2 ;
wire \Q_reg[16]_i_3_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_3_n_0 ;
wire \Q_reg[20]_i_3_n_1 ;
wire \Q_reg[20]_i_3_n_2 ;
wire \Q_reg[20]_i_3_n_3 ;
wire [3:0]\Q_reg[24]_0 ;
wire [22:0]\Q_reg[24]_1 ;
wire \Q_reg[24]_i_3_n_1 ;
wire \Q_reg[24]_i_3_n_2 ;
wire \Q_reg[24]_i_3_n_3 ;
wire [30:0]\Q_reg[30]_0 ;
wire \Q_reg[4]_i_3_n_0 ;
wire \Q_reg[4]_i_3_n_1 ;
wire \Q_reg[4]_i_3_n_2 ;
wire \Q_reg[4]_i_3_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_3_n_0 ;
wire \Q_reg[8]_i_3_n_1 ;
wire \Q_reg[8]_i_3_n_2 ;
wire \Q_reg[8]_i_3_n_3 ;
wire [0:0]S;
LUT2 #(
.INIT(4'h6))
\Q[12]_i_10
(.I0(Q[8]),
.I1(\Q_reg[24]_1 [8]),
.O(\Q[12]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_11
(.I0(Q[7]),
.I1(\Q_reg[24]_1 [7]),
.O(\Q[12]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_8
(.I0(Q[10]),
.I1(\Q_reg[24]_1 [10]),
.O(\Q[12]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[12]_i_9
(.I0(Q[9]),
.I1(\Q_reg[24]_1 [9]),
.O(\Q[12]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_10
(.I0(Q[12]),
.I1(\Q_reg[24]_1 [12]),
.O(\Q[16]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_11
(.I0(Q[11]),
.I1(\Q_reg[24]_1 [11]),
.O(\Q[16]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_8
(.I0(Q[14]),
.I1(\Q_reg[24]_1 [14]),
.O(\Q[16]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[16]_i_9
(.I0(Q[13]),
.I1(\Q_reg[24]_1 [13]),
.O(\Q[16]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_10
(.I0(Q[16]),
.I1(\Q_reg[24]_1 [16]),
.O(\Q[20]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_11
(.I0(Q[15]),
.I1(\Q_reg[24]_1 [15]),
.O(\Q[20]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_8
(.I0(Q[18]),
.I1(\Q_reg[24]_1 [18]),
.O(\Q[20]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[20]_i_9
(.I0(Q[17]),
.I1(\Q_reg[24]_1 [17]),
.O(\Q[20]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_10
(.I0(Q[20]),
.I1(\Q_reg[24]_1 [20]),
.O(\Q[24]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_11
(.I0(Q[19]),
.I1(\Q_reg[24]_1 [19]),
.O(\Q[24]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_8
(.I0(Q[22]),
.I1(\Q_reg[24]_1 [22]),
.O(\Q[24]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[24]_i_9
(.I0(Q[21]),
.I1(\Q_reg[24]_1 [21]),
.O(\Q[24]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_10
(.I0(Q[1]),
.I1(\Q_reg[24]_1 [1]),
.O(\Q[4]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_11
(.I0(Q[0]),
.I1(\Q_reg[24]_1 [0]),
.O(\Q[4]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[4]_i_9
(.I0(Q[2]),
.I1(\Q_reg[24]_1 [2]),
.O(\Q[4]_i_9_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_10
(.I0(Q[4]),
.I1(\Q_reg[24]_1 [4]),
.O(\Q[8]_i_10_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_11
(.I0(Q[3]),
.I1(\Q_reg[24]_1 [3]),
.O(\Q[8]_i_11_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_8
(.I0(Q[6]),
.I1(\Q_reg[24]_1 [6]),
.O(\Q[8]_i_8_n_0 ));
LUT2 #(
.INIT(4'h6))
\Q[8]_i_9
(.I0(Q[5]),
.I1(\Q_reg[24]_1 [5]),
.O(\Q[8]_i_9_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [12]),
.Q(Q[12]));
CARRY4 \Q_reg[12]_i_3
(.CI(\Q_reg[8]_i_3_n_0 ),
.CO({\Q_reg[12]_i_3_n_0 ,\Q_reg[12]_i_3_n_1 ,\Q_reg[12]_i_3_n_2 ,\Q_reg[12]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_8_n_0 ,\Q[12]_i_9_n_0 ,\Q[12]_i_10_n_0 ,\Q[12]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [16]),
.Q(Q[16]));
CARRY4 \Q_reg[16]_i_3
(.CI(\Q_reg[12]_i_3_n_0 ),
.CO({\Q_reg[16]_i_3_n_0 ,\Q_reg[16]_i_3_n_1 ,\Q_reg[16]_i_3_n_2 ,\Q_reg[16]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_8_n_0 ,\Q[16]_i_9_n_0 ,\Q[16]_i_10_n_0 ,\Q[16]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [20]),
.Q(Q[20]));
CARRY4 \Q_reg[20]_i_3
(.CI(\Q_reg[16]_i_3_n_0 ),
.CO({\Q_reg[20]_i_3_n_0 ,\Q_reg[20]_i_3_n_1 ,\Q_reg[20]_i_3_n_2 ,\Q_reg[20]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_8_n_0 ,\Q[20]_i_9_n_0 ,\Q[20]_i_10_n_0 ,\Q[20]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [24]),
.Q(Q[24]));
CARRY4 \Q_reg[24]_i_3
(.CI(\Q_reg[20]_i_3_n_0 ),
.CO({CO,\Q_reg[24]_i_3_n_1 ,\Q_reg[24]_i_3_n_2 ,\Q_reg[24]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_8_n_0 ,\Q[24]_i_9_n_0 ,\Q[24]_i_10_n_0 ,\Q[24]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [4]),
.Q(Q[4]));
CARRY4 \Q_reg[4]_i_3
(.CI(1'b0),
.CO({\Q_reg[4]_i_3_n_0 ,\Q_reg[4]_i_3_n_1 ,\Q_reg[4]_i_3_n_2 ,\Q_reg[4]_i_3_n_3 }),
.CYINIT(1'b0),
.DI({Q[2:0],1'b0}),
.O(O),
.S({\Q[4]_i_9_n_0 ,\Q[4]_i_10_n_0 ,\Q[4]_i_11_n_0 ,S}));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [8]),
.Q(Q[8]));
CARRY4 \Q_reg[8]_i_3
(.CI(\Q_reg[4]_i_3_n_0 ),
.CO({\Q_reg[8]_i_3_n_0 ,\Q_reg[8]_i_3_n_1 ,\Q_reg[8]_i_3_n_2 ,\Q_reg[8]_i_3_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_8_n_0 ,\Q[8]_i_9_n_0 ,\Q[8]_i_10_n_0 ,\Q[8]_i_11_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[30]_0 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized16
(O,
\Q_reg[8]_0 ,
\Q_reg[12]_0 ,
\Q_reg[16]_0 ,
\Q_reg[20]_0 ,
\Q_reg[24]_0 ,
\Q_reg[25]_0 ,
CO,
\Q_reg[25]_1 ,
\Q_reg[24]_1 ,
S,
Q,
\Q_reg[22]_0 ,
E,
D,
CLK,
AR);
output [3:0]O;
output [3:0]\Q_reg[8]_0 ;
output [3:0]\Q_reg[12]_0 ;
output [3:0]\Q_reg[16]_0 ;
output [3:0]\Q_reg[20]_0 ;
output [3:0]\Q_reg[24]_0 ;
output [0:0]\Q_reg[25]_0 ;
output [0:0]CO;
output [0:0]\Q_reg[25]_1 ;
output [23:0]\Q_reg[24]_1 ;
output [0:0]S;
input [22:0]Q;
input [0:0]\Q_reg[22]_0 ;
input [0:0]E;
input [25:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [0:0]E;
wire [3:0]O;
wire [22:0]Q;
wire \Q[12]_i_4__0_n_0 ;
wire \Q[12]_i_5__0_n_0 ;
wire \Q[12]_i_6__0_n_0 ;
wire \Q[12]_i_7_n_0 ;
wire \Q[16]_i_4_n_0 ;
wire \Q[16]_i_5_n_0 ;
wire \Q[16]_i_6_n_0 ;
wire \Q[16]_i_7_n_0 ;
wire \Q[20]_i_4__0_n_0 ;
wire \Q[20]_i_5__0_n_0 ;
wire \Q[20]_i_6_n_0 ;
wire \Q[20]_i_7_n_0 ;
wire \Q[24]_i_4__0_n_0 ;
wire \Q[24]_i_5_n_0 ;
wire \Q[24]_i_6_n_0 ;
wire \Q[24]_i_7_n_0 ;
wire \Q[25]_i_5__0_n_0 ;
wire \Q[4]_i_5_n_0 ;
wire \Q[4]_i_6_n_0 ;
wire \Q[4]_i_7_n_0 ;
wire \Q[8]_i_4__0_n_0 ;
wire \Q[8]_i_5__0_n_0 ;
wire \Q[8]_i_6_n_0 ;
wire \Q[8]_i_7_n_0 ;
wire [3:0]\Q_reg[12]_0 ;
wire \Q_reg[12]_i_2_n_0 ;
wire \Q_reg[12]_i_2_n_1 ;
wire \Q_reg[12]_i_2_n_2 ;
wire \Q_reg[12]_i_2_n_3 ;
wire [3:0]\Q_reg[16]_0 ;
wire \Q_reg[16]_i_2_n_0 ;
wire \Q_reg[16]_i_2_n_1 ;
wire \Q_reg[16]_i_2_n_2 ;
wire \Q_reg[16]_i_2_n_3 ;
wire [3:0]\Q_reg[20]_0 ;
wire \Q_reg[20]_i_2_n_0 ;
wire \Q_reg[20]_i_2_n_1 ;
wire \Q_reg[20]_i_2_n_2 ;
wire \Q_reg[20]_i_2_n_3 ;
wire [0:0]\Q_reg[22]_0 ;
wire [3:0]\Q_reg[24]_0 ;
wire [23:0]\Q_reg[24]_1 ;
wire \Q_reg[24]_i_2_n_0 ;
wire \Q_reg[24]_i_2_n_1 ;
wire \Q_reg[24]_i_2_n_2 ;
wire \Q_reg[24]_i_2_n_3 ;
wire [0:0]\Q_reg[25]_0 ;
wire [0:0]\Q_reg[25]_1 ;
wire \Q_reg[4]_i_2_n_0 ;
wire \Q_reg[4]_i_2_n_1 ;
wire \Q_reg[4]_i_2_n_2 ;
wire \Q_reg[4]_i_2_n_3 ;
wire [3:0]\Q_reg[8]_0 ;
wire \Q_reg[8]_i_2_n_0 ;
wire \Q_reg[8]_i_2_n_1 ;
wire \Q_reg[8]_i_2_n_2 ;
wire \Q_reg[8]_i_2_n_3 ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[25] ;
wire [1:0]p_0_in;
wire [3:0]\NLW_Q_reg[25]_i_2_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_2_O_UNCONNECTED ;
wire [3:0]\NLW_Q_reg[25]_i_3_CO_UNCONNECTED ;
wire [3:1]\NLW_Q_reg[25]_i_3_O_UNCONNECTED ;
assign S[0] = \Q_reg_n_0_[1] ;
LUT2 #(
.INIT(4'h9))
\Q[12]_i_4__0
(.I0(\Q_reg[24]_1 [11]),
.I1(Q[10]),
.O(\Q[12]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_5__0
(.I0(\Q_reg[24]_1 [10]),
.I1(Q[9]),
.O(\Q[12]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_6__0
(.I0(\Q_reg[24]_1 [9]),
.I1(Q[8]),
.O(\Q[12]_i_6__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[12]_i_7
(.I0(\Q_reg[24]_1 [8]),
.I1(Q[7]),
.O(\Q[12]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_4
(.I0(\Q_reg[24]_1 [15]),
.I1(Q[14]),
.O(\Q[16]_i_4_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_5
(.I0(\Q_reg[24]_1 [14]),
.I1(Q[13]),
.O(\Q[16]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_6
(.I0(\Q_reg[24]_1 [13]),
.I1(Q[12]),
.O(\Q[16]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[16]_i_7
(.I0(\Q_reg[24]_1 [12]),
.I1(Q[11]),
.O(\Q[16]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_4__0
(.I0(\Q_reg[24]_1 [19]),
.I1(Q[18]),
.O(\Q[20]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_5__0
(.I0(\Q_reg[24]_1 [18]),
.I1(Q[17]),
.O(\Q[20]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_6
(.I0(\Q_reg[24]_1 [17]),
.I1(Q[16]),
.O(\Q[20]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[20]_i_7
(.I0(\Q_reg[24]_1 [16]),
.I1(Q[15]),
.O(\Q[20]_i_7_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_4__0
(.I0(\Q_reg[24]_1 [23]),
.I1(Q[22]),
.O(\Q[24]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_5
(.I0(\Q_reg[24]_1 [22]),
.I1(Q[21]),
.O(\Q[24]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_6
(.I0(\Q_reg[24]_1 [21]),
.I1(Q[20]),
.O(\Q[24]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[24]_i_7
(.I0(\Q_reg[24]_1 [20]),
.I1(Q[19]),
.O(\Q[24]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[25]_i_5__0
(.I0(\Q_reg_n_0_[25] ),
.O(\Q[25]_i_5__0_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_4
(.I0(\Q_reg[24]_1 [0]),
.O(p_0_in[0]));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_5
(.I0(\Q_reg[24]_1 [3]),
.I1(Q[2]),
.O(\Q[4]_i_5_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_6
(.I0(\Q_reg[24]_1 [2]),
.I1(Q[1]),
.O(\Q[4]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[4]_i_7
(.I0(\Q_reg[24]_1 [1]),
.I1(Q[0]),
.O(\Q[4]_i_7_n_0 ));
LUT1 #(
.INIT(2'h1))
\Q[4]_i_8
(.I0(\Q_reg_n_0_[1] ),
.O(p_0_in[1]));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_4__0
(.I0(\Q_reg[24]_1 [7]),
.I1(Q[6]),
.O(\Q[8]_i_4__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_5__0
(.I0(\Q_reg[24]_1 [6]),
.I1(Q[5]),
.O(\Q[8]_i_5__0_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_6
(.I0(\Q_reg[24]_1 [5]),
.I1(Q[4]),
.O(\Q[8]_i_6_n_0 ));
LUT2 #(
.INIT(4'h9))
\Q[8]_i_7
(.I0(\Q_reg[24]_1 [4]),
.I1(Q[3]),
.O(\Q[8]_i_7_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[0]),
.Q(\Q_reg[24]_1 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[10]),
.Q(\Q_reg[24]_1 [9]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[11]),
.Q(\Q_reg[24]_1 [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[12]),
.Q(\Q_reg[24]_1 [11]));
CARRY4 \Q_reg[12]_i_2
(.CI(\Q_reg[8]_i_2_n_0 ),
.CO({\Q_reg[12]_i_2_n_0 ,\Q_reg[12]_i_2_n_1 ,\Q_reg[12]_i_2_n_2 ,\Q_reg[12]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[10:7]),
.O(\Q_reg[12]_0 ),
.S({\Q[12]_i_4__0_n_0 ,\Q[12]_i_5__0_n_0 ,\Q[12]_i_6__0_n_0 ,\Q[12]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[13]),
.Q(\Q_reg[24]_1 [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[14]),
.Q(\Q_reg[24]_1 [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[15]),
.Q(\Q_reg[24]_1 [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[16]),
.Q(\Q_reg[24]_1 [15]));
CARRY4 \Q_reg[16]_i_2
(.CI(\Q_reg[12]_i_2_n_0 ),
.CO({\Q_reg[16]_i_2_n_0 ,\Q_reg[16]_i_2_n_1 ,\Q_reg[16]_i_2_n_2 ,\Q_reg[16]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[14:11]),
.O(\Q_reg[16]_0 ),
.S({\Q[16]_i_4_n_0 ,\Q[16]_i_5_n_0 ,\Q[16]_i_6_n_0 ,\Q[16]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[17]),
.Q(\Q_reg[24]_1 [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[18]),
.Q(\Q_reg[24]_1 [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[19]),
.Q(\Q_reg[24]_1 [18]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[20]),
.Q(\Q_reg[24]_1 [19]));
CARRY4 \Q_reg[20]_i_2
(.CI(\Q_reg[16]_i_2_n_0 ),
.CO({\Q_reg[20]_i_2_n_0 ,\Q_reg[20]_i_2_n_1 ,\Q_reg[20]_i_2_n_2 ,\Q_reg[20]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[18:15]),
.O(\Q_reg[20]_0 ),
.S({\Q[20]_i_4__0_n_0 ,\Q[20]_i_5__0_n_0 ,\Q[20]_i_6_n_0 ,\Q[20]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[21]),
.Q(\Q_reg[24]_1 [20]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[22]),
.Q(\Q_reg[24]_1 [21]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[23]),
.Q(\Q_reg[24]_1 [22]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[24]),
.Q(\Q_reg[24]_1 [23]));
CARRY4 \Q_reg[24]_i_2
(.CI(\Q_reg[20]_i_2_n_0 ),
.CO({\Q_reg[24]_i_2_n_0 ,\Q_reg[24]_i_2_n_1 ,\Q_reg[24]_i_2_n_2 ,\Q_reg[24]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[22:19]),
.O(\Q_reg[24]_0 ),
.S({\Q[24]_i_4__0_n_0 ,\Q[24]_i_5_n_0 ,\Q[24]_i_6_n_0 ,\Q[24]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[25]),
.Q(\Q_reg_n_0_[25] ));
CARRY4 \Q_reg[25]_i_2
(.CI(\Q_reg[24]_i_2_n_0 ),
.CO(\NLW_Q_reg[25]_i_2_CO_UNCONNECTED [3:0]),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,1'b0}),
.O({\NLW_Q_reg[25]_i_2_O_UNCONNECTED [3:1],\Q_reg[25]_0 }),
.S({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }));
CARRY4 \Q_reg[25]_i_3
(.CI(\Q_reg[22]_0 ),
.CO({\NLW_Q_reg[25]_i_3_CO_UNCONNECTED [3:2],CO,\NLW_Q_reg[25]_i_3_CO_UNCONNECTED [0]}),
.CYINIT(1'b0),
.DI({1'b0,1'b0,1'b0,\Q_reg_n_0_[25] }),
.O({\NLW_Q_reg[25]_i_3_O_UNCONNECTED [3:1],\Q_reg[25]_1 }),
.S({1'b0,1'b0,1'b1,\Q[25]_i_5__0_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[2]),
.Q(\Q_reg[24]_1 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[3]),
.Q(\Q_reg[24]_1 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[4]),
.Q(\Q_reg[24]_1 [3]));
CARRY4 \Q_reg[4]_i_2
(.CI(1'b0),
.CO({\Q_reg[4]_i_2_n_0 ,\Q_reg[4]_i_2_n_1 ,\Q_reg[4]_i_2_n_2 ,\Q_reg[4]_i_2_n_3 }),
.CYINIT(p_0_in[0]),
.DI({Q[2:0],1'b0}),
.O(O),
.S({\Q[4]_i_5_n_0 ,\Q[4]_i_6_n_0 ,\Q[4]_i_7_n_0 ,p_0_in[1]}));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[5]),
.Q(\Q_reg[24]_1 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[6]),
.Q(\Q_reg[24]_1 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[7]),
.Q(\Q_reg[24]_1 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[8]),
.Q(\Q_reg[24]_1 [7]));
CARRY4 \Q_reg[8]_i_2
(.CI(\Q_reg[4]_i_2_n_0 ),
.CO({\Q_reg[8]_i_2_n_0 ,\Q_reg[8]_i_2_n_1 ,\Q_reg[8]_i_2_n_2 ,\Q_reg[8]_i_2_n_3 }),
.CYINIT(1'b0),
.DI(Q[6:3]),
.O(\Q_reg[8]_0 ),
.S({\Q[8]_i_4__0_n_0 ,\Q[8]_i_5__0_n_0 ,\Q[8]_i_6_n_0 ,\Q[8]_i_7_n_0 }));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(D[9]),
.Q(\Q_reg[24]_1 [8]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized17
(\Q_reg[2]_0 ,
Q,
\Q_reg[25] ,
CO,
O,
\Q_reg[2]_1 ,
\Q_reg[6] ,
\Q_reg[6]_0 ,
\Q_reg[10] ,
\Q_reg[10]_0 ,
\Q_reg[14] ,
\Q_reg[14]_0 ,
\Q_reg[18] ,
\Q_reg[18]_0 ,
\Q_reg[22] ,
\Q_reg[22]_0 ,
\Q_reg[22]_1 ,
\Q_reg[25]_0 ,
E,
\Q_reg[2]_2 ,
CLK,
AR);
output [2:0]\Q_reg[2]_0 ;
output [0:0]Q;
output [24:0]\Q_reg[25] ;
input [0:0]CO;
input [3:0]O;
input [3:0]\Q_reg[2]_1 ;
input [3:0]\Q_reg[6] ;
input [3:0]\Q_reg[6]_0 ;
input [3:0]\Q_reg[10] ;
input [3:0]\Q_reg[10]_0 ;
input [3:0]\Q_reg[14] ;
input [3:0]\Q_reg[14]_0 ;
input [3:0]\Q_reg[18] ;
input [3:0]\Q_reg[18]_0 ;
input [3:0]\Q_reg[22] ;
input [3:0]\Q_reg[22]_0 ;
input [0:0]\Q_reg[22]_1 ;
input [0:0]\Q_reg[25]_0 ;
input [0:0]E;
input [2:0]\Q_reg[2]_2 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]E;
wire [3:0]O;
wire [0:0]Q;
wire [3:0]\Q_reg[10] ;
wire [3:0]\Q_reg[10]_0 ;
wire [3:0]\Q_reg[14] ;
wire [3:0]\Q_reg[14]_0 ;
wire [3:0]\Q_reg[18] ;
wire [3:0]\Q_reg[18]_0 ;
wire [3:0]\Q_reg[22] ;
wire [3:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[22]_1 ;
wire [24:0]\Q_reg[25] ;
wire [0:0]\Q_reg[25]_0 ;
wire [2:0]\Q_reg[2]_0 ;
wire [3:0]\Q_reg[2]_1 ;
wire [2:0]\Q_reg[2]_2 ;
wire [3:0]\Q_reg[6] ;
wire [3:0]\Q_reg[6]_0 ;
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[10]_i_1__0
(.I0(\Q_reg[10] [1]),
.I1(\Q_reg[10]_0 [1]),
.I2(Q),
.O(\Q_reg[25] [9]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[11]_i_1__1
(.I0(\Q_reg[10] [2]),
.I1(\Q_reg[10]_0 [2]),
.I2(Q),
.O(\Q_reg[25] [10]));
(* SOFT_HLUTNM = "soft_lutpair51" *)
LUT3 #(
.INIT(8'hAC))
\Q[12]_i_1__0
(.I0(\Q_reg[10] [3]),
.I1(\Q_reg[10]_0 [3]),
.I2(Q),
.O(\Q_reg[25] [11]));
(* SOFT_HLUTNM = "soft_lutpair50" *)
LUT3 #(
.INIT(8'hAC))
\Q[13]_i_1__0
(.I0(\Q_reg[14] [0]),
.I1(\Q_reg[14]_0 [0]),
.I2(Q),
.O(\Q_reg[25] [12]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[14]_i_1__0
(.I0(\Q_reg[14] [1]),
.I1(\Q_reg[14]_0 [1]),
.I2(Q),
.O(\Q_reg[25] [13]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[15]_i_1__0
(.I0(\Q_reg[14] [2]),
.I1(\Q_reg[14]_0 [2]),
.I2(Q),
.O(\Q_reg[25] [14]));
(* SOFT_HLUTNM = "soft_lutpair49" *)
LUT3 #(
.INIT(8'hAC))
\Q[16]_i_1__0
(.I0(\Q_reg[14] [3]),
.I1(\Q_reg[14]_0 [3]),
.I2(Q),
.O(\Q_reg[25] [15]));
(* SOFT_HLUTNM = "soft_lutpair48" *)
LUT3 #(
.INIT(8'hAC))
\Q[17]_i_1__0
(.I0(\Q_reg[18] [0]),
.I1(\Q_reg[18]_0 [0]),
.I2(Q),
.O(\Q_reg[25] [16]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[18]_i_1__0
(.I0(\Q_reg[18] [1]),
.I1(\Q_reg[18]_0 [1]),
.I2(Q),
.O(\Q_reg[25] [17]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[19]_i_1__0
(.I0(\Q_reg[18] [2]),
.I1(\Q_reg[18]_0 [2]),
.I2(Q),
.O(\Q_reg[25] [18]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[1]_i_1__1
(.I0(O[0]),
.I1(\Q_reg[2]_1 [0]),
.I2(Q),
.O(\Q_reg[25] [0]));
(* SOFT_HLUTNM = "soft_lutpair47" *)
LUT3 #(
.INIT(8'hAC))
\Q[20]_i_1__0
(.I0(\Q_reg[18] [3]),
.I1(\Q_reg[18]_0 [3]),
.I2(Q),
.O(\Q_reg[25] [19]));
(* SOFT_HLUTNM = "soft_lutpair46" *)
LUT3 #(
.INIT(8'hAC))
\Q[21]_i_1__0
(.I0(\Q_reg[22] [0]),
.I1(\Q_reg[22]_0 [0]),
.I2(Q),
.O(\Q_reg[25] [20]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[22]_i_1__0
(.I0(\Q_reg[22] [1]),
.I1(\Q_reg[22]_0 [1]),
.I2(Q),
.O(\Q_reg[25] [21]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[23]_i_1__0
(.I0(\Q_reg[22] [2]),
.I1(\Q_reg[22]_0 [2]),
.I2(Q),
.O(\Q_reg[25] [22]));
(* SOFT_HLUTNM = "soft_lutpair45" *)
LUT3 #(
.INIT(8'hAC))
\Q[24]_i_1__0
(.I0(\Q_reg[22] [3]),
.I1(\Q_reg[22]_0 [3]),
.I2(Q),
.O(\Q_reg[25] [23]));
(* SOFT_HLUTNM = "soft_lutpair44" *)
LUT3 #(
.INIT(8'hAC))
\Q[25]_i_1__0
(.I0(\Q_reg[22]_1 ),
.I1(\Q_reg[25]_0 ),
.I2(Q),
.O(\Q_reg[25] [24]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__0
(.I0(CO),
.I1(Q),
.O(\Q_reg[2]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__3
(.I0(O[1]),
.I1(\Q_reg[2]_1 [1]),
.I2(Q),
.O(\Q_reg[25] [1]));
(* SOFT_HLUTNM = "soft_lutpair56" *)
LUT3 #(
.INIT(8'hAC))
\Q[3]_i_1__1
(.I0(O[2]),
.I1(\Q_reg[2]_1 [2]),
.I2(Q),
.O(\Q_reg[25] [2]));
(* SOFT_HLUTNM = "soft_lutpair55" *)
LUT3 #(
.INIT(8'hAC))
\Q[4]_i_1__1
(.I0(O[3]),
.I1(\Q_reg[2]_1 [3]),
.I2(Q),
.O(\Q_reg[25] [3]));
(* SOFT_HLUTNM = "soft_lutpair54" *)
LUT3 #(
.INIT(8'hAC))
\Q[5]_i_1__0
(.I0(\Q_reg[6] [0]),
.I1(\Q_reg[6]_0 [0]),
.I2(Q),
.O(\Q_reg[25] [4]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[6]_i_1__0
(.I0(\Q_reg[6] [1]),
.I1(\Q_reg[6]_0 [1]),
.I2(Q),
.O(\Q_reg[25] [5]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[7]_i_1__0
(.I0(\Q_reg[6] [2]),
.I1(\Q_reg[6]_0 [2]),
.I2(Q),
.O(\Q_reg[25] [6]));
(* SOFT_HLUTNM = "soft_lutpair53" *)
LUT3 #(
.INIT(8'hAC))
\Q[8]_i_1__0
(.I0(\Q_reg[6] [3]),
.I1(\Q_reg[6]_0 [3]),
.I2(Q),
.O(\Q_reg[25] [7]));
(* SOFT_HLUTNM = "soft_lutpair52" *)
LUT3 #(
.INIT(8'hAC))
\Q[9]_i_1__0
(.I0(\Q_reg[10] [0]),
.I1(\Q_reg[10]_0 [0]),
.I2(Q),
.O(\Q_reg[25] [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_2 [0]),
.Q(\Q_reg[2]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_2 [1]),
.Q(Q));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_2 [2]),
.Q(\Q_reg[2]_0 [1]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized18
(D,
\Q_reg[12]_0 ,
\Q_reg[4]_0 ,
\Q_reg[2]_0 ,
Q,
\Q_reg[1]_0 ,
CO,
\Q_reg[22]_0 ,
left_right_SHT1,
\Q_reg[4]_1 ,
\Q_reg[1]_1 ,
CLK,
AR);
output [25:0]D;
output [4:0]\Q_reg[12]_0 ;
output [2:0]\Q_reg[4]_0 ;
input [0:0]\Q_reg[2]_0 ;
input [1:0]Q;
input [0:0]\Q_reg[1]_0 ;
input [0:0]CO;
input [22:0]\Q_reg[22]_0 ;
input left_right_SHT1;
input [4:0]\Q_reg[4]_1 ;
input [25:0]\Q_reg[1]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [25:0]D;
wire [25:0]\Data_array_SWR[0] ;
wire [1:0]Q;
wire \Q[10]_i_2__0_n_0 ;
wire \Q[10]_i_3_n_0 ;
wire \Q[10]_i_4_n_0 ;
wire \Q[11]_i_2__0_n_0 ;
wire \Q[11]_i_3_n_0 ;
wire \Q[11]_i_4_n_0 ;
wire \Q[11]_i_5_n_0 ;
wire \Q[11]_i_6_n_0 ;
wire \Q[12]_i_2__0_n_0 ;
wire \Q[12]_i_3_n_0 ;
wire \Q[12]_i_4_n_0 ;
wire \Q[12]_i_5_n_0 ;
wire \Q[12]_i_6_n_0 ;
wire \Q[12]_i_7__0_n_0 ;
wire \Q[8]_i_10__0_n_0 ;
wire \Q[8]_i_11__0_n_0 ;
wire \Q[8]_i_2__0_n_0 ;
wire \Q[8]_i_3_n_0 ;
wire \Q[8]_i_4_n_0 ;
wire \Q[8]_i_5_n_0 ;
wire \Q[8]_i_6__0_n_0 ;
wire \Q[8]_i_7__0_n_0 ;
wire \Q[8]_i_8__0_n_0 ;
wire \Q[8]_i_9__0_n_0 ;
wire \Q[9]_i_2__0_n_0 ;
wire \Q[9]_i_3_n_0 ;
wire \Q[9]_i_4_n_0 ;
wire \Q[9]_i_5_n_0 ;
wire \Q[9]_i_6_n_0 ;
wire [4:0]\Q_reg[12]_0 ;
wire [0:0]\Q_reg[1]_0 ;
wire [25:0]\Q_reg[1]_1 ;
wire [22:0]\Q_reg[22]_0 ;
wire [0:0]\Q_reg[2]_0 ;
wire [2:0]\Q_reg[4]_0 ;
wire [4:0]\Q_reg[4]_1 ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[10] ;
wire \Q_reg_n_0_[11] ;
wire \Q_reg_n_0_[12] ;
wire \Q_reg_n_0_[13] ;
wire \Q_reg_n_0_[14] ;
wire \Q_reg_n_0_[15] ;
wire \Q_reg_n_0_[16] ;
wire \Q_reg_n_0_[17] ;
wire \Q_reg_n_0_[18] ;
wire \Q_reg_n_0_[19] ;
wire \Q_reg_n_0_[1] ;
wire \Q_reg_n_0_[20] ;
wire \Q_reg_n_0_[21] ;
wire \Q_reg_n_0_[22] ;
wire \Q_reg_n_0_[23] ;
wire \Q_reg_n_0_[24] ;
wire \Q_reg_n_0_[25] ;
wire \Q_reg_n_0_[2] ;
wire \Q_reg_n_0_[3] ;
wire \Q_reg_n_0_[4] ;
wire \Q_reg_n_0_[5] ;
wire \Q_reg_n_0_[6] ;
wire \Q_reg_n_0_[7] ;
wire \Q_reg_n_0_[8] ;
wire \Q_reg_n_0_[9] ;
wire left_right_SHT1;
wire [1:0]shft_value_mux_o_EWR__0;
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[0]_i_1
(.I0(\Data_array_SWR[0] [3]),
.I1(\Data_array_SWR[0] [2]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [1]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'h8C888088))
\Q[0]_i_2
(.I0(\Q_reg_n_0_[25] ),
.I1(Q[0]),
.I2(\Q_reg[1]_0 ),
.I3(CO),
.I4(\Q_reg_n_0_[0] ),
.O(\Data_array_SWR[0] [0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[10]_i_1
(.I0(\Data_array_SWR[0] [13]),
.I1(\Data_array_SWR[0] [12]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [11]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [10]),
.O(D[10]));
LUT6 #(
.INIT(64'h000000000000000E))
\Q[10]_i_1__3
(.I0(\Q[10]_i_2__0_n_0 ),
.I1(\Q[12]_i_2__0_n_0 ),
.I2(\Q_reg_n_0_[24] ),
.I3(\Q_reg_n_0_[25] ),
.I4(\Q_reg_n_0_[22] ),
.I5(\Q_reg_n_0_[23] ),
.O(\Q_reg[12]_0 [2]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[10]_i_2
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg[22]_0 [13]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[10] ),
.I4(\Q_reg[22]_0 [8]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [10]));
LUT6 #(
.INIT(64'h00000000FFFFFFFE))
\Q[10]_i_2__0
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[12] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[10]_i_3_n_0 ),
.I5(\Q[12]_i_6_n_0 ),
.O(\Q[10]_i_2__0_n_0 ));
LUT5 #(
.INIT(32'h00000002))
\Q[10]_i_3
(.I0(\Q[10]_i_4_n_0 ),
.I1(\Q_reg_n_0_[6] ),
.I2(\Q_reg_n_0_[7] ),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg_n_0_[8] ),
.O(\Q[10]_i_3_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFFFFFFFF4))
\Q[10]_i_4
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg_n_0_[0] ),
.I2(\Q_reg_n_0_[3] ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg_n_0_[4] ),
.I5(\Q_reg_n_0_[5] ),
.O(\Q[10]_i_4_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[11]_i_1
(.I0(\Data_array_SWR[0] [14]),
.I1(\Data_array_SWR[0] [13]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [12]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [11]),
.O(D[11]));
LUT6 #(
.INIT(64'h1010101010101110))
\Q[11]_i_1__0
(.I0(\Q[11]_i_2__0_n_0 ),
.I1(\Q[12]_i_2__0_n_0 ),
.I2(\Q[11]_i_3_n_0 ),
.I3(\Q[11]_i_4_n_0 ),
.I4(\Q_reg_n_0_[7] ),
.I5(\Q[11]_i_5_n_0 ),
.O(\Q_reg[12]_0 [3]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[11]_i_2
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg[22]_0 [12]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg[22]_0 [9]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [11]));
LUT4 #(
.INIT(16'hFFFE))
\Q[11]_i_2__0
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg_n_0_[22] ),
.I2(\Q_reg_n_0_[25] ),
.I3(\Q_reg_n_0_[24] ),
.O(\Q[11]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[11]_i_3
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q[11]_i_6_n_0 ),
.O(\Q[11]_i_3_n_0 ));
LUT6 #(
.INIT(64'h0000000000000002))
\Q[11]_i_4
(.I0(\Q_reg_n_0_[1] ),
.I1(\Q_reg_n_0_[5] ),
.I2(\Q_reg_n_0_[2] ),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg_n_0_[4] ),
.I5(\Q_reg_n_0_[3] ),
.O(\Q[11]_i_4_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT2 #(
.INIT(4'hE))
\Q[11]_i_5
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[9] ),
.O(\Q[11]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[11]_i_6
(.I0(\Q_reg_n_0_[14] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[16] ),
.I3(\Q_reg_n_0_[15] ),
.O(\Q[11]_i_6_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[12]_i_1
(.I0(\Data_array_SWR[0] [15]),
.I1(\Data_array_SWR[0] [14]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [13]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [12]),
.O(D[12]));
LUT6 #(
.INIT(64'h0000000000000001))
\Q[12]_i_1__2
(.I0(\Q[12]_i_2__0_n_0 ),
.I1(\Q[12]_i_3_n_0 ),
.I2(\Q_reg_n_0_[22] ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q[12]_i_4_n_0 ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [4]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[12]_i_2
(.I0(\Q_reg_n_0_[13] ),
.I1(\Q_reg[22]_0 [11]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[12] ),
.I4(\Q_reg[22]_0 [10]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [12]));
LUT4 #(
.INIT(16'hFFFE))
\Q[12]_i_2__0
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg_n_0_[18] ),
.I2(\Q_reg_n_0_[21] ),
.I3(\Q_reg_n_0_[20] ),
.O(\Q[12]_i_2__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair37" *)
LUT5 #(
.INIT(32'hAAAAAAAB))
\Q[12]_i_3
(.I0(\Q_reg_n_0_[24] ),
.I1(\Q_reg_n_0_[8] ),
.I2(\Q[12]_i_5_n_0 ),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg_n_0_[9] ),
.O(\Q[12]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT5 #(
.INIT(32'hFFFFFFFE))
\Q[12]_i_4
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[13] ),
.I2(\Q_reg_n_0_[10] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q[12]_i_6_n_0 ),
.O(\Q[12]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFEFFFFFFFF))
\Q[12]_i_5
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.I3(\Q_reg_n_0_[1] ),
.I4(\Q_reg_n_0_[0] ),
.I5(\Q[12]_i_7__0_n_0 ),
.O(\Q[12]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair39" *)
LUT4 #(
.INIT(16'hFFFE))
\Q[12]_i_6
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[17] ),
.I3(\Q_reg_n_0_[16] ),
.O(\Q[12]_i_6_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT2 #(
.INIT(4'h1))
\Q[12]_i_7__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.O(\Q[12]_i_7__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_1
(.I0(\Data_array_SWR[0] [16]),
.I1(\Data_array_SWR[0] [15]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [14]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [13]),
.O(D[13]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[13]_i_2
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg[22]_0 [10]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[13] ),
.I4(\Q_reg[22]_0 [11]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_1
(.I0(\Data_array_SWR[0] [17]),
.I1(\Data_array_SWR[0] [16]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [15]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [14]),
.O(D[14]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[14]_i_2
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg[22]_0 [9]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[14] ),
.I4(\Q_reg[22]_0 [12]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [14]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_1
(.I0(\Data_array_SWR[0] [18]),
.I1(\Data_array_SWR[0] [17]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [16]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [15]),
.O(D[15]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[15]_i_2
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg[22]_0 [8]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[15] ),
.I4(\Q_reg[22]_0 [13]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [15]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_1
(.I0(\Data_array_SWR[0] [19]),
.I1(\Data_array_SWR[0] [18]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [17]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [16]),
.O(D[16]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[16]_i_2
(.I0(\Q_reg_n_0_[9] ),
.I1(\Q_reg[22]_0 [7]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg[22]_0 [14]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [16]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_1
(.I0(\Data_array_SWR[0] [20]),
.I1(\Data_array_SWR[0] [19]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [18]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [17]),
.O(D[17]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[17]_i_2
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg[22]_0 [6]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[17] ),
.I4(\Q_reg[22]_0 [15]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [17]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_1
(.I0(\Data_array_SWR[0] [21]),
.I1(\Data_array_SWR[0] [20]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [19]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [18]),
.O(D[18]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[18]_i_2
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg[22]_0 [5]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg[22]_0 [16]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [18]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_1
(.I0(\Data_array_SWR[0] [22]),
.I1(\Data_array_SWR[0] [21]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [20]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [19]),
.O(D[19]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[19]_i_2
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg[22]_0 [4]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[19] ),
.I4(\Q_reg[22]_0 [17]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [19]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[1]_i_1
(.I0(\Data_array_SWR[0] [4]),
.I1(\Data_array_SWR[0] [3]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [2]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [1]),
.O(D[1]));
LUT5 #(
.INIT(32'h8C888088))
\Q[1]_i_2
(.I0(\Q_reg_n_0_[24] ),
.I1(Q[0]),
.I2(\Q_reg[1]_0 ),
.I3(CO),
.I4(\Q_reg_n_0_[1] ),
.O(\Data_array_SWR[0] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_1
(.I0(\Data_array_SWR[0] [23]),
.I1(\Data_array_SWR[0] [22]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [21]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [20]),
.O(D[20]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[20]_i_2
(.I0(\Q_reg_n_0_[5] ),
.I1(\Q_reg[22]_0 [3]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[20] ),
.I4(\Q_reg[22]_0 [18]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [20]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_1
(.I0(\Data_array_SWR[0] [24]),
.I1(\Data_array_SWR[0] [23]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [22]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [21]),
.O(D[21]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[21]_i_2
(.I0(\Q_reg_n_0_[4] ),
.I1(\Q_reg[22]_0 [2]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg[22]_0 [19]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [21]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_1
(.I0(\Data_array_SWR[0] [25]),
.I1(\Data_array_SWR[0] [24]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [23]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [22]),
.O(D[22]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[22]_i_2
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg[22]_0 [1]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[22] ),
.I4(\Q_reg[22]_0 [20]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [22]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_1
(.I0(\Q_reg[2]_0 ),
.I1(\Data_array_SWR[0] [25]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [24]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [23]),
.O(D[23]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[23]_i_2
(.I0(\Q_reg_n_0_[2] ),
.I1(\Q_reg[22]_0 [0]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg[22]_0 [21]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [23]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT5 #(
.INIT(32'hB8BBB888))
\Q[24]_i_1
(.I0(\Q_reg[2]_0 ),
.I1(shft_value_mux_o_EWR__0[1]),
.I2(\Data_array_SWR[0] [25]),
.I3(shft_value_mux_o_EWR__0[0]),
.I4(\Data_array_SWR[0] [24]),
.O(D[24]));
LUT6 #(
.INIT(64'hBFBBB3BB8C888088))
\Q[24]_i_2
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[0]),
.I2(\Q_reg[1]_0 ),
.I3(CO),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg[22]_0 [22]),
.O(\Data_array_SWR[0] [24]));
(* SOFT_HLUTNM = "soft_lutpair33" *)
LUT4 #(
.INIT(16'hCDC8))
\Q[25]_i_2
(.I0(shft_value_mux_o_EWR__0[1]),
.I1(\Q_reg[2]_0 ),
.I2(shft_value_mux_o_EWR__0[0]),
.I3(\Data_array_SWR[0] [25]),
.O(D[25]));
LUT4 #(
.INIT(16'h2F20))
\Q[25]_i_3
(.I0(\Q_reg[12]_0 [1]),
.I1(\Q_reg[2]_0 ),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [1]),
.O(shft_value_mux_o_EWR__0[1]));
LUT4 #(
.INIT(16'hEEF0))
\Q[25]_i_4
(.I0(\Q_reg[12]_0 [0]),
.I1(\Q_reg[2]_0 ),
.I2(\Q_reg[4]_1 [0]),
.I3(Q[0]),
.O(shft_value_mux_o_EWR__0[0]));
(* SOFT_HLUTNM = "soft_lutpair31" *)
LUT5 #(
.INIT(32'hBFBBB3BB))
\Q[25]_i_5
(.I0(\Q_reg_n_0_[0] ),
.I1(Q[0]),
.I2(\Q_reg[1]_0 ),
.I3(CO),
.I4(\Q_reg_n_0_[25] ),
.O(\Data_array_SWR[0] [25]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[2]_i_1
(.I0(\Data_array_SWR[0] [5]),
.I1(\Data_array_SWR[0] [4]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [3]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [2]),
.O(D[2]));
LUT4 #(
.INIT(16'h2F20))
\Q[2]_i_1__1
(.I0(\Q_reg[12]_0 [2]),
.I1(\Q_reg[2]_0 ),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [2]),
.O(\Q_reg[4]_0 [0]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[2]_i_2
(.I0(\Q_reg_n_0_[23] ),
.I1(\Q_reg[22]_0 [21]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg[22]_0 [0]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[3]_i_1
(.I0(\Data_array_SWR[0] [6]),
.I1(\Data_array_SWR[0] [5]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [4]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [3]),
.O(D[3]));
LUT4 #(
.INIT(16'h2F20))
\Q[3]_i_1__0
(.I0(\Q_reg[12]_0 [3]),
.I1(\Q_reg[2]_0 ),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [3]),
.O(\Q_reg[4]_0 [1]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[3]_i_2
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg[22]_0 [20]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[3] ),
.I4(\Q_reg[22]_0 [1]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[4]_i_1
(.I0(\Data_array_SWR[0] [7]),
.I1(\Data_array_SWR[0] [6]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [5]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [4]),
.O(D[4]));
LUT4 #(
.INIT(16'h2F20))
\Q[4]_i_1__0
(.I0(\Q_reg[12]_0 [4]),
.I1(\Q_reg[2]_0 ),
.I2(Q[0]),
.I3(\Q_reg[4]_1 [4]),
.O(\Q_reg[4]_0 [2]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[4]_i_2
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg[22]_0 [19]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[4] ),
.I4(\Q_reg[22]_0 [2]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[5]_i_1
(.I0(\Data_array_SWR[0] [8]),
.I1(\Data_array_SWR[0] [7]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [6]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [5]),
.O(D[5]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[5]_i_2
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg[22]_0 [18]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[5] ),
.I4(\Q_reg[22]_0 [3]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[6]_i_1
(.I0(\Data_array_SWR[0] [9]),
.I1(\Data_array_SWR[0] [8]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [7]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [6]),
.O(D[6]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[6]_i_2
(.I0(\Q_reg_n_0_[19] ),
.I1(\Q_reg[22]_0 [17]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[6] ),
.I4(\Q_reg[22]_0 [4]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[7]_i_1
(.I0(\Data_array_SWR[0] [10]),
.I1(\Data_array_SWR[0] [9]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [8]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [7]),
.O(D[7]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[7]_i_2
(.I0(\Q_reg_n_0_[18] ),
.I1(\Q_reg[22]_0 [16]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[7] ),
.I4(\Q_reg[22]_0 [5]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[8]_i_1
(.I0(\Data_array_SWR[0] [11]),
.I1(\Data_array_SWR[0] [10]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [9]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [8]),
.O(D[8]));
(* SOFT_HLUTNM = "soft_lutpair32" *)
LUT5 #(
.INIT(32'h00004544))
\Q[8]_i_10__0
(.I0(\Q_reg_n_0_[3] ),
.I1(\Q_reg_n_0_[2] ),
.I2(\Q_reg_n_0_[1] ),
.I3(\Q_reg_n_0_[0] ),
.I4(\Q_reg_n_0_[5] ),
.O(\Q[8]_i_10__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT2 #(
.INIT(4'hE))
\Q[8]_i_11__0
(.I0(\Q_reg_n_0_[8] ),
.I1(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_11__0_n_0 ));
LUT6 #(
.INIT(64'h00000000FFFF888A))
\Q[8]_i_1__2
(.I0(\Q[8]_i_2__0_n_0 ),
.I1(\Q[8]_i_3_n_0 ),
.I2(\Q[8]_i_4_n_0 ),
.I3(\Q[8]_i_5_n_0 ),
.I4(\Q_reg_n_0_[24] ),
.I5(\Q_reg_n_0_[25] ),
.O(\Q_reg[12]_0 [0]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[8]_i_2
(.I0(\Q_reg_n_0_[17] ),
.I1(\Q_reg[22]_0 [15]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[8] ),
.I4(\Q_reg[22]_0 [6]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [8]));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT5 #(
.INIT(32'h0000AAEF))
\Q[8]_i_2__0
(.I0(\Q_reg_n_0_[22] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[21] ),
.I4(\Q_reg_n_0_[23] ),
.O(\Q[8]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFF0F0FFF4))
\Q[8]_i_3
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[18] ),
.I3(\Q_reg_n_0_[16] ),
.I4(\Q_reg_n_0_[17] ),
.I5(\Q[8]_i_6__0_n_0 ),
.O(\Q[8]_i_3_n_0 ));
LUT5 #(
.INIT(32'hFEFEFFFE))
\Q[8]_i_4
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[17] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[11] ),
.I4(\Q_reg_n_0_[12] ),
.O(\Q[8]_i_4_n_0 ));
LUT6 #(
.INIT(64'h5555555577775557))
\Q[8]_i_5
(.I0(\Q[8]_i_7__0_n_0 ),
.I1(\Q[8]_i_8__0_n_0 ),
.I2(\Q[8]_i_9__0_n_0 ),
.I3(\Q[8]_i_10__0_n_0 ),
.I4(\Q_reg_n_0_[7] ),
.I5(\Q[8]_i_11__0_n_0 ),
.O(\Q[8]_i_5_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair34" *)
LUT2 #(
.INIT(4'hE))
\Q[8]_i_6__0
(.I0(\Q_reg_n_0_[20] ),
.I1(\Q_reg_n_0_[22] ),
.O(\Q[8]_i_6__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair38" *)
LUT4 #(
.INIT(16'hAEFF))
\Q[8]_i_7__0
(.I0(\Q_reg_n_0_[12] ),
.I1(\Q_reg_n_0_[10] ),
.I2(\Q_reg_n_0_[11] ),
.I3(\Q_reg_n_0_[9] ),
.O(\Q[8]_i_7__0_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair36" *)
LUT2 #(
.INIT(4'h2))
\Q[8]_i_8__0
(.I0(\Q_reg_n_0_[10] ),
.I1(\Q_reg_n_0_[11] ),
.O(\Q[8]_i_8__0_n_0 ));
LUT3 #(
.INIT(8'hAE))
\Q[8]_i_9__0
(.I0(\Q_reg_n_0_[6] ),
.I1(\Q_reg_n_0_[4] ),
.I2(\Q_reg_n_0_[5] ),
.O(\Q[8]_i_9__0_n_0 ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[9]_i_1
(.I0(\Data_array_SWR[0] [12]),
.I1(\Data_array_SWR[0] [11]),
.I2(shft_value_mux_o_EWR__0[1]),
.I3(\Data_array_SWR[0] [10]),
.I4(shft_value_mux_o_EWR__0[0]),
.I5(\Data_array_SWR[0] [9]),
.O(D[9]));
LUT6 #(
.INIT(64'h000000000000FFF8))
\Q[9]_i_1__2
(.I0(\Q[9]_i_2__0_n_0 ),
.I1(\Q[9]_i_3_n_0 ),
.I2(\Q_reg_n_0_[22] ),
.I3(\Q_reg_n_0_[23] ),
.I4(\Q_reg_n_0_[25] ),
.I5(\Q_reg_n_0_[24] ),
.O(\Q_reg[12]_0 [1]));
LUT6 #(
.INIT(64'hAFA0AFA0CFCFC0C0))
\Q[9]_i_2
(.I0(\Q_reg_n_0_[16] ),
.I1(\Q_reg[22]_0 [14]),
.I2(left_right_SHT1),
.I3(\Q_reg_n_0_[9] ),
.I4(\Q_reg[22]_0 [7]),
.I5(Q[0]),
.O(\Data_array_SWR[0] [9]));
LUT6 #(
.INIT(64'h1110111011101111))
\Q[9]_i_2__0
(.I0(\Q_reg_n_0_[21] ),
.I1(\Q_reg_n_0_[20] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.I4(\Q_reg_n_0_[16] ),
.I5(\Q_reg_n_0_[17] ),
.O(\Q[9]_i_2__0_n_0 ));
LUT6 #(
.INIT(64'hFFFFFFFFAAAAAABA))
\Q[9]_i_3
(.I0(\Q[9]_i_4_n_0 ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q[9]_i_5_n_0 ),
.I3(\Q[11]_i_5_n_0 ),
.I4(\Q_reg_n_0_[13] ),
.I5(\Q[9]_i_6_n_0 ),
.O(\Q[9]_i_3_n_0 ));
(* SOFT_HLUTNM = "soft_lutpair35" *)
LUT4 #(
.INIT(16'h0302))
\Q[9]_i_4
(.I0(\Q_reg_n_0_[11] ),
.I1(\Q_reg_n_0_[12] ),
.I2(\Q_reg_n_0_[13] ),
.I3(\Q_reg_n_0_[10] ),
.O(\Q[9]_i_4_n_0 ));
LUT6 #(
.INIT(64'hFAFAFAFAFAFAFFFE))
\Q[9]_i_5
(.I0(\Q_reg_n_0_[7] ),
.I1(\Q_reg_n_0_[3] ),
.I2(\Q_reg_n_0_[6] ),
.I3(\Q_reg_n_0_[2] ),
.I4(\Q_reg_n_0_[5] ),
.I5(\Q_reg_n_0_[4] ),
.O(\Q[9]_i_5_n_0 ));
LUT4 #(
.INIT(16'hFFFE))
\Q[9]_i_6
(.I0(\Q_reg_n_0_[15] ),
.I1(\Q_reg_n_0_[14] ),
.I2(\Q_reg_n_0_[19] ),
.I3(\Q_reg_n_0_[18] ),
.O(\Q[9]_i_6_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [10]),
.Q(\Q_reg_n_0_[10] ));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [11]),
.Q(\Q_reg_n_0_[11] ));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [12]),
.Q(\Q_reg_n_0_[12] ));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [13]),
.Q(\Q_reg_n_0_[13] ));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [14]),
.Q(\Q_reg_n_0_[14] ));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [15]),
.Q(\Q_reg_n_0_[15] ));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [16]),
.Q(\Q_reg_n_0_[16] ));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [17]),
.Q(\Q_reg_n_0_[17] ));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [18]),
.Q(\Q_reg_n_0_[18] ));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [19]),
.Q(\Q_reg_n_0_[19] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [20]),
.Q(\Q_reg_n_0_[20] ));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [21]),
.Q(\Q_reg_n_0_[21] ));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [22]),
.Q(\Q_reg_n_0_[22] ));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [23]),
.Q(\Q_reg_n_0_[23] ));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [24]),
.Q(\Q_reg_n_0_[24] ));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [25]),
.Q(\Q_reg_n_0_[25] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [2]),
.Q(\Q_reg_n_0_[2] ));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [4]),
.Q(\Q_reg_n_0_[4] ));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [5]),
.Q(\Q_reg_n_0_[5] ));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [6]),
.Q(\Q_reg_n_0_[6] ));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [7]),
.Q(\Q_reg_n_0_[7] ));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [8]),
.Q(\Q_reg_n_0_[8] ));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(Q[1]),
.CLR(AR),
.D(\Q_reg[1]_1 [9]),
.Q(\Q_reg_n_0_[9] ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized19
(Q,
\Q_reg[2]_0 ,
\Q_reg[30] ,
CLK,
AR);
output [7:0]Q;
input [0:0]\Q_reg[2]_0 ;
input [7:0]\Q_reg[30] ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [7:0]Q;
wire [0:0]\Q_reg[2]_0 ;
wire [7:0]\Q_reg[30] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[2]_0 ),
.CLR(AR),
.D(\Q_reg[30] [7]),
.Q(Q[7]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized2
(D,
Q,
\Q_reg[27]_0 ,
\Q_reg[6]_0 ,
\Q_reg[27]_1 ,
CLK,
AR);
output [2:0]D;
output [25:0]Q;
input [4:0]\Q_reg[27]_0 ;
input [0:0]\Q_reg[6]_0 ;
input [27:0]\Q_reg[27]_1 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [25:0]Q;
wire \Q[4]_i_2__0_n_0 ;
wire [4:0]\Q_reg[27]_0 ;
wire [27:0]\Q_reg[27]_1 ;
wire [0:0]\Q_reg[6]_0 ;
wire \Q_reg_n_0_[26] ;
wire \Q_reg_n_0_[27] ;
LUT4 #(
.INIT(16'h2DD2))
\Q[1]_i_1__4
(.I0(Q[23]),
.I1(\Q_reg[27]_0 [0]),
.I2(Q[24]),
.I3(\Q_reg[27]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT3 #(
.INIT(8'h69))
\Q[3]_i_1__4
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg_n_0_[26] ),
.I2(\Q_reg[27]_0 [3]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair0" *)
LUT5 #(
.INIT(32'h718E8E71))
\Q[4]_i_1__3
(.I0(\Q[4]_i_2__0_n_0 ),
.I1(\Q_reg[27]_0 [3]),
.I2(\Q_reg_n_0_[26] ),
.I3(\Q_reg_n_0_[27] ),
.I4(\Q_reg[27]_0 [4]),
.O(D[2]));
LUT6 #(
.INIT(64'hD4DD4444DDDDD4DD))
\Q[4]_i_2__0
(.I0(Q[25]),
.I1(\Q_reg[27]_0 [2]),
.I2(\Q_reg[27]_0 [0]),
.I3(Q[23]),
.I4(\Q_reg[27]_0 [1]),
.I5(Q[24]),
.O(\Q[4]_i_2__0_n_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [26]),
.Q(\Q_reg_n_0_[26] ));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [27]),
.Q(\Q_reg_n_0_[27] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[6]_0 ),
.CLR(AR),
.D(\Q_reg[27]_1 [9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized20
(D,
\Q_reg[0]_0 ,
Q,
\Q_reg[2]_0 ,
\Q_reg[1]_0 ,
CLK,
AR);
output [1:0]D;
output [0:0]\Q_reg[0]_0 ;
input [1:0]Q;
input [1:0]\Q_reg[2]_0 ;
input [2:0]\Q_reg[1]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [1:0]D;
wire [1:0]Q;
wire [0:0]\Q_reg[0]_0 ;
wire [2:0]\Q_reg[1]_0 ;
wire [1:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[0] ;
wire \Q_reg_n_0_[1] ;
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[0]_i_1__0
(.I0(\Q_reg_n_0_[0] ),
.I1(Q[0]),
.I2(\Q_reg[2]_0 [0]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair30" *)
LUT3 #(
.INIT(8'hAC))
\Q[2]_i_1__2
(.I0(\Q_reg_n_0_[1] ),
.I1(Q[1]),
.I2(\Q_reg[2]_0 [0]),
.O(D[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [0]),
.Q(\Q_reg_n_0_[0] ));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [1]),
.Q(\Q_reg_n_0_[1] ));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[2]_0 [1]),
.CLR(AR),
.D(\Q_reg[1]_0 [2]),
.Q(\Q_reg[0]_0 ));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized21
(Q,
D,
CLK,
AR);
output [3:0]Q;
input [3:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [3:0]D;
wire [3:0]Q;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(D[0]),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(D[0]),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(D[0]),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(D[0]),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized3
(Q,
\Q_reg[6] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[6] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[6] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[6] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized4
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [30:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized5
(Q,
\Q_reg[5]_0 ,
D,
CLK,
AR);
output [22:0]Q;
input [0:0]\Q_reg[5]_0 ;
input [22:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [22:0]D;
wire [22:0]Q;
wire [0:0]\Q_reg[5]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[5]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized6
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [4:0]Q;
input [0:0]\Q_reg[5] ;
input [4:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [4:0]D;
wire [4:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized7
(Q,
\Q_reg[5] ,
D,
CLK,
AR);
output [2:0]Q;
input [0:0]\Q_reg[5] ;
input [2:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [2:0]Q;
wire [0:0]\Q_reg[5] ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[5] ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized8
(Q,
\Q_reg[4]_0 ,
D,
CLK,
AR);
output [30:0]Q;
input [0:0]\Q_reg[4]_0 ;
input [30:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [30:0]D;
wire [30:0]Q;
wire [0:0]\Q_reg[4]_0 ;
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[0]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[10]),
.Q(Q[10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[11]),
.Q(Q[11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[12]),
.Q(Q[12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[13]),
.Q(Q[13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[14]),
.Q(Q[14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[15]),
.Q(Q[15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[16]),
.Q(Q[16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[17]),
.Q(Q[17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[18]),
.Q(Q[18]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[19]),
.Q(Q[19]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[1]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[20]),
.Q(Q[20]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[21]),
.Q(Q[21]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[22]),
.Q(Q[22]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[23]),
.Q(Q[23]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[24]),
.Q(Q[24]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[25]),
.Q(Q[25]));
FDCE #(
.INIT(1'b0))
\Q_reg[26]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[26]),
.Q(Q[26]));
FDCE #(
.INIT(1'b0))
\Q_reg[27]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[27]),
.Q(Q[27]));
FDCE #(
.INIT(1'b0))
\Q_reg[28]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[28]),
.Q(Q[28]));
FDCE #(
.INIT(1'b0))
\Q_reg[29]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[29]),
.Q(Q[29]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[2]),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[30]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[30]),
.Q(Q[30]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[3]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[4]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[5]),
.Q(Q[5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[6]),
.Q(Q[6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[7]),
.Q(Q[7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[8]),
.Q(Q[8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(\Q_reg[4]_0 ),
.CLR(AR),
.D(D[9]),
.Q(Q[9]));
endmodule
(* ORIG_REF_NAME = "RegisterAdd" *)
module RegisterAdd__parameterized9
(D,
\Q_reg[25]_0 ,
\Q_reg[8]_0 ,
\Data_array_SWR[6] ,
\Q_reg[13]_0 ,
\Data_array_SWR[4] ,
\Q_reg[0]_0 ,
Q,
\Q_reg[4]_0 ,
\Q_reg[4]_1 ,
E,
\Q_reg[2]_0 ,
CLK,
AR);
output [2:0]D;
output [4:0]\Q_reg[25]_0 ;
output [11:0]\Q_reg[8]_0 ;
output [0:0]\Data_array_SWR[6] ;
output [7:0]\Q_reg[13]_0 ;
output [1:0]\Data_array_SWR[4] ;
input [1:0]\Q_reg[0]_0 ;
input [1:0]Q;
input [2:0]\Q_reg[4]_0 ;
input [1:0]\Q_reg[4]_1 ;
input [0:0]E;
input [25:0]\Q_reg[2]_0 ;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [2:0]D;
wire [17:0]\Data_array_SWR[3] ;
wire [1:0]\Data_array_SWR[4] ;
wire [13:0]\Data_array_SWR[5] ;
wire [0:0]\Data_array_SWR[6] ;
wire [0:0]E;
wire [1:0]Q;
wire [1:0]\Q_reg[0]_0 ;
wire [7:0]\Q_reg[13]_0 ;
wire [4:0]\Q_reg[25]_0 ;
wire [25:0]\Q_reg[2]_0 ;
wire [2:0]\Q_reg[4]_0 ;
wire [1:0]\Q_reg[4]_1 ;
wire [11:0]\Q_reg[8]_0 ;
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'hFF00B8B8))
\Q[0]_i_1__4
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [0]),
.I3(\Q_reg[4]_1 [1]),
.I4(Q[1]),
.O(\Q_reg[25]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'h02))
\Q[10]_i_1__1
(.I0(\Q_reg[25]_0 [1]),
.I1(\Q_reg[0]_0 [0]),
.I2(\Q_reg[0]_0 [1]),
.O(D[0]));
(* SOFT_HLUTNM = "soft_lutpair61" *)
LUT3 #(
.INIT(8'h02))
\Q[11]_i_1__2
(.I0(\Q_reg[25]_0 [2]),
.I1(\Q_reg[0]_0 [0]),
.I2(\Q_reg[0]_0 [1]),
.O(D[1]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[12]_i_1__1
(.I0(\Data_array_SWR[5] [13]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_0 [2]),
.I4(\Data_array_SWR[5] [12]),
.O(\Q_reg[25]_0 [1]));
(* SOFT_HLUTNM = "soft_lutpair57" *)
LUT5 #(
.INIT(32'hF0BBF088))
\Q[13]_i_1__1
(.I0(\Data_array_SWR[5] [12]),
.I1(Q[1]),
.I2(Q[0]),
.I3(\Q_reg[4]_0 [2]),
.I4(\Data_array_SWR[5] [13]),
.O(\Q_reg[25]_0 [2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_2__0
(.I0(\Q_reg[13]_0 [6]),
.I1(\Q_reg[13]_0 [2]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [16]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [12]),
.O(\Data_array_SWR[5] [12]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[13]_i_3
(.I0(\Q_reg[13]_0 [7]),
.I1(\Q_reg[13]_0 [3]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [17]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [13]),
.O(\Data_array_SWR[5] [13]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[14]_i_4
(.I0(\Q_reg[13]_0 [5]),
.I1(\Q_reg[13]_0 [1]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [15]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [11]),
.O(\Q_reg[8]_0 [9]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[14]_i_5
(.I0(\Q_reg[13]_0 [0]),
.I1(\Q_reg[4]_0 [0]),
.I2(\Data_array_SWR[3] [14]),
.O(\Data_array_SWR[4] [0]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[15]_i_4
(.I0(\Q_reg[13]_0 [4]),
.I1(\Q_reg[13]_0 [0]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [14]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [10]),
.O(\Q_reg[8]_0 [8]));
(* SOFT_HLUTNM = "soft_lutpair60" *)
LUT3 #(
.INIT(8'hB8))
\Q[15]_i_5
(.I0(\Q_reg[13]_0 [1]),
.I1(\Q_reg[4]_0 [0]),
.I2(\Data_array_SWR[3] [15]),
.O(\Data_array_SWR[4] [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[16]_i_3
(.I0(\Q_reg[13]_0 [3]),
.I1(\Data_array_SWR[3] [17]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [13]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [9]),
.O(\Q_reg[8]_0 [7]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_3
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [7]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Q_reg[13]_0 [3]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [17]),
.O(\Q_reg[8]_0 [11]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[17]_i_4
(.I0(\Q_reg[13]_0 [2]),
.I1(\Data_array_SWR[3] [16]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [12]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [8]),
.O(\Q_reg[8]_0 [6]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[18]_i_4
(.I0(\Q_reg[13]_0 [1]),
.I1(\Data_array_SWR[3] [15]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [11]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [7]),
.O(\Q_reg[8]_0 [5]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[19]_i_4
(.I0(\Q_reg[13]_0 [0]),
.I1(\Data_array_SWR[3] [14]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [10]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [6]),
.O(\Q_reg[8]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[20]_i_5
(.I0(\Data_array_SWR[3] [17]),
.I1(\Data_array_SWR[3] [13]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [9]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [5]),
.O(\Q_reg[8]_0 [3]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[21]_i_5
(.I0(\Data_array_SWR[3] [16]),
.I1(\Data_array_SWR[3] [12]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [8]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [4]),
.O(\Q_reg[8]_0 [2]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT5 #(
.INIT(32'h000000B8))
\Q[22]_i_1__2
(.I0(\Data_array_SWR[6] ),
.I1(Q[1]),
.I2(\Q_reg[4]_1 [0]),
.I3(\Q_reg[0]_0 [0]),
.I4(\Q_reg[0]_0 [1]),
.O(D[2]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[22]_i_5
(.I0(\Data_array_SWR[3] [15]),
.I1(\Data_array_SWR[3] [11]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [7]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [3]),
.O(\Q_reg[8]_0 [1]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[23]_i_5
(.I0(\Data_array_SWR[3] [14]),
.I1(\Data_array_SWR[3] [10]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [6]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [2]),
.O(\Q_reg[8]_0 [0]));
(* SOFT_HLUTNM = "soft_lutpair58" *)
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_1__2
(.I0(\Data_array_SWR[6] ),
.I1(Q[1]),
.I2(\Q_reg[4]_1 [0]),
.O(\Q_reg[25]_0 [3]));
LUT3 #(
.INIT(8'hB8))
\Q[24]_i_2__0
(.I0(\Q_reg[8]_0 [11]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [1]),
.O(\Data_array_SWR[6] ));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[24]_i_4
(.I0(\Data_array_SWR[3] [13]),
.I1(\Data_array_SWR[3] [9]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [5]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [1]),
.O(\Data_array_SWR[5] [1]));
(* SOFT_HLUTNM = "soft_lutpair59" *)
LUT5 #(
.INIT(32'hB8FFB800))
\Q[25]_i_1__2
(.I0(\Q_reg[8]_0 [10]),
.I1(\Q_reg[4]_0 [2]),
.I2(\Data_array_SWR[5] [0]),
.I3(Q[1]),
.I4(\Q_reg[4]_1 [1]),
.O(\Q_reg[25]_0 [4]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_2__0
(.I0(Q[0]),
.I1(\Q_reg[13]_0 [6]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Q_reg[13]_0 [2]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [16]),
.O(\Q_reg[8]_0 [10]));
LUT6 #(
.INIT(64'hAFA0CFCFAFA0C0C0))
\Q[25]_i_3__0
(.I0(\Data_array_SWR[3] [12]),
.I1(\Data_array_SWR[3] [8]),
.I2(\Q_reg[4]_0 [1]),
.I3(\Data_array_SWR[3] [4]),
.I4(\Q_reg[4]_0 [0]),
.I5(\Data_array_SWR[3] [0]),
.O(\Data_array_SWR[5] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [0]),
.Q(\Data_array_SWR[3] [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[10]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [10]),
.Q(\Data_array_SWR[3] [10]));
FDCE #(
.INIT(1'b0))
\Q_reg[11]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [11]),
.Q(\Data_array_SWR[3] [11]));
FDCE #(
.INIT(1'b0))
\Q_reg[12]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [12]),
.Q(\Data_array_SWR[3] [12]));
FDCE #(
.INIT(1'b0))
\Q_reg[13]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [13]),
.Q(\Data_array_SWR[3] [13]));
FDCE #(
.INIT(1'b0))
\Q_reg[14]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [14]),
.Q(\Data_array_SWR[3] [14]));
FDCE #(
.INIT(1'b0))
\Q_reg[15]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [15]),
.Q(\Data_array_SWR[3] [15]));
FDCE #(
.INIT(1'b0))
\Q_reg[16]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [16]),
.Q(\Data_array_SWR[3] [16]));
FDCE #(
.INIT(1'b0))
\Q_reg[17]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [17]),
.Q(\Data_array_SWR[3] [17]));
FDCE #(
.INIT(1'b0))
\Q_reg[18]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [18]),
.Q(\Q_reg[13]_0 [0]));
FDCE #(
.INIT(1'b0))
\Q_reg[19]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [19]),
.Q(\Q_reg[13]_0 [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [1]),
.Q(\Data_array_SWR[3] [1]));
FDCE #(
.INIT(1'b0))
\Q_reg[20]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [20]),
.Q(\Q_reg[13]_0 [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[21]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [21]),
.Q(\Q_reg[13]_0 [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[22]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [22]),
.Q(\Q_reg[13]_0 [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[23]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [23]),
.Q(\Q_reg[13]_0 [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[24]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [24]),
.Q(\Q_reg[13]_0 [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[25]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [25]),
.Q(\Q_reg[13]_0 [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [2]),
.Q(\Data_array_SWR[3] [2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [3]),
.Q(\Data_array_SWR[3] [3]));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [4]),
.Q(\Data_array_SWR[3] [4]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [5]),
.Q(\Data_array_SWR[3] [5]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [6]),
.Q(\Data_array_SWR[3] [6]));
FDCE #(
.INIT(1'b0))
\Q_reg[7]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [7]),
.Q(\Data_array_SWR[3] [7]));
FDCE #(
.INIT(1'b0))
\Q_reg[8]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [8]),
.Q(\Data_array_SWR[3] [8]));
FDCE #(
.INIT(1'b0))
\Q_reg[9]
(.C(CLK),
.CE(E),
.CLR(AR),
.D(\Q_reg[2]_0 [9]),
.Q(\Data_array_SWR[3] [9]));
endmodule
module ShiftRegister
(\Q_reg[1]_0 ,
Q,
E,
\Q_reg[2]_0 ,
\Q_reg[1]_1 ,
CO,
\FSM_sequential_state_reg_reg[2] ,
D,
CLK,
AR);
output [0:0]\Q_reg[1]_0 ;
output [5:0]Q;
output [0:0]E;
output [0:0]\Q_reg[2]_0 ;
input [0:0]\Q_reg[1]_1 ;
input [0:0]CO;
input [0:0]\FSM_sequential_state_reg_reg[2] ;
input [0:0]D;
input CLK;
input [0:0]AR;
wire [0:0]AR;
wire CLK;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]E;
wire [0:0]\FSM_sequential_state_reg_reg[2] ;
wire [5:0]Q;
wire [0:0]\Q_reg[1]_0 ;
wire [0:0]\Q_reg[1]_1 ;
wire [0:0]\Q_reg[2]_0 ;
wire \Q_reg_n_0_[3] ;
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT3 #(
.INIT(8'h8A))
\Q[1]_i_1__0
(.I0(Q[1]),
.I1(\Q_reg[1]_1 ),
.I2(CO),
.O(\Q_reg[1]_0 ));
(* SOFT_HLUTNM = "soft_lutpair83" *)
LUT2 #(
.INIT(4'hE))
\Q[25]_i_1
(.I0(Q[1]),
.I1(Q[3]),
.O(E));
LUT2 #(
.INIT(4'h2))
\Q[2]_i_1__7
(.I0(\Q_reg_n_0_[3] ),
.I1(Q[0]),
.O(\Q_reg[2]_0 ));
FDCE #(
.INIT(1'b0))
\Q_reg[0]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[1]),
.Q(Q[0]));
FDCE #(
.INIT(1'b0))
\Q_reg[1]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[2]),
.Q(Q[1]));
FDCE #(
.INIT(1'b0))
\Q_reg[2]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(\Q_reg_n_0_[3] ),
.Q(Q[2]));
FDCE #(
.INIT(1'b0))
\Q_reg[3]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[3]),
.Q(\Q_reg_n_0_[3] ));
FDCE #(
.INIT(1'b0))
\Q_reg[4]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[4]),
.Q(Q[3]));
FDCE #(
.INIT(1'b0))
\Q_reg[5]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(Q[5]),
.Q(Q[4]));
FDCE #(
.INIT(1'b0))
\Q_reg[6]
(.C(CLK),
.CE(\FSM_sequential_state_reg_reg[2] ),
.CLR(AR),
.D(D),
.Q(Q[5]));
endmodule
module sgn_result
(D,
\Q_reg[30] ,
Q,
intAS,
CO,
\Q_reg[31] );
output [0:0]D;
input [0:0]\Q_reg[30] ;
input [0:0]Q;
input intAS;
input [0:0]CO;
input [0:0]\Q_reg[31] ;
wire [0:0]CO;
wire [0:0]D;
wire [0:0]Q;
wire [0:0]\Q_reg[30] ;
wire [0:0]\Q_reg[31] ;
wire intAS;
LUT5 #(
.INIT(32'hFF3C0014))
sgn_result_o
(.I0(\Q_reg[30] ),
.I1(Q),
.I2(intAS),
.I3(CO),
.I4(\Q_reg[31] ),
.O(D));
endmodule
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
/*===========================================================================*/
/* Copyright (C) 2001 Authors */
/* */
/* This source file may be used and distributed without restriction provided */
/* that this copyright statement is not removed from the file and that any */
/* derivative work contains the original copyright notice and the associated */
/* disclaimer. */
/* */
/* This source file is free software; you can redistribute it and/or modify */
/* it under the terms of the GNU Lesser General Public License as published */
/* by the Free Software Foundation; either version 2.1 of the License, or */
/* (at your option) any later version. */
/* */
/* This source is distributed in the hope that it will be useful, but WITHOUT*/
/* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or */
/* FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public */
/* License for more details. */
/* */
/* You should have received a copy of the GNU Lesser General Public License */
/* along with this source; if not, write to the Free Software Foundation, */
/* Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA */
/* */
/*===========================================================================*/
/* CLOCK MODULE */
/*---------------------------------------------------------------------------*/
/* Test the clock module: */
/* - Check the MCLK clock generation. */
/* */
/* Author(s): */
/* - Olivier Girard, [email protected] */
/* */
/*---------------------------------------------------------------------------*/
/* $Rev: 19 $ */
/* $LastChangedBy: olivier.girard $ */
/* $LastChangedDate: 2009-08-04 23:47:15 +0200 (Tue, 04 Aug 2009) $ */
/*===========================================================================*/
`define LONG_TIMEOUT
integer mclk_counter;
always @ (negedge mclk)
mclk_counter <= mclk_counter+1;
integer dco_clk_counter;
always @ (negedge dco_clk)
dco_clk_counter <= dco_clk_counter+1;
integer lfxt_clk_counter;
always @ (negedge lfxt_clk)
lfxt_clk_counter <= lfxt_clk_counter+1;
reg [15:0] reg_val;
initial
begin
$display(" ===============================================");
$display("| START SIMULATION |");
$display(" ===============================================");
repeat(5) @(posedge mclk);
stimulus_done = 0;
force tb_openMSP430.dut.wdt_reset = 1'b0;
`ifdef ASIC_CLOCKING
//--------------------------------------------------------
// MCLK GENERATION - LFXT_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h0001);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
`endif
// ------- Divider /2 ----------
@(r15 === 16'h0002);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
`endif
`endif
// ------- Divider /4 ----------
@(r15 === 16'h0003);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
`endif
`endif
// ------- Divider /8 ----------
@(r15 === 16'h0004);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 1: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
`endif
`endif
//--------------------------------------------------------
// SMCLK GENERATION - DCO_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h1001);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
// ------- Divider /2 ----------
@(r15 === 16'h1002);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
// ------- Divider /4 ----------
@(r15 === 16'h1003);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
// ------- Divider /8 ----------
@(r15 === 16'h1004);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 2: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
//--------------------------------------------------------
// MCLK GENERATION - LFXT_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h2001);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 1 =====");
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /1) - TEST 3 =====");
`endif
// ------- Divider /2 ----------
@(r15 === 16'h2002);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /2) - TEST 5 =====");
`endif
`endif
// ------- Divider /4 ----------
@(r15 === 16'h2003);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /4) - TEST 5 =====");
`endif
`endif
// ------- Divider /8 ----------
@(r15 === 16'h2004);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef MCLK_DIVIDER
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
`else
`ifdef MCLK_MUX
if (lfxt_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 4 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 3: MCLK - LFXT_CLK INPUT (DIV /8) - TEST 5 =====");
`endif
`endif
//--------------------------------------------------------
// SMCLK GENERATION - DCO_CLK INPUT
//--------------------------------------------------------
// ------- Divider /1 ----------
@(r15 === 16'h3001);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 1 =====");
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /1) - TEST 2 =====");
// ------- Divider /2 ----------
@(r15 === 16'h3002);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 30) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /2) - TEST 3 =====");
`endif
// ------- Divider /4 ----------
@(r15 === 16'h3003);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 60) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /4) - TEST 3 =====");
`endif
// ------- Divider /8 ----------
@(r15 === 16'h3004);
repeat(2) @(posedge mclk);
mclk_counter = 0;
lfxt_clk_counter = 0;
dco_clk_counter = 0;
repeat(15) @(posedge mclk);
if (mclk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 1 =====");
`ifdef MCLK_DIVIDER
if (dco_clk_counter !== 120) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 2 =====");
`else
if (dco_clk_counter !== 15) tb_error("====== CLOCK GENERATOR 4: MCLK - DCO_CLK INPUT (DIV /8) - TEST 3 =====");
`endif
`else
tb_skip_finish("| (this test is not supported in FPGA mode) |");
`endif
stimulus_done = 1;
end
|
// $Id: c_wf_alloc.v 1534 2009-09-16 16:10:23Z dub $
/*
Copyright (c) 2007-2009, Trustees of The Leland Stanford Junior University
All rights reserved.
Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:
Redistributions of source code must retain the above copyright notice, this list
of conditions and the following disclaimer.
Redistributions in binary form must reproduce the above copyright notice, this
list of conditions and the following disclaimer in the documentation and/or
other materials provided with the distribution.
Neither the name of the Stanford University nor the names of its contributors
may be used to endorse or promote products derived from this software without
specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR
ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
// generic wavefront allocator
module c_wf_alloc
(clk, reset, update, req, gnt);
`include "c_constants.v"
// number of input/output ports
// each input can bid for any combination of outputs
parameter num_ports = 8;
// select implementation variant
parameter wf_alloc_type = `WF_ALLOC_TYPE_REP;
// try to recover from errors
parameter error_recovery = 0;
parameter reset_type = `RESET_TYPE_ASYNC;
input clk;
input reset;
// update arbitration priorities
input update;
// request matrix
input [0:num_ports*num_ports-1] req;
// grant matrix
output [0:num_ports*num_ports-1] gnt;
wire [0:num_ports*num_ports-1] gnt;
generate
case(wf_alloc_type)
`WF_ALLOC_TYPE_MUX:
begin
c_wf_alloc_mux
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_mux
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_REP:
begin
c_wf_alloc_rep
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_rep
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_DPA:
begin
c_wf_alloc_dpa
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_dpa
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_ROT:
begin
c_wf_alloc_rot
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_rot
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
`WF_ALLOC_TYPE_LOOP:
begin
c_wf_alloc_loop
#(.num_ports(num_ports),
.error_recovery(error_recovery),
.reset_type(reset_type))
core_loop
(.clk(clk),
.reset(reset),
.update(update),
.req(req),
.gnt(gnt));
end
endcase
endgenerate
endmodule
|
/*
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
`define SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V
/**
* dfxbp: Delay flop, complementary outputs.
*
* Verilog simulation functional model.
*/
`timescale 1ns / 1ps
`default_nettype none
// Import user defined primitives.
`include "../../models/udp_dff_p_pp_pg_n/sky130_fd_sc_ms__udp_dff_p_pp_pg_n.v"
`celldefine
module sky130_fd_sc_ms__dfxbp (
Q ,
Q_N ,
CLK ,
D ,
VPWR,
VGND,
VPB ,
VNB
);
// Module ports
output Q ;
output Q_N ;
input CLK ;
input D ;
input VPWR;
input VGND;
input VPB ;
input VNB ;
// Local signals
wire buf_Q;
// Delay Name Output Other arguments
sky130_fd_sc_ms__udp_dff$P_pp$PG$N `UNIT_DELAY dff0 (buf_Q , D, CLK, , VPWR, VGND);
buf buf0 (Q , buf_Q );
not not0 (Q_N , buf_Q );
endmodule
`endcelldefine
`default_nettype wire
`endif // SKY130_FD_SC_MS__DFXBP_FUNCTIONAL_PP_V |
/**
* Copyright 2020 The SkyWater PDK Authors
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* https://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* SPDX-License-Identifier: Apache-2.0
*/
`ifndef SKY130_FD_SC_LP__DFSBP_LP_V
`define SKY130_FD_SC_LP__DFSBP_LP_V
/**
* dfsbp: Delay flop, inverted set, complementary outputs.
*
* Verilog wrapper for dfsbp with size for low power.
*
* WARNING: This file is autogenerated, do not modify directly!
*/
`timescale 1ns / 1ps
`default_nettype none
`include "sky130_fd_sc_lp__dfsbp.v"
`ifdef USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SET_B,
VPWR ,
VGND ,
VPB ,
VNB
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
input VPWR ;
input VGND ;
input VPB ;
input VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPB),
.VNB(VNB)
);
endmodule
`endcelldefine
/*********************************************************/
`else // If not USE_POWER_PINS
/*********************************************************/
`celldefine
module sky130_fd_sc_lp__dfsbp_lp (
Q ,
Q_N ,
CLK ,
D ,
SET_B
);
output Q ;
output Q_N ;
input CLK ;
input D ;
input SET_B;
// Voltage supply signals
supply1 VPWR;
supply0 VGND;
supply1 VPB ;
supply0 VNB ;
sky130_fd_sc_lp__dfsbp base (
.Q(Q),
.Q_N(Q_N),
.CLK(CLK),
.D(D),
.SET_B(SET_B)
);
endmodule
`endcelldefine
/*********************************************************/
`endif // USE_POWER_PINS
`default_nettype wire
`endif // SKY130_FD_SC_LP__DFSBP_LP_V
|
//Copyright (C) 1991-2013 Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors. Please refer to the
//applicable agreement for further details.
// synopsys translate_off
`timescale 1 ps / 1 ps
// synopsys translate_on
module acl_fp_sin_s5 (
enable,
clock,
dataa,
result);
input enable;
input clock;
input [31:0] dataa;
output [31:0] result;
wire [31:0] sub_wire0;
wire [31:0] result = sub_wire0[31:0];
fp_sin_s5 inst(
.en (enable),
.clk (clock),
.a (dataa),
.q (sub_wire0),
.areset(1'b0));
endmodule
|
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 22:45:38 09/23/2013
// Design Name:
// Module Name: Clock_Divider
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module Clock_Divider(input clock, input reset, output reg clock_out);
//Lleva la cuenta de los ciclos de reloj transcurridos
reg [25:0] counter;
initial
begin
counter <= 26'b0;
clock_out <= 1'b1;
end
always @(posedge clock or posedge reset)
begin
if(reset)
begin
counter <= 26'b0;
clock_out <= 1'b1;
end
else
if(counter == 26'd1134) //va convertir un clk de 50MHz a 1Hz
begin
counter <= 26'b0;
clock_out <= ~clock_out;
end
else
begin
counter <= counter+1;
end
end
endmodule
|
// $Header: /devl/xcs/repo/env/Databases/CAEInterfaces/verunilibs/data/glbl.v,v 1.14 2010/10/28 20:44:00 fphillip Exp $
`ifndef GLBL
`define GLBL
`timescale 1 ps / 1 ps
module glbl ();
parameter ROC_WIDTH = 100000;
parameter TOC_WIDTH = 0;
//-------- STARTUP Globals --------------
wire GSR;
wire GTS;
wire GWE;
wire PRLD;
tri1 p_up_tmp;
tri (weak1, strong0) PLL_LOCKG = p_up_tmp;
wire PROGB_GLBL;
wire CCLKO_GLBL;
wire FCSBO_GLBL;
wire [3:0] DO_GLBL;
wire [3:0] DI_GLBL;
reg GSR_int;
reg GTS_int;
reg PRLD_int;
//-------- JTAG Globals --------------
wire JTAG_TDO_GLBL;
wire JTAG_TCK_GLBL;
wire JTAG_TDI_GLBL;
wire JTAG_TMS_GLBL;
wire JTAG_TRST_GLBL;
reg JTAG_CAPTURE_GLBL;
reg JTAG_RESET_GLBL;
reg JTAG_SHIFT_GLBL;
reg JTAG_UPDATE_GLBL;
reg JTAG_RUNTEST_GLBL;
reg JTAG_SEL1_GLBL = 0;
reg JTAG_SEL2_GLBL = 0 ;
reg JTAG_SEL3_GLBL = 0;
reg JTAG_SEL4_GLBL = 0;
reg JTAG_USER_TDO1_GLBL = 1'bz;
reg JTAG_USER_TDO2_GLBL = 1'bz;
reg JTAG_USER_TDO3_GLBL = 1'bz;
reg JTAG_USER_TDO4_GLBL = 1'bz;
assign (weak1, weak0) GSR = GSR_int;
assign (weak1, weak0) GTS = GTS_int;
assign (weak1, weak0) PRLD = PRLD_int;
initial begin
GSR_int = 1'b1;
PRLD_int = 1'b1;
#(ROC_WIDTH)
GSR_int = 1'b0;
PRLD_int = 1'b0;
end
initial begin
GTS_int = 1'b1;
#(TOC_WIDTH)
GTS_int = 1'b0;
end
endmodule
`endif
|
Subsets and Splits